]>
Commit | Line | Data |
---|---|---|
f045b2c9 | 1 | /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
cf011243 | 3 | 2000, 2001 Free Software Foundation, Inc. |
6a7ec0a7 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
f045b2c9 RS |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
f045b2c9 RS |
22 | |
23 | ||
24 | /* Note that some other tm.h files include this one and then override | |
9ebbca7d | 25 | many of the definitions. */ |
f045b2c9 | 26 | |
9ebbca7d GK |
27 | /* Definitions for the object file format. These are set at |
28 | compile-time. */ | |
f045b2c9 | 29 | |
9ebbca7d GK |
30 | #define OBJECT_XCOFF 1 |
31 | #define OBJECT_ELF 2 | |
32 | #define OBJECT_PEF 3 | |
ee890fe2 | 33 | #define OBJECT_MACHO 4 |
f045b2c9 | 34 | |
9ebbca7d | 35 | #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) |
2bfcf297 | 36 | #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) |
9ebbca7d | 37 | #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) |
ee890fe2 | 38 | #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) |
f045b2c9 | 39 | |
2bfcf297 DB |
40 | #ifndef TARGET_AIX |
41 | #define TARGET_AIX 0 | |
42 | #endif | |
43 | ||
f045b2c9 RS |
44 | /* Print subsidiary information on the compiler version in use. */ |
45 | #define TARGET_VERSION ; | |
46 | ||
8e3f41e7 MM |
47 | /* Default string to use for cpu if not specified. */ |
48 | #ifndef TARGET_CPU_DEFAULT | |
49 | #define TARGET_CPU_DEFAULT ((char *)0) | |
50 | #endif | |
51 | ||
841faeed MM |
52 | /* This macro defines names of additional specifications to put in the specs |
53 | that can be used in various specifications like CC1_SPEC. Its definition | |
54 | is an initializer with a subgrouping for each command option. | |
55 | ||
56 | Each subgrouping contains a string constant, that defines the | |
57 | specification name, and a string constant that used by the GNU CC driver | |
58 | program. | |
59 | ||
60 | Do not define this macro if it does not need to do anything. */ | |
61 | ||
7509c759 | 62 | #define SUBTARGET_EXTRA_SPECS |
7509c759 | 63 | |
c81bebd7 MM |
64 | #define EXTRA_SPECS \ |
65 | { "cpp_cpu", CPP_CPU_SPEC }, \ | |
66 | { "cpp_default", CPP_DEFAULT_SPEC }, \ | |
c81bebd7 MM |
67 | { "asm_cpu", ASM_CPU_SPEC }, \ |
68 | { "asm_default", ASM_DEFAULT_SPEC }, \ | |
7509c759 MM |
69 | SUBTARGET_EXTRA_SPECS |
70 | ||
fb623df5 | 71 | /* Architecture type. */ |
f045b2c9 | 72 | |
fb623df5 RK |
73 | extern int target_flags; |
74 | ||
75 | /* Use POWER architecture instructions and MQ register. */ | |
38c1f2d7 | 76 | #define MASK_POWER 0x00000001 |
fb623df5 | 77 | |
6febd581 | 78 | /* Use POWER2 extensions to POWER architecture. */ |
38c1f2d7 | 79 | #define MASK_POWER2 0x00000002 |
6febd581 | 80 | |
fb623df5 | 81 | /* Use PowerPC architecture instructions. */ |
38c1f2d7 | 82 | #define MASK_POWERPC 0x00000004 |
6febd581 | 83 | |
583cf4db | 84 | /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */ |
38c1f2d7 | 85 | #define MASK_PPC_GPOPT 0x00000008 |
583cf4db RK |
86 | |
87 | /* Use PowerPC Graphics group optional instructions, e.g. fsel. */ | |
38c1f2d7 | 88 | #define MASK_PPC_GFXOPT 0x00000010 |
f045b2c9 | 89 | |
fb623df5 | 90 | /* Use PowerPC-64 architecture instructions. */ |
38c1f2d7 | 91 | #define MASK_POWERPC64 0x00000020 |
f045b2c9 | 92 | |
fb623df5 | 93 | /* Use revised mnemonic names defined for PowerPC architecture. */ |
38c1f2d7 | 94 | #define MASK_NEW_MNEMONICS 0x00000040 |
fb623df5 RK |
95 | |
96 | /* Disable placing fp constants in the TOC; can be turned on when the | |
97 | TOC overflows. */ | |
38c1f2d7 | 98 | #define MASK_NO_FP_IN_TOC 0x00000080 |
fb623df5 | 99 | |
0b9ccabc RK |
100 | /* Disable placing symbol+offset constants in the TOC; can be turned on when |
101 | the TOC overflows. */ | |
38c1f2d7 | 102 | #define MASK_NO_SUM_IN_TOC 0x00000100 |
0b9ccabc | 103 | |
fb623df5 | 104 | /* Output only one TOC entry per module. Normally linking fails if |
642a35f1 JW |
105 | there are more than 16K unique variables/constants in an executable. With |
106 | this option, linking fails only if there are more than 16K modules, or | |
107 | if there are more than 16K unique variables/constant in a single module. | |
108 | ||
109 | This is at the cost of having 2 extra loads and one extra store per | |
956d6950 | 110 | function, and one less allocable register. */ |
38c1f2d7 | 111 | #define MASK_MINIMAL_TOC 0x00000200 |
642a35f1 | 112 | |
9e654916 | 113 | /* Nonzero for the 64bit model: ints, longs, and pointers are 64 bits. */ |
38c1f2d7 | 114 | #define MASK_64BIT 0x00000400 |
9e654916 | 115 | |
f85f4585 | 116 | /* Disable use of FPRs. */ |
38c1f2d7 | 117 | #define MASK_SOFT_FLOAT 0x00000800 |
f85f4585 | 118 | |
4d30c363 | 119 | /* Enable load/store multiple, even on powerpc */ |
38c1f2d7 MM |
120 | #define MASK_MULTIPLE 0x00001000 |
121 | #define MASK_MULTIPLE_SET 0x00002000 | |
4d30c363 | 122 | |
7e69e155 | 123 | /* Use string instructions for block moves */ |
38c1f2d7 MM |
124 | #define MASK_STRING 0x00004000 |
125 | #define MASK_STRING_SET 0x00008000 | |
7e69e155 | 126 | |
38c1f2d7 MM |
127 | /* Disable update form of load/store */ |
128 | #define MASK_NO_UPDATE 0x00010000 | |
129 | ||
130 | /* Disable fused multiply/add operations */ | |
131 | #define MASK_NO_FUSED_MADD 0x00020000 | |
4697a36c | 132 | |
9ebbca7d GK |
133 | /* Nonzero if we need to schedule the prolog and epilog. */ |
134 | #define MASK_SCHED_PROLOG 0x00040000 | |
135 | ||
7e69e155 MM |
136 | #define TARGET_POWER (target_flags & MASK_POWER) |
137 | #define TARGET_POWER2 (target_flags & MASK_POWER2) | |
138 | #define TARGET_POWERPC (target_flags & MASK_POWERPC) | |
139 | #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT) | |
140 | #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT) | |
7e69e155 MM |
141 | #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS) |
142 | #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC) | |
143 | #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC) | |
144 | #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC) | |
145 | #define TARGET_64BIT (target_flags & MASK_64BIT) | |
146 | #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT) | |
147 | #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE) | |
148 | #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET) | |
149 | #define TARGET_STRING (target_flags & MASK_STRING) | |
938937d8 | 150 | #define TARGET_STRING_SET (target_flags & MASK_STRING_SET) |
38c1f2d7 MM |
151 | #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE) |
152 | #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD) | |
9ebbca7d | 153 | #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG) |
7e69e155 | 154 | |
2f3e5814 | 155 | #define TARGET_32BIT (! TARGET_64BIT) |
7e69e155 | 156 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) |
38c1f2d7 MM |
157 | #define TARGET_UPDATE (! TARGET_NO_UPDATE) |
158 | #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD) | |
d14a6d05 | 159 | |
996ed075 JJ |
160 | #ifdef IN_LIBGCC2 |
161 | /* For libgcc2 we make sure this is a compile time constant */ | |
996ed075 JJ |
162 | #ifdef __64BIT__ |
163 | #define TARGET_POWERPC64 1 | |
164 | #else | |
165 | #define TARGET_POWERPC64 0 | |
166 | #endif | |
b6c9286a | 167 | #else |
9ebbca7d | 168 | #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64) |
b6c9286a MM |
169 | #endif |
170 | ||
a3950905 | 171 | #define TARGET_XL_CALL 0 |
a3950905 | 172 | |
fb623df5 | 173 | /* Run-time compilation parameters selecting different hardware subsets. |
f045b2c9 | 174 | |
fb623df5 | 175 | Macro to define tables used to set the flags. |
f045b2c9 RS |
176 | This is a list in braces of pairs in braces, |
177 | each pair being { "NAME", VALUE } | |
178 | where VALUE is the bits to set or minus the bits to clear. | |
179 | An empty string NAME is used to identify the default VALUE. */ | |
180 | ||
938937d8 | 181 | #define TARGET_SWITCHES \ |
9ebbca7d | 182 | {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \ |
047142d3 | 183 | N_("Use POWER instruction set")}, \ |
938937d8 | 184 | {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \ |
9ebbca7d | 185 | | MASK_POWER2), \ |
047142d3 | 186 | N_("Use POWER2 instruction set")}, \ |
9ebbca7d | 187 | {"no-power2", - MASK_POWER2, \ |
047142d3 | 188 | N_("Do not use POWER2 instruction set")}, \ |
938937d8 | 189 | {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \ |
9ebbca7d | 190 | | MASK_STRING), \ |
047142d3 | 191 | N_("Do not use POWER instruction set")}, \ |
9ebbca7d | 192 | {"powerpc", MASK_POWERPC, \ |
047142d3 | 193 | N_("Use PowerPC instruction set")}, \ |
938937d8 | 194 | {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \ |
9ebbca7d | 195 | | MASK_PPC_GFXOPT | MASK_POWERPC64), \ |
047142d3 | 196 | N_("Do not use PowerPC instruction set")}, \ |
9ebbca7d | 197 | {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \ |
047142d3 | 198 | N_("Use PowerPC General Purpose group optional instructions")},\ |
9ebbca7d | 199 | {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \ |
047142d3 | 200 | N_("Don't use PowerPC General Purpose group optional instructions")},\ |
9ebbca7d | 201 | {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \ |
047142d3 | 202 | N_("Use PowerPC Graphics group optional instructions")},\ |
9ebbca7d | 203 | {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \ |
047142d3 | 204 | N_("Don't use PowerPC Graphics group optional instructions")},\ |
9ebbca7d | 205 | {"powerpc64", MASK_POWERPC64, \ |
047142d3 | 206 | N_("Use PowerPC-64 instruction set")}, \ |
9ebbca7d | 207 | {"no-powerpc64", - MASK_POWERPC64, \ |
047142d3 | 208 | N_("Don't use PowerPC-64 instruction set")}, \ |
9ebbca7d | 209 | {"new-mnemonics", MASK_NEW_MNEMONICS, \ |
047142d3 | 210 | N_("Use new mnemonics for PowerPC architecture")},\ |
9ebbca7d | 211 | {"old-mnemonics", -MASK_NEW_MNEMONICS, \ |
047142d3 | 212 | N_("Use old mnemonics for PowerPC architecture")},\ |
938937d8 | 213 | {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \ |
9ebbca7d | 214 | | MASK_MINIMAL_TOC), \ |
047142d3 | 215 | N_("Put everything in the regular TOC")}, \ |
9ebbca7d | 216 | {"fp-in-toc", - MASK_NO_FP_IN_TOC, \ |
047142d3 | 217 | N_("Place floating point constants in TOC")}, \ |
9ebbca7d | 218 | {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \ |
047142d3 | 219 | N_("Don't place floating point constants in TOC")},\ |
9ebbca7d | 220 | {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \ |
047142d3 | 221 | N_("Place symbol+offset constants in TOC")}, \ |
9ebbca7d | 222 | {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \ |
047142d3 | 223 | N_("Don't place symbol+offset constants in TOC")},\ |
9ebbca7d GK |
224 | {"minimal-toc", MASK_MINIMAL_TOC, \ |
225 | "Use only one TOC entry per procedure"}, \ | |
226 | {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \ | |
047142d3 | 227 | ""}, \ |
9ebbca7d | 228 | {"no-minimal-toc", - MASK_MINIMAL_TOC, \ |
047142d3 | 229 | N_("Place variable addresses in the regular TOC")},\ |
9ebbca7d | 230 | {"hard-float", - MASK_SOFT_FLOAT, \ |
047142d3 | 231 | N_("Use hardware fp")}, \ |
9ebbca7d | 232 | {"soft-float", MASK_SOFT_FLOAT, \ |
047142d3 | 233 | N_("Do not use hardware fp")}, \ |
9ebbca7d | 234 | {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \ |
047142d3 | 235 | N_("Generate load/store multiple instructions")}, \ |
9ebbca7d | 236 | {"no-multiple", - MASK_MULTIPLE, \ |
047142d3 | 237 | N_("Do not generate load/store multiple instructions")},\ |
9ebbca7d | 238 | {"no-multiple", MASK_MULTIPLE_SET, \ |
047142d3 | 239 | ""}, \ |
9ebbca7d | 240 | {"string", MASK_STRING | MASK_STRING_SET, \ |
047142d3 | 241 | N_("Generate string instructions for block moves")},\ |
9ebbca7d | 242 | {"no-string", - MASK_STRING, \ |
047142d3 | 243 | N_("Do not generate string instructions for block moves")},\ |
9ebbca7d | 244 | {"no-string", MASK_STRING_SET, \ |
047142d3 | 245 | ""}, \ |
9ebbca7d | 246 | {"update", - MASK_NO_UPDATE, \ |
047142d3 | 247 | N_("Generate load/store with update instructions")},\ |
9ebbca7d | 248 | {"no-update", MASK_NO_UPDATE, \ |
047142d3 | 249 | N_("Do not generate load/store with update instructions")},\ |
9ebbca7d | 250 | {"fused-madd", - MASK_NO_FUSED_MADD, \ |
047142d3 | 251 | N_("Generate fused multiply/add instructions")},\ |
9ebbca7d | 252 | {"no-fused-madd", MASK_NO_FUSED_MADD, \ |
047142d3 | 253 | N_("Don't generate fused multiply/add instructions")},\ |
9ebbca7d GK |
254 | {"sched-prolog", MASK_SCHED_PROLOG, \ |
255 | ""}, \ | |
256 | {"no-sched-prolog", -MASK_SCHED_PROLOG, \ | |
047142d3 | 257 | N_("Don't schedule the start and end of the procedure")},\ |
9ebbca7d GK |
258 | {"sched-epilog", MASK_SCHED_PROLOG, \ |
259 | ""}, \ | |
260 | {"no-sched-epilog", -MASK_SCHED_PROLOG, \ | |
261 | ""}, \ | |
938937d8 | 262 | SUBTARGET_SWITCHES \ |
9ebbca7d GK |
263 | {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \ |
264 | ""}} | |
fb623df5 | 265 | |
938937d8 | 266 | #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING) |
9ebbca7d GK |
267 | |
268 | /* This is meant to be redefined in the host dependent files */ | |
269 | #define SUBTARGET_SWITCHES | |
fb623df5 | 270 | |
cac8ce95 | 271 | /* Processor type. Order must match cpu attribute in MD file. */ |
fb623df5 | 272 | enum processor_type |
bef84347 VM |
273 | { |
274 | PROCESSOR_RIOS1, | |
275 | PROCESSOR_RIOS2, | |
3cb999d8 | 276 | PROCESSOR_RS64A, |
bef84347 VM |
277 | PROCESSOR_MPCCORE, |
278 | PROCESSOR_PPC403, | |
279 | PROCESSOR_PPC601, | |
280 | PROCESSOR_PPC603, | |
281 | PROCESSOR_PPC604, | |
282 | PROCESSOR_PPC604e, | |
283 | PROCESSOR_PPC620, | |
3cb999d8 | 284 | PROCESSOR_PPC630, |
bef84347 VM |
285 | PROCESSOR_PPC750 |
286 | }; | |
fb623df5 RK |
287 | |
288 | extern enum processor_type rs6000_cpu; | |
289 | ||
290 | /* Recast the processor type to the cpu attribute. */ | |
291 | #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) | |
292 | ||
8482e358 | 293 | /* Define generic processor types based upon current deployment. */ |
3cb999d8 DE |
294 | #define PROCESSOR_COMMON PROCESSOR_PPC601 |
295 | #define PROCESSOR_POWER PROCESSOR_RIOS1 | |
296 | #define PROCESSOR_POWERPC PROCESSOR_PPC604 | |
297 | #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
6e151478 | 298 | |
fb623df5 | 299 | /* Define the default processor. This is overridden by other tm.h files. */ |
3cb999d8 DE |
300 | #define PROCESSOR_DEFAULT PROCESSOR_RIOS1 |
301 | #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A | |
fb623df5 | 302 | |
6febd581 RK |
303 | /* Specify the dialect of assembler to use. New mnemonics is dialect one |
304 | and the old mnemonics are dialect zero. */ | |
9ebbca7d | 305 | #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0) |
6febd581 | 306 | |
fb623df5 RK |
307 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
308 | command options that have values. Its definition is an | |
309 | initializer with a subgrouping for each command option. | |
310 | ||
311 | Each subgrouping contains a string constant, that defines the | |
312 | fixed part of the option name, and the address of a variable. | |
313 | The variable, type `char *', is set to the variable part of the | |
314 | given option if the fixed part matches. The actual option name | |
315 | is made by appending `-m' to the specified name. | |
316 | ||
317 | Here is an example which defines `-mshort-data-NUMBER'. If the | |
318 | given option is `-mshort-data-512', the variable `m88k_short_data' | |
319 | will be set to the string `"512"'. | |
320 | ||
321 | extern char *m88k_short_data; | |
322 | #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */ | |
323 | ||
956d6950 | 324 | /* This is meant to be overridden in target specific files. */ |
b6c9286a | 325 | #define SUBTARGET_OPTIONS |
b6c9286a | 326 | |
9ebbca7d GK |
327 | #define TARGET_OPTIONS \ |
328 | { \ | |
047142d3 PT |
329 | {"cpu=", &rs6000_select[1].string, \ |
330 | N_("Use features of and schedule code for given CPU") }, \ | |
331 | {"tune=", &rs6000_select[2].string, \ | |
332 | N_("Schedule code for given CPU") }, \ | |
333 | {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \ | |
9ebbca7d | 334 | SUBTARGET_OPTIONS \ |
b6c9286a | 335 | } |
fb623df5 | 336 | |
ff222560 | 337 | /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */ |
8e3f41e7 MM |
338 | struct rs6000_cpu_select |
339 | { | |
815cdc52 MM |
340 | const char *string; |
341 | const char *name; | |
8e3f41e7 MM |
342 | int set_tune_p; |
343 | int set_arch_p; | |
344 | }; | |
345 | ||
346 | extern struct rs6000_cpu_select rs6000_select[]; | |
fb623df5 | 347 | |
38c1f2d7 | 348 | /* Debug support */ |
815cdc52 | 349 | extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */ |
38c1f2d7 MM |
350 | extern int rs6000_debug_stack; /* debug stack applications */ |
351 | extern int rs6000_debug_arg; /* debug argument handling */ | |
352 | ||
353 | #define TARGET_DEBUG_STACK rs6000_debug_stack | |
354 | #define TARGET_DEBUG_ARG rs6000_debug_arg | |
355 | ||
fb623df5 RK |
356 | /* Sometimes certain combinations of command options do not make sense |
357 | on a particular target machine. You can define a macro | |
358 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
359 | defined, is executed once just after all the command options have | |
360 | been parsed. | |
361 | ||
5accd822 DE |
362 | Don't use this macro to turn on various extra optimizations for |
363 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. | |
364 | ||
fb623df5 RK |
365 | On the RS/6000 this is used to define the target cpu type. */ |
366 | ||
8e3f41e7 | 367 | #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT) |
f045b2c9 | 368 | |
5accd822 DE |
369 | /* Define this to change the optimizations performed by default. */ |
370 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE) | |
371 | ||
4f074454 RK |
372 | /* Show we can debug even without a frame pointer. */ |
373 | #define CAN_DEBUG_WITHOUT_FP | |
f045b2c9 RS |
374 | \f |
375 | /* target machine storage layout */ | |
376 | ||
df44fa77 RK |
377 | /* Define to support cross compilation to an RS6000 target. */ |
378 | #define REAL_ARITHMETIC | |
379 | ||
13d39dbc | 380 | /* Define this macro if it is advisable to hold scalars in registers |
c81bebd7 | 381 | in a wider mode than that declared by the program. In such cases, |
ef457bda RK |
382 | the value is constrained to be within the bounds of the declared |
383 | type, but kept valid in the wider mode. The signedness of the | |
384 | extension may differ from that of the type. */ | |
385 | ||
39403d82 DE |
386 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
387 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
388 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
3cb999d8 | 389 | (MODE) = word_mode; |
39403d82 DE |
390 | |
391 | /* Define this if function arguments should also be promoted using the above | |
392 | procedure. */ | |
393 | ||
394 | #define PROMOTE_FUNCTION_ARGS | |
395 | ||
396 | /* Likewise, if the function return value is promoted. */ | |
397 | ||
398 | #define PROMOTE_FUNCTION_RETURN | |
ef457bda | 399 | |
f045b2c9 RS |
400 | /* Define this if most significant bit is lowest numbered |
401 | in instructions that operate on numbered bit-fields. */ | |
402 | /* That is true on RS/6000. */ | |
403 | #define BITS_BIG_ENDIAN 1 | |
404 | ||
405 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
406 | /* That is true on RS/6000. */ | |
407 | #define BYTES_BIG_ENDIAN 1 | |
408 | ||
409 | /* Define this if most significant word of a multiword number is lowest | |
c81bebd7 | 410 | numbered. |
f045b2c9 RS |
411 | |
412 | For RS/6000 we can decide arbitrarily since there are no machine | |
413 | instructions for them. Might as well be consistent with bits and bytes. */ | |
414 | #define WORDS_BIG_ENDIAN 1 | |
415 | ||
fdaff8ba | 416 | /* number of bits in an addressable storage unit */ |
f045b2c9 RS |
417 | #define BITS_PER_UNIT 8 |
418 | ||
419 | /* Width in bits of a "word", which is the contents of a machine register. | |
420 | Note that this is not necessarily the width of data type `int'; | |
421 | if using 16-bit ints on a 68000, this would still be 32. | |
422 | But on a machine with 16-bit registers, this would be 16. */ | |
2f3e5814 | 423 | #define BITS_PER_WORD (! TARGET_POWERPC64 ? 32 : 64) |
2e360ab3 | 424 | #define MAX_BITS_PER_WORD 64 |
f045b2c9 RS |
425 | |
426 | /* Width of a word, in units (bytes). */ | |
2f3e5814 | 427 | #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) |
ef0e53ce | 428 | #define MIN_UNITS_PER_WORD 4 |
2e360ab3 | 429 | #define UNITS_PER_FP_WORD 8 |
f045b2c9 | 430 | |
915f619f JW |
431 | /* Type used for ptrdiff_t, as a string used in a declaration. */ |
432 | #define PTRDIFF_TYPE "int" | |
433 | ||
058ef853 DE |
434 | /* Type used for size_t, as a string used in a declaration. */ |
435 | #define SIZE_TYPE "long unsigned int" | |
436 | ||
f045b2c9 RS |
437 | /* Type used for wchar_t, as a string used in a declaration. */ |
438 | #define WCHAR_TYPE "short unsigned int" | |
439 | ||
440 | /* Width of wchar_t in bits. */ | |
441 | #define WCHAR_TYPE_SIZE 16 | |
442 | ||
9e654916 RK |
443 | /* A C expression for the size in bits of the type `short' on the |
444 | target machine. If you don't define this, the default is half a | |
445 | word. (If this would be less than one storage unit, it is | |
446 | rounded up to one unit.) */ | |
447 | #define SHORT_TYPE_SIZE 16 | |
448 | ||
449 | /* A C expression for the size in bits of the type `int' on the | |
450 | target machine. If you don't define this, the default is one | |
451 | word. */ | |
19d2d16f | 452 | #define INT_TYPE_SIZE 32 |
9e654916 RK |
453 | |
454 | /* A C expression for the size in bits of the type `long' on the | |
455 | target machine. If you don't define this, the default is one | |
456 | word. */ | |
2f3e5814 | 457 | #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) |
9e654916 RK |
458 | #define MAX_LONG_TYPE_SIZE 64 |
459 | ||
460 | /* A C expression for the size in bits of the type `long long' on the | |
461 | target machine. If you don't define this, the default is two | |
462 | words. */ | |
463 | #define LONG_LONG_TYPE_SIZE 64 | |
464 | ||
465 | /* A C expression for the size in bits of the type `char' on the | |
466 | target machine. If you don't define this, the default is one | |
467 | quarter of a word. (If this would be less than one storage unit, | |
468 | it is rounded up to one unit.) */ | |
469 | #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
470 | ||
471 | /* A C expression for the size in bits of the type `float' on the | |
472 | target machine. If you don't define this, the default is one | |
473 | word. */ | |
474 | #define FLOAT_TYPE_SIZE 32 | |
475 | ||
476 | /* A C expression for the size in bits of the type `double' on the | |
477 | target machine. If you don't define this, the default is two | |
478 | words. */ | |
479 | #define DOUBLE_TYPE_SIZE 64 | |
480 | ||
481 | /* A C expression for the size in bits of the type `long double' on | |
482 | the target machine. If you don't define this, the default is two | |
483 | words. */ | |
484 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
485 | ||
f045b2c9 RS |
486 | /* Width in bits of a pointer. |
487 | See also the macro `Pmode' defined below. */ | |
2f3e5814 | 488 | #define POINTER_SIZE (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
489 | |
490 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
2f3e5814 | 491 | #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
492 | |
493 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
a260abc9 | 494 | #define STACK_BOUNDARY (TARGET_32BIT ? 64 : 128) |
f045b2c9 RS |
495 | |
496 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
497 | #define FUNCTION_BOUNDARY 32 | |
498 | ||
499 | /* No data type wants to be aligned rounder than this. */ | |
b73fd26c DE |
500 | #define BIGGEST_ALIGNMENT 64 |
501 | ||
e1565e65 DE |
502 | /* Handle #pragma pack. */ |
503 | #define HANDLE_PRAGMA_PACK 1 | |
504 | ||
f045b2c9 RS |
505 | /* Alignment of field after `int : 0' in a structure. */ |
506 | #define EMPTY_FIELD_BOUNDARY 32 | |
507 | ||
508 | /* Every structure's size must be a multiple of this. */ | |
509 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
510 | ||
511 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
512 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
513 | ||
514 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
515 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
516 | (TREE_CODE (EXP) == STRING_CST \ | |
517 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
518 | ||
519 | /* Make arrays of chars word-aligned for the same reasons. */ | |
520 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
521 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
522 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
523 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
524 | ||
fdaff8ba | 525 | /* Non-zero if move instructions will actually fail to work |
f045b2c9 | 526 | when given unaligned data. */ |
fdaff8ba | 527 | #define STRICT_ALIGNMENT 0 |
e1565e65 DE |
528 | |
529 | /* Define this macro to be the value 1 if unaligned accesses have a cost | |
530 | many times greater than aligned accesses, for example if they are | |
531 | emulated in a trap handler. */ | |
532 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ | |
9ebbca7d GK |
533 | ((STRICT_ALIGNMENT \ |
534 | || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \ | |
19caa751 | 535 | && (ALIGN) < 32)) ? 1 : 0) |
f045b2c9 RS |
536 | \f |
537 | /* Standard register usage. */ | |
538 | ||
539 | /* Number of actual hardware registers. | |
540 | The hardware registers are assigned numbers for the compiler | |
541 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
542 | All registers that the compiler knows about must be given numbers, | |
543 | even those that are not normally considered general registers. | |
544 | ||
545 | RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
546 | an MQ register, a count register, a link register, and 8 condition | |
547 | register fields, which we view here as separate registers. | |
548 | ||
549 | In addition, the difference between the frame and argument pointers is | |
550 | a function of the number of registers saved, so we need to have a | |
551 | register for AP that will later be eliminated in favor of SP or FP. | |
802a0058 | 552 | This is a normal register, but it is fixed. |
f045b2c9 | 553 | |
802a0058 MM |
554 | We also create a pseudo register for float/int conversions, that will |
555 | really represent the memory location used. It is represented here as | |
556 | a register, in order to work around problems in allocating stack storage | |
557 | in inline functions. */ | |
558 | ||
559 | #define FIRST_PSEUDO_REGISTER 77 | |
f045b2c9 | 560 | |
62153b61 JM |
561 | /* This must not decrease, for backwards compatibility. If |
562 | FIRST_PSEUDO_REGISTER increases, this should as well. */ | |
563 | #define DWARF_FRAME_REGISTERS 77 | |
564 | ||
f045b2c9 RS |
565 | /* 1 for registers that have pervasive standard uses |
566 | and are not available for the register allocator. | |
567 | ||
c81bebd7 | 568 | On RS/6000, r1 is used for the stack and r2 is used as the TOC pointer. |
f045b2c9 | 569 | |
a127c4e5 RK |
570 | cr5 is not supposed to be used. |
571 | ||
572 | On System V implementations, r13 is fixed and not available for use. */ | |
573 | ||
f045b2c9 | 574 | #define FIXED_REGISTERS \ |
a127c4e5 | 575 | {0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
576 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
577 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
578 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
802a0058 | 579 | 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1} |
f045b2c9 RS |
580 | |
581 | /* 1 for registers not available across function calls. | |
582 | These must include the FIXED_REGISTERS and also any | |
583 | registers that can be used without being saved. | |
584 | The latter must include the registers where values are returned | |
585 | and the register where structure-value addresses are passed. | |
586 | Aside from that, you can include as many other registers as you like. */ | |
587 | ||
588 | #define CALL_USED_REGISTERS \ | |
a127c4e5 | 589 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
590 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
591 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
592 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
802a0058 | 593 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1} |
f045b2c9 | 594 | |
9ebbca7d GK |
595 | #define MQ_REGNO 64 |
596 | #define CR0_REGNO 68 | |
597 | #define CR1_REGNO 69 | |
598 | #define CR2_REGNO 70 | |
599 | #define CR3_REGNO 71 | |
600 | #define CR4_REGNO 72 | |
601 | #define MAX_CR_REGNO 75 | |
602 | #define XER_REGNO 76 | |
603 | ||
f045b2c9 RS |
604 | /* List the order in which to allocate registers. Each register must be |
605 | listed once, even those in FIXED_REGISTERS. | |
606 | ||
607 | We allocate in the following order: | |
608 | fp0 (not saved or used for anything) | |
609 | fp13 - fp2 (not saved; incoming fp arg registers) | |
610 | fp1 (not saved; return value) | |
611 | fp31 - fp14 (saved; order given to save least number) | |
5accd822 DE |
612 | cr7, cr6 (not saved or special) |
613 | cr1 (not saved, but used for FP operations) | |
f045b2c9 | 614 | cr0 (not saved, but used for arithmetic operations) |
5accd822 | 615 | cr4, cr3, cr2 (saved) |
f045b2c9 RS |
616 | r0 (not saved; cannot be base reg) |
617 | r9 (not saved; best for TImode) | |
618 | r11, r10, r8-r4 (not saved; highest used first to make less conflict) | |
619 | r3 (not saved; return value register) | |
620 | r31 - r13 (saved; order given to save least number) | |
621 | r12 (not saved; if used for DImode or DFmode would use r13) | |
622 | mq (not saved; best to use it if we can) | |
623 | ctr (not saved; when we have the choice ctr is better) | |
624 | lr (saved) | |
9ebbca7d | 625 | cr5, r1, r2, ap, xer (fixed) */ |
f045b2c9 RS |
626 | |
627 | #define REG_ALLOC_ORDER \ | |
628 | {32, \ | |
629 | 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ | |
630 | 33, \ | |
631 | 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
632 | 50, 49, 48, 47, 46, \ | |
5accd822 | 633 | 75, 74, 69, 68, 72, 71, 70, \ |
f045b2c9 RS |
634 | 0, \ |
635 | 9, 11, 10, 8, 7, 6, 5, 4, \ | |
636 | 3, \ | |
637 | 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ | |
638 | 18, 17, 16, 15, 14, 13, 12, \ | |
639 | 64, 66, 65, \ | |
802a0058 | 640 | 73, 1, 2, 67, 76} |
f045b2c9 RS |
641 | |
642 | /* True if register is floating-point. */ | |
643 | #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
644 | ||
645 | /* True if register is a condition register. */ | |
646 | #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75) | |
647 | ||
815cdc52 MM |
648 | /* True if register is a condition register, but not cr0. */ |
649 | #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75) | |
650 | ||
f045b2c9 | 651 | /* True if register is an integer register. */ |
9ebbca7d | 652 | #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM) |
f045b2c9 | 653 | |
0d86f538 | 654 | /* True if register is the XER register. */ |
9ebbca7d | 655 | #define XER_REGNO_P(N) ((N) == XER_REGNO) |
802a0058 | 656 | |
f045b2c9 RS |
657 | /* Return number of consecutive hard regs needed starting at reg REGNO |
658 | to hold something of mode MODE. | |
659 | This is ordinarily the length in words of a value of mode MODE | |
660 | but can be less for certain modes in special long registers. | |
661 | ||
a260abc9 DE |
662 | POWER and PowerPC GPRs hold 32 bits worth; |
663 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
f045b2c9 | 664 | |
802a0058 | 665 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
9ebbca7d | 666 | (FP_REGNO_P (REGNO) \ |
2e360ab3 | 667 | ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ |
f045b2c9 RS |
668 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
669 | ||
670 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
bdfd4e31 RK |
671 | For POWER and PowerPC, the GPRs can hold any mode, but the float |
672 | registers only can hold floating modes and DImode, and CR register only | |
673 | can hold CC modes. We cannot put TImode anywhere except general | |
674 | register and it must be able to fit within the register set. */ | |
f045b2c9 | 675 | |
802a0058 MM |
676 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
677 | (FP_REGNO_P (REGNO) ? \ | |
678 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
679 | || (GET_MODE_CLASS (MODE) == MODE_INT \ | |
680 | && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \ | |
681 | : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \ | |
9ebbca7d | 682 | : XER_REGNO_P (REGNO) ? (MODE) == PSImode \ |
802a0058 | 683 | : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \ |
bdfd4e31 | 684 | && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \ |
f045b2c9 RS |
685 | : 1) |
686 | ||
687 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
688 | when one has mode MODE1 and one has mode MODE2. | |
689 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
690 | for any hard reg, then this must be 0 for correct output. */ | |
691 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
692 | (GET_MODE_CLASS (MODE1) == MODE_FLOAT \ | |
693 | ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
694 | : GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
695 | ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \ | |
696 | : GET_MODE_CLASS (MODE1) == MODE_CC \ | |
697 | ? GET_MODE_CLASS (MODE2) == MODE_CC \ | |
698 | : GET_MODE_CLASS (MODE2) == MODE_CC \ | |
699 | ? GET_MODE_CLASS (MODE1) == MODE_CC \ | |
700 | : 1) | |
701 | ||
702 | /* A C expression returning the cost of moving data from a register of class | |
703 | CLASS1 to one of CLASS2. | |
704 | ||
705 | On the RS/6000, copying between floating-point and fixed-point | |
706 | registers is expensive. */ | |
707 | ||
cf011243 | 708 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
2bfcf297 | 709 | ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \ |
f045b2c9 RS |
710 | : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \ |
711 | : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \ | |
a4b970a0 | 712 | : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \ |
5119dc13 RK |
713 | || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \ |
714 | || (CLASS1) == LINK_OR_CTR_REGS) \ | |
a4b970a0 | 715 | && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \ |
5119dc13 | 716 | || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \ |
802a0058 | 717 | || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \ |
f045b2c9 RS |
718 | : 2) |
719 | ||
720 | /* A C expressions returning the cost of moving data of MODE from a register to | |
721 | or from memory. | |
722 | ||
723 | On the RS/6000, bump this up a bit. */ | |
724 | ||
e1565e65 DE |
725 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ |
726 | ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
ab4a5fc9 RK |
727 | && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \ |
728 | ? 3 : 2) \ | |
729 | + 4) | |
f045b2c9 RS |
730 | |
731 | /* Specify the cost of a branch insn; roughly the number of extra insns that | |
732 | should be added to avoid a branch. | |
733 | ||
ef457bda | 734 | Set this to 3 on the RS/6000 since that is roughly the average cost of an |
f045b2c9 RS |
735 | unscheduled conditional branch. */ |
736 | ||
ef457bda | 737 | #define BRANCH_COST 3 |
f045b2c9 | 738 | |
5a5e4c2c RK |
739 | /* A C statement (sans semicolon) to update the integer variable COST |
740 | based on the relationship between INSN that is dependent on | |
741 | DEP_INSN through the dependence LINK. The default is to make no | |
742 | adjustment to COST. On the RS/6000, ignore the cost of anti- and | |
743 | output-dependencies. In fact, output dependencies on the CR do have | |
744 | a cost, but it is probably not worthwhile to track it. */ | |
745 | ||
e1565e65 | 746 | #define ADJUST_COST(INSN, LINK, DEP_INSN, COST) \ |
b0634e74 | 747 | (COST) = rs6000_adjust_cost (INSN,LINK,DEP_INSN,COST) |
5a5e4c2c | 748 | |
bef84347 VM |
749 | /* A C statement (sans semicolon) to update the integer scheduling priority |
750 | INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier, | |
751 | increase the priority to execute INSN later. Do not define this macro if | |
752 | you do not need to adjust the scheduling priorities of insns. */ | |
753 | ||
754 | #define ADJUST_PRIORITY(INSN) \ | |
755 | INSN_PRIORITY (INSN) = rs6000_adjust_priority (INSN, INSN_PRIORITY (INSN)) | |
756 | ||
6febd581 RK |
757 | /* Define this macro to change register usage conditional on target flags. |
758 | Set MQ register fixed (already call_used) if not POWER architecture | |
f85f4585 | 759 | (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated. |
a238cd8b | 760 | 64-bit AIX reserves GPR13 for thread-private data. |
f85f4585 RK |
761 | Conditionally disable FPRs. */ |
762 | ||
8d30c4ee FS |
763 | #define CONDITIONAL_REGISTER_USAGE \ |
764 | { \ | |
765 | if (! TARGET_POWER) \ | |
766 | fixed_regs[64] = 1; \ | |
767 | if (TARGET_64BIT) \ | |
768 | fixed_regs[13] = call_used_regs[13] = 1; \ | |
769 | if (TARGET_SOFT_FLOAT) \ | |
770 | for (i = 32; i < 64; i++) \ | |
771 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
772 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \ | |
773 | && flag_pic == 1) \ | |
774 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ | |
775 | = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
ee890fe2 SS |
776 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic) \ |
777 | global_regs[PIC_OFFSET_TABLE_REGNUM] \ | |
778 | = fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ | |
779 | = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
f85f4585 | 780 | } |
6febd581 | 781 | |
f045b2c9 RS |
782 | /* Specify the registers used for certain standard purposes. |
783 | The values of these macros are register numbers. */ | |
784 | ||
785 | /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
786 | /* #define PC_REGNUM */ | |
787 | ||
788 | /* Register to use for pushing function arguments. */ | |
789 | #define STACK_POINTER_REGNUM 1 | |
790 | ||
791 | /* Base register for access to local variables of the function. */ | |
792 | #define FRAME_POINTER_REGNUM 31 | |
793 | ||
794 | /* Value should be nonzero if functions must have frame pointers. | |
795 | Zero means the frame pointer need not be set up (and parms | |
796 | may be accessed via the stack pointer) in functions that seem suitable. | |
797 | This is computed in `reload', in reload1.c. */ | |
798 | #define FRAME_POINTER_REQUIRED 0 | |
799 | ||
800 | /* Base register for access to arguments of the function. */ | |
801 | #define ARG_POINTER_REGNUM 67 | |
802 | ||
803 | /* Place to put static chain when calling a function that requires it. */ | |
804 | #define STATIC_CHAIN_REGNUM 11 | |
805 | ||
9ebbca7d GK |
806 | /* Link register number. */ |
807 | #define LINK_REGISTER_REGNUM 65 | |
b6c9286a | 808 | |
9ebbca7d GK |
809 | /* Count register number. */ |
810 | #define COUNT_REGISTER_REGNUM 66 | |
802a0058 | 811 | |
f045b2c9 RS |
812 | /* Place that structure value return address is placed. |
813 | ||
814 | On the RS/6000, it is passed as an extra parameter. */ | |
1ff7789b | 815 | #define STRUCT_VALUE 0 |
f045b2c9 RS |
816 | \f |
817 | /* Define the classes of registers for register constraints in the | |
818 | machine description. Also define ranges of constants. | |
819 | ||
820 | One of the classes must always be named ALL_REGS and include all hard regs. | |
821 | If there is more than one class, another class must be named NO_REGS | |
822 | and contain no registers. | |
823 | ||
824 | The name GENERAL_REGS must be the name of a class (or an alias for | |
825 | another name such as ALL_REGS). This is the class of registers | |
826 | that is allowed by "g" or "r" in a register constraint. | |
827 | Also, registers outside this class are allocated only when | |
828 | instructions express preferences for them. | |
829 | ||
830 | The classes must be numbered in nondecreasing order; that is, | |
831 | a larger-numbered class must never be contained completely | |
832 | in a smaller-numbered class. | |
833 | ||
834 | For any two classes, it is very desirable that there be another | |
835 | class that represents their union. */ | |
c81bebd7 | 836 | |
f045b2c9 RS |
837 | /* The RS/6000 has three types of registers, fixed-point, floating-point, |
838 | and condition registers, plus three special registers, MQ, CTR, and the | |
839 | link register. | |
840 | ||
841 | However, r0 is special in that it cannot be used as a base register. | |
842 | So make a class for registers valid as base registers. | |
843 | ||
844 | Also, cr0 is the only condition code register that can be used in | |
0d86f538 | 845 | arithmetic insns, so make a separate class for it. */ |
f045b2c9 | 846 | |
ebedb4dd MM |
847 | enum reg_class |
848 | { | |
849 | NO_REGS, | |
ebedb4dd MM |
850 | BASE_REGS, |
851 | GENERAL_REGS, | |
852 | FLOAT_REGS, | |
853 | NON_SPECIAL_REGS, | |
854 | MQ_REGS, | |
855 | LINK_REGS, | |
856 | CTR_REGS, | |
857 | LINK_OR_CTR_REGS, | |
858 | SPECIAL_REGS, | |
859 | SPEC_OR_GEN_REGS, | |
860 | CR0_REGS, | |
ebedb4dd MM |
861 | CR_REGS, |
862 | NON_FLOAT_REGS, | |
9ebbca7d | 863 | XER_REGS, |
ebedb4dd MM |
864 | ALL_REGS, |
865 | LIM_REG_CLASSES | |
866 | }; | |
f045b2c9 RS |
867 | |
868 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
869 | ||
870 | /* Give names of register classes as strings for dump file. */ | |
871 | ||
ebedb4dd MM |
872 | #define REG_CLASS_NAMES \ |
873 | { \ | |
874 | "NO_REGS", \ | |
ebedb4dd MM |
875 | "BASE_REGS", \ |
876 | "GENERAL_REGS", \ | |
877 | "FLOAT_REGS", \ | |
878 | "NON_SPECIAL_REGS", \ | |
879 | "MQ_REGS", \ | |
880 | "LINK_REGS", \ | |
881 | "CTR_REGS", \ | |
882 | "LINK_OR_CTR_REGS", \ | |
883 | "SPECIAL_REGS", \ | |
884 | "SPEC_OR_GEN_REGS", \ | |
885 | "CR0_REGS", \ | |
ebedb4dd MM |
886 | "CR_REGS", \ |
887 | "NON_FLOAT_REGS", \ | |
9ebbca7d | 888 | "XER_REGS", \ |
ebedb4dd MM |
889 | "ALL_REGS" \ |
890 | } | |
f045b2c9 RS |
891 | |
892 | /* Define which registers fit in which classes. | |
893 | This is an initializer for a vector of HARD_REG_SET | |
894 | of length N_REG_CLASSES. */ | |
895 | ||
ebedb4dd MM |
896 | #define REG_CLASS_CONTENTS \ |
897 | { \ | |
898 | { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
ebedb4dd MM |
899 | { 0xfffffffe, 0x00000000, 0x00000008 }, /* BASE_REGS */ \ |
900 | { 0xffffffff, 0x00000000, 0x00000008 }, /* GENERAL_REGS */ \ | |
901 | { 0x00000000, 0xffffffff, 0x00000000 }, /* FLOAT_REGS */ \ | |
902 | { 0xffffffff, 0xffffffff, 0x00000008 }, /* NON_SPECIAL_REGS */ \ | |
903 | { 0x00000000, 0x00000000, 0x00000001 }, /* MQ_REGS */ \ | |
904 | { 0x00000000, 0x00000000, 0x00000002 }, /* LINK_REGS */ \ | |
905 | { 0x00000000, 0x00000000, 0x00000004 }, /* CTR_REGS */ \ | |
906 | { 0x00000000, 0x00000000, 0x00000006 }, /* LINK_OR_CTR_REGS */ \ | |
907 | { 0x00000000, 0x00000000, 0x00000007 }, /* SPECIAL_REGS */ \ | |
908 | { 0xffffffff, 0x00000000, 0x0000000f }, /* SPEC_OR_GEN_REGS */ \ | |
909 | { 0x00000000, 0x00000000, 0x00000010 }, /* CR0_REGS */ \ | |
ebedb4dd MM |
910 | { 0x00000000, 0x00000000, 0x00000ff0 }, /* CR_REGS */ \ |
911 | { 0xffffffff, 0x00000000, 0x0000ffff }, /* NON_FLOAT_REGS */ \ | |
9ebbca7d | 912 | { 0x00000000, 0x00000000, 0x00010000 }, /* XER_REGS */ \ |
802a0058 | 913 | { 0xffffffff, 0xffffffff, 0x0001ffff } /* ALL_REGS */ \ |
ebedb4dd | 914 | } |
f045b2c9 RS |
915 | |
916 | /* The same information, inverted: | |
917 | Return the class number of the smallest class containing | |
918 | reg number REGNO. This could be a conditional expression | |
919 | or could index an array. */ | |
920 | ||
0d86f538 GK |
921 | #define REGNO_REG_CLASS(REGNO) \ |
922 | ((REGNO) == 0 ? GENERAL_REGS \ | |
923 | : (REGNO) < 32 ? BASE_REGS \ | |
924 | : FP_REGNO_P (REGNO) ? FLOAT_REGS \ | |
925 | : (REGNO) == CR0_REGNO ? CR0_REGS \ | |
926 | : CR_REGNO_P (REGNO) ? CR_REGS \ | |
927 | : (REGNO) == MQ_REGNO ? MQ_REGS \ | |
928 | : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \ | |
929 | : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \ | |
930 | : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \ | |
931 | : (REGNO) == XER_REGNO ? XER_REGS \ | |
f045b2c9 RS |
932 | : NO_REGS) |
933 | ||
934 | /* The class value for index registers, and the one for base regs. */ | |
935 | #define INDEX_REG_CLASS GENERAL_REGS | |
936 | #define BASE_REG_CLASS BASE_REGS | |
937 | ||
938 | /* Get reg_class from a letter such as appears in the machine description. */ | |
939 | ||
940 | #define REG_CLASS_FROM_LETTER(C) \ | |
941 | ((C) == 'f' ? FLOAT_REGS \ | |
942 | : (C) == 'b' ? BASE_REGS \ | |
943 | : (C) == 'h' ? SPECIAL_REGS \ | |
944 | : (C) == 'q' ? MQ_REGS \ | |
945 | : (C) == 'c' ? CTR_REGS \ | |
946 | : (C) == 'l' ? LINK_REGS \ | |
947 | : (C) == 'x' ? CR0_REGS \ | |
948 | : (C) == 'y' ? CR_REGS \ | |
9ebbca7d | 949 | : (C) == 'z' ? XER_REGS \ |
f045b2c9 RS |
950 | : NO_REGS) |
951 | ||
952 | /* The letters I, J, K, L, M, N, and P in a register constraint string | |
953 | can be used to stand for particular ranges of immediate operands. | |
954 | This macro defines what the ranges are. | |
955 | C is the letter, and VALUE is a constant value. | |
956 | Return 1 if VALUE is in the range specified by C. | |
957 | ||
9615f239 | 958 | `I' is a signed 16-bit constant |
f045b2c9 RS |
959 | `J' is a constant with only the high-order 16 bits non-zero |
960 | `K' is a constant with only the low-order 16 bits non-zero | |
9615f239 | 961 | `L' is a signed 16-bit constant shifted left 16 bits |
f045b2c9 | 962 | `M' is a constant that is greater than 31 |
2bfcf297 | 963 | `N' is a positive constant that is an exact power of two |
f045b2c9 RS |
964 | `O' is the constant zero |
965 | `P' is a constant whose negation is a signed 16-bit constant */ | |
966 | ||
5b6f7b96 RK |
967 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
968 | ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \ | |
0858c623 | 969 | : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \ |
a260abc9 | 970 | : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \ |
9615f239 DE |
971 | : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \ |
972 | && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \ | |
5b6f7b96 | 973 | : (C) == 'M' ? (VALUE) > 31 \ |
2bfcf297 | 974 | : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \ |
5b6f7b96 | 975 | : (C) == 'O' ? (VALUE) == 0 \ |
9615f239 | 976 | : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \ |
f045b2c9 RS |
977 | : 0) |
978 | ||
979 | /* Similar, but for floating constants, and defining letters G and H. | |
980 | Here VALUE is the CONST_DOUBLE rtx itself. | |
981 | ||
982 | We flag for special constants when we can copy the constant into | |
4e74d8ec | 983 | a general register in two insns for DF/DI and one insn for SF. |
f045b2c9 | 984 | |
c4c40373 | 985 | 'H' is used for DI/DF constants that take 3 insns. */ |
4e74d8ec MM |
986 | |
987 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
c4c40373 MM |
988 | ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \ |
989 | == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \ | |
990 | : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \ | |
991 | : 0) | |
f045b2c9 RS |
992 | |
993 | /* Optional extra constraints for this machine. | |
994 | ||
b6c9286a MM |
995 | 'Q' means that is a memory operand that is just an offset from a reg. |
996 | 'R' is for AIX TOC entries. | |
a260abc9 | 997 | 'S' is a constant that can be placed into a 64-bit mask operand |
9615f239 | 998 | 'T' is a consatnt that can be placed into a 32-bit mask operand |
88228c4b | 999 | 'U' is for V.4 small data references. */ |
f045b2c9 | 1000 | |
e8a8bc24 RK |
1001 | #define EXTRA_CONSTRAINT(OP, C) \ |
1002 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ | |
d537c24d | 1003 | : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \ |
a260abc9 | 1004 | : (C) == 'S' ? mask64_operand (OP, VOIDmode) \ |
9615f239 | 1005 | : (C) == 'T' ? mask_operand (OP, VOIDmode) \ |
c81bebd7 MM |
1006 | : (C) == 'U' ? ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \ |
1007 | && small_data_operand (OP, GET_MODE (OP))) \ | |
e8a8bc24 | 1008 | : 0) |
f045b2c9 RS |
1009 | |
1010 | /* Given an rtx X being reloaded into a reg required to be | |
1011 | in class CLASS, return the class of reg to actually use. | |
1012 | In general this is just CLASS; but on some machines | |
c81bebd7 | 1013 | in some cases it is preferable to use a more restrictive class. |
f045b2c9 RS |
1014 | |
1015 | On the RS/6000, we have to return NO_REGS when we want to reload a | |
1e66d555 GK |
1016 | floating-point CONST_DOUBLE to force it to be copied to memory. |
1017 | ||
1018 | We also don't want to reload integer values into floating-point | |
1019 | registers if we can at all help it. In fact, this can | |
1020 | cause reload to abort, if it tries to generate a reload of CTR | |
1021 | into a FP register and discovers it doesn't have the memory location | |
1022 | required. | |
1023 | ||
1024 | ??? Would it be a good idea to have reload do the converse, that is | |
1025 | try to reload floating modes into FP registers if possible? | |
1026 | */ | |
f045b2c9 | 1027 | |
802a0058 | 1028 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
1e66d555 GK |
1029 | (((GET_CODE (X) == CONST_DOUBLE \ |
1030 | && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ | |
1031 | ? NO_REGS \ | |
1032 | : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ | |
1033 | && (CLASS) == NON_SPECIAL_REGS) \ | |
1034 | ? GENERAL_REGS \ | |
1035 | : (CLASS))) | |
c81bebd7 | 1036 | |
f045b2c9 RS |
1037 | /* Return the register class of a scratch register needed to copy IN into |
1038 | or out of a register in CLASS in MODE. If it can be done directly, | |
1039 | NO_REGS is returned. */ | |
1040 | ||
1041 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
1042 | secondary_reload_class (CLASS, MODE, IN) | |
1043 | ||
7ea555a4 RK |
1044 | /* If we are copying between FP registers and anything else, we need a memory |
1045 | location. */ | |
1046 | ||
1047 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ | |
1048 | ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS || (CLASS2) == FLOAT_REGS)) | |
1049 | ||
f045b2c9 RS |
1050 | /* Return the maximum number of consecutive registers |
1051 | needed to represent mode MODE in a register of class CLASS. | |
1052 | ||
1053 | On RS/6000, this is the size of MODE in words, | |
1054 | except in the FP regs, where a single reg is enough for two words. */ | |
802a0058 | 1055 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
9ebbca7d | 1056 | (((CLASS) == FLOAT_REGS) \ |
2e360ab3 | 1057 | ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ |
f045b2c9 | 1058 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
580d3230 RK |
1059 | |
1060 | /* If defined, gives a class of registers that cannot be used as the | |
02188693 | 1061 | operand of a SUBREG that changes the mode of the object illegally. */ |
580d3230 | 1062 | |
02188693 RH |
1063 | #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS |
1064 | ||
1065 | /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ | |
1066 | ||
1067 | #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ | |
1068 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) | |
f045b2c9 RS |
1069 | \f |
1070 | /* Stack layout; function entry, exit and calling. */ | |
1071 | ||
6b67933e RK |
1072 | /* Enumeration to give which calling sequence to use. */ |
1073 | enum rs6000_abi { | |
1074 | ABI_NONE, | |
1075 | ABI_AIX, /* IBM's AIX */ | |
b6c9286a MM |
1076 | ABI_AIX_NODESC, /* AIX calling sequence minus function descriptors */ |
1077 | ABI_V4, /* System V.4/eabi */ | |
ee890fe2 SS |
1078 | ABI_SOLARIS, /* Solaris */ |
1079 | ABI_DARWIN /* Apple's Darwin (OS X kernel) */ | |
6b67933e RK |
1080 | }; |
1081 | ||
b6c9286a MM |
1082 | extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */ |
1083 | ||
4697a36c MM |
1084 | /* Structure used to define the rs6000 stack */ |
1085 | typedef struct rs6000_stack { | |
1086 | int first_gp_reg_save; /* first callee saved GP register used */ | |
1087 | int first_fp_reg_save; /* first callee saved FP register used */ | |
1088 | int lr_save_p; /* true if the link reg needs to be saved */ | |
1089 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
b6c9286a | 1090 | int toc_save_p; /* true if the TOC needs to be saved */ |
4697a36c MM |
1091 | int push_p; /* true if we need to allocate stack space */ |
1092 | int calls_p; /* true if the function makes any calls */ | |
6b67933e | 1093 | enum rs6000_abi abi; /* which ABI to use */ |
abc95ed3 RK |
1094 | int gp_save_offset; /* offset to save GP regs from initial SP */ |
1095 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
4697a36c MM |
1096 | int lr_save_offset; /* offset to save LR from initial SP */ |
1097 | int cr_save_offset; /* offset to save CR from initial SP */ | |
b6c9286a | 1098 | int toc_save_offset; /* offset to save the TOC pointer */ |
4697a36c | 1099 | int varargs_save_offset; /* offset to save the varargs registers */ |
83720594 | 1100 | int ehrd_offset; /* offset to EH return data */ |
4697a36c MM |
1101 | int reg_size; /* register size (4 or 8) */ |
1102 | int varargs_size; /* size to hold V.4 args passed in regs */ | |
1103 | int vars_size; /* variable save area size */ | |
1104 | int parm_size; /* outgoing parameter size */ | |
1105 | int save_size; /* save area size */ | |
1106 | int fixed_size; /* fixed size of stack frame */ | |
1107 | int gp_size; /* size of saved GP registers */ | |
1108 | int fp_size; /* size of saved FP registers */ | |
1109 | int cr_size; /* size to hold CR if not in save_size */ | |
b6c9286a MM |
1110 | int lr_size; /* size to hold LR if not in save_size */ |
1111 | int toc_size; /* size to hold TOC if not in save_size */ | |
4697a36c MM |
1112 | int total_size; /* total bytes allocated for stack */ |
1113 | } rs6000_stack_t; | |
1114 | ||
f045b2c9 RS |
1115 | /* Define this if pushing a word on the stack |
1116 | makes the stack pointer a smaller address. */ | |
1117 | #define STACK_GROWS_DOWNWARD | |
1118 | ||
1119 | /* Define this if the nominal address of the stack frame | |
1120 | is at the high-address end of the local variables; | |
1121 | that is, each additional local variable allocated | |
1122 | goes at a more negative offset in the frame. | |
1123 | ||
1124 | On the RS/6000, we grow upwards, from the area after the outgoing | |
1125 | arguments. */ | |
1126 | /* #define FRAME_GROWS_DOWNWARD */ | |
1127 | ||
4697a36c | 1128 | /* Size of the outgoing register save area */ |
9ebbca7d | 1129 | #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ |
ee890fe2 SS |
1130 | || DEFAULT_ABI == ABI_AIX_NODESC \ |
1131 | || DEFAULT_ABI == ABI_DARWIN) \ | |
9ebbca7d GK |
1132 | ? (TARGET_64BIT ? 64 : 32) \ |
1133 | : 0) | |
4697a36c MM |
1134 | |
1135 | /* Size of the fixed area on the stack */ | |
9ebbca7d | 1136 | #define RS6000_SAVE_AREA \ |
ee890fe2 | 1137 | (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ |
9ebbca7d | 1138 | << (TARGET_64BIT ? 1 : 0)) |
4697a36c | 1139 | |
97f6e72f DE |
1140 | /* MEM representing address to save the TOC register */ |
1141 | #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ | |
1142 | plus_constant (stack_pointer_rtx, \ | |
1143 | (TARGET_32BIT ? 20 : 40))) | |
b6c9286a | 1144 | |
4697a36c MM |
1145 | /* Size of the V.4 varargs area if needed */ |
1146 | #define RS6000_VARARGS_AREA 0 | |
1147 | ||
4697a36c | 1148 | /* Align an address */ |
ed33106f | 1149 | #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) |
4697a36c MM |
1150 | |
1151 | /* Size of V.4 varargs area in bytes */ | |
1152 | #define RS6000_VARARGS_SIZE \ | |
2f3e5814 | 1153 | ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8) |
4697a36c | 1154 | |
f045b2c9 RS |
1155 | /* Offset within stack frame to start allocating local variables at. |
1156 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1157 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
c81bebd7 | 1158 | of the first local allocated. |
f045b2c9 RS |
1159 | |
1160 | On the RS/6000, the frame pointer is the same as the stack pointer, | |
1161 | except for dynamic allocations. So we start after the fixed area and | |
1162 | outgoing parameter area. */ | |
1163 | ||
802a0058 | 1164 | #define STARTING_FRAME_OFFSET \ |
ed33106f | 1165 | (RS6000_ALIGN (current_function_outgoing_args_size, 8) \ |
802a0058 MM |
1166 | + RS6000_VARARGS_AREA \ |
1167 | + RS6000_SAVE_AREA) | |
1168 | ||
1169 | /* Offset from the stack pointer register to an item dynamically | |
1170 | allocated on the stack, e.g., by `alloca'. | |
1171 | ||
1172 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1173 | length of the outgoing arguments. The default is correct for most | |
1174 | machines. See `function.c' for details. */ | |
1175 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ | |
ed33106f | 1176 | (RS6000_ALIGN (current_function_outgoing_args_size, 8) \ |
802a0058 | 1177 | + (STACK_POINTER_OFFSET)) |
f045b2c9 RS |
1178 | |
1179 | /* If we generate an insn to push BYTES bytes, | |
1180 | this says how many the stack pointer really advances by. | |
1181 | On RS/6000, don't define this because there are no push insns. */ | |
1182 | /* #define PUSH_ROUNDING(BYTES) */ | |
1183 | ||
1184 | /* Offset of first parameter from the argument pointer register value. | |
1185 | On the RS/6000, we define the argument pointer to the start of the fixed | |
1186 | area. */ | |
4697a36c | 1187 | #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA |
f045b2c9 | 1188 | |
62153b61 JM |
1189 | /* Offset from the argument pointer register value to the top of |
1190 | stack. This is different from FIRST_PARM_OFFSET because of the | |
1191 | register save area. */ | |
1192 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1193 | ||
f045b2c9 RS |
1194 | /* Define this if stack space is still allocated for a parameter passed |
1195 | in a register. The value is the number of bytes allocated to this | |
1196 | area. */ | |
4697a36c | 1197 | #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE |
f045b2c9 RS |
1198 | |
1199 | /* Define this if the above stack space is to be considered part of the | |
1200 | space allocated by the caller. */ | |
1201 | #define OUTGOING_REG_PARM_STACK_SPACE | |
1202 | ||
1203 | /* This is the difference between the logical top of stack and the actual sp. | |
1204 | ||
1205 | For the RS/6000, sp points past the fixed area. */ | |
4697a36c | 1206 | #define STACK_POINTER_OFFSET RS6000_SAVE_AREA |
f045b2c9 RS |
1207 | |
1208 | /* Define this if the maximum size of all the outgoing args is to be | |
1209 | accumulated and pushed during the prologue. The amount can be | |
1210 | found in the variable current_function_outgoing_args_size. */ | |
f73ad30e | 1211 | #define ACCUMULATE_OUTGOING_ARGS 1 |
f045b2c9 RS |
1212 | |
1213 | /* Value is the number of bytes of arguments automatically | |
1214 | popped when returning from a subroutine call. | |
8b109b37 | 1215 | FUNDECL is the declaration node of the function (as a tree), |
f045b2c9 RS |
1216 | FUNTYPE is the data type of the function (as a tree), |
1217 | or for a library call it is an identifier node for the subroutine name. | |
1218 | SIZE is the number of bytes of arguments passed on the stack. */ | |
1219 | ||
8b109b37 | 1220 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
f045b2c9 RS |
1221 | |
1222 | /* Define how to find the value returned by a function. | |
1223 | VALTYPE is the data type of the value (as a tree). | |
1224 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1225 | otherwise, FUNC is 0. | |
1226 | ||
c81bebd7 | 1227 | On RS/6000 an integer value is in r3 and a floating-point value is in |
d14a6d05 | 1228 | fp1, unless -msoft-float. */ |
f045b2c9 | 1229 | |
39403d82 DE |
1230 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
1231 | gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \ | |
1232 | && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ | |
1233 | || POINTER_TYPE_P (VALTYPE) \ | |
1234 | ? word_mode : TYPE_MODE (VALTYPE), \ | |
1235 | TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT ? 33 : 3) | |
f045b2c9 RS |
1236 | |
1237 | /* Define how to find the value returned by a library function | |
1238 | assuming the value has mode MODE. */ | |
1239 | ||
1240 | #define LIBCALL_VALUE(MODE) \ | |
c5c76735 JL |
1241 | gen_rtx_REG (MODE, (GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1242 | && TARGET_HARD_FLOAT ? 33 : 3)) | |
f045b2c9 RS |
1243 | |
1244 | /* The definition of this macro implies that there are cases where | |
1245 | a scalar value cannot be returned in registers. | |
1246 | ||
c81bebd7 MM |
1247 | For the RS/6000, any structure or union type is returned in memory, except for |
1248 | Solaris, which returns structures <= 8 bytes in registers. */ | |
f045b2c9 | 1249 | |
c81bebd7 MM |
1250 | #define RETURN_IN_MEMORY(TYPE) \ |
1251 | (TYPE_MODE (TYPE) == BLKmode \ | |
1252 | && (DEFAULT_ABI != ABI_SOLARIS || int_size_in_bytes (TYPE) > 8)) | |
f045b2c9 | 1253 | |
a260abc9 | 1254 | /* Mode of stack savearea. |
dfdfa60f DE |
1255 | FUNCTION is VOIDmode because calling convention maintains SP. |
1256 | BLOCK needs Pmode for SP. | |
a260abc9 DE |
1257 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ |
1258 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
dfdfa60f DE |
1259 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ |
1260 | : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) | |
a260abc9 | 1261 | |
4697a36c MM |
1262 | /* Minimum and maximum general purpose registers used to hold arguments. */ |
1263 | #define GP_ARG_MIN_REG 3 | |
1264 | #define GP_ARG_MAX_REG 10 | |
1265 | #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1266 | ||
1267 | /* Minimum and maximum floating point registers used to hold arguments. */ | |
1268 | #define FP_ARG_MIN_REG 33 | |
7509c759 MM |
1269 | #define FP_ARG_AIX_MAX_REG 45 |
1270 | #define FP_ARG_V4_MAX_REG 40 | |
9ebbca7d | 1271 | #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ |
ee890fe2 SS |
1272 | || DEFAULT_ABI == ABI_AIX_NODESC \ |
1273 | || DEFAULT_ABI == ABI_DARWIN) \ | |
9ebbca7d | 1274 | ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) |
4697a36c MM |
1275 | #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
1276 | ||
1277 | /* Return registers */ | |
1278 | #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1279 | #define FP_ARG_RETURN FP_ARG_MIN_REG | |
1280 | ||
7509c759 | 1281 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
6a4cee5f | 1282 | #define CALL_NORMAL 0x00000000 /* no special processing */ |
9ebbca7d | 1283 | /* Bits in 0x00000001 are unused. */ |
6a4cee5f MM |
1284 | #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ |
1285 | #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1286 | #define CALL_LONG 0x00000008 /* always call indirect */ | |
7509c759 | 1287 | |
f045b2c9 RS |
1288 | /* 1 if N is a possible register number for a function value |
1289 | as seen by the caller. | |
1290 | ||
1291 | On RS/6000, this is r3 and fp1. */ | |
4697a36c | 1292 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN || ((N) == FP_ARG_RETURN)) |
f045b2c9 RS |
1293 | |
1294 | /* 1 if N is a possible register number for function argument passing. | |
1295 | On RS/6000, these are r3-r10 and fp1-fp13. */ | |
4697a36c | 1296 | #define FUNCTION_ARG_REGNO_P(N) \ |
2bfcf297 DB |
1297 | ((((N) - GP_ARG_MIN_REG) < (GP_ARG_NUM_REG)) \ |
1298 | || (((N) - FP_ARG_MIN_REG) < (FP_ARG_NUM_REG))) | |
f045b2c9 | 1299 | |
f045b2c9 | 1300 | \f |
00dba523 NC |
1301 | /* A C structure for machine-specific, per-function data. |
1302 | This is added to the cfun structure. */ | |
1303 | typedef struct machine_function | |
1304 | { | |
1305 | /* Whether a System V.4 varargs area was created. */ | |
1306 | int sysv_varargs_p; | |
71f123ca FS |
1307 | /* Flags if __builtin_return_address (n) with n >= 1 was used. */ |
1308 | int ra_needs_full_frame; | |
00dba523 NC |
1309 | } machine_function; |
1310 | ||
f045b2c9 RS |
1311 | /* Define a data type for recording info about an argument list |
1312 | during the scan of that argument list. This data type should | |
1313 | hold all necessary information about the function itself | |
1314 | and about the args processed so far, enough to enable macros | |
1315 | such as FUNCTION_ARG to determine where the next arg should go. | |
1316 | ||
1317 | On the RS/6000, this is a structure. The first element is the number of | |
1318 | total argument words, the second is used to store the next | |
1319 | floating-point register number, and the third says how many more args we | |
4697a36c MM |
1320 | have prototype types for. |
1321 | ||
4cc833b7 RH |
1322 | For ABI_V4, we treat these slightly differently -- `sysv_gregno' is |
1323 | the next availible GP register, `fregno' is the next available FP | |
1324 | register, and `words' is the number of words used on the stack. | |
1325 | ||
bd227acc | 1326 | The varargs/stdarg support requires that this structure's size |
4cc833b7 | 1327 | be a multiple of sizeof(int). */ |
4697a36c MM |
1328 | |
1329 | typedef struct rs6000_args | |
1330 | { | |
4cc833b7 | 1331 | int words; /* # words used for passing GP registers */ |
6a4cee5f MM |
1332 | int fregno; /* next available FP register */ |
1333 | int nargs_prototype; /* # args left in the current prototype */ | |
1334 | int orig_nargs; /* Original value of nargs_prototype */ | |
6a4cee5f MM |
1335 | int prototype; /* Whether a prototype was defined */ |
1336 | int call_cookie; /* Do special things for this call */ | |
4cc833b7 | 1337 | int sysv_gregno; /* next available GP register */ |
4697a36c | 1338 | } CUMULATIVE_ARGS; |
f045b2c9 RS |
1339 | |
1340 | /* Define intermediate macro to compute the size (in registers) of an argument | |
1341 | for the RS/6000. */ | |
1342 | ||
d34c5b80 DE |
1343 | #define RS6000_ARG_SIZE(MODE, TYPE) \ |
1344 | ((MODE) != BLKmode \ | |
c5d71f39 GK |
1345 | ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ |
1346 | : ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \ | |
1347 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
f045b2c9 RS |
1348 | |
1349 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1350 | for a call to a function whose data type is FNTYPE. | |
1351 | For a library call, FNTYPE is 0. */ | |
1352 | ||
2c7ee1a6 | 1353 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
4697a36c | 1354 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE) |
f045b2c9 RS |
1355 | |
1356 | /* Similar, but when scanning the definition of a procedure. We always | |
1357 | set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1358 | ||
4697a36c MM |
1359 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \ |
1360 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE) | |
f045b2c9 RS |
1361 | |
1362 | /* Update the data in CUM to advance over an argument | |
1363 | of mode MODE and data type TYPE. | |
1364 | (TYPE is null for libcalls where that information may not be available.) */ | |
1365 | ||
1366 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
4697a36c | 1367 | function_arg_advance (&CUM, MODE, TYPE, NAMED) |
f045b2c9 RS |
1368 | |
1369 | /* Non-zero if we can use a floating-point register to pass this arg. */ | |
4697a36c MM |
1370 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ |
1371 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1372 | && (CUM).fregno <= FP_ARG_MAX_REG \ | |
1373 | && TARGET_HARD_FLOAT) | |
f045b2c9 RS |
1374 | |
1375 | /* Determine where to put an argument to a function. | |
1376 | Value is zero to push the argument on the stack, | |
1377 | or a hard register in which to store the argument. | |
1378 | ||
1379 | MODE is the argument's machine mode. | |
1380 | TYPE is the data type of the argument (as a tree). | |
1381 | This is null for libcalls where that information may | |
1382 | not be available. | |
1383 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1384 | the preceding args and about the function being called. | |
1385 | NAMED is nonzero if this argument is a named parameter | |
1386 | (otherwise it is an extra parameter matching an ellipsis). | |
1387 | ||
1388 | On RS/6000 the first eight words of non-FP are normally in registers | |
1389 | and the rest are pushed. The first 13 FP args are in registers. | |
1390 | ||
1391 | If this is floating-point and no prototype is specified, we use | |
4d6697ca RK |
1392 | both an FP and integer register (or possibly FP reg and stack). Library |
1393 | functions (when TYPE is zero) always have the proper types for args, | |
1394 | so we can pass the FP value just in one register. emit_library_function | |
1395 | doesn't support EXPR_LIST anyway. */ | |
f045b2c9 | 1396 | |
4697a36c MM |
1397 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1398 | function_arg (&CUM, MODE, TYPE, NAMED) | |
f045b2c9 RS |
1399 | |
1400 | /* For an arg passed partly in registers and partly in memory, | |
1401 | this is the number of registers used. | |
1402 | For args passed entirely in registers or entirely in memory, zero. */ | |
1403 | ||
4697a36c MM |
1404 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
1405 | function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) | |
1406 | ||
1407 | /* A C expression that indicates when an argument must be passed by | |
1408 | reference. If nonzero for an argument, a copy of that argument is | |
1409 | made in memory and a pointer to the argument is passed instead of | |
1410 | the argument itself. The pointer is passed in whatever way is | |
1411 | appropriate for passing a pointer to that type. */ | |
1412 | ||
1413 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ | |
1414 | function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED) | |
f045b2c9 | 1415 | |
c229cba9 DE |
1416 | /* If defined, a C expression which determines whether, and in which |
1417 | direction, to pad out an argument with extra space. The value | |
1418 | should be of type `enum direction': either `upward' to pad above | |
1419 | the argument, `downward' to pad below, or `none' to inhibit | |
1420 | padding. */ | |
1421 | ||
9ebbca7d | 1422 | #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) |
c229cba9 | 1423 | |
b6c9286a | 1424 | /* If defined, a C expression that gives the alignment boundary, in bits, |
c81bebd7 | 1425 | of an argument with the specified mode and type. If it is not defined, |
b6c9286a MM |
1426 | PARM_BOUNDARY is used for all arguments. */ |
1427 | ||
1428 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
1429 | function_arg_boundary (MODE, TYPE) | |
1430 | ||
f045b2c9 | 1431 | /* Perform any needed actions needed for a function that is receiving a |
c81bebd7 | 1432 | variable number of arguments. |
f045b2c9 RS |
1433 | |
1434 | CUM is as above. | |
1435 | ||
1436 | MODE and TYPE are the mode and type of the current parameter. | |
1437 | ||
1438 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
1439 | that must be pushed by the prolog to pretend that our caller pushed | |
1440 | it. | |
1441 | ||
1442 | Normally, this macro will push all remaining incoming registers on the | |
1443 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
1444 | ||
4697a36c MM |
1445 | #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ |
1446 | setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL) | |
1447 | ||
dfafc897 FS |
1448 | /* Define the `__builtin_va_list' type for the ABI. */ |
1449 | #define BUILD_VA_LIST_TYPE(VALIST) \ | |
1450 | (VALIST) = rs6000_build_va_list () | |
4697a36c | 1451 | |
dfafc897 FS |
1452 | /* Implement `va_start' for varargs and stdarg. */ |
1453 | #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \ | |
1454 | rs6000_va_start (stdarg, valist, nextarg) | |
1455 | ||
1456 | /* Implement `va_arg'. */ | |
1457 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
1458 | rs6000_va_arg (valist, type) | |
f045b2c9 | 1459 | |
d34c5b80 DE |
1460 | /* Define this macro to be a nonzero value if the location where a function |
1461 | argument is passed depends on whether or not it is a named argument. */ | |
1462 | #define STRICT_ARGUMENT_NAMING 1 | |
1463 | ||
2bfcf297 DB |
1464 | /* This macro generates the assembly code for function entry. |
1465 | FILE is a stdio stream to output the code to. | |
1466 | SIZE is an int: how many units of temporary storage to allocate. | |
1467 | Refer to the array `regs_ever_live' to determine which registers | |
1468 | to save; `regs_ever_live[I]' is nonzero if register number I | |
1469 | is ever used in the function. This macro is responsible for | |
1470 | knowing which registers should not be saved even if used. */ | |
1471 | ||
1472 | #define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE) | |
1473 | ||
f045b2c9 | 1474 | /* Output assembler code to FILE to increment profiler label # LABELNO |
58a39e45 | 1475 | for profiling a function entry. */ |
f045b2c9 RS |
1476 | |
1477 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
58a39e45 | 1478 | output_function_profiler ((FILE), (LABELNO)); |
f045b2c9 RS |
1479 | |
1480 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1481 | the stack pointer does not matter. No definition is equivalent to | |
1482 | always zero. | |
1483 | ||
1484 | On the RS/6000, this is non-zero because we can restore the stack from | |
1485 | its backpointer, which we maintain. */ | |
1486 | #define EXIT_IGNORE_STACK 1 | |
1487 | ||
a701949a FS |
1488 | /* Define this macro as a C expression that is nonzero for registers |
1489 | that are used by the epilogue or the return' pattern. The stack | |
1490 | and frame pointer registers are already be assumed to be used as | |
1491 | needed. */ | |
1492 | ||
83720594 RH |
1493 | #define EPILOGUE_USES(REGNO) \ |
1494 | ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \ | |
1495 | || (current_function_calls_eh_return \ | |
3553b09d | 1496 | && TARGET_AIX \ |
83720594 | 1497 | && (REGNO) == TOC_REGISTER)) |
2bfcf297 DB |
1498 | |
1499 | /* This macro generates the assembly code for function exit, | |
1500 | on machines that need it. If FUNCTION_EPILOGUE is not defined | |
1501 | then individual return instructions are generated for each | |
1502 | return statement. Args are same as for FUNCTION_PROLOGUE. | |
1503 | ||
1504 | The function epilogue should not depend on the current stack pointer! | |
1505 | It should use the frame pointer only. This is mandatory because | |
1506 | of alloca; we also take advantage of it to omit stack adjustments | |
1507 | before returning. */ | |
1508 | ||
1509 | #define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE) | |
f045b2c9 | 1510 | \f |
eaf1bcf1 | 1511 | /* TRAMPOLINE_TEMPLATE deleted */ |
f045b2c9 RS |
1512 | |
1513 | /* Length in units of the trampoline for entering a nested function. */ | |
1514 | ||
b6c9286a | 1515 | #define TRAMPOLINE_SIZE rs6000_trampoline_size () |
f045b2c9 RS |
1516 | |
1517 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1518 | FNADDR is an RTX for the address of the function's pure code. | |
1519 | CXT is an RTX for the static chain value for the function. */ | |
1520 | ||
1521 | #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ | |
b6c9286a | 1522 | rs6000_initialize_trampoline (ADDR, FNADDR, CXT) |
f045b2c9 | 1523 | \f |
f33985c6 MS |
1524 | /* Definitions for __builtin_return_address and __builtin_frame_address. |
1525 | __builtin_return_address (0) should give link register (65), enable | |
1526 | this. */ | |
1527 | /* This should be uncommented, so that the link register is used, but | |
1528 | currently this would result in unmatched insns and spilling fixed | |
1529 | registers so we'll leave it for another day. When these problems are | |
1530 | taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1531 | (mrs) */ | |
1532 | /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
f09d4c33 | 1533 | |
b6c9286a MM |
1534 | /* Number of bytes into the frame return addresses can be found. See |
1535 | rs6000_stack_info in rs6000.c for more information on how the different | |
1536 | abi's store the return address. */ | |
1537 | #define RETURN_ADDRESS_OFFSET \ | |
1538 | ((DEFAULT_ABI == ABI_AIX \ | |
ee890fe2 | 1539 | || DEFAULT_ABI == ABI_DARWIN \ |
05ef2698 | 1540 | || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \ |
c81bebd7 MM |
1541 | (DEFAULT_ABI == ABI_V4 \ |
1542 | || DEFAULT_ABI == ABI_SOLARIS) ? (TARGET_32BIT ? 4 : 8) : \ | |
c4636dd1 | 1543 | (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) |
f09d4c33 | 1544 | |
f33985c6 MS |
1545 | /* The current return address is in link register (65). The return address |
1546 | of anything farther back is accessed normally at an offset of 8 from the | |
1547 | frame pointer. */ | |
71f123ca FS |
1548 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1549 | (rs6000_return_addr (COUNT, FRAME)) | |
1550 | ||
f33985c6 | 1551 | \f |
f045b2c9 RS |
1552 | /* Definitions for register eliminations. |
1553 | ||
1554 | We have two registers that can be eliminated on the RS/6000. First, the | |
1555 | frame pointer register can often be eliminated in favor of the stack | |
1556 | pointer register. Secondly, the argument pointer register can always be | |
642a35f1 JW |
1557 | eliminated; it is replaced with either the stack or frame pointer. |
1558 | ||
1559 | In addition, we use the elimination mechanism to see if r30 is needed | |
1560 | Initially we assume that it isn't. If it is, we spill it. This is done | |
1561 | by making it an eliminable register. We replace it with itself so that | |
1562 | if it isn't needed, then existing uses won't be modified. */ | |
f045b2c9 RS |
1563 | |
1564 | /* This is an array of structures. Each structure initializes one pair | |
1565 | of eliminable registers. The "from" register number is given first, | |
1566 | followed by "to". Eliminations of the same "from" register are listed | |
1567 | in order of preference. */ | |
1568 | #define ELIMINABLE_REGS \ | |
1569 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1570 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
642a35f1 JW |
1571 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ |
1572 | { 30, 30} } | |
f045b2c9 RS |
1573 | |
1574 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
1575 | Frame pointer elimination is automatically handled. | |
1576 | ||
1577 | For the RS/6000, if frame pointer elimination is being done, we would like | |
642a35f1 JW |
1578 | to convert ap into fp, not sp. |
1579 | ||
abc95ed3 | 1580 | We need r30 if -mminimal-toc was specified, and there are constant pool |
642a35f1 | 1581 | references. */ |
f045b2c9 RS |
1582 | |
1583 | #define CAN_ELIMINATE(FROM, TO) \ | |
1584 | ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ | |
1585 | ? ! frame_pointer_needed \ | |
4697a36c | 1586 | : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \ |
f045b2c9 RS |
1587 | : 1) |
1588 | ||
1589 | /* Define the offset between two registers, one to be eliminated, and the other | |
1590 | its replacement, at the start of a routine. */ | |
1591 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1592 | { \ | |
4697a36c | 1593 | rs6000_stack_t *info = rs6000_stack_info (); \ |
f045b2c9 RS |
1594 | \ |
1595 | if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
4697a36c MM |
1596 | (OFFSET) = (info->push_p) ? 0 : - info->total_size; \ |
1597 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ | |
1598 | (OFFSET) = info->total_size; \ | |
1599 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
1600 | (OFFSET) = (info->push_p) ? info->total_size : 0; \ | |
642a35f1 JW |
1601 | else if ((FROM) == 30) \ |
1602 | (OFFSET) = 0; \ | |
f045b2c9 RS |
1603 | else \ |
1604 | abort (); \ | |
1605 | } | |
1606 | \f | |
1607 | /* Addressing modes, and classification of registers for them. */ | |
1608 | ||
940da324 JL |
1609 | /* #define HAVE_POST_INCREMENT 0 */ |
1610 | /* #define HAVE_POST_DECREMENT 0 */ | |
f045b2c9 | 1611 | |
940da324 JL |
1612 | #define HAVE_PRE_DECREMENT 1 |
1613 | #define HAVE_PRE_INCREMENT 1 | |
f045b2c9 RS |
1614 | |
1615 | /* Macros to check register numbers against specific register classes. */ | |
1616 | ||
1617 | /* These assume that REGNO is a hard or pseudo reg number. | |
1618 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1619 | or a pseudo reg currently allocated to a suitable hard reg. | |
1620 | Since they use reg_renumber, they are safe only once reg_renumber | |
1621 | has been allocated, which happens in local-alloc.c. */ | |
1622 | ||
1623 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1624 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1625 | ? (REGNO) <= 31 || (REGNO) == 67 \ | |
1626 | : (reg_renumber[REGNO] >= 0 \ | |
1627 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67))) | |
1628 | ||
1629 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1630 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1631 | ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
1632 | : (reg_renumber[REGNO] > 0 \ | |
1633 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67))) | |
1634 | \f | |
1635 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1636 | ||
1637 | #define MAX_REGS_PER_ADDRESS 2 | |
1638 | ||
1639 | /* Recognize any constant value that is a valid address. */ | |
1640 | ||
6eff269e BK |
1641 | #define CONSTANT_ADDRESS_P(X) \ |
1642 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1643 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1644 | || GET_CODE (X) == HIGH) | |
f045b2c9 RS |
1645 | |
1646 | /* Nonzero if the constant value X is a legitimate general operand. | |
1647 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1648 | ||
1649 | On the RS/6000, all integer constants are acceptable, most won't be valid | |
1650 | for particular insns, though. Only easy FP constants are | |
1651 | acceptable. */ | |
1652 | ||
1653 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1654 | (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \ | |
a260abc9 | 1655 | || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \ |
f045b2c9 RS |
1656 | || easy_fp_constant (X, GET_MODE (X))) |
1657 | ||
1658 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1659 | and check its validity for a certain class. | |
1660 | We have two alternate definitions for each of them. | |
1661 | The usual definition accepts all pseudo regs; the other rejects | |
1662 | them unless they have been allocated suitable hard regs. | |
1663 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1664 | ||
1665 | Most source files want to accept pseudo regs in the hope that | |
1666 | they will get allocated to the class that the insn wants them to be in. | |
1667 | Source files for reload pass need to be strict. | |
1668 | After reload, it makes no difference, since pseudo regs have | |
1669 | been eliminated by then. */ | |
1670 | ||
258bfae2 FS |
1671 | #ifdef REG_OK_STRICT |
1672 | # define REG_OK_STRICT_FLAG 1 | |
1673 | #else | |
1674 | # define REG_OK_STRICT_FLAG 0 | |
1675 | #endif | |
f045b2c9 RS |
1676 | |
1677 | /* Nonzero if X is a hard reg that can be used as an index | |
258bfae2 FS |
1678 | or if it is a pseudo reg in the non-strict case. */ |
1679 | #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ | |
1680 | ((! (STRICT) \ | |
1681 | && (REGNO (X) <= 31 \ | |
1682 | || REGNO (X) == ARG_POINTER_REGNUM \ | |
1683 | || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \ | |
1684 | || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X)))) | |
f045b2c9 RS |
1685 | |
1686 | /* Nonzero if X is a hard reg that can be used as a base reg | |
258bfae2 FS |
1687 | or if it is a pseudo reg in the non-strict case. */ |
1688 | #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ | |
1689 | (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT))) | |
f045b2c9 | 1690 | |
258bfae2 FS |
1691 | #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG) |
1692 | #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG) | |
f045b2c9 RS |
1693 | \f |
1694 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1695 | that is a valid memory address for an instruction. | |
1696 | The MODE argument is the machine mode for the MEM expression | |
1697 | that wants to use this address. | |
1698 | ||
1699 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1700 | refers to a constant pool entry of an address (or the sum of it | |
1701 | plus a constant), a short (16-bit signed) constant plus a register, | |
1702 | the sum of two registers, or a register indirect, possibly with an | |
1703 | auto-increment. For DFmode and DImode with an constant plus register, | |
2f3e5814 | 1704 | we must ensure that both words are addressable or PowerPC64 with offset |
1427100a DE |
1705 | word aligned. |
1706 | ||
1707 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1708 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1709 | adjacent memory cells are accessed by adding word-sized offsets | |
1710 | during assembly output. */ | |
f045b2c9 | 1711 | |
9ebbca7d GK |
1712 | #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X)) |
1713 | ||
1714 | #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X)) | |
f045b2c9 RS |
1715 | |
1716 | #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \ | |
9ebbca7d GK |
1717 | (TARGET_TOC \ |
1718 | && GET_CODE (X) == PLUS \ | |
1719 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1720 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \ | |
1721 | && CONSTANT_POOL_EXPR_P (XEXP (X, 1))) | |
f045b2c9 | 1722 | |
7509c759 | 1723 | #define LEGITIMATE_SMALL_DATA_P(MODE, X) \ |
c81bebd7 | 1724 | ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \ |
81795281 | 1725 | && !flag_pic && !TARGET_TOC \ |
88228c4b MM |
1726 | && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \ |
1727 | && small_data_operand (X, MODE)) | |
7509c759 | 1728 | |
258bfae2 | 1729 | #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \ |
f045b2c9 | 1730 | (GET_CODE (X) == CONST_INT \ |
5b6f7b96 | 1731 | && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000) |
f045b2c9 | 1732 | |
258bfae2 FS |
1733 | #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \ |
1734 | (GET_CODE (X) == PLUS \ | |
1735 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1736 | && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ | |
1737 | && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \ | |
1738 | && (((MODE) != DFmode && (MODE) != DImode) \ | |
1739 | || (TARGET_32BIT \ | |
1740 | ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \ | |
1741 | : ! (INTVAL (XEXP (X, 1)) & 3))) \ | |
1742 | && ((MODE) != TImode \ | |
1743 | || (TARGET_32BIT \ | |
1744 | ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \ | |
1745 | : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \ | |
1465faec | 1746 | && ! (INTVAL (XEXP (X, 1)) & 3))))) |
f045b2c9 | 1747 | |
258bfae2 FS |
1748 | #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \ |
1749 | (GET_CODE (X) == PLUS \ | |
1750 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1751 | && GET_CODE (XEXP (X, 1)) == REG \ | |
1752 | && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ | |
1753 | && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \ | |
1754 | || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \ | |
1755 | && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT))))) | |
1756 | ||
1757 | #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \ | |
1758 | (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT))) | |
1759 | ||
1760 | #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \ | |
1761 | (TARGET_ELF \ | |
1762 | && ! flag_pic && ! TARGET_TOC \ | |
1763 | && (MODE) != DImode \ | |
1764 | && (MODE) != TImode \ | |
1765 | && (TARGET_HARD_FLOAT || (MODE) != DFmode) \ | |
1766 | && GET_CODE (X) == LO_SUM \ | |
1767 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1768 | && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ | |
4697a36c MM |
1769 | && CONSTANT_P (XEXP (X, 1))) |
1770 | ||
258bfae2 FS |
1771 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
1772 | { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \ | |
1773 | goto ADDR; \ | |
f045b2c9 RS |
1774 | } |
1775 | \f | |
1776 | /* Try machine-dependent ways of modifying an illegitimate address | |
1777 | to be legitimate. If we find one, return the new, valid address. | |
1778 | This macro is used in only one place: `memory_address' in explow.c. | |
1779 | ||
1780 | OLDX is the address as it was before break_out_memory_refs was called. | |
1781 | In some cases it is useful to look at this to decide what needs to be done. | |
1782 | ||
1783 | MODE and WIN are passed so that this macro can use | |
1784 | GO_IF_LEGITIMATE_ADDRESS. | |
1785 | ||
1786 | It is always safe for this macro to do nothing. It exists to recognize | |
1787 | opportunities to optimize the output. | |
1788 | ||
1789 | On RS/6000, first check for the sum of a register with a constant | |
1790 | integer that is out of range. If so, generate code to add the | |
1791 | constant with the low-order 16 bits masked to the register and force | |
1792 | this result into another register (this can be done with `cau'). | |
c81bebd7 | 1793 | Then generate an address of REG+(CONST&0xffff), allowing for the |
f045b2c9 RS |
1794 | possibility of bit 16 being a one. |
1795 | ||
1796 | Then check for the sum of a register and something not constant, try to | |
1797 | load the other things into a register and return the sum. */ | |
1798 | ||
9ebbca7d GK |
1799 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ |
1800 | { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \ | |
1801 | if (result != NULL_RTX) \ | |
1802 | { \ | |
1803 | (X) = result; \ | |
1804 | goto WIN; \ | |
1805 | } \ | |
f045b2c9 RS |
1806 | } |
1807 | ||
a260abc9 DE |
1808 | /* Try a machine-dependent way of reloading an illegitimate address |
1809 | operand. If we find one, push the reload and jump to WIN. This | |
1810 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1811 | ||
1812 | For RS/6000, we wish to handle large displacements off a base | |
1813 | register by splitting the addend across an addiu/addis and the mem insn. | |
1814 | This cuts number of extra insns needed from 3 to 1. */ | |
1815 | ||
a9098fd0 GK |
1816 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
1817 | do { \ | |
1818 | /* We must recognize output that we have already generated ourselves. */ \ | |
1819 | if (GET_CODE (X) == PLUS \ | |
1820 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1821 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1822 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1823 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1824 | { \ | |
df4ae160 | 1825 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
a9098fd0 GK |
1826 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ |
1827 | OPNUM, TYPE); \ | |
1828 | goto WIN; \ | |
1829 | } \ | |
1830 | if (GET_CODE (X) == PLUS \ | |
1831 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1832 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1833 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1834 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1835 | { \ | |
1836 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1837 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \ | |
1838 | HOST_WIDE_INT high \ | |
0858c623 | 1839 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \ |
a9098fd0 GK |
1840 | \ |
1841 | /* Check for 32-bit overflow. */ \ | |
1842 | if (high + low != val) \ | |
1843 | break; \ | |
1844 | \ | |
1845 | /* Reload the high part into a base reg; leave the low part \ | |
1846 | in the mem directly. */ \ | |
1847 | \ | |
1848 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1849 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1850 | GEN_INT (high)), \ | |
1851 | GEN_INT (low)); \ | |
1852 | \ | |
df4ae160 | 1853 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
a9098fd0 GK |
1854 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ |
1855 | OPNUM, TYPE); \ | |
1856 | goto WIN; \ | |
1857 | } \ | |
1858 | else if (TARGET_TOC \ | |
1859 | && CONSTANT_POOL_EXPR_P (X) \ | |
1860 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (X), MODE)) \ | |
1861 | { \ | |
1862 | (X) = create_TOC_reference (X); \ | |
1863 | goto WIN; \ | |
1864 | } \ | |
a260abc9 DE |
1865 | } while (0) |
1866 | ||
f045b2c9 RS |
1867 | /* Go to LABEL if ADDR (a legitimate address expression) |
1868 | has an effect that depends on the machine mode it is used for. | |
1869 | ||
1870 | On the RS/6000 this is true if the address is valid with a zero offset | |
1871 | but not with an offset of four (this means it cannot be used as an | |
1872 | address for DImode or DFmode) or is a pre-increment or decrement. Since | |
1873 | we know it is valid, we just check for an address that is not valid with | |
1874 | an offset of four. */ | |
1875 | ||
1876 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1877 | { if (GET_CODE (ADDR) == PLUS \ | |
1878 | && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \ | |
2f3e5814 DE |
1879 | && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \ |
1880 | (TARGET_32BIT ? 4 : 8))) \ | |
f045b2c9 | 1881 | goto LABEL; \ |
38c1f2d7 | 1882 | if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \ |
f045b2c9 | 1883 | goto LABEL; \ |
38c1f2d7 | 1884 | if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \ |
f045b2c9 | 1885 | goto LABEL; \ |
4697a36c MM |
1886 | if (GET_CODE (ADDR) == LO_SUM) \ |
1887 | goto LABEL; \ | |
f045b2c9 | 1888 | } |
766a866c MM |
1889 | \f |
1890 | /* The register number of the register used to address a table of | |
1891 | static data addresses in memory. In some cases this register is | |
1892 | defined by a processor's "application binary interface" (ABI). | |
1893 | When this macro is defined, RTL is generated for this register | |
1894 | once, as with the stack pointer and frame pointer registers. If | |
1895 | this macro is not defined, it is up to the machine-dependent files | |
1896 | to allocate such a register (if necessary). */ | |
1897 | ||
8d30c4ee | 1898 | #define PIC_OFFSET_TABLE_REGNUM 30 |
766a866c | 1899 | |
9ebbca7d GK |
1900 | #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2) |
1901 | ||
766a866c MM |
1902 | /* Define this macro if the register defined by |
1903 | `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
1904 | this macro if `PPIC_OFFSET_TABLE_REGNUM' is not defined. */ | |
1905 | ||
1906 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
1907 | ||
1908 | /* By generating position-independent code, when two different | |
1909 | programs (A and B) share a common library (libC.a), the text of | |
1910 | the library can be shared whether or not the library is linked at | |
1911 | the same address for both programs. In some of these | |
1912 | environments, position-independent code requires not only the use | |
1913 | of different addressing modes, but also special code to enable the | |
1914 | use of these addressing modes. | |
1915 | ||
1916 | The `FINALIZE_PIC' macro serves as a hook to emit these special | |
1917 | codes once the function is being compiled into assembly code, but | |
1918 | not before. (It is not done before, because in the case of | |
1919 | compiling an inline function, it would lead to multiple PIC | |
1920 | prologues being included in functions which used inline functions | |
1921 | and were compiled to assembly language.) */ | |
1922 | ||
8d30c4ee | 1923 | /* #define FINALIZE_PIC */ |
766a866c | 1924 | |
766a866c MM |
1925 | /* A C expression that is nonzero if X is a legitimate immediate |
1926 | operand on the target machine when generating position independent | |
1927 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
1928 | not check this. You can also assume FLAG_PIC is true, so you need | |
1929 | not check it either. You need not define this macro if all | |
1930 | constants (including `SYMBOL_REF') can be immediate operands when | |
1931 | generating position independent code. */ | |
1932 | ||
1933 | /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
1934 | ||
30ea98f1 MM |
1935 | /* In rare cases, correct code generation requires extra machine |
1936 | dependent processing between the second jump optimization pass and | |
1937 | delayed branch scheduling. On those machines, define this macro | |
9ebbca7d | 1938 | as a C statement to act on the code starting at INSN. */ |
30ea98f1 | 1939 | |
9ebbca7d | 1940 | /* #define MACHINE_DEPENDENT_REORG(INSN) */ |
30ea98f1 | 1941 | |
f045b2c9 RS |
1942 | \f |
1943 | /* Define this if some processing needs to be done immediately before | |
4255474b | 1944 | emitting code for an insn. */ |
f045b2c9 | 1945 | |
4255474b | 1946 | /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */ |
f045b2c9 RS |
1947 | |
1948 | /* Specify the machine mode that this machine uses | |
1949 | for the index in the tablejump instruction. */ | |
e1565e65 | 1950 | #define CASE_VECTOR_MODE SImode |
f045b2c9 | 1951 | |
18543a22 ILT |
1952 | /* Define as C expression which evaluates to nonzero if the tablejump |
1953 | instruction expects the table to contain offsets from the address of the | |
1954 | table. | |
1955 | Do not define this if the table should contain absolute addresses. */ | |
1956 | #define CASE_VECTOR_PC_RELATIVE 1 | |
f045b2c9 RS |
1957 | |
1958 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1959 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1960 | ||
1961 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1962 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1963 | ||
1964 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1965 | #define DEFAULT_SIGNED_CHAR 0 | |
1966 | ||
1967 | /* This flag, if defined, says the same insns that convert to a signed fixnum | |
1968 | also convert validly to an unsigned one. */ | |
1969 | ||
1970 | /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ | |
1971 | ||
1972 | /* Max number of bytes we can move from memory to memory | |
1973 | in one reasonably fast instruction. */ | |
2f3e5814 | 1974 | #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) |
7e69e155 | 1975 | #define MAX_MOVE_MAX 8 |
f045b2c9 RS |
1976 | |
1977 | /* Nonzero if access to memory by bytes is no faster than for words. | |
1978 | Also non-zero if doing byte operations (specifically shifts) in registers | |
1979 | is undesirable. */ | |
1980 | #define SLOW_BYTE_ACCESS 1 | |
1981 | ||
9a63901f RK |
1982 | /* Define if operations between registers always perform the operation |
1983 | on the full register even if a narrower mode is specified. */ | |
1984 | #define WORD_REGISTER_OPERATIONS | |
1985 | ||
1986 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1987 | will either zero-extend or sign-extend. The value of this macro should | |
1988 | be the code that says which one of the two operations is implicitly | |
1989 | done, NIL if none. */ | |
1990 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
225211e2 RK |
1991 | |
1992 | /* Define if loading short immediate values into registers sign extends. */ | |
1993 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
fdaff8ba | 1994 | \f |
f045b2c9 RS |
1995 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1996 | is done just by pretending it is already truncated. */ | |
1997 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1998 | ||
1999 | /* Specify the machine mode that pointers have. | |
2000 | After generation of rtl, the compiler makes no further distinction | |
2001 | between pointers and any other objects of this machine mode. */ | |
2f3e5814 | 2002 | #define Pmode (TARGET_32BIT ? SImode : DImode) |
f045b2c9 RS |
2003 | |
2004 | /* Mode of a function address in a call instruction (for indexing purposes). | |
f045b2c9 | 2005 | Doesn't matter on RS/6000. */ |
2f3e5814 | 2006 | #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode) |
f045b2c9 RS |
2007 | |
2008 | /* Define this if addresses of constant functions | |
2009 | shouldn't be put through pseudo regs where they can be cse'd. | |
2010 | Desirable on machines where ordinary constants are expensive | |
2011 | but a CALL with constant address is cheap. */ | |
2012 | #define NO_FUNCTION_CSE | |
2013 | ||
d969caf8 | 2014 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
6febd581 RK |
2015 | few bits. |
2016 | ||
2017 | The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
2018 | have been dropped from the PowerPC architecture. */ | |
2019 | ||
4697a36c | 2020 | #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0) |
f045b2c9 | 2021 | |
f045b2c9 RS |
2022 | /* Compute the cost of computing a constant rtl expression RTX |
2023 | whose rtx-code is CODE. The body of this macro is a portion | |
2024 | of a switch statement. If the code is computed here, | |
2025 | return it with a return statement. Otherwise, break from the switch. | |
2026 | ||
01554f00 | 2027 | On the RS/6000, if it is valid in the insn, it is free. So this |
f045b2c9 RS |
2028 | always returns 0. */ |
2029 | ||
4697a36c | 2030 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
f045b2c9 RS |
2031 | case CONST_INT: \ |
2032 | case CONST: \ | |
2033 | case LABEL_REF: \ | |
2034 | case SYMBOL_REF: \ | |
2035 | case CONST_DOUBLE: \ | |
4697a36c | 2036 | case HIGH: \ |
f045b2c9 RS |
2037 | return 0; |
2038 | ||
2039 | /* Provide the costs of a rtl expression. This is in the body of a | |
2040 | switch on CODE. */ | |
2041 | ||
38c1f2d7 MM |
2042 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
2043 | case PLUS: \ | |
2044 | return ((GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
a260abc9 DE |
2045 | && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \ |
2046 | + 0x8000) >= 0x10000) \ | |
296b8152 | 2047 | && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \ |
38c1f2d7 MM |
2048 | ? COSTS_N_INSNS (2) \ |
2049 | : COSTS_N_INSNS (1)); \ | |
2050 | case AND: \ | |
38c1f2d7 MM |
2051 | case IOR: \ |
2052 | case XOR: \ | |
a260abc9 DE |
2053 | return ((GET_CODE (XEXP (X, 1)) == CONST_INT \ |
2054 | && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \ | |
296b8152 | 2055 | && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \ |
38c1f2d7 MM |
2056 | ? COSTS_N_INSNS (2) \ |
2057 | : COSTS_N_INSNS (1)); \ | |
2058 | case MULT: \ | |
2059 | switch (rs6000_cpu) \ | |
2060 | { \ | |
2061 | case PROCESSOR_RIOS1: \ | |
2062 | return (GET_CODE (XEXP (X, 1)) != CONST_INT \ | |
2063 | ? COSTS_N_INSNS (5) \ | |
2064 | : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ | |
2065 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \ | |
3cb999d8 DE |
2066 | case PROCESSOR_RS64A: \ |
2067 | return (GET_CODE (XEXP (X, 1)) != CONST_INT \ | |
2068 | ? GET_MODE (XEXP (X, 1)) != DImode \ | |
2069 | ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \ | |
2070 | : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ | |
2071 | ? COSTS_N_INSNS (12) : COSTS_N_INSNS (14)); \ | |
38c1f2d7 MM |
2072 | case PROCESSOR_RIOS2: \ |
2073 | case PROCESSOR_MPCCORE: \ | |
5a41b476 | 2074 | case PROCESSOR_PPC604e: \ |
38c1f2d7 MM |
2075 | return COSTS_N_INSNS (2); \ |
2076 | case PROCESSOR_PPC601: \ | |
2077 | return COSTS_N_INSNS (5); \ | |
2078 | case PROCESSOR_PPC603: \ | |
bef84347 | 2079 | case PROCESSOR_PPC750: \ |
38c1f2d7 MM |
2080 | return (GET_CODE (XEXP (X, 1)) != CONST_INT \ |
2081 | ? COSTS_N_INSNS (5) \ | |
2082 | : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ | |
2083 | ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \ | |
2084 | case PROCESSOR_PPC403: \ | |
2085 | case PROCESSOR_PPC604: \ | |
38c1f2d7 | 2086 | return COSTS_N_INSNS (4); \ |
3cb999d8 DE |
2087 | case PROCESSOR_PPC620: \ |
2088 | case PROCESSOR_PPC630: \ | |
2089 | return (GET_CODE (XEXP (X, 1)) != CONST_INT \ | |
2090 | ? GET_MODE (XEXP (X, 1)) != DImode \ | |
2091 | ? COSTS_N_INSNS (4) : COSTS_N_INSNS (7) \ | |
2092 | : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ | |
2093 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \ | |
38c1f2d7 MM |
2094 | } \ |
2095 | case DIV: \ | |
2096 | case MOD: \ | |
2097 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2098 | && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \ | |
2099 | return COSTS_N_INSNS (2); \ | |
2100 | /* otherwise fall through to normal divide. */ \ | |
2101 | case UDIV: \ | |
2102 | case UMOD: \ | |
2103 | switch (rs6000_cpu) \ | |
2104 | { \ | |
2105 | case PROCESSOR_RIOS1: \ | |
2106 | return COSTS_N_INSNS (19); \ | |
2107 | case PROCESSOR_RIOS2: \ | |
2108 | return COSTS_N_INSNS (13); \ | |
3cb999d8 DE |
2109 | case PROCESSOR_RS64A: \ |
2110 | return (GET_MODE (XEXP (X, 1)) != DImode \ | |
2111 | ? COSTS_N_INSNS (65) \ | |
2112 | : COSTS_N_INSNS (67)); \ | |
38c1f2d7 MM |
2113 | case PROCESSOR_MPCCORE: \ |
2114 | return COSTS_N_INSNS (6); \ | |
2115 | case PROCESSOR_PPC403: \ | |
2116 | return COSTS_N_INSNS (33); \ | |
2117 | case PROCESSOR_PPC601: \ | |
2118 | return COSTS_N_INSNS (36); \ | |
2119 | case PROCESSOR_PPC603: \ | |
2120 | return COSTS_N_INSNS (37); \ | |
2121 | case PROCESSOR_PPC604: \ | |
5a41b476 | 2122 | case PROCESSOR_PPC604e: \ |
38c1f2d7 | 2123 | return COSTS_N_INSNS (20); \ |
3cb999d8 DE |
2124 | case PROCESSOR_PPC620: \ |
2125 | case PROCESSOR_PPC630: \ | |
2126 | return (GET_MODE (XEXP (X, 1)) != DImode \ | |
2127 | ? COSTS_N_INSNS (21) \ | |
2128 | : COSTS_N_INSNS (37)); \ | |
bef84347 VM |
2129 | case PROCESSOR_PPC750: \ |
2130 | return COSTS_N_INSNS (19); \ | |
38c1f2d7 MM |
2131 | } \ |
2132 | case FFS: \ | |
2133 | return COSTS_N_INSNS (4); \ | |
2134 | case MEM: \ | |
f045b2c9 RS |
2135 | /* MEM should be slightly more expensive than (plus (reg) (const)) */ \ |
2136 | return 5; | |
2137 | ||
2138 | /* Compute the cost of an address. This is meant to approximate the size | |
2139 | and/or execution delay of an insn using that address. If the cost is | |
2140 | approximated by the RTL complexity, including CONST_COSTS above, as | |
2141 | is usually the case for CISC machines, this macro should not be defined. | |
2142 | For aggressively RISCy machines, only one insn format is allowed, so | |
2143 | this macro should be a constant. The value of this macro only matters | |
2144 | for valid addresses. | |
2145 | ||
2146 | For the RS/6000, everything is cost 0. */ | |
2147 | ||
2148 | #define ADDRESS_COST(RTX) 0 | |
2149 | ||
2150 | /* Adjust the length of an INSN. LENGTH is the currently-computed length and | |
2151 | should be adjusted to reflect any required changes. This macro is used when | |
2152 | there is some systematic length adjustment required that would be difficult | |
2153 | to express in the length attribute. */ | |
2154 | ||
2155 | /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
2156 | ||
2157 | /* Add any extra modes needed to represent the condition code. | |
2158 | ||
2159 | For the RS/6000, we need separate modes when unsigned (logical) comparisons | |
c5defebb RK |
2160 | are being done and we need a separate mode for floating-point. We also |
2161 | use a mode for the case when we are comparing the results of two | |
39a10a29 | 2162 | comparisons, as then only the EQ bit is valid in the register. */ |
f045b2c9 | 2163 | |
aa0b4465 ZW |
2164 | #define EXTRA_CC_MODES \ |
2165 | CC(CCUNSmode, "CCUNS") \ | |
2166 | CC(CCFPmode, "CCFP") \ | |
2167 | CC(CCEQmode, "CCEQ") | |
f045b2c9 | 2168 | |
39a10a29 GK |
2169 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a |
2170 | COMPARE, return the mode to be used for the comparison. For | |
2171 | floating-point, CCFPmode should be used. CCUNSmode should be used | |
2172 | for unsigned comparisons. CCEQmode should be used when we are | |
2173 | doing an inequality comparison on the result of a | |
2174 | comparison. CCmode should be used in all other cases. */ | |
c5defebb | 2175 | |
b565a316 | 2176 | #define SELECT_CC_MODE(OP,X,Y) \ |
f045b2c9 | 2177 | (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \ |
c5defebb RK |
2178 | : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ |
2179 | : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \ | |
2180 | ? CCEQmode : CCmode)) | |
f045b2c9 RS |
2181 | |
2182 | /* Define the information needed to generate branch and scc insns. This is | |
2183 | stored from the compare operation. Note that we can't use "rtx" here | |
2184 | since it hasn't been defined! */ | |
2185 | ||
2186 | extern struct rtx_def *rs6000_compare_op0, *rs6000_compare_op1; | |
2187 | extern int rs6000_compare_fp_p; | |
f045b2c9 RS |
2188 | \f |
2189 | /* Control the assembler format that we output. */ | |
2190 | ||
1b279f39 DE |
2191 | /* A C string constant describing how to begin a comment in the target |
2192 | assembler language. The compiler assumes that the comment will end at | |
2193 | the end of the line. */ | |
2194 | #define ASM_COMMENT_START " #" | |
6b67933e | 2195 | |
fdaff8ba RS |
2196 | /* Implicit library calls should use memcpy, not bcopy, etc. */ |
2197 | ||
2198 | #define TARGET_MEM_FUNCTIONS | |
2199 | ||
38c1f2d7 MM |
2200 | /* Flag to say the TOC is initialized */ |
2201 | extern int toc_initialized; | |
2202 | ||
f045b2c9 RS |
2203 | /* Macro to output a special constant pool entry. Go to WIN if we output |
2204 | it. Otherwise, it is written the usual way. | |
2205 | ||
2206 | On the RS/6000, toc entries are handled this way. */ | |
2207 | ||
a9098fd0 GK |
2208 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ |
2209 | { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
2210 | { \ | |
2211 | output_toc (FILE, X, LABELNO, MODE); \ | |
2212 | goto WIN; \ | |
2213 | } \ | |
f045b2c9 RS |
2214 | } |
2215 | ||
9ebbca7d | 2216 | /* This implementes the `alias' attribute. */ |
290ad355 | 2217 | |
9ebbca7d GK |
2218 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE,decl,target) \ |
2219 | do { \ | |
53cd5d6c | 2220 | const char * alias = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ |
9ebbca7d GK |
2221 | char * name = IDENTIFIER_POINTER (target); \ |
2222 | if (TREE_CODE (decl) == FUNCTION_DECL \ | |
2223 | && DEFAULT_ABI == ABI_AIX) \ | |
2224 | { \ | |
2225 | if (TREE_PUBLIC (decl)) \ | |
2226 | { \ | |
2227 | fputs ("\t.globl .", FILE); \ | |
2228 | assemble_name (FILE, alias); \ | |
2229 | putc ('\n', FILE); \ | |
2230 | } \ | |
2231 | else \ | |
2232 | { \ | |
2233 | fputs ("\t.lglobl .", FILE); \ | |
2234 | assemble_name (FILE, alias); \ | |
2235 | putc ('\n', FILE); \ | |
2236 | } \ | |
2237 | fputs ("\t.set .", FILE); \ | |
2238 | assemble_name (FILE, alias); \ | |
2239 | fputs (",.", FILE); \ | |
2240 | assemble_name (FILE, name); \ | |
2241 | fputc ('\n', FILE); \ | |
2242 | } \ | |
2243 | ASM_OUTPUT_DEF (FILE, alias, name); \ | |
290ad355 RH |
2244 | } while (0) |
2245 | ||
f045b2c9 RS |
2246 | /* Output to assembler file text saying following lines |
2247 | may contain character constants, extra white space, comments, etc. */ | |
2248 | ||
2249 | #define ASM_APP_ON "" | |
2250 | ||
2251 | /* Output to assembler file text saying following lines | |
2252 | no longer contain unusual constructs. */ | |
2253 | ||
2254 | #define ASM_APP_OFF "" | |
2255 | ||
f045b2c9 RS |
2256 | /* How to refer to registers in assembler output. |
2257 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2258 | ||
802a0058 | 2259 | extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ |
c81bebd7 MM |
2260 | |
2261 | #define REGISTER_NAMES \ | |
2262 | { \ | |
2263 | &rs6000_reg_names[ 0][0], /* r0 */ \ | |
2264 | &rs6000_reg_names[ 1][0], /* r1 */ \ | |
2265 | &rs6000_reg_names[ 2][0], /* r2 */ \ | |
2266 | &rs6000_reg_names[ 3][0], /* r3 */ \ | |
2267 | &rs6000_reg_names[ 4][0], /* r4 */ \ | |
2268 | &rs6000_reg_names[ 5][0], /* r5 */ \ | |
2269 | &rs6000_reg_names[ 6][0], /* r6 */ \ | |
2270 | &rs6000_reg_names[ 7][0], /* r7 */ \ | |
2271 | &rs6000_reg_names[ 8][0], /* r8 */ \ | |
2272 | &rs6000_reg_names[ 9][0], /* r9 */ \ | |
2273 | &rs6000_reg_names[10][0], /* r10 */ \ | |
2274 | &rs6000_reg_names[11][0], /* r11 */ \ | |
2275 | &rs6000_reg_names[12][0], /* r12 */ \ | |
2276 | &rs6000_reg_names[13][0], /* r13 */ \ | |
2277 | &rs6000_reg_names[14][0], /* r14 */ \ | |
2278 | &rs6000_reg_names[15][0], /* r15 */ \ | |
2279 | &rs6000_reg_names[16][0], /* r16 */ \ | |
2280 | &rs6000_reg_names[17][0], /* r17 */ \ | |
2281 | &rs6000_reg_names[18][0], /* r18 */ \ | |
2282 | &rs6000_reg_names[19][0], /* r19 */ \ | |
2283 | &rs6000_reg_names[20][0], /* r20 */ \ | |
2284 | &rs6000_reg_names[21][0], /* r21 */ \ | |
2285 | &rs6000_reg_names[22][0], /* r22 */ \ | |
2286 | &rs6000_reg_names[23][0], /* r23 */ \ | |
2287 | &rs6000_reg_names[24][0], /* r24 */ \ | |
2288 | &rs6000_reg_names[25][0], /* r25 */ \ | |
2289 | &rs6000_reg_names[26][0], /* r26 */ \ | |
2290 | &rs6000_reg_names[27][0], /* r27 */ \ | |
2291 | &rs6000_reg_names[28][0], /* r28 */ \ | |
2292 | &rs6000_reg_names[29][0], /* r29 */ \ | |
2293 | &rs6000_reg_names[30][0], /* r30 */ \ | |
2294 | &rs6000_reg_names[31][0], /* r31 */ \ | |
2295 | \ | |
2296 | &rs6000_reg_names[32][0], /* fr0 */ \ | |
2297 | &rs6000_reg_names[33][0], /* fr1 */ \ | |
2298 | &rs6000_reg_names[34][0], /* fr2 */ \ | |
2299 | &rs6000_reg_names[35][0], /* fr3 */ \ | |
2300 | &rs6000_reg_names[36][0], /* fr4 */ \ | |
2301 | &rs6000_reg_names[37][0], /* fr5 */ \ | |
2302 | &rs6000_reg_names[38][0], /* fr6 */ \ | |
2303 | &rs6000_reg_names[39][0], /* fr7 */ \ | |
2304 | &rs6000_reg_names[40][0], /* fr8 */ \ | |
2305 | &rs6000_reg_names[41][0], /* fr9 */ \ | |
2306 | &rs6000_reg_names[42][0], /* fr10 */ \ | |
2307 | &rs6000_reg_names[43][0], /* fr11 */ \ | |
2308 | &rs6000_reg_names[44][0], /* fr12 */ \ | |
2309 | &rs6000_reg_names[45][0], /* fr13 */ \ | |
2310 | &rs6000_reg_names[46][0], /* fr14 */ \ | |
2311 | &rs6000_reg_names[47][0], /* fr15 */ \ | |
2312 | &rs6000_reg_names[48][0], /* fr16 */ \ | |
2313 | &rs6000_reg_names[49][0], /* fr17 */ \ | |
2314 | &rs6000_reg_names[50][0], /* fr18 */ \ | |
2315 | &rs6000_reg_names[51][0], /* fr19 */ \ | |
2316 | &rs6000_reg_names[52][0], /* fr20 */ \ | |
2317 | &rs6000_reg_names[53][0], /* fr21 */ \ | |
2318 | &rs6000_reg_names[54][0], /* fr22 */ \ | |
2319 | &rs6000_reg_names[55][0], /* fr23 */ \ | |
2320 | &rs6000_reg_names[56][0], /* fr24 */ \ | |
2321 | &rs6000_reg_names[57][0], /* fr25 */ \ | |
2322 | &rs6000_reg_names[58][0], /* fr26 */ \ | |
2323 | &rs6000_reg_names[59][0], /* fr27 */ \ | |
2324 | &rs6000_reg_names[60][0], /* fr28 */ \ | |
2325 | &rs6000_reg_names[61][0], /* fr29 */ \ | |
2326 | &rs6000_reg_names[62][0], /* fr30 */ \ | |
2327 | &rs6000_reg_names[63][0], /* fr31 */ \ | |
2328 | \ | |
2329 | &rs6000_reg_names[64][0], /* mq */ \ | |
2330 | &rs6000_reg_names[65][0], /* lr */ \ | |
2331 | &rs6000_reg_names[66][0], /* ctr */ \ | |
2332 | &rs6000_reg_names[67][0], /* ap */ \ | |
2333 | \ | |
2334 | &rs6000_reg_names[68][0], /* cr0 */ \ | |
2335 | &rs6000_reg_names[69][0], /* cr1 */ \ | |
2336 | &rs6000_reg_names[70][0], /* cr2 */ \ | |
2337 | &rs6000_reg_names[71][0], /* cr3 */ \ | |
2338 | &rs6000_reg_names[72][0], /* cr4 */ \ | |
2339 | &rs6000_reg_names[73][0], /* cr5 */ \ | |
2340 | &rs6000_reg_names[74][0], /* cr6 */ \ | |
2341 | &rs6000_reg_names[75][0], /* cr7 */ \ | |
802a0058 | 2342 | \ |
9ebbca7d | 2343 | &rs6000_reg_names[76][0], /* xer */ \ |
c81bebd7 MM |
2344 | } |
2345 | ||
2346 | /* print-rtl can't handle the above REGISTER_NAMES, so define the | |
2347 | following for it. Switch to use the alternate names since | |
2348 | they are more mnemonic. */ | |
2349 | ||
2350 | #define DEBUG_REGISTER_NAMES \ | |
2351 | { \ | |
802a0058 MM |
2352 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ |
2353 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
2354 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ | |
2355 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ | |
2356 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
2357 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
2358 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ | |
2359 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \ | |
2360 | "mq", "lr", "ctr", "ap", \ | |
2361 | "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \ | |
9ebbca7d | 2362 | "xer" \ |
c81bebd7 | 2363 | } |
f045b2c9 RS |
2364 | |
2365 | /* Table of additional register names to use in user input. */ | |
2366 | ||
2367 | #define ADDITIONAL_REGISTER_NAMES \ | |
c4d38ccb MM |
2368 | {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ |
2369 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2370 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2371 | {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2372 | {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2373 | {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2374 | {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2375 | {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2376 | {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2377 | {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2378 | {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2379 | {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2380 | {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2381 | {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2382 | {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2383 | {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
2384 | /* no additional names for: mq, lr, ctr, ap */ \ | |
2385 | {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ | |
2386 | {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
2387 | {"cc", 68}, {"sp", 1}, {"toc", 2} } | |
f045b2c9 RS |
2388 | |
2389 | /* How to renumber registers for dbx and gdb. */ | |
2390 | ||
2391 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
2392 | ||
0da40b09 RK |
2393 | /* Text to write out after a CALL that may be replaced by glue code by |
2394 | the loader. This depends on the AIX version. */ | |
2395 | #define RS6000_CALL_GLUE "cror 31,31,31" | |
11117bb9 | 2396 | |
f045b2c9 RS |
2397 | /* This is how to output an assembler line defining a `double' constant. */ |
2398 | ||
b5253831 DE |
2399 | #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \ |
2400 | { \ | |
2401 | long t[2]; \ | |
2402 | REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ | |
2403 | fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", \ | |
0858c623 | 2404 | t[0] & 0xffffffff, t[1] & 0xffffffff); \ |
a5b1eb34 | 2405 | } |
f045b2c9 RS |
2406 | |
2407 | /* This is how to output an assembler line defining a `float' constant. */ | |
2408 | ||
b5253831 DE |
2409 | #define ASM_OUTPUT_FLOAT(FILE, VALUE) \ |
2410 | { \ | |
2411 | long t; \ | |
2412 | REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ | |
0858c623 | 2413 | fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \ |
a5b1eb34 | 2414 | } |
f045b2c9 RS |
2415 | |
2416 | /* This is how to output an assembler line defining an `int' constant. */ | |
2417 | ||
5854b0d0 DE |
2418 | #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ |
2419 | do { \ | |
2420 | if (TARGET_32BIT) \ | |
2421 | { \ | |
2422 | assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \ | |
2423 | UNITS_PER_WORD, 1); \ | |
2424 | assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \ | |
2425 | UNITS_PER_WORD, 1); \ | |
2426 | } \ | |
2427 | else \ | |
2428 | { \ | |
2bfcf297 | 2429 | fprintf (FILE, "\t%s ", DOUBLE_INT_ASM_OP); \ |
5854b0d0 DE |
2430 | output_addr_const (FILE, (VALUE)); \ |
2431 | putc ('\n', FILE); \ | |
2432 | } \ | |
2433 | } while (0) | |
2434 | ||
f045b2c9 | 2435 | #define ASM_OUTPUT_INT(FILE,VALUE) \ |
19d2d16f | 2436 | ( fputs ("\t.long ", FILE), \ |
f045b2c9 | 2437 | output_addr_const (FILE, (VALUE)), \ |
19d2d16f | 2438 | putc ('\n', FILE)) |
f045b2c9 RS |
2439 | |
2440 | /* Likewise for `char' and `short' constants. */ | |
2441 | ||
2442 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
19d2d16f | 2443 | ( fputs ("\t.short ", FILE), \ |
f045b2c9 | 2444 | output_addr_const (FILE, (VALUE)), \ |
19d2d16f | 2445 | putc ('\n', FILE)) |
f045b2c9 RS |
2446 | |
2447 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
19d2d16f | 2448 | ( fputs ("\t.byte ", FILE), \ |
f045b2c9 | 2449 | output_addr_const (FILE, (VALUE)), \ |
19d2d16f | 2450 | putc ('\n', FILE)) |
f045b2c9 RS |
2451 | |
2452 | /* This is how to output an assembler line for a numeric constant byte. */ | |
2453 | ||
2454 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
2455 | fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) | |
2456 | ||
9ebbca7d | 2457 | /* This is used by the definition of ASM_OUTPUT_ADDR_ELT in defaults.h. */ |
2bfcf297 | 2458 | #define ASM_LONG (TARGET_32BIT ? ".long" : DOUBLE_INT_ASM_OP) |
f045b2c9 RS |
2459 | |
2460 | /* This is how to output an element of a case-vector that is relative. */ | |
2461 | ||
e1565e65 | 2462 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3daf36a4 | 2463 | do { char buf[100]; \ |
e1565e65 | 2464 | fputs ("\t.long ", FILE); \ |
3daf36a4 ILT |
2465 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ |
2466 | assemble_name (FILE, buf); \ | |
19d2d16f | 2467 | putc ('-', FILE); \ |
3daf36a4 ILT |
2468 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ |
2469 | assemble_name (FILE, buf); \ | |
19d2d16f | 2470 | putc ('\n', FILE); \ |
3daf36a4 | 2471 | } while (0) |
f045b2c9 RS |
2472 | |
2473 | /* This is how to output an assembler line | |
2474 | that says to advance the location counter | |
2475 | to a multiple of 2**LOG bytes. */ | |
2476 | ||
2477 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2478 | if ((LOG) != 0) \ | |
2479 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
2480 | ||
f045b2c9 RS |
2481 | /* Store in OUTPUT a string (made with alloca) containing |
2482 | an assembler-name for a local static variable named NAME. | |
2483 | LABELNO is an integer which is different for each call. */ | |
2484 | ||
2485 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
2486 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
2487 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
2488 | ||
2bfcf297 DB |
2489 | /* Define the parentheses used to group arithmetic operations |
2490 | in assembler code. */ | |
2491 | ||
2492 | #define ASM_OPEN_PAREN "(" | |
2493 | #define ASM_CLOSE_PAREN ")" | |
2494 | ||
9ebbca7d GK |
2495 | /* Pick up the return address upon entry to a procedure. Used for |
2496 | dwarf2 unwind information. This also enables the table driven | |
2497 | mechanism. */ | |
2498 | ||
2499 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
8034da37 | 2500 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM) |
9ebbca7d | 2501 | |
83720594 RH |
2502 | /* Describe how we implement __builtin_eh_return. */ |
2503 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2504 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2505 | ||
f045b2c9 RS |
2506 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2507 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2508 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2509 | ||
2510 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2511 | ||
2512 | /* Define which CODE values are valid. */ | |
2513 | ||
c81bebd7 MM |
2514 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
2515 | ((CODE) == '.' || (CODE) == '*' || (CODE) == '$') | |
f045b2c9 RS |
2516 | |
2517 | /* Print a memory address as an operand to reference that memory location. */ | |
2518 | ||
2519 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2520 | ||
2521 | /* Define the codes that are matched by predicates in rs6000.c. */ | |
2522 | ||
39a10a29 GK |
2523 | #define PREDICATE_CODES \ |
2524 | {"short_cint_operand", {CONST_INT}}, \ | |
2525 | {"u_short_cint_operand", {CONST_INT}}, \ | |
2526 | {"non_short_cint_operand", {CONST_INT}}, \ | |
2bfcf297 | 2527 | {"exact_log2_cint_operand", {CONST_INT}}, \ |
39a10a29 GK |
2528 | {"gpc_reg_operand", {SUBREG, REG}}, \ |
2529 | {"cc_reg_operand", {SUBREG, REG}}, \ | |
2530 | {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \ | |
2531 | {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \ | |
2532 | {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \ | |
2533 | {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \ | |
2534 | {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ | |
2535 | {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \ | |
2bfcf297 DB |
2536 | {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \ |
2537 | {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \ | |
1d328b19 | 2538 | {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ |
39a10a29 GK |
2539 | {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ |
2540 | {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \ | |
2541 | {"easy_fp_constant", {CONST_DOUBLE}}, \ | |
50a0b056 | 2542 | {"zero_fp_constant", {CONST_DOUBLE}}, \ |
39a10a29 GK |
2543 | {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \ |
2544 | {"lwa_operand", {SUBREG, MEM, REG}}, \ | |
2545 | {"volatile_mem_operand", {MEM}}, \ | |
2546 | {"offsettable_mem_operand", {MEM}}, \ | |
2547 | {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \ | |
2548 | {"add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2549 | {"non_add_cint_operand", {CONST_INT}}, \ | |
2550 | {"and_operand", {SUBREG, REG, CONST_INT}}, \ | |
2551 | {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
2552 | {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
2553 | {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \ | |
2554 | {"mask_operand", {CONST_INT}}, \ | |
2555 | {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \ | |
2556 | {"rldic_operand", {CONST_INT, CONST_DOUBLE}}, \ | |
2557 | {"count_register_operand", {REG}}, \ | |
2558 | {"xer_operand", {REG}}, \ | |
2559 | {"call_operand", {SYMBOL_REF, REG}}, \ | |
2560 | {"current_file_function_operand", {SYMBOL_REF}}, \ | |
2561 | {"input_operand", {SUBREG, MEM, REG, CONST_INT, \ | |
2562 | CONST_DOUBLE, SYMBOL_REF}}, \ | |
2563 | {"load_multiple_operation", {PARALLEL}}, \ | |
2564 | {"store_multiple_operation", {PARALLEL}}, \ | |
2565 | {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \ | |
2566 | GT, LEU, LTU, GEU, GTU, \ | |
2567 | UNORDERED, ORDERED, \ | |
2568 | UNGE, UNLE }}, \ | |
2569 | {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \ | |
2570 | UNORDERED }}, \ | |
2571 | {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \ | |
2572 | GT, LEU, LTU, GEU, GTU, \ | |
2573 | UNORDERED, ORDERED, \ | |
2574 | UNGE, UNLE }}, \ | |
2575 | {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \ | |
2576 | GT, LEU, LTU, GEU, GTU}}, \ | |
2577 | {"boolean_operator", {AND, IOR, XOR}}, \ | |
50a0b056 GK |
2578 | {"boolean_or_operator", {IOR, XOR}}, \ |
2579 | {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}}, | |
75814ad4 | 2580 | |
b6c9286a MM |
2581 | /* uncomment for disabling the corresponding default options */ |
2582 | /* #define MACHINE_no_sched_interblock */ | |
2583 | /* #define MACHINE_no_sched_speculative */ | |
2584 | /* #define MACHINE_no_sched_speculative_load */ | |
2585 | ||
2586 | /* indicate that issue rate is defined for this machine | |
2587 | (no need to use the default) */ | |
246853b9 | 2588 | #define ISSUE_RATE get_issue_rate () |
b6c9286a | 2589 | |
766a866c MM |
2590 | /* General flags. */ |
2591 | extern int flag_pic; | |
354b734b MM |
2592 | extern int optimize; |
2593 | extern int flag_expensive_optimizations; | |
a7df97e6 | 2594 | extern int frame_pointer_needed; |