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configure.ac: Add test for dci instruction.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.h
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f045b2c9 1/* Definitions of target machine for GNU compiler, for IBM RS/6000.
9ebbca7d 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
748086b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
602ea4d3 4 Free Software Foundation, Inc.
6a7ec0a7 5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
f045b2c9 6
5de601cf 7 This file is part of GCC.
f045b2c9 8
5de601cf
NC		 9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
2f83c7d6 11 by the Free Software Foundation; either version 3, or (at your
5de601cf 12 option) any later version.
f045b2c9 13
5de601cf
NC		 14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
f045b2c9 18
748086b7
JJ		 19 Under Section 7 of GPL version 3, you are granted additional
20 permissions described in the GCC Runtime Library Exception, version
21 3.1, as published by the Free Software Foundation.
22
23 You should have received a copy of the GNU General Public License and
24 a copy of the GCC Runtime Library Exception along with this program;
25 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2f83c7d6 26 <http://www.gnu.org/licenses/>. */
f045b2c9
RS		 27
28/* Note that some other tm.h files include this one and then override
9ebbca7d 29 many of the definitions. */
f045b2c9 30
9ebbca7d
GK		 31/* Definitions for the object file format. These are set at
32 compile-time. */
f045b2c9 33
9ebbca7d
GK		 34#define OBJECT_XCOFF 1
35#define OBJECT_ELF 2
36#define OBJECT_PEF 3
ee890fe2 37#define OBJECT_MACHO 4
f045b2c9 38
9ebbca7d 39#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
2bfcf297 40#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
9ebbca7d 41#define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
ee890fe2 42#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
f045b2c9 43
2bfcf297
DB		 44#ifndef TARGET_AIX
45#define TARGET_AIX 0
46#endif
47
85b776df
AM		 48/* Control whether function entry points use a "dot" symbol when
49 ABI_AIX. */
50#define DOT_SYMBOLS 1
51
8e3f41e7
MM		 52/* Default string to use for cpu if not specified. */
53#ifndef TARGET_CPU_DEFAULT
54#define TARGET_CPU_DEFAULT ((char *)0)
55#endif
56
f565b0a1 57/* If configured for PPC405, support PPC405CR Erratum77. */
b0bfee6e 58#ifdef CONFIG_PPC405CR
f565b0a1
DE		 59#define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
60#else
61#define PPC405_ERRATUM77 0
62#endif
63
96038623
DE		 64#ifndef TARGET_PAIRED_FLOAT
65#define TARGET_PAIRED_FLOAT 0
66#endif
67
cd679487
BE		 68#ifdef HAVE_AS_POPCNTB
69#define ASM_CPU_POWER5_SPEC "-mpower5"
70#else
71#define ASM_CPU_POWER5_SPEC "-mpower4"
72#endif
73
74#ifdef HAVE_AS_DFP
75#define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
76#else
77#define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
78#endif
79
cacf1ca8 80#ifdef HAVE_AS_POPCNTD
d40c9e33
PB		 81#define ASM_CPU_POWER7_SPEC "-mpower7"
82#else
83#define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
84#endif
85
47f67e51
PB		 86#ifdef HAVE_AS_DCI
87#define ASM_CPU_476_SPEC "-m476"
88#else
89#define ASM_CPU_476_SPEC "-mpower4"
90#endif
91
cacf1ca8
MM		 92/* Common ASM definitions used by ASM_SPEC among the various targets for
93 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
94 provide the default assembler options if the user uses -mcpu=native, so if
95 you make changes here, make them also there. */
f984d8df
DB		 96#define ASM_CPU_SPEC \
97"%{!mcpu*: \
98 %{mpower: %{!mpower2: -mpwr}} \
99 %{mpower2: -mpwrx} \
93ae5495
AM		 100 %{mpowerpc64*: -mppc64} \
101 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
f984d8df 102 %{mno-power: %{!mpowerpc*: -mcom}} \
93ae5495 103 %{!mno-power: %{!mpower*: %(asm_default)}}} \
cacf1ca8 104%{mcpu=native: %(asm_cpu_native)} \
f984d8df 105%{mcpu=common: -mcom} \
d296e02e 106%{mcpu=cell: -mcell} \
f984d8df
DB		 107%{mcpu=power: -mpwr} \
108%{mcpu=power2: -mpwrx} \
93ae5495 109%{mcpu=power3: -mppc64} \
957e9e48 110%{mcpu=power4: -mpower4} \
cd679487
BE		 111%{mcpu=power5: %(asm_cpu_power5)} \
112%{mcpu=power5+: %(asm_cpu_power5)} \
113%{mcpu=power6: %(asm_cpu_power6) -maltivec} \
114%{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
d40c9e33 115%{mcpu=power7: %(asm_cpu_power7)} \
ebde32fd 116%{mcpu=a2: -ma2} \
f984d8df
DB		 117%{mcpu=powerpc: -mppc} \
118%{mcpu=rios: -mpwr} \
119%{mcpu=rios1: -mpwr} \
120%{mcpu=rios2: -mpwrx} \
121%{mcpu=rsc: -mpwr} \
122%{mcpu=rsc1: -mpwr} \
93ae5495 123%{mcpu=rs64a: -mppc64} \
f984d8df 124%{mcpu=401: -mppc} \
61a8515c
JS		 125%{mcpu=403: -m403} \
126%{mcpu=405: -m405} \
2c9d95ef
DE		 127%{mcpu=405fp: -m405} \
128%{mcpu=440: -m440} \
129%{mcpu=440fp: -m440} \
4adf8008
PB		 130%{mcpu=464: -m440} \
131%{mcpu=464fp: -m440} \
47f67e51
PB		 132%{mcpu=476: %(asm_cpu_476)} \
133%{mcpu=476fp: %(asm_cpu_476)} \
f984d8df
DB		 134%{mcpu=505: -mppc} \
135%{mcpu=601: -m601} \
136%{mcpu=602: -mppc} \
137%{mcpu=603: -mppc} \
138%{mcpu=603e: -mppc} \
139%{mcpu=ec603e: -mppc} \
140%{mcpu=604: -mppc} \
141%{mcpu=604e: -mppc} \
93ae5495
AM		 142%{mcpu=620: -mppc64} \
143%{mcpu=630: -mppc64} \
f984d8df
DB		 144%{mcpu=740: -mppc} \
145%{mcpu=750: -mppc} \
49ffe578 146%{mcpu=G3: -mppc} \
93ae5495
AM		 147%{mcpu=7400: -mppc -maltivec} \
148%{mcpu=7450: -mppc -maltivec} \
149%{mcpu=G4: -mppc -maltivec} \
f984d8df
DB		 150%{mcpu=801: -mppc} \
151%{mcpu=821: -mppc} \
152%{mcpu=823: -mppc} \
775db490 153%{mcpu=860: -mppc} \
93ae5495
AM		 154%{mcpu=970: -mpower4 -maltivec} \
155%{mcpu=G5: -mpower4 -maltivec} \
a3170dc6 156%{mcpu=8540: -me500} \
5ca0373f 157%{mcpu=8548: -me500} \
fa41c305
EW		 158%{mcpu=e300c2: -me300} \
159%{mcpu=e300c3: -me300} \
edae5fe3 160%{mcpu=e500mc: -me500mc} \
93ae5495
AM		 161%{maltivec: -maltivec} \
162-many"
f984d8df
DB		 163
164#define CPP_DEFAULT_SPEC ""
165
166#define ASM_DEFAULT_SPEC ""
167
841faeed
MM		 168/* This macro defines names of additional specifications to put in the specs
169 that can be used in various specifications like CC1_SPEC. Its definition
170 is an initializer with a subgrouping for each command option.
171
172 Each subgrouping contains a string constant, that defines the
5de601cf 173 specification name, and a string constant that used by the GCC driver
841faeed
MM		 174 program.
175
176 Do not define this macro if it does not need to do anything. */
177
7509c759 178#define SUBTARGET_EXTRA_SPECS
7509c759 179
c81bebd7 180#define EXTRA_SPECS \
c81bebd7 181 { "cpp_default", CPP_DEFAULT_SPEC }, \
c81bebd7 182 { "asm_cpu", ASM_CPU_SPEC }, \
cacf1ca8 183 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
c81bebd7 184 { "asm_default", ASM_DEFAULT_SPEC }, \
0eab6840 185 { "cc1_cpu", CC1_CPU_SPEC }, \
cd679487
BE		 186 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
187 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
d40c9e33 188 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
47f67e51 189 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
7509c759
MM		 190 SUBTARGET_EXTRA_SPECS
191
0eab6840
DE		 192/* -mcpu=native handling only makes sense with compiler running on
193 an PowerPC chip. If changing this condition, also change
194 the condition in driver-rs6000.c. */
195#if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
196/* In driver-rs6000.c. */
197extern const char *host_detect_local_cpu (int argc, const char **argv);
198#define EXTRA_SPEC_FUNCTIONS \
199 { "local_cpu_detect", host_detect_local_cpu },
200#define HAVE_LOCAL_CPU_DETECT
cacf1ca8
MM		 201#define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
202
203#else
204#define ASM_CPU_NATIVE_SPEC "%(asm_default)"
0eab6840
DE		 205#endif
206
ee7caeb3
DE		 207#ifndef CC1_CPU_SPEC
208#ifdef HAVE_LOCAL_CPU_DETECT
0eab6840
DE		 209#define CC1_CPU_SPEC \
210"%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
211 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
ee7caeb3
DE		 212#else
213#define CC1_CPU_SPEC ""
214#endif
0eab6840
DE		 215#endif
216
fb623df5 217/* Architecture type. */
f045b2c9 218
bb22512c 219/* Define TARGET_MFCRF if the target assembler does not support the
78f5898b 220 optional field operand for mfcr. */
fb623df5 221
78f5898b 222#ifndef HAVE_AS_MFCRF
432218ba 223#undef TARGET_MFCRF
ffa22984
DE		 224#define TARGET_MFCRF 0
225#endif
226
0fa2e4df 227/* Define TARGET_POPCNTB if the target assembler does not support the
432218ba
DE		 228 popcount byte instruction. */
229
230#ifndef HAVE_AS_POPCNTB
231#undef TARGET_POPCNTB
232#define TARGET_POPCNTB 0
233#endif
234
9719f3b7
DE		 235/* Define TARGET_FPRND if the target assembler does not support the
236 fp rounding instructions. */
237
238#ifndef HAVE_AS_FPRND
239#undef TARGET_FPRND
240#define TARGET_FPRND 0
241#endif
242
b639c3c2
JJ		 243/* Define TARGET_CMPB if the target assembler does not support the
244 cmpb instruction. */
245
246#ifndef HAVE_AS_CMPB
247#undef TARGET_CMPB
248#define TARGET_CMPB 0
249#endif
250
44cd321e
PS		 251/* Define TARGET_MFPGPR if the target assembler does not support the
252 mffpr and mftgpr instructions. */
253
254#ifndef HAVE_AS_MFPGPR
255#undef TARGET_MFPGPR
256#define TARGET_MFPGPR 0
257#endif
258
b639c3c2
JJ		 259/* Define TARGET_DFP if the target assembler does not support decimal
260 floating point instructions. */
261#ifndef HAVE_AS_DFP
262#undef TARGET_DFP
263#define TARGET_DFP 0
264#endif
265
cacf1ca8
MM		 266/* Define TARGET_POPCNTD if the target assembler does not support the
267 popcount word and double word instructions. */
268
269#ifndef HAVE_AS_POPCNTD
270#undef TARGET_POPCNTD
271#define TARGET_POPCNTD 0
272#endif
273
274/* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
275 not, generate the lwsync code as an integer constant. */
276#ifdef HAVE_AS_LWSYNC
277#define TARGET_LWSYNC_INSTRUCTION 1
278#else
279#define TARGET_LWSYNC_INSTRUCTION 0
280#endif
281
9752c4ad
AM		 282/* Define TARGET_TLS_MARKERS if the target assembler does not support
283 arg markers for __tls_get_addr calls. */
284#ifndef HAVE_AS_TLS_MARKERS
285#undef TARGET_TLS_MARKERS
286#define TARGET_TLS_MARKERS 0
287#else
288#define TARGET_TLS_MARKERS tls_markers
289#endif
290
7f970b70
AM		 291#ifndef TARGET_SECURE_PLT
292#define TARGET_SECURE_PLT 0
293#endif
294
2f3e5814 295#define TARGET_32BIT (! TARGET_64BIT)
d14a6d05 296
c4501e62
JJ		 297#ifndef HAVE_AS_TLS
298#define HAVE_AS_TLS 0
299#endif
300
48d72335
DE		 301/* Return 1 for a symbol ref for a thread-local storage symbol. */
302#define RS6000_SYMBOL_REF_TLS_P(RTX) \
303 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
304
996ed075
JJ		 305#ifdef IN_LIBGCC2
306/* For libgcc2 we make sure this is a compile time constant */
67796c1f 307#if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
78f5898b 308#undef TARGET_POWERPC64
996ed075
JJ		 309#define TARGET_POWERPC64 1
310#else
78f5898b 311#undef TARGET_POWERPC64
996ed075
JJ		 312#define TARGET_POWERPC64 0
313#endif
b6c9286a 314#else
78f5898b 315 /* The option machinery will define this. */
b6c9286a
MM		 316#endif
317
938937d8 318#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
9ebbca7d 319
cac8ce95 320/* Processor type. Order must match cpu attribute in MD file. */
fb623df5 321enum processor_type
bef84347
VM		 322 {
323 PROCESSOR_RIOS1,
324 PROCESSOR_RIOS2,
3cb999d8 325 PROCESSOR_RS64A,
bef84347
VM		 326 PROCESSOR_MPCCORE,
327 PROCESSOR_PPC403,
fe7f5677 328 PROCESSOR_PPC405,
b54cf83a 329 PROCESSOR_PPC440,
47f67e51 330 PROCESSOR_PPC476,
bef84347
VM		 331 PROCESSOR_PPC601,
332 PROCESSOR_PPC603,
333 PROCESSOR_PPC604,
334 PROCESSOR_PPC604e,
335 PROCESSOR_PPC620,
3cb999d8 336 PROCESSOR_PPC630,
ed947a96
DJ		 337 PROCESSOR_PPC750,
338 PROCESSOR_PPC7400,
309323c2 339 PROCESSOR_PPC7450,
a3170dc6 340 PROCESSOR_PPC8540,
fa41c305
EW		 341 PROCESSOR_PPCE300C2,
342 PROCESSOR_PPCE300C3,
edae5fe3 343 PROCESSOR_PPCE500MC,
ec507f2d 344 PROCESSOR_POWER4,
44cd321e 345 PROCESSOR_POWER5,
d296e02e 346 PROCESSOR_POWER6,
cacf1ca8 347 PROCESSOR_POWER7,
ebde32fd
BE		 348 PROCESSOR_CELL,
349 PROCESSOR_PPCA2
bef84347 350};
fb623df5 351
696e45ba
ME		 352/* FPU operations supported.
353 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
354 also test TARGET_HARD_FLOAT. */
355#define TARGET_SINGLE_FLOAT 1
356#define TARGET_DOUBLE_FLOAT 1
357#define TARGET_SINGLE_FPU 0
358#define TARGET_SIMPLE_FPU 0
0bb7b92e 359#define TARGET_XILINX_FPU 0
696e45ba 360
fb623df5
RK		 361extern enum processor_type rs6000_cpu;
362
363/* Recast the processor type to the cpu attribute. */
364#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
365
8482e358 366/* Define generic processor types based upon current deployment. */
3cb999d8
DE		 367#define PROCESSOR_COMMON PROCESSOR_PPC601
368#define PROCESSOR_POWER PROCESSOR_RIOS1
369#define PROCESSOR_POWERPC PROCESSOR_PPC604
370#define PROCESSOR_POWERPC64 PROCESSOR_RS64A
6e151478 371
fb623df5 372/* Define the default processor. This is overridden by other tm.h files. */
3cb999d8
DE		 373#define PROCESSOR_DEFAULT PROCESSOR_RIOS1
374#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
fb623df5 375
0bb7b92e
ME		 376/* FP processor type. */
377enum fpu_type_t
378{
379 FPU_NONE, /* No FPU */
380 FPU_SF_LITE, /* Limited Single Precision FPU */
381 FPU_DF_LITE, /* Limited Double Precision FPU */
382 FPU_SF_FULL, /* Full Single Precision FPU */
383 FPU_DF_FULL /* Full Double Single Precision FPU */
384};
385
386extern enum fpu_type_t fpu_type;
387
6febd581
RK		 388/* Specify the dialect of assembler to use. New mnemonics is dialect one
389 and the old mnemonics are dialect zero. */
9ebbca7d 390#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
6febd581 391
569fa502
DN		 392/* Types of costly dependences. */
393enum rs6000_dependence_cost
394 {
395 max_dep_latency = 1000,
396 no_dep_costly,
397 all_deps_costly,
398 true_store_to_load_dep_costly,
399 store_to_load_dep_costly
400 };
401
cbe26ab8
DN		 402/* Types of nop insertion schemes in sched target hook sched_finish. */
403enum rs6000_nop_insertion
404 {
405 sched_finish_regroup_exact = 1000,
406 sched_finish_pad_groups,
407 sched_finish_none
408 };
409
410/* Dispatch group termination caused by an insn. */
411enum group_termination
412 {
413 current_group,
414 previous_group
415 };
416
ff222560 417/* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
8e3f41e7
MM		 418struct rs6000_cpu_select
419{
815cdc52
MM		 420 const char *string;
421 const char *name;
8e3f41e7
MM		 422 int set_tune_p;
423 int set_arch_p;
424};
425
426extern struct rs6000_cpu_select rs6000_select[];
fb623df5 427
38c1f2d7 428/* Debug support */
0ac081f6 429extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
38c1f2d7
MM		 430extern int rs6000_debug_stack; /* debug stack applications */
431extern int rs6000_debug_arg; /* debug argument handling */
cacf1ca8
MM		 432extern int rs6000_debug_reg; /* debug register handling */
433extern int rs6000_debug_addr; /* debug memory addressing */
434extern int rs6000_debug_cost; /* debug rtx_costs */
38c1f2d7
MM		 435
436#define TARGET_DEBUG_STACK rs6000_debug_stack
437#define TARGET_DEBUG_ARG rs6000_debug_arg
cacf1ca8
MM		 438#define TARGET_DEBUG_REG rs6000_debug_reg
439#define TARGET_DEBUG_ADDR rs6000_debug_addr
440#define TARGET_DEBUG_COST rs6000_debug_cost
38c1f2d7 441
57ac7be9
AM		 442extern const char *rs6000_traceback_name; /* Type of traceback table. */
443
6fa3f289
ZW		 444/* These are separate from target_flags because we've run out of bits
445 there. */
6fa3f289 446extern int rs6000_long_double_type_size;
602ea4d3 447extern int rs6000_ieeequad;
6fa3f289 448extern int rs6000_altivec_abi;
a3170dc6 449extern int rs6000_spe_abi;
94f4765c 450extern int rs6000_spe;
5da702b1 451extern int rs6000_float_gprs;
025d9908 452extern int rs6000_alignment_flags;
cbe26ab8
DN		 453extern const char *rs6000_sched_insert_nops_str;
454extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
0bb7b92e 455extern int rs6000_xilinx_fpu;
025d9908 456
cacf1ca8
MM		 457/* Describe which vector unit to use for a given machine mode. */
458enum rs6000_vector {
459 VECTOR_NONE, /* Type is not a vector or not supported */
460 VECTOR_ALTIVEC, /* Use altivec for vector processing */
461 VECTOR_VSX, /* Use VSX for vector processing */
462 VECTOR_PAIRED, /* Use paired floating point for vectors */
463 VECTOR_SPE, /* Use SPE for vector processing */
464 VECTOR_OTHER /* Some other vector unit */
465};
466
467extern enum rs6000_vector rs6000_vector_unit[];
468
469#define VECTOR_UNIT_NONE_P(MODE) \
470 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
471
472#define VECTOR_UNIT_VSX_P(MODE) \
473 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
474
475#define VECTOR_UNIT_ALTIVEC_P(MODE) \
476 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
477
478#define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
479 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \
480 || rs6000_vector_unit[(MODE)] == VECTOR_VSX)
481
482/* Describe whether to use VSX loads or Altivec loads. For now, just use the
483 same unit as the vector unit we are using, but we may want to migrate to
484 using VSX style loads even for types handled by altivec. */
485extern enum rs6000_vector rs6000_vector_mem[];
486
487#define VECTOR_MEM_NONE_P(MODE) \
488 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
489
490#define VECTOR_MEM_VSX_P(MODE) \
491 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
492
493#define VECTOR_MEM_ALTIVEC_P(MODE) \
494 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
495
496#define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
497 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \
498 || rs6000_vector_mem[(MODE)] == VECTOR_VSX)
499
500/* Return the alignment of a given vector type, which is set based on the
501 vector unit use. VSX for instance can load 32 or 64 bit aligned words
502 without problems, while Altivec requires 128-bit aligned vectors. */
503extern int rs6000_vector_align[];
504
505#define VECTOR_ALIGN(MODE) \
506 ((rs6000_vector_align[(MODE)] != 0) \
507 ? rs6000_vector_align[(MODE)] \
508 : (int)GET_MODE_BITSIZE ((MODE)))
509
025d9908
KH		 510/* Alignment options for fields in structures for sub-targets following
511 AIX-like ABI.
512 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
513 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
514
515 Override the macro definitions when compiling libobjc to avoid undefined
516 reference to rs6000_alignment_flags due to library's use of GCC alignment
517 macros which use the macros below. */
f676971a 518
025d9908
KH		 519#ifndef IN_TARGET_LIBS
520#define MASK_ALIGN_POWER 0x00000000
521#define MASK_ALIGN_NATURAL 0x00000001
522#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
523#else
524#define TARGET_ALIGN_NATURAL 0
525#endif
6fa3f289
ZW		 526
527#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
602ea4d3 528#define TARGET_IEEEQUAD rs6000_ieeequad
6fa3f289 529#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
cacf1ca8 530#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
6fa3f289 531
a3170dc6
AH		 532#define TARGET_SPE_ABI 0
533#define TARGET_SPE 0
993f19a8 534#define TARGET_E500 0
cacf1ca8 535#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
a3170dc6 536#define TARGET_FPRS 1
4d4cbc0e
AH		 537#define TARGET_E500_SINGLE 0
538#define TARGET_E500_DOUBLE 0
eca0d5e8 539#define CHECK_E500_OPTIONS do { } while (0)
a3170dc6 540
86098753
JM		 541/* E500 processors only support plain "sync", not lwsync. */
542#define TARGET_NO_LWSYNC TARGET_E500
543
fb623df5
RK		 544/* Sometimes certain combinations of command options do not make sense
545 on a particular target machine. You can define a macro
546 `OVERRIDE_OPTIONS' to take account of this. This macro, if
547 defined, is executed once just after all the command options have
548 been parsed.
549
ffa22984 550 Do not use this macro to turn on various extra optimizations for
5accd822
DE		 551 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
552
fb623df5
RK		 553 On the RS/6000 this is used to define the target cpu type. */
554
8e3f41e7 555#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
f045b2c9 556
5accd822
DE		 557/* Define this to change the optimizations performed by default. */
558#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
559
4c4eb375
GK		 560/* Show we can debug even without a frame pointer. */
561#define CAN_DEBUG_WITHOUT_FP
562
a5c76ee6 563/* Target pragma. */
c58b209a
NB		 564#define REGISTER_TARGET_PRAGMAS() do { \
565 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
2fab365e 566 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
a5c76ee6
ZW		 567} while (0)
568
4c4eb375
GK		 569/* Target #defines. */
570#define TARGET_CPU_CPP_BUILTINS() \
571 rs6000_cpu_cpp_builtins (pfile)
647d340d
JT		 572
573/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
574 we're compiling for. Some configurations may need to override it. */
575#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
576 do \
577 { \
578 if (BYTES_BIG_ENDIAN) \
579 { \
580 builtin_define ("__BIG_ENDIAN__"); \
581 builtin_define ("_BIG_ENDIAN"); \
582 builtin_assert ("machine=bigendian"); \
583 } \
584 else \
585 { \
586 builtin_define ("__LITTLE_ENDIAN__"); \
587 builtin_define ("_LITTLE_ENDIAN"); \
588 builtin_assert ("machine=littleendian"); \
589 } \
590 } \
591 while (0)
f045b2c9 592\f
4c4eb375 593/* Target machine storage layout. */
f045b2c9 594
13d39dbc 595/* Define this macro if it is advisable to hold scalars in registers
c81bebd7 596 in a wider mode than that declared by the program. In such cases,
ef457bda
RK		 597 the value is constrained to be within the bounds of the declared
598 type, but kept valid in the wider mode. The signedness of the
599 extension may differ from that of the type. */
600
39403d82
DE		 601#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
602 if (GET_MODE_CLASS (MODE) == MODE_INT \
603 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
b78d48dd 604 (MODE) = TARGET_32BIT ? SImode : DImode;
39403d82 605
f045b2c9 606/* Define this if most significant bit is lowest numbered
82e41834
KH		 607 in instructions that operate on numbered bit-fields. */
608/* That is true on RS/6000. */
f045b2c9
RS		 609#define BITS_BIG_ENDIAN 1
610
611/* Define this if most significant byte of a word is the lowest numbered. */
612/* That is true on RS/6000. */
613#define BYTES_BIG_ENDIAN 1
614
615/* Define this if most significant word of a multiword number is lowest
c81bebd7 616 numbered.
f045b2c9
RS		 617
618 For RS/6000 we can decide arbitrarily since there are no machine
82e41834 619 instructions for them. Might as well be consistent with bits and bytes. */
f045b2c9
RS		 620#define WORDS_BIG_ENDIAN 1
621
2e360ab3 622#define MAX_BITS_PER_WORD 64
f045b2c9
RS		 623
624/* Width of a word, in units (bytes). */
c1aa3958 625#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
f34fc46e
DE		 626#ifdef IN_LIBGCC2
627#define MIN_UNITS_PER_WORD UNITS_PER_WORD
628#else
ef0e53ce 629#define MIN_UNITS_PER_WORD 4
f34fc46e 630#endif
2e360ab3 631#define UNITS_PER_FP_WORD 8
0ac081f6 632#define UNITS_PER_ALTIVEC_WORD 16
cacf1ca8 633#define UNITS_PER_VSX_WORD 16
a3170dc6 634#define UNITS_PER_SPE_WORD 8
96038623 635#define UNITS_PER_PAIRED_WORD 8
f045b2c9 636
915f619f
JW		 637/* Type used for ptrdiff_t, as a string used in a declaration. */
638#define PTRDIFF_TYPE "int"
639
058ef853
DE		 640/* Type used for size_t, as a string used in a declaration. */
641#define SIZE_TYPE "long unsigned int"
642
f045b2c9
RS		 643/* Type used for wchar_t, as a string used in a declaration. */
644#define WCHAR_TYPE "short unsigned int"
645
646/* Width of wchar_t in bits. */
647#define WCHAR_TYPE_SIZE 16
648
9e654916
RK		 649/* A C expression for the size in bits of the type `short' on the
650 target machine. If you don't define this, the default is half a
651 word. (If this would be less than one storage unit, it is
652 rounded up to one unit.) */
653#define SHORT_TYPE_SIZE 16
654
655/* A C expression for the size in bits of the type `int' on the
656 target machine. If you don't define this, the default is one
657 word. */
19d2d16f 658#define INT_TYPE_SIZE 32
9e654916
RK		 659
660/* A C expression for the size in bits of the type `long' on the
661 target machine. If you don't define this, the default is one
662 word. */
2f3e5814 663#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
9e654916
RK		 664
665/* A C expression for the size in bits of the type `long long' on the
666 target machine. If you don't define this, the default is two
667 words. */
668#define LONG_LONG_TYPE_SIZE 64
669
9e654916
RK		 670/* A C expression for the size in bits of the type `float' on the
671 target machine. If you don't define this, the default is one
672 word. */
673#define FLOAT_TYPE_SIZE 32
674
675/* A C expression for the size in bits of the type `double' on the
676 target machine. If you don't define this, the default is two
677 words. */
678#define DOUBLE_TYPE_SIZE 64
679
680/* A C expression for the size in bits of the type `long double' on
681 the target machine. If you don't define this, the default is two
682 words. */
6fa3f289 683#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
06f4e019 684
06f4e019
DE		 685/* Define this to set long double type size to use in libgcc2.c, which can
686 not depend on target_flags. */
687#ifdef __LONG_DOUBLE_128__
688#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
689#else
690#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
691#endif
9e654916 692
5b8f5865
DE		 693/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
694#define WIDEST_HARDWARE_FP_SIZE 64
695
f045b2c9
RS		 696/* Width in bits of a pointer.
697 See also the macro `Pmode' defined below. */
cacf1ca8
MM		 698extern unsigned rs6000_pointer_size;
699#define POINTER_SIZE rs6000_pointer_size
f045b2c9
RS		 700
701/* Allocation boundary (in *bits*) for storing arguments in argument list. */
2f3e5814 702#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
f045b2c9
RS		 703
704/* Boundary (in *bits*) on which stack pointer should be aligned. */
cacf1ca8
MM		 705#define STACK_BOUNDARY \
706 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
707 ? 64 : 128)
f045b2c9
RS		 708
709/* Allocation boundary (in *bits*) for the code of a function. */
710#define FUNCTION_BOUNDARY 32
711
712/* No data type wants to be aligned rounder than this. */
0ac081f6
AH		 713#define BIGGEST_ALIGNMENT 128
714
715/* A C expression to compute the alignment for a variables in the
716 local store. TYPE is the data type, and ALIGN is the alignment
717 that the object would ordinarily have. */
718#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
777a3a6a 719 DATA_ALIGNMENT (TYPE, ALIGN)
b73fd26c 720
f045b2c9
RS		 721/* Alignment of field after `int : 0' in a structure. */
722#define EMPTY_FIELD_BOUNDARY 32
723
724/* Every structure's size must be a multiple of this. */
725#define STRUCTURE_SIZE_BOUNDARY 8
726
a3170dc6
AH		 727/* Return 1 if a structure or array containing FIELD should be
728 accessed using `BLKMODE'.
729
730 For the SPE, simd types are V2SI, and gcc can be tempted to put the
731 entire thing in a DI and use subregs to access the internals.
732 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
733 back-end. Because a single GPR can hold a V2SI, but not a DI, the
734 best thing to do is set structs to BLKmode and avoid Severe Tire
de334ef6
AH		 735 Damage.
736
737 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
738 fit into 1, whereas DI still needs two. */
a3170dc6 739#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
de334ef6 740 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
4f011e1e 741 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
a3170dc6 742
43a88a8c 743/* A bit-field declared as `int' forces `int' alignment for the struct. */
f045b2c9
RS		 744#define PCC_BITFIELD_TYPE_MATTERS 1
745
69ef87e2
AH		 746/* Make strings word-aligned so strcpy from constants will be faster.
747 Make vector constants quadword aligned. */
748#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
749 (TREE_CODE (EXP) == STRING_CST \
153fbec8 750 && (STRICT_ALIGNMENT || !optimize_size) \
69ef87e2
AH		 751 && (ALIGN) < BITS_PER_WORD \
752 ? BITS_PER_WORD \
753 : (ALIGN))
f045b2c9 754
0ac081f6 755/* Make arrays of chars word-aligned for the same reasons.
f82f556d
AH		 756 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
757 64 bits. */
b851135c
NF		 758#define DATA_ALIGNMENT(TYPE, ALIGN) \
759 (TREE_CODE (TYPE) == VECTOR_TYPE \
760 ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \
761 || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \
762 ? 64 : 128) \
763 : ((TARGET_E500_DOUBLE \
764 && TREE_CODE (TYPE) == REAL_TYPE \
765 && TYPE_MODE (TYPE) == DFmode) \
766 ? 64 \
767 : (TREE_CODE (TYPE) == ARRAY_TYPE \
768 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
769 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)))
f045b2c9 770
a0ab749a 771/* Nonzero if move instructions will actually fail to work
f045b2c9 772 when given unaligned data. */
fdaff8ba 773#define STRICT_ALIGNMENT 0
e1565e65
DE		 774
775/* Define this macro to be the value 1 if unaligned accesses have a cost
776 many times greater than aligned accesses, for example if they are
777 emulated in a trap handler. */
cacf1ca8
MM		 778/* Altivec vector memory instructions simply ignore the low bits; SPE vector
779 memory instructions trap on unaligned accesses; VSX memory instructions are
780 aligned to 4 or 8 bytes. */
41543739
GK		 781#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
782 (STRICT_ALIGNMENT \
fcce224d 783 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
e41b2a33 784 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \
fcce224d 785 || (MODE) == DImode) \
54ce9cc2 786 && (ALIGN) < 32) \
cacf1ca8
MM		 787 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))
788
f045b2c9
RS		 789\f
790/* Standard register usage. */
791
792/* Number of actual hardware registers.
793 The hardware registers are assigned numbers for the compiler
794 from 0 to just below FIRST_PSEUDO_REGISTER.
795 All registers that the compiler knows about must be given numbers,
796 even those that are not normally considered general registers.
797
798 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
799 an MQ register, a count register, a link register, and 8 condition
07488f32
ZW		 800 register fields, which we view here as separate registers. AltiVec
801 adds 32 vector registers and a VRsave register.
f045b2c9
RS		 802
803 In addition, the difference between the frame and argument pointers is
804 a function of the number of registers saved, so we need to have a
805 register for AP that will later be eliminated in favor of SP or FP.
802a0058 806 This is a normal register, but it is fixed.
f045b2c9 807
802a0058
MM		 808 We also create a pseudo register for float/int conversions, that will
809 really represent the memory location used. It is represented here as
810 a register, in order to work around problems in allocating stack storage
7d5175e1 811 in inline functions.
802a0058 812
7d5175e1
JJ		 813 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
814 pointer, which is eventually eliminated in favor of SP or FP. */
815
816#define FIRST_PSEUDO_REGISTER 114
f045b2c9 817
d6a7951f 818/* This must be included for pre gcc 3.0 glibc compatibility. */
7d5f33bc 819#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
62153b61 820
93c9d1ba 821/* Add 32 dwarf columns for synthetic SPE registers. */
7d5175e1 822#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
c19de7aa 823
93c9d1ba
AM		 824/* The SPE has an additional 32 synthetic registers, with DWARF debug
825 info numbering for these registers starting at 1200. While eh_frame
826 register numbering need not be the same as the debug info numbering,
827 we choose to number these regs for eh_frame at 1200 too. This allows
828 future versions of the rs6000 backend to add hard registers and
829 continue to use the gcc hard register numbering for eh_frame. If the
830 extra SPE registers in eh_frame were numbered starting from the
831 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
832 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
833 avoid invalidating older SPE eh_frame info.
834
835 We must map them here to avoid huge unwinder tables mostly consisting
f676971a 836 of unused space. */
93c9d1ba 837#define DWARF_REG_TO_UNWIND_COLUMN(r) \
7d5175e1 838 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
93c9d1ba 839
ed1cf8ff
GK		 840/* Use standard DWARF numbering for DWARF debugging information. */
841#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
842
93c9d1ba
AM		 843/* Use gcc hard register numbering for eh_frame. */
844#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
41f3a930 845
ed1cf8ff
GK		 846/* Map register numbers held in the call frame info that gcc has
847 collected using DWARF_FRAME_REGNUM to those that should be output in
848 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
849 for .eh_frame, but use the numbers mandated by the various ABIs for
850 .debug_frame. rs6000_emit_prologue has translated any combination of
851 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
852 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
853#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
854 ((FOR_EH) ? (REGNO) \
855 : (REGNO) == CR2_REGNO ? 64 \
856 : DBX_REGISTER_NUMBER (REGNO))
857
f045b2c9
RS		 858/* 1 for registers that have pervasive standard uses
859 and are not available for the register allocator.
860
5dead3e5
DJ		 861 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
862 as a local register; for all other OS's r2 is the TOC pointer.
f045b2c9 863
a127c4e5
RK		 864 cr5 is not supposed to be used.
865
866 On System V implementations, r13 is fixed and not available for use. */
867
f045b2c9 868#define FIXED_REGISTERS \
5dead3e5 869 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
f045b2c9
RS		 870 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
871 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
872 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0ac081f6
AH		 873 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
874 /* AltiVec registers. */ \
875 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
876 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 877 1, 1 \
7d5175e1 878 , 1, 1, 1 \
0ac081f6 879}
f045b2c9
RS		 880
881/* 1 for registers not available across function calls.
882 These must include the FIXED_REGISTERS and also any
883 registers that can be used without being saved.
884 The latter must include the registers where values are returned
885 and the register where structure-value addresses are passed.
886 Aside from that, you can include as many other registers as you like. */
887
888#define CALL_USED_REGISTERS \
a127c4e5 889 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
f045b2c9
RS		 890 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
891 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
892 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0ac081f6
AH		 893 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
894 /* AltiVec registers. */ \
895 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
896 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 897 1, 1 \
7d5175e1 898 , 1, 1, 1 \
0ac081f6
AH		 899}
900
289e96b2
AH		 901/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
902 the entire set of `FIXED_REGISTERS' be included.
903 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
904 This macro is optional. If not specified, it defaults to the value
905 of `CALL_USED_REGISTERS'. */
f676971a 906
289e96b2
AH		 907#define CALL_REALLY_USED_REGISTERS \
908 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
909 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
910 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
911 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
912 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
913 /* AltiVec registers. */ \
914 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
915 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 916 0, 0 \
7d5175e1 917 , 0, 0, 0 \
289e96b2 918}
f045b2c9 919
28bcfd4d 920#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
9ebbca7d 921
d62294f5
FJ		 922#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
923#define FIRST_SAVED_FP_REGNO (14+32)
924#define FIRST_SAVED_GP_REGNO 13
925
f045b2c9
RS		 926/* List the order in which to allocate registers. Each register must be
927 listed once, even those in FIXED_REGISTERS.
928
929 We allocate in the following order:
930 fp0 (not saved or used for anything)
931 fp13 - fp2 (not saved; incoming fp arg registers)
932 fp1 (not saved; return value)
9390387d 933 fp31 - fp14 (saved; order given to save least number)
5accd822
DE		 934 cr7, cr6 (not saved or special)
935 cr1 (not saved, but used for FP operations)
f045b2c9 936 cr0 (not saved, but used for arithmetic operations)
5accd822 937 cr4, cr3, cr2 (saved)
9390387d 938 r0 (not saved; cannot be base reg)
f045b2c9
RS		 939 r9 (not saved; best for TImode)
940 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
9390387d 941 r3 (not saved; return value register)
f045b2c9
RS		 942 r31 - r13 (saved; order given to save least number)
943 r12 (not saved; if used for DImode or DFmode would use r13)
944 mq (not saved; best to use it if we can)
945 ctr (not saved; when we have the choice ctr is better)
946 lr (saved)
9390387d
AM		 947 cr5, r1, r2, ap, xer (fixed)
948 v0 - v1 (not saved or used for anything)
949 v13 - v3 (not saved; incoming vector arg registers)
950 v2 (not saved; incoming vector arg reg; return value)
951 v19 - v14 (not saved or used for anything)
952 v31 - v20 (saved; order given to save least number)
953 vrsave, vscr (fixed)
a3170dc6 954 spe_acc, spefscr (fixed)
7d5175e1 955 sfp (fixed)
0ac081f6 956*/
f676971a 957
6b13641d
DJ		 958#if FIXED_R2 == 1
959#define MAYBE_R2_AVAILABLE
960#define MAYBE_R2_FIXED 2,
961#else
962#define MAYBE_R2_AVAILABLE 2,
963#define MAYBE_R2_FIXED
964#endif
f045b2c9 965
9390387d
AM		 966#define REG_ALLOC_ORDER \
967 {32, \
968 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
969 33, \
970 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
971 50, 49, 48, 47, 46, \
972 75, 74, 69, 68, 72, 71, 70, \
973 0, MAYBE_R2_AVAILABLE \
974 9, 11, 10, 8, 7, 6, 5, 4, \
975 3, \
976 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
977 18, 17, 16, 15, 14, 13, 12, \
978 64, 66, 65, \
979 73, 1, MAYBE_R2_FIXED 67, 76, \
980 /* AltiVec registers. */ \
981 77, 78, \
982 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
983 79, \
984 96, 95, 94, 93, 92, 91, \
985 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
986 109, 110, \
7d5175e1 987 111, 112, 113 \
0ac081f6 988}
f045b2c9
RS		 989
990/* True if register is floating-point. */
991#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
992
993/* True if register is a condition register. */
1de43f85 994#define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
f045b2c9 995
815cdc52 996/* True if register is a condition register, but not cr0. */
1de43f85 997#define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
815cdc52 998
f045b2c9 999/* True if register is an integer register. */
7d5175e1
JJ		 1000#define INT_REGNO_P(N) \
1001 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
f045b2c9 1002
a3170dc6
AH		 1003/* SPE SIMD registers are just the GPRs. */
1004#define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1005
96038623
DE		 1006/* PAIRED SIMD registers are just the FPRs. */
1007#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1008
0d86f538 1009/* True if register is the XER register. */
9ebbca7d 1010#define XER_REGNO_P(N) ((N) == XER_REGNO)
802a0058 1011
0ac081f6
AH		 1012/* True if register is an AltiVec register. */
1013#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1014
cacf1ca8
MM		 1015/* True if register is a VSX register. */
1016#define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1017
1018/* Alternate name for any vector register supporting floating point, no matter
1019 which instruction set(s) are available. */
1020#define VFLOAT_REGNO_P(N) \
1021 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1022
1023/* Alternate name for any vector register supporting integer, no matter which
1024 instruction set(s) are available. */
1025#define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1026
1027/* Alternate name for any vector register supporting logical operations, no
1028 matter which instruction set(s) are available. */
1029#define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)
1030
f045b2c9 1031/* Return number of consecutive hard regs needed starting at reg REGNO
d8ecbcdb
AH		 1032 to hold something of mode MODE. */
1033
cacf1ca8 1034#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
0e67400a
FJ		 1035
1036#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1037 ((TARGET_32BIT && TARGET_POWERPC64 \
2e6c9641 1038 && (GET_MODE_SIZE (MODE) > 4) \
0e67400a 1039 && INT_REGNO_P (REGNO)) ? 1 : 0)
f045b2c9 1040
cacf1ca8
MM		 1041#define VSX_VECTOR_MODE(MODE) \
1042 ((MODE) == V4SFmode \
1043 || (MODE) == V2DFmode) \
1044
1045#define VSX_SCALAR_MODE(MODE) \
1046 ((MODE) == DFmode)
1047
1048#define VSX_MODE(MODE) \
1049 (VSX_VECTOR_MODE (MODE) \
1050 || VSX_SCALAR_MODE (MODE))
1051
1052#define VSX_MOVE_MODE(MODE) \
1053 (VSX_VECTOR_MODE (MODE) \
1054 || VSX_SCALAR_MODE (MODE) \
1055 || ALTIVEC_VECTOR_MODE (MODE) \
1056 || (MODE) == TImode)
1057
0ac081f6 1058#define ALTIVEC_VECTOR_MODE(MODE) \
cb2a532e
AH		 1059 ((MODE) == V16QImode \
1060 || (MODE) == V8HImode \
1061 || (MODE) == V4SFmode \
6e1f54e2 1062 || (MODE) == V4SImode)
0ac081f6 1063
a3170dc6
AH		 1064#define SPE_VECTOR_MODE(MODE) \
1065 ((MODE) == V4HImode \
1066 || (MODE) == V2SFmode \
00a892b8 1067 || (MODE) == V1DImode \
a3170dc6
AH		 1068 || (MODE) == V2SImode)
1069
96038623
DE		 1070#define PAIRED_VECTOR_MODE(MODE) \
1071 ((MODE) == V2SFmode)
1072
cacf1ca8
MM		 1073#define UNITS_PER_SIMD_WORD(MODE) \
1074 (TARGET_VSX ? UNITS_PER_VSX_WORD \
1075 : (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
1076 : (TARGET_SPE ? UNITS_PER_SPE_WORD \
1077 : (TARGET_PAIRED_FLOAT ? UNITS_PER_PAIRED_WORD \
1078 : UNITS_PER_WORD))))
0bf43309 1079
0d1fbc8c
AH		 1080/* Value is TRUE if hard register REGNO can hold a value of
1081 machine-mode MODE. */
1082#define HARD_REGNO_MODE_OK(REGNO, MODE) \
1083 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
f045b2c9
RS		 1084
1085/* Value is 1 if it is a good idea to tie two pseudo registers
1086 when one has mode MODE1 and one has mode MODE2.
1087 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1088 for any hard reg, then this must be 0 for correct output. */
1089#define MODES_TIEABLE_P(MODE1, MODE2) \
ebb109ad
BE		 1090 (SCALAR_FLOAT_MODE_P (MODE1) \
1091 ? SCALAR_FLOAT_MODE_P (MODE2) \
1092 : SCALAR_FLOAT_MODE_P (MODE2) \
1093 ? SCALAR_FLOAT_MODE_P (MODE1) \
f045b2c9
RS		 1094 : GET_MODE_CLASS (MODE1) == MODE_CC \
1095 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1096 : GET_MODE_CLASS (MODE2) == MODE_CC \
1097 ? GET_MODE_CLASS (MODE1) == MODE_CC \
4dcc01f3
AH		 1098 : SPE_VECTOR_MODE (MODE1) \
1099 ? SPE_VECTOR_MODE (MODE2) \
1100 : SPE_VECTOR_MODE (MODE2) \
1101 ? SPE_VECTOR_MODE (MODE1) \
0ac081f6
AH		 1102 : ALTIVEC_VECTOR_MODE (MODE1) \
1103 ? ALTIVEC_VECTOR_MODE (MODE2) \
1104 : ALTIVEC_VECTOR_MODE (MODE2) \
1105 ? ALTIVEC_VECTOR_MODE (MODE1) \
cacf1ca8
MM		 1106 : VSX_VECTOR_MODE (MODE1) \
1107 ? VSX_VECTOR_MODE (MODE2) \
1108 : VSX_VECTOR_MODE (MODE2) \
1109 ? VSX_VECTOR_MODE (MODE1) \
f045b2c9
RS		 1110 : 1)
1111
c8ae788f
SB		 1112/* Post-reload, we can't use any new AltiVec registers, as we already
1113 emitted the vrsave mask. */
1114
1115#define HARD_REGNO_RENAME_OK(SRC, DST) \
6fb5fa3c 1116 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
c8ae788f 1117
f045b2c9 1118/* A C expression returning the cost of moving data from a register of class
34bb030a 1119 CLASS1 to one of CLASS2. */
f045b2c9 1120
34bb030a 1121#define REGISTER_MOVE_COST rs6000_register_move_cost
f045b2c9 1122
34bb030a
DE		 1123/* A C expressions returning the cost of moving data of MODE from a register to
1124 or from memory. */
f045b2c9 1125
34bb030a 1126#define MEMORY_MOVE_COST rs6000_memory_move_cost
f045b2c9
RS		 1127
1128/* Specify the cost of a branch insn; roughly the number of extra insns that
1129 should be added to avoid a branch.
1130
ef457bda 1131 Set this to 3 on the RS/6000 since that is roughly the average cost of an
f045b2c9
RS		 1132 unscheduled conditional branch. */
1133
3a4fd356 1134#define BRANCH_COST(speed_p, predictable_p) 3
f045b2c9 1135
85e50b6b 1136/* Override BRANCH_COST heuristic which empirically produces worse
b8610a53 1137 performance for removing short circuiting from the logical ops. */
85e50b6b 1138
b8610a53 1139#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
a3170dc6 1140
52ff33d0
NF		 1141/* A fixed register used at epilogue generation to address SPE registers
1142 with negative offsets. The 64-bit load/store instructions on the SPE
1143 only take positive offsets (and small ones at that), so we need to
1144 reserve a register for consing up negative offsets. */
a3170dc6 1145
52ff33d0 1146#define FIXED_SCRATCH 0
a3170dc6 1147
2aa4498c
AH		 1148/* Define this macro to change register usage conditional on target
1149 flags. */
f85f4585 1150
2aa4498c 1151#define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
6febd581 1152
f045b2c9
RS		 1153/* Specify the registers used for certain standard purposes.
1154 The values of these macros are register numbers. */
1155
1156/* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1157/* #define PC_REGNUM */
1158
1159/* Register to use for pushing function arguments. */
1160#define STACK_POINTER_REGNUM 1
1161
1162/* Base register for access to local variables of the function. */
7d5175e1
JJ		 1163#define HARD_FRAME_POINTER_REGNUM 31
1164
1165/* Base register for access to local variables of the function. */
1166#define FRAME_POINTER_REGNUM 113
f045b2c9 1167
f045b2c9
RS		 1168/* Base register for access to arguments of the function. */
1169#define ARG_POINTER_REGNUM 67
1170
1171/* Place to put static chain when calling a function that requires it. */
1172#define STATIC_CHAIN_REGNUM 11
1173
f045b2c9
RS		 1174\f
1175/* Define the classes of registers for register constraints in the
1176 machine description. Also define ranges of constants.
1177
1178 One of the classes must always be named ALL_REGS and include all hard regs.
1179 If there is more than one class, another class must be named NO_REGS
1180 and contain no registers.
1181
1182 The name GENERAL_REGS must be the name of a class (or an alias for
1183 another name such as ALL_REGS). This is the class of registers
1184 that is allowed by "g" or "r" in a register constraint.
1185 Also, registers outside this class are allocated only when
1186 instructions express preferences for them.
1187
1188 The classes must be numbered in nondecreasing order; that is,
1189 a larger-numbered class must never be contained completely
1190 in a smaller-numbered class.
1191
1192 For any two classes, it is very desirable that there be another
1193 class that represents their union. */
c81bebd7 1194
cacf1ca8
MM		 1195/* The RS/6000 has three types of registers, fixed-point, floating-point, and
1196 condition registers, plus three special registers, MQ, CTR, and the link
1197 register. AltiVec adds a vector register class. VSX registers overlap the
1198 FPR registers and the Altivec registers.
f045b2c9
RS		 1199
1200 However, r0 is special in that it cannot be used as a base register.
1201 So make a class for registers valid as base registers.
1202
1203 Also, cr0 is the only condition code register that can be used in
0d86f538 1204 arithmetic insns, so make a separate class for it. */
f045b2c9 1205
ebedb4dd
MM		 1206enum reg_class
1207{
1208 NO_REGS,
ebedb4dd
MM		 1209 BASE_REGS,
1210 GENERAL_REGS,
1211 FLOAT_REGS,
0ac081f6 1212 ALTIVEC_REGS,
8beb65e3 1213 VSX_REGS,
0ac081f6 1214 VRSAVE_REGS,
5f004351 1215 VSCR_REGS,
a3170dc6
AH		 1216 SPE_ACC_REGS,
1217 SPEFSCR_REGS,
ebedb4dd
MM		 1218 NON_SPECIAL_REGS,
1219 MQ_REGS,
1220 LINK_REGS,
1221 CTR_REGS,
1222 LINK_OR_CTR_REGS,
1223 SPECIAL_REGS,
1224 SPEC_OR_GEN_REGS,
1225 CR0_REGS,
ebedb4dd
MM		 1226 CR_REGS,
1227 NON_FLOAT_REGS,
9ebbca7d 1228 XER_REGS,
ebedb4dd
MM		 1229 ALL_REGS,
1230 LIM_REG_CLASSES
1231};
f045b2c9
RS		 1232
1233#define N_REG_CLASSES (int) LIM_REG_CLASSES
1234
82e41834 1235/* Give names of register classes as strings for dump file. */
f045b2c9 1236
ebedb4dd
MM		 1237#define REG_CLASS_NAMES \
1238{ \
1239 "NO_REGS", \
ebedb4dd
MM		 1240 "BASE_REGS", \
1241 "GENERAL_REGS", \
1242 "FLOAT_REGS", \
0ac081f6 1243 "ALTIVEC_REGS", \
8beb65e3 1244 "VSX_REGS", \
0ac081f6 1245 "VRSAVE_REGS", \
5f004351 1246 "VSCR_REGS", \
a3170dc6
AH		 1247 "SPE_ACC_REGS", \
1248 "SPEFSCR_REGS", \
ebedb4dd
MM		 1249 "NON_SPECIAL_REGS", \
1250 "MQ_REGS", \
1251 "LINK_REGS", \
1252 "CTR_REGS", \
1253 "LINK_OR_CTR_REGS", \
1254 "SPECIAL_REGS", \
1255 "SPEC_OR_GEN_REGS", \
1256 "CR0_REGS", \
ebedb4dd
MM		 1257 "CR_REGS", \
1258 "NON_FLOAT_REGS", \
9ebbca7d 1259 "XER_REGS", \
ebedb4dd
MM		 1260 "ALL_REGS" \
1261}
f045b2c9
RS		 1262
1263/* Define which registers fit in which classes.
1264 This is an initializer for a vector of HARD_REG_SET
1265 of length N_REG_CLASSES. */
1266
0ac081f6
AH		 1267#define REG_CLASS_CONTENTS \
1268{ \
1269 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
7d5175e1
JJ		 1270 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1271 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
0ac081f6 1272 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
089a05b8 1273 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
8beb65e3 1274 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \
089a05b8 1275 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
5f004351 1276 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
a3170dc6
AH		 1277 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1278 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
7d5175e1 1279 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
0ac081f6
AH		 1280 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1281 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1282 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1283 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
a004eb82 1284 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
7d5175e1 1285 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
0ac081f6
AH		 1286 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1287 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
e3604432 1288 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
089a05b8 1289 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
7d5175e1 1290 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
ebedb4dd 1291}
f045b2c9 1292
058e97ec
VM		 1293/* The following macro defines cover classes for Integrated Register
1294 Allocator. Cover classes is a set of non-intersected register
1295 classes covering all hard registers used for register allocation
1296 purpose. Any move between two registers of a cover class should be
1297 cheaper than load or store of the registers. The macro value is
1298 array of register classes with LIM_REG_CLASSES used as the end
a72c65c7 1299 marker.
058e97ec 1300
a72c65c7
MM		 1301 We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to
1302 account for the Altivec and Floating registers being subsets of the VSX
1303 register set. */
1304
1305#define IRA_COVER_CLASSES_PRE_VSX \
058e97ec 1306{ \
a72c65c7
MM		 1307 GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */ \
1308 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
1309 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
1310 CR_REGS, XER_REGS, LIM_REG_CLASSES \
1311}
1312
1313#define IRA_COVER_CLASSES_VSX \
1314{ \
1315 GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS, \
1316 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
058e97ec
VM		 1317 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
1318 CR_REGS, XER_REGS, LIM_REG_CLASSES \
1319}
1320
f045b2c9
RS		 1321/* The same information, inverted:
1322 Return the class number of the smallest class containing
1323 reg number REGNO. This could be a conditional expression
1324 or could index an array. */
1325
cacf1ca8
MM		 1326extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1327
1328#if ENABLE_CHECKING
1329#define REGNO_REG_CLASS(REGNO) \
1330 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \
1331 rs6000_regno_regclass[(REGNO)])
1332
1333#else
1334#define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)]
1335#endif
1336
a72c65c7
MM		 1337/* Register classes for various constraints that are based on the target
1338 switches. */
1339enum r6000_reg_class_enum {
1340 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1341 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1342 RS6000_CONSTRAINT_v, /* Altivec registers */
1343 RS6000_CONSTRAINT_wa, /* Any VSX register */
1344 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1345 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1346 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1347 RS6000_CONSTRAINT_MAX
1348};
1349
1350extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
f045b2c9
RS		 1351
1352/* The class value for index registers, and the one for base regs. */
1353#define INDEX_REG_CLASS GENERAL_REGS
1354#define BASE_REG_CLASS BASE_REGS
1355
cacf1ca8
MM		 1356/* Return whether a given register class can hold VSX objects. */
1357#define VSX_REG_CLASS_P(CLASS) \
1358 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1359
f045b2c9
RS		 1360/* Given an rtx X being reloaded into a reg required to be
1361 in class CLASS, return the class of reg to actually use.
1362 In general this is just CLASS; but on some machines
c81bebd7 1363 in some cases it is preferable to use a more restrictive class.
f045b2c9
RS		 1364
1365 On the RS/6000, we have to return NO_REGS when we want to reload a
f676971a 1366 floating-point CONST_DOUBLE to force it to be copied to memory.
1e66d555
GK		 1367
1368 We also don't want to reload integer values into floating-point
1369 registers if we can at all help it. In fact, this can
37409796 1370 cause reload to die, if it tries to generate a reload of CTR
1e66d555
GK		 1371 into a FP register and discovers it doesn't have the memory location
1372 required.
1373
1374 ??? Would it be a good idea to have reload do the converse, that is
1375 try to reload floating modes into FP registers if possible?
1376 */
f045b2c9 1377
802a0058 1378#define PREFERRED_RELOAD_CLASS(X,CLASS) \
8beb65e3 1379 rs6000_preferred_reload_class_ptr (X, CLASS)
c81bebd7 1380
f045b2c9
RS		 1381/* Return the register class of a scratch register needed to copy IN into
1382 or out of a register in CLASS in MODE. If it can be done directly,
1383 NO_REGS is returned. */
1384
1385#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
8beb65e3 1386 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
f045b2c9 1387
0ac081f6 1388/* If we are copying between FP or AltiVec registers and anything
44cd321e
PS		 1389 else, we need a memory location. The exception is when we are
1390 targeting ppc64 and the move to/from fpr to gpr instructions
1391 are available.*/
1392
1393#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
8beb65e3 1394 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE)
7ea555a4 1395
e41b2a33
PB		 1396/* For cpus that cannot load/store SDmode values from the 64-bit
1397 FP registers without using a full 64-bit load/store, we need
1398 to allocate a full 64-bit stack slot for them. */
1399
1400#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1401 rs6000_secondary_memory_needed_rtx (MODE)
1402
f045b2c9
RS		 1403/* Return the maximum number of consecutive registers
1404 needed to represent mode MODE in a register of class CLASS.
1405
cacf1ca8
MM		 1406 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1407 a single reg is enough for two words, unless we have VSX, where the FP
1408 registers can hold 128 bits. */
1409#define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
580d3230 1410
ca0e79d9
AM		 1411/* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1412
1413#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
8beb65e3 1414 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS)
02188693 1415
f045b2c9
RS		 1416/* Stack layout; function entry, exit and calling. */
1417
6b67933e
RK		 1418/* Enumeration to give which calling sequence to use. */
1419enum rs6000_abi {
1420 ABI_NONE,
1421 ABI_AIX, /* IBM's AIX */
b6c9286a 1422 ABI_V4, /* System V.4/eabi */
ee890fe2 1423 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
6b67933e
RK		 1424};
1425
b6c9286a
MM		 1426extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1427
f045b2c9
RS		 1428/* Define this if pushing a word on the stack
1429 makes the stack pointer a smaller address. */
1430#define STACK_GROWS_DOWNWARD
1431
327e5343
FJ		 1432/* Offsets recorded in opcodes are a multiple of this alignment factor. */
1433#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1434
a4d05547 1435/* Define this to nonzero if the nominal address of the stack frame
f045b2c9
RS		 1436 is at the high-address end of the local variables;
1437 that is, each additional local variable allocated
1438 goes at a more negative offset in the frame.
1439
1440 On the RS/6000, we grow upwards, from the area after the outgoing
1441 arguments. */
3aebbe5f 1442#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
f045b2c9 1443
4697a36c 1444/* Size of the outgoing register save area */
9ebbca7d 1445#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
ee890fe2 1446 || DEFAULT_ABI == ABI_DARWIN) \
9ebbca7d
GK		 1447 ? (TARGET_64BIT ? 64 : 32) \
1448 : 0)
4697a36c
MM		 1449
1450/* Size of the fixed area on the stack */
9ebbca7d 1451#define RS6000_SAVE_AREA \
50d440bc 1452 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
9ebbca7d 1453 << (TARGET_64BIT ? 1 : 0))
4697a36c 1454
97f6e72f
DE		 1455/* MEM representing address to save the TOC register */
1456#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1457 plus_constant (stack_pointer_rtx, \
1458 (TARGET_32BIT ? 20 : 40)))
b6c9286a 1459
4697a36c 1460/* Align an address */
ed33106f 1461#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
4697a36c 1462
f045b2c9
RS		 1463/* Offset within stack frame to start allocating local variables at.
1464 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1465 first local allocated. Otherwise, it is the offset to the BEGINNING
c81bebd7 1466 of the first local allocated.
f045b2c9
RS		 1467
1468 On the RS/6000, the frame pointer is the same as the stack pointer,
1469 except for dynamic allocations. So we start after the fixed area and
1470 outgoing parameter area. */
1471
802a0058 1472#define STARTING_FRAME_OFFSET \
7d5175e1
JJ		 1473 (FRAME_GROWS_DOWNWARD \
1474 ? 0 \
cacf1ca8
MM		 1475 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1476 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
7d5175e1 1477 + RS6000_SAVE_AREA))
802a0058
MM		 1478
1479/* Offset from the stack pointer register to an item dynamically
1480 allocated on the stack, e.g., by `alloca'.
1481
1482 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1483 length of the outgoing arguments. The default is correct for most
1484 machines. See `function.c' for details. */
1485#define STACK_DYNAMIC_OFFSET(FUNDECL) \
cacf1ca8
MM		 1486 (RS6000_ALIGN (crtl->outgoing_args_size, \
1487 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
802a0058 1488 + (STACK_POINTER_OFFSET))
f045b2c9
RS		 1489
1490/* If we generate an insn to push BYTES bytes,
1491 this says how many the stack pointer really advances by.
1492 On RS/6000, don't define this because there are no push insns. */
1493/* #define PUSH_ROUNDING(BYTES) */
1494
1495/* Offset of first parameter from the argument pointer register value.
1496 On the RS/6000, we define the argument pointer to the start of the fixed
1497 area. */
4697a36c 1498#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
f045b2c9 1499
62153b61
JM		 1500/* Offset from the argument pointer register value to the top of
1501 stack. This is different from FIRST_PARM_OFFSET because of the
1502 register save area. */
1503#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1504
f045b2c9
RS		 1505/* Define this if stack space is still allocated for a parameter passed
1506 in a register. The value is the number of bytes allocated to this
1507 area. */
4697a36c 1508#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
f045b2c9
RS		 1509
1510/* Define this if the above stack space is to be considered part of the
1511 space allocated by the caller. */
81464b2c 1512#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
f045b2c9
RS		 1513
1514/* This is the difference between the logical top of stack and the actual sp.
1515
82e41834 1516 For the RS/6000, sp points past the fixed area. */
4697a36c 1517#define STACK_POINTER_OFFSET RS6000_SAVE_AREA
f045b2c9
RS		 1518
1519/* Define this if the maximum size of all the outgoing args is to be
1520 accumulated and pushed during the prologue. The amount can be
38173d38 1521 found in the variable crtl->outgoing_args_size. */
f73ad30e 1522#define ACCUMULATE_OUTGOING_ARGS 1
f045b2c9
RS		 1523
1524/* Value is the number of bytes of arguments automatically
1525 popped when returning from a subroutine call.
8b109b37 1526 FUNDECL is the declaration node of the function (as a tree),
f045b2c9
RS		 1527 FUNTYPE is the data type of the function (as a tree),
1528 or for a library call it is an identifier node for the subroutine name.
1529 SIZE is the number of bytes of arguments passed on the stack. */
1530
8b109b37 1531#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
f045b2c9 1532
f045b2c9
RS		 1533/* Define how to find the value returned by a library function
1534 assuming the value has mode MODE. */
1535
ded9bf77 1536#define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
f045b2c9 1537
6fa3f289
ZW		 1538/* DRAFT_V4_STRUCT_RET defaults off. */
1539#define DRAFT_V4_STRUCT_RET 0
f607bc57 1540
bd5bd7ac 1541/* Let TARGET_RETURN_IN_MEMORY control what happens. */
f607bc57 1542#define DEFAULT_PCC_STRUCT_RETURN 0
f045b2c9 1543
a260abc9 1544/* Mode of stack savearea.
dfdfa60f
DE		 1545 FUNCTION is VOIDmode because calling convention maintains SP.
1546 BLOCK needs Pmode for SP.
a260abc9
DE		 1547 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1548#define STACK_SAVEAREA_MODE(LEVEL) \
dfdfa60f
DE		 1549 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1550 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
a260abc9 1551
4697a36c
MM		 1552/* Minimum and maximum general purpose registers used to hold arguments. */
1553#define GP_ARG_MIN_REG 3
1554#define GP_ARG_MAX_REG 10
1555#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1556
1557/* Minimum and maximum floating point registers used to hold arguments. */
1558#define FP_ARG_MIN_REG 33
7509c759
MM		 1559#define FP_ARG_AIX_MAX_REG 45
1560#define FP_ARG_V4_MAX_REG 40
9ebbca7d 1561#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
ee890fe2 1562 || DEFAULT_ABI == ABI_DARWIN) \
9ebbca7d 1563 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
4697a36c
MM		 1564#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1565
0ac081f6
AH		 1566/* Minimum and maximum AltiVec registers used to hold arguments. */
1567#define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1568#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1569#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1570
4697a36c
MM		 1571/* Return registers */
1572#define GP_ARG_RETURN GP_ARG_MIN_REG
1573#define FP_ARG_RETURN FP_ARG_MIN_REG
0ac081f6 1574#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
4697a36c 1575
7509c759 1576/* Flags for the call/call_value rtl operations set up by function_arg */
6a4cee5f 1577#define CALL_NORMAL 0x00000000 /* no special processing */
9ebbca7d 1578/* Bits in 0x00000001 are unused. */
6a4cee5f
MM		 1579#define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1580#define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1581#define CALL_LONG 0x00000008 /* always call indirect */
b9599e46 1582#define CALL_LIBCALL 0x00000010 /* libcall */
7509c759 1583
f57fe068
AM		 1584/* We don't have prologue and epilogue functions to save/restore
1585 everything for most ABIs. */
1586#define WORLD_SAVE_P(INFO) 0
1587
f045b2c9
RS		 1588/* 1 if N is a possible register number for a function value
1589 as seen by the caller.
1590
0ac081f6 1591 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
e87a88d3
AM		 1592#define FUNCTION_VALUE_REGNO_P(N) \
1593 ((N) == GP_ARG_RETURN \
b2df7d08 1594 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
44688022 1595 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
f045b2c9
RS		 1596
1597/* 1 if N is a possible register number for function argument passing.
0ac081f6
AH		 1598 On RS/6000, these are r3-r10 and fp1-fp13.
1599 On AltiVec, v2 - v13 are used for passing vectors. */
4697a36c 1600#define FUNCTION_ARG_REGNO_P(N) \
e87a88d3
AM		 1601 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1602 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
44688022 1603 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
e87a88d3 1604 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
b2df7d08 1605 && TARGET_HARD_FLOAT && TARGET_FPRS))
f045b2c9
RS		 1606\f
1607/* Define a data type for recording info about an argument list
1608 during the scan of that argument list. This data type should
1609 hold all necessary information about the function itself
1610 and about the args processed so far, enough to enable macros
1611 such as FUNCTION_ARG to determine where the next arg should go.
1612
1613 On the RS/6000, this is a structure. The first element is the number of
1614 total argument words, the second is used to store the next
1615 floating-point register number, and the third says how many more args we
4697a36c
MM		 1616 have prototype types for.
1617
4cc833b7 1618 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
07488f32 1619 the next available GP register, `fregno' is the next available FP
4cc833b7
RH		 1620 register, and `words' is the number of words used on the stack.
1621
bd227acc 1622 The varargs/stdarg support requires that this structure's size
4cc833b7 1623 be a multiple of sizeof(int). */
4697a36c
MM		 1624
1625typedef struct rs6000_args
1626{
4cc833b7 1627 int words; /* # words used for passing GP registers */
6a4cee5f 1628 int fregno; /* next available FP register */
0ac081f6 1629 int vregno; /* next available AltiVec register */
6a4cee5f 1630 int nargs_prototype; /* # args left in the current prototype */
6a4cee5f 1631 int prototype; /* Whether a prototype was defined */
a6c9bed4 1632 int stdarg; /* Whether function is a stdarg function. */
6a4cee5f 1633 int call_cookie; /* Do special things for this call */
4cc833b7 1634 int sysv_gregno; /* next available GP register */
0b5383eb
DJ		 1635 int intoffset; /* running offset in struct (darwin64) */
1636 int use_stack; /* any part of struct on stack (darwin64) */
1637 int named; /* false for varargs params */
4697a36c 1638} CUMULATIVE_ARGS;
f045b2c9 1639
f045b2c9
RS		 1640/* Initialize a variable CUM of type CUMULATIVE_ARGS
1641 for a call to a function whose data type is FNTYPE.
1642 For a library call, FNTYPE is 0. */
1643
0f6937fe
AM		 1644#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1645 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
f045b2c9
RS		 1646
1647/* Similar, but when scanning the definition of a procedure. We always
1648 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1649
0f6937fe
AM		 1650#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1651 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
b9599e46
FS		 1652
1653/* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1654
1655#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
0f6937fe 1656 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
f045b2c9
RS		 1657
1658/* Update the data in CUM to advance over an argument
1659 of mode MODE and data type TYPE.
1660 (TYPE is null for libcalls where that information may not be available.) */
1661
1662#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
594a51fe 1663 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
f045b2c9 1664
f045b2c9
RS		 1665/* Determine where to put an argument to a function.
1666 Value is zero to push the argument on the stack,
1667 or a hard register in which to store the argument.
1668
1669 MODE is the argument's machine mode.
1670 TYPE is the data type of the argument (as a tree).
1671 This is null for libcalls where that information may
1672 not be available.
1673 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1674 the preceding args and about the function being called.
1675 NAMED is nonzero if this argument is a named parameter
1676 (otherwise it is an extra parameter matching an ellipsis).
1677
1678 On RS/6000 the first eight words of non-FP are normally in registers
1679 and the rest are pushed. The first 13 FP args are in registers.
1680
1681 If this is floating-point and no prototype is specified, we use
4d6697ca
RK		 1682 both an FP and integer register (or possibly FP reg and stack). Library
1683 functions (when TYPE is zero) always have the proper types for args,
1684 so we can pass the FP value just in one register. emit_library_function
1685 doesn't support EXPR_LIST anyway. */
f045b2c9 1686
4697a36c
MM		 1687#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1688 function_arg (&CUM, MODE, TYPE, NAMED)
f045b2c9 1689
c229cba9
DE		 1690/* If defined, a C expression which determines whether, and in which
1691 direction, to pad out an argument with extra space. The value
1692 should be of type `enum direction': either `upward' to pad above
1693 the argument, `downward' to pad below, or `none' to inhibit
1694 padding. */
1695
9ebbca7d 1696#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
c229cba9 1697
b6c9286a 1698/* If defined, a C expression that gives the alignment boundary, in bits,
c81bebd7 1699 of an argument with the specified mode and type. If it is not defined,
b6c9286a
MM		 1700 PARM_BOUNDARY is used for all arguments. */
1701
1702#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1703 function_arg_boundary (MODE, TYPE)
1704
6e985040
AM		 1705#define PAD_VARARGS_DOWN \
1706 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
2a55fd42 1707
f045b2c9 1708/* Output assembler code to FILE to increment profiler label # LABELNO
58a39e45 1709 for profiling a function entry. */
f045b2c9
RS		 1710
1711#define FUNCTION_PROFILER(FILE, LABELNO) \
58a39e45 1712 output_function_profiler ((FILE), (LABELNO));
f045b2c9
RS		 1713
1714/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1715 the stack pointer does not matter. No definition is equivalent to
1716 always zero.
1717
a0ab749a 1718 On the RS/6000, this is nonzero because we can restore the stack from
f045b2c9
RS		 1719 its backpointer, which we maintain. */
1720#define EXIT_IGNORE_STACK 1
1721
a701949a
FS		 1722/* Define this macro as a C expression that is nonzero for registers
1723 that are used by the epilogue or the return' pattern. The stack
1724 and frame pointer registers are already be assumed to be used as
1725 needed. */
1726
83720594 1727#define EPILOGUE_USES(REGNO) \
1de43f85 1728 ((reload_completed && (REGNO) == LR_REGNO) \
b1765bde 1729 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
cacf1ca8 1730 || (crtl->calls_eh_return \
3553b09d 1731 && TARGET_AIX \
ff3867ae 1732 && (REGNO) == 2))
2bfcf297 1733
f045b2c9 1734\f
f045b2c9
RS		 1735/* Length in units of the trampoline for entering a nested function. */
1736
b6c9286a 1737#define TRAMPOLINE_SIZE rs6000_trampoline_size ()
f045b2c9 1738\f
f33985c6
MS		 1739/* Definitions for __builtin_return_address and __builtin_frame_address.
1740 __builtin_return_address (0) should give link register (65), enable
82e41834 1741 this. */
f33985c6
MS		 1742/* This should be uncommented, so that the link register is used, but
1743 currently this would result in unmatched insns and spilling fixed
1744 registers so we'll leave it for another day. When these problems are
1745 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1746 (mrs) */
1747/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
f09d4c33 1748
b6c9286a
MM		 1749/* Number of bytes into the frame return addresses can be found. See
1750 rs6000_stack_info in rs6000.c for more information on how the different
1751 abi's store the return address. */
1752#define RETURN_ADDRESS_OFFSET \
1753 ((DEFAULT_ABI == ABI_AIX \
50d440bc 1754 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
3b370352 1755 (DEFAULT_ABI == ABI_V4) ? 4 : \
c4636dd1 1756 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
f09d4c33 1757
f33985c6
MS		 1758/* The current return address is in link register (65). The return address
1759 of anything farther back is accessed normally at an offset of 8 from the
1760 frame pointer. */
71f123ca
FS		 1761#define RETURN_ADDR_RTX(COUNT, FRAME) \
1762 (rs6000_return_addr (COUNT, FRAME))
1763
f33985c6 1764\f
f045b2c9
RS		 1765/* Definitions for register eliminations.
1766
1767 We have two registers that can be eliminated on the RS/6000. First, the
1768 frame pointer register can often be eliminated in favor of the stack
1769 pointer register. Secondly, the argument pointer register can always be
642a35f1
JW		 1770 eliminated; it is replaced with either the stack or frame pointer.
1771
1772 In addition, we use the elimination mechanism to see if r30 is needed
1773 Initially we assume that it isn't. If it is, we spill it. This is done
1774 by making it an eliminable register. We replace it with itself so that
1775 if it isn't needed, then existing uses won't be modified. */
f045b2c9
RS		 1776
1777/* This is an array of structures. Each structure initializes one pair
1778 of eliminable registers. The "from" register number is given first,
1779 followed by "to". Eliminations of the same "from" register are listed
1780 in order of preference. */
7d5175e1
JJ		 1781#define ELIMINABLE_REGS \
1782{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1783 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1784 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1785 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1786 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
97b23853 1787 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
f045b2c9 1788
f045b2c9
RS		 1789/* Define the offset between two registers, one to be eliminated, and the other
1790 its replacement, at the start of a routine. */
d1d0c603
JJ		 1791#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1792 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
f045b2c9
RS		 1793\f
1794/* Addressing modes, and classification of registers for them. */
1795
940da324
JL		 1796#define HAVE_PRE_DECREMENT 1
1797#define HAVE_PRE_INCREMENT 1
6fb5fa3c
DB		 1798#define HAVE_PRE_MODIFY_DISP 1
1799#define HAVE_PRE_MODIFY_REG 1
f045b2c9
RS		 1800
1801/* Macros to check register numbers against specific register classes. */
1802
1803/* These assume that REGNO is a hard or pseudo reg number.
1804 They give nonzero only if REGNO is a hard reg of the suitable class
1805 or a pseudo reg currently allocated to a suitable hard reg.
1806 Since they use reg_renumber, they are safe only once reg_renumber
1807 has been allocated, which happens in local-alloc.c. */
1808
1809#define REGNO_OK_FOR_INDEX_P(REGNO) \
1810((REGNO) < FIRST_PSEUDO_REGISTER \
1811 ? (REGNO) <= 31 || (REGNO) == 67 \
7d5175e1 1812 || (REGNO) == FRAME_POINTER_REGNUM \
f045b2c9 1813 : (reg_renumber[REGNO] >= 0 \
7d5175e1
JJ		 1814 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1815 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
f045b2c9
RS		 1816
1817#define REGNO_OK_FOR_BASE_P(REGNO) \
1818((REGNO) < FIRST_PSEUDO_REGISTER \
1819 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
7d5175e1 1820 || (REGNO) == FRAME_POINTER_REGNUM \
f045b2c9 1821 : (reg_renumber[REGNO] > 0 \
7d5175e1
JJ		 1822 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1823 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
c6c3dba9
PB		 1824
1825/* Nonzero if X is a hard reg that can be used as an index
1826 or if it is a pseudo reg in the non-strict case. */
1827#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1828 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1829 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1830
1831/* Nonzero if X is a hard reg that can be used as a base reg
1832 or if it is a pseudo reg in the non-strict case. */
1833#define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1834 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1835 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1836
f045b2c9
RS		 1837\f
1838/* Maximum number of registers that can appear in a valid memory address. */
1839
1840#define MAX_REGS_PER_ADDRESS 2
1841
1842/* Recognize any constant value that is a valid address. */
1843
6eff269e
BK		 1844#define CONSTANT_ADDRESS_P(X) \
1845 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1846 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1847 || GET_CODE (X) == HIGH)
f045b2c9
RS		 1848
1849/* Nonzero if the constant value X is a legitimate general operand.
1850 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1851
1852 On the RS/6000, all integer constants are acceptable, most won't be valid
1853 for particular insns, though. Only easy FP constants are
1854 acceptable. */
1855
1856#define LEGITIMATE_CONSTANT_P(X) \
49a2166f
AH		 1857 (((GET_CODE (X) != CONST_DOUBLE \
1858 && GET_CODE (X) != CONST_VECTOR) \
1859 || GET_MODE (X) == VOIDmode \
c4501e62 1860 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
49a2166f
AH		 1861 || easy_fp_constant (X, GET_MODE (X)) \
1862 || easy_vector_constant (X, GET_MODE (X))) \
c4501e62 1863 && !rs6000_tls_referenced_p (X))
f045b2c9 1864
48d72335 1865#define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
66180ff3 1866#define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
76492753
PB		 1867 && EASY_VECTOR_15((n) >> 1) \
1868 && ((n) & 1) == 0)
48d72335 1869
29e6733c
MM		 1870#define EASY_VECTOR_MSB(n,mode) \
1871 (((unsigned HOST_WIDE_INT)n) == \
1872 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1873
f045b2c9 1874\f
a260abc9
DE		 1875/* Try a machine-dependent way of reloading an illegitimate address
1876 operand. If we find one, push the reload and jump to WIN. This
1877 macro is used in only one place: `find_reloads_address' in reload.c.
1878
f676971a 1879 Implemented on rs6000 by rs6000_legitimize_reload_address.
24ea750e 1880 Note that (X) is evaluated twice; this is safe in current usage. */
f676971a 1881
a9098fd0
GK		 1882#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1883do { \
24ea750e 1884 int win; \
8beb65e3 1885 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
24ea750e
DJ		 1886 (int)(TYPE), (IND_LEVELS), &win); \
1887 if ( win ) \
1888 goto WIN; \
a260abc9
DE		 1889} while (0)
1890
f045b2c9 1891/* Go to LABEL if ADDR (a legitimate address expression)
4d588c14 1892 has an effect that depends on the machine mode it is used for. */
f045b2c9
RS		 1893
1894#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
4d588c14 1895do { \
8beb65e3 1896 if (rs6000_mode_dependent_address_ptr (ADDR)) \
f045b2c9 1897 goto LABEL; \
4d588c14 1898} while (0)
944258eb
RS		 1899
1900#define FIND_BASE_TERM rs6000_find_base_term
766a866c
MM		 1901\f
1902/* The register number of the register used to address a table of
1903 static data addresses in memory. In some cases this register is
1904 defined by a processor's "application binary interface" (ABI).
1905 When this macro is defined, RTL is generated for this register
1906 once, as with the stack pointer and frame pointer registers. If
1907 this macro is not defined, it is up to the machine-dependent files
1908 to allocate such a register (if necessary). */
1909
1db02437
FS		 1910#define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1911#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
766a866c 1912
97b23853 1913#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
9ebbca7d 1914
766a866c
MM		 1915/* Define this macro if the register defined by
1916 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
089a05b8 1917 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
766a866c
MM		 1918
1919/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1920
766a866c
MM		 1921/* A C expression that is nonzero if X is a legitimate immediate
1922 operand on the target machine when generating position independent
1923 code. You can assume that X satisfies `CONSTANT_P', so you need
1924 not check this. You can also assume FLAG_PIC is true, so you need
1925 not check it either. You need not define this macro if all
1926 constants (including `SYMBOL_REF') can be immediate operands when
1927 generating position independent code. */
1928
1929/* #define LEGITIMATE_PIC_OPERAND_P (X) */
f045b2c9
RS		 1930\f
1931/* Define this if some processing needs to be done immediately before
4255474b 1932 emitting code for an insn. */
f045b2c9 1933
c921bad8
AP		 1934#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
1935 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
f045b2c9
RS		 1936
1937/* Specify the machine mode that this machine uses
1938 for the index in the tablejump instruction. */
e1565e65 1939#define CASE_VECTOR_MODE SImode
f045b2c9 1940
18543a22
ILT		 1941/* Define as C expression which evaluates to nonzero if the tablejump
1942 instruction expects the table to contain offsets from the address of the
1943 table.
82e41834 1944 Do not define this if the table should contain absolute addresses. */
18543a22 1945#define CASE_VECTOR_PC_RELATIVE 1
f045b2c9 1946
f045b2c9
RS		 1947/* Define this as 1 if `char' should by default be signed; else as 0. */
1948#define DEFAULT_SIGNED_CHAR 0
1949
1950/* This flag, if defined, says the same insns that convert to a signed fixnum
1951 also convert validly to an unsigned one. */
1952
1953/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1954
c1618c0c
DE		 1955/* An integer expression for the size in bits of the largest integer machine
1956 mode that should actually be used. */
1957
1958/* Allow pairs of registers to be used, which is the intent of the default. */
1959#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1960
f045b2c9
RS		 1961/* Max number of bytes we can move from memory to memory
1962 in one reasonably fast instruction. */
2f3e5814 1963#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
7e69e155 1964#define MAX_MOVE_MAX 8
f045b2c9
RS		 1965
1966/* Nonzero if access to memory by bytes is no faster than for words.
a0ab749a 1967 Also nonzero if doing byte operations (specifically shifts) in registers
f045b2c9
RS		 1968 is undesirable. */
1969#define SLOW_BYTE_ACCESS 1
1970
9a63901f
RK		 1971/* Define if operations between registers always perform the operation
1972 on the full register even if a narrower mode is specified. */
1973#define WORD_REGISTER_OPERATIONS
1974
1975/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1976 will either zero-extend or sign-extend. The value of this macro should
1977 be the code that says which one of the two operations is implicitly
f822d252 1978 done, UNKNOWN if none. */
9a63901f 1979#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
225211e2
RK		 1980
1981/* Define if loading short immediate values into registers sign extends. */
1982#define SHORT_IMMEDIATES_SIGN_EXTEND
fdaff8ba 1983\f
f045b2c9
RS		 1984/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1985 is done just by pretending it is already truncated. */
1986#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1987
94993909 1988/* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
d865b122 1989#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
14670a74 1990 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
d865b122 1991
94993909 1992/* The CTZ patterns return -1 for input of zero. */
14670a74 1993#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
94993909 1994
f045b2c9
RS		 1995/* Specify the machine mode that pointers have.
1996 After generation of rtl, the compiler makes no further distinction
1997 between pointers and any other objects of this machine mode. */
cacf1ca8
MM		 1998extern unsigned rs6000_pmode;
1999#define Pmode ((enum machine_mode)rs6000_pmode)
f045b2c9 2000
a3c9585f 2001/* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
4c81e946
FJ		 2002#define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2003
f045b2c9 2004/* Mode of a function address in a call instruction (for indexing purposes).
f045b2c9 2005 Doesn't matter on RS/6000. */
5b71a4e7 2006#define FUNCTION_MODE SImode
f045b2c9
RS		 2007
2008/* Define this if addresses of constant functions
2009 shouldn't be put through pseudo regs where they can be cse'd.
2010 Desirable on machines where ordinary constants are expensive
2011 but a CALL with constant address is cheap. */
2012#define NO_FUNCTION_CSE
2013
d969caf8 2014/* Define this to be nonzero if shift instructions ignore all but the low-order
6febd581
RK		 2015 few bits.
2016
2017 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2018 have been dropped from the PowerPC architecture. */
2019
4697a36c 2020#define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
f045b2c9 2021
f045b2c9
RS		 2022/* Adjust the length of an INSN. LENGTH is the currently-computed length and
2023 should be adjusted to reflect any required changes. This macro is used when
2024 there is some systematic length adjustment required that would be difficult
2025 to express in the length attribute. */
2026
2027/* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2028
39a10a29
GK		 2029/* Given a comparison code (EQ, NE, etc.) and the first operand of a
2030 COMPARE, return the mode to be used for the comparison. For
2031 floating-point, CCFPmode should be used. CCUNSmode should be used
2032 for unsigned comparisons. CCEQmode should be used when we are
2033 doing an inequality comparison on the result of a
2034 comparison. CCmode should be used in all other cases. */
c5defebb 2035
b565a316 2036#define SELECT_CC_MODE(OP,X,Y) \
ebb109ad 2037 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
c5defebb 2038 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
ec8e098d 2039 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
c5defebb 2040 ? CCEQmode : CCmode))
f045b2c9 2041
b39358e1
GK		 2042/* Can the condition code MODE be safely reversed? This is safe in
2043 all cases on this port, because at present it doesn't use the
2044 trapping FP comparisons (fcmpo). */
2045#define REVERSIBLE_CC_MODE(MODE) 1
2046
2047/* Given a condition code and a mode, return the inverse condition. */
2048#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2049
f045b2c9
RS		 2050\f
2051/* Control the assembler format that we output. */
2052
1b279f39
DE		 2053/* A C string constant describing how to begin a comment in the target
2054 assembler language. The compiler assumes that the comment will end at
2055 the end of the line. */
2056#define ASM_COMMENT_START " #"
6b67933e 2057
38c1f2d7
MM		 2058/* Flag to say the TOC is initialized */
2059extern int toc_initialized;
2060
f045b2c9
RS		 2061/* Macro to output a special constant pool entry. Go to WIN if we output
2062 it. Otherwise, it is written the usual way.
2063
2064 On the RS/6000, toc entries are handled this way. */
2065
a9098fd0
GK		 2066#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2067{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2068 { \
2069 output_toc (FILE, X, LABELNO, MODE); \
2070 goto WIN; \
2071 } \
f045b2c9
RS		 2072}
2073
ebd97b96
DE		 2074#ifdef HAVE_GAS_WEAK
2075#define RS6000_WEAK 1
2076#else
2077#define RS6000_WEAK 0
2078#endif
290ad355 2079
79c4e63f
AM		 2080#if RS6000_WEAK
2081/* Used in lieu of ASM_WEAKEN_LABEL. */
2082#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2083 do \
2084 { \
2085 fputs ("\t.weak\t", (FILE)); \
85b776df 2086 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f 2087 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 2088 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f 2089 { \
cbaaba19
DE		 2090 if (TARGET_XCOFF) \
2091 fputs ("[DS]", (FILE)); \
ca734b39 2092 fputs ("\n\t.weak\t.", (FILE)); \
cbaaba19 2093 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f
AM		 2094 } \
2095 fputc ('\n', (FILE)); \
2096 if (VAL) \
2097 { \
2098 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2099 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 2100 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f
AM		 2101 { \
2102 fputs ("\t.set\t.", (FILE)); \
cbaaba19 2103 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f 2104 fputs (",.", (FILE)); \
cbaaba19 2105 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
79c4e63f
AM		 2106 fputc ('\n', (FILE)); \
2107 } \
2108 } \
2109 } \
2110 while (0)
2111#endif
2112
ff2d10c1
AO		 2113#if HAVE_GAS_WEAKREF
2114#define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2115 do \
2116 { \
2117 fputs ("\t.weakref\t", (FILE)); \
2118 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2119 fputs (", ", (FILE)); \
2120 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2121 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2122 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2123 { \
2124 fputs ("\n\t.weakref\t.", (FILE)); \
2125 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2126 fputs (", .", (FILE)); \
2127 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2128 } \
2129 fputc ('\n', (FILE)); \
2130 } while (0)
2131#endif
2132
79c4e63f
AM		 2133/* This implements the `alias' attribute. */
2134#undef ASM_OUTPUT_DEF_FROM_DECLS
2135#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2136 do \
2137 { \
2138 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2139 const char *name = IDENTIFIER_POINTER (TARGET); \
2140 if (TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 2141 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f
AM		 2142 { \
2143 if (TREE_PUBLIC (DECL)) \
2144 { \
2145 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2146 { \
2147 fputs ("\t.globl\t.", FILE); \
cbaaba19 2148 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f
AM		 2149 putc ('\n', FILE); \
2150 } \
2151 } \
2152 else if (TARGET_XCOFF) \
2153 { \
2154 fputs ("\t.lglobl\t.", FILE); \
cbaaba19 2155 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f
AM		 2156 putc ('\n', FILE); \
2157 } \
2158 fputs ("\t.set\t.", FILE); \
cbaaba19 2159 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f 2160 fputs (",.", FILE); \
cbaaba19 2161 RS6000_OUTPUT_BASENAME (FILE, name); \
79c4e63f
AM		 2162 fputc ('\n', FILE); \
2163 } \
2164 ASM_OUTPUT_DEF (FILE, alias, name); \
2165 } \
2166 while (0)
290ad355 2167
1bc7c5b6
ZW		 2168#define TARGET_ASM_FILE_START rs6000_file_start
2169
f045b2c9
RS		 2170/* Output to assembler file text saying following lines
2171 may contain character constants, extra white space, comments, etc. */
2172
2173#define ASM_APP_ON ""
2174
2175/* Output to assembler file text saying following lines
2176 no longer contain unusual constructs. */
2177
2178#define ASM_APP_OFF ""
2179
f045b2c9
RS		 2180/* How to refer to registers in assembler output.
2181 This sequence is indexed by compiler's hard-register-number (see above). */
2182
82e41834 2183extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
c81bebd7
MM		 2184
2185#define REGISTER_NAMES \
2186{ \
2187 &rs6000_reg_names[ 0][0], /* r0 */ \
2188 &rs6000_reg_names[ 1][0], /* r1 */ \
2189 &rs6000_reg_names[ 2][0], /* r2 */ \
2190 &rs6000_reg_names[ 3][0], /* r3 */ \
2191 &rs6000_reg_names[ 4][0], /* r4 */ \
2192 &rs6000_reg_names[ 5][0], /* r5 */ \
2193 &rs6000_reg_names[ 6][0], /* r6 */ \
2194 &rs6000_reg_names[ 7][0], /* r7 */ \
2195 &rs6000_reg_names[ 8][0], /* r8 */ \
2196 &rs6000_reg_names[ 9][0], /* r9 */ \
2197 &rs6000_reg_names[10][0], /* r10 */ \
2198 &rs6000_reg_names[11][0], /* r11 */ \
2199 &rs6000_reg_names[12][0], /* r12 */ \
2200 &rs6000_reg_names[13][0], /* r13 */ \
2201 &rs6000_reg_names[14][0], /* r14 */ \
2202 &rs6000_reg_names[15][0], /* r15 */ \
2203 &rs6000_reg_names[16][0], /* r16 */ \
2204 &rs6000_reg_names[17][0], /* r17 */ \
2205 &rs6000_reg_names[18][0], /* r18 */ \
2206 &rs6000_reg_names[19][0], /* r19 */ \
2207 &rs6000_reg_names[20][0], /* r20 */ \
2208 &rs6000_reg_names[21][0], /* r21 */ \
2209 &rs6000_reg_names[22][0], /* r22 */ \
2210 &rs6000_reg_names[23][0], /* r23 */ \
2211 &rs6000_reg_names[24][0], /* r24 */ \
2212 &rs6000_reg_names[25][0], /* r25 */ \
2213 &rs6000_reg_names[26][0], /* r26 */ \
2214 &rs6000_reg_names[27][0], /* r27 */ \
2215 &rs6000_reg_names[28][0], /* r28 */ \
2216 &rs6000_reg_names[29][0], /* r29 */ \
2217 &rs6000_reg_names[30][0], /* r30 */ \
2218 &rs6000_reg_names[31][0], /* r31 */ \
2219 \
2220 &rs6000_reg_names[32][0], /* fr0 */ \
2221 &rs6000_reg_names[33][0], /* fr1 */ \
2222 &rs6000_reg_names[34][0], /* fr2 */ \
2223 &rs6000_reg_names[35][0], /* fr3 */ \
2224 &rs6000_reg_names[36][0], /* fr4 */ \
2225 &rs6000_reg_names[37][0], /* fr5 */ \
2226 &rs6000_reg_names[38][0], /* fr6 */ \
2227 &rs6000_reg_names[39][0], /* fr7 */ \
2228 &rs6000_reg_names[40][0], /* fr8 */ \
2229 &rs6000_reg_names[41][0], /* fr9 */ \
2230 &rs6000_reg_names[42][0], /* fr10 */ \
2231 &rs6000_reg_names[43][0], /* fr11 */ \
2232 &rs6000_reg_names[44][0], /* fr12 */ \
2233 &rs6000_reg_names[45][0], /* fr13 */ \
2234 &rs6000_reg_names[46][0], /* fr14 */ \
2235 &rs6000_reg_names[47][0], /* fr15 */ \
2236 &rs6000_reg_names[48][0], /* fr16 */ \
2237 &rs6000_reg_names[49][0], /* fr17 */ \
2238 &rs6000_reg_names[50][0], /* fr18 */ \
2239 &rs6000_reg_names[51][0], /* fr19 */ \
2240 &rs6000_reg_names[52][0], /* fr20 */ \
2241 &rs6000_reg_names[53][0], /* fr21 */ \
2242 &rs6000_reg_names[54][0], /* fr22 */ \
2243 &rs6000_reg_names[55][0], /* fr23 */ \
2244 &rs6000_reg_names[56][0], /* fr24 */ \
2245 &rs6000_reg_names[57][0], /* fr25 */ \
2246 &rs6000_reg_names[58][0], /* fr26 */ \
2247 &rs6000_reg_names[59][0], /* fr27 */ \
2248 &rs6000_reg_names[60][0], /* fr28 */ \
2249 &rs6000_reg_names[61][0], /* fr29 */ \
2250 &rs6000_reg_names[62][0], /* fr30 */ \
2251 &rs6000_reg_names[63][0], /* fr31 */ \
2252 \
2253 &rs6000_reg_names[64][0], /* mq */ \
2254 &rs6000_reg_names[65][0], /* lr */ \
2255 &rs6000_reg_names[66][0], /* ctr */ \
2256 &rs6000_reg_names[67][0], /* ap */ \
2257 \
2258 &rs6000_reg_names[68][0], /* cr0 */ \
2259 &rs6000_reg_names[69][0], /* cr1 */ \
2260 &rs6000_reg_names[70][0], /* cr2 */ \
2261 &rs6000_reg_names[71][0], /* cr3 */ \
2262 &rs6000_reg_names[72][0], /* cr4 */ \
2263 &rs6000_reg_names[73][0], /* cr5 */ \
2264 &rs6000_reg_names[74][0], /* cr6 */ \
2265 &rs6000_reg_names[75][0], /* cr7 */ \
802a0058 2266 \
9ebbca7d 2267 &rs6000_reg_names[76][0], /* xer */ \
0ac081f6
AH		 2268 \
2269 &rs6000_reg_names[77][0], /* v0 */ \
2270 &rs6000_reg_names[78][0], /* v1 */ \
2271 &rs6000_reg_names[79][0], /* v2 */ \
2272 &rs6000_reg_names[80][0], /* v3 */ \
2273 &rs6000_reg_names[81][0], /* v4 */ \
2274 &rs6000_reg_names[82][0], /* v5 */ \
2275 &rs6000_reg_names[83][0], /* v6 */ \
2276 &rs6000_reg_names[84][0], /* v7 */ \
2277 &rs6000_reg_names[85][0], /* v8 */ \
2278 &rs6000_reg_names[86][0], /* v9 */ \
2279 &rs6000_reg_names[87][0], /* v10 */ \
2280 &rs6000_reg_names[88][0], /* v11 */ \
2281 &rs6000_reg_names[89][0], /* v12 */ \
2282 &rs6000_reg_names[90][0], /* v13 */ \
2283 &rs6000_reg_names[91][0], /* v14 */ \
2284 &rs6000_reg_names[92][0], /* v15 */ \
2285 &rs6000_reg_names[93][0], /* v16 */ \
2286 &rs6000_reg_names[94][0], /* v17 */ \
2287 &rs6000_reg_names[95][0], /* v18 */ \
2288 &rs6000_reg_names[96][0], /* v19 */ \
2289 &rs6000_reg_names[97][0], /* v20 */ \
2290 &rs6000_reg_names[98][0], /* v21 */ \
2291 &rs6000_reg_names[99][0], /* v22 */ \
2292 &rs6000_reg_names[100][0], /* v23 */ \
2293 &rs6000_reg_names[101][0], /* v24 */ \
2294 &rs6000_reg_names[102][0], /* v25 */ \
2295 &rs6000_reg_names[103][0], /* v26 */ \
2296 &rs6000_reg_names[104][0], /* v27 */ \
2297 &rs6000_reg_names[105][0], /* v28 */ \
2298 &rs6000_reg_names[106][0], /* v29 */ \
2299 &rs6000_reg_names[107][0], /* v30 */ \
2300 &rs6000_reg_names[108][0], /* v31 */ \
2301 &rs6000_reg_names[109][0], /* vrsave */ \
5f004351 2302 &rs6000_reg_names[110][0], /* vscr */ \
a3170dc6
AH		 2303 &rs6000_reg_names[111][0], /* spe_acc */ \
2304 &rs6000_reg_names[112][0], /* spefscr */ \
7d5175e1 2305 &rs6000_reg_names[113][0], /* sfp */ \
c81bebd7
MM		 2306}
2307
f045b2c9
RS		 2308/* Table of additional register names to use in user input. */
2309
2310#define ADDITIONAL_REGISTER_NAMES \
c4d38ccb
MM		 2311 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2312 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2313 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2314 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2315 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2316 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2317 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2318 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2319 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2320 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2321 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2322 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2323 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2324 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2325 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2326 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
0ac081f6
AH		 2327 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2328 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2329 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2330 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2331 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2332 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2333 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2334 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
5f004351 2335 {"vrsave", 109}, {"vscr", 110}, \
a3170dc6 2336 {"spe_acc", 111}, {"spefscr", 112}, \
c4d38ccb
MM		 2337 /* no additional names for: mq, lr, ctr, ap */ \
2338 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2339 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
cacf1ca8
MM		 2340 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2341 /* VSX registers overlaid on top of FR, Altivec registers */ \
2342 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2343 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2344 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2345 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2346 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2347 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2348 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2349 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2350 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2351 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2352 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2353 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2354 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2355 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2356 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2357 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }
f045b2c9 2358
0da40b09
RK		 2359/* Text to write out after a CALL that may be replaced by glue code by
2360 the loader. This depends on the AIX version. */
2361#define RS6000_CALL_GLUE "cror 31,31,31"
11117bb9 2362
f045b2c9
RS		 2363/* This is how to output an element of a case-vector that is relative. */
2364
e1565e65 2365#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3daf36a4 2366 do { char buf[100]; \
e1565e65 2367 fputs ("\t.long ", FILE); \
3daf36a4
ILT		 2368 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2369 assemble_name (FILE, buf); \
19d2d16f 2370 putc ('-', FILE); \
3daf36a4
ILT		 2371 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2372 assemble_name (FILE, buf); \
19d2d16f 2373 putc ('\n', FILE); \
3daf36a4 2374 } while (0)
f045b2c9
RS		 2375
2376/* This is how to output an assembler line
2377 that says to advance the location counter
2378 to a multiple of 2**LOG bytes. */
2379
2380#define ASM_OUTPUT_ALIGN(FILE,LOG) \
2381 if ((LOG) != 0) \
2382 fprintf (FILE, "\t.align %d\n", (LOG))
2383
9ebbca7d
GK		 2384/* Pick up the return address upon entry to a procedure. Used for
2385 dwarf2 unwind information. This also enables the table driven
2386 mechanism. */
2387
1de43f85
DE		 2388#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2389#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
9ebbca7d 2390
83720594
RH		 2391/* Describe how we implement __builtin_eh_return. */
2392#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2393#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2394
f045b2c9
RS		 2395/* Print operand X (an rtx) in assembler syntax to file FILE.
2396 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2397 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2398
2399#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2400
2401/* Define which CODE values are valid. */
2402
c81bebd7 2403#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
c4501e62 2404 ((CODE) == '.' || (CODE) == '&')
f045b2c9
RS		 2405
2406/* Print a memory address as an operand to reference that memory location. */
2407
2408#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2409
2e4316da
RS		 2410#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2411 do \
2412 if (!rs6000_output_addr_const_extra (STREAM, X)) \
2413 goto FAIL; \
2414 while (0)
2415
b6c9286a
MM		 2416/* uncomment for disabling the corresponding default options */
2417/* #define MACHINE_no_sched_interblock */
2418/* #define MACHINE_no_sched_speculative */
2419/* #define MACHINE_no_sched_speculative_load */
2420
766a866c
MM		 2421/* General flags. */
2422extern int flag_pic;
354b734b
MM		 2423extern int optimize;
2424extern int flag_expensive_optimizations;
a7df97e6 2425extern int frame_pointer_needed;
0ac081f6
AH		 2426
2427enum rs6000_builtins
2428{
2429 /* AltiVec builtins. */
f18c054f
DB		 2430 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2431 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2432 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2433 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2434 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2435 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2436 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2437 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
0ac081f6
AH		 2438 ALTIVEC_BUILTIN_VADDUBM,
2439 ALTIVEC_BUILTIN_VADDUHM,
2440 ALTIVEC_BUILTIN_VADDUWM,
2441 ALTIVEC_BUILTIN_VADDFP,
2442 ALTIVEC_BUILTIN_VADDCUW,
2443 ALTIVEC_BUILTIN_VADDUBS,
2444 ALTIVEC_BUILTIN_VADDSBS,
2445 ALTIVEC_BUILTIN_VADDUHS,
2446 ALTIVEC_BUILTIN_VADDSHS,
2447 ALTIVEC_BUILTIN_VADDUWS,
2448 ALTIVEC_BUILTIN_VADDSWS,
2449 ALTIVEC_BUILTIN_VAND,
2450 ALTIVEC_BUILTIN_VANDC,
2451 ALTIVEC_BUILTIN_VAVGUB,
2452 ALTIVEC_BUILTIN_VAVGSB,
2453 ALTIVEC_BUILTIN_VAVGUH,
2454 ALTIVEC_BUILTIN_VAVGSH,
2455 ALTIVEC_BUILTIN_VAVGUW,
2456 ALTIVEC_BUILTIN_VAVGSW,
617e0e1d
DB		 2457 ALTIVEC_BUILTIN_VCFUX,
2458 ALTIVEC_BUILTIN_VCFSX,
2459 ALTIVEC_BUILTIN_VCTSXS,
2460 ALTIVEC_BUILTIN_VCTUXS,
0ac081f6
AH		 2461 ALTIVEC_BUILTIN_VCMPBFP,
2462 ALTIVEC_BUILTIN_VCMPEQUB,
2463 ALTIVEC_BUILTIN_VCMPEQUH,
2464 ALTIVEC_BUILTIN_VCMPEQUW,
2465 ALTIVEC_BUILTIN_VCMPEQFP,
2466 ALTIVEC_BUILTIN_VCMPGEFP,
2467 ALTIVEC_BUILTIN_VCMPGTUB,
2468 ALTIVEC_BUILTIN_VCMPGTSB,
2469 ALTIVEC_BUILTIN_VCMPGTUH,
2470 ALTIVEC_BUILTIN_VCMPGTSH,
2471 ALTIVEC_BUILTIN_VCMPGTUW,
2472 ALTIVEC_BUILTIN_VCMPGTSW,
2473 ALTIVEC_BUILTIN_VCMPGTFP,
617e0e1d
DB		 2474 ALTIVEC_BUILTIN_VEXPTEFP,
2475 ALTIVEC_BUILTIN_VLOGEFP,
2212663f 2476 ALTIVEC_BUILTIN_VMADDFP,
0ac081f6
AH		 2477 ALTIVEC_BUILTIN_VMAXUB,
2478 ALTIVEC_BUILTIN_VMAXSB,
2479 ALTIVEC_BUILTIN_VMAXUH,
2480 ALTIVEC_BUILTIN_VMAXSH,
2481 ALTIVEC_BUILTIN_VMAXUW,
2482 ALTIVEC_BUILTIN_VMAXSW,
2483 ALTIVEC_BUILTIN_VMAXFP,
2212663f
DB		 2484 ALTIVEC_BUILTIN_VMHADDSHS,
2485 ALTIVEC_BUILTIN_VMHRADDSHS,
2486 ALTIVEC_BUILTIN_VMLADDUHM,
0ac081f6
AH		 2487 ALTIVEC_BUILTIN_VMRGHB,
2488 ALTIVEC_BUILTIN_VMRGHH,
2489 ALTIVEC_BUILTIN_VMRGHW,
2490 ALTIVEC_BUILTIN_VMRGLB,
2491 ALTIVEC_BUILTIN_VMRGLH,
2492 ALTIVEC_BUILTIN_VMRGLW,
2212663f
DB		 2493 ALTIVEC_BUILTIN_VMSUMUBM,
2494 ALTIVEC_BUILTIN_VMSUMMBM,
2495 ALTIVEC_BUILTIN_VMSUMUHM,
2496 ALTIVEC_BUILTIN_VMSUMSHM,
2497 ALTIVEC_BUILTIN_VMSUMUHS,
2498 ALTIVEC_BUILTIN_VMSUMSHS,
0ac081f6
AH		 2499 ALTIVEC_BUILTIN_VMINUB,
2500 ALTIVEC_BUILTIN_VMINSB,
2501 ALTIVEC_BUILTIN_VMINUH,
2502 ALTIVEC_BUILTIN_VMINSH,
2503 ALTIVEC_BUILTIN_VMINUW,
2504 ALTIVEC_BUILTIN_VMINSW,
2505 ALTIVEC_BUILTIN_VMINFP,
2506 ALTIVEC_BUILTIN_VMULEUB,
a72c65c7 2507 ALTIVEC_BUILTIN_VMULEUB_UNS,
0ac081f6
AH		 2508 ALTIVEC_BUILTIN_VMULESB,
2509 ALTIVEC_BUILTIN_VMULEUH,
a72c65c7 2510 ALTIVEC_BUILTIN_VMULEUH_UNS,
0ac081f6
AH		 2511 ALTIVEC_BUILTIN_VMULESH,
2512 ALTIVEC_BUILTIN_VMULOUB,
a72c65c7 2513 ALTIVEC_BUILTIN_VMULOUB_UNS,
0ac081f6
AH		 2514 ALTIVEC_BUILTIN_VMULOSB,
2515 ALTIVEC_BUILTIN_VMULOUH,
a72c65c7 2516 ALTIVEC_BUILTIN_VMULOUH_UNS,
0ac081f6 2517 ALTIVEC_BUILTIN_VMULOSH,
2212663f 2518 ALTIVEC_BUILTIN_VNMSUBFP,
0ac081f6
AH		 2519 ALTIVEC_BUILTIN_VNOR,
2520 ALTIVEC_BUILTIN_VOR,
a72c65c7
MM		 2521 ALTIVEC_BUILTIN_VSEL_2DF, /* needed for VSX */
2522 ALTIVEC_BUILTIN_VSEL_2DI, /* needed for VSX */
617e0e1d
DB		 2523 ALTIVEC_BUILTIN_VSEL_4SI,
2524 ALTIVEC_BUILTIN_VSEL_4SF,
2525 ALTIVEC_BUILTIN_VSEL_8HI,
2526 ALTIVEC_BUILTIN_VSEL_16QI,
a72c65c7
MM		 2527 ALTIVEC_BUILTIN_VSEL_2DI_UNS,
2528 ALTIVEC_BUILTIN_VSEL_4SI_UNS,
2529 ALTIVEC_BUILTIN_VSEL_8HI_UNS,
2530 ALTIVEC_BUILTIN_VSEL_16QI_UNS,
2531 ALTIVEC_BUILTIN_VPERM_2DF, /* needed for VSX */
2532 ALTIVEC_BUILTIN_VPERM_2DI, /* needed for VSX */
2212663f
DB		 2533 ALTIVEC_BUILTIN_VPERM_4SI,
2534 ALTIVEC_BUILTIN_VPERM_4SF,
2535 ALTIVEC_BUILTIN_VPERM_8HI,
2536 ALTIVEC_BUILTIN_VPERM_16QI,
a72c65c7
MM		 2537 ALTIVEC_BUILTIN_VPERM_2DI_UNS,
2538 ALTIVEC_BUILTIN_VPERM_4SI_UNS,
2539 ALTIVEC_BUILTIN_VPERM_8HI_UNS,
2540 ALTIVEC_BUILTIN_VPERM_16QI_UNS,
0ac081f6
AH		 2541 ALTIVEC_BUILTIN_VPKUHUM,
2542 ALTIVEC_BUILTIN_VPKUWUM,
2543 ALTIVEC_BUILTIN_VPKPX,
2544 ALTIVEC_BUILTIN_VPKUHSS,
2545 ALTIVEC_BUILTIN_VPKSHSS,
2546 ALTIVEC_BUILTIN_VPKUWSS,
2547 ALTIVEC_BUILTIN_VPKSWSS,
2548 ALTIVEC_BUILTIN_VPKUHUS,
2549 ALTIVEC_BUILTIN_VPKSHUS,
2550 ALTIVEC_BUILTIN_VPKUWUS,
2551 ALTIVEC_BUILTIN_VPKSWUS,
617e0e1d
DB		 2552 ALTIVEC_BUILTIN_VREFP,
2553 ALTIVEC_BUILTIN_VRFIM,
2554 ALTIVEC_BUILTIN_VRFIN,
2555 ALTIVEC_BUILTIN_VRFIP,
2556 ALTIVEC_BUILTIN_VRFIZ,
0ac081f6
AH		 2557 ALTIVEC_BUILTIN_VRLB,
2558 ALTIVEC_BUILTIN_VRLH,
2559 ALTIVEC_BUILTIN_VRLW,
617e0e1d 2560 ALTIVEC_BUILTIN_VRSQRTEFP,
0ac081f6
AH		 2561 ALTIVEC_BUILTIN_VSLB,
2562 ALTIVEC_BUILTIN_VSLH,
2563 ALTIVEC_BUILTIN_VSLW,
2564 ALTIVEC_BUILTIN_VSL,
2565 ALTIVEC_BUILTIN_VSLO,
2212663f
DB		 2566 ALTIVEC_BUILTIN_VSPLTB,
2567 ALTIVEC_BUILTIN_VSPLTH,
2568 ALTIVEC_BUILTIN_VSPLTW,
2569 ALTIVEC_BUILTIN_VSPLTISB,
2570 ALTIVEC_BUILTIN_VSPLTISH,
2571 ALTIVEC_BUILTIN_VSPLTISW,
0ac081f6 2572 ALTIVEC_BUILTIN_VSRB,
f18c054f
DB		 2573 ALTIVEC_BUILTIN_VSRH,
2574 ALTIVEC_BUILTIN_VSRW,
0ac081f6
AH		 2575 ALTIVEC_BUILTIN_VSRAB,
2576 ALTIVEC_BUILTIN_VSRAH,
2577 ALTIVEC_BUILTIN_VSRAW,
2578 ALTIVEC_BUILTIN_VSR,
2579 ALTIVEC_BUILTIN_VSRO,
2580 ALTIVEC_BUILTIN_VSUBUBM,
2581 ALTIVEC_BUILTIN_VSUBUHM,
2582 ALTIVEC_BUILTIN_VSUBUWM,
2583 ALTIVEC_BUILTIN_VSUBFP,
2584 ALTIVEC_BUILTIN_VSUBCUW,
2585 ALTIVEC_BUILTIN_VSUBUBS,
2586 ALTIVEC_BUILTIN_VSUBSBS,
2587 ALTIVEC_BUILTIN_VSUBUHS,
2588 ALTIVEC_BUILTIN_VSUBSHS,
2589 ALTIVEC_BUILTIN_VSUBUWS,
2590 ALTIVEC_BUILTIN_VSUBSWS,
2591 ALTIVEC_BUILTIN_VSUM4UBS,
2592 ALTIVEC_BUILTIN_VSUM4SBS,
2593 ALTIVEC_BUILTIN_VSUM4SHS,
2594 ALTIVEC_BUILTIN_VSUM2SWS,
2595 ALTIVEC_BUILTIN_VSUMSWS,
24408032
AH		 2596 ALTIVEC_BUILTIN_VXOR,
2597 ALTIVEC_BUILTIN_VSLDOI_16QI,
2598 ALTIVEC_BUILTIN_VSLDOI_8HI,
2599 ALTIVEC_BUILTIN_VSLDOI_4SI,
20e26713
AH		 2600 ALTIVEC_BUILTIN_VSLDOI_4SF,
2601 ALTIVEC_BUILTIN_VUPKHSB,
2602 ALTIVEC_BUILTIN_VUPKHPX,
2603 ALTIVEC_BUILTIN_VUPKHSH,
2604 ALTIVEC_BUILTIN_VUPKLSB,
2605 ALTIVEC_BUILTIN_VUPKLPX,
fa066a23 2606 ALTIVEC_BUILTIN_VUPKLSH,
95385cbb
AH		 2607 ALTIVEC_BUILTIN_MTVSCR,
2608 ALTIVEC_BUILTIN_MFVSCR,
2609 ALTIVEC_BUILTIN_DSSALL,
2610 ALTIVEC_BUILTIN_DSS,
2611 ALTIVEC_BUILTIN_LVSL,
2612 ALTIVEC_BUILTIN_LVSR,
2613 ALTIVEC_BUILTIN_DSTT,
2614 ALTIVEC_BUILTIN_DSTST,
2615 ALTIVEC_BUILTIN_DSTSTT,
6525c0e7
AH		 2616 ALTIVEC_BUILTIN_DST,
2617 ALTIVEC_BUILTIN_LVEBX,
2618 ALTIVEC_BUILTIN_LVEHX,
2619 ALTIVEC_BUILTIN_LVEWX,
2620 ALTIVEC_BUILTIN_LVXL,
2621 ALTIVEC_BUILTIN_LVX,
2622 ALTIVEC_BUILTIN_STVX,
0b61703c
AP		 2623 ALTIVEC_BUILTIN_LVLX,
2624 ALTIVEC_BUILTIN_LVLXL,
2625 ALTIVEC_BUILTIN_LVRX,
2626 ALTIVEC_BUILTIN_LVRXL,
6525c0e7
AH		 2627 ALTIVEC_BUILTIN_STVEBX,
2628 ALTIVEC_BUILTIN_STVEHX,
2629 ALTIVEC_BUILTIN_STVEWX,
ae4b4a02 2630 ALTIVEC_BUILTIN_STVXL,
0b61703c
AP		 2631 ALTIVEC_BUILTIN_STVLX,
2632 ALTIVEC_BUILTIN_STVLXL,
2633 ALTIVEC_BUILTIN_STVRX,
2634 ALTIVEC_BUILTIN_STVRXL,
ae4b4a02
AH		 2635 ALTIVEC_BUILTIN_VCMPBFP_P,
2636 ALTIVEC_BUILTIN_VCMPEQFP_P,
2637 ALTIVEC_BUILTIN_VCMPEQUB_P,
2638 ALTIVEC_BUILTIN_VCMPEQUH_P,
2639 ALTIVEC_BUILTIN_VCMPEQUW_P,
2640 ALTIVEC_BUILTIN_VCMPGEFP_P,
2641 ALTIVEC_BUILTIN_VCMPGTFP_P,
2642 ALTIVEC_BUILTIN_VCMPGTSB_P,
2643 ALTIVEC_BUILTIN_VCMPGTSH_P,
2644 ALTIVEC_BUILTIN_VCMPGTSW_P,
2645 ALTIVEC_BUILTIN_VCMPGTUB_P,
2646 ALTIVEC_BUILTIN_VCMPGTUH_P,
100c4561
AH		 2647 ALTIVEC_BUILTIN_VCMPGTUW_P,
2648 ALTIVEC_BUILTIN_ABSS_V4SI,
2649 ALTIVEC_BUILTIN_ABSS_V8HI,
2650 ALTIVEC_BUILTIN_ABSS_V16QI,
2651 ALTIVEC_BUILTIN_ABS_V4SI,
2652 ALTIVEC_BUILTIN_ABS_V4SF,
2653 ALTIVEC_BUILTIN_ABS_V8HI,
8bb418a3 2654 ALTIVEC_BUILTIN_ABS_V16QI,
7ccf35ed
DN		 2655 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2656 ALTIVEC_BUILTIN_MASK_FOR_STORE,
7a4eca66
DE		 2657 ALTIVEC_BUILTIN_VEC_INIT_V4SI,
2658 ALTIVEC_BUILTIN_VEC_INIT_V8HI,
2659 ALTIVEC_BUILTIN_VEC_INIT_V16QI,
2660 ALTIVEC_BUILTIN_VEC_INIT_V4SF,
2661 ALTIVEC_BUILTIN_VEC_SET_V4SI,
2662 ALTIVEC_BUILTIN_VEC_SET_V8HI,
2663 ALTIVEC_BUILTIN_VEC_SET_V16QI,
2664 ALTIVEC_BUILTIN_VEC_SET_V4SF,
2665 ALTIVEC_BUILTIN_VEC_EXT_V4SI,
2666 ALTIVEC_BUILTIN_VEC_EXT_V8HI,
2667 ALTIVEC_BUILTIN_VEC_EXT_V16QI,
2668 ALTIVEC_BUILTIN_VEC_EXT_V4SF,
29e6733c 2669 ALTIVEC_BUILTIN_COPYSIGN_V4SF,
8bb418a3 2670
58646b77
PB		 2671 /* Altivec overloaded builtins. */
2672 ALTIVEC_BUILTIN_VCMPEQ_P,
2673 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
2674 ALTIVEC_BUILTIN_VCMPGT_P,
2675 ALTIVEC_BUILTIN_VCMPGE_P,
2676 ALTIVEC_BUILTIN_VEC_ABS,
2677 ALTIVEC_BUILTIN_VEC_ABSS,
2678 ALTIVEC_BUILTIN_VEC_ADD,
2679 ALTIVEC_BUILTIN_VEC_ADDC,
2680 ALTIVEC_BUILTIN_VEC_ADDS,
2681 ALTIVEC_BUILTIN_VEC_AND,
2682 ALTIVEC_BUILTIN_VEC_ANDC,
2683 ALTIVEC_BUILTIN_VEC_AVG,
266b4890 2684 ALTIVEC_BUILTIN_VEC_EXTRACT,
58646b77
PB		 2685 ALTIVEC_BUILTIN_VEC_CEIL,
2686 ALTIVEC_BUILTIN_VEC_CMPB,
2687 ALTIVEC_BUILTIN_VEC_CMPEQ,
2688 ALTIVEC_BUILTIN_VEC_CMPEQUB,
2689 ALTIVEC_BUILTIN_VEC_CMPEQUH,
2690 ALTIVEC_BUILTIN_VEC_CMPEQUW,
2691 ALTIVEC_BUILTIN_VEC_CMPGE,
2692 ALTIVEC_BUILTIN_VEC_CMPGT,
2693 ALTIVEC_BUILTIN_VEC_CMPLE,
2694 ALTIVEC_BUILTIN_VEC_CMPLT,
29e6733c 2695 ALTIVEC_BUILTIN_VEC_COPYSIGN,
58646b77
PB		 2696 ALTIVEC_BUILTIN_VEC_CTF,
2697 ALTIVEC_BUILTIN_VEC_CTS,
2698 ALTIVEC_BUILTIN_VEC_CTU,
2699 ALTIVEC_BUILTIN_VEC_DST,
2700 ALTIVEC_BUILTIN_VEC_DSTST,
2701 ALTIVEC_BUILTIN_VEC_DSTSTT,
2702 ALTIVEC_BUILTIN_VEC_DSTT,
2703 ALTIVEC_BUILTIN_VEC_EXPTE,
2704 ALTIVEC_BUILTIN_VEC_FLOOR,
2705 ALTIVEC_BUILTIN_VEC_LD,
2706 ALTIVEC_BUILTIN_VEC_LDE,
2707 ALTIVEC_BUILTIN_VEC_LDL,
2708 ALTIVEC_BUILTIN_VEC_LOGE,
2709 ALTIVEC_BUILTIN_VEC_LVEBX,
2710 ALTIVEC_BUILTIN_VEC_LVEHX,
2711 ALTIVEC_BUILTIN_VEC_LVEWX,
0b61703c
AP		 2712 ALTIVEC_BUILTIN_VEC_LVLX,
2713 ALTIVEC_BUILTIN_VEC_LVLXL,
2714 ALTIVEC_BUILTIN_VEC_LVRX,
2715 ALTIVEC_BUILTIN_VEC_LVRXL,
58646b77
PB		 2716 ALTIVEC_BUILTIN_VEC_LVSL,
2717 ALTIVEC_BUILTIN_VEC_LVSR,
2718 ALTIVEC_BUILTIN_VEC_MADD,
2719 ALTIVEC_BUILTIN_VEC_MADDS,
2720 ALTIVEC_BUILTIN_VEC_MAX,
2721 ALTIVEC_BUILTIN_VEC_MERGEH,
2722 ALTIVEC_BUILTIN_VEC_MERGEL,
2723 ALTIVEC_BUILTIN_VEC_MIN,
2724 ALTIVEC_BUILTIN_VEC_MLADD,
2725 ALTIVEC_BUILTIN_VEC_MPERM,
2726 ALTIVEC_BUILTIN_VEC_MRADDS,
2727 ALTIVEC_BUILTIN_VEC_MRGHB,
2728 ALTIVEC_BUILTIN_VEC_MRGHH,
2729 ALTIVEC_BUILTIN_VEC_MRGHW,
2730 ALTIVEC_BUILTIN_VEC_MRGLB,
2731 ALTIVEC_BUILTIN_VEC_MRGLH,
2732 ALTIVEC_BUILTIN_VEC_MRGLW,
2733 ALTIVEC_BUILTIN_VEC_MSUM,
2734 ALTIVEC_BUILTIN_VEC_MSUMS,
2735 ALTIVEC_BUILTIN_VEC_MTVSCR,
2736 ALTIVEC_BUILTIN_VEC_MULE,
2737 ALTIVEC_BUILTIN_VEC_MULO,
29e6733c 2738 ALTIVEC_BUILTIN_VEC_NEARBYINT,
58646b77
PB		 2739 ALTIVEC_BUILTIN_VEC_NMSUB,
2740 ALTIVEC_BUILTIN_VEC_NOR,
2741 ALTIVEC_BUILTIN_VEC_OR,
2742 ALTIVEC_BUILTIN_VEC_PACK,
2743 ALTIVEC_BUILTIN_VEC_PACKPX,
2744 ALTIVEC_BUILTIN_VEC_PACKS,
2745 ALTIVEC_BUILTIN_VEC_PACKSU,
2746 ALTIVEC_BUILTIN_VEC_PERM,
2747 ALTIVEC_BUILTIN_VEC_RE,
2748 ALTIVEC_BUILTIN_VEC_RL,
29e6733c 2749 ALTIVEC_BUILTIN_VEC_RINT,
58646b77
PB		 2750 ALTIVEC_BUILTIN_VEC_ROUND,
2751 ALTIVEC_BUILTIN_VEC_RSQRTE,
2752 ALTIVEC_BUILTIN_VEC_SEL,
2753 ALTIVEC_BUILTIN_VEC_SL,
2754 ALTIVEC_BUILTIN_VEC_SLD,
2755 ALTIVEC_BUILTIN_VEC_SLL,
2756 ALTIVEC_BUILTIN_VEC_SLO,
2757 ALTIVEC_BUILTIN_VEC_SPLAT,
2758 ALTIVEC_BUILTIN_VEC_SPLAT_S16,
2759 ALTIVEC_BUILTIN_VEC_SPLAT_S32,
2760 ALTIVEC_BUILTIN_VEC_SPLAT_S8,
2761 ALTIVEC_BUILTIN_VEC_SPLAT_U16,
2762 ALTIVEC_BUILTIN_VEC_SPLAT_U32,
2763 ALTIVEC_BUILTIN_VEC_SPLAT_U8,
2764 ALTIVEC_BUILTIN_VEC_SPLTB,
2765 ALTIVEC_BUILTIN_VEC_SPLTH,
2766 ALTIVEC_BUILTIN_VEC_SPLTW,
29e6733c 2767 ALTIVEC_BUILTIN_VEC_SQRT,
58646b77
PB		 2768 ALTIVEC_BUILTIN_VEC_SR,
2769 ALTIVEC_BUILTIN_VEC_SRA,
2770 ALTIVEC_BUILTIN_VEC_SRL,
2771 ALTIVEC_BUILTIN_VEC_SRO,
2772 ALTIVEC_BUILTIN_VEC_ST,
2773 ALTIVEC_BUILTIN_VEC_STE,
2774 ALTIVEC_BUILTIN_VEC_STL,
2775 ALTIVEC_BUILTIN_VEC_STVEBX,
2776 ALTIVEC_BUILTIN_VEC_STVEHX,
2777 ALTIVEC_BUILTIN_VEC_STVEWX,
0b61703c
AP		 2778 ALTIVEC_BUILTIN_VEC_STVLX,
2779 ALTIVEC_BUILTIN_VEC_STVLXL,
2780 ALTIVEC_BUILTIN_VEC_STVRX,
2781 ALTIVEC_BUILTIN_VEC_STVRXL,
58646b77
PB		 2782 ALTIVEC_BUILTIN_VEC_SUB,
2783 ALTIVEC_BUILTIN_VEC_SUBC,
2784 ALTIVEC_BUILTIN_VEC_SUBS,
2785 ALTIVEC_BUILTIN_VEC_SUM2S,
2786 ALTIVEC_BUILTIN_VEC_SUM4S,
2787 ALTIVEC_BUILTIN_VEC_SUMS,
2788 ALTIVEC_BUILTIN_VEC_TRUNC,
2789 ALTIVEC_BUILTIN_VEC_UNPACKH,
2790 ALTIVEC_BUILTIN_VEC_UNPACKL,
2791 ALTIVEC_BUILTIN_VEC_VADDFP,
2792 ALTIVEC_BUILTIN_VEC_VADDSBS,
2793 ALTIVEC_BUILTIN_VEC_VADDSHS,
2794 ALTIVEC_BUILTIN_VEC_VADDSWS,
2795 ALTIVEC_BUILTIN_VEC_VADDUBM,
2796 ALTIVEC_BUILTIN_VEC_VADDUBS,
2797 ALTIVEC_BUILTIN_VEC_VADDUHM,
2798 ALTIVEC_BUILTIN_VEC_VADDUHS,
2799 ALTIVEC_BUILTIN_VEC_VADDUWM,
2800 ALTIVEC_BUILTIN_VEC_VADDUWS,
2801 ALTIVEC_BUILTIN_VEC_VAVGSB,
2802 ALTIVEC_BUILTIN_VEC_VAVGSH,
2803 ALTIVEC_BUILTIN_VEC_VAVGSW,
2804 ALTIVEC_BUILTIN_VEC_VAVGUB,
2805 ALTIVEC_BUILTIN_VEC_VAVGUH,
2806 ALTIVEC_BUILTIN_VEC_VAVGUW,
2807 ALTIVEC_BUILTIN_VEC_VCFSX,
2808 ALTIVEC_BUILTIN_VEC_VCFUX,
2809 ALTIVEC_BUILTIN_VEC_VCMPEQFP,
2810 ALTIVEC_BUILTIN_VEC_VCMPEQUB,
2811 ALTIVEC_BUILTIN_VEC_VCMPEQUH,
2812 ALTIVEC_BUILTIN_VEC_VCMPEQUW,
2813 ALTIVEC_BUILTIN_VEC_VCMPGTFP,
2814 ALTIVEC_BUILTIN_VEC_VCMPGTSB,
2815 ALTIVEC_BUILTIN_VEC_VCMPGTSH,
2816 ALTIVEC_BUILTIN_VEC_VCMPGTSW,
2817 ALTIVEC_BUILTIN_VEC_VCMPGTUB,
2818 ALTIVEC_BUILTIN_VEC_VCMPGTUH,
2819 ALTIVEC_BUILTIN_VEC_VCMPGTUW,
2820 ALTIVEC_BUILTIN_VEC_VMAXFP,
2821 ALTIVEC_BUILTIN_VEC_VMAXSB,
2822 ALTIVEC_BUILTIN_VEC_VMAXSH,
2823 ALTIVEC_BUILTIN_VEC_VMAXSW,
2824 ALTIVEC_BUILTIN_VEC_VMAXUB,
2825 ALTIVEC_BUILTIN_VEC_VMAXUH,
2826 ALTIVEC_BUILTIN_VEC_VMAXUW,
2827 ALTIVEC_BUILTIN_VEC_VMINFP,
2828 ALTIVEC_BUILTIN_VEC_VMINSB,
2829 ALTIVEC_BUILTIN_VEC_VMINSH,
2830 ALTIVEC_BUILTIN_VEC_VMINSW,
2831 ALTIVEC_BUILTIN_VEC_VMINUB,
2832 ALTIVEC_BUILTIN_VEC_VMINUH,
2833 ALTIVEC_BUILTIN_VEC_VMINUW,
2834 ALTIVEC_BUILTIN_VEC_VMRGHB,
2835 ALTIVEC_BUILTIN_VEC_VMRGHH,
2836 ALTIVEC_BUILTIN_VEC_VMRGHW,
2837 ALTIVEC_BUILTIN_VEC_VMRGLB,
2838 ALTIVEC_BUILTIN_VEC_VMRGLH,
2839 ALTIVEC_BUILTIN_VEC_VMRGLW,
2840 ALTIVEC_BUILTIN_VEC_VMSUMMBM,
2841 ALTIVEC_BUILTIN_VEC_VMSUMSHM,
2842 ALTIVEC_BUILTIN_VEC_VMSUMSHS,
2843 ALTIVEC_BUILTIN_VEC_VMSUMUBM,
2844 ALTIVEC_BUILTIN_VEC_VMSUMUHM,
2845 ALTIVEC_BUILTIN_VEC_VMSUMUHS,
2846 ALTIVEC_BUILTIN_VEC_VMULESB,
2847 ALTIVEC_BUILTIN_VEC_VMULESH,
2848 ALTIVEC_BUILTIN_VEC_VMULEUB,
2849 ALTIVEC_BUILTIN_VEC_VMULEUH,
2850 ALTIVEC_BUILTIN_VEC_VMULOSB,
2851 ALTIVEC_BUILTIN_VEC_VMULOSH,
2852 ALTIVEC_BUILTIN_VEC_VMULOUB,
2853 ALTIVEC_BUILTIN_VEC_VMULOUH,
2854 ALTIVEC_BUILTIN_VEC_VPKSHSS,
2855 ALTIVEC_BUILTIN_VEC_VPKSHUS,
2856 ALTIVEC_BUILTIN_VEC_VPKSWSS,
2857 ALTIVEC_BUILTIN_VEC_VPKSWUS,
2858 ALTIVEC_BUILTIN_VEC_VPKUHUM,
2859 ALTIVEC_BUILTIN_VEC_VPKUHUS,
2860 ALTIVEC_BUILTIN_VEC_VPKUWUM,
2861 ALTIVEC_BUILTIN_VEC_VPKUWUS,
2862 ALTIVEC_BUILTIN_VEC_VRLB,
2863 ALTIVEC_BUILTIN_VEC_VRLH,
2864 ALTIVEC_BUILTIN_VEC_VRLW,
2865 ALTIVEC_BUILTIN_VEC_VSLB,
2866 ALTIVEC_BUILTIN_VEC_VSLH,
2867 ALTIVEC_BUILTIN_VEC_VSLW,
2868 ALTIVEC_BUILTIN_VEC_VSPLTB,
2869 ALTIVEC_BUILTIN_VEC_VSPLTH,
2870 ALTIVEC_BUILTIN_VEC_VSPLTW,
2871 ALTIVEC_BUILTIN_VEC_VSRAB,
2872 ALTIVEC_BUILTIN_VEC_VSRAH,
2873 ALTIVEC_BUILTIN_VEC_VSRAW,
2874 ALTIVEC_BUILTIN_VEC_VSRB,
2875 ALTIVEC_BUILTIN_VEC_VSRH,
2876 ALTIVEC_BUILTIN_VEC_VSRW,
2877 ALTIVEC_BUILTIN_VEC_VSUBFP,
2878 ALTIVEC_BUILTIN_VEC_VSUBSBS,
2879 ALTIVEC_BUILTIN_VEC_VSUBSHS,
2880 ALTIVEC_BUILTIN_VEC_VSUBSWS,
2881 ALTIVEC_BUILTIN_VEC_VSUBUBM,
2882 ALTIVEC_BUILTIN_VEC_VSUBUBS,
2883 ALTIVEC_BUILTIN_VEC_VSUBUHM,
2884 ALTIVEC_BUILTIN_VEC_VSUBUHS,
2885 ALTIVEC_BUILTIN_VEC_VSUBUWM,
2886 ALTIVEC_BUILTIN_VEC_VSUBUWS,
2887 ALTIVEC_BUILTIN_VEC_VSUM4SBS,
2888 ALTIVEC_BUILTIN_VEC_VSUM4SHS,
2889 ALTIVEC_BUILTIN_VEC_VSUM4UBS,
2890 ALTIVEC_BUILTIN_VEC_VUPKHPX,
2891 ALTIVEC_BUILTIN_VEC_VUPKHSB,
2892 ALTIVEC_BUILTIN_VEC_VUPKHSH,
2893 ALTIVEC_BUILTIN_VEC_VUPKLPX,
2894 ALTIVEC_BUILTIN_VEC_VUPKLSB,
2895 ALTIVEC_BUILTIN_VEC_VUPKLSH,
2896 ALTIVEC_BUILTIN_VEC_XOR,
2897 ALTIVEC_BUILTIN_VEC_STEP,
266b4890
AP		 2898 ALTIVEC_BUILTIN_VEC_PROMOTE,
2899 ALTIVEC_BUILTIN_VEC_INSERT,
2900 ALTIVEC_BUILTIN_VEC_SPLATS,
2901 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_SPLATS,
58646b77 2902
a3170dc6 2903 /* SPE builtins. */
8bb418a3 2904 SPE_BUILTIN_EVADDW,
a3170dc6
AH		 2905 SPE_BUILTIN_EVAND,
2906 SPE_BUILTIN_EVANDC,
2907 SPE_BUILTIN_EVDIVWS,
2908 SPE_BUILTIN_EVDIVWU,
2909 SPE_BUILTIN_EVEQV,
2910 SPE_BUILTIN_EVFSADD,
2911 SPE_BUILTIN_EVFSDIV,
2912 SPE_BUILTIN_EVFSMUL,
2913 SPE_BUILTIN_EVFSSUB,
2914 SPE_BUILTIN_EVLDDX,
2915 SPE_BUILTIN_EVLDHX,
2916 SPE_BUILTIN_EVLDWX,
2917 SPE_BUILTIN_EVLHHESPLATX,
2918 SPE_BUILTIN_EVLHHOSSPLATX,
2919 SPE_BUILTIN_EVLHHOUSPLATX,
2920 SPE_BUILTIN_EVLWHEX,
2921 SPE_BUILTIN_EVLWHOSX,
2922 SPE_BUILTIN_EVLWHOUX,
2923 SPE_BUILTIN_EVLWHSPLATX,
2924 SPE_BUILTIN_EVLWWSPLATX,
2925 SPE_BUILTIN_EVMERGEHI,
2926 SPE_BUILTIN_EVMERGEHILO,
2927 SPE_BUILTIN_EVMERGELO,
2928 SPE_BUILTIN_EVMERGELOHI,
2929 SPE_BUILTIN_EVMHEGSMFAA,
2930 SPE_BUILTIN_EVMHEGSMFAN,
2931 SPE_BUILTIN_EVMHEGSMIAA,
2932 SPE_BUILTIN_EVMHEGSMIAN,
2933 SPE_BUILTIN_EVMHEGUMIAA,
2934 SPE_BUILTIN_EVMHEGUMIAN,
2935 SPE_BUILTIN_EVMHESMF,
2936 SPE_BUILTIN_EVMHESMFA,
2937 SPE_BUILTIN_EVMHESMFAAW,
2938 SPE_BUILTIN_EVMHESMFANW,
2939 SPE_BUILTIN_EVMHESMI,
2940 SPE_BUILTIN_EVMHESMIA,
2941 SPE_BUILTIN_EVMHESMIAAW,
2942 SPE_BUILTIN_EVMHESMIANW,
2943 SPE_BUILTIN_EVMHESSF,
2944 SPE_BUILTIN_EVMHESSFA,
2945 SPE_BUILTIN_EVMHESSFAAW,
2946 SPE_BUILTIN_EVMHESSFANW,
2947 SPE_BUILTIN_EVMHESSIAAW,
2948 SPE_BUILTIN_EVMHESSIANW,
2949 SPE_BUILTIN_EVMHEUMI,
2950 SPE_BUILTIN_EVMHEUMIA,
2951 SPE_BUILTIN_EVMHEUMIAAW,
2952 SPE_BUILTIN_EVMHEUMIANW,
2953 SPE_BUILTIN_EVMHEUSIAAW,
2954 SPE_BUILTIN_EVMHEUSIANW,
2955 SPE_BUILTIN_EVMHOGSMFAA,
2956 SPE_BUILTIN_EVMHOGSMFAN,
2957 SPE_BUILTIN_EVMHOGSMIAA,
2958 SPE_BUILTIN_EVMHOGSMIAN,
2959 SPE_BUILTIN_EVMHOGUMIAA,
2960 SPE_BUILTIN_EVMHOGUMIAN,
2961 SPE_BUILTIN_EVMHOSMF,
2962 SPE_BUILTIN_EVMHOSMFA,
2963 SPE_BUILTIN_EVMHOSMFAAW,
2964 SPE_BUILTIN_EVMHOSMFANW,
2965 SPE_BUILTIN_EVMHOSMI,
2966 SPE_BUILTIN_EVMHOSMIA,
2967 SPE_BUILTIN_EVMHOSMIAAW,
2968 SPE_BUILTIN_EVMHOSMIANW,
2969 SPE_BUILTIN_EVMHOSSF,
2970 SPE_BUILTIN_EVMHOSSFA,
2971 SPE_BUILTIN_EVMHOSSFAAW,
2972 SPE_BUILTIN_EVMHOSSFANW,
2973 SPE_BUILTIN_EVMHOSSIAAW,
2974 SPE_BUILTIN_EVMHOSSIANW,
2975 SPE_BUILTIN_EVMHOUMI,
2976 SPE_BUILTIN_EVMHOUMIA,
2977 SPE_BUILTIN_EVMHOUMIAAW,
2978 SPE_BUILTIN_EVMHOUMIANW,
2979 SPE_BUILTIN_EVMHOUSIAAW,
2980 SPE_BUILTIN_EVMHOUSIANW,
2981 SPE_BUILTIN_EVMWHSMF,
2982 SPE_BUILTIN_EVMWHSMFA,
2983 SPE_BUILTIN_EVMWHSMI,
2984 SPE_BUILTIN_EVMWHSMIA,
2985 SPE_BUILTIN_EVMWHSSF,
2986 SPE_BUILTIN_EVMWHSSFA,
2987 SPE_BUILTIN_EVMWHUMI,
2988 SPE_BUILTIN_EVMWHUMIA,
a3170dc6
AH		 2989 SPE_BUILTIN_EVMWLSMIAAW,
2990 SPE_BUILTIN_EVMWLSMIANW,
a3170dc6
AH		 2991 SPE_BUILTIN_EVMWLSSIAAW,
2992 SPE_BUILTIN_EVMWLSSIANW,
2993 SPE_BUILTIN_EVMWLUMI,
2994 SPE_BUILTIN_EVMWLUMIA,
2995 SPE_BUILTIN_EVMWLUMIAAW,
2996 SPE_BUILTIN_EVMWLUMIANW,
2997 SPE_BUILTIN_EVMWLUSIAAW,
2998 SPE_BUILTIN_EVMWLUSIANW,
2999 SPE_BUILTIN_EVMWSMF,
3000 SPE_BUILTIN_EVMWSMFA,
3001 SPE_BUILTIN_EVMWSMFAA,
3002 SPE_BUILTIN_EVMWSMFAN,
3003 SPE_BUILTIN_EVMWSMI,
3004 SPE_BUILTIN_EVMWSMIA,
3005 SPE_BUILTIN_EVMWSMIAA,
3006 SPE_BUILTIN_EVMWSMIAN,
3007 SPE_BUILTIN_EVMWHSSFAA,
3008 SPE_BUILTIN_EVMWSSF,
3009 SPE_BUILTIN_EVMWSSFA,
3010 SPE_BUILTIN_EVMWSSFAA,
3011 SPE_BUILTIN_EVMWSSFAN,
3012 SPE_BUILTIN_EVMWUMI,
3013 SPE_BUILTIN_EVMWUMIA,
3014 SPE_BUILTIN_EVMWUMIAA,
3015 SPE_BUILTIN_EVMWUMIAN,
3016 SPE_BUILTIN_EVNAND,
3017 SPE_BUILTIN_EVNOR,
3018 SPE_BUILTIN_EVOR,
3019 SPE_BUILTIN_EVORC,
3020 SPE_BUILTIN_EVRLW,
3021 SPE_BUILTIN_EVSLW,
3022 SPE_BUILTIN_EVSRWS,
3023 SPE_BUILTIN_EVSRWU,
3024 SPE_BUILTIN_EVSTDDX,
3025 SPE_BUILTIN_EVSTDHX,
3026 SPE_BUILTIN_EVSTDWX,
3027 SPE_BUILTIN_EVSTWHEX,
3028 SPE_BUILTIN_EVSTWHOX,
3029 SPE_BUILTIN_EVSTWWEX,
3030 SPE_BUILTIN_EVSTWWOX,
3031 SPE_BUILTIN_EVSUBFW,
3032 SPE_BUILTIN_EVXOR,
3033 SPE_BUILTIN_EVABS,
3034 SPE_BUILTIN_EVADDSMIAAW,
3035 SPE_BUILTIN_EVADDSSIAAW,
3036 SPE_BUILTIN_EVADDUMIAAW,
3037 SPE_BUILTIN_EVADDUSIAAW,
3038 SPE_BUILTIN_EVCNTLSW,
3039 SPE_BUILTIN_EVCNTLZW,
3040 SPE_BUILTIN_EVEXTSB,
3041 SPE_BUILTIN_EVEXTSH,
3042 SPE_BUILTIN_EVFSABS,
3043 SPE_BUILTIN_EVFSCFSF,
3044 SPE_BUILTIN_EVFSCFSI,
3045 SPE_BUILTIN_EVFSCFUF,
3046 SPE_BUILTIN_EVFSCFUI,
3047 SPE_BUILTIN_EVFSCTSF,
3048 SPE_BUILTIN_EVFSCTSI,
3049 SPE_BUILTIN_EVFSCTSIZ,
3050 SPE_BUILTIN_EVFSCTUF,
3051 SPE_BUILTIN_EVFSCTUI,
3052 SPE_BUILTIN_EVFSCTUIZ,
3053 SPE_BUILTIN_EVFSNABS,
3054 SPE_BUILTIN_EVFSNEG,
3055 SPE_BUILTIN_EVMRA,
3056 SPE_BUILTIN_EVNEG,
3057 SPE_BUILTIN_EVRNDW,
3058 SPE_BUILTIN_EVSUBFSMIAAW,
3059 SPE_BUILTIN_EVSUBFSSIAAW,
3060 SPE_BUILTIN_EVSUBFUMIAAW,
3061 SPE_BUILTIN_EVSUBFUSIAAW,
3062 SPE_BUILTIN_EVADDIW,
3063 SPE_BUILTIN_EVLDD,
3064 SPE_BUILTIN_EVLDH,
3065 SPE_BUILTIN_EVLDW,
3066 SPE_BUILTIN_EVLHHESPLAT,
3067 SPE_BUILTIN_EVLHHOSSPLAT,
3068 SPE_BUILTIN_EVLHHOUSPLAT,
3069 SPE_BUILTIN_EVLWHE,
3070 SPE_BUILTIN_EVLWHOS,
3071 SPE_BUILTIN_EVLWHOU,
3072 SPE_BUILTIN_EVLWHSPLAT,
3073 SPE_BUILTIN_EVLWWSPLAT,
3074 SPE_BUILTIN_EVRLWI,
3075 SPE_BUILTIN_EVSLWI,
3076 SPE_BUILTIN_EVSRWIS,
3077 SPE_BUILTIN_EVSRWIU,
3078 SPE_BUILTIN_EVSTDD,
3079 SPE_BUILTIN_EVSTDH,
3080 SPE_BUILTIN_EVSTDW,
3081 SPE_BUILTIN_EVSTWHE,
3082 SPE_BUILTIN_EVSTWHO,
3083 SPE_BUILTIN_EVSTWWE,
3084 SPE_BUILTIN_EVSTWWO,
3085 SPE_BUILTIN_EVSUBIFW,
3086
3087 /* Compares. */
3088 SPE_BUILTIN_EVCMPEQ,
3089 SPE_BUILTIN_EVCMPGTS,
3090 SPE_BUILTIN_EVCMPGTU,
3091 SPE_BUILTIN_EVCMPLTS,
3092 SPE_BUILTIN_EVCMPLTU,
3093 SPE_BUILTIN_EVFSCMPEQ,
3094 SPE_BUILTIN_EVFSCMPGT,
3095 SPE_BUILTIN_EVFSCMPLT,
3096 SPE_BUILTIN_EVFSTSTEQ,
3097 SPE_BUILTIN_EVFSTSTGT,
3098 SPE_BUILTIN_EVFSTSTLT,
3099
3100 /* EVSEL compares. */
3101 SPE_BUILTIN_EVSEL_CMPEQ,
3102 SPE_BUILTIN_EVSEL_CMPGTS,
3103 SPE_BUILTIN_EVSEL_CMPGTU,
3104 SPE_BUILTIN_EVSEL_CMPLTS,
3105 SPE_BUILTIN_EVSEL_CMPLTU,
3106 SPE_BUILTIN_EVSEL_FSCMPEQ,
3107 SPE_BUILTIN_EVSEL_FSCMPGT,
3108 SPE_BUILTIN_EVSEL_FSCMPLT,
3109 SPE_BUILTIN_EVSEL_FSTSTEQ,
3110 SPE_BUILTIN_EVSEL_FSTSTGT,
3111 SPE_BUILTIN_EVSEL_FSTSTLT,
3112
3113 SPE_BUILTIN_EVSPLATFI,
3114 SPE_BUILTIN_EVSPLATI,
3115 SPE_BUILTIN_EVMWHSSMAA,
3116 SPE_BUILTIN_EVMWHSMFAA,
3117 SPE_BUILTIN_EVMWHSMIAA,
3118 SPE_BUILTIN_EVMWHUSIAA,
3119 SPE_BUILTIN_EVMWHUMIAA,
3120 SPE_BUILTIN_EVMWHSSFAN,
3121 SPE_BUILTIN_EVMWHSSIAN,
3122 SPE_BUILTIN_EVMWHSMFAN,
3123 SPE_BUILTIN_EVMWHSMIAN,
3124 SPE_BUILTIN_EVMWHUSIAN,
3125 SPE_BUILTIN_EVMWHUMIAN,
3126 SPE_BUILTIN_EVMWHGSSFAA,
3127 SPE_BUILTIN_EVMWHGSMFAA,
3128 SPE_BUILTIN_EVMWHGSMIAA,
3129 SPE_BUILTIN_EVMWHGUMIAA,
3130 SPE_BUILTIN_EVMWHGSSFAN,
3131 SPE_BUILTIN_EVMWHGSMFAN,
3132 SPE_BUILTIN_EVMWHGSMIAN,
3133 SPE_BUILTIN_EVMWHGUMIAN,
3134 SPE_BUILTIN_MTSPEFSCR,
3135 SPE_BUILTIN_MFSPEFSCR,
58646b77
PB		 3136 SPE_BUILTIN_BRINC,
3137
96038623
DE		 3138 /* PAIRED builtins. */
3139 PAIRED_BUILTIN_DIVV2SF3,
3140 PAIRED_BUILTIN_ABSV2SF2,
3141 PAIRED_BUILTIN_NEGV2SF2,
3142 PAIRED_BUILTIN_SQRTV2SF2,
3143 PAIRED_BUILTIN_ADDV2SF3,
3144 PAIRED_BUILTIN_SUBV2SF3,
3145 PAIRED_BUILTIN_RESV2SF2,
3146 PAIRED_BUILTIN_MULV2SF3,
3147 PAIRED_BUILTIN_MSUB,
3148 PAIRED_BUILTIN_MADD,
3149 PAIRED_BUILTIN_NMSUB,
3150 PAIRED_BUILTIN_NMADD,
3151 PAIRED_BUILTIN_NABSV2SF2,
3152 PAIRED_BUILTIN_SUM0,
3153 PAIRED_BUILTIN_SUM1,
3154 PAIRED_BUILTIN_MULS0,
3155 PAIRED_BUILTIN_MULS1,
3156 PAIRED_BUILTIN_MERGE00,
3157 PAIRED_BUILTIN_MERGE01,
3158 PAIRED_BUILTIN_MERGE10,
3159 PAIRED_BUILTIN_MERGE11,
3160 PAIRED_BUILTIN_MADDS0,
3161 PAIRED_BUILTIN_MADDS1,
3162 PAIRED_BUILTIN_STX,
3163 PAIRED_BUILTIN_LX,
49e39588 3164 PAIRED_BUILTIN_SELV2SF4,
96038623
DE		 3165 PAIRED_BUILTIN_CMPU0,
3166 PAIRED_BUILTIN_CMPU1,
3167
9c78b944
DE		 3168 RS6000_BUILTIN_RECIP,
3169 RS6000_BUILTIN_RECIPF,
3170 RS6000_BUILTIN_RSQRTF,
8beb65e3 3171 RS6000_BUILTIN_BSWAP_HI,
9c78b944 3172
a72c65c7 3173 /* VSX builtins. */
a72c65c7 3174 VSX_BUILTIN_LXSDX,
a72c65c7
MM		 3175 VSX_BUILTIN_LXVD2X,
3176 VSX_BUILTIN_LXVDSX,
a72c65c7 3177 VSX_BUILTIN_LXVW4X,
a72c65c7 3178 VSX_BUILTIN_STXSDX,
a72c65c7 3179 VSX_BUILTIN_STXVD2X,
a72c65c7
MM		 3180 VSX_BUILTIN_STXVW4X,
3181 VSX_BUILTIN_XSABSDP,
3182 VSX_BUILTIN_XSADDDP,
3183 VSX_BUILTIN_XSCMPODP,
3184 VSX_BUILTIN_XSCMPUDP,
3185 VSX_BUILTIN_XSCPSGNDP,
3186 VSX_BUILTIN_XSCVDPSP,
3187 VSX_BUILTIN_XSCVDPSXDS,
3188 VSX_BUILTIN_XSCVDPSXWS,
3189 VSX_BUILTIN_XSCVDPUXDS,
3190 VSX_BUILTIN_XSCVDPUXWS,
3191 VSX_BUILTIN_XSCVSPDP,
3192 VSX_BUILTIN_XSCVSXDDP,
3193 VSX_BUILTIN_XSCVUXDDP,
3194 VSX_BUILTIN_XSDIVDP,
3195 VSX_BUILTIN_XSMADDADP,
3196 VSX_BUILTIN_XSMADDMDP,
3197 VSX_BUILTIN_XSMAXDP,
3198 VSX_BUILTIN_XSMINDP,
3199 VSX_BUILTIN_XSMOVDP,
3200 VSX_BUILTIN_XSMSUBADP,
3201 VSX_BUILTIN_XSMSUBMDP,
3202 VSX_BUILTIN_XSMULDP,
3203 VSX_BUILTIN_XSNABSDP,
3204 VSX_BUILTIN_XSNEGDP,
3205 VSX_BUILTIN_XSNMADDADP,
3206 VSX_BUILTIN_XSNMADDMDP,
3207 VSX_BUILTIN_XSNMSUBADP,
3208 VSX_BUILTIN_XSNMSUBMDP,
3209 VSX_BUILTIN_XSRDPI,
3210 VSX_BUILTIN_XSRDPIC,
3211 VSX_BUILTIN_XSRDPIM,
3212 VSX_BUILTIN_XSRDPIP,
3213 VSX_BUILTIN_XSRDPIZ,
3214 VSX_BUILTIN_XSREDP,
3215 VSX_BUILTIN_XSRSQRTEDP,
3216 VSX_BUILTIN_XSSQRTDP,
3217 VSX_BUILTIN_XSSUBDP,
29e6733c
MM		 3218 VSX_BUILTIN_CPSGNDP,
3219 VSX_BUILTIN_CPSGNSP,
a72c65c7
MM		 3220 VSX_BUILTIN_XSTDIVDP_FE,
3221 VSX_BUILTIN_XSTDIVDP_FG,
3222 VSX_BUILTIN_XSTSQRTDP_FE,
3223 VSX_BUILTIN_XSTSQRTDP_FG,
3224 VSX_BUILTIN_XVABSDP,
3225 VSX_BUILTIN_XVABSSP,
3226 VSX_BUILTIN_XVADDDP,
3227 VSX_BUILTIN_XVADDSP,
3228 VSX_BUILTIN_XVCMPEQDP,
3229 VSX_BUILTIN_XVCMPEQSP,
3230 VSX_BUILTIN_XVCMPGEDP,
3231 VSX_BUILTIN_XVCMPGESP,
3232 VSX_BUILTIN_XVCMPGTDP,
3233 VSX_BUILTIN_XVCMPGTSP,
3234 VSX_BUILTIN_XVCMPEQDP_P,
3235 VSX_BUILTIN_XVCMPEQSP_P,
3236 VSX_BUILTIN_XVCMPGEDP_P,
3237 VSX_BUILTIN_XVCMPGESP_P,
3238 VSX_BUILTIN_XVCMPGTDP_P,
3239 VSX_BUILTIN_XVCMPGTSP_P,
3240 VSX_BUILTIN_XVCPSGNDP,
3241 VSX_BUILTIN_XVCPSGNSP,
3242 VSX_BUILTIN_XVCVDPSP,
3243 VSX_BUILTIN_XVCVDPSXDS,
3244 VSX_BUILTIN_XVCVDPSXWS,
3245 VSX_BUILTIN_XVCVDPUXDS,
3246 VSX_BUILTIN_XVCVDPUXDS_UNS,
3247 VSX_BUILTIN_XVCVDPUXWS,
3248 VSX_BUILTIN_XVCVSPDP,
3249 VSX_BUILTIN_XVCVSPSXDS,
3250 VSX_BUILTIN_XVCVSPSXWS,
3251 VSX_BUILTIN_XVCVSPUXDS,
3252 VSX_BUILTIN_XVCVSPUXWS,
3253 VSX_BUILTIN_XVCVSXDDP,
3254 VSX_BUILTIN_XVCVSXDSP,
3255 VSX_BUILTIN_XVCVSXWDP,
3256 VSX_BUILTIN_XVCVSXWSP,
3257 VSX_BUILTIN_XVCVUXDDP,
3258 VSX_BUILTIN_XVCVUXDDP_UNS,
3259 VSX_BUILTIN_XVCVUXDSP,
3260 VSX_BUILTIN_XVCVUXWDP,
3261 VSX_BUILTIN_XVCVUXWSP,
3262 VSX_BUILTIN_XVDIVDP,
3263 VSX_BUILTIN_XVDIVSP,
3264 VSX_BUILTIN_XVMADDDP,
3265 VSX_BUILTIN_XVMADDSP,
3266 VSX_BUILTIN_XVMAXDP,
3267 VSX_BUILTIN_XVMAXSP,
3268 VSX_BUILTIN_XVMINDP,
3269 VSX_BUILTIN_XVMINSP,
3270 VSX_BUILTIN_XVMSUBDP,
3271 VSX_BUILTIN_XVMSUBSP,
3272 VSX_BUILTIN_XVMULDP,
3273 VSX_BUILTIN_XVMULSP,
3274 VSX_BUILTIN_XVNABSDP,
3275 VSX_BUILTIN_XVNABSSP,
3276 VSX_BUILTIN_XVNEGDP,
3277 VSX_BUILTIN_XVNEGSP,
3278 VSX_BUILTIN_XVNMADDDP,
3279 VSX_BUILTIN_XVNMADDSP,
3280 VSX_BUILTIN_XVNMSUBDP,
3281 VSX_BUILTIN_XVNMSUBSP,
3282 VSX_BUILTIN_XVRDPI,
3283 VSX_BUILTIN_XVRDPIC,
3284 VSX_BUILTIN_XVRDPIM,
3285 VSX_BUILTIN_XVRDPIP,
3286 VSX_BUILTIN_XVRDPIZ,
3287 VSX_BUILTIN_XVREDP,
3288 VSX_BUILTIN_XVRESP,
3289 VSX_BUILTIN_XVRSPI,
3290 VSX_BUILTIN_XVRSPIC,
3291 VSX_BUILTIN_XVRSPIM,
3292 VSX_BUILTIN_XVRSPIP,
3293 VSX_BUILTIN_XVRSPIZ,
3294 VSX_BUILTIN_XVRSQRTEDP,
3295 VSX_BUILTIN_XVRSQRTESP,
3296 VSX_BUILTIN_XVSQRTDP,
3297 VSX_BUILTIN_XVSQRTSP,
3298 VSX_BUILTIN_XVSUBDP,
3299 VSX_BUILTIN_XVSUBSP,
3300 VSX_BUILTIN_XVTDIVDP_FE,
3301 VSX_BUILTIN_XVTDIVDP_FG,
3302 VSX_BUILTIN_XVTDIVSP_FE,
3303 VSX_BUILTIN_XVTDIVSP_FG,
3304 VSX_BUILTIN_XVTSQRTDP_FE,
3305 VSX_BUILTIN_XVTSQRTDP_FG,
3306 VSX_BUILTIN_XVTSQRTSP_FE,
3307 VSX_BUILTIN_XVTSQRTSP_FG,
3308 VSX_BUILTIN_XXSEL_2DI,
3309 VSX_BUILTIN_XXSEL_2DF,
3310 VSX_BUILTIN_XXSEL_4SI,
3311 VSX_BUILTIN_XXSEL_4SF,
3312 VSX_BUILTIN_XXSEL_8HI,
3313 VSX_BUILTIN_XXSEL_16QI,
3314 VSX_BUILTIN_XXSEL_2DI_UNS,
3315 VSX_BUILTIN_XXSEL_4SI_UNS,
3316 VSX_BUILTIN_XXSEL_8HI_UNS,
3317 VSX_BUILTIN_XXSEL_16QI_UNS,
3318 VSX_BUILTIN_VPERM_2DI,
3319 VSX_BUILTIN_VPERM_2DF,
3320 VSX_BUILTIN_VPERM_4SI,
3321 VSX_BUILTIN_VPERM_4SF,
3322 VSX_BUILTIN_VPERM_8HI,
3323 VSX_BUILTIN_VPERM_16QI,
3324 VSX_BUILTIN_VPERM_2DI_UNS,
3325 VSX_BUILTIN_VPERM_4SI_UNS,
3326 VSX_BUILTIN_VPERM_8HI_UNS,
3327 VSX_BUILTIN_VPERM_16QI_UNS,
3328 VSX_BUILTIN_XXPERMDI_2DF,
3329 VSX_BUILTIN_XXPERMDI_2DI,
3330 VSX_BUILTIN_XXPERMDI_4SF,
3331 VSX_BUILTIN_XXPERMDI_4SI,
3332 VSX_BUILTIN_XXPERMDI_8HI,
3333 VSX_BUILTIN_XXPERMDI_16QI,
3334 VSX_BUILTIN_CONCAT_2DF,
3335 VSX_BUILTIN_CONCAT_2DI,
3336 VSX_BUILTIN_SET_2DF,
3337 VSX_BUILTIN_SET_2DI,
3338 VSX_BUILTIN_SPLAT_2DF,
3339 VSX_BUILTIN_SPLAT_2DI,
3340 VSX_BUILTIN_XXMRGHW_4SF,
3341 VSX_BUILTIN_XXMRGHW_4SI,
3342 VSX_BUILTIN_XXMRGLW_4SF,
3343 VSX_BUILTIN_XXMRGLW_4SI,
3344 VSX_BUILTIN_XXSLDWI_16QI,
3345 VSX_BUILTIN_XXSLDWI_8HI,
3346 VSX_BUILTIN_XXSLDWI_4SI,
3347 VSX_BUILTIN_XXSLDWI_4SF,
3348 VSX_BUILTIN_XXSLDWI_2DI,
3349 VSX_BUILTIN_XXSLDWI_2DF,
3350 VSX_BUILTIN_VEC_INIT_V2DF,
3351 VSX_BUILTIN_VEC_INIT_V2DI,
3352 VSX_BUILTIN_VEC_SET_V2DF,
3353 VSX_BUILTIN_VEC_SET_V2DI,
3354 VSX_BUILTIN_VEC_EXT_V2DF,
3355 VSX_BUILTIN_VEC_EXT_V2DI,
3356
3357 /* VSX overloaded builtins, add the overloaded functions not present in
3358 Altivec. */
3359 VSX_BUILTIN_VEC_MUL,
3360 VSX_BUILTIN_OVERLOADED_FIRST = VSX_BUILTIN_VEC_MUL,
3361 VSX_BUILTIN_VEC_MSUB,
3362 VSX_BUILTIN_VEC_NMADD,
3363 VSX_BUITLIN_VEC_NMSUB,
3364 VSX_BUILTIN_VEC_DIV,
3365 VSX_BUILTIN_VEC_XXMRGHW,
3366 VSX_BUILTIN_VEC_XXMRGLW,
3367 VSX_BUILTIN_VEC_XXPERMDI,
3368 VSX_BUILTIN_VEC_XXSLDWI,
3369 VSX_BUILTIN_VEC_XXSPLTD,
3370 VSX_BUILTIN_VEC_XXSPLTW,
3371 VSX_BUILTIN_OVERLOADED_LAST = VSX_BUILTIN_VEC_XXSPLTW,
3372
3373 /* Combined VSX/Altivec builtins. */
3374 VECTOR_BUILTIN_FLOAT_V4SI_V4SF,
3375 VECTOR_BUILTIN_UNSFLOAT_V4SI_V4SF,
3376 VECTOR_BUILTIN_FIX_V4SF_V4SI,
3377 VECTOR_BUILTIN_FIXUNS_V4SF_V4SI,
3378
3379 /* Power7 builtins, that aren't VSX instructions. */
3380 POWER7_BUILTIN_BPERMD,
3381
58646b77
PB		 3382 RS6000_BUILTIN_COUNT
3383};
3384
3385enum rs6000_builtin_type_index
3386{
3387 RS6000_BTI_NOT_OPAQUE,
3388 RS6000_BTI_opaque_V2SI,
3389 RS6000_BTI_opaque_V2SF,
3390 RS6000_BTI_opaque_p_V2SI,
3391 RS6000_BTI_opaque_V4SI,
3392 RS6000_BTI_V16QI,
3393 RS6000_BTI_V2SI,
3394 RS6000_BTI_V2SF,
a72c65c7
MM		 3395 RS6000_BTI_V2DI,
3396 RS6000_BTI_V2DF,
58646b77
PB		 3397 RS6000_BTI_V4HI,
3398 RS6000_BTI_V4SI,
3399 RS6000_BTI_V4SF,
3400 RS6000_BTI_V8HI,
3401 RS6000_BTI_unsigned_V16QI,
3402 RS6000_BTI_unsigned_V8HI,
3403 RS6000_BTI_unsigned_V4SI,
a72c65c7 3404 RS6000_BTI_unsigned_V2DI,
58646b77
PB		 3405 RS6000_BTI_bool_char, /* __bool char */
3406 RS6000_BTI_bool_short, /* __bool short */
3407 RS6000_BTI_bool_int, /* __bool int */
a72c65c7 3408 RS6000_BTI_bool_long, /* __bool long */
58646b77
PB		 3409 RS6000_BTI_pixel, /* __pixel */
3410 RS6000_BTI_bool_V16QI, /* __vector __bool char */
3411 RS6000_BTI_bool_V8HI, /* __vector __bool short */
3412 RS6000_BTI_bool_V4SI, /* __vector __bool int */
a72c65c7 3413 RS6000_BTI_bool_V2DI, /* __vector __bool long */
58646b77
PB		 3414 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
3415 RS6000_BTI_long, /* long_integer_type_node */
3416 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
3417 RS6000_BTI_INTQI, /* intQI_type_node */
3418 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
3419 RS6000_BTI_INTHI, /* intHI_type_node */
3420 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
3421 RS6000_BTI_INTSI, /* intSI_type_node */
3422 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
a72c65c7
MM		 3423 RS6000_BTI_INTDI, /* intDI_type_node */
3424 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
58646b77 3425 RS6000_BTI_float, /* float_type_node */
a72c65c7 3426 RS6000_BTI_double, /* double_type_node */
58646b77
PB		 3427 RS6000_BTI_void, /* void_type_node */
3428 RS6000_BTI_MAX
0ac081f6 3429};
58646b77
PB		 3430
3431
3432#define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
3433#define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
3434#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
3435#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
3436#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
a72c65c7
MM		 3437#define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
3438#define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
58646b77
PB		 3439#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
3440#define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
3441#define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
3442#define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
3443#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
3444#define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
3445#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
3446#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
3447#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
a72c65c7 3448#define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
58646b77
PB		 3449#define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
3450#define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
3451#define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
a72c65c7 3452#define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
58646b77
PB		 3453#define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
3454#define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
3455#define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
3456#define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
a72c65c7 3457#define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
58646b77
PB		 3458#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
3459
3460#define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
3461#define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
3462#define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
3463#define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
3464#define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
3465#define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
3466#define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
3467#define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
a72c65c7
MM		 3468#define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
3469#define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
58646b77 3470#define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
a72c65c7 3471#define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
58646b77
PB		 3472#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
3473
3474extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
3475extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
3476
Mirror of https://gcc.gnu.org/git/gcc.git