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config.gcc (avr-*-rtems*, avr-*-*): Set extra_gcc_objs and extra_objs.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.h
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f045b2c9 1/* Definitions of target machine for GNU compiler, for IBM RS/6000.
9ebbca7d 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
748086b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
602ea4d3 4 Free Software Foundation, Inc.
6a7ec0a7 5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
f045b2c9 6
5de601cf 7 This file is part of GCC.
f045b2c9 8
5de601cf
NC		 9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
2f83c7d6 11 by the Free Software Foundation; either version 3, or (at your
5de601cf 12 option) any later version.
f045b2c9 13
5de601cf
NC		 14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
f045b2c9 18
748086b7
JJ		 19 Under Section 7 of GPL version 3, you are granted additional
20 permissions described in the GCC Runtime Library Exception, version
21 3.1, as published by the Free Software Foundation.
22
23 You should have received a copy of the GNU General Public License and
24 a copy of the GCC Runtime Library Exception along with this program;
25 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2f83c7d6 26 <http://www.gnu.org/licenses/>. */
f045b2c9
RS		 27
28/* Note that some other tm.h files include this one and then override
9ebbca7d 29 many of the definitions. */
f045b2c9 30
9ebbca7d
GK		 31/* Definitions for the object file format. These are set at
32 compile-time. */
f045b2c9 33
9ebbca7d
GK		 34#define OBJECT_XCOFF 1
35#define OBJECT_ELF 2
36#define OBJECT_PEF 3
ee890fe2 37#define OBJECT_MACHO 4
f045b2c9 38
9ebbca7d 39#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
2bfcf297 40#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
9ebbca7d 41#define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
ee890fe2 42#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
f045b2c9 43
2bfcf297
DB		 44#ifndef TARGET_AIX
45#define TARGET_AIX 0
46#endif
47
85b776df
AM		 48/* Control whether function entry points use a "dot" symbol when
49 ABI_AIX. */
50#define DOT_SYMBOLS 1
51
8e3f41e7
MM		 52/* Default string to use for cpu if not specified. */
53#ifndef TARGET_CPU_DEFAULT
54#define TARGET_CPU_DEFAULT ((char *)0)
55#endif
56
f565b0a1 57/* If configured for PPC405, support PPC405CR Erratum77. */
b0bfee6e 58#ifdef CONFIG_PPC405CR
f565b0a1
DE		 59#define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
60#else
61#define PPC405_ERRATUM77 0
62#endif
63
96038623
DE		 64#ifndef TARGET_PAIRED_FLOAT
65#define TARGET_PAIRED_FLOAT 0
66#endif
67
cd679487
BE		 68#ifdef HAVE_AS_POPCNTB
69#define ASM_CPU_POWER5_SPEC "-mpower5"
70#else
71#define ASM_CPU_POWER5_SPEC "-mpower4"
72#endif
73
74#ifdef HAVE_AS_DFP
75#define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
76#else
77#define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
78#endif
79
d40c9e33
PB		 80#ifdef HAVE_AS_VSX
81#define ASM_CPU_POWER7_SPEC "-mpower7"
82#else
83#define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
84#endif
85
f984d8df
DB		 86/* Common ASM definitions used by ASM_SPEC among the various targets
87 for handling -mcpu=xxx switches. */
88#define ASM_CPU_SPEC \
89"%{!mcpu*: \
90 %{mpower: %{!mpower2: -mpwr}} \
91 %{mpower2: -mpwrx} \
93ae5495
AM		 92 %{mpowerpc64*: -mppc64} \
93 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
f984d8df 94 %{mno-power: %{!mpowerpc*: -mcom}} \
93ae5495 95 %{!mno-power: %{!mpower*: %(asm_default)}}} \
f984d8df 96%{mcpu=common: -mcom} \
d296e02e 97%{mcpu=cell: -mcell} \
f984d8df
DB		 98%{mcpu=power: -mpwr} \
99%{mcpu=power2: -mpwrx} \
93ae5495 100%{mcpu=power3: -mppc64} \
957e9e48 101%{mcpu=power4: -mpower4} \
cd679487
BE		 102%{mcpu=power5: %(asm_cpu_power5)} \
103%{mcpu=power5+: %(asm_cpu_power5)} \
104%{mcpu=power6: %(asm_cpu_power6) -maltivec} \
105%{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
d40c9e33 106%{mcpu=power7: %(asm_cpu_power7)} \
f984d8df
DB		 107%{mcpu=powerpc: -mppc} \
108%{mcpu=rios: -mpwr} \
109%{mcpu=rios1: -mpwr} \
110%{mcpu=rios2: -mpwrx} \
111%{mcpu=rsc: -mpwr} \
112%{mcpu=rsc1: -mpwr} \
93ae5495 113%{mcpu=rs64a: -mppc64} \
f984d8df 114%{mcpu=401: -mppc} \
61a8515c
JS		 115%{mcpu=403: -m403} \
116%{mcpu=405: -m405} \
2c9d95ef
DE		 117%{mcpu=405fp: -m405} \
118%{mcpu=440: -m440} \
119%{mcpu=440fp: -m440} \
4adf8008
PB		 120%{mcpu=464: -m440} \
121%{mcpu=464fp: -m440} \
f984d8df
DB		 122%{mcpu=505: -mppc} \
123%{mcpu=601: -m601} \
124%{mcpu=602: -mppc} \
125%{mcpu=603: -mppc} \
126%{mcpu=603e: -mppc} \
127%{mcpu=ec603e: -mppc} \
128%{mcpu=604: -mppc} \
129%{mcpu=604e: -mppc} \
93ae5495
AM		 130%{mcpu=620: -mppc64} \
131%{mcpu=630: -mppc64} \
f984d8df
DB		 132%{mcpu=740: -mppc} \
133%{mcpu=750: -mppc} \
49ffe578 134%{mcpu=G3: -mppc} \
93ae5495
AM		 135%{mcpu=7400: -mppc -maltivec} \
136%{mcpu=7450: -mppc -maltivec} \
137%{mcpu=G4: -mppc -maltivec} \
f984d8df
DB		 138%{mcpu=801: -mppc} \
139%{mcpu=821: -mppc} \
140%{mcpu=823: -mppc} \
775db490 141%{mcpu=860: -mppc} \
93ae5495
AM		 142%{mcpu=970: -mpower4 -maltivec} \
143%{mcpu=G5: -mpower4 -maltivec} \
a3170dc6 144%{mcpu=8540: -me500} \
5ca0373f 145%{mcpu=8548: -me500} \
fa41c305
EW		 146%{mcpu=e300c2: -me300} \
147%{mcpu=e300c3: -me300} \
edae5fe3 148%{mcpu=e500mc: -me500mc} \
93ae5495
AM		 149%{maltivec: -maltivec} \
150-many"
f984d8df
DB		 151
152#define CPP_DEFAULT_SPEC ""
153
154#define ASM_DEFAULT_SPEC ""
155
841faeed
MM		 156/* This macro defines names of additional specifications to put in the specs
157 that can be used in various specifications like CC1_SPEC. Its definition
158 is an initializer with a subgrouping for each command option.
159
160 Each subgrouping contains a string constant, that defines the
5de601cf 161 specification name, and a string constant that used by the GCC driver
841faeed
MM		 162 program.
163
164 Do not define this macro if it does not need to do anything. */
165
7509c759 166#define SUBTARGET_EXTRA_SPECS
7509c759 167
c81bebd7 168#define EXTRA_SPECS \
c81bebd7 169 { "cpp_default", CPP_DEFAULT_SPEC }, \
c81bebd7
MM		 170 { "asm_cpu", ASM_CPU_SPEC }, \
171 { "asm_default", ASM_DEFAULT_SPEC }, \
0eab6840 172 { "cc1_cpu", CC1_CPU_SPEC }, \
cd679487
BE		 173 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
174 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
d40c9e33 175 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
7509c759
MM		 176 SUBTARGET_EXTRA_SPECS
177
0eab6840
DE		 178/* -mcpu=native handling only makes sense with compiler running on
179 an PowerPC chip. If changing this condition, also change
180 the condition in driver-rs6000.c. */
181#if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
182/* In driver-rs6000.c. */
183extern const char *host_detect_local_cpu (int argc, const char **argv);
184#define EXTRA_SPEC_FUNCTIONS \
185 { "local_cpu_detect", host_detect_local_cpu },
186#define HAVE_LOCAL_CPU_DETECT
187#endif
188
ee7caeb3
DE		 189#ifndef CC1_CPU_SPEC
190#ifdef HAVE_LOCAL_CPU_DETECT
0eab6840
DE		 191#define CC1_CPU_SPEC \
192"%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
193 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
ee7caeb3
DE		 194#else
195#define CC1_CPU_SPEC ""
196#endif
0eab6840
DE		 197#endif
198
fb623df5 199/* Architecture type. */
f045b2c9 200
bb22512c 201/* Define TARGET_MFCRF if the target assembler does not support the
78f5898b 202 optional field operand for mfcr. */
fb623df5 203
78f5898b 204#ifndef HAVE_AS_MFCRF
432218ba 205#undef TARGET_MFCRF
ffa22984
DE		 206#define TARGET_MFCRF 0
207#endif
208
0fa2e4df 209/* Define TARGET_POPCNTB if the target assembler does not support the
432218ba
DE		 210 popcount byte instruction. */
211
212#ifndef HAVE_AS_POPCNTB
213#undef TARGET_POPCNTB
214#define TARGET_POPCNTB 0
215#endif
216
9719f3b7
DE		 217/* Define TARGET_FPRND if the target assembler does not support the
218 fp rounding instructions. */
219
220#ifndef HAVE_AS_FPRND
221#undef TARGET_FPRND
222#define TARGET_FPRND 0
223#endif
224
b639c3c2
JJ		 225/* Define TARGET_CMPB if the target assembler does not support the
226 cmpb instruction. */
227
228#ifndef HAVE_AS_CMPB
229#undef TARGET_CMPB
230#define TARGET_CMPB 0
231#endif
232
44cd321e
PS		 233/* Define TARGET_MFPGPR if the target assembler does not support the
234 mffpr and mftgpr instructions. */
235
236#ifndef HAVE_AS_MFPGPR
237#undef TARGET_MFPGPR
238#define TARGET_MFPGPR 0
239#endif
240
b639c3c2
JJ		 241/* Define TARGET_DFP if the target assembler does not support decimal
242 floating point instructions. */
243#ifndef HAVE_AS_DFP
244#undef TARGET_DFP
245#define TARGET_DFP 0
246#endif
247
9752c4ad
AM		 248/* Define TARGET_TLS_MARKERS if the target assembler does not support
249 arg markers for __tls_get_addr calls. */
250#ifndef HAVE_AS_TLS_MARKERS
251#undef TARGET_TLS_MARKERS
252#define TARGET_TLS_MARKERS 0
253#else
254#define TARGET_TLS_MARKERS tls_markers
255#endif
256
7f970b70
AM		 257#ifndef TARGET_SECURE_PLT
258#define TARGET_SECURE_PLT 0
259#endif
260
2f3e5814 261#define TARGET_32BIT (! TARGET_64BIT)
d14a6d05 262
c4501e62
JJ		 263#ifndef HAVE_AS_TLS
264#define HAVE_AS_TLS 0
265#endif
266
48d72335
DE		 267/* Return 1 for a symbol ref for a thread-local storage symbol. */
268#define RS6000_SYMBOL_REF_TLS_P(RTX) \
269 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
270
996ed075
JJ		 271#ifdef IN_LIBGCC2
272/* For libgcc2 we make sure this is a compile time constant */
67796c1f 273#if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
78f5898b 274#undef TARGET_POWERPC64
996ed075
JJ		 275#define TARGET_POWERPC64 1
276#else
78f5898b 277#undef TARGET_POWERPC64
996ed075
JJ		 278#define TARGET_POWERPC64 0
279#endif
b6c9286a 280#else
78f5898b 281 /* The option machinery will define this. */
b6c9286a
MM		 282#endif
283
938937d8 284#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
9ebbca7d 285
cac8ce95 286/* Processor type. Order must match cpu attribute in MD file. */
fb623df5 287enum processor_type
bef84347
VM		 288 {
289 PROCESSOR_RIOS1,
290 PROCESSOR_RIOS2,
3cb999d8 291 PROCESSOR_RS64A,
bef84347
VM		 292 PROCESSOR_MPCCORE,
293 PROCESSOR_PPC403,
fe7f5677 294 PROCESSOR_PPC405,
b54cf83a 295 PROCESSOR_PPC440,
bef84347
VM		 296 PROCESSOR_PPC601,
297 PROCESSOR_PPC603,
298 PROCESSOR_PPC604,
299 PROCESSOR_PPC604e,
300 PROCESSOR_PPC620,
3cb999d8 301 PROCESSOR_PPC630,
ed947a96
DJ		 302 PROCESSOR_PPC750,
303 PROCESSOR_PPC7400,
309323c2 304 PROCESSOR_PPC7450,
a3170dc6 305 PROCESSOR_PPC8540,
fa41c305
EW		 306 PROCESSOR_PPCE300C2,
307 PROCESSOR_PPCE300C3,
edae5fe3 308 PROCESSOR_PPCE500MC,
ec507f2d 309 PROCESSOR_POWER4,
44cd321e 310 PROCESSOR_POWER5,
d296e02e
AP		 311 PROCESSOR_POWER6,
312 PROCESSOR_CELL
bef84347 313};
fb623df5 314
696e45ba
ME		 315/* FPU operations supported.
316 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
317 also test TARGET_HARD_FLOAT. */
318#define TARGET_SINGLE_FLOAT 1
319#define TARGET_DOUBLE_FLOAT 1
320#define TARGET_SINGLE_FPU 0
321#define TARGET_SIMPLE_FPU 0
0bb7b92e 322#define TARGET_XILINX_FPU 0
696e45ba 323
fb623df5
RK		 324extern enum processor_type rs6000_cpu;
325
326/* Recast the processor type to the cpu attribute. */
327#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
328
8482e358 329/* Define generic processor types based upon current deployment. */
3cb999d8
DE		 330#define PROCESSOR_COMMON PROCESSOR_PPC601
331#define PROCESSOR_POWER PROCESSOR_RIOS1
332#define PROCESSOR_POWERPC PROCESSOR_PPC604
333#define PROCESSOR_POWERPC64 PROCESSOR_RS64A
6e151478 334
fb623df5 335/* Define the default processor. This is overridden by other tm.h files. */
3cb999d8
DE		 336#define PROCESSOR_DEFAULT PROCESSOR_RIOS1
337#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
fb623df5 338
0bb7b92e
ME		 339/* FP processor type. */
340enum fpu_type_t
341{
342 FPU_NONE, /* No FPU */
343 FPU_SF_LITE, /* Limited Single Precision FPU */
344 FPU_DF_LITE, /* Limited Double Precision FPU */
345 FPU_SF_FULL, /* Full Single Precision FPU */
346 FPU_DF_FULL /* Full Double Single Precision FPU */
347};
348
349extern enum fpu_type_t fpu_type;
350
6febd581
RK		 351/* Specify the dialect of assembler to use. New mnemonics is dialect one
352 and the old mnemonics are dialect zero. */
9ebbca7d 353#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
6febd581 354
569fa502
DN		 355/* Types of costly dependences. */
356enum rs6000_dependence_cost
357 {
358 max_dep_latency = 1000,
359 no_dep_costly,
360 all_deps_costly,
361 true_store_to_load_dep_costly,
362 store_to_load_dep_costly
363 };
364
cbe26ab8
DN		 365/* Types of nop insertion schemes in sched target hook sched_finish. */
366enum rs6000_nop_insertion
367 {
368 sched_finish_regroup_exact = 1000,
369 sched_finish_pad_groups,
370 sched_finish_none
371 };
372
373/* Dispatch group termination caused by an insn. */
374enum group_termination
375 {
376 current_group,
377 previous_group
378 };
379
ff222560 380/* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
8e3f41e7
MM		 381struct rs6000_cpu_select
382{
815cdc52
MM		 383 const char *string;
384 const char *name;
8e3f41e7
MM		 385 int set_tune_p;
386 int set_arch_p;
387};
388
389extern struct rs6000_cpu_select rs6000_select[];
fb623df5 390
38c1f2d7 391/* Debug support */
0ac081f6 392extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
38c1f2d7
MM		 393extern int rs6000_debug_stack; /* debug stack applications */
394extern int rs6000_debug_arg; /* debug argument handling */
395
396#define TARGET_DEBUG_STACK rs6000_debug_stack
397#define TARGET_DEBUG_ARG rs6000_debug_arg
398
57ac7be9
AM		 399extern const char *rs6000_traceback_name; /* Type of traceback table. */
400
6fa3f289
ZW		 401/* These are separate from target_flags because we've run out of bits
402 there. */
6fa3f289 403extern int rs6000_long_double_type_size;
602ea4d3 404extern int rs6000_ieeequad;
6fa3f289 405extern int rs6000_altivec_abi;
a3170dc6 406extern int rs6000_spe_abi;
94f4765c
NF		 407extern int rs6000_spe;
408extern int rs6000_isel;
5da702b1 409extern int rs6000_float_gprs;
025d9908 410extern int rs6000_alignment_flags;
cbe26ab8
DN		 411extern const char *rs6000_sched_insert_nops_str;
412extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
0bb7b92e 413extern int rs6000_xilinx_fpu;
025d9908
KH		 414
415/* Alignment options for fields in structures for sub-targets following
416 AIX-like ABI.
417 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
418 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
419
420 Override the macro definitions when compiling libobjc to avoid undefined
421 reference to rs6000_alignment_flags due to library's use of GCC alignment
422 macros which use the macros below. */
f676971a 423
025d9908
KH		 424#ifndef IN_TARGET_LIBS
425#define MASK_ALIGN_POWER 0x00000000
426#define MASK_ALIGN_NATURAL 0x00000001
427#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
428#else
429#define TARGET_ALIGN_NATURAL 0
430#endif
6fa3f289
ZW		 431
432#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
602ea4d3 433#define TARGET_IEEEQUAD rs6000_ieeequad
6fa3f289
ZW		 434#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
435
a3170dc6
AH		 436#define TARGET_SPE_ABI 0
437#define TARGET_SPE 0
993f19a8 438#define TARGET_E500 0
edae5fe3 439#define TARGET_ISEL rs6000_isel
a3170dc6 440#define TARGET_FPRS 1
4d4cbc0e
AH		 441#define TARGET_E500_SINGLE 0
442#define TARGET_E500_DOUBLE 0
eca0d5e8 443#define CHECK_E500_OPTIONS do { } while (0)
a3170dc6 444
86098753
JM		 445/* E500 processors only support plain "sync", not lwsync. */
446#define TARGET_NO_LWSYNC TARGET_E500
447
fb623df5
RK		 448/* Sometimes certain combinations of command options do not make sense
449 on a particular target machine. You can define a macro
450 `OVERRIDE_OPTIONS' to take account of this. This macro, if
451 defined, is executed once just after all the command options have
452 been parsed.
453
ffa22984 454 Do not use this macro to turn on various extra optimizations for
5accd822
DE		 455 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
456
fb623df5
RK		 457 On the RS/6000 this is used to define the target cpu type. */
458
8e3f41e7 459#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
f045b2c9 460
5accd822
DE		 461/* Define this to change the optimizations performed by default. */
462#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
463
4c4eb375
GK		 464/* Show we can debug even without a frame pointer. */
465#define CAN_DEBUG_WITHOUT_FP
466
a5c76ee6 467/* Target pragma. */
c58b209a
NB		 468#define REGISTER_TARGET_PRAGMAS() do { \
469 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
2fab365e 470 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
a5c76ee6
ZW		 471} while (0)
472
4c4eb375
GK		 473/* Target #defines. */
474#define TARGET_CPU_CPP_BUILTINS() \
475 rs6000_cpu_cpp_builtins (pfile)
647d340d
JT		 476
477/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
478 we're compiling for. Some configurations may need to override it. */
479#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
480 do \
481 { \
482 if (BYTES_BIG_ENDIAN) \
483 { \
484 builtin_define ("__BIG_ENDIAN__"); \
485 builtin_define ("_BIG_ENDIAN"); \
486 builtin_assert ("machine=bigendian"); \
487 } \
488 else \
489 { \
490 builtin_define ("__LITTLE_ENDIAN__"); \
491 builtin_define ("_LITTLE_ENDIAN"); \
492 builtin_assert ("machine=littleendian"); \
493 } \
494 } \
495 while (0)
f045b2c9 496\f
4c4eb375 497/* Target machine storage layout. */
f045b2c9 498
13d39dbc 499/* Define this macro if it is advisable to hold scalars in registers
c81bebd7 500 in a wider mode than that declared by the program. In such cases,
ef457bda
RK		 501 the value is constrained to be within the bounds of the declared
502 type, but kept valid in the wider mode. The signedness of the
503 extension may differ from that of the type. */
504
39403d82
DE		 505#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
506 if (GET_MODE_CLASS (MODE) == MODE_INT \
507 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
b78d48dd 508 (MODE) = TARGET_32BIT ? SImode : DImode;
39403d82 509
f045b2c9 510/* Define this if most significant bit is lowest numbered
82e41834
KH		 511 in instructions that operate on numbered bit-fields. */
512/* That is true on RS/6000. */
f045b2c9
RS		 513#define BITS_BIG_ENDIAN 1
514
515/* Define this if most significant byte of a word is the lowest numbered. */
516/* That is true on RS/6000. */
517#define BYTES_BIG_ENDIAN 1
518
519/* Define this if most significant word of a multiword number is lowest
c81bebd7 520 numbered.
f045b2c9
RS		 521
522 For RS/6000 we can decide arbitrarily since there are no machine
82e41834 523 instructions for them. Might as well be consistent with bits and bytes. */
f045b2c9
RS		 524#define WORDS_BIG_ENDIAN 1
525
2e360ab3 526#define MAX_BITS_PER_WORD 64
f045b2c9
RS		 527
528/* Width of a word, in units (bytes). */
c1aa3958 529#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
f34fc46e
DE		 530#ifdef IN_LIBGCC2
531#define MIN_UNITS_PER_WORD UNITS_PER_WORD
532#else
ef0e53ce 533#define MIN_UNITS_PER_WORD 4
f34fc46e 534#endif
2e360ab3 535#define UNITS_PER_FP_WORD 8
0ac081f6 536#define UNITS_PER_ALTIVEC_WORD 16
a3170dc6 537#define UNITS_PER_SPE_WORD 8
96038623 538#define UNITS_PER_PAIRED_WORD 8
f045b2c9 539
915f619f
JW		 540/* Type used for ptrdiff_t, as a string used in a declaration. */
541#define PTRDIFF_TYPE "int"
542
058ef853
DE		 543/* Type used for size_t, as a string used in a declaration. */
544#define SIZE_TYPE "long unsigned int"
545
f045b2c9
RS		 546/* Type used for wchar_t, as a string used in a declaration. */
547#define WCHAR_TYPE "short unsigned int"
548
549/* Width of wchar_t in bits. */
550#define WCHAR_TYPE_SIZE 16
551
9e654916
RK		 552/* A C expression for the size in bits of the type `short' on the
553 target machine. If you don't define this, the default is half a
554 word. (If this would be less than one storage unit, it is
555 rounded up to one unit.) */
556#define SHORT_TYPE_SIZE 16
557
558/* A C expression for the size in bits of the type `int' on the
559 target machine. If you don't define this, the default is one
560 word. */
19d2d16f 561#define INT_TYPE_SIZE 32
9e654916
RK		 562
563/* A C expression for the size in bits of the type `long' on the
564 target machine. If you don't define this, the default is one
565 word. */
2f3e5814 566#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
9e654916
RK		 567
568/* A C expression for the size in bits of the type `long long' on the
569 target machine. If you don't define this, the default is two
570 words. */
571#define LONG_LONG_TYPE_SIZE 64
572
9e654916
RK		 573/* A C expression for the size in bits of the type `float' on the
574 target machine. If you don't define this, the default is one
575 word. */
576#define FLOAT_TYPE_SIZE 32
577
578/* A C expression for the size in bits of the type `double' on the
579 target machine. If you don't define this, the default is two
580 words. */
581#define DOUBLE_TYPE_SIZE 64
582
583/* A C expression for the size in bits of the type `long double' on
584 the target machine. If you don't define this, the default is two
585 words. */
6fa3f289 586#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
06f4e019 587
06f4e019
DE		 588/* Define this to set long double type size to use in libgcc2.c, which can
589 not depend on target_flags. */
590#ifdef __LONG_DOUBLE_128__
591#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
592#else
593#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
594#endif
9e654916 595
5b8f5865
DE		 596/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
597#define WIDEST_HARDWARE_FP_SIZE 64
598
f045b2c9
RS		 599/* Width in bits of a pointer.
600 See also the macro `Pmode' defined below. */
2f3e5814 601#define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
f045b2c9
RS		 602
603/* Allocation boundary (in *bits*) for storing arguments in argument list. */
2f3e5814 604#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
f045b2c9
RS		 605
606/* Boundary (in *bits*) on which stack pointer should be aligned. */
19fb36e3
AM		 607#define STACK_BOUNDARY \
608 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
f045b2c9
RS		 609
610/* Allocation boundary (in *bits*) for the code of a function. */
611#define FUNCTION_BOUNDARY 32
612
613/* No data type wants to be aligned rounder than this. */
0ac081f6
AH		 614#define BIGGEST_ALIGNMENT 128
615
616/* A C expression to compute the alignment for a variables in the
617 local store. TYPE is the data type, and ALIGN is the alignment
618 that the object would ordinarily have. */
619#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
a3170dc6 620 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
4d4447b5 621 (TARGET_E500_DOUBLE \
4f011e1e 622 && TYPE_MODE (TYPE) == DFmode) ? 64 : \
96038623
DE		 623 ((TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE \
624 && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) || (TARGET_PAIRED_FLOAT \
625 && TREE_CODE (TYPE) == VECTOR_TYPE \
626 && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) ? 64 : ALIGN)
b73fd26c 627
f045b2c9
RS		 628/* Alignment of field after `int : 0' in a structure. */
629#define EMPTY_FIELD_BOUNDARY 32
630
631/* Every structure's size must be a multiple of this. */
632#define STRUCTURE_SIZE_BOUNDARY 8
633
a3170dc6
AH		 634/* Return 1 if a structure or array containing FIELD should be
635 accessed using `BLKMODE'.
636
637 For the SPE, simd types are V2SI, and gcc can be tempted to put the
638 entire thing in a DI and use subregs to access the internals.
639 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
640 back-end. Because a single GPR can hold a V2SI, but not a DI, the
641 best thing to do is set structs to BLKmode and avoid Severe Tire
de334ef6
AH		 642 Damage.
643
644 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
645 fit into 1, whereas DI still needs two. */
a3170dc6 646#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
de334ef6 647 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
4f011e1e 648 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
a3170dc6 649
43a88a8c 650/* A bit-field declared as `int' forces `int' alignment for the struct. */
f045b2c9
RS		 651#define PCC_BITFIELD_TYPE_MATTERS 1
652
69ef87e2
AH		 653/* Make strings word-aligned so strcpy from constants will be faster.
654 Make vector constants quadword aligned. */
655#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
656 (TREE_CODE (EXP) == STRING_CST \
153fbec8 657 && (STRICT_ALIGNMENT || !optimize_size) \
69ef87e2
AH		 658 && (ALIGN) < BITS_PER_WORD \
659 ? BITS_PER_WORD \
660 : (ALIGN))
f045b2c9 661
0ac081f6 662/* Make arrays of chars word-aligned for the same reasons.
f82f556d
AH		 663 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
664 64 bits. */
f045b2c9 665#define DATA_ALIGNMENT(TYPE, ALIGN) \
96038623
DE		 666 (TREE_CODE (TYPE) == VECTOR_TYPE ? ((TARGET_SPE_ABI \
667 || TARGET_PAIRED_FLOAT) ? 64 : 128) \
4d4447b5 668 : (TARGET_E500_DOUBLE \
4f011e1e 669 && TYPE_MODE (TYPE) == DFmode) ? 64 \
0ac081f6 670 : TREE_CODE (TYPE) == ARRAY_TYPE \
f045b2c9
RS		 671 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
672 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
673
a0ab749a 674/* Nonzero if move instructions will actually fail to work
f045b2c9 675 when given unaligned data. */
fdaff8ba 676#define STRICT_ALIGNMENT 0
e1565e65
DE		 677
678/* Define this macro to be the value 1 if unaligned accesses have a cost
679 many times greater than aligned accesses, for example if they are
680 emulated in a trap handler. */
54ce9cc2
NF		 681/* Altivec vector memory instructions simply ignore the low bits; SPE
682 vector memory instructions trap on unaligned accesses. */
41543739
GK		 683#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
684 (STRICT_ALIGNMENT \
fcce224d 685 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
e41b2a33 686 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \
fcce224d 687 || (MODE) == DImode) \
54ce9cc2
NF		 688 && (ALIGN) < 32) \
689 || (VECTOR_MODE_P ((MODE)) && (ALIGN) < GET_MODE_BITSIZE ((MODE))))
f045b2c9
RS		 690\f
691/* Standard register usage. */
692
693/* Number of actual hardware registers.
694 The hardware registers are assigned numbers for the compiler
695 from 0 to just below FIRST_PSEUDO_REGISTER.
696 All registers that the compiler knows about must be given numbers,
697 even those that are not normally considered general registers.
698
699 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
700 an MQ register, a count register, a link register, and 8 condition
07488f32
ZW		 701 register fields, which we view here as separate registers. AltiVec
702 adds 32 vector registers and a VRsave register.
f045b2c9
RS		 703
704 In addition, the difference between the frame and argument pointers is
705 a function of the number of registers saved, so we need to have a
706 register for AP that will later be eliminated in favor of SP or FP.
802a0058 707 This is a normal register, but it is fixed.
f045b2c9 708
802a0058
MM		 709 We also create a pseudo register for float/int conversions, that will
710 really represent the memory location used. It is represented here as
711 a register, in order to work around problems in allocating stack storage
7d5175e1 712 in inline functions.
802a0058 713
7d5175e1
JJ		 714 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
715 pointer, which is eventually eliminated in favor of SP or FP. */
716
717#define FIRST_PSEUDO_REGISTER 114
f045b2c9 718
d6a7951f 719/* This must be included for pre gcc 3.0 glibc compatibility. */
7d5f33bc 720#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
62153b61 721
93c9d1ba 722/* Add 32 dwarf columns for synthetic SPE registers. */
7d5175e1 723#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
c19de7aa 724
93c9d1ba
AM		 725/* The SPE has an additional 32 synthetic registers, with DWARF debug
726 info numbering for these registers starting at 1200. While eh_frame
727 register numbering need not be the same as the debug info numbering,
728 we choose to number these regs for eh_frame at 1200 too. This allows
729 future versions of the rs6000 backend to add hard registers and
730 continue to use the gcc hard register numbering for eh_frame. If the
731 extra SPE registers in eh_frame were numbered starting from the
732 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
733 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
734 avoid invalidating older SPE eh_frame info.
735
736 We must map them here to avoid huge unwinder tables mostly consisting
f676971a 737 of unused space. */
93c9d1ba 738#define DWARF_REG_TO_UNWIND_COLUMN(r) \
7d5175e1 739 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
93c9d1ba 740
ed1cf8ff
GK		 741/* Use standard DWARF numbering for DWARF debugging information. */
742#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
743
93c9d1ba
AM		 744/* Use gcc hard register numbering for eh_frame. */
745#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
41f3a930 746
ed1cf8ff
GK		 747/* Map register numbers held in the call frame info that gcc has
748 collected using DWARF_FRAME_REGNUM to those that should be output in
749 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
750 for .eh_frame, but use the numbers mandated by the various ABIs for
751 .debug_frame. rs6000_emit_prologue has translated any combination of
752 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
753 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
754#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
755 ((FOR_EH) ? (REGNO) \
756 : (REGNO) == CR2_REGNO ? 64 \
757 : DBX_REGISTER_NUMBER (REGNO))
758
f045b2c9
RS		 759/* 1 for registers that have pervasive standard uses
760 and are not available for the register allocator.
761
5dead3e5
DJ		 762 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
763 as a local register; for all other OS's r2 is the TOC pointer.
f045b2c9 764
a127c4e5
RK		 765 cr5 is not supposed to be used.
766
767 On System V implementations, r13 is fixed and not available for use. */
768
f045b2c9 769#define FIXED_REGISTERS \
5dead3e5 770 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
f045b2c9
RS		 771 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
772 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
773 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0ac081f6
AH		 774 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
775 /* AltiVec registers. */ \
776 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
777 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 778 1, 1 \
7d5175e1 779 , 1, 1, 1 \
0ac081f6 780}
f045b2c9
RS		 781
782/* 1 for registers not available across function calls.
783 These must include the FIXED_REGISTERS and also any
784 registers that can be used without being saved.
785 The latter must include the registers where values are returned
786 and the register where structure-value addresses are passed.
787 Aside from that, you can include as many other registers as you like. */
788
789#define CALL_USED_REGISTERS \
a127c4e5 790 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
f045b2c9
RS		 791 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
792 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
793 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0ac081f6
AH		 794 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
795 /* AltiVec registers. */ \
796 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
797 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 798 1, 1 \
7d5175e1 799 , 1, 1, 1 \
0ac081f6
AH		 800}
801
289e96b2
AH		 802/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
803 the entire set of `FIXED_REGISTERS' be included.
804 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
805 This macro is optional. If not specified, it defaults to the value
806 of `CALL_USED_REGISTERS'. */
f676971a 807
289e96b2
AH		 808#define CALL_REALLY_USED_REGISTERS \
809 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
810 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
811 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
812 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
813 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
814 /* AltiVec registers. */ \
815 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
816 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 817 0, 0 \
7d5175e1 818 , 0, 0, 0 \
289e96b2 819}
f045b2c9 820
28bcfd4d 821#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
9ebbca7d 822
d62294f5
FJ		 823#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
824#define FIRST_SAVED_FP_REGNO (14+32)
825#define FIRST_SAVED_GP_REGNO 13
826
f045b2c9
RS		 827/* List the order in which to allocate registers. Each register must be
828 listed once, even those in FIXED_REGISTERS.
829
830 We allocate in the following order:
831 fp0 (not saved or used for anything)
832 fp13 - fp2 (not saved; incoming fp arg registers)
833 fp1 (not saved; return value)
9390387d 834 fp31 - fp14 (saved; order given to save least number)
5accd822
DE		 835 cr7, cr6 (not saved or special)
836 cr1 (not saved, but used for FP operations)
f045b2c9 837 cr0 (not saved, but used for arithmetic operations)
5accd822 838 cr4, cr3, cr2 (saved)
9390387d 839 r0 (not saved; cannot be base reg)
f045b2c9
RS		 840 r9 (not saved; best for TImode)
841 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
9390387d 842 r3 (not saved; return value register)
f045b2c9
RS		 843 r31 - r13 (saved; order given to save least number)
844 r12 (not saved; if used for DImode or DFmode would use r13)
845 mq (not saved; best to use it if we can)
846 ctr (not saved; when we have the choice ctr is better)
847 lr (saved)
9390387d
AM		 848 cr5, r1, r2, ap, xer (fixed)
849 v0 - v1 (not saved or used for anything)
850 v13 - v3 (not saved; incoming vector arg registers)
851 v2 (not saved; incoming vector arg reg; return value)
852 v19 - v14 (not saved or used for anything)
853 v31 - v20 (saved; order given to save least number)
854 vrsave, vscr (fixed)
a3170dc6 855 spe_acc, spefscr (fixed)
7d5175e1 856 sfp (fixed)
0ac081f6 857*/
f676971a 858
6b13641d
DJ		 859#if FIXED_R2 == 1
860#define MAYBE_R2_AVAILABLE
861#define MAYBE_R2_FIXED 2,
862#else
863#define MAYBE_R2_AVAILABLE 2,
864#define MAYBE_R2_FIXED
865#endif
f045b2c9 866
9390387d
AM		 867#define REG_ALLOC_ORDER \
868 {32, \
869 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
870 33, \
871 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
872 50, 49, 48, 47, 46, \
873 75, 74, 69, 68, 72, 71, 70, \
874 0, MAYBE_R2_AVAILABLE \
875 9, 11, 10, 8, 7, 6, 5, 4, \
876 3, \
877 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
878 18, 17, 16, 15, 14, 13, 12, \
879 64, 66, 65, \
880 73, 1, MAYBE_R2_FIXED 67, 76, \
881 /* AltiVec registers. */ \
882 77, 78, \
883 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
884 79, \
885 96, 95, 94, 93, 92, 91, \
886 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
887 109, 110, \
7d5175e1 888 111, 112, 113 \
0ac081f6 889}
f045b2c9
RS		 890
891/* True if register is floating-point. */
892#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
893
894/* True if register is a condition register. */
1de43f85 895#define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
f045b2c9 896
815cdc52 897/* True if register is a condition register, but not cr0. */
1de43f85 898#define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
815cdc52 899
f045b2c9 900/* True if register is an integer register. */
7d5175e1
JJ		 901#define INT_REGNO_P(N) \
902 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
f045b2c9 903
a3170dc6
AH		 904/* SPE SIMD registers are just the GPRs. */
905#define SPE_SIMD_REGNO_P(N) ((N) <= 31)
906
96038623
DE		 907/* PAIRED SIMD registers are just the FPRs. */
908#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
909
0d86f538 910/* True if register is the XER register. */
9ebbca7d 911#define XER_REGNO_P(N) ((N) == XER_REGNO)
802a0058 912
0ac081f6
AH		 913/* True if register is an AltiVec register. */
914#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
915
f045b2c9 916/* Return number of consecutive hard regs needed starting at reg REGNO
d8ecbcdb
AH		 917 to hold something of mode MODE. */
918
919#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
0e67400a
FJ		 920
921#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
922 ((TARGET_32BIT && TARGET_POWERPC64 \
2e6c9641 923 && (GET_MODE_SIZE (MODE) > 4) \
0e67400a 924 && INT_REGNO_P (REGNO)) ? 1 : 0)
f045b2c9 925
0ac081f6 926#define ALTIVEC_VECTOR_MODE(MODE) \
cb2a532e
AH		 927 ((MODE) == V16QImode \
928 || (MODE) == V8HImode \
929 || (MODE) == V4SFmode \
6e1f54e2 930 || (MODE) == V4SImode)
0ac081f6 931
a3170dc6
AH		 932#define SPE_VECTOR_MODE(MODE) \
933 ((MODE) == V4HImode \
934 || (MODE) == V2SFmode \
00a892b8 935 || (MODE) == V1DImode \
a3170dc6
AH		 936 || (MODE) == V2SImode)
937
96038623
DE		 938#define PAIRED_VECTOR_MODE(MODE) \
939 ((MODE) == V2SFmode)
940
9d3a9de1 941#define UNITS_PER_SIMD_WORD(MODE) \
96038623
DE		 942 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
943 : (TARGET_SPE ? UNITS_PER_SPE_WORD : (TARGET_PAIRED_FLOAT ? \
944 UNITS_PER_PAIRED_WORD : UNITS_PER_WORD)))
0bf43309 945
0d1fbc8c
AH		 946/* Value is TRUE if hard register REGNO can hold a value of
947 machine-mode MODE. */
948#define HARD_REGNO_MODE_OK(REGNO, MODE) \
949 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
f045b2c9
RS		 950
951/* Value is 1 if it is a good idea to tie two pseudo registers
952 when one has mode MODE1 and one has mode MODE2.
953 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
954 for any hard reg, then this must be 0 for correct output. */
955#define MODES_TIEABLE_P(MODE1, MODE2) \
ebb109ad
BE		 956 (SCALAR_FLOAT_MODE_P (MODE1) \
957 ? SCALAR_FLOAT_MODE_P (MODE2) \
958 : SCALAR_FLOAT_MODE_P (MODE2) \
959 ? SCALAR_FLOAT_MODE_P (MODE1) \
f045b2c9
RS		 960 : GET_MODE_CLASS (MODE1) == MODE_CC \
961 ? GET_MODE_CLASS (MODE2) == MODE_CC \
962 : GET_MODE_CLASS (MODE2) == MODE_CC \
963 ? GET_MODE_CLASS (MODE1) == MODE_CC \
4dcc01f3
AH		 964 : SPE_VECTOR_MODE (MODE1) \
965 ? SPE_VECTOR_MODE (MODE2) \
966 : SPE_VECTOR_MODE (MODE2) \
967 ? SPE_VECTOR_MODE (MODE1) \
0ac081f6
AH		 968 : ALTIVEC_VECTOR_MODE (MODE1) \
969 ? ALTIVEC_VECTOR_MODE (MODE2) \
970 : ALTIVEC_VECTOR_MODE (MODE2) \
971 ? ALTIVEC_VECTOR_MODE (MODE1) \
f045b2c9
RS		 972 : 1)
973
c8ae788f
SB		 974/* Post-reload, we can't use any new AltiVec registers, as we already
975 emitted the vrsave mask. */
976
977#define HARD_REGNO_RENAME_OK(SRC, DST) \
6fb5fa3c 978 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
c8ae788f 979
f045b2c9 980/* A C expression returning the cost of moving data from a register of class
34bb030a 981 CLASS1 to one of CLASS2. */
f045b2c9 982
34bb030a 983#define REGISTER_MOVE_COST rs6000_register_move_cost
f045b2c9 984
34bb030a
DE		 985/* A C expressions returning the cost of moving data of MODE from a register to
986 or from memory. */
f045b2c9 987
34bb030a 988#define MEMORY_MOVE_COST rs6000_memory_move_cost
f045b2c9
RS		 989
990/* Specify the cost of a branch insn; roughly the number of extra insns that
991 should be added to avoid a branch.
992
ef457bda 993 Set this to 3 on the RS/6000 since that is roughly the average cost of an
f045b2c9
RS		 994 unscheduled conditional branch. */
995
3a4fd356 996#define BRANCH_COST(speed_p, predictable_p) 3
f045b2c9 997
85e50b6b 998/* Override BRANCH_COST heuristic which empirically produces worse
b8610a53 999 performance for removing short circuiting from the logical ops. */
85e50b6b 1000
b8610a53 1001#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
a3170dc6 1002
52ff33d0
NF		 1003/* A fixed register used at epilogue generation to address SPE registers
1004 with negative offsets. The 64-bit load/store instructions on the SPE
1005 only take positive offsets (and small ones at that), so we need to
1006 reserve a register for consing up negative offsets. */
a3170dc6 1007
52ff33d0 1008#define FIXED_SCRATCH 0
a3170dc6 1009
2aa4498c
AH		 1010/* Define this macro to change register usage conditional on target
1011 flags. */
f85f4585 1012
2aa4498c 1013#define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
6febd581 1014
f045b2c9
RS		 1015/* Specify the registers used for certain standard purposes.
1016 The values of these macros are register numbers. */
1017
1018/* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1019/* #define PC_REGNUM */
1020
1021/* Register to use for pushing function arguments. */
1022#define STACK_POINTER_REGNUM 1
1023
1024/* Base register for access to local variables of the function. */
7d5175e1
JJ		 1025#define HARD_FRAME_POINTER_REGNUM 31
1026
1027/* Base register for access to local variables of the function. */
1028#define FRAME_POINTER_REGNUM 113
f045b2c9 1029
f045b2c9
RS		 1030/* Base register for access to arguments of the function. */
1031#define ARG_POINTER_REGNUM 67
1032
1033/* Place to put static chain when calling a function that requires it. */
1034#define STATIC_CHAIN_REGNUM 11
1035
f045b2c9
RS		 1036\f
1037/* Define the classes of registers for register constraints in the
1038 machine description. Also define ranges of constants.
1039
1040 One of the classes must always be named ALL_REGS and include all hard regs.
1041 If there is more than one class, another class must be named NO_REGS
1042 and contain no registers.
1043
1044 The name GENERAL_REGS must be the name of a class (or an alias for
1045 another name such as ALL_REGS). This is the class of registers
1046 that is allowed by "g" or "r" in a register constraint.
1047 Also, registers outside this class are allocated only when
1048 instructions express preferences for them.
1049
1050 The classes must be numbered in nondecreasing order; that is,
1051 a larger-numbered class must never be contained completely
1052 in a smaller-numbered class.
1053
1054 For any two classes, it is very desirable that there be another
1055 class that represents their union. */
c81bebd7 1056
f045b2c9
RS		 1057/* The RS/6000 has three types of registers, fixed-point, floating-point,
1058 and condition registers, plus three special registers, MQ, CTR, and the
07488f32 1059 link register. AltiVec adds a vector register class.
f045b2c9
RS		 1060
1061 However, r0 is special in that it cannot be used as a base register.
1062 So make a class for registers valid as base registers.
1063
1064 Also, cr0 is the only condition code register that can be used in
0d86f538 1065 arithmetic insns, so make a separate class for it. */
f045b2c9 1066
ebedb4dd
MM		 1067enum reg_class
1068{
1069 NO_REGS,
ebedb4dd
MM		 1070 BASE_REGS,
1071 GENERAL_REGS,
1072 FLOAT_REGS,
0ac081f6
AH		 1073 ALTIVEC_REGS,
1074 VRSAVE_REGS,
5f004351 1075 VSCR_REGS,
a3170dc6
AH		 1076 SPE_ACC_REGS,
1077 SPEFSCR_REGS,
ebedb4dd
MM		 1078 NON_SPECIAL_REGS,
1079 MQ_REGS,
1080 LINK_REGS,
1081 CTR_REGS,
1082 LINK_OR_CTR_REGS,
1083 SPECIAL_REGS,
1084 SPEC_OR_GEN_REGS,
1085 CR0_REGS,
ebedb4dd
MM		 1086 CR_REGS,
1087 NON_FLOAT_REGS,
9ebbca7d 1088 XER_REGS,
ebedb4dd
MM		 1089 ALL_REGS,
1090 LIM_REG_CLASSES
1091};
f045b2c9
RS		 1092
1093#define N_REG_CLASSES (int) LIM_REG_CLASSES
1094
82e41834 1095/* Give names of register classes as strings for dump file. */
f045b2c9 1096
ebedb4dd
MM		 1097#define REG_CLASS_NAMES \
1098{ \
1099 "NO_REGS", \
ebedb4dd
MM		 1100 "BASE_REGS", \
1101 "GENERAL_REGS", \
1102 "FLOAT_REGS", \
0ac081f6
AH		 1103 "ALTIVEC_REGS", \
1104 "VRSAVE_REGS", \
5f004351 1105 "VSCR_REGS", \
a3170dc6
AH		 1106 "SPE_ACC_REGS", \
1107 "SPEFSCR_REGS", \
ebedb4dd
MM		 1108 "NON_SPECIAL_REGS", \
1109 "MQ_REGS", \
1110 "LINK_REGS", \
1111 "CTR_REGS", \
1112 "LINK_OR_CTR_REGS", \
1113 "SPECIAL_REGS", \
1114 "SPEC_OR_GEN_REGS", \
1115 "CR0_REGS", \
ebedb4dd
MM		 1116 "CR_REGS", \
1117 "NON_FLOAT_REGS", \
9ebbca7d 1118 "XER_REGS", \
ebedb4dd
MM		 1119 "ALL_REGS" \
1120}
f045b2c9
RS		 1121
1122/* Define which registers fit in which classes.
1123 This is an initializer for a vector of HARD_REG_SET
1124 of length N_REG_CLASSES. */
1125
0ac081f6
AH		 1126#define REG_CLASS_CONTENTS \
1127{ \
1128 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
7d5175e1
JJ		 1129 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1130 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
0ac081f6 1131 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
089a05b8
SS		 1132 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1133 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
5f004351 1134 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
a3170dc6
AH		 1135 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1136 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
7d5175e1 1137 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
0ac081f6
AH		 1138 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1139 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1140 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1141 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
a004eb82 1142 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
7d5175e1 1143 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
0ac081f6
AH		 1144 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1145 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
e3604432 1146 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
089a05b8 1147 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
7d5175e1 1148 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
ebedb4dd 1149}
f045b2c9 1150
058e97ec
VM		 1151/* The following macro defines cover classes for Integrated Register
1152 Allocator. Cover classes is a set of non-intersected register
1153 classes covering all hard registers used for register allocation
1154 purpose. Any move between two registers of a cover class should be
1155 cheaper than load or store of the registers. The macro value is
1156 array of register classes with LIM_REG_CLASSES used as the end
1157 marker. */
1158
1159#define IRA_COVER_CLASSES \
1160{ \
1161 GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, \
1162 /*VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
1163 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
1164 CR_REGS, XER_REGS, LIM_REG_CLASSES \
1165}
1166
f045b2c9
RS		 1167/* The same information, inverted:
1168 Return the class number of the smallest class containing
1169 reg number REGNO. This could be a conditional expression
1170 or could index an array. */
1171
0d86f538
GK		 1172#define REGNO_REG_CLASS(REGNO) \
1173 ((REGNO) == 0 ? GENERAL_REGS \
1174 : (REGNO) < 32 ? BASE_REGS \
1175 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
0ac081f6 1176 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
0d86f538
GK		 1177 : (REGNO) == CR0_REGNO ? CR0_REGS \
1178 : CR_REGNO_P (REGNO) ? CR_REGS \
1179 : (REGNO) == MQ_REGNO ? MQ_REGS \
1de43f85
DE		 1180 : (REGNO) == LR_REGNO ? LINK_REGS \
1181 : (REGNO) == CTR_REGNO ? CTR_REGS \
0d86f538
GK		 1182 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1183 : (REGNO) == XER_REGNO ? XER_REGS \
0ac081f6 1184 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
7d5175e1 1185 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
a3170dc6
AH		 1186 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1187 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
7d5175e1 1188 : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \
f045b2c9
RS		 1189 : NO_REGS)
1190
1191/* The class value for index registers, and the one for base regs. */
1192#define INDEX_REG_CLASS GENERAL_REGS
1193#define BASE_REG_CLASS BASE_REGS
1194
f045b2c9
RS		 1195/* Given an rtx X being reloaded into a reg required to be
1196 in class CLASS, return the class of reg to actually use.
1197 In general this is just CLASS; but on some machines
c81bebd7 1198 in some cases it is preferable to use a more restrictive class.
f045b2c9
RS		 1199
1200 On the RS/6000, we have to return NO_REGS when we want to reload a
f676971a 1201 floating-point CONST_DOUBLE to force it to be copied to memory.
1e66d555
GK		 1202
1203 We also don't want to reload integer values into floating-point
1204 registers if we can at all help it. In fact, this can
37409796 1205 cause reload to die, if it tries to generate a reload of CTR
1e66d555
GK		 1206 into a FP register and discovers it doesn't have the memory location
1207 required.
1208
1209 ??? Would it be a good idea to have reload do the converse, that is
1210 try to reload floating modes into FP registers if possible?
1211 */
f045b2c9 1212
802a0058 1213#define PREFERRED_RELOAD_CLASS(X,CLASS) \
343f6bbf
DE		 1214 ((CONSTANT_P (X) \
1215 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
1216 ? NO_REGS \
1217 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1218 && (CLASS) == NON_SPECIAL_REGS) \
1219 ? GENERAL_REGS \
1220 : (CLASS))
c81bebd7 1221
f045b2c9
RS		 1222/* Return the register class of a scratch register needed to copy IN into
1223 or out of a register in CLASS in MODE. If it can be done directly,
1224 NO_REGS is returned. */
1225
1226#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
3c4774e0 1227 rs6000_secondary_reload_class (CLASS, MODE, IN)
f045b2c9 1228
0ac081f6 1229/* If we are copying between FP or AltiVec registers and anything
44cd321e
PS		 1230 else, we need a memory location. The exception is when we are
1231 targeting ppc64 and the move to/from fpr to gpr instructions
1232 are available.*/
1233
1234#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1235 ((CLASS1) != (CLASS2) && (((CLASS1) == FLOAT_REGS \
1236 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
c092b045
PB		 1237 || ((MODE != DFmode) \
1238 && (MODE != DDmode) \
1239 && (MODE != DImode)))) \
44cd321e
PS		 1240 || ((CLASS2) == FLOAT_REGS \
1241 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
c092b045
PB		 1242 || ((MODE != DFmode) \
1243 && (MODE != DDmode) \
1244 && (MODE != DImode)))) \
44cd321e 1245 || (CLASS1) == ALTIVEC_REGS \
0ac081f6 1246 || (CLASS2) == ALTIVEC_REGS))
7ea555a4 1247
e41b2a33
PB		 1248/* For cpus that cannot load/store SDmode values from the 64-bit
1249 FP registers without using a full 64-bit load/store, we need
1250 to allocate a full 64-bit stack slot for them. */
1251
1252#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1253 rs6000_secondary_memory_needed_rtx (MODE)
1254
f045b2c9
RS		 1255/* Return the maximum number of consecutive registers
1256 needed to represent mode MODE in a register of class CLASS.
1257
1258 On RS/6000, this is the size of MODE in words,
1259 except in the FP regs, where a single reg is enough for two words. */
802a0058 1260#define CLASS_MAX_NREGS(CLASS, MODE) \
9ebbca7d 1261 (((CLASS) == FLOAT_REGS) \
2e360ab3 1262 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
4d4447b5 1263 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS \
4f011e1e 1264 && (MODE) == DFmode) \
54b695e7 1265 ? 1 \
c1aa3958 1266 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
580d3230 1267
ca0e79d9
AM		 1268/* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1269
1270#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1271 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1272 ? ((GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8 \
1273 || TARGET_IEEEQUAD) \
1274 && reg_classes_intersect_p (FLOAT_REGS, CLASS)) \
1275 : (((TARGET_E500_DOUBLE \
1276 && ((((TO) == DFmode) + ((FROM) == DFmode)) == 1 \
17caeff2 1277 || (((TO) == TFmode) + ((FROM) == TFmode)) == 1 \
4d4447b5
PB		 1278 || (((TO) == DDmode) + ((FROM) == DDmode)) == 1 \
1279 || (((TO) == TDmode) + ((FROM) == TDmode)) == 1 \
ca0e79d9
AM		 1280 || (((TO) == DImode) + ((FROM) == DImode)) == 1)) \
1281 || (TARGET_SPE \
1282 && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \
1283 && reg_classes_intersect_p (GENERAL_REGS, CLASS)))
02188693 1284
f045b2c9
RS		 1285/* Stack layout; function entry, exit and calling. */
1286
6b67933e
RK		 1287/* Enumeration to give which calling sequence to use. */
1288enum rs6000_abi {
1289 ABI_NONE,
1290 ABI_AIX, /* IBM's AIX */
b6c9286a 1291 ABI_V4, /* System V.4/eabi */
ee890fe2 1292 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
6b67933e
RK		 1293};
1294
b6c9286a
MM		 1295extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1296
f045b2c9
RS		 1297/* Define this if pushing a word on the stack
1298 makes the stack pointer a smaller address. */
1299#define STACK_GROWS_DOWNWARD
1300
327e5343
FJ		 1301/* Offsets recorded in opcodes are a multiple of this alignment factor. */
1302#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1303
a4d05547 1304/* Define this to nonzero if the nominal address of the stack frame
f045b2c9
RS		 1305 is at the high-address end of the local variables;
1306 that is, each additional local variable allocated
1307 goes at a more negative offset in the frame.
1308
1309 On the RS/6000, we grow upwards, from the area after the outgoing
1310 arguments. */
3aebbe5f 1311#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
f045b2c9 1312
4697a36c 1313/* Size of the outgoing register save area */
9ebbca7d 1314#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
ee890fe2 1315 || DEFAULT_ABI == ABI_DARWIN) \
9ebbca7d
GK		 1316 ? (TARGET_64BIT ? 64 : 32) \
1317 : 0)
4697a36c
MM		 1318
1319/* Size of the fixed area on the stack */
9ebbca7d 1320#define RS6000_SAVE_AREA \
50d440bc 1321 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
9ebbca7d 1322 << (TARGET_64BIT ? 1 : 0))
4697a36c 1323
97f6e72f
DE		 1324/* MEM representing address to save the TOC register */
1325#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1326 plus_constant (stack_pointer_rtx, \
1327 (TARGET_32BIT ? 20 : 40)))
b6c9286a 1328
4697a36c 1329/* Align an address */
ed33106f 1330#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
4697a36c 1331
f045b2c9
RS		 1332/* Offset within stack frame to start allocating local variables at.
1333 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1334 first local allocated. Otherwise, it is the offset to the BEGINNING
c81bebd7 1335 of the first local allocated.
f045b2c9
RS		 1336
1337 On the RS/6000, the frame pointer is the same as the stack pointer,
1338 except for dynamic allocations. So we start after the fixed area and
1339 outgoing parameter area. */
1340
802a0058 1341#define STARTING_FRAME_OFFSET \
7d5175e1
JJ		 1342 (FRAME_GROWS_DOWNWARD \
1343 ? 0 \
38173d38 1344 : (RS6000_ALIGN (crtl->outgoing_args_size, \
7d5175e1 1345 TARGET_ALTIVEC ? 16 : 8) \
7d5175e1 1346 + RS6000_SAVE_AREA))
802a0058
MM		 1347
1348/* Offset from the stack pointer register to an item dynamically
1349 allocated on the stack, e.g., by `alloca'.
1350
1351 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1352 length of the outgoing arguments. The default is correct for most
1353 machines. See `function.c' for details. */
1354#define STACK_DYNAMIC_OFFSET(FUNDECL) \
38173d38 1355 (RS6000_ALIGN (crtl->outgoing_args_size, \
7b094d6e 1356 TARGET_ALTIVEC ? 16 : 8) \
802a0058 1357 + (STACK_POINTER_OFFSET))
f045b2c9
RS		 1358
1359/* If we generate an insn to push BYTES bytes,
1360 this says how many the stack pointer really advances by.
1361 On RS/6000, don't define this because there are no push insns. */
1362/* #define PUSH_ROUNDING(BYTES) */
1363
1364/* Offset of first parameter from the argument pointer register value.
1365 On the RS/6000, we define the argument pointer to the start of the fixed
1366 area. */
4697a36c 1367#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
f045b2c9 1368
62153b61
JM		 1369/* Offset from the argument pointer register value to the top of
1370 stack. This is different from FIRST_PARM_OFFSET because of the
1371 register save area. */
1372#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1373
f045b2c9
RS		 1374/* Define this if stack space is still allocated for a parameter passed
1375 in a register. The value is the number of bytes allocated to this
1376 area. */
4697a36c 1377#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
f045b2c9
RS		 1378
1379/* Define this if the above stack space is to be considered part of the
1380 space allocated by the caller. */
81464b2c 1381#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
f045b2c9
RS		 1382
1383/* This is the difference between the logical top of stack and the actual sp.
1384
82e41834 1385 For the RS/6000, sp points past the fixed area. */
4697a36c 1386#define STACK_POINTER_OFFSET RS6000_SAVE_AREA
f045b2c9
RS		 1387
1388/* Define this if the maximum size of all the outgoing args is to be
1389 accumulated and pushed during the prologue. The amount can be
38173d38 1390 found in the variable crtl->outgoing_args_size. */
f73ad30e 1391#define ACCUMULATE_OUTGOING_ARGS 1
f045b2c9
RS		 1392
1393/* Value is the number of bytes of arguments automatically
1394 popped when returning from a subroutine call.
8b109b37 1395 FUNDECL is the declaration node of the function (as a tree),
f045b2c9
RS		 1396 FUNTYPE is the data type of the function (as a tree),
1397 or for a library call it is an identifier node for the subroutine name.
1398 SIZE is the number of bytes of arguments passed on the stack. */
1399
8b109b37 1400#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
f045b2c9
RS		 1401
1402/* Define how to find the value returned by a function.
1403 VALTYPE is the data type of the value (as a tree).
1404 If the precise function being called is known, FUNC is its FUNCTION_DECL;
a6ebc39a
AH		 1405 otherwise, FUNC is 0. */
1406
1407#define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
f045b2c9
RS		 1408
1409/* Define how to find the value returned by a library function
1410 assuming the value has mode MODE. */
1411
ded9bf77 1412#define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
f045b2c9 1413
6fa3f289
ZW		 1414/* DRAFT_V4_STRUCT_RET defaults off. */
1415#define DRAFT_V4_STRUCT_RET 0
f607bc57 1416
bd5bd7ac 1417/* Let TARGET_RETURN_IN_MEMORY control what happens. */
f607bc57 1418#define DEFAULT_PCC_STRUCT_RETURN 0
f045b2c9 1419
a260abc9 1420/* Mode of stack savearea.
dfdfa60f
DE		 1421 FUNCTION is VOIDmode because calling convention maintains SP.
1422 BLOCK needs Pmode for SP.
a260abc9
DE		 1423 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1424#define STACK_SAVEAREA_MODE(LEVEL) \
dfdfa60f
DE		 1425 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1426 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
a260abc9 1427
4697a36c
MM		 1428/* Minimum and maximum general purpose registers used to hold arguments. */
1429#define GP_ARG_MIN_REG 3
1430#define GP_ARG_MAX_REG 10
1431#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1432
1433/* Minimum and maximum floating point registers used to hold arguments. */
1434#define FP_ARG_MIN_REG 33
7509c759
MM		 1435#define FP_ARG_AIX_MAX_REG 45
1436#define FP_ARG_V4_MAX_REG 40
9ebbca7d 1437#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
ee890fe2 1438 || DEFAULT_ABI == ABI_DARWIN) \
9ebbca7d 1439 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
4697a36c
MM		 1440#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1441
0ac081f6
AH		 1442/* Minimum and maximum AltiVec registers used to hold arguments. */
1443#define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1444#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1445#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1446
4697a36c
MM		 1447/* Return registers */
1448#define GP_ARG_RETURN GP_ARG_MIN_REG
1449#define FP_ARG_RETURN FP_ARG_MIN_REG
0ac081f6 1450#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
4697a36c 1451
7509c759 1452/* Flags for the call/call_value rtl operations set up by function_arg */
6a4cee5f 1453#define CALL_NORMAL 0x00000000 /* no special processing */
9ebbca7d 1454/* Bits in 0x00000001 are unused. */
6a4cee5f
MM		 1455#define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1456#define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1457#define CALL_LONG 0x00000008 /* always call indirect */
b9599e46 1458#define CALL_LIBCALL 0x00000010 /* libcall */
7509c759 1459
f57fe068
AM		 1460/* We don't have prologue and epilogue functions to save/restore
1461 everything for most ABIs. */
1462#define WORLD_SAVE_P(INFO) 0
1463
f045b2c9
RS		 1464/* 1 if N is a possible register number for a function value
1465 as seen by the caller.
1466
0ac081f6 1467 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
e87a88d3
AM		 1468#define FUNCTION_VALUE_REGNO_P(N) \
1469 ((N) == GP_ARG_RETURN \
b2df7d08 1470 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
44688022 1471 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
f045b2c9
RS		 1472
1473/* 1 if N is a possible register number for function argument passing.
0ac081f6
AH		 1474 On RS/6000, these are r3-r10 and fp1-fp13.
1475 On AltiVec, v2 - v13 are used for passing vectors. */
4697a36c 1476#define FUNCTION_ARG_REGNO_P(N) \
e87a88d3
AM		 1477 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1478 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
44688022 1479 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
e87a88d3 1480 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
b2df7d08 1481 && TARGET_HARD_FLOAT && TARGET_FPRS))
f045b2c9
RS		 1482\f
1483/* Define a data type for recording info about an argument list
1484 during the scan of that argument list. This data type should
1485 hold all necessary information about the function itself
1486 and about the args processed so far, enough to enable macros
1487 such as FUNCTION_ARG to determine where the next arg should go.
1488
1489 On the RS/6000, this is a structure. The first element is the number of
1490 total argument words, the second is used to store the next
1491 floating-point register number, and the third says how many more args we
4697a36c
MM		 1492 have prototype types for.
1493
4cc833b7 1494 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
07488f32 1495 the next available GP register, `fregno' is the next available FP
4cc833b7
RH		 1496 register, and `words' is the number of words used on the stack.
1497
bd227acc 1498 The varargs/stdarg support requires that this structure's size
4cc833b7 1499 be a multiple of sizeof(int). */
4697a36c
MM		 1500
1501typedef struct rs6000_args
1502{
4cc833b7 1503 int words; /* # words used for passing GP registers */
6a4cee5f 1504 int fregno; /* next available FP register */
0ac081f6 1505 int vregno; /* next available AltiVec register */
6a4cee5f 1506 int nargs_prototype; /* # args left in the current prototype */
6a4cee5f 1507 int prototype; /* Whether a prototype was defined */
a6c9bed4 1508 int stdarg; /* Whether function is a stdarg function. */
6a4cee5f 1509 int call_cookie; /* Do special things for this call */
4cc833b7 1510 int sysv_gregno; /* next available GP register */
0b5383eb
DJ		 1511 int intoffset; /* running offset in struct (darwin64) */
1512 int use_stack; /* any part of struct on stack (darwin64) */
1513 int named; /* false for varargs params */
4697a36c 1514} CUMULATIVE_ARGS;
f045b2c9 1515
f045b2c9
RS		 1516/* Initialize a variable CUM of type CUMULATIVE_ARGS
1517 for a call to a function whose data type is FNTYPE.
1518 For a library call, FNTYPE is 0. */
1519
0f6937fe
AM		 1520#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1521 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
f045b2c9
RS		 1522
1523/* Similar, but when scanning the definition of a procedure. We always
1524 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1525
0f6937fe
AM		 1526#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1527 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
b9599e46
FS		 1528
1529/* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1530
1531#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
0f6937fe 1532 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
f045b2c9
RS		 1533
1534/* Update the data in CUM to advance over an argument
1535 of mode MODE and data type TYPE.
1536 (TYPE is null for libcalls where that information may not be available.) */
1537
1538#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
594a51fe 1539 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
f045b2c9 1540
f045b2c9
RS		 1541/* Determine where to put an argument to a function.
1542 Value is zero to push the argument on the stack,
1543 or a hard register in which to store the argument.
1544
1545 MODE is the argument's machine mode.
1546 TYPE is the data type of the argument (as a tree).
1547 This is null for libcalls where that information may
1548 not be available.
1549 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1550 the preceding args and about the function being called.
1551 NAMED is nonzero if this argument is a named parameter
1552 (otherwise it is an extra parameter matching an ellipsis).
1553
1554 On RS/6000 the first eight words of non-FP are normally in registers
1555 and the rest are pushed. The first 13 FP args are in registers.
1556
1557 If this is floating-point and no prototype is specified, we use
4d6697ca
RK		 1558 both an FP and integer register (or possibly FP reg and stack). Library
1559 functions (when TYPE is zero) always have the proper types for args,
1560 so we can pass the FP value just in one register. emit_library_function
1561 doesn't support EXPR_LIST anyway. */
f045b2c9 1562
4697a36c
MM		 1563#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1564 function_arg (&CUM, MODE, TYPE, NAMED)
f045b2c9 1565
c229cba9
DE		 1566/* If defined, a C expression which determines whether, and in which
1567 direction, to pad out an argument with extra space. The value
1568 should be of type `enum direction': either `upward' to pad above
1569 the argument, `downward' to pad below, or `none' to inhibit
1570 padding. */
1571
9ebbca7d 1572#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
c229cba9 1573
b6c9286a 1574/* If defined, a C expression that gives the alignment boundary, in bits,
c81bebd7 1575 of an argument with the specified mode and type. If it is not defined,
b6c9286a
MM		 1576 PARM_BOUNDARY is used for all arguments. */
1577
1578#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1579 function_arg_boundary (MODE, TYPE)
1580
6e985040
AM		 1581#define PAD_VARARGS_DOWN \
1582 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
2a55fd42 1583
f045b2c9 1584/* Output assembler code to FILE to increment profiler label # LABELNO
58a39e45 1585 for profiling a function entry. */
f045b2c9
RS		 1586
1587#define FUNCTION_PROFILER(FILE, LABELNO) \
58a39e45 1588 output_function_profiler ((FILE), (LABELNO));
f045b2c9
RS		 1589
1590/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1591 the stack pointer does not matter. No definition is equivalent to
1592 always zero.
1593
a0ab749a 1594 On the RS/6000, this is nonzero because we can restore the stack from
f045b2c9
RS		 1595 its backpointer, which we maintain. */
1596#define EXIT_IGNORE_STACK 1
1597
a701949a
FS		 1598/* Define this macro as a C expression that is nonzero for registers
1599 that are used by the epilogue or the return' pattern. The stack
1600 and frame pointer registers are already be assumed to be used as
1601 needed. */
1602
83720594 1603#define EPILOGUE_USES(REGNO) \
1de43f85 1604 ((reload_completed && (REGNO) == LR_REGNO) \
b1765bde 1605 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
e3b5732b 1606 || (crtl->calls_eh_return \
3553b09d 1607 && TARGET_AIX \
ff3867ae 1608 && (REGNO) == 2))
2bfcf297 1609
f045b2c9 1610\f
eaf1bcf1 1611/* TRAMPOLINE_TEMPLATE deleted */
f045b2c9
RS		 1612
1613/* Length in units of the trampoline for entering a nested function. */
1614
b6c9286a 1615#define TRAMPOLINE_SIZE rs6000_trampoline_size ()
f045b2c9
RS		 1616
1617/* Emit RTL insns to initialize the variable parts of a trampoline.
1618 FNADDR is an RTX for the address of the function's pure code.
1619 CXT is an RTX for the static chain value for the function. */
1620
1621#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
b6c9286a 1622 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
f045b2c9 1623\f
f33985c6
MS		 1624/* Definitions for __builtin_return_address and __builtin_frame_address.
1625 __builtin_return_address (0) should give link register (65), enable
82e41834 1626 this. */
f33985c6
MS		 1627/* This should be uncommented, so that the link register is used, but
1628 currently this would result in unmatched insns and spilling fixed
1629 registers so we'll leave it for another day. When these problems are
1630 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1631 (mrs) */
1632/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
f09d4c33 1633
b6c9286a
MM		 1634/* Number of bytes into the frame return addresses can be found. See
1635 rs6000_stack_info in rs6000.c for more information on how the different
1636 abi's store the return address. */
1637#define RETURN_ADDRESS_OFFSET \
1638 ((DEFAULT_ABI == ABI_AIX \
50d440bc 1639 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
3b370352 1640 (DEFAULT_ABI == ABI_V4) ? 4 : \
c4636dd1 1641 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
f09d4c33 1642
f33985c6
MS		 1643/* The current return address is in link register (65). The return address
1644 of anything farther back is accessed normally at an offset of 8 from the
1645 frame pointer. */
71f123ca
FS		 1646#define RETURN_ADDR_RTX(COUNT, FRAME) \
1647 (rs6000_return_addr (COUNT, FRAME))
1648
f33985c6 1649\f
f045b2c9
RS		 1650/* Definitions for register eliminations.
1651
1652 We have two registers that can be eliminated on the RS/6000. First, the
1653 frame pointer register can often be eliminated in favor of the stack
1654 pointer register. Secondly, the argument pointer register can always be
642a35f1
JW		 1655 eliminated; it is replaced with either the stack or frame pointer.
1656
1657 In addition, we use the elimination mechanism to see if r30 is needed
1658 Initially we assume that it isn't. If it is, we spill it. This is done
1659 by making it an eliminable register. We replace it with itself so that
1660 if it isn't needed, then existing uses won't be modified. */
f045b2c9
RS		 1661
1662/* This is an array of structures. Each structure initializes one pair
1663 of eliminable registers. The "from" register number is given first,
1664 followed by "to". Eliminations of the same "from" register are listed
1665 in order of preference. */
7d5175e1
JJ		 1666#define ELIMINABLE_REGS \
1667{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1668 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1669 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1670 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1671 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
97b23853 1672 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
f045b2c9
RS		 1673
1674/* Given FROM and TO register numbers, say whether this elimination is allowed.
1675 Frame pointer elimination is automatically handled.
1676
1677 For the RS/6000, if frame pointer elimination is being done, we would like
642a35f1
JW		 1678 to convert ap into fp, not sp.
1679
abc95ed3 1680 We need r30 if -mminimal-toc was specified, and there are constant pool
642a35f1 1681 references. */
f045b2c9 1682
97b23853
GK		 1683#define CAN_ELIMINATE(FROM, TO) \
1684 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1685 ? ! frame_pointer_needed \
1686 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1687 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
f045b2c9
RS		 1688 : 1)
1689
1690/* Define the offset between two registers, one to be eliminated, and the other
1691 its replacement, at the start of a routine. */
d1d0c603
JJ		 1692#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1693 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
f045b2c9
RS		 1694\f
1695/* Addressing modes, and classification of registers for them. */
1696
940da324
JL		 1697#define HAVE_PRE_DECREMENT 1
1698#define HAVE_PRE_INCREMENT 1
6fb5fa3c
DB		 1699#define HAVE_PRE_MODIFY_DISP 1
1700#define HAVE_PRE_MODIFY_REG 1
f045b2c9
RS		 1701
1702/* Macros to check register numbers against specific register classes. */
1703
1704/* These assume that REGNO is a hard or pseudo reg number.
1705 They give nonzero only if REGNO is a hard reg of the suitable class
1706 or a pseudo reg currently allocated to a suitable hard reg.
1707 Since they use reg_renumber, they are safe only once reg_renumber
1708 has been allocated, which happens in local-alloc.c. */
1709
1710#define REGNO_OK_FOR_INDEX_P(REGNO) \
1711((REGNO) < FIRST_PSEUDO_REGISTER \
1712 ? (REGNO) <= 31 || (REGNO) == 67 \
7d5175e1 1713 || (REGNO) == FRAME_POINTER_REGNUM \
f045b2c9 1714 : (reg_renumber[REGNO] >= 0 \
7d5175e1
JJ		 1715 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1716 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
f045b2c9
RS		 1717
1718#define REGNO_OK_FOR_BASE_P(REGNO) \
1719((REGNO) < FIRST_PSEUDO_REGISTER \
1720 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
7d5175e1 1721 || (REGNO) == FRAME_POINTER_REGNUM \
f045b2c9 1722 : (reg_renumber[REGNO] > 0 \
7d5175e1
JJ		 1723 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1724 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
c6c3dba9
PB		 1725
1726/* Nonzero if X is a hard reg that can be used as an index
1727 or if it is a pseudo reg in the non-strict case. */
1728#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1729 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1730 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1731
1732/* Nonzero if X is a hard reg that can be used as a base reg
1733 or if it is a pseudo reg in the non-strict case. */
1734#define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1735 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1736 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1737
f045b2c9
RS		 1738\f
1739/* Maximum number of registers that can appear in a valid memory address. */
1740
1741#define MAX_REGS_PER_ADDRESS 2
1742
1743/* Recognize any constant value that is a valid address. */
1744
6eff269e
BK		 1745#define CONSTANT_ADDRESS_P(X) \
1746 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1747 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1748 || GET_CODE (X) == HIGH)
f045b2c9
RS		 1749
1750/* Nonzero if the constant value X is a legitimate general operand.
1751 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1752
1753 On the RS/6000, all integer constants are acceptable, most won't be valid
1754 for particular insns, though. Only easy FP constants are
1755 acceptable. */
1756
1757#define LEGITIMATE_CONSTANT_P(X) \
49a2166f
AH		 1758 (((GET_CODE (X) != CONST_DOUBLE \
1759 && GET_CODE (X) != CONST_VECTOR) \
1760 || GET_MODE (X) == VOIDmode \
c4501e62 1761 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
49a2166f
AH		 1762 || easy_fp_constant (X, GET_MODE (X)) \
1763 || easy_vector_constant (X, GET_MODE (X))) \
c4501e62 1764 && !rs6000_tls_referenced_p (X))
f045b2c9 1765
48d72335 1766#define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
66180ff3 1767#define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
76492753
PB		 1768 && EASY_VECTOR_15((n) >> 1) \
1769 && ((n) & 1) == 0)
48d72335 1770
f045b2c9 1771\f
a260abc9
DE		 1772/* Try a machine-dependent way of reloading an illegitimate address
1773 operand. If we find one, push the reload and jump to WIN. This
1774 macro is used in only one place: `find_reloads_address' in reload.c.
1775
f676971a 1776 Implemented on rs6000 by rs6000_legitimize_reload_address.
24ea750e 1777 Note that (X) is evaluated twice; this is safe in current usage. */
f676971a 1778
a9098fd0
GK		 1779#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1780do { \
24ea750e
DJ		 1781 int win; \
1782 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
1783 (int)(TYPE), (IND_LEVELS), &win); \
1784 if ( win ) \
1785 goto WIN; \
a260abc9
DE		 1786} while (0)
1787
f045b2c9 1788/* Go to LABEL if ADDR (a legitimate address expression)
4d588c14 1789 has an effect that depends on the machine mode it is used for. */
f045b2c9
RS		 1790
1791#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
4d588c14
RH		 1792do { \
1793 if (rs6000_mode_dependent_address (ADDR)) \
f045b2c9 1794 goto LABEL; \
4d588c14 1795} while (0)
944258eb
RS		 1796
1797#define FIND_BASE_TERM rs6000_find_base_term
766a866c
MM		 1798\f
1799/* The register number of the register used to address a table of
1800 static data addresses in memory. In some cases this register is
1801 defined by a processor's "application binary interface" (ABI).
1802 When this macro is defined, RTL is generated for this register
1803 once, as with the stack pointer and frame pointer registers. If
1804 this macro is not defined, it is up to the machine-dependent files
1805 to allocate such a register (if necessary). */
1806
1db02437
FS		 1807#define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1808#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
766a866c 1809
97b23853 1810#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
9ebbca7d 1811
766a866c
MM		 1812/* Define this macro if the register defined by
1813 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
089a05b8 1814 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
766a866c
MM		 1815
1816/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1817
766a866c
MM		 1818/* A C expression that is nonzero if X is a legitimate immediate
1819 operand on the target machine when generating position independent
1820 code. You can assume that X satisfies `CONSTANT_P', so you need
1821 not check this. You can also assume FLAG_PIC is true, so you need
1822 not check it either. You need not define this macro if all
1823 constants (including `SYMBOL_REF') can be immediate operands when
1824 generating position independent code. */
1825
1826/* #define LEGITIMATE_PIC_OPERAND_P (X) */
f045b2c9
RS		 1827\f
1828/* Define this if some processing needs to be done immediately before
4255474b 1829 emitting code for an insn. */
f045b2c9 1830
c921bad8
AP		 1831#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
1832 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
f045b2c9
RS		 1833
1834/* Specify the machine mode that this machine uses
1835 for the index in the tablejump instruction. */
e1565e65 1836#define CASE_VECTOR_MODE SImode
f045b2c9 1837
18543a22
ILT		 1838/* Define as C expression which evaluates to nonzero if the tablejump
1839 instruction expects the table to contain offsets from the address of the
1840 table.
82e41834 1841 Do not define this if the table should contain absolute addresses. */
18543a22 1842#define CASE_VECTOR_PC_RELATIVE 1
f045b2c9 1843
f045b2c9
RS		 1844/* Define this as 1 if `char' should by default be signed; else as 0. */
1845#define DEFAULT_SIGNED_CHAR 0
1846
1847/* This flag, if defined, says the same insns that convert to a signed fixnum
1848 also convert validly to an unsigned one. */
1849
1850/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1851
c1618c0c
DE		 1852/* An integer expression for the size in bits of the largest integer machine
1853 mode that should actually be used. */
1854
1855/* Allow pairs of registers to be used, which is the intent of the default. */
1856#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1857
f045b2c9
RS		 1858/* Max number of bytes we can move from memory to memory
1859 in one reasonably fast instruction. */
2f3e5814 1860#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
7e69e155 1861#define MAX_MOVE_MAX 8
f045b2c9
RS		 1862
1863/* Nonzero if access to memory by bytes is no faster than for words.
a0ab749a 1864 Also nonzero if doing byte operations (specifically shifts) in registers
f045b2c9
RS		 1865 is undesirable. */
1866#define SLOW_BYTE_ACCESS 1
1867
9a63901f
RK		 1868/* Define if operations between registers always perform the operation
1869 on the full register even if a narrower mode is specified. */
1870#define WORD_REGISTER_OPERATIONS
1871
1872/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1873 will either zero-extend or sign-extend. The value of this macro should
1874 be the code that says which one of the two operations is implicitly
f822d252 1875 done, UNKNOWN if none. */
9a63901f 1876#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
225211e2
RK		 1877
1878/* Define if loading short immediate values into registers sign extends. */
1879#define SHORT_IMMEDIATES_SIGN_EXTEND
fdaff8ba 1880\f
f045b2c9
RS		 1881/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1882 is done just by pretending it is already truncated. */
1883#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1884
94993909 1885/* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
d865b122 1886#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
14670a74 1887 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
d865b122 1888
94993909 1889/* The CTZ patterns return -1 for input of zero. */
14670a74 1890#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
94993909 1891
f045b2c9
RS		 1892/* Specify the machine mode that pointers have.
1893 After generation of rtl, the compiler makes no further distinction
1894 between pointers and any other objects of this machine mode. */
2f3e5814 1895#define Pmode (TARGET_32BIT ? SImode : DImode)
f045b2c9 1896
a3c9585f 1897/* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
4c81e946
FJ		 1898#define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1899
f045b2c9 1900/* Mode of a function address in a call instruction (for indexing purposes).
f045b2c9 1901 Doesn't matter on RS/6000. */
5b71a4e7 1902#define FUNCTION_MODE SImode
f045b2c9
RS		 1903
1904/* Define this if addresses of constant functions
1905 shouldn't be put through pseudo regs where they can be cse'd.
1906 Desirable on machines where ordinary constants are expensive
1907 but a CALL with constant address is cheap. */
1908#define NO_FUNCTION_CSE
1909
d969caf8 1910/* Define this to be nonzero if shift instructions ignore all but the low-order
6febd581
RK		 1911 few bits.
1912
1913 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1914 have been dropped from the PowerPC architecture. */
1915
4697a36c 1916#define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
f045b2c9 1917
f045b2c9
RS		 1918/* Adjust the length of an INSN. LENGTH is the currently-computed length and
1919 should be adjusted to reflect any required changes. This macro is used when
1920 there is some systematic length adjustment required that would be difficult
1921 to express in the length attribute. */
1922
1923/* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1924
39a10a29
GK		 1925/* Given a comparison code (EQ, NE, etc.) and the first operand of a
1926 COMPARE, return the mode to be used for the comparison. For
1927 floating-point, CCFPmode should be used. CCUNSmode should be used
1928 for unsigned comparisons. CCEQmode should be used when we are
1929 doing an inequality comparison on the result of a
1930 comparison. CCmode should be used in all other cases. */
c5defebb 1931
b565a316 1932#define SELECT_CC_MODE(OP,X,Y) \
ebb109ad 1933 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
c5defebb 1934 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
ec8e098d 1935 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
c5defebb 1936 ? CCEQmode : CCmode))
f045b2c9 1937
b39358e1
GK		 1938/* Can the condition code MODE be safely reversed? This is safe in
1939 all cases on this port, because at present it doesn't use the
1940 trapping FP comparisons (fcmpo). */
1941#define REVERSIBLE_CC_MODE(MODE) 1
1942
1943/* Given a condition code and a mode, return the inverse condition. */
1944#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1945
f045b2c9
RS		 1946\f
1947/* Control the assembler format that we output. */
1948
1b279f39
DE		 1949/* A C string constant describing how to begin a comment in the target
1950 assembler language. The compiler assumes that the comment will end at
1951 the end of the line. */
1952#define ASM_COMMENT_START " #"
6b67933e 1953
38c1f2d7
MM		 1954/* Flag to say the TOC is initialized */
1955extern int toc_initialized;
1956
f045b2c9
RS		 1957/* Macro to output a special constant pool entry. Go to WIN if we output
1958 it. Otherwise, it is written the usual way.
1959
1960 On the RS/6000, toc entries are handled this way. */
1961
a9098fd0
GK		 1962#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1963{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1964 { \
1965 output_toc (FILE, X, LABELNO, MODE); \
1966 goto WIN; \
1967 } \
f045b2c9
RS		 1968}
1969
ebd97b96
DE		 1970#ifdef HAVE_GAS_WEAK
1971#define RS6000_WEAK 1
1972#else
1973#define RS6000_WEAK 0
1974#endif
290ad355 1975
79c4e63f
AM		 1976#if RS6000_WEAK
1977/* Used in lieu of ASM_WEAKEN_LABEL. */
1978#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1979 do \
1980 { \
1981 fputs ("\t.weak\t", (FILE)); \
85b776df 1982 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f 1983 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 1984 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f 1985 { \
cbaaba19
DE		 1986 if (TARGET_XCOFF) \
1987 fputs ("[DS]", (FILE)); \
ca734b39 1988 fputs ("\n\t.weak\t.", (FILE)); \
cbaaba19 1989 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f
AM		 1990 } \
1991 fputc ('\n', (FILE)); \
1992 if (VAL) \
1993 { \
1994 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
1995 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 1996 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f
AM		 1997 { \
1998 fputs ("\t.set\t.", (FILE)); \
cbaaba19 1999 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f 2000 fputs (",.", (FILE)); \
cbaaba19 2001 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
79c4e63f
AM		 2002 fputc ('\n', (FILE)); \
2003 } \
2004 } \
2005 } \
2006 while (0)
2007#endif
2008
ff2d10c1
AO		 2009#if HAVE_GAS_WEAKREF
2010#define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2011 do \
2012 { \
2013 fputs ("\t.weakref\t", (FILE)); \
2014 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2015 fputs (", ", (FILE)); \
2016 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2017 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2018 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2019 { \
2020 fputs ("\n\t.weakref\t.", (FILE)); \
2021 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2022 fputs (", .", (FILE)); \
2023 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2024 } \
2025 fputc ('\n', (FILE)); \
2026 } while (0)
2027#endif
2028
79c4e63f
AM		 2029/* This implements the `alias' attribute. */
2030#undef ASM_OUTPUT_DEF_FROM_DECLS
2031#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2032 do \
2033 { \
2034 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2035 const char *name = IDENTIFIER_POINTER (TARGET); \
2036 if (TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 2037 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f
AM		 2038 { \
2039 if (TREE_PUBLIC (DECL)) \
2040 { \
2041 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2042 { \
2043 fputs ("\t.globl\t.", FILE); \
cbaaba19 2044 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f
AM		 2045 putc ('\n', FILE); \
2046 } \
2047 } \
2048 else if (TARGET_XCOFF) \
2049 { \
2050 fputs ("\t.lglobl\t.", FILE); \
cbaaba19 2051 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f
AM		 2052 putc ('\n', FILE); \
2053 } \
2054 fputs ("\t.set\t.", FILE); \
cbaaba19 2055 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f 2056 fputs (",.", FILE); \
cbaaba19 2057 RS6000_OUTPUT_BASENAME (FILE, name); \
79c4e63f
AM		 2058 fputc ('\n', FILE); \
2059 } \
2060 ASM_OUTPUT_DEF (FILE, alias, name); \
2061 } \
2062 while (0)
290ad355 2063
1bc7c5b6
ZW		 2064#define TARGET_ASM_FILE_START rs6000_file_start
2065
f045b2c9
RS		 2066/* Output to assembler file text saying following lines
2067 may contain character constants, extra white space, comments, etc. */
2068
2069#define ASM_APP_ON ""
2070
2071/* Output to assembler file text saying following lines
2072 no longer contain unusual constructs. */
2073
2074#define ASM_APP_OFF ""
2075
f045b2c9
RS		 2076/* How to refer to registers in assembler output.
2077 This sequence is indexed by compiler's hard-register-number (see above). */
2078
82e41834 2079extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
c81bebd7
MM		 2080
2081#define REGISTER_NAMES \
2082{ \
2083 &rs6000_reg_names[ 0][0], /* r0 */ \
2084 &rs6000_reg_names[ 1][0], /* r1 */ \
2085 &rs6000_reg_names[ 2][0], /* r2 */ \
2086 &rs6000_reg_names[ 3][0], /* r3 */ \
2087 &rs6000_reg_names[ 4][0], /* r4 */ \
2088 &rs6000_reg_names[ 5][0], /* r5 */ \
2089 &rs6000_reg_names[ 6][0], /* r6 */ \
2090 &rs6000_reg_names[ 7][0], /* r7 */ \
2091 &rs6000_reg_names[ 8][0], /* r8 */ \
2092 &rs6000_reg_names[ 9][0], /* r9 */ \
2093 &rs6000_reg_names[10][0], /* r10 */ \
2094 &rs6000_reg_names[11][0], /* r11 */ \
2095 &rs6000_reg_names[12][0], /* r12 */ \
2096 &rs6000_reg_names[13][0], /* r13 */ \
2097 &rs6000_reg_names[14][0], /* r14 */ \
2098 &rs6000_reg_names[15][0], /* r15 */ \
2099 &rs6000_reg_names[16][0], /* r16 */ \
2100 &rs6000_reg_names[17][0], /* r17 */ \
2101 &rs6000_reg_names[18][0], /* r18 */ \
2102 &rs6000_reg_names[19][0], /* r19 */ \
2103 &rs6000_reg_names[20][0], /* r20 */ \
2104 &rs6000_reg_names[21][0], /* r21 */ \
2105 &rs6000_reg_names[22][0], /* r22 */ \
2106 &rs6000_reg_names[23][0], /* r23 */ \
2107 &rs6000_reg_names[24][0], /* r24 */ \
2108 &rs6000_reg_names[25][0], /* r25 */ \
2109 &rs6000_reg_names[26][0], /* r26 */ \
2110 &rs6000_reg_names[27][0], /* r27 */ \
2111 &rs6000_reg_names[28][0], /* r28 */ \
2112 &rs6000_reg_names[29][0], /* r29 */ \
2113 &rs6000_reg_names[30][0], /* r30 */ \
2114 &rs6000_reg_names[31][0], /* r31 */ \
2115 \
2116 &rs6000_reg_names[32][0], /* fr0 */ \
2117 &rs6000_reg_names[33][0], /* fr1 */ \
2118 &rs6000_reg_names[34][0], /* fr2 */ \
2119 &rs6000_reg_names[35][0], /* fr3 */ \
2120 &rs6000_reg_names[36][0], /* fr4 */ \
2121 &rs6000_reg_names[37][0], /* fr5 */ \
2122 &rs6000_reg_names[38][0], /* fr6 */ \
2123 &rs6000_reg_names[39][0], /* fr7 */ \
2124 &rs6000_reg_names[40][0], /* fr8 */ \
2125 &rs6000_reg_names[41][0], /* fr9 */ \
2126 &rs6000_reg_names[42][0], /* fr10 */ \
2127 &rs6000_reg_names[43][0], /* fr11 */ \
2128 &rs6000_reg_names[44][0], /* fr12 */ \
2129 &rs6000_reg_names[45][0], /* fr13 */ \
2130 &rs6000_reg_names[46][0], /* fr14 */ \
2131 &rs6000_reg_names[47][0], /* fr15 */ \
2132 &rs6000_reg_names[48][0], /* fr16 */ \
2133 &rs6000_reg_names[49][0], /* fr17 */ \
2134 &rs6000_reg_names[50][0], /* fr18 */ \
2135 &rs6000_reg_names[51][0], /* fr19 */ \
2136 &rs6000_reg_names[52][0], /* fr20 */ \
2137 &rs6000_reg_names[53][0], /* fr21 */ \
2138 &rs6000_reg_names[54][0], /* fr22 */ \
2139 &rs6000_reg_names[55][0], /* fr23 */ \
2140 &rs6000_reg_names[56][0], /* fr24 */ \
2141 &rs6000_reg_names[57][0], /* fr25 */ \
2142 &rs6000_reg_names[58][0], /* fr26 */ \
2143 &rs6000_reg_names[59][0], /* fr27 */ \
2144 &rs6000_reg_names[60][0], /* fr28 */ \
2145 &rs6000_reg_names[61][0], /* fr29 */ \
2146 &rs6000_reg_names[62][0], /* fr30 */ \
2147 &rs6000_reg_names[63][0], /* fr31 */ \
2148 \
2149 &rs6000_reg_names[64][0], /* mq */ \
2150 &rs6000_reg_names[65][0], /* lr */ \
2151 &rs6000_reg_names[66][0], /* ctr */ \
2152 &rs6000_reg_names[67][0], /* ap */ \
2153 \
2154 &rs6000_reg_names[68][0], /* cr0 */ \
2155 &rs6000_reg_names[69][0], /* cr1 */ \
2156 &rs6000_reg_names[70][0], /* cr2 */ \
2157 &rs6000_reg_names[71][0], /* cr3 */ \
2158 &rs6000_reg_names[72][0], /* cr4 */ \
2159 &rs6000_reg_names[73][0], /* cr5 */ \
2160 &rs6000_reg_names[74][0], /* cr6 */ \
2161 &rs6000_reg_names[75][0], /* cr7 */ \
802a0058 2162 \
9ebbca7d 2163 &rs6000_reg_names[76][0], /* xer */ \
0ac081f6
AH		 2164 \
2165 &rs6000_reg_names[77][0], /* v0 */ \
2166 &rs6000_reg_names[78][0], /* v1 */ \
2167 &rs6000_reg_names[79][0], /* v2 */ \
2168 &rs6000_reg_names[80][0], /* v3 */ \
2169 &rs6000_reg_names[81][0], /* v4 */ \
2170 &rs6000_reg_names[82][0], /* v5 */ \
2171 &rs6000_reg_names[83][0], /* v6 */ \
2172 &rs6000_reg_names[84][0], /* v7 */ \
2173 &rs6000_reg_names[85][0], /* v8 */ \
2174 &rs6000_reg_names[86][0], /* v9 */ \
2175 &rs6000_reg_names[87][0], /* v10 */ \
2176 &rs6000_reg_names[88][0], /* v11 */ \
2177 &rs6000_reg_names[89][0], /* v12 */ \
2178 &rs6000_reg_names[90][0], /* v13 */ \
2179 &rs6000_reg_names[91][0], /* v14 */ \
2180 &rs6000_reg_names[92][0], /* v15 */ \
2181 &rs6000_reg_names[93][0], /* v16 */ \
2182 &rs6000_reg_names[94][0], /* v17 */ \
2183 &rs6000_reg_names[95][0], /* v18 */ \
2184 &rs6000_reg_names[96][0], /* v19 */ \
2185 &rs6000_reg_names[97][0], /* v20 */ \
2186 &rs6000_reg_names[98][0], /* v21 */ \
2187 &rs6000_reg_names[99][0], /* v22 */ \
2188 &rs6000_reg_names[100][0], /* v23 */ \
2189 &rs6000_reg_names[101][0], /* v24 */ \
2190 &rs6000_reg_names[102][0], /* v25 */ \
2191 &rs6000_reg_names[103][0], /* v26 */ \
2192 &rs6000_reg_names[104][0], /* v27 */ \
2193 &rs6000_reg_names[105][0], /* v28 */ \
2194 &rs6000_reg_names[106][0], /* v29 */ \
2195 &rs6000_reg_names[107][0], /* v30 */ \
2196 &rs6000_reg_names[108][0], /* v31 */ \
2197 &rs6000_reg_names[109][0], /* vrsave */ \
5f004351 2198 &rs6000_reg_names[110][0], /* vscr */ \
a3170dc6
AH		 2199 &rs6000_reg_names[111][0], /* spe_acc */ \
2200 &rs6000_reg_names[112][0], /* spefscr */ \
7d5175e1 2201 &rs6000_reg_names[113][0], /* sfp */ \
c81bebd7
MM		 2202}
2203
f045b2c9
RS		 2204/* Table of additional register names to use in user input. */
2205
2206#define ADDITIONAL_REGISTER_NAMES \
c4d38ccb
MM		 2207 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2208 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2209 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2210 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2211 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2212 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2213 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2214 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2215 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2216 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2217 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2218 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2219 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2220 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2221 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2222 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
0ac081f6
AH		 2223 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2224 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2225 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2226 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2227 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2228 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2229 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2230 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
5f004351 2231 {"vrsave", 109}, {"vscr", 110}, \
a3170dc6 2232 {"spe_acc", 111}, {"spefscr", 112}, \
c4d38ccb
MM		 2233 /* no additional names for: mq, lr, ctr, ap */ \
2234 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2235 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2236 {"cc", 68}, {"sp", 1}, {"toc", 2} }
f045b2c9 2237
0da40b09
RK		 2238/* Text to write out after a CALL that may be replaced by glue code by
2239 the loader. This depends on the AIX version. */
2240#define RS6000_CALL_GLUE "cror 31,31,31"
11117bb9 2241
f045b2c9
RS		 2242/* This is how to output an element of a case-vector that is relative. */
2243
e1565e65 2244#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3daf36a4 2245 do { char buf[100]; \
e1565e65 2246 fputs ("\t.long ", FILE); \
3daf36a4
ILT		 2247 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2248 assemble_name (FILE, buf); \
19d2d16f 2249 putc ('-', FILE); \
3daf36a4
ILT		 2250 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2251 assemble_name (FILE, buf); \
19d2d16f 2252 putc ('\n', FILE); \
3daf36a4 2253 } while (0)
f045b2c9
RS		 2254
2255/* This is how to output an assembler line
2256 that says to advance the location counter
2257 to a multiple of 2**LOG bytes. */
2258
2259#define ASM_OUTPUT_ALIGN(FILE,LOG) \
2260 if ((LOG) != 0) \
2261 fprintf (FILE, "\t.align %d\n", (LOG))
2262
9ebbca7d
GK		 2263/* Pick up the return address upon entry to a procedure. Used for
2264 dwarf2 unwind information. This also enables the table driven
2265 mechanism. */
2266
1de43f85
DE		 2267#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2268#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
9ebbca7d 2269
83720594
RH		 2270/* Describe how we implement __builtin_eh_return. */
2271#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2272#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2273
f045b2c9
RS		 2274/* Print operand X (an rtx) in assembler syntax to file FILE.
2275 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2276 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2277
2278#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2279
2280/* Define which CODE values are valid. */
2281
c81bebd7 2282#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
c4501e62 2283 ((CODE) == '.' || (CODE) == '&')
f045b2c9
RS		 2284
2285/* Print a memory address as an operand to reference that memory location. */
2286
2287#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2288
2e4316da
RS		 2289#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2290 do \
2291 if (!rs6000_output_addr_const_extra (STREAM, X)) \
2292 goto FAIL; \
2293 while (0)
2294
b6c9286a
MM		 2295/* uncomment for disabling the corresponding default options */
2296/* #define MACHINE_no_sched_interblock */
2297/* #define MACHINE_no_sched_speculative */
2298/* #define MACHINE_no_sched_speculative_load */
2299
766a866c
MM		 2300/* General flags. */
2301extern int flag_pic;
354b734b
MM		 2302extern int optimize;
2303extern int flag_expensive_optimizations;
a7df97e6 2304extern int frame_pointer_needed;
0ac081f6
AH		 2305
2306enum rs6000_builtins
2307{
2308 /* AltiVec builtins. */
f18c054f
DB		 2309 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2310 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2311 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2312 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2313 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2314 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2315 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2316 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
0ac081f6
AH		 2317 ALTIVEC_BUILTIN_VADDUBM,
2318 ALTIVEC_BUILTIN_VADDUHM,
2319 ALTIVEC_BUILTIN_VADDUWM,
2320 ALTIVEC_BUILTIN_VADDFP,
2321 ALTIVEC_BUILTIN_VADDCUW,
2322 ALTIVEC_BUILTIN_VADDUBS,
2323 ALTIVEC_BUILTIN_VADDSBS,
2324 ALTIVEC_BUILTIN_VADDUHS,
2325 ALTIVEC_BUILTIN_VADDSHS,
2326 ALTIVEC_BUILTIN_VADDUWS,
2327 ALTIVEC_BUILTIN_VADDSWS,
2328 ALTIVEC_BUILTIN_VAND,
2329 ALTIVEC_BUILTIN_VANDC,
2330 ALTIVEC_BUILTIN_VAVGUB,
2331 ALTIVEC_BUILTIN_VAVGSB,
2332 ALTIVEC_BUILTIN_VAVGUH,
2333 ALTIVEC_BUILTIN_VAVGSH,
2334 ALTIVEC_BUILTIN_VAVGUW,
2335 ALTIVEC_BUILTIN_VAVGSW,
617e0e1d
DB		 2336 ALTIVEC_BUILTIN_VCFUX,
2337 ALTIVEC_BUILTIN_VCFSX,
2338 ALTIVEC_BUILTIN_VCTSXS,
2339 ALTIVEC_BUILTIN_VCTUXS,
0ac081f6
AH		 2340 ALTIVEC_BUILTIN_VCMPBFP,
2341 ALTIVEC_BUILTIN_VCMPEQUB,
2342 ALTIVEC_BUILTIN_VCMPEQUH,
2343 ALTIVEC_BUILTIN_VCMPEQUW,
2344 ALTIVEC_BUILTIN_VCMPEQFP,
2345 ALTIVEC_BUILTIN_VCMPGEFP,
2346 ALTIVEC_BUILTIN_VCMPGTUB,
2347 ALTIVEC_BUILTIN_VCMPGTSB,
2348 ALTIVEC_BUILTIN_VCMPGTUH,
2349 ALTIVEC_BUILTIN_VCMPGTSH,
2350 ALTIVEC_BUILTIN_VCMPGTUW,
2351 ALTIVEC_BUILTIN_VCMPGTSW,
2352 ALTIVEC_BUILTIN_VCMPGTFP,
617e0e1d
DB		 2353 ALTIVEC_BUILTIN_VEXPTEFP,
2354 ALTIVEC_BUILTIN_VLOGEFP,
2212663f 2355 ALTIVEC_BUILTIN_VMADDFP,
0ac081f6
AH		 2356 ALTIVEC_BUILTIN_VMAXUB,
2357 ALTIVEC_BUILTIN_VMAXSB,
2358 ALTIVEC_BUILTIN_VMAXUH,
2359 ALTIVEC_BUILTIN_VMAXSH,
2360 ALTIVEC_BUILTIN_VMAXUW,
2361 ALTIVEC_BUILTIN_VMAXSW,
2362 ALTIVEC_BUILTIN_VMAXFP,
2212663f
DB		 2363 ALTIVEC_BUILTIN_VMHADDSHS,
2364 ALTIVEC_BUILTIN_VMHRADDSHS,
2365 ALTIVEC_BUILTIN_VMLADDUHM,
0ac081f6
AH		 2366 ALTIVEC_BUILTIN_VMRGHB,
2367 ALTIVEC_BUILTIN_VMRGHH,
2368 ALTIVEC_BUILTIN_VMRGHW,
2369 ALTIVEC_BUILTIN_VMRGLB,
2370 ALTIVEC_BUILTIN_VMRGLH,
2371 ALTIVEC_BUILTIN_VMRGLW,
2212663f
DB		 2372 ALTIVEC_BUILTIN_VMSUMUBM,
2373 ALTIVEC_BUILTIN_VMSUMMBM,
2374 ALTIVEC_BUILTIN_VMSUMUHM,
2375 ALTIVEC_BUILTIN_VMSUMSHM,
2376 ALTIVEC_BUILTIN_VMSUMUHS,
2377 ALTIVEC_BUILTIN_VMSUMSHS,
0ac081f6
AH		 2378 ALTIVEC_BUILTIN_VMINUB,
2379 ALTIVEC_BUILTIN_VMINSB,
2380 ALTIVEC_BUILTIN_VMINUH,
2381 ALTIVEC_BUILTIN_VMINSH,
2382 ALTIVEC_BUILTIN_VMINUW,
2383 ALTIVEC_BUILTIN_VMINSW,
2384 ALTIVEC_BUILTIN_VMINFP,
2385 ALTIVEC_BUILTIN_VMULEUB,
2386 ALTIVEC_BUILTIN_VMULESB,
2387 ALTIVEC_BUILTIN_VMULEUH,
2388 ALTIVEC_BUILTIN_VMULESH,
2389 ALTIVEC_BUILTIN_VMULOUB,
2390 ALTIVEC_BUILTIN_VMULOSB,
2391 ALTIVEC_BUILTIN_VMULOUH,
2392 ALTIVEC_BUILTIN_VMULOSH,
2212663f 2393 ALTIVEC_BUILTIN_VNMSUBFP,
0ac081f6
AH		 2394 ALTIVEC_BUILTIN_VNOR,
2395 ALTIVEC_BUILTIN_VOR,
617e0e1d
DB		 2396 ALTIVEC_BUILTIN_VSEL_4SI,
2397 ALTIVEC_BUILTIN_VSEL_4SF,
2398 ALTIVEC_BUILTIN_VSEL_8HI,
2399 ALTIVEC_BUILTIN_VSEL_16QI,
2212663f
DB		 2400 ALTIVEC_BUILTIN_VPERM_4SI,
2401 ALTIVEC_BUILTIN_VPERM_4SF,
2402 ALTIVEC_BUILTIN_VPERM_8HI,
2403 ALTIVEC_BUILTIN_VPERM_16QI,
0ac081f6
AH		 2404 ALTIVEC_BUILTIN_VPKUHUM,
2405 ALTIVEC_BUILTIN_VPKUWUM,
2406 ALTIVEC_BUILTIN_VPKPX,
2407 ALTIVEC_BUILTIN_VPKUHSS,
2408 ALTIVEC_BUILTIN_VPKSHSS,
2409 ALTIVEC_BUILTIN_VPKUWSS,
2410 ALTIVEC_BUILTIN_VPKSWSS,
2411 ALTIVEC_BUILTIN_VPKUHUS,
2412 ALTIVEC_BUILTIN_VPKSHUS,
2413 ALTIVEC_BUILTIN_VPKUWUS,
2414 ALTIVEC_BUILTIN_VPKSWUS,
617e0e1d
DB		 2415 ALTIVEC_BUILTIN_VREFP,
2416 ALTIVEC_BUILTIN_VRFIM,
2417 ALTIVEC_BUILTIN_VRFIN,
2418 ALTIVEC_BUILTIN_VRFIP,
2419 ALTIVEC_BUILTIN_VRFIZ,
0ac081f6
AH		 2420 ALTIVEC_BUILTIN_VRLB,
2421 ALTIVEC_BUILTIN_VRLH,
2422 ALTIVEC_BUILTIN_VRLW,
617e0e1d 2423 ALTIVEC_BUILTIN_VRSQRTEFP,
0ac081f6
AH		 2424 ALTIVEC_BUILTIN_VSLB,
2425 ALTIVEC_BUILTIN_VSLH,
2426 ALTIVEC_BUILTIN_VSLW,
2427 ALTIVEC_BUILTIN_VSL,
2428 ALTIVEC_BUILTIN_VSLO,
2212663f
DB		 2429 ALTIVEC_BUILTIN_VSPLTB,
2430 ALTIVEC_BUILTIN_VSPLTH,
2431 ALTIVEC_BUILTIN_VSPLTW,
2432 ALTIVEC_BUILTIN_VSPLTISB,
2433 ALTIVEC_BUILTIN_VSPLTISH,
2434 ALTIVEC_BUILTIN_VSPLTISW,
0ac081f6 2435 ALTIVEC_BUILTIN_VSRB,
f18c054f
DB		 2436 ALTIVEC_BUILTIN_VSRH,
2437 ALTIVEC_BUILTIN_VSRW,
0ac081f6
AH		 2438 ALTIVEC_BUILTIN_VSRAB,
2439 ALTIVEC_BUILTIN_VSRAH,
2440 ALTIVEC_BUILTIN_VSRAW,
2441 ALTIVEC_BUILTIN_VSR,
2442 ALTIVEC_BUILTIN_VSRO,
2443 ALTIVEC_BUILTIN_VSUBUBM,
2444 ALTIVEC_BUILTIN_VSUBUHM,
2445 ALTIVEC_BUILTIN_VSUBUWM,
2446 ALTIVEC_BUILTIN_VSUBFP,
2447 ALTIVEC_BUILTIN_VSUBCUW,
2448 ALTIVEC_BUILTIN_VSUBUBS,
2449 ALTIVEC_BUILTIN_VSUBSBS,
2450 ALTIVEC_BUILTIN_VSUBUHS,
2451 ALTIVEC_BUILTIN_VSUBSHS,
2452 ALTIVEC_BUILTIN_VSUBUWS,
2453 ALTIVEC_BUILTIN_VSUBSWS,
2454 ALTIVEC_BUILTIN_VSUM4UBS,
2455 ALTIVEC_BUILTIN_VSUM4SBS,
2456 ALTIVEC_BUILTIN_VSUM4SHS,
2457 ALTIVEC_BUILTIN_VSUM2SWS,
2458 ALTIVEC_BUILTIN_VSUMSWS,
24408032
AH		 2459 ALTIVEC_BUILTIN_VXOR,
2460 ALTIVEC_BUILTIN_VSLDOI_16QI,
2461 ALTIVEC_BUILTIN_VSLDOI_8HI,
2462 ALTIVEC_BUILTIN_VSLDOI_4SI,
20e26713
AH		 2463 ALTIVEC_BUILTIN_VSLDOI_4SF,
2464 ALTIVEC_BUILTIN_VUPKHSB,
2465 ALTIVEC_BUILTIN_VUPKHPX,
2466 ALTIVEC_BUILTIN_VUPKHSH,
2467 ALTIVEC_BUILTIN_VUPKLSB,
2468 ALTIVEC_BUILTIN_VUPKLPX,
fa066a23 2469 ALTIVEC_BUILTIN_VUPKLSH,
95385cbb
AH		 2470 ALTIVEC_BUILTIN_MTVSCR,
2471 ALTIVEC_BUILTIN_MFVSCR,
2472 ALTIVEC_BUILTIN_DSSALL,
2473 ALTIVEC_BUILTIN_DSS,
2474 ALTIVEC_BUILTIN_LVSL,
2475 ALTIVEC_BUILTIN_LVSR,
2476 ALTIVEC_BUILTIN_DSTT,
2477 ALTIVEC_BUILTIN_DSTST,
2478 ALTIVEC_BUILTIN_DSTSTT,
6525c0e7
AH		 2479 ALTIVEC_BUILTIN_DST,
2480 ALTIVEC_BUILTIN_LVEBX,
2481 ALTIVEC_BUILTIN_LVEHX,
2482 ALTIVEC_BUILTIN_LVEWX,
2483 ALTIVEC_BUILTIN_LVXL,
2484 ALTIVEC_BUILTIN_LVX,
2485 ALTIVEC_BUILTIN_STVX,
0b61703c
AP		 2486 ALTIVEC_BUILTIN_LVLX,
2487 ALTIVEC_BUILTIN_LVLXL,
2488 ALTIVEC_BUILTIN_LVRX,
2489 ALTIVEC_BUILTIN_LVRXL,
6525c0e7
AH		 2490 ALTIVEC_BUILTIN_STVEBX,
2491 ALTIVEC_BUILTIN_STVEHX,
2492 ALTIVEC_BUILTIN_STVEWX,
ae4b4a02 2493 ALTIVEC_BUILTIN_STVXL,
0b61703c
AP		 2494 ALTIVEC_BUILTIN_STVLX,
2495 ALTIVEC_BUILTIN_STVLXL,
2496 ALTIVEC_BUILTIN_STVRX,
2497 ALTIVEC_BUILTIN_STVRXL,
ae4b4a02
AH		 2498 ALTIVEC_BUILTIN_VCMPBFP_P,
2499 ALTIVEC_BUILTIN_VCMPEQFP_P,
2500 ALTIVEC_BUILTIN_VCMPEQUB_P,
2501 ALTIVEC_BUILTIN_VCMPEQUH_P,
2502 ALTIVEC_BUILTIN_VCMPEQUW_P,
2503 ALTIVEC_BUILTIN_VCMPGEFP_P,
2504 ALTIVEC_BUILTIN_VCMPGTFP_P,
2505 ALTIVEC_BUILTIN_VCMPGTSB_P,
2506 ALTIVEC_BUILTIN_VCMPGTSH_P,
2507 ALTIVEC_BUILTIN_VCMPGTSW_P,
2508 ALTIVEC_BUILTIN_VCMPGTUB_P,
2509 ALTIVEC_BUILTIN_VCMPGTUH_P,
100c4561
AH		 2510 ALTIVEC_BUILTIN_VCMPGTUW_P,
2511 ALTIVEC_BUILTIN_ABSS_V4SI,
2512 ALTIVEC_BUILTIN_ABSS_V8HI,
2513 ALTIVEC_BUILTIN_ABSS_V16QI,
2514 ALTIVEC_BUILTIN_ABS_V4SI,
2515 ALTIVEC_BUILTIN_ABS_V4SF,
2516 ALTIVEC_BUILTIN_ABS_V8HI,
8bb418a3 2517 ALTIVEC_BUILTIN_ABS_V16QI,
7ccf35ed
DN		 2518 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2519 ALTIVEC_BUILTIN_MASK_FOR_STORE,
7a4eca66
DE		 2520 ALTIVEC_BUILTIN_VEC_INIT_V4SI,
2521 ALTIVEC_BUILTIN_VEC_INIT_V8HI,
2522 ALTIVEC_BUILTIN_VEC_INIT_V16QI,
2523 ALTIVEC_BUILTIN_VEC_INIT_V4SF,
2524 ALTIVEC_BUILTIN_VEC_SET_V4SI,
2525 ALTIVEC_BUILTIN_VEC_SET_V8HI,
2526 ALTIVEC_BUILTIN_VEC_SET_V16QI,
2527 ALTIVEC_BUILTIN_VEC_SET_V4SF,
2528 ALTIVEC_BUILTIN_VEC_EXT_V4SI,
2529 ALTIVEC_BUILTIN_VEC_EXT_V8HI,
2530 ALTIVEC_BUILTIN_VEC_EXT_V16QI,
2531 ALTIVEC_BUILTIN_VEC_EXT_V4SF,
8bb418a3 2532
58646b77
PB		 2533 /* Altivec overloaded builtins. */
2534 ALTIVEC_BUILTIN_VCMPEQ_P,
2535 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
2536 ALTIVEC_BUILTIN_VCMPGT_P,
2537 ALTIVEC_BUILTIN_VCMPGE_P,
2538 ALTIVEC_BUILTIN_VEC_ABS,
2539 ALTIVEC_BUILTIN_VEC_ABSS,
2540 ALTIVEC_BUILTIN_VEC_ADD,
2541 ALTIVEC_BUILTIN_VEC_ADDC,
2542 ALTIVEC_BUILTIN_VEC_ADDS,
2543 ALTIVEC_BUILTIN_VEC_AND,
2544 ALTIVEC_BUILTIN_VEC_ANDC,
2545 ALTIVEC_BUILTIN_VEC_AVG,
266b4890 2546 ALTIVEC_BUILTIN_VEC_EXTRACT,
58646b77
PB		 2547 ALTIVEC_BUILTIN_VEC_CEIL,
2548 ALTIVEC_BUILTIN_VEC_CMPB,
2549 ALTIVEC_BUILTIN_VEC_CMPEQ,
2550 ALTIVEC_BUILTIN_VEC_CMPEQUB,
2551 ALTIVEC_BUILTIN_VEC_CMPEQUH,
2552 ALTIVEC_BUILTIN_VEC_CMPEQUW,
2553 ALTIVEC_BUILTIN_VEC_CMPGE,
2554 ALTIVEC_BUILTIN_VEC_CMPGT,
2555 ALTIVEC_BUILTIN_VEC_CMPLE,
2556 ALTIVEC_BUILTIN_VEC_CMPLT,
2557 ALTIVEC_BUILTIN_VEC_CTF,
2558 ALTIVEC_BUILTIN_VEC_CTS,
2559 ALTIVEC_BUILTIN_VEC_CTU,
2560 ALTIVEC_BUILTIN_VEC_DST,
2561 ALTIVEC_BUILTIN_VEC_DSTST,
2562 ALTIVEC_BUILTIN_VEC_DSTSTT,
2563 ALTIVEC_BUILTIN_VEC_DSTT,
2564 ALTIVEC_BUILTIN_VEC_EXPTE,
2565 ALTIVEC_BUILTIN_VEC_FLOOR,
2566 ALTIVEC_BUILTIN_VEC_LD,
2567 ALTIVEC_BUILTIN_VEC_LDE,
2568 ALTIVEC_BUILTIN_VEC_LDL,
2569 ALTIVEC_BUILTIN_VEC_LOGE,
2570 ALTIVEC_BUILTIN_VEC_LVEBX,
2571 ALTIVEC_BUILTIN_VEC_LVEHX,
2572 ALTIVEC_BUILTIN_VEC_LVEWX,
0b61703c
AP		 2573 ALTIVEC_BUILTIN_VEC_LVLX,
2574 ALTIVEC_BUILTIN_VEC_LVLXL,
2575 ALTIVEC_BUILTIN_VEC_LVRX,
2576 ALTIVEC_BUILTIN_VEC_LVRXL,
58646b77
PB		 2577 ALTIVEC_BUILTIN_VEC_LVSL,
2578 ALTIVEC_BUILTIN_VEC_LVSR,
2579 ALTIVEC_BUILTIN_VEC_MADD,
2580 ALTIVEC_BUILTIN_VEC_MADDS,
2581 ALTIVEC_BUILTIN_VEC_MAX,
2582 ALTIVEC_BUILTIN_VEC_MERGEH,
2583 ALTIVEC_BUILTIN_VEC_MERGEL,
2584 ALTIVEC_BUILTIN_VEC_MIN,
2585 ALTIVEC_BUILTIN_VEC_MLADD,
2586 ALTIVEC_BUILTIN_VEC_MPERM,
2587 ALTIVEC_BUILTIN_VEC_MRADDS,
2588 ALTIVEC_BUILTIN_VEC_MRGHB,
2589 ALTIVEC_BUILTIN_VEC_MRGHH,
2590 ALTIVEC_BUILTIN_VEC_MRGHW,
2591 ALTIVEC_BUILTIN_VEC_MRGLB,
2592 ALTIVEC_BUILTIN_VEC_MRGLH,
2593 ALTIVEC_BUILTIN_VEC_MRGLW,
2594 ALTIVEC_BUILTIN_VEC_MSUM,
2595 ALTIVEC_BUILTIN_VEC_MSUMS,
2596 ALTIVEC_BUILTIN_VEC_MTVSCR,
2597 ALTIVEC_BUILTIN_VEC_MULE,
2598 ALTIVEC_BUILTIN_VEC_MULO,
2599 ALTIVEC_BUILTIN_VEC_NMSUB,
2600 ALTIVEC_BUILTIN_VEC_NOR,
2601 ALTIVEC_BUILTIN_VEC_OR,
2602 ALTIVEC_BUILTIN_VEC_PACK,
2603 ALTIVEC_BUILTIN_VEC_PACKPX,
2604 ALTIVEC_BUILTIN_VEC_PACKS,
2605 ALTIVEC_BUILTIN_VEC_PACKSU,
2606 ALTIVEC_BUILTIN_VEC_PERM,
2607 ALTIVEC_BUILTIN_VEC_RE,
2608 ALTIVEC_BUILTIN_VEC_RL,
2609 ALTIVEC_BUILTIN_VEC_ROUND,
2610 ALTIVEC_BUILTIN_VEC_RSQRTE,
2611 ALTIVEC_BUILTIN_VEC_SEL,
2612 ALTIVEC_BUILTIN_VEC_SL,
2613 ALTIVEC_BUILTIN_VEC_SLD,
2614 ALTIVEC_BUILTIN_VEC_SLL,
2615 ALTIVEC_BUILTIN_VEC_SLO,
2616 ALTIVEC_BUILTIN_VEC_SPLAT,
2617 ALTIVEC_BUILTIN_VEC_SPLAT_S16,
2618 ALTIVEC_BUILTIN_VEC_SPLAT_S32,
2619 ALTIVEC_BUILTIN_VEC_SPLAT_S8,
2620 ALTIVEC_BUILTIN_VEC_SPLAT_U16,
2621 ALTIVEC_BUILTIN_VEC_SPLAT_U32,
2622 ALTIVEC_BUILTIN_VEC_SPLAT_U8,
2623 ALTIVEC_BUILTIN_VEC_SPLTB,
2624 ALTIVEC_BUILTIN_VEC_SPLTH,
2625 ALTIVEC_BUILTIN_VEC_SPLTW,
2626 ALTIVEC_BUILTIN_VEC_SR,
2627 ALTIVEC_BUILTIN_VEC_SRA,
2628 ALTIVEC_BUILTIN_VEC_SRL,
2629 ALTIVEC_BUILTIN_VEC_SRO,
2630 ALTIVEC_BUILTIN_VEC_ST,
2631 ALTIVEC_BUILTIN_VEC_STE,
2632 ALTIVEC_BUILTIN_VEC_STL,
2633 ALTIVEC_BUILTIN_VEC_STVEBX,
2634 ALTIVEC_BUILTIN_VEC_STVEHX,
2635 ALTIVEC_BUILTIN_VEC_STVEWX,
0b61703c
AP		 2636 ALTIVEC_BUILTIN_VEC_STVLX,
2637 ALTIVEC_BUILTIN_VEC_STVLXL,
2638 ALTIVEC_BUILTIN_VEC_STVRX,
2639 ALTIVEC_BUILTIN_VEC_STVRXL,
58646b77
PB		 2640 ALTIVEC_BUILTIN_VEC_SUB,
2641 ALTIVEC_BUILTIN_VEC_SUBC,
2642 ALTIVEC_BUILTIN_VEC_SUBS,
2643 ALTIVEC_BUILTIN_VEC_SUM2S,
2644 ALTIVEC_BUILTIN_VEC_SUM4S,
2645 ALTIVEC_BUILTIN_VEC_SUMS,
2646 ALTIVEC_BUILTIN_VEC_TRUNC,
2647 ALTIVEC_BUILTIN_VEC_UNPACKH,
2648 ALTIVEC_BUILTIN_VEC_UNPACKL,
2649 ALTIVEC_BUILTIN_VEC_VADDFP,
2650 ALTIVEC_BUILTIN_VEC_VADDSBS,
2651 ALTIVEC_BUILTIN_VEC_VADDSHS,
2652 ALTIVEC_BUILTIN_VEC_VADDSWS,
2653 ALTIVEC_BUILTIN_VEC_VADDUBM,
2654 ALTIVEC_BUILTIN_VEC_VADDUBS,
2655 ALTIVEC_BUILTIN_VEC_VADDUHM,
2656 ALTIVEC_BUILTIN_VEC_VADDUHS,
2657 ALTIVEC_BUILTIN_VEC_VADDUWM,
2658 ALTIVEC_BUILTIN_VEC_VADDUWS,
2659 ALTIVEC_BUILTIN_VEC_VAVGSB,
2660 ALTIVEC_BUILTIN_VEC_VAVGSH,
2661 ALTIVEC_BUILTIN_VEC_VAVGSW,
2662 ALTIVEC_BUILTIN_VEC_VAVGUB,
2663 ALTIVEC_BUILTIN_VEC_VAVGUH,
2664 ALTIVEC_BUILTIN_VEC_VAVGUW,
2665 ALTIVEC_BUILTIN_VEC_VCFSX,
2666 ALTIVEC_BUILTIN_VEC_VCFUX,
2667 ALTIVEC_BUILTIN_VEC_VCMPEQFP,
2668 ALTIVEC_BUILTIN_VEC_VCMPEQUB,
2669 ALTIVEC_BUILTIN_VEC_VCMPEQUH,
2670 ALTIVEC_BUILTIN_VEC_VCMPEQUW,
2671 ALTIVEC_BUILTIN_VEC_VCMPGTFP,
2672 ALTIVEC_BUILTIN_VEC_VCMPGTSB,
2673 ALTIVEC_BUILTIN_VEC_VCMPGTSH,
2674 ALTIVEC_BUILTIN_VEC_VCMPGTSW,
2675 ALTIVEC_BUILTIN_VEC_VCMPGTUB,
2676 ALTIVEC_BUILTIN_VEC_VCMPGTUH,
2677 ALTIVEC_BUILTIN_VEC_VCMPGTUW,
2678 ALTIVEC_BUILTIN_VEC_VMAXFP,
2679 ALTIVEC_BUILTIN_VEC_VMAXSB,
2680 ALTIVEC_BUILTIN_VEC_VMAXSH,
2681 ALTIVEC_BUILTIN_VEC_VMAXSW,
2682 ALTIVEC_BUILTIN_VEC_VMAXUB,
2683 ALTIVEC_BUILTIN_VEC_VMAXUH,
2684 ALTIVEC_BUILTIN_VEC_VMAXUW,
2685 ALTIVEC_BUILTIN_VEC_VMINFP,
2686 ALTIVEC_BUILTIN_VEC_VMINSB,
2687 ALTIVEC_BUILTIN_VEC_VMINSH,
2688 ALTIVEC_BUILTIN_VEC_VMINSW,
2689 ALTIVEC_BUILTIN_VEC_VMINUB,
2690 ALTIVEC_BUILTIN_VEC_VMINUH,
2691 ALTIVEC_BUILTIN_VEC_VMINUW,
2692 ALTIVEC_BUILTIN_VEC_VMRGHB,
2693 ALTIVEC_BUILTIN_VEC_VMRGHH,
2694 ALTIVEC_BUILTIN_VEC_VMRGHW,
2695 ALTIVEC_BUILTIN_VEC_VMRGLB,
2696 ALTIVEC_BUILTIN_VEC_VMRGLH,
2697 ALTIVEC_BUILTIN_VEC_VMRGLW,
2698 ALTIVEC_BUILTIN_VEC_VMSUMMBM,
2699 ALTIVEC_BUILTIN_VEC_VMSUMSHM,
2700 ALTIVEC_BUILTIN_VEC_VMSUMSHS,
2701 ALTIVEC_BUILTIN_VEC_VMSUMUBM,
2702 ALTIVEC_BUILTIN_VEC_VMSUMUHM,
2703 ALTIVEC_BUILTIN_VEC_VMSUMUHS,
2704 ALTIVEC_BUILTIN_VEC_VMULESB,
2705 ALTIVEC_BUILTIN_VEC_VMULESH,
2706 ALTIVEC_BUILTIN_VEC_VMULEUB,
2707 ALTIVEC_BUILTIN_VEC_VMULEUH,
2708 ALTIVEC_BUILTIN_VEC_VMULOSB,
2709 ALTIVEC_BUILTIN_VEC_VMULOSH,
2710 ALTIVEC_BUILTIN_VEC_VMULOUB,
2711 ALTIVEC_BUILTIN_VEC_VMULOUH,
2712 ALTIVEC_BUILTIN_VEC_VPKSHSS,
2713 ALTIVEC_BUILTIN_VEC_VPKSHUS,
2714 ALTIVEC_BUILTIN_VEC_VPKSWSS,
2715 ALTIVEC_BUILTIN_VEC_VPKSWUS,
2716 ALTIVEC_BUILTIN_VEC_VPKUHUM,
2717 ALTIVEC_BUILTIN_VEC_VPKUHUS,
2718 ALTIVEC_BUILTIN_VEC_VPKUWUM,
2719 ALTIVEC_BUILTIN_VEC_VPKUWUS,
2720 ALTIVEC_BUILTIN_VEC_VRLB,
2721 ALTIVEC_BUILTIN_VEC_VRLH,
2722 ALTIVEC_BUILTIN_VEC_VRLW,
2723 ALTIVEC_BUILTIN_VEC_VSLB,
2724 ALTIVEC_BUILTIN_VEC_VSLH,
2725 ALTIVEC_BUILTIN_VEC_VSLW,
2726 ALTIVEC_BUILTIN_VEC_VSPLTB,
2727 ALTIVEC_BUILTIN_VEC_VSPLTH,
2728 ALTIVEC_BUILTIN_VEC_VSPLTW,
2729 ALTIVEC_BUILTIN_VEC_VSRAB,
2730 ALTIVEC_BUILTIN_VEC_VSRAH,
2731 ALTIVEC_BUILTIN_VEC_VSRAW,
2732 ALTIVEC_BUILTIN_VEC_VSRB,
2733 ALTIVEC_BUILTIN_VEC_VSRH,
2734 ALTIVEC_BUILTIN_VEC_VSRW,
2735 ALTIVEC_BUILTIN_VEC_VSUBFP,
2736 ALTIVEC_BUILTIN_VEC_VSUBSBS,
2737 ALTIVEC_BUILTIN_VEC_VSUBSHS,
2738 ALTIVEC_BUILTIN_VEC_VSUBSWS,
2739 ALTIVEC_BUILTIN_VEC_VSUBUBM,
2740 ALTIVEC_BUILTIN_VEC_VSUBUBS,
2741 ALTIVEC_BUILTIN_VEC_VSUBUHM,
2742 ALTIVEC_BUILTIN_VEC_VSUBUHS,
2743 ALTIVEC_BUILTIN_VEC_VSUBUWM,
2744 ALTIVEC_BUILTIN_VEC_VSUBUWS,
2745 ALTIVEC_BUILTIN_VEC_VSUM4SBS,
2746 ALTIVEC_BUILTIN_VEC_VSUM4SHS,
2747 ALTIVEC_BUILTIN_VEC_VSUM4UBS,
2748 ALTIVEC_BUILTIN_VEC_VUPKHPX,
2749 ALTIVEC_BUILTIN_VEC_VUPKHSB,
2750 ALTIVEC_BUILTIN_VEC_VUPKHSH,
2751 ALTIVEC_BUILTIN_VEC_VUPKLPX,
2752 ALTIVEC_BUILTIN_VEC_VUPKLSB,
2753 ALTIVEC_BUILTIN_VEC_VUPKLSH,
2754 ALTIVEC_BUILTIN_VEC_XOR,
2755 ALTIVEC_BUILTIN_VEC_STEP,
266b4890
AP		 2756 ALTIVEC_BUILTIN_VEC_PROMOTE,
2757 ALTIVEC_BUILTIN_VEC_INSERT,
2758 ALTIVEC_BUILTIN_VEC_SPLATS,
2759 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_SPLATS,
58646b77 2760
a3170dc6 2761 /* SPE builtins. */
8bb418a3 2762 SPE_BUILTIN_EVADDW,
a3170dc6
AH		 2763 SPE_BUILTIN_EVAND,
2764 SPE_BUILTIN_EVANDC,
2765 SPE_BUILTIN_EVDIVWS,
2766 SPE_BUILTIN_EVDIVWU,
2767 SPE_BUILTIN_EVEQV,
2768 SPE_BUILTIN_EVFSADD,
2769 SPE_BUILTIN_EVFSDIV,
2770 SPE_BUILTIN_EVFSMUL,
2771 SPE_BUILTIN_EVFSSUB,
2772 SPE_BUILTIN_EVLDDX,
2773 SPE_BUILTIN_EVLDHX,
2774 SPE_BUILTIN_EVLDWX,
2775 SPE_BUILTIN_EVLHHESPLATX,
2776 SPE_BUILTIN_EVLHHOSSPLATX,
2777 SPE_BUILTIN_EVLHHOUSPLATX,
2778 SPE_BUILTIN_EVLWHEX,
2779 SPE_BUILTIN_EVLWHOSX,
2780 SPE_BUILTIN_EVLWHOUX,
2781 SPE_BUILTIN_EVLWHSPLATX,
2782 SPE_BUILTIN_EVLWWSPLATX,
2783 SPE_BUILTIN_EVMERGEHI,
2784 SPE_BUILTIN_EVMERGEHILO,
2785 SPE_BUILTIN_EVMERGELO,
2786 SPE_BUILTIN_EVMERGELOHI,
2787 SPE_BUILTIN_EVMHEGSMFAA,
2788 SPE_BUILTIN_EVMHEGSMFAN,
2789 SPE_BUILTIN_EVMHEGSMIAA,
2790 SPE_BUILTIN_EVMHEGSMIAN,
2791 SPE_BUILTIN_EVMHEGUMIAA,
2792 SPE_BUILTIN_EVMHEGUMIAN,
2793 SPE_BUILTIN_EVMHESMF,
2794 SPE_BUILTIN_EVMHESMFA,
2795 SPE_BUILTIN_EVMHESMFAAW,
2796 SPE_BUILTIN_EVMHESMFANW,
2797 SPE_BUILTIN_EVMHESMI,
2798 SPE_BUILTIN_EVMHESMIA,
2799 SPE_BUILTIN_EVMHESMIAAW,
2800 SPE_BUILTIN_EVMHESMIANW,
2801 SPE_BUILTIN_EVMHESSF,
2802 SPE_BUILTIN_EVMHESSFA,
2803 SPE_BUILTIN_EVMHESSFAAW,
2804 SPE_BUILTIN_EVMHESSFANW,
2805 SPE_BUILTIN_EVMHESSIAAW,
2806 SPE_BUILTIN_EVMHESSIANW,
2807 SPE_BUILTIN_EVMHEUMI,
2808 SPE_BUILTIN_EVMHEUMIA,
2809 SPE_BUILTIN_EVMHEUMIAAW,
2810 SPE_BUILTIN_EVMHEUMIANW,
2811 SPE_BUILTIN_EVMHEUSIAAW,
2812 SPE_BUILTIN_EVMHEUSIANW,
2813 SPE_BUILTIN_EVMHOGSMFAA,
2814 SPE_BUILTIN_EVMHOGSMFAN,
2815 SPE_BUILTIN_EVMHOGSMIAA,
2816 SPE_BUILTIN_EVMHOGSMIAN,
2817 SPE_BUILTIN_EVMHOGUMIAA,
2818 SPE_BUILTIN_EVMHOGUMIAN,
2819 SPE_BUILTIN_EVMHOSMF,
2820 SPE_BUILTIN_EVMHOSMFA,
2821 SPE_BUILTIN_EVMHOSMFAAW,
2822 SPE_BUILTIN_EVMHOSMFANW,
2823 SPE_BUILTIN_EVMHOSMI,
2824 SPE_BUILTIN_EVMHOSMIA,
2825 SPE_BUILTIN_EVMHOSMIAAW,
2826 SPE_BUILTIN_EVMHOSMIANW,
2827 SPE_BUILTIN_EVMHOSSF,
2828 SPE_BUILTIN_EVMHOSSFA,
2829 SPE_BUILTIN_EVMHOSSFAAW,
2830 SPE_BUILTIN_EVMHOSSFANW,
2831 SPE_BUILTIN_EVMHOSSIAAW,
2832 SPE_BUILTIN_EVMHOSSIANW,
2833 SPE_BUILTIN_EVMHOUMI,
2834 SPE_BUILTIN_EVMHOUMIA,
2835 SPE_BUILTIN_EVMHOUMIAAW,
2836 SPE_BUILTIN_EVMHOUMIANW,
2837 SPE_BUILTIN_EVMHOUSIAAW,
2838 SPE_BUILTIN_EVMHOUSIANW,
2839 SPE_BUILTIN_EVMWHSMF,
2840 SPE_BUILTIN_EVMWHSMFA,
2841 SPE_BUILTIN_EVMWHSMI,
2842 SPE_BUILTIN_EVMWHSMIA,
2843 SPE_BUILTIN_EVMWHSSF,
2844 SPE_BUILTIN_EVMWHSSFA,
2845 SPE_BUILTIN_EVMWHUMI,
2846 SPE_BUILTIN_EVMWHUMIA,
a3170dc6
AH		 2847 SPE_BUILTIN_EVMWLSMIAAW,
2848 SPE_BUILTIN_EVMWLSMIANW,
a3170dc6
AH		 2849 SPE_BUILTIN_EVMWLSSIAAW,
2850 SPE_BUILTIN_EVMWLSSIANW,
2851 SPE_BUILTIN_EVMWLUMI,
2852 SPE_BUILTIN_EVMWLUMIA,
2853 SPE_BUILTIN_EVMWLUMIAAW,
2854 SPE_BUILTIN_EVMWLUMIANW,
2855 SPE_BUILTIN_EVMWLUSIAAW,
2856 SPE_BUILTIN_EVMWLUSIANW,
2857 SPE_BUILTIN_EVMWSMF,
2858 SPE_BUILTIN_EVMWSMFA,
2859 SPE_BUILTIN_EVMWSMFAA,
2860 SPE_BUILTIN_EVMWSMFAN,
2861 SPE_BUILTIN_EVMWSMI,
2862 SPE_BUILTIN_EVMWSMIA,
2863 SPE_BUILTIN_EVMWSMIAA,
2864 SPE_BUILTIN_EVMWSMIAN,
2865 SPE_BUILTIN_EVMWHSSFAA,
2866 SPE_BUILTIN_EVMWSSF,
2867 SPE_BUILTIN_EVMWSSFA,
2868 SPE_BUILTIN_EVMWSSFAA,
2869 SPE_BUILTIN_EVMWSSFAN,
2870 SPE_BUILTIN_EVMWUMI,
2871 SPE_BUILTIN_EVMWUMIA,
2872 SPE_BUILTIN_EVMWUMIAA,
2873 SPE_BUILTIN_EVMWUMIAN,
2874 SPE_BUILTIN_EVNAND,
2875 SPE_BUILTIN_EVNOR,
2876 SPE_BUILTIN_EVOR,
2877 SPE_BUILTIN_EVORC,
2878 SPE_BUILTIN_EVRLW,
2879 SPE_BUILTIN_EVSLW,
2880 SPE_BUILTIN_EVSRWS,
2881 SPE_BUILTIN_EVSRWU,
2882 SPE_BUILTIN_EVSTDDX,
2883 SPE_BUILTIN_EVSTDHX,
2884 SPE_BUILTIN_EVSTDWX,
2885 SPE_BUILTIN_EVSTWHEX,
2886 SPE_BUILTIN_EVSTWHOX,
2887 SPE_BUILTIN_EVSTWWEX,
2888 SPE_BUILTIN_EVSTWWOX,
2889 SPE_BUILTIN_EVSUBFW,
2890 SPE_BUILTIN_EVXOR,
2891 SPE_BUILTIN_EVABS,
2892 SPE_BUILTIN_EVADDSMIAAW,
2893 SPE_BUILTIN_EVADDSSIAAW,
2894 SPE_BUILTIN_EVADDUMIAAW,
2895 SPE_BUILTIN_EVADDUSIAAW,
2896 SPE_BUILTIN_EVCNTLSW,
2897 SPE_BUILTIN_EVCNTLZW,
2898 SPE_BUILTIN_EVEXTSB,
2899 SPE_BUILTIN_EVEXTSH,
2900 SPE_BUILTIN_EVFSABS,
2901 SPE_BUILTIN_EVFSCFSF,
2902 SPE_BUILTIN_EVFSCFSI,
2903 SPE_BUILTIN_EVFSCFUF,
2904 SPE_BUILTIN_EVFSCFUI,
2905 SPE_BUILTIN_EVFSCTSF,
2906 SPE_BUILTIN_EVFSCTSI,
2907 SPE_BUILTIN_EVFSCTSIZ,
2908 SPE_BUILTIN_EVFSCTUF,
2909 SPE_BUILTIN_EVFSCTUI,
2910 SPE_BUILTIN_EVFSCTUIZ,
2911 SPE_BUILTIN_EVFSNABS,
2912 SPE_BUILTIN_EVFSNEG,
2913 SPE_BUILTIN_EVMRA,
2914 SPE_BUILTIN_EVNEG,
2915 SPE_BUILTIN_EVRNDW,
2916 SPE_BUILTIN_EVSUBFSMIAAW,
2917 SPE_BUILTIN_EVSUBFSSIAAW,
2918 SPE_BUILTIN_EVSUBFUMIAAW,
2919 SPE_BUILTIN_EVSUBFUSIAAW,
2920 SPE_BUILTIN_EVADDIW,
2921 SPE_BUILTIN_EVLDD,
2922 SPE_BUILTIN_EVLDH,
2923 SPE_BUILTIN_EVLDW,
2924 SPE_BUILTIN_EVLHHESPLAT,
2925 SPE_BUILTIN_EVLHHOSSPLAT,
2926 SPE_BUILTIN_EVLHHOUSPLAT,
2927 SPE_BUILTIN_EVLWHE,
2928 SPE_BUILTIN_EVLWHOS,
2929 SPE_BUILTIN_EVLWHOU,
2930 SPE_BUILTIN_EVLWHSPLAT,
2931 SPE_BUILTIN_EVLWWSPLAT,
2932 SPE_BUILTIN_EVRLWI,
2933 SPE_BUILTIN_EVSLWI,
2934 SPE_BUILTIN_EVSRWIS,
2935 SPE_BUILTIN_EVSRWIU,
2936 SPE_BUILTIN_EVSTDD,
2937 SPE_BUILTIN_EVSTDH,
2938 SPE_BUILTIN_EVSTDW,
2939 SPE_BUILTIN_EVSTWHE,
2940 SPE_BUILTIN_EVSTWHO,
2941 SPE_BUILTIN_EVSTWWE,
2942 SPE_BUILTIN_EVSTWWO,
2943 SPE_BUILTIN_EVSUBIFW,
2944
2945 /* Compares. */
2946 SPE_BUILTIN_EVCMPEQ,
2947 SPE_BUILTIN_EVCMPGTS,
2948 SPE_BUILTIN_EVCMPGTU,
2949 SPE_BUILTIN_EVCMPLTS,
2950 SPE_BUILTIN_EVCMPLTU,
2951 SPE_BUILTIN_EVFSCMPEQ,
2952 SPE_BUILTIN_EVFSCMPGT,
2953 SPE_BUILTIN_EVFSCMPLT,
2954 SPE_BUILTIN_EVFSTSTEQ,
2955 SPE_BUILTIN_EVFSTSTGT,
2956 SPE_BUILTIN_EVFSTSTLT,
2957
2958 /* EVSEL compares. */
2959 SPE_BUILTIN_EVSEL_CMPEQ,
2960 SPE_BUILTIN_EVSEL_CMPGTS,
2961 SPE_BUILTIN_EVSEL_CMPGTU,
2962 SPE_BUILTIN_EVSEL_CMPLTS,
2963 SPE_BUILTIN_EVSEL_CMPLTU,
2964 SPE_BUILTIN_EVSEL_FSCMPEQ,
2965 SPE_BUILTIN_EVSEL_FSCMPGT,
2966 SPE_BUILTIN_EVSEL_FSCMPLT,
2967 SPE_BUILTIN_EVSEL_FSTSTEQ,
2968 SPE_BUILTIN_EVSEL_FSTSTGT,
2969 SPE_BUILTIN_EVSEL_FSTSTLT,
2970
2971 SPE_BUILTIN_EVSPLATFI,
2972 SPE_BUILTIN_EVSPLATI,
2973 SPE_BUILTIN_EVMWHSSMAA,
2974 SPE_BUILTIN_EVMWHSMFAA,
2975 SPE_BUILTIN_EVMWHSMIAA,
2976 SPE_BUILTIN_EVMWHUSIAA,
2977 SPE_BUILTIN_EVMWHUMIAA,
2978 SPE_BUILTIN_EVMWHSSFAN,
2979 SPE_BUILTIN_EVMWHSSIAN,
2980 SPE_BUILTIN_EVMWHSMFAN,
2981 SPE_BUILTIN_EVMWHSMIAN,
2982 SPE_BUILTIN_EVMWHUSIAN,
2983 SPE_BUILTIN_EVMWHUMIAN,
2984 SPE_BUILTIN_EVMWHGSSFAA,
2985 SPE_BUILTIN_EVMWHGSMFAA,
2986 SPE_BUILTIN_EVMWHGSMIAA,
2987 SPE_BUILTIN_EVMWHGUMIAA,
2988 SPE_BUILTIN_EVMWHGSSFAN,
2989 SPE_BUILTIN_EVMWHGSMFAN,
2990 SPE_BUILTIN_EVMWHGSMIAN,
2991 SPE_BUILTIN_EVMWHGUMIAN,
2992 SPE_BUILTIN_MTSPEFSCR,
2993 SPE_BUILTIN_MFSPEFSCR,
58646b77
PB		 2994 SPE_BUILTIN_BRINC,
2995
96038623
DE		 2996 /* PAIRED builtins. */
2997 PAIRED_BUILTIN_DIVV2SF3,
2998 PAIRED_BUILTIN_ABSV2SF2,
2999 PAIRED_BUILTIN_NEGV2SF2,
3000 PAIRED_BUILTIN_SQRTV2SF2,
3001 PAIRED_BUILTIN_ADDV2SF3,
3002 PAIRED_BUILTIN_SUBV2SF3,
3003 PAIRED_BUILTIN_RESV2SF2,
3004 PAIRED_BUILTIN_MULV2SF3,
3005 PAIRED_BUILTIN_MSUB,
3006 PAIRED_BUILTIN_MADD,
3007 PAIRED_BUILTIN_NMSUB,
3008 PAIRED_BUILTIN_NMADD,
3009 PAIRED_BUILTIN_NABSV2SF2,
3010 PAIRED_BUILTIN_SUM0,
3011 PAIRED_BUILTIN_SUM1,
3012 PAIRED_BUILTIN_MULS0,
3013 PAIRED_BUILTIN_MULS1,
3014 PAIRED_BUILTIN_MERGE00,
3015 PAIRED_BUILTIN_MERGE01,
3016 PAIRED_BUILTIN_MERGE10,
3017 PAIRED_BUILTIN_MERGE11,
3018 PAIRED_BUILTIN_MADDS0,
3019 PAIRED_BUILTIN_MADDS1,
3020 PAIRED_BUILTIN_STX,
3021 PAIRED_BUILTIN_LX,
49e39588 3022 PAIRED_BUILTIN_SELV2SF4,
96038623
DE		 3023 PAIRED_BUILTIN_CMPU0,
3024 PAIRED_BUILTIN_CMPU1,
3025
9c78b944
DE		 3026 RS6000_BUILTIN_RECIP,
3027 RS6000_BUILTIN_RECIPF,
3028 RS6000_BUILTIN_RSQRTF,
3029
58646b77
PB		 3030 RS6000_BUILTIN_COUNT
3031};
3032
3033enum rs6000_builtin_type_index
3034{
3035 RS6000_BTI_NOT_OPAQUE,
3036 RS6000_BTI_opaque_V2SI,
3037 RS6000_BTI_opaque_V2SF,
3038 RS6000_BTI_opaque_p_V2SI,
3039 RS6000_BTI_opaque_V4SI,
3040 RS6000_BTI_V16QI,
3041 RS6000_BTI_V2SI,
3042 RS6000_BTI_V2SF,
3043 RS6000_BTI_V4HI,
3044 RS6000_BTI_V4SI,
3045 RS6000_BTI_V4SF,
3046 RS6000_BTI_V8HI,
3047 RS6000_BTI_unsigned_V16QI,
3048 RS6000_BTI_unsigned_V8HI,
3049 RS6000_BTI_unsigned_V4SI,
3050 RS6000_BTI_bool_char, /* __bool char */
3051 RS6000_BTI_bool_short, /* __bool short */
3052 RS6000_BTI_bool_int, /* __bool int */
3053 RS6000_BTI_pixel, /* __pixel */
3054 RS6000_BTI_bool_V16QI, /* __vector __bool char */
3055 RS6000_BTI_bool_V8HI, /* __vector __bool short */
3056 RS6000_BTI_bool_V4SI, /* __vector __bool int */
3057 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
3058 RS6000_BTI_long, /* long_integer_type_node */
3059 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
3060 RS6000_BTI_INTQI, /* intQI_type_node */
3061 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
3062 RS6000_BTI_INTHI, /* intHI_type_node */
3063 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
3064 RS6000_BTI_INTSI, /* intSI_type_node */
3065 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
3066 RS6000_BTI_float, /* float_type_node */
3067 RS6000_BTI_void, /* void_type_node */
3068 RS6000_BTI_MAX
0ac081f6 3069};
58646b77
PB		 3070
3071
3072#define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
3073#define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
3074#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
3075#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
3076#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
3077#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
3078#define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
3079#define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
3080#define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
3081#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
3082#define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
3083#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
3084#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
3085#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
3086#define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
3087#define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
3088#define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
3089#define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
3090#define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
3091#define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
3092#define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
3093#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
3094
3095#define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
3096#define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
3097#define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
3098#define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
3099#define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
3100#define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
3101#define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
3102#define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
3103#define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
3104#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
3105
3106extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
3107extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
3108
Mirror of https://gcc.gnu.org/git/gcc.git