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f045b2c9 | 1 | /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
16c484c7 | 3 | 2000, 2001, 2002 Free Software Foundation, Inc. |
6a7ec0a7 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
f045b2c9 RS |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
f045b2c9 RS |
22 | |
23 | ||
24 | /* Note that some other tm.h files include this one and then override | |
9ebbca7d | 25 | many of the definitions. */ |
f045b2c9 | 26 | |
9ebbca7d GK |
27 | /* Definitions for the object file format. These are set at |
28 | compile-time. */ | |
f045b2c9 | 29 | |
9ebbca7d GK |
30 | #define OBJECT_XCOFF 1 |
31 | #define OBJECT_ELF 2 | |
32 | #define OBJECT_PEF 3 | |
ee890fe2 | 33 | #define OBJECT_MACHO 4 |
f045b2c9 | 34 | |
9ebbca7d | 35 | #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) |
2bfcf297 | 36 | #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) |
9ebbca7d | 37 | #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) |
ee890fe2 | 38 | #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) |
f045b2c9 | 39 | |
2bfcf297 DB |
40 | #ifndef TARGET_AIX |
41 | #define TARGET_AIX 0 | |
42 | #endif | |
43 | ||
8e3f41e7 MM |
44 | /* Default string to use for cpu if not specified. */ |
45 | #ifndef TARGET_CPU_DEFAULT | |
46 | #define TARGET_CPU_DEFAULT ((char *)0) | |
47 | #endif | |
48 | ||
f984d8df DB |
49 | /* Common ASM definitions used by ASM_SPEC among the various targets |
50 | for handling -mcpu=xxx switches. */ | |
51 | #define ASM_CPU_SPEC \ | |
52 | "%{!mcpu*: \ | |
53 | %{mpower: %{!mpower2: -mpwr}} \ | |
54 | %{mpower2: -mpwrx} \ | |
55 | %{mpowerpc*: -mppc} \ | |
56 | %{mno-power: %{!mpowerpc*: -mcom}} \ | |
57 | %{!mno-power: %{!mpower2: %(asm_default)}}} \ | |
58 | %{mcpu=common: -mcom} \ | |
59 | %{mcpu=power: -mpwr} \ | |
60 | %{mcpu=power2: -mpwrx} \ | |
309323c2 | 61 | %{mcpu=power3: -m604} \ |
957e9e48 | 62 | %{mcpu=power4: -mpower4} \ |
f984d8df DB |
63 | %{mcpu=powerpc: -mppc} \ |
64 | %{mcpu=rios: -mpwr} \ | |
65 | %{mcpu=rios1: -mpwr} \ | |
66 | %{mcpu=rios2: -mpwrx} \ | |
67 | %{mcpu=rsc: -mpwr} \ | |
68 | %{mcpu=rsc1: -mpwr} \ | |
69 | %{mcpu=401: -mppc} \ | |
61a8515c JS |
70 | %{mcpu=403: -m403} \ |
71 | %{mcpu=405: -m405} \ | |
4977bab6 | 72 | %{mcpu=405f: -m405} \ |
f984d8df DB |
73 | %{mcpu=505: -mppc} \ |
74 | %{mcpu=601: -m601} \ | |
75 | %{mcpu=602: -mppc} \ | |
76 | %{mcpu=603: -mppc} \ | |
77 | %{mcpu=603e: -mppc} \ | |
78 | %{mcpu=ec603e: -mppc} \ | |
79 | %{mcpu=604: -mppc} \ | |
80 | %{mcpu=604e: -mppc} \ | |
81 | %{mcpu=620: -mppc} \ | |
309323c2 | 82 | %{mcpu=630: -m604} \ |
f984d8df | 83 | %{mcpu=740: -mppc} \ |
fd3b43f2 | 84 | %{mcpu=7400: -mppc} \ |
f18c054f | 85 | %{mcpu=7450: -mppc} \ |
f984d8df DB |
86 | %{mcpu=750: -mppc} \ |
87 | %{mcpu=801: -mppc} \ | |
88 | %{mcpu=821: -mppc} \ | |
89 | %{mcpu=823: -mppc} \ | |
775db490 | 90 | %{mcpu=860: -mppc} \ |
a3170dc6 | 91 | %{mcpu=8540: -me500} \ |
775db490 | 92 | %{maltivec: -maltivec}" |
f984d8df DB |
93 | |
94 | #define CPP_DEFAULT_SPEC "" | |
95 | ||
96 | #define ASM_DEFAULT_SPEC "" | |
97 | ||
841faeed MM |
98 | /* This macro defines names of additional specifications to put in the specs |
99 | that can be used in various specifications like CC1_SPEC. Its definition | |
100 | is an initializer with a subgrouping for each command option. | |
101 | ||
102 | Each subgrouping contains a string constant, that defines the | |
103 | specification name, and a string constant that used by the GNU CC driver | |
104 | program. | |
105 | ||
106 | Do not define this macro if it does not need to do anything. */ | |
107 | ||
7509c759 | 108 | #define SUBTARGET_EXTRA_SPECS |
7509c759 | 109 | |
c81bebd7 | 110 | #define EXTRA_SPECS \ |
c81bebd7 | 111 | { "cpp_default", CPP_DEFAULT_SPEC }, \ |
c81bebd7 MM |
112 | { "asm_cpu", ASM_CPU_SPEC }, \ |
113 | { "asm_default", ASM_DEFAULT_SPEC }, \ | |
7509c759 MM |
114 | SUBTARGET_EXTRA_SPECS |
115 | ||
fb623df5 | 116 | /* Architecture type. */ |
f045b2c9 | 117 | |
fb623df5 RK |
118 | extern int target_flags; |
119 | ||
120 | /* Use POWER architecture instructions and MQ register. */ | |
38c1f2d7 | 121 | #define MASK_POWER 0x00000001 |
fb623df5 | 122 | |
6febd581 | 123 | /* Use POWER2 extensions to POWER architecture. */ |
38c1f2d7 | 124 | #define MASK_POWER2 0x00000002 |
6febd581 | 125 | |
fb623df5 | 126 | /* Use PowerPC architecture instructions. */ |
38c1f2d7 | 127 | #define MASK_POWERPC 0x00000004 |
6febd581 | 128 | |
583cf4db | 129 | /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */ |
38c1f2d7 | 130 | #define MASK_PPC_GPOPT 0x00000008 |
583cf4db RK |
131 | |
132 | /* Use PowerPC Graphics group optional instructions, e.g. fsel. */ | |
38c1f2d7 | 133 | #define MASK_PPC_GFXOPT 0x00000010 |
f045b2c9 | 134 | |
fb623df5 | 135 | /* Use PowerPC-64 architecture instructions. */ |
38c1f2d7 | 136 | #define MASK_POWERPC64 0x00000020 |
f045b2c9 | 137 | |
fb623df5 | 138 | /* Use revised mnemonic names defined for PowerPC architecture. */ |
38c1f2d7 | 139 | #define MASK_NEW_MNEMONICS 0x00000040 |
fb623df5 RK |
140 | |
141 | /* Disable placing fp constants in the TOC; can be turned on when the | |
142 | TOC overflows. */ | |
38c1f2d7 | 143 | #define MASK_NO_FP_IN_TOC 0x00000080 |
fb623df5 | 144 | |
0b9ccabc RK |
145 | /* Disable placing symbol+offset constants in the TOC; can be turned on when |
146 | the TOC overflows. */ | |
38c1f2d7 | 147 | #define MASK_NO_SUM_IN_TOC 0x00000100 |
0b9ccabc | 148 | |
fb623df5 | 149 | /* Output only one TOC entry per module. Normally linking fails if |
642a35f1 JW |
150 | there are more than 16K unique variables/constants in an executable. With |
151 | this option, linking fails only if there are more than 16K modules, or | |
152 | if there are more than 16K unique variables/constant in a single module. | |
153 | ||
154 | This is at the cost of having 2 extra loads and one extra store per | |
956d6950 | 155 | function, and one less allocable register. */ |
38c1f2d7 | 156 | #define MASK_MINIMAL_TOC 0x00000200 |
642a35f1 | 157 | |
b1765bde | 158 | /* Nonzero for the 64bit model: longs and pointers are 64 bits. */ |
38c1f2d7 | 159 | #define MASK_64BIT 0x00000400 |
9e654916 | 160 | |
f85f4585 | 161 | /* Disable use of FPRs. */ |
38c1f2d7 | 162 | #define MASK_SOFT_FLOAT 0x00000800 |
f85f4585 | 163 | |
88cad84b | 164 | /* Enable load/store multiple, even on PowerPC */ |
b21fb038 | 165 | #define MASK_MULTIPLE 0x00001000 |
4d30c363 | 166 | |
7e69e155 | 167 | /* Use string instructions for block moves */ |
b21fb038 | 168 | #define MASK_STRING 0x00002000 |
7e69e155 | 169 | |
38c1f2d7 | 170 | /* Disable update form of load/store */ |
b21fb038 | 171 | #define MASK_NO_UPDATE 0x00004000 |
38c1f2d7 MM |
172 | |
173 | /* Disable fused multiply/add operations */ | |
b21fb038 | 174 | #define MASK_NO_FUSED_MADD 0x00008000 |
4697a36c | 175 | |
9ebbca7d | 176 | /* Nonzero if we need to schedule the prolog and epilog. */ |
b21fb038 | 177 | #define MASK_SCHED_PROLOG 0x00010000 |
9ebbca7d | 178 | |
0ac081f6 | 179 | /* Use AltiVec instructions. */ |
b21fb038 | 180 | #define MASK_ALTIVEC 0x00020000 |
0ac081f6 | 181 | |
6fa3f289 | 182 | /* Return small structures in memory (as the AIX ABI requires). */ |
b21fb038 | 183 | #define MASK_AIX_STRUCT_RET 0x00040000 |
0ac081f6 | 184 | |
b21fb038 | 185 | /* The only remaining free bits are 0x00780000. sysv4.h uses |
6fa3f289 ZW |
186 | 0x00800000 -> 0x40000000, and 0x80000000 is not available |
187 | because target_flags is signed. */ | |
06f4e019 | 188 | |
7e69e155 MM |
189 | #define TARGET_POWER (target_flags & MASK_POWER) |
190 | #define TARGET_POWER2 (target_flags & MASK_POWER2) | |
191 | #define TARGET_POWERPC (target_flags & MASK_POWERPC) | |
192 | #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT) | |
193 | #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT) | |
7e69e155 MM |
194 | #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS) |
195 | #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC) | |
196 | #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC) | |
197 | #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC) | |
198 | #define TARGET_64BIT (target_flags & MASK_64BIT) | |
199 | #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT) | |
b21fb038 | 200 | #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE) |
7e69e155 | 201 | #define TARGET_STRING (target_flags & MASK_STRING) |
38c1f2d7 MM |
202 | #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE) |
203 | #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD) | |
9ebbca7d | 204 | #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG) |
0ac081f6 | 205 | #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC) |
6fa3f289 | 206 | #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET) |
7e69e155 | 207 | |
2f3e5814 | 208 | #define TARGET_32BIT (! TARGET_64BIT) |
7e69e155 | 209 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) |
38c1f2d7 MM |
210 | #define TARGET_UPDATE (! TARGET_NO_UPDATE) |
211 | #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD) | |
d14a6d05 | 212 | |
996ed075 JJ |
213 | #ifdef IN_LIBGCC2 |
214 | /* For libgcc2 we make sure this is a compile time constant */ | |
0134bf2d | 215 | #if defined (__64BIT__) || defined (__powerpc64__) |
996ed075 JJ |
216 | #define TARGET_POWERPC64 1 |
217 | #else | |
218 | #define TARGET_POWERPC64 0 | |
219 | #endif | |
b6c9286a | 220 | #else |
9ebbca7d | 221 | #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64) |
b6c9286a MM |
222 | #endif |
223 | ||
a3950905 | 224 | #define TARGET_XL_CALL 0 |
a3950905 | 225 | |
fb623df5 | 226 | /* Run-time compilation parameters selecting different hardware subsets. |
f045b2c9 | 227 | |
fb623df5 | 228 | Macro to define tables used to set the flags. |
f045b2c9 RS |
229 | This is a list in braces of pairs in braces, |
230 | each pair being { "NAME", VALUE } | |
231 | where VALUE is the bits to set or minus the bits to clear. | |
232 | An empty string NAME is used to identify the default VALUE. */ | |
233 | ||
938937d8 | 234 | #define TARGET_SWITCHES \ |
9ebbca7d | 235 | {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \ |
047142d3 | 236 | N_("Use POWER instruction set")}, \ |
938937d8 | 237 | {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \ |
9ebbca7d | 238 | | MASK_POWER2), \ |
047142d3 | 239 | N_("Use POWER2 instruction set")}, \ |
9ebbca7d | 240 | {"no-power2", - MASK_POWER2, \ |
047142d3 | 241 | N_("Do not use POWER2 instruction set")}, \ |
938937d8 | 242 | {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \ |
9ebbca7d | 243 | | MASK_STRING), \ |
047142d3 | 244 | N_("Do not use POWER instruction set")}, \ |
9ebbca7d | 245 | {"powerpc", MASK_POWERPC, \ |
047142d3 | 246 | N_("Use PowerPC instruction set")}, \ |
938937d8 | 247 | {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \ |
9ebbca7d | 248 | | MASK_PPC_GFXOPT | MASK_POWERPC64), \ |
047142d3 | 249 | N_("Do not use PowerPC instruction set")}, \ |
9ebbca7d | 250 | {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \ |
047142d3 | 251 | N_("Use PowerPC General Purpose group optional instructions")},\ |
9ebbca7d | 252 | {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \ |
047142d3 | 253 | N_("Don't use PowerPC General Purpose group optional instructions")},\ |
9ebbca7d | 254 | {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \ |
047142d3 | 255 | N_("Use PowerPC Graphics group optional instructions")},\ |
9ebbca7d | 256 | {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \ |
047142d3 | 257 | N_("Don't use PowerPC Graphics group optional instructions")},\ |
9ebbca7d | 258 | {"powerpc64", MASK_POWERPC64, \ |
047142d3 | 259 | N_("Use PowerPC-64 instruction set")}, \ |
9ebbca7d | 260 | {"no-powerpc64", - MASK_POWERPC64, \ |
047142d3 | 261 | N_("Don't use PowerPC-64 instruction set")}, \ |
f18c054f | 262 | {"altivec", MASK_ALTIVEC , \ |
c725bd79 | 263 | N_("Use AltiVec instructions")}, \ |
f18c054f | 264 | {"no-altivec", - MASK_ALTIVEC , \ |
c725bd79 | 265 | N_("Don't use AltiVec instructions")}, \ |
9ebbca7d | 266 | {"new-mnemonics", MASK_NEW_MNEMONICS, \ |
047142d3 | 267 | N_("Use new mnemonics for PowerPC architecture")},\ |
9ebbca7d | 268 | {"old-mnemonics", -MASK_NEW_MNEMONICS, \ |
047142d3 | 269 | N_("Use old mnemonics for PowerPC architecture")},\ |
938937d8 | 270 | {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \ |
9ebbca7d | 271 | | MASK_MINIMAL_TOC), \ |
047142d3 | 272 | N_("Put everything in the regular TOC")}, \ |
9ebbca7d | 273 | {"fp-in-toc", - MASK_NO_FP_IN_TOC, \ |
047142d3 | 274 | N_("Place floating point constants in TOC")}, \ |
9ebbca7d | 275 | {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \ |
047142d3 | 276 | N_("Don't place floating point constants in TOC")},\ |
9ebbca7d | 277 | {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \ |
047142d3 | 278 | N_("Place symbol+offset constants in TOC")}, \ |
9ebbca7d | 279 | {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \ |
047142d3 | 280 | N_("Don't place symbol+offset constants in TOC")},\ |
9ebbca7d GK |
281 | {"minimal-toc", MASK_MINIMAL_TOC, \ |
282 | "Use only one TOC entry per procedure"}, \ | |
283 | {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \ | |
047142d3 | 284 | ""}, \ |
9ebbca7d | 285 | {"no-minimal-toc", - MASK_MINIMAL_TOC, \ |
047142d3 | 286 | N_("Place variable addresses in the regular TOC")},\ |
9ebbca7d | 287 | {"hard-float", - MASK_SOFT_FLOAT, \ |
047142d3 | 288 | N_("Use hardware fp")}, \ |
9ebbca7d | 289 | {"soft-float", MASK_SOFT_FLOAT, \ |
047142d3 | 290 | N_("Do not use hardware fp")}, \ |
b21fb038 | 291 | {"multiple", MASK_MULTIPLE, \ |
047142d3 | 292 | N_("Generate load/store multiple instructions")}, \ |
9ebbca7d | 293 | {"no-multiple", - MASK_MULTIPLE, \ |
047142d3 | 294 | N_("Do not generate load/store multiple instructions")},\ |
b21fb038 | 295 | {"string", MASK_STRING, \ |
047142d3 | 296 | N_("Generate string instructions for block moves")},\ |
9ebbca7d | 297 | {"no-string", - MASK_STRING, \ |
047142d3 | 298 | N_("Do not generate string instructions for block moves")},\ |
9ebbca7d | 299 | {"update", - MASK_NO_UPDATE, \ |
047142d3 | 300 | N_("Generate load/store with update instructions")},\ |
9ebbca7d | 301 | {"no-update", MASK_NO_UPDATE, \ |
047142d3 | 302 | N_("Do not generate load/store with update instructions")},\ |
9ebbca7d | 303 | {"fused-madd", - MASK_NO_FUSED_MADD, \ |
047142d3 | 304 | N_("Generate fused multiply/add instructions")},\ |
9ebbca7d | 305 | {"no-fused-madd", MASK_NO_FUSED_MADD, \ |
047142d3 | 306 | N_("Don't generate fused multiply/add instructions")},\ |
9ebbca7d GK |
307 | {"sched-prolog", MASK_SCHED_PROLOG, \ |
308 | ""}, \ | |
309 | {"no-sched-prolog", -MASK_SCHED_PROLOG, \ | |
047142d3 | 310 | N_("Don't schedule the start and end of the procedure")},\ |
9ebbca7d GK |
311 | {"sched-epilog", MASK_SCHED_PROLOG, \ |
312 | ""}, \ | |
313 | {"no-sched-epilog", -MASK_SCHED_PROLOG, \ | |
314 | ""}, \ | |
b21fb038 | 315 | {"aix-struct-return", MASK_AIX_STRUCT_RET, \ |
6fa3f289 | 316 | N_("Return all structures in memory (AIX default)")},\ |
b21fb038 | 317 | {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \ |
6fa3f289 | 318 | N_("Return small structures in registers (SVR4 default)")},\ |
b21fb038 | 319 | {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \ |
6fa3f289 | 320 | ""},\ |
b21fb038 | 321 | {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \ |
6fa3f289 | 322 | ""},\ |
938937d8 | 323 | SUBTARGET_SWITCHES \ |
9ebbca7d GK |
324 | {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \ |
325 | ""}} | |
fb623df5 | 326 | |
938937d8 | 327 | #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING) |
9ebbca7d GK |
328 | |
329 | /* This is meant to be redefined in the host dependent files */ | |
330 | #define SUBTARGET_SWITCHES | |
fb623df5 | 331 | |
cac8ce95 | 332 | /* Processor type. Order must match cpu attribute in MD file. */ |
fb623df5 | 333 | enum processor_type |
bef84347 VM |
334 | { |
335 | PROCESSOR_RIOS1, | |
336 | PROCESSOR_RIOS2, | |
3cb999d8 | 337 | PROCESSOR_RS64A, |
bef84347 VM |
338 | PROCESSOR_MPCCORE, |
339 | PROCESSOR_PPC403, | |
fe7f5677 | 340 | PROCESSOR_PPC405, |
bef84347 VM |
341 | PROCESSOR_PPC601, |
342 | PROCESSOR_PPC603, | |
343 | PROCESSOR_PPC604, | |
344 | PROCESSOR_PPC604e, | |
345 | PROCESSOR_PPC620, | |
3cb999d8 | 346 | PROCESSOR_PPC630, |
ed947a96 DJ |
347 | PROCESSOR_PPC750, |
348 | PROCESSOR_PPC7400, | |
309323c2 | 349 | PROCESSOR_PPC7450, |
a3170dc6 | 350 | PROCESSOR_PPC8540, |
309323c2 | 351 | PROCESSOR_POWER4 |
bef84347 | 352 | }; |
fb623df5 RK |
353 | |
354 | extern enum processor_type rs6000_cpu; | |
355 | ||
356 | /* Recast the processor type to the cpu attribute. */ | |
357 | #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) | |
358 | ||
8482e358 | 359 | /* Define generic processor types based upon current deployment. */ |
3cb999d8 DE |
360 | #define PROCESSOR_COMMON PROCESSOR_PPC601 |
361 | #define PROCESSOR_POWER PROCESSOR_RIOS1 | |
362 | #define PROCESSOR_POWERPC PROCESSOR_PPC604 | |
363 | #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
6e151478 | 364 | |
fb623df5 | 365 | /* Define the default processor. This is overridden by other tm.h files. */ |
3cb999d8 DE |
366 | #define PROCESSOR_DEFAULT PROCESSOR_RIOS1 |
367 | #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A | |
fb623df5 | 368 | |
6febd581 RK |
369 | /* Specify the dialect of assembler to use. New mnemonics is dialect one |
370 | and the old mnemonics are dialect zero. */ | |
9ebbca7d | 371 | #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0) |
6febd581 | 372 | |
956d6950 | 373 | /* This is meant to be overridden in target specific files. */ |
b6c9286a | 374 | #define SUBTARGET_OPTIONS |
b6c9286a | 375 | |
9ebbca7d GK |
376 | #define TARGET_OPTIONS \ |
377 | { \ | |
047142d3 PT |
378 | {"cpu=", &rs6000_select[1].string, \ |
379 | N_("Use features of and schedule code for given CPU") }, \ | |
380 | {"tune=", &rs6000_select[2].string, \ | |
381 | N_("Schedule code for given CPU") }, \ | |
382 | {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \ | |
57ac7be9 AM |
383 | {"traceback=", &rs6000_traceback_name, \ |
384 | N_("Select full, part, or no traceback table") }, \ | |
0ac081f6 | 385 | {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \ |
6fa3f289 ZW |
386 | {"long-double-", &rs6000_long_double_size_string, \ |
387 | N_("Specify size of long double (64 or 128 bits)") }, \ | |
a3170dc6 AH |
388 | {"isel=", &rs6000_isel_string, \ |
389 | N_("Specify yes/no if isel instructions should be generated") }, \ | |
08b57fb3 AH |
390 | {"vrsave=", &rs6000_altivec_vrsave_string, \ |
391 | N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \ | |
a5c76ee6 ZW |
392 | {"longcall", &rs6000_longcall_switch, \ |
393 | N_("Avoid all range limits on call instructions") }, \ | |
394 | {"no-longcall", &rs6000_longcall_switch, "" }, \ | |
9ebbca7d | 395 | SUBTARGET_OPTIONS \ |
b6c9286a | 396 | } |
fb623df5 | 397 | |
ff222560 | 398 | /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */ |
8e3f41e7 MM |
399 | struct rs6000_cpu_select |
400 | { | |
815cdc52 MM |
401 | const char *string; |
402 | const char *name; | |
8e3f41e7 MM |
403 | int set_tune_p; |
404 | int set_arch_p; | |
405 | }; | |
406 | ||
407 | extern struct rs6000_cpu_select rs6000_select[]; | |
fb623df5 | 408 | |
38c1f2d7 | 409 | /* Debug support */ |
0ac081f6 | 410 | extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */ |
f607bc57 | 411 | extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */ |
38c1f2d7 MM |
412 | extern int rs6000_debug_stack; /* debug stack applications */ |
413 | extern int rs6000_debug_arg; /* debug argument handling */ | |
414 | ||
415 | #define TARGET_DEBUG_STACK rs6000_debug_stack | |
416 | #define TARGET_DEBUG_ARG rs6000_debug_arg | |
417 | ||
57ac7be9 AM |
418 | extern const char *rs6000_traceback_name; /* Type of traceback table. */ |
419 | ||
6fa3f289 ZW |
420 | /* These are separate from target_flags because we've run out of bits |
421 | there. */ | |
422 | extern const char *rs6000_long_double_size_string; | |
423 | extern int rs6000_long_double_type_size; | |
424 | extern int rs6000_altivec_abi; | |
a3170dc6 AH |
425 | extern int rs6000_spe_abi; |
426 | extern int rs6000_isel; | |
427 | extern int rs6000_fprs; | |
428 | extern const char *rs6000_isel_string; | |
08b57fb3 AH |
429 | extern const char *rs6000_altivec_vrsave_string; |
430 | extern int rs6000_altivec_vrsave; | |
a5c76ee6 ZW |
431 | extern const char *rs6000_longcall_switch; |
432 | extern int rs6000_default_long_calls; | |
6fa3f289 ZW |
433 | |
434 | #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) | |
435 | #define TARGET_ALTIVEC_ABI rs6000_altivec_abi | |
08b57fb3 | 436 | #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave |
6fa3f289 | 437 | |
a3170dc6 AH |
438 | #define TARGET_SPE_ABI 0 |
439 | #define TARGET_SPE 0 | |
440 | #define TARGET_ISEL 0 | |
441 | #define TARGET_FPRS 1 | |
442 | ||
fb623df5 RK |
443 | /* Sometimes certain combinations of command options do not make sense |
444 | on a particular target machine. You can define a macro | |
445 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
446 | defined, is executed once just after all the command options have | |
447 | been parsed. | |
448 | ||
5accd822 DE |
449 | Don't use this macro to turn on various extra optimizations for |
450 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. | |
451 | ||
fb623df5 RK |
452 | On the RS/6000 this is used to define the target cpu type. */ |
453 | ||
8e3f41e7 | 454 | #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT) |
f045b2c9 | 455 | |
5accd822 DE |
456 | /* Define this to change the optimizations performed by default. */ |
457 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE) | |
458 | ||
4c4eb375 GK |
459 | /* Show we can debug even without a frame pointer. */ |
460 | #define CAN_DEBUG_WITHOUT_FP | |
461 | ||
a5c76ee6 ZW |
462 | /* Target pragma. */ |
463 | #define REGISTER_TARGET_PRAGMAS(PFILE) do { \ | |
464 | cpp_register_pragma (PFILE, 0, "longcall", rs6000_pragma_longcall); \ | |
465 | } while (0) | |
466 | ||
4c4eb375 GK |
467 | /* Target #defines. */ |
468 | #define TARGET_CPU_CPP_BUILTINS() \ | |
469 | rs6000_cpu_cpp_builtins (pfile) | |
647d340d JT |
470 | |
471 | /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
472 | we're compiling for. Some configurations may need to override it. */ | |
473 | #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
474 | do \ | |
475 | { \ | |
476 | if (BYTES_BIG_ENDIAN) \ | |
477 | { \ | |
478 | builtin_define ("__BIG_ENDIAN__"); \ | |
479 | builtin_define ("_BIG_ENDIAN"); \ | |
480 | builtin_assert ("machine=bigendian"); \ | |
481 | } \ | |
482 | else \ | |
483 | { \ | |
484 | builtin_define ("__LITTLE_ENDIAN__"); \ | |
485 | builtin_define ("_LITTLE_ENDIAN"); \ | |
486 | builtin_assert ("machine=littleendian"); \ | |
487 | } \ | |
488 | } \ | |
489 | while (0) | |
f045b2c9 | 490 | \f |
4c4eb375 | 491 | /* Target machine storage layout. */ |
f045b2c9 | 492 | |
13d39dbc | 493 | /* Define this macro if it is advisable to hold scalars in registers |
c81bebd7 | 494 | in a wider mode than that declared by the program. In such cases, |
ef457bda RK |
495 | the value is constrained to be within the bounds of the declared |
496 | type, but kept valid in the wider mode. The signedness of the | |
497 | extension may differ from that of the type. */ | |
498 | ||
39403d82 DE |
499 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
500 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
501 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
3cb999d8 | 502 | (MODE) = word_mode; |
39403d82 DE |
503 | |
504 | /* Define this if function arguments should also be promoted using the above | |
505 | procedure. */ | |
506 | ||
507 | #define PROMOTE_FUNCTION_ARGS | |
508 | ||
509 | /* Likewise, if the function return value is promoted. */ | |
510 | ||
511 | #define PROMOTE_FUNCTION_RETURN | |
ef457bda | 512 | |
f045b2c9 | 513 | /* Define this if most significant bit is lowest numbered |
82e41834 KH |
514 | in instructions that operate on numbered bit-fields. */ |
515 | /* That is true on RS/6000. */ | |
f045b2c9 RS |
516 | #define BITS_BIG_ENDIAN 1 |
517 | ||
518 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
519 | /* That is true on RS/6000. */ | |
520 | #define BYTES_BIG_ENDIAN 1 | |
521 | ||
522 | /* Define this if most significant word of a multiword number is lowest | |
c81bebd7 | 523 | numbered. |
f045b2c9 RS |
524 | |
525 | For RS/6000 we can decide arbitrarily since there are no machine | |
82e41834 | 526 | instructions for them. Might as well be consistent with bits and bytes. */ |
f045b2c9 RS |
527 | #define WORDS_BIG_ENDIAN 1 |
528 | ||
2e360ab3 | 529 | #define MAX_BITS_PER_WORD 64 |
f045b2c9 RS |
530 | |
531 | /* Width of a word, in units (bytes). */ | |
2f3e5814 | 532 | #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) |
f34fc46e DE |
533 | #ifdef IN_LIBGCC2 |
534 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
535 | #else | |
ef0e53ce | 536 | #define MIN_UNITS_PER_WORD 4 |
f34fc46e | 537 | #endif |
2e360ab3 | 538 | #define UNITS_PER_FP_WORD 8 |
0ac081f6 | 539 | #define UNITS_PER_ALTIVEC_WORD 16 |
a3170dc6 | 540 | #define UNITS_PER_SPE_WORD 8 |
f045b2c9 | 541 | |
915f619f JW |
542 | /* Type used for ptrdiff_t, as a string used in a declaration. */ |
543 | #define PTRDIFF_TYPE "int" | |
544 | ||
058ef853 DE |
545 | /* Type used for size_t, as a string used in a declaration. */ |
546 | #define SIZE_TYPE "long unsigned int" | |
547 | ||
f045b2c9 RS |
548 | /* Type used for wchar_t, as a string used in a declaration. */ |
549 | #define WCHAR_TYPE "short unsigned int" | |
550 | ||
551 | /* Width of wchar_t in bits. */ | |
552 | #define WCHAR_TYPE_SIZE 16 | |
553 | ||
9e654916 RK |
554 | /* A C expression for the size in bits of the type `short' on the |
555 | target machine. If you don't define this, the default is half a | |
556 | word. (If this would be less than one storage unit, it is | |
557 | rounded up to one unit.) */ | |
558 | #define SHORT_TYPE_SIZE 16 | |
559 | ||
560 | /* A C expression for the size in bits of the type `int' on the | |
561 | target machine. If you don't define this, the default is one | |
562 | word. */ | |
19d2d16f | 563 | #define INT_TYPE_SIZE 32 |
9e654916 RK |
564 | |
565 | /* A C expression for the size in bits of the type `long' on the | |
566 | target machine. If you don't define this, the default is one | |
567 | word. */ | |
2f3e5814 | 568 | #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) |
9e654916 RK |
569 | #define MAX_LONG_TYPE_SIZE 64 |
570 | ||
571 | /* A C expression for the size in bits of the type `long long' on the | |
572 | target machine. If you don't define this, the default is two | |
573 | words. */ | |
574 | #define LONG_LONG_TYPE_SIZE 64 | |
575 | ||
9e654916 RK |
576 | /* A C expression for the size in bits of the type `float' on the |
577 | target machine. If you don't define this, the default is one | |
578 | word. */ | |
579 | #define FLOAT_TYPE_SIZE 32 | |
580 | ||
581 | /* A C expression for the size in bits of the type `double' on the | |
582 | target machine. If you don't define this, the default is two | |
583 | words. */ | |
584 | #define DOUBLE_TYPE_SIZE 64 | |
585 | ||
586 | /* A C expression for the size in bits of the type `long double' on | |
587 | the target machine. If you don't define this, the default is two | |
588 | words. */ | |
6fa3f289 | 589 | #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
06f4e019 DE |
590 | |
591 | /* Constant which presents upper bound of the above value. */ | |
592 | #define MAX_LONG_DOUBLE_TYPE_SIZE 128 | |
593 | ||
594 | /* Define this to set long double type size to use in libgcc2.c, which can | |
595 | not depend on target_flags. */ | |
596 | #ifdef __LONG_DOUBLE_128__ | |
597 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
598 | #else | |
599 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
600 | #endif | |
9e654916 | 601 | |
5b8f5865 DE |
602 | /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ |
603 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
604 | ||
f045b2c9 RS |
605 | /* Width in bits of a pointer. |
606 | See also the macro `Pmode' defined below. */ | |
2f3e5814 | 607 | #define POINTER_SIZE (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
608 | |
609 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
2f3e5814 | 610 | #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
611 | |
612 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
0ac081f6 | 613 | #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128) |
f045b2c9 RS |
614 | |
615 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
616 | #define FUNCTION_BOUNDARY 32 | |
617 | ||
618 | /* No data type wants to be aligned rounder than this. */ | |
0ac081f6 AH |
619 | #define BIGGEST_ALIGNMENT 128 |
620 | ||
621 | /* A C expression to compute the alignment for a variables in the | |
622 | local store. TYPE is the data type, and ALIGN is the alignment | |
623 | that the object would ordinarily have. */ | |
624 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
a3170dc6 AH |
625 | ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \ |
626 | (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN) | |
b73fd26c | 627 | |
f045b2c9 RS |
628 | /* Alignment of field after `int : 0' in a structure. */ |
629 | #define EMPTY_FIELD_BOUNDARY 32 | |
630 | ||
631 | /* Every structure's size must be a multiple of this. */ | |
632 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
633 | ||
a3170dc6 AH |
634 | /* Return 1 if a structure or array containing FIELD should be |
635 | accessed using `BLKMODE'. | |
636 | ||
637 | For the SPE, simd types are V2SI, and gcc can be tempted to put the | |
638 | entire thing in a DI and use subregs to access the internals. | |
639 | store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the | |
640 | back-end. Because a single GPR can hold a V2SI, but not a DI, the | |
641 | best thing to do is set structs to BLKmode and avoid Severe Tire | |
642 | Damage. */ | |
643 | #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ | |
644 | (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) | |
645 | ||
43a88a8c | 646 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
f045b2c9 RS |
647 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
648 | ||
69ef87e2 AH |
649 | /* Make strings word-aligned so strcpy from constants will be faster. |
650 | Make vector constants quadword aligned. */ | |
651 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
652 | (TREE_CODE (EXP) == STRING_CST \ | |
653 | && (ALIGN) < BITS_PER_WORD \ | |
654 | ? BITS_PER_WORD \ | |
655 | : (ALIGN)) | |
f045b2c9 | 656 | |
0ac081f6 AH |
657 | /* Make arrays of chars word-aligned for the same reasons. |
658 | Align vectors to 128 bits. */ | |
f045b2c9 | 659 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
a3170dc6 | 660 | (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \ |
0ac081f6 | 661 | : TREE_CODE (TYPE) == ARRAY_TYPE \ |
f045b2c9 RS |
662 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ |
663 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
664 | ||
a0ab749a | 665 | /* Nonzero if move instructions will actually fail to work |
f045b2c9 | 666 | when given unaligned data. */ |
fdaff8ba | 667 | #define STRICT_ALIGNMENT 0 |
e1565e65 DE |
668 | |
669 | /* Define this macro to be the value 1 if unaligned accesses have a cost | |
670 | many times greater than aligned accesses, for example if they are | |
671 | emulated in a trap handler. */ | |
41543739 GK |
672 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ |
673 | (STRICT_ALIGNMENT \ | |
fcce224d DE |
674 | || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ |
675 | || (MODE) == DImode) \ | |
41543739 | 676 | && (ALIGN) < 32)) |
f045b2c9 RS |
677 | \f |
678 | /* Standard register usage. */ | |
679 | ||
680 | /* Number of actual hardware registers. | |
681 | The hardware registers are assigned numbers for the compiler | |
682 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
683 | All registers that the compiler knows about must be given numbers, | |
684 | even those that are not normally considered general registers. | |
685 | ||
686 | RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
687 | an MQ register, a count register, a link register, and 8 condition | |
688 | register fields, which we view here as separate registers. | |
689 | ||
690 | In addition, the difference between the frame and argument pointers is | |
691 | a function of the number of registers saved, so we need to have a | |
692 | register for AP that will later be eliminated in favor of SP or FP. | |
802a0058 | 693 | This is a normal register, but it is fixed. |
f045b2c9 | 694 | |
802a0058 MM |
695 | We also create a pseudo register for float/int conversions, that will |
696 | really represent the memory location used. It is represented here as | |
697 | a register, in order to work around problems in allocating stack storage | |
698 | in inline functions. */ | |
699 | ||
a3170dc6 | 700 | #define FIRST_PSEUDO_REGISTER 113 |
f045b2c9 | 701 | |
d6a7951f | 702 | /* This must be included for pre gcc 3.0 glibc compatibility. */ |
7d5f33bc | 703 | #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 |
62153b61 | 704 | |
f045b2c9 RS |
705 | /* 1 for registers that have pervasive standard uses |
706 | and are not available for the register allocator. | |
707 | ||
5dead3e5 DJ |
708 | On RS/6000, r1 is used for the stack. On Darwin, r2 is available |
709 | as a local register; for all other OS's r2 is the TOC pointer. | |
f045b2c9 | 710 | |
a127c4e5 RK |
711 | cr5 is not supposed to be used. |
712 | ||
713 | On System V implementations, r13 is fixed and not available for use. */ | |
714 | ||
f045b2c9 | 715 | #define FIXED_REGISTERS \ |
5dead3e5 | 716 | {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
717 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
718 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
719 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
720 | 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ |
721 | /* AltiVec registers. */ \ | |
722 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
723 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 724 | 1, 1 \ |
a3170dc6 | 725 | , 1, 1 \ |
0ac081f6 | 726 | } |
f045b2c9 RS |
727 | |
728 | /* 1 for registers not available across function calls. | |
729 | These must include the FIXED_REGISTERS and also any | |
730 | registers that can be used without being saved. | |
731 | The latter must include the registers where values are returned | |
732 | and the register where structure-value addresses are passed. | |
733 | Aside from that, you can include as many other registers as you like. */ | |
734 | ||
735 | #define CALL_USED_REGISTERS \ | |
a127c4e5 | 736 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
737 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
738 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
739 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
740 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
741 | /* AltiVec registers. */ \ | |
742 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
743 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 744 | 1, 1 \ |
a3170dc6 | 745 | , 1, 1 \ |
0ac081f6 AH |
746 | } |
747 | ||
289e96b2 AH |
748 | /* Like `CALL_USED_REGISTERS' except this macro doesn't require that |
749 | the entire set of `FIXED_REGISTERS' be included. | |
750 | (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
751 | This macro is optional. If not specified, it defaults to the value | |
752 | of `CALL_USED_REGISTERS'. */ | |
753 | ||
754 | #define CALL_REALLY_USED_REGISTERS \ | |
755 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
756 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
757 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
758 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
759 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ | |
760 | /* AltiVec registers. */ \ | |
761 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
762 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 763 | 0, 0 \ |
a3170dc6 | 764 | , 0, 0 \ |
289e96b2 | 765 | } |
f045b2c9 | 766 | |
9ebbca7d GK |
767 | #define MQ_REGNO 64 |
768 | #define CR0_REGNO 68 | |
769 | #define CR1_REGNO 69 | |
770 | #define CR2_REGNO 70 | |
771 | #define CR3_REGNO 71 | |
772 | #define CR4_REGNO 72 | |
773 | #define MAX_CR_REGNO 75 | |
774 | #define XER_REGNO 76 | |
0ac081f6 AH |
775 | #define FIRST_ALTIVEC_REGNO 77 |
776 | #define LAST_ALTIVEC_REGNO 108 | |
28bcfd4d | 777 | #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) |
0ac081f6 | 778 | #define VRSAVE_REGNO 109 |
5f004351 | 779 | #define VSCR_REGNO 110 |
a3170dc6 AH |
780 | #define SPE_ACC_REGNO 111 |
781 | #define SPEFSCR_REGNO 112 | |
9ebbca7d | 782 | |
f045b2c9 RS |
783 | /* List the order in which to allocate registers. Each register must be |
784 | listed once, even those in FIXED_REGISTERS. | |
785 | ||
786 | We allocate in the following order: | |
787 | fp0 (not saved or used for anything) | |
788 | fp13 - fp2 (not saved; incoming fp arg registers) | |
789 | fp1 (not saved; return value) | |
790 | fp31 - fp14 (saved; order given to save least number) | |
5accd822 DE |
791 | cr7, cr6 (not saved or special) |
792 | cr1 (not saved, but used for FP operations) | |
f045b2c9 | 793 | cr0 (not saved, but used for arithmetic operations) |
5accd822 | 794 | cr4, cr3, cr2 (saved) |
f045b2c9 RS |
795 | r0 (not saved; cannot be base reg) |
796 | r9 (not saved; best for TImode) | |
797 | r11, r10, r8-r4 (not saved; highest used first to make less conflict) | |
798 | r3 (not saved; return value register) | |
799 | r31 - r13 (saved; order given to save least number) | |
800 | r12 (not saved; if used for DImode or DFmode would use r13) | |
801 | mq (not saved; best to use it if we can) | |
802 | ctr (not saved; when we have the choice ctr is better) | |
803 | lr (saved) | |
5f004351 | 804 | cr5, r1, r2, ap, xer, vrsave, vscr (fixed) |
a3170dc6 | 805 | spe_acc, spefscr (fixed) |
0ac081f6 AH |
806 | |
807 | AltiVec registers: | |
808 | v0 - v1 (not saved or used for anything) | |
809 | v13 - v3 (not saved; incoming vector arg registers) | |
810 | v2 (not saved; incoming vector arg reg; return value) | |
811 | v19 - v14 (not saved or used for anything) | |
812 | v31 - v20 (saved; order given to save least number) | |
813 | */ | |
814 | ||
f045b2c9 RS |
815 | |
816 | #define REG_ALLOC_ORDER \ | |
817 | {32, \ | |
818 | 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ | |
819 | 33, \ | |
820 | 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
821 | 50, 49, 48, 47, 46, \ | |
5accd822 | 822 | 75, 74, 69, 68, 72, 71, 70, \ |
f045b2c9 RS |
823 | 0, \ |
824 | 9, 11, 10, 8, 7, 6, 5, 4, \ | |
825 | 3, \ | |
826 | 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ | |
827 | 18, 17, 16, 15, 14, 13, 12, \ | |
828 | 64, 66, 65, \ | |
0ac081f6 AH |
829 | 73, 1, 2, 67, 76, \ |
830 | /* AltiVec registers. */ \ | |
831 | 77, 78, \ | |
832 | 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
833 | 79, \ | |
834 | 96, 95, 94, 93, 92, 91, \ | |
58568475 | 835 | 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \ |
5f004351 | 836 | 97, 109, 110 \ |
a3170dc6 | 837 | , 111, 112 \ |
0ac081f6 | 838 | } |
f045b2c9 RS |
839 | |
840 | /* True if register is floating-point. */ | |
841 | #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
842 | ||
843 | /* True if register is a condition register. */ | |
844 | #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75) | |
845 | ||
815cdc52 MM |
846 | /* True if register is a condition register, but not cr0. */ |
847 | #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75) | |
848 | ||
f045b2c9 | 849 | /* True if register is an integer register. */ |
9ebbca7d | 850 | #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM) |
f045b2c9 | 851 | |
a3170dc6 AH |
852 | /* SPE SIMD registers are just the GPRs. */ |
853 | #define SPE_SIMD_REGNO_P(N) ((N) <= 31) | |
854 | ||
0d86f538 | 855 | /* True if register is the XER register. */ |
9ebbca7d | 856 | #define XER_REGNO_P(N) ((N) == XER_REGNO) |
802a0058 | 857 | |
0ac081f6 AH |
858 | /* True if register is an AltiVec register. */ |
859 | #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
860 | ||
f045b2c9 RS |
861 | /* Return number of consecutive hard regs needed starting at reg REGNO |
862 | to hold something of mode MODE. | |
863 | This is ordinarily the length in words of a value of mode MODE | |
864 | but can be less for certain modes in special long registers. | |
865 | ||
a3170dc6 AH |
866 | For the SPE, GPRs are 64 bits but only 32 bits are visible in |
867 | scalar instructions. The upper 32 bits are only available to the | |
868 | SIMD instructions. | |
869 | ||
a260abc9 DE |
870 | POWER and PowerPC GPRs hold 32 bits worth; |
871 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
f045b2c9 | 872 | |
802a0058 | 873 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
9ebbca7d | 874 | (FP_REGNO_P (REGNO) \ |
2e360ab3 | 875 | ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ |
a3170dc6 AH |
876 | : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ |
877 | ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \ | |
0ac081f6 AH |
878 | : ALTIVEC_REGNO_P (REGNO) \ |
879 | ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \ | |
f045b2c9 RS |
880 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
881 | ||
0ac081f6 | 882 | #define ALTIVEC_VECTOR_MODE(MODE) \ |
cb2a532e AH |
883 | ((MODE) == V16QImode \ |
884 | || (MODE) == V8HImode \ | |
885 | || (MODE) == V4SFmode \ | |
6e1f54e2 | 886 | || (MODE) == V4SImode) |
0ac081f6 | 887 | |
a3170dc6 AH |
888 | #define SPE_VECTOR_MODE(MODE) \ |
889 | ((MODE) == V4HImode \ | |
890 | || (MODE) == V2SFmode \ | |
00a892b8 | 891 | || (MODE) == V1DImode \ |
a3170dc6 AH |
892 | || (MODE) == V2SImode) |
893 | ||
0ac081f6 AH |
894 | /* Define this macro to be nonzero if the port is prepared to handle |
895 | insns involving vector mode MODE. At the very least, it must have | |
896 | move patterns for this mode. */ | |
897 | ||
a3170dc6 AH |
898 | #define VECTOR_MODE_SUPPORTED_P(MODE) \ |
899 | ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ | |
900 | || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))) | |
0ac081f6 | 901 | |
f045b2c9 | 902 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. |
bdfd4e31 RK |
903 | For POWER and PowerPC, the GPRs can hold any mode, but the float |
904 | registers only can hold floating modes and DImode, and CR register only | |
905 | can hold CC modes. We cannot put TImode anywhere except general | |
82e41834 | 906 | register and it must be able to fit within the register set. */ |
f045b2c9 | 907 | |
802a0058 MM |
908 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
909 | (FP_REGNO_P (REGNO) ? \ | |
910 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
911 | || (GET_MODE_CLASS (MODE) == MODE_INT \ | |
912 | && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \ | |
0ac081f6 | 913 | : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \ |
a3170dc6 | 914 | : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \ |
802a0058 | 915 | : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \ |
9ebbca7d | 916 | : XER_REGNO_P (REGNO) ? (MODE) == PSImode \ |
b991a865 | 917 | : ! INT_REGNO_P (REGNO) ? GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \ |
f045b2c9 RS |
918 | : 1) |
919 | ||
920 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
921 | when one has mode MODE1 and one has mode MODE2. | |
922 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
923 | for any hard reg, then this must be 0 for correct output. */ | |
924 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
925 | (GET_MODE_CLASS (MODE1) == MODE_FLOAT \ | |
926 | ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
927 | : GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
928 | ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \ | |
929 | : GET_MODE_CLASS (MODE1) == MODE_CC \ | |
930 | ? GET_MODE_CLASS (MODE2) == MODE_CC \ | |
931 | : GET_MODE_CLASS (MODE2) == MODE_CC \ | |
932 | ? GET_MODE_CLASS (MODE1) == MODE_CC \ | |
0ac081f6 AH |
933 | : ALTIVEC_VECTOR_MODE (MODE1) \ |
934 | ? ALTIVEC_VECTOR_MODE (MODE2) \ | |
935 | : ALTIVEC_VECTOR_MODE (MODE2) \ | |
936 | ? ALTIVEC_VECTOR_MODE (MODE1) \ | |
f045b2c9 RS |
937 | : 1) |
938 | ||
939 | /* A C expression returning the cost of moving data from a register of class | |
34bb030a | 940 | CLASS1 to one of CLASS2. */ |
f045b2c9 | 941 | |
34bb030a | 942 | #define REGISTER_MOVE_COST rs6000_register_move_cost |
f045b2c9 | 943 | |
34bb030a DE |
944 | /* A C expressions returning the cost of moving data of MODE from a register to |
945 | or from memory. */ | |
f045b2c9 | 946 | |
34bb030a | 947 | #define MEMORY_MOVE_COST rs6000_memory_move_cost |
f045b2c9 RS |
948 | |
949 | /* Specify the cost of a branch insn; roughly the number of extra insns that | |
950 | should be added to avoid a branch. | |
951 | ||
ef457bda | 952 | Set this to 3 on the RS/6000 since that is roughly the average cost of an |
f045b2c9 RS |
953 | unscheduled conditional branch. */ |
954 | ||
ef457bda | 955 | #define BRANCH_COST 3 |
f045b2c9 | 956 | |
a3170dc6 AH |
957 | |
958 | /* A fixed register used at prologue and epilogue generation to fix | |
959 | addressing modes. The SPE needs heavy addressing fixes at the last | |
960 | minute, and it's best to save a register for it. | |
961 | ||
962 | AltiVec also needs fixes, but we've gotten around using r11, which | |
963 | is actually wrong because when use_backchain_to_restore_sp is true, | |
964 | we end up clobbering r11. | |
965 | ||
966 | The AltiVec case needs to be fixed. Dunno if we should break ABI | |
967 | compatability and reserve a register for it as well.. */ | |
968 | ||
969 | #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11) | |
970 | ||
6febd581 RK |
971 | /* Define this macro to change register usage conditional on target flags. |
972 | Set MQ register fixed (already call_used) if not POWER architecture | |
f85f4585 | 973 | (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated. |
a238cd8b | 974 | 64-bit AIX reserves GPR13 for thread-private data. |
f85f4585 RK |
975 | Conditionally disable FPRs. */ |
976 | ||
8d30c4ee FS |
977 | #define CONDITIONAL_REGISTER_USAGE \ |
978 | { \ | |
e9e4208a | 979 | int i; \ |
8d30c4ee FS |
980 | if (! TARGET_POWER) \ |
981 | fixed_regs[64] = 1; \ | |
982 | if (TARGET_64BIT) \ | |
289e96b2 AH |
983 | fixed_regs[13] = call_used_regs[13] \ |
984 | = call_really_used_regs[13] = 1; \ | |
a3170dc6 | 985 | if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \ |
8d30c4ee | 986 | for (i = 32; i < 64; i++) \ |
289e96b2 AH |
987 | fixed_regs[i] = call_used_regs[i] \ |
988 | = call_really_used_regs[i] = 1; \ | |
1db02437 FS |
989 | if (DEFAULT_ABI == ABI_V4 \ |
990 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \ | |
991 | && flag_pic == 1) \ | |
992 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ | |
993 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ | |
994 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
995 | if (DEFAULT_ABI == ABI_DARWIN \ | |
996 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ | |
997 | global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ | |
998 | = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ | |
999 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ | |
1000 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
5f004351 AH |
1001 | if (TARGET_ALTIVEC) \ |
1002 | global_regs[VSCR_REGNO] = 1; \ | |
a3170dc6 AH |
1003 | if (TARGET_SPE) \ |
1004 | { \ | |
1005 | global_regs[SPEFSCR_REGNO] = 1; \ | |
1006 | fixed_regs[FIXED_SCRATCH] \ | |
1007 | = call_used_regs[FIXED_SCRATCH] \ | |
1008 | = call_really_used_regs[FIXED_SCRATCH] = 1; \ | |
1009 | } \ | |
2473ee11 | 1010 | if (! TARGET_ALTIVEC) \ |
c1f11548 DE |
1011 | { \ |
1012 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \ | |
1013 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \ | |
1014 | call_really_used_regs[VRSAVE_REGNO] = 1; \ | |
1015 | } \ | |
0ac081f6 | 1016 | if (TARGET_ALTIVEC_ABI) \ |
2473ee11 | 1017 | for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \ |
289e96b2 | 1018 | call_used_regs[i] = call_really_used_regs[i] = 1; \ |
f85f4585 | 1019 | } |
6febd581 | 1020 | |
f045b2c9 RS |
1021 | /* Specify the registers used for certain standard purposes. |
1022 | The values of these macros are register numbers. */ | |
1023 | ||
1024 | /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
1025 | /* #define PC_REGNUM */ | |
1026 | ||
1027 | /* Register to use for pushing function arguments. */ | |
1028 | #define STACK_POINTER_REGNUM 1 | |
1029 | ||
1030 | /* Base register for access to local variables of the function. */ | |
1031 | #define FRAME_POINTER_REGNUM 31 | |
1032 | ||
1033 | /* Value should be nonzero if functions must have frame pointers. | |
1034 | Zero means the frame pointer need not be set up (and parms | |
1035 | may be accessed via the stack pointer) in functions that seem suitable. | |
1036 | This is computed in `reload', in reload1.c. */ | |
1037 | #define FRAME_POINTER_REQUIRED 0 | |
1038 | ||
1039 | /* Base register for access to arguments of the function. */ | |
1040 | #define ARG_POINTER_REGNUM 67 | |
1041 | ||
1042 | /* Place to put static chain when calling a function that requires it. */ | |
1043 | #define STATIC_CHAIN_REGNUM 11 | |
1044 | ||
82e41834 | 1045 | /* Link register number. */ |
9ebbca7d | 1046 | #define LINK_REGISTER_REGNUM 65 |
b6c9286a | 1047 | |
82e41834 | 1048 | /* Count register number. */ |
9ebbca7d | 1049 | #define COUNT_REGISTER_REGNUM 66 |
802a0058 | 1050 | |
f045b2c9 RS |
1051 | /* Place that structure value return address is placed. |
1052 | ||
1053 | On the RS/6000, it is passed as an extra parameter. */ | |
1ff7789b | 1054 | #define STRUCT_VALUE 0 |
f045b2c9 RS |
1055 | \f |
1056 | /* Define the classes of registers for register constraints in the | |
1057 | machine description. Also define ranges of constants. | |
1058 | ||
1059 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1060 | If there is more than one class, another class must be named NO_REGS | |
1061 | and contain no registers. | |
1062 | ||
1063 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1064 | another name such as ALL_REGS). This is the class of registers | |
1065 | that is allowed by "g" or "r" in a register constraint. | |
1066 | Also, registers outside this class are allocated only when | |
1067 | instructions express preferences for them. | |
1068 | ||
1069 | The classes must be numbered in nondecreasing order; that is, | |
1070 | a larger-numbered class must never be contained completely | |
1071 | in a smaller-numbered class. | |
1072 | ||
1073 | For any two classes, it is very desirable that there be another | |
1074 | class that represents their union. */ | |
c81bebd7 | 1075 | |
f045b2c9 RS |
1076 | /* The RS/6000 has three types of registers, fixed-point, floating-point, |
1077 | and condition registers, plus three special registers, MQ, CTR, and the | |
1078 | link register. | |
1079 | ||
1080 | However, r0 is special in that it cannot be used as a base register. | |
1081 | So make a class for registers valid as base registers. | |
1082 | ||
1083 | Also, cr0 is the only condition code register that can be used in | |
0d86f538 | 1084 | arithmetic insns, so make a separate class for it. */ |
f045b2c9 | 1085 | |
ebedb4dd MM |
1086 | enum reg_class |
1087 | { | |
1088 | NO_REGS, | |
ebedb4dd MM |
1089 | BASE_REGS, |
1090 | GENERAL_REGS, | |
1091 | FLOAT_REGS, | |
0ac081f6 AH |
1092 | ALTIVEC_REGS, |
1093 | VRSAVE_REGS, | |
5f004351 | 1094 | VSCR_REGS, |
a3170dc6 AH |
1095 | SPE_ACC_REGS, |
1096 | SPEFSCR_REGS, | |
ebedb4dd MM |
1097 | NON_SPECIAL_REGS, |
1098 | MQ_REGS, | |
1099 | LINK_REGS, | |
1100 | CTR_REGS, | |
1101 | LINK_OR_CTR_REGS, | |
1102 | SPECIAL_REGS, | |
1103 | SPEC_OR_GEN_REGS, | |
1104 | CR0_REGS, | |
ebedb4dd MM |
1105 | CR_REGS, |
1106 | NON_FLOAT_REGS, | |
9ebbca7d | 1107 | XER_REGS, |
ebedb4dd MM |
1108 | ALL_REGS, |
1109 | LIM_REG_CLASSES | |
1110 | }; | |
f045b2c9 RS |
1111 | |
1112 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1113 | ||
82e41834 | 1114 | /* Give names of register classes as strings for dump file. */ |
f045b2c9 | 1115 | |
ebedb4dd MM |
1116 | #define REG_CLASS_NAMES \ |
1117 | { \ | |
1118 | "NO_REGS", \ | |
ebedb4dd MM |
1119 | "BASE_REGS", \ |
1120 | "GENERAL_REGS", \ | |
1121 | "FLOAT_REGS", \ | |
0ac081f6 AH |
1122 | "ALTIVEC_REGS", \ |
1123 | "VRSAVE_REGS", \ | |
5f004351 | 1124 | "VSCR_REGS", \ |
a3170dc6 AH |
1125 | "SPE_ACC_REGS", \ |
1126 | "SPEFSCR_REGS", \ | |
ebedb4dd MM |
1127 | "NON_SPECIAL_REGS", \ |
1128 | "MQ_REGS", \ | |
1129 | "LINK_REGS", \ | |
1130 | "CTR_REGS", \ | |
1131 | "LINK_OR_CTR_REGS", \ | |
1132 | "SPECIAL_REGS", \ | |
1133 | "SPEC_OR_GEN_REGS", \ | |
1134 | "CR0_REGS", \ | |
ebedb4dd MM |
1135 | "CR_REGS", \ |
1136 | "NON_FLOAT_REGS", \ | |
9ebbca7d | 1137 | "XER_REGS", \ |
ebedb4dd MM |
1138 | "ALL_REGS" \ |
1139 | } | |
f045b2c9 RS |
1140 | |
1141 | /* Define which registers fit in which classes. | |
1142 | This is an initializer for a vector of HARD_REG_SET | |
1143 | of length N_REG_CLASSES. */ | |
1144 | ||
0ac081f6 AH |
1145 | #define REG_CLASS_CONTENTS \ |
1146 | { \ | |
1147 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
1148 | { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \ | |
1149 | { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \ | |
1150 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ | |
089a05b8 SS |
1151 | { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ |
1152 | { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ | |
5f004351 | 1153 | { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ |
a3170dc6 AH |
1154 | { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ |
1155 | { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ | |
0ac081f6 AH |
1156 | { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \ |
1157 | { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \ | |
1158 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ | |
1159 | { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ | |
1160 | { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ | |
a004eb82 | 1161 | { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \ |
0ac081f6 AH |
1162 | { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \ |
1163 | { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ | |
1164 | { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ | |
089a05b8 SS |
1165 | { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \ |
1166 | { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \ | |
1167 | { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \ | |
ebedb4dd | 1168 | } |
f045b2c9 RS |
1169 | |
1170 | /* The same information, inverted: | |
1171 | Return the class number of the smallest class containing | |
1172 | reg number REGNO. This could be a conditional expression | |
1173 | or could index an array. */ | |
1174 | ||
0d86f538 GK |
1175 | #define REGNO_REG_CLASS(REGNO) \ |
1176 | ((REGNO) == 0 ? GENERAL_REGS \ | |
1177 | : (REGNO) < 32 ? BASE_REGS \ | |
1178 | : FP_REGNO_P (REGNO) ? FLOAT_REGS \ | |
0ac081f6 | 1179 | : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \ |
0d86f538 GK |
1180 | : (REGNO) == CR0_REGNO ? CR0_REGS \ |
1181 | : CR_REGNO_P (REGNO) ? CR_REGS \ | |
1182 | : (REGNO) == MQ_REGNO ? MQ_REGS \ | |
1183 | : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \ | |
1184 | : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \ | |
1185 | : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \ | |
1186 | : (REGNO) == XER_REGNO ? XER_REGS \ | |
0ac081f6 | 1187 | : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \ |
5f004351 | 1188 | : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \ |
a3170dc6 AH |
1189 | : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \ |
1190 | : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \ | |
f045b2c9 RS |
1191 | : NO_REGS) |
1192 | ||
1193 | /* The class value for index registers, and the one for base regs. */ | |
1194 | #define INDEX_REG_CLASS GENERAL_REGS | |
1195 | #define BASE_REG_CLASS BASE_REGS | |
1196 | ||
1197 | /* Get reg_class from a letter such as appears in the machine description. */ | |
1198 | ||
1199 | #define REG_CLASS_FROM_LETTER(C) \ | |
1200 | ((C) == 'f' ? FLOAT_REGS \ | |
1201 | : (C) == 'b' ? BASE_REGS \ | |
1202 | : (C) == 'h' ? SPECIAL_REGS \ | |
1203 | : (C) == 'q' ? MQ_REGS \ | |
1204 | : (C) == 'c' ? CTR_REGS \ | |
1205 | : (C) == 'l' ? LINK_REGS \ | |
0ac081f6 | 1206 | : (C) == 'v' ? ALTIVEC_REGS \ |
f045b2c9 RS |
1207 | : (C) == 'x' ? CR0_REGS \ |
1208 | : (C) == 'y' ? CR_REGS \ | |
9ebbca7d | 1209 | : (C) == 'z' ? XER_REGS \ |
f045b2c9 RS |
1210 | : NO_REGS) |
1211 | ||
1212 | /* The letters I, J, K, L, M, N, and P in a register constraint string | |
1213 | can be used to stand for particular ranges of immediate operands. | |
1214 | This macro defines what the ranges are. | |
1215 | C is the letter, and VALUE is a constant value. | |
1216 | Return 1 if VALUE is in the range specified by C. | |
1217 | ||
9615f239 | 1218 | `I' is a signed 16-bit constant |
a0ab749a KH |
1219 | `J' is a constant with only the high-order 16 bits nonzero |
1220 | `K' is a constant with only the low-order 16 bits nonzero | |
9615f239 | 1221 | `L' is a signed 16-bit constant shifted left 16 bits |
f045b2c9 | 1222 | `M' is a constant that is greater than 31 |
2bfcf297 | 1223 | `N' is a positive constant that is an exact power of two |
f045b2c9 RS |
1224 | `O' is the constant zero |
1225 | `P' is a constant whose negation is a signed 16-bit constant */ | |
1226 | ||
5b6f7b96 RK |
1227 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
1228 | ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \ | |
0858c623 | 1229 | : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \ |
a260abc9 | 1230 | : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \ |
9615f239 DE |
1231 | : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \ |
1232 | && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \ | |
5b6f7b96 | 1233 | : (C) == 'M' ? (VALUE) > 31 \ |
2bfcf297 | 1234 | : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \ |
5b6f7b96 | 1235 | : (C) == 'O' ? (VALUE) == 0 \ |
9615f239 | 1236 | : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \ |
f045b2c9 RS |
1237 | : 0) |
1238 | ||
1239 | /* Similar, but for floating constants, and defining letters G and H. | |
1240 | Here VALUE is the CONST_DOUBLE rtx itself. | |
1241 | ||
1242 | We flag for special constants when we can copy the constant into | |
4e74d8ec | 1243 | a general register in two insns for DF/DI and one insn for SF. |
f045b2c9 | 1244 | |
c4c40373 | 1245 | 'H' is used for DI/DF constants that take 3 insns. */ |
4e74d8ec MM |
1246 | |
1247 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
c4c40373 MM |
1248 | ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \ |
1249 | == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \ | |
1250 | : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \ | |
1251 | : 0) | |
f045b2c9 RS |
1252 | |
1253 | /* Optional extra constraints for this machine. | |
1254 | ||
b6c9286a MM |
1255 | 'Q' means that is a memory operand that is just an offset from a reg. |
1256 | 'R' is for AIX TOC entries. | |
a260abc9 | 1257 | 'S' is a constant that can be placed into a 64-bit mask operand |
b1765bde | 1258 | 'T' is a constant that can be placed into a 32-bit mask operand |
0ba1b2ff AM |
1259 | 'U' is for V.4 small data references. |
1260 | 't' is for AND masks that can be performed by two rldic{l,r} insns. */ | |
f045b2c9 | 1261 | |
e8a8bc24 RK |
1262 | #define EXTRA_CONSTRAINT(OP, C) \ |
1263 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ | |
d537c24d | 1264 | : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \ |
b1765bde DE |
1265 | : (C) == 'S' ? mask64_operand (OP, DImode) \ |
1266 | : (C) == 'T' ? mask_operand (OP, SImode) \ | |
f607bc57 | 1267 | : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \ |
c81bebd7 | 1268 | && small_data_operand (OP, GET_MODE (OP))) \ |
0ba1b2ff AM |
1269 | : (C) == 't' ? (mask64_2_operand (OP, DImode) \ |
1270 | && (fixed_regs[CR0_REGNO] \ | |
1271 | || !logical_operand (OP, DImode)) \ | |
1272 | && !mask64_operand (OP, DImode)) \ | |
e8a8bc24 | 1273 | : 0) |
f045b2c9 RS |
1274 | |
1275 | /* Given an rtx X being reloaded into a reg required to be | |
1276 | in class CLASS, return the class of reg to actually use. | |
1277 | In general this is just CLASS; but on some machines | |
c81bebd7 | 1278 | in some cases it is preferable to use a more restrictive class. |
f045b2c9 RS |
1279 | |
1280 | On the RS/6000, we have to return NO_REGS when we want to reload a | |
1e66d555 GK |
1281 | floating-point CONST_DOUBLE to force it to be copied to memory. |
1282 | ||
1283 | We also don't want to reload integer values into floating-point | |
1284 | registers if we can at all help it. In fact, this can | |
1285 | cause reload to abort, if it tries to generate a reload of CTR | |
1286 | into a FP register and discovers it doesn't have the memory location | |
1287 | required. | |
1288 | ||
1289 | ??? Would it be a good idea to have reload do the converse, that is | |
1290 | try to reload floating modes into FP registers if possible? | |
1291 | */ | |
f045b2c9 | 1292 | |
802a0058 | 1293 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
1e66d555 GK |
1294 | (((GET_CODE (X) == CONST_DOUBLE \ |
1295 | && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ | |
1296 | ? NO_REGS \ | |
1297 | : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ | |
1298 | && (CLASS) == NON_SPECIAL_REGS) \ | |
1299 | ? GENERAL_REGS \ | |
1300 | : (CLASS))) | |
c81bebd7 | 1301 | |
f045b2c9 RS |
1302 | /* Return the register class of a scratch register needed to copy IN into |
1303 | or out of a register in CLASS in MODE. If it can be done directly, | |
1304 | NO_REGS is returned. */ | |
1305 | ||
1306 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
1307 | secondary_reload_class (CLASS, MODE, IN) | |
1308 | ||
0ac081f6 AH |
1309 | /* If we are copying between FP or AltiVec registers and anything |
1310 | else, we need a memory location. */ | |
7ea555a4 | 1311 | |
0ac081f6 AH |
1312 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ |
1313 | ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \ | |
1314 | || (CLASS2) == FLOAT_REGS \ | |
1315 | || (CLASS1) == ALTIVEC_REGS \ | |
1316 | || (CLASS2) == ALTIVEC_REGS)) | |
7ea555a4 | 1317 | |
f045b2c9 RS |
1318 | /* Return the maximum number of consecutive registers |
1319 | needed to represent mode MODE in a register of class CLASS. | |
1320 | ||
1321 | On RS/6000, this is the size of MODE in words, | |
1322 | except in the FP regs, where a single reg is enough for two words. */ | |
802a0058 | 1323 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
9ebbca7d | 1324 | (((CLASS) == FLOAT_REGS) \ |
2e360ab3 | 1325 | ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ |
f045b2c9 | 1326 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
580d3230 | 1327 | |
580d3230 | 1328 | |
cff9f8d5 | 1329 | /* Return a class of registers that cannot change FROM mode to TO mode. */ |
02188693 | 1330 | |
cff9f8d5 AH |
1331 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \ |
1332 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) ? FLOAT_REGS \ | |
1333 | : (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1 ? GENERAL_REGS \ | |
1334 | : NO_REGS) | |
02188693 | 1335 | |
f045b2c9 RS |
1336 | /* Stack layout; function entry, exit and calling. */ |
1337 | ||
6b67933e RK |
1338 | /* Enumeration to give which calling sequence to use. */ |
1339 | enum rs6000_abi { | |
1340 | ABI_NONE, | |
1341 | ABI_AIX, /* IBM's AIX */ | |
f607bc57 ZW |
1342 | ABI_AIX_NODESC, /* AIX calling sequence minus |
1343 | function descriptors */ | |
b6c9286a | 1344 | ABI_V4, /* System V.4/eabi */ |
ee890fe2 | 1345 | ABI_DARWIN /* Apple's Darwin (OS X kernel) */ |
6b67933e RK |
1346 | }; |
1347 | ||
b6c9286a MM |
1348 | extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */ |
1349 | ||
4697a36c MM |
1350 | /* Structure used to define the rs6000 stack */ |
1351 | typedef struct rs6000_stack { | |
1352 | int first_gp_reg_save; /* first callee saved GP register used */ | |
1353 | int first_fp_reg_save; /* first callee saved FP register used */ | |
00b960c7 | 1354 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ |
4697a36c MM |
1355 | int lr_save_p; /* true if the link reg needs to be saved */ |
1356 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
00b960c7 | 1357 | unsigned int vrsave_mask; /* mask of vec registers to save */ |
b6c9286a | 1358 | int toc_save_p; /* true if the TOC needs to be saved */ |
4697a36c MM |
1359 | int push_p; /* true if we need to allocate stack space */ |
1360 | int calls_p; /* true if the function makes any calls */ | |
6b67933e | 1361 | enum rs6000_abi abi; /* which ABI to use */ |
abc95ed3 RK |
1362 | int gp_save_offset; /* offset to save GP regs from initial SP */ |
1363 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
00b960c7 | 1364 | int altivec_save_offset; /* offset to save AltiVec regs from inital SP */ |
4697a36c MM |
1365 | int lr_save_offset; /* offset to save LR from initial SP */ |
1366 | int cr_save_offset; /* offset to save CR from initial SP */ | |
00b960c7 | 1367 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ |
a3170dc6 | 1368 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ |
b6c9286a | 1369 | int toc_save_offset; /* offset to save the TOC pointer */ |
4697a36c | 1370 | int varargs_save_offset; /* offset to save the varargs registers */ |
83720594 | 1371 | int ehrd_offset; /* offset to EH return data */ |
4697a36c MM |
1372 | int reg_size; /* register size (4 or 8) */ |
1373 | int varargs_size; /* size to hold V.4 args passed in regs */ | |
1374 | int vars_size; /* variable save area size */ | |
1375 | int parm_size; /* outgoing parameter size */ | |
1376 | int save_size; /* save area size */ | |
1377 | int fixed_size; /* fixed size of stack frame */ | |
1378 | int gp_size; /* size of saved GP registers */ | |
1379 | int fp_size; /* size of saved FP registers */ | |
00b960c7 | 1380 | int altivec_size; /* size of saved AltiVec registers */ |
4697a36c | 1381 | int cr_size; /* size to hold CR if not in save_size */ |
b6c9286a | 1382 | int lr_size; /* size to hold LR if not in save_size */ |
00b960c7 AH |
1383 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ |
1384 | int altivec_padding_size; /* size of altivec alignment padding if | |
1385 | not in save_size */ | |
a3170dc6 AH |
1386 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ |
1387 | int spe_padding_size; | |
b6c9286a | 1388 | int toc_size; /* size to hold TOC if not in save_size */ |
4697a36c MM |
1389 | int total_size; /* total bytes allocated for stack */ |
1390 | } rs6000_stack_t; | |
1391 | ||
f045b2c9 RS |
1392 | /* Define this if pushing a word on the stack |
1393 | makes the stack pointer a smaller address. */ | |
1394 | #define STACK_GROWS_DOWNWARD | |
1395 | ||
1396 | /* Define this if the nominal address of the stack frame | |
1397 | is at the high-address end of the local variables; | |
1398 | that is, each additional local variable allocated | |
1399 | goes at a more negative offset in the frame. | |
1400 | ||
1401 | On the RS/6000, we grow upwards, from the area after the outgoing | |
1402 | arguments. */ | |
1403 | /* #define FRAME_GROWS_DOWNWARD */ | |
1404 | ||
4697a36c | 1405 | /* Size of the outgoing register save area */ |
9ebbca7d | 1406 | #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ |
ee890fe2 SS |
1407 | || DEFAULT_ABI == ABI_AIX_NODESC \ |
1408 | || DEFAULT_ABI == ABI_DARWIN) \ | |
9ebbca7d GK |
1409 | ? (TARGET_64BIT ? 64 : 32) \ |
1410 | : 0) | |
4697a36c MM |
1411 | |
1412 | /* Size of the fixed area on the stack */ | |
9ebbca7d | 1413 | #define RS6000_SAVE_AREA \ |
ee890fe2 | 1414 | (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ |
9ebbca7d | 1415 | << (TARGET_64BIT ? 1 : 0)) |
4697a36c | 1416 | |
97f6e72f DE |
1417 | /* MEM representing address to save the TOC register */ |
1418 | #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ | |
1419 | plus_constant (stack_pointer_rtx, \ | |
1420 | (TARGET_32BIT ? 20 : 40))) | |
b6c9286a | 1421 | |
4697a36c MM |
1422 | /* Size of the V.4 varargs area if needed */ |
1423 | #define RS6000_VARARGS_AREA 0 | |
1424 | ||
4697a36c | 1425 | /* Align an address */ |
ed33106f | 1426 | #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) |
4697a36c MM |
1427 | |
1428 | /* Size of V.4 varargs area in bytes */ | |
1429 | #define RS6000_VARARGS_SIZE \ | |
2f3e5814 | 1430 | ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8) |
4697a36c | 1431 | |
f045b2c9 RS |
1432 | /* Offset within stack frame to start allocating local variables at. |
1433 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1434 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
c81bebd7 | 1435 | of the first local allocated. |
f045b2c9 RS |
1436 | |
1437 | On the RS/6000, the frame pointer is the same as the stack pointer, | |
1438 | except for dynamic allocations. So we start after the fixed area and | |
1439 | outgoing parameter area. */ | |
1440 | ||
802a0058 | 1441 | #define STARTING_FRAME_OFFSET \ |
7b094d6e AH |
1442 | (RS6000_ALIGN (current_function_outgoing_args_size, \ |
1443 | TARGET_ALTIVEC ? 16 : 8) \ | |
802a0058 MM |
1444 | + RS6000_VARARGS_AREA \ |
1445 | + RS6000_SAVE_AREA) | |
1446 | ||
1447 | /* Offset from the stack pointer register to an item dynamically | |
1448 | allocated on the stack, e.g., by `alloca'. | |
1449 | ||
1450 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1451 | length of the outgoing arguments. The default is correct for most | |
1452 | machines. See `function.c' for details. */ | |
1453 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ | |
7b094d6e AH |
1454 | (RS6000_ALIGN (current_function_outgoing_args_size, \ |
1455 | TARGET_ALTIVEC ? 16 : 8) \ | |
802a0058 | 1456 | + (STACK_POINTER_OFFSET)) |
f045b2c9 RS |
1457 | |
1458 | /* If we generate an insn to push BYTES bytes, | |
1459 | this says how many the stack pointer really advances by. | |
1460 | On RS/6000, don't define this because there are no push insns. */ | |
1461 | /* #define PUSH_ROUNDING(BYTES) */ | |
1462 | ||
1463 | /* Offset of first parameter from the argument pointer register value. | |
1464 | On the RS/6000, we define the argument pointer to the start of the fixed | |
1465 | area. */ | |
4697a36c | 1466 | #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA |
f045b2c9 | 1467 | |
62153b61 JM |
1468 | /* Offset from the argument pointer register value to the top of |
1469 | stack. This is different from FIRST_PARM_OFFSET because of the | |
1470 | register save area. */ | |
1471 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1472 | ||
f045b2c9 RS |
1473 | /* Define this if stack space is still allocated for a parameter passed |
1474 | in a register. The value is the number of bytes allocated to this | |
1475 | area. */ | |
4697a36c | 1476 | #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE |
f045b2c9 RS |
1477 | |
1478 | /* Define this if the above stack space is to be considered part of the | |
1479 | space allocated by the caller. */ | |
1480 | #define OUTGOING_REG_PARM_STACK_SPACE | |
1481 | ||
1482 | /* This is the difference between the logical top of stack and the actual sp. | |
1483 | ||
82e41834 | 1484 | For the RS/6000, sp points past the fixed area. */ |
4697a36c | 1485 | #define STACK_POINTER_OFFSET RS6000_SAVE_AREA |
f045b2c9 RS |
1486 | |
1487 | /* Define this if the maximum size of all the outgoing args is to be | |
1488 | accumulated and pushed during the prologue. The amount can be | |
1489 | found in the variable current_function_outgoing_args_size. */ | |
f73ad30e | 1490 | #define ACCUMULATE_OUTGOING_ARGS 1 |
f045b2c9 RS |
1491 | |
1492 | /* Value is the number of bytes of arguments automatically | |
1493 | popped when returning from a subroutine call. | |
8b109b37 | 1494 | FUNDECL is the declaration node of the function (as a tree), |
f045b2c9 RS |
1495 | FUNTYPE is the data type of the function (as a tree), |
1496 | or for a library call it is an identifier node for the subroutine name. | |
1497 | SIZE is the number of bytes of arguments passed on the stack. */ | |
1498 | ||
8b109b37 | 1499 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
f045b2c9 RS |
1500 | |
1501 | /* Define how to find the value returned by a function. | |
1502 | VALTYPE is the data type of the value (as a tree). | |
1503 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1504 | otherwise, FUNC is 0. | |
1505 | ||
a3170dc6 AH |
1506 | On the SPE, both FPs and vectors are returned in r3. |
1507 | ||
c81bebd7 | 1508 | On RS/6000 an integer value is in r3 and a floating-point value is in |
d14a6d05 | 1509 | fp1, unless -msoft-float. */ |
f045b2c9 | 1510 | |
39403d82 DE |
1511 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
1512 | gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \ | |
1513 | && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ | |
1514 | || POINTER_TYPE_P (VALTYPE) \ | |
1515 | ? word_mode : TYPE_MODE (VALTYPE), \ | |
16861f33 AH |
1516 | TREE_CODE (VALTYPE) == VECTOR_TYPE \ |
1517 | && TARGET_ALTIVEC ? ALTIVEC_ARG_RETURN \ | |
a3170dc6 AH |
1518 | : TREE_CODE (VALTYPE) == REAL_TYPE \ |
1519 | && TARGET_SPE_ABI && !TARGET_FPRS \ | |
1520 | ? GP_ARG_RETURN \ | |
1521 | : TREE_CODE (VALTYPE) == REAL_TYPE \ | |
1522 | && TARGET_HARD_FLOAT && TARGET_FPRS \ | |
e9cf9523 | 1523 | ? FP_ARG_RETURN : GP_ARG_RETURN) |
f045b2c9 RS |
1524 | |
1525 | /* Define how to find the value returned by a library function | |
1526 | assuming the value has mode MODE. */ | |
1527 | ||
0ac081f6 AH |
1528 | #define LIBCALL_VALUE(MODE) \ |
1529 | gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \ | |
1530 | : GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
a3170dc6 | 1531 | && TARGET_HARD_FLOAT && TARGET_FPRS \ |
0ac081f6 | 1532 | ? FP_ARG_RETURN : GP_ARG_RETURN) |
f045b2c9 | 1533 | |
6fa3f289 ZW |
1534 | /* The AIX ABI for the RS/6000 specifies that all structures are |
1535 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
1536 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
1537 | draft put them in memory, and GCC used to implement the draft | |
1538 | instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET | |
1539 | controls this instead of DEFAULT_ABI; V.4 targets needing backward | |
1540 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
1541 | default, and -m switches get the final word. See | |
52acbdcb ZW |
1542 | rs6000_override_options for more details. |
1543 | ||
0e9f8e82 JW |
1544 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit |
1545 | long double support is enabled. These values are returned in memory. | |
1546 | ||
52acbdcb ZW |
1547 | int_size_in_bytes returns -1 for variable size objects, which go in |
1548 | memory always. The cast to unsigned makes -1 > 8. */ | |
1549 | ||
6fa3f289 | 1550 | #define RETURN_IN_MEMORY(TYPE) \ |
0e9f8e82 JW |
1551 | ((AGGREGATE_TYPE_P (TYPE) \ |
1552 | && (TARGET_AIX_STRUCT_RET \ | |
1553 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 8)) \ | |
1554 | || (DEFAULT_ABI == ABI_V4 && TYPE_MODE (TYPE) == TFmode)) | |
f045b2c9 | 1555 | |
6fa3f289 ZW |
1556 | /* DRAFT_V4_STRUCT_RET defaults off. */ |
1557 | #define DRAFT_V4_STRUCT_RET 0 | |
f607bc57 ZW |
1558 | |
1559 | /* Let RETURN_IN_MEMORY control what happens. */ | |
1560 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
f045b2c9 | 1561 | |
a260abc9 | 1562 | /* Mode of stack savearea. |
dfdfa60f DE |
1563 | FUNCTION is VOIDmode because calling convention maintains SP. |
1564 | BLOCK needs Pmode for SP. | |
a260abc9 DE |
1565 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ |
1566 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
dfdfa60f DE |
1567 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ |
1568 | : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) | |
a260abc9 | 1569 | |
4697a36c MM |
1570 | /* Minimum and maximum general purpose registers used to hold arguments. */ |
1571 | #define GP_ARG_MIN_REG 3 | |
1572 | #define GP_ARG_MAX_REG 10 | |
1573 | #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1574 | ||
1575 | /* Minimum and maximum floating point registers used to hold arguments. */ | |
1576 | #define FP_ARG_MIN_REG 33 | |
7509c759 MM |
1577 | #define FP_ARG_AIX_MAX_REG 45 |
1578 | #define FP_ARG_V4_MAX_REG 40 | |
9ebbca7d | 1579 | #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ |
ee890fe2 SS |
1580 | || DEFAULT_ABI == ABI_AIX_NODESC \ |
1581 | || DEFAULT_ABI == ABI_DARWIN) \ | |
9ebbca7d | 1582 | ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) |
4697a36c MM |
1583 | #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
1584 | ||
0ac081f6 AH |
1585 | /* Minimum and maximum AltiVec registers used to hold arguments. */ |
1586 | #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
1587 | #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
1588 | #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
1589 | ||
4697a36c MM |
1590 | /* Return registers */ |
1591 | #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1592 | #define FP_ARG_RETURN FP_ARG_MIN_REG | |
0ac081f6 | 1593 | #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) |
4697a36c | 1594 | |
7509c759 | 1595 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
6a4cee5f | 1596 | #define CALL_NORMAL 0x00000000 /* no special processing */ |
9ebbca7d | 1597 | /* Bits in 0x00000001 are unused. */ |
6a4cee5f MM |
1598 | #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ |
1599 | #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1600 | #define CALL_LONG 0x00000008 /* always call indirect */ | |
7509c759 | 1601 | |
f045b2c9 RS |
1602 | /* 1 if N is a possible register number for a function value |
1603 | as seen by the caller. | |
1604 | ||
0ac081f6 AH |
1605 | On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ |
1606 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \ | |
1607 | || ((N) == FP_ARG_RETURN) \ | |
1608 | || (TARGET_ALTIVEC && \ | |
1609 | (N) == ALTIVEC_ARG_RETURN)) | |
f045b2c9 RS |
1610 | |
1611 | /* 1 if N is a possible register number for function argument passing. | |
0ac081f6 AH |
1612 | On RS/6000, these are r3-r10 and fp1-fp13. |
1613 | On AltiVec, v2 - v13 are used for passing vectors. */ | |
4697a36c | 1614 | #define FUNCTION_ARG_REGNO_P(N) \ |
b1765bde | 1615 | (((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \ |
0ac081f6 | 1616 | || (TARGET_ALTIVEC && \ |
1a3ab9e1 | 1617 | (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \ |
6d0f55e6 | 1618 | || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG))) |
f045b2c9 | 1619 | |
f045b2c9 | 1620 | \f |
00dba523 NC |
1621 | /* A C structure for machine-specific, per-function data. |
1622 | This is added to the cfun structure. */ | |
e2500fed | 1623 | typedef struct machine_function GTY(()) |
00dba523 NC |
1624 | { |
1625 | /* Whether a System V.4 varargs area was created. */ | |
1626 | int sysv_varargs_p; | |
71f123ca FS |
1627 | /* Flags if __builtin_return_address (n) with n >= 1 was used. */ |
1628 | int ra_needs_full_frame; | |
00dba523 NC |
1629 | } machine_function; |
1630 | ||
f045b2c9 RS |
1631 | /* Define a data type for recording info about an argument list |
1632 | during the scan of that argument list. This data type should | |
1633 | hold all necessary information about the function itself | |
1634 | and about the args processed so far, enough to enable macros | |
1635 | such as FUNCTION_ARG to determine where the next arg should go. | |
1636 | ||
1637 | On the RS/6000, this is a structure. The first element is the number of | |
1638 | total argument words, the second is used to store the next | |
1639 | floating-point register number, and the third says how many more args we | |
4697a36c MM |
1640 | have prototype types for. |
1641 | ||
4cc833b7 RH |
1642 | For ABI_V4, we treat these slightly differently -- `sysv_gregno' is |
1643 | the next availible GP register, `fregno' is the next available FP | |
1644 | register, and `words' is the number of words used on the stack. | |
1645 | ||
bd227acc | 1646 | The varargs/stdarg support requires that this structure's size |
4cc833b7 | 1647 | be a multiple of sizeof(int). */ |
4697a36c MM |
1648 | |
1649 | typedef struct rs6000_args | |
1650 | { | |
4cc833b7 | 1651 | int words; /* # words used for passing GP registers */ |
6a4cee5f | 1652 | int fregno; /* next available FP register */ |
0ac081f6 | 1653 | int vregno; /* next available AltiVec register */ |
6a4cee5f MM |
1654 | int nargs_prototype; /* # args left in the current prototype */ |
1655 | int orig_nargs; /* Original value of nargs_prototype */ | |
6a4cee5f MM |
1656 | int prototype; /* Whether a prototype was defined */ |
1657 | int call_cookie; /* Do special things for this call */ | |
4cc833b7 | 1658 | int sysv_gregno; /* next available GP register */ |
4697a36c | 1659 | } CUMULATIVE_ARGS; |
f045b2c9 RS |
1660 | |
1661 | /* Define intermediate macro to compute the size (in registers) of an argument | |
1662 | for the RS/6000. */ | |
1663 | ||
d34c5b80 DE |
1664 | #define RS6000_ARG_SIZE(MODE, TYPE) \ |
1665 | ((MODE) != BLKmode \ | |
c5d71f39 | 1666 | ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ |
0c769cf8 | 1667 | : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) |
f045b2c9 RS |
1668 | |
1669 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1670 | for a call to a function whose data type is FNTYPE. | |
1671 | For a library call, FNTYPE is 0. */ | |
1672 | ||
2c7ee1a6 | 1673 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
4697a36c | 1674 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE) |
f045b2c9 RS |
1675 | |
1676 | /* Similar, but when scanning the definition of a procedure. We always | |
1677 | set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1678 | ||
4697a36c MM |
1679 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \ |
1680 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE) | |
f045b2c9 RS |
1681 | |
1682 | /* Update the data in CUM to advance over an argument | |
1683 | of mode MODE and data type TYPE. | |
1684 | (TYPE is null for libcalls where that information may not be available.) */ | |
1685 | ||
1686 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
4697a36c | 1687 | function_arg_advance (&CUM, MODE, TYPE, NAMED) |
f045b2c9 | 1688 | |
a0ab749a | 1689 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
4697a36c MM |
1690 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ |
1691 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1692 | && (CUM).fregno <= FP_ARG_MAX_REG \ | |
a3170dc6 | 1693 | && TARGET_HARD_FLOAT && TARGET_FPRS) |
f045b2c9 | 1694 | |
a0ab749a | 1695 | /* Nonzero if we can use an AltiVec register to pass this arg. */ |
0ac081f6 AH |
1696 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \ |
1697 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
1698 | && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \ | |
1699 | && TARGET_ALTIVEC_ABI) | |
1700 | ||
f045b2c9 RS |
1701 | /* Determine where to put an argument to a function. |
1702 | Value is zero to push the argument on the stack, | |
1703 | or a hard register in which to store the argument. | |
1704 | ||
1705 | MODE is the argument's machine mode. | |
1706 | TYPE is the data type of the argument (as a tree). | |
1707 | This is null for libcalls where that information may | |
1708 | not be available. | |
1709 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1710 | the preceding args and about the function being called. | |
1711 | NAMED is nonzero if this argument is a named parameter | |
1712 | (otherwise it is an extra parameter matching an ellipsis). | |
1713 | ||
1714 | On RS/6000 the first eight words of non-FP are normally in registers | |
1715 | and the rest are pushed. The first 13 FP args are in registers. | |
1716 | ||
1717 | If this is floating-point and no prototype is specified, we use | |
4d6697ca RK |
1718 | both an FP and integer register (or possibly FP reg and stack). Library |
1719 | functions (when TYPE is zero) always have the proper types for args, | |
1720 | so we can pass the FP value just in one register. emit_library_function | |
1721 | doesn't support EXPR_LIST anyway. */ | |
f045b2c9 | 1722 | |
4697a36c MM |
1723 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1724 | function_arg (&CUM, MODE, TYPE, NAMED) | |
f045b2c9 RS |
1725 | |
1726 | /* For an arg passed partly in registers and partly in memory, | |
1727 | this is the number of registers used. | |
1728 | For args passed entirely in registers or entirely in memory, zero. */ | |
1729 | ||
4697a36c MM |
1730 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
1731 | function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) | |
1732 | ||
1733 | /* A C expression that indicates when an argument must be passed by | |
1734 | reference. If nonzero for an argument, a copy of that argument is | |
1735 | made in memory and a pointer to the argument is passed instead of | |
1736 | the argument itself. The pointer is passed in whatever way is | |
82e41834 | 1737 | appropriate for passing a pointer to that type. */ |
4697a36c MM |
1738 | |
1739 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ | |
1740 | function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED) | |
f045b2c9 | 1741 | |
c229cba9 DE |
1742 | /* If defined, a C expression which determines whether, and in which |
1743 | direction, to pad out an argument with extra space. The value | |
1744 | should be of type `enum direction': either `upward' to pad above | |
1745 | the argument, `downward' to pad below, or `none' to inhibit | |
1746 | padding. */ | |
1747 | ||
9ebbca7d | 1748 | #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) |
c229cba9 | 1749 | |
b6c9286a | 1750 | /* If defined, a C expression that gives the alignment boundary, in bits, |
c81bebd7 | 1751 | of an argument with the specified mode and type. If it is not defined, |
b6c9286a MM |
1752 | PARM_BOUNDARY is used for all arguments. */ |
1753 | ||
1754 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
1755 | function_arg_boundary (MODE, TYPE) | |
1756 | ||
f045b2c9 | 1757 | /* Perform any needed actions needed for a function that is receiving a |
c81bebd7 | 1758 | variable number of arguments. |
f045b2c9 RS |
1759 | |
1760 | CUM is as above. | |
1761 | ||
1762 | MODE and TYPE are the mode and type of the current parameter. | |
1763 | ||
1764 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
1765 | that must be pushed by the prolog to pretend that our caller pushed | |
1766 | it. | |
1767 | ||
1768 | Normally, this macro will push all remaining incoming registers on the | |
1769 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
1770 | ||
4697a36c MM |
1771 | #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ |
1772 | setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL) | |
1773 | ||
dfafc897 FS |
1774 | /* Define the `__builtin_va_list' type for the ABI. */ |
1775 | #define BUILD_VA_LIST_TYPE(VALIST) \ | |
1776 | (VALIST) = rs6000_build_va_list () | |
4697a36c | 1777 | |
dfafc897 | 1778 | /* Implement `va_start' for varargs and stdarg. */ |
e5faf155 ZW |
1779 | #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ |
1780 | rs6000_va_start (valist, nextarg) | |
dfafc897 FS |
1781 | |
1782 | /* Implement `va_arg'. */ | |
1783 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
1784 | rs6000_va_arg (valist, type) | |
f045b2c9 | 1785 | |
2a55fd42 DE |
1786 | /* For AIX, the rule is that structures are passed left-aligned in |
1787 | their stack slot. However, GCC does not presently do this: | |
1788 | structures which are the same size as integer types are passed | |
1789 | right-aligned, as if they were in fact integers. This only | |
1790 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. | |
1791 | ABI_V4 does not use std_expand_builtin_va_arg. */ | |
1792 | #define PAD_VARARGS_DOWN (TYPE_MODE (type) != BLKmode) | |
1793 | ||
d34c5b80 DE |
1794 | /* Define this macro to be a nonzero value if the location where a function |
1795 | argument is passed depends on whether or not it is a named argument. */ | |
1796 | #define STRICT_ARGUMENT_NAMING 1 | |
1797 | ||
f045b2c9 | 1798 | /* Output assembler code to FILE to increment profiler label # LABELNO |
58a39e45 | 1799 | for profiling a function entry. */ |
f045b2c9 RS |
1800 | |
1801 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
58a39e45 | 1802 | output_function_profiler ((FILE), (LABELNO)); |
f045b2c9 RS |
1803 | |
1804 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1805 | the stack pointer does not matter. No definition is equivalent to | |
1806 | always zero. | |
1807 | ||
a0ab749a | 1808 | On the RS/6000, this is nonzero because we can restore the stack from |
f045b2c9 RS |
1809 | its backpointer, which we maintain. */ |
1810 | #define EXIT_IGNORE_STACK 1 | |
1811 | ||
a701949a FS |
1812 | /* Define this macro as a C expression that is nonzero for registers |
1813 | that are used by the epilogue or the return' pattern. The stack | |
1814 | and frame pointer registers are already be assumed to be used as | |
1815 | needed. */ | |
1816 | ||
83720594 RH |
1817 | #define EPILOGUE_USES(REGNO) \ |
1818 | ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \ | |
b1765bde | 1819 | || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ |
83720594 | 1820 | || (current_function_calls_eh_return \ |
3553b09d | 1821 | && TARGET_AIX \ |
83720594 | 1822 | && (REGNO) == TOC_REGISTER)) |
2bfcf297 | 1823 | |
f045b2c9 | 1824 | \f |
eaf1bcf1 | 1825 | /* TRAMPOLINE_TEMPLATE deleted */ |
f045b2c9 RS |
1826 | |
1827 | /* Length in units of the trampoline for entering a nested function. */ | |
1828 | ||
b6c9286a | 1829 | #define TRAMPOLINE_SIZE rs6000_trampoline_size () |
f045b2c9 RS |
1830 | |
1831 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1832 | FNADDR is an RTX for the address of the function's pure code. | |
1833 | CXT is an RTX for the static chain value for the function. */ | |
1834 | ||
1835 | #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ | |
b6c9286a | 1836 | rs6000_initialize_trampoline (ADDR, FNADDR, CXT) |
f045b2c9 | 1837 | \f |
f33985c6 MS |
1838 | /* Definitions for __builtin_return_address and __builtin_frame_address. |
1839 | __builtin_return_address (0) should give link register (65), enable | |
82e41834 | 1840 | this. */ |
f33985c6 MS |
1841 | /* This should be uncommented, so that the link register is used, but |
1842 | currently this would result in unmatched insns and spilling fixed | |
1843 | registers so we'll leave it for another day. When these problems are | |
1844 | taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1845 | (mrs) */ | |
1846 | /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
f09d4c33 | 1847 | |
b6c9286a MM |
1848 | /* Number of bytes into the frame return addresses can be found. See |
1849 | rs6000_stack_info in rs6000.c for more information on how the different | |
1850 | abi's store the return address. */ | |
1851 | #define RETURN_ADDRESS_OFFSET \ | |
1852 | ((DEFAULT_ABI == ABI_AIX \ | |
ee890fe2 | 1853 | || DEFAULT_ABI == ABI_DARWIN \ |
05ef2698 | 1854 | || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \ |
3b370352 | 1855 | (DEFAULT_ABI == ABI_V4) ? 4 : \ |
c4636dd1 | 1856 | (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) |
f09d4c33 | 1857 | |
f33985c6 MS |
1858 | /* The current return address is in link register (65). The return address |
1859 | of anything farther back is accessed normally at an offset of 8 from the | |
1860 | frame pointer. */ | |
71f123ca FS |
1861 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1862 | (rs6000_return_addr (COUNT, FRAME)) | |
1863 | ||
f33985c6 | 1864 | \f |
f045b2c9 RS |
1865 | /* Definitions for register eliminations. |
1866 | ||
1867 | We have two registers that can be eliminated on the RS/6000. First, the | |
1868 | frame pointer register can often be eliminated in favor of the stack | |
1869 | pointer register. Secondly, the argument pointer register can always be | |
642a35f1 JW |
1870 | eliminated; it is replaced with either the stack or frame pointer. |
1871 | ||
1872 | In addition, we use the elimination mechanism to see if r30 is needed | |
1873 | Initially we assume that it isn't. If it is, we spill it. This is done | |
1874 | by making it an eliminable register. We replace it with itself so that | |
1875 | if it isn't needed, then existing uses won't be modified. */ | |
f045b2c9 RS |
1876 | |
1877 | /* This is an array of structures. Each structure initializes one pair | |
1878 | of eliminable registers. The "from" register number is given first, | |
1879 | followed by "to". Eliminations of the same "from" register are listed | |
1880 | in order of preference. */ | |
1881 | #define ELIMINABLE_REGS \ | |
1882 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1883 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
642a35f1 | 1884 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ |
97b23853 | 1885 | { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } |
f045b2c9 RS |
1886 | |
1887 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
1888 | Frame pointer elimination is automatically handled. | |
1889 | ||
1890 | For the RS/6000, if frame pointer elimination is being done, we would like | |
642a35f1 JW |
1891 | to convert ap into fp, not sp. |
1892 | ||
abc95ed3 | 1893 | We need r30 if -mminimal-toc was specified, and there are constant pool |
642a35f1 | 1894 | references. */ |
f045b2c9 | 1895 | |
97b23853 GK |
1896 | #define CAN_ELIMINATE(FROM, TO) \ |
1897 | ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ | |
1898 | ? ! frame_pointer_needed \ | |
1899 | : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \ | |
1900 | ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \ | |
f045b2c9 RS |
1901 | : 1) |
1902 | ||
1903 | /* Define the offset between two registers, one to be eliminated, and the other | |
1904 | its replacement, at the start of a routine. */ | |
1905 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1906 | { \ | |
4697a36c | 1907 | rs6000_stack_t *info = rs6000_stack_info (); \ |
f045b2c9 RS |
1908 | \ |
1909 | if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
4697a36c MM |
1910 | (OFFSET) = (info->push_p) ? 0 : - info->total_size; \ |
1911 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ | |
1912 | (OFFSET) = info->total_size; \ | |
1913 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
1914 | (OFFSET) = (info->push_p) ? info->total_size : 0; \ | |
97b23853 | 1915 | else if ((FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM) \ |
642a35f1 | 1916 | (OFFSET) = 0; \ |
f045b2c9 RS |
1917 | else \ |
1918 | abort (); \ | |
1919 | } | |
1920 | \f | |
1921 | /* Addressing modes, and classification of registers for them. */ | |
1922 | ||
940da324 JL |
1923 | #define HAVE_PRE_DECREMENT 1 |
1924 | #define HAVE_PRE_INCREMENT 1 | |
f045b2c9 RS |
1925 | |
1926 | /* Macros to check register numbers against specific register classes. */ | |
1927 | ||
1928 | /* These assume that REGNO is a hard or pseudo reg number. | |
1929 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1930 | or a pseudo reg currently allocated to a suitable hard reg. | |
1931 | Since they use reg_renumber, they are safe only once reg_renumber | |
1932 | has been allocated, which happens in local-alloc.c. */ | |
1933 | ||
1934 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1935 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1936 | ? (REGNO) <= 31 || (REGNO) == 67 \ | |
1937 | : (reg_renumber[REGNO] >= 0 \ | |
1938 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67))) | |
1939 | ||
1940 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1941 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1942 | ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
1943 | : (reg_renumber[REGNO] > 0 \ | |
1944 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67))) | |
1945 | \f | |
1946 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1947 | ||
1948 | #define MAX_REGS_PER_ADDRESS 2 | |
1949 | ||
1950 | /* Recognize any constant value that is a valid address. */ | |
1951 | ||
6eff269e BK |
1952 | #define CONSTANT_ADDRESS_P(X) \ |
1953 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1954 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1955 | || GET_CODE (X) == HIGH) | |
f045b2c9 RS |
1956 | |
1957 | /* Nonzero if the constant value X is a legitimate general operand. | |
1958 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1959 | ||
1960 | On the RS/6000, all integer constants are acceptable, most won't be valid | |
1961 | for particular insns, though. Only easy FP constants are | |
1962 | acceptable. */ | |
1963 | ||
1964 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1965 | (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \ | |
a260abc9 | 1966 | || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \ |
f045b2c9 RS |
1967 | || easy_fp_constant (X, GET_MODE (X))) |
1968 | ||
1969 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1970 | and check its validity for a certain class. | |
1971 | We have two alternate definitions for each of them. | |
1972 | The usual definition accepts all pseudo regs; the other rejects | |
1973 | them unless they have been allocated suitable hard regs. | |
1974 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1975 | ||
1976 | Most source files want to accept pseudo regs in the hope that | |
1977 | they will get allocated to the class that the insn wants them to be in. | |
1978 | Source files for reload pass need to be strict. | |
1979 | After reload, it makes no difference, since pseudo regs have | |
1980 | been eliminated by then. */ | |
1981 | ||
258bfae2 FS |
1982 | #ifdef REG_OK_STRICT |
1983 | # define REG_OK_STRICT_FLAG 1 | |
1984 | #else | |
1985 | # define REG_OK_STRICT_FLAG 0 | |
1986 | #endif | |
f045b2c9 RS |
1987 | |
1988 | /* Nonzero if X is a hard reg that can be used as an index | |
258bfae2 FS |
1989 | or if it is a pseudo reg in the non-strict case. */ |
1990 | #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ | |
1991 | ((! (STRICT) \ | |
1992 | && (REGNO (X) <= 31 \ | |
1993 | || REGNO (X) == ARG_POINTER_REGNUM \ | |
1994 | || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \ | |
1995 | || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X)))) | |
f045b2c9 RS |
1996 | |
1997 | /* Nonzero if X is a hard reg that can be used as a base reg | |
258bfae2 FS |
1998 | or if it is a pseudo reg in the non-strict case. */ |
1999 | #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ | |
2000 | (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT))) | |
f045b2c9 | 2001 | |
258bfae2 FS |
2002 | #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG) |
2003 | #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG) | |
f045b2c9 RS |
2004 | \f |
2005 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
2006 | that is a valid memory address for an instruction. | |
2007 | The MODE argument is the machine mode for the MEM expression | |
2008 | that wants to use this address. | |
2009 | ||
2010 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
2011 | refers to a constant pool entry of an address (or the sum of it | |
2012 | plus a constant), a short (16-bit signed) constant plus a register, | |
2013 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 2014 | auto-increment. For DFmode and DImode with a constant plus register, |
2f3e5814 | 2015 | we must ensure that both words are addressable or PowerPC64 with offset |
1427100a DE |
2016 | word aligned. |
2017 | ||
2018 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
2019 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
2020 | adjacent memory cells are accessed by adding word-sized offsets | |
2021 | during assembly output. */ | |
f045b2c9 | 2022 | |
9ebbca7d GK |
2023 | #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X)) |
2024 | ||
2025 | #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X)) | |
f045b2c9 | 2026 | |
17072732 | 2027 | /* SPE offset addressing is limited to 5-bits worth of double words. */ |
88c38659 | 2028 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) |
a3170dc6 | 2029 | |
f045b2c9 | 2030 | #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \ |
9ebbca7d GK |
2031 | (TARGET_TOC \ |
2032 | && GET_CODE (X) == PLUS \ | |
2033 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2034 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \ | |
2035 | && CONSTANT_POOL_EXPR_P (XEXP (X, 1))) | |
f045b2c9 | 2036 | |
7509c759 | 2037 | #define LEGITIMATE_SMALL_DATA_P(MODE, X) \ |
f607bc57 | 2038 | (DEFAULT_ABI == ABI_V4 \ |
81795281 | 2039 | && !flag_pic && !TARGET_TOC \ |
88228c4b MM |
2040 | && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \ |
2041 | && small_data_operand (X, MODE)) | |
7509c759 | 2042 | |
258bfae2 | 2043 | #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \ |
f045b2c9 | 2044 | (GET_CODE (X) == CONST_INT \ |
5b6f7b96 | 2045 | && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000) |
f045b2c9 | 2046 | |
258bfae2 FS |
2047 | #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \ |
2048 | (GET_CODE (X) == PLUS \ | |
2049 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2050 | && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ | |
2051 | && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \ | |
37fa124a AM |
2052 | && (! ALTIVEC_VECTOR_MODE (MODE) \ |
2053 | || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \ | |
a3170dc6 AH |
2054 | && (! SPE_VECTOR_MODE (MODE) \ |
2055 | || (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2056 | && SPE_CONST_OFFSET_OK (INTVAL (XEXP (X, 1))))) \ | |
258bfae2 FS |
2057 | && (((MODE) != DFmode && (MODE) != DImode) \ |
2058 | || (TARGET_32BIT \ | |
2059 | ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \ | |
2060 | : ! (INTVAL (XEXP (X, 1)) & 3))) \ | |
fcce224d | 2061 | && (((MODE) != TFmode && (MODE) != TImode) \ |
258bfae2 FS |
2062 | || (TARGET_32BIT \ |
2063 | ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \ | |
2064 | : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \ | |
1465faec | 2065 | && ! (INTVAL (XEXP (X, 1)) & 3))))) |
f045b2c9 | 2066 | |
258bfae2 FS |
2067 | #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \ |
2068 | (GET_CODE (X) == PLUS \ | |
2069 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2070 | && GET_CODE (XEXP (X, 1)) == REG \ | |
2071 | && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ | |
2072 | && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \ | |
2073 | || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \ | |
2074 | && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT))))) | |
2075 | ||
2076 | #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \ | |
2077 | (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT))) | |
2078 | ||
6ac7bf2c GK |
2079 | #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \ |
2080 | (TARGET_ELF \ | |
2081 | && ! flag_pic && ! TARGET_TOC \ | |
2082 | && GET_MODE_NUNITS (MODE) == 1 \ | |
2083 | && (GET_MODE_BITSIZE (MODE) <= 32 \ | |
a3170dc6 | 2084 | || (TARGET_HARD_FLOAT && TARGET_FPRS && (MODE) == DFmode)) \ |
6ac7bf2c GK |
2085 | && GET_CODE (X) == LO_SUM \ |
2086 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2087 | && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ | |
4697a36c MM |
2088 | && CONSTANT_P (XEXP (X, 1))) |
2089 | ||
258bfae2 FS |
2090 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
2091 | { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \ | |
2092 | goto ADDR; \ | |
f045b2c9 RS |
2093 | } |
2094 | \f | |
2095 | /* Try machine-dependent ways of modifying an illegitimate address | |
2096 | to be legitimate. If we find one, return the new, valid address. | |
2097 | This macro is used in only one place: `memory_address' in explow.c. | |
2098 | ||
2099 | OLDX is the address as it was before break_out_memory_refs was called. | |
2100 | In some cases it is useful to look at this to decide what needs to be done. | |
2101 | ||
2102 | MODE and WIN are passed so that this macro can use | |
2103 | GO_IF_LEGITIMATE_ADDRESS. | |
2104 | ||
2105 | It is always safe for this macro to do nothing. It exists to recognize | |
2106 | opportunities to optimize the output. | |
2107 | ||
2108 | On RS/6000, first check for the sum of a register with a constant | |
2109 | integer that is out of range. If so, generate code to add the | |
2110 | constant with the low-order 16 bits masked to the register and force | |
2111 | this result into another register (this can be done with `cau'). | |
c81bebd7 | 2112 | Then generate an address of REG+(CONST&0xffff), allowing for the |
f045b2c9 RS |
2113 | possibility of bit 16 being a one. |
2114 | ||
2115 | Then check for the sum of a register and something not constant, try to | |
2116 | load the other things into a register and return the sum. */ | |
2117 | ||
9ebbca7d GK |
2118 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ |
2119 | { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \ | |
2120 | if (result != NULL_RTX) \ | |
2121 | { \ | |
2122 | (X) = result; \ | |
2123 | goto WIN; \ | |
2124 | } \ | |
f045b2c9 RS |
2125 | } |
2126 | ||
a260abc9 DE |
2127 | /* Try a machine-dependent way of reloading an illegitimate address |
2128 | operand. If we find one, push the reload and jump to WIN. This | |
2129 | macro is used in only one place: `find_reloads_address' in reload.c. | |
2130 | ||
24ea750e DJ |
2131 | Implemented on rs6000 by rs6000_legitimize_reload_address. |
2132 | Note that (X) is evaluated twice; this is safe in current usage. */ | |
a260abc9 | 2133 | |
a9098fd0 GK |
2134 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
2135 | do { \ | |
24ea750e DJ |
2136 | int win; \ |
2137 | (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \ | |
2138 | (int)(TYPE), (IND_LEVELS), &win); \ | |
2139 | if ( win ) \ | |
2140 | goto WIN; \ | |
a260abc9 DE |
2141 | } while (0) |
2142 | ||
f045b2c9 RS |
2143 | /* Go to LABEL if ADDR (a legitimate address expression) |
2144 | has an effect that depends on the machine mode it is used for. | |
2145 | ||
2146 | On the RS/6000 this is true if the address is valid with a zero offset | |
2147 | but not with an offset of four (this means it cannot be used as an | |
2148 | address for DImode or DFmode) or is a pre-increment or decrement. Since | |
2149 | we know it is valid, we just check for an address that is not valid with | |
2150 | an offset of four. */ | |
2151 | ||
2152 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
2153 | { if (GET_CODE (ADDR) == PLUS \ | |
2154 | && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \ | |
2f3e5814 DE |
2155 | && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \ |
2156 | (TARGET_32BIT ? 4 : 8))) \ | |
f045b2c9 | 2157 | goto LABEL; \ |
38c1f2d7 | 2158 | if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \ |
f045b2c9 | 2159 | goto LABEL; \ |
38c1f2d7 | 2160 | if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \ |
f045b2c9 | 2161 | goto LABEL; \ |
4697a36c MM |
2162 | if (GET_CODE (ADDR) == LO_SUM) \ |
2163 | goto LABEL; \ | |
f045b2c9 | 2164 | } |
766a866c MM |
2165 | \f |
2166 | /* The register number of the register used to address a table of | |
2167 | static data addresses in memory. In some cases this register is | |
2168 | defined by a processor's "application binary interface" (ABI). | |
2169 | When this macro is defined, RTL is generated for this register | |
2170 | once, as with the stack pointer and frame pointer registers. If | |
2171 | this macro is not defined, it is up to the machine-dependent files | |
2172 | to allocate such a register (if necessary). */ | |
2173 | ||
1db02437 FS |
2174 | #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 |
2175 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) | |
766a866c | 2176 | |
97b23853 | 2177 | #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) |
9ebbca7d | 2178 | |
766a866c MM |
2179 | /* Define this macro if the register defined by |
2180 | `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
089a05b8 | 2181 | this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ |
766a866c MM |
2182 | |
2183 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
2184 | ||
2185 | /* By generating position-independent code, when two different | |
2186 | programs (A and B) share a common library (libC.a), the text of | |
2187 | the library can be shared whether or not the library is linked at | |
2188 | the same address for both programs. In some of these | |
2189 | environments, position-independent code requires not only the use | |
2190 | of different addressing modes, but also special code to enable the | |
2191 | use of these addressing modes. | |
2192 | ||
2193 | The `FINALIZE_PIC' macro serves as a hook to emit these special | |
2194 | codes once the function is being compiled into assembly code, but | |
2195 | not before. (It is not done before, because in the case of | |
2196 | compiling an inline function, it would lead to multiple PIC | |
2197 | prologues being included in functions which used inline functions | |
2198 | and were compiled to assembly language.) */ | |
2199 | ||
8d30c4ee | 2200 | /* #define FINALIZE_PIC */ |
766a866c | 2201 | |
766a866c MM |
2202 | /* A C expression that is nonzero if X is a legitimate immediate |
2203 | operand on the target machine when generating position independent | |
2204 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
2205 | not check this. You can also assume FLAG_PIC is true, so you need | |
2206 | not check it either. You need not define this macro if all | |
2207 | constants (including `SYMBOL_REF') can be immediate operands when | |
2208 | generating position independent code. */ | |
2209 | ||
2210 | /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
2211 | ||
30ea98f1 MM |
2212 | /* In rare cases, correct code generation requires extra machine |
2213 | dependent processing between the second jump optimization pass and | |
2214 | delayed branch scheduling. On those machines, define this macro | |
9ebbca7d | 2215 | as a C statement to act on the code starting at INSN. */ |
30ea98f1 | 2216 | |
9ebbca7d | 2217 | /* #define MACHINE_DEPENDENT_REORG(INSN) */ |
30ea98f1 | 2218 | |
f045b2c9 RS |
2219 | \f |
2220 | /* Define this if some processing needs to be done immediately before | |
4255474b | 2221 | emitting code for an insn. */ |
f045b2c9 | 2222 | |
4255474b | 2223 | /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */ |
f045b2c9 RS |
2224 | |
2225 | /* Specify the machine mode that this machine uses | |
2226 | for the index in the tablejump instruction. */ | |
e1565e65 | 2227 | #define CASE_VECTOR_MODE SImode |
f045b2c9 | 2228 | |
18543a22 ILT |
2229 | /* Define as C expression which evaluates to nonzero if the tablejump |
2230 | instruction expects the table to contain offsets from the address of the | |
2231 | table. | |
82e41834 | 2232 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 2233 | #define CASE_VECTOR_PC_RELATIVE 1 |
f045b2c9 | 2234 | |
f045b2c9 RS |
2235 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
2236 | #define DEFAULT_SIGNED_CHAR 0 | |
2237 | ||
2238 | /* This flag, if defined, says the same insns that convert to a signed fixnum | |
2239 | also convert validly to an unsigned one. */ | |
2240 | ||
2241 | /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ | |
2242 | ||
2243 | /* Max number of bytes we can move from memory to memory | |
2244 | in one reasonably fast instruction. */ | |
2f3e5814 | 2245 | #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) |
7e69e155 | 2246 | #define MAX_MOVE_MAX 8 |
f045b2c9 RS |
2247 | |
2248 | /* Nonzero if access to memory by bytes is no faster than for words. | |
a0ab749a | 2249 | Also nonzero if doing byte operations (specifically shifts) in registers |
f045b2c9 RS |
2250 | is undesirable. */ |
2251 | #define SLOW_BYTE_ACCESS 1 | |
2252 | ||
9a63901f RK |
2253 | /* Define if operations between registers always perform the operation |
2254 | on the full register even if a narrower mode is specified. */ | |
2255 | #define WORD_REGISTER_OPERATIONS | |
2256 | ||
2257 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2258 | will either zero-extend or sign-extend. The value of this macro should | |
2259 | be the code that says which one of the two operations is implicitly | |
2260 | done, NIL if none. */ | |
2261 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
225211e2 RK |
2262 | |
2263 | /* Define if loading short immediate values into registers sign extends. */ | |
2264 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
fdaff8ba | 2265 | \f |
f045b2c9 RS |
2266 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
2267 | is done just by pretending it is already truncated. */ | |
2268 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2269 | ||
2270 | /* Specify the machine mode that pointers have. | |
2271 | After generation of rtl, the compiler makes no further distinction | |
2272 | between pointers and any other objects of this machine mode. */ | |
2f3e5814 | 2273 | #define Pmode (TARGET_32BIT ? SImode : DImode) |
f045b2c9 RS |
2274 | |
2275 | /* Mode of a function address in a call instruction (for indexing purposes). | |
f045b2c9 | 2276 | Doesn't matter on RS/6000. */ |
2f3e5814 | 2277 | #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode) |
f045b2c9 RS |
2278 | |
2279 | /* Define this if addresses of constant functions | |
2280 | shouldn't be put through pseudo regs where they can be cse'd. | |
2281 | Desirable on machines where ordinary constants are expensive | |
2282 | but a CALL with constant address is cheap. */ | |
2283 | #define NO_FUNCTION_CSE | |
2284 | ||
d969caf8 | 2285 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
6febd581 RK |
2286 | few bits. |
2287 | ||
2288 | The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
2289 | have been dropped from the PowerPC architecture. */ | |
2290 | ||
4697a36c | 2291 | #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0) |
f045b2c9 | 2292 | |
f045b2c9 RS |
2293 | /* Compute the cost of computing a constant rtl expression RTX |
2294 | whose rtx-code is CODE. The body of this macro is a portion | |
2295 | of a switch statement. If the code is computed here, | |
2296 | return it with a return statement. Otherwise, break from the switch. | |
2297 | ||
01554f00 | 2298 | On the RS/6000, if it is valid in the insn, it is free. So this |
f045b2c9 RS |
2299 | always returns 0. */ |
2300 | ||
4697a36c | 2301 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
f045b2c9 RS |
2302 | case CONST_INT: \ |
2303 | case CONST: \ | |
2304 | case LABEL_REF: \ | |
2305 | case SYMBOL_REF: \ | |
2306 | case CONST_DOUBLE: \ | |
4697a36c | 2307 | case HIGH: \ |
f045b2c9 RS |
2308 | return 0; |
2309 | ||
2310 | /* Provide the costs of a rtl expression. This is in the body of a | |
2311 | switch on CODE. */ | |
2312 | ||
38c1f2d7 MM |
2313 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
2314 | case PLUS: \ | |
2315 | return ((GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
a260abc9 DE |
2316 | && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \ |
2317 | + 0x8000) >= 0x10000) \ | |
296b8152 | 2318 | && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \ |
38c1f2d7 MM |
2319 | ? COSTS_N_INSNS (2) \ |
2320 | : COSTS_N_INSNS (1)); \ | |
2321 | case AND: \ | |
38c1f2d7 MM |
2322 | case IOR: \ |
2323 | case XOR: \ | |
a260abc9 DE |
2324 | return ((GET_CODE (XEXP (X, 1)) == CONST_INT \ |
2325 | && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \ | |
296b8152 | 2326 | && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \ |
38c1f2d7 MM |
2327 | ? COSTS_N_INSNS (2) \ |
2328 | : COSTS_N_INSNS (1)); \ | |
2329 | case MULT: \ | |
055dd007 DE |
2330 | if (optimize_size) \ |
2331 | return COSTS_N_INSNS (2); \ | |
38c1f2d7 MM |
2332 | switch (rs6000_cpu) \ |
2333 | { \ | |
2334 | case PROCESSOR_RIOS1: \ | |
fe7f5677 | 2335 | case PROCESSOR_PPC405: \ |
38c1f2d7 MM |
2336 | return (GET_CODE (XEXP (X, 1)) != CONST_INT \ |
2337 | ? COSTS_N_INSNS (5) \ | |
2338 | : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ | |
2339 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \ | |
3cb999d8 DE |
2340 | case PROCESSOR_RS64A: \ |
2341 | return (GET_CODE (XEXP (X, 1)) != CONST_INT \ | |
2342 | ? GET_MODE (XEXP (X, 1)) != DImode \ | |
2343 | ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \ | |
2344 | : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ | |
fe7f5677 | 2345 | ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12)); \ |
38c1f2d7 MM |
2346 | case PROCESSOR_RIOS2: \ |
2347 | case PROCESSOR_MPCCORE: \ | |
5a41b476 | 2348 | case PROCESSOR_PPC604e: \ |
38c1f2d7 MM |
2349 | return COSTS_N_INSNS (2); \ |
2350 | case PROCESSOR_PPC601: \ | |
2351 | return COSTS_N_INSNS (5); \ | |
2352 | case PROCESSOR_PPC603: \ | |
7960cfbb | 2353 | case PROCESSOR_PPC7400: \ |
bef84347 | 2354 | case PROCESSOR_PPC750: \ |
38c1f2d7 MM |
2355 | return (GET_CODE (XEXP (X, 1)) != CONST_INT \ |
2356 | ? COSTS_N_INSNS (5) \ | |
2357 | : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ | |
2358 | ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \ | |
fd3b43f2 DJ |
2359 | case PROCESSOR_PPC7450: \ |
2360 | return (GET_CODE (XEXP (X, 1)) != CONST_INT \ | |
2361 | ? COSTS_N_INSNS (4) \ | |
2362 | : COSTS_N_INSNS (3)); \ | |
38c1f2d7 MM |
2363 | case PROCESSOR_PPC403: \ |
2364 | case PROCESSOR_PPC604: \ | |
a23acaa6 | 2365 | case PROCESSOR_PPC8540: \ |
38c1f2d7 | 2366 | return COSTS_N_INSNS (4); \ |
3cb999d8 DE |
2367 | case PROCESSOR_PPC620: \ |
2368 | case PROCESSOR_PPC630: \ | |
309323c2 | 2369 | case PROCESSOR_POWER4: \ |
3cb999d8 DE |
2370 | return (GET_CODE (XEXP (X, 1)) != CONST_INT \ |
2371 | ? GET_MODE (XEXP (X, 1)) != DImode \ | |
fe7f5677 | 2372 | ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) \ |
3cb999d8 DE |
2373 | : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ |
2374 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \ | |
38c1f2d7 MM |
2375 | } \ |
2376 | case DIV: \ | |
2377 | case MOD: \ | |
2378 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2379 | && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \ | |
2380 | return COSTS_N_INSNS (2); \ | |
2381 | /* otherwise fall through to normal divide. */ \ | |
2382 | case UDIV: \ | |
2383 | case UMOD: \ | |
2384 | switch (rs6000_cpu) \ | |
2385 | { \ | |
2386 | case PROCESSOR_RIOS1: \ | |
2387 | return COSTS_N_INSNS (19); \ | |
2388 | case PROCESSOR_RIOS2: \ | |
2389 | return COSTS_N_INSNS (13); \ | |
3cb999d8 DE |
2390 | case PROCESSOR_RS64A: \ |
2391 | return (GET_MODE (XEXP (X, 1)) != DImode \ | |
2392 | ? COSTS_N_INSNS (65) \ | |
2393 | : COSTS_N_INSNS (67)); \ | |
38c1f2d7 MM |
2394 | case PROCESSOR_MPCCORE: \ |
2395 | return COSTS_N_INSNS (6); \ | |
2396 | case PROCESSOR_PPC403: \ | |
2397 | return COSTS_N_INSNS (33); \ | |
fe7f5677 DE |
2398 | case PROCESSOR_PPC405: \ |
2399 | return COSTS_N_INSNS (35); \ | |
38c1f2d7 MM |
2400 | case PROCESSOR_PPC601: \ |
2401 | return COSTS_N_INSNS (36); \ | |
2402 | case PROCESSOR_PPC603: \ | |
2403 | return COSTS_N_INSNS (37); \ | |
2404 | case PROCESSOR_PPC604: \ | |
5a41b476 | 2405 | case PROCESSOR_PPC604e: \ |
38c1f2d7 | 2406 | return COSTS_N_INSNS (20); \ |
3cb999d8 DE |
2407 | case PROCESSOR_PPC620: \ |
2408 | case PROCESSOR_PPC630: \ | |
309323c2 | 2409 | case PROCESSOR_POWER4: \ |
3cb999d8 DE |
2410 | return (GET_MODE (XEXP (X, 1)) != DImode \ |
2411 | ? COSTS_N_INSNS (21) \ | |
2412 | : COSTS_N_INSNS (37)); \ | |
bef84347 | 2413 | case PROCESSOR_PPC750: \ |
a3170dc6 | 2414 | case PROCESSOR_PPC8540: \ |
ed947a96 | 2415 | case PROCESSOR_PPC7400: \ |
bef84347 | 2416 | return COSTS_N_INSNS (19); \ |
ed947a96 DJ |
2417 | case PROCESSOR_PPC7450: \ |
2418 | return COSTS_N_INSNS (23); \ | |
38c1f2d7 MM |
2419 | } \ |
2420 | case FFS: \ | |
2421 | return COSTS_N_INSNS (4); \ | |
2422 | case MEM: \ | |
f045b2c9 RS |
2423 | /* MEM should be slightly more expensive than (plus (reg) (const)) */ \ |
2424 | return 5; | |
2425 | ||
2426 | /* Compute the cost of an address. This is meant to approximate the size | |
2427 | and/or execution delay of an insn using that address. If the cost is | |
2428 | approximated by the RTL complexity, including CONST_COSTS above, as | |
2429 | is usually the case for CISC machines, this macro should not be defined. | |
2430 | For aggressively RISCy machines, only one insn format is allowed, so | |
2431 | this macro should be a constant. The value of this macro only matters | |
2432 | for valid addresses. | |
2433 | ||
2434 | For the RS/6000, everything is cost 0. */ | |
2435 | ||
2436 | #define ADDRESS_COST(RTX) 0 | |
2437 | ||
2438 | /* Adjust the length of an INSN. LENGTH is the currently-computed length and | |
2439 | should be adjusted to reflect any required changes. This macro is used when | |
2440 | there is some systematic length adjustment required that would be difficult | |
2441 | to express in the length attribute. */ | |
2442 | ||
2443 | /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
2444 | ||
39a10a29 GK |
2445 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a |
2446 | COMPARE, return the mode to be used for the comparison. For | |
2447 | floating-point, CCFPmode should be used. CCUNSmode should be used | |
2448 | for unsigned comparisons. CCEQmode should be used when we are | |
2449 | doing an inequality comparison on the result of a | |
2450 | comparison. CCmode should be used in all other cases. */ | |
c5defebb | 2451 | |
b565a316 | 2452 | #define SELECT_CC_MODE(OP,X,Y) \ |
f045b2c9 | 2453 | (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \ |
c5defebb RK |
2454 | : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ |
2455 | : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \ | |
2456 | ? CCEQmode : CCmode)) | |
f045b2c9 RS |
2457 | |
2458 | /* Define the information needed to generate branch and scc insns. This is | |
2459 | stored from the compare operation. Note that we can't use "rtx" here | |
2460 | since it hasn't been defined! */ | |
2461 | ||
e2500fed GK |
2462 | extern GTY(()) rtx rs6000_compare_op0; |
2463 | extern GTY(()) rtx rs6000_compare_op1; | |
f045b2c9 | 2464 | extern int rs6000_compare_fp_p; |
f045b2c9 RS |
2465 | \f |
2466 | /* Control the assembler format that we output. */ | |
2467 | ||
1b279f39 DE |
2468 | /* A C string constant describing how to begin a comment in the target |
2469 | assembler language. The compiler assumes that the comment will end at | |
2470 | the end of the line. */ | |
2471 | #define ASM_COMMENT_START " #" | |
6b67933e | 2472 | |
fdaff8ba RS |
2473 | /* Implicit library calls should use memcpy, not bcopy, etc. */ |
2474 | ||
2475 | #define TARGET_MEM_FUNCTIONS | |
2476 | ||
38c1f2d7 MM |
2477 | /* Flag to say the TOC is initialized */ |
2478 | extern int toc_initialized; | |
2479 | ||
f045b2c9 RS |
2480 | /* Macro to output a special constant pool entry. Go to WIN if we output |
2481 | it. Otherwise, it is written the usual way. | |
2482 | ||
2483 | On the RS/6000, toc entries are handled this way. */ | |
2484 | ||
a9098fd0 GK |
2485 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ |
2486 | { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
2487 | { \ | |
2488 | output_toc (FILE, X, LABELNO, MODE); \ | |
2489 | goto WIN; \ | |
2490 | } \ | |
f045b2c9 RS |
2491 | } |
2492 | ||
ebd97b96 DE |
2493 | #ifdef HAVE_GAS_WEAK |
2494 | #define RS6000_WEAK 1 | |
2495 | #else | |
2496 | #define RS6000_WEAK 0 | |
2497 | #endif | |
290ad355 | 2498 | |
79c4e63f AM |
2499 | #if RS6000_WEAK |
2500 | /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
2501 | #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ | |
2502 | do \ | |
2503 | { \ | |
2504 | fputs ("\t.weak\t", (FILE)); \ | |
cbaaba19 | 2505 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f AM |
2506 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ |
2507 | && DEFAULT_ABI == ABI_AIX) \ | |
2508 | { \ | |
cbaaba19 DE |
2509 | if (TARGET_XCOFF) \ |
2510 | fputs ("[DS]", (FILE)); \ | |
ca734b39 | 2511 | fputs ("\n\t.weak\t.", (FILE)); \ |
cbaaba19 | 2512 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f AM |
2513 | } \ |
2514 | fputc ('\n', (FILE)); \ | |
2515 | if (VAL) \ | |
2516 | { \ | |
2517 | ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ | |
2518 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
2519 | && DEFAULT_ABI == ABI_AIX) \ | |
2520 | { \ | |
2521 | fputs ("\t.set\t.", (FILE)); \ | |
cbaaba19 | 2522 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f | 2523 | fputs (",.", (FILE)); \ |
cbaaba19 | 2524 | RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ |
79c4e63f AM |
2525 | fputc ('\n', (FILE)); \ |
2526 | } \ | |
2527 | } \ | |
2528 | } \ | |
2529 | while (0) | |
2530 | #endif | |
2531 | ||
2532 | /* This implements the `alias' attribute. */ | |
2533 | #undef ASM_OUTPUT_DEF_FROM_DECLS | |
2534 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
2535 | do \ | |
2536 | { \ | |
2537 | const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
2538 | const char *name = IDENTIFIER_POINTER (TARGET); \ | |
2539 | if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
2540 | && DEFAULT_ABI == ABI_AIX) \ | |
2541 | { \ | |
2542 | if (TREE_PUBLIC (DECL)) \ | |
2543 | { \ | |
2544 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
2545 | { \ | |
2546 | fputs ("\t.globl\t.", FILE); \ | |
cbaaba19 | 2547 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
2548 | putc ('\n', FILE); \ |
2549 | } \ | |
2550 | } \ | |
2551 | else if (TARGET_XCOFF) \ | |
2552 | { \ | |
2553 | fputs ("\t.lglobl\t.", FILE); \ | |
cbaaba19 | 2554 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
2555 | putc ('\n', FILE); \ |
2556 | } \ | |
2557 | fputs ("\t.set\t.", FILE); \ | |
cbaaba19 | 2558 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f | 2559 | fputs (",.", FILE); \ |
cbaaba19 | 2560 | RS6000_OUTPUT_BASENAME (FILE, name); \ |
79c4e63f AM |
2561 | fputc ('\n', FILE); \ |
2562 | } \ | |
2563 | ASM_OUTPUT_DEF (FILE, alias, name); \ | |
2564 | } \ | |
2565 | while (0) | |
290ad355 | 2566 | |
f045b2c9 RS |
2567 | /* Output to assembler file text saying following lines |
2568 | may contain character constants, extra white space, comments, etc. */ | |
2569 | ||
2570 | #define ASM_APP_ON "" | |
2571 | ||
2572 | /* Output to assembler file text saying following lines | |
2573 | no longer contain unusual constructs. */ | |
2574 | ||
2575 | #define ASM_APP_OFF "" | |
2576 | ||
f045b2c9 RS |
2577 | /* How to refer to registers in assembler output. |
2578 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2579 | ||
82e41834 | 2580 | extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ |
c81bebd7 MM |
2581 | |
2582 | #define REGISTER_NAMES \ | |
2583 | { \ | |
2584 | &rs6000_reg_names[ 0][0], /* r0 */ \ | |
2585 | &rs6000_reg_names[ 1][0], /* r1 */ \ | |
2586 | &rs6000_reg_names[ 2][0], /* r2 */ \ | |
2587 | &rs6000_reg_names[ 3][0], /* r3 */ \ | |
2588 | &rs6000_reg_names[ 4][0], /* r4 */ \ | |
2589 | &rs6000_reg_names[ 5][0], /* r5 */ \ | |
2590 | &rs6000_reg_names[ 6][0], /* r6 */ \ | |
2591 | &rs6000_reg_names[ 7][0], /* r7 */ \ | |
2592 | &rs6000_reg_names[ 8][0], /* r8 */ \ | |
2593 | &rs6000_reg_names[ 9][0], /* r9 */ \ | |
2594 | &rs6000_reg_names[10][0], /* r10 */ \ | |
2595 | &rs6000_reg_names[11][0], /* r11 */ \ | |
2596 | &rs6000_reg_names[12][0], /* r12 */ \ | |
2597 | &rs6000_reg_names[13][0], /* r13 */ \ | |
2598 | &rs6000_reg_names[14][0], /* r14 */ \ | |
2599 | &rs6000_reg_names[15][0], /* r15 */ \ | |
2600 | &rs6000_reg_names[16][0], /* r16 */ \ | |
2601 | &rs6000_reg_names[17][0], /* r17 */ \ | |
2602 | &rs6000_reg_names[18][0], /* r18 */ \ | |
2603 | &rs6000_reg_names[19][0], /* r19 */ \ | |
2604 | &rs6000_reg_names[20][0], /* r20 */ \ | |
2605 | &rs6000_reg_names[21][0], /* r21 */ \ | |
2606 | &rs6000_reg_names[22][0], /* r22 */ \ | |
2607 | &rs6000_reg_names[23][0], /* r23 */ \ | |
2608 | &rs6000_reg_names[24][0], /* r24 */ \ | |
2609 | &rs6000_reg_names[25][0], /* r25 */ \ | |
2610 | &rs6000_reg_names[26][0], /* r26 */ \ | |
2611 | &rs6000_reg_names[27][0], /* r27 */ \ | |
2612 | &rs6000_reg_names[28][0], /* r28 */ \ | |
2613 | &rs6000_reg_names[29][0], /* r29 */ \ | |
2614 | &rs6000_reg_names[30][0], /* r30 */ \ | |
2615 | &rs6000_reg_names[31][0], /* r31 */ \ | |
2616 | \ | |
2617 | &rs6000_reg_names[32][0], /* fr0 */ \ | |
2618 | &rs6000_reg_names[33][0], /* fr1 */ \ | |
2619 | &rs6000_reg_names[34][0], /* fr2 */ \ | |
2620 | &rs6000_reg_names[35][0], /* fr3 */ \ | |
2621 | &rs6000_reg_names[36][0], /* fr4 */ \ | |
2622 | &rs6000_reg_names[37][0], /* fr5 */ \ | |
2623 | &rs6000_reg_names[38][0], /* fr6 */ \ | |
2624 | &rs6000_reg_names[39][0], /* fr7 */ \ | |
2625 | &rs6000_reg_names[40][0], /* fr8 */ \ | |
2626 | &rs6000_reg_names[41][0], /* fr9 */ \ | |
2627 | &rs6000_reg_names[42][0], /* fr10 */ \ | |
2628 | &rs6000_reg_names[43][0], /* fr11 */ \ | |
2629 | &rs6000_reg_names[44][0], /* fr12 */ \ | |
2630 | &rs6000_reg_names[45][0], /* fr13 */ \ | |
2631 | &rs6000_reg_names[46][0], /* fr14 */ \ | |
2632 | &rs6000_reg_names[47][0], /* fr15 */ \ | |
2633 | &rs6000_reg_names[48][0], /* fr16 */ \ | |
2634 | &rs6000_reg_names[49][0], /* fr17 */ \ | |
2635 | &rs6000_reg_names[50][0], /* fr18 */ \ | |
2636 | &rs6000_reg_names[51][0], /* fr19 */ \ | |
2637 | &rs6000_reg_names[52][0], /* fr20 */ \ | |
2638 | &rs6000_reg_names[53][0], /* fr21 */ \ | |
2639 | &rs6000_reg_names[54][0], /* fr22 */ \ | |
2640 | &rs6000_reg_names[55][0], /* fr23 */ \ | |
2641 | &rs6000_reg_names[56][0], /* fr24 */ \ | |
2642 | &rs6000_reg_names[57][0], /* fr25 */ \ | |
2643 | &rs6000_reg_names[58][0], /* fr26 */ \ | |
2644 | &rs6000_reg_names[59][0], /* fr27 */ \ | |
2645 | &rs6000_reg_names[60][0], /* fr28 */ \ | |
2646 | &rs6000_reg_names[61][0], /* fr29 */ \ | |
2647 | &rs6000_reg_names[62][0], /* fr30 */ \ | |
2648 | &rs6000_reg_names[63][0], /* fr31 */ \ | |
2649 | \ | |
2650 | &rs6000_reg_names[64][0], /* mq */ \ | |
2651 | &rs6000_reg_names[65][0], /* lr */ \ | |
2652 | &rs6000_reg_names[66][0], /* ctr */ \ | |
2653 | &rs6000_reg_names[67][0], /* ap */ \ | |
2654 | \ | |
2655 | &rs6000_reg_names[68][0], /* cr0 */ \ | |
2656 | &rs6000_reg_names[69][0], /* cr1 */ \ | |
2657 | &rs6000_reg_names[70][0], /* cr2 */ \ | |
2658 | &rs6000_reg_names[71][0], /* cr3 */ \ | |
2659 | &rs6000_reg_names[72][0], /* cr4 */ \ | |
2660 | &rs6000_reg_names[73][0], /* cr5 */ \ | |
2661 | &rs6000_reg_names[74][0], /* cr6 */ \ | |
2662 | &rs6000_reg_names[75][0], /* cr7 */ \ | |
802a0058 | 2663 | \ |
9ebbca7d | 2664 | &rs6000_reg_names[76][0], /* xer */ \ |
0ac081f6 AH |
2665 | \ |
2666 | &rs6000_reg_names[77][0], /* v0 */ \ | |
2667 | &rs6000_reg_names[78][0], /* v1 */ \ | |
2668 | &rs6000_reg_names[79][0], /* v2 */ \ | |
2669 | &rs6000_reg_names[80][0], /* v3 */ \ | |
2670 | &rs6000_reg_names[81][0], /* v4 */ \ | |
2671 | &rs6000_reg_names[82][0], /* v5 */ \ | |
2672 | &rs6000_reg_names[83][0], /* v6 */ \ | |
2673 | &rs6000_reg_names[84][0], /* v7 */ \ | |
2674 | &rs6000_reg_names[85][0], /* v8 */ \ | |
2675 | &rs6000_reg_names[86][0], /* v9 */ \ | |
2676 | &rs6000_reg_names[87][0], /* v10 */ \ | |
2677 | &rs6000_reg_names[88][0], /* v11 */ \ | |
2678 | &rs6000_reg_names[89][0], /* v12 */ \ | |
2679 | &rs6000_reg_names[90][0], /* v13 */ \ | |
2680 | &rs6000_reg_names[91][0], /* v14 */ \ | |
2681 | &rs6000_reg_names[92][0], /* v15 */ \ | |
2682 | &rs6000_reg_names[93][0], /* v16 */ \ | |
2683 | &rs6000_reg_names[94][0], /* v17 */ \ | |
2684 | &rs6000_reg_names[95][0], /* v18 */ \ | |
2685 | &rs6000_reg_names[96][0], /* v19 */ \ | |
2686 | &rs6000_reg_names[97][0], /* v20 */ \ | |
2687 | &rs6000_reg_names[98][0], /* v21 */ \ | |
2688 | &rs6000_reg_names[99][0], /* v22 */ \ | |
2689 | &rs6000_reg_names[100][0], /* v23 */ \ | |
2690 | &rs6000_reg_names[101][0], /* v24 */ \ | |
2691 | &rs6000_reg_names[102][0], /* v25 */ \ | |
2692 | &rs6000_reg_names[103][0], /* v26 */ \ | |
2693 | &rs6000_reg_names[104][0], /* v27 */ \ | |
2694 | &rs6000_reg_names[105][0], /* v28 */ \ | |
2695 | &rs6000_reg_names[106][0], /* v29 */ \ | |
2696 | &rs6000_reg_names[107][0], /* v30 */ \ | |
2697 | &rs6000_reg_names[108][0], /* v31 */ \ | |
2698 | &rs6000_reg_names[109][0], /* vrsave */ \ | |
5f004351 | 2699 | &rs6000_reg_names[110][0], /* vscr */ \ |
a3170dc6 AH |
2700 | &rs6000_reg_names[111][0], /* spe_acc */ \ |
2701 | &rs6000_reg_names[112][0], /* spefscr */ \ | |
c81bebd7 MM |
2702 | } |
2703 | ||
2704 | /* print-rtl can't handle the above REGISTER_NAMES, so define the | |
2705 | following for it. Switch to use the alternate names since | |
2706 | they are more mnemonic. */ | |
2707 | ||
2708 | #define DEBUG_REGISTER_NAMES \ | |
2709 | { \ | |
802a0058 MM |
2710 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ |
2711 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
2712 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ | |
2713 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ | |
2714 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
2715 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
2716 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ | |
2717 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \ | |
2718 | "mq", "lr", "ctr", "ap", \ | |
2719 | "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \ | |
0ac081f6 AH |
2720 | "xer", \ |
2721 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ | |
2722 | "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ | |
2723 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ | |
2724 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ | |
5f004351 | 2725 | "vrsave", "vscr" \ |
a3170dc6 | 2726 | , "spe_acc", "spefscr" \ |
c81bebd7 | 2727 | } |
f045b2c9 RS |
2728 | |
2729 | /* Table of additional register names to use in user input. */ | |
2730 | ||
2731 | #define ADDITIONAL_REGISTER_NAMES \ | |
c4d38ccb MM |
2732 | {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ |
2733 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2734 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2735 | {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2736 | {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2737 | {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2738 | {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2739 | {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2740 | {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2741 | {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2742 | {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2743 | {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2744 | {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2745 | {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2746 | {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2747 | {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
0ac081f6 AH |
2748 | {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ |
2749 | {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
2750 | {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
2751 | {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
2752 | {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
2753 | {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
2754 | {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
2755 | {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
5f004351 | 2756 | {"vrsave", 109}, {"vscr", 110}, \ |
a3170dc6 | 2757 | {"spe_acc", 111}, {"spefscr", 112}, \ |
c4d38ccb MM |
2758 | /* no additional names for: mq, lr, ctr, ap */ \ |
2759 | {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ | |
2760 | {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
2761 | {"cc", 68}, {"sp", 1}, {"toc", 2} } | |
f045b2c9 | 2762 | |
0da40b09 RK |
2763 | /* Text to write out after a CALL that may be replaced by glue code by |
2764 | the loader. This depends on the AIX version. */ | |
2765 | #define RS6000_CALL_GLUE "cror 31,31,31" | |
11117bb9 | 2766 | |
f045b2c9 RS |
2767 | /* This is how to output an element of a case-vector that is relative. */ |
2768 | ||
e1565e65 | 2769 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3daf36a4 | 2770 | do { char buf[100]; \ |
e1565e65 | 2771 | fputs ("\t.long ", FILE); \ |
3daf36a4 ILT |
2772 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ |
2773 | assemble_name (FILE, buf); \ | |
19d2d16f | 2774 | putc ('-', FILE); \ |
3daf36a4 ILT |
2775 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ |
2776 | assemble_name (FILE, buf); \ | |
19d2d16f | 2777 | putc ('\n', FILE); \ |
3daf36a4 | 2778 | } while (0) |
f045b2c9 RS |
2779 | |
2780 | /* This is how to output an assembler line | |
2781 | that says to advance the location counter | |
2782 | to a multiple of 2**LOG bytes. */ | |
2783 | ||
2784 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2785 | if ((LOG) != 0) \ | |
2786 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
2787 | ||
9ebbca7d GK |
2788 | /* Pick up the return address upon entry to a procedure. Used for |
2789 | dwarf2 unwind information. This also enables the table driven | |
2790 | mechanism. */ | |
2791 | ||
2792 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
8034da37 | 2793 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM) |
9ebbca7d | 2794 | |
83720594 RH |
2795 | /* Describe how we implement __builtin_eh_return. */ |
2796 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2797 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2798 | ||
f045b2c9 RS |
2799 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2800 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2801 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2802 | ||
2803 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2804 | ||
2805 | /* Define which CODE values are valid. */ | |
2806 | ||
c81bebd7 | 2807 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
6fa3f289 | 2808 | ((CODE) == '.') |
f045b2c9 RS |
2809 | |
2810 | /* Print a memory address as an operand to reference that memory location. */ | |
2811 | ||
2812 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2813 | ||
2814 | /* Define the codes that are matched by predicates in rs6000.c. */ | |
2815 | ||
39a10a29 | 2816 | #define PREDICATE_CODES \ |
a65c591c | 2817 | {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ |
df15fbc7 | 2818 | LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \ |
a65c591c DE |
2819 | {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ |
2820 | LABEL_REF, SUBREG, REG, MEM}}, \ | |
39a10a29 GK |
2821 | {"short_cint_operand", {CONST_INT}}, \ |
2822 | {"u_short_cint_operand", {CONST_INT}}, \ | |
2823 | {"non_short_cint_operand", {CONST_INT}}, \ | |
2bfcf297 | 2824 | {"exact_log2_cint_operand", {CONST_INT}}, \ |
39a10a29 GK |
2825 | {"gpc_reg_operand", {SUBREG, REG}}, \ |
2826 | {"cc_reg_operand", {SUBREG, REG}}, \ | |
2827 | {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \ | |
2828 | {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \ | |
2829 | {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \ | |
768070a0 | 2830 | {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \ |
39a10a29 GK |
2831 | {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \ |
2832 | {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ | |
2833 | {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \ | |
2bfcf297 DB |
2834 | {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \ |
2835 | {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \ | |
1d328b19 | 2836 | {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ |
39a10a29 GK |
2837 | {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ |
2838 | {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \ | |
2839 | {"easy_fp_constant", {CONST_DOUBLE}}, \ | |
50a0b056 | 2840 | {"zero_fp_constant", {CONST_DOUBLE}}, \ |
39a10a29 GK |
2841 | {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \ |
2842 | {"lwa_operand", {SUBREG, MEM, REG}}, \ | |
2843 | {"volatile_mem_operand", {MEM}}, \ | |
2844 | {"offsettable_mem_operand", {MEM}}, \ | |
2845 | {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \ | |
2846 | {"add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2847 | {"non_add_cint_operand", {CONST_INT}}, \ | |
2848 | {"and_operand", {SUBREG, REG, CONST_INT}}, \ | |
2849 | {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
0ba1b2ff | 2850 | {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \ |
39a10a29 GK |
2851 | {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ |
2852 | {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \ | |
2853 | {"mask_operand", {CONST_INT}}, \ | |
0ba1b2ff AM |
2854 | {"mask_operand_wrap", {CONST_INT}}, \ |
2855 | {"mask64_operand", {CONST_INT}}, \ | |
2856 | {"mask64_2_operand", {CONST_INT}}, \ | |
39a10a29 GK |
2857 | {"count_register_operand", {REG}}, \ |
2858 | {"xer_operand", {REG}}, \ | |
cc4d5fec | 2859 | {"symbol_ref_operand", {SYMBOL_REF}}, \ |
39a10a29 GK |
2860 | {"call_operand", {SYMBOL_REF, REG}}, \ |
2861 | {"current_file_function_operand", {SYMBOL_REF}}, \ | |
2862 | {"input_operand", {SUBREG, MEM, REG, CONST_INT, \ | |
2863 | CONST_DOUBLE, SYMBOL_REF}}, \ | |
2864 | {"load_multiple_operation", {PARALLEL}}, \ | |
2865 | {"store_multiple_operation", {PARALLEL}}, \ | |
00b960c7 | 2866 | {"vrsave_operation", {PARALLEL}}, \ |
39a10a29 GK |
2867 | {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \ |
2868 | GT, LEU, LTU, GEU, GTU, \ | |
2869 | UNORDERED, ORDERED, \ | |
2870 | UNGE, UNLE }}, \ | |
2871 | {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \ | |
2872 | UNORDERED }}, \ | |
2873 | {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \ | |
2874 | GT, LEU, LTU, GEU, GTU, \ | |
2875 | UNORDERED, ORDERED, \ | |
2876 | UNGE, UNLE }}, \ | |
2877 | {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \ | |
2878 | GT, LEU, LTU, GEU, GTU}}, \ | |
2879 | {"boolean_operator", {AND, IOR, XOR}}, \ | |
50a0b056 | 2880 | {"boolean_or_operator", {IOR, XOR}}, \ |
0ec4e2a8 | 2881 | {"altivec_register_operand", {REG}}, \ |
50a0b056 | 2882 | {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}}, |
75814ad4 | 2883 | |
b6c9286a MM |
2884 | /* uncomment for disabling the corresponding default options */ |
2885 | /* #define MACHINE_no_sched_interblock */ | |
2886 | /* #define MACHINE_no_sched_speculative */ | |
2887 | /* #define MACHINE_no_sched_speculative_load */ | |
2888 | ||
766a866c MM |
2889 | /* General flags. */ |
2890 | extern int flag_pic; | |
354b734b MM |
2891 | extern int optimize; |
2892 | extern int flag_expensive_optimizations; | |
a7df97e6 | 2893 | extern int frame_pointer_needed; |
0ac081f6 AH |
2894 | |
2895 | enum rs6000_builtins | |
2896 | { | |
2897 | /* AltiVec builtins. */ | |
f18c054f DB |
2898 | ALTIVEC_BUILTIN_ST_INTERNAL_4si, |
2899 | ALTIVEC_BUILTIN_LD_INTERNAL_4si, | |
2900 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi, | |
2901 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi, | |
2902 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi, | |
2903 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi, | |
2904 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf, | |
2905 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf, | |
0ac081f6 AH |
2906 | ALTIVEC_BUILTIN_VADDUBM, |
2907 | ALTIVEC_BUILTIN_VADDUHM, | |
2908 | ALTIVEC_BUILTIN_VADDUWM, | |
2909 | ALTIVEC_BUILTIN_VADDFP, | |
2910 | ALTIVEC_BUILTIN_VADDCUW, | |
2911 | ALTIVEC_BUILTIN_VADDUBS, | |
2912 | ALTIVEC_BUILTIN_VADDSBS, | |
2913 | ALTIVEC_BUILTIN_VADDUHS, | |
2914 | ALTIVEC_BUILTIN_VADDSHS, | |
2915 | ALTIVEC_BUILTIN_VADDUWS, | |
2916 | ALTIVEC_BUILTIN_VADDSWS, | |
2917 | ALTIVEC_BUILTIN_VAND, | |
2918 | ALTIVEC_BUILTIN_VANDC, | |
2919 | ALTIVEC_BUILTIN_VAVGUB, | |
2920 | ALTIVEC_BUILTIN_VAVGSB, | |
2921 | ALTIVEC_BUILTIN_VAVGUH, | |
2922 | ALTIVEC_BUILTIN_VAVGSH, | |
2923 | ALTIVEC_BUILTIN_VAVGUW, | |
2924 | ALTIVEC_BUILTIN_VAVGSW, | |
617e0e1d DB |
2925 | ALTIVEC_BUILTIN_VCFUX, |
2926 | ALTIVEC_BUILTIN_VCFSX, | |
2927 | ALTIVEC_BUILTIN_VCTSXS, | |
2928 | ALTIVEC_BUILTIN_VCTUXS, | |
0ac081f6 AH |
2929 | ALTIVEC_BUILTIN_VCMPBFP, |
2930 | ALTIVEC_BUILTIN_VCMPEQUB, | |
2931 | ALTIVEC_BUILTIN_VCMPEQUH, | |
2932 | ALTIVEC_BUILTIN_VCMPEQUW, | |
2933 | ALTIVEC_BUILTIN_VCMPEQFP, | |
2934 | ALTIVEC_BUILTIN_VCMPGEFP, | |
2935 | ALTIVEC_BUILTIN_VCMPGTUB, | |
2936 | ALTIVEC_BUILTIN_VCMPGTSB, | |
2937 | ALTIVEC_BUILTIN_VCMPGTUH, | |
2938 | ALTIVEC_BUILTIN_VCMPGTSH, | |
2939 | ALTIVEC_BUILTIN_VCMPGTUW, | |
2940 | ALTIVEC_BUILTIN_VCMPGTSW, | |
2941 | ALTIVEC_BUILTIN_VCMPGTFP, | |
617e0e1d DB |
2942 | ALTIVEC_BUILTIN_VEXPTEFP, |
2943 | ALTIVEC_BUILTIN_VLOGEFP, | |
2212663f | 2944 | ALTIVEC_BUILTIN_VMADDFP, |
0ac081f6 AH |
2945 | ALTIVEC_BUILTIN_VMAXUB, |
2946 | ALTIVEC_BUILTIN_VMAXSB, | |
2947 | ALTIVEC_BUILTIN_VMAXUH, | |
2948 | ALTIVEC_BUILTIN_VMAXSH, | |
2949 | ALTIVEC_BUILTIN_VMAXUW, | |
2950 | ALTIVEC_BUILTIN_VMAXSW, | |
2951 | ALTIVEC_BUILTIN_VMAXFP, | |
2212663f DB |
2952 | ALTIVEC_BUILTIN_VMHADDSHS, |
2953 | ALTIVEC_BUILTIN_VMHRADDSHS, | |
2954 | ALTIVEC_BUILTIN_VMLADDUHM, | |
0ac081f6 AH |
2955 | ALTIVEC_BUILTIN_VMRGHB, |
2956 | ALTIVEC_BUILTIN_VMRGHH, | |
2957 | ALTIVEC_BUILTIN_VMRGHW, | |
2958 | ALTIVEC_BUILTIN_VMRGLB, | |
2959 | ALTIVEC_BUILTIN_VMRGLH, | |
2960 | ALTIVEC_BUILTIN_VMRGLW, | |
2212663f DB |
2961 | ALTIVEC_BUILTIN_VMSUMUBM, |
2962 | ALTIVEC_BUILTIN_VMSUMMBM, | |
2963 | ALTIVEC_BUILTIN_VMSUMUHM, | |
2964 | ALTIVEC_BUILTIN_VMSUMSHM, | |
2965 | ALTIVEC_BUILTIN_VMSUMUHS, | |
2966 | ALTIVEC_BUILTIN_VMSUMSHS, | |
0ac081f6 AH |
2967 | ALTIVEC_BUILTIN_VMINUB, |
2968 | ALTIVEC_BUILTIN_VMINSB, | |
2969 | ALTIVEC_BUILTIN_VMINUH, | |
2970 | ALTIVEC_BUILTIN_VMINSH, | |
2971 | ALTIVEC_BUILTIN_VMINUW, | |
2972 | ALTIVEC_BUILTIN_VMINSW, | |
2973 | ALTIVEC_BUILTIN_VMINFP, | |
2974 | ALTIVEC_BUILTIN_VMULEUB, | |
2975 | ALTIVEC_BUILTIN_VMULESB, | |
2976 | ALTIVEC_BUILTIN_VMULEUH, | |
2977 | ALTIVEC_BUILTIN_VMULESH, | |
2978 | ALTIVEC_BUILTIN_VMULOUB, | |
2979 | ALTIVEC_BUILTIN_VMULOSB, | |
2980 | ALTIVEC_BUILTIN_VMULOUH, | |
2981 | ALTIVEC_BUILTIN_VMULOSH, | |
2212663f | 2982 | ALTIVEC_BUILTIN_VNMSUBFP, |
0ac081f6 AH |
2983 | ALTIVEC_BUILTIN_VNOR, |
2984 | ALTIVEC_BUILTIN_VOR, | |
617e0e1d DB |
2985 | ALTIVEC_BUILTIN_VSEL_4SI, |
2986 | ALTIVEC_BUILTIN_VSEL_4SF, | |
2987 | ALTIVEC_BUILTIN_VSEL_8HI, | |
2988 | ALTIVEC_BUILTIN_VSEL_16QI, | |
2212663f DB |
2989 | ALTIVEC_BUILTIN_VPERM_4SI, |
2990 | ALTIVEC_BUILTIN_VPERM_4SF, | |
2991 | ALTIVEC_BUILTIN_VPERM_8HI, | |
2992 | ALTIVEC_BUILTIN_VPERM_16QI, | |
0ac081f6 AH |
2993 | ALTIVEC_BUILTIN_VPKUHUM, |
2994 | ALTIVEC_BUILTIN_VPKUWUM, | |
2995 | ALTIVEC_BUILTIN_VPKPX, | |
2996 | ALTIVEC_BUILTIN_VPKUHSS, | |
2997 | ALTIVEC_BUILTIN_VPKSHSS, | |
2998 | ALTIVEC_BUILTIN_VPKUWSS, | |
2999 | ALTIVEC_BUILTIN_VPKSWSS, | |
3000 | ALTIVEC_BUILTIN_VPKUHUS, | |
3001 | ALTIVEC_BUILTIN_VPKSHUS, | |
3002 | ALTIVEC_BUILTIN_VPKUWUS, | |
3003 | ALTIVEC_BUILTIN_VPKSWUS, | |
617e0e1d DB |
3004 | ALTIVEC_BUILTIN_VREFP, |
3005 | ALTIVEC_BUILTIN_VRFIM, | |
3006 | ALTIVEC_BUILTIN_VRFIN, | |
3007 | ALTIVEC_BUILTIN_VRFIP, | |
3008 | ALTIVEC_BUILTIN_VRFIZ, | |
0ac081f6 AH |
3009 | ALTIVEC_BUILTIN_VRLB, |
3010 | ALTIVEC_BUILTIN_VRLH, | |
3011 | ALTIVEC_BUILTIN_VRLW, | |
617e0e1d | 3012 | ALTIVEC_BUILTIN_VRSQRTEFP, |
0ac081f6 AH |
3013 | ALTIVEC_BUILTIN_VSLB, |
3014 | ALTIVEC_BUILTIN_VSLH, | |
3015 | ALTIVEC_BUILTIN_VSLW, | |
3016 | ALTIVEC_BUILTIN_VSL, | |
3017 | ALTIVEC_BUILTIN_VSLO, | |
2212663f DB |
3018 | ALTIVEC_BUILTIN_VSPLTB, |
3019 | ALTIVEC_BUILTIN_VSPLTH, | |
3020 | ALTIVEC_BUILTIN_VSPLTW, | |
3021 | ALTIVEC_BUILTIN_VSPLTISB, | |
3022 | ALTIVEC_BUILTIN_VSPLTISH, | |
3023 | ALTIVEC_BUILTIN_VSPLTISW, | |
0ac081f6 | 3024 | ALTIVEC_BUILTIN_VSRB, |
f18c054f DB |
3025 | ALTIVEC_BUILTIN_VSRH, |
3026 | ALTIVEC_BUILTIN_VSRW, | |
0ac081f6 AH |
3027 | ALTIVEC_BUILTIN_VSRAB, |
3028 | ALTIVEC_BUILTIN_VSRAH, | |
3029 | ALTIVEC_BUILTIN_VSRAW, | |
3030 | ALTIVEC_BUILTIN_VSR, | |
3031 | ALTIVEC_BUILTIN_VSRO, | |
3032 | ALTIVEC_BUILTIN_VSUBUBM, | |
3033 | ALTIVEC_BUILTIN_VSUBUHM, | |
3034 | ALTIVEC_BUILTIN_VSUBUWM, | |
3035 | ALTIVEC_BUILTIN_VSUBFP, | |
3036 | ALTIVEC_BUILTIN_VSUBCUW, | |
3037 | ALTIVEC_BUILTIN_VSUBUBS, | |
3038 | ALTIVEC_BUILTIN_VSUBSBS, | |
3039 | ALTIVEC_BUILTIN_VSUBUHS, | |
3040 | ALTIVEC_BUILTIN_VSUBSHS, | |
3041 | ALTIVEC_BUILTIN_VSUBUWS, | |
3042 | ALTIVEC_BUILTIN_VSUBSWS, | |
3043 | ALTIVEC_BUILTIN_VSUM4UBS, | |
3044 | ALTIVEC_BUILTIN_VSUM4SBS, | |
3045 | ALTIVEC_BUILTIN_VSUM4SHS, | |
3046 | ALTIVEC_BUILTIN_VSUM2SWS, | |
3047 | ALTIVEC_BUILTIN_VSUMSWS, | |
24408032 AH |
3048 | ALTIVEC_BUILTIN_VXOR, |
3049 | ALTIVEC_BUILTIN_VSLDOI_16QI, | |
3050 | ALTIVEC_BUILTIN_VSLDOI_8HI, | |
3051 | ALTIVEC_BUILTIN_VSLDOI_4SI, | |
20e26713 AH |
3052 | ALTIVEC_BUILTIN_VSLDOI_4SF, |
3053 | ALTIVEC_BUILTIN_VUPKHSB, | |
3054 | ALTIVEC_BUILTIN_VUPKHPX, | |
3055 | ALTIVEC_BUILTIN_VUPKHSH, | |
3056 | ALTIVEC_BUILTIN_VUPKLSB, | |
3057 | ALTIVEC_BUILTIN_VUPKLPX, | |
fa066a23 | 3058 | ALTIVEC_BUILTIN_VUPKLSH, |
95385cbb AH |
3059 | ALTIVEC_BUILTIN_MTVSCR, |
3060 | ALTIVEC_BUILTIN_MFVSCR, | |
3061 | ALTIVEC_BUILTIN_DSSALL, | |
3062 | ALTIVEC_BUILTIN_DSS, | |
3063 | ALTIVEC_BUILTIN_LVSL, | |
3064 | ALTIVEC_BUILTIN_LVSR, | |
3065 | ALTIVEC_BUILTIN_DSTT, | |
3066 | ALTIVEC_BUILTIN_DSTST, | |
3067 | ALTIVEC_BUILTIN_DSTSTT, | |
6525c0e7 AH |
3068 | ALTIVEC_BUILTIN_DST, |
3069 | ALTIVEC_BUILTIN_LVEBX, | |
3070 | ALTIVEC_BUILTIN_LVEHX, | |
3071 | ALTIVEC_BUILTIN_LVEWX, | |
3072 | ALTIVEC_BUILTIN_LVXL, | |
3073 | ALTIVEC_BUILTIN_LVX, | |
3074 | ALTIVEC_BUILTIN_STVX, | |
3075 | ALTIVEC_BUILTIN_STVEBX, | |
3076 | ALTIVEC_BUILTIN_STVEHX, | |
3077 | ALTIVEC_BUILTIN_STVEWX, | |
ae4b4a02 AH |
3078 | ALTIVEC_BUILTIN_STVXL, |
3079 | ALTIVEC_BUILTIN_VCMPBFP_P, | |
3080 | ALTIVEC_BUILTIN_VCMPEQFP_P, | |
3081 | ALTIVEC_BUILTIN_VCMPEQUB_P, | |
3082 | ALTIVEC_BUILTIN_VCMPEQUH_P, | |
3083 | ALTIVEC_BUILTIN_VCMPEQUW_P, | |
3084 | ALTIVEC_BUILTIN_VCMPGEFP_P, | |
3085 | ALTIVEC_BUILTIN_VCMPGTFP_P, | |
3086 | ALTIVEC_BUILTIN_VCMPGTSB_P, | |
3087 | ALTIVEC_BUILTIN_VCMPGTSH_P, | |
3088 | ALTIVEC_BUILTIN_VCMPGTSW_P, | |
3089 | ALTIVEC_BUILTIN_VCMPGTUB_P, | |
3090 | ALTIVEC_BUILTIN_VCMPGTUH_P, | |
100c4561 AH |
3091 | ALTIVEC_BUILTIN_VCMPGTUW_P, |
3092 | ALTIVEC_BUILTIN_ABSS_V4SI, | |
3093 | ALTIVEC_BUILTIN_ABSS_V8HI, | |
3094 | ALTIVEC_BUILTIN_ABSS_V16QI, | |
3095 | ALTIVEC_BUILTIN_ABS_V4SI, | |
3096 | ALTIVEC_BUILTIN_ABS_V4SF, | |
3097 | ALTIVEC_BUILTIN_ABS_V8HI, | |
3098 | ALTIVEC_BUILTIN_ABS_V16QI | |
a3170dc6 AH |
3099 | /* SPE builtins. */ |
3100 | , SPE_BUILTIN_EVADDW, | |
3101 | SPE_BUILTIN_EVAND, | |
3102 | SPE_BUILTIN_EVANDC, | |
3103 | SPE_BUILTIN_EVDIVWS, | |
3104 | SPE_BUILTIN_EVDIVWU, | |
3105 | SPE_BUILTIN_EVEQV, | |
3106 | SPE_BUILTIN_EVFSADD, | |
3107 | SPE_BUILTIN_EVFSDIV, | |
3108 | SPE_BUILTIN_EVFSMUL, | |
3109 | SPE_BUILTIN_EVFSSUB, | |
3110 | SPE_BUILTIN_EVLDDX, | |
3111 | SPE_BUILTIN_EVLDHX, | |
3112 | SPE_BUILTIN_EVLDWX, | |
3113 | SPE_BUILTIN_EVLHHESPLATX, | |
3114 | SPE_BUILTIN_EVLHHOSSPLATX, | |
3115 | SPE_BUILTIN_EVLHHOUSPLATX, | |
3116 | SPE_BUILTIN_EVLWHEX, | |
3117 | SPE_BUILTIN_EVLWHOSX, | |
3118 | SPE_BUILTIN_EVLWHOUX, | |
3119 | SPE_BUILTIN_EVLWHSPLATX, | |
3120 | SPE_BUILTIN_EVLWWSPLATX, | |
3121 | SPE_BUILTIN_EVMERGEHI, | |
3122 | SPE_BUILTIN_EVMERGEHILO, | |
3123 | SPE_BUILTIN_EVMERGELO, | |
3124 | SPE_BUILTIN_EVMERGELOHI, | |
3125 | SPE_BUILTIN_EVMHEGSMFAA, | |
3126 | SPE_BUILTIN_EVMHEGSMFAN, | |
3127 | SPE_BUILTIN_EVMHEGSMIAA, | |
3128 | SPE_BUILTIN_EVMHEGSMIAN, | |
3129 | SPE_BUILTIN_EVMHEGUMIAA, | |
3130 | SPE_BUILTIN_EVMHEGUMIAN, | |
3131 | SPE_BUILTIN_EVMHESMF, | |
3132 | SPE_BUILTIN_EVMHESMFA, | |
3133 | SPE_BUILTIN_EVMHESMFAAW, | |
3134 | SPE_BUILTIN_EVMHESMFANW, | |
3135 | SPE_BUILTIN_EVMHESMI, | |
3136 | SPE_BUILTIN_EVMHESMIA, | |
3137 | SPE_BUILTIN_EVMHESMIAAW, | |
3138 | SPE_BUILTIN_EVMHESMIANW, | |
3139 | SPE_BUILTIN_EVMHESSF, | |
3140 | SPE_BUILTIN_EVMHESSFA, | |
3141 | SPE_BUILTIN_EVMHESSFAAW, | |
3142 | SPE_BUILTIN_EVMHESSFANW, | |
3143 | SPE_BUILTIN_EVMHESSIAAW, | |
3144 | SPE_BUILTIN_EVMHESSIANW, | |
3145 | SPE_BUILTIN_EVMHEUMI, | |
3146 | SPE_BUILTIN_EVMHEUMIA, | |
3147 | SPE_BUILTIN_EVMHEUMIAAW, | |
3148 | SPE_BUILTIN_EVMHEUMIANW, | |
3149 | SPE_BUILTIN_EVMHEUSIAAW, | |
3150 | SPE_BUILTIN_EVMHEUSIANW, | |
3151 | SPE_BUILTIN_EVMHOGSMFAA, | |
3152 | SPE_BUILTIN_EVMHOGSMFAN, | |
3153 | SPE_BUILTIN_EVMHOGSMIAA, | |
3154 | SPE_BUILTIN_EVMHOGSMIAN, | |
3155 | SPE_BUILTIN_EVMHOGUMIAA, | |
3156 | SPE_BUILTIN_EVMHOGUMIAN, | |
3157 | SPE_BUILTIN_EVMHOSMF, | |
3158 | SPE_BUILTIN_EVMHOSMFA, | |
3159 | SPE_BUILTIN_EVMHOSMFAAW, | |
3160 | SPE_BUILTIN_EVMHOSMFANW, | |
3161 | SPE_BUILTIN_EVMHOSMI, | |
3162 | SPE_BUILTIN_EVMHOSMIA, | |
3163 | SPE_BUILTIN_EVMHOSMIAAW, | |
3164 | SPE_BUILTIN_EVMHOSMIANW, | |
3165 | SPE_BUILTIN_EVMHOSSF, | |
3166 | SPE_BUILTIN_EVMHOSSFA, | |
3167 | SPE_BUILTIN_EVMHOSSFAAW, | |
3168 | SPE_BUILTIN_EVMHOSSFANW, | |
3169 | SPE_BUILTIN_EVMHOSSIAAW, | |
3170 | SPE_BUILTIN_EVMHOSSIANW, | |
3171 | SPE_BUILTIN_EVMHOUMI, | |
3172 | SPE_BUILTIN_EVMHOUMIA, | |
3173 | SPE_BUILTIN_EVMHOUMIAAW, | |
3174 | SPE_BUILTIN_EVMHOUMIANW, | |
3175 | SPE_BUILTIN_EVMHOUSIAAW, | |
3176 | SPE_BUILTIN_EVMHOUSIANW, | |
3177 | SPE_BUILTIN_EVMWHSMF, | |
3178 | SPE_BUILTIN_EVMWHSMFA, | |
3179 | SPE_BUILTIN_EVMWHSMI, | |
3180 | SPE_BUILTIN_EVMWHSMIA, | |
3181 | SPE_BUILTIN_EVMWHSSF, | |
3182 | SPE_BUILTIN_EVMWHSSFA, | |
3183 | SPE_BUILTIN_EVMWHUMI, | |
3184 | SPE_BUILTIN_EVMWHUMIA, | |
a3170dc6 AH |
3185 | SPE_BUILTIN_EVMWLSMIAAW, |
3186 | SPE_BUILTIN_EVMWLSMIANW, | |
a3170dc6 AH |
3187 | SPE_BUILTIN_EVMWLSSIAAW, |
3188 | SPE_BUILTIN_EVMWLSSIANW, | |
3189 | SPE_BUILTIN_EVMWLUMI, | |
3190 | SPE_BUILTIN_EVMWLUMIA, | |
3191 | SPE_BUILTIN_EVMWLUMIAAW, | |
3192 | SPE_BUILTIN_EVMWLUMIANW, | |
3193 | SPE_BUILTIN_EVMWLUSIAAW, | |
3194 | SPE_BUILTIN_EVMWLUSIANW, | |
3195 | SPE_BUILTIN_EVMWSMF, | |
3196 | SPE_BUILTIN_EVMWSMFA, | |
3197 | SPE_BUILTIN_EVMWSMFAA, | |
3198 | SPE_BUILTIN_EVMWSMFAN, | |
3199 | SPE_BUILTIN_EVMWSMI, | |
3200 | SPE_BUILTIN_EVMWSMIA, | |
3201 | SPE_BUILTIN_EVMWSMIAA, | |
3202 | SPE_BUILTIN_EVMWSMIAN, | |
3203 | SPE_BUILTIN_EVMWHSSFAA, | |
3204 | SPE_BUILTIN_EVMWSSF, | |
3205 | SPE_BUILTIN_EVMWSSFA, | |
3206 | SPE_BUILTIN_EVMWSSFAA, | |
3207 | SPE_BUILTIN_EVMWSSFAN, | |
3208 | SPE_BUILTIN_EVMWUMI, | |
3209 | SPE_BUILTIN_EVMWUMIA, | |
3210 | SPE_BUILTIN_EVMWUMIAA, | |
3211 | SPE_BUILTIN_EVMWUMIAN, | |
3212 | SPE_BUILTIN_EVNAND, | |
3213 | SPE_BUILTIN_EVNOR, | |
3214 | SPE_BUILTIN_EVOR, | |
3215 | SPE_BUILTIN_EVORC, | |
3216 | SPE_BUILTIN_EVRLW, | |
3217 | SPE_BUILTIN_EVSLW, | |
3218 | SPE_BUILTIN_EVSRWS, | |
3219 | SPE_BUILTIN_EVSRWU, | |
3220 | SPE_BUILTIN_EVSTDDX, | |
3221 | SPE_BUILTIN_EVSTDHX, | |
3222 | SPE_BUILTIN_EVSTDWX, | |
3223 | SPE_BUILTIN_EVSTWHEX, | |
3224 | SPE_BUILTIN_EVSTWHOX, | |
3225 | SPE_BUILTIN_EVSTWWEX, | |
3226 | SPE_BUILTIN_EVSTWWOX, | |
3227 | SPE_BUILTIN_EVSUBFW, | |
3228 | SPE_BUILTIN_EVXOR, | |
3229 | SPE_BUILTIN_EVABS, | |
3230 | SPE_BUILTIN_EVADDSMIAAW, | |
3231 | SPE_BUILTIN_EVADDSSIAAW, | |
3232 | SPE_BUILTIN_EVADDUMIAAW, | |
3233 | SPE_BUILTIN_EVADDUSIAAW, | |
3234 | SPE_BUILTIN_EVCNTLSW, | |
3235 | SPE_BUILTIN_EVCNTLZW, | |
3236 | SPE_BUILTIN_EVEXTSB, | |
3237 | SPE_BUILTIN_EVEXTSH, | |
3238 | SPE_BUILTIN_EVFSABS, | |
3239 | SPE_BUILTIN_EVFSCFSF, | |
3240 | SPE_BUILTIN_EVFSCFSI, | |
3241 | SPE_BUILTIN_EVFSCFUF, | |
3242 | SPE_BUILTIN_EVFSCFUI, | |
3243 | SPE_BUILTIN_EVFSCTSF, | |
3244 | SPE_BUILTIN_EVFSCTSI, | |
3245 | SPE_BUILTIN_EVFSCTSIZ, | |
3246 | SPE_BUILTIN_EVFSCTUF, | |
3247 | SPE_BUILTIN_EVFSCTUI, | |
3248 | SPE_BUILTIN_EVFSCTUIZ, | |
3249 | SPE_BUILTIN_EVFSNABS, | |
3250 | SPE_BUILTIN_EVFSNEG, | |
3251 | SPE_BUILTIN_EVMRA, | |
3252 | SPE_BUILTIN_EVNEG, | |
3253 | SPE_BUILTIN_EVRNDW, | |
3254 | SPE_BUILTIN_EVSUBFSMIAAW, | |
3255 | SPE_BUILTIN_EVSUBFSSIAAW, | |
3256 | SPE_BUILTIN_EVSUBFUMIAAW, | |
3257 | SPE_BUILTIN_EVSUBFUSIAAW, | |
3258 | SPE_BUILTIN_EVADDIW, | |
3259 | SPE_BUILTIN_EVLDD, | |
3260 | SPE_BUILTIN_EVLDH, | |
3261 | SPE_BUILTIN_EVLDW, | |
3262 | SPE_BUILTIN_EVLHHESPLAT, | |
3263 | SPE_BUILTIN_EVLHHOSSPLAT, | |
3264 | SPE_BUILTIN_EVLHHOUSPLAT, | |
3265 | SPE_BUILTIN_EVLWHE, | |
3266 | SPE_BUILTIN_EVLWHOS, | |
3267 | SPE_BUILTIN_EVLWHOU, | |
3268 | SPE_BUILTIN_EVLWHSPLAT, | |
3269 | SPE_BUILTIN_EVLWWSPLAT, | |
3270 | SPE_BUILTIN_EVRLWI, | |
3271 | SPE_BUILTIN_EVSLWI, | |
3272 | SPE_BUILTIN_EVSRWIS, | |
3273 | SPE_BUILTIN_EVSRWIU, | |
3274 | SPE_BUILTIN_EVSTDD, | |
3275 | SPE_BUILTIN_EVSTDH, | |
3276 | SPE_BUILTIN_EVSTDW, | |
3277 | SPE_BUILTIN_EVSTWHE, | |
3278 | SPE_BUILTIN_EVSTWHO, | |
3279 | SPE_BUILTIN_EVSTWWE, | |
3280 | SPE_BUILTIN_EVSTWWO, | |
3281 | SPE_BUILTIN_EVSUBIFW, | |
3282 | ||
3283 | /* Compares. */ | |
3284 | SPE_BUILTIN_EVCMPEQ, | |
3285 | SPE_BUILTIN_EVCMPGTS, | |
3286 | SPE_BUILTIN_EVCMPGTU, | |
3287 | SPE_BUILTIN_EVCMPLTS, | |
3288 | SPE_BUILTIN_EVCMPLTU, | |
3289 | SPE_BUILTIN_EVFSCMPEQ, | |
3290 | SPE_BUILTIN_EVFSCMPGT, | |
3291 | SPE_BUILTIN_EVFSCMPLT, | |
3292 | SPE_BUILTIN_EVFSTSTEQ, | |
3293 | SPE_BUILTIN_EVFSTSTGT, | |
3294 | SPE_BUILTIN_EVFSTSTLT, | |
3295 | ||
3296 | /* EVSEL compares. */ | |
3297 | SPE_BUILTIN_EVSEL_CMPEQ, | |
3298 | SPE_BUILTIN_EVSEL_CMPGTS, | |
3299 | SPE_BUILTIN_EVSEL_CMPGTU, | |
3300 | SPE_BUILTIN_EVSEL_CMPLTS, | |
3301 | SPE_BUILTIN_EVSEL_CMPLTU, | |
3302 | SPE_BUILTIN_EVSEL_FSCMPEQ, | |
3303 | SPE_BUILTIN_EVSEL_FSCMPGT, | |
3304 | SPE_BUILTIN_EVSEL_FSCMPLT, | |
3305 | SPE_BUILTIN_EVSEL_FSTSTEQ, | |
3306 | SPE_BUILTIN_EVSEL_FSTSTGT, | |
3307 | SPE_BUILTIN_EVSEL_FSTSTLT, | |
3308 | ||
3309 | SPE_BUILTIN_EVSPLATFI, | |
3310 | SPE_BUILTIN_EVSPLATI, | |
3311 | SPE_BUILTIN_EVMWHSSMAA, | |
3312 | SPE_BUILTIN_EVMWHSMFAA, | |
3313 | SPE_BUILTIN_EVMWHSMIAA, | |
3314 | SPE_BUILTIN_EVMWHUSIAA, | |
3315 | SPE_BUILTIN_EVMWHUMIAA, | |
3316 | SPE_BUILTIN_EVMWHSSFAN, | |
3317 | SPE_BUILTIN_EVMWHSSIAN, | |
3318 | SPE_BUILTIN_EVMWHSMFAN, | |
3319 | SPE_BUILTIN_EVMWHSMIAN, | |
3320 | SPE_BUILTIN_EVMWHUSIAN, | |
3321 | SPE_BUILTIN_EVMWHUMIAN, | |
3322 | SPE_BUILTIN_EVMWHGSSFAA, | |
3323 | SPE_BUILTIN_EVMWHGSMFAA, | |
3324 | SPE_BUILTIN_EVMWHGSMIAA, | |
3325 | SPE_BUILTIN_EVMWHGUMIAA, | |
3326 | SPE_BUILTIN_EVMWHGSSFAN, | |
3327 | SPE_BUILTIN_EVMWHGSMFAN, | |
3328 | SPE_BUILTIN_EVMWHGSMIAN, | |
3329 | SPE_BUILTIN_EVMWHGUMIAN, | |
3330 | SPE_BUILTIN_MTSPEFSCR, | |
3331 | SPE_BUILTIN_MFSPEFSCR, | |
3332 | SPE_BUILTIN_BRINC | |
0ac081f6 | 3333 | }; |