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f045b2c9 | 1 | /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
cbe34bb5 | 2 | Copyright (C) 1992-2017 Free Software Foundation, Inc. |
6a7ec0a7 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
f045b2c9 | 4 | |
5de601cf | 5 | This file is part of GCC. |
f045b2c9 | 6 | |
5de601cf NC |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
5de601cf | 10 | option) any later version. |
f045b2c9 | 11 | |
5de601cf NC |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
f045b2c9 | 16 | |
748086b7 JJ |
17 | Under Section 7 of GPL version 3, you are granted additional |
18 | permissions described in the GCC Runtime Library Exception, version | |
19 | 3.1, as published by the Free Software Foundation. | |
20 | ||
21 | You should have received a copy of the GNU General Public License and | |
22 | a copy of the GCC Runtime Library Exception along with this program; | |
23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 24 | <http://www.gnu.org/licenses/>. */ |
f045b2c9 RS |
25 | |
26 | /* Note that some other tm.h files include this one and then override | |
9ebbca7d | 27 | many of the definitions. */ |
f045b2c9 | 28 | |
fd438373 MM |
29 | #ifndef RS6000_OPTS_H |
30 | #include "config/rs6000/rs6000-opts.h" | |
31 | #endif | |
32 | ||
9ebbca7d GK |
33 | /* Definitions for the object file format. These are set at |
34 | compile-time. */ | |
f045b2c9 | 35 | |
9ebbca7d GK |
36 | #define OBJECT_XCOFF 1 |
37 | #define OBJECT_ELF 2 | |
38 | #define OBJECT_PEF 3 | |
ee890fe2 | 39 | #define OBJECT_MACHO 4 |
f045b2c9 | 40 | |
9ebbca7d | 41 | #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) |
2bfcf297 | 42 | #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) |
9ebbca7d | 43 | #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) |
ee890fe2 | 44 | #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) |
f045b2c9 | 45 | |
2bfcf297 DB |
46 | #ifndef TARGET_AIX |
47 | #define TARGET_AIX 0 | |
48 | #endif | |
49 | ||
78009d9f MM |
50 | #ifndef TARGET_AIX_OS |
51 | #define TARGET_AIX_OS 0 | |
52 | #endif | |
53 | ||
85b776df AM |
54 | /* Control whether function entry points use a "dot" symbol when |
55 | ABI_AIX. */ | |
56 | #define DOT_SYMBOLS 1 | |
57 | ||
8e3f41e7 MM |
58 | /* Default string to use for cpu if not specified. */ |
59 | #ifndef TARGET_CPU_DEFAULT | |
60 | #define TARGET_CPU_DEFAULT ((char *)0) | |
61 | #endif | |
62 | ||
f565b0a1 | 63 | /* If configured for PPC405, support PPC405CR Erratum77. */ |
b0bfee6e | 64 | #ifdef CONFIG_PPC405CR |
f565b0a1 DE |
65 | #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) |
66 | #else | |
67 | #define PPC405_ERRATUM77 0 | |
68 | #endif | |
69 | ||
96038623 DE |
70 | #ifndef TARGET_PAIRED_FLOAT |
71 | #define TARGET_PAIRED_FLOAT 0 | |
72 | #endif | |
73 | ||
cd679487 BE |
74 | #ifdef HAVE_AS_POPCNTB |
75 | #define ASM_CPU_POWER5_SPEC "-mpower5" | |
76 | #else | |
77 | #define ASM_CPU_POWER5_SPEC "-mpower4" | |
78 | #endif | |
79 | ||
80 | #ifdef HAVE_AS_DFP | |
81 | #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" | |
82 | #else | |
83 | #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" | |
84 | #endif | |
85 | ||
cacf1ca8 | 86 | #ifdef HAVE_AS_POPCNTD |
d40c9e33 PB |
87 | #define ASM_CPU_POWER7_SPEC "-mpower7" |
88 | #else | |
89 | #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" | |
90 | #endif | |
91 | ||
428bffcb PB |
92 | #ifdef HAVE_AS_POWER8 |
93 | #define ASM_CPU_POWER8_SPEC "-mpower8" | |
94 | #else | |
f62511da | 95 | #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC |
428bffcb PB |
96 | #endif |
97 | ||
d1f0d376 MM |
98 | #ifdef HAVE_AS_POWER9 |
99 | #define ASM_CPU_POWER9_SPEC "-mpower9" | |
100 | #else | |
101 | #define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC | |
102 | #endif | |
103 | ||
47f67e51 PB |
104 | #ifdef HAVE_AS_DCI |
105 | #define ASM_CPU_476_SPEC "-m476" | |
106 | #else | |
107 | #define ASM_CPU_476_SPEC "-mpower4" | |
108 | #endif | |
109 | ||
cacf1ca8 MM |
110 | /* Common ASM definitions used by ASM_SPEC among the various targets for |
111 | handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to | |
112 | provide the default assembler options if the user uses -mcpu=native, so if | |
113 | you make changes here, make them also there. */ | |
f984d8df DB |
114 | #define ASM_CPU_SPEC \ |
115 | "%{!mcpu*: \ | |
93ae5495 | 116 | %{mpowerpc64*: -mppc64} \ |
a441dedb | 117 | %{!mpowerpc64*: %(asm_default)}} \ |
cacf1ca8 | 118 | %{mcpu=native: %(asm_cpu_native)} \ |
d296e02e | 119 | %{mcpu=cell: -mcell} \ |
93ae5495 | 120 | %{mcpu=power3: -mppc64} \ |
957e9e48 | 121 | %{mcpu=power4: -mpower4} \ |
cd679487 BE |
122 | %{mcpu=power5: %(asm_cpu_power5)} \ |
123 | %{mcpu=power5+: %(asm_cpu_power5)} \ | |
124 | %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ | |
125 | %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ | |
d40c9e33 | 126 | %{mcpu=power7: %(asm_cpu_power7)} \ |
428bffcb | 127 | %{mcpu=power8: %(asm_cpu_power8)} \ |
d1f0d376 | 128 | %{mcpu=power9: %(asm_cpu_power9)} \ |
ebde32fd | 129 | %{mcpu=a2: -ma2} \ |
f984d8df | 130 | %{mcpu=powerpc: -mppc} \ |
fa17b3db | 131 | %{mcpu=powerpc64le: %(asm_cpu_power8)} \ |
93ae5495 | 132 | %{mcpu=rs64a: -mppc64} \ |
f984d8df | 133 | %{mcpu=401: -mppc} \ |
61a8515c JS |
134 | %{mcpu=403: -m403} \ |
135 | %{mcpu=405: -m405} \ | |
2c9d95ef DE |
136 | %{mcpu=405fp: -m405} \ |
137 | %{mcpu=440: -m440} \ | |
138 | %{mcpu=440fp: -m440} \ | |
4adf8008 PB |
139 | %{mcpu=464: -m440} \ |
140 | %{mcpu=464fp: -m440} \ | |
47f67e51 PB |
141 | %{mcpu=476: %(asm_cpu_476)} \ |
142 | %{mcpu=476fp: %(asm_cpu_476)} \ | |
f984d8df DB |
143 | %{mcpu=505: -mppc} \ |
144 | %{mcpu=601: -m601} \ | |
145 | %{mcpu=602: -mppc} \ | |
146 | %{mcpu=603: -mppc} \ | |
147 | %{mcpu=603e: -mppc} \ | |
148 | %{mcpu=ec603e: -mppc} \ | |
149 | %{mcpu=604: -mppc} \ | |
150 | %{mcpu=604e: -mppc} \ | |
93ae5495 AM |
151 | %{mcpu=620: -mppc64} \ |
152 | %{mcpu=630: -mppc64} \ | |
f984d8df DB |
153 | %{mcpu=740: -mppc} \ |
154 | %{mcpu=750: -mppc} \ | |
49ffe578 | 155 | %{mcpu=G3: -mppc} \ |
93ae5495 AM |
156 | %{mcpu=7400: -mppc -maltivec} \ |
157 | %{mcpu=7450: -mppc -maltivec} \ | |
158 | %{mcpu=G4: -mppc -maltivec} \ | |
f984d8df DB |
159 | %{mcpu=801: -mppc} \ |
160 | %{mcpu=821: -mppc} \ | |
161 | %{mcpu=823: -mppc} \ | |
775db490 | 162 | %{mcpu=860: -mppc} \ |
93ae5495 AM |
163 | %{mcpu=970: -mpower4 -maltivec} \ |
164 | %{mcpu=G5: -mpower4 -maltivec} \ | |
a3170dc6 | 165 | %{mcpu=8540: -me500} \ |
5ca0373f | 166 | %{mcpu=8548: -me500} \ |
fa41c305 EW |
167 | %{mcpu=e300c2: -me300} \ |
168 | %{mcpu=e300c3: -me300} \ | |
edae5fe3 | 169 | %{mcpu=e500mc: -me500mc} \ |
b17f98b1 | 170 | %{mcpu=e500mc64: -me500mc64} \ |
683ed19e EW |
171 | %{mcpu=e5500: -me5500} \ |
172 | %{mcpu=e6500: -me6500} \ | |
93ae5495 | 173 | %{maltivec: -maltivec} \ |
2c9ccc21 | 174 | %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ |
0258b6e4 | 175 | %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \ |
93ae5495 | 176 | -many" |
f984d8df DB |
177 | |
178 | #define CPP_DEFAULT_SPEC "" | |
179 | ||
180 | #define ASM_DEFAULT_SPEC "" | |
181 | ||
841faeed MM |
182 | /* This macro defines names of additional specifications to put in the specs |
183 | that can be used in various specifications like CC1_SPEC. Its definition | |
184 | is an initializer with a subgrouping for each command option. | |
185 | ||
186 | Each subgrouping contains a string constant, that defines the | |
5de601cf | 187 | specification name, and a string constant that used by the GCC driver |
841faeed MM |
188 | program. |
189 | ||
190 | Do not define this macro if it does not need to do anything. */ | |
191 | ||
7509c759 | 192 | #define SUBTARGET_EXTRA_SPECS |
7509c759 | 193 | |
c81bebd7 | 194 | #define EXTRA_SPECS \ |
c81bebd7 | 195 | { "cpp_default", CPP_DEFAULT_SPEC }, \ |
c81bebd7 | 196 | { "asm_cpu", ASM_CPU_SPEC }, \ |
cacf1ca8 | 197 | { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
c81bebd7 | 198 | { "asm_default", ASM_DEFAULT_SPEC }, \ |
0eab6840 | 199 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
cd679487 BE |
200 | { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ |
201 | { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ | |
d40c9e33 | 202 | { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ |
428bffcb | 203 | { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ |
d1f0d376 | 204 | { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \ |
47f67e51 | 205 | { "asm_cpu_476", ASM_CPU_476_SPEC }, \ |
7509c759 MM |
206 | SUBTARGET_EXTRA_SPECS |
207 | ||
0eab6840 DE |
208 | /* -mcpu=native handling only makes sense with compiler running on |
209 | an PowerPC chip. If changing this condition, also change | |
210 | the condition in driver-rs6000.c. */ | |
211 | #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) | |
212 | /* In driver-rs6000.c. */ | |
213 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
214 | #define EXTRA_SPEC_FUNCTIONS \ | |
215 | { "local_cpu_detect", host_detect_local_cpu }, | |
216 | #define HAVE_LOCAL_CPU_DETECT | |
cacf1ca8 MM |
217 | #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
218 | ||
219 | #else | |
220 | #define ASM_CPU_NATIVE_SPEC "%(asm_default)" | |
0eab6840 DE |
221 | #endif |
222 | ||
ee7caeb3 DE |
223 | #ifndef CC1_CPU_SPEC |
224 | #ifdef HAVE_LOCAL_CPU_DETECT | |
0eab6840 DE |
225 | #define CC1_CPU_SPEC \ |
226 | "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
227 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
ee7caeb3 DE |
228 | #else |
229 | #define CC1_CPU_SPEC "" | |
230 | #endif | |
0eab6840 DE |
231 | #endif |
232 | ||
fb623df5 | 233 | /* Architecture type. */ |
f045b2c9 | 234 | |
bb22512c | 235 | /* Define TARGET_MFCRF if the target assembler does not support the |
78f5898b | 236 | optional field operand for mfcr. */ |
fb623df5 | 237 | |
78f5898b | 238 | #ifndef HAVE_AS_MFCRF |
432218ba | 239 | #undef TARGET_MFCRF |
ffa22984 DE |
240 | #define TARGET_MFCRF 0 |
241 | #endif | |
242 | ||
0fa2e4df | 243 | /* Define TARGET_POPCNTB if the target assembler does not support the |
432218ba DE |
244 | popcount byte instruction. */ |
245 | ||
246 | #ifndef HAVE_AS_POPCNTB | |
247 | #undef TARGET_POPCNTB | |
248 | #define TARGET_POPCNTB 0 | |
249 | #endif | |
250 | ||
9719f3b7 DE |
251 | /* Define TARGET_FPRND if the target assembler does not support the |
252 | fp rounding instructions. */ | |
253 | ||
254 | #ifndef HAVE_AS_FPRND | |
255 | #undef TARGET_FPRND | |
256 | #define TARGET_FPRND 0 | |
257 | #endif | |
258 | ||
b639c3c2 JJ |
259 | /* Define TARGET_CMPB if the target assembler does not support the |
260 | cmpb instruction. */ | |
261 | ||
262 | #ifndef HAVE_AS_CMPB | |
263 | #undef TARGET_CMPB | |
264 | #define TARGET_CMPB 0 | |
265 | #endif | |
266 | ||
44cd321e PS |
267 | /* Define TARGET_MFPGPR if the target assembler does not support the |
268 | mffpr and mftgpr instructions. */ | |
269 | ||
270 | #ifndef HAVE_AS_MFPGPR | |
271 | #undef TARGET_MFPGPR | |
272 | #define TARGET_MFPGPR 0 | |
273 | #endif | |
274 | ||
b639c3c2 JJ |
275 | /* Define TARGET_DFP if the target assembler does not support decimal |
276 | floating point instructions. */ | |
277 | #ifndef HAVE_AS_DFP | |
278 | #undef TARGET_DFP | |
279 | #define TARGET_DFP 0 | |
280 | #endif | |
281 | ||
cacf1ca8 MM |
282 | /* Define TARGET_POPCNTD if the target assembler does not support the |
283 | popcount word and double word instructions. */ | |
284 | ||
285 | #ifndef HAVE_AS_POPCNTD | |
286 | #undef TARGET_POPCNTD | |
287 | #define TARGET_POPCNTD 0 | |
288 | #endif | |
289 | ||
f62511da MM |
290 | /* Define the ISA 2.07 flags as 0 if the target assembler does not support the |
291 | waitasecond instruction. Allow -mpower8-fusion, since it does not add new | |
292 | instructions. */ | |
293 | ||
294 | #ifndef HAVE_AS_POWER8 | |
295 | #undef TARGET_DIRECT_MOVE | |
296 | #undef TARGET_CRYPTO | |
0258b6e4 | 297 | #undef TARGET_HTM |
f62511da MM |
298 | #undef TARGET_P8_VECTOR |
299 | #define TARGET_DIRECT_MOVE 0 | |
300 | #define TARGET_CRYPTO 0 | |
0258b6e4 | 301 | #define TARGET_HTM 0 |
f62511da MM |
302 | #define TARGET_P8_VECTOR 0 |
303 | #endif | |
304 | ||
caea59ff KN |
305 | /* Define the ISA 3.0 flags as 0 if the target assembler does not support |
306 | Power9 instructions. Allow -mpower9-fusion, since it does not add new | |
307 | instructions. Allow -misel, since it predates ISA 3.0 and does | |
308 | not require any Power9 features. */ | |
309 | ||
310 | #ifndef HAVE_AS_POWER9 | |
311 | #undef TARGET_FLOAT128_HW | |
312 | #undef TARGET_MODULO | |
313 | #undef TARGET_P9_VECTOR | |
314 | #undef TARGET_P9_MINMAX | |
5a3a6a5e | 315 | #undef TARGET_P9_MISC |
caea59ff KN |
316 | #define TARGET_FLOAT128_HW 0 |
317 | #define TARGET_MODULO 0 | |
318 | #define TARGET_P9_VECTOR 0 | |
319 | #define TARGET_P9_MINMAX 0 | |
5a3a6a5e | 320 | #define TARGET_P9_MISC 0 |
caea59ff KN |
321 | #endif |
322 | ||
cacf1ca8 MM |
323 | /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If |
324 | not, generate the lwsync code as an integer constant. */ | |
325 | #ifdef HAVE_AS_LWSYNC | |
326 | #define TARGET_LWSYNC_INSTRUCTION 1 | |
327 | #else | |
328 | #define TARGET_LWSYNC_INSTRUCTION 0 | |
329 | #endif | |
330 | ||
9752c4ad AM |
331 | /* Define TARGET_TLS_MARKERS if the target assembler does not support |
332 | arg markers for __tls_get_addr calls. */ | |
333 | #ifndef HAVE_AS_TLS_MARKERS | |
334 | #undef TARGET_TLS_MARKERS | |
335 | #define TARGET_TLS_MARKERS 0 | |
336 | #else | |
337 | #define TARGET_TLS_MARKERS tls_markers | |
338 | #endif | |
339 | ||
7f970b70 AM |
340 | #ifndef TARGET_SECURE_PLT |
341 | #define TARGET_SECURE_PLT 0 | |
342 | #endif | |
343 | ||
070b27da AM |
344 | #ifndef TARGET_CMODEL |
345 | #define TARGET_CMODEL CMODEL_SMALL | |
346 | #endif | |
347 | ||
2f3e5814 | 348 | #define TARGET_32BIT (! TARGET_64BIT) |
d14a6d05 | 349 | |
c4501e62 JJ |
350 | #ifndef HAVE_AS_TLS |
351 | #define HAVE_AS_TLS 0 | |
352 | #endif | |
353 | ||
be26142a PB |
354 | #ifndef TARGET_LINK_STACK |
355 | #define TARGET_LINK_STACK 0 | |
356 | #endif | |
357 | ||
358 | #ifndef SET_TARGET_LINK_STACK | |
359 | #define SET_TARGET_LINK_STACK(X) do { } while (0) | |
360 | #endif | |
361 | ||
08213983 MM |
362 | #ifndef TARGET_FLOAT128_ENABLE_TYPE |
363 | #define TARGET_FLOAT128_ENABLE_TYPE 0 | |
364 | #endif | |
365 | ||
48d72335 DE |
366 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ |
367 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
368 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
369 | ||
996ed075 JJ |
370 | #ifdef IN_LIBGCC2 |
371 | /* For libgcc2 we make sure this is a compile time constant */ | |
67796c1f | 372 | #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) |
78f5898b | 373 | #undef TARGET_POWERPC64 |
996ed075 JJ |
374 | #define TARGET_POWERPC64 1 |
375 | #else | |
78f5898b | 376 | #undef TARGET_POWERPC64 |
996ed075 JJ |
377 | #define TARGET_POWERPC64 0 |
378 | #endif | |
b6c9286a | 379 | #else |
78f5898b | 380 | /* The option machinery will define this. */ |
b6c9286a MM |
381 | #endif |
382 | ||
c28a7c24 | 383 | #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) |
9ebbca7d | 384 | |
696e45ba ME |
385 | /* FPU operations supported. |
386 | Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must | |
387 | also test TARGET_HARD_FLOAT. */ | |
388 | #define TARGET_SINGLE_FLOAT 1 | |
389 | #define TARGET_DOUBLE_FLOAT 1 | |
390 | #define TARGET_SINGLE_FPU 0 | |
391 | #define TARGET_SIMPLE_FPU 0 | |
0bb7b92e | 392 | #define TARGET_XILINX_FPU 0 |
696e45ba | 393 | |
fb623df5 RK |
394 | /* Recast the processor type to the cpu attribute. */ |
395 | #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) | |
396 | ||
8482e358 | 397 | /* Define generic processor types based upon current deployment. */ |
3cb999d8 | 398 | #define PROCESSOR_COMMON PROCESSOR_PPC601 |
3cb999d8 DE |
399 | #define PROCESSOR_POWERPC PROCESSOR_PPC604 |
400 | #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
6e151478 | 401 | |
fb623df5 | 402 | /* Define the default processor. This is overridden by other tm.h files. */ |
f3061fa4 | 403 | #define PROCESSOR_DEFAULT PROCESSOR_PPC603 |
3cb999d8 | 404 | #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A |
fb623df5 | 405 | |
59ac9a55 JJ |
406 | /* Specify the dialect of assembler to use. Only new mnemonics are supported |
407 | starting with GCC 4.8, i.e. just one dialect, but for backwards | |
408 | compatibility with older inline asm ASSEMBLER_DIALECT needs to be | |
409 | defined. */ | |
410 | #define ASSEMBLER_DIALECT 1 | |
411 | ||
38c1f2d7 | 412 | /* Debug support */ |
fd438373 MM |
413 | #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
414 | #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ | |
415 | #define MASK_DEBUG_REG 0x04 /* debug register handling */ | |
416 | #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ | |
417 | #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ | |
418 | #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ | |
7fa14a01 | 419 | #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ |
fd438373 MM |
420 | #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
421 | | MASK_DEBUG_ARG \ | |
422 | | MASK_DEBUG_REG \ | |
423 | | MASK_DEBUG_ADDR \ | |
424 | | MASK_DEBUG_COST \ | |
7fa14a01 MM |
425 | | MASK_DEBUG_TARGET \ |
426 | | MASK_DEBUG_BUILTIN) | |
fd438373 MM |
427 | |
428 | #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) | |
429 | #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) | |
430 | #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) | |
431 | #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) | |
432 | #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) | |
433 | #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) | |
7fa14a01 | 434 | #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) |
cacf1ca8 | 435 | |
2c83faf8 MM |
436 | /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM |
437 | long double format that uses a pair of doubles, or IEEE 128-bit floating | |
438 | point. KFmode was added as a way to represent IEEE 128-bit floating point, | |
439 | even if the default for long double is the IBM long double format. | |
440 | Similarly IFmode is the IBM long double format even if the default is IEEE | |
0bc36dec | 441 | 128-bit. Don't allow IFmode if -msoft-float. */ |
2c83faf8 | 442 | #define FLOAT128_IEEE_P(MODE) \ |
4304ccfd MM |
443 | ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ |
444 | || ((MODE) == KFmode) || ((MODE) == KCmode)) | |
2c83faf8 MM |
445 | |
446 | #define FLOAT128_IBM_P(MODE) \ | |
4304ccfd | 447 | ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ |
11d8d07e | 448 | || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) |
2c83faf8 MM |
449 | |
450 | /* Helper macros to say whether a 128-bit floating point type can go in a | |
451 | single vector register, or whether it needs paired scalar values. */ | |
08213983 | 452 | #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) |
2c83faf8 MM |
453 | |
454 | #define FLOAT128_2REG_P(MODE) \ | |
455 | (FLOAT128_IBM_P (MODE) \ | |
456 | || ((MODE) == TDmode) \ | |
08213983 | 457 | || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) |
2c83faf8 MM |
458 | |
459 | /* Return true for floating point that does not use a vector register. */ | |
460 | #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ | |
461 | (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) | |
462 | ||
f62511da | 463 | /* Describe the vector unit used for arithmetic operations. */ |
cacf1ca8 MM |
464 | extern enum rs6000_vector rs6000_vector_unit[]; |
465 | ||
466 | #define VECTOR_UNIT_NONE_P(MODE) \ | |
467 | (rs6000_vector_unit[(MODE)] == VECTOR_NONE) | |
468 | ||
469 | #define VECTOR_UNIT_VSX_P(MODE) \ | |
470 | (rs6000_vector_unit[(MODE)] == VECTOR_VSX) | |
471 | ||
f62511da MM |
472 | #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ |
473 | (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) | |
474 | ||
cacf1ca8 MM |
475 | #define VECTOR_UNIT_ALTIVEC_P(MODE) \ |
476 | (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) | |
477 | ||
f62511da MM |
478 | #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ |
479 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ | |
480 | (int)VECTOR_VSX, \ | |
481 | (int)VECTOR_P8_VECTOR)) | |
482 | ||
483 | /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either | |
484 | altivec (VMX) or VSX vector instructions. P8 vector support is upwards | |
485 | compatible, so allow it as well, rather than changing all of the uses of the | |
486 | macro. */ | |
cacf1ca8 | 487 | #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ |
f62511da MM |
488 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ |
489 | (int)VECTOR_ALTIVEC, \ | |
490 | (int)VECTOR_P8_VECTOR)) | |
cacf1ca8 MM |
491 | |
492 | /* Describe whether to use VSX loads or Altivec loads. For now, just use the | |
493 | same unit as the vector unit we are using, but we may want to migrate to | |
494 | using VSX style loads even for types handled by altivec. */ | |
495 | extern enum rs6000_vector rs6000_vector_mem[]; | |
496 | ||
497 | #define VECTOR_MEM_NONE_P(MODE) \ | |
498 | (rs6000_vector_mem[(MODE)] == VECTOR_NONE) | |
499 | ||
500 | #define VECTOR_MEM_VSX_P(MODE) \ | |
501 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
502 | ||
f62511da MM |
503 | #define VECTOR_MEM_P8_VECTOR_P(MODE) \ |
504 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
505 | ||
cacf1ca8 MM |
506 | #define VECTOR_MEM_ALTIVEC_P(MODE) \ |
507 | (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) | |
508 | ||
f62511da MM |
509 | #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ |
510 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ | |
511 | (int)VECTOR_VSX, \ | |
512 | (int)VECTOR_P8_VECTOR)) | |
513 | ||
cacf1ca8 | 514 | #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ |
f62511da MM |
515 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ |
516 | (int)VECTOR_ALTIVEC, \ | |
517 | (int)VECTOR_P8_VECTOR)) | |
cacf1ca8 MM |
518 | |
519 | /* Return the alignment of a given vector type, which is set based on the | |
520 | vector unit use. VSX for instance can load 32 or 64 bit aligned words | |
521 | without problems, while Altivec requires 128-bit aligned vectors. */ | |
522 | extern int rs6000_vector_align[]; | |
523 | ||
524 | #define VECTOR_ALIGN(MODE) \ | |
525 | ((rs6000_vector_align[(MODE)] != 0) \ | |
526 | ? rs6000_vector_align[(MODE)] \ | |
527 | : (int)GET_MODE_BITSIZE ((MODE))) | |
528 | ||
6edc217d BS |
529 | /* Determine the element order to use for vector instructions. By |
530 | default we use big-endian element order when targeting big-endian, | |
531 | and little-endian element order when targeting little-endian. For | |
532 | programs being ported from BE Power to LE Power, it can sometimes | |
533 | be useful to use big-endian element order when targeting little-endian. | |
534 | This is set via -maltivec=be, for example. */ | |
535 | #define VECTOR_ELT_ORDER_BIG \ | |
536 | (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) | |
537 | ||
117f16fb MM |
538 | /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
539 | with scalar instructions. */ | |
540 | #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) | |
541 | ||
dd551aa1 MM |
542 | /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
543 | with the ISA 3.0 MFVSRLD instructions. */ | |
544 | #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) | |
545 | ||
025d9908 KH |
546 | /* Alignment options for fields in structures for sub-targets following |
547 | AIX-like ABI. | |
548 | ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
549 | ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
550 | ||
551 | Override the macro definitions when compiling libobjc to avoid undefined | |
552 | reference to rs6000_alignment_flags due to library's use of GCC alignment | |
553 | macros which use the macros below. */ | |
f676971a | 554 | |
025d9908 KH |
555 | #ifndef IN_TARGET_LIBS |
556 | #define MASK_ALIGN_POWER 0x00000000 | |
557 | #define MASK_ALIGN_NATURAL 0x00000001 | |
558 | #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
559 | #else | |
560 | #define TARGET_ALIGN_NATURAL 0 | |
561 | #endif | |
6fa3f289 ZW |
562 | |
563 | #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) | |
602ea4d3 | 564 | #define TARGET_IEEEQUAD rs6000_ieeequad |
6fa3f289 | 565 | #define TARGET_ALTIVEC_ABI rs6000_altivec_abi |
cacf1ca8 | 566 | #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
6fa3f289 | 567 | |
cacf1ca8 | 568 | #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) |
a3170dc6 | 569 | |
7042fe5e MM |
570 | /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
571 | Enable 32-bit fcfid's on any of the switches for newer ISA machines or | |
572 | XILINX. */ | |
c3f8384f MM |
573 | #define TARGET_FCFID (TARGET_POWERPC64 \ |
574 | || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
575 | || TARGET_POPCNTB /* ISA 2.02 */ \ | |
576 | || TARGET_CMPB /* ISA 2.05 */ \ | |
577 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
7042fe5e MM |
578 | || TARGET_XILINX_FPU) |
579 | ||
580 | #define TARGET_FCTIDZ TARGET_FCFID | |
581 | #define TARGET_STFIWX TARGET_PPC_GFXOPT | |
582 | #define TARGET_LFIWAX TARGET_CMPB | |
583 | #define TARGET_LFIWZX TARGET_POPCNTD | |
584 | #define TARGET_FCFIDS TARGET_POPCNTD | |
585 | #define TARGET_FCFIDU TARGET_POPCNTD | |
586 | #define TARGET_FCFIDUS TARGET_POPCNTD | |
587 | #define TARGET_FCTIDUZ TARGET_POPCNTD | |
588 | #define TARGET_FCTIWUZ TARGET_POPCNTD | |
0299bc72 MM |
589 | #define TARGET_CTZ TARGET_MODULO |
590 | #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) | |
dd551aa1 | 591 | #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) |
7042fe5e | 592 | |
f62511da MM |
593 | #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) |
594 | #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
a16a872d | 595 | #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) |
dd551aa1 MM |
596 | #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ |
597 | && TARGET_POWERPC64) | |
c5e74d9d | 598 | #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ |
6bd6f4f4 | 599 | && TARGET_POWERPC64) |
fba4b861 | 600 | |
fba4b861 MM |
601 | /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ |
602 | #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT | |
603 | #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) | |
604 | ||
87b44b83 AS |
605 | /* This wants to be set for p8 and newer. On p7, overlapping unaligned |
606 | loads are slow. */ | |
607 | #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX | |
f62511da MM |
608 | |
609 | /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present | |
610 | in power7, so conditionalize them on p8 features. TImode syncs need quad | |
611 | memory support. */ | |
b846c948 MM |
612 | #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ |
613 | || TARGET_QUAD_MEMORY_ATOMIC \ | |
614 | || TARGET_DIRECT_MOVE) | |
615 | ||
616 | #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC | |
f62511da | 617 | |
c6d5ff83 MM |
618 | /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need |
619 | to allocate the SDmode stack slot to get the value into the proper location | |
620 | in the register. */ | |
621 | #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) | |
622 | ||
21316320 MM |
623 | /* ISA 3.0 has new min/max functions that don't need fast math that are being |
624 | phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct | |
625 | answers if the arguments are not in the normal range. */ | |
626 | #define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \ | |
627 | && (TARGET_P9_MINMAX || !flag_trapping_math)) | |
628 | ||
629 | #define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \ | |
630 | && (TARGET_P9_MINMAX || !flag_trapping_math)) | |
631 | ||
4d967549 MM |
632 | /* In switching from using target_flags to using rs6000_isa_flags, the options |
633 | machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map | |
634 | OPTION_MASK_<xxx> back into MASK_<xxx>. */ | |
635 | #define MASK_ALTIVEC OPTION_MASK_ALTIVEC | |
636 | #define MASK_CMPB OPTION_MASK_CMPB | |
f62511da | 637 | #define MASK_CRYPTO OPTION_MASK_CRYPTO |
4d967549 | 638 | #define MASK_DFP OPTION_MASK_DFP |
f62511da | 639 | #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE |
4d967549 MM |
640 | #define MASK_DLMZB OPTION_MASK_DLMZB |
641 | #define MASK_EABI OPTION_MASK_EABI | |
bbd35101 | 642 | #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD |
4d967549 | 643 | #define MASK_FPRND OPTION_MASK_FPRND |
f62511da | 644 | #define MASK_P8_FUSION OPTION_MASK_P8_FUSION |
4d967549 | 645 | #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT |
0258b6e4 | 646 | #define MASK_HTM OPTION_MASK_HTM |
4d967549 MM |
647 | #define MASK_ISEL OPTION_MASK_ISEL |
648 | #define MASK_MFCRF OPTION_MASK_MFCRF | |
649 | #define MASK_MFPGPR OPTION_MASK_MFPGPR | |
650 | #define MASK_MULHW OPTION_MASK_MULHW | |
651 | #define MASK_MULTIPLE OPTION_MASK_MULTIPLE | |
652 | #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE | |
f62511da | 653 | #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR |
8fa97501 | 654 | #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR |
5a3a6a5e | 655 | #define MASK_P9_MISC OPTION_MASK_P9_MISC |
4d967549 MM |
656 | #define MASK_POPCNTB OPTION_MASK_POPCNTB |
657 | #define MASK_POPCNTD OPTION_MASK_POPCNTD | |
658 | #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT | |
659 | #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT | |
660 | #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION | |
661 | #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT | |
662 | #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN | |
663 | #define MASK_STRING OPTION_MASK_STRING | |
664 | #define MASK_UPDATE OPTION_MASK_UPDATE | |
665 | #define MASK_VSX OPTION_MASK_VSX | |
666 | ||
667 | #ifndef IN_LIBGCC2 | |
668 | #define MASK_POWERPC64 OPTION_MASK_POWERPC64 | |
669 | #endif | |
670 | ||
671 | #ifdef TARGET_64BIT | |
672 | #define MASK_64BIT OPTION_MASK_64BIT | |
673 | #endif | |
674 | ||
4d967549 MM |
675 | #ifdef TARGET_LITTLE_ENDIAN |
676 | #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN | |
677 | #endif | |
678 | ||
4d967549 MM |
679 | #ifdef TARGET_REGNAMES |
680 | #define MASK_REGNAMES OPTION_MASK_REGNAMES | |
681 | #endif | |
682 | ||
683 | #ifdef TARGET_PROTOTYPE | |
684 | #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE | |
685 | #endif | |
686 | ||
4f45da44 KN |
687 | #ifdef TARGET_MODULO |
688 | #define RS6000_BTM_MODULO OPTION_MASK_MODULO | |
689 | #endif | |
690 | ||
691 | ||
7fa14a01 MM |
692 | /* For power systems, we want to enable Altivec and VSX builtins even if the |
693 | user did not use -maltivec or -mvsx to allow the builtins to be used inside | |
694 | of #pragma GCC target or the target attribute to change the code level for a | |
6ae036b3 SB |
695 | given system. The Paired builtins are only enabled if you configure the |
696 | compiler for those builtins, and those machines don't support altivec or | |
7fa14a01 MM |
697 | VSX. */ |
698 | ||
e075a6cc | 699 | #define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \ |
7fa14a01 | 700 | && ((TARGET_POWERPC64 \ |
c3f8384f | 701 | || TARGET_PPC_GPOPT /* 970/power4 */ \ |
7fa14a01 MM |
702 | || TARGET_POPCNTB /* ISA 2.02 */ \ |
703 | || TARGET_CMPB /* ISA 2.05 */ \ | |
704 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
705 | || TARGET_ALTIVEC \ | |
f93bc5b3 PB |
706 | || TARGET_VSX \ |
707 | || TARGET_HARD_FLOAT))) | |
7fa14a01 | 708 | |
a7c6c6d6 OH |
709 | /* E500 cores only support plain "sync", not lwsync. */ |
710 | #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | |
711 | || rs6000_cpu == PROCESSOR_PPC8548) | |
7fa14a01 MM |
712 | |
713 | ||
026c3cfd | 714 | /* Whether SF/DF operations are supported by the normal floating point unit |
0609bdf2 | 715 | (or the vector/scalar unit). */ |
11d8d07e SB |
716 | #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT) |
717 | #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) | |
0609bdf2 MM |
718 | |
719 | /* Whether SF/DF operations are supported by any hardware. */ | |
11d8d07e SB |
720 | #define TARGET_SF_INSN TARGET_SF_FPR |
721 | #define TARGET_DF_INSN TARGET_DF_FPR | |
0609bdf2 | 722 | |
92902797 MM |
723 | /* Which machine supports the various reciprocal estimate instructions. */ |
724 | #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ | |
11d8d07e | 725 | && TARGET_SINGLE_FLOAT) |
92902797 | 726 | |
11d8d07e | 727 | #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ |
92902797 MM |
728 | && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) |
729 | ||
730 | #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ | |
11d8d07e | 731 | && TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT) |
92902797 | 732 | |
11d8d07e | 733 | #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ |
92902797 MM |
734 | && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) |
735 | ||
0299bc72 MM |
736 | /* Conditions to allow TOC fusion for loading/storing integers. */ |
737 | #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \ | |
738 | && TARGET_TOC_FUSION \ | |
739 | && (TARGET_CMODEL != CMODEL_SMALL) \ | |
740 | && TARGET_POWERPC64) | |
741 | ||
742 | /* Conditions to allow TOC fusion for loading/storing floating point. */ | |
743 | #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \ | |
744 | && TARGET_TOC_FUSION \ | |
745 | && (TARGET_CMODEL != CMODEL_SMALL) \ | |
746 | && TARGET_POWERPC64 \ | |
747 | && TARGET_HARD_FLOAT \ | |
0299bc72 MM |
748 | && TARGET_SINGLE_FLOAT \ |
749 | && TARGET_DOUBLE_FLOAT) | |
750 | ||
6019c0fc MM |
751 | /* Macro to say whether we can do optimizations where we need to do parts of |
752 | the calculation in 64-bit GPRs and then is transfered to the vector | |
753 | registers. Do not allow -maltivec=be for these optimizations, because it | |
754 | adds to the complexity of the code. */ | |
e0d32185 MM |
755 | #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ |
756 | && TARGET_P8_VECTOR \ | |
757 | && TARGET_POWERPC64 \ | |
6019c0fc | 758 | && (rs6000_altivec_element_order != 2)) |
e0d32185 | 759 | |
92902797 MM |
760 | /* Whether the various reciprocal divide/square root estimate instructions |
761 | exist, and whether we should automatically generate code for the instruction | |
762 | by default. */ | |
763 | #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ | |
764 | #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ | |
765 | #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ | |
766 | #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ | |
767 | ||
768 | extern unsigned char rs6000_recip_bits[]; | |
769 | ||
770 | #define RS6000_RECIP_HAVE_RE_P(MODE) \ | |
771 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) | |
772 | ||
773 | #define RS6000_RECIP_AUTO_RE_P(MODE) \ | |
774 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) | |
775 | ||
776 | #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ | |
777 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) | |
778 | ||
779 | #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ | |
780 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) | |
781 | ||
c5387660 JM |
782 | /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
783 | #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT | |
f045b2c9 | 784 | |
a5c76ee6 | 785 | /* Target pragma. */ |
c58b209a NB |
786 | #define REGISTER_TARGET_PRAGMAS() do { \ |
787 | c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
fd438373 | 788 | targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
2fab365e | 789 | targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
7fa14a01 | 790 | rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ |
a5c76ee6 ZW |
791 | } while (0) |
792 | ||
4c4eb375 GK |
793 | /* Target #defines. */ |
794 | #define TARGET_CPU_CPP_BUILTINS() \ | |
795 | rs6000_cpu_cpp_builtins (pfile) | |
647d340d JT |
796 | |
797 | /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
798 | we're compiling for. Some configurations may need to override it. */ | |
799 | #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
800 | do \ | |
801 | { \ | |
802 | if (BYTES_BIG_ENDIAN) \ | |
803 | { \ | |
804 | builtin_define ("__BIG_ENDIAN__"); \ | |
805 | builtin_define ("_BIG_ENDIAN"); \ | |
806 | builtin_assert ("machine=bigendian"); \ | |
807 | } \ | |
808 | else \ | |
809 | { \ | |
810 | builtin_define ("__LITTLE_ENDIAN__"); \ | |
811 | builtin_define ("_LITTLE_ENDIAN"); \ | |
812 | builtin_assert ("machine=littleendian"); \ | |
813 | } \ | |
814 | } \ | |
815 | while (0) | |
f045b2c9 | 816 | \f |
4c4eb375 | 817 | /* Target machine storage layout. */ |
f045b2c9 | 818 | |
13d39dbc | 819 | /* Define this macro if it is advisable to hold scalars in registers |
c81bebd7 | 820 | in a wider mode than that declared by the program. In such cases, |
ef457bda RK |
821 | the value is constrained to be within the bounds of the declared |
822 | type, but kept valid in the wider mode. The signedness of the | |
823 | extension may differ from that of the type. */ | |
824 | ||
39403d82 DE |
825 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
826 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
96922e4c | 827 | && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ |
b78d48dd | 828 | (MODE) = TARGET_32BIT ? SImode : DImode; |
39403d82 | 829 | |
f045b2c9 | 830 | /* Define this if most significant bit is lowest numbered |
82e41834 KH |
831 | in instructions that operate on numbered bit-fields. */ |
832 | /* That is true on RS/6000. */ | |
f045b2c9 RS |
833 | #define BITS_BIG_ENDIAN 1 |
834 | ||
835 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
836 | /* That is true on RS/6000. */ | |
837 | #define BYTES_BIG_ENDIAN 1 | |
838 | ||
839 | /* Define this if most significant word of a multiword number is lowest | |
c81bebd7 | 840 | numbered. |
f045b2c9 RS |
841 | |
842 | For RS/6000 we can decide arbitrarily since there are no machine | |
82e41834 | 843 | instructions for them. Might as well be consistent with bits and bytes. */ |
f045b2c9 RS |
844 | #define WORDS_BIG_ENDIAN 1 |
845 | ||
50751417 AM |
846 | /* This says that for the IBM long double the larger magnitude double |
847 | comes first. It's really a two element double array, and arrays | |
848 | don't index differently between little- and big-endian. */ | |
849 | #define LONG_DOUBLE_LARGE_FIRST 1 | |
850 | ||
2e360ab3 | 851 | #define MAX_BITS_PER_WORD 64 |
f045b2c9 RS |
852 | |
853 | /* Width of a word, in units (bytes). */ | |
c1aa3958 | 854 | #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) |
f34fc46e DE |
855 | #ifdef IN_LIBGCC2 |
856 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
857 | #else | |
ef0e53ce | 858 | #define MIN_UNITS_PER_WORD 4 |
f34fc46e | 859 | #endif |
2e360ab3 | 860 | #define UNITS_PER_FP_WORD 8 |
0ac081f6 | 861 | #define UNITS_PER_ALTIVEC_WORD 16 |
cacf1ca8 | 862 | #define UNITS_PER_VSX_WORD 16 |
96038623 | 863 | #define UNITS_PER_PAIRED_WORD 8 |
f045b2c9 | 864 | |
915f619f JW |
865 | /* Type used for ptrdiff_t, as a string used in a declaration. */ |
866 | #define PTRDIFF_TYPE "int" | |
867 | ||
058ef853 DE |
868 | /* Type used for size_t, as a string used in a declaration. */ |
869 | #define SIZE_TYPE "long unsigned int" | |
870 | ||
f045b2c9 RS |
871 | /* Type used for wchar_t, as a string used in a declaration. */ |
872 | #define WCHAR_TYPE "short unsigned int" | |
873 | ||
874 | /* Width of wchar_t in bits. */ | |
875 | #define WCHAR_TYPE_SIZE 16 | |
876 | ||
9e654916 RK |
877 | /* A C expression for the size in bits of the type `short' on the |
878 | target machine. If you don't define this, the default is half a | |
879 | word. (If this would be less than one storage unit, it is | |
880 | rounded up to one unit.) */ | |
881 | #define SHORT_TYPE_SIZE 16 | |
882 | ||
883 | /* A C expression for the size in bits of the type `int' on the | |
884 | target machine. If you don't define this, the default is one | |
885 | word. */ | |
19d2d16f | 886 | #define INT_TYPE_SIZE 32 |
9e654916 RK |
887 | |
888 | /* A C expression for the size in bits of the type `long' on the | |
889 | target machine. If you don't define this, the default is one | |
890 | word. */ | |
2f3e5814 | 891 | #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) |
9e654916 RK |
892 | |
893 | /* A C expression for the size in bits of the type `long long' on the | |
894 | target machine. If you don't define this, the default is two | |
895 | words. */ | |
896 | #define LONG_LONG_TYPE_SIZE 64 | |
897 | ||
9e654916 RK |
898 | /* A C expression for the size in bits of the type `float' on the |
899 | target machine. If you don't define this, the default is one | |
900 | word. */ | |
901 | #define FLOAT_TYPE_SIZE 32 | |
902 | ||
903 | /* A C expression for the size in bits of the type `double' on the | |
904 | target machine. If you don't define this, the default is two | |
905 | words. */ | |
906 | #define DOUBLE_TYPE_SIZE 64 | |
907 | ||
908 | /* A C expression for the size in bits of the type `long double' on | |
909 | the target machine. If you don't define this, the default is two | |
910 | words. */ | |
6fa3f289 | 911 | #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
06f4e019 | 912 | |
5b8f5865 DE |
913 | /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ |
914 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
915 | ||
f045b2c9 RS |
916 | /* Width in bits of a pointer. |
917 | See also the macro `Pmode' defined below. */ | |
cacf1ca8 MM |
918 | extern unsigned rs6000_pointer_size; |
919 | #define POINTER_SIZE rs6000_pointer_size | |
f045b2c9 RS |
920 | |
921 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
2f3e5814 | 922 | #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
923 | |
924 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
cacf1ca8 MM |
925 | #define STACK_BOUNDARY \ |
926 | ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ | |
927 | ? 64 : 128) | |
f045b2c9 RS |
928 | |
929 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
930 | #define FUNCTION_BOUNDARY 32 | |
931 | ||
932 | /* No data type wants to be aligned rounder than this. */ | |
0ac081f6 AH |
933 | #define BIGGEST_ALIGNMENT 128 |
934 | ||
f045b2c9 RS |
935 | /* Alignment of field after `int : 0' in a structure. */ |
936 | #define EMPTY_FIELD_BOUNDARY 32 | |
937 | ||
938 | /* Every structure's size must be a multiple of this. */ | |
939 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
940 | ||
43a88a8c | 941 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
f045b2c9 RS |
942 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
943 | ||
69eff9da AM |
944 | enum data_align { align_abi, align_opt, align_both }; |
945 | ||
946 | /* A C expression to compute the alignment for a variables in the | |
947 | local store. TYPE is the data type, and ALIGN is the alignment | |
948 | that the object would ordinarily have. */ | |
949 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
950 | rs6000_data_alignment (TYPE, ALIGN, align_both) | |
951 | ||
952 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
69ef87e2 AH |
953 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
954 | (TREE_CODE (EXP) == STRING_CST \ | |
153fbec8 | 955 | && (STRICT_ALIGNMENT || !optimize_size) \ |
69ef87e2 AH |
956 | && (ALIGN) < BITS_PER_WORD \ |
957 | ? BITS_PER_WORD \ | |
958 | : (ALIGN)) | |
f045b2c9 | 959 | |
69eff9da AM |
960 | /* Make arrays of chars word-aligned for the same reasons. */ |
961 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
962 | rs6000_data_alignment (TYPE, ALIGN, align_opt) | |
963 | ||
e075a6cc | 964 | /* Align vectors to 128 bits. */ |
69eff9da AM |
965 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ |
966 | rs6000_data_alignment (TYPE, ALIGN, align_abi) | |
f045b2c9 | 967 | |
a0ab749a | 968 | /* Nonzero if move instructions will actually fail to work |
f045b2c9 | 969 | when given unaligned data. */ |
fdaff8ba | 970 | #define STRICT_ALIGNMENT 0 |
f045b2c9 RS |
971 | \f |
972 | /* Standard register usage. */ | |
973 | ||
974 | /* Number of actual hardware registers. | |
975 | The hardware registers are assigned numbers for the compiler | |
976 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
977 | All registers that the compiler knows about must be given numbers, | |
978 | even those that are not normally considered general registers. | |
979 | ||
980 | RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
462f7901 SB |
981 | a count register, a link register, and 8 condition register fields, |
982 | which we view here as separate registers. AltiVec adds 32 vector | |
983 | registers and a VRsave register. | |
f045b2c9 RS |
984 | |
985 | In addition, the difference between the frame and argument pointers is | |
986 | a function of the number of registers saved, so we need to have a | |
987 | register for AP that will later be eliminated in favor of SP or FP. | |
802a0058 | 988 | This is a normal register, but it is fixed. |
f045b2c9 | 989 | |
802a0058 MM |
990 | We also create a pseudo register for float/int conversions, that will |
991 | really represent the memory location used. It is represented here as | |
992 | a register, in order to work around problems in allocating stack storage | |
7d5175e1 | 993 | in inline functions. |
802a0058 | 994 | |
7d5175e1 | 995 | Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame |
7a5add18 PB |
996 | pointer, which is eventually eliminated in favor of SP or FP. |
997 | ||
998 | The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ | |
7d5175e1 | 999 | |
346081bd | 1000 | #define FIRST_PSEUDO_REGISTER 115 |
f045b2c9 | 1001 | |
d6a7951f | 1002 | /* This must be included for pre gcc 3.0 glibc compatibility. */ |
7d5f33bc | 1003 | #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 |
62153b61 | 1004 | |
e075a6cc | 1005 | /* The sfp register and 3 HTM registers |
23742a9e RAR |
1006 | aren't included in DWARF_FRAME_REGISTERS. */ |
1007 | #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) | |
c19de7aa | 1008 | |
ed1cf8ff | 1009 | /* Use standard DWARF numbering for DWARF debugging information. */ |
3d36d470 | 1010 | #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) |
ed1cf8ff | 1011 | |
93c9d1ba | 1012 | /* Use gcc hard register numbering for eh_frame. */ |
3d36d470 | 1013 | #define DWARF_FRAME_REGNUM(REGNO) (REGNO) |
41f3a930 | 1014 | |
ed1cf8ff GK |
1015 | /* Map register numbers held in the call frame info that gcc has |
1016 | collected using DWARF_FRAME_REGNUM to those that should be output in | |
3d36d470 UW |
1017 | .debug_frame and .eh_frame. */ |
1018 | #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
1019 | rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1) | |
ed1cf8ff | 1020 | |
f045b2c9 RS |
1021 | /* 1 for registers that have pervasive standard uses |
1022 | and are not available for the register allocator. | |
1023 | ||
5dead3e5 DJ |
1024 | On RS/6000, r1 is used for the stack. On Darwin, r2 is available |
1025 | as a local register; for all other OS's r2 is the TOC pointer. | |
f045b2c9 | 1026 | |
a127c4e5 RK |
1027 | On System V implementations, r13 is fixed and not available for use. */ |
1028 | ||
f045b2c9 | 1029 | #define FIXED_REGISTERS \ |
5dead3e5 | 1030 | {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
1031 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1032 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1033 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
36bd0c3e | 1034 | 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ |
0ac081f6 AH |
1035 | /* AltiVec registers. */ \ |
1036 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1037 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 1038 | 1, 1 \ |
346081bd | 1039 | , 1, 1, 1, 1 \ |
0ac081f6 | 1040 | } |
f045b2c9 RS |
1041 | |
1042 | /* 1 for registers not available across function calls. | |
1043 | These must include the FIXED_REGISTERS and also any | |
1044 | registers that can be used without being saved. | |
1045 | The latter must include the registers where values are returned | |
1046 | and the register where structure-value addresses are passed. | |
1047 | Aside from that, you can include as many other registers as you like. */ | |
1048 | ||
1049 | #define CALL_USED_REGISTERS \ | |
a127c4e5 | 1050 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
1051 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1052 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
1053 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
1054 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
1055 | /* AltiVec registers. */ \ | |
1056 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1057 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 1058 | 1, 1 \ |
346081bd | 1059 | , 1, 1, 1, 1 \ |
0ac081f6 AH |
1060 | } |
1061 | ||
289e96b2 AH |
1062 | /* Like `CALL_USED_REGISTERS' except this macro doesn't require that |
1063 | the entire set of `FIXED_REGISTERS' be included. | |
1064 | (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
1065 | This macro is optional. If not specified, it defaults to the value | |
1066 | of `CALL_USED_REGISTERS'. */ | |
f676971a | 1067 | |
289e96b2 AH |
1068 | #define CALL_REALLY_USED_REGISTERS \ |
1069 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
1070 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1071 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
1072 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0b390d60 | 1073 | 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
289e96b2 AH |
1074 | /* AltiVec registers. */ \ |
1075 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1076 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 1077 | 0, 0 \ |
346081bd | 1078 | , 0, 0, 0, 0 \ |
289e96b2 | 1079 | } |
f045b2c9 | 1080 | |
28bcfd4d | 1081 | #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) |
9ebbca7d | 1082 | |
d62294f5 | 1083 | #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) |
b427dd7a AM |
1084 | #define FIRST_SAVED_FP_REGNO (14+32) |
1085 | #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) | |
d62294f5 | 1086 | |
f045b2c9 RS |
1087 | /* List the order in which to allocate registers. Each register must be |
1088 | listed once, even those in FIXED_REGISTERS. | |
1089 | ||
1090 | We allocate in the following order: | |
1091 | fp0 (not saved or used for anything) | |
1092 | fp13 - fp2 (not saved; incoming fp arg registers) | |
1093 | fp1 (not saved; return value) | |
9390387d | 1094 | fp31 - fp14 (saved; order given to save least number) |
36bd0c3e SB |
1095 | cr7, cr5 (not saved or special) |
1096 | cr6 (not saved, but used for vector operations) | |
5accd822 | 1097 | cr1 (not saved, but used for FP operations) |
f045b2c9 | 1098 | cr0 (not saved, but used for arithmetic operations) |
5accd822 | 1099 | cr4, cr3, cr2 (saved) |
f045b2c9 | 1100 | r9 (not saved; best for TImode) |
d44b26bd | 1101 | r10, r8-r4 (not saved; highest first for less conflict with params) |
9390387d | 1102 | r3 (not saved; return value register) |
d44b26bd AM |
1103 | r11 (not saved; later alloc to help shrink-wrap) |
1104 | r0 (not saved; cannot be base reg) | |
f045b2c9 RS |
1105 | r31 - r13 (saved; order given to save least number) |
1106 | r12 (not saved; if used for DImode or DFmode would use r13) | |
f045b2c9 RS |
1107 | ctr (not saved; when we have the choice ctr is better) |
1108 | lr (saved) | |
36bd0c3e | 1109 | r1, r2, ap, ca (fixed) |
9390387d AM |
1110 | v0 - v1 (not saved or used for anything) |
1111 | v13 - v3 (not saved; incoming vector arg registers) | |
1112 | v2 (not saved; incoming vector arg reg; return value) | |
1113 | v19 - v14 (not saved or used for anything) | |
1114 | v31 - v20 (saved; order given to save least number) | |
1115 | vrsave, vscr (fixed) | |
7d5175e1 | 1116 | sfp (fixed) |
0258b6e4 PB |
1117 | tfhar (fixed) |
1118 | tfiar (fixed) | |
1119 | texasr (fixed) | |
0ac081f6 | 1120 | */ |
f676971a | 1121 | |
6b13641d DJ |
1122 | #if FIXED_R2 == 1 |
1123 | #define MAYBE_R2_AVAILABLE | |
1124 | #define MAYBE_R2_FIXED 2, | |
1125 | #else | |
1126 | #define MAYBE_R2_AVAILABLE 2, | |
1127 | #define MAYBE_R2_FIXED | |
1128 | #endif | |
f045b2c9 | 1129 | |
d44b26bd AM |
1130 | #if FIXED_R13 == 1 |
1131 | #define EARLY_R12 12, | |
1132 | #define LATE_R12 | |
1133 | #else | |
1134 | #define EARLY_R12 | |
1135 | #define LATE_R12 12, | |
1136 | #endif | |
1137 | ||
9390387d AM |
1138 | #define REG_ALLOC_ORDER \ |
1139 | {32, \ | |
f62511da MM |
1140 | /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ |
1141 | /* not use fr14 which is a saved register. */ \ | |
1142 | 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ | |
9390387d AM |
1143 | 33, \ |
1144 | 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
1145 | 50, 49, 48, 47, 46, \ | |
36bd0c3e | 1146 | 75, 73, 74, 69, 68, 72, 71, 70, \ |
d44b26bd AM |
1147 | MAYBE_R2_AVAILABLE \ |
1148 | 9, 10, 8, 7, 6, 5, 4, \ | |
1149 | 3, EARLY_R12 11, 0, \ | |
9390387d | 1150 | 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ |
d44b26bd | 1151 | 18, 17, 16, 15, 14, 13, LATE_R12 \ |
462f7901 | 1152 | 66, 65, \ |
36bd0c3e | 1153 | 1, MAYBE_R2_FIXED 67, 76, \ |
9390387d AM |
1154 | /* AltiVec registers. */ \ |
1155 | 77, 78, \ | |
1156 | 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
1157 | 79, \ | |
1158 | 96, 95, 94, 93, 92, 91, \ | |
1159 | 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ | |
1160 | 109, 110, \ | |
346081bd | 1161 | 111, 112, 113, 114 \ |
0ac081f6 | 1162 | } |
f045b2c9 RS |
1163 | |
1164 | /* True if register is floating-point. */ | |
1165 | #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
1166 | ||
1167 | /* True if register is a condition register. */ | |
1de43f85 | 1168 | #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) |
f045b2c9 | 1169 | |
815cdc52 | 1170 | /* True if register is a condition register, but not cr0. */ |
1de43f85 | 1171 | #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) |
815cdc52 | 1172 | |
f045b2c9 | 1173 | /* True if register is an integer register. */ |
7d5175e1 JJ |
1174 | #define INT_REGNO_P(N) \ |
1175 | ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
f045b2c9 | 1176 | |
96038623 DE |
1177 | /* PAIRED SIMD registers are just the FPRs. */ |
1178 | #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
1179 | ||
f6b5d695 SB |
1180 | /* True if register is the CA register. */ |
1181 | #define CA_REGNO_P(N) ((N) == CA_REGNO) | |
802a0058 | 1182 | |
0ac081f6 AH |
1183 | /* True if register is an AltiVec register. */ |
1184 | #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
1185 | ||
cacf1ca8 MM |
1186 | /* True if register is a VSX register. */ |
1187 | #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) | |
1188 | ||
1189 | /* Alternate name for any vector register supporting floating point, no matter | |
1190 | which instruction set(s) are available. */ | |
1191 | #define VFLOAT_REGNO_P(N) \ | |
1192 | (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) | |
1193 | ||
1194 | /* Alternate name for any vector register supporting integer, no matter which | |
1195 | instruction set(s) are available. */ | |
1196 | #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) | |
1197 | ||
1198 | /* Alternate name for any vector register supporting logical operations, no | |
dd7a40e1 MM |
1199 | matter which instruction set(s) are available. Allow GPRs as well as the |
1200 | vector registers. */ | |
f62511da | 1201 | #define VLOGICAL_REGNO_P(N) \ |
dd7a40e1 MM |
1202 | (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ |
1203 | || (TARGET_VSX && FP_REGNO_P (N))) \ | |
cacf1ca8 | 1204 | |
79eefb0d | 1205 | /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
5ec6aff2 MM |
1206 | enough space to account for vectors in FP regs. However, TFmode/TDmode |
1207 | should not use VSX instructions to do a caller save. */ | |
dbcc9f08 | 1208 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
90b725f0 PB |
1209 | ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ |
1210 | ? (MODE) \ | |
1211 | : TARGET_VSX \ | |
1212 | && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ | |
1213 | && FP_REGNO_P (REGNO) \ | |
5ec6aff2 | 1214 | ? V2DFmode \ |
f7c12ec4 | 1215 | : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ |
5ec6aff2 | 1216 | ? DFmode \ |
f7c12ec4 | 1217 | : (MODE) == TDmode && FP_REGNO_P (REGNO) \ |
5ec6aff2 | 1218 | ? DImode \ |
79eefb0d PH |
1219 | : choose_hard_reg_mode ((REGNO), (NREGS), false)) |
1220 | ||
cacf1ca8 MM |
1221 | #define VSX_VECTOR_MODE(MODE) \ |
1222 | ((MODE) == V4SFmode \ | |
1223 | || (MODE) == V2DFmode) \ | |
1224 | ||
bdb60a10 MM |
1225 | /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not |
1226 | really a vector, but we want to treat it as a vector for moves, and | |
1227 | such. */ | |
1228 | ||
1229 | #define ALTIVEC_VECTOR_MODE(MODE) \ | |
1230 | ((MODE) == V16QImode \ | |
1231 | || (MODE) == V8HImode \ | |
1232 | || (MODE) == V4SFmode \ | |
1233 | || (MODE) == V4SImode \ | |
1234 | || FLOAT128_VECTOR_P (MODE)) | |
0ac081f6 | 1235 | |
dbcc9f08 MM |
1236 | #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ |
1237 | (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ | |
a16a872d | 1238 | || (MODE) == V2DImode || (MODE) == V1TImode) |
dbcc9f08 | 1239 | |
96038623 DE |
1240 | #define PAIRED_VECTOR_MODE(MODE) \ |
1241 | ((MODE) == V2SFmode) | |
1242 | ||
c8ae788f SB |
1243 | /* Post-reload, we can't use any new AltiVec registers, as we already |
1244 | emitted the vrsave mask. */ | |
1245 | ||
1246 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
6fb5fa3c | 1247 | (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) |
c8ae788f | 1248 | |
f045b2c9 RS |
1249 | /* Specify the cost of a branch insn; roughly the number of extra insns that |
1250 | should be added to avoid a branch. | |
1251 | ||
ef457bda | 1252 | Set this to 3 on the RS/6000 since that is roughly the average cost of an |
f045b2c9 RS |
1253 | unscheduled conditional branch. */ |
1254 | ||
3a4fd356 | 1255 | #define BRANCH_COST(speed_p, predictable_p) 3 |
f045b2c9 | 1256 | |
85e50b6b | 1257 | /* Override BRANCH_COST heuristic which empirically produces worse |
b8610a53 | 1258 | performance for removing short circuiting from the logical ops. */ |
85e50b6b | 1259 | |
b8610a53 | 1260 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 |
a3170dc6 | 1261 | |
f045b2c9 RS |
1262 | /* Specify the registers used for certain standard purposes. |
1263 | The values of these macros are register numbers. */ | |
1264 | ||
1265 | /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
1266 | /* #define PC_REGNUM */ | |
1267 | ||
1268 | /* Register to use for pushing function arguments. */ | |
1269 | #define STACK_POINTER_REGNUM 1 | |
1270 | ||
1271 | /* Base register for access to local variables of the function. */ | |
7d5175e1 JJ |
1272 | #define HARD_FRAME_POINTER_REGNUM 31 |
1273 | ||
1274 | /* Base register for access to local variables of the function. */ | |
346081bd | 1275 | #define FRAME_POINTER_REGNUM 111 |
f045b2c9 | 1276 | |
f045b2c9 RS |
1277 | /* Base register for access to arguments of the function. */ |
1278 | #define ARG_POINTER_REGNUM 67 | |
1279 | ||
1280 | /* Place to put static chain when calling a function that requires it. */ | |
1281 | #define STATIC_CHAIN_REGNUM 11 | |
1282 | ||
26a2e6ae PB |
1283 | /* Base register for access to thread local storage variables. */ |
1284 | #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) | |
1285 | ||
f045b2c9 RS |
1286 | \f |
1287 | /* Define the classes of registers for register constraints in the | |
1288 | machine description. Also define ranges of constants. | |
1289 | ||
1290 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1291 | If there is more than one class, another class must be named NO_REGS | |
1292 | and contain no registers. | |
1293 | ||
1294 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1295 | another name such as ALL_REGS). This is the class of registers | |
1296 | that is allowed by "g" or "r" in a register constraint. | |
1297 | Also, registers outside this class are allocated only when | |
1298 | instructions express preferences for them. | |
1299 | ||
1300 | The classes must be numbered in nondecreasing order; that is, | |
1301 | a larger-numbered class must never be contained completely | |
1302 | in a smaller-numbered class. | |
1303 | ||
1304 | For any two classes, it is very desirable that there be another | |
1305 | class that represents their union. */ | |
c81bebd7 | 1306 | |
cacf1ca8 | 1307 | /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
462f7901 | 1308 | condition registers, plus three special registers, CTR, and the link |
cacf1ca8 MM |
1309 | register. AltiVec adds a vector register class. VSX registers overlap the |
1310 | FPR registers and the Altivec registers. | |
f045b2c9 RS |
1311 | |
1312 | However, r0 is special in that it cannot be used as a base register. | |
1313 | So make a class for registers valid as base registers. | |
1314 | ||
1315 | Also, cr0 is the only condition code register that can be used in | |
0d86f538 | 1316 | arithmetic insns, so make a separate class for it. */ |
f045b2c9 | 1317 | |
ebedb4dd MM |
1318 | enum reg_class |
1319 | { | |
1320 | NO_REGS, | |
ebedb4dd MM |
1321 | BASE_REGS, |
1322 | GENERAL_REGS, | |
1323 | FLOAT_REGS, | |
0ac081f6 | 1324 | ALTIVEC_REGS, |
8beb65e3 | 1325 | VSX_REGS, |
0ac081f6 | 1326 | VRSAVE_REGS, |
5f004351 | 1327 | VSCR_REGS, |
0258b6e4 | 1328 | SPR_REGS, |
ebedb4dd | 1329 | NON_SPECIAL_REGS, |
ebedb4dd MM |
1330 | LINK_REGS, |
1331 | CTR_REGS, | |
1332 | LINK_OR_CTR_REGS, | |
1333 | SPECIAL_REGS, | |
1334 | SPEC_OR_GEN_REGS, | |
1335 | CR0_REGS, | |
ebedb4dd MM |
1336 | CR_REGS, |
1337 | NON_FLOAT_REGS, | |
f6b5d695 | 1338 | CA_REGS, |
ebedb4dd MM |
1339 | ALL_REGS, |
1340 | LIM_REG_CLASSES | |
1341 | }; | |
f045b2c9 RS |
1342 | |
1343 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1344 | ||
82e41834 | 1345 | /* Give names of register classes as strings for dump file. */ |
f045b2c9 | 1346 | |
ebedb4dd MM |
1347 | #define REG_CLASS_NAMES \ |
1348 | { \ | |
1349 | "NO_REGS", \ | |
ebedb4dd MM |
1350 | "BASE_REGS", \ |
1351 | "GENERAL_REGS", \ | |
1352 | "FLOAT_REGS", \ | |
0ac081f6 | 1353 | "ALTIVEC_REGS", \ |
8beb65e3 | 1354 | "VSX_REGS", \ |
0ac081f6 | 1355 | "VRSAVE_REGS", \ |
5f004351 | 1356 | "VSCR_REGS", \ |
0258b6e4 | 1357 | "SPR_REGS", \ |
ebedb4dd | 1358 | "NON_SPECIAL_REGS", \ |
ebedb4dd MM |
1359 | "LINK_REGS", \ |
1360 | "CTR_REGS", \ | |
1361 | "LINK_OR_CTR_REGS", \ | |
1362 | "SPECIAL_REGS", \ | |
1363 | "SPEC_OR_GEN_REGS", \ | |
1364 | "CR0_REGS", \ | |
ebedb4dd MM |
1365 | "CR_REGS", \ |
1366 | "NON_FLOAT_REGS", \ | |
f6b5d695 | 1367 | "CA_REGS", \ |
ebedb4dd MM |
1368 | "ALL_REGS" \ |
1369 | } | |
f045b2c9 RS |
1370 | |
1371 | /* Define which registers fit in which classes. | |
1372 | This is an initializer for a vector of HARD_REG_SET | |
1373 | of length N_REG_CLASSES. */ | |
1374 | ||
23742a9e RAR |
1375 | #define REG_CLASS_CONTENTS \ |
1376 | { \ | |
1377 | /* NO_REGS. */ \ | |
3e2bca2e | 1378 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ |
23742a9e | 1379 | /* BASE_REGS. */ \ |
346081bd | 1380 | { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \ |
23742a9e | 1381 | /* GENERAL_REGS. */ \ |
346081bd | 1382 | { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \ |
23742a9e | 1383 | /* FLOAT_REGS. */ \ |
3e2bca2e | 1384 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ |
23742a9e | 1385 | /* ALTIVEC_REGS. */ \ |
3e2bca2e | 1386 | { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \ |
23742a9e | 1387 | /* VSX_REGS. */ \ |
3e2bca2e | 1388 | { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \ |
23742a9e | 1389 | /* VRSAVE_REGS. */ \ |
3e2bca2e | 1390 | { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ |
23742a9e | 1391 | /* VSCR_REGS. */ \ |
3e2bca2e | 1392 | { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \ |
23742a9e | 1393 | /* SPR_REGS. */ \ |
346081bd | 1394 | { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \ |
23742a9e | 1395 | /* NON_SPECIAL_REGS. */ \ |
346081bd | 1396 | { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \ |
23742a9e | 1397 | /* LINK_REGS. */ \ |
3e2bca2e | 1398 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \ |
23742a9e | 1399 | /* CTR_REGS. */ \ |
3e2bca2e | 1400 | { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \ |
23742a9e | 1401 | /* LINK_OR_CTR_REGS. */ \ |
3e2bca2e | 1402 | { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \ |
23742a9e | 1403 | /* SPECIAL_REGS. */ \ |
3e2bca2e | 1404 | { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \ |
23742a9e | 1405 | /* SPEC_OR_GEN_REGS. */ \ |
346081bd | 1406 | { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \ |
23742a9e | 1407 | /* CR0_REGS. */ \ |
3e2bca2e | 1408 | { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \ |
23742a9e | 1409 | /* CR_REGS. */ \ |
3e2bca2e | 1410 | { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \ |
23742a9e | 1411 | /* NON_FLOAT_REGS. */ \ |
346081bd | 1412 | { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \ |
23742a9e | 1413 | /* CA_REGS. */ \ |
3e2bca2e | 1414 | { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \ |
23742a9e | 1415 | /* ALL_REGS. */ \ |
346081bd | 1416 | { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \ |
ebedb4dd | 1417 | } |
f045b2c9 RS |
1418 | |
1419 | /* The same information, inverted: | |
1420 | Return the class number of the smallest class containing | |
1421 | reg number REGNO. This could be a conditional expression | |
1422 | or could index an array. */ | |
1423 | ||
cacf1ca8 MM |
1424 | extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
1425 | ||
cacf1ca8 | 1426 | #define REGNO_REG_CLASS(REGNO) \ |
e28c2052 | 1427 | (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ |
cacf1ca8 MM |
1428 | rs6000_regno_regclass[(REGNO)]) |
1429 | ||
a72c65c7 MM |
1430 | /* Register classes for various constraints that are based on the target |
1431 | switches. */ | |
1432 | enum r6000_reg_class_enum { | |
1433 | RS6000_CONSTRAINT_d, /* fpr registers for double values */ | |
1434 | RS6000_CONSTRAINT_f, /* fpr registers for single values */ | |
1435 | RS6000_CONSTRAINT_v, /* Altivec registers */ | |
1436 | RS6000_CONSTRAINT_wa, /* Any VSX register */ | |
d5906efc | 1437 | RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */ |
a72c65c7 | 1438 | RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ |
dd551aa1 | 1439 | RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ |
a72c65c7 | 1440 | RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ |
5e8586d7 | 1441 | RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ |
59f5868d MM |
1442 | RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ |
1443 | RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ | |
1444 | RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ | |
1445 | RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ | |
c6d5ff83 | 1446 | RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ |
f62511da | 1447 | RS6000_CONSTRAINT_wm, /* VSX register for direct move */ |
4e8a3a35 | 1448 | RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */ |
c477a667 MM |
1449 | RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ |
1450 | RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ | |
f62511da | 1451 | RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ |
a72c65c7 | 1452 | RS6000_CONSTRAINT_ws, /* VSX register for DF */ |
c6d5ff83 | 1453 | RS6000_CONSTRAINT_wt, /* VSX register for TImode */ |
5e8586d7 MM |
1454 | RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */ |
1455 | RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ | |
1456 | RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ | |
c6d5ff83 | 1457 | RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ |
5e8586d7 | 1458 | RS6000_CONSTRAINT_wy, /* VSX register for SF */ |
c6d5ff83 | 1459 | RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ |
99211352 | 1460 | RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ |
787c7a65 MM |
1461 | RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */ |
1462 | RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */ | |
1463 | RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */ | |
1464 | RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */ | |
a72c65c7 MM |
1465 | RS6000_CONSTRAINT_MAX |
1466 | }; | |
1467 | ||
1468 | extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; | |
f045b2c9 RS |
1469 | |
1470 | /* The class value for index registers, and the one for base regs. */ | |
1471 | #define INDEX_REG_CLASS GENERAL_REGS | |
1472 | #define BASE_REG_CLASS BASE_REGS | |
1473 | ||
cacf1ca8 MM |
1474 | /* Return whether a given register class can hold VSX objects. */ |
1475 | #define VSX_REG_CLASS_P(CLASS) \ | |
1476 | ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) | |
1477 | ||
59f5868d MM |
1478 | /* Return whether a given register class targets general purpose registers. */ |
1479 | #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) | |
1480 | ||
f045b2c9 RS |
1481 | /* Given an rtx X being reloaded into a reg required to be |
1482 | in class CLASS, return the class of reg to actually use. | |
1483 | In general this is just CLASS; but on some machines | |
c81bebd7 | 1484 | in some cases it is preferable to use a more restrictive class. |
f045b2c9 RS |
1485 | |
1486 | On the RS/6000, we have to return NO_REGS when we want to reload a | |
f676971a | 1487 | floating-point CONST_DOUBLE to force it to be copied to memory. |
1e66d555 GK |
1488 | |
1489 | We also don't want to reload integer values into floating-point | |
1490 | registers if we can at all help it. In fact, this can | |
37409796 | 1491 | cause reload to die, if it tries to generate a reload of CTR |
1e66d555 GK |
1492 | into a FP register and discovers it doesn't have the memory location |
1493 | required. | |
1494 | ||
1495 | ??? Would it be a good idea to have reload do the converse, that is | |
1496 | try to reload floating modes into FP registers if possible? | |
1497 | */ | |
f045b2c9 | 1498 | |
802a0058 | 1499 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
8beb65e3 | 1500 | rs6000_preferred_reload_class_ptr (X, CLASS) |
c81bebd7 | 1501 | |
f045b2c9 RS |
1502 | /* Return the register class of a scratch register needed to copy IN into |
1503 | or out of a register in CLASS in MODE. If it can be done directly, | |
1504 | NO_REGS is returned. */ | |
1505 | ||
1506 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
8beb65e3 | 1507 | rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
f045b2c9 | 1508 | |
0ac081f6 | 1509 | /* If we are copying between FP or AltiVec registers and anything |
44cd321e PS |
1510 | else, we need a memory location. The exception is when we are |
1511 | targeting ppc64 and the move to/from fpr to gpr instructions | |
1512 | are available.*/ | |
1513 | ||
1514 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ | |
8beb65e3 | 1515 | rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE) |
7ea555a4 | 1516 | |
01b1efaa VM |
1517 | /* Specify the mode to be used for memory when a secondary memory |
1518 | location is needed. For cpus that cannot load/store SDmode values | |
1519 | from the 64-bit FP registers without using a full 64-bit | |
1520 | load/store, we need a wider mode. */ | |
1521 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1522 | rs6000_secondary_memory_needed_mode (MODE) | |
1523 | ||
f045b2c9 RS |
1524 | /* Return the maximum number of consecutive registers |
1525 | needed to represent mode MODE in a register of class CLASS. | |
1526 | ||
cacf1ca8 MM |
1527 | On RS/6000, this is the size of MODE in words, except in the FP regs, where |
1528 | a single reg is enough for two words, unless we have VSX, where the FP | |
1529 | registers can hold 128 bits. */ | |
1530 | #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] | |
580d3230 | 1531 | |
ca0e79d9 AM |
1532 | /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ |
1533 | ||
1534 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
8beb65e3 | 1535 | rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS) |
02188693 | 1536 | |
f045b2c9 RS |
1537 | /* Stack layout; function entry, exit and calling. */ |
1538 | ||
1539 | /* Define this if pushing a word on the stack | |
1540 | makes the stack pointer a smaller address. */ | |
62f9f30b | 1541 | #define STACK_GROWS_DOWNWARD 1 |
f045b2c9 | 1542 | |
327e5343 FJ |
1543 | /* Offsets recorded in opcodes are a multiple of this alignment factor. */ |
1544 | #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
1545 | ||
a4d05547 | 1546 | /* Define this to nonzero if the nominal address of the stack frame |
f045b2c9 RS |
1547 | is at the high-address end of the local variables; |
1548 | that is, each additional local variable allocated | |
1549 | goes at a more negative offset in the frame. | |
1550 | ||
1551 | On the RS/6000, we grow upwards, from the area after the outgoing | |
1552 | arguments. */ | |
de5a5fa1 MP |
1553 | #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ |
1554 | || (flag_sanitize & SANITIZE_ADDRESS) != 0) | |
f045b2c9 | 1555 | |
4697a36c | 1556 | /* Size of the fixed area on the stack */ |
9ebbca7d | 1557 | #define RS6000_SAVE_AREA \ |
b54214fe UW |
1558 | ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ |
1559 | << (TARGET_64BIT ? 1 : 0)) | |
4697a36c | 1560 | |
b54214fe UW |
1561 | /* Stack offset for toc save slot. */ |
1562 | #define RS6000_TOC_SAVE_SLOT \ | |
1563 | ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) | |
b6c9286a | 1564 | |
4697a36c | 1565 | /* Align an address */ |
4f59f9f2 | 1566 | #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) |
4697a36c | 1567 | |
f045b2c9 RS |
1568 | /* Offset within stack frame to start allocating local variables at. |
1569 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1570 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
c81bebd7 | 1571 | of the first local allocated. |
f045b2c9 RS |
1572 | |
1573 | On the RS/6000, the frame pointer is the same as the stack pointer, | |
1574 | except for dynamic allocations. So we start after the fixed area and | |
a7790c71 DV |
1575 | outgoing parameter area. |
1576 | ||
1577 | If the function uses dynamic stack space (CALLS_ALLOCA is set), that | |
1578 | space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the | |
1579 | sizes of the fixed area and the parameter area must be a multiple of | |
1580 | STACK_BOUNDARY. */ | |
f045b2c9 | 1581 | |
802a0058 | 1582 | #define STARTING_FRAME_OFFSET \ |
7d5175e1 JJ |
1583 | (FRAME_GROWS_DOWNWARD \ |
1584 | ? 0 \ | |
a7790c71 DV |
1585 | : (cfun->calls_alloca \ |
1586 | ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ | |
1587 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ | |
1588 | : (RS6000_ALIGN (crtl->outgoing_args_size, \ | |
1589 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ | |
1590 | + RS6000_SAVE_AREA))) | |
802a0058 MM |
1591 | |
1592 | /* Offset from the stack pointer register to an item dynamically | |
1593 | allocated on the stack, e.g., by `alloca'. | |
1594 | ||
1595 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1596 | length of the outgoing arguments. The default is correct for most | |
a7790c71 DV |
1597 | machines. See `function.c' for details. |
1598 | ||
1599 | This value must be a multiple of STACK_BOUNDARY (hard coded in | |
1600 | `emit-rtl.c'). */ | |
802a0058 | 1601 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
a7790c71 DV |
1602 | RS6000_ALIGN (crtl->outgoing_args_size + STACK_POINTER_OFFSET, \ |
1603 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) | |
f045b2c9 RS |
1604 | |
1605 | /* If we generate an insn to push BYTES bytes, | |
1606 | this says how many the stack pointer really advances by. | |
1607 | On RS/6000, don't define this because there are no push insns. */ | |
1608 | /* #define PUSH_ROUNDING(BYTES) */ | |
1609 | ||
1610 | /* Offset of first parameter from the argument pointer register value. | |
1611 | On the RS/6000, we define the argument pointer to the start of the fixed | |
1612 | area. */ | |
4697a36c | 1613 | #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA |
f045b2c9 | 1614 | |
62153b61 JM |
1615 | /* Offset from the argument pointer register value to the top of |
1616 | stack. This is different from FIRST_PARM_OFFSET because of the | |
1617 | register save area. */ | |
1618 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1619 | ||
f045b2c9 RS |
1620 | /* Define this if stack space is still allocated for a parameter passed |
1621 | in a register. The value is the number of bytes allocated to this | |
1622 | area. */ | |
ddbb449f AM |
1623 | #define REG_PARM_STACK_SPACE(FNDECL) \ |
1624 | rs6000_reg_parm_stack_space ((FNDECL), false) | |
1625 | ||
1626 | /* Define this macro if space guaranteed when compiling a function body | |
1627 | is different to space required when making a call, a situation that | |
1628 | can arise with K&R style function definitions. */ | |
1629 | #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ | |
1630 | rs6000_reg_parm_stack_space ((FNDECL), true) | |
f045b2c9 RS |
1631 | |
1632 | /* Define this if the above stack space is to be considered part of the | |
1633 | space allocated by the caller. */ | |
81464b2c | 1634 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
f045b2c9 RS |
1635 | |
1636 | /* This is the difference between the logical top of stack and the actual sp. | |
1637 | ||
82e41834 | 1638 | For the RS/6000, sp points past the fixed area. */ |
4697a36c | 1639 | #define STACK_POINTER_OFFSET RS6000_SAVE_AREA |
f045b2c9 RS |
1640 | |
1641 | /* Define this if the maximum size of all the outgoing args is to be | |
1642 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1643 | found in the variable crtl->outgoing_args_size. */ |
f73ad30e | 1644 | #define ACCUMULATE_OUTGOING_ARGS 1 |
f045b2c9 | 1645 | |
f045b2c9 RS |
1646 | /* Define how to find the value returned by a library function |
1647 | assuming the value has mode MODE. */ | |
1648 | ||
ded9bf77 | 1649 | #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) |
f045b2c9 | 1650 | |
6fa3f289 ZW |
1651 | /* DRAFT_V4_STRUCT_RET defaults off. */ |
1652 | #define DRAFT_V4_STRUCT_RET 0 | |
f607bc57 | 1653 | |
bd5bd7ac | 1654 | /* Let TARGET_RETURN_IN_MEMORY control what happens. */ |
f607bc57 | 1655 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
f045b2c9 | 1656 | |
a260abc9 | 1657 | /* Mode of stack savearea. |
dfdfa60f DE |
1658 | FUNCTION is VOIDmode because calling convention maintains SP. |
1659 | BLOCK needs Pmode for SP. | |
a260abc9 DE |
1660 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ |
1661 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
dfdfa60f | 1662 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ |
c6d5ff83 | 1663 | : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) |
a260abc9 | 1664 | |
4697a36c MM |
1665 | /* Minimum and maximum general purpose registers used to hold arguments. */ |
1666 | #define GP_ARG_MIN_REG 3 | |
1667 | #define GP_ARG_MAX_REG 10 | |
1668 | #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1669 | ||
1670 | /* Minimum and maximum floating point registers used to hold arguments. */ | |
1671 | #define FP_ARG_MIN_REG 33 | |
7509c759 MM |
1672 | #define FP_ARG_AIX_MAX_REG 45 |
1673 | #define FP_ARG_V4_MAX_REG 40 | |
008e32c0 UW |
1674 | #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ |
1675 | ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) | |
4697a36c MM |
1676 | #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
1677 | ||
0ac081f6 AH |
1678 | /* Minimum and maximum AltiVec registers used to hold arguments. */ |
1679 | #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
1680 | #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
1681 | #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
1682 | ||
b54214fe UW |
1683 | /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ |
1684 | #define AGGR_ARG_NUM_REG 8 | |
1685 | ||
4697a36c MM |
1686 | /* Return registers */ |
1687 | #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1688 | #define FP_ARG_RETURN FP_ARG_MIN_REG | |
0ac081f6 | 1689 | #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) |
b54214fe UW |
1690 | #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ |
1691 | : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
4304ccfd MM |
1692 | #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ |
1693 | ? (ALTIVEC_ARG_RETURN \ | |
08213983 | 1694 | + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ |
b54214fe | 1695 | : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) |
4697a36c | 1696 | |
7509c759 | 1697 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
6a4cee5f | 1698 | #define CALL_NORMAL 0x00000000 /* no special processing */ |
9ebbca7d | 1699 | /* Bits in 0x00000001 are unused. */ |
6a4cee5f MM |
1700 | #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ |
1701 | #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1702 | #define CALL_LONG 0x00000008 /* always call indirect */ | |
b9599e46 | 1703 | #define CALL_LIBCALL 0x00000010 /* libcall */ |
7509c759 | 1704 | |
f57fe068 AM |
1705 | /* We don't have prologue and epilogue functions to save/restore |
1706 | everything for most ABIs. */ | |
1707 | #define WORLD_SAVE_P(INFO) 0 | |
1708 | ||
f045b2c9 RS |
1709 | /* 1 if N is a possible register number for a function value |
1710 | as seen by the caller. | |
1711 | ||
0ac081f6 | 1712 | On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ |
e87a88d3 AM |
1713 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1714 | ((N) == GP_ARG_RETURN \ | |
202687fb | 1715 | || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ |
11d8d07e | 1716 | && TARGET_HARD_FLOAT) \ |
202687fb | 1717 | || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ |
b54214fe | 1718 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) |
f045b2c9 RS |
1719 | |
1720 | /* 1 if N is a possible register number for function argument passing. | |
0ac081f6 AH |
1721 | On RS/6000, these are r3-r10 and fp1-fp13. |
1722 | On AltiVec, v2 - v13 are used for passing vectors. */ | |
4697a36c | 1723 | #define FUNCTION_ARG_REGNO_P(N) \ |
202687fb MM |
1724 | (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ |
1725 | || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ | |
44688022 | 1726 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
202687fb | 1727 | || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ |
11d8d07e | 1728 | && TARGET_HARD_FLOAT)) |
f045b2c9 RS |
1729 | \f |
1730 | /* Define a data type for recording info about an argument list | |
1731 | during the scan of that argument list. This data type should | |
1732 | hold all necessary information about the function itself | |
1733 | and about the args processed so far, enough to enable macros | |
1734 | such as FUNCTION_ARG to determine where the next arg should go. | |
1735 | ||
1736 | On the RS/6000, this is a structure. The first element is the number of | |
1737 | total argument words, the second is used to store the next | |
1738 | floating-point register number, and the third says how many more args we | |
4697a36c MM |
1739 | have prototype types for. |
1740 | ||
4cc833b7 | 1741 | For ABI_V4, we treat these slightly differently -- `sysv_gregno' is |
07488f32 | 1742 | the next available GP register, `fregno' is the next available FP |
4cc833b7 RH |
1743 | register, and `words' is the number of words used on the stack. |
1744 | ||
bd227acc | 1745 | The varargs/stdarg support requires that this structure's size |
4cc833b7 | 1746 | be a multiple of sizeof(int). */ |
4697a36c MM |
1747 | |
1748 | typedef struct rs6000_args | |
1749 | { | |
4cc833b7 | 1750 | int words; /* # words used for passing GP registers */ |
6a4cee5f | 1751 | int fregno; /* next available FP register */ |
0ac081f6 | 1752 | int vregno; /* next available AltiVec register */ |
6a4cee5f | 1753 | int nargs_prototype; /* # args left in the current prototype */ |
6a4cee5f | 1754 | int prototype; /* Whether a prototype was defined */ |
a6c9bed4 | 1755 | int stdarg; /* Whether function is a stdarg function. */ |
6a4cee5f | 1756 | int call_cookie; /* Do special things for this call */ |
4cc833b7 | 1757 | int sysv_gregno; /* next available GP register */ |
0b5383eb DJ |
1758 | int intoffset; /* running offset in struct (darwin64) */ |
1759 | int use_stack; /* any part of struct on stack (darwin64) */ | |
a9ab25e2 IS |
1760 | int floats_in_gpr; /* count of SFmode floats taking up |
1761 | GPR space (darwin64) */ | |
0b5383eb | 1762 | int named; /* false for varargs params */ |
617718f7 | 1763 | int escapes; /* if function visible outside tu */ |
bdb60a10 | 1764 | int libcall; /* If this is a compiler generated call. */ |
4697a36c | 1765 | } CUMULATIVE_ARGS; |
f045b2c9 | 1766 | |
f045b2c9 RS |
1767 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1768 | for a call to a function whose data type is FNTYPE. | |
1769 | For a library call, FNTYPE is 0. */ | |
1770 | ||
617718f7 AM |
1771 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
1772 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ | |
1773 | N_NAMED_ARGS, FNDECL, VOIDmode) | |
f045b2c9 RS |
1774 | |
1775 | /* Similar, but when scanning the definition of a procedure. We always | |
1776 | set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1777 | ||
0f6937fe | 1778 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ |
617718f7 AM |
1779 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
1780 | 1000, current_function_decl, VOIDmode) | |
b9599e46 FS |
1781 | |
1782 | /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
1783 | ||
1784 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
617718f7 AM |
1785 | init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
1786 | 0, NULL_TREE, MODE) | |
f045b2c9 | 1787 | |
6e985040 | 1788 | #define PAD_VARARGS_DOWN \ |
76b0cbf8 | 1789 | (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) |
2a55fd42 | 1790 | |
f045b2c9 | 1791 | /* Output assembler code to FILE to increment profiler label # LABELNO |
58a39e45 | 1792 | for profiling a function entry. */ |
f045b2c9 RS |
1793 | |
1794 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
58a39e45 | 1795 | output_function_profiler ((FILE), (LABELNO)); |
f045b2c9 RS |
1796 | |
1797 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1798 | the stack pointer does not matter. No definition is equivalent to | |
1799 | always zero. | |
1800 | ||
a0ab749a | 1801 | On the RS/6000, this is nonzero because we can restore the stack from |
f045b2c9 RS |
1802 | its backpointer, which we maintain. */ |
1803 | #define EXIT_IGNORE_STACK 1 | |
1804 | ||
a701949a FS |
1805 | /* Define this macro as a C expression that is nonzero for registers |
1806 | that are used by the epilogue or the return' pattern. The stack | |
1807 | and frame pointer registers are already be assumed to be used as | |
1808 | needed. */ | |
1809 | ||
83720594 | 1810 | #define EPILOGUE_USES(REGNO) \ |
1de43f85 | 1811 | ((reload_completed && (REGNO) == LR_REGNO) \ |
b1765bde | 1812 | || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ |
cacf1ca8 | 1813 | || (crtl->calls_eh_return \ |
3553b09d | 1814 | && TARGET_AIX \ |
ff3867ae | 1815 | && (REGNO) == 2)) |
2bfcf297 | 1816 | |
f045b2c9 | 1817 | \f |
f045b2c9 RS |
1818 | /* Length in units of the trampoline for entering a nested function. */ |
1819 | ||
b6c9286a | 1820 | #define TRAMPOLINE_SIZE rs6000_trampoline_size () |
f045b2c9 | 1821 | \f |
f33985c6 | 1822 | /* Definitions for __builtin_return_address and __builtin_frame_address. |
893fc0a0 | 1823 | __builtin_return_address (0) should give link register (LR_REGNO), enable |
82e41834 | 1824 | this. */ |
f33985c6 MS |
1825 | /* This should be uncommented, so that the link register is used, but |
1826 | currently this would result in unmatched insns and spilling fixed | |
1827 | registers so we'll leave it for another day. When these problems are | |
1828 | taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1829 | (mrs) */ | |
1830 | /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
f09d4c33 | 1831 | |
b6c9286a MM |
1832 | /* Number of bytes into the frame return addresses can be found. See |
1833 | rs6000_stack_info in rs6000.c for more information on how the different | |
1834 | abi's store the return address. */ | |
008e32c0 UW |
1835 | #define RETURN_ADDRESS_OFFSET \ |
1836 | ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) | |
f09d4c33 | 1837 | |
f33985c6 MS |
1838 | /* The current return address is in link register (65). The return address |
1839 | of anything farther back is accessed normally at an offset of 8 from the | |
1840 | frame pointer. */ | |
71f123ca FS |
1841 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1842 | (rs6000_return_addr (COUNT, FRAME)) | |
1843 | ||
f33985c6 | 1844 | \f |
f045b2c9 RS |
1845 | /* Definitions for register eliminations. |
1846 | ||
1847 | We have two registers that can be eliminated on the RS/6000. First, the | |
1848 | frame pointer register can often be eliminated in favor of the stack | |
1849 | pointer register. Secondly, the argument pointer register can always be | |
642a35f1 JW |
1850 | eliminated; it is replaced with either the stack or frame pointer. |
1851 | ||
1852 | In addition, we use the elimination mechanism to see if r30 is needed | |
1853 | Initially we assume that it isn't. If it is, we spill it. This is done | |
1854 | by making it an eliminable register. We replace it with itself so that | |
1855 | if it isn't needed, then existing uses won't be modified. */ | |
f045b2c9 RS |
1856 | |
1857 | /* This is an array of structures. Each structure initializes one pair | |
1858 | of eliminable registers. The "from" register number is given first, | |
1859 | followed by "to". Eliminations of the same "from" register are listed | |
1860 | in order of preference. */ | |
7d5175e1 JJ |
1861 | #define ELIMINABLE_REGS \ |
1862 | {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1863 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1864 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1865 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1866 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
97b23853 | 1867 | { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } |
f045b2c9 | 1868 | |
f045b2c9 RS |
1869 | /* Define the offset between two registers, one to be eliminated, and the other |
1870 | its replacement, at the start of a routine. */ | |
d1d0c603 JJ |
1871 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1872 | ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
f045b2c9 RS |
1873 | \f |
1874 | /* Addressing modes, and classification of registers for them. */ | |
1875 | ||
940da324 JL |
1876 | #define HAVE_PRE_DECREMENT 1 |
1877 | #define HAVE_PRE_INCREMENT 1 | |
6fb5fa3c DB |
1878 | #define HAVE_PRE_MODIFY_DISP 1 |
1879 | #define HAVE_PRE_MODIFY_REG 1 | |
f045b2c9 RS |
1880 | |
1881 | /* Macros to check register numbers against specific register classes. */ | |
1882 | ||
1883 | /* These assume that REGNO is a hard or pseudo reg number. | |
1884 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1885 | or a pseudo reg currently allocated to a suitable hard reg. | |
1886 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1887 | has been allocated, which happens in reginfo.c during register |
1888 | allocation. */ | |
f045b2c9 RS |
1889 | |
1890 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1891 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1892 | ? (REGNO) <= 31 || (REGNO) == 67 \ | |
7d5175e1 | 1893 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1894 | : (reg_renumber[REGNO] >= 0 \ |
7d5175e1 JJ |
1895 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1896 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
f045b2c9 RS |
1897 | |
1898 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1899 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1900 | ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
7d5175e1 | 1901 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1902 | : (reg_renumber[REGNO] > 0 \ |
7d5175e1 JJ |
1903 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1904 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
c6c3dba9 PB |
1905 | |
1906 | /* Nonzero if X is a hard reg that can be used as an index | |
1907 | or if it is a pseudo reg in the non-strict case. */ | |
1908 | #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ | |
1909 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
1910 | || REGNO_OK_FOR_INDEX_P (REGNO (X))) | |
1911 | ||
1912 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1913 | or if it is a pseudo reg in the non-strict case. */ | |
1914 | #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ | |
1915 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
1916 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
1917 | ||
f045b2c9 RS |
1918 | \f |
1919 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1920 | ||
1921 | #define MAX_REGS_PER_ADDRESS 2 | |
1922 | ||
1923 | /* Recognize any constant value that is a valid address. */ | |
1924 | ||
6eff269e BK |
1925 | #define CONSTANT_ADDRESS_P(X) \ |
1926 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1927 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1928 | || GET_CODE (X) == HIGH) | |
f045b2c9 | 1929 | |
48d72335 | 1930 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
66180ff3 | 1931 | #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ |
76492753 PB |
1932 | && EASY_VECTOR_15((n) >> 1) \ |
1933 | && ((n) & 1) == 0) | |
48d72335 | 1934 | |
29e6733c | 1935 | #define EASY_VECTOR_MSB(n,mode) \ |
683be46f | 1936 | ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ |
29e6733c MM |
1937 | ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) |
1938 | ||
f045b2c9 | 1939 | \f |
a260abc9 DE |
1940 | /* Try a machine-dependent way of reloading an illegitimate address |
1941 | operand. If we find one, push the reload and jump to WIN. This | |
1942 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1943 | ||
f676971a | 1944 | Implemented on rs6000 by rs6000_legitimize_reload_address. |
24ea750e | 1945 | Note that (X) is evaluated twice; this is safe in current usage. */ |
f676971a | 1946 | |
a9098fd0 GK |
1947 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
1948 | do { \ | |
24ea750e | 1949 | int win; \ |
8beb65e3 | 1950 | (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ |
24ea750e DJ |
1951 | (int)(TYPE), (IND_LEVELS), &win); \ |
1952 | if ( win ) \ | |
1953 | goto WIN; \ | |
a260abc9 DE |
1954 | } while (0) |
1955 | ||
944258eb | 1956 | #define FIND_BASE_TERM rs6000_find_base_term |
766a866c MM |
1957 | \f |
1958 | /* The register number of the register used to address a table of | |
1959 | static data addresses in memory. In some cases this register is | |
1960 | defined by a processor's "application binary interface" (ABI). | |
1961 | When this macro is defined, RTL is generated for this register | |
1962 | once, as with the stack pointer and frame pointer registers. If | |
1963 | this macro is not defined, it is up to the machine-dependent files | |
1964 | to allocate such a register (if necessary). */ | |
1965 | ||
1db02437 | 1966 | #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 |
24f77f59 AM |
1967 | #define PIC_OFFSET_TABLE_REGNUM \ |
1968 | (TARGET_TOC ? TOC_REGISTER \ | |
1969 | : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ | |
1970 | : INVALID_REGNUM) | |
766a866c | 1971 | |
97b23853 | 1972 | #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) |
9ebbca7d | 1973 | |
766a866c MM |
1974 | /* Define this macro if the register defined by |
1975 | `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
089a05b8 | 1976 | this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ |
766a866c MM |
1977 | |
1978 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
1979 | ||
766a866c MM |
1980 | /* A C expression that is nonzero if X is a legitimate immediate |
1981 | operand on the target machine when generating position independent | |
1982 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
1983 | not check this. You can also assume FLAG_PIC is true, so you need | |
1984 | not check it either. You need not define this macro if all | |
1985 | constants (including `SYMBOL_REF') can be immediate operands when | |
1986 | generating position independent code. */ | |
1987 | ||
1988 | /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
f045b2c9 | 1989 | \f |
f045b2c9 RS |
1990 | /* Specify the machine mode that this machine uses |
1991 | for the index in the tablejump instruction. */ | |
e1565e65 | 1992 | #define CASE_VECTOR_MODE SImode |
f045b2c9 | 1993 | |
18543a22 ILT |
1994 | /* Define as C expression which evaluates to nonzero if the tablejump |
1995 | instruction expects the table to contain offsets from the address of the | |
1996 | table. | |
82e41834 | 1997 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 1998 | #define CASE_VECTOR_PC_RELATIVE 1 |
f045b2c9 | 1999 | |
f045b2c9 RS |
2000 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
2001 | #define DEFAULT_SIGNED_CHAR 0 | |
2002 | ||
c1618c0c DE |
2003 | /* An integer expression for the size in bits of the largest integer machine |
2004 | mode that should actually be used. */ | |
2005 | ||
2006 | /* Allow pairs of registers to be used, which is the intent of the default. */ | |
2007 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
2008 | ||
f045b2c9 RS |
2009 | /* Max number of bytes we can move from memory to memory |
2010 | in one reasonably fast instruction. */ | |
2f3e5814 | 2011 | #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) |
7e69e155 | 2012 | #define MAX_MOVE_MAX 8 |
f045b2c9 RS |
2013 | |
2014 | /* Nonzero if access to memory by bytes is no faster than for words. | |
a0ab749a | 2015 | Also nonzero if doing byte operations (specifically shifts) in registers |
f045b2c9 RS |
2016 | is undesirable. */ |
2017 | #define SLOW_BYTE_ACCESS 1 | |
2018 | ||
9a63901f RK |
2019 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD |
2020 | will either zero-extend or sign-extend. The value of this macro should | |
2021 | be the code that says which one of the two operations is implicitly | |
f822d252 | 2022 | done, UNKNOWN if none. */ |
9a63901f | 2023 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
225211e2 RK |
2024 | |
2025 | /* Define if loading short immediate values into registers sign extends. */ | |
58f2ae18 | 2026 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
fdaff8ba | 2027 | \f |
f045b2c9 RS |
2028 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
2029 | is done just by pretending it is already truncated. */ | |
2030 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2031 | ||
94993909 | 2032 | /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ |
d865b122 | 2033 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
bb0f9c02 | 2034 | ((VALUE) = GET_MODE_BITSIZE (MODE), 2) |
d865b122 | 2035 | |
0299bc72 | 2036 | /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of |
bb0f9c02 SB |
2037 | zero. The hardware instructions added in Power9 and the sequences using |
2038 | popcount return 32 or 64. */ | |
0299bc72 | 2039 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
bb0f9c02 SB |
2040 | (TARGET_CTZ || TARGET_POPCNTD \ |
2041 | ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ | |
2042 | : ((VALUE) = -1, 2)) | |
94993909 | 2043 | |
f045b2c9 RS |
2044 | /* Specify the machine mode that pointers have. |
2045 | After generation of rtl, the compiler makes no further distinction | |
2046 | between pointers and any other objects of this machine mode. */ | |
501623d4 RS |
2047 | extern scalar_int_mode rs6000_pmode; |
2048 | #define Pmode rs6000_pmode | |
f045b2c9 | 2049 | |
a3c9585f | 2050 | /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ |
4c81e946 FJ |
2051 | #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) |
2052 | ||
f045b2c9 | 2053 | /* Mode of a function address in a call instruction (for indexing purposes). |
f045b2c9 | 2054 | Doesn't matter on RS/6000. */ |
5b71a4e7 | 2055 | #define FUNCTION_MODE SImode |
f045b2c9 RS |
2056 | |
2057 | /* Define this if addresses of constant functions | |
2058 | shouldn't be put through pseudo regs where they can be cse'd. | |
2059 | Desirable on machines where ordinary constants are expensive | |
2060 | but a CALL with constant address is cheap. */ | |
1e8552c2 | 2061 | #define NO_FUNCTION_CSE 1 |
f045b2c9 | 2062 | |
d969caf8 | 2063 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
6febd581 RK |
2064 | few bits. |
2065 | ||
2066 | The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
2067 | have been dropped from the PowerPC architecture. */ | |
c28a7c24 | 2068 | #define SHIFT_COUNT_TRUNCATED 0 |
f045b2c9 | 2069 | |
f045b2c9 RS |
2070 | /* Adjust the length of an INSN. LENGTH is the currently-computed length and |
2071 | should be adjusted to reflect any required changes. This macro is used when | |
2072 | there is some systematic length adjustment required that would be difficult | |
2073 | to express in the length attribute. */ | |
2074 | ||
2075 | /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
2076 | ||
39a10a29 GK |
2077 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a |
2078 | COMPARE, return the mode to be used for the comparison. For | |
2079 | floating-point, CCFPmode should be used. CCUNSmode should be used | |
2080 | for unsigned comparisons. CCEQmode should be used when we are | |
2081 | doing an inequality comparison on the result of a | |
2082 | comparison. CCmode should be used in all other cases. */ | |
c5defebb | 2083 | |
b565a316 | 2084 | #define SELECT_CC_MODE(OP,X,Y) \ |
ebb109ad | 2085 | (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ |
c5defebb | 2086 | : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ |
ec8e098d | 2087 | : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ |
c5defebb | 2088 | ? CCEQmode : CCmode)) |
f045b2c9 | 2089 | |
b39358e1 GK |
2090 | /* Can the condition code MODE be safely reversed? This is safe in |
2091 | all cases on this port, because at present it doesn't use the | |
2092 | trapping FP comparisons (fcmpo). */ | |
2093 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2094 | ||
2095 | /* Given a condition code and a mode, return the inverse condition. */ | |
2096 | #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
2097 | ||
f045b2c9 RS |
2098 | \f |
2099 | /* Control the assembler format that we output. */ | |
2100 | ||
1b279f39 DE |
2101 | /* A C string constant describing how to begin a comment in the target |
2102 | assembler language. The compiler assumes that the comment will end at | |
2103 | the end of the line. */ | |
2104 | #define ASM_COMMENT_START " #" | |
6b67933e | 2105 | |
38c1f2d7 MM |
2106 | /* Flag to say the TOC is initialized */ |
2107 | extern int toc_initialized; | |
2108 | ||
f045b2c9 RS |
2109 | /* Macro to output a special constant pool entry. Go to WIN if we output |
2110 | it. Otherwise, it is written the usual way. | |
2111 | ||
2112 | On the RS/6000, toc entries are handled this way. */ | |
2113 | ||
a9098fd0 GK |
2114 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ |
2115 | { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
2116 | { \ | |
2117 | output_toc (FILE, X, LABELNO, MODE); \ | |
2118 | goto WIN; \ | |
2119 | } \ | |
f045b2c9 RS |
2120 | } |
2121 | ||
ebd97b96 DE |
2122 | #ifdef HAVE_GAS_WEAK |
2123 | #define RS6000_WEAK 1 | |
2124 | #else | |
2125 | #define RS6000_WEAK 0 | |
2126 | #endif | |
290ad355 | 2127 | |
79c4e63f AM |
2128 | #if RS6000_WEAK |
2129 | /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
8d91472f DE |
2130 | #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ |
2131 | rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) | |
79c4e63f AM |
2132 | #endif |
2133 | ||
ff2d10c1 AO |
2134 | #if HAVE_GAS_WEAKREF |
2135 | #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
2136 | do \ | |
2137 | { \ | |
2138 | fputs ("\t.weakref\t", (FILE)); \ | |
2139 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2140 | fputs (", ", (FILE)); \ | |
2141 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2142 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
2143 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
2144 | { \ | |
2145 | fputs ("\n\t.weakref\t.", (FILE)); \ | |
2146 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2147 | fputs (", .", (FILE)); \ | |
2148 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2149 | } \ | |
2150 | fputc ('\n', (FILE)); \ | |
2151 | } while (0) | |
2152 | #endif | |
2153 | ||
79c4e63f AM |
2154 | /* This implements the `alias' attribute. */ |
2155 | #undef ASM_OUTPUT_DEF_FROM_DECLS | |
2156 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
2157 | do \ | |
2158 | { \ | |
2159 | const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
2160 | const char *name = IDENTIFIER_POINTER (TARGET); \ | |
2161 | if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
85b776df | 2162 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f AM |
2163 | { \ |
2164 | if (TREE_PUBLIC (DECL)) \ | |
2165 | { \ | |
2166 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
2167 | { \ | |
2168 | fputs ("\t.globl\t.", FILE); \ | |
cbaaba19 | 2169 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
2170 | putc ('\n', FILE); \ |
2171 | } \ | |
2172 | } \ | |
2173 | else if (TARGET_XCOFF) \ | |
2174 | { \ | |
c167bc5b DE |
2175 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ |
2176 | { \ | |
2177 | fputs ("\t.lglobl\t.", FILE); \ | |
2178 | RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
2179 | putc ('\n', FILE); \ | |
2180 | fputs ("\t.lglobl\t", FILE); \ | |
2181 | RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
2182 | putc ('\n', FILE); \ | |
2183 | } \ | |
79c4e63f AM |
2184 | } \ |
2185 | fputs ("\t.set\t.", FILE); \ | |
cbaaba19 | 2186 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f | 2187 | fputs (",.", FILE); \ |
cbaaba19 | 2188 | RS6000_OUTPUT_BASENAME (FILE, name); \ |
79c4e63f AM |
2189 | fputc ('\n', FILE); \ |
2190 | } \ | |
2191 | ASM_OUTPUT_DEF (FILE, alias, name); \ | |
2192 | } \ | |
2193 | while (0) | |
290ad355 | 2194 | |
1bc7c5b6 ZW |
2195 | #define TARGET_ASM_FILE_START rs6000_file_start |
2196 | ||
f045b2c9 RS |
2197 | /* Output to assembler file text saying following lines |
2198 | may contain character constants, extra white space, comments, etc. */ | |
2199 | ||
2200 | #define ASM_APP_ON "" | |
2201 | ||
2202 | /* Output to assembler file text saying following lines | |
2203 | no longer contain unusual constructs. */ | |
2204 | ||
2205 | #define ASM_APP_OFF "" | |
2206 | ||
f045b2c9 RS |
2207 | /* How to refer to registers in assembler output. |
2208 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2209 | ||
82e41834 | 2210 | extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ |
c81bebd7 MM |
2211 | |
2212 | #define REGISTER_NAMES \ | |
2213 | { \ | |
2214 | &rs6000_reg_names[ 0][0], /* r0 */ \ | |
2215 | &rs6000_reg_names[ 1][0], /* r1 */ \ | |
2216 | &rs6000_reg_names[ 2][0], /* r2 */ \ | |
2217 | &rs6000_reg_names[ 3][0], /* r3 */ \ | |
2218 | &rs6000_reg_names[ 4][0], /* r4 */ \ | |
2219 | &rs6000_reg_names[ 5][0], /* r5 */ \ | |
2220 | &rs6000_reg_names[ 6][0], /* r6 */ \ | |
2221 | &rs6000_reg_names[ 7][0], /* r7 */ \ | |
2222 | &rs6000_reg_names[ 8][0], /* r8 */ \ | |
2223 | &rs6000_reg_names[ 9][0], /* r9 */ \ | |
2224 | &rs6000_reg_names[10][0], /* r10 */ \ | |
2225 | &rs6000_reg_names[11][0], /* r11 */ \ | |
2226 | &rs6000_reg_names[12][0], /* r12 */ \ | |
2227 | &rs6000_reg_names[13][0], /* r13 */ \ | |
2228 | &rs6000_reg_names[14][0], /* r14 */ \ | |
2229 | &rs6000_reg_names[15][0], /* r15 */ \ | |
2230 | &rs6000_reg_names[16][0], /* r16 */ \ | |
2231 | &rs6000_reg_names[17][0], /* r17 */ \ | |
2232 | &rs6000_reg_names[18][0], /* r18 */ \ | |
2233 | &rs6000_reg_names[19][0], /* r19 */ \ | |
2234 | &rs6000_reg_names[20][0], /* r20 */ \ | |
2235 | &rs6000_reg_names[21][0], /* r21 */ \ | |
2236 | &rs6000_reg_names[22][0], /* r22 */ \ | |
2237 | &rs6000_reg_names[23][0], /* r23 */ \ | |
2238 | &rs6000_reg_names[24][0], /* r24 */ \ | |
2239 | &rs6000_reg_names[25][0], /* r25 */ \ | |
2240 | &rs6000_reg_names[26][0], /* r26 */ \ | |
2241 | &rs6000_reg_names[27][0], /* r27 */ \ | |
2242 | &rs6000_reg_names[28][0], /* r28 */ \ | |
2243 | &rs6000_reg_names[29][0], /* r29 */ \ | |
2244 | &rs6000_reg_names[30][0], /* r30 */ \ | |
2245 | &rs6000_reg_names[31][0], /* r31 */ \ | |
2246 | \ | |
2247 | &rs6000_reg_names[32][0], /* fr0 */ \ | |
2248 | &rs6000_reg_names[33][0], /* fr1 */ \ | |
2249 | &rs6000_reg_names[34][0], /* fr2 */ \ | |
2250 | &rs6000_reg_names[35][0], /* fr3 */ \ | |
2251 | &rs6000_reg_names[36][0], /* fr4 */ \ | |
2252 | &rs6000_reg_names[37][0], /* fr5 */ \ | |
2253 | &rs6000_reg_names[38][0], /* fr6 */ \ | |
2254 | &rs6000_reg_names[39][0], /* fr7 */ \ | |
2255 | &rs6000_reg_names[40][0], /* fr8 */ \ | |
2256 | &rs6000_reg_names[41][0], /* fr9 */ \ | |
2257 | &rs6000_reg_names[42][0], /* fr10 */ \ | |
2258 | &rs6000_reg_names[43][0], /* fr11 */ \ | |
2259 | &rs6000_reg_names[44][0], /* fr12 */ \ | |
2260 | &rs6000_reg_names[45][0], /* fr13 */ \ | |
2261 | &rs6000_reg_names[46][0], /* fr14 */ \ | |
2262 | &rs6000_reg_names[47][0], /* fr15 */ \ | |
2263 | &rs6000_reg_names[48][0], /* fr16 */ \ | |
2264 | &rs6000_reg_names[49][0], /* fr17 */ \ | |
2265 | &rs6000_reg_names[50][0], /* fr18 */ \ | |
2266 | &rs6000_reg_names[51][0], /* fr19 */ \ | |
2267 | &rs6000_reg_names[52][0], /* fr20 */ \ | |
2268 | &rs6000_reg_names[53][0], /* fr21 */ \ | |
2269 | &rs6000_reg_names[54][0], /* fr22 */ \ | |
2270 | &rs6000_reg_names[55][0], /* fr23 */ \ | |
2271 | &rs6000_reg_names[56][0], /* fr24 */ \ | |
2272 | &rs6000_reg_names[57][0], /* fr25 */ \ | |
2273 | &rs6000_reg_names[58][0], /* fr26 */ \ | |
2274 | &rs6000_reg_names[59][0], /* fr27 */ \ | |
2275 | &rs6000_reg_names[60][0], /* fr28 */ \ | |
2276 | &rs6000_reg_names[61][0], /* fr29 */ \ | |
2277 | &rs6000_reg_names[62][0], /* fr30 */ \ | |
2278 | &rs6000_reg_names[63][0], /* fr31 */ \ | |
2279 | \ | |
462f7901 | 2280 | &rs6000_reg_names[64][0], /* was mq */ \ |
c81bebd7 MM |
2281 | &rs6000_reg_names[65][0], /* lr */ \ |
2282 | &rs6000_reg_names[66][0], /* ctr */ \ | |
2283 | &rs6000_reg_names[67][0], /* ap */ \ | |
2284 | \ | |
2285 | &rs6000_reg_names[68][0], /* cr0 */ \ | |
2286 | &rs6000_reg_names[69][0], /* cr1 */ \ | |
2287 | &rs6000_reg_names[70][0], /* cr2 */ \ | |
2288 | &rs6000_reg_names[71][0], /* cr3 */ \ | |
2289 | &rs6000_reg_names[72][0], /* cr4 */ \ | |
2290 | &rs6000_reg_names[73][0], /* cr5 */ \ | |
2291 | &rs6000_reg_names[74][0], /* cr6 */ \ | |
2292 | &rs6000_reg_names[75][0], /* cr7 */ \ | |
802a0058 | 2293 | \ |
f6b5d695 | 2294 | &rs6000_reg_names[76][0], /* ca */ \ |
0ac081f6 AH |
2295 | \ |
2296 | &rs6000_reg_names[77][0], /* v0 */ \ | |
2297 | &rs6000_reg_names[78][0], /* v1 */ \ | |
2298 | &rs6000_reg_names[79][0], /* v2 */ \ | |
2299 | &rs6000_reg_names[80][0], /* v3 */ \ | |
2300 | &rs6000_reg_names[81][0], /* v4 */ \ | |
2301 | &rs6000_reg_names[82][0], /* v5 */ \ | |
2302 | &rs6000_reg_names[83][0], /* v6 */ \ | |
2303 | &rs6000_reg_names[84][0], /* v7 */ \ | |
2304 | &rs6000_reg_names[85][0], /* v8 */ \ | |
2305 | &rs6000_reg_names[86][0], /* v9 */ \ | |
2306 | &rs6000_reg_names[87][0], /* v10 */ \ | |
2307 | &rs6000_reg_names[88][0], /* v11 */ \ | |
2308 | &rs6000_reg_names[89][0], /* v12 */ \ | |
2309 | &rs6000_reg_names[90][0], /* v13 */ \ | |
2310 | &rs6000_reg_names[91][0], /* v14 */ \ | |
2311 | &rs6000_reg_names[92][0], /* v15 */ \ | |
2312 | &rs6000_reg_names[93][0], /* v16 */ \ | |
2313 | &rs6000_reg_names[94][0], /* v17 */ \ | |
2314 | &rs6000_reg_names[95][0], /* v18 */ \ | |
2315 | &rs6000_reg_names[96][0], /* v19 */ \ | |
2316 | &rs6000_reg_names[97][0], /* v20 */ \ | |
2317 | &rs6000_reg_names[98][0], /* v21 */ \ | |
2318 | &rs6000_reg_names[99][0], /* v22 */ \ | |
2319 | &rs6000_reg_names[100][0], /* v23 */ \ | |
2320 | &rs6000_reg_names[101][0], /* v24 */ \ | |
2321 | &rs6000_reg_names[102][0], /* v25 */ \ | |
2322 | &rs6000_reg_names[103][0], /* v26 */ \ | |
2323 | &rs6000_reg_names[104][0], /* v27 */ \ | |
2324 | &rs6000_reg_names[105][0], /* v28 */ \ | |
2325 | &rs6000_reg_names[106][0], /* v29 */ \ | |
2326 | &rs6000_reg_names[107][0], /* v30 */ \ | |
2327 | &rs6000_reg_names[108][0], /* v31 */ \ | |
2328 | &rs6000_reg_names[109][0], /* vrsave */ \ | |
5f004351 | 2329 | &rs6000_reg_names[110][0], /* vscr */ \ |
346081bd SB |
2330 | &rs6000_reg_names[111][0], /* sfp */ \ |
2331 | &rs6000_reg_names[112][0], /* tfhar */ \ | |
2332 | &rs6000_reg_names[113][0], /* tfiar */ \ | |
2333 | &rs6000_reg_names[114][0], /* texasr */ \ | |
c81bebd7 MM |
2334 | } |
2335 | ||
f045b2c9 RS |
2336 | /* Table of additional register names to use in user input. */ |
2337 | ||
2338 | #define ADDITIONAL_REGISTER_NAMES \ | |
c4d38ccb MM |
2339 | {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ |
2340 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2341 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2342 | {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2343 | {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2344 | {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2345 | {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2346 | {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2347 | {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2348 | {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2349 | {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2350 | {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2351 | {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2352 | {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2353 | {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2354 | {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
0ac081f6 AH |
2355 | {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ |
2356 | {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
2357 | {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
2358 | {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
2359 | {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
2360 | {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
2361 | {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
2362 | {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
5f004351 | 2363 | {"vrsave", 109}, {"vscr", 110}, \ |
462f7901 | 2364 | /* no additional names for: lr, ctr, ap */ \ |
c4d38ccb MM |
2365 | {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ |
2366 | {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
cacf1ca8 | 2367 | {"cc", 68}, {"sp", 1}, {"toc", 2}, \ |
f6b5d695 SB |
2368 | /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
2369 | {"xer", 76}, \ | |
cacf1ca8 MM |
2370 | /* VSX registers overlaid on top of FR, Altivec registers */ \ |
2371 | {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ | |
2372 | {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ | |
2373 | {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ | |
2374 | {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ | |
2375 | {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ | |
2376 | {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ | |
2377 | {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ | |
2378 | {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ | |
2379 | {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ | |
2380 | {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ | |
2381 | {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ | |
2382 | {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ | |
2383 | {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ | |
2384 | {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ | |
2385 | {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ | |
0258b6e4 PB |
2386 | {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ |
2387 | /* Transactional Memory Facility (HTM) Registers. */ \ | |
346081bd | 2388 | {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \ |
23742a9e | 2389 | } |
f045b2c9 | 2390 | |
f045b2c9 RS |
2391 | /* This is how to output an element of a case-vector that is relative. */ |
2392 | ||
e1565e65 | 2393 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3daf36a4 | 2394 | do { char buf[100]; \ |
e1565e65 | 2395 | fputs ("\t.long ", FILE); \ |
3daf36a4 ILT |
2396 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ |
2397 | assemble_name (FILE, buf); \ | |
19d2d16f | 2398 | putc ('-', FILE); \ |
3daf36a4 ILT |
2399 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ |
2400 | assemble_name (FILE, buf); \ | |
19d2d16f | 2401 | putc ('\n', FILE); \ |
3daf36a4 | 2402 | } while (0) |
f045b2c9 RS |
2403 | |
2404 | /* This is how to output an assembler line | |
2405 | that says to advance the location counter | |
2406 | to a multiple of 2**LOG bytes. */ | |
2407 | ||
2408 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2409 | if ((LOG) != 0) \ | |
2410 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
2411 | ||
58082ff6 PH |
2412 | /* How to align the given loop. */ |
2413 | #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) | |
2414 | ||
d28073d4 BS |
2415 | /* Alignment guaranteed by __builtin_malloc. */ |
2416 | /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. | |
2417 | However, specifying the stronger guarantee currently leads to | |
2418 | a regression in SPEC CPU2006 437.leslie3d. The stronger | |
2419 | guarantee should be implemented here once that's fixed. */ | |
2420 | #define MALLOC_ABI_ALIGNMENT (64) | |
2421 | ||
9ebbca7d GK |
2422 | /* Pick up the return address upon entry to a procedure. Used for |
2423 | dwarf2 unwind information. This also enables the table driven | |
2424 | mechanism. */ | |
2425 | ||
1de43f85 DE |
2426 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) |
2427 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
9ebbca7d | 2428 | |
83720594 RH |
2429 | /* Describe how we implement __builtin_eh_return. */ |
2430 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2431 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2432 | ||
f045b2c9 RS |
2433 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2434 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2435 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2436 | ||
2437 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2438 | ||
2439 | /* Define which CODE values are valid. */ | |
2440 | ||
3cf437d4 | 2441 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') |
f045b2c9 RS |
2442 | |
2443 | /* Print a memory address as an operand to reference that memory location. */ | |
2444 | ||
2445 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2446 | ||
c82846bc DE |
2447 | /* For switching between functions with different target attributes. */ |
2448 | #define SWITCHABLE_TARGET 1 | |
2449 | ||
b6c9286a MM |
2450 | /* uncomment for disabling the corresponding default options */ |
2451 | /* #define MACHINE_no_sched_interblock */ | |
2452 | /* #define MACHINE_no_sched_speculative */ | |
2453 | /* #define MACHINE_no_sched_speculative_load */ | |
2454 | ||
766a866c | 2455 | /* General flags. */ |
a7df97e6 | 2456 | extern int frame_pointer_needed; |
0ac081f6 | 2457 | |
7fa14a01 MM |
2458 | /* Classification of the builtin functions as to which switches enable the |
2459 | builtin, and what attributes it should have. We used to use the target | |
2460 | flags macros, but we've run out of bits, so we now map the options into new | |
2461 | settings used here. */ | |
2462 | ||
2463 | /* Builtin attributes. */ | |
2464 | #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ | |
2465 | #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ | |
2466 | #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ | |
2467 | #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ | |
2468 | #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ | |
2469 | #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ | |
7fa14a01 MM |
2470 | #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ |
2471 | #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ | |
2472 | ||
2473 | #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ | |
902cb7b1 KN |
2474 | #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor |
2475 | modifies global state. */ | |
4f45da44 KN |
2476 | #define RS6000_BTC_PURE 0x00000200 /* reads global |
2477 | state/mem and does | |
2478 | not modify global state. */ | |
7fa14a01 MM |
2479 | #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ |
2480 | #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ | |
2481 | ||
2482 | /* Miscellaneous information. */ | |
0258b6e4 PB |
2483 | #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ |
2484 | #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ | |
01f61a78 PB |
2485 | #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ |
2486 | #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ | |
0258b6e4 | 2487 | #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ |
1c9df37c MM |
2488 | |
2489 | /* Convenience macros to document the instruction type. */ | |
7fa14a01 MM |
2490 | #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ |
2491 | #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ | |
2492 | ||
2493 | /* Builtin targets. For now, we reuse the masks for those options that are in | |
e075a6cc | 2494 | target flags, and pick two random bits for paired and ldbl128, which |
8241efd1 | 2495 | aren't in target_flags. */ |
4b705221 | 2496 | #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ |
7fa14a01 | 2497 | #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ |
4fd18c78 | 2498 | #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ |
7fa14a01 | 2499 | #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ |
f62511da | 2500 | #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ |
8fa97501 | 2501 | #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ |
5a3a6a5e | 2502 | #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ |
f62511da | 2503 | #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ |
0258b6e4 | 2504 | #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ |
7fa14a01 MM |
2505 | #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ |
2506 | #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ | |
2507 | #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ | |
2508 | #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ | |
2509 | #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ | |
2510 | #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ | |
7fa14a01 | 2511 | #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ |
06b39289 | 2512 | #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ |
f93bc5b3 | 2513 | #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ |
8241efd1 | 2514 | #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ |
4f45da44 | 2515 | #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ |
bbd35101 | 2516 | #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ |
7fa14a01 MM |
2517 | |
2518 | #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | |
2519 | | RS6000_BTM_VSX \ | |
f62511da | 2520 | | RS6000_BTM_P8_VECTOR \ |
8fa97501 | 2521 | | RS6000_BTM_P9_VECTOR \ |
5a3a6a5e | 2522 | | RS6000_BTM_P9_MISC \ |
402e60c5 | 2523 | | RS6000_BTM_MODULO \ |
f62511da | 2524 | | RS6000_BTM_CRYPTO \ |
7fa14a01 MM |
2525 | | RS6000_BTM_FRE \ |
2526 | | RS6000_BTM_FRES \ | |
2527 | | RS6000_BTM_FRSQRTE \ | |
2528 | | RS6000_BTM_FRSQRTES \ | |
0258b6e4 | 2529 | | RS6000_BTM_HTM \ |
7fa14a01 | 2530 | | RS6000_BTM_POPCNTD \ |
06b39289 | 2531 | | RS6000_BTM_CELL \ |
f93bc5b3 | 2532 | | RS6000_BTM_DFP \ |
8241efd1 | 2533 | | RS6000_BTM_HARD_FLOAT \ |
53605f35 BS |
2534 | | RS6000_BTM_LDBL128 \ |
2535 | | RS6000_BTM_FLOAT128) | |
7fa14a01 MM |
2536 | |
2537 | /* Define builtin enum index. */ | |
2538 | ||
4f45da44 | 2539 | #undef RS6000_BUILTIN_0 |
7fa14a01 MM |
2540 | #undef RS6000_BUILTIN_1 |
2541 | #undef RS6000_BUILTIN_2 | |
2542 | #undef RS6000_BUILTIN_3 | |
2543 | #undef RS6000_BUILTIN_A | |
2544 | #undef RS6000_BUILTIN_D | |
0258b6e4 | 2545 | #undef RS6000_BUILTIN_H |
7fa14a01 MM |
2546 | #undef RS6000_BUILTIN_P |
2547 | #undef RS6000_BUILTIN_Q | |
7fa14a01 MM |
2548 | #undef RS6000_BUILTIN_X |
2549 | ||
4f45da44 | 2550 | #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
7fa14a01 MM |
2551 | #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
2552 | #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2553 | #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2554 | #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2555 | #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
0258b6e4 | 2556 | #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
7fa14a01 MM |
2557 | #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
2558 | #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
7fa14a01 | 2559 | #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
1c9df37c | 2560 | |
0ac081f6 AH |
2561 | enum rs6000_builtins |
2562 | { | |
1c9df37c | 2563 | #include "rs6000-builtin.def" |
a72c65c7 | 2564 | |
58646b77 PB |
2565 | RS6000_BUILTIN_COUNT |
2566 | }; | |
2567 | ||
4f45da44 | 2568 | #undef RS6000_BUILTIN_0 |
7fa14a01 MM |
2569 | #undef RS6000_BUILTIN_1 |
2570 | #undef RS6000_BUILTIN_2 | |
2571 | #undef RS6000_BUILTIN_3 | |
2572 | #undef RS6000_BUILTIN_A | |
2573 | #undef RS6000_BUILTIN_D | |
0258b6e4 | 2574 | #undef RS6000_BUILTIN_H |
7fa14a01 MM |
2575 | #undef RS6000_BUILTIN_P |
2576 | #undef RS6000_BUILTIN_Q | |
7fa14a01 | 2577 | #undef RS6000_BUILTIN_X |
1c9df37c | 2578 | |
58646b77 PB |
2579 | enum rs6000_builtin_type_index |
2580 | { | |
2581 | RS6000_BTI_NOT_OPAQUE, | |
2582 | RS6000_BTI_opaque_V2SI, | |
2583 | RS6000_BTI_opaque_V2SF, | |
2584 | RS6000_BTI_opaque_p_V2SI, | |
2585 | RS6000_BTI_opaque_V4SI, | |
2586 | RS6000_BTI_V16QI, | |
a16a872d | 2587 | RS6000_BTI_V1TI, |
58646b77 PB |
2588 | RS6000_BTI_V2SI, |
2589 | RS6000_BTI_V2SF, | |
a72c65c7 MM |
2590 | RS6000_BTI_V2DI, |
2591 | RS6000_BTI_V2DF, | |
58646b77 PB |
2592 | RS6000_BTI_V4HI, |
2593 | RS6000_BTI_V4SI, | |
2594 | RS6000_BTI_V4SF, | |
2595 | RS6000_BTI_V8HI, | |
2596 | RS6000_BTI_unsigned_V16QI, | |
a16a872d | 2597 | RS6000_BTI_unsigned_V1TI, |
58646b77 PB |
2598 | RS6000_BTI_unsigned_V8HI, |
2599 | RS6000_BTI_unsigned_V4SI, | |
a72c65c7 | 2600 | RS6000_BTI_unsigned_V2DI, |
58646b77 PB |
2601 | RS6000_BTI_bool_char, /* __bool char */ |
2602 | RS6000_BTI_bool_short, /* __bool short */ | |
2603 | RS6000_BTI_bool_int, /* __bool int */ | |
a72c65c7 | 2604 | RS6000_BTI_bool_long, /* __bool long */ |
58646b77 PB |
2605 | RS6000_BTI_pixel, /* __pixel */ |
2606 | RS6000_BTI_bool_V16QI, /* __vector __bool char */ | |
2607 | RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
2608 | RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
a72c65c7 | 2609 | RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
58646b77 PB |
2610 | RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
2611 | RS6000_BTI_long, /* long_integer_type_node */ | |
2612 | RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
c9485473 MM |
2613 | RS6000_BTI_long_long, /* long_long_integer_type_node */ |
2614 | RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ | |
58646b77 PB |
2615 | RS6000_BTI_INTQI, /* intQI_type_node */ |
2616 | RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ | |
2617 | RS6000_BTI_INTHI, /* intHI_type_node */ | |
2618 | RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
2619 | RS6000_BTI_INTSI, /* intSI_type_node */ | |
2620 | RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ | |
a72c65c7 MM |
2621 | RS6000_BTI_INTDI, /* intDI_type_node */ |
2622 | RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ | |
a16a872d MM |
2623 | RS6000_BTI_INTTI, /* intTI_type_node */ |
2624 | RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ | |
58646b77 | 2625 | RS6000_BTI_float, /* float_type_node */ |
a72c65c7 | 2626 | RS6000_BTI_double, /* double_type_node */ |
06b39289 MM |
2627 | RS6000_BTI_long_double, /* long_double_type_node */ |
2628 | RS6000_BTI_dfloat64, /* dfloat64_type_node */ | |
2629 | RS6000_BTI_dfloat128, /* dfloat128_type_node */ | |
58646b77 | 2630 | RS6000_BTI_void, /* void_type_node */ |
6712d6fd MM |
2631 | RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ |
2632 | RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ | |
53605f35 | 2633 | RS6000_BTI_const_str, /* pointer to const char * */ |
58646b77 | 2634 | RS6000_BTI_MAX |
0ac081f6 | 2635 | }; |
58646b77 PB |
2636 | |
2637 | ||
2638 | #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) | |
2639 | #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) | |
2640 | #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) | |
2641 | #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) | |
2642 | #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
a16a872d | 2643 | #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) |
a72c65c7 MM |
2644 | #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
2645 | #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) | |
58646b77 PB |
2646 | #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) |
2647 | #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) | |
2648 | #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) | |
2649 | #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
2650 | #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
2651 | #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
2652 | #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
a16a872d | 2653 | #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) |
58646b77 PB |
2654 | #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) |
2655 | #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
a72c65c7 | 2656 | #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
58646b77 PB |
2657 | #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
2658 | #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
2659 | #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
a72c65c7 | 2660 | #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) |
58646b77 PB |
2661 | #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
2662 | #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
2663 | #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
2664 | #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
a72c65c7 | 2665 | #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
58646b77 PB |
2666 | #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
2667 | ||
c9485473 MM |
2668 | #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
2669 | #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) | |
58646b77 PB |
2670 | #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
2671 | #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
2672 | #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
2673 | #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
2674 | #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
2675 | #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
2676 | #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
2677 | #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
a72c65c7 MM |
2678 | #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
2679 | #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) | |
a16a872d MM |
2680 | #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) |
2681 | #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) | |
58646b77 | 2682 | #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
a72c65c7 | 2683 | #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
06b39289 MM |
2684 | #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) |
2685 | #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) | |
2686 | #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) | |
58646b77 | 2687 | #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
6712d6fd MM |
2688 | #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) |
2689 | #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) | |
53605f35 | 2690 | #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) |
58646b77 PB |
2691 | |
2692 | extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
2693 | extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
2694 | ||
807e902e | 2695 | #define TARGET_SUPPORTS_WIDE_INT 1 |
08213983 MM |
2696 | |
2697 | #if (GCC_VERSION >= 3000) | |
2698 | #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 | |
2699 | #endif |