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f045b2c9 | 1 | /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
f3061fa4 | 2 | Copyright (C) 1992-2012 Free Software Foundation, Inc. |
6a7ec0a7 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
f045b2c9 | 4 | |
5de601cf | 5 | This file is part of GCC. |
f045b2c9 | 6 | |
5de601cf NC |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
5de601cf | 10 | option) any later version. |
f045b2c9 | 11 | |
5de601cf NC |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
f045b2c9 | 16 | |
748086b7 JJ |
17 | Under Section 7 of GPL version 3, you are granted additional |
18 | permissions described in the GCC Runtime Library Exception, version | |
19 | 3.1, as published by the Free Software Foundation. | |
20 | ||
21 | You should have received a copy of the GNU General Public License and | |
22 | a copy of the GCC Runtime Library Exception along with this program; | |
23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 24 | <http://www.gnu.org/licenses/>. */ |
f045b2c9 RS |
25 | |
26 | /* Note that some other tm.h files include this one and then override | |
9ebbca7d | 27 | many of the definitions. */ |
f045b2c9 | 28 | |
fd438373 MM |
29 | #ifndef RS6000_OPTS_H |
30 | #include "config/rs6000/rs6000-opts.h" | |
31 | #endif | |
32 | ||
9ebbca7d GK |
33 | /* Definitions for the object file format. These are set at |
34 | compile-time. */ | |
f045b2c9 | 35 | |
9ebbca7d GK |
36 | #define OBJECT_XCOFF 1 |
37 | #define OBJECT_ELF 2 | |
38 | #define OBJECT_PEF 3 | |
ee890fe2 | 39 | #define OBJECT_MACHO 4 |
f045b2c9 | 40 | |
9ebbca7d | 41 | #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) |
2bfcf297 | 42 | #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) |
9ebbca7d | 43 | #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) |
ee890fe2 | 44 | #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) |
f045b2c9 | 45 | |
2bfcf297 DB |
46 | #ifndef TARGET_AIX |
47 | #define TARGET_AIX 0 | |
48 | #endif | |
49 | ||
78009d9f MM |
50 | #ifndef TARGET_AIX_OS |
51 | #define TARGET_AIX_OS 0 | |
52 | #endif | |
53 | ||
85b776df AM |
54 | /* Control whether function entry points use a "dot" symbol when |
55 | ABI_AIX. */ | |
56 | #define DOT_SYMBOLS 1 | |
57 | ||
8e3f41e7 MM |
58 | /* Default string to use for cpu if not specified. */ |
59 | #ifndef TARGET_CPU_DEFAULT | |
60 | #define TARGET_CPU_DEFAULT ((char *)0) | |
61 | #endif | |
62 | ||
f565b0a1 | 63 | /* If configured for PPC405, support PPC405CR Erratum77. */ |
b0bfee6e | 64 | #ifdef CONFIG_PPC405CR |
f565b0a1 DE |
65 | #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) |
66 | #else | |
67 | #define PPC405_ERRATUM77 0 | |
68 | #endif | |
69 | ||
96038623 DE |
70 | #ifndef TARGET_PAIRED_FLOAT |
71 | #define TARGET_PAIRED_FLOAT 0 | |
72 | #endif | |
73 | ||
cd679487 BE |
74 | #ifdef HAVE_AS_POPCNTB |
75 | #define ASM_CPU_POWER5_SPEC "-mpower5" | |
76 | #else | |
77 | #define ASM_CPU_POWER5_SPEC "-mpower4" | |
78 | #endif | |
79 | ||
80 | #ifdef HAVE_AS_DFP | |
81 | #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" | |
82 | #else | |
83 | #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" | |
84 | #endif | |
85 | ||
cacf1ca8 | 86 | #ifdef HAVE_AS_POPCNTD |
d40c9e33 PB |
87 | #define ASM_CPU_POWER7_SPEC "-mpower7" |
88 | #else | |
89 | #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" | |
90 | #endif | |
91 | ||
47f67e51 PB |
92 | #ifdef HAVE_AS_DCI |
93 | #define ASM_CPU_476_SPEC "-m476" | |
94 | #else | |
95 | #define ASM_CPU_476_SPEC "-mpower4" | |
96 | #endif | |
97 | ||
cacf1ca8 MM |
98 | /* Common ASM definitions used by ASM_SPEC among the various targets for |
99 | handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to | |
100 | provide the default assembler options if the user uses -mcpu=native, so if | |
101 | you make changes here, make them also there. */ | |
f984d8df DB |
102 | #define ASM_CPU_SPEC \ |
103 | "%{!mcpu*: \ | |
93ae5495 | 104 | %{mpowerpc64*: -mppc64} \ |
a441dedb | 105 | %{!mpowerpc64*: %(asm_default)}} \ |
cacf1ca8 | 106 | %{mcpu=native: %(asm_cpu_native)} \ |
d296e02e | 107 | %{mcpu=cell: -mcell} \ |
93ae5495 | 108 | %{mcpu=power3: -mppc64} \ |
957e9e48 | 109 | %{mcpu=power4: -mpower4} \ |
cd679487 BE |
110 | %{mcpu=power5: %(asm_cpu_power5)} \ |
111 | %{mcpu=power5+: %(asm_cpu_power5)} \ | |
112 | %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ | |
113 | %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ | |
d40c9e33 | 114 | %{mcpu=power7: %(asm_cpu_power7)} \ |
ebde32fd | 115 | %{mcpu=a2: -ma2} \ |
f984d8df | 116 | %{mcpu=powerpc: -mppc} \ |
93ae5495 | 117 | %{mcpu=rs64a: -mppc64} \ |
f984d8df | 118 | %{mcpu=401: -mppc} \ |
61a8515c JS |
119 | %{mcpu=403: -m403} \ |
120 | %{mcpu=405: -m405} \ | |
2c9d95ef DE |
121 | %{mcpu=405fp: -m405} \ |
122 | %{mcpu=440: -m440} \ | |
123 | %{mcpu=440fp: -m440} \ | |
4adf8008 PB |
124 | %{mcpu=464: -m440} \ |
125 | %{mcpu=464fp: -m440} \ | |
47f67e51 PB |
126 | %{mcpu=476: %(asm_cpu_476)} \ |
127 | %{mcpu=476fp: %(asm_cpu_476)} \ | |
f984d8df DB |
128 | %{mcpu=505: -mppc} \ |
129 | %{mcpu=601: -m601} \ | |
130 | %{mcpu=602: -mppc} \ | |
131 | %{mcpu=603: -mppc} \ | |
132 | %{mcpu=603e: -mppc} \ | |
133 | %{mcpu=ec603e: -mppc} \ | |
134 | %{mcpu=604: -mppc} \ | |
135 | %{mcpu=604e: -mppc} \ | |
93ae5495 AM |
136 | %{mcpu=620: -mppc64} \ |
137 | %{mcpu=630: -mppc64} \ | |
f984d8df DB |
138 | %{mcpu=740: -mppc} \ |
139 | %{mcpu=750: -mppc} \ | |
49ffe578 | 140 | %{mcpu=G3: -mppc} \ |
93ae5495 AM |
141 | %{mcpu=7400: -mppc -maltivec} \ |
142 | %{mcpu=7450: -mppc -maltivec} \ | |
143 | %{mcpu=G4: -mppc -maltivec} \ | |
f984d8df DB |
144 | %{mcpu=801: -mppc} \ |
145 | %{mcpu=821: -mppc} \ | |
146 | %{mcpu=823: -mppc} \ | |
775db490 | 147 | %{mcpu=860: -mppc} \ |
93ae5495 AM |
148 | %{mcpu=970: -mpower4 -maltivec} \ |
149 | %{mcpu=G5: -mpower4 -maltivec} \ | |
a3170dc6 | 150 | %{mcpu=8540: -me500} \ |
5ca0373f | 151 | %{mcpu=8548: -me500} \ |
fa41c305 EW |
152 | %{mcpu=e300c2: -me300} \ |
153 | %{mcpu=e300c3: -me300} \ | |
edae5fe3 | 154 | %{mcpu=e500mc: -me500mc} \ |
b17f98b1 | 155 | %{mcpu=e500mc64: -me500mc64} \ |
683ed19e EW |
156 | %{mcpu=e5500: -me5500} \ |
157 | %{mcpu=e6500: -me6500} \ | |
93ae5495 | 158 | %{maltivec: -maltivec} \ |
2c9ccc21 | 159 | %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ |
93ae5495 | 160 | -many" |
f984d8df DB |
161 | |
162 | #define CPP_DEFAULT_SPEC "" | |
163 | ||
164 | #define ASM_DEFAULT_SPEC "" | |
165 | ||
841faeed MM |
166 | /* This macro defines names of additional specifications to put in the specs |
167 | that can be used in various specifications like CC1_SPEC. Its definition | |
168 | is an initializer with a subgrouping for each command option. | |
169 | ||
170 | Each subgrouping contains a string constant, that defines the | |
5de601cf | 171 | specification name, and a string constant that used by the GCC driver |
841faeed MM |
172 | program. |
173 | ||
174 | Do not define this macro if it does not need to do anything. */ | |
175 | ||
7509c759 | 176 | #define SUBTARGET_EXTRA_SPECS |
7509c759 | 177 | |
c81bebd7 | 178 | #define EXTRA_SPECS \ |
c81bebd7 | 179 | { "cpp_default", CPP_DEFAULT_SPEC }, \ |
c81bebd7 | 180 | { "asm_cpu", ASM_CPU_SPEC }, \ |
cacf1ca8 | 181 | { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
c81bebd7 | 182 | { "asm_default", ASM_DEFAULT_SPEC }, \ |
0eab6840 | 183 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
cd679487 BE |
184 | { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ |
185 | { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ | |
d40c9e33 | 186 | { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ |
47f67e51 | 187 | { "asm_cpu_476", ASM_CPU_476_SPEC }, \ |
7509c759 MM |
188 | SUBTARGET_EXTRA_SPECS |
189 | ||
0eab6840 DE |
190 | /* -mcpu=native handling only makes sense with compiler running on |
191 | an PowerPC chip. If changing this condition, also change | |
192 | the condition in driver-rs6000.c. */ | |
193 | #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) | |
194 | /* In driver-rs6000.c. */ | |
195 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
196 | #define EXTRA_SPEC_FUNCTIONS \ | |
197 | { "local_cpu_detect", host_detect_local_cpu }, | |
198 | #define HAVE_LOCAL_CPU_DETECT | |
cacf1ca8 MM |
199 | #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
200 | ||
201 | #else | |
202 | #define ASM_CPU_NATIVE_SPEC "%(asm_default)" | |
0eab6840 DE |
203 | #endif |
204 | ||
ee7caeb3 DE |
205 | #ifndef CC1_CPU_SPEC |
206 | #ifdef HAVE_LOCAL_CPU_DETECT | |
0eab6840 DE |
207 | #define CC1_CPU_SPEC \ |
208 | "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
209 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
ee7caeb3 DE |
210 | #else |
211 | #define CC1_CPU_SPEC "" | |
212 | #endif | |
0eab6840 DE |
213 | #endif |
214 | ||
fb623df5 | 215 | /* Architecture type. */ |
f045b2c9 | 216 | |
bb22512c | 217 | /* Define TARGET_MFCRF if the target assembler does not support the |
78f5898b | 218 | optional field operand for mfcr. */ |
fb623df5 | 219 | |
78f5898b | 220 | #ifndef HAVE_AS_MFCRF |
432218ba | 221 | #undef TARGET_MFCRF |
ffa22984 DE |
222 | #define TARGET_MFCRF 0 |
223 | #endif | |
224 | ||
0fa2e4df | 225 | /* Define TARGET_POPCNTB if the target assembler does not support the |
432218ba DE |
226 | popcount byte instruction. */ |
227 | ||
228 | #ifndef HAVE_AS_POPCNTB | |
229 | #undef TARGET_POPCNTB | |
230 | #define TARGET_POPCNTB 0 | |
231 | #endif | |
232 | ||
9719f3b7 DE |
233 | /* Define TARGET_FPRND if the target assembler does not support the |
234 | fp rounding instructions. */ | |
235 | ||
236 | #ifndef HAVE_AS_FPRND | |
237 | #undef TARGET_FPRND | |
238 | #define TARGET_FPRND 0 | |
239 | #endif | |
240 | ||
b639c3c2 JJ |
241 | /* Define TARGET_CMPB if the target assembler does not support the |
242 | cmpb instruction. */ | |
243 | ||
244 | #ifndef HAVE_AS_CMPB | |
245 | #undef TARGET_CMPB | |
246 | #define TARGET_CMPB 0 | |
247 | #endif | |
248 | ||
44cd321e PS |
249 | /* Define TARGET_MFPGPR if the target assembler does not support the |
250 | mffpr and mftgpr instructions. */ | |
251 | ||
252 | #ifndef HAVE_AS_MFPGPR | |
253 | #undef TARGET_MFPGPR | |
254 | #define TARGET_MFPGPR 0 | |
255 | #endif | |
256 | ||
b639c3c2 JJ |
257 | /* Define TARGET_DFP if the target assembler does not support decimal |
258 | floating point instructions. */ | |
259 | #ifndef HAVE_AS_DFP | |
260 | #undef TARGET_DFP | |
261 | #define TARGET_DFP 0 | |
262 | #endif | |
263 | ||
cacf1ca8 MM |
264 | /* Define TARGET_POPCNTD if the target assembler does not support the |
265 | popcount word and double word instructions. */ | |
266 | ||
267 | #ifndef HAVE_AS_POPCNTD | |
268 | #undef TARGET_POPCNTD | |
269 | #define TARGET_POPCNTD 0 | |
270 | #endif | |
271 | ||
272 | /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If | |
273 | not, generate the lwsync code as an integer constant. */ | |
274 | #ifdef HAVE_AS_LWSYNC | |
275 | #define TARGET_LWSYNC_INSTRUCTION 1 | |
276 | #else | |
277 | #define TARGET_LWSYNC_INSTRUCTION 0 | |
278 | #endif | |
279 | ||
9752c4ad AM |
280 | /* Define TARGET_TLS_MARKERS if the target assembler does not support |
281 | arg markers for __tls_get_addr calls. */ | |
282 | #ifndef HAVE_AS_TLS_MARKERS | |
283 | #undef TARGET_TLS_MARKERS | |
284 | #define TARGET_TLS_MARKERS 0 | |
285 | #else | |
286 | #define TARGET_TLS_MARKERS tls_markers | |
287 | #endif | |
288 | ||
7f970b70 AM |
289 | #ifndef TARGET_SECURE_PLT |
290 | #define TARGET_SECURE_PLT 0 | |
291 | #endif | |
292 | ||
070b27da AM |
293 | #ifndef TARGET_CMODEL |
294 | #define TARGET_CMODEL CMODEL_SMALL | |
295 | #endif | |
296 | ||
2f3e5814 | 297 | #define TARGET_32BIT (! TARGET_64BIT) |
d14a6d05 | 298 | |
c4501e62 JJ |
299 | #ifndef HAVE_AS_TLS |
300 | #define HAVE_AS_TLS 0 | |
301 | #endif | |
302 | ||
be26142a PB |
303 | #ifndef TARGET_LINK_STACK |
304 | #define TARGET_LINK_STACK 0 | |
305 | #endif | |
306 | ||
307 | #ifndef SET_TARGET_LINK_STACK | |
308 | #define SET_TARGET_LINK_STACK(X) do { } while (0) | |
309 | #endif | |
310 | ||
48d72335 DE |
311 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ |
312 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
313 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
314 | ||
996ed075 JJ |
315 | #ifdef IN_LIBGCC2 |
316 | /* For libgcc2 we make sure this is a compile time constant */ | |
67796c1f | 317 | #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) |
78f5898b | 318 | #undef TARGET_POWERPC64 |
996ed075 JJ |
319 | #define TARGET_POWERPC64 1 |
320 | #else | |
78f5898b | 321 | #undef TARGET_POWERPC64 |
996ed075 JJ |
322 | #define TARGET_POWERPC64 0 |
323 | #endif | |
b6c9286a | 324 | #else |
78f5898b | 325 | /* The option machinery will define this. */ |
b6c9286a MM |
326 | #endif |
327 | ||
c28a7c24 | 328 | #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) |
9ebbca7d | 329 | |
696e45ba ME |
330 | /* FPU operations supported. |
331 | Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must | |
332 | also test TARGET_HARD_FLOAT. */ | |
333 | #define TARGET_SINGLE_FLOAT 1 | |
334 | #define TARGET_DOUBLE_FLOAT 1 | |
335 | #define TARGET_SINGLE_FPU 0 | |
336 | #define TARGET_SIMPLE_FPU 0 | |
0bb7b92e | 337 | #define TARGET_XILINX_FPU 0 |
696e45ba | 338 | |
fb623df5 RK |
339 | /* Recast the processor type to the cpu attribute. */ |
340 | #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) | |
341 | ||
8482e358 | 342 | /* Define generic processor types based upon current deployment. */ |
3cb999d8 | 343 | #define PROCESSOR_COMMON PROCESSOR_PPC601 |
3cb999d8 DE |
344 | #define PROCESSOR_POWERPC PROCESSOR_PPC604 |
345 | #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
6e151478 | 346 | |
fb623df5 | 347 | /* Define the default processor. This is overridden by other tm.h files. */ |
f3061fa4 | 348 | #define PROCESSOR_DEFAULT PROCESSOR_PPC603 |
3cb999d8 | 349 | #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A |
fb623df5 | 350 | |
38c1f2d7 | 351 | /* Debug support */ |
fd438373 MM |
352 | #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
353 | #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ | |
354 | #define MASK_DEBUG_REG 0x04 /* debug register handling */ | |
355 | #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ | |
356 | #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ | |
357 | #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ | |
7fa14a01 | 358 | #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ |
fd438373 MM |
359 | #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
360 | | MASK_DEBUG_ARG \ | |
361 | | MASK_DEBUG_REG \ | |
362 | | MASK_DEBUG_ADDR \ | |
363 | | MASK_DEBUG_COST \ | |
7fa14a01 MM |
364 | | MASK_DEBUG_TARGET \ |
365 | | MASK_DEBUG_BUILTIN) | |
fd438373 MM |
366 | |
367 | #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) | |
368 | #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) | |
369 | #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) | |
370 | #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) | |
371 | #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) | |
372 | #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) | |
7fa14a01 | 373 | #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) |
cacf1ca8 MM |
374 | |
375 | extern enum rs6000_vector rs6000_vector_unit[]; | |
376 | ||
377 | #define VECTOR_UNIT_NONE_P(MODE) \ | |
378 | (rs6000_vector_unit[(MODE)] == VECTOR_NONE) | |
379 | ||
380 | #define VECTOR_UNIT_VSX_P(MODE) \ | |
381 | (rs6000_vector_unit[(MODE)] == VECTOR_VSX) | |
382 | ||
383 | #define VECTOR_UNIT_ALTIVEC_P(MODE) \ | |
384 | (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) | |
385 | ||
386 | #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ | |
387 | (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \ | |
388 | || rs6000_vector_unit[(MODE)] == VECTOR_VSX) | |
389 | ||
390 | /* Describe whether to use VSX loads or Altivec loads. For now, just use the | |
391 | same unit as the vector unit we are using, but we may want to migrate to | |
392 | using VSX style loads even for types handled by altivec. */ | |
393 | extern enum rs6000_vector rs6000_vector_mem[]; | |
394 | ||
395 | #define VECTOR_MEM_NONE_P(MODE) \ | |
396 | (rs6000_vector_mem[(MODE)] == VECTOR_NONE) | |
397 | ||
398 | #define VECTOR_MEM_VSX_P(MODE) \ | |
399 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
400 | ||
401 | #define VECTOR_MEM_ALTIVEC_P(MODE) \ | |
402 | (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) | |
403 | ||
404 | #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ | |
405 | (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \ | |
406 | || rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
407 | ||
408 | /* Return the alignment of a given vector type, which is set based on the | |
409 | vector unit use. VSX for instance can load 32 or 64 bit aligned words | |
410 | without problems, while Altivec requires 128-bit aligned vectors. */ | |
411 | extern int rs6000_vector_align[]; | |
412 | ||
413 | #define VECTOR_ALIGN(MODE) \ | |
414 | ((rs6000_vector_align[(MODE)] != 0) \ | |
415 | ? rs6000_vector_align[(MODE)] \ | |
416 | : (int)GET_MODE_BITSIZE ((MODE))) | |
417 | ||
025d9908 KH |
418 | /* Alignment options for fields in structures for sub-targets following |
419 | AIX-like ABI. | |
420 | ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
421 | ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
422 | ||
423 | Override the macro definitions when compiling libobjc to avoid undefined | |
424 | reference to rs6000_alignment_flags due to library's use of GCC alignment | |
425 | macros which use the macros below. */ | |
f676971a | 426 | |
025d9908 KH |
427 | #ifndef IN_TARGET_LIBS |
428 | #define MASK_ALIGN_POWER 0x00000000 | |
429 | #define MASK_ALIGN_NATURAL 0x00000001 | |
430 | #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
431 | #else | |
432 | #define TARGET_ALIGN_NATURAL 0 | |
433 | #endif | |
6fa3f289 ZW |
434 | |
435 | #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) | |
602ea4d3 | 436 | #define TARGET_IEEEQUAD rs6000_ieeequad |
6fa3f289 | 437 | #define TARGET_ALTIVEC_ABI rs6000_altivec_abi |
cacf1ca8 | 438 | #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
6fa3f289 | 439 | |
a3170dc6 AH |
440 | #define TARGET_SPE_ABI 0 |
441 | #define TARGET_SPE 0 | |
cacf1ca8 | 442 | #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) |
a3170dc6 | 443 | #define TARGET_FPRS 1 |
4d4cbc0e AH |
444 | #define TARGET_E500_SINGLE 0 |
445 | #define TARGET_E500_DOUBLE 0 | |
eca0d5e8 | 446 | #define CHECK_E500_OPTIONS do { } while (0) |
a3170dc6 | 447 | |
7042fe5e MM |
448 | /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
449 | Enable 32-bit fcfid's on any of the switches for newer ISA machines or | |
450 | XILINX. */ | |
c3f8384f MM |
451 | #define TARGET_FCFID (TARGET_POWERPC64 \ |
452 | || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
453 | || TARGET_POPCNTB /* ISA 2.02 */ \ | |
454 | || TARGET_CMPB /* ISA 2.05 */ \ | |
455 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
7042fe5e MM |
456 | || TARGET_XILINX_FPU) |
457 | ||
458 | #define TARGET_FCTIDZ TARGET_FCFID | |
459 | #define TARGET_STFIWX TARGET_PPC_GFXOPT | |
460 | #define TARGET_LFIWAX TARGET_CMPB | |
461 | #define TARGET_LFIWZX TARGET_POPCNTD | |
462 | #define TARGET_FCFIDS TARGET_POPCNTD | |
463 | #define TARGET_FCFIDU TARGET_POPCNTD | |
464 | #define TARGET_FCFIDUS TARGET_POPCNTD | |
465 | #define TARGET_FCTIDUZ TARGET_POPCNTD | |
466 | #define TARGET_FCTIWUZ TARGET_POPCNTD | |
467 | ||
4d967549 MM |
468 | /* In switching from using target_flags to using rs6000_isa_flags, the options |
469 | machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map | |
470 | OPTION_MASK_<xxx> back into MASK_<xxx>. */ | |
471 | #define MASK_ALTIVEC OPTION_MASK_ALTIVEC | |
472 | #define MASK_CMPB OPTION_MASK_CMPB | |
473 | #define MASK_DFP OPTION_MASK_DFP | |
474 | #define MASK_DLMZB OPTION_MASK_DLMZB | |
475 | #define MASK_EABI OPTION_MASK_EABI | |
476 | #define MASK_FPRND OPTION_MASK_FPRND | |
477 | #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT | |
478 | #define MASK_ISEL OPTION_MASK_ISEL | |
479 | #define MASK_MFCRF OPTION_MASK_MFCRF | |
480 | #define MASK_MFPGPR OPTION_MASK_MFPGPR | |
481 | #define MASK_MULHW OPTION_MASK_MULHW | |
482 | #define MASK_MULTIPLE OPTION_MASK_MULTIPLE | |
483 | #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE | |
484 | #define MASK_POPCNTB OPTION_MASK_POPCNTB | |
485 | #define MASK_POPCNTD OPTION_MASK_POPCNTD | |
486 | #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT | |
487 | #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT | |
488 | #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION | |
489 | #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT | |
490 | #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN | |
491 | #define MASK_STRING OPTION_MASK_STRING | |
492 | #define MASK_UPDATE OPTION_MASK_UPDATE | |
493 | #define MASK_VSX OPTION_MASK_VSX | |
494 | ||
495 | #ifndef IN_LIBGCC2 | |
496 | #define MASK_POWERPC64 OPTION_MASK_POWERPC64 | |
497 | #endif | |
498 | ||
499 | #ifdef TARGET_64BIT | |
500 | #define MASK_64BIT OPTION_MASK_64BIT | |
501 | #endif | |
502 | ||
503 | #ifdef TARGET_RELOCATABLE | |
504 | #define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE | |
505 | #endif | |
506 | ||
507 | #ifdef TARGET_LITTLE_ENDIAN | |
508 | #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN | |
509 | #endif | |
510 | ||
511 | #ifdef TARGET_MINIMAL_TOC | |
512 | #define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC | |
513 | #endif | |
514 | ||
515 | #ifdef TARGET_REGNAMES | |
516 | #define MASK_REGNAMES OPTION_MASK_REGNAMES | |
517 | #endif | |
518 | ||
519 | #ifdef TARGET_PROTOTYPE | |
520 | #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE | |
521 | #endif | |
522 | ||
523 | /* Explicit ISA options that were set. */ | |
524 | #define rs6000_isa_flags_explicit global_options_set.x_rs6000_isa_flags | |
525 | ||
7fa14a01 MM |
526 | /* For power systems, we want to enable Altivec and VSX builtins even if the |
527 | user did not use -maltivec or -mvsx to allow the builtins to be used inside | |
528 | of #pragma GCC target or the target attribute to change the code level for a | |
529 | given system. The SPE and Paired builtins are only enabled if you configure | |
530 | the compiler for those builtins, and those machines don't support altivec or | |
531 | VSX. */ | |
532 | ||
533 | #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \ | |
534 | && ((TARGET_POWERPC64 \ | |
c3f8384f | 535 | || TARGET_PPC_GPOPT /* 970/power4 */ \ |
7fa14a01 MM |
536 | || TARGET_POPCNTB /* ISA 2.02 */ \ |
537 | || TARGET_CMPB /* ISA 2.05 */ \ | |
538 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
539 | || TARGET_ALTIVEC \ | |
540 | || TARGET_VSX))) | |
541 | ||
a7c6c6d6 OH |
542 | /* E500 cores only support plain "sync", not lwsync. */ |
543 | #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | |
544 | || rs6000_cpu == PROCESSOR_PPC8548) | |
7fa14a01 MM |
545 | |
546 | ||
92902797 MM |
547 | /* Which machine supports the various reciprocal estimate instructions. */ |
548 | #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ | |
549 | && TARGET_FPRS && TARGET_SINGLE_FLOAT) | |
550 | ||
551 | #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ | |
552 | && TARGET_DOUBLE_FLOAT \ | |
553 | && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) | |
554 | ||
555 | #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ | |
556 | && TARGET_FPRS && TARGET_SINGLE_FLOAT) | |
557 | ||
558 | #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ | |
559 | && TARGET_DOUBLE_FLOAT \ | |
560 | && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) | |
561 | ||
562 | /* Whether the various reciprocal divide/square root estimate instructions | |
563 | exist, and whether we should automatically generate code for the instruction | |
564 | by default. */ | |
565 | #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ | |
566 | #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ | |
567 | #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ | |
568 | #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ | |
569 | ||
570 | extern unsigned char rs6000_recip_bits[]; | |
571 | ||
572 | #define RS6000_RECIP_HAVE_RE_P(MODE) \ | |
573 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) | |
574 | ||
575 | #define RS6000_RECIP_AUTO_RE_P(MODE) \ | |
576 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) | |
577 | ||
578 | #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ | |
579 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) | |
580 | ||
581 | #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ | |
582 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) | |
583 | ||
584 | #define RS6000_RECIP_HIGH_PRECISION_P(MODE) \ | |
585 | ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION) | |
586 | ||
c5387660 JM |
587 | /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
588 | #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT | |
f045b2c9 | 589 | |
a5c76ee6 | 590 | /* Target pragma. */ |
c58b209a NB |
591 | #define REGISTER_TARGET_PRAGMAS() do { \ |
592 | c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
fd438373 | 593 | targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
2fab365e | 594 | targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
7fa14a01 | 595 | rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ |
a5c76ee6 ZW |
596 | } while (0) |
597 | ||
4c4eb375 GK |
598 | /* Target #defines. */ |
599 | #define TARGET_CPU_CPP_BUILTINS() \ | |
600 | rs6000_cpu_cpp_builtins (pfile) | |
647d340d JT |
601 | |
602 | /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
603 | we're compiling for. Some configurations may need to override it. */ | |
604 | #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
605 | do \ | |
606 | { \ | |
607 | if (BYTES_BIG_ENDIAN) \ | |
608 | { \ | |
609 | builtin_define ("__BIG_ENDIAN__"); \ | |
610 | builtin_define ("_BIG_ENDIAN"); \ | |
611 | builtin_assert ("machine=bigendian"); \ | |
612 | } \ | |
613 | else \ | |
614 | { \ | |
615 | builtin_define ("__LITTLE_ENDIAN__"); \ | |
616 | builtin_define ("_LITTLE_ENDIAN"); \ | |
617 | builtin_assert ("machine=littleendian"); \ | |
618 | } \ | |
619 | } \ | |
620 | while (0) | |
f045b2c9 | 621 | \f |
4c4eb375 | 622 | /* Target machine storage layout. */ |
f045b2c9 | 623 | |
13d39dbc | 624 | /* Define this macro if it is advisable to hold scalars in registers |
c81bebd7 | 625 | in a wider mode than that declared by the program. In such cases, |
ef457bda RK |
626 | the value is constrained to be within the bounds of the declared |
627 | type, but kept valid in the wider mode. The signedness of the | |
628 | extension may differ from that of the type. */ | |
629 | ||
39403d82 DE |
630 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
631 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
632 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
b78d48dd | 633 | (MODE) = TARGET_32BIT ? SImode : DImode; |
39403d82 | 634 | |
f045b2c9 | 635 | /* Define this if most significant bit is lowest numbered |
82e41834 KH |
636 | in instructions that operate on numbered bit-fields. */ |
637 | /* That is true on RS/6000. */ | |
f045b2c9 RS |
638 | #define BITS_BIG_ENDIAN 1 |
639 | ||
640 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
641 | /* That is true on RS/6000. */ | |
642 | #define BYTES_BIG_ENDIAN 1 | |
643 | ||
644 | /* Define this if most significant word of a multiword number is lowest | |
c81bebd7 | 645 | numbered. |
f045b2c9 RS |
646 | |
647 | For RS/6000 we can decide arbitrarily since there are no machine | |
82e41834 | 648 | instructions for them. Might as well be consistent with bits and bytes. */ |
f045b2c9 RS |
649 | #define WORDS_BIG_ENDIAN 1 |
650 | ||
2e360ab3 | 651 | #define MAX_BITS_PER_WORD 64 |
f045b2c9 RS |
652 | |
653 | /* Width of a word, in units (bytes). */ | |
c1aa3958 | 654 | #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) |
f34fc46e DE |
655 | #ifdef IN_LIBGCC2 |
656 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
657 | #else | |
ef0e53ce | 658 | #define MIN_UNITS_PER_WORD 4 |
f34fc46e | 659 | #endif |
2e360ab3 | 660 | #define UNITS_PER_FP_WORD 8 |
0ac081f6 | 661 | #define UNITS_PER_ALTIVEC_WORD 16 |
cacf1ca8 | 662 | #define UNITS_PER_VSX_WORD 16 |
a3170dc6 | 663 | #define UNITS_PER_SPE_WORD 8 |
96038623 | 664 | #define UNITS_PER_PAIRED_WORD 8 |
f045b2c9 | 665 | |
915f619f JW |
666 | /* Type used for ptrdiff_t, as a string used in a declaration. */ |
667 | #define PTRDIFF_TYPE "int" | |
668 | ||
058ef853 DE |
669 | /* Type used for size_t, as a string used in a declaration. */ |
670 | #define SIZE_TYPE "long unsigned int" | |
671 | ||
f045b2c9 RS |
672 | /* Type used for wchar_t, as a string used in a declaration. */ |
673 | #define WCHAR_TYPE "short unsigned int" | |
674 | ||
675 | /* Width of wchar_t in bits. */ | |
676 | #define WCHAR_TYPE_SIZE 16 | |
677 | ||
9e654916 RK |
678 | /* A C expression for the size in bits of the type `short' on the |
679 | target machine. If you don't define this, the default is half a | |
680 | word. (If this would be less than one storage unit, it is | |
681 | rounded up to one unit.) */ | |
682 | #define SHORT_TYPE_SIZE 16 | |
683 | ||
684 | /* A C expression for the size in bits of the type `int' on the | |
685 | target machine. If you don't define this, the default is one | |
686 | word. */ | |
19d2d16f | 687 | #define INT_TYPE_SIZE 32 |
9e654916 RK |
688 | |
689 | /* A C expression for the size in bits of the type `long' on the | |
690 | target machine. If you don't define this, the default is one | |
691 | word. */ | |
2f3e5814 | 692 | #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) |
9e654916 RK |
693 | |
694 | /* A C expression for the size in bits of the type `long long' on the | |
695 | target machine. If you don't define this, the default is two | |
696 | words. */ | |
697 | #define LONG_LONG_TYPE_SIZE 64 | |
698 | ||
9e654916 RK |
699 | /* A C expression for the size in bits of the type `float' on the |
700 | target machine. If you don't define this, the default is one | |
701 | word. */ | |
702 | #define FLOAT_TYPE_SIZE 32 | |
703 | ||
704 | /* A C expression for the size in bits of the type `double' on the | |
705 | target machine. If you don't define this, the default is two | |
706 | words. */ | |
707 | #define DOUBLE_TYPE_SIZE 64 | |
708 | ||
709 | /* A C expression for the size in bits of the type `long double' on | |
710 | the target machine. If you don't define this, the default is two | |
711 | words. */ | |
6fa3f289 | 712 | #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
06f4e019 | 713 | |
06f4e019 DE |
714 | /* Define this to set long double type size to use in libgcc2.c, which can |
715 | not depend on target_flags. */ | |
716 | #ifdef __LONG_DOUBLE_128__ | |
717 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
718 | #else | |
719 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
720 | #endif | |
9e654916 | 721 | |
5b8f5865 DE |
722 | /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ |
723 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
724 | ||
f045b2c9 RS |
725 | /* Width in bits of a pointer. |
726 | See also the macro `Pmode' defined below. */ | |
cacf1ca8 MM |
727 | extern unsigned rs6000_pointer_size; |
728 | #define POINTER_SIZE rs6000_pointer_size | |
f045b2c9 RS |
729 | |
730 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
2f3e5814 | 731 | #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
732 | |
733 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
cacf1ca8 MM |
734 | #define STACK_BOUNDARY \ |
735 | ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ | |
736 | ? 64 : 128) | |
f045b2c9 RS |
737 | |
738 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
739 | #define FUNCTION_BOUNDARY 32 | |
740 | ||
741 | /* No data type wants to be aligned rounder than this. */ | |
0ac081f6 AH |
742 | #define BIGGEST_ALIGNMENT 128 |
743 | ||
744 | /* A C expression to compute the alignment for a variables in the | |
745 | local store. TYPE is the data type, and ALIGN is the alignment | |
746 | that the object would ordinarily have. */ | |
747 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
777a3a6a | 748 | DATA_ALIGNMENT (TYPE, ALIGN) |
b73fd26c | 749 | |
f045b2c9 RS |
750 | /* Alignment of field after `int : 0' in a structure. */ |
751 | #define EMPTY_FIELD_BOUNDARY 32 | |
752 | ||
753 | /* Every structure's size must be a multiple of this. */ | |
754 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
755 | ||
43a88a8c | 756 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
f045b2c9 RS |
757 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
758 | ||
69ef87e2 AH |
759 | /* Make strings word-aligned so strcpy from constants will be faster. |
760 | Make vector constants quadword aligned. */ | |
761 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
762 | (TREE_CODE (EXP) == STRING_CST \ | |
153fbec8 | 763 | && (STRICT_ALIGNMENT || !optimize_size) \ |
69ef87e2 AH |
764 | && (ALIGN) < BITS_PER_WORD \ |
765 | ? BITS_PER_WORD \ | |
766 | : (ALIGN)) | |
f045b2c9 | 767 | |
0ac081f6 | 768 | /* Make arrays of chars word-aligned for the same reasons. |
f82f556d AH |
769 | Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to |
770 | 64 bits. */ | |
b851135c NF |
771 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
772 | (TREE_CODE (TYPE) == VECTOR_TYPE \ | |
773 | ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \ | |
774 | || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \ | |
775 | ? 64 : 128) \ | |
776 | : ((TARGET_E500_DOUBLE \ | |
777 | && TREE_CODE (TYPE) == REAL_TYPE \ | |
778 | && TYPE_MODE (TYPE) == DFmode) \ | |
779 | ? 64 \ | |
780 | : (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
781 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
782 | && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))) | |
f045b2c9 | 783 | |
a0ab749a | 784 | /* Nonzero if move instructions will actually fail to work |
f045b2c9 | 785 | when given unaligned data. */ |
fdaff8ba | 786 | #define STRICT_ALIGNMENT 0 |
e1565e65 DE |
787 | |
788 | /* Define this macro to be the value 1 if unaligned accesses have a cost | |
789 | many times greater than aligned accesses, for example if they are | |
790 | emulated in a trap handler. */ | |
cacf1ca8 MM |
791 | /* Altivec vector memory instructions simply ignore the low bits; SPE vector |
792 | memory instructions trap on unaligned accesses; VSX memory instructions are | |
793 | aligned to 4 or 8 bytes. */ | |
41543739 GK |
794 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ |
795 | (STRICT_ALIGNMENT \ | |
fcce224d | 796 | || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ |
9f89e66e | 797 | || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) \ |
54ce9cc2 | 798 | && (ALIGN) < 32) \ |
cacf1ca8 MM |
799 | || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE)))) |
800 | ||
f045b2c9 RS |
801 | \f |
802 | /* Standard register usage. */ | |
803 | ||
804 | /* Number of actual hardware registers. | |
805 | The hardware registers are assigned numbers for the compiler | |
806 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
807 | All registers that the compiler knows about must be given numbers, | |
808 | even those that are not normally considered general registers. | |
809 | ||
810 | RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
462f7901 SB |
811 | a count register, a link register, and 8 condition register fields, |
812 | which we view here as separate registers. AltiVec adds 32 vector | |
813 | registers and a VRsave register. | |
f045b2c9 RS |
814 | |
815 | In addition, the difference between the frame and argument pointers is | |
816 | a function of the number of registers saved, so we need to have a | |
817 | register for AP that will later be eliminated in favor of SP or FP. | |
802a0058 | 818 | This is a normal register, but it is fixed. |
f045b2c9 | 819 | |
802a0058 MM |
820 | We also create a pseudo register for float/int conversions, that will |
821 | really represent the memory location used. It is represented here as | |
822 | a register, in order to work around problems in allocating stack storage | |
7d5175e1 | 823 | in inline functions. |
802a0058 | 824 | |
7d5175e1 JJ |
825 | Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame |
826 | pointer, which is eventually eliminated in favor of SP or FP. */ | |
827 | ||
828 | #define FIRST_PSEUDO_REGISTER 114 | |
f045b2c9 | 829 | |
d6a7951f | 830 | /* This must be included for pre gcc 3.0 glibc compatibility. */ |
7d5f33bc | 831 | #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 |
62153b61 | 832 | |
93c9d1ba | 833 | /* Add 32 dwarf columns for synthetic SPE registers. */ |
7d5175e1 | 834 | #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32) |
c19de7aa | 835 | |
93c9d1ba AM |
836 | /* The SPE has an additional 32 synthetic registers, with DWARF debug |
837 | info numbering for these registers starting at 1200. While eh_frame | |
838 | register numbering need not be the same as the debug info numbering, | |
839 | we choose to number these regs for eh_frame at 1200 too. This allows | |
840 | future versions of the rs6000 backend to add hard registers and | |
841 | continue to use the gcc hard register numbering for eh_frame. If the | |
842 | extra SPE registers in eh_frame were numbered starting from the | |
843 | current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER | |
844 | changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to | |
845 | avoid invalidating older SPE eh_frame info. | |
846 | ||
847 | We must map them here to avoid huge unwinder tables mostly consisting | |
f676971a | 848 | of unused space. */ |
93c9d1ba | 849 | #define DWARF_REG_TO_UNWIND_COLUMN(r) \ |
7d5175e1 | 850 | ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r)) |
93c9d1ba | 851 | |
ed1cf8ff GK |
852 | /* Use standard DWARF numbering for DWARF debugging information. */ |
853 | #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) | |
854 | ||
93c9d1ba AM |
855 | /* Use gcc hard register numbering for eh_frame. */ |
856 | #define DWARF_FRAME_REGNUM(REGNO) (REGNO) | |
41f3a930 | 857 | |
ed1cf8ff GK |
858 | /* Map register numbers held in the call frame info that gcc has |
859 | collected using DWARF_FRAME_REGNUM to those that should be output in | |
860 | .debug_frame and .eh_frame. We continue to use gcc hard reg numbers | |
861 | for .eh_frame, but use the numbers mandated by the various ABIs for | |
862 | .debug_frame. rs6000_emit_prologue has translated any combination of | |
863 | CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves | |
864 | the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */ | |
865 | #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
866 | ((FOR_EH) ? (REGNO) \ | |
867 | : (REGNO) == CR2_REGNO ? 64 \ | |
868 | : DBX_REGISTER_NUMBER (REGNO)) | |
869 | ||
f045b2c9 RS |
870 | /* 1 for registers that have pervasive standard uses |
871 | and are not available for the register allocator. | |
872 | ||
5dead3e5 DJ |
873 | On RS/6000, r1 is used for the stack. On Darwin, r2 is available |
874 | as a local register; for all other OS's r2 is the TOC pointer. | |
f045b2c9 | 875 | |
a127c4e5 RK |
876 | cr5 is not supposed to be used. |
877 | ||
878 | On System V implementations, r13 is fixed and not available for use. */ | |
879 | ||
f045b2c9 | 880 | #define FIXED_REGISTERS \ |
5dead3e5 | 881 | {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
882 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
883 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
884 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
885 | 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ |
886 | /* AltiVec registers. */ \ | |
887 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
888 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 889 | 1, 1 \ |
7d5175e1 | 890 | , 1, 1, 1 \ |
0ac081f6 | 891 | } |
f045b2c9 RS |
892 | |
893 | /* 1 for registers not available across function calls. | |
894 | These must include the FIXED_REGISTERS and also any | |
895 | registers that can be used without being saved. | |
896 | The latter must include the registers where values are returned | |
897 | and the register where structure-value addresses are passed. | |
898 | Aside from that, you can include as many other registers as you like. */ | |
899 | ||
900 | #define CALL_USED_REGISTERS \ | |
a127c4e5 | 901 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
902 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
903 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
904 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
905 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
906 | /* AltiVec registers. */ \ | |
907 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
908 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 909 | 1, 1 \ |
7d5175e1 | 910 | , 1, 1, 1 \ |
0ac081f6 AH |
911 | } |
912 | ||
289e96b2 AH |
913 | /* Like `CALL_USED_REGISTERS' except this macro doesn't require that |
914 | the entire set of `FIXED_REGISTERS' be included. | |
915 | (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
916 | This macro is optional. If not specified, it defaults to the value | |
917 | of `CALL_USED_REGISTERS'. */ | |
f676971a | 918 | |
289e96b2 AH |
919 | #define CALL_REALLY_USED_REGISTERS \ |
920 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
921 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
922 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
923 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
924 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ | |
925 | /* AltiVec registers. */ \ | |
926 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
927 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 928 | 0, 0 \ |
7d5175e1 | 929 | , 0, 0, 0 \ |
289e96b2 | 930 | } |
f045b2c9 | 931 | |
28bcfd4d | 932 | #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) |
9ebbca7d | 933 | |
d62294f5 | 934 | #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) |
b427dd7a AM |
935 | #define FIRST_SAVED_FP_REGNO (14+32) |
936 | #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) | |
d62294f5 | 937 | |
f045b2c9 RS |
938 | /* List the order in which to allocate registers. Each register must be |
939 | listed once, even those in FIXED_REGISTERS. | |
940 | ||
941 | We allocate in the following order: | |
942 | fp0 (not saved or used for anything) | |
943 | fp13 - fp2 (not saved; incoming fp arg registers) | |
944 | fp1 (not saved; return value) | |
9390387d | 945 | fp31 - fp14 (saved; order given to save least number) |
5accd822 DE |
946 | cr7, cr6 (not saved or special) |
947 | cr1 (not saved, but used for FP operations) | |
f045b2c9 | 948 | cr0 (not saved, but used for arithmetic operations) |
5accd822 | 949 | cr4, cr3, cr2 (saved) |
f045b2c9 | 950 | r9 (not saved; best for TImode) |
d44b26bd | 951 | r10, r8-r4 (not saved; highest first for less conflict with params) |
9390387d | 952 | r3 (not saved; return value register) |
d44b26bd AM |
953 | r11 (not saved; later alloc to help shrink-wrap) |
954 | r0 (not saved; cannot be base reg) | |
f045b2c9 RS |
955 | r31 - r13 (saved; order given to save least number) |
956 | r12 (not saved; if used for DImode or DFmode would use r13) | |
f045b2c9 RS |
957 | ctr (not saved; when we have the choice ctr is better) |
958 | lr (saved) | |
f6b5d695 | 959 | cr5, r1, r2, ap, ca (fixed) |
9390387d AM |
960 | v0 - v1 (not saved or used for anything) |
961 | v13 - v3 (not saved; incoming vector arg registers) | |
962 | v2 (not saved; incoming vector arg reg; return value) | |
963 | v19 - v14 (not saved or used for anything) | |
964 | v31 - v20 (saved; order given to save least number) | |
965 | vrsave, vscr (fixed) | |
a3170dc6 | 966 | spe_acc, spefscr (fixed) |
7d5175e1 | 967 | sfp (fixed) |
0ac081f6 | 968 | */ |
f676971a | 969 | |
6b13641d DJ |
970 | #if FIXED_R2 == 1 |
971 | #define MAYBE_R2_AVAILABLE | |
972 | #define MAYBE_R2_FIXED 2, | |
973 | #else | |
974 | #define MAYBE_R2_AVAILABLE 2, | |
975 | #define MAYBE_R2_FIXED | |
976 | #endif | |
f045b2c9 | 977 | |
d44b26bd AM |
978 | #if FIXED_R13 == 1 |
979 | #define EARLY_R12 12, | |
980 | #define LATE_R12 | |
981 | #else | |
982 | #define EARLY_R12 | |
983 | #define LATE_R12 12, | |
984 | #endif | |
985 | ||
9390387d AM |
986 | #define REG_ALLOC_ORDER \ |
987 | {32, \ | |
988 | 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ | |
989 | 33, \ | |
990 | 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
991 | 50, 49, 48, 47, 46, \ | |
992 | 75, 74, 69, 68, 72, 71, 70, \ | |
d44b26bd AM |
993 | MAYBE_R2_AVAILABLE \ |
994 | 9, 10, 8, 7, 6, 5, 4, \ | |
995 | 3, EARLY_R12 11, 0, \ | |
9390387d | 996 | 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ |
d44b26bd | 997 | 18, 17, 16, 15, 14, 13, LATE_R12 \ |
462f7901 | 998 | 66, 65, \ |
9390387d AM |
999 | 73, 1, MAYBE_R2_FIXED 67, 76, \ |
1000 | /* AltiVec registers. */ \ | |
1001 | 77, 78, \ | |
1002 | 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
1003 | 79, \ | |
1004 | 96, 95, 94, 93, 92, 91, \ | |
1005 | 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ | |
1006 | 109, 110, \ | |
7d5175e1 | 1007 | 111, 112, 113 \ |
0ac081f6 | 1008 | } |
f045b2c9 RS |
1009 | |
1010 | /* True if register is floating-point. */ | |
1011 | #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
1012 | ||
1013 | /* True if register is a condition register. */ | |
1de43f85 | 1014 | #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) |
f045b2c9 | 1015 | |
815cdc52 | 1016 | /* True if register is a condition register, but not cr0. */ |
1de43f85 | 1017 | #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) |
815cdc52 | 1018 | |
f045b2c9 | 1019 | /* True if register is an integer register. */ |
7d5175e1 JJ |
1020 | #define INT_REGNO_P(N) \ |
1021 | ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
f045b2c9 | 1022 | |
a3170dc6 AH |
1023 | /* SPE SIMD registers are just the GPRs. */ |
1024 | #define SPE_SIMD_REGNO_P(N) ((N) <= 31) | |
1025 | ||
96038623 DE |
1026 | /* PAIRED SIMD registers are just the FPRs. */ |
1027 | #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
1028 | ||
f6b5d695 SB |
1029 | /* True if register is the CA register. */ |
1030 | #define CA_REGNO_P(N) ((N) == CA_REGNO) | |
802a0058 | 1031 | |
0ac081f6 AH |
1032 | /* True if register is an AltiVec register. */ |
1033 | #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
1034 | ||
cacf1ca8 MM |
1035 | /* True if register is a VSX register. */ |
1036 | #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) | |
1037 | ||
1038 | /* Alternate name for any vector register supporting floating point, no matter | |
1039 | which instruction set(s) are available. */ | |
1040 | #define VFLOAT_REGNO_P(N) \ | |
1041 | (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) | |
1042 | ||
1043 | /* Alternate name for any vector register supporting integer, no matter which | |
1044 | instruction set(s) are available. */ | |
1045 | #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) | |
1046 | ||
1047 | /* Alternate name for any vector register supporting logical operations, no | |
1048 | matter which instruction set(s) are available. */ | |
1049 | #define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N) | |
1050 | ||
f045b2c9 | 1051 | /* Return number of consecutive hard regs needed starting at reg REGNO |
d8ecbcdb AH |
1052 | to hold something of mode MODE. */ |
1053 | ||
cacf1ca8 | 1054 | #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] |
0e67400a | 1055 | |
79eefb0d PH |
1056 | /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
1057 | enough space to account for vectors in FP regs. */ | |
dbcc9f08 MM |
1058 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1059 | (TARGET_VSX \ | |
1060 | && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ | |
79eefb0d PH |
1061 | && FP_REGNO_P (REGNO) \ |
1062 | ? V2DFmode \ | |
1063 | : choose_hard_reg_mode ((REGNO), (NREGS), false)) | |
1064 | ||
3fc841c8 MM |
1065 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ |
1066 | (((TARGET_32BIT && TARGET_POWERPC64 \ | |
1067 | && (GET_MODE_SIZE (MODE) > 4) \ | |
1068 | && INT_REGNO_P (REGNO)) ? 1 : 0) \ | |
1069 | || (TARGET_VSX && FP_REGNO_P (REGNO) \ | |
1070 | && GET_MODE_SIZE (MODE) > 8)) | |
f045b2c9 | 1071 | |
cacf1ca8 MM |
1072 | #define VSX_VECTOR_MODE(MODE) \ |
1073 | ((MODE) == V4SFmode \ | |
1074 | || (MODE) == V2DFmode) \ | |
1075 | ||
0ac081f6 | 1076 | #define ALTIVEC_VECTOR_MODE(MODE) \ |
cb2a532e AH |
1077 | ((MODE) == V16QImode \ |
1078 | || (MODE) == V8HImode \ | |
1079 | || (MODE) == V4SFmode \ | |
6e1f54e2 | 1080 | || (MODE) == V4SImode) |
0ac081f6 | 1081 | |
dbcc9f08 MM |
1082 | #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ |
1083 | (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ | |
1084 | || (MODE) == V2DImode) | |
1085 | ||
a3170dc6 AH |
1086 | #define SPE_VECTOR_MODE(MODE) \ |
1087 | ((MODE) == V4HImode \ | |
1088 | || (MODE) == V2SFmode \ | |
00a892b8 | 1089 | || (MODE) == V1DImode \ |
a3170dc6 AH |
1090 | || (MODE) == V2SImode) |
1091 | ||
96038623 DE |
1092 | #define PAIRED_VECTOR_MODE(MODE) \ |
1093 | ((MODE) == V2SFmode) | |
1094 | ||
0d1fbc8c AH |
1095 | /* Value is TRUE if hard register REGNO can hold a value of |
1096 | machine-mode MODE. */ | |
1097 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
1098 | rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] | |
f045b2c9 RS |
1099 | |
1100 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1101 | when one has mode MODE1 and one has mode MODE2. | |
1102 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1103 | for any hard reg, then this must be 0 for correct output. */ | |
1104 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
ebb109ad BE |
1105 | (SCALAR_FLOAT_MODE_P (MODE1) \ |
1106 | ? SCALAR_FLOAT_MODE_P (MODE2) \ | |
1107 | : SCALAR_FLOAT_MODE_P (MODE2) \ | |
1108 | ? SCALAR_FLOAT_MODE_P (MODE1) \ | |
f045b2c9 RS |
1109 | : GET_MODE_CLASS (MODE1) == MODE_CC \ |
1110 | ? GET_MODE_CLASS (MODE2) == MODE_CC \ | |
1111 | : GET_MODE_CLASS (MODE2) == MODE_CC \ | |
1112 | ? GET_MODE_CLASS (MODE1) == MODE_CC \ | |
4dcc01f3 AH |
1113 | : SPE_VECTOR_MODE (MODE1) \ |
1114 | ? SPE_VECTOR_MODE (MODE2) \ | |
1115 | : SPE_VECTOR_MODE (MODE2) \ | |
1116 | ? SPE_VECTOR_MODE (MODE1) \ | |
0ac081f6 AH |
1117 | : ALTIVEC_VECTOR_MODE (MODE1) \ |
1118 | ? ALTIVEC_VECTOR_MODE (MODE2) \ | |
1119 | : ALTIVEC_VECTOR_MODE (MODE2) \ | |
1120 | ? ALTIVEC_VECTOR_MODE (MODE1) \ | |
dbcc9f08 MM |
1121 | : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ |
1122 | ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ | |
1123 | : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ | |
1124 | ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ | |
f045b2c9 RS |
1125 | : 1) |
1126 | ||
c8ae788f SB |
1127 | /* Post-reload, we can't use any new AltiVec registers, as we already |
1128 | emitted the vrsave mask. */ | |
1129 | ||
1130 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
6fb5fa3c | 1131 | (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) |
c8ae788f | 1132 | |
f045b2c9 RS |
1133 | /* Specify the cost of a branch insn; roughly the number of extra insns that |
1134 | should be added to avoid a branch. | |
1135 | ||
ef457bda | 1136 | Set this to 3 on the RS/6000 since that is roughly the average cost of an |
f045b2c9 RS |
1137 | unscheduled conditional branch. */ |
1138 | ||
3a4fd356 | 1139 | #define BRANCH_COST(speed_p, predictable_p) 3 |
f045b2c9 | 1140 | |
85e50b6b | 1141 | /* Override BRANCH_COST heuristic which empirically produces worse |
b8610a53 | 1142 | performance for removing short circuiting from the logical ops. */ |
85e50b6b | 1143 | |
b8610a53 | 1144 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 |
a3170dc6 | 1145 | |
52ff33d0 NF |
1146 | /* A fixed register used at epilogue generation to address SPE registers |
1147 | with negative offsets. The 64-bit load/store instructions on the SPE | |
1148 | only take positive offsets (and small ones at that), so we need to | |
1149 | reserve a register for consing up negative offsets. */ | |
a3170dc6 | 1150 | |
52ff33d0 | 1151 | #define FIXED_SCRATCH 0 |
a3170dc6 | 1152 | |
f045b2c9 RS |
1153 | /* Specify the registers used for certain standard purposes. |
1154 | The values of these macros are register numbers. */ | |
1155 | ||
1156 | /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
1157 | /* #define PC_REGNUM */ | |
1158 | ||
1159 | /* Register to use for pushing function arguments. */ | |
1160 | #define STACK_POINTER_REGNUM 1 | |
1161 | ||
1162 | /* Base register for access to local variables of the function. */ | |
7d5175e1 JJ |
1163 | #define HARD_FRAME_POINTER_REGNUM 31 |
1164 | ||
1165 | /* Base register for access to local variables of the function. */ | |
1166 | #define FRAME_POINTER_REGNUM 113 | |
f045b2c9 | 1167 | |
f045b2c9 RS |
1168 | /* Base register for access to arguments of the function. */ |
1169 | #define ARG_POINTER_REGNUM 67 | |
1170 | ||
1171 | /* Place to put static chain when calling a function that requires it. */ | |
1172 | #define STATIC_CHAIN_REGNUM 11 | |
1173 | ||
f045b2c9 RS |
1174 | \f |
1175 | /* Define the classes of registers for register constraints in the | |
1176 | machine description. Also define ranges of constants. | |
1177 | ||
1178 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1179 | If there is more than one class, another class must be named NO_REGS | |
1180 | and contain no registers. | |
1181 | ||
1182 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1183 | another name such as ALL_REGS). This is the class of registers | |
1184 | that is allowed by "g" or "r" in a register constraint. | |
1185 | Also, registers outside this class are allocated only when | |
1186 | instructions express preferences for them. | |
1187 | ||
1188 | The classes must be numbered in nondecreasing order; that is, | |
1189 | a larger-numbered class must never be contained completely | |
1190 | in a smaller-numbered class. | |
1191 | ||
1192 | For any two classes, it is very desirable that there be another | |
1193 | class that represents their union. */ | |
c81bebd7 | 1194 | |
cacf1ca8 | 1195 | /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
462f7901 | 1196 | condition registers, plus three special registers, CTR, and the link |
cacf1ca8 MM |
1197 | register. AltiVec adds a vector register class. VSX registers overlap the |
1198 | FPR registers and the Altivec registers. | |
f045b2c9 RS |
1199 | |
1200 | However, r0 is special in that it cannot be used as a base register. | |
1201 | So make a class for registers valid as base registers. | |
1202 | ||
1203 | Also, cr0 is the only condition code register that can be used in | |
0d86f538 | 1204 | arithmetic insns, so make a separate class for it. */ |
f045b2c9 | 1205 | |
ebedb4dd MM |
1206 | enum reg_class |
1207 | { | |
1208 | NO_REGS, | |
ebedb4dd MM |
1209 | BASE_REGS, |
1210 | GENERAL_REGS, | |
1211 | FLOAT_REGS, | |
0ac081f6 | 1212 | ALTIVEC_REGS, |
8beb65e3 | 1213 | VSX_REGS, |
0ac081f6 | 1214 | VRSAVE_REGS, |
5f004351 | 1215 | VSCR_REGS, |
a3170dc6 AH |
1216 | SPE_ACC_REGS, |
1217 | SPEFSCR_REGS, | |
ebedb4dd | 1218 | NON_SPECIAL_REGS, |
ebedb4dd MM |
1219 | LINK_REGS, |
1220 | CTR_REGS, | |
1221 | LINK_OR_CTR_REGS, | |
1222 | SPECIAL_REGS, | |
1223 | SPEC_OR_GEN_REGS, | |
1224 | CR0_REGS, | |
ebedb4dd MM |
1225 | CR_REGS, |
1226 | NON_FLOAT_REGS, | |
f6b5d695 | 1227 | CA_REGS, |
ebedb4dd MM |
1228 | ALL_REGS, |
1229 | LIM_REG_CLASSES | |
1230 | }; | |
f045b2c9 RS |
1231 | |
1232 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1233 | ||
82e41834 | 1234 | /* Give names of register classes as strings for dump file. */ |
f045b2c9 | 1235 | |
ebedb4dd MM |
1236 | #define REG_CLASS_NAMES \ |
1237 | { \ | |
1238 | "NO_REGS", \ | |
ebedb4dd MM |
1239 | "BASE_REGS", \ |
1240 | "GENERAL_REGS", \ | |
1241 | "FLOAT_REGS", \ | |
0ac081f6 | 1242 | "ALTIVEC_REGS", \ |
8beb65e3 | 1243 | "VSX_REGS", \ |
0ac081f6 | 1244 | "VRSAVE_REGS", \ |
5f004351 | 1245 | "VSCR_REGS", \ |
a3170dc6 AH |
1246 | "SPE_ACC_REGS", \ |
1247 | "SPEFSCR_REGS", \ | |
ebedb4dd | 1248 | "NON_SPECIAL_REGS", \ |
ebedb4dd MM |
1249 | "LINK_REGS", \ |
1250 | "CTR_REGS", \ | |
1251 | "LINK_OR_CTR_REGS", \ | |
1252 | "SPECIAL_REGS", \ | |
1253 | "SPEC_OR_GEN_REGS", \ | |
1254 | "CR0_REGS", \ | |
ebedb4dd MM |
1255 | "CR_REGS", \ |
1256 | "NON_FLOAT_REGS", \ | |
f6b5d695 | 1257 | "CA_REGS", \ |
ebedb4dd MM |
1258 | "ALL_REGS" \ |
1259 | } | |
f045b2c9 RS |
1260 | |
1261 | /* Define which registers fit in which classes. | |
1262 | This is an initializer for a vector of HARD_REG_SET | |
1263 | of length N_REG_CLASSES. */ | |
1264 | ||
0ac081f6 AH |
1265 | #define REG_CLASS_CONTENTS \ |
1266 | { \ | |
1267 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
7d5175e1 JJ |
1268 | { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ |
1269 | { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ | |
0ac081f6 | 1270 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ |
089a05b8 | 1271 | { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ |
8beb65e3 | 1272 | { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \ |
089a05b8 | 1273 | { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ |
5f004351 | 1274 | { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ |
a3170dc6 AH |
1275 | { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ |
1276 | { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ | |
7d5175e1 | 1277 | { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ |
0ac081f6 AH |
1278 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ |
1279 | { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ | |
1280 | { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ | |
462f7901 SB |
1281 | { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \ |
1282 | { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ | |
0ac081f6 AH |
1283 | { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ |
1284 | { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ | |
462f7901 | 1285 | { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ |
f6b5d695 | 1286 | { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ |
462f7901 | 1287 | { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0003ffff } /* ALL_REGS */ \ |
ebedb4dd | 1288 | } |
f045b2c9 RS |
1289 | |
1290 | /* The same information, inverted: | |
1291 | Return the class number of the smallest class containing | |
1292 | reg number REGNO. This could be a conditional expression | |
1293 | or could index an array. */ | |
1294 | ||
cacf1ca8 MM |
1295 | extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
1296 | ||
1297 | #if ENABLE_CHECKING | |
1298 | #define REGNO_REG_CLASS(REGNO) \ | |
1299 | (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \ | |
1300 | rs6000_regno_regclass[(REGNO)]) | |
1301 | ||
1302 | #else | |
1303 | #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)] | |
1304 | #endif | |
1305 | ||
a72c65c7 MM |
1306 | /* Register classes for various constraints that are based on the target |
1307 | switches. */ | |
1308 | enum r6000_reg_class_enum { | |
1309 | RS6000_CONSTRAINT_d, /* fpr registers for double values */ | |
1310 | RS6000_CONSTRAINT_f, /* fpr registers for single values */ | |
1311 | RS6000_CONSTRAINT_v, /* Altivec registers */ | |
1312 | RS6000_CONSTRAINT_wa, /* Any VSX register */ | |
1313 | RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ | |
1314 | RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ | |
1315 | RS6000_CONSTRAINT_ws, /* VSX register for DF */ | |
1316 | RS6000_CONSTRAINT_MAX | |
1317 | }; | |
1318 | ||
1319 | extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; | |
f045b2c9 RS |
1320 | |
1321 | /* The class value for index registers, and the one for base regs. */ | |
1322 | #define INDEX_REG_CLASS GENERAL_REGS | |
1323 | #define BASE_REG_CLASS BASE_REGS | |
1324 | ||
cacf1ca8 MM |
1325 | /* Return whether a given register class can hold VSX objects. */ |
1326 | #define VSX_REG_CLASS_P(CLASS) \ | |
1327 | ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) | |
1328 | ||
f045b2c9 RS |
1329 | /* Given an rtx X being reloaded into a reg required to be |
1330 | in class CLASS, return the class of reg to actually use. | |
1331 | In general this is just CLASS; but on some machines | |
c81bebd7 | 1332 | in some cases it is preferable to use a more restrictive class. |
f045b2c9 RS |
1333 | |
1334 | On the RS/6000, we have to return NO_REGS when we want to reload a | |
f676971a | 1335 | floating-point CONST_DOUBLE to force it to be copied to memory. |
1e66d555 GK |
1336 | |
1337 | We also don't want to reload integer values into floating-point | |
1338 | registers if we can at all help it. In fact, this can | |
37409796 | 1339 | cause reload to die, if it tries to generate a reload of CTR |
1e66d555 GK |
1340 | into a FP register and discovers it doesn't have the memory location |
1341 | required. | |
1342 | ||
1343 | ??? Would it be a good idea to have reload do the converse, that is | |
1344 | try to reload floating modes into FP registers if possible? | |
1345 | */ | |
f045b2c9 | 1346 | |
802a0058 | 1347 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
8beb65e3 | 1348 | rs6000_preferred_reload_class_ptr (X, CLASS) |
c81bebd7 | 1349 | |
f045b2c9 RS |
1350 | /* Return the register class of a scratch register needed to copy IN into |
1351 | or out of a register in CLASS in MODE. If it can be done directly, | |
1352 | NO_REGS is returned. */ | |
1353 | ||
1354 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
8beb65e3 | 1355 | rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
f045b2c9 | 1356 | |
0ac081f6 | 1357 | /* If we are copying between FP or AltiVec registers and anything |
44cd321e PS |
1358 | else, we need a memory location. The exception is when we are |
1359 | targeting ppc64 and the move to/from fpr to gpr instructions | |
1360 | are available.*/ | |
1361 | ||
1362 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ | |
8beb65e3 | 1363 | rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE) |
7ea555a4 | 1364 | |
e41b2a33 PB |
1365 | /* For cpus that cannot load/store SDmode values from the 64-bit |
1366 | FP registers without using a full 64-bit load/store, we need | |
1367 | to allocate a full 64-bit stack slot for them. */ | |
1368 | ||
1369 | #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ | |
1370 | rs6000_secondary_memory_needed_rtx (MODE) | |
1371 | ||
f045b2c9 RS |
1372 | /* Return the maximum number of consecutive registers |
1373 | needed to represent mode MODE in a register of class CLASS. | |
1374 | ||
cacf1ca8 MM |
1375 | On RS/6000, this is the size of MODE in words, except in the FP regs, where |
1376 | a single reg is enough for two words, unless we have VSX, where the FP | |
1377 | registers can hold 128 bits. */ | |
1378 | #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] | |
580d3230 | 1379 | |
ca0e79d9 AM |
1380 | /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ |
1381 | ||
1382 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
8beb65e3 | 1383 | rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS) |
02188693 | 1384 | |
f045b2c9 RS |
1385 | /* Stack layout; function entry, exit and calling. */ |
1386 | ||
1387 | /* Define this if pushing a word on the stack | |
1388 | makes the stack pointer a smaller address. */ | |
1389 | #define STACK_GROWS_DOWNWARD | |
1390 | ||
327e5343 FJ |
1391 | /* Offsets recorded in opcodes are a multiple of this alignment factor. */ |
1392 | #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
1393 | ||
a4d05547 | 1394 | /* Define this to nonzero if the nominal address of the stack frame |
f045b2c9 RS |
1395 | is at the high-address end of the local variables; |
1396 | that is, each additional local variable allocated | |
1397 | goes at a more negative offset in the frame. | |
1398 | ||
1399 | On the RS/6000, we grow upwards, from the area after the outgoing | |
1400 | arguments. */ | |
3aebbe5f | 1401 | #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0) |
f045b2c9 | 1402 | |
4697a36c | 1403 | /* Size of the outgoing register save area */ |
9ebbca7d | 1404 | #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ |
ee890fe2 | 1405 | || DEFAULT_ABI == ABI_DARWIN) \ |
9ebbca7d GK |
1406 | ? (TARGET_64BIT ? 64 : 32) \ |
1407 | : 0) | |
4697a36c MM |
1408 | |
1409 | /* Size of the fixed area on the stack */ | |
9ebbca7d | 1410 | #define RS6000_SAVE_AREA \ |
50d440bc | 1411 | (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ |
9ebbca7d | 1412 | << (TARGET_64BIT ? 1 : 0)) |
4697a36c | 1413 | |
97f6e72f DE |
1414 | /* MEM representing address to save the TOC register */ |
1415 | #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ | |
0a81f074 | 1416 | plus_constant (Pmode, stack_pointer_rtx, \ |
97f6e72f | 1417 | (TARGET_32BIT ? 20 : 40))) |
b6c9286a | 1418 | |
4697a36c | 1419 | /* Align an address */ |
ed33106f | 1420 | #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) |
4697a36c | 1421 | |
f045b2c9 RS |
1422 | /* Offset within stack frame to start allocating local variables at. |
1423 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1424 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
c81bebd7 | 1425 | of the first local allocated. |
f045b2c9 RS |
1426 | |
1427 | On the RS/6000, the frame pointer is the same as the stack pointer, | |
1428 | except for dynamic allocations. So we start after the fixed area and | |
1429 | outgoing parameter area. */ | |
1430 | ||
802a0058 | 1431 | #define STARTING_FRAME_OFFSET \ |
7d5175e1 JJ |
1432 | (FRAME_GROWS_DOWNWARD \ |
1433 | ? 0 \ | |
cacf1ca8 MM |
1434 | : (RS6000_ALIGN (crtl->outgoing_args_size, \ |
1435 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ | |
7d5175e1 | 1436 | + RS6000_SAVE_AREA)) |
802a0058 MM |
1437 | |
1438 | /* Offset from the stack pointer register to an item dynamically | |
1439 | allocated on the stack, e.g., by `alloca'. | |
1440 | ||
1441 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1442 | length of the outgoing arguments. The default is correct for most | |
1443 | machines. See `function.c' for details. */ | |
1444 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ | |
cacf1ca8 MM |
1445 | (RS6000_ALIGN (crtl->outgoing_args_size, \ |
1446 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ | |
802a0058 | 1447 | + (STACK_POINTER_OFFSET)) |
f045b2c9 RS |
1448 | |
1449 | /* If we generate an insn to push BYTES bytes, | |
1450 | this says how many the stack pointer really advances by. | |
1451 | On RS/6000, don't define this because there are no push insns. */ | |
1452 | /* #define PUSH_ROUNDING(BYTES) */ | |
1453 | ||
1454 | /* Offset of first parameter from the argument pointer register value. | |
1455 | On the RS/6000, we define the argument pointer to the start of the fixed | |
1456 | area. */ | |
4697a36c | 1457 | #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA |
f045b2c9 | 1458 | |
62153b61 JM |
1459 | /* Offset from the argument pointer register value to the top of |
1460 | stack. This is different from FIRST_PARM_OFFSET because of the | |
1461 | register save area. */ | |
1462 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1463 | ||
f045b2c9 RS |
1464 | /* Define this if stack space is still allocated for a parameter passed |
1465 | in a register. The value is the number of bytes allocated to this | |
1466 | area. */ | |
4697a36c | 1467 | #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE |
f045b2c9 RS |
1468 | |
1469 | /* Define this if the above stack space is to be considered part of the | |
1470 | space allocated by the caller. */ | |
81464b2c | 1471 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
f045b2c9 RS |
1472 | |
1473 | /* This is the difference between the logical top of stack and the actual sp. | |
1474 | ||
82e41834 | 1475 | For the RS/6000, sp points past the fixed area. */ |
4697a36c | 1476 | #define STACK_POINTER_OFFSET RS6000_SAVE_AREA |
f045b2c9 RS |
1477 | |
1478 | /* Define this if the maximum size of all the outgoing args is to be | |
1479 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1480 | found in the variable crtl->outgoing_args_size. */ |
f73ad30e | 1481 | #define ACCUMULATE_OUTGOING_ARGS 1 |
f045b2c9 | 1482 | |
f045b2c9 RS |
1483 | /* Define how to find the value returned by a library function |
1484 | assuming the value has mode MODE. */ | |
1485 | ||
ded9bf77 | 1486 | #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) |
f045b2c9 | 1487 | |
6fa3f289 ZW |
1488 | /* DRAFT_V4_STRUCT_RET defaults off. */ |
1489 | #define DRAFT_V4_STRUCT_RET 0 | |
f607bc57 | 1490 | |
bd5bd7ac | 1491 | /* Let TARGET_RETURN_IN_MEMORY control what happens. */ |
f607bc57 | 1492 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
f045b2c9 | 1493 | |
a260abc9 | 1494 | /* Mode of stack savearea. |
dfdfa60f DE |
1495 | FUNCTION is VOIDmode because calling convention maintains SP. |
1496 | BLOCK needs Pmode for SP. | |
a260abc9 DE |
1497 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ |
1498 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
dfdfa60f DE |
1499 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ |
1500 | : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) | |
a260abc9 | 1501 | |
4697a36c MM |
1502 | /* Minimum and maximum general purpose registers used to hold arguments. */ |
1503 | #define GP_ARG_MIN_REG 3 | |
1504 | #define GP_ARG_MAX_REG 10 | |
1505 | #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1506 | ||
1507 | /* Minimum and maximum floating point registers used to hold arguments. */ | |
1508 | #define FP_ARG_MIN_REG 33 | |
7509c759 MM |
1509 | #define FP_ARG_AIX_MAX_REG 45 |
1510 | #define FP_ARG_V4_MAX_REG 40 | |
9ebbca7d | 1511 | #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ |
ee890fe2 | 1512 | || DEFAULT_ABI == ABI_DARWIN) \ |
9ebbca7d | 1513 | ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) |
4697a36c MM |
1514 | #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
1515 | ||
0ac081f6 AH |
1516 | /* Minimum and maximum AltiVec registers used to hold arguments. */ |
1517 | #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
1518 | #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
1519 | #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
1520 | ||
4697a36c MM |
1521 | /* Return registers */ |
1522 | #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1523 | #define FP_ARG_RETURN FP_ARG_MIN_REG | |
0ac081f6 | 1524 | #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) |
4697a36c | 1525 | |
7509c759 | 1526 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
6a4cee5f | 1527 | #define CALL_NORMAL 0x00000000 /* no special processing */ |
9ebbca7d | 1528 | /* Bits in 0x00000001 are unused. */ |
6a4cee5f MM |
1529 | #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ |
1530 | #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1531 | #define CALL_LONG 0x00000008 /* always call indirect */ | |
b9599e46 | 1532 | #define CALL_LIBCALL 0x00000010 /* libcall */ |
7509c759 | 1533 | |
f57fe068 AM |
1534 | /* We don't have prologue and epilogue functions to save/restore |
1535 | everything for most ABIs. */ | |
1536 | #define WORLD_SAVE_P(INFO) 0 | |
1537 | ||
f045b2c9 RS |
1538 | /* 1 if N is a possible register number for a function value |
1539 | as seen by the caller. | |
1540 | ||
0ac081f6 | 1541 | On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ |
e87a88d3 AM |
1542 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1543 | ((N) == GP_ARG_RETURN \ | |
b2df7d08 | 1544 | || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \ |
44688022 | 1545 | || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) |
f045b2c9 RS |
1546 | |
1547 | /* 1 if N is a possible register number for function argument passing. | |
0ac081f6 AH |
1548 | On RS/6000, these are r3-r10 and fp1-fp13. |
1549 | On AltiVec, v2 - v13 are used for passing vectors. */ | |
4697a36c | 1550 | #define FUNCTION_ARG_REGNO_P(N) \ |
e87a88d3 AM |
1551 | ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ |
1552 | || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ | |
44688022 | 1553 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
e87a88d3 | 1554 | || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ |
b2df7d08 | 1555 | && TARGET_HARD_FLOAT && TARGET_FPRS)) |
f045b2c9 RS |
1556 | \f |
1557 | /* Define a data type for recording info about an argument list | |
1558 | during the scan of that argument list. This data type should | |
1559 | hold all necessary information about the function itself | |
1560 | and about the args processed so far, enough to enable macros | |
1561 | such as FUNCTION_ARG to determine where the next arg should go. | |
1562 | ||
1563 | On the RS/6000, this is a structure. The first element is the number of | |
1564 | total argument words, the second is used to store the next | |
1565 | floating-point register number, and the third says how many more args we | |
4697a36c MM |
1566 | have prototype types for. |
1567 | ||
4cc833b7 | 1568 | For ABI_V4, we treat these slightly differently -- `sysv_gregno' is |
07488f32 | 1569 | the next available GP register, `fregno' is the next available FP |
4cc833b7 RH |
1570 | register, and `words' is the number of words used on the stack. |
1571 | ||
bd227acc | 1572 | The varargs/stdarg support requires that this structure's size |
4cc833b7 | 1573 | be a multiple of sizeof(int). */ |
4697a36c MM |
1574 | |
1575 | typedef struct rs6000_args | |
1576 | { | |
4cc833b7 | 1577 | int words; /* # words used for passing GP registers */ |
6a4cee5f | 1578 | int fregno; /* next available FP register */ |
0ac081f6 | 1579 | int vregno; /* next available AltiVec register */ |
6a4cee5f | 1580 | int nargs_prototype; /* # args left in the current prototype */ |
6a4cee5f | 1581 | int prototype; /* Whether a prototype was defined */ |
a6c9bed4 | 1582 | int stdarg; /* Whether function is a stdarg function. */ |
6a4cee5f | 1583 | int call_cookie; /* Do special things for this call */ |
4cc833b7 | 1584 | int sysv_gregno; /* next available GP register */ |
0b5383eb DJ |
1585 | int intoffset; /* running offset in struct (darwin64) */ |
1586 | int use_stack; /* any part of struct on stack (darwin64) */ | |
a9ab25e2 IS |
1587 | int floats_in_gpr; /* count of SFmode floats taking up |
1588 | GPR space (darwin64) */ | |
0b5383eb | 1589 | int named; /* false for varargs params */ |
617718f7 | 1590 | int escapes; /* if function visible outside tu */ |
4697a36c | 1591 | } CUMULATIVE_ARGS; |
f045b2c9 | 1592 | |
f045b2c9 RS |
1593 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1594 | for a call to a function whose data type is FNTYPE. | |
1595 | For a library call, FNTYPE is 0. */ | |
1596 | ||
617718f7 AM |
1597 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
1598 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ | |
1599 | N_NAMED_ARGS, FNDECL, VOIDmode) | |
f045b2c9 RS |
1600 | |
1601 | /* Similar, but when scanning the definition of a procedure. We always | |
1602 | set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1603 | ||
0f6937fe | 1604 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ |
617718f7 AM |
1605 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
1606 | 1000, current_function_decl, VOIDmode) | |
b9599e46 FS |
1607 | |
1608 | /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
1609 | ||
1610 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
617718f7 AM |
1611 | init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
1612 | 0, NULL_TREE, MODE) | |
f045b2c9 | 1613 | |
c229cba9 DE |
1614 | /* If defined, a C expression which determines whether, and in which |
1615 | direction, to pad out an argument with extra space. The value | |
1616 | should be of type `enum direction': either `upward' to pad above | |
1617 | the argument, `downward' to pad below, or `none' to inhibit | |
1618 | padding. */ | |
1619 | ||
9ebbca7d | 1620 | #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) |
c229cba9 | 1621 | |
6e985040 AM |
1622 | #define PAD_VARARGS_DOWN \ |
1623 | (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) | |
2a55fd42 | 1624 | |
f045b2c9 | 1625 | /* Output assembler code to FILE to increment profiler label # LABELNO |
58a39e45 | 1626 | for profiling a function entry. */ |
f045b2c9 RS |
1627 | |
1628 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
58a39e45 | 1629 | output_function_profiler ((FILE), (LABELNO)); |
f045b2c9 RS |
1630 | |
1631 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1632 | the stack pointer does not matter. No definition is equivalent to | |
1633 | always zero. | |
1634 | ||
a0ab749a | 1635 | On the RS/6000, this is nonzero because we can restore the stack from |
f045b2c9 RS |
1636 | its backpointer, which we maintain. */ |
1637 | #define EXIT_IGNORE_STACK 1 | |
1638 | ||
a701949a FS |
1639 | /* Define this macro as a C expression that is nonzero for registers |
1640 | that are used by the epilogue or the return' pattern. The stack | |
1641 | and frame pointer registers are already be assumed to be used as | |
1642 | needed. */ | |
1643 | ||
83720594 | 1644 | #define EPILOGUE_USES(REGNO) \ |
1de43f85 | 1645 | ((reload_completed && (REGNO) == LR_REGNO) \ |
b1765bde | 1646 | || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ |
cacf1ca8 | 1647 | || (crtl->calls_eh_return \ |
3553b09d | 1648 | && TARGET_AIX \ |
ff3867ae | 1649 | && (REGNO) == 2)) |
2bfcf297 | 1650 | |
f045b2c9 | 1651 | \f |
f045b2c9 RS |
1652 | /* Length in units of the trampoline for entering a nested function. */ |
1653 | ||
b6c9286a | 1654 | #define TRAMPOLINE_SIZE rs6000_trampoline_size () |
f045b2c9 | 1655 | \f |
f33985c6 MS |
1656 | /* Definitions for __builtin_return_address and __builtin_frame_address. |
1657 | __builtin_return_address (0) should give link register (65), enable | |
82e41834 | 1658 | this. */ |
f33985c6 MS |
1659 | /* This should be uncommented, so that the link register is used, but |
1660 | currently this would result in unmatched insns and spilling fixed | |
1661 | registers so we'll leave it for another day. When these problems are | |
1662 | taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1663 | (mrs) */ | |
1664 | /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
f09d4c33 | 1665 | |
b6c9286a MM |
1666 | /* Number of bytes into the frame return addresses can be found. See |
1667 | rs6000_stack_info in rs6000.c for more information on how the different | |
1668 | abi's store the return address. */ | |
1669 | #define RETURN_ADDRESS_OFFSET \ | |
1670 | ((DEFAULT_ABI == ABI_AIX \ | |
50d440bc | 1671 | || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \ |
3b370352 | 1672 | (DEFAULT_ABI == ABI_V4) ? 4 : \ |
c4636dd1 | 1673 | (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) |
f09d4c33 | 1674 | |
f33985c6 MS |
1675 | /* The current return address is in link register (65). The return address |
1676 | of anything farther back is accessed normally at an offset of 8 from the | |
1677 | frame pointer. */ | |
71f123ca FS |
1678 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1679 | (rs6000_return_addr (COUNT, FRAME)) | |
1680 | ||
f33985c6 | 1681 | \f |
f045b2c9 RS |
1682 | /* Definitions for register eliminations. |
1683 | ||
1684 | We have two registers that can be eliminated on the RS/6000. First, the | |
1685 | frame pointer register can often be eliminated in favor of the stack | |
1686 | pointer register. Secondly, the argument pointer register can always be | |
642a35f1 JW |
1687 | eliminated; it is replaced with either the stack or frame pointer. |
1688 | ||
1689 | In addition, we use the elimination mechanism to see if r30 is needed | |
1690 | Initially we assume that it isn't. If it is, we spill it. This is done | |
1691 | by making it an eliminable register. We replace it with itself so that | |
1692 | if it isn't needed, then existing uses won't be modified. */ | |
f045b2c9 RS |
1693 | |
1694 | /* This is an array of structures. Each structure initializes one pair | |
1695 | of eliminable registers. The "from" register number is given first, | |
1696 | followed by "to". Eliminations of the same "from" register are listed | |
1697 | in order of preference. */ | |
7d5175e1 JJ |
1698 | #define ELIMINABLE_REGS \ |
1699 | {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1700 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1701 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1702 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1703 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
97b23853 | 1704 | { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } |
f045b2c9 | 1705 | |
f045b2c9 RS |
1706 | /* Define the offset between two registers, one to be eliminated, and the other |
1707 | its replacement, at the start of a routine. */ | |
d1d0c603 JJ |
1708 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1709 | ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
f045b2c9 RS |
1710 | \f |
1711 | /* Addressing modes, and classification of registers for them. */ | |
1712 | ||
940da324 JL |
1713 | #define HAVE_PRE_DECREMENT 1 |
1714 | #define HAVE_PRE_INCREMENT 1 | |
6fb5fa3c DB |
1715 | #define HAVE_PRE_MODIFY_DISP 1 |
1716 | #define HAVE_PRE_MODIFY_REG 1 | |
f045b2c9 RS |
1717 | |
1718 | /* Macros to check register numbers against specific register classes. */ | |
1719 | ||
1720 | /* These assume that REGNO is a hard or pseudo reg number. | |
1721 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1722 | or a pseudo reg currently allocated to a suitable hard reg. | |
1723 | Since they use reg_renumber, they are safe only once reg_renumber | |
1724 | has been allocated, which happens in local-alloc.c. */ | |
1725 | ||
1726 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1727 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1728 | ? (REGNO) <= 31 || (REGNO) == 67 \ | |
7d5175e1 | 1729 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1730 | : (reg_renumber[REGNO] >= 0 \ |
7d5175e1 JJ |
1731 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1732 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
f045b2c9 RS |
1733 | |
1734 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1735 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1736 | ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
7d5175e1 | 1737 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1738 | : (reg_renumber[REGNO] > 0 \ |
7d5175e1 JJ |
1739 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1740 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
c6c3dba9 PB |
1741 | |
1742 | /* Nonzero if X is a hard reg that can be used as an index | |
1743 | or if it is a pseudo reg in the non-strict case. */ | |
1744 | #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ | |
1745 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
1746 | || REGNO_OK_FOR_INDEX_P (REGNO (X))) | |
1747 | ||
1748 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1749 | or if it is a pseudo reg in the non-strict case. */ | |
1750 | #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ | |
1751 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
1752 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
1753 | ||
f045b2c9 RS |
1754 | \f |
1755 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1756 | ||
1757 | #define MAX_REGS_PER_ADDRESS 2 | |
1758 | ||
1759 | /* Recognize any constant value that is a valid address. */ | |
1760 | ||
6eff269e BK |
1761 | #define CONSTANT_ADDRESS_P(X) \ |
1762 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1763 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1764 | || GET_CODE (X) == HIGH) | |
f045b2c9 | 1765 | |
48d72335 | 1766 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
66180ff3 | 1767 | #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ |
76492753 PB |
1768 | && EASY_VECTOR_15((n) >> 1) \ |
1769 | && ((n) & 1) == 0) | |
48d72335 | 1770 | |
29e6733c MM |
1771 | #define EASY_VECTOR_MSB(n,mode) \ |
1772 | (((unsigned HOST_WIDE_INT)n) == \ | |
1773 | ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) | |
1774 | ||
f045b2c9 | 1775 | \f |
a260abc9 DE |
1776 | /* Try a machine-dependent way of reloading an illegitimate address |
1777 | operand. If we find one, push the reload and jump to WIN. This | |
1778 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1779 | ||
f676971a | 1780 | Implemented on rs6000 by rs6000_legitimize_reload_address. |
24ea750e | 1781 | Note that (X) is evaluated twice; this is safe in current usage. */ |
f676971a | 1782 | |
a9098fd0 GK |
1783 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
1784 | do { \ | |
24ea750e | 1785 | int win; \ |
8beb65e3 | 1786 | (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ |
24ea750e DJ |
1787 | (int)(TYPE), (IND_LEVELS), &win); \ |
1788 | if ( win ) \ | |
1789 | goto WIN; \ | |
a260abc9 DE |
1790 | } while (0) |
1791 | ||
944258eb | 1792 | #define FIND_BASE_TERM rs6000_find_base_term |
766a866c MM |
1793 | \f |
1794 | /* The register number of the register used to address a table of | |
1795 | static data addresses in memory. In some cases this register is | |
1796 | defined by a processor's "application binary interface" (ABI). | |
1797 | When this macro is defined, RTL is generated for this register | |
1798 | once, as with the stack pointer and frame pointer registers. If | |
1799 | this macro is not defined, it is up to the machine-dependent files | |
1800 | to allocate such a register (if necessary). */ | |
1801 | ||
1db02437 FS |
1802 | #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 |
1803 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) | |
766a866c | 1804 | |
97b23853 | 1805 | #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) |
9ebbca7d | 1806 | |
766a866c MM |
1807 | /* Define this macro if the register defined by |
1808 | `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
089a05b8 | 1809 | this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ |
766a866c MM |
1810 | |
1811 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
1812 | ||
766a866c MM |
1813 | /* A C expression that is nonzero if X is a legitimate immediate |
1814 | operand on the target machine when generating position independent | |
1815 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
1816 | not check this. You can also assume FLAG_PIC is true, so you need | |
1817 | not check it either. You need not define this macro if all | |
1818 | constants (including `SYMBOL_REF') can be immediate operands when | |
1819 | generating position independent code. */ | |
1820 | ||
1821 | /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
f045b2c9 RS |
1822 | \f |
1823 | /* Define this if some processing needs to be done immediately before | |
4255474b | 1824 | emitting code for an insn. */ |
f045b2c9 | 1825 | |
c921bad8 AP |
1826 | #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \ |
1827 | rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS) | |
f045b2c9 RS |
1828 | |
1829 | /* Specify the machine mode that this machine uses | |
1830 | for the index in the tablejump instruction. */ | |
e1565e65 | 1831 | #define CASE_VECTOR_MODE SImode |
f045b2c9 | 1832 | |
18543a22 ILT |
1833 | /* Define as C expression which evaluates to nonzero if the tablejump |
1834 | instruction expects the table to contain offsets from the address of the | |
1835 | table. | |
82e41834 | 1836 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 1837 | #define CASE_VECTOR_PC_RELATIVE 1 |
f045b2c9 | 1838 | |
f045b2c9 RS |
1839 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1840 | #define DEFAULT_SIGNED_CHAR 0 | |
1841 | ||
c1618c0c DE |
1842 | /* An integer expression for the size in bits of the largest integer machine |
1843 | mode that should actually be used. */ | |
1844 | ||
1845 | /* Allow pairs of registers to be used, which is the intent of the default. */ | |
1846 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
1847 | ||
f045b2c9 RS |
1848 | /* Max number of bytes we can move from memory to memory |
1849 | in one reasonably fast instruction. */ | |
2f3e5814 | 1850 | #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) |
7e69e155 | 1851 | #define MAX_MOVE_MAX 8 |
f045b2c9 RS |
1852 | |
1853 | /* Nonzero if access to memory by bytes is no faster than for words. | |
a0ab749a | 1854 | Also nonzero if doing byte operations (specifically shifts) in registers |
f045b2c9 RS |
1855 | is undesirable. */ |
1856 | #define SLOW_BYTE_ACCESS 1 | |
1857 | ||
9a63901f RK |
1858 | /* Define if operations between registers always perform the operation |
1859 | on the full register even if a narrower mode is specified. */ | |
1860 | #define WORD_REGISTER_OPERATIONS | |
1861 | ||
1862 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1863 | will either zero-extend or sign-extend. The value of this macro should | |
1864 | be the code that says which one of the two operations is implicitly | |
f822d252 | 1865 | done, UNKNOWN if none. */ |
9a63901f | 1866 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
225211e2 RK |
1867 | |
1868 | /* Define if loading short immediate values into registers sign extends. */ | |
1869 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
fdaff8ba | 1870 | \f |
f045b2c9 RS |
1871 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1872 | is done just by pretending it is already truncated. */ | |
1873 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1874 | ||
94993909 | 1875 | /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ |
d865b122 | 1876 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
14670a74 | 1877 | ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) |
d865b122 | 1878 | |
94993909 | 1879 | /* The CTZ patterns return -1 for input of zero. */ |
14670a74 | 1880 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) |
94993909 | 1881 | |
f045b2c9 RS |
1882 | /* Specify the machine mode that pointers have. |
1883 | After generation of rtl, the compiler makes no further distinction | |
1884 | between pointers and any other objects of this machine mode. */ | |
cacf1ca8 MM |
1885 | extern unsigned rs6000_pmode; |
1886 | #define Pmode ((enum machine_mode)rs6000_pmode) | |
f045b2c9 | 1887 | |
a3c9585f | 1888 | /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ |
4c81e946 FJ |
1889 | #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) |
1890 | ||
f045b2c9 | 1891 | /* Mode of a function address in a call instruction (for indexing purposes). |
f045b2c9 | 1892 | Doesn't matter on RS/6000. */ |
5b71a4e7 | 1893 | #define FUNCTION_MODE SImode |
f045b2c9 RS |
1894 | |
1895 | /* Define this if addresses of constant functions | |
1896 | shouldn't be put through pseudo regs where they can be cse'd. | |
1897 | Desirable on machines where ordinary constants are expensive | |
1898 | but a CALL with constant address is cheap. */ | |
1899 | #define NO_FUNCTION_CSE | |
1900 | ||
d969caf8 | 1901 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
6febd581 RK |
1902 | few bits. |
1903 | ||
1904 | The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
1905 | have been dropped from the PowerPC architecture. */ | |
c28a7c24 | 1906 | #define SHIFT_COUNT_TRUNCATED 0 |
f045b2c9 | 1907 | |
f045b2c9 RS |
1908 | /* Adjust the length of an INSN. LENGTH is the currently-computed length and |
1909 | should be adjusted to reflect any required changes. This macro is used when | |
1910 | there is some systematic length adjustment required that would be difficult | |
1911 | to express in the length attribute. */ | |
1912 | ||
1913 | /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
1914 | ||
39a10a29 GK |
1915 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a |
1916 | COMPARE, return the mode to be used for the comparison. For | |
1917 | floating-point, CCFPmode should be used. CCUNSmode should be used | |
1918 | for unsigned comparisons. CCEQmode should be used when we are | |
1919 | doing an inequality comparison on the result of a | |
1920 | comparison. CCmode should be used in all other cases. */ | |
c5defebb | 1921 | |
b565a316 | 1922 | #define SELECT_CC_MODE(OP,X,Y) \ |
ebb109ad | 1923 | (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ |
c5defebb | 1924 | : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ |
ec8e098d | 1925 | : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ |
c5defebb | 1926 | ? CCEQmode : CCmode)) |
f045b2c9 | 1927 | |
b39358e1 GK |
1928 | /* Can the condition code MODE be safely reversed? This is safe in |
1929 | all cases on this port, because at present it doesn't use the | |
1930 | trapping FP comparisons (fcmpo). */ | |
1931 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
1932 | ||
1933 | /* Given a condition code and a mode, return the inverse condition. */ | |
1934 | #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
1935 | ||
f045b2c9 RS |
1936 | \f |
1937 | /* Control the assembler format that we output. */ | |
1938 | ||
1b279f39 DE |
1939 | /* A C string constant describing how to begin a comment in the target |
1940 | assembler language. The compiler assumes that the comment will end at | |
1941 | the end of the line. */ | |
1942 | #define ASM_COMMENT_START " #" | |
6b67933e | 1943 | |
38c1f2d7 MM |
1944 | /* Flag to say the TOC is initialized */ |
1945 | extern int toc_initialized; | |
1946 | ||
f045b2c9 RS |
1947 | /* Macro to output a special constant pool entry. Go to WIN if we output |
1948 | it. Otherwise, it is written the usual way. | |
1949 | ||
1950 | On the RS/6000, toc entries are handled this way. */ | |
1951 | ||
a9098fd0 GK |
1952 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ |
1953 | { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
1954 | { \ | |
1955 | output_toc (FILE, X, LABELNO, MODE); \ | |
1956 | goto WIN; \ | |
1957 | } \ | |
f045b2c9 RS |
1958 | } |
1959 | ||
ebd97b96 DE |
1960 | #ifdef HAVE_GAS_WEAK |
1961 | #define RS6000_WEAK 1 | |
1962 | #else | |
1963 | #define RS6000_WEAK 0 | |
1964 | #endif | |
290ad355 | 1965 | |
79c4e63f AM |
1966 | #if RS6000_WEAK |
1967 | /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
1968 | #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ | |
1969 | do \ | |
1970 | { \ | |
1971 | fputs ("\t.weak\t", (FILE)); \ | |
85b776df | 1972 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f | 1973 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ |
85b776df | 1974 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f | 1975 | { \ |
cbaaba19 DE |
1976 | if (TARGET_XCOFF) \ |
1977 | fputs ("[DS]", (FILE)); \ | |
ca734b39 | 1978 | fputs ("\n\t.weak\t.", (FILE)); \ |
cbaaba19 | 1979 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f AM |
1980 | } \ |
1981 | fputc ('\n', (FILE)); \ | |
1982 | if (VAL) \ | |
1983 | { \ | |
1984 | ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ | |
1985 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
85b776df | 1986 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f AM |
1987 | { \ |
1988 | fputs ("\t.set\t.", (FILE)); \ | |
cbaaba19 | 1989 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f | 1990 | fputs (",.", (FILE)); \ |
cbaaba19 | 1991 | RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ |
79c4e63f AM |
1992 | fputc ('\n', (FILE)); \ |
1993 | } \ | |
1994 | } \ | |
1995 | } \ | |
1996 | while (0) | |
1997 | #endif | |
1998 | ||
ff2d10c1 AO |
1999 | #if HAVE_GAS_WEAKREF |
2000 | #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
2001 | do \ | |
2002 | { \ | |
2003 | fputs ("\t.weakref\t", (FILE)); \ | |
2004 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2005 | fputs (", ", (FILE)); \ | |
2006 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2007 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
2008 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
2009 | { \ | |
2010 | fputs ("\n\t.weakref\t.", (FILE)); \ | |
2011 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2012 | fputs (", .", (FILE)); \ | |
2013 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2014 | } \ | |
2015 | fputc ('\n', (FILE)); \ | |
2016 | } while (0) | |
2017 | #endif | |
2018 | ||
79c4e63f AM |
2019 | /* This implements the `alias' attribute. */ |
2020 | #undef ASM_OUTPUT_DEF_FROM_DECLS | |
2021 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
2022 | do \ | |
2023 | { \ | |
2024 | const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
2025 | const char *name = IDENTIFIER_POINTER (TARGET); \ | |
2026 | if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
85b776df | 2027 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f AM |
2028 | { \ |
2029 | if (TREE_PUBLIC (DECL)) \ | |
2030 | { \ | |
2031 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
2032 | { \ | |
2033 | fputs ("\t.globl\t.", FILE); \ | |
cbaaba19 | 2034 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
2035 | putc ('\n', FILE); \ |
2036 | } \ | |
2037 | } \ | |
2038 | else if (TARGET_XCOFF) \ | |
2039 | { \ | |
2040 | fputs ("\t.lglobl\t.", FILE); \ | |
cbaaba19 | 2041 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
2042 | putc ('\n', FILE); \ |
2043 | } \ | |
2044 | fputs ("\t.set\t.", FILE); \ | |
cbaaba19 | 2045 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f | 2046 | fputs (",.", FILE); \ |
cbaaba19 | 2047 | RS6000_OUTPUT_BASENAME (FILE, name); \ |
79c4e63f AM |
2048 | fputc ('\n', FILE); \ |
2049 | } \ | |
2050 | ASM_OUTPUT_DEF (FILE, alias, name); \ | |
2051 | } \ | |
2052 | while (0) | |
290ad355 | 2053 | |
1bc7c5b6 ZW |
2054 | #define TARGET_ASM_FILE_START rs6000_file_start |
2055 | ||
f045b2c9 RS |
2056 | /* Output to assembler file text saying following lines |
2057 | may contain character constants, extra white space, comments, etc. */ | |
2058 | ||
2059 | #define ASM_APP_ON "" | |
2060 | ||
2061 | /* Output to assembler file text saying following lines | |
2062 | no longer contain unusual constructs. */ | |
2063 | ||
2064 | #define ASM_APP_OFF "" | |
2065 | ||
f045b2c9 RS |
2066 | /* How to refer to registers in assembler output. |
2067 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2068 | ||
82e41834 | 2069 | extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ |
c81bebd7 MM |
2070 | |
2071 | #define REGISTER_NAMES \ | |
2072 | { \ | |
2073 | &rs6000_reg_names[ 0][0], /* r0 */ \ | |
2074 | &rs6000_reg_names[ 1][0], /* r1 */ \ | |
2075 | &rs6000_reg_names[ 2][0], /* r2 */ \ | |
2076 | &rs6000_reg_names[ 3][0], /* r3 */ \ | |
2077 | &rs6000_reg_names[ 4][0], /* r4 */ \ | |
2078 | &rs6000_reg_names[ 5][0], /* r5 */ \ | |
2079 | &rs6000_reg_names[ 6][0], /* r6 */ \ | |
2080 | &rs6000_reg_names[ 7][0], /* r7 */ \ | |
2081 | &rs6000_reg_names[ 8][0], /* r8 */ \ | |
2082 | &rs6000_reg_names[ 9][0], /* r9 */ \ | |
2083 | &rs6000_reg_names[10][0], /* r10 */ \ | |
2084 | &rs6000_reg_names[11][0], /* r11 */ \ | |
2085 | &rs6000_reg_names[12][0], /* r12 */ \ | |
2086 | &rs6000_reg_names[13][0], /* r13 */ \ | |
2087 | &rs6000_reg_names[14][0], /* r14 */ \ | |
2088 | &rs6000_reg_names[15][0], /* r15 */ \ | |
2089 | &rs6000_reg_names[16][0], /* r16 */ \ | |
2090 | &rs6000_reg_names[17][0], /* r17 */ \ | |
2091 | &rs6000_reg_names[18][0], /* r18 */ \ | |
2092 | &rs6000_reg_names[19][0], /* r19 */ \ | |
2093 | &rs6000_reg_names[20][0], /* r20 */ \ | |
2094 | &rs6000_reg_names[21][0], /* r21 */ \ | |
2095 | &rs6000_reg_names[22][0], /* r22 */ \ | |
2096 | &rs6000_reg_names[23][0], /* r23 */ \ | |
2097 | &rs6000_reg_names[24][0], /* r24 */ \ | |
2098 | &rs6000_reg_names[25][0], /* r25 */ \ | |
2099 | &rs6000_reg_names[26][0], /* r26 */ \ | |
2100 | &rs6000_reg_names[27][0], /* r27 */ \ | |
2101 | &rs6000_reg_names[28][0], /* r28 */ \ | |
2102 | &rs6000_reg_names[29][0], /* r29 */ \ | |
2103 | &rs6000_reg_names[30][0], /* r30 */ \ | |
2104 | &rs6000_reg_names[31][0], /* r31 */ \ | |
2105 | \ | |
2106 | &rs6000_reg_names[32][0], /* fr0 */ \ | |
2107 | &rs6000_reg_names[33][0], /* fr1 */ \ | |
2108 | &rs6000_reg_names[34][0], /* fr2 */ \ | |
2109 | &rs6000_reg_names[35][0], /* fr3 */ \ | |
2110 | &rs6000_reg_names[36][0], /* fr4 */ \ | |
2111 | &rs6000_reg_names[37][0], /* fr5 */ \ | |
2112 | &rs6000_reg_names[38][0], /* fr6 */ \ | |
2113 | &rs6000_reg_names[39][0], /* fr7 */ \ | |
2114 | &rs6000_reg_names[40][0], /* fr8 */ \ | |
2115 | &rs6000_reg_names[41][0], /* fr9 */ \ | |
2116 | &rs6000_reg_names[42][0], /* fr10 */ \ | |
2117 | &rs6000_reg_names[43][0], /* fr11 */ \ | |
2118 | &rs6000_reg_names[44][0], /* fr12 */ \ | |
2119 | &rs6000_reg_names[45][0], /* fr13 */ \ | |
2120 | &rs6000_reg_names[46][0], /* fr14 */ \ | |
2121 | &rs6000_reg_names[47][0], /* fr15 */ \ | |
2122 | &rs6000_reg_names[48][0], /* fr16 */ \ | |
2123 | &rs6000_reg_names[49][0], /* fr17 */ \ | |
2124 | &rs6000_reg_names[50][0], /* fr18 */ \ | |
2125 | &rs6000_reg_names[51][0], /* fr19 */ \ | |
2126 | &rs6000_reg_names[52][0], /* fr20 */ \ | |
2127 | &rs6000_reg_names[53][0], /* fr21 */ \ | |
2128 | &rs6000_reg_names[54][0], /* fr22 */ \ | |
2129 | &rs6000_reg_names[55][0], /* fr23 */ \ | |
2130 | &rs6000_reg_names[56][0], /* fr24 */ \ | |
2131 | &rs6000_reg_names[57][0], /* fr25 */ \ | |
2132 | &rs6000_reg_names[58][0], /* fr26 */ \ | |
2133 | &rs6000_reg_names[59][0], /* fr27 */ \ | |
2134 | &rs6000_reg_names[60][0], /* fr28 */ \ | |
2135 | &rs6000_reg_names[61][0], /* fr29 */ \ | |
2136 | &rs6000_reg_names[62][0], /* fr30 */ \ | |
2137 | &rs6000_reg_names[63][0], /* fr31 */ \ | |
2138 | \ | |
462f7901 | 2139 | &rs6000_reg_names[64][0], /* was mq */ \ |
c81bebd7 MM |
2140 | &rs6000_reg_names[65][0], /* lr */ \ |
2141 | &rs6000_reg_names[66][0], /* ctr */ \ | |
2142 | &rs6000_reg_names[67][0], /* ap */ \ | |
2143 | \ | |
2144 | &rs6000_reg_names[68][0], /* cr0 */ \ | |
2145 | &rs6000_reg_names[69][0], /* cr1 */ \ | |
2146 | &rs6000_reg_names[70][0], /* cr2 */ \ | |
2147 | &rs6000_reg_names[71][0], /* cr3 */ \ | |
2148 | &rs6000_reg_names[72][0], /* cr4 */ \ | |
2149 | &rs6000_reg_names[73][0], /* cr5 */ \ | |
2150 | &rs6000_reg_names[74][0], /* cr6 */ \ | |
2151 | &rs6000_reg_names[75][0], /* cr7 */ \ | |
802a0058 | 2152 | \ |
f6b5d695 | 2153 | &rs6000_reg_names[76][0], /* ca */ \ |
0ac081f6 AH |
2154 | \ |
2155 | &rs6000_reg_names[77][0], /* v0 */ \ | |
2156 | &rs6000_reg_names[78][0], /* v1 */ \ | |
2157 | &rs6000_reg_names[79][0], /* v2 */ \ | |
2158 | &rs6000_reg_names[80][0], /* v3 */ \ | |
2159 | &rs6000_reg_names[81][0], /* v4 */ \ | |
2160 | &rs6000_reg_names[82][0], /* v5 */ \ | |
2161 | &rs6000_reg_names[83][0], /* v6 */ \ | |
2162 | &rs6000_reg_names[84][0], /* v7 */ \ | |
2163 | &rs6000_reg_names[85][0], /* v8 */ \ | |
2164 | &rs6000_reg_names[86][0], /* v9 */ \ | |
2165 | &rs6000_reg_names[87][0], /* v10 */ \ | |
2166 | &rs6000_reg_names[88][0], /* v11 */ \ | |
2167 | &rs6000_reg_names[89][0], /* v12 */ \ | |
2168 | &rs6000_reg_names[90][0], /* v13 */ \ | |
2169 | &rs6000_reg_names[91][0], /* v14 */ \ | |
2170 | &rs6000_reg_names[92][0], /* v15 */ \ | |
2171 | &rs6000_reg_names[93][0], /* v16 */ \ | |
2172 | &rs6000_reg_names[94][0], /* v17 */ \ | |
2173 | &rs6000_reg_names[95][0], /* v18 */ \ | |
2174 | &rs6000_reg_names[96][0], /* v19 */ \ | |
2175 | &rs6000_reg_names[97][0], /* v20 */ \ | |
2176 | &rs6000_reg_names[98][0], /* v21 */ \ | |
2177 | &rs6000_reg_names[99][0], /* v22 */ \ | |
2178 | &rs6000_reg_names[100][0], /* v23 */ \ | |
2179 | &rs6000_reg_names[101][0], /* v24 */ \ | |
2180 | &rs6000_reg_names[102][0], /* v25 */ \ | |
2181 | &rs6000_reg_names[103][0], /* v26 */ \ | |
2182 | &rs6000_reg_names[104][0], /* v27 */ \ | |
2183 | &rs6000_reg_names[105][0], /* v28 */ \ | |
2184 | &rs6000_reg_names[106][0], /* v29 */ \ | |
2185 | &rs6000_reg_names[107][0], /* v30 */ \ | |
2186 | &rs6000_reg_names[108][0], /* v31 */ \ | |
2187 | &rs6000_reg_names[109][0], /* vrsave */ \ | |
5f004351 | 2188 | &rs6000_reg_names[110][0], /* vscr */ \ |
a3170dc6 AH |
2189 | &rs6000_reg_names[111][0], /* spe_acc */ \ |
2190 | &rs6000_reg_names[112][0], /* spefscr */ \ | |
7d5175e1 | 2191 | &rs6000_reg_names[113][0], /* sfp */ \ |
c81bebd7 MM |
2192 | } |
2193 | ||
f045b2c9 RS |
2194 | /* Table of additional register names to use in user input. */ |
2195 | ||
2196 | #define ADDITIONAL_REGISTER_NAMES \ | |
c4d38ccb MM |
2197 | {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ |
2198 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2199 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2200 | {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2201 | {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2202 | {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2203 | {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2204 | {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2205 | {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2206 | {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2207 | {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2208 | {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2209 | {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2210 | {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2211 | {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2212 | {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
0ac081f6 AH |
2213 | {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ |
2214 | {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
2215 | {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
2216 | {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
2217 | {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
2218 | {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
2219 | {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
2220 | {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
5f004351 | 2221 | {"vrsave", 109}, {"vscr", 110}, \ |
a3170dc6 | 2222 | {"spe_acc", 111}, {"spefscr", 112}, \ |
462f7901 | 2223 | /* no additional names for: lr, ctr, ap */ \ |
c4d38ccb MM |
2224 | {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ |
2225 | {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
cacf1ca8 | 2226 | {"cc", 68}, {"sp", 1}, {"toc", 2}, \ |
f6b5d695 SB |
2227 | /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
2228 | {"xer", 76}, \ | |
cacf1ca8 MM |
2229 | /* VSX registers overlaid on top of FR, Altivec registers */ \ |
2230 | {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ | |
2231 | {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ | |
2232 | {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ | |
2233 | {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ | |
2234 | {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ | |
2235 | {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ | |
2236 | {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ | |
2237 | {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ | |
2238 | {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ | |
2239 | {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ | |
2240 | {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ | |
2241 | {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ | |
2242 | {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ | |
2243 | {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ | |
2244 | {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ | |
2245 | {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} } | |
f045b2c9 | 2246 | |
f045b2c9 RS |
2247 | /* This is how to output an element of a case-vector that is relative. */ |
2248 | ||
e1565e65 | 2249 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3daf36a4 | 2250 | do { char buf[100]; \ |
e1565e65 | 2251 | fputs ("\t.long ", FILE); \ |
3daf36a4 ILT |
2252 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ |
2253 | assemble_name (FILE, buf); \ | |
19d2d16f | 2254 | putc ('-', FILE); \ |
3daf36a4 ILT |
2255 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ |
2256 | assemble_name (FILE, buf); \ | |
19d2d16f | 2257 | putc ('\n', FILE); \ |
3daf36a4 | 2258 | } while (0) |
f045b2c9 RS |
2259 | |
2260 | /* This is how to output an assembler line | |
2261 | that says to advance the location counter | |
2262 | to a multiple of 2**LOG bytes. */ | |
2263 | ||
2264 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2265 | if ((LOG) != 0) \ | |
2266 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
2267 | ||
58082ff6 PH |
2268 | /* How to align the given loop. */ |
2269 | #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) | |
2270 | ||
9ebbca7d GK |
2271 | /* Pick up the return address upon entry to a procedure. Used for |
2272 | dwarf2 unwind information. This also enables the table driven | |
2273 | mechanism. */ | |
2274 | ||
1de43f85 DE |
2275 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) |
2276 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
9ebbca7d | 2277 | |
83720594 RH |
2278 | /* Describe how we implement __builtin_eh_return. */ |
2279 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2280 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2281 | ||
f045b2c9 RS |
2282 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2283 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2284 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2285 | ||
2286 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2287 | ||
2288 | /* Define which CODE values are valid. */ | |
2289 | ||
3cf437d4 | 2290 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') |
f045b2c9 RS |
2291 | |
2292 | /* Print a memory address as an operand to reference that memory location. */ | |
2293 | ||
2294 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2295 | ||
b6c9286a MM |
2296 | /* uncomment for disabling the corresponding default options */ |
2297 | /* #define MACHINE_no_sched_interblock */ | |
2298 | /* #define MACHINE_no_sched_speculative */ | |
2299 | /* #define MACHINE_no_sched_speculative_load */ | |
2300 | ||
766a866c | 2301 | /* General flags. */ |
a7df97e6 | 2302 | extern int frame_pointer_needed; |
0ac081f6 | 2303 | |
7fa14a01 MM |
2304 | /* Classification of the builtin functions as to which switches enable the |
2305 | builtin, and what attributes it should have. We used to use the target | |
2306 | flags macros, but we've run out of bits, so we now map the options into new | |
2307 | settings used here. */ | |
2308 | ||
2309 | /* Builtin attributes. */ | |
2310 | #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ | |
2311 | #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ | |
2312 | #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ | |
2313 | #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ | |
2314 | #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ | |
2315 | #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ | |
2316 | #define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */ | |
2317 | #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ | |
2318 | #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ | |
2319 | ||
2320 | #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ | |
2321 | #define RS6000_BTC_CONST 0x00000100 /* uses no global state. */ | |
2322 | #define RS6000_BTC_PURE 0x00000200 /* reads global state/mem. */ | |
2323 | #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ | |
2324 | #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ | |
2325 | ||
2326 | /* Miscellaneous information. */ | |
2327 | #define RS6000_BTC_OVERLOADED 0x4000000 /* function is overloaded. */ | |
1c9df37c MM |
2328 | |
2329 | /* Convenience macros to document the instruction type. */ | |
7fa14a01 MM |
2330 | #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ |
2331 | #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ | |
2332 | ||
2333 | /* Builtin targets. For now, we reuse the masks for those options that are in | |
2334 | target flags, and pick two random bits for SPE and paired which aren't in | |
2335 | target_flags. */ | |
4b705221 | 2336 | #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ |
7fa14a01 MM |
2337 | #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ |
2338 | #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ | |
2339 | #define RS6000_BTM_SPE MASK_STRING /* E500 */ | |
2340 | #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ | |
2341 | #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ | |
2342 | #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ | |
2343 | #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ | |
2344 | #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ | |
2345 | #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ | |
7fa14a01 MM |
2346 | #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ |
2347 | ||
2348 | #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | |
2349 | | RS6000_BTM_VSX \ | |
2350 | | RS6000_BTM_FRE \ | |
2351 | | RS6000_BTM_FRES \ | |
2352 | | RS6000_BTM_FRSQRTE \ | |
2353 | | RS6000_BTM_FRSQRTES \ | |
2354 | | RS6000_BTM_POPCNTD \ | |
7fa14a01 MM |
2355 | | RS6000_BTM_CELL) |
2356 | ||
2357 | /* Define builtin enum index. */ | |
2358 | ||
2359 | #undef RS6000_BUILTIN_1 | |
2360 | #undef RS6000_BUILTIN_2 | |
2361 | #undef RS6000_BUILTIN_3 | |
2362 | #undef RS6000_BUILTIN_A | |
2363 | #undef RS6000_BUILTIN_D | |
2364 | #undef RS6000_BUILTIN_E | |
2365 | #undef RS6000_BUILTIN_P | |
2366 | #undef RS6000_BUILTIN_Q | |
2367 | #undef RS6000_BUILTIN_S | |
2368 | #undef RS6000_BUILTIN_X | |
2369 | ||
2370 | #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2371 | #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2372 | #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2373 | #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2374 | #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2375 | #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2376 | #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2377 | #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2378 | #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2379 | #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
1c9df37c | 2380 | |
0ac081f6 AH |
2381 | enum rs6000_builtins |
2382 | { | |
1c9df37c | 2383 | #include "rs6000-builtin.def" |
a72c65c7 | 2384 | |
58646b77 PB |
2385 | RS6000_BUILTIN_COUNT |
2386 | }; | |
2387 | ||
7fa14a01 MM |
2388 | #undef RS6000_BUILTIN_1 |
2389 | #undef RS6000_BUILTIN_2 | |
2390 | #undef RS6000_BUILTIN_3 | |
2391 | #undef RS6000_BUILTIN_A | |
2392 | #undef RS6000_BUILTIN_D | |
2393 | #undef RS6000_BUILTIN_E | |
2394 | #undef RS6000_BUILTIN_P | |
2395 | #undef RS6000_BUILTIN_Q | |
2396 | #undef RS6000_BUILTIN_S | |
2397 | #undef RS6000_BUILTIN_X | |
1c9df37c | 2398 | |
58646b77 PB |
2399 | enum rs6000_builtin_type_index |
2400 | { | |
2401 | RS6000_BTI_NOT_OPAQUE, | |
2402 | RS6000_BTI_opaque_V2SI, | |
2403 | RS6000_BTI_opaque_V2SF, | |
2404 | RS6000_BTI_opaque_p_V2SI, | |
2405 | RS6000_BTI_opaque_V4SI, | |
2406 | RS6000_BTI_V16QI, | |
2407 | RS6000_BTI_V2SI, | |
2408 | RS6000_BTI_V2SF, | |
a72c65c7 MM |
2409 | RS6000_BTI_V2DI, |
2410 | RS6000_BTI_V2DF, | |
58646b77 PB |
2411 | RS6000_BTI_V4HI, |
2412 | RS6000_BTI_V4SI, | |
2413 | RS6000_BTI_V4SF, | |
2414 | RS6000_BTI_V8HI, | |
2415 | RS6000_BTI_unsigned_V16QI, | |
2416 | RS6000_BTI_unsigned_V8HI, | |
2417 | RS6000_BTI_unsigned_V4SI, | |
a72c65c7 | 2418 | RS6000_BTI_unsigned_V2DI, |
58646b77 PB |
2419 | RS6000_BTI_bool_char, /* __bool char */ |
2420 | RS6000_BTI_bool_short, /* __bool short */ | |
2421 | RS6000_BTI_bool_int, /* __bool int */ | |
a72c65c7 | 2422 | RS6000_BTI_bool_long, /* __bool long */ |
58646b77 PB |
2423 | RS6000_BTI_pixel, /* __pixel */ |
2424 | RS6000_BTI_bool_V16QI, /* __vector __bool char */ | |
2425 | RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
2426 | RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
a72c65c7 | 2427 | RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
58646b77 PB |
2428 | RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
2429 | RS6000_BTI_long, /* long_integer_type_node */ | |
2430 | RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
c9485473 MM |
2431 | RS6000_BTI_long_long, /* long_long_integer_type_node */ |
2432 | RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ | |
58646b77 PB |
2433 | RS6000_BTI_INTQI, /* intQI_type_node */ |
2434 | RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ | |
2435 | RS6000_BTI_INTHI, /* intHI_type_node */ | |
2436 | RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
2437 | RS6000_BTI_INTSI, /* intSI_type_node */ | |
2438 | RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ | |
a72c65c7 MM |
2439 | RS6000_BTI_INTDI, /* intDI_type_node */ |
2440 | RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ | |
58646b77 | 2441 | RS6000_BTI_float, /* float_type_node */ |
a72c65c7 | 2442 | RS6000_BTI_double, /* double_type_node */ |
58646b77 PB |
2443 | RS6000_BTI_void, /* void_type_node */ |
2444 | RS6000_BTI_MAX | |
0ac081f6 | 2445 | }; |
58646b77 PB |
2446 | |
2447 | ||
2448 | #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) | |
2449 | #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) | |
2450 | #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) | |
2451 | #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) | |
2452 | #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
a72c65c7 MM |
2453 | #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
2454 | #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) | |
58646b77 PB |
2455 | #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) |
2456 | #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) | |
2457 | #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) | |
2458 | #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
2459 | #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
2460 | #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
2461 | #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
2462 | #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) | |
2463 | #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
a72c65c7 | 2464 | #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
58646b77 PB |
2465 | #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
2466 | #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
2467 | #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
a72c65c7 | 2468 | #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) |
58646b77 PB |
2469 | #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
2470 | #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
2471 | #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
2472 | #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
a72c65c7 | 2473 | #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
58646b77 PB |
2474 | #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
2475 | ||
c9485473 MM |
2476 | #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
2477 | #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) | |
58646b77 PB |
2478 | #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
2479 | #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
2480 | #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
2481 | #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
2482 | #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
2483 | #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
2484 | #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
2485 | #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
a72c65c7 MM |
2486 | #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
2487 | #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) | |
58646b77 | 2488 | #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
a72c65c7 | 2489 | #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
58646b77 PB |
2490 | #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
2491 | ||
2492 | extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
2493 | extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
2494 |