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Step 1 of VSX changes: Powerpc infrstructure changes
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.h
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f045b2c9 1/* Definitions of target machine for GNU compiler, for IBM RS/6000.
9ebbca7d 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
748086b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
602ea4d3 4 Free Software Foundation, Inc.
6a7ec0a7 5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
f045b2c9 6
5de601cf 7 This file is part of GCC.
f045b2c9 8
5de601cf
NC		 9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
2f83c7d6 11 by the Free Software Foundation; either version 3, or (at your
5de601cf 12 option) any later version.
f045b2c9 13
5de601cf
NC		 14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
f045b2c9 18
748086b7
JJ		 19 Under Section 7 of GPL version 3, you are granted additional
20 permissions described in the GCC Runtime Library Exception, version
21 3.1, as published by the Free Software Foundation.
22
23 You should have received a copy of the GNU General Public License and
24 a copy of the GCC Runtime Library Exception along with this program;
25 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2f83c7d6 26 <http://www.gnu.org/licenses/>. */
f045b2c9
RS		 27
28/* Note that some other tm.h files include this one and then override
9ebbca7d 29 many of the definitions. */
f045b2c9 30
9ebbca7d
GK		 31/* Definitions for the object file format. These are set at
32 compile-time. */
f045b2c9 33
9ebbca7d
GK		 34#define OBJECT_XCOFF 1
35#define OBJECT_ELF 2
36#define OBJECT_PEF 3
ee890fe2 37#define OBJECT_MACHO 4
f045b2c9 38
9ebbca7d 39#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
2bfcf297 40#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
9ebbca7d 41#define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
ee890fe2 42#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
f045b2c9 43
2bfcf297
DB		 44#ifndef TARGET_AIX
45#define TARGET_AIX 0
46#endif
47
85b776df
AM		 48/* Control whether function entry points use a "dot" symbol when
49 ABI_AIX. */
50#define DOT_SYMBOLS 1
51
8e3f41e7
MM		 52/* Default string to use for cpu if not specified. */
53#ifndef TARGET_CPU_DEFAULT
54#define TARGET_CPU_DEFAULT ((char *)0)
55#endif
56
f565b0a1 57/* If configured for PPC405, support PPC405CR Erratum77. */
b0bfee6e 58#ifdef CONFIG_PPC405CR
f565b0a1
DE		 59#define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
60#else
61#define PPC405_ERRATUM77 0
62#endif
63
96038623
DE		 64#ifndef TARGET_PAIRED_FLOAT
65#define TARGET_PAIRED_FLOAT 0
66#endif
67
cd679487
BE		 68#ifdef HAVE_AS_POPCNTB
69#define ASM_CPU_POWER5_SPEC "-mpower5"
70#else
71#define ASM_CPU_POWER5_SPEC "-mpower4"
72#endif
73
74#ifdef HAVE_AS_DFP
75#define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
76#else
77#define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
78#endif
79
cacf1ca8 80#ifdef HAVE_AS_POPCNTD
d40c9e33
PB		 81#define ASM_CPU_POWER7_SPEC "-mpower7"
82#else
83#define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
84#endif
85
cacf1ca8
MM		 86/* Common ASM definitions used by ASM_SPEC among the various targets for
87 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
88 provide the default assembler options if the user uses -mcpu=native, so if
89 you make changes here, make them also there. */
f984d8df
DB		 90#define ASM_CPU_SPEC \
91"%{!mcpu*: \
92 %{mpower: %{!mpower2: -mpwr}} \
93 %{mpower2: -mpwrx} \
93ae5495
AM		 94 %{mpowerpc64*: -mppc64} \
95 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
f984d8df 96 %{mno-power: %{!mpowerpc*: -mcom}} \
93ae5495 97 %{!mno-power: %{!mpower*: %(asm_default)}}} \
cacf1ca8 98%{mcpu=native: %(asm_cpu_native)} \
f984d8df 99%{mcpu=common: -mcom} \
d296e02e 100%{mcpu=cell: -mcell} \
f984d8df
DB		 101%{mcpu=power: -mpwr} \
102%{mcpu=power2: -mpwrx} \
93ae5495 103%{mcpu=power3: -mppc64} \
957e9e48 104%{mcpu=power4: -mpower4} \
cd679487
BE		 105%{mcpu=power5: %(asm_cpu_power5)} \
106%{mcpu=power5+: %(asm_cpu_power5)} \
107%{mcpu=power6: %(asm_cpu_power6) -maltivec} \
108%{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
d40c9e33 109%{mcpu=power7: %(asm_cpu_power7)} \
f984d8df
DB		 110%{mcpu=powerpc: -mppc} \
111%{mcpu=rios: -mpwr} \
112%{mcpu=rios1: -mpwr} \
113%{mcpu=rios2: -mpwrx} \
114%{mcpu=rsc: -mpwr} \
115%{mcpu=rsc1: -mpwr} \
93ae5495 116%{mcpu=rs64a: -mppc64} \
f984d8df 117%{mcpu=401: -mppc} \
61a8515c
JS		 118%{mcpu=403: -m403} \
119%{mcpu=405: -m405} \
2c9d95ef
DE		 120%{mcpu=405fp: -m405} \
121%{mcpu=440: -m440} \
122%{mcpu=440fp: -m440} \
4adf8008
PB		 123%{mcpu=464: -m440} \
124%{mcpu=464fp: -m440} \
f984d8df
DB		 125%{mcpu=505: -mppc} \
126%{mcpu=601: -m601} \
127%{mcpu=602: -mppc} \
128%{mcpu=603: -mppc} \
129%{mcpu=603e: -mppc} \
130%{mcpu=ec603e: -mppc} \
131%{mcpu=604: -mppc} \
132%{mcpu=604e: -mppc} \
93ae5495
AM		 133%{mcpu=620: -mppc64} \
134%{mcpu=630: -mppc64} \
f984d8df
DB		 135%{mcpu=740: -mppc} \
136%{mcpu=750: -mppc} \
49ffe578 137%{mcpu=G3: -mppc} \
93ae5495
AM		 138%{mcpu=7400: -mppc -maltivec} \
139%{mcpu=7450: -mppc -maltivec} \
140%{mcpu=G4: -mppc -maltivec} \
f984d8df
DB		 141%{mcpu=801: -mppc} \
142%{mcpu=821: -mppc} \
143%{mcpu=823: -mppc} \
775db490 144%{mcpu=860: -mppc} \
93ae5495
AM		 145%{mcpu=970: -mpower4 -maltivec} \
146%{mcpu=G5: -mpower4 -maltivec} \
a3170dc6 147%{mcpu=8540: -me500} \
5ca0373f 148%{mcpu=8548: -me500} \
fa41c305
EW		 149%{mcpu=e300c2: -me300} \
150%{mcpu=e300c3: -me300} \
edae5fe3 151%{mcpu=e500mc: -me500mc} \
93ae5495
AM		 152%{maltivec: -maltivec} \
153-many"
f984d8df
DB		 154
155#define CPP_DEFAULT_SPEC ""
156
157#define ASM_DEFAULT_SPEC ""
158
841faeed
MM		 159/* This macro defines names of additional specifications to put in the specs
160 that can be used in various specifications like CC1_SPEC. Its definition
161 is an initializer with a subgrouping for each command option.
162
163 Each subgrouping contains a string constant, that defines the
5de601cf 164 specification name, and a string constant that used by the GCC driver
841faeed
MM		 165 program.
166
167 Do not define this macro if it does not need to do anything. */
168
7509c759 169#define SUBTARGET_EXTRA_SPECS
7509c759 170
c81bebd7 171#define EXTRA_SPECS \
c81bebd7 172 { "cpp_default", CPP_DEFAULT_SPEC }, \
c81bebd7 173 { "asm_cpu", ASM_CPU_SPEC }, \
cacf1ca8 174 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
c81bebd7 175 { "asm_default", ASM_DEFAULT_SPEC }, \
0eab6840 176 { "cc1_cpu", CC1_CPU_SPEC }, \
cd679487
BE		 177 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
178 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
d40c9e33 179 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
7509c759
MM		 180 SUBTARGET_EXTRA_SPECS
181
0eab6840
DE		 182/* -mcpu=native handling only makes sense with compiler running on
183 an PowerPC chip. If changing this condition, also change
184 the condition in driver-rs6000.c. */
185#if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
186/* In driver-rs6000.c. */
187extern const char *host_detect_local_cpu (int argc, const char **argv);
188#define EXTRA_SPEC_FUNCTIONS \
189 { "local_cpu_detect", host_detect_local_cpu },
190#define HAVE_LOCAL_CPU_DETECT
cacf1ca8
MM		 191#define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
192
193#else
194#define ASM_CPU_NATIVE_SPEC "%(asm_default)"
0eab6840
DE		 195#endif
196
ee7caeb3
DE		 197#ifndef CC1_CPU_SPEC
198#ifdef HAVE_LOCAL_CPU_DETECT
0eab6840
DE		 199#define CC1_CPU_SPEC \
200"%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
201 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
ee7caeb3
DE		 202#else
203#define CC1_CPU_SPEC ""
204#endif
0eab6840
DE		 205#endif
206
fb623df5 207/* Architecture type. */
f045b2c9 208
bb22512c 209/* Define TARGET_MFCRF if the target assembler does not support the
78f5898b 210 optional field operand for mfcr. */
fb623df5 211
78f5898b 212#ifndef HAVE_AS_MFCRF
432218ba 213#undef TARGET_MFCRF
ffa22984
DE		 214#define TARGET_MFCRF 0
215#endif
216
0fa2e4df 217/* Define TARGET_POPCNTB if the target assembler does not support the
432218ba
DE		 218 popcount byte instruction. */
219
220#ifndef HAVE_AS_POPCNTB
221#undef TARGET_POPCNTB
222#define TARGET_POPCNTB 0
223#endif
224
9719f3b7
DE		 225/* Define TARGET_FPRND if the target assembler does not support the
226 fp rounding instructions. */
227
228#ifndef HAVE_AS_FPRND
229#undef TARGET_FPRND
230#define TARGET_FPRND 0
231#endif
232
b639c3c2
JJ		 233/* Define TARGET_CMPB if the target assembler does not support the
234 cmpb instruction. */
235
236#ifndef HAVE_AS_CMPB
237#undef TARGET_CMPB
238#define TARGET_CMPB 0
239#endif
240
44cd321e
PS		 241/* Define TARGET_MFPGPR if the target assembler does not support the
242 mffpr and mftgpr instructions. */
243
244#ifndef HAVE_AS_MFPGPR
245#undef TARGET_MFPGPR
246#define TARGET_MFPGPR 0
247#endif
248
b639c3c2
JJ		 249/* Define TARGET_DFP if the target assembler does not support decimal
250 floating point instructions. */
251#ifndef HAVE_AS_DFP
252#undef TARGET_DFP
253#define TARGET_DFP 0
254#endif
255
cacf1ca8
MM		 256/* Define TARGET_POPCNTD if the target assembler does not support the
257 popcount word and double word instructions. */
258
259#ifndef HAVE_AS_POPCNTD
260#undef TARGET_POPCNTD
261#define TARGET_POPCNTD 0
262#endif
263
264/* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
265 not, generate the lwsync code as an integer constant. */
266#ifdef HAVE_AS_LWSYNC
267#define TARGET_LWSYNC_INSTRUCTION 1
268#else
269#define TARGET_LWSYNC_INSTRUCTION 0
270#endif
271
9752c4ad
AM		 272/* Define TARGET_TLS_MARKERS if the target assembler does not support
273 arg markers for __tls_get_addr calls. */
274#ifndef HAVE_AS_TLS_MARKERS
275#undef TARGET_TLS_MARKERS
276#define TARGET_TLS_MARKERS 0
277#else
278#define TARGET_TLS_MARKERS tls_markers
279#endif
280
7f970b70
AM		 281#ifndef TARGET_SECURE_PLT
282#define TARGET_SECURE_PLT 0
283#endif
284
2f3e5814 285#define TARGET_32BIT (! TARGET_64BIT)
d14a6d05 286
c4501e62
JJ		 287#ifndef HAVE_AS_TLS
288#define HAVE_AS_TLS 0
289#endif
290
48d72335
DE		 291/* Return 1 for a symbol ref for a thread-local storage symbol. */
292#define RS6000_SYMBOL_REF_TLS_P(RTX) \
293 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
294
996ed075
JJ		 295#ifdef IN_LIBGCC2
296/* For libgcc2 we make sure this is a compile time constant */
67796c1f 297#if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
78f5898b 298#undef TARGET_POWERPC64
996ed075
JJ		 299#define TARGET_POWERPC64 1
300#else
78f5898b 301#undef TARGET_POWERPC64
996ed075
JJ		 302#define TARGET_POWERPC64 0
303#endif
b6c9286a 304#else
78f5898b 305 /* The option machinery will define this. */
b6c9286a
MM		 306#endif
307
938937d8 308#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
9ebbca7d 309
cac8ce95 310/* Processor type. Order must match cpu attribute in MD file. */
fb623df5 311enum processor_type
bef84347
VM		 312 {
313 PROCESSOR_RIOS1,
314 PROCESSOR_RIOS2,
3cb999d8 315 PROCESSOR_RS64A,
bef84347
VM		 316 PROCESSOR_MPCCORE,
317 PROCESSOR_PPC403,
fe7f5677 318 PROCESSOR_PPC405,
b54cf83a 319 PROCESSOR_PPC440,
bef84347
VM		 320 PROCESSOR_PPC601,
321 PROCESSOR_PPC603,
322 PROCESSOR_PPC604,
323 PROCESSOR_PPC604e,
324 PROCESSOR_PPC620,
3cb999d8 325 PROCESSOR_PPC630,
ed947a96
DJ		 326 PROCESSOR_PPC750,
327 PROCESSOR_PPC7400,
309323c2 328 PROCESSOR_PPC7450,
a3170dc6 329 PROCESSOR_PPC8540,
fa41c305
EW		 330 PROCESSOR_PPCE300C2,
331 PROCESSOR_PPCE300C3,
edae5fe3 332 PROCESSOR_PPCE500MC,
ec507f2d 333 PROCESSOR_POWER4,
44cd321e 334 PROCESSOR_POWER5,
d296e02e 335 PROCESSOR_POWER6,
cacf1ca8 336 PROCESSOR_POWER7,
d296e02e 337 PROCESSOR_CELL
bef84347 338};
fb623df5 339
696e45ba
ME		 340/* FPU operations supported.
341 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
342 also test TARGET_HARD_FLOAT. */
343#define TARGET_SINGLE_FLOAT 1
344#define TARGET_DOUBLE_FLOAT 1
345#define TARGET_SINGLE_FPU 0
346#define TARGET_SIMPLE_FPU 0
0bb7b92e 347#define TARGET_XILINX_FPU 0
696e45ba 348
fb623df5
RK		 349extern enum processor_type rs6000_cpu;
350
351/* Recast the processor type to the cpu attribute. */
352#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
353
8482e358 354/* Define generic processor types based upon current deployment. */
3cb999d8
DE		 355#define PROCESSOR_COMMON PROCESSOR_PPC601
356#define PROCESSOR_POWER PROCESSOR_RIOS1
357#define PROCESSOR_POWERPC PROCESSOR_PPC604
358#define PROCESSOR_POWERPC64 PROCESSOR_RS64A
6e151478 359
fb623df5 360/* Define the default processor. This is overridden by other tm.h files. */
3cb999d8
DE		 361#define PROCESSOR_DEFAULT PROCESSOR_RIOS1
362#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
fb623df5 363
0bb7b92e
ME		 364/* FP processor type. */
365enum fpu_type_t
366{
367 FPU_NONE, /* No FPU */
368 FPU_SF_LITE, /* Limited Single Precision FPU */
369 FPU_DF_LITE, /* Limited Double Precision FPU */
370 FPU_SF_FULL, /* Full Single Precision FPU */
371 FPU_DF_FULL /* Full Double Single Precision FPU */
372};
373
374extern enum fpu_type_t fpu_type;
375
6febd581
RK		 376/* Specify the dialect of assembler to use. New mnemonics is dialect one
377 and the old mnemonics are dialect zero. */
9ebbca7d 378#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
6febd581 379
569fa502
DN		 380/* Types of costly dependences. */
381enum rs6000_dependence_cost
382 {
383 max_dep_latency = 1000,
384 no_dep_costly,
385 all_deps_costly,
386 true_store_to_load_dep_costly,
387 store_to_load_dep_costly
388 };
389
cbe26ab8
DN		 390/* Types of nop insertion schemes in sched target hook sched_finish. */
391enum rs6000_nop_insertion
392 {
393 sched_finish_regroup_exact = 1000,
394 sched_finish_pad_groups,
395 sched_finish_none
396 };
397
398/* Dispatch group termination caused by an insn. */
399enum group_termination
400 {
401 current_group,
402 previous_group
403 };
404
ff222560 405/* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
8e3f41e7
MM		 406struct rs6000_cpu_select
407{
815cdc52
MM		 408 const char *string;
409 const char *name;
8e3f41e7
MM		 410 int set_tune_p;
411 int set_arch_p;
412};
413
414extern struct rs6000_cpu_select rs6000_select[];
fb623df5 415
38c1f2d7 416/* Debug support */
0ac081f6 417extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
38c1f2d7
MM		 418extern int rs6000_debug_stack; /* debug stack applications */
419extern int rs6000_debug_arg; /* debug argument handling */
cacf1ca8
MM		 420extern int rs6000_debug_reg; /* debug register handling */
421extern int rs6000_debug_addr; /* debug memory addressing */
422extern int rs6000_debug_cost; /* debug rtx_costs */
38c1f2d7
MM		 423
424#define TARGET_DEBUG_STACK rs6000_debug_stack
425#define TARGET_DEBUG_ARG rs6000_debug_arg
cacf1ca8
MM		 426#define TARGET_DEBUG_REG rs6000_debug_reg
427#define TARGET_DEBUG_ADDR rs6000_debug_addr
428#define TARGET_DEBUG_COST rs6000_debug_cost
38c1f2d7 429
57ac7be9
AM		 430extern const char *rs6000_traceback_name; /* Type of traceback table. */
431
6fa3f289
ZW		 432/* These are separate from target_flags because we've run out of bits
433 there. */
6fa3f289 434extern int rs6000_long_double_type_size;
602ea4d3 435extern int rs6000_ieeequad;
6fa3f289 436extern int rs6000_altivec_abi;
a3170dc6 437extern int rs6000_spe_abi;
94f4765c 438extern int rs6000_spe;
5da702b1 439extern int rs6000_float_gprs;
025d9908 440extern int rs6000_alignment_flags;
cbe26ab8
DN		 441extern const char *rs6000_sched_insert_nops_str;
442extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
0bb7b92e 443extern int rs6000_xilinx_fpu;
025d9908 444
cacf1ca8
MM		 445/* Describe which vector unit to use for a given machine mode. */
446enum rs6000_vector {
447 VECTOR_NONE, /* Type is not a vector or not supported */
448 VECTOR_ALTIVEC, /* Use altivec for vector processing */
449 VECTOR_VSX, /* Use VSX for vector processing */
450 VECTOR_PAIRED, /* Use paired floating point for vectors */
451 VECTOR_SPE, /* Use SPE for vector processing */
452 VECTOR_OTHER /* Some other vector unit */
453};
454
455extern enum rs6000_vector rs6000_vector_unit[];
456
457#define VECTOR_UNIT_NONE_P(MODE) \
458 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
459
460#define VECTOR_UNIT_VSX_P(MODE) \
461 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
462
463#define VECTOR_UNIT_ALTIVEC_P(MODE) \
464 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
465
466#define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
467 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \
468 || rs6000_vector_unit[(MODE)] == VECTOR_VSX)
469
470/* Describe whether to use VSX loads or Altivec loads. For now, just use the
471 same unit as the vector unit we are using, but we may want to migrate to
472 using VSX style loads even for types handled by altivec. */
473extern enum rs6000_vector rs6000_vector_mem[];
474
475#define VECTOR_MEM_NONE_P(MODE) \
476 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
477
478#define VECTOR_MEM_VSX_P(MODE) \
479 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
480
481#define VECTOR_MEM_ALTIVEC_P(MODE) \
482 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
483
484#define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
485 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \
486 || rs6000_vector_mem[(MODE)] == VECTOR_VSX)
487
488/* Return the alignment of a given vector type, which is set based on the
489 vector unit use. VSX for instance can load 32 or 64 bit aligned words
490 without problems, while Altivec requires 128-bit aligned vectors. */
491extern int rs6000_vector_align[];
492
493#define VECTOR_ALIGN(MODE) \
494 ((rs6000_vector_align[(MODE)] != 0) \
495 ? rs6000_vector_align[(MODE)] \
496 : (int)GET_MODE_BITSIZE ((MODE)))
497
025d9908
KH		 498/* Alignment options for fields in structures for sub-targets following
499 AIX-like ABI.
500 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
501 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
502
503 Override the macro definitions when compiling libobjc to avoid undefined
504 reference to rs6000_alignment_flags due to library's use of GCC alignment
505 macros which use the macros below. */
f676971a 506
025d9908
KH		 507#ifndef IN_TARGET_LIBS
508#define MASK_ALIGN_POWER 0x00000000
509#define MASK_ALIGN_NATURAL 0x00000001
510#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
511#else
512#define TARGET_ALIGN_NATURAL 0
513#endif
6fa3f289
ZW		 514
515#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
602ea4d3 516#define TARGET_IEEEQUAD rs6000_ieeequad
6fa3f289 517#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
cacf1ca8 518#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
6fa3f289 519
a3170dc6
AH		 520#define TARGET_SPE_ABI 0
521#define TARGET_SPE 0
993f19a8 522#define TARGET_E500 0
cacf1ca8 523#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
a3170dc6 524#define TARGET_FPRS 1
4d4cbc0e
AH		 525#define TARGET_E500_SINGLE 0
526#define TARGET_E500_DOUBLE 0
eca0d5e8 527#define CHECK_E500_OPTIONS do { } while (0)
a3170dc6 528
86098753
JM		 529/* E500 processors only support plain "sync", not lwsync. */
530#define TARGET_NO_LWSYNC TARGET_E500
531
fb623df5
RK		 532/* Sometimes certain combinations of command options do not make sense
533 on a particular target machine. You can define a macro
534 `OVERRIDE_OPTIONS' to take account of this. This macro, if
535 defined, is executed once just after all the command options have
536 been parsed.
537
ffa22984 538 Do not use this macro to turn on various extra optimizations for
5accd822
DE		 539 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
540
fb623df5
RK		 541 On the RS/6000 this is used to define the target cpu type. */
542
8e3f41e7 543#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
f045b2c9 544
5accd822
DE		 545/* Define this to change the optimizations performed by default. */
546#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
547
4c4eb375
GK		 548/* Show we can debug even without a frame pointer. */
549#define CAN_DEBUG_WITHOUT_FP
550
a5c76ee6 551/* Target pragma. */
c58b209a
NB		 552#define REGISTER_TARGET_PRAGMAS() do { \
553 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
2fab365e 554 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
a5c76ee6
ZW		 555} while (0)
556
4c4eb375
GK		 557/* Target #defines. */
558#define TARGET_CPU_CPP_BUILTINS() \
559 rs6000_cpu_cpp_builtins (pfile)
647d340d
JT		 560
561/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
562 we're compiling for. Some configurations may need to override it. */
563#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
564 do \
565 { \
566 if (BYTES_BIG_ENDIAN) \
567 { \
568 builtin_define ("__BIG_ENDIAN__"); \
569 builtin_define ("_BIG_ENDIAN"); \
570 builtin_assert ("machine=bigendian"); \
571 } \
572 else \
573 { \
574 builtin_define ("__LITTLE_ENDIAN__"); \
575 builtin_define ("_LITTLE_ENDIAN"); \
576 builtin_assert ("machine=littleendian"); \
577 } \
578 } \
579 while (0)
f045b2c9 580\f
4c4eb375 581/* Target machine storage layout. */
f045b2c9 582
13d39dbc 583/* Define this macro if it is advisable to hold scalars in registers
c81bebd7 584 in a wider mode than that declared by the program. In such cases,
ef457bda
RK		 585 the value is constrained to be within the bounds of the declared
586 type, but kept valid in the wider mode. The signedness of the
587 extension may differ from that of the type. */
588
39403d82
DE		 589#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
590 if (GET_MODE_CLASS (MODE) == MODE_INT \
591 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
b78d48dd 592 (MODE) = TARGET_32BIT ? SImode : DImode;
39403d82 593
f045b2c9 594/* Define this if most significant bit is lowest numbered
82e41834
KH		 595 in instructions that operate on numbered bit-fields. */
596/* That is true on RS/6000. */
f045b2c9
RS		 597#define BITS_BIG_ENDIAN 1
598
599/* Define this if most significant byte of a word is the lowest numbered. */
600/* That is true on RS/6000. */
601#define BYTES_BIG_ENDIAN 1
602
603/* Define this if most significant word of a multiword number is lowest
c81bebd7 604 numbered.
f045b2c9
RS		 605
606 For RS/6000 we can decide arbitrarily since there are no machine
82e41834 607 instructions for them. Might as well be consistent with bits and bytes. */
f045b2c9
RS		 608#define WORDS_BIG_ENDIAN 1
609
2e360ab3 610#define MAX_BITS_PER_WORD 64
f045b2c9
RS		 611
612/* Width of a word, in units (bytes). */
c1aa3958 613#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
f34fc46e
DE		 614#ifdef IN_LIBGCC2
615#define MIN_UNITS_PER_WORD UNITS_PER_WORD
616#else
ef0e53ce 617#define MIN_UNITS_PER_WORD 4
f34fc46e 618#endif
2e360ab3 619#define UNITS_PER_FP_WORD 8
0ac081f6 620#define UNITS_PER_ALTIVEC_WORD 16
cacf1ca8 621#define UNITS_PER_VSX_WORD 16
a3170dc6 622#define UNITS_PER_SPE_WORD 8
96038623 623#define UNITS_PER_PAIRED_WORD 8
f045b2c9 624
915f619f
JW		 625/* Type used for ptrdiff_t, as a string used in a declaration. */
626#define PTRDIFF_TYPE "int"
627
058ef853
DE		 628/* Type used for size_t, as a string used in a declaration. */
629#define SIZE_TYPE "long unsigned int"
630
f045b2c9
RS		 631/* Type used for wchar_t, as a string used in a declaration. */
632#define WCHAR_TYPE "short unsigned int"
633
634/* Width of wchar_t in bits. */
635#define WCHAR_TYPE_SIZE 16
636
9e654916
RK		 637/* A C expression for the size in bits of the type `short' on the
638 target machine. If you don't define this, the default is half a
639 word. (If this would be less than one storage unit, it is
640 rounded up to one unit.) */
641#define SHORT_TYPE_SIZE 16
642
643/* A C expression for the size in bits of the type `int' on the
644 target machine. If you don't define this, the default is one
645 word. */
19d2d16f 646#define INT_TYPE_SIZE 32
9e654916
RK		 647
648/* A C expression for the size in bits of the type `long' on the
649 target machine. If you don't define this, the default is one
650 word. */
2f3e5814 651#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
9e654916
RK		 652
653/* A C expression for the size in bits of the type `long long' on the
654 target machine. If you don't define this, the default is two
655 words. */
656#define LONG_LONG_TYPE_SIZE 64
657
9e654916
RK		 658/* A C expression for the size in bits of the type `float' on the
659 target machine. If you don't define this, the default is one
660 word. */
661#define FLOAT_TYPE_SIZE 32
662
663/* A C expression for the size in bits of the type `double' on the
664 target machine. If you don't define this, the default is two
665 words. */
666#define DOUBLE_TYPE_SIZE 64
667
668/* A C expression for the size in bits of the type `long double' on
669 the target machine. If you don't define this, the default is two
670 words. */
6fa3f289 671#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
06f4e019 672
06f4e019
DE		 673/* Define this to set long double type size to use in libgcc2.c, which can
674 not depend on target_flags. */
675#ifdef __LONG_DOUBLE_128__
676#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
677#else
678#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
679#endif
9e654916 680
5b8f5865
DE		 681/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
682#define WIDEST_HARDWARE_FP_SIZE 64
683
f045b2c9
RS		 684/* Width in bits of a pointer.
685 See also the macro `Pmode' defined below. */
cacf1ca8
MM		 686extern unsigned rs6000_pointer_size;
687#define POINTER_SIZE rs6000_pointer_size
f045b2c9
RS		 688
689/* Allocation boundary (in *bits*) for storing arguments in argument list. */
2f3e5814 690#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
f045b2c9
RS		 691
692/* Boundary (in *bits*) on which stack pointer should be aligned. */
cacf1ca8
MM		 693#define STACK_BOUNDARY \
694 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
695 ? 64 : 128)
f045b2c9
RS		 696
697/* Allocation boundary (in *bits*) for the code of a function. */
698#define FUNCTION_BOUNDARY 32
699
700/* No data type wants to be aligned rounder than this. */
0ac081f6
AH		 701#define BIGGEST_ALIGNMENT 128
702
703/* A C expression to compute the alignment for a variables in the
704 local store. TYPE is the data type, and ALIGN is the alignment
705 that the object would ordinarily have. */
706#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
cacf1ca8
MM		 707 (((TARGET_ALTIVEC || TARGET_VSX) \
708 && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
4d4447b5 709 (TARGET_E500_DOUBLE \
cacf1ca8
MM		 710 && TYPE_MODE (TYPE) == DFmode) ? 64 : \
711 ((TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE \
96038623
DE		 712 && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) || (TARGET_PAIRED_FLOAT \
713 && TREE_CODE (TYPE) == VECTOR_TYPE \
714 && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) ? 64 : ALIGN)
b73fd26c 715
f045b2c9
RS		 716/* Alignment of field after `int : 0' in a structure. */
717#define EMPTY_FIELD_BOUNDARY 32
718
719/* Every structure's size must be a multiple of this. */
720#define STRUCTURE_SIZE_BOUNDARY 8
721
a3170dc6
AH		 722/* Return 1 if a structure or array containing FIELD should be
723 accessed using `BLKMODE'.
724
725 For the SPE, simd types are V2SI, and gcc can be tempted to put the
726 entire thing in a DI and use subregs to access the internals.
727 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
728 back-end. Because a single GPR can hold a V2SI, but not a DI, the
729 best thing to do is set structs to BLKmode and avoid Severe Tire
de334ef6
AH		 730 Damage.
731
732 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
733 fit into 1, whereas DI still needs two. */
a3170dc6 734#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
de334ef6 735 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
4f011e1e 736 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
a3170dc6 737
43a88a8c 738/* A bit-field declared as `int' forces `int' alignment for the struct. */
f045b2c9
RS		 739#define PCC_BITFIELD_TYPE_MATTERS 1
740
69ef87e2
AH		 741/* Make strings word-aligned so strcpy from constants will be faster.
742 Make vector constants quadword aligned. */
743#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
744 (TREE_CODE (EXP) == STRING_CST \
153fbec8 745 && (STRICT_ALIGNMENT || !optimize_size) \
69ef87e2
AH		 746 && (ALIGN) < BITS_PER_WORD \
747 ? BITS_PER_WORD \
748 : (ALIGN))
f045b2c9 749
0ac081f6 750/* Make arrays of chars word-aligned for the same reasons.
f82f556d
AH		 751 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
752 64 bits. */
f045b2c9 753#define DATA_ALIGNMENT(TYPE, ALIGN) \
96038623
DE		 754 (TREE_CODE (TYPE) == VECTOR_TYPE ? ((TARGET_SPE_ABI \
755 || TARGET_PAIRED_FLOAT) ? 64 : 128) \
4d4447b5 756 : (TARGET_E500_DOUBLE \
4f011e1e 757 && TYPE_MODE (TYPE) == DFmode) ? 64 \
0ac081f6 758 : TREE_CODE (TYPE) == ARRAY_TYPE \
f045b2c9
RS		 759 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
760 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
761
a0ab749a 762/* Nonzero if move instructions will actually fail to work
f045b2c9 763 when given unaligned data. */
fdaff8ba 764#define STRICT_ALIGNMENT 0
e1565e65
DE		 765
766/* Define this macro to be the value 1 if unaligned accesses have a cost
767 many times greater than aligned accesses, for example if they are
768 emulated in a trap handler. */
cacf1ca8
MM		 769/* Altivec vector memory instructions simply ignore the low bits; SPE vector
770 memory instructions trap on unaligned accesses; VSX memory instructions are
771 aligned to 4 or 8 bytes. */
41543739
GK		 772#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
773 (STRICT_ALIGNMENT \
fcce224d 774 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
e41b2a33 775 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \
fcce224d 776 || (MODE) == DImode) \
54ce9cc2 777 && (ALIGN) < 32) \
cacf1ca8
MM		 778 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))
779
f045b2c9
RS		 780\f
781/* Standard register usage. */
782
783/* Number of actual hardware registers.
784 The hardware registers are assigned numbers for the compiler
785 from 0 to just below FIRST_PSEUDO_REGISTER.
786 All registers that the compiler knows about must be given numbers,
787 even those that are not normally considered general registers.
788
789 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
790 an MQ register, a count register, a link register, and 8 condition
07488f32
ZW		 791 register fields, which we view here as separate registers. AltiVec
792 adds 32 vector registers and a VRsave register.
f045b2c9
RS		 793
794 In addition, the difference between the frame and argument pointers is
795 a function of the number of registers saved, so we need to have a
796 register for AP that will later be eliminated in favor of SP or FP.
802a0058 797 This is a normal register, but it is fixed.
f045b2c9 798
802a0058
MM		 799 We also create a pseudo register for float/int conversions, that will
800 really represent the memory location used. It is represented here as
801 a register, in order to work around problems in allocating stack storage
7d5175e1 802 in inline functions.
802a0058 803
7d5175e1
JJ		 804 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
805 pointer, which is eventually eliminated in favor of SP or FP. */
806
807#define FIRST_PSEUDO_REGISTER 114
f045b2c9 808
d6a7951f 809/* This must be included for pre gcc 3.0 glibc compatibility. */
7d5f33bc 810#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
62153b61 811
93c9d1ba 812/* Add 32 dwarf columns for synthetic SPE registers. */
7d5175e1 813#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
c19de7aa 814
93c9d1ba
AM		 815/* The SPE has an additional 32 synthetic registers, with DWARF debug
816 info numbering for these registers starting at 1200. While eh_frame
817 register numbering need not be the same as the debug info numbering,
818 we choose to number these regs for eh_frame at 1200 too. This allows
819 future versions of the rs6000 backend to add hard registers and
820 continue to use the gcc hard register numbering for eh_frame. If the
821 extra SPE registers in eh_frame were numbered starting from the
822 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
823 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
824 avoid invalidating older SPE eh_frame info.
825
826 We must map them here to avoid huge unwinder tables mostly consisting
f676971a 827 of unused space. */
93c9d1ba 828#define DWARF_REG_TO_UNWIND_COLUMN(r) \
7d5175e1 829 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
93c9d1ba 830
ed1cf8ff
GK		 831/* Use standard DWARF numbering for DWARF debugging information. */
832#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
833
93c9d1ba
AM		 834/* Use gcc hard register numbering for eh_frame. */
835#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
41f3a930 836
ed1cf8ff
GK		 837/* Map register numbers held in the call frame info that gcc has
838 collected using DWARF_FRAME_REGNUM to those that should be output in
839 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
840 for .eh_frame, but use the numbers mandated by the various ABIs for
841 .debug_frame. rs6000_emit_prologue has translated any combination of
842 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
843 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
844#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
845 ((FOR_EH) ? (REGNO) \
846 : (REGNO) == CR2_REGNO ? 64 \
847 : DBX_REGISTER_NUMBER (REGNO))
848
f045b2c9
RS		 849/* 1 for registers that have pervasive standard uses
850 and are not available for the register allocator.
851
5dead3e5
DJ		 852 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
853 as a local register; for all other OS's r2 is the TOC pointer.
f045b2c9 854
a127c4e5
RK		 855 cr5 is not supposed to be used.
856
857 On System V implementations, r13 is fixed and not available for use. */
858
f045b2c9 859#define FIXED_REGISTERS \
5dead3e5 860 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
f045b2c9
RS		 861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
863 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0ac081f6
AH		 864 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
865 /* AltiVec registers. */ \
866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
867 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 868 1, 1 \
7d5175e1 869 , 1, 1, 1 \
0ac081f6 870}
f045b2c9
RS		 871
872/* 1 for registers not available across function calls.
873 These must include the FIXED_REGISTERS and also any
874 registers that can be used without being saved.
875 The latter must include the registers where values are returned
876 and the register where structure-value addresses are passed.
877 Aside from that, you can include as many other registers as you like. */
878
879#define CALL_USED_REGISTERS \
a127c4e5 880 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
f045b2c9
RS		 881 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
882 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
883 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0ac081f6
AH		 884 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
885 /* AltiVec registers. */ \
886 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
887 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 888 1, 1 \
7d5175e1 889 , 1, 1, 1 \
0ac081f6
AH		 890}
891
289e96b2
AH		 892/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
893 the entire set of `FIXED_REGISTERS' be included.
894 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
895 This macro is optional. If not specified, it defaults to the value
896 of `CALL_USED_REGISTERS'. */
f676971a 897
289e96b2
AH		 898#define CALL_REALLY_USED_REGISTERS \
899 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
900 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
901 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
902 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
903 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
904 /* AltiVec registers. */ \
905 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
906 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 907 0, 0 \
7d5175e1 908 , 0, 0, 0 \
289e96b2 909}
f045b2c9 910
28bcfd4d 911#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
9ebbca7d 912
d62294f5
FJ		 913#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
914#define FIRST_SAVED_FP_REGNO (14+32)
915#define FIRST_SAVED_GP_REGNO 13
916
f045b2c9
RS		 917/* List the order in which to allocate registers. Each register must be
918 listed once, even those in FIXED_REGISTERS.
919
920 We allocate in the following order:
921 fp0 (not saved or used for anything)
922 fp13 - fp2 (not saved; incoming fp arg registers)
923 fp1 (not saved; return value)
9390387d 924 fp31 - fp14 (saved; order given to save least number)
5accd822
DE		 925 cr7, cr6 (not saved or special)
926 cr1 (not saved, but used for FP operations)
f045b2c9 927 cr0 (not saved, but used for arithmetic operations)
5accd822 928 cr4, cr3, cr2 (saved)
9390387d 929 r0 (not saved; cannot be base reg)
f045b2c9
RS		 930 r9 (not saved; best for TImode)
931 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
9390387d 932 r3 (not saved; return value register)
f045b2c9
RS		 933 r31 - r13 (saved; order given to save least number)
934 r12 (not saved; if used for DImode or DFmode would use r13)
935 mq (not saved; best to use it if we can)
936 ctr (not saved; when we have the choice ctr is better)
937 lr (saved)
9390387d
AM		 938 cr5, r1, r2, ap, xer (fixed)
939 v0 - v1 (not saved or used for anything)
940 v13 - v3 (not saved; incoming vector arg registers)
941 v2 (not saved; incoming vector arg reg; return value)
942 v19 - v14 (not saved or used for anything)
943 v31 - v20 (saved; order given to save least number)
944 vrsave, vscr (fixed)
a3170dc6 945 spe_acc, spefscr (fixed)
7d5175e1 946 sfp (fixed)
0ac081f6 947*/
f676971a 948
6b13641d
DJ		 949#if FIXED_R2 == 1
950#define MAYBE_R2_AVAILABLE
951#define MAYBE_R2_FIXED 2,
952#else
953#define MAYBE_R2_AVAILABLE 2,
954#define MAYBE_R2_FIXED
955#endif
f045b2c9 956
9390387d
AM		 957#define REG_ALLOC_ORDER \
958 {32, \
959 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
960 33, \
961 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
962 50, 49, 48, 47, 46, \
963 75, 74, 69, 68, 72, 71, 70, \
964 0, MAYBE_R2_AVAILABLE \
965 9, 11, 10, 8, 7, 6, 5, 4, \
966 3, \
967 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
968 18, 17, 16, 15, 14, 13, 12, \
969 64, 66, 65, \
970 73, 1, MAYBE_R2_FIXED 67, 76, \
971 /* AltiVec registers. */ \
972 77, 78, \
973 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
974 79, \
975 96, 95, 94, 93, 92, 91, \
976 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
977 109, 110, \
7d5175e1 978 111, 112, 113 \
0ac081f6 979}
f045b2c9
RS		 980
981/* True if register is floating-point. */
982#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
983
984/* True if register is a condition register. */
1de43f85 985#define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
f045b2c9 986
815cdc52 987/* True if register is a condition register, but not cr0. */
1de43f85 988#define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
815cdc52 989
f045b2c9 990/* True if register is an integer register. */
7d5175e1
JJ		 991#define INT_REGNO_P(N) \
992 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
f045b2c9 993
a3170dc6
AH		 994/* SPE SIMD registers are just the GPRs. */
995#define SPE_SIMD_REGNO_P(N) ((N) <= 31)
996
96038623
DE		 997/* PAIRED SIMD registers are just the FPRs. */
998#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
999
0d86f538 1000/* True if register is the XER register. */
9ebbca7d 1001#define XER_REGNO_P(N) ((N) == XER_REGNO)
802a0058 1002
0ac081f6
AH		 1003/* True if register is an AltiVec register. */
1004#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1005
cacf1ca8
MM		 1006/* True if register is a VSX register. */
1007#define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1008
1009/* Alternate name for any vector register supporting floating point, no matter
1010 which instruction set(s) are available. */
1011#define VFLOAT_REGNO_P(N) \
1012 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1013
1014/* Alternate name for any vector register supporting integer, no matter which
1015 instruction set(s) are available. */
1016#define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1017
1018/* Alternate name for any vector register supporting logical operations, no
1019 matter which instruction set(s) are available. */
1020#define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)
1021
f045b2c9 1022/* Return number of consecutive hard regs needed starting at reg REGNO
d8ecbcdb
AH		 1023 to hold something of mode MODE. */
1024
cacf1ca8 1025#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
0e67400a
FJ		 1026
1027#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1028 ((TARGET_32BIT && TARGET_POWERPC64 \
2e6c9641 1029 && (GET_MODE_SIZE (MODE) > 4) \
0e67400a 1030 && INT_REGNO_P (REGNO)) ? 1 : 0)
f045b2c9 1031
cacf1ca8
MM		 1032#define VSX_VECTOR_MODE(MODE) \
1033 ((MODE) == V4SFmode \
1034 || (MODE) == V2DFmode) \
1035
1036#define VSX_SCALAR_MODE(MODE) \
1037 ((MODE) == DFmode)
1038
1039#define VSX_MODE(MODE) \
1040 (VSX_VECTOR_MODE (MODE) \
1041 || VSX_SCALAR_MODE (MODE))
1042
1043#define VSX_MOVE_MODE(MODE) \
1044 (VSX_VECTOR_MODE (MODE) \
1045 || VSX_SCALAR_MODE (MODE) \
1046 || ALTIVEC_VECTOR_MODE (MODE) \
1047 || (MODE) == TImode)
1048
0ac081f6 1049#define ALTIVEC_VECTOR_MODE(MODE) \
cb2a532e
AH		 1050 ((MODE) == V16QImode \
1051 || (MODE) == V8HImode \
1052 || (MODE) == V4SFmode \
6e1f54e2 1053 || (MODE) == V4SImode)
0ac081f6 1054
a3170dc6
AH		 1055#define SPE_VECTOR_MODE(MODE) \
1056 ((MODE) == V4HImode \
1057 || (MODE) == V2SFmode \
00a892b8 1058 || (MODE) == V1DImode \
a3170dc6
AH		 1059 || (MODE) == V2SImode)
1060
96038623
DE		 1061#define PAIRED_VECTOR_MODE(MODE) \
1062 ((MODE) == V2SFmode)
1063
cacf1ca8
MM		 1064#define UNITS_PER_SIMD_WORD(MODE) \
1065 (TARGET_VSX ? UNITS_PER_VSX_WORD \
1066 : (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
1067 : (TARGET_SPE ? UNITS_PER_SPE_WORD \
1068 : (TARGET_PAIRED_FLOAT ? UNITS_PER_PAIRED_WORD \
1069 : UNITS_PER_WORD))))
0bf43309 1070
0d1fbc8c
AH		 1071/* Value is TRUE if hard register REGNO can hold a value of
1072 machine-mode MODE. */
1073#define HARD_REGNO_MODE_OK(REGNO, MODE) \
1074 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
f045b2c9
RS		 1075
1076/* Value is 1 if it is a good idea to tie two pseudo registers
1077 when one has mode MODE1 and one has mode MODE2.
1078 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1079 for any hard reg, then this must be 0 for correct output. */
1080#define MODES_TIEABLE_P(MODE1, MODE2) \
ebb109ad
BE		 1081 (SCALAR_FLOAT_MODE_P (MODE1) \
1082 ? SCALAR_FLOAT_MODE_P (MODE2) \
1083 : SCALAR_FLOAT_MODE_P (MODE2) \
1084 ? SCALAR_FLOAT_MODE_P (MODE1) \
f045b2c9
RS		 1085 : GET_MODE_CLASS (MODE1) == MODE_CC \
1086 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1087 : GET_MODE_CLASS (MODE2) == MODE_CC \
1088 ? GET_MODE_CLASS (MODE1) == MODE_CC \
4dcc01f3
AH		 1089 : SPE_VECTOR_MODE (MODE1) \
1090 ? SPE_VECTOR_MODE (MODE2) \
1091 : SPE_VECTOR_MODE (MODE2) \
1092 ? SPE_VECTOR_MODE (MODE1) \
0ac081f6
AH		 1093 : ALTIVEC_VECTOR_MODE (MODE1) \
1094 ? ALTIVEC_VECTOR_MODE (MODE2) \
1095 : ALTIVEC_VECTOR_MODE (MODE2) \
1096 ? ALTIVEC_VECTOR_MODE (MODE1) \
cacf1ca8
MM		 1097 : VSX_VECTOR_MODE (MODE1) \
1098 ? VSX_VECTOR_MODE (MODE2) \
1099 : VSX_VECTOR_MODE (MODE2) \
1100 ? VSX_VECTOR_MODE (MODE1) \
f045b2c9
RS		 1101 : 1)
1102
c8ae788f
SB		 1103/* Post-reload, we can't use any new AltiVec registers, as we already
1104 emitted the vrsave mask. */
1105
1106#define HARD_REGNO_RENAME_OK(SRC, DST) \
6fb5fa3c 1107 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
c8ae788f 1108
f045b2c9 1109/* A C expression returning the cost of moving data from a register of class
34bb030a 1110 CLASS1 to one of CLASS2. */
f045b2c9 1111
34bb030a 1112#define REGISTER_MOVE_COST rs6000_register_move_cost
f045b2c9 1113
34bb030a
DE		 1114/* A C expressions returning the cost of moving data of MODE from a register to
1115 or from memory. */
f045b2c9 1116
34bb030a 1117#define MEMORY_MOVE_COST rs6000_memory_move_cost
f045b2c9
RS		 1118
1119/* Specify the cost of a branch insn; roughly the number of extra insns that
1120 should be added to avoid a branch.
1121
ef457bda 1122 Set this to 3 on the RS/6000 since that is roughly the average cost of an
f045b2c9
RS		 1123 unscheduled conditional branch. */
1124
3a4fd356 1125#define BRANCH_COST(speed_p, predictable_p) 3
f045b2c9 1126
85e50b6b 1127/* Override BRANCH_COST heuristic which empirically produces worse
b8610a53 1128 performance for removing short circuiting from the logical ops. */
85e50b6b 1129
b8610a53 1130#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
a3170dc6 1131
52ff33d0
NF		 1132/* A fixed register used at epilogue generation to address SPE registers
1133 with negative offsets. The 64-bit load/store instructions on the SPE
1134 only take positive offsets (and small ones at that), so we need to
1135 reserve a register for consing up negative offsets. */
a3170dc6 1136
52ff33d0 1137#define FIXED_SCRATCH 0
a3170dc6 1138
2aa4498c
AH		 1139/* Define this macro to change register usage conditional on target
1140 flags. */
f85f4585 1141
2aa4498c 1142#define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
6febd581 1143
f045b2c9
RS		 1144/* Specify the registers used for certain standard purposes.
1145 The values of these macros are register numbers. */
1146
1147/* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1148/* #define PC_REGNUM */
1149
1150/* Register to use for pushing function arguments. */
1151#define STACK_POINTER_REGNUM 1
1152
1153/* Base register for access to local variables of the function. */
7d5175e1
JJ		 1154#define HARD_FRAME_POINTER_REGNUM 31
1155
1156/* Base register for access to local variables of the function. */
1157#define FRAME_POINTER_REGNUM 113
f045b2c9 1158
f045b2c9
RS		 1159/* Base register for access to arguments of the function. */
1160#define ARG_POINTER_REGNUM 67
1161
1162/* Place to put static chain when calling a function that requires it. */
1163#define STATIC_CHAIN_REGNUM 11
1164
f045b2c9
RS		 1165\f
1166/* Define the classes of registers for register constraints in the
1167 machine description. Also define ranges of constants.
1168
1169 One of the classes must always be named ALL_REGS and include all hard regs.
1170 If there is more than one class, another class must be named NO_REGS
1171 and contain no registers.
1172
1173 The name GENERAL_REGS must be the name of a class (or an alias for
1174 another name such as ALL_REGS). This is the class of registers
1175 that is allowed by "g" or "r" in a register constraint.
1176 Also, registers outside this class are allocated only when
1177 instructions express preferences for them.
1178
1179 The classes must be numbered in nondecreasing order; that is,
1180 a larger-numbered class must never be contained completely
1181 in a smaller-numbered class.
1182
1183 For any two classes, it is very desirable that there be another
1184 class that represents their union. */
c81bebd7 1185
cacf1ca8
MM		 1186/* The RS/6000 has three types of registers, fixed-point, floating-point, and
1187 condition registers, plus three special registers, MQ, CTR, and the link
1188 register. AltiVec adds a vector register class. VSX registers overlap the
1189 FPR registers and the Altivec registers.
f045b2c9
RS		 1190
1191 However, r0 is special in that it cannot be used as a base register.
1192 So make a class for registers valid as base registers.
1193
1194 Also, cr0 is the only condition code register that can be used in
0d86f538 1195 arithmetic insns, so make a separate class for it. */
f045b2c9 1196
ebedb4dd
MM		 1197enum reg_class
1198{
1199 NO_REGS,
ebedb4dd
MM		 1200 BASE_REGS,
1201 GENERAL_REGS,
1202 FLOAT_REGS,
0ac081f6
AH		 1203 ALTIVEC_REGS,
1204 VRSAVE_REGS,
5f004351 1205 VSCR_REGS,
a3170dc6
AH		 1206 SPE_ACC_REGS,
1207 SPEFSCR_REGS,
ebedb4dd
MM		 1208 NON_SPECIAL_REGS,
1209 MQ_REGS,
1210 LINK_REGS,
1211 CTR_REGS,
1212 LINK_OR_CTR_REGS,
1213 SPECIAL_REGS,
1214 SPEC_OR_GEN_REGS,
1215 CR0_REGS,
ebedb4dd
MM		 1216 CR_REGS,
1217 NON_FLOAT_REGS,
9ebbca7d 1218 XER_REGS,
ebedb4dd
MM		 1219 ALL_REGS,
1220 LIM_REG_CLASSES
1221};
f045b2c9
RS		 1222
1223#define N_REG_CLASSES (int) LIM_REG_CLASSES
1224
82e41834 1225/* Give names of register classes as strings for dump file. */
f045b2c9 1226
ebedb4dd
MM		 1227#define REG_CLASS_NAMES \
1228{ \
1229 "NO_REGS", \
ebedb4dd
MM		 1230 "BASE_REGS", \
1231 "GENERAL_REGS", \
1232 "FLOAT_REGS", \
0ac081f6
AH		 1233 "ALTIVEC_REGS", \
1234 "VRSAVE_REGS", \
5f004351 1235 "VSCR_REGS", \
a3170dc6
AH		 1236 "SPE_ACC_REGS", \
1237 "SPEFSCR_REGS", \
ebedb4dd
MM		 1238 "NON_SPECIAL_REGS", \
1239 "MQ_REGS", \
1240 "LINK_REGS", \
1241 "CTR_REGS", \
1242 "LINK_OR_CTR_REGS", \
1243 "SPECIAL_REGS", \
1244 "SPEC_OR_GEN_REGS", \
1245 "CR0_REGS", \
ebedb4dd
MM		 1246 "CR_REGS", \
1247 "NON_FLOAT_REGS", \
9ebbca7d 1248 "XER_REGS", \
ebedb4dd
MM		 1249 "ALL_REGS" \
1250}
f045b2c9
RS		 1251
1252/* Define which registers fit in which classes.
1253 This is an initializer for a vector of HARD_REG_SET
1254 of length N_REG_CLASSES. */
1255
0ac081f6
AH		 1256#define REG_CLASS_CONTENTS \
1257{ \
1258 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
7d5175e1
JJ		 1259 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1260 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
0ac081f6 1261 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
089a05b8
SS		 1262 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1263 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
5f004351 1264 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
a3170dc6
AH		 1265 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1266 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
7d5175e1 1267 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
0ac081f6
AH		 1268 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1269 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1270 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1271 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
a004eb82 1272 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
7d5175e1 1273 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
0ac081f6
AH		 1274 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1275 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
e3604432 1276 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
089a05b8 1277 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
7d5175e1 1278 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
ebedb4dd 1279}
f045b2c9 1280
058e97ec
VM		 1281/* The following macro defines cover classes for Integrated Register
1282 Allocator. Cover classes is a set of non-intersected register
1283 classes covering all hard registers used for register allocation
1284 purpose. Any move between two registers of a cover class should be
1285 cheaper than load or store of the registers. The macro value is
1286 array of register classes with LIM_REG_CLASSES used as the end
1287 marker. */
1288
1289#define IRA_COVER_CLASSES \
1290{ \
1291 GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, \
1292 /*VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
1293 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
1294 CR_REGS, XER_REGS, LIM_REG_CLASSES \
1295}
1296
f045b2c9
RS		 1297/* The same information, inverted:
1298 Return the class number of the smallest class containing
1299 reg number REGNO. This could be a conditional expression
1300 or could index an array. */
1301
cacf1ca8
MM		 1302extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1303
1304#if ENABLE_CHECKING
1305#define REGNO_REG_CLASS(REGNO) \
1306 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \
1307 rs6000_regno_regclass[(REGNO)])
1308
1309#else
1310#define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)]
1311#endif
1312
1313/* VSX register classes. */
1314extern enum reg_class rs6000_vector_reg_class[];
f045b2c9
RS		 1315
1316/* The class value for index registers, and the one for base regs. */
1317#define INDEX_REG_CLASS GENERAL_REGS
1318#define BASE_REG_CLASS BASE_REGS
1319
cacf1ca8
MM		 1320/* Return whether a given register class can hold VSX objects. */
1321#define VSX_REG_CLASS_P(CLASS) \
1322 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1323
f045b2c9
RS		 1324/* Given an rtx X being reloaded into a reg required to be
1325 in class CLASS, return the class of reg to actually use.
1326 In general this is just CLASS; but on some machines
c81bebd7 1327 in some cases it is preferable to use a more restrictive class.
f045b2c9
RS		 1328
1329 On the RS/6000, we have to return NO_REGS when we want to reload a
f676971a 1330 floating-point CONST_DOUBLE to force it to be copied to memory.
1e66d555
GK		 1331
1332 We also don't want to reload integer values into floating-point
1333 registers if we can at all help it. In fact, this can
37409796 1334 cause reload to die, if it tries to generate a reload of CTR
1e66d555
GK		 1335 into a FP register and discovers it doesn't have the memory location
1336 required.
1337
1338 ??? Would it be a good idea to have reload do the converse, that is
1339 try to reload floating modes into FP registers if possible?
1340 */
f045b2c9 1341
802a0058 1342#define PREFERRED_RELOAD_CLASS(X,CLASS) \
343f6bbf
DE		 1343 ((CONSTANT_P (X) \
1344 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
1345 ? NO_REGS \
1346 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1347 && (CLASS) == NON_SPECIAL_REGS) \
1348 ? GENERAL_REGS \
1349 : (CLASS))
c81bebd7 1350
f045b2c9
RS		 1351/* Return the register class of a scratch register needed to copy IN into
1352 or out of a register in CLASS in MODE. If it can be done directly,
1353 NO_REGS is returned. */
1354
1355#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
3c4774e0 1356 rs6000_secondary_reload_class (CLASS, MODE, IN)
f045b2c9 1357
0ac081f6 1358/* If we are copying between FP or AltiVec registers and anything
44cd321e
PS		 1359 else, we need a memory location. The exception is when we are
1360 targeting ppc64 and the move to/from fpr to gpr instructions
1361 are available.*/
1362
1363#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1364 ((CLASS1) != (CLASS2) && (((CLASS1) == FLOAT_REGS \
1365 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
c092b045
PB		 1366 || ((MODE != DFmode) \
1367 && (MODE != DDmode) \
1368 && (MODE != DImode)))) \
44cd321e
PS		 1369 || ((CLASS2) == FLOAT_REGS \
1370 && (!TARGET_MFPGPR || !TARGET_POWERPC64 \
c092b045
PB		 1371 || ((MODE != DFmode) \
1372 && (MODE != DDmode) \
1373 && (MODE != DImode)))) \
44cd321e 1374 || (CLASS1) == ALTIVEC_REGS \
0ac081f6 1375 || (CLASS2) == ALTIVEC_REGS))
7ea555a4 1376
e41b2a33
PB		 1377/* For cpus that cannot load/store SDmode values from the 64-bit
1378 FP registers without using a full 64-bit load/store, we need
1379 to allocate a full 64-bit stack slot for them. */
1380
1381#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1382 rs6000_secondary_memory_needed_rtx (MODE)
1383
f045b2c9
RS		 1384/* Return the maximum number of consecutive registers
1385 needed to represent mode MODE in a register of class CLASS.
1386
cacf1ca8
MM		 1387 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1388 a single reg is enough for two words, unless we have VSX, where the FP
1389 registers can hold 128 bits. */
1390#define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
580d3230 1391
ca0e79d9
AM		 1392/* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1393
1394#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1395 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1396 ? ((GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8 \
1397 || TARGET_IEEEQUAD) \
1398 && reg_classes_intersect_p (FLOAT_REGS, CLASS)) \
1399 : (((TARGET_E500_DOUBLE \
1400 && ((((TO) == DFmode) + ((FROM) == DFmode)) == 1 \
17caeff2 1401 || (((TO) == TFmode) + ((FROM) == TFmode)) == 1 \
4d4447b5
PB		 1402 || (((TO) == DDmode) + ((FROM) == DDmode)) == 1 \
1403 || (((TO) == TDmode) + ((FROM) == TDmode)) == 1 \
ca0e79d9
AM		 1404 || (((TO) == DImode) + ((FROM) == DImode)) == 1)) \
1405 || (TARGET_SPE \
1406 && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \
1407 && reg_classes_intersect_p (GENERAL_REGS, CLASS)))
02188693 1408
f045b2c9
RS		 1409/* Stack layout; function entry, exit and calling. */
1410
6b67933e
RK		 1411/* Enumeration to give which calling sequence to use. */
1412enum rs6000_abi {
1413 ABI_NONE,
1414 ABI_AIX, /* IBM's AIX */
b6c9286a 1415 ABI_V4, /* System V.4/eabi */
ee890fe2 1416 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
6b67933e
RK		 1417};
1418
b6c9286a
MM		 1419extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1420
f045b2c9
RS		 1421/* Define this if pushing a word on the stack
1422 makes the stack pointer a smaller address. */
1423#define STACK_GROWS_DOWNWARD
1424
327e5343
FJ		 1425/* Offsets recorded in opcodes are a multiple of this alignment factor. */
1426#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1427
a4d05547 1428/* Define this to nonzero if the nominal address of the stack frame
f045b2c9
RS		 1429 is at the high-address end of the local variables;
1430 that is, each additional local variable allocated
1431 goes at a more negative offset in the frame.
1432
1433 On the RS/6000, we grow upwards, from the area after the outgoing
1434 arguments. */
3aebbe5f 1435#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
f045b2c9 1436
4697a36c 1437/* Size of the outgoing register save area */
9ebbca7d 1438#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
ee890fe2 1439 || DEFAULT_ABI == ABI_DARWIN) \
9ebbca7d
GK		 1440 ? (TARGET_64BIT ? 64 : 32) \
1441 : 0)
4697a36c
MM		 1442
1443/* Size of the fixed area on the stack */
9ebbca7d 1444#define RS6000_SAVE_AREA \
50d440bc 1445 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
9ebbca7d 1446 << (TARGET_64BIT ? 1 : 0))
4697a36c 1447
97f6e72f
DE		 1448/* MEM representing address to save the TOC register */
1449#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1450 plus_constant (stack_pointer_rtx, \
1451 (TARGET_32BIT ? 20 : 40)))
b6c9286a 1452
4697a36c 1453/* Align an address */
ed33106f 1454#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
4697a36c 1455
f045b2c9
RS		 1456/* Offset within stack frame to start allocating local variables at.
1457 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1458 first local allocated. Otherwise, it is the offset to the BEGINNING
c81bebd7 1459 of the first local allocated.
f045b2c9
RS		 1460
1461 On the RS/6000, the frame pointer is the same as the stack pointer,
1462 except for dynamic allocations. So we start after the fixed area and
1463 outgoing parameter area. */
1464
802a0058 1465#define STARTING_FRAME_OFFSET \
7d5175e1
JJ		 1466 (FRAME_GROWS_DOWNWARD \
1467 ? 0 \
cacf1ca8
MM		 1468 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1469 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
7d5175e1 1470 + RS6000_SAVE_AREA))
802a0058
MM		 1471
1472/* Offset from the stack pointer register to an item dynamically
1473 allocated on the stack, e.g., by `alloca'.
1474
1475 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1476 length of the outgoing arguments. The default is correct for most
1477 machines. See `function.c' for details. */
1478#define STACK_DYNAMIC_OFFSET(FUNDECL) \
cacf1ca8
MM		 1479 (RS6000_ALIGN (crtl->outgoing_args_size, \
1480 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
802a0058 1481 + (STACK_POINTER_OFFSET))
f045b2c9
RS		 1482
1483/* If we generate an insn to push BYTES bytes,
1484 this says how many the stack pointer really advances by.
1485 On RS/6000, don't define this because there are no push insns. */
1486/* #define PUSH_ROUNDING(BYTES) */
1487
1488/* Offset of first parameter from the argument pointer register value.
1489 On the RS/6000, we define the argument pointer to the start of the fixed
1490 area. */
4697a36c 1491#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
f045b2c9 1492
62153b61
JM		 1493/* Offset from the argument pointer register value to the top of
1494 stack. This is different from FIRST_PARM_OFFSET because of the
1495 register save area. */
1496#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1497
f045b2c9
RS		 1498/* Define this if stack space is still allocated for a parameter passed
1499 in a register. The value is the number of bytes allocated to this
1500 area. */
4697a36c 1501#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
f045b2c9
RS		 1502
1503/* Define this if the above stack space is to be considered part of the
1504 space allocated by the caller. */
81464b2c 1505#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
f045b2c9
RS		 1506
1507/* This is the difference between the logical top of stack and the actual sp.
1508
82e41834 1509 For the RS/6000, sp points past the fixed area. */
4697a36c 1510#define STACK_POINTER_OFFSET RS6000_SAVE_AREA
f045b2c9
RS		 1511
1512/* Define this if the maximum size of all the outgoing args is to be
1513 accumulated and pushed during the prologue. The amount can be
38173d38 1514 found in the variable crtl->outgoing_args_size. */
f73ad30e 1515#define ACCUMULATE_OUTGOING_ARGS 1
f045b2c9
RS		 1516
1517/* Value is the number of bytes of arguments automatically
1518 popped when returning from a subroutine call.
8b109b37 1519 FUNDECL is the declaration node of the function (as a tree),
f045b2c9
RS		 1520 FUNTYPE is the data type of the function (as a tree),
1521 or for a library call it is an identifier node for the subroutine name.
1522 SIZE is the number of bytes of arguments passed on the stack. */
1523
8b109b37 1524#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
f045b2c9
RS		 1525
1526/* Define how to find the value returned by a function.
1527 VALTYPE is the data type of the value (as a tree).
1528 If the precise function being called is known, FUNC is its FUNCTION_DECL;
a6ebc39a
AH		 1529 otherwise, FUNC is 0. */
1530
1531#define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
f045b2c9
RS		 1532
1533/* Define how to find the value returned by a library function
1534 assuming the value has mode MODE. */
1535
ded9bf77 1536#define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
f045b2c9 1537
6fa3f289
ZW		 1538/* DRAFT_V4_STRUCT_RET defaults off. */
1539#define DRAFT_V4_STRUCT_RET 0
f607bc57 1540
bd5bd7ac 1541/* Let TARGET_RETURN_IN_MEMORY control what happens. */
f607bc57 1542#define DEFAULT_PCC_STRUCT_RETURN 0
f045b2c9 1543
a260abc9 1544/* Mode of stack savearea.
dfdfa60f
DE		 1545 FUNCTION is VOIDmode because calling convention maintains SP.
1546 BLOCK needs Pmode for SP.
a260abc9
DE		 1547 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1548#define STACK_SAVEAREA_MODE(LEVEL) \
dfdfa60f
DE		 1549 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1550 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
a260abc9 1551
4697a36c
MM		 1552/* Minimum and maximum general purpose registers used to hold arguments. */
1553#define GP_ARG_MIN_REG 3
1554#define GP_ARG_MAX_REG 10
1555#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1556
1557/* Minimum and maximum floating point registers used to hold arguments. */
1558#define FP_ARG_MIN_REG 33
7509c759
MM		 1559#define FP_ARG_AIX_MAX_REG 45
1560#define FP_ARG_V4_MAX_REG 40
9ebbca7d 1561#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
ee890fe2 1562 || DEFAULT_ABI == ABI_DARWIN) \
9ebbca7d 1563 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
4697a36c
MM		 1564#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1565
0ac081f6
AH		 1566/* Minimum and maximum AltiVec registers used to hold arguments. */
1567#define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1568#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1569#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1570
4697a36c
MM		 1571/* Return registers */
1572#define GP_ARG_RETURN GP_ARG_MIN_REG
1573#define FP_ARG_RETURN FP_ARG_MIN_REG
0ac081f6 1574#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
4697a36c 1575
7509c759 1576/* Flags for the call/call_value rtl operations set up by function_arg */
6a4cee5f 1577#define CALL_NORMAL 0x00000000 /* no special processing */
9ebbca7d 1578/* Bits in 0x00000001 are unused. */
6a4cee5f
MM		 1579#define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1580#define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1581#define CALL_LONG 0x00000008 /* always call indirect */
b9599e46 1582#define CALL_LIBCALL 0x00000010 /* libcall */
7509c759 1583
f57fe068
AM		 1584/* We don't have prologue and epilogue functions to save/restore
1585 everything for most ABIs. */
1586#define WORLD_SAVE_P(INFO) 0
1587
f045b2c9
RS		 1588/* 1 if N is a possible register number for a function value
1589 as seen by the caller.
1590
0ac081f6 1591 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
e87a88d3
AM		 1592#define FUNCTION_VALUE_REGNO_P(N) \
1593 ((N) == GP_ARG_RETURN \
b2df7d08 1594 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
44688022 1595 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
f045b2c9
RS		 1596
1597/* 1 if N is a possible register number for function argument passing.
0ac081f6
AH		 1598 On RS/6000, these are r3-r10 and fp1-fp13.
1599 On AltiVec, v2 - v13 are used for passing vectors. */
4697a36c 1600#define FUNCTION_ARG_REGNO_P(N) \
e87a88d3
AM		 1601 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1602 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
44688022 1603 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
e87a88d3 1604 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
b2df7d08 1605 && TARGET_HARD_FLOAT && TARGET_FPRS))
f045b2c9
RS		 1606\f
1607/* Define a data type for recording info about an argument list
1608 during the scan of that argument list. This data type should
1609 hold all necessary information about the function itself
1610 and about the args processed so far, enough to enable macros
1611 such as FUNCTION_ARG to determine where the next arg should go.
1612
1613 On the RS/6000, this is a structure. The first element is the number of
1614 total argument words, the second is used to store the next
1615 floating-point register number, and the third says how many more args we
4697a36c
MM		 1616 have prototype types for.
1617
4cc833b7 1618 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
07488f32 1619 the next available GP register, `fregno' is the next available FP
4cc833b7
RH		 1620 register, and `words' is the number of words used on the stack.
1621
bd227acc 1622 The varargs/stdarg support requires that this structure's size
4cc833b7 1623 be a multiple of sizeof(int). */
4697a36c
MM		 1624
1625typedef struct rs6000_args
1626{
4cc833b7 1627 int words; /* # words used for passing GP registers */
6a4cee5f 1628 int fregno; /* next available FP register */
0ac081f6 1629 int vregno; /* next available AltiVec register */
6a4cee5f 1630 int nargs_prototype; /* # args left in the current prototype */
6a4cee5f 1631 int prototype; /* Whether a prototype was defined */
a6c9bed4 1632 int stdarg; /* Whether function is a stdarg function. */
6a4cee5f 1633 int call_cookie; /* Do special things for this call */
4cc833b7 1634 int sysv_gregno; /* next available GP register */
0b5383eb
DJ		 1635 int intoffset; /* running offset in struct (darwin64) */
1636 int use_stack; /* any part of struct on stack (darwin64) */
1637 int named; /* false for varargs params */
4697a36c 1638} CUMULATIVE_ARGS;
f045b2c9 1639
f045b2c9
RS		 1640/* Initialize a variable CUM of type CUMULATIVE_ARGS
1641 for a call to a function whose data type is FNTYPE.
1642 For a library call, FNTYPE is 0. */
1643
0f6937fe
AM		 1644#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1645 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
f045b2c9
RS		 1646
1647/* Similar, but when scanning the definition of a procedure. We always
1648 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1649
0f6937fe
AM		 1650#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1651 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
b9599e46
FS		 1652
1653/* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1654
1655#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
0f6937fe 1656 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
f045b2c9
RS		 1657
1658/* Update the data in CUM to advance over an argument
1659 of mode MODE and data type TYPE.
1660 (TYPE is null for libcalls where that information may not be available.) */
1661
1662#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
594a51fe 1663 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
f045b2c9 1664
f045b2c9
RS		 1665/* Determine where to put an argument to a function.
1666 Value is zero to push the argument on the stack,
1667 or a hard register in which to store the argument.
1668
1669 MODE is the argument's machine mode.
1670 TYPE is the data type of the argument (as a tree).
1671 This is null for libcalls where that information may
1672 not be available.
1673 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1674 the preceding args and about the function being called.
1675 NAMED is nonzero if this argument is a named parameter
1676 (otherwise it is an extra parameter matching an ellipsis).
1677
1678 On RS/6000 the first eight words of non-FP are normally in registers
1679 and the rest are pushed. The first 13 FP args are in registers.
1680
1681 If this is floating-point and no prototype is specified, we use
4d6697ca
RK		 1682 both an FP and integer register (or possibly FP reg and stack). Library
1683 functions (when TYPE is zero) always have the proper types for args,
1684 so we can pass the FP value just in one register. emit_library_function
1685 doesn't support EXPR_LIST anyway. */
f045b2c9 1686
4697a36c
MM		 1687#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1688 function_arg (&CUM, MODE, TYPE, NAMED)
f045b2c9 1689
c229cba9
DE		 1690/* If defined, a C expression which determines whether, and in which
1691 direction, to pad out an argument with extra space. The value
1692 should be of type `enum direction': either `upward' to pad above
1693 the argument, `downward' to pad below, or `none' to inhibit
1694 padding. */
1695
9ebbca7d 1696#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
c229cba9 1697
b6c9286a 1698/* If defined, a C expression that gives the alignment boundary, in bits,
c81bebd7 1699 of an argument with the specified mode and type. If it is not defined,
b6c9286a
MM		 1700 PARM_BOUNDARY is used for all arguments. */
1701
1702#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1703 function_arg_boundary (MODE, TYPE)
1704
6e985040
AM		 1705#define PAD_VARARGS_DOWN \
1706 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
2a55fd42 1707
f045b2c9 1708/* Output assembler code to FILE to increment profiler label # LABELNO
58a39e45 1709 for profiling a function entry. */
f045b2c9
RS		 1710
1711#define FUNCTION_PROFILER(FILE, LABELNO) \
58a39e45 1712 output_function_profiler ((FILE), (LABELNO));
f045b2c9
RS		 1713
1714/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1715 the stack pointer does not matter. No definition is equivalent to
1716 always zero.
1717
a0ab749a 1718 On the RS/6000, this is nonzero because we can restore the stack from
f045b2c9
RS		 1719 its backpointer, which we maintain. */
1720#define EXIT_IGNORE_STACK 1
1721
a701949a
FS		 1722/* Define this macro as a C expression that is nonzero for registers
1723 that are used by the epilogue or the return' pattern. The stack
1724 and frame pointer registers are already be assumed to be used as
1725 needed. */
1726
83720594 1727#define EPILOGUE_USES(REGNO) \
1de43f85 1728 ((reload_completed && (REGNO) == LR_REGNO) \
b1765bde 1729 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
cacf1ca8 1730 || (crtl->calls_eh_return \
3553b09d 1731 && TARGET_AIX \
ff3867ae 1732 && (REGNO) == 2))
2bfcf297 1733
f045b2c9 1734\f
eaf1bcf1 1735/* TRAMPOLINE_TEMPLATE deleted */
f045b2c9
RS		 1736
1737/* Length in units of the trampoline for entering a nested function. */
1738
b6c9286a 1739#define TRAMPOLINE_SIZE rs6000_trampoline_size ()
f045b2c9
RS		 1740
1741/* Emit RTL insns to initialize the variable parts of a trampoline.
1742 FNADDR is an RTX for the address of the function's pure code.
1743 CXT is an RTX for the static chain value for the function. */
1744
1745#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
b6c9286a 1746 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
f045b2c9 1747\f
f33985c6
MS		 1748/* Definitions for __builtin_return_address and __builtin_frame_address.
1749 __builtin_return_address (0) should give link register (65), enable
82e41834 1750 this. */
f33985c6
MS		 1751/* This should be uncommented, so that the link register is used, but
1752 currently this would result in unmatched insns and spilling fixed
1753 registers so we'll leave it for another day. When these problems are
1754 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1755 (mrs) */
1756/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
f09d4c33 1757
b6c9286a
MM		 1758/* Number of bytes into the frame return addresses can be found. See
1759 rs6000_stack_info in rs6000.c for more information on how the different
1760 abi's store the return address. */
1761#define RETURN_ADDRESS_OFFSET \
1762 ((DEFAULT_ABI == ABI_AIX \
50d440bc 1763 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
3b370352 1764 (DEFAULT_ABI == ABI_V4) ? 4 : \
c4636dd1 1765 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
f09d4c33 1766
f33985c6
MS		 1767/* The current return address is in link register (65). The return address
1768 of anything farther back is accessed normally at an offset of 8 from the
1769 frame pointer. */
71f123ca
FS		 1770#define RETURN_ADDR_RTX(COUNT, FRAME) \
1771 (rs6000_return_addr (COUNT, FRAME))
1772
f33985c6 1773\f
f045b2c9
RS		 1774/* Definitions for register eliminations.
1775
1776 We have two registers that can be eliminated on the RS/6000. First, the
1777 frame pointer register can often be eliminated in favor of the stack
1778 pointer register. Secondly, the argument pointer register can always be
642a35f1
JW		 1779 eliminated; it is replaced with either the stack or frame pointer.
1780
1781 In addition, we use the elimination mechanism to see if r30 is needed
1782 Initially we assume that it isn't. If it is, we spill it. This is done
1783 by making it an eliminable register. We replace it with itself so that
1784 if it isn't needed, then existing uses won't be modified. */
f045b2c9
RS		 1785
1786/* This is an array of structures. Each structure initializes one pair
1787 of eliminable registers. The "from" register number is given first,
1788 followed by "to". Eliminations of the same "from" register are listed
1789 in order of preference. */
7d5175e1
JJ		 1790#define ELIMINABLE_REGS \
1791{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1792 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1793 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1794 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1795 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
97b23853 1796 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
f045b2c9
RS		 1797
1798/* Given FROM and TO register numbers, say whether this elimination is allowed.
1799 Frame pointer elimination is automatically handled.
1800
1801 For the RS/6000, if frame pointer elimination is being done, we would like
642a35f1
JW		 1802 to convert ap into fp, not sp.
1803
abc95ed3 1804 We need r30 if -mminimal-toc was specified, and there are constant pool
642a35f1 1805 references. */
f045b2c9 1806
97b23853
GK		 1807#define CAN_ELIMINATE(FROM, TO) \
1808 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1809 ? ! frame_pointer_needed \
1810 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1811 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
f045b2c9
RS		 1812 : 1)
1813
1814/* Define the offset between two registers, one to be eliminated, and the other
1815 its replacement, at the start of a routine. */
d1d0c603
JJ		 1816#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1817 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
f045b2c9
RS		 1818\f
1819/* Addressing modes, and classification of registers for them. */
1820
940da324
JL		 1821#define HAVE_PRE_DECREMENT 1
1822#define HAVE_PRE_INCREMENT 1
6fb5fa3c
DB		 1823#define HAVE_PRE_MODIFY_DISP 1
1824#define HAVE_PRE_MODIFY_REG 1
f045b2c9
RS		 1825
1826/* Macros to check register numbers against specific register classes. */
1827
1828/* These assume that REGNO is a hard or pseudo reg number.
1829 They give nonzero only if REGNO is a hard reg of the suitable class
1830 or a pseudo reg currently allocated to a suitable hard reg.
1831 Since they use reg_renumber, they are safe only once reg_renumber
1832 has been allocated, which happens in local-alloc.c. */
1833
1834#define REGNO_OK_FOR_INDEX_P(REGNO) \
1835((REGNO) < FIRST_PSEUDO_REGISTER \
1836 ? (REGNO) <= 31 || (REGNO) == 67 \
7d5175e1 1837 || (REGNO) == FRAME_POINTER_REGNUM \
f045b2c9 1838 : (reg_renumber[REGNO] >= 0 \
7d5175e1
JJ		 1839 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1840 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
f045b2c9
RS		 1841
1842#define REGNO_OK_FOR_BASE_P(REGNO) \
1843((REGNO) < FIRST_PSEUDO_REGISTER \
1844 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
7d5175e1 1845 || (REGNO) == FRAME_POINTER_REGNUM \
f045b2c9 1846 : (reg_renumber[REGNO] > 0 \
7d5175e1
JJ		 1847 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1848 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
c6c3dba9
PB		 1849
1850/* Nonzero if X is a hard reg that can be used as an index
1851 or if it is a pseudo reg in the non-strict case. */
1852#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1853 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1854 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1855
1856/* Nonzero if X is a hard reg that can be used as a base reg
1857 or if it is a pseudo reg in the non-strict case. */
1858#define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1859 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1860 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1861
f045b2c9
RS		 1862\f
1863/* Maximum number of registers that can appear in a valid memory address. */
1864
1865#define MAX_REGS_PER_ADDRESS 2
1866
1867/* Recognize any constant value that is a valid address. */
1868
6eff269e
BK		 1869#define CONSTANT_ADDRESS_P(X) \
1870 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1871 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1872 || GET_CODE (X) == HIGH)
f045b2c9
RS		 1873
1874/* Nonzero if the constant value X is a legitimate general operand.
1875 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1876
1877 On the RS/6000, all integer constants are acceptable, most won't be valid
1878 for particular insns, though. Only easy FP constants are
1879 acceptable. */
1880
1881#define LEGITIMATE_CONSTANT_P(X) \
49a2166f
AH		 1882 (((GET_CODE (X) != CONST_DOUBLE \
1883 && GET_CODE (X) != CONST_VECTOR) \
1884 || GET_MODE (X) == VOIDmode \
c4501e62 1885 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
49a2166f
AH		 1886 || easy_fp_constant (X, GET_MODE (X)) \
1887 || easy_vector_constant (X, GET_MODE (X))) \
c4501e62 1888 && !rs6000_tls_referenced_p (X))
f045b2c9 1889
48d72335 1890#define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
66180ff3 1891#define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
76492753
PB		 1892 && EASY_VECTOR_15((n) >> 1) \
1893 && ((n) & 1) == 0)
48d72335 1894
f045b2c9 1895\f
a260abc9
DE		 1896/* Try a machine-dependent way of reloading an illegitimate address
1897 operand. If we find one, push the reload and jump to WIN. This
1898 macro is used in only one place: `find_reloads_address' in reload.c.
1899
f676971a 1900 Implemented on rs6000 by rs6000_legitimize_reload_address.
24ea750e 1901 Note that (X) is evaluated twice; this is safe in current usage. */
f676971a 1902
a9098fd0
GK		 1903#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1904do { \
24ea750e
DJ		 1905 int win; \
1906 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
1907 (int)(TYPE), (IND_LEVELS), &win); \
1908 if ( win ) \
1909 goto WIN; \
a260abc9
DE		 1910} while (0)
1911
f045b2c9 1912/* Go to LABEL if ADDR (a legitimate address expression)
4d588c14 1913 has an effect that depends on the machine mode it is used for. */
f045b2c9
RS		 1914
1915#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
4d588c14
RH		 1916do { \
1917 if (rs6000_mode_dependent_address (ADDR)) \
f045b2c9 1918 goto LABEL; \
4d588c14 1919} while (0)
944258eb
RS		 1920
1921#define FIND_BASE_TERM rs6000_find_base_term
766a866c
MM		 1922\f
1923/* The register number of the register used to address a table of
1924 static data addresses in memory. In some cases this register is
1925 defined by a processor's "application binary interface" (ABI).
1926 When this macro is defined, RTL is generated for this register
1927 once, as with the stack pointer and frame pointer registers. If
1928 this macro is not defined, it is up to the machine-dependent files
1929 to allocate such a register (if necessary). */
1930
1db02437
FS		 1931#define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1932#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
766a866c 1933
97b23853 1934#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
9ebbca7d 1935
766a866c
MM		 1936/* Define this macro if the register defined by
1937 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
089a05b8 1938 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
766a866c
MM		 1939
1940/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1941
766a866c
MM		 1942/* A C expression that is nonzero if X is a legitimate immediate
1943 operand on the target machine when generating position independent
1944 code. You can assume that X satisfies `CONSTANT_P', so you need
1945 not check this. You can also assume FLAG_PIC is true, so you need
1946 not check it either. You need not define this macro if all
1947 constants (including `SYMBOL_REF') can be immediate operands when
1948 generating position independent code. */
1949
1950/* #define LEGITIMATE_PIC_OPERAND_P (X) */
f045b2c9
RS		 1951\f
1952/* Define this if some processing needs to be done immediately before
4255474b 1953 emitting code for an insn. */
f045b2c9 1954
c921bad8
AP		 1955#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
1956 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
f045b2c9
RS		 1957
1958/* Specify the machine mode that this machine uses
1959 for the index in the tablejump instruction. */
e1565e65 1960#define CASE_VECTOR_MODE SImode
f045b2c9 1961
18543a22
ILT		 1962/* Define as C expression which evaluates to nonzero if the tablejump
1963 instruction expects the table to contain offsets from the address of the
1964 table.
82e41834 1965 Do not define this if the table should contain absolute addresses. */
18543a22 1966#define CASE_VECTOR_PC_RELATIVE 1
f045b2c9 1967
f045b2c9
RS		 1968/* Define this as 1 if `char' should by default be signed; else as 0. */
1969#define DEFAULT_SIGNED_CHAR 0
1970
1971/* This flag, if defined, says the same insns that convert to a signed fixnum
1972 also convert validly to an unsigned one. */
1973
1974/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1975
c1618c0c
DE		 1976/* An integer expression for the size in bits of the largest integer machine
1977 mode that should actually be used. */
1978
1979/* Allow pairs of registers to be used, which is the intent of the default. */
1980#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1981
f045b2c9
RS		 1982/* Max number of bytes we can move from memory to memory
1983 in one reasonably fast instruction. */
2f3e5814 1984#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
7e69e155 1985#define MAX_MOVE_MAX 8
f045b2c9
RS		 1986
1987/* Nonzero if access to memory by bytes is no faster than for words.
a0ab749a 1988 Also nonzero if doing byte operations (specifically shifts) in registers
f045b2c9
RS		 1989 is undesirable. */
1990#define SLOW_BYTE_ACCESS 1
1991
9a63901f
RK		 1992/* Define if operations between registers always perform the operation
1993 on the full register even if a narrower mode is specified. */
1994#define WORD_REGISTER_OPERATIONS
1995
1996/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1997 will either zero-extend or sign-extend. The value of this macro should
1998 be the code that says which one of the two operations is implicitly
f822d252 1999 done, UNKNOWN if none. */
9a63901f 2000#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
225211e2
RK		 2001
2002/* Define if loading short immediate values into registers sign extends. */
2003#define SHORT_IMMEDIATES_SIGN_EXTEND
fdaff8ba 2004\f
f045b2c9
RS		 2005/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2006 is done just by pretending it is already truncated. */
2007#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2008
94993909 2009/* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
d865b122 2010#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
14670a74 2011 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
d865b122 2012
94993909 2013/* The CTZ patterns return -1 for input of zero. */
14670a74 2014#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
94993909 2015
f045b2c9
RS		 2016/* Specify the machine mode that pointers have.
2017 After generation of rtl, the compiler makes no further distinction
2018 between pointers and any other objects of this machine mode. */
cacf1ca8
MM		 2019extern unsigned rs6000_pmode;
2020#define Pmode ((enum machine_mode)rs6000_pmode)
f045b2c9 2021
a3c9585f 2022/* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
4c81e946
FJ		 2023#define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2024
f045b2c9 2025/* Mode of a function address in a call instruction (for indexing purposes).
f045b2c9 2026 Doesn't matter on RS/6000. */
5b71a4e7 2027#define FUNCTION_MODE SImode
f045b2c9
RS		 2028
2029/* Define this if addresses of constant functions
2030 shouldn't be put through pseudo regs where they can be cse'd.
2031 Desirable on machines where ordinary constants are expensive
2032 but a CALL with constant address is cheap. */
2033#define NO_FUNCTION_CSE
2034
d969caf8 2035/* Define this to be nonzero if shift instructions ignore all but the low-order
6febd581
RK		 2036 few bits.
2037
2038 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2039 have been dropped from the PowerPC architecture. */
2040
4697a36c 2041#define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
f045b2c9 2042
f045b2c9
RS		 2043/* Adjust the length of an INSN. LENGTH is the currently-computed length and
2044 should be adjusted to reflect any required changes. This macro is used when
2045 there is some systematic length adjustment required that would be difficult
2046 to express in the length attribute. */
2047
2048/* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2049
39a10a29
GK		 2050/* Given a comparison code (EQ, NE, etc.) and the first operand of a
2051 COMPARE, return the mode to be used for the comparison. For
2052 floating-point, CCFPmode should be used. CCUNSmode should be used
2053 for unsigned comparisons. CCEQmode should be used when we are
2054 doing an inequality comparison on the result of a
2055 comparison. CCmode should be used in all other cases. */
c5defebb 2056
b565a316 2057#define SELECT_CC_MODE(OP,X,Y) \
ebb109ad 2058 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
c5defebb 2059 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
ec8e098d 2060 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
c5defebb 2061 ? CCEQmode : CCmode))
f045b2c9 2062
b39358e1
GK		 2063/* Can the condition code MODE be safely reversed? This is safe in
2064 all cases on this port, because at present it doesn't use the
2065 trapping FP comparisons (fcmpo). */
2066#define REVERSIBLE_CC_MODE(MODE) 1
2067
2068/* Given a condition code and a mode, return the inverse condition. */
2069#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2070
f045b2c9
RS		 2071\f
2072/* Control the assembler format that we output. */
2073
1b279f39
DE		 2074/* A C string constant describing how to begin a comment in the target
2075 assembler language. The compiler assumes that the comment will end at
2076 the end of the line. */
2077#define ASM_COMMENT_START " #"
6b67933e 2078
38c1f2d7
MM		 2079/* Flag to say the TOC is initialized */
2080extern int toc_initialized;
2081
f045b2c9
RS		 2082/* Macro to output a special constant pool entry. Go to WIN if we output
2083 it. Otherwise, it is written the usual way.
2084
2085 On the RS/6000, toc entries are handled this way. */
2086
a9098fd0
GK		 2087#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2088{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2089 { \
2090 output_toc (FILE, X, LABELNO, MODE); \
2091 goto WIN; \
2092 } \
f045b2c9
RS		 2093}
2094
ebd97b96
DE		 2095#ifdef HAVE_GAS_WEAK
2096#define RS6000_WEAK 1
2097#else
2098#define RS6000_WEAK 0
2099#endif
290ad355 2100
79c4e63f
AM		 2101#if RS6000_WEAK
2102/* Used in lieu of ASM_WEAKEN_LABEL. */
2103#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2104 do \
2105 { \
2106 fputs ("\t.weak\t", (FILE)); \
85b776df 2107 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f 2108 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 2109 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f 2110 { \
cbaaba19
DE		 2111 if (TARGET_XCOFF) \
2112 fputs ("[DS]", (FILE)); \
ca734b39 2113 fputs ("\n\t.weak\t.", (FILE)); \
cbaaba19 2114 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f
AM		 2115 } \
2116 fputc ('\n', (FILE)); \
2117 if (VAL) \
2118 { \
2119 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2120 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 2121 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f
AM		 2122 { \
2123 fputs ("\t.set\t.", (FILE)); \
cbaaba19 2124 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f 2125 fputs (",.", (FILE)); \
cbaaba19 2126 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
79c4e63f
AM		 2127 fputc ('\n', (FILE)); \
2128 } \
2129 } \
2130 } \
2131 while (0)
2132#endif
2133
ff2d10c1
AO		 2134#if HAVE_GAS_WEAKREF
2135#define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2136 do \
2137 { \
2138 fputs ("\t.weakref\t", (FILE)); \
2139 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2140 fputs (", ", (FILE)); \
2141 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2142 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2143 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2144 { \
2145 fputs ("\n\t.weakref\t.", (FILE)); \
2146 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2147 fputs (", .", (FILE)); \
2148 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2149 } \
2150 fputc ('\n', (FILE)); \
2151 } while (0)
2152#endif
2153
79c4e63f
AM		 2154/* This implements the `alias' attribute. */
2155#undef ASM_OUTPUT_DEF_FROM_DECLS
2156#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2157 do \
2158 { \
2159 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2160 const char *name = IDENTIFIER_POINTER (TARGET); \
2161 if (TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 2162 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f
AM		 2163 { \
2164 if (TREE_PUBLIC (DECL)) \
2165 { \
2166 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2167 { \
2168 fputs ("\t.globl\t.", FILE); \
cbaaba19 2169 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f
AM		 2170 putc ('\n', FILE); \
2171 } \
2172 } \
2173 else if (TARGET_XCOFF) \
2174 { \
2175 fputs ("\t.lglobl\t.", FILE); \
cbaaba19 2176 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f
AM		 2177 putc ('\n', FILE); \
2178 } \
2179 fputs ("\t.set\t.", FILE); \
cbaaba19 2180 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f 2181 fputs (",.", FILE); \
cbaaba19 2182 RS6000_OUTPUT_BASENAME (FILE, name); \
79c4e63f
AM		 2183 fputc ('\n', FILE); \
2184 } \
2185 ASM_OUTPUT_DEF (FILE, alias, name); \
2186 } \
2187 while (0)
290ad355 2188
1bc7c5b6
ZW		 2189#define TARGET_ASM_FILE_START rs6000_file_start
2190
f045b2c9
RS		 2191/* Output to assembler file text saying following lines
2192 may contain character constants, extra white space, comments, etc. */
2193
2194#define ASM_APP_ON ""
2195
2196/* Output to assembler file text saying following lines
2197 no longer contain unusual constructs. */
2198
2199#define ASM_APP_OFF ""
2200
f045b2c9
RS		 2201/* How to refer to registers in assembler output.
2202 This sequence is indexed by compiler's hard-register-number (see above). */
2203
82e41834 2204extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
c81bebd7
MM		 2205
2206#define REGISTER_NAMES \
2207{ \
2208 &rs6000_reg_names[ 0][0], /* r0 */ \
2209 &rs6000_reg_names[ 1][0], /* r1 */ \
2210 &rs6000_reg_names[ 2][0], /* r2 */ \
2211 &rs6000_reg_names[ 3][0], /* r3 */ \
2212 &rs6000_reg_names[ 4][0], /* r4 */ \
2213 &rs6000_reg_names[ 5][0], /* r5 */ \
2214 &rs6000_reg_names[ 6][0], /* r6 */ \
2215 &rs6000_reg_names[ 7][0], /* r7 */ \
2216 &rs6000_reg_names[ 8][0], /* r8 */ \
2217 &rs6000_reg_names[ 9][0], /* r9 */ \
2218 &rs6000_reg_names[10][0], /* r10 */ \
2219 &rs6000_reg_names[11][0], /* r11 */ \
2220 &rs6000_reg_names[12][0], /* r12 */ \
2221 &rs6000_reg_names[13][0], /* r13 */ \
2222 &rs6000_reg_names[14][0], /* r14 */ \
2223 &rs6000_reg_names[15][0], /* r15 */ \
2224 &rs6000_reg_names[16][0], /* r16 */ \
2225 &rs6000_reg_names[17][0], /* r17 */ \
2226 &rs6000_reg_names[18][0], /* r18 */ \
2227 &rs6000_reg_names[19][0], /* r19 */ \
2228 &rs6000_reg_names[20][0], /* r20 */ \
2229 &rs6000_reg_names[21][0], /* r21 */ \
2230 &rs6000_reg_names[22][0], /* r22 */ \
2231 &rs6000_reg_names[23][0], /* r23 */ \
2232 &rs6000_reg_names[24][0], /* r24 */ \
2233 &rs6000_reg_names[25][0], /* r25 */ \
2234 &rs6000_reg_names[26][0], /* r26 */ \
2235 &rs6000_reg_names[27][0], /* r27 */ \
2236 &rs6000_reg_names[28][0], /* r28 */ \
2237 &rs6000_reg_names[29][0], /* r29 */ \
2238 &rs6000_reg_names[30][0], /* r30 */ \
2239 &rs6000_reg_names[31][0], /* r31 */ \
2240 \
2241 &rs6000_reg_names[32][0], /* fr0 */ \
2242 &rs6000_reg_names[33][0], /* fr1 */ \
2243 &rs6000_reg_names[34][0], /* fr2 */ \
2244 &rs6000_reg_names[35][0], /* fr3 */ \
2245 &rs6000_reg_names[36][0], /* fr4 */ \
2246 &rs6000_reg_names[37][0], /* fr5 */ \
2247 &rs6000_reg_names[38][0], /* fr6 */ \
2248 &rs6000_reg_names[39][0], /* fr7 */ \
2249 &rs6000_reg_names[40][0], /* fr8 */ \
2250 &rs6000_reg_names[41][0], /* fr9 */ \
2251 &rs6000_reg_names[42][0], /* fr10 */ \
2252 &rs6000_reg_names[43][0], /* fr11 */ \
2253 &rs6000_reg_names[44][0], /* fr12 */ \
2254 &rs6000_reg_names[45][0], /* fr13 */ \
2255 &rs6000_reg_names[46][0], /* fr14 */ \
2256 &rs6000_reg_names[47][0], /* fr15 */ \
2257 &rs6000_reg_names[48][0], /* fr16 */ \
2258 &rs6000_reg_names[49][0], /* fr17 */ \
2259 &rs6000_reg_names[50][0], /* fr18 */ \
2260 &rs6000_reg_names[51][0], /* fr19 */ \
2261 &rs6000_reg_names[52][0], /* fr20 */ \
2262 &rs6000_reg_names[53][0], /* fr21 */ \
2263 &rs6000_reg_names[54][0], /* fr22 */ \
2264 &rs6000_reg_names[55][0], /* fr23 */ \
2265 &rs6000_reg_names[56][0], /* fr24 */ \
2266 &rs6000_reg_names[57][0], /* fr25 */ \
2267 &rs6000_reg_names[58][0], /* fr26 */ \
2268 &rs6000_reg_names[59][0], /* fr27 */ \
2269 &rs6000_reg_names[60][0], /* fr28 */ \
2270 &rs6000_reg_names[61][0], /* fr29 */ \
2271 &rs6000_reg_names[62][0], /* fr30 */ \
2272 &rs6000_reg_names[63][0], /* fr31 */ \
2273 \
2274 &rs6000_reg_names[64][0], /* mq */ \
2275 &rs6000_reg_names[65][0], /* lr */ \
2276 &rs6000_reg_names[66][0], /* ctr */ \
2277 &rs6000_reg_names[67][0], /* ap */ \
2278 \
2279 &rs6000_reg_names[68][0], /* cr0 */ \
2280 &rs6000_reg_names[69][0], /* cr1 */ \
2281 &rs6000_reg_names[70][0], /* cr2 */ \
2282 &rs6000_reg_names[71][0], /* cr3 */ \
2283 &rs6000_reg_names[72][0], /* cr4 */ \
2284 &rs6000_reg_names[73][0], /* cr5 */ \
2285 &rs6000_reg_names[74][0], /* cr6 */ \
2286 &rs6000_reg_names[75][0], /* cr7 */ \
802a0058 2287 \
9ebbca7d 2288 &rs6000_reg_names[76][0], /* xer */ \
0ac081f6
AH		 2289 \
2290 &rs6000_reg_names[77][0], /* v0 */ \
2291 &rs6000_reg_names[78][0], /* v1 */ \
2292 &rs6000_reg_names[79][0], /* v2 */ \
2293 &rs6000_reg_names[80][0], /* v3 */ \
2294 &rs6000_reg_names[81][0], /* v4 */ \
2295 &rs6000_reg_names[82][0], /* v5 */ \
2296 &rs6000_reg_names[83][0], /* v6 */ \
2297 &rs6000_reg_names[84][0], /* v7 */ \
2298 &rs6000_reg_names[85][0], /* v8 */ \
2299 &rs6000_reg_names[86][0], /* v9 */ \
2300 &rs6000_reg_names[87][0], /* v10 */ \
2301 &rs6000_reg_names[88][0], /* v11 */ \
2302 &rs6000_reg_names[89][0], /* v12 */ \
2303 &rs6000_reg_names[90][0], /* v13 */ \
2304 &rs6000_reg_names[91][0], /* v14 */ \
2305 &rs6000_reg_names[92][0], /* v15 */ \
2306 &rs6000_reg_names[93][0], /* v16 */ \
2307 &rs6000_reg_names[94][0], /* v17 */ \
2308 &rs6000_reg_names[95][0], /* v18 */ \
2309 &rs6000_reg_names[96][0], /* v19 */ \
2310 &rs6000_reg_names[97][0], /* v20 */ \
2311 &rs6000_reg_names[98][0], /* v21 */ \
2312 &rs6000_reg_names[99][0], /* v22 */ \
2313 &rs6000_reg_names[100][0], /* v23 */ \
2314 &rs6000_reg_names[101][0], /* v24 */ \
2315 &rs6000_reg_names[102][0], /* v25 */ \
2316 &rs6000_reg_names[103][0], /* v26 */ \
2317 &rs6000_reg_names[104][0], /* v27 */ \
2318 &rs6000_reg_names[105][0], /* v28 */ \
2319 &rs6000_reg_names[106][0], /* v29 */ \
2320 &rs6000_reg_names[107][0], /* v30 */ \
2321 &rs6000_reg_names[108][0], /* v31 */ \
2322 &rs6000_reg_names[109][0], /* vrsave */ \
5f004351 2323 &rs6000_reg_names[110][0], /* vscr */ \
a3170dc6
AH		 2324 &rs6000_reg_names[111][0], /* spe_acc */ \
2325 &rs6000_reg_names[112][0], /* spefscr */ \
7d5175e1 2326 &rs6000_reg_names[113][0], /* sfp */ \
c81bebd7
MM		 2327}
2328
f045b2c9
RS		 2329/* Table of additional register names to use in user input. */
2330
2331#define ADDITIONAL_REGISTER_NAMES \
c4d38ccb
MM		 2332 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2333 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2334 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2335 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2336 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2337 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2338 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2339 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2340 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2341 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2342 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2343 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2344 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2345 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2346 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2347 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
0ac081f6
AH		 2348 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2349 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2350 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2351 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2352 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2353 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2354 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2355 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
5f004351 2356 {"vrsave", 109}, {"vscr", 110}, \
a3170dc6 2357 {"spe_acc", 111}, {"spefscr", 112}, \
c4d38ccb
MM		 2358 /* no additional names for: mq, lr, ctr, ap */ \
2359 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2360 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
cacf1ca8
MM		 2361 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2362 /* VSX registers overlaid on top of FR, Altivec registers */ \
2363 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2364 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2365 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2366 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2367 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2368 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2369 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2370 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2371 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2372 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2373 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2374 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2375 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2376 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2377 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2378 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }
f045b2c9 2379
0da40b09
RK		 2380/* Text to write out after a CALL that may be replaced by glue code by
2381 the loader. This depends on the AIX version. */
2382#define RS6000_CALL_GLUE "cror 31,31,31"
11117bb9 2383
f045b2c9
RS		 2384/* This is how to output an element of a case-vector that is relative. */
2385
e1565e65 2386#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3daf36a4 2387 do { char buf[100]; \
e1565e65 2388 fputs ("\t.long ", FILE); \
3daf36a4
ILT		 2389 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2390 assemble_name (FILE, buf); \
19d2d16f 2391 putc ('-', FILE); \
3daf36a4
ILT		 2392 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2393 assemble_name (FILE, buf); \
19d2d16f 2394 putc ('\n', FILE); \
3daf36a4 2395 } while (0)
f045b2c9
RS		 2396
2397/* This is how to output an assembler line
2398 that says to advance the location counter
2399 to a multiple of 2**LOG bytes. */
2400
2401#define ASM_OUTPUT_ALIGN(FILE,LOG) \
2402 if ((LOG) != 0) \
2403 fprintf (FILE, "\t.align %d\n", (LOG))
2404
9ebbca7d
GK		 2405/* Pick up the return address upon entry to a procedure. Used for
2406 dwarf2 unwind information. This also enables the table driven
2407 mechanism. */
2408
1de43f85
DE		 2409#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2410#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
9ebbca7d 2411
83720594
RH		 2412/* Describe how we implement __builtin_eh_return. */
2413#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2414#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2415
f045b2c9
RS		 2416/* Print operand X (an rtx) in assembler syntax to file FILE.
2417 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2418 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2419
2420#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2421
2422/* Define which CODE values are valid. */
2423
c81bebd7 2424#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
c4501e62 2425 ((CODE) == '.' || (CODE) == '&')
f045b2c9
RS		 2426
2427/* Print a memory address as an operand to reference that memory location. */
2428
2429#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2430
2e4316da
RS		 2431#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2432 do \
2433 if (!rs6000_output_addr_const_extra (STREAM, X)) \
2434 goto FAIL; \
2435 while (0)
2436
b6c9286a
MM		 2437/* uncomment for disabling the corresponding default options */
2438/* #define MACHINE_no_sched_interblock */
2439/* #define MACHINE_no_sched_speculative */
2440/* #define MACHINE_no_sched_speculative_load */
2441
766a866c
MM		 2442/* General flags. */
2443extern int flag_pic;
354b734b
MM		 2444extern int optimize;
2445extern int flag_expensive_optimizations;
a7df97e6 2446extern int frame_pointer_needed;
0ac081f6
AH		 2447
2448enum rs6000_builtins
2449{
2450 /* AltiVec builtins. */
f18c054f
DB		 2451 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2452 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2453 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2454 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2455 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2456 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2457 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2458 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
0ac081f6
AH		 2459 ALTIVEC_BUILTIN_VADDUBM,
2460 ALTIVEC_BUILTIN_VADDUHM,
2461 ALTIVEC_BUILTIN_VADDUWM,
2462 ALTIVEC_BUILTIN_VADDFP,
2463 ALTIVEC_BUILTIN_VADDCUW,
2464 ALTIVEC_BUILTIN_VADDUBS,
2465 ALTIVEC_BUILTIN_VADDSBS,
2466 ALTIVEC_BUILTIN_VADDUHS,
2467 ALTIVEC_BUILTIN_VADDSHS,
2468 ALTIVEC_BUILTIN_VADDUWS,
2469 ALTIVEC_BUILTIN_VADDSWS,
2470 ALTIVEC_BUILTIN_VAND,
2471 ALTIVEC_BUILTIN_VANDC,
2472 ALTIVEC_BUILTIN_VAVGUB,
2473 ALTIVEC_BUILTIN_VAVGSB,
2474 ALTIVEC_BUILTIN_VAVGUH,
2475 ALTIVEC_BUILTIN_VAVGSH,
2476 ALTIVEC_BUILTIN_VAVGUW,
2477 ALTIVEC_BUILTIN_VAVGSW,
617e0e1d
DB		 2478 ALTIVEC_BUILTIN_VCFUX,
2479 ALTIVEC_BUILTIN_VCFSX,
2480 ALTIVEC_BUILTIN_VCTSXS,
2481 ALTIVEC_BUILTIN_VCTUXS,
0ac081f6
AH		 2482 ALTIVEC_BUILTIN_VCMPBFP,
2483 ALTIVEC_BUILTIN_VCMPEQUB,
2484 ALTIVEC_BUILTIN_VCMPEQUH,
2485 ALTIVEC_BUILTIN_VCMPEQUW,
2486 ALTIVEC_BUILTIN_VCMPEQFP,
2487 ALTIVEC_BUILTIN_VCMPGEFP,
2488 ALTIVEC_BUILTIN_VCMPGTUB,
2489 ALTIVEC_BUILTIN_VCMPGTSB,
2490 ALTIVEC_BUILTIN_VCMPGTUH,
2491 ALTIVEC_BUILTIN_VCMPGTSH,
2492 ALTIVEC_BUILTIN_VCMPGTUW,
2493 ALTIVEC_BUILTIN_VCMPGTSW,
2494 ALTIVEC_BUILTIN_VCMPGTFP,
617e0e1d
DB		 2495 ALTIVEC_BUILTIN_VEXPTEFP,
2496 ALTIVEC_BUILTIN_VLOGEFP,
2212663f 2497 ALTIVEC_BUILTIN_VMADDFP,
0ac081f6
AH		 2498 ALTIVEC_BUILTIN_VMAXUB,
2499 ALTIVEC_BUILTIN_VMAXSB,
2500 ALTIVEC_BUILTIN_VMAXUH,
2501 ALTIVEC_BUILTIN_VMAXSH,
2502 ALTIVEC_BUILTIN_VMAXUW,
2503 ALTIVEC_BUILTIN_VMAXSW,
2504 ALTIVEC_BUILTIN_VMAXFP,
2212663f
DB		 2505 ALTIVEC_BUILTIN_VMHADDSHS,
2506 ALTIVEC_BUILTIN_VMHRADDSHS,
2507 ALTIVEC_BUILTIN_VMLADDUHM,
0ac081f6
AH		 2508 ALTIVEC_BUILTIN_VMRGHB,
2509 ALTIVEC_BUILTIN_VMRGHH,
2510 ALTIVEC_BUILTIN_VMRGHW,
2511 ALTIVEC_BUILTIN_VMRGLB,
2512 ALTIVEC_BUILTIN_VMRGLH,
2513 ALTIVEC_BUILTIN_VMRGLW,
2212663f
DB		 2514 ALTIVEC_BUILTIN_VMSUMUBM,
2515 ALTIVEC_BUILTIN_VMSUMMBM,
2516 ALTIVEC_BUILTIN_VMSUMUHM,
2517 ALTIVEC_BUILTIN_VMSUMSHM,
2518 ALTIVEC_BUILTIN_VMSUMUHS,
2519 ALTIVEC_BUILTIN_VMSUMSHS,
0ac081f6
AH		 2520 ALTIVEC_BUILTIN_VMINUB,
2521 ALTIVEC_BUILTIN_VMINSB,
2522 ALTIVEC_BUILTIN_VMINUH,
2523 ALTIVEC_BUILTIN_VMINSH,
2524 ALTIVEC_BUILTIN_VMINUW,
2525 ALTIVEC_BUILTIN_VMINSW,
2526 ALTIVEC_BUILTIN_VMINFP,
2527 ALTIVEC_BUILTIN_VMULEUB,
2528 ALTIVEC_BUILTIN_VMULESB,
2529 ALTIVEC_BUILTIN_VMULEUH,
2530 ALTIVEC_BUILTIN_VMULESH,
2531 ALTIVEC_BUILTIN_VMULOUB,
2532 ALTIVEC_BUILTIN_VMULOSB,
2533 ALTIVEC_BUILTIN_VMULOUH,
2534 ALTIVEC_BUILTIN_VMULOSH,
2212663f 2535 ALTIVEC_BUILTIN_VNMSUBFP,
0ac081f6
AH		 2536 ALTIVEC_BUILTIN_VNOR,
2537 ALTIVEC_BUILTIN_VOR,
617e0e1d
DB		 2538 ALTIVEC_BUILTIN_VSEL_4SI,
2539 ALTIVEC_BUILTIN_VSEL_4SF,
2540 ALTIVEC_BUILTIN_VSEL_8HI,
2541 ALTIVEC_BUILTIN_VSEL_16QI,
2212663f
DB		 2542 ALTIVEC_BUILTIN_VPERM_4SI,
2543 ALTIVEC_BUILTIN_VPERM_4SF,
2544 ALTIVEC_BUILTIN_VPERM_8HI,
2545 ALTIVEC_BUILTIN_VPERM_16QI,
0ac081f6
AH		 2546 ALTIVEC_BUILTIN_VPKUHUM,
2547 ALTIVEC_BUILTIN_VPKUWUM,
2548 ALTIVEC_BUILTIN_VPKPX,
2549 ALTIVEC_BUILTIN_VPKUHSS,
2550 ALTIVEC_BUILTIN_VPKSHSS,
2551 ALTIVEC_BUILTIN_VPKUWSS,
2552 ALTIVEC_BUILTIN_VPKSWSS,
2553 ALTIVEC_BUILTIN_VPKUHUS,
2554 ALTIVEC_BUILTIN_VPKSHUS,
2555 ALTIVEC_BUILTIN_VPKUWUS,
2556 ALTIVEC_BUILTIN_VPKSWUS,
617e0e1d
DB		 2557 ALTIVEC_BUILTIN_VREFP,
2558 ALTIVEC_BUILTIN_VRFIM,
2559 ALTIVEC_BUILTIN_VRFIN,
2560 ALTIVEC_BUILTIN_VRFIP,
2561 ALTIVEC_BUILTIN_VRFIZ,
0ac081f6
AH		 2562 ALTIVEC_BUILTIN_VRLB,
2563 ALTIVEC_BUILTIN_VRLH,
2564 ALTIVEC_BUILTIN_VRLW,
617e0e1d 2565 ALTIVEC_BUILTIN_VRSQRTEFP,
0ac081f6
AH		 2566 ALTIVEC_BUILTIN_VSLB,
2567 ALTIVEC_BUILTIN_VSLH,
2568 ALTIVEC_BUILTIN_VSLW,
2569 ALTIVEC_BUILTIN_VSL,
2570 ALTIVEC_BUILTIN_VSLO,
2212663f
DB		 2571 ALTIVEC_BUILTIN_VSPLTB,
2572 ALTIVEC_BUILTIN_VSPLTH,
2573 ALTIVEC_BUILTIN_VSPLTW,
2574 ALTIVEC_BUILTIN_VSPLTISB,
2575 ALTIVEC_BUILTIN_VSPLTISH,
2576 ALTIVEC_BUILTIN_VSPLTISW,
0ac081f6 2577 ALTIVEC_BUILTIN_VSRB,
f18c054f
DB		 2578 ALTIVEC_BUILTIN_VSRH,
2579 ALTIVEC_BUILTIN_VSRW,
0ac081f6
AH		 2580 ALTIVEC_BUILTIN_VSRAB,
2581 ALTIVEC_BUILTIN_VSRAH,
2582 ALTIVEC_BUILTIN_VSRAW,
2583 ALTIVEC_BUILTIN_VSR,
2584 ALTIVEC_BUILTIN_VSRO,
2585 ALTIVEC_BUILTIN_VSUBUBM,
2586 ALTIVEC_BUILTIN_VSUBUHM,
2587 ALTIVEC_BUILTIN_VSUBUWM,
2588 ALTIVEC_BUILTIN_VSUBFP,
2589 ALTIVEC_BUILTIN_VSUBCUW,
2590 ALTIVEC_BUILTIN_VSUBUBS,
2591 ALTIVEC_BUILTIN_VSUBSBS,
2592 ALTIVEC_BUILTIN_VSUBUHS,
2593 ALTIVEC_BUILTIN_VSUBSHS,
2594 ALTIVEC_BUILTIN_VSUBUWS,
2595 ALTIVEC_BUILTIN_VSUBSWS,
2596 ALTIVEC_BUILTIN_VSUM4UBS,
2597 ALTIVEC_BUILTIN_VSUM4SBS,
2598 ALTIVEC_BUILTIN_VSUM4SHS,
2599 ALTIVEC_BUILTIN_VSUM2SWS,
2600 ALTIVEC_BUILTIN_VSUMSWS,
24408032
AH		 2601 ALTIVEC_BUILTIN_VXOR,
2602 ALTIVEC_BUILTIN_VSLDOI_16QI,
2603 ALTIVEC_BUILTIN_VSLDOI_8HI,
2604 ALTIVEC_BUILTIN_VSLDOI_4SI,
20e26713
AH		 2605 ALTIVEC_BUILTIN_VSLDOI_4SF,
2606 ALTIVEC_BUILTIN_VUPKHSB,
2607 ALTIVEC_BUILTIN_VUPKHPX,
2608 ALTIVEC_BUILTIN_VUPKHSH,
2609 ALTIVEC_BUILTIN_VUPKLSB,
2610 ALTIVEC_BUILTIN_VUPKLPX,
fa066a23 2611 ALTIVEC_BUILTIN_VUPKLSH,
95385cbb
AH		 2612 ALTIVEC_BUILTIN_MTVSCR,
2613 ALTIVEC_BUILTIN_MFVSCR,
2614 ALTIVEC_BUILTIN_DSSALL,
2615 ALTIVEC_BUILTIN_DSS,
2616 ALTIVEC_BUILTIN_LVSL,
2617 ALTIVEC_BUILTIN_LVSR,
2618 ALTIVEC_BUILTIN_DSTT,
2619 ALTIVEC_BUILTIN_DSTST,
2620 ALTIVEC_BUILTIN_DSTSTT,
6525c0e7
AH		 2621 ALTIVEC_BUILTIN_DST,
2622 ALTIVEC_BUILTIN_LVEBX,
2623 ALTIVEC_BUILTIN_LVEHX,
2624 ALTIVEC_BUILTIN_LVEWX,
2625 ALTIVEC_BUILTIN_LVXL,
2626 ALTIVEC_BUILTIN_LVX,
2627 ALTIVEC_BUILTIN_STVX,
0b61703c
AP		 2628 ALTIVEC_BUILTIN_LVLX,
2629 ALTIVEC_BUILTIN_LVLXL,
2630 ALTIVEC_BUILTIN_LVRX,
2631 ALTIVEC_BUILTIN_LVRXL,
6525c0e7
AH		 2632 ALTIVEC_BUILTIN_STVEBX,
2633 ALTIVEC_BUILTIN_STVEHX,
2634 ALTIVEC_BUILTIN_STVEWX,
ae4b4a02 2635 ALTIVEC_BUILTIN_STVXL,
0b61703c
AP		 2636 ALTIVEC_BUILTIN_STVLX,
2637 ALTIVEC_BUILTIN_STVLXL,
2638 ALTIVEC_BUILTIN_STVRX,
2639 ALTIVEC_BUILTIN_STVRXL,
ae4b4a02
AH		 2640 ALTIVEC_BUILTIN_VCMPBFP_P,
2641 ALTIVEC_BUILTIN_VCMPEQFP_P,
2642 ALTIVEC_BUILTIN_VCMPEQUB_P,
2643 ALTIVEC_BUILTIN_VCMPEQUH_P,
2644 ALTIVEC_BUILTIN_VCMPEQUW_P,
2645 ALTIVEC_BUILTIN_VCMPGEFP_P,
2646 ALTIVEC_BUILTIN_VCMPGTFP_P,
2647 ALTIVEC_BUILTIN_VCMPGTSB_P,
2648 ALTIVEC_BUILTIN_VCMPGTSH_P,
2649 ALTIVEC_BUILTIN_VCMPGTSW_P,
2650 ALTIVEC_BUILTIN_VCMPGTUB_P,
2651 ALTIVEC_BUILTIN_VCMPGTUH_P,
100c4561
AH		 2652 ALTIVEC_BUILTIN_VCMPGTUW_P,
2653 ALTIVEC_BUILTIN_ABSS_V4SI,
2654 ALTIVEC_BUILTIN_ABSS_V8HI,
2655 ALTIVEC_BUILTIN_ABSS_V16QI,
2656 ALTIVEC_BUILTIN_ABS_V4SI,
2657 ALTIVEC_BUILTIN_ABS_V4SF,
2658 ALTIVEC_BUILTIN_ABS_V8HI,
8bb418a3 2659 ALTIVEC_BUILTIN_ABS_V16QI,
7ccf35ed
DN		 2660 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2661 ALTIVEC_BUILTIN_MASK_FOR_STORE,
7a4eca66
DE		 2662 ALTIVEC_BUILTIN_VEC_INIT_V4SI,
2663 ALTIVEC_BUILTIN_VEC_INIT_V8HI,
2664 ALTIVEC_BUILTIN_VEC_INIT_V16QI,
2665 ALTIVEC_BUILTIN_VEC_INIT_V4SF,
2666 ALTIVEC_BUILTIN_VEC_SET_V4SI,
2667 ALTIVEC_BUILTIN_VEC_SET_V8HI,
2668 ALTIVEC_BUILTIN_VEC_SET_V16QI,
2669 ALTIVEC_BUILTIN_VEC_SET_V4SF,
2670 ALTIVEC_BUILTIN_VEC_EXT_V4SI,
2671 ALTIVEC_BUILTIN_VEC_EXT_V8HI,
2672 ALTIVEC_BUILTIN_VEC_EXT_V16QI,
2673 ALTIVEC_BUILTIN_VEC_EXT_V4SF,
8bb418a3 2674
58646b77
PB		 2675 /* Altivec overloaded builtins. */
2676 ALTIVEC_BUILTIN_VCMPEQ_P,
2677 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
2678 ALTIVEC_BUILTIN_VCMPGT_P,
2679 ALTIVEC_BUILTIN_VCMPGE_P,
2680 ALTIVEC_BUILTIN_VEC_ABS,
2681 ALTIVEC_BUILTIN_VEC_ABSS,
2682 ALTIVEC_BUILTIN_VEC_ADD,
2683 ALTIVEC_BUILTIN_VEC_ADDC,
2684 ALTIVEC_BUILTIN_VEC_ADDS,
2685 ALTIVEC_BUILTIN_VEC_AND,
2686 ALTIVEC_BUILTIN_VEC_ANDC,
2687 ALTIVEC_BUILTIN_VEC_AVG,
266b4890 2688 ALTIVEC_BUILTIN_VEC_EXTRACT,
58646b77
PB		 2689 ALTIVEC_BUILTIN_VEC_CEIL,
2690 ALTIVEC_BUILTIN_VEC_CMPB,
2691 ALTIVEC_BUILTIN_VEC_CMPEQ,
2692 ALTIVEC_BUILTIN_VEC_CMPEQUB,
2693 ALTIVEC_BUILTIN_VEC_CMPEQUH,
2694 ALTIVEC_BUILTIN_VEC_CMPEQUW,
2695 ALTIVEC_BUILTIN_VEC_CMPGE,
2696 ALTIVEC_BUILTIN_VEC_CMPGT,
2697 ALTIVEC_BUILTIN_VEC_CMPLE,
2698 ALTIVEC_BUILTIN_VEC_CMPLT,
2699 ALTIVEC_BUILTIN_VEC_CTF,
2700 ALTIVEC_BUILTIN_VEC_CTS,
2701 ALTIVEC_BUILTIN_VEC_CTU,
2702 ALTIVEC_BUILTIN_VEC_DST,
2703 ALTIVEC_BUILTIN_VEC_DSTST,
2704 ALTIVEC_BUILTIN_VEC_DSTSTT,
2705 ALTIVEC_BUILTIN_VEC_DSTT,
2706 ALTIVEC_BUILTIN_VEC_EXPTE,
2707 ALTIVEC_BUILTIN_VEC_FLOOR,
2708 ALTIVEC_BUILTIN_VEC_LD,
2709 ALTIVEC_BUILTIN_VEC_LDE,
2710 ALTIVEC_BUILTIN_VEC_LDL,
2711 ALTIVEC_BUILTIN_VEC_LOGE,
2712 ALTIVEC_BUILTIN_VEC_LVEBX,
2713 ALTIVEC_BUILTIN_VEC_LVEHX,
2714 ALTIVEC_BUILTIN_VEC_LVEWX,
0b61703c
AP		 2715 ALTIVEC_BUILTIN_VEC_LVLX,
2716 ALTIVEC_BUILTIN_VEC_LVLXL,
2717 ALTIVEC_BUILTIN_VEC_LVRX,
2718 ALTIVEC_BUILTIN_VEC_LVRXL,
58646b77
PB		 2719 ALTIVEC_BUILTIN_VEC_LVSL,
2720 ALTIVEC_BUILTIN_VEC_LVSR,
2721 ALTIVEC_BUILTIN_VEC_MADD,
2722 ALTIVEC_BUILTIN_VEC_MADDS,
2723 ALTIVEC_BUILTIN_VEC_MAX,
2724 ALTIVEC_BUILTIN_VEC_MERGEH,
2725 ALTIVEC_BUILTIN_VEC_MERGEL,
2726 ALTIVEC_BUILTIN_VEC_MIN,
2727 ALTIVEC_BUILTIN_VEC_MLADD,
2728 ALTIVEC_BUILTIN_VEC_MPERM,
2729 ALTIVEC_BUILTIN_VEC_MRADDS,
2730 ALTIVEC_BUILTIN_VEC_MRGHB,
2731 ALTIVEC_BUILTIN_VEC_MRGHH,
2732 ALTIVEC_BUILTIN_VEC_MRGHW,
2733 ALTIVEC_BUILTIN_VEC_MRGLB,
2734 ALTIVEC_BUILTIN_VEC_MRGLH,
2735 ALTIVEC_BUILTIN_VEC_MRGLW,
2736 ALTIVEC_BUILTIN_VEC_MSUM,
2737 ALTIVEC_BUILTIN_VEC_MSUMS,
2738 ALTIVEC_BUILTIN_VEC_MTVSCR,
2739 ALTIVEC_BUILTIN_VEC_MULE,
2740 ALTIVEC_BUILTIN_VEC_MULO,
2741 ALTIVEC_BUILTIN_VEC_NMSUB,
2742 ALTIVEC_BUILTIN_VEC_NOR,
2743 ALTIVEC_BUILTIN_VEC_OR,
2744 ALTIVEC_BUILTIN_VEC_PACK,
2745 ALTIVEC_BUILTIN_VEC_PACKPX,
2746 ALTIVEC_BUILTIN_VEC_PACKS,
2747 ALTIVEC_BUILTIN_VEC_PACKSU,
2748 ALTIVEC_BUILTIN_VEC_PERM,
2749 ALTIVEC_BUILTIN_VEC_RE,
2750 ALTIVEC_BUILTIN_VEC_RL,
2751 ALTIVEC_BUILTIN_VEC_ROUND,
2752 ALTIVEC_BUILTIN_VEC_RSQRTE,
2753 ALTIVEC_BUILTIN_VEC_SEL,
2754 ALTIVEC_BUILTIN_VEC_SL,
2755 ALTIVEC_BUILTIN_VEC_SLD,
2756 ALTIVEC_BUILTIN_VEC_SLL,
2757 ALTIVEC_BUILTIN_VEC_SLO,
2758 ALTIVEC_BUILTIN_VEC_SPLAT,
2759 ALTIVEC_BUILTIN_VEC_SPLAT_S16,
2760 ALTIVEC_BUILTIN_VEC_SPLAT_S32,
2761 ALTIVEC_BUILTIN_VEC_SPLAT_S8,
2762 ALTIVEC_BUILTIN_VEC_SPLAT_U16,
2763 ALTIVEC_BUILTIN_VEC_SPLAT_U32,
2764 ALTIVEC_BUILTIN_VEC_SPLAT_U8,
2765 ALTIVEC_BUILTIN_VEC_SPLTB,
2766 ALTIVEC_BUILTIN_VEC_SPLTH,
2767 ALTIVEC_BUILTIN_VEC_SPLTW,
2768 ALTIVEC_BUILTIN_VEC_SR,
2769 ALTIVEC_BUILTIN_VEC_SRA,
2770 ALTIVEC_BUILTIN_VEC_SRL,
2771 ALTIVEC_BUILTIN_VEC_SRO,
2772 ALTIVEC_BUILTIN_VEC_ST,
2773 ALTIVEC_BUILTIN_VEC_STE,
2774 ALTIVEC_BUILTIN_VEC_STL,
2775 ALTIVEC_BUILTIN_VEC_STVEBX,
2776 ALTIVEC_BUILTIN_VEC_STVEHX,
2777 ALTIVEC_BUILTIN_VEC_STVEWX,
0b61703c
AP		 2778 ALTIVEC_BUILTIN_VEC_STVLX,
2779 ALTIVEC_BUILTIN_VEC_STVLXL,
2780 ALTIVEC_BUILTIN_VEC_STVRX,
2781 ALTIVEC_BUILTIN_VEC_STVRXL,
58646b77
PB		 2782 ALTIVEC_BUILTIN_VEC_SUB,
2783 ALTIVEC_BUILTIN_VEC_SUBC,
2784 ALTIVEC_BUILTIN_VEC_SUBS,
2785 ALTIVEC_BUILTIN_VEC_SUM2S,
2786 ALTIVEC_BUILTIN_VEC_SUM4S,
2787 ALTIVEC_BUILTIN_VEC_SUMS,
2788 ALTIVEC_BUILTIN_VEC_TRUNC,
2789 ALTIVEC_BUILTIN_VEC_UNPACKH,
2790 ALTIVEC_BUILTIN_VEC_UNPACKL,
2791 ALTIVEC_BUILTIN_VEC_VADDFP,
2792 ALTIVEC_BUILTIN_VEC_VADDSBS,
2793 ALTIVEC_BUILTIN_VEC_VADDSHS,
2794 ALTIVEC_BUILTIN_VEC_VADDSWS,
2795 ALTIVEC_BUILTIN_VEC_VADDUBM,
2796 ALTIVEC_BUILTIN_VEC_VADDUBS,
2797 ALTIVEC_BUILTIN_VEC_VADDUHM,
2798 ALTIVEC_BUILTIN_VEC_VADDUHS,
2799 ALTIVEC_BUILTIN_VEC_VADDUWM,
2800 ALTIVEC_BUILTIN_VEC_VADDUWS,
2801 ALTIVEC_BUILTIN_VEC_VAVGSB,
2802 ALTIVEC_BUILTIN_VEC_VAVGSH,
2803 ALTIVEC_BUILTIN_VEC_VAVGSW,
2804 ALTIVEC_BUILTIN_VEC_VAVGUB,
2805 ALTIVEC_BUILTIN_VEC_VAVGUH,
2806 ALTIVEC_BUILTIN_VEC_VAVGUW,
2807 ALTIVEC_BUILTIN_VEC_VCFSX,
2808 ALTIVEC_BUILTIN_VEC_VCFUX,
2809 ALTIVEC_BUILTIN_VEC_VCMPEQFP,
2810 ALTIVEC_BUILTIN_VEC_VCMPEQUB,
2811 ALTIVEC_BUILTIN_VEC_VCMPEQUH,
2812 ALTIVEC_BUILTIN_VEC_VCMPEQUW,
2813 ALTIVEC_BUILTIN_VEC_VCMPGTFP,
2814 ALTIVEC_BUILTIN_VEC_VCMPGTSB,
2815 ALTIVEC_BUILTIN_VEC_VCMPGTSH,
2816 ALTIVEC_BUILTIN_VEC_VCMPGTSW,
2817 ALTIVEC_BUILTIN_VEC_VCMPGTUB,
2818 ALTIVEC_BUILTIN_VEC_VCMPGTUH,
2819 ALTIVEC_BUILTIN_VEC_VCMPGTUW,
2820 ALTIVEC_BUILTIN_VEC_VMAXFP,
2821 ALTIVEC_BUILTIN_VEC_VMAXSB,
2822 ALTIVEC_BUILTIN_VEC_VMAXSH,
2823 ALTIVEC_BUILTIN_VEC_VMAXSW,
2824 ALTIVEC_BUILTIN_VEC_VMAXUB,
2825 ALTIVEC_BUILTIN_VEC_VMAXUH,
2826 ALTIVEC_BUILTIN_VEC_VMAXUW,
2827 ALTIVEC_BUILTIN_VEC_VMINFP,
2828 ALTIVEC_BUILTIN_VEC_VMINSB,
2829 ALTIVEC_BUILTIN_VEC_VMINSH,
2830 ALTIVEC_BUILTIN_VEC_VMINSW,
2831 ALTIVEC_BUILTIN_VEC_VMINUB,
2832 ALTIVEC_BUILTIN_VEC_VMINUH,
2833 ALTIVEC_BUILTIN_VEC_VMINUW,
2834 ALTIVEC_BUILTIN_VEC_VMRGHB,
2835 ALTIVEC_BUILTIN_VEC_VMRGHH,
2836 ALTIVEC_BUILTIN_VEC_VMRGHW,
2837 ALTIVEC_BUILTIN_VEC_VMRGLB,
2838 ALTIVEC_BUILTIN_VEC_VMRGLH,
2839 ALTIVEC_BUILTIN_VEC_VMRGLW,
2840 ALTIVEC_BUILTIN_VEC_VMSUMMBM,
2841 ALTIVEC_BUILTIN_VEC_VMSUMSHM,
2842 ALTIVEC_BUILTIN_VEC_VMSUMSHS,
2843 ALTIVEC_BUILTIN_VEC_VMSUMUBM,
2844 ALTIVEC_BUILTIN_VEC_VMSUMUHM,
2845 ALTIVEC_BUILTIN_VEC_VMSUMUHS,
2846 ALTIVEC_BUILTIN_VEC_VMULESB,
2847 ALTIVEC_BUILTIN_VEC_VMULESH,
2848 ALTIVEC_BUILTIN_VEC_VMULEUB,
2849 ALTIVEC_BUILTIN_VEC_VMULEUH,
2850 ALTIVEC_BUILTIN_VEC_VMULOSB,
2851 ALTIVEC_BUILTIN_VEC_VMULOSH,
2852 ALTIVEC_BUILTIN_VEC_VMULOUB,
2853 ALTIVEC_BUILTIN_VEC_VMULOUH,
2854 ALTIVEC_BUILTIN_VEC_VPKSHSS,
2855 ALTIVEC_BUILTIN_VEC_VPKSHUS,
2856 ALTIVEC_BUILTIN_VEC_VPKSWSS,
2857 ALTIVEC_BUILTIN_VEC_VPKSWUS,
2858 ALTIVEC_BUILTIN_VEC_VPKUHUM,
2859 ALTIVEC_BUILTIN_VEC_VPKUHUS,
2860 ALTIVEC_BUILTIN_VEC_VPKUWUM,
2861 ALTIVEC_BUILTIN_VEC_VPKUWUS,
2862 ALTIVEC_BUILTIN_VEC_VRLB,
2863 ALTIVEC_BUILTIN_VEC_VRLH,
2864 ALTIVEC_BUILTIN_VEC_VRLW,
2865 ALTIVEC_BUILTIN_VEC_VSLB,
2866 ALTIVEC_BUILTIN_VEC_VSLH,
2867 ALTIVEC_BUILTIN_VEC_VSLW,
2868 ALTIVEC_BUILTIN_VEC_VSPLTB,
2869 ALTIVEC_BUILTIN_VEC_VSPLTH,
2870 ALTIVEC_BUILTIN_VEC_VSPLTW,
2871 ALTIVEC_BUILTIN_VEC_VSRAB,
2872 ALTIVEC_BUILTIN_VEC_VSRAH,
2873 ALTIVEC_BUILTIN_VEC_VSRAW,
2874 ALTIVEC_BUILTIN_VEC_VSRB,
2875 ALTIVEC_BUILTIN_VEC_VSRH,
2876 ALTIVEC_BUILTIN_VEC_VSRW,
2877 ALTIVEC_BUILTIN_VEC_VSUBFP,
2878 ALTIVEC_BUILTIN_VEC_VSUBSBS,
2879 ALTIVEC_BUILTIN_VEC_VSUBSHS,
2880 ALTIVEC_BUILTIN_VEC_VSUBSWS,
2881 ALTIVEC_BUILTIN_VEC_VSUBUBM,
2882 ALTIVEC_BUILTIN_VEC_VSUBUBS,
2883 ALTIVEC_BUILTIN_VEC_VSUBUHM,
2884 ALTIVEC_BUILTIN_VEC_VSUBUHS,
2885 ALTIVEC_BUILTIN_VEC_VSUBUWM,
2886 ALTIVEC_BUILTIN_VEC_VSUBUWS,
2887 ALTIVEC_BUILTIN_VEC_VSUM4SBS,
2888 ALTIVEC_BUILTIN_VEC_VSUM4SHS,
2889 ALTIVEC_BUILTIN_VEC_VSUM4UBS,
2890 ALTIVEC_BUILTIN_VEC_VUPKHPX,
2891 ALTIVEC_BUILTIN_VEC_VUPKHSB,
2892 ALTIVEC_BUILTIN_VEC_VUPKHSH,
2893 ALTIVEC_BUILTIN_VEC_VUPKLPX,
2894 ALTIVEC_BUILTIN_VEC_VUPKLSB,
2895 ALTIVEC_BUILTIN_VEC_VUPKLSH,
2896 ALTIVEC_BUILTIN_VEC_XOR,
2897 ALTIVEC_BUILTIN_VEC_STEP,
266b4890
AP		 2898 ALTIVEC_BUILTIN_VEC_PROMOTE,
2899 ALTIVEC_BUILTIN_VEC_INSERT,
2900 ALTIVEC_BUILTIN_VEC_SPLATS,
2901 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_SPLATS,
58646b77 2902
a3170dc6 2903 /* SPE builtins. */
8bb418a3 2904 SPE_BUILTIN_EVADDW,
a3170dc6
AH		 2905 SPE_BUILTIN_EVAND,
2906 SPE_BUILTIN_EVANDC,
2907 SPE_BUILTIN_EVDIVWS,
2908 SPE_BUILTIN_EVDIVWU,
2909 SPE_BUILTIN_EVEQV,
2910 SPE_BUILTIN_EVFSADD,
2911 SPE_BUILTIN_EVFSDIV,
2912 SPE_BUILTIN_EVFSMUL,
2913 SPE_BUILTIN_EVFSSUB,
2914 SPE_BUILTIN_EVLDDX,
2915 SPE_BUILTIN_EVLDHX,
2916 SPE_BUILTIN_EVLDWX,
2917 SPE_BUILTIN_EVLHHESPLATX,
2918 SPE_BUILTIN_EVLHHOSSPLATX,
2919 SPE_BUILTIN_EVLHHOUSPLATX,
2920 SPE_BUILTIN_EVLWHEX,
2921 SPE_BUILTIN_EVLWHOSX,
2922 SPE_BUILTIN_EVLWHOUX,
2923 SPE_BUILTIN_EVLWHSPLATX,
2924 SPE_BUILTIN_EVLWWSPLATX,
2925 SPE_BUILTIN_EVMERGEHI,
2926 SPE_BUILTIN_EVMERGEHILO,
2927 SPE_BUILTIN_EVMERGELO,
2928 SPE_BUILTIN_EVMERGELOHI,
2929 SPE_BUILTIN_EVMHEGSMFAA,
2930 SPE_BUILTIN_EVMHEGSMFAN,
2931 SPE_BUILTIN_EVMHEGSMIAA,
2932 SPE_BUILTIN_EVMHEGSMIAN,
2933 SPE_BUILTIN_EVMHEGUMIAA,
2934 SPE_BUILTIN_EVMHEGUMIAN,
2935 SPE_BUILTIN_EVMHESMF,
2936 SPE_BUILTIN_EVMHESMFA,
2937 SPE_BUILTIN_EVMHESMFAAW,
2938 SPE_BUILTIN_EVMHESMFANW,
2939 SPE_BUILTIN_EVMHESMI,
2940 SPE_BUILTIN_EVMHESMIA,
2941 SPE_BUILTIN_EVMHESMIAAW,
2942 SPE_BUILTIN_EVMHESMIANW,
2943 SPE_BUILTIN_EVMHESSF,
2944 SPE_BUILTIN_EVMHESSFA,
2945 SPE_BUILTIN_EVMHESSFAAW,
2946 SPE_BUILTIN_EVMHESSFANW,
2947 SPE_BUILTIN_EVMHESSIAAW,
2948 SPE_BUILTIN_EVMHESSIANW,
2949 SPE_BUILTIN_EVMHEUMI,
2950 SPE_BUILTIN_EVMHEUMIA,
2951 SPE_BUILTIN_EVMHEUMIAAW,
2952 SPE_BUILTIN_EVMHEUMIANW,
2953 SPE_BUILTIN_EVMHEUSIAAW,
2954 SPE_BUILTIN_EVMHEUSIANW,
2955 SPE_BUILTIN_EVMHOGSMFAA,
2956 SPE_BUILTIN_EVMHOGSMFAN,
2957 SPE_BUILTIN_EVMHOGSMIAA,
2958 SPE_BUILTIN_EVMHOGSMIAN,
2959 SPE_BUILTIN_EVMHOGUMIAA,
2960 SPE_BUILTIN_EVMHOGUMIAN,
2961 SPE_BUILTIN_EVMHOSMF,
2962 SPE_BUILTIN_EVMHOSMFA,
2963 SPE_BUILTIN_EVMHOSMFAAW,
2964 SPE_BUILTIN_EVMHOSMFANW,
2965 SPE_BUILTIN_EVMHOSMI,
2966 SPE_BUILTIN_EVMHOSMIA,
2967 SPE_BUILTIN_EVMHOSMIAAW,
2968 SPE_BUILTIN_EVMHOSMIANW,
2969 SPE_BUILTIN_EVMHOSSF,
2970 SPE_BUILTIN_EVMHOSSFA,
2971 SPE_BUILTIN_EVMHOSSFAAW,
2972 SPE_BUILTIN_EVMHOSSFANW,
2973 SPE_BUILTIN_EVMHOSSIAAW,
2974 SPE_BUILTIN_EVMHOSSIANW,
2975 SPE_BUILTIN_EVMHOUMI,
2976 SPE_BUILTIN_EVMHOUMIA,
2977 SPE_BUILTIN_EVMHOUMIAAW,
2978 SPE_BUILTIN_EVMHOUMIANW,
2979 SPE_BUILTIN_EVMHOUSIAAW,
2980 SPE_BUILTIN_EVMHOUSIANW,
2981 SPE_BUILTIN_EVMWHSMF,
2982 SPE_BUILTIN_EVMWHSMFA,
2983 SPE_BUILTIN_EVMWHSMI,
2984 SPE_BUILTIN_EVMWHSMIA,
2985 SPE_BUILTIN_EVMWHSSF,
2986 SPE_BUILTIN_EVMWHSSFA,
2987 SPE_BUILTIN_EVMWHUMI,
2988 SPE_BUILTIN_EVMWHUMIA,
a3170dc6
AH		 2989 SPE_BUILTIN_EVMWLSMIAAW,
2990 SPE_BUILTIN_EVMWLSMIANW,
a3170dc6
AH		 2991 SPE_BUILTIN_EVMWLSSIAAW,
2992 SPE_BUILTIN_EVMWLSSIANW,
2993 SPE_BUILTIN_EVMWLUMI,
2994 SPE_BUILTIN_EVMWLUMIA,
2995 SPE_BUILTIN_EVMWLUMIAAW,
2996 SPE_BUILTIN_EVMWLUMIANW,
2997 SPE_BUILTIN_EVMWLUSIAAW,
2998 SPE_BUILTIN_EVMWLUSIANW,
2999 SPE_BUILTIN_EVMWSMF,
3000 SPE_BUILTIN_EVMWSMFA,
3001 SPE_BUILTIN_EVMWSMFAA,
3002 SPE_BUILTIN_EVMWSMFAN,
3003 SPE_BUILTIN_EVMWSMI,
3004 SPE_BUILTIN_EVMWSMIA,
3005 SPE_BUILTIN_EVMWSMIAA,
3006 SPE_BUILTIN_EVMWSMIAN,
3007 SPE_BUILTIN_EVMWHSSFAA,
3008 SPE_BUILTIN_EVMWSSF,
3009 SPE_BUILTIN_EVMWSSFA,
3010 SPE_BUILTIN_EVMWSSFAA,
3011 SPE_BUILTIN_EVMWSSFAN,
3012 SPE_BUILTIN_EVMWUMI,
3013 SPE_BUILTIN_EVMWUMIA,
3014 SPE_BUILTIN_EVMWUMIAA,
3015 SPE_BUILTIN_EVMWUMIAN,
3016 SPE_BUILTIN_EVNAND,
3017 SPE_BUILTIN_EVNOR,
3018 SPE_BUILTIN_EVOR,
3019 SPE_BUILTIN_EVORC,
3020 SPE_BUILTIN_EVRLW,
3021 SPE_BUILTIN_EVSLW,
3022 SPE_BUILTIN_EVSRWS,
3023 SPE_BUILTIN_EVSRWU,
3024 SPE_BUILTIN_EVSTDDX,
3025 SPE_BUILTIN_EVSTDHX,
3026 SPE_BUILTIN_EVSTDWX,
3027 SPE_BUILTIN_EVSTWHEX,
3028 SPE_BUILTIN_EVSTWHOX,
3029 SPE_BUILTIN_EVSTWWEX,
3030 SPE_BUILTIN_EVSTWWOX,
3031 SPE_BUILTIN_EVSUBFW,
3032 SPE_BUILTIN_EVXOR,
3033 SPE_BUILTIN_EVABS,
3034 SPE_BUILTIN_EVADDSMIAAW,
3035 SPE_BUILTIN_EVADDSSIAAW,
3036 SPE_BUILTIN_EVADDUMIAAW,
3037 SPE_BUILTIN_EVADDUSIAAW,
3038 SPE_BUILTIN_EVCNTLSW,
3039 SPE_BUILTIN_EVCNTLZW,
3040 SPE_BUILTIN_EVEXTSB,
3041 SPE_BUILTIN_EVEXTSH,
3042 SPE_BUILTIN_EVFSABS,
3043 SPE_BUILTIN_EVFSCFSF,
3044 SPE_BUILTIN_EVFSCFSI,
3045 SPE_BUILTIN_EVFSCFUF,
3046 SPE_BUILTIN_EVFSCFUI,
3047 SPE_BUILTIN_EVFSCTSF,
3048 SPE_BUILTIN_EVFSCTSI,
3049 SPE_BUILTIN_EVFSCTSIZ,
3050 SPE_BUILTIN_EVFSCTUF,
3051 SPE_BUILTIN_EVFSCTUI,
3052 SPE_BUILTIN_EVFSCTUIZ,
3053 SPE_BUILTIN_EVFSNABS,
3054 SPE_BUILTIN_EVFSNEG,
3055 SPE_BUILTIN_EVMRA,
3056 SPE_BUILTIN_EVNEG,
3057 SPE_BUILTIN_EVRNDW,
3058 SPE_BUILTIN_EVSUBFSMIAAW,
3059 SPE_BUILTIN_EVSUBFSSIAAW,
3060 SPE_BUILTIN_EVSUBFUMIAAW,
3061 SPE_BUILTIN_EVSUBFUSIAAW,
3062 SPE_BUILTIN_EVADDIW,
3063 SPE_BUILTIN_EVLDD,
3064 SPE_BUILTIN_EVLDH,
3065 SPE_BUILTIN_EVLDW,
3066 SPE_BUILTIN_EVLHHESPLAT,
3067 SPE_BUILTIN_EVLHHOSSPLAT,
3068 SPE_BUILTIN_EVLHHOUSPLAT,
3069 SPE_BUILTIN_EVLWHE,
3070 SPE_BUILTIN_EVLWHOS,
3071 SPE_BUILTIN_EVLWHOU,
3072 SPE_BUILTIN_EVLWHSPLAT,
3073 SPE_BUILTIN_EVLWWSPLAT,
3074 SPE_BUILTIN_EVRLWI,
3075 SPE_BUILTIN_EVSLWI,
3076 SPE_BUILTIN_EVSRWIS,
3077 SPE_BUILTIN_EVSRWIU,
3078 SPE_BUILTIN_EVSTDD,
3079 SPE_BUILTIN_EVSTDH,
3080 SPE_BUILTIN_EVSTDW,
3081 SPE_BUILTIN_EVSTWHE,
3082 SPE_BUILTIN_EVSTWHO,
3083 SPE_BUILTIN_EVSTWWE,
3084 SPE_BUILTIN_EVSTWWO,
3085 SPE_BUILTIN_EVSUBIFW,
3086
3087 /* Compares. */
3088 SPE_BUILTIN_EVCMPEQ,
3089 SPE_BUILTIN_EVCMPGTS,
3090 SPE_BUILTIN_EVCMPGTU,
3091 SPE_BUILTIN_EVCMPLTS,
3092 SPE_BUILTIN_EVCMPLTU,
3093 SPE_BUILTIN_EVFSCMPEQ,
3094 SPE_BUILTIN_EVFSCMPGT,
3095 SPE_BUILTIN_EVFSCMPLT,
3096 SPE_BUILTIN_EVFSTSTEQ,
3097 SPE_BUILTIN_EVFSTSTGT,
3098 SPE_BUILTIN_EVFSTSTLT,
3099
3100 /* EVSEL compares. */
3101 SPE_BUILTIN_EVSEL_CMPEQ,
3102 SPE_BUILTIN_EVSEL_CMPGTS,
3103 SPE_BUILTIN_EVSEL_CMPGTU,
3104 SPE_BUILTIN_EVSEL_CMPLTS,
3105 SPE_BUILTIN_EVSEL_CMPLTU,
3106 SPE_BUILTIN_EVSEL_FSCMPEQ,
3107 SPE_BUILTIN_EVSEL_FSCMPGT,
3108 SPE_BUILTIN_EVSEL_FSCMPLT,
3109 SPE_BUILTIN_EVSEL_FSTSTEQ,
3110 SPE_BUILTIN_EVSEL_FSTSTGT,
3111 SPE_BUILTIN_EVSEL_FSTSTLT,
3112
3113 SPE_BUILTIN_EVSPLATFI,
3114 SPE_BUILTIN_EVSPLATI,
3115 SPE_BUILTIN_EVMWHSSMAA,
3116 SPE_BUILTIN_EVMWHSMFAA,
3117 SPE_BUILTIN_EVMWHSMIAA,
3118 SPE_BUILTIN_EVMWHUSIAA,
3119 SPE_BUILTIN_EVMWHUMIAA,
3120 SPE_BUILTIN_EVMWHSSFAN,
3121 SPE_BUILTIN_EVMWHSSIAN,
3122 SPE_BUILTIN_EVMWHSMFAN,
3123 SPE_BUILTIN_EVMWHSMIAN,
3124 SPE_BUILTIN_EVMWHUSIAN,
3125 SPE_BUILTIN_EVMWHUMIAN,
3126 SPE_BUILTIN_EVMWHGSSFAA,
3127 SPE_BUILTIN_EVMWHGSMFAA,
3128 SPE_BUILTIN_EVMWHGSMIAA,
3129 SPE_BUILTIN_EVMWHGUMIAA,
3130 SPE_BUILTIN_EVMWHGSSFAN,
3131 SPE_BUILTIN_EVMWHGSMFAN,
3132 SPE_BUILTIN_EVMWHGSMIAN,
3133 SPE_BUILTIN_EVMWHGUMIAN,
3134 SPE_BUILTIN_MTSPEFSCR,
3135 SPE_BUILTIN_MFSPEFSCR,
58646b77
PB		 3136 SPE_BUILTIN_BRINC,
3137
96038623
DE		 3138 /* PAIRED builtins. */
3139 PAIRED_BUILTIN_DIVV2SF3,
3140 PAIRED_BUILTIN_ABSV2SF2,
3141 PAIRED_BUILTIN_NEGV2SF2,
3142 PAIRED_BUILTIN_SQRTV2SF2,
3143 PAIRED_BUILTIN_ADDV2SF3,
3144 PAIRED_BUILTIN_SUBV2SF3,
3145 PAIRED_BUILTIN_RESV2SF2,
3146 PAIRED_BUILTIN_MULV2SF3,
3147 PAIRED_BUILTIN_MSUB,
3148 PAIRED_BUILTIN_MADD,
3149 PAIRED_BUILTIN_NMSUB,
3150 PAIRED_BUILTIN_NMADD,
3151 PAIRED_BUILTIN_NABSV2SF2,
3152 PAIRED_BUILTIN_SUM0,
3153 PAIRED_BUILTIN_SUM1,
3154 PAIRED_BUILTIN_MULS0,
3155 PAIRED_BUILTIN_MULS1,
3156 PAIRED_BUILTIN_MERGE00,
3157 PAIRED_BUILTIN_MERGE01,
3158 PAIRED_BUILTIN_MERGE10,
3159 PAIRED_BUILTIN_MERGE11,
3160 PAIRED_BUILTIN_MADDS0,
3161 PAIRED_BUILTIN_MADDS1,
3162 PAIRED_BUILTIN_STX,
3163 PAIRED_BUILTIN_LX,
49e39588 3164 PAIRED_BUILTIN_SELV2SF4,
96038623
DE		 3165 PAIRED_BUILTIN_CMPU0,
3166 PAIRED_BUILTIN_CMPU1,
3167
9c78b944
DE		 3168 RS6000_BUILTIN_RECIP,
3169 RS6000_BUILTIN_RECIPF,
3170 RS6000_BUILTIN_RSQRTF,
3171
58646b77
PB		 3172 RS6000_BUILTIN_COUNT
3173};
3174
3175enum rs6000_builtin_type_index
3176{
3177 RS6000_BTI_NOT_OPAQUE,
3178 RS6000_BTI_opaque_V2SI,
3179 RS6000_BTI_opaque_V2SF,
3180 RS6000_BTI_opaque_p_V2SI,
3181 RS6000_BTI_opaque_V4SI,
3182 RS6000_BTI_V16QI,
3183 RS6000_BTI_V2SI,
3184 RS6000_BTI_V2SF,
3185 RS6000_BTI_V4HI,
3186 RS6000_BTI_V4SI,
3187 RS6000_BTI_V4SF,
3188 RS6000_BTI_V8HI,
3189 RS6000_BTI_unsigned_V16QI,
3190 RS6000_BTI_unsigned_V8HI,
3191 RS6000_BTI_unsigned_V4SI,
3192 RS6000_BTI_bool_char, /* __bool char */
3193 RS6000_BTI_bool_short, /* __bool short */
3194 RS6000_BTI_bool_int, /* __bool int */
3195 RS6000_BTI_pixel, /* __pixel */
3196 RS6000_BTI_bool_V16QI, /* __vector __bool char */
3197 RS6000_BTI_bool_V8HI, /* __vector __bool short */
3198 RS6000_BTI_bool_V4SI, /* __vector __bool int */
3199 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
3200 RS6000_BTI_long, /* long_integer_type_node */
3201 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
3202 RS6000_BTI_INTQI, /* intQI_type_node */
3203 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
3204 RS6000_BTI_INTHI, /* intHI_type_node */
3205 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
3206 RS6000_BTI_INTSI, /* intSI_type_node */
3207 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
3208 RS6000_BTI_float, /* float_type_node */
3209 RS6000_BTI_void, /* void_type_node */
3210 RS6000_BTI_MAX
0ac081f6 3211};
58646b77
PB		 3212
3213
3214#define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
3215#define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
3216#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
3217#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
3218#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
3219#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
3220#define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
3221#define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
3222#define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
3223#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
3224#define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
3225#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
3226#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
3227#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
3228#define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
3229#define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
3230#define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
3231#define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
3232#define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
3233#define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
3234#define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
3235#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
3236
3237#define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
3238#define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
3239#define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
3240#define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
3241#define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
3242#define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
3243#define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
3244#define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
3245#define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
3246#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
3247
3248extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
3249extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
3250
Mirror of https://gcc.gnu.org/git/gcc.git