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f045b2c9 | 1 | /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
818ab71a | 2 | Copyright (C) 1992-2016 Free Software Foundation, Inc. |
6a7ec0a7 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
f045b2c9 | 4 | |
5de601cf | 5 | This file is part of GCC. |
f045b2c9 | 6 | |
5de601cf NC |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
5de601cf | 10 | option) any later version. |
f045b2c9 | 11 | |
5de601cf NC |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
f045b2c9 | 16 | |
748086b7 JJ |
17 | Under Section 7 of GPL version 3, you are granted additional |
18 | permissions described in the GCC Runtime Library Exception, version | |
19 | 3.1, as published by the Free Software Foundation. | |
20 | ||
21 | You should have received a copy of the GNU General Public License and | |
22 | a copy of the GCC Runtime Library Exception along with this program; | |
23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 24 | <http://www.gnu.org/licenses/>. */ |
f045b2c9 RS |
25 | |
26 | /* Note that some other tm.h files include this one and then override | |
9ebbca7d | 27 | many of the definitions. */ |
f045b2c9 | 28 | |
fd438373 MM |
29 | #ifndef RS6000_OPTS_H |
30 | #include "config/rs6000/rs6000-opts.h" | |
31 | #endif | |
32 | ||
9ebbca7d GK |
33 | /* Definitions for the object file format. These are set at |
34 | compile-time. */ | |
f045b2c9 | 35 | |
9ebbca7d GK |
36 | #define OBJECT_XCOFF 1 |
37 | #define OBJECT_ELF 2 | |
38 | #define OBJECT_PEF 3 | |
ee890fe2 | 39 | #define OBJECT_MACHO 4 |
f045b2c9 | 40 | |
9ebbca7d | 41 | #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) |
2bfcf297 | 42 | #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) |
9ebbca7d | 43 | #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) |
ee890fe2 | 44 | #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) |
f045b2c9 | 45 | |
2bfcf297 DB |
46 | #ifndef TARGET_AIX |
47 | #define TARGET_AIX 0 | |
48 | #endif | |
49 | ||
78009d9f MM |
50 | #ifndef TARGET_AIX_OS |
51 | #define TARGET_AIX_OS 0 | |
52 | #endif | |
53 | ||
85b776df AM |
54 | /* Control whether function entry points use a "dot" symbol when |
55 | ABI_AIX. */ | |
56 | #define DOT_SYMBOLS 1 | |
57 | ||
8e3f41e7 MM |
58 | /* Default string to use for cpu if not specified. */ |
59 | #ifndef TARGET_CPU_DEFAULT | |
60 | #define TARGET_CPU_DEFAULT ((char *)0) | |
61 | #endif | |
62 | ||
f565b0a1 | 63 | /* If configured for PPC405, support PPC405CR Erratum77. */ |
b0bfee6e | 64 | #ifdef CONFIG_PPC405CR |
f565b0a1 DE |
65 | #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) |
66 | #else | |
67 | #define PPC405_ERRATUM77 0 | |
68 | #endif | |
69 | ||
96038623 DE |
70 | #ifndef TARGET_PAIRED_FLOAT |
71 | #define TARGET_PAIRED_FLOAT 0 | |
72 | #endif | |
73 | ||
cd679487 BE |
74 | #ifdef HAVE_AS_POPCNTB |
75 | #define ASM_CPU_POWER5_SPEC "-mpower5" | |
76 | #else | |
77 | #define ASM_CPU_POWER5_SPEC "-mpower4" | |
78 | #endif | |
79 | ||
80 | #ifdef HAVE_AS_DFP | |
81 | #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" | |
82 | #else | |
83 | #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" | |
84 | #endif | |
85 | ||
cacf1ca8 | 86 | #ifdef HAVE_AS_POPCNTD |
d40c9e33 PB |
87 | #define ASM_CPU_POWER7_SPEC "-mpower7" |
88 | #else | |
89 | #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" | |
90 | #endif | |
91 | ||
428bffcb PB |
92 | #ifdef HAVE_AS_POWER8 |
93 | #define ASM_CPU_POWER8_SPEC "-mpower8" | |
94 | #else | |
f62511da | 95 | #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC |
428bffcb PB |
96 | #endif |
97 | ||
d1f0d376 MM |
98 | #ifdef HAVE_AS_POWER9 |
99 | #define ASM_CPU_POWER9_SPEC "-mpower9" | |
100 | #else | |
101 | #define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC | |
102 | #endif | |
103 | ||
47f67e51 PB |
104 | #ifdef HAVE_AS_DCI |
105 | #define ASM_CPU_476_SPEC "-m476" | |
106 | #else | |
107 | #define ASM_CPU_476_SPEC "-mpower4" | |
108 | #endif | |
109 | ||
cacf1ca8 MM |
110 | /* Common ASM definitions used by ASM_SPEC among the various targets for |
111 | handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to | |
112 | provide the default assembler options if the user uses -mcpu=native, so if | |
113 | you make changes here, make them also there. */ | |
f984d8df DB |
114 | #define ASM_CPU_SPEC \ |
115 | "%{!mcpu*: \ | |
93ae5495 | 116 | %{mpowerpc64*: -mppc64} \ |
a441dedb | 117 | %{!mpowerpc64*: %(asm_default)}} \ |
cacf1ca8 | 118 | %{mcpu=native: %(asm_cpu_native)} \ |
d296e02e | 119 | %{mcpu=cell: -mcell} \ |
93ae5495 | 120 | %{mcpu=power3: -mppc64} \ |
957e9e48 | 121 | %{mcpu=power4: -mpower4} \ |
cd679487 BE |
122 | %{mcpu=power5: %(asm_cpu_power5)} \ |
123 | %{mcpu=power5+: %(asm_cpu_power5)} \ | |
124 | %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ | |
125 | %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ | |
d40c9e33 | 126 | %{mcpu=power7: %(asm_cpu_power7)} \ |
428bffcb | 127 | %{mcpu=power8: %(asm_cpu_power8)} \ |
d1f0d376 | 128 | %{mcpu=power9: %(asm_cpu_power9)} \ |
ebde32fd | 129 | %{mcpu=a2: -ma2} \ |
f984d8df | 130 | %{mcpu=powerpc: -mppc} \ |
fa17b3db | 131 | %{mcpu=powerpc64le: %(asm_cpu_power8)} \ |
93ae5495 | 132 | %{mcpu=rs64a: -mppc64} \ |
f984d8df | 133 | %{mcpu=401: -mppc} \ |
61a8515c JS |
134 | %{mcpu=403: -m403} \ |
135 | %{mcpu=405: -m405} \ | |
2c9d95ef DE |
136 | %{mcpu=405fp: -m405} \ |
137 | %{mcpu=440: -m440} \ | |
138 | %{mcpu=440fp: -m440} \ | |
4adf8008 PB |
139 | %{mcpu=464: -m440} \ |
140 | %{mcpu=464fp: -m440} \ | |
47f67e51 PB |
141 | %{mcpu=476: %(asm_cpu_476)} \ |
142 | %{mcpu=476fp: %(asm_cpu_476)} \ | |
f984d8df DB |
143 | %{mcpu=505: -mppc} \ |
144 | %{mcpu=601: -m601} \ | |
145 | %{mcpu=602: -mppc} \ | |
146 | %{mcpu=603: -mppc} \ | |
147 | %{mcpu=603e: -mppc} \ | |
148 | %{mcpu=ec603e: -mppc} \ | |
149 | %{mcpu=604: -mppc} \ | |
150 | %{mcpu=604e: -mppc} \ | |
93ae5495 AM |
151 | %{mcpu=620: -mppc64} \ |
152 | %{mcpu=630: -mppc64} \ | |
f984d8df DB |
153 | %{mcpu=740: -mppc} \ |
154 | %{mcpu=750: -mppc} \ | |
49ffe578 | 155 | %{mcpu=G3: -mppc} \ |
93ae5495 AM |
156 | %{mcpu=7400: -mppc -maltivec} \ |
157 | %{mcpu=7450: -mppc -maltivec} \ | |
158 | %{mcpu=G4: -mppc -maltivec} \ | |
f984d8df DB |
159 | %{mcpu=801: -mppc} \ |
160 | %{mcpu=821: -mppc} \ | |
161 | %{mcpu=823: -mppc} \ | |
775db490 | 162 | %{mcpu=860: -mppc} \ |
93ae5495 AM |
163 | %{mcpu=970: -mpower4 -maltivec} \ |
164 | %{mcpu=G5: -mpower4 -maltivec} \ | |
a3170dc6 | 165 | %{mcpu=8540: -me500} \ |
5ca0373f | 166 | %{mcpu=8548: -me500} \ |
fa41c305 EW |
167 | %{mcpu=e300c2: -me300} \ |
168 | %{mcpu=e300c3: -me300} \ | |
edae5fe3 | 169 | %{mcpu=e500mc: -me500mc} \ |
b17f98b1 | 170 | %{mcpu=e500mc64: -me500mc64} \ |
683ed19e EW |
171 | %{mcpu=e5500: -me5500} \ |
172 | %{mcpu=e6500: -me6500} \ | |
93ae5495 | 173 | %{maltivec: -maltivec} \ |
2c9ccc21 | 174 | %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ |
0258b6e4 | 175 | %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \ |
93ae5495 | 176 | -many" |
f984d8df DB |
177 | |
178 | #define CPP_DEFAULT_SPEC "" | |
179 | ||
180 | #define ASM_DEFAULT_SPEC "" | |
181 | ||
841faeed MM |
182 | /* This macro defines names of additional specifications to put in the specs |
183 | that can be used in various specifications like CC1_SPEC. Its definition | |
184 | is an initializer with a subgrouping for each command option. | |
185 | ||
186 | Each subgrouping contains a string constant, that defines the | |
5de601cf | 187 | specification name, and a string constant that used by the GCC driver |
841faeed MM |
188 | program. |
189 | ||
190 | Do not define this macro if it does not need to do anything. */ | |
191 | ||
7509c759 | 192 | #define SUBTARGET_EXTRA_SPECS |
7509c759 | 193 | |
c81bebd7 | 194 | #define EXTRA_SPECS \ |
c81bebd7 | 195 | { "cpp_default", CPP_DEFAULT_SPEC }, \ |
c81bebd7 | 196 | { "asm_cpu", ASM_CPU_SPEC }, \ |
cacf1ca8 | 197 | { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
c81bebd7 | 198 | { "asm_default", ASM_DEFAULT_SPEC }, \ |
0eab6840 | 199 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
cd679487 BE |
200 | { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ |
201 | { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ | |
d40c9e33 | 202 | { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ |
428bffcb | 203 | { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ |
d1f0d376 | 204 | { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \ |
47f67e51 | 205 | { "asm_cpu_476", ASM_CPU_476_SPEC }, \ |
7509c759 MM |
206 | SUBTARGET_EXTRA_SPECS |
207 | ||
0eab6840 DE |
208 | /* -mcpu=native handling only makes sense with compiler running on |
209 | an PowerPC chip. If changing this condition, also change | |
210 | the condition in driver-rs6000.c. */ | |
211 | #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) | |
212 | /* In driver-rs6000.c. */ | |
213 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
214 | #define EXTRA_SPEC_FUNCTIONS \ | |
215 | { "local_cpu_detect", host_detect_local_cpu }, | |
216 | #define HAVE_LOCAL_CPU_DETECT | |
cacf1ca8 MM |
217 | #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
218 | ||
219 | #else | |
220 | #define ASM_CPU_NATIVE_SPEC "%(asm_default)" | |
0eab6840 DE |
221 | #endif |
222 | ||
ee7caeb3 DE |
223 | #ifndef CC1_CPU_SPEC |
224 | #ifdef HAVE_LOCAL_CPU_DETECT | |
0eab6840 DE |
225 | #define CC1_CPU_SPEC \ |
226 | "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
227 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
ee7caeb3 DE |
228 | #else |
229 | #define CC1_CPU_SPEC "" | |
230 | #endif | |
0eab6840 DE |
231 | #endif |
232 | ||
fb623df5 | 233 | /* Architecture type. */ |
f045b2c9 | 234 | |
bb22512c | 235 | /* Define TARGET_MFCRF if the target assembler does not support the |
78f5898b | 236 | optional field operand for mfcr. */ |
fb623df5 | 237 | |
78f5898b | 238 | #ifndef HAVE_AS_MFCRF |
432218ba | 239 | #undef TARGET_MFCRF |
ffa22984 DE |
240 | #define TARGET_MFCRF 0 |
241 | #endif | |
242 | ||
0fa2e4df | 243 | /* Define TARGET_POPCNTB if the target assembler does not support the |
432218ba DE |
244 | popcount byte instruction. */ |
245 | ||
246 | #ifndef HAVE_AS_POPCNTB | |
247 | #undef TARGET_POPCNTB | |
248 | #define TARGET_POPCNTB 0 | |
249 | #endif | |
250 | ||
9719f3b7 DE |
251 | /* Define TARGET_FPRND if the target assembler does not support the |
252 | fp rounding instructions. */ | |
253 | ||
254 | #ifndef HAVE_AS_FPRND | |
255 | #undef TARGET_FPRND | |
256 | #define TARGET_FPRND 0 | |
257 | #endif | |
258 | ||
b639c3c2 JJ |
259 | /* Define TARGET_CMPB if the target assembler does not support the |
260 | cmpb instruction. */ | |
261 | ||
262 | #ifndef HAVE_AS_CMPB | |
263 | #undef TARGET_CMPB | |
264 | #define TARGET_CMPB 0 | |
265 | #endif | |
266 | ||
44cd321e PS |
267 | /* Define TARGET_MFPGPR if the target assembler does not support the |
268 | mffpr and mftgpr instructions. */ | |
269 | ||
270 | #ifndef HAVE_AS_MFPGPR | |
271 | #undef TARGET_MFPGPR | |
272 | #define TARGET_MFPGPR 0 | |
273 | #endif | |
274 | ||
b639c3c2 JJ |
275 | /* Define TARGET_DFP if the target assembler does not support decimal |
276 | floating point instructions. */ | |
277 | #ifndef HAVE_AS_DFP | |
278 | #undef TARGET_DFP | |
279 | #define TARGET_DFP 0 | |
280 | #endif | |
281 | ||
cacf1ca8 MM |
282 | /* Define TARGET_POPCNTD if the target assembler does not support the |
283 | popcount word and double word instructions. */ | |
284 | ||
285 | #ifndef HAVE_AS_POPCNTD | |
286 | #undef TARGET_POPCNTD | |
287 | #define TARGET_POPCNTD 0 | |
288 | #endif | |
289 | ||
f62511da MM |
290 | /* Define the ISA 2.07 flags as 0 if the target assembler does not support the |
291 | waitasecond instruction. Allow -mpower8-fusion, since it does not add new | |
292 | instructions. */ | |
293 | ||
294 | #ifndef HAVE_AS_POWER8 | |
295 | #undef TARGET_DIRECT_MOVE | |
296 | #undef TARGET_CRYPTO | |
0258b6e4 | 297 | #undef TARGET_HTM |
f62511da MM |
298 | #undef TARGET_P8_VECTOR |
299 | #define TARGET_DIRECT_MOVE 0 | |
300 | #define TARGET_CRYPTO 0 | |
0258b6e4 | 301 | #define TARGET_HTM 0 |
f62511da MM |
302 | #define TARGET_P8_VECTOR 0 |
303 | #endif | |
304 | ||
cacf1ca8 MM |
305 | /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If |
306 | not, generate the lwsync code as an integer constant. */ | |
307 | #ifdef HAVE_AS_LWSYNC | |
308 | #define TARGET_LWSYNC_INSTRUCTION 1 | |
309 | #else | |
310 | #define TARGET_LWSYNC_INSTRUCTION 0 | |
311 | #endif | |
312 | ||
9752c4ad AM |
313 | /* Define TARGET_TLS_MARKERS if the target assembler does not support |
314 | arg markers for __tls_get_addr calls. */ | |
315 | #ifndef HAVE_AS_TLS_MARKERS | |
316 | #undef TARGET_TLS_MARKERS | |
317 | #define TARGET_TLS_MARKERS 0 | |
318 | #else | |
319 | #define TARGET_TLS_MARKERS tls_markers | |
320 | #endif | |
321 | ||
7f970b70 AM |
322 | #ifndef TARGET_SECURE_PLT |
323 | #define TARGET_SECURE_PLT 0 | |
324 | #endif | |
325 | ||
070b27da AM |
326 | #ifndef TARGET_CMODEL |
327 | #define TARGET_CMODEL CMODEL_SMALL | |
328 | #endif | |
329 | ||
2f3e5814 | 330 | #define TARGET_32BIT (! TARGET_64BIT) |
d14a6d05 | 331 | |
c4501e62 JJ |
332 | #ifndef HAVE_AS_TLS |
333 | #define HAVE_AS_TLS 0 | |
334 | #endif | |
335 | ||
be26142a PB |
336 | #ifndef TARGET_LINK_STACK |
337 | #define TARGET_LINK_STACK 0 | |
338 | #endif | |
339 | ||
340 | #ifndef SET_TARGET_LINK_STACK | |
341 | #define SET_TARGET_LINK_STACK(X) do { } while (0) | |
342 | #endif | |
343 | ||
48d72335 DE |
344 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ |
345 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
346 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
347 | ||
996ed075 JJ |
348 | #ifdef IN_LIBGCC2 |
349 | /* For libgcc2 we make sure this is a compile time constant */ | |
67796c1f | 350 | #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) |
78f5898b | 351 | #undef TARGET_POWERPC64 |
996ed075 JJ |
352 | #define TARGET_POWERPC64 1 |
353 | #else | |
78f5898b | 354 | #undef TARGET_POWERPC64 |
996ed075 JJ |
355 | #define TARGET_POWERPC64 0 |
356 | #endif | |
b6c9286a | 357 | #else |
78f5898b | 358 | /* The option machinery will define this. */ |
b6c9286a MM |
359 | #endif |
360 | ||
c28a7c24 | 361 | #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) |
9ebbca7d | 362 | |
696e45ba ME |
363 | /* FPU operations supported. |
364 | Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must | |
365 | also test TARGET_HARD_FLOAT. */ | |
366 | #define TARGET_SINGLE_FLOAT 1 | |
367 | #define TARGET_DOUBLE_FLOAT 1 | |
368 | #define TARGET_SINGLE_FPU 0 | |
369 | #define TARGET_SIMPLE_FPU 0 | |
0bb7b92e | 370 | #define TARGET_XILINX_FPU 0 |
696e45ba | 371 | |
fb623df5 RK |
372 | /* Recast the processor type to the cpu attribute. */ |
373 | #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) | |
374 | ||
8482e358 | 375 | /* Define generic processor types based upon current deployment. */ |
3cb999d8 | 376 | #define PROCESSOR_COMMON PROCESSOR_PPC601 |
3cb999d8 DE |
377 | #define PROCESSOR_POWERPC PROCESSOR_PPC604 |
378 | #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
6e151478 | 379 | |
fb623df5 | 380 | /* Define the default processor. This is overridden by other tm.h files. */ |
f3061fa4 | 381 | #define PROCESSOR_DEFAULT PROCESSOR_PPC603 |
3cb999d8 | 382 | #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A |
fb623df5 | 383 | |
59ac9a55 JJ |
384 | /* Specify the dialect of assembler to use. Only new mnemonics are supported |
385 | starting with GCC 4.8, i.e. just one dialect, but for backwards | |
386 | compatibility with older inline asm ASSEMBLER_DIALECT needs to be | |
387 | defined. */ | |
388 | #define ASSEMBLER_DIALECT 1 | |
389 | ||
38c1f2d7 | 390 | /* Debug support */ |
fd438373 MM |
391 | #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
392 | #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ | |
393 | #define MASK_DEBUG_REG 0x04 /* debug register handling */ | |
394 | #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ | |
395 | #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ | |
396 | #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ | |
7fa14a01 | 397 | #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ |
fd438373 MM |
398 | #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
399 | | MASK_DEBUG_ARG \ | |
400 | | MASK_DEBUG_REG \ | |
401 | | MASK_DEBUG_ADDR \ | |
402 | | MASK_DEBUG_COST \ | |
7fa14a01 MM |
403 | | MASK_DEBUG_TARGET \ |
404 | | MASK_DEBUG_BUILTIN) | |
fd438373 MM |
405 | |
406 | #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) | |
407 | #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) | |
408 | #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) | |
409 | #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) | |
410 | #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) | |
411 | #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) | |
7fa14a01 | 412 | #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) |
cacf1ca8 | 413 | |
2c83faf8 MM |
414 | /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM |
415 | long double format that uses a pair of doubles, or IEEE 128-bit floating | |
416 | point. KFmode was added as a way to represent IEEE 128-bit floating point, | |
417 | even if the default for long double is the IBM long double format. | |
418 | Similarly IFmode is the IBM long double format even if the default is IEEE | |
419 | 128-bit. */ | |
420 | #define FLOAT128_IEEE_P(MODE) \ | |
421 | (((MODE) == TFmode && TARGET_IEEEQUAD) \ | |
422 | || ((MODE) == KFmode)) | |
423 | ||
424 | #define FLOAT128_IBM_P(MODE) \ | |
425 | (((MODE) == TFmode && !TARGET_IEEEQUAD) \ | |
426 | || ((MODE) == IFmode)) | |
427 | ||
428 | /* Helper macros to say whether a 128-bit floating point type can go in a | |
429 | single vector register, or whether it needs paired scalar values. */ | |
430 | #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128 && FLOAT128_IEEE_P (MODE)) | |
431 | ||
432 | #define FLOAT128_2REG_P(MODE) \ | |
433 | (FLOAT128_IBM_P (MODE) \ | |
434 | || ((MODE) == TDmode) \ | |
435 | || (!TARGET_FLOAT128 && FLOAT128_IEEE_P (MODE))) | |
436 | ||
437 | /* Return true for floating point that does not use a vector register. */ | |
438 | #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ | |
439 | (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) | |
440 | ||
f62511da | 441 | /* Describe the vector unit used for arithmetic operations. */ |
cacf1ca8 MM |
442 | extern enum rs6000_vector rs6000_vector_unit[]; |
443 | ||
444 | #define VECTOR_UNIT_NONE_P(MODE) \ | |
445 | (rs6000_vector_unit[(MODE)] == VECTOR_NONE) | |
446 | ||
447 | #define VECTOR_UNIT_VSX_P(MODE) \ | |
448 | (rs6000_vector_unit[(MODE)] == VECTOR_VSX) | |
449 | ||
f62511da MM |
450 | #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ |
451 | (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) | |
452 | ||
cacf1ca8 MM |
453 | #define VECTOR_UNIT_ALTIVEC_P(MODE) \ |
454 | (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) | |
455 | ||
f62511da MM |
456 | #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ |
457 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ | |
458 | (int)VECTOR_VSX, \ | |
459 | (int)VECTOR_P8_VECTOR)) | |
460 | ||
461 | /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either | |
462 | altivec (VMX) or VSX vector instructions. P8 vector support is upwards | |
463 | compatible, so allow it as well, rather than changing all of the uses of the | |
464 | macro. */ | |
cacf1ca8 | 465 | #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ |
f62511da MM |
466 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ |
467 | (int)VECTOR_ALTIVEC, \ | |
468 | (int)VECTOR_P8_VECTOR)) | |
cacf1ca8 MM |
469 | |
470 | /* Describe whether to use VSX loads or Altivec loads. For now, just use the | |
471 | same unit as the vector unit we are using, but we may want to migrate to | |
472 | using VSX style loads even for types handled by altivec. */ | |
473 | extern enum rs6000_vector rs6000_vector_mem[]; | |
474 | ||
475 | #define VECTOR_MEM_NONE_P(MODE) \ | |
476 | (rs6000_vector_mem[(MODE)] == VECTOR_NONE) | |
477 | ||
478 | #define VECTOR_MEM_VSX_P(MODE) \ | |
479 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
480 | ||
f62511da MM |
481 | #define VECTOR_MEM_P8_VECTOR_P(MODE) \ |
482 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
483 | ||
cacf1ca8 MM |
484 | #define VECTOR_MEM_ALTIVEC_P(MODE) \ |
485 | (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) | |
486 | ||
f62511da MM |
487 | #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ |
488 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ | |
489 | (int)VECTOR_VSX, \ | |
490 | (int)VECTOR_P8_VECTOR)) | |
491 | ||
cacf1ca8 | 492 | #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ |
f62511da MM |
493 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ |
494 | (int)VECTOR_ALTIVEC, \ | |
495 | (int)VECTOR_P8_VECTOR)) | |
cacf1ca8 MM |
496 | |
497 | /* Return the alignment of a given vector type, which is set based on the | |
498 | vector unit use. VSX for instance can load 32 or 64 bit aligned words | |
499 | without problems, while Altivec requires 128-bit aligned vectors. */ | |
500 | extern int rs6000_vector_align[]; | |
501 | ||
502 | #define VECTOR_ALIGN(MODE) \ | |
503 | ((rs6000_vector_align[(MODE)] != 0) \ | |
504 | ? rs6000_vector_align[(MODE)] \ | |
505 | : (int)GET_MODE_BITSIZE ((MODE))) | |
506 | ||
6edc217d BS |
507 | /* Determine the element order to use for vector instructions. By |
508 | default we use big-endian element order when targeting big-endian, | |
509 | and little-endian element order when targeting little-endian. For | |
510 | programs being ported from BE Power to LE Power, it can sometimes | |
511 | be useful to use big-endian element order when targeting little-endian. | |
512 | This is set via -maltivec=be, for example. */ | |
513 | #define VECTOR_ELT_ORDER_BIG \ | |
514 | (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) | |
515 | ||
117f16fb MM |
516 | /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
517 | with scalar instructions. */ | |
518 | #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) | |
519 | ||
dd551aa1 MM |
520 | /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
521 | with the ISA 3.0 MFVSRLD instructions. */ | |
522 | #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) | |
523 | ||
025d9908 KH |
524 | /* Alignment options for fields in structures for sub-targets following |
525 | AIX-like ABI. | |
526 | ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
527 | ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
528 | ||
529 | Override the macro definitions when compiling libobjc to avoid undefined | |
530 | reference to rs6000_alignment_flags due to library's use of GCC alignment | |
531 | macros which use the macros below. */ | |
f676971a | 532 | |
025d9908 KH |
533 | #ifndef IN_TARGET_LIBS |
534 | #define MASK_ALIGN_POWER 0x00000000 | |
535 | #define MASK_ALIGN_NATURAL 0x00000001 | |
536 | #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
537 | #else | |
538 | #define TARGET_ALIGN_NATURAL 0 | |
539 | #endif | |
6fa3f289 ZW |
540 | |
541 | #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) | |
602ea4d3 | 542 | #define TARGET_IEEEQUAD rs6000_ieeequad |
6fa3f289 | 543 | #define TARGET_ALTIVEC_ABI rs6000_altivec_abi |
cacf1ca8 | 544 | #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
6fa3f289 | 545 | |
a3170dc6 AH |
546 | #define TARGET_SPE_ABI 0 |
547 | #define TARGET_SPE 0 | |
cacf1ca8 | 548 | #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) |
a3170dc6 | 549 | #define TARGET_FPRS 1 |
4d4cbc0e AH |
550 | #define TARGET_E500_SINGLE 0 |
551 | #define TARGET_E500_DOUBLE 0 | |
eca0d5e8 | 552 | #define CHECK_E500_OPTIONS do { } while (0) |
a3170dc6 | 553 | |
7042fe5e MM |
554 | /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
555 | Enable 32-bit fcfid's on any of the switches for newer ISA machines or | |
556 | XILINX. */ | |
c3f8384f MM |
557 | #define TARGET_FCFID (TARGET_POWERPC64 \ |
558 | || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
559 | || TARGET_POPCNTB /* ISA 2.02 */ \ | |
560 | || TARGET_CMPB /* ISA 2.05 */ \ | |
561 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
7042fe5e MM |
562 | || TARGET_XILINX_FPU) |
563 | ||
564 | #define TARGET_FCTIDZ TARGET_FCFID | |
565 | #define TARGET_STFIWX TARGET_PPC_GFXOPT | |
566 | #define TARGET_LFIWAX TARGET_CMPB | |
567 | #define TARGET_LFIWZX TARGET_POPCNTD | |
568 | #define TARGET_FCFIDS TARGET_POPCNTD | |
569 | #define TARGET_FCFIDU TARGET_POPCNTD | |
570 | #define TARGET_FCFIDUS TARGET_POPCNTD | |
571 | #define TARGET_FCTIDUZ TARGET_POPCNTD | |
572 | #define TARGET_FCTIWUZ TARGET_POPCNTD | |
0299bc72 MM |
573 | #define TARGET_CTZ TARGET_MODULO |
574 | #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) | |
dd551aa1 | 575 | #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) |
7042fe5e | 576 | |
f62511da MM |
577 | #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) |
578 | #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
a16a872d | 579 | #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) |
dd551aa1 MM |
580 | #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ |
581 | && TARGET_POWERPC64) | |
f62511da MM |
582 | |
583 | /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present | |
584 | in power7, so conditionalize them on p8 features. TImode syncs need quad | |
585 | memory support. */ | |
b846c948 MM |
586 | #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ |
587 | || TARGET_QUAD_MEMORY_ATOMIC \ | |
588 | || TARGET_DIRECT_MOVE) | |
589 | ||
590 | #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC | |
f62511da | 591 | |
c6d5ff83 MM |
592 | /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need |
593 | to allocate the SDmode stack slot to get the value into the proper location | |
594 | in the register. */ | |
595 | #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) | |
596 | ||
4d967549 MM |
597 | /* In switching from using target_flags to using rs6000_isa_flags, the options |
598 | machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map | |
599 | OPTION_MASK_<xxx> back into MASK_<xxx>. */ | |
600 | #define MASK_ALTIVEC OPTION_MASK_ALTIVEC | |
601 | #define MASK_CMPB OPTION_MASK_CMPB | |
f62511da | 602 | #define MASK_CRYPTO OPTION_MASK_CRYPTO |
4d967549 | 603 | #define MASK_DFP OPTION_MASK_DFP |
f62511da | 604 | #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE |
4d967549 MM |
605 | #define MASK_DLMZB OPTION_MASK_DLMZB |
606 | #define MASK_EABI OPTION_MASK_EABI | |
607 | #define MASK_FPRND OPTION_MASK_FPRND | |
f62511da | 608 | #define MASK_P8_FUSION OPTION_MASK_P8_FUSION |
4d967549 | 609 | #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT |
0258b6e4 | 610 | #define MASK_HTM OPTION_MASK_HTM |
4d967549 MM |
611 | #define MASK_ISEL OPTION_MASK_ISEL |
612 | #define MASK_MFCRF OPTION_MASK_MFCRF | |
613 | #define MASK_MFPGPR OPTION_MASK_MFPGPR | |
614 | #define MASK_MULHW OPTION_MASK_MULHW | |
615 | #define MASK_MULTIPLE OPTION_MASK_MULTIPLE | |
616 | #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE | |
f62511da | 617 | #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR |
8fa97501 | 618 | #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR |
4d967549 MM |
619 | #define MASK_POPCNTB OPTION_MASK_POPCNTB |
620 | #define MASK_POPCNTD OPTION_MASK_POPCNTD | |
621 | #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT | |
622 | #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT | |
623 | #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION | |
624 | #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT | |
625 | #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN | |
626 | #define MASK_STRING OPTION_MASK_STRING | |
627 | #define MASK_UPDATE OPTION_MASK_UPDATE | |
628 | #define MASK_VSX OPTION_MASK_VSX | |
c6d5ff83 | 629 | #define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE |
4d967549 MM |
630 | |
631 | #ifndef IN_LIBGCC2 | |
632 | #define MASK_POWERPC64 OPTION_MASK_POWERPC64 | |
633 | #endif | |
634 | ||
635 | #ifdef TARGET_64BIT | |
636 | #define MASK_64BIT OPTION_MASK_64BIT | |
637 | #endif | |
638 | ||
639 | #ifdef TARGET_RELOCATABLE | |
640 | #define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE | |
641 | #endif | |
642 | ||
643 | #ifdef TARGET_LITTLE_ENDIAN | |
644 | #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN | |
645 | #endif | |
646 | ||
647 | #ifdef TARGET_MINIMAL_TOC | |
648 | #define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC | |
649 | #endif | |
650 | ||
651 | #ifdef TARGET_REGNAMES | |
652 | #define MASK_REGNAMES OPTION_MASK_REGNAMES | |
653 | #endif | |
654 | ||
655 | #ifdef TARGET_PROTOTYPE | |
656 | #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE | |
657 | #endif | |
658 | ||
7fa14a01 MM |
659 | /* For power systems, we want to enable Altivec and VSX builtins even if the |
660 | user did not use -maltivec or -mvsx to allow the builtins to be used inside | |
661 | of #pragma GCC target or the target attribute to change the code level for a | |
662 | given system. The SPE and Paired builtins are only enabled if you configure | |
663 | the compiler for those builtins, and those machines don't support altivec or | |
664 | VSX. */ | |
665 | ||
666 | #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \ | |
667 | && ((TARGET_POWERPC64 \ | |
c3f8384f | 668 | || TARGET_PPC_GPOPT /* 970/power4 */ \ |
7fa14a01 MM |
669 | || TARGET_POPCNTB /* ISA 2.02 */ \ |
670 | || TARGET_CMPB /* ISA 2.05 */ \ | |
671 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
672 | || TARGET_ALTIVEC \ | |
f93bc5b3 PB |
673 | || TARGET_VSX \ |
674 | || TARGET_HARD_FLOAT))) | |
7fa14a01 | 675 | |
a7c6c6d6 OH |
676 | /* E500 cores only support plain "sync", not lwsync. */ |
677 | #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | |
678 | || rs6000_cpu == PROCESSOR_PPC8548) | |
7fa14a01 MM |
679 | |
680 | ||
0609bdf2 MM |
681 | /* Whether SF/DF operations are supported on the E500. */ |
682 | #define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \ | |
683 | && !TARGET_FPRS) | |
684 | ||
685 | #define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ | |
686 | && !TARGET_FPRS && TARGET_E500_DOUBLE) | |
687 | ||
026c3cfd | 688 | /* Whether SF/DF operations are supported by the normal floating point unit |
0609bdf2 MM |
689 | (or the vector/scalar unit). */ |
690 | #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ | |
691 | && TARGET_SINGLE_FLOAT) | |
692 | ||
693 | #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ | |
694 | && TARGET_DOUBLE_FLOAT) | |
695 | ||
696 | /* Whether SF/DF operations are supported by any hardware. */ | |
697 | #define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE) | |
698 | #define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE) | |
699 | ||
92902797 MM |
700 | /* Which machine supports the various reciprocal estimate instructions. */ |
701 | #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ | |
702 | && TARGET_FPRS && TARGET_SINGLE_FLOAT) | |
703 | ||
704 | #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ | |
705 | && TARGET_DOUBLE_FLOAT \ | |
706 | && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) | |
707 | ||
708 | #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ | |
709 | && TARGET_FPRS && TARGET_SINGLE_FLOAT) | |
710 | ||
711 | #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ | |
712 | && TARGET_DOUBLE_FLOAT \ | |
713 | && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) | |
714 | ||
0299bc72 MM |
715 | /* Conditions to allow TOC fusion for loading/storing integers. */ |
716 | #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \ | |
717 | && TARGET_TOC_FUSION \ | |
718 | && (TARGET_CMODEL != CMODEL_SMALL) \ | |
719 | && TARGET_POWERPC64) | |
720 | ||
721 | /* Conditions to allow TOC fusion for loading/storing floating point. */ | |
722 | #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \ | |
723 | && TARGET_TOC_FUSION \ | |
724 | && (TARGET_CMODEL != CMODEL_SMALL) \ | |
725 | && TARGET_POWERPC64 \ | |
726 | && TARGET_HARD_FLOAT \ | |
727 | && TARGET_FPRS \ | |
728 | && TARGET_SINGLE_FLOAT \ | |
729 | && TARGET_DOUBLE_FLOAT) | |
730 | ||
92902797 MM |
731 | /* Whether the various reciprocal divide/square root estimate instructions |
732 | exist, and whether we should automatically generate code for the instruction | |
733 | by default. */ | |
734 | #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ | |
735 | #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ | |
736 | #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ | |
737 | #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ | |
738 | ||
739 | extern unsigned char rs6000_recip_bits[]; | |
740 | ||
741 | #define RS6000_RECIP_HAVE_RE_P(MODE) \ | |
742 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) | |
743 | ||
744 | #define RS6000_RECIP_AUTO_RE_P(MODE) \ | |
745 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) | |
746 | ||
747 | #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ | |
748 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) | |
749 | ||
750 | #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ | |
751 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) | |
752 | ||
c5387660 JM |
753 | /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
754 | #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT | |
f045b2c9 | 755 | |
a5c76ee6 | 756 | /* Target pragma. */ |
c58b209a NB |
757 | #define REGISTER_TARGET_PRAGMAS() do { \ |
758 | c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
fd438373 | 759 | targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
2fab365e | 760 | targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
7fa14a01 | 761 | rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ |
a5c76ee6 ZW |
762 | } while (0) |
763 | ||
4c4eb375 GK |
764 | /* Target #defines. */ |
765 | #define TARGET_CPU_CPP_BUILTINS() \ | |
766 | rs6000_cpu_cpp_builtins (pfile) | |
647d340d JT |
767 | |
768 | /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
769 | we're compiling for. Some configurations may need to override it. */ | |
770 | #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
771 | do \ | |
772 | { \ | |
773 | if (BYTES_BIG_ENDIAN) \ | |
774 | { \ | |
775 | builtin_define ("__BIG_ENDIAN__"); \ | |
776 | builtin_define ("_BIG_ENDIAN"); \ | |
777 | builtin_assert ("machine=bigendian"); \ | |
778 | } \ | |
779 | else \ | |
780 | { \ | |
781 | builtin_define ("__LITTLE_ENDIAN__"); \ | |
782 | builtin_define ("_LITTLE_ENDIAN"); \ | |
783 | builtin_assert ("machine=littleendian"); \ | |
784 | } \ | |
785 | } \ | |
786 | while (0) | |
f045b2c9 | 787 | \f |
4c4eb375 | 788 | /* Target machine storage layout. */ |
f045b2c9 | 789 | |
13d39dbc | 790 | /* Define this macro if it is advisable to hold scalars in registers |
c81bebd7 | 791 | in a wider mode than that declared by the program. In such cases, |
ef457bda RK |
792 | the value is constrained to be within the bounds of the declared |
793 | type, but kept valid in the wider mode. The signedness of the | |
794 | extension may differ from that of the type. */ | |
795 | ||
39403d82 DE |
796 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
797 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
96922e4c | 798 | && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ |
b78d48dd | 799 | (MODE) = TARGET_32BIT ? SImode : DImode; |
39403d82 | 800 | |
f045b2c9 | 801 | /* Define this if most significant bit is lowest numbered |
82e41834 KH |
802 | in instructions that operate on numbered bit-fields. */ |
803 | /* That is true on RS/6000. */ | |
f045b2c9 RS |
804 | #define BITS_BIG_ENDIAN 1 |
805 | ||
806 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
807 | /* That is true on RS/6000. */ | |
808 | #define BYTES_BIG_ENDIAN 1 | |
809 | ||
810 | /* Define this if most significant word of a multiword number is lowest | |
c81bebd7 | 811 | numbered. |
f045b2c9 RS |
812 | |
813 | For RS/6000 we can decide arbitrarily since there are no machine | |
82e41834 | 814 | instructions for them. Might as well be consistent with bits and bytes. */ |
f045b2c9 RS |
815 | #define WORDS_BIG_ENDIAN 1 |
816 | ||
50751417 AM |
817 | /* This says that for the IBM long double the larger magnitude double |
818 | comes first. It's really a two element double array, and arrays | |
819 | don't index differently between little- and big-endian. */ | |
820 | #define LONG_DOUBLE_LARGE_FIRST 1 | |
821 | ||
2e360ab3 | 822 | #define MAX_BITS_PER_WORD 64 |
f045b2c9 RS |
823 | |
824 | /* Width of a word, in units (bytes). */ | |
c1aa3958 | 825 | #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) |
f34fc46e DE |
826 | #ifdef IN_LIBGCC2 |
827 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
828 | #else | |
ef0e53ce | 829 | #define MIN_UNITS_PER_WORD 4 |
f34fc46e | 830 | #endif |
2e360ab3 | 831 | #define UNITS_PER_FP_WORD 8 |
0ac081f6 | 832 | #define UNITS_PER_ALTIVEC_WORD 16 |
cacf1ca8 | 833 | #define UNITS_PER_VSX_WORD 16 |
a3170dc6 | 834 | #define UNITS_PER_SPE_WORD 8 |
96038623 | 835 | #define UNITS_PER_PAIRED_WORD 8 |
f045b2c9 | 836 | |
915f619f JW |
837 | /* Type used for ptrdiff_t, as a string used in a declaration. */ |
838 | #define PTRDIFF_TYPE "int" | |
839 | ||
058ef853 DE |
840 | /* Type used for size_t, as a string used in a declaration. */ |
841 | #define SIZE_TYPE "long unsigned int" | |
842 | ||
f045b2c9 RS |
843 | /* Type used for wchar_t, as a string used in a declaration. */ |
844 | #define WCHAR_TYPE "short unsigned int" | |
845 | ||
846 | /* Width of wchar_t in bits. */ | |
847 | #define WCHAR_TYPE_SIZE 16 | |
848 | ||
9e654916 RK |
849 | /* A C expression for the size in bits of the type `short' on the |
850 | target machine. If you don't define this, the default is half a | |
851 | word. (If this would be less than one storage unit, it is | |
852 | rounded up to one unit.) */ | |
853 | #define SHORT_TYPE_SIZE 16 | |
854 | ||
855 | /* A C expression for the size in bits of the type `int' on the | |
856 | target machine. If you don't define this, the default is one | |
857 | word. */ | |
19d2d16f | 858 | #define INT_TYPE_SIZE 32 |
9e654916 RK |
859 | |
860 | /* A C expression for the size in bits of the type `long' on the | |
861 | target machine. If you don't define this, the default is one | |
862 | word. */ | |
2f3e5814 | 863 | #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) |
9e654916 RK |
864 | |
865 | /* A C expression for the size in bits of the type `long long' on the | |
866 | target machine. If you don't define this, the default is two | |
867 | words. */ | |
868 | #define LONG_LONG_TYPE_SIZE 64 | |
869 | ||
9e654916 RK |
870 | /* A C expression for the size in bits of the type `float' on the |
871 | target machine. If you don't define this, the default is one | |
872 | word. */ | |
873 | #define FLOAT_TYPE_SIZE 32 | |
874 | ||
875 | /* A C expression for the size in bits of the type `double' on the | |
876 | target machine. If you don't define this, the default is two | |
877 | words. */ | |
878 | #define DOUBLE_TYPE_SIZE 64 | |
879 | ||
880 | /* A C expression for the size in bits of the type `long double' on | |
881 | the target machine. If you don't define this, the default is two | |
882 | words. */ | |
6fa3f289 | 883 | #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
06f4e019 | 884 | |
5b8f5865 DE |
885 | /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ |
886 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
887 | ||
f045b2c9 RS |
888 | /* Width in bits of a pointer. |
889 | See also the macro `Pmode' defined below. */ | |
cacf1ca8 MM |
890 | extern unsigned rs6000_pointer_size; |
891 | #define POINTER_SIZE rs6000_pointer_size | |
f045b2c9 RS |
892 | |
893 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
2f3e5814 | 894 | #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
895 | |
896 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
cacf1ca8 MM |
897 | #define STACK_BOUNDARY \ |
898 | ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ | |
899 | ? 64 : 128) | |
f045b2c9 RS |
900 | |
901 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
902 | #define FUNCTION_BOUNDARY 32 | |
903 | ||
904 | /* No data type wants to be aligned rounder than this. */ | |
0ac081f6 AH |
905 | #define BIGGEST_ALIGNMENT 128 |
906 | ||
f045b2c9 RS |
907 | /* Alignment of field after `int : 0' in a structure. */ |
908 | #define EMPTY_FIELD_BOUNDARY 32 | |
909 | ||
910 | /* Every structure's size must be a multiple of this. */ | |
911 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
912 | ||
43a88a8c | 913 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
f045b2c9 RS |
914 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
915 | ||
69eff9da AM |
916 | enum data_align { align_abi, align_opt, align_both }; |
917 | ||
918 | /* A C expression to compute the alignment for a variables in the | |
919 | local store. TYPE is the data type, and ALIGN is the alignment | |
920 | that the object would ordinarily have. */ | |
921 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
922 | rs6000_data_alignment (TYPE, ALIGN, align_both) | |
923 | ||
924 | /* Make strings word-aligned so strcpy from constants will be faster. */ | |
69ef87e2 AH |
925 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
926 | (TREE_CODE (EXP) == STRING_CST \ | |
153fbec8 | 927 | && (STRICT_ALIGNMENT || !optimize_size) \ |
69ef87e2 AH |
928 | && (ALIGN) < BITS_PER_WORD \ |
929 | ? BITS_PER_WORD \ | |
930 | : (ALIGN)) | |
f045b2c9 | 931 | |
69eff9da AM |
932 | /* Make arrays of chars word-aligned for the same reasons. */ |
933 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
934 | rs6000_data_alignment (TYPE, ALIGN, align_opt) | |
935 | ||
936 | /* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to | |
f82f556d | 937 | 64 bits. */ |
69eff9da AM |
938 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ |
939 | rs6000_data_alignment (TYPE, ALIGN, align_abi) | |
f045b2c9 | 940 | |
a0ab749a | 941 | /* Nonzero if move instructions will actually fail to work |
f045b2c9 | 942 | when given unaligned data. */ |
fdaff8ba | 943 | #define STRICT_ALIGNMENT 0 |
e1565e65 DE |
944 | |
945 | /* Define this macro to be the value 1 if unaligned accesses have a cost | |
946 | many times greater than aligned accesses, for example if they are | |
947 | emulated in a trap handler. */ | |
cacf1ca8 MM |
948 | /* Altivec vector memory instructions simply ignore the low bits; SPE vector |
949 | memory instructions trap on unaligned accesses; VSX memory instructions are | |
950 | aligned to 4 or 8 bytes. */ | |
41543739 GK |
951 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ |
952 | (STRICT_ALIGNMENT \ | |
2c83faf8 | 953 | || (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) && (ALIGN) < 32) \ |
047b83ff | 954 | || (!TARGET_EFFICIENT_UNALIGNED_VSX \ |
2c83faf8 MM |
955 | && ((VECTOR_MODE_P (MODE) || FLOAT128_VECTOR_P (MODE)) \ |
956 | && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))) | |
cacf1ca8 | 957 | |
f045b2c9 RS |
958 | \f |
959 | /* Standard register usage. */ | |
960 | ||
961 | /* Number of actual hardware registers. | |
962 | The hardware registers are assigned numbers for the compiler | |
963 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
964 | All registers that the compiler knows about must be given numbers, | |
965 | even those that are not normally considered general registers. | |
966 | ||
967 | RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
462f7901 SB |
968 | a count register, a link register, and 8 condition register fields, |
969 | which we view here as separate registers. AltiVec adds 32 vector | |
970 | registers and a VRsave register. | |
f045b2c9 RS |
971 | |
972 | In addition, the difference between the frame and argument pointers is | |
973 | a function of the number of registers saved, so we need to have a | |
974 | register for AP that will later be eliminated in favor of SP or FP. | |
802a0058 | 975 | This is a normal register, but it is fixed. |
f045b2c9 | 976 | |
802a0058 MM |
977 | We also create a pseudo register for float/int conversions, that will |
978 | really represent the memory location used. It is represented here as | |
979 | a register, in order to work around problems in allocating stack storage | |
7d5175e1 | 980 | in inline functions. |
802a0058 | 981 | |
7d5175e1 | 982 | Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame |
7a5add18 PB |
983 | pointer, which is eventually eliminated in favor of SP or FP. |
984 | ||
985 | The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ | |
7d5175e1 | 986 | |
23742a9e | 987 | #define FIRST_PSEUDO_REGISTER 149 |
f045b2c9 | 988 | |
d6a7951f | 989 | /* This must be included for pre gcc 3.0 glibc compatibility. */ |
7d5f33bc | 990 | #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 |
62153b61 | 991 | |
23742a9e RAR |
992 | /* True if register is an SPE High register. */ |
993 | #define SPE_HIGH_REGNO_P(N) \ | |
994 | ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO) | |
995 | ||
996 | /* SPE high registers added as hard regs. | |
997 | The sfp register and 3 HTM registers | |
998 | aren't included in DWARF_FRAME_REGISTERS. */ | |
999 | #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) | |
c19de7aa | 1000 | |
93c9d1ba AM |
1001 | /* The SPE has an additional 32 synthetic registers, with DWARF debug |
1002 | info numbering for these registers starting at 1200. While eh_frame | |
1003 | register numbering need not be the same as the debug info numbering, | |
23742a9e | 1004 | we choose to number these regs for eh_frame at 1200 too. |
93c9d1ba AM |
1005 | |
1006 | We must map them here to avoid huge unwinder tables mostly consisting | |
f676971a | 1007 | of unused space. */ |
93c9d1ba | 1008 | #define DWARF_REG_TO_UNWIND_COLUMN(r) \ |
23742a9e | 1009 | ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) |
93c9d1ba | 1010 | |
ed1cf8ff | 1011 | /* Use standard DWARF numbering for DWARF debugging information. */ |
3d36d470 | 1012 | #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) |
ed1cf8ff | 1013 | |
93c9d1ba | 1014 | /* Use gcc hard register numbering for eh_frame. */ |
3d36d470 | 1015 | #define DWARF_FRAME_REGNUM(REGNO) (REGNO) |
41f3a930 | 1016 | |
ed1cf8ff GK |
1017 | /* Map register numbers held in the call frame info that gcc has |
1018 | collected using DWARF_FRAME_REGNUM to those that should be output in | |
3d36d470 UW |
1019 | .debug_frame and .eh_frame. */ |
1020 | #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
1021 | rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1) | |
ed1cf8ff | 1022 | |
f045b2c9 RS |
1023 | /* 1 for registers that have pervasive standard uses |
1024 | and are not available for the register allocator. | |
1025 | ||
5dead3e5 DJ |
1026 | On RS/6000, r1 is used for the stack. On Darwin, r2 is available |
1027 | as a local register; for all other OS's r2 is the TOC pointer. | |
f045b2c9 | 1028 | |
a127c4e5 RK |
1029 | On System V implementations, r13 is fixed and not available for use. */ |
1030 | ||
f045b2c9 | 1031 | #define FIXED_REGISTERS \ |
5dead3e5 | 1032 | {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
1033 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1034 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1035 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
36bd0c3e | 1036 | 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ |
0ac081f6 AH |
1037 | /* AltiVec registers. */ \ |
1038 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1039 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 1040 | 1, 1 \ |
23742a9e RAR |
1041 | , 1, 1, 1, 1, 1, 1, \ |
1042 | /* SPE High registers. */ \ | |
1043 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1044 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ | |
0ac081f6 | 1045 | } |
f045b2c9 RS |
1046 | |
1047 | /* 1 for registers not available across function calls. | |
1048 | These must include the FIXED_REGISTERS and also any | |
1049 | registers that can be used without being saved. | |
1050 | The latter must include the registers where values are returned | |
1051 | and the register where structure-value addresses are passed. | |
1052 | Aside from that, you can include as many other registers as you like. */ | |
1053 | ||
1054 | #define CALL_USED_REGISTERS \ | |
a127c4e5 | 1055 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
1056 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1057 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
1058 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
1059 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
1060 | /* AltiVec registers. */ \ | |
1061 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1062 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 1063 | 1, 1 \ |
23742a9e RAR |
1064 | , 1, 1, 1, 1, 1, 1, \ |
1065 | /* SPE High registers. */ \ | |
1066 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1067 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ | |
0ac081f6 AH |
1068 | } |
1069 | ||
289e96b2 AH |
1070 | /* Like `CALL_USED_REGISTERS' except this macro doesn't require that |
1071 | the entire set of `FIXED_REGISTERS' be included. | |
1072 | (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
1073 | This macro is optional. If not specified, it defaults to the value | |
1074 | of `CALL_USED_REGISTERS'. */ | |
f676971a | 1075 | |
289e96b2 AH |
1076 | #define CALL_REALLY_USED_REGISTERS \ |
1077 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
1078 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1079 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
1080 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1081 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ | |
1082 | /* AltiVec registers. */ \ | |
1083 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1084 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 1085 | 0, 0 \ |
23742a9e RAR |
1086 | , 0, 0, 0, 0, 0, 0, \ |
1087 | /* SPE High registers. */ \ | |
1088 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1089 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ | |
289e96b2 | 1090 | } |
f045b2c9 | 1091 | |
28bcfd4d | 1092 | #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) |
9ebbca7d | 1093 | |
d62294f5 | 1094 | #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) |
b427dd7a AM |
1095 | #define FIRST_SAVED_FP_REGNO (14+32) |
1096 | #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) | |
d62294f5 | 1097 | |
f045b2c9 RS |
1098 | /* List the order in which to allocate registers. Each register must be |
1099 | listed once, even those in FIXED_REGISTERS. | |
1100 | ||
1101 | We allocate in the following order: | |
1102 | fp0 (not saved or used for anything) | |
1103 | fp13 - fp2 (not saved; incoming fp arg registers) | |
1104 | fp1 (not saved; return value) | |
9390387d | 1105 | fp31 - fp14 (saved; order given to save least number) |
36bd0c3e SB |
1106 | cr7, cr5 (not saved or special) |
1107 | cr6 (not saved, but used for vector operations) | |
5accd822 | 1108 | cr1 (not saved, but used for FP operations) |
f045b2c9 | 1109 | cr0 (not saved, but used for arithmetic operations) |
5accd822 | 1110 | cr4, cr3, cr2 (saved) |
f045b2c9 | 1111 | r9 (not saved; best for TImode) |
d44b26bd | 1112 | r10, r8-r4 (not saved; highest first for less conflict with params) |
9390387d | 1113 | r3 (not saved; return value register) |
d44b26bd AM |
1114 | r11 (not saved; later alloc to help shrink-wrap) |
1115 | r0 (not saved; cannot be base reg) | |
f045b2c9 RS |
1116 | r31 - r13 (saved; order given to save least number) |
1117 | r12 (not saved; if used for DImode or DFmode would use r13) | |
f045b2c9 RS |
1118 | ctr (not saved; when we have the choice ctr is better) |
1119 | lr (saved) | |
36bd0c3e | 1120 | r1, r2, ap, ca (fixed) |
9390387d AM |
1121 | v0 - v1 (not saved or used for anything) |
1122 | v13 - v3 (not saved; incoming vector arg registers) | |
1123 | v2 (not saved; incoming vector arg reg; return value) | |
1124 | v19 - v14 (not saved or used for anything) | |
1125 | v31 - v20 (saved; order given to save least number) | |
1126 | vrsave, vscr (fixed) | |
a3170dc6 | 1127 | spe_acc, spefscr (fixed) |
7d5175e1 | 1128 | sfp (fixed) |
0258b6e4 PB |
1129 | tfhar (fixed) |
1130 | tfiar (fixed) | |
1131 | texasr (fixed) | |
0ac081f6 | 1132 | */ |
f676971a | 1133 | |
6b13641d DJ |
1134 | #if FIXED_R2 == 1 |
1135 | #define MAYBE_R2_AVAILABLE | |
1136 | #define MAYBE_R2_FIXED 2, | |
1137 | #else | |
1138 | #define MAYBE_R2_AVAILABLE 2, | |
1139 | #define MAYBE_R2_FIXED | |
1140 | #endif | |
f045b2c9 | 1141 | |
d44b26bd AM |
1142 | #if FIXED_R13 == 1 |
1143 | #define EARLY_R12 12, | |
1144 | #define LATE_R12 | |
1145 | #else | |
1146 | #define EARLY_R12 | |
1147 | #define LATE_R12 12, | |
1148 | #endif | |
1149 | ||
9390387d AM |
1150 | #define REG_ALLOC_ORDER \ |
1151 | {32, \ | |
f62511da MM |
1152 | /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ |
1153 | /* not use fr14 which is a saved register. */ \ | |
1154 | 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ | |
9390387d AM |
1155 | 33, \ |
1156 | 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
1157 | 50, 49, 48, 47, 46, \ | |
36bd0c3e | 1158 | 75, 73, 74, 69, 68, 72, 71, 70, \ |
d44b26bd AM |
1159 | MAYBE_R2_AVAILABLE \ |
1160 | 9, 10, 8, 7, 6, 5, 4, \ | |
1161 | 3, EARLY_R12 11, 0, \ | |
9390387d | 1162 | 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ |
d44b26bd | 1163 | 18, 17, 16, 15, 14, 13, LATE_R12 \ |
462f7901 | 1164 | 66, 65, \ |
36bd0c3e | 1165 | 1, MAYBE_R2_FIXED 67, 76, \ |
9390387d AM |
1166 | /* AltiVec registers. */ \ |
1167 | 77, 78, \ | |
1168 | 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
1169 | 79, \ | |
1170 | 96, 95, 94, 93, 92, 91, \ | |
1171 | 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ | |
1172 | 109, 110, \ | |
23742a9e RAR |
1173 | 111, 112, 113, 114, 115, 116, \ |
1174 | 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \ | |
1175 | 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ | |
1176 | 141, 142, 143, 144, 145, 146, 147, 148 \ | |
0ac081f6 | 1177 | } |
f045b2c9 RS |
1178 | |
1179 | /* True if register is floating-point. */ | |
1180 | #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
1181 | ||
1182 | /* True if register is a condition register. */ | |
1de43f85 | 1183 | #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) |
f045b2c9 | 1184 | |
815cdc52 | 1185 | /* True if register is a condition register, but not cr0. */ |
1de43f85 | 1186 | #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) |
815cdc52 | 1187 | |
f045b2c9 | 1188 | /* True if register is an integer register. */ |
7d5175e1 JJ |
1189 | #define INT_REGNO_P(N) \ |
1190 | ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
f045b2c9 | 1191 | |
a3170dc6 AH |
1192 | /* SPE SIMD registers are just the GPRs. */ |
1193 | #define SPE_SIMD_REGNO_P(N) ((N) <= 31) | |
1194 | ||
96038623 DE |
1195 | /* PAIRED SIMD registers are just the FPRs. */ |
1196 | #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
1197 | ||
f6b5d695 SB |
1198 | /* True if register is the CA register. */ |
1199 | #define CA_REGNO_P(N) ((N) == CA_REGNO) | |
802a0058 | 1200 | |
0ac081f6 AH |
1201 | /* True if register is an AltiVec register. */ |
1202 | #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
1203 | ||
cacf1ca8 MM |
1204 | /* True if register is a VSX register. */ |
1205 | #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) | |
1206 | ||
1207 | /* Alternate name for any vector register supporting floating point, no matter | |
1208 | which instruction set(s) are available. */ | |
1209 | #define VFLOAT_REGNO_P(N) \ | |
1210 | (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) | |
1211 | ||
1212 | /* Alternate name for any vector register supporting integer, no matter which | |
1213 | instruction set(s) are available. */ | |
1214 | #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) | |
1215 | ||
1216 | /* Alternate name for any vector register supporting logical operations, no | |
dd7a40e1 MM |
1217 | matter which instruction set(s) are available. Allow GPRs as well as the |
1218 | vector registers. */ | |
f62511da | 1219 | #define VLOGICAL_REGNO_P(N) \ |
dd7a40e1 MM |
1220 | (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ |
1221 | || (TARGET_VSX && FP_REGNO_P (N))) \ | |
cacf1ca8 | 1222 | |
f045b2c9 | 1223 | /* Return number of consecutive hard regs needed starting at reg REGNO |
d8ecbcdb AH |
1224 | to hold something of mode MODE. */ |
1225 | ||
cacf1ca8 | 1226 | #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] |
0e67400a | 1227 | |
79eefb0d | 1228 | /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
5ec6aff2 MM |
1229 | enough space to account for vectors in FP regs. However, TFmode/TDmode |
1230 | should not use VSX instructions to do a caller save. */ | |
dbcc9f08 MM |
1231 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1232 | (TARGET_VSX \ | |
1233 | && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ | |
5ec6aff2 MM |
1234 | && FP_REGNO_P (REGNO) \ |
1235 | ? V2DFmode \ | |
bbdb5098 | 1236 | : TARGET_E500_DOUBLE && ((MODE) == VOIDmode || (MODE) == DFmode) \ |
5ec6aff2 | 1237 | ? DFmode \ |
2c83faf8 | 1238 | : !TARGET_E500_DOUBLE && FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ |
bbdb5098 MR |
1239 | ? DFmode \ |
1240 | : !TARGET_E500_DOUBLE && (MODE) == TDmode && FP_REGNO_P (REGNO) \ | |
5ec6aff2 | 1241 | ? DImode \ |
79eefb0d PH |
1242 | : choose_hard_reg_mode ((REGNO), (NREGS), false)) |
1243 | ||
3fc841c8 MM |
1244 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ |
1245 | (((TARGET_32BIT && TARGET_POWERPC64 \ | |
1246 | && (GET_MODE_SIZE (MODE) > 4) \ | |
1247 | && INT_REGNO_P (REGNO)) ? 1 : 0) \ | |
1248 | || (TARGET_VSX && FP_REGNO_P (REGNO) \ | |
2c83faf8 | 1249 | && GET_MODE_SIZE (MODE) > 8 && !FLOAT128_2REG_P (MODE))) |
f045b2c9 | 1250 | |
cacf1ca8 MM |
1251 | #define VSX_VECTOR_MODE(MODE) \ |
1252 | ((MODE) == V4SFmode \ | |
1253 | || (MODE) == V2DFmode) \ | |
1254 | ||
bdb60a10 MM |
1255 | /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not |
1256 | really a vector, but we want to treat it as a vector for moves, and | |
1257 | such. */ | |
1258 | ||
1259 | #define ALTIVEC_VECTOR_MODE(MODE) \ | |
1260 | ((MODE) == V16QImode \ | |
1261 | || (MODE) == V8HImode \ | |
1262 | || (MODE) == V4SFmode \ | |
1263 | || (MODE) == V4SImode \ | |
1264 | || FLOAT128_VECTOR_P (MODE)) | |
0ac081f6 | 1265 | |
dbcc9f08 MM |
1266 | #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ |
1267 | (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ | |
a16a872d | 1268 | || (MODE) == V2DImode || (MODE) == V1TImode) |
dbcc9f08 | 1269 | |
a3170dc6 AH |
1270 | #define SPE_VECTOR_MODE(MODE) \ |
1271 | ((MODE) == V4HImode \ | |
1272 | || (MODE) == V2SFmode \ | |
00a892b8 | 1273 | || (MODE) == V1DImode \ |
a3170dc6 AH |
1274 | || (MODE) == V2SImode) |
1275 | ||
96038623 DE |
1276 | #define PAIRED_VECTOR_MODE(MODE) \ |
1277 | ((MODE) == V2SFmode) | |
1278 | ||
0d1fbc8c AH |
1279 | /* Value is TRUE if hard register REGNO can hold a value of |
1280 | machine-mode MODE. */ | |
1281 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
1282 | rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] | |
f045b2c9 RS |
1283 | |
1284 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1285 | when one has mode MODE1 and one has mode MODE2. | |
1286 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
f161bfd3 MM |
1287 | for any hard reg, then this must be 0 for correct output. |
1288 | ||
1289 | PTImode cannot tie with other modes because PTImode is restricted to even | |
1290 | GPR registers, and TImode can go in any GPR as well as VSX registers (PR | |
bdb60a10 MM |
1291 | 57744). |
1292 | ||
1293 | Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE | |
1294 | 128-bit floating point on VSX systems ties with other vectors. */ | |
f62511da | 1295 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
f161bfd3 MM |
1296 | ((MODE1) == PTImode \ |
1297 | ? (MODE2) == PTImode \ | |
1298 | : (MODE2) == PTImode \ | |
1299 | ? 0 \ | |
bdb60a10 MM |
1300 | : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ |
1301 | ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ | |
1302 | : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ | |
1303 | ? 0 \ | |
f161bfd3 | 1304 | : SCALAR_FLOAT_MODE_P (MODE1) \ |
ebb109ad BE |
1305 | ? SCALAR_FLOAT_MODE_P (MODE2) \ |
1306 | : SCALAR_FLOAT_MODE_P (MODE2) \ | |
f161bfd3 | 1307 | ? 0 \ |
f045b2c9 RS |
1308 | : GET_MODE_CLASS (MODE1) == MODE_CC \ |
1309 | ? GET_MODE_CLASS (MODE2) == MODE_CC \ | |
1310 | : GET_MODE_CLASS (MODE2) == MODE_CC \ | |
f161bfd3 | 1311 | ? 0 \ |
4dcc01f3 AH |
1312 | : SPE_VECTOR_MODE (MODE1) \ |
1313 | ? SPE_VECTOR_MODE (MODE2) \ | |
1314 | : SPE_VECTOR_MODE (MODE2) \ | |
f161bfd3 | 1315 | ? 0 \ |
f045b2c9 RS |
1316 | : 1) |
1317 | ||
c8ae788f SB |
1318 | /* Post-reload, we can't use any new AltiVec registers, as we already |
1319 | emitted the vrsave mask. */ | |
1320 | ||
1321 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
6fb5fa3c | 1322 | (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) |
c8ae788f | 1323 | |
f045b2c9 RS |
1324 | /* Specify the cost of a branch insn; roughly the number of extra insns that |
1325 | should be added to avoid a branch. | |
1326 | ||
ef457bda | 1327 | Set this to 3 on the RS/6000 since that is roughly the average cost of an |
f045b2c9 RS |
1328 | unscheduled conditional branch. */ |
1329 | ||
3a4fd356 | 1330 | #define BRANCH_COST(speed_p, predictable_p) 3 |
f045b2c9 | 1331 | |
85e50b6b | 1332 | /* Override BRANCH_COST heuristic which empirically produces worse |
b8610a53 | 1333 | performance for removing short circuiting from the logical ops. */ |
85e50b6b | 1334 | |
b8610a53 | 1335 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 |
a3170dc6 | 1336 | |
52ff33d0 NF |
1337 | /* A fixed register used at epilogue generation to address SPE registers |
1338 | with negative offsets. The 64-bit load/store instructions on the SPE | |
1339 | only take positive offsets (and small ones at that), so we need to | |
1340 | reserve a register for consing up negative offsets. */ | |
a3170dc6 | 1341 | |
52ff33d0 | 1342 | #define FIXED_SCRATCH 0 |
a3170dc6 | 1343 | |
f045b2c9 RS |
1344 | /* Specify the registers used for certain standard purposes. |
1345 | The values of these macros are register numbers. */ | |
1346 | ||
1347 | /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
1348 | /* #define PC_REGNUM */ | |
1349 | ||
1350 | /* Register to use for pushing function arguments. */ | |
1351 | #define STACK_POINTER_REGNUM 1 | |
1352 | ||
1353 | /* Base register for access to local variables of the function. */ | |
7d5175e1 JJ |
1354 | #define HARD_FRAME_POINTER_REGNUM 31 |
1355 | ||
1356 | /* Base register for access to local variables of the function. */ | |
1357 | #define FRAME_POINTER_REGNUM 113 | |
f045b2c9 | 1358 | |
f045b2c9 RS |
1359 | /* Base register for access to arguments of the function. */ |
1360 | #define ARG_POINTER_REGNUM 67 | |
1361 | ||
1362 | /* Place to put static chain when calling a function that requires it. */ | |
1363 | #define STATIC_CHAIN_REGNUM 11 | |
1364 | ||
26a2e6ae PB |
1365 | /* Base register for access to thread local storage variables. */ |
1366 | #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) | |
1367 | ||
f045b2c9 RS |
1368 | \f |
1369 | /* Define the classes of registers for register constraints in the | |
1370 | machine description. Also define ranges of constants. | |
1371 | ||
1372 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1373 | If there is more than one class, another class must be named NO_REGS | |
1374 | and contain no registers. | |
1375 | ||
1376 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1377 | another name such as ALL_REGS). This is the class of registers | |
1378 | that is allowed by "g" or "r" in a register constraint. | |
1379 | Also, registers outside this class are allocated only when | |
1380 | instructions express preferences for them. | |
1381 | ||
1382 | The classes must be numbered in nondecreasing order; that is, | |
1383 | a larger-numbered class must never be contained completely | |
1384 | in a smaller-numbered class. | |
1385 | ||
1386 | For any two classes, it is very desirable that there be another | |
1387 | class that represents their union. */ | |
c81bebd7 | 1388 | |
cacf1ca8 | 1389 | /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
462f7901 | 1390 | condition registers, plus three special registers, CTR, and the link |
cacf1ca8 MM |
1391 | register. AltiVec adds a vector register class. VSX registers overlap the |
1392 | FPR registers and the Altivec registers. | |
f045b2c9 RS |
1393 | |
1394 | However, r0 is special in that it cannot be used as a base register. | |
1395 | So make a class for registers valid as base registers. | |
1396 | ||
1397 | Also, cr0 is the only condition code register that can be used in | |
0d86f538 | 1398 | arithmetic insns, so make a separate class for it. */ |
f045b2c9 | 1399 | |
ebedb4dd MM |
1400 | enum reg_class |
1401 | { | |
1402 | NO_REGS, | |
ebedb4dd MM |
1403 | BASE_REGS, |
1404 | GENERAL_REGS, | |
1405 | FLOAT_REGS, | |
0ac081f6 | 1406 | ALTIVEC_REGS, |
8beb65e3 | 1407 | VSX_REGS, |
0ac081f6 | 1408 | VRSAVE_REGS, |
5f004351 | 1409 | VSCR_REGS, |
a3170dc6 AH |
1410 | SPE_ACC_REGS, |
1411 | SPEFSCR_REGS, | |
0258b6e4 | 1412 | SPR_REGS, |
ebedb4dd | 1413 | NON_SPECIAL_REGS, |
ebedb4dd MM |
1414 | LINK_REGS, |
1415 | CTR_REGS, | |
1416 | LINK_OR_CTR_REGS, | |
1417 | SPECIAL_REGS, | |
1418 | SPEC_OR_GEN_REGS, | |
1419 | CR0_REGS, | |
ebedb4dd MM |
1420 | CR_REGS, |
1421 | NON_FLOAT_REGS, | |
f6b5d695 | 1422 | CA_REGS, |
23742a9e | 1423 | SPE_HIGH_REGS, |
ebedb4dd MM |
1424 | ALL_REGS, |
1425 | LIM_REG_CLASSES | |
1426 | }; | |
f045b2c9 RS |
1427 | |
1428 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1429 | ||
82e41834 | 1430 | /* Give names of register classes as strings for dump file. */ |
f045b2c9 | 1431 | |
ebedb4dd MM |
1432 | #define REG_CLASS_NAMES \ |
1433 | { \ | |
1434 | "NO_REGS", \ | |
ebedb4dd MM |
1435 | "BASE_REGS", \ |
1436 | "GENERAL_REGS", \ | |
1437 | "FLOAT_REGS", \ | |
0ac081f6 | 1438 | "ALTIVEC_REGS", \ |
8beb65e3 | 1439 | "VSX_REGS", \ |
0ac081f6 | 1440 | "VRSAVE_REGS", \ |
5f004351 | 1441 | "VSCR_REGS", \ |
a3170dc6 AH |
1442 | "SPE_ACC_REGS", \ |
1443 | "SPEFSCR_REGS", \ | |
0258b6e4 | 1444 | "SPR_REGS", \ |
ebedb4dd | 1445 | "NON_SPECIAL_REGS", \ |
ebedb4dd MM |
1446 | "LINK_REGS", \ |
1447 | "CTR_REGS", \ | |
1448 | "LINK_OR_CTR_REGS", \ | |
1449 | "SPECIAL_REGS", \ | |
1450 | "SPEC_OR_GEN_REGS", \ | |
1451 | "CR0_REGS", \ | |
ebedb4dd MM |
1452 | "CR_REGS", \ |
1453 | "NON_FLOAT_REGS", \ | |
f6b5d695 | 1454 | "CA_REGS", \ |
23742a9e | 1455 | "SPE_HIGH_REGS", \ |
ebedb4dd MM |
1456 | "ALL_REGS" \ |
1457 | } | |
f045b2c9 RS |
1458 | |
1459 | /* Define which registers fit in which classes. | |
1460 | This is an initializer for a vector of HARD_REG_SET | |
1461 | of length N_REG_CLASSES. */ | |
1462 | ||
23742a9e RAR |
1463 | #define REG_CLASS_CONTENTS \ |
1464 | { \ | |
1465 | /* NO_REGS. */ \ | |
1466 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
1467 | /* BASE_REGS. */ \ | |
1468 | { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ | |
1469 | /* GENERAL_REGS. */ \ | |
1470 | { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ | |
1471 | /* FLOAT_REGS. */ \ | |
1472 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \ | |
1473 | /* ALTIVEC_REGS. */ \ | |
1474 | { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \ | |
1475 | /* VSX_REGS. */ \ | |
1476 | { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \ | |
1477 | /* VRSAVE_REGS. */ \ | |
1478 | { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \ | |
1479 | /* VSCR_REGS. */ \ | |
1480 | { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \ | |
1481 | /* SPE_ACC_REGS. */ \ | |
1482 | { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \ | |
1483 | /* SPEFSCR_REGS. */ \ | |
1484 | { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \ | |
1485 | /* SPR_REGS. */ \ | |
1486 | { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \ | |
1487 | /* NON_SPECIAL_REGS. */ \ | |
1488 | { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \ | |
1489 | /* LINK_REGS. */ \ | |
1490 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \ | |
1491 | /* CTR_REGS. */ \ | |
1492 | { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \ | |
1493 | /* LINK_OR_CTR_REGS. */ \ | |
1494 | { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \ | |
1495 | /* SPECIAL_REGS. */ \ | |
1496 | { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \ | |
1497 | /* SPEC_OR_GEN_REGS. */ \ | |
1498 | { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \ | |
1499 | /* CR0_REGS. */ \ | |
1500 | { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \ | |
1501 | /* CR_REGS. */ \ | |
1502 | { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \ | |
1503 | /* NON_FLOAT_REGS. */ \ | |
1504 | { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \ | |
1505 | /* CA_REGS. */ \ | |
1506 | { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \ | |
1507 | /* SPE_HIGH_REGS. */ \ | |
1508 | { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \ | |
1509 | /* ALL_REGS. */ \ | |
1510 | { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \ | |
ebedb4dd | 1511 | } |
f045b2c9 RS |
1512 | |
1513 | /* The same information, inverted: | |
1514 | Return the class number of the smallest class containing | |
1515 | reg number REGNO. This could be a conditional expression | |
1516 | or could index an array. */ | |
1517 | ||
cacf1ca8 MM |
1518 | extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
1519 | ||
cacf1ca8 | 1520 | #define REGNO_REG_CLASS(REGNO) \ |
e28c2052 | 1521 | (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ |
cacf1ca8 MM |
1522 | rs6000_regno_regclass[(REGNO)]) |
1523 | ||
a72c65c7 MM |
1524 | /* Register classes for various constraints that are based on the target |
1525 | switches. */ | |
1526 | enum r6000_reg_class_enum { | |
1527 | RS6000_CONSTRAINT_d, /* fpr registers for double values */ | |
1528 | RS6000_CONSTRAINT_f, /* fpr registers for single values */ | |
1529 | RS6000_CONSTRAINT_v, /* Altivec registers */ | |
1530 | RS6000_CONSTRAINT_wa, /* Any VSX register */ | |
d5906efc | 1531 | RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */ |
a72c65c7 | 1532 | RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ |
dd551aa1 | 1533 | RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ |
a72c65c7 | 1534 | RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ |
5e8586d7 | 1535 | RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ |
59f5868d MM |
1536 | RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ |
1537 | RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ | |
1538 | RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ | |
1539 | RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ | |
c6d5ff83 | 1540 | RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ |
f62511da | 1541 | RS6000_CONSTRAINT_wm, /* VSX register for direct move */ |
4e8a3a35 | 1542 | RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */ |
c477a667 MM |
1543 | RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ |
1544 | RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ | |
f62511da | 1545 | RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ |
a72c65c7 | 1546 | RS6000_CONSTRAINT_ws, /* VSX register for DF */ |
c6d5ff83 | 1547 | RS6000_CONSTRAINT_wt, /* VSX register for TImode */ |
5e8586d7 MM |
1548 | RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */ |
1549 | RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ | |
1550 | RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ | |
c6d5ff83 | 1551 | RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ |
5e8586d7 | 1552 | RS6000_CONSTRAINT_wy, /* VSX register for SF */ |
c6d5ff83 | 1553 | RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ |
a72c65c7 MM |
1554 | RS6000_CONSTRAINT_MAX |
1555 | }; | |
1556 | ||
1557 | extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; | |
f045b2c9 RS |
1558 | |
1559 | /* The class value for index registers, and the one for base regs. */ | |
1560 | #define INDEX_REG_CLASS GENERAL_REGS | |
1561 | #define BASE_REG_CLASS BASE_REGS | |
1562 | ||
cacf1ca8 MM |
1563 | /* Return whether a given register class can hold VSX objects. */ |
1564 | #define VSX_REG_CLASS_P(CLASS) \ | |
1565 | ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) | |
1566 | ||
59f5868d MM |
1567 | /* Return whether a given register class targets general purpose registers. */ |
1568 | #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) | |
1569 | ||
f045b2c9 RS |
1570 | /* Given an rtx X being reloaded into a reg required to be |
1571 | in class CLASS, return the class of reg to actually use. | |
1572 | In general this is just CLASS; but on some machines | |
c81bebd7 | 1573 | in some cases it is preferable to use a more restrictive class. |
f045b2c9 RS |
1574 | |
1575 | On the RS/6000, we have to return NO_REGS when we want to reload a | |
f676971a | 1576 | floating-point CONST_DOUBLE to force it to be copied to memory. |
1e66d555 GK |
1577 | |
1578 | We also don't want to reload integer values into floating-point | |
1579 | registers if we can at all help it. In fact, this can | |
37409796 | 1580 | cause reload to die, if it tries to generate a reload of CTR |
1e66d555 GK |
1581 | into a FP register and discovers it doesn't have the memory location |
1582 | required. | |
1583 | ||
1584 | ??? Would it be a good idea to have reload do the converse, that is | |
1585 | try to reload floating modes into FP registers if possible? | |
1586 | */ | |
f045b2c9 | 1587 | |
802a0058 | 1588 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
8beb65e3 | 1589 | rs6000_preferred_reload_class_ptr (X, CLASS) |
c81bebd7 | 1590 | |
f045b2c9 RS |
1591 | /* Return the register class of a scratch register needed to copy IN into |
1592 | or out of a register in CLASS in MODE. If it can be done directly, | |
1593 | NO_REGS is returned. */ | |
1594 | ||
1595 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
8beb65e3 | 1596 | rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
f045b2c9 | 1597 | |
0ac081f6 | 1598 | /* If we are copying between FP or AltiVec registers and anything |
44cd321e PS |
1599 | else, we need a memory location. The exception is when we are |
1600 | targeting ppc64 and the move to/from fpr to gpr instructions | |
1601 | are available.*/ | |
1602 | ||
1603 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ | |
8beb65e3 | 1604 | rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE) |
7ea555a4 | 1605 | |
e41b2a33 PB |
1606 | /* For cpus that cannot load/store SDmode values from the 64-bit |
1607 | FP registers without using a full 64-bit load/store, we need | |
1608 | to allocate a full 64-bit stack slot for them. */ | |
1609 | ||
1610 | #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ | |
1611 | rs6000_secondary_memory_needed_rtx (MODE) | |
1612 | ||
01b1efaa VM |
1613 | /* Specify the mode to be used for memory when a secondary memory |
1614 | location is needed. For cpus that cannot load/store SDmode values | |
1615 | from the 64-bit FP registers without using a full 64-bit | |
1616 | load/store, we need a wider mode. */ | |
1617 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1618 | rs6000_secondary_memory_needed_mode (MODE) | |
1619 | ||
f045b2c9 RS |
1620 | /* Return the maximum number of consecutive registers |
1621 | needed to represent mode MODE in a register of class CLASS. | |
1622 | ||
cacf1ca8 MM |
1623 | On RS/6000, this is the size of MODE in words, except in the FP regs, where |
1624 | a single reg is enough for two words, unless we have VSX, where the FP | |
1625 | registers can hold 128 bits. */ | |
1626 | #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] | |
580d3230 | 1627 | |
ca0e79d9 AM |
1628 | /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ |
1629 | ||
1630 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
8beb65e3 | 1631 | rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS) |
02188693 | 1632 | |
f045b2c9 RS |
1633 | /* Stack layout; function entry, exit and calling. */ |
1634 | ||
1635 | /* Define this if pushing a word on the stack | |
1636 | makes the stack pointer a smaller address. */ | |
62f9f30b | 1637 | #define STACK_GROWS_DOWNWARD 1 |
f045b2c9 | 1638 | |
327e5343 FJ |
1639 | /* Offsets recorded in opcodes are a multiple of this alignment factor. */ |
1640 | #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
1641 | ||
a4d05547 | 1642 | /* Define this to nonzero if the nominal address of the stack frame |
f045b2c9 RS |
1643 | is at the high-address end of the local variables; |
1644 | that is, each additional local variable allocated | |
1645 | goes at a more negative offset in the frame. | |
1646 | ||
1647 | On the RS/6000, we grow upwards, from the area after the outgoing | |
1648 | arguments. */ | |
de5a5fa1 MP |
1649 | #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ |
1650 | || (flag_sanitize & SANITIZE_ADDRESS) != 0) | |
f045b2c9 | 1651 | |
4697a36c | 1652 | /* Size of the fixed area on the stack */ |
9ebbca7d | 1653 | #define RS6000_SAVE_AREA \ |
b54214fe UW |
1654 | ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ |
1655 | << (TARGET_64BIT ? 1 : 0)) | |
4697a36c | 1656 | |
b54214fe UW |
1657 | /* Stack offset for toc save slot. */ |
1658 | #define RS6000_TOC_SAVE_SLOT \ | |
1659 | ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) | |
b6c9286a | 1660 | |
4697a36c | 1661 | /* Align an address */ |
4f59f9f2 | 1662 | #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) |
4697a36c | 1663 | |
f045b2c9 RS |
1664 | /* Offset within stack frame to start allocating local variables at. |
1665 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1666 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
c81bebd7 | 1667 | of the first local allocated. |
f045b2c9 RS |
1668 | |
1669 | On the RS/6000, the frame pointer is the same as the stack pointer, | |
1670 | except for dynamic allocations. So we start after the fixed area and | |
1671 | outgoing parameter area. */ | |
1672 | ||
802a0058 | 1673 | #define STARTING_FRAME_OFFSET \ |
7d5175e1 JJ |
1674 | (FRAME_GROWS_DOWNWARD \ |
1675 | ? 0 \ | |
cacf1ca8 MM |
1676 | : (RS6000_ALIGN (crtl->outgoing_args_size, \ |
1677 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ | |
7d5175e1 | 1678 | + RS6000_SAVE_AREA)) |
802a0058 MM |
1679 | |
1680 | /* Offset from the stack pointer register to an item dynamically | |
1681 | allocated on the stack, e.g., by `alloca'. | |
1682 | ||
1683 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1684 | length of the outgoing arguments. The default is correct for most | |
1685 | machines. See `function.c' for details. */ | |
1686 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ | |
cacf1ca8 MM |
1687 | (RS6000_ALIGN (crtl->outgoing_args_size, \ |
1688 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ | |
802a0058 | 1689 | + (STACK_POINTER_OFFSET)) |
f045b2c9 RS |
1690 | |
1691 | /* If we generate an insn to push BYTES bytes, | |
1692 | this says how many the stack pointer really advances by. | |
1693 | On RS/6000, don't define this because there are no push insns. */ | |
1694 | /* #define PUSH_ROUNDING(BYTES) */ | |
1695 | ||
1696 | /* Offset of first parameter from the argument pointer register value. | |
1697 | On the RS/6000, we define the argument pointer to the start of the fixed | |
1698 | area. */ | |
4697a36c | 1699 | #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA |
f045b2c9 | 1700 | |
62153b61 JM |
1701 | /* Offset from the argument pointer register value to the top of |
1702 | stack. This is different from FIRST_PARM_OFFSET because of the | |
1703 | register save area. */ | |
1704 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1705 | ||
f045b2c9 RS |
1706 | /* Define this if stack space is still allocated for a parameter passed |
1707 | in a register. The value is the number of bytes allocated to this | |
1708 | area. */ | |
ddbb449f AM |
1709 | #define REG_PARM_STACK_SPACE(FNDECL) \ |
1710 | rs6000_reg_parm_stack_space ((FNDECL), false) | |
1711 | ||
1712 | /* Define this macro if space guaranteed when compiling a function body | |
1713 | is different to space required when making a call, a situation that | |
1714 | can arise with K&R style function definitions. */ | |
1715 | #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ | |
1716 | rs6000_reg_parm_stack_space ((FNDECL), true) | |
f045b2c9 RS |
1717 | |
1718 | /* Define this if the above stack space is to be considered part of the | |
1719 | space allocated by the caller. */ | |
81464b2c | 1720 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
f045b2c9 RS |
1721 | |
1722 | /* This is the difference between the logical top of stack and the actual sp. | |
1723 | ||
82e41834 | 1724 | For the RS/6000, sp points past the fixed area. */ |
4697a36c | 1725 | #define STACK_POINTER_OFFSET RS6000_SAVE_AREA |
f045b2c9 RS |
1726 | |
1727 | /* Define this if the maximum size of all the outgoing args is to be | |
1728 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1729 | found in the variable crtl->outgoing_args_size. */ |
f73ad30e | 1730 | #define ACCUMULATE_OUTGOING_ARGS 1 |
f045b2c9 | 1731 | |
f045b2c9 RS |
1732 | /* Define how to find the value returned by a library function |
1733 | assuming the value has mode MODE. */ | |
1734 | ||
ded9bf77 | 1735 | #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) |
f045b2c9 | 1736 | |
6fa3f289 ZW |
1737 | /* DRAFT_V4_STRUCT_RET defaults off. */ |
1738 | #define DRAFT_V4_STRUCT_RET 0 | |
f607bc57 | 1739 | |
bd5bd7ac | 1740 | /* Let TARGET_RETURN_IN_MEMORY control what happens. */ |
f607bc57 | 1741 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
f045b2c9 | 1742 | |
a260abc9 | 1743 | /* Mode of stack savearea. |
dfdfa60f DE |
1744 | FUNCTION is VOIDmode because calling convention maintains SP. |
1745 | BLOCK needs Pmode for SP. | |
a260abc9 DE |
1746 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ |
1747 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
dfdfa60f | 1748 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ |
c6d5ff83 | 1749 | : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) |
a260abc9 | 1750 | |
4697a36c MM |
1751 | /* Minimum and maximum general purpose registers used to hold arguments. */ |
1752 | #define GP_ARG_MIN_REG 3 | |
1753 | #define GP_ARG_MAX_REG 10 | |
1754 | #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1755 | ||
1756 | /* Minimum and maximum floating point registers used to hold arguments. */ | |
1757 | #define FP_ARG_MIN_REG 33 | |
7509c759 MM |
1758 | #define FP_ARG_AIX_MAX_REG 45 |
1759 | #define FP_ARG_V4_MAX_REG 40 | |
008e32c0 UW |
1760 | #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ |
1761 | ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) | |
4697a36c MM |
1762 | #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
1763 | ||
0ac081f6 AH |
1764 | /* Minimum and maximum AltiVec registers used to hold arguments. */ |
1765 | #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
1766 | #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
1767 | #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
1768 | ||
b54214fe UW |
1769 | /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ |
1770 | #define AGGR_ARG_NUM_REG 8 | |
1771 | ||
4697a36c MM |
1772 | /* Return registers */ |
1773 | #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1774 | #define FP_ARG_RETURN FP_ARG_MIN_REG | |
0ac081f6 | 1775 | #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) |
b54214fe UW |
1776 | #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ |
1777 | : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
1778 | #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \ | |
1779 | : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
4697a36c | 1780 | |
7509c759 | 1781 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
6a4cee5f | 1782 | #define CALL_NORMAL 0x00000000 /* no special processing */ |
9ebbca7d | 1783 | /* Bits in 0x00000001 are unused. */ |
6a4cee5f MM |
1784 | #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ |
1785 | #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1786 | #define CALL_LONG 0x00000008 /* always call indirect */ | |
b9599e46 | 1787 | #define CALL_LIBCALL 0x00000010 /* libcall */ |
7509c759 | 1788 | |
f57fe068 AM |
1789 | /* We don't have prologue and epilogue functions to save/restore |
1790 | everything for most ABIs. */ | |
1791 | #define WORLD_SAVE_P(INFO) 0 | |
1792 | ||
f045b2c9 RS |
1793 | /* 1 if N is a possible register number for a function value |
1794 | as seen by the caller. | |
1795 | ||
0ac081f6 | 1796 | On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ |
e87a88d3 AM |
1797 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1798 | ((N) == GP_ARG_RETURN \ | |
b54214fe UW |
1799 | || ((N) >= FP_ARG_RETURN && (N) <= FP_ARG_MAX_RETURN \ |
1800 | && TARGET_HARD_FLOAT && TARGET_FPRS) \ | |
1801 | || ((N) >= ALTIVEC_ARG_RETURN && (N) <= ALTIVEC_ARG_MAX_RETURN \ | |
1802 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) | |
f045b2c9 RS |
1803 | |
1804 | /* 1 if N is a possible register number for function argument passing. | |
0ac081f6 AH |
1805 | On RS/6000, these are r3-r10 and fp1-fp13. |
1806 | On AltiVec, v2 - v13 are used for passing vectors. */ | |
4697a36c | 1807 | #define FUNCTION_ARG_REGNO_P(N) \ |
e87a88d3 AM |
1808 | ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ |
1809 | || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ | |
44688022 | 1810 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
e87a88d3 | 1811 | || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ |
b2df7d08 | 1812 | && TARGET_HARD_FLOAT && TARGET_FPRS)) |
f045b2c9 RS |
1813 | \f |
1814 | /* Define a data type for recording info about an argument list | |
1815 | during the scan of that argument list. This data type should | |
1816 | hold all necessary information about the function itself | |
1817 | and about the args processed so far, enough to enable macros | |
1818 | such as FUNCTION_ARG to determine where the next arg should go. | |
1819 | ||
1820 | On the RS/6000, this is a structure. The first element is the number of | |
1821 | total argument words, the second is used to store the next | |
1822 | floating-point register number, and the third says how many more args we | |
4697a36c MM |
1823 | have prototype types for. |
1824 | ||
4cc833b7 | 1825 | For ABI_V4, we treat these slightly differently -- `sysv_gregno' is |
07488f32 | 1826 | the next available GP register, `fregno' is the next available FP |
4cc833b7 RH |
1827 | register, and `words' is the number of words used on the stack. |
1828 | ||
bd227acc | 1829 | The varargs/stdarg support requires that this structure's size |
4cc833b7 | 1830 | be a multiple of sizeof(int). */ |
4697a36c MM |
1831 | |
1832 | typedef struct rs6000_args | |
1833 | { | |
4cc833b7 | 1834 | int words; /* # words used for passing GP registers */ |
6a4cee5f | 1835 | int fregno; /* next available FP register */ |
0ac081f6 | 1836 | int vregno; /* next available AltiVec register */ |
6a4cee5f | 1837 | int nargs_prototype; /* # args left in the current prototype */ |
6a4cee5f | 1838 | int prototype; /* Whether a prototype was defined */ |
a6c9bed4 | 1839 | int stdarg; /* Whether function is a stdarg function. */ |
6a4cee5f | 1840 | int call_cookie; /* Do special things for this call */ |
4cc833b7 | 1841 | int sysv_gregno; /* next available GP register */ |
0b5383eb DJ |
1842 | int intoffset; /* running offset in struct (darwin64) */ |
1843 | int use_stack; /* any part of struct on stack (darwin64) */ | |
a9ab25e2 IS |
1844 | int floats_in_gpr; /* count of SFmode floats taking up |
1845 | GPR space (darwin64) */ | |
0b5383eb | 1846 | int named; /* false for varargs params */ |
617718f7 | 1847 | int escapes; /* if function visible outside tu */ |
bdb60a10 | 1848 | int libcall; /* If this is a compiler generated call. */ |
4697a36c | 1849 | } CUMULATIVE_ARGS; |
f045b2c9 | 1850 | |
f045b2c9 RS |
1851 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1852 | for a call to a function whose data type is FNTYPE. | |
1853 | For a library call, FNTYPE is 0. */ | |
1854 | ||
617718f7 AM |
1855 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
1856 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ | |
1857 | N_NAMED_ARGS, FNDECL, VOIDmode) | |
f045b2c9 RS |
1858 | |
1859 | /* Similar, but when scanning the definition of a procedure. We always | |
1860 | set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1861 | ||
0f6937fe | 1862 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ |
617718f7 AM |
1863 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
1864 | 1000, current_function_decl, VOIDmode) | |
b9599e46 FS |
1865 | |
1866 | /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
1867 | ||
1868 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
617718f7 AM |
1869 | init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
1870 | 0, NULL_TREE, MODE) | |
f045b2c9 | 1871 | |
c229cba9 DE |
1872 | /* If defined, a C expression which determines whether, and in which |
1873 | direction, to pad out an argument with extra space. The value | |
1874 | should be of type `enum direction': either `upward' to pad above | |
1875 | the argument, `downward' to pad below, or `none' to inhibit | |
1876 | padding. */ | |
1877 | ||
9ebbca7d | 1878 | #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) |
c229cba9 | 1879 | |
6e985040 AM |
1880 | #define PAD_VARARGS_DOWN \ |
1881 | (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) | |
2a55fd42 | 1882 | |
f045b2c9 | 1883 | /* Output assembler code to FILE to increment profiler label # LABELNO |
58a39e45 | 1884 | for profiling a function entry. */ |
f045b2c9 RS |
1885 | |
1886 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
58a39e45 | 1887 | output_function_profiler ((FILE), (LABELNO)); |
f045b2c9 RS |
1888 | |
1889 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1890 | the stack pointer does not matter. No definition is equivalent to | |
1891 | always zero. | |
1892 | ||
a0ab749a | 1893 | On the RS/6000, this is nonzero because we can restore the stack from |
f045b2c9 RS |
1894 | its backpointer, which we maintain. */ |
1895 | #define EXIT_IGNORE_STACK 1 | |
1896 | ||
a701949a FS |
1897 | /* Define this macro as a C expression that is nonzero for registers |
1898 | that are used by the epilogue or the return' pattern. The stack | |
1899 | and frame pointer registers are already be assumed to be used as | |
1900 | needed. */ | |
1901 | ||
83720594 | 1902 | #define EPILOGUE_USES(REGNO) \ |
1de43f85 | 1903 | ((reload_completed && (REGNO) == LR_REGNO) \ |
b1765bde | 1904 | || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ |
cacf1ca8 | 1905 | || (crtl->calls_eh_return \ |
3553b09d | 1906 | && TARGET_AIX \ |
ff3867ae | 1907 | && (REGNO) == 2)) |
2bfcf297 | 1908 | |
f045b2c9 | 1909 | \f |
f045b2c9 RS |
1910 | /* Length in units of the trampoline for entering a nested function. */ |
1911 | ||
b6c9286a | 1912 | #define TRAMPOLINE_SIZE rs6000_trampoline_size () |
f045b2c9 | 1913 | \f |
f33985c6 MS |
1914 | /* Definitions for __builtin_return_address and __builtin_frame_address. |
1915 | __builtin_return_address (0) should give link register (65), enable | |
82e41834 | 1916 | this. */ |
f33985c6 MS |
1917 | /* This should be uncommented, so that the link register is used, but |
1918 | currently this would result in unmatched insns and spilling fixed | |
1919 | registers so we'll leave it for another day. When these problems are | |
1920 | taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1921 | (mrs) */ | |
1922 | /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
f09d4c33 | 1923 | |
b6c9286a MM |
1924 | /* Number of bytes into the frame return addresses can be found. See |
1925 | rs6000_stack_info in rs6000.c for more information on how the different | |
1926 | abi's store the return address. */ | |
008e32c0 UW |
1927 | #define RETURN_ADDRESS_OFFSET \ |
1928 | ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) | |
f09d4c33 | 1929 | |
f33985c6 MS |
1930 | /* The current return address is in link register (65). The return address |
1931 | of anything farther back is accessed normally at an offset of 8 from the | |
1932 | frame pointer. */ | |
71f123ca FS |
1933 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1934 | (rs6000_return_addr (COUNT, FRAME)) | |
1935 | ||
f33985c6 | 1936 | \f |
f045b2c9 RS |
1937 | /* Definitions for register eliminations. |
1938 | ||
1939 | We have two registers that can be eliminated on the RS/6000. First, the | |
1940 | frame pointer register can often be eliminated in favor of the stack | |
1941 | pointer register. Secondly, the argument pointer register can always be | |
642a35f1 JW |
1942 | eliminated; it is replaced with either the stack or frame pointer. |
1943 | ||
1944 | In addition, we use the elimination mechanism to see if r30 is needed | |
1945 | Initially we assume that it isn't. If it is, we spill it. This is done | |
1946 | by making it an eliminable register. We replace it with itself so that | |
1947 | if it isn't needed, then existing uses won't be modified. */ | |
f045b2c9 RS |
1948 | |
1949 | /* This is an array of structures. Each structure initializes one pair | |
1950 | of eliminable registers. The "from" register number is given first, | |
1951 | followed by "to". Eliminations of the same "from" register are listed | |
1952 | in order of preference. */ | |
7d5175e1 JJ |
1953 | #define ELIMINABLE_REGS \ |
1954 | {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1955 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1956 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1957 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1958 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
97b23853 | 1959 | { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } |
f045b2c9 | 1960 | |
f045b2c9 RS |
1961 | /* Define the offset between two registers, one to be eliminated, and the other |
1962 | its replacement, at the start of a routine. */ | |
d1d0c603 JJ |
1963 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1964 | ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
f045b2c9 RS |
1965 | \f |
1966 | /* Addressing modes, and classification of registers for them. */ | |
1967 | ||
940da324 JL |
1968 | #define HAVE_PRE_DECREMENT 1 |
1969 | #define HAVE_PRE_INCREMENT 1 | |
6fb5fa3c DB |
1970 | #define HAVE_PRE_MODIFY_DISP 1 |
1971 | #define HAVE_PRE_MODIFY_REG 1 | |
f045b2c9 RS |
1972 | |
1973 | /* Macros to check register numbers against specific register classes. */ | |
1974 | ||
1975 | /* These assume that REGNO is a hard or pseudo reg number. | |
1976 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1977 | or a pseudo reg currently allocated to a suitable hard reg. | |
1978 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1979 | has been allocated, which happens in reginfo.c during register |
1980 | allocation. */ | |
f045b2c9 RS |
1981 | |
1982 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1983 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1984 | ? (REGNO) <= 31 || (REGNO) == 67 \ | |
7d5175e1 | 1985 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1986 | : (reg_renumber[REGNO] >= 0 \ |
7d5175e1 JJ |
1987 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1988 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
f045b2c9 RS |
1989 | |
1990 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1991 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1992 | ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
7d5175e1 | 1993 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1994 | : (reg_renumber[REGNO] > 0 \ |
7d5175e1 JJ |
1995 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1996 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
c6c3dba9 PB |
1997 | |
1998 | /* Nonzero if X is a hard reg that can be used as an index | |
1999 | or if it is a pseudo reg in the non-strict case. */ | |
2000 | #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ | |
2001 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
2002 | || REGNO_OK_FOR_INDEX_P (REGNO (X))) | |
2003 | ||
2004 | /* Nonzero if X is a hard reg that can be used as a base reg | |
2005 | or if it is a pseudo reg in the non-strict case. */ | |
2006 | #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ | |
2007 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
2008 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
2009 | ||
f045b2c9 RS |
2010 | \f |
2011 | /* Maximum number of registers that can appear in a valid memory address. */ | |
2012 | ||
2013 | #define MAX_REGS_PER_ADDRESS 2 | |
2014 | ||
2015 | /* Recognize any constant value that is a valid address. */ | |
2016 | ||
6eff269e BK |
2017 | #define CONSTANT_ADDRESS_P(X) \ |
2018 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
2019 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
2020 | || GET_CODE (X) == HIGH) | |
f045b2c9 | 2021 | |
48d72335 | 2022 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
66180ff3 | 2023 | #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ |
76492753 PB |
2024 | && EASY_VECTOR_15((n) >> 1) \ |
2025 | && ((n) & 1) == 0) | |
48d72335 | 2026 | |
29e6733c | 2027 | #define EASY_VECTOR_MSB(n,mode) \ |
683be46f | 2028 | ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ |
29e6733c MM |
2029 | ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) |
2030 | ||
f045b2c9 | 2031 | \f |
a260abc9 DE |
2032 | /* Try a machine-dependent way of reloading an illegitimate address |
2033 | operand. If we find one, push the reload and jump to WIN. This | |
2034 | macro is used in only one place: `find_reloads_address' in reload.c. | |
2035 | ||
f676971a | 2036 | Implemented on rs6000 by rs6000_legitimize_reload_address. |
24ea750e | 2037 | Note that (X) is evaluated twice; this is safe in current usage. */ |
f676971a | 2038 | |
a9098fd0 GK |
2039 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
2040 | do { \ | |
24ea750e | 2041 | int win; \ |
8beb65e3 | 2042 | (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ |
24ea750e DJ |
2043 | (int)(TYPE), (IND_LEVELS), &win); \ |
2044 | if ( win ) \ | |
2045 | goto WIN; \ | |
a260abc9 DE |
2046 | } while (0) |
2047 | ||
944258eb | 2048 | #define FIND_BASE_TERM rs6000_find_base_term |
766a866c MM |
2049 | \f |
2050 | /* The register number of the register used to address a table of | |
2051 | static data addresses in memory. In some cases this register is | |
2052 | defined by a processor's "application binary interface" (ABI). | |
2053 | When this macro is defined, RTL is generated for this register | |
2054 | once, as with the stack pointer and frame pointer registers. If | |
2055 | this macro is not defined, it is up to the machine-dependent files | |
2056 | to allocate such a register (if necessary). */ | |
2057 | ||
1db02437 FS |
2058 | #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 |
2059 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) | |
766a866c | 2060 | |
97b23853 | 2061 | #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) |
9ebbca7d | 2062 | |
766a866c MM |
2063 | /* Define this macro if the register defined by |
2064 | `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
089a05b8 | 2065 | this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ |
766a866c MM |
2066 | |
2067 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
2068 | ||
766a866c MM |
2069 | /* A C expression that is nonzero if X is a legitimate immediate |
2070 | operand on the target machine when generating position independent | |
2071 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
2072 | not check this. You can also assume FLAG_PIC is true, so you need | |
2073 | not check it either. You need not define this macro if all | |
2074 | constants (including `SYMBOL_REF') can be immediate operands when | |
2075 | generating position independent code. */ | |
2076 | ||
2077 | /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
f045b2c9 RS |
2078 | \f |
2079 | /* Define this if some processing needs to be done immediately before | |
4255474b | 2080 | emitting code for an insn. */ |
f045b2c9 | 2081 | |
c921bad8 AP |
2082 | #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \ |
2083 | rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS) | |
f045b2c9 RS |
2084 | |
2085 | /* Specify the machine mode that this machine uses | |
2086 | for the index in the tablejump instruction. */ | |
e1565e65 | 2087 | #define CASE_VECTOR_MODE SImode |
f045b2c9 | 2088 | |
18543a22 ILT |
2089 | /* Define as C expression which evaluates to nonzero if the tablejump |
2090 | instruction expects the table to contain offsets from the address of the | |
2091 | table. | |
82e41834 | 2092 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 2093 | #define CASE_VECTOR_PC_RELATIVE 1 |
f045b2c9 | 2094 | |
f045b2c9 RS |
2095 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
2096 | #define DEFAULT_SIGNED_CHAR 0 | |
2097 | ||
c1618c0c DE |
2098 | /* An integer expression for the size in bits of the largest integer machine |
2099 | mode that should actually be used. */ | |
2100 | ||
2101 | /* Allow pairs of registers to be used, which is the intent of the default. */ | |
2102 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
2103 | ||
f045b2c9 RS |
2104 | /* Max number of bytes we can move from memory to memory |
2105 | in one reasonably fast instruction. */ | |
2f3e5814 | 2106 | #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) |
7e69e155 | 2107 | #define MAX_MOVE_MAX 8 |
f045b2c9 RS |
2108 | |
2109 | /* Nonzero if access to memory by bytes is no faster than for words. | |
a0ab749a | 2110 | Also nonzero if doing byte operations (specifically shifts) in registers |
f045b2c9 RS |
2111 | is undesirable. */ |
2112 | #define SLOW_BYTE_ACCESS 1 | |
2113 | ||
9a63901f RK |
2114 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD |
2115 | will either zero-extend or sign-extend. The value of this macro should | |
2116 | be the code that says which one of the two operations is implicitly | |
f822d252 | 2117 | done, UNKNOWN if none. */ |
9a63901f | 2118 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
225211e2 RK |
2119 | |
2120 | /* Define if loading short immediate values into registers sign extends. */ | |
58f2ae18 | 2121 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
fdaff8ba | 2122 | \f |
f045b2c9 RS |
2123 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
2124 | is done just by pretending it is already truncated. */ | |
2125 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2126 | ||
94993909 | 2127 | /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ |
d865b122 | 2128 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
14670a74 | 2129 | ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) |
d865b122 | 2130 | |
0299bc72 MM |
2131 | /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of |
2132 | zero. The hardware instructions added in Power9 return 32 or 64. */ | |
2133 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
2134 | ((!TARGET_CTZ) \ | |
2135 | ? ((VALUE) = -1, 1) \ | |
2136 | : ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)) | |
94993909 | 2137 | |
f045b2c9 RS |
2138 | /* Specify the machine mode that pointers have. |
2139 | After generation of rtl, the compiler makes no further distinction | |
2140 | between pointers and any other objects of this machine mode. */ | |
cacf1ca8 | 2141 | extern unsigned rs6000_pmode; |
ef4bddc2 | 2142 | #define Pmode ((machine_mode)rs6000_pmode) |
f045b2c9 | 2143 | |
a3c9585f | 2144 | /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ |
4c81e946 FJ |
2145 | #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) |
2146 | ||
f045b2c9 | 2147 | /* Mode of a function address in a call instruction (for indexing purposes). |
f045b2c9 | 2148 | Doesn't matter on RS/6000. */ |
5b71a4e7 | 2149 | #define FUNCTION_MODE SImode |
f045b2c9 RS |
2150 | |
2151 | /* Define this if addresses of constant functions | |
2152 | shouldn't be put through pseudo regs where they can be cse'd. | |
2153 | Desirable on machines where ordinary constants are expensive | |
2154 | but a CALL with constant address is cheap. */ | |
1e8552c2 | 2155 | #define NO_FUNCTION_CSE 1 |
f045b2c9 | 2156 | |
d969caf8 | 2157 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
6febd581 RK |
2158 | few bits. |
2159 | ||
2160 | The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
2161 | have been dropped from the PowerPC architecture. */ | |
c28a7c24 | 2162 | #define SHIFT_COUNT_TRUNCATED 0 |
f045b2c9 | 2163 | |
f045b2c9 RS |
2164 | /* Adjust the length of an INSN. LENGTH is the currently-computed length and |
2165 | should be adjusted to reflect any required changes. This macro is used when | |
2166 | there is some systematic length adjustment required that would be difficult | |
2167 | to express in the length attribute. */ | |
2168 | ||
2169 | /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
2170 | ||
39a10a29 GK |
2171 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a |
2172 | COMPARE, return the mode to be used for the comparison. For | |
2173 | floating-point, CCFPmode should be used. CCUNSmode should be used | |
2174 | for unsigned comparisons. CCEQmode should be used when we are | |
2175 | doing an inequality comparison on the result of a | |
2176 | comparison. CCmode should be used in all other cases. */ | |
c5defebb | 2177 | |
b565a316 | 2178 | #define SELECT_CC_MODE(OP,X,Y) \ |
ebb109ad | 2179 | (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ |
c5defebb | 2180 | : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ |
ec8e098d | 2181 | : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ |
c5defebb | 2182 | ? CCEQmode : CCmode)) |
f045b2c9 | 2183 | |
b39358e1 GK |
2184 | /* Can the condition code MODE be safely reversed? This is safe in |
2185 | all cases on this port, because at present it doesn't use the | |
2186 | trapping FP comparisons (fcmpo). */ | |
2187 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2188 | ||
2189 | /* Given a condition code and a mode, return the inverse condition. */ | |
2190 | #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
2191 | ||
f045b2c9 RS |
2192 | \f |
2193 | /* Control the assembler format that we output. */ | |
2194 | ||
1b279f39 DE |
2195 | /* A C string constant describing how to begin a comment in the target |
2196 | assembler language. The compiler assumes that the comment will end at | |
2197 | the end of the line. */ | |
2198 | #define ASM_COMMENT_START " #" | |
6b67933e | 2199 | |
38c1f2d7 MM |
2200 | /* Flag to say the TOC is initialized */ |
2201 | extern int toc_initialized; | |
2202 | ||
f045b2c9 RS |
2203 | /* Macro to output a special constant pool entry. Go to WIN if we output |
2204 | it. Otherwise, it is written the usual way. | |
2205 | ||
2206 | On the RS/6000, toc entries are handled this way. */ | |
2207 | ||
a9098fd0 GK |
2208 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ |
2209 | { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
2210 | { \ | |
2211 | output_toc (FILE, X, LABELNO, MODE); \ | |
2212 | goto WIN; \ | |
2213 | } \ | |
f045b2c9 RS |
2214 | } |
2215 | ||
ebd97b96 DE |
2216 | #ifdef HAVE_GAS_WEAK |
2217 | #define RS6000_WEAK 1 | |
2218 | #else | |
2219 | #define RS6000_WEAK 0 | |
2220 | #endif | |
290ad355 | 2221 | |
79c4e63f AM |
2222 | #if RS6000_WEAK |
2223 | /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
2224 | #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ | |
2225 | do \ | |
2226 | { \ | |
2227 | fputs ("\t.weak\t", (FILE)); \ | |
85b776df | 2228 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f | 2229 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ |
85b776df | 2230 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f | 2231 | { \ |
cbaaba19 DE |
2232 | if (TARGET_XCOFF) \ |
2233 | fputs ("[DS]", (FILE)); \ | |
ca734b39 | 2234 | fputs ("\n\t.weak\t.", (FILE)); \ |
cbaaba19 | 2235 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f AM |
2236 | } \ |
2237 | fputc ('\n', (FILE)); \ | |
2238 | if (VAL) \ | |
2239 | { \ | |
2240 | ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ | |
2241 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
85b776df | 2242 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f AM |
2243 | { \ |
2244 | fputs ("\t.set\t.", (FILE)); \ | |
cbaaba19 | 2245 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f | 2246 | fputs (",.", (FILE)); \ |
cbaaba19 | 2247 | RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ |
79c4e63f AM |
2248 | fputc ('\n', (FILE)); \ |
2249 | } \ | |
2250 | } \ | |
2251 | } \ | |
2252 | while (0) | |
2253 | #endif | |
2254 | ||
ff2d10c1 AO |
2255 | #if HAVE_GAS_WEAKREF |
2256 | #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
2257 | do \ | |
2258 | { \ | |
2259 | fputs ("\t.weakref\t", (FILE)); \ | |
2260 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2261 | fputs (", ", (FILE)); \ | |
2262 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2263 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
2264 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
2265 | { \ | |
2266 | fputs ("\n\t.weakref\t.", (FILE)); \ | |
2267 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2268 | fputs (", .", (FILE)); \ | |
2269 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2270 | } \ | |
2271 | fputc ('\n', (FILE)); \ | |
2272 | } while (0) | |
2273 | #endif | |
2274 | ||
79c4e63f AM |
2275 | /* This implements the `alias' attribute. */ |
2276 | #undef ASM_OUTPUT_DEF_FROM_DECLS | |
2277 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
2278 | do \ | |
2279 | { \ | |
2280 | const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
2281 | const char *name = IDENTIFIER_POINTER (TARGET); \ | |
2282 | if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
85b776df | 2283 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f AM |
2284 | { \ |
2285 | if (TREE_PUBLIC (DECL)) \ | |
2286 | { \ | |
2287 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
2288 | { \ | |
2289 | fputs ("\t.globl\t.", FILE); \ | |
cbaaba19 | 2290 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
2291 | putc ('\n', FILE); \ |
2292 | } \ | |
2293 | } \ | |
2294 | else if (TARGET_XCOFF) \ | |
2295 | { \ | |
c167bc5b DE |
2296 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ |
2297 | { \ | |
2298 | fputs ("\t.lglobl\t.", FILE); \ | |
2299 | RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
2300 | putc ('\n', FILE); \ | |
2301 | fputs ("\t.lglobl\t", FILE); \ | |
2302 | RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
2303 | putc ('\n', FILE); \ | |
2304 | } \ | |
79c4e63f AM |
2305 | } \ |
2306 | fputs ("\t.set\t.", FILE); \ | |
cbaaba19 | 2307 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f | 2308 | fputs (",.", FILE); \ |
cbaaba19 | 2309 | RS6000_OUTPUT_BASENAME (FILE, name); \ |
79c4e63f AM |
2310 | fputc ('\n', FILE); \ |
2311 | } \ | |
2312 | ASM_OUTPUT_DEF (FILE, alias, name); \ | |
2313 | } \ | |
2314 | while (0) | |
290ad355 | 2315 | |
1bc7c5b6 ZW |
2316 | #define TARGET_ASM_FILE_START rs6000_file_start |
2317 | ||
f045b2c9 RS |
2318 | /* Output to assembler file text saying following lines |
2319 | may contain character constants, extra white space, comments, etc. */ | |
2320 | ||
2321 | #define ASM_APP_ON "" | |
2322 | ||
2323 | /* Output to assembler file text saying following lines | |
2324 | no longer contain unusual constructs. */ | |
2325 | ||
2326 | #define ASM_APP_OFF "" | |
2327 | ||
f045b2c9 RS |
2328 | /* How to refer to registers in assembler output. |
2329 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2330 | ||
82e41834 | 2331 | extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ |
c81bebd7 MM |
2332 | |
2333 | #define REGISTER_NAMES \ | |
2334 | { \ | |
2335 | &rs6000_reg_names[ 0][0], /* r0 */ \ | |
2336 | &rs6000_reg_names[ 1][0], /* r1 */ \ | |
2337 | &rs6000_reg_names[ 2][0], /* r2 */ \ | |
2338 | &rs6000_reg_names[ 3][0], /* r3 */ \ | |
2339 | &rs6000_reg_names[ 4][0], /* r4 */ \ | |
2340 | &rs6000_reg_names[ 5][0], /* r5 */ \ | |
2341 | &rs6000_reg_names[ 6][0], /* r6 */ \ | |
2342 | &rs6000_reg_names[ 7][0], /* r7 */ \ | |
2343 | &rs6000_reg_names[ 8][0], /* r8 */ \ | |
2344 | &rs6000_reg_names[ 9][0], /* r9 */ \ | |
2345 | &rs6000_reg_names[10][0], /* r10 */ \ | |
2346 | &rs6000_reg_names[11][0], /* r11 */ \ | |
2347 | &rs6000_reg_names[12][0], /* r12 */ \ | |
2348 | &rs6000_reg_names[13][0], /* r13 */ \ | |
2349 | &rs6000_reg_names[14][0], /* r14 */ \ | |
2350 | &rs6000_reg_names[15][0], /* r15 */ \ | |
2351 | &rs6000_reg_names[16][0], /* r16 */ \ | |
2352 | &rs6000_reg_names[17][0], /* r17 */ \ | |
2353 | &rs6000_reg_names[18][0], /* r18 */ \ | |
2354 | &rs6000_reg_names[19][0], /* r19 */ \ | |
2355 | &rs6000_reg_names[20][0], /* r20 */ \ | |
2356 | &rs6000_reg_names[21][0], /* r21 */ \ | |
2357 | &rs6000_reg_names[22][0], /* r22 */ \ | |
2358 | &rs6000_reg_names[23][0], /* r23 */ \ | |
2359 | &rs6000_reg_names[24][0], /* r24 */ \ | |
2360 | &rs6000_reg_names[25][0], /* r25 */ \ | |
2361 | &rs6000_reg_names[26][0], /* r26 */ \ | |
2362 | &rs6000_reg_names[27][0], /* r27 */ \ | |
2363 | &rs6000_reg_names[28][0], /* r28 */ \ | |
2364 | &rs6000_reg_names[29][0], /* r29 */ \ | |
2365 | &rs6000_reg_names[30][0], /* r30 */ \ | |
2366 | &rs6000_reg_names[31][0], /* r31 */ \ | |
2367 | \ | |
2368 | &rs6000_reg_names[32][0], /* fr0 */ \ | |
2369 | &rs6000_reg_names[33][0], /* fr1 */ \ | |
2370 | &rs6000_reg_names[34][0], /* fr2 */ \ | |
2371 | &rs6000_reg_names[35][0], /* fr3 */ \ | |
2372 | &rs6000_reg_names[36][0], /* fr4 */ \ | |
2373 | &rs6000_reg_names[37][0], /* fr5 */ \ | |
2374 | &rs6000_reg_names[38][0], /* fr6 */ \ | |
2375 | &rs6000_reg_names[39][0], /* fr7 */ \ | |
2376 | &rs6000_reg_names[40][0], /* fr8 */ \ | |
2377 | &rs6000_reg_names[41][0], /* fr9 */ \ | |
2378 | &rs6000_reg_names[42][0], /* fr10 */ \ | |
2379 | &rs6000_reg_names[43][0], /* fr11 */ \ | |
2380 | &rs6000_reg_names[44][0], /* fr12 */ \ | |
2381 | &rs6000_reg_names[45][0], /* fr13 */ \ | |
2382 | &rs6000_reg_names[46][0], /* fr14 */ \ | |
2383 | &rs6000_reg_names[47][0], /* fr15 */ \ | |
2384 | &rs6000_reg_names[48][0], /* fr16 */ \ | |
2385 | &rs6000_reg_names[49][0], /* fr17 */ \ | |
2386 | &rs6000_reg_names[50][0], /* fr18 */ \ | |
2387 | &rs6000_reg_names[51][0], /* fr19 */ \ | |
2388 | &rs6000_reg_names[52][0], /* fr20 */ \ | |
2389 | &rs6000_reg_names[53][0], /* fr21 */ \ | |
2390 | &rs6000_reg_names[54][0], /* fr22 */ \ | |
2391 | &rs6000_reg_names[55][0], /* fr23 */ \ | |
2392 | &rs6000_reg_names[56][0], /* fr24 */ \ | |
2393 | &rs6000_reg_names[57][0], /* fr25 */ \ | |
2394 | &rs6000_reg_names[58][0], /* fr26 */ \ | |
2395 | &rs6000_reg_names[59][0], /* fr27 */ \ | |
2396 | &rs6000_reg_names[60][0], /* fr28 */ \ | |
2397 | &rs6000_reg_names[61][0], /* fr29 */ \ | |
2398 | &rs6000_reg_names[62][0], /* fr30 */ \ | |
2399 | &rs6000_reg_names[63][0], /* fr31 */ \ | |
2400 | \ | |
462f7901 | 2401 | &rs6000_reg_names[64][0], /* was mq */ \ |
c81bebd7 MM |
2402 | &rs6000_reg_names[65][0], /* lr */ \ |
2403 | &rs6000_reg_names[66][0], /* ctr */ \ | |
2404 | &rs6000_reg_names[67][0], /* ap */ \ | |
2405 | \ | |
2406 | &rs6000_reg_names[68][0], /* cr0 */ \ | |
2407 | &rs6000_reg_names[69][0], /* cr1 */ \ | |
2408 | &rs6000_reg_names[70][0], /* cr2 */ \ | |
2409 | &rs6000_reg_names[71][0], /* cr3 */ \ | |
2410 | &rs6000_reg_names[72][0], /* cr4 */ \ | |
2411 | &rs6000_reg_names[73][0], /* cr5 */ \ | |
2412 | &rs6000_reg_names[74][0], /* cr6 */ \ | |
2413 | &rs6000_reg_names[75][0], /* cr7 */ \ | |
802a0058 | 2414 | \ |
f6b5d695 | 2415 | &rs6000_reg_names[76][0], /* ca */ \ |
0ac081f6 AH |
2416 | \ |
2417 | &rs6000_reg_names[77][0], /* v0 */ \ | |
2418 | &rs6000_reg_names[78][0], /* v1 */ \ | |
2419 | &rs6000_reg_names[79][0], /* v2 */ \ | |
2420 | &rs6000_reg_names[80][0], /* v3 */ \ | |
2421 | &rs6000_reg_names[81][0], /* v4 */ \ | |
2422 | &rs6000_reg_names[82][0], /* v5 */ \ | |
2423 | &rs6000_reg_names[83][0], /* v6 */ \ | |
2424 | &rs6000_reg_names[84][0], /* v7 */ \ | |
2425 | &rs6000_reg_names[85][0], /* v8 */ \ | |
2426 | &rs6000_reg_names[86][0], /* v9 */ \ | |
2427 | &rs6000_reg_names[87][0], /* v10 */ \ | |
2428 | &rs6000_reg_names[88][0], /* v11 */ \ | |
2429 | &rs6000_reg_names[89][0], /* v12 */ \ | |
2430 | &rs6000_reg_names[90][0], /* v13 */ \ | |
2431 | &rs6000_reg_names[91][0], /* v14 */ \ | |
2432 | &rs6000_reg_names[92][0], /* v15 */ \ | |
2433 | &rs6000_reg_names[93][0], /* v16 */ \ | |
2434 | &rs6000_reg_names[94][0], /* v17 */ \ | |
2435 | &rs6000_reg_names[95][0], /* v18 */ \ | |
2436 | &rs6000_reg_names[96][0], /* v19 */ \ | |
2437 | &rs6000_reg_names[97][0], /* v20 */ \ | |
2438 | &rs6000_reg_names[98][0], /* v21 */ \ | |
2439 | &rs6000_reg_names[99][0], /* v22 */ \ | |
2440 | &rs6000_reg_names[100][0], /* v23 */ \ | |
2441 | &rs6000_reg_names[101][0], /* v24 */ \ | |
2442 | &rs6000_reg_names[102][0], /* v25 */ \ | |
2443 | &rs6000_reg_names[103][0], /* v26 */ \ | |
2444 | &rs6000_reg_names[104][0], /* v27 */ \ | |
2445 | &rs6000_reg_names[105][0], /* v28 */ \ | |
2446 | &rs6000_reg_names[106][0], /* v29 */ \ | |
2447 | &rs6000_reg_names[107][0], /* v30 */ \ | |
2448 | &rs6000_reg_names[108][0], /* v31 */ \ | |
2449 | &rs6000_reg_names[109][0], /* vrsave */ \ | |
5f004351 | 2450 | &rs6000_reg_names[110][0], /* vscr */ \ |
a3170dc6 AH |
2451 | &rs6000_reg_names[111][0], /* spe_acc */ \ |
2452 | &rs6000_reg_names[112][0], /* spefscr */ \ | |
7d5175e1 | 2453 | &rs6000_reg_names[113][0], /* sfp */ \ |
0258b6e4 PB |
2454 | &rs6000_reg_names[114][0], /* tfhar */ \ |
2455 | &rs6000_reg_names[115][0], /* tfiar */ \ | |
2456 | &rs6000_reg_names[116][0], /* texasr */ \ | |
23742a9e RAR |
2457 | \ |
2458 | &rs6000_reg_names[117][0], /* SPE rh0. */ \ | |
2459 | &rs6000_reg_names[118][0], /* SPE rh1. */ \ | |
2460 | &rs6000_reg_names[119][0], /* SPE rh2. */ \ | |
2461 | &rs6000_reg_names[120][0], /* SPE rh3. */ \ | |
2462 | &rs6000_reg_names[121][0], /* SPE rh4. */ \ | |
2463 | &rs6000_reg_names[122][0], /* SPE rh5. */ \ | |
2464 | &rs6000_reg_names[123][0], /* SPE rh6. */ \ | |
2465 | &rs6000_reg_names[124][0], /* SPE rh7. */ \ | |
2466 | &rs6000_reg_names[125][0], /* SPE rh8. */ \ | |
2467 | &rs6000_reg_names[126][0], /* SPE rh9. */ \ | |
2468 | &rs6000_reg_names[127][0], /* SPE rh10. */ \ | |
2469 | &rs6000_reg_names[128][0], /* SPE rh11. */ \ | |
2470 | &rs6000_reg_names[129][0], /* SPE rh12. */ \ | |
2471 | &rs6000_reg_names[130][0], /* SPE rh13. */ \ | |
2472 | &rs6000_reg_names[131][0], /* SPE rh14. */ \ | |
2473 | &rs6000_reg_names[132][0], /* SPE rh15. */ \ | |
2474 | &rs6000_reg_names[133][0], /* SPE rh16. */ \ | |
2475 | &rs6000_reg_names[134][0], /* SPE rh17. */ \ | |
2476 | &rs6000_reg_names[135][0], /* SPE rh18. */ \ | |
2477 | &rs6000_reg_names[136][0], /* SPE rh19. */ \ | |
2478 | &rs6000_reg_names[137][0], /* SPE rh20. */ \ | |
2479 | &rs6000_reg_names[138][0], /* SPE rh21. */ \ | |
2480 | &rs6000_reg_names[139][0], /* SPE rh22. */ \ | |
2481 | &rs6000_reg_names[140][0], /* SPE rh22. */ \ | |
2482 | &rs6000_reg_names[141][0], /* SPE rh24. */ \ | |
2483 | &rs6000_reg_names[142][0], /* SPE rh25. */ \ | |
2484 | &rs6000_reg_names[143][0], /* SPE rh26. */ \ | |
2485 | &rs6000_reg_names[144][0], /* SPE rh27. */ \ | |
2486 | &rs6000_reg_names[145][0], /* SPE rh28. */ \ | |
2487 | &rs6000_reg_names[146][0], /* SPE rh29. */ \ | |
2488 | &rs6000_reg_names[147][0], /* SPE rh30. */ \ | |
2489 | &rs6000_reg_names[148][0], /* SPE rh31. */ \ | |
c81bebd7 MM |
2490 | } |
2491 | ||
f045b2c9 RS |
2492 | /* Table of additional register names to use in user input. */ |
2493 | ||
2494 | #define ADDITIONAL_REGISTER_NAMES \ | |
c4d38ccb MM |
2495 | {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ |
2496 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2497 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2498 | {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2499 | {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2500 | {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2501 | {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2502 | {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2503 | {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2504 | {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2505 | {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2506 | {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2507 | {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2508 | {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2509 | {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2510 | {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
0ac081f6 AH |
2511 | {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ |
2512 | {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
2513 | {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
2514 | {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
2515 | {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
2516 | {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
2517 | {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
2518 | {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
5f004351 | 2519 | {"vrsave", 109}, {"vscr", 110}, \ |
a3170dc6 | 2520 | {"spe_acc", 111}, {"spefscr", 112}, \ |
462f7901 | 2521 | /* no additional names for: lr, ctr, ap */ \ |
c4d38ccb MM |
2522 | {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ |
2523 | {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
cacf1ca8 | 2524 | {"cc", 68}, {"sp", 1}, {"toc", 2}, \ |
f6b5d695 SB |
2525 | /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
2526 | {"xer", 76}, \ | |
cacf1ca8 MM |
2527 | /* VSX registers overlaid on top of FR, Altivec registers */ \ |
2528 | {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ | |
2529 | {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ | |
2530 | {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ | |
2531 | {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ | |
2532 | {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ | |
2533 | {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ | |
2534 | {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ | |
2535 | {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ | |
2536 | {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ | |
2537 | {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ | |
2538 | {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ | |
2539 | {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ | |
2540 | {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ | |
2541 | {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ | |
2542 | {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ | |
0258b6e4 PB |
2543 | {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ |
2544 | /* Transactional Memory Facility (HTM) Registers. */ \ | |
23742a9e RAR |
2545 | {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \ |
2546 | /* SPE high registers. */ \ | |
2547 | {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \ | |
2548 | {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \ | |
2549 | {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \ | |
2550 | {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \ | |
2551 | {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \ | |
2552 | {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \ | |
2553 | {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \ | |
2554 | {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \ | |
2555 | } | |
f045b2c9 | 2556 | |
f045b2c9 RS |
2557 | /* This is how to output an element of a case-vector that is relative. */ |
2558 | ||
e1565e65 | 2559 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3daf36a4 | 2560 | do { char buf[100]; \ |
e1565e65 | 2561 | fputs ("\t.long ", FILE); \ |
3daf36a4 ILT |
2562 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ |
2563 | assemble_name (FILE, buf); \ | |
19d2d16f | 2564 | putc ('-', FILE); \ |
3daf36a4 ILT |
2565 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ |
2566 | assemble_name (FILE, buf); \ | |
19d2d16f | 2567 | putc ('\n', FILE); \ |
3daf36a4 | 2568 | } while (0) |
f045b2c9 RS |
2569 | |
2570 | /* This is how to output an assembler line | |
2571 | that says to advance the location counter | |
2572 | to a multiple of 2**LOG bytes. */ | |
2573 | ||
2574 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2575 | if ((LOG) != 0) \ | |
2576 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
2577 | ||
58082ff6 PH |
2578 | /* How to align the given loop. */ |
2579 | #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) | |
2580 | ||
d28073d4 BS |
2581 | /* Alignment guaranteed by __builtin_malloc. */ |
2582 | /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. | |
2583 | However, specifying the stronger guarantee currently leads to | |
2584 | a regression in SPEC CPU2006 437.leslie3d. The stronger | |
2585 | guarantee should be implemented here once that's fixed. */ | |
2586 | #define MALLOC_ABI_ALIGNMENT (64) | |
2587 | ||
9ebbca7d GK |
2588 | /* Pick up the return address upon entry to a procedure. Used for |
2589 | dwarf2 unwind information. This also enables the table driven | |
2590 | mechanism. */ | |
2591 | ||
1de43f85 DE |
2592 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) |
2593 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
9ebbca7d | 2594 | |
83720594 RH |
2595 | /* Describe how we implement __builtin_eh_return. */ |
2596 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2597 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2598 | ||
f045b2c9 RS |
2599 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2600 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2601 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2602 | ||
2603 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2604 | ||
2605 | /* Define which CODE values are valid. */ | |
2606 | ||
3cf437d4 | 2607 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') |
f045b2c9 RS |
2608 | |
2609 | /* Print a memory address as an operand to reference that memory location. */ | |
2610 | ||
2611 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2612 | ||
c82846bc DE |
2613 | /* For switching between functions with different target attributes. */ |
2614 | #define SWITCHABLE_TARGET 1 | |
2615 | ||
b6c9286a MM |
2616 | /* uncomment for disabling the corresponding default options */ |
2617 | /* #define MACHINE_no_sched_interblock */ | |
2618 | /* #define MACHINE_no_sched_speculative */ | |
2619 | /* #define MACHINE_no_sched_speculative_load */ | |
2620 | ||
766a866c | 2621 | /* General flags. */ |
a7df97e6 | 2622 | extern int frame_pointer_needed; |
0ac081f6 | 2623 | |
7fa14a01 MM |
2624 | /* Classification of the builtin functions as to which switches enable the |
2625 | builtin, and what attributes it should have. We used to use the target | |
2626 | flags macros, but we've run out of bits, so we now map the options into new | |
2627 | settings used here. */ | |
2628 | ||
2629 | /* Builtin attributes. */ | |
2630 | #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ | |
2631 | #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ | |
2632 | #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ | |
2633 | #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ | |
2634 | #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ | |
2635 | #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ | |
2636 | #define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */ | |
2637 | #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ | |
2638 | #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ | |
2639 | ||
2640 | #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ | |
2641 | #define RS6000_BTC_CONST 0x00000100 /* uses no global state. */ | |
2642 | #define RS6000_BTC_PURE 0x00000200 /* reads global state/mem. */ | |
2643 | #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ | |
2644 | #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ | |
2645 | ||
2646 | /* Miscellaneous information. */ | |
0258b6e4 PB |
2647 | #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ |
2648 | #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ | |
01f61a78 PB |
2649 | #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ |
2650 | #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ | |
0258b6e4 | 2651 | #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ |
1c9df37c MM |
2652 | |
2653 | /* Convenience macros to document the instruction type. */ | |
7fa14a01 MM |
2654 | #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ |
2655 | #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ | |
2656 | ||
2657 | /* Builtin targets. For now, we reuse the masks for those options that are in | |
8241efd1 PB |
2658 | target flags, and pick three random bits for SPE, paired and ldbl128 which |
2659 | aren't in target_flags. */ | |
4b705221 | 2660 | #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ |
7fa14a01 MM |
2661 | #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ |
2662 | #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ | |
f62511da | 2663 | #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ |
8fa97501 | 2664 | #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ |
f62511da | 2665 | #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ |
0258b6e4 | 2666 | #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ |
7fa14a01 MM |
2667 | #define RS6000_BTM_SPE MASK_STRING /* E500 */ |
2668 | #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ | |
2669 | #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ | |
2670 | #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ | |
2671 | #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ | |
2672 | #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ | |
2673 | #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ | |
7fa14a01 | 2674 | #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ |
06b39289 | 2675 | #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ |
f93bc5b3 | 2676 | #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ |
8241efd1 | 2677 | #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ |
7fa14a01 MM |
2678 | |
2679 | #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | |
2680 | | RS6000_BTM_VSX \ | |
f62511da | 2681 | | RS6000_BTM_P8_VECTOR \ |
8fa97501 | 2682 | | RS6000_BTM_P9_VECTOR \ |
f62511da | 2683 | | RS6000_BTM_CRYPTO \ |
7fa14a01 MM |
2684 | | RS6000_BTM_FRE \ |
2685 | | RS6000_BTM_FRES \ | |
2686 | | RS6000_BTM_FRSQRTE \ | |
2687 | | RS6000_BTM_FRSQRTES \ | |
0258b6e4 | 2688 | | RS6000_BTM_HTM \ |
7fa14a01 | 2689 | | RS6000_BTM_POPCNTD \ |
06b39289 | 2690 | | RS6000_BTM_CELL \ |
f93bc5b3 | 2691 | | RS6000_BTM_DFP \ |
8241efd1 | 2692 | | RS6000_BTM_HARD_FLOAT \ |
006df05d | 2693 | | RS6000_BTM_LDBL128) |
7fa14a01 MM |
2694 | |
2695 | /* Define builtin enum index. */ | |
2696 | ||
2697 | #undef RS6000_BUILTIN_1 | |
2698 | #undef RS6000_BUILTIN_2 | |
2699 | #undef RS6000_BUILTIN_3 | |
2700 | #undef RS6000_BUILTIN_A | |
2701 | #undef RS6000_BUILTIN_D | |
2702 | #undef RS6000_BUILTIN_E | |
0258b6e4 | 2703 | #undef RS6000_BUILTIN_H |
7fa14a01 MM |
2704 | #undef RS6000_BUILTIN_P |
2705 | #undef RS6000_BUILTIN_Q | |
2706 | #undef RS6000_BUILTIN_S | |
2707 | #undef RS6000_BUILTIN_X | |
2708 | ||
2709 | #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2710 | #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2711 | #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2712 | #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2713 | #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2714 | #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
0258b6e4 | 2715 | #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
7fa14a01 MM |
2716 | #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
2717 | #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2718 | #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2719 | #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
1c9df37c | 2720 | |
0ac081f6 AH |
2721 | enum rs6000_builtins |
2722 | { | |
1c9df37c | 2723 | #include "rs6000-builtin.def" |
a72c65c7 | 2724 | |
58646b77 PB |
2725 | RS6000_BUILTIN_COUNT |
2726 | }; | |
2727 | ||
7fa14a01 MM |
2728 | #undef RS6000_BUILTIN_1 |
2729 | #undef RS6000_BUILTIN_2 | |
2730 | #undef RS6000_BUILTIN_3 | |
2731 | #undef RS6000_BUILTIN_A | |
2732 | #undef RS6000_BUILTIN_D | |
2733 | #undef RS6000_BUILTIN_E | |
0258b6e4 | 2734 | #undef RS6000_BUILTIN_H |
7fa14a01 MM |
2735 | #undef RS6000_BUILTIN_P |
2736 | #undef RS6000_BUILTIN_Q | |
2737 | #undef RS6000_BUILTIN_S | |
2738 | #undef RS6000_BUILTIN_X | |
1c9df37c | 2739 | |
58646b77 PB |
2740 | enum rs6000_builtin_type_index |
2741 | { | |
2742 | RS6000_BTI_NOT_OPAQUE, | |
2743 | RS6000_BTI_opaque_V2SI, | |
2744 | RS6000_BTI_opaque_V2SF, | |
2745 | RS6000_BTI_opaque_p_V2SI, | |
2746 | RS6000_BTI_opaque_V4SI, | |
2747 | RS6000_BTI_V16QI, | |
a16a872d | 2748 | RS6000_BTI_V1TI, |
58646b77 PB |
2749 | RS6000_BTI_V2SI, |
2750 | RS6000_BTI_V2SF, | |
a72c65c7 MM |
2751 | RS6000_BTI_V2DI, |
2752 | RS6000_BTI_V2DF, | |
58646b77 PB |
2753 | RS6000_BTI_V4HI, |
2754 | RS6000_BTI_V4SI, | |
2755 | RS6000_BTI_V4SF, | |
2756 | RS6000_BTI_V8HI, | |
2757 | RS6000_BTI_unsigned_V16QI, | |
a16a872d | 2758 | RS6000_BTI_unsigned_V1TI, |
58646b77 PB |
2759 | RS6000_BTI_unsigned_V8HI, |
2760 | RS6000_BTI_unsigned_V4SI, | |
a72c65c7 | 2761 | RS6000_BTI_unsigned_V2DI, |
58646b77 PB |
2762 | RS6000_BTI_bool_char, /* __bool char */ |
2763 | RS6000_BTI_bool_short, /* __bool short */ | |
2764 | RS6000_BTI_bool_int, /* __bool int */ | |
a72c65c7 | 2765 | RS6000_BTI_bool_long, /* __bool long */ |
58646b77 PB |
2766 | RS6000_BTI_pixel, /* __pixel */ |
2767 | RS6000_BTI_bool_V16QI, /* __vector __bool char */ | |
2768 | RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
2769 | RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
a72c65c7 | 2770 | RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
58646b77 PB |
2771 | RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
2772 | RS6000_BTI_long, /* long_integer_type_node */ | |
2773 | RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
c9485473 MM |
2774 | RS6000_BTI_long_long, /* long_long_integer_type_node */ |
2775 | RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ | |
58646b77 PB |
2776 | RS6000_BTI_INTQI, /* intQI_type_node */ |
2777 | RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ | |
2778 | RS6000_BTI_INTHI, /* intHI_type_node */ | |
2779 | RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
2780 | RS6000_BTI_INTSI, /* intSI_type_node */ | |
2781 | RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ | |
a72c65c7 MM |
2782 | RS6000_BTI_INTDI, /* intDI_type_node */ |
2783 | RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ | |
a16a872d MM |
2784 | RS6000_BTI_INTTI, /* intTI_type_node */ |
2785 | RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ | |
58646b77 | 2786 | RS6000_BTI_float, /* float_type_node */ |
a72c65c7 | 2787 | RS6000_BTI_double, /* double_type_node */ |
06b39289 MM |
2788 | RS6000_BTI_long_double, /* long_double_type_node */ |
2789 | RS6000_BTI_dfloat64, /* dfloat64_type_node */ | |
2790 | RS6000_BTI_dfloat128, /* dfloat128_type_node */ | |
58646b77 | 2791 | RS6000_BTI_void, /* void_type_node */ |
6712d6fd MM |
2792 | RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ |
2793 | RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ | |
58646b77 | 2794 | RS6000_BTI_MAX |
0ac081f6 | 2795 | }; |
58646b77 PB |
2796 | |
2797 | ||
2798 | #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) | |
2799 | #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) | |
2800 | #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) | |
2801 | #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) | |
2802 | #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
a16a872d | 2803 | #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) |
a72c65c7 MM |
2804 | #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
2805 | #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) | |
58646b77 PB |
2806 | #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) |
2807 | #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) | |
2808 | #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) | |
2809 | #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
2810 | #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
2811 | #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
2812 | #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
a16a872d | 2813 | #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) |
58646b77 PB |
2814 | #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) |
2815 | #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
a72c65c7 | 2816 | #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
58646b77 PB |
2817 | #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
2818 | #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
2819 | #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
a72c65c7 | 2820 | #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) |
58646b77 PB |
2821 | #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
2822 | #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
2823 | #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
2824 | #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
a72c65c7 | 2825 | #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
58646b77 PB |
2826 | #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
2827 | ||
c9485473 MM |
2828 | #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
2829 | #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) | |
58646b77 PB |
2830 | #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
2831 | #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
2832 | #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
2833 | #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
2834 | #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
2835 | #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
2836 | #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
2837 | #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
a72c65c7 MM |
2838 | #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
2839 | #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) | |
a16a872d MM |
2840 | #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) |
2841 | #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) | |
58646b77 | 2842 | #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
a72c65c7 | 2843 | #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
06b39289 MM |
2844 | #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) |
2845 | #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) | |
2846 | #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) | |
58646b77 | 2847 | #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
6712d6fd MM |
2848 | #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) |
2849 | #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) | |
58646b77 PB |
2850 | |
2851 | extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
2852 | extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
2853 | ||
807e902e | 2854 | #define TARGET_SUPPORTS_WIDE_INT 1 |