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996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
8ef65e3d 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
602ea4d3 4;; Free Software Foundation, Inc.
996a5f59 5;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 6
5de601cf 7;; This file is part of GCC.
1fd4e8c1 8
5de601cf
NC		 9;; GCC is free software; you can redistribute it and/or modify it
10;; under the terms of the GNU General Public License as published
2f83c7d6 11;; by the Free Software Foundation; either version 3, or (at your
5de601cf 12;; option) any later version.
1fd4e8c1 13
5de601cf
NC		 14;; GCC is distributed in the hope that it will be useful, but WITHOUT
15;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17;; License for more details.
1fd4e8c1
RK		 18
19;; You should have received a copy of the GNU General Public License
2f83c7d6
NC		 20;; along with GCC; see the file COPYING3. If not see
21;; <http://www.gnu.org/licenses/>.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 24
1de43f85
DE		 25;;
26;; REGNOS
27;;
28
29(define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
615158e2
JJ		 52;;
53;; UNSPEC usage
54;;
55
56(define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
9719f3b7
DE		 64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
615158e2
JJ		 68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
ecb62ae7 83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
cef6b86c 84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
da4c340c 85 (UNSPEC_STFIWX 32)
9f0076e5
DE		 86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
716019c0
JM		 98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
615158e2
JJ		 101 ])
102
103;;
104;; UNSPEC_VOLATILE usage
105;;
106
107(define_constants
108 [(UNSPECV_BLOCK 0)
b52110d4
DE		 109 (UNSPECV_LL 1) ; load-locked
110 (UNSPECV_SC 2) ; store-conditional
615158e2
JJ		 111 (UNSPECV_EH_RR 9) ; eh_reg_restore
112 ])
1fd4e8c1
RK		 113\f
114;; Define an insn type attribute. This is used in function unit delay
115;; computations.
44cd321e 116(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
1fd4e8c1
RK		 117 (const_string "integer"))
118
b19003d8 119;; Length (in bytes).
6ae08853 120; '(pc)' in the following doesn't include the instruction itself; it is
6cbadf36 121; calculated as if the instruction had zero size.
b19003d8
RK		 122(define_attr "length" ""
123 (if_then_else (eq_attr "type" "branch")
6cbadf36 124 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 125 (const_int -32768))
6cbadf36
GK		 126 (lt (minus (match_dup 0) (pc))
127 (const_int 32764)))
39a10a29
GK		 128 (const_int 4)
129 (const_int 8))
b19003d8
RK		 130 (const_int 4)))
131
cfb557c4
RK		 132;; Processor type -- this attribute must exactly match the processor_type
133;; enumeration in rs6000.h.
134
d296e02e 135(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
cfb557c4
RK		 136 (const (symbol_ref "rs6000_cpu_attr")))
137
d296e02e
AP		 138
139;; If this instruction is microcoded on the CELL processor
140; The default for load and stores is conditional
141; The default for load extended and the recorded instructions is always microcoded
142(define_attr "cell_micro" "not,conditional,always"
143 (if_then_else (ior (ior (eq_attr "type" "load")
144 (eq_attr "type" "store"))
145 (ior (eq_attr "type" "fpload")
146 (eq_attr "type" "fpstore")))
147 (const_string "conditional")
148 (if_then_else (ior (eq_attr "type" "load_ext")
149 (ior (eq_attr "type" "compare")
150 (eq_attr "type" "delayed_compare")))
151 (const_string "always")
152 (const_string "not"))))
153
154
b54cf83a
DE		 155(automata_option "ndfa")
156
157(include "rios1.md")
158(include "rios2.md")
159(include "rs64.md")
160(include "mpc.md")
161(include "40x.md")
02ca7595 162(include "440.md")
b54cf83a
DE		 163(include "603.md")
164(include "6xx.md")
165(include "7xx.md")
166(include "7450.md")
5e8006fa 167(include "8540.md")
b54cf83a 168(include "power4.md")
ec507f2d 169(include "power5.md")
44cd321e 170(include "power6.md")
d296e02e 171(include "cell.md")
48d72335
DE		 172
173(include "predicates.md")
279bb624 174(include "constraints.md")
48d72335 175
ac9e2cff 176(include "darwin.md")
309323c2 177
1fd4e8c1 178\f
3abcb3a7 179;; Mode iterators
915167f5 180
3abcb3a7 181; This mode iterator allows :GPR to be used to indicate the allowable size
915167f5 182; of whole values in GPRs.
3abcb3a7 183(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
915167f5 184
0354e5d8 185; Any supported integer mode.
3abcb3a7 186(define_mode_iterator INT [QI HI SI DI TI])
915167f5 187
0354e5d8 188; Any supported integer mode that fits in one register.
3abcb3a7 189(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
915167f5 190
b5568f07 191; extend modes for DImode
3abcb3a7 192(define_mode_iterator QHSI [QI HI SI])
b5568f07 193
0354e5d8 194; SImode or DImode, even if DImode doesn't fit in GPRs.
3abcb3a7 195(define_mode_iterator SDI [SI DI])
0354e5d8
GK		 196
197; The size of a pointer. Also, the size of the value that a record-condition
198; (one with a '.') will compare.
3abcb3a7 199(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
2e6c9641 200
4ae234b0 201; Any hardware-supported floating-point mode
3abcb3a7 202(define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
4ae234b0 203 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
602ea4d3 204 (TF "!TARGET_IEEEQUAD
17caeff2
JM		 205 && TARGET_HARD_FLOAT
206 && (TARGET_FPRS || TARGET_E500_DOUBLE)
207 && TARGET_LONG_DOUBLE_128")])
4ae234b0 208
915167f5 209; Various instructions that come in SI and DI forms.
0354e5d8 210; A generic w/d attribute, for things like cmpw/cmpd.
b5568f07
DE		 211(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
212
213; DImode bits
214(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
915167f5
GK		 215
216\f
1fd4e8c1
RK		 217;; Start with fixed-point load and store insns. Here we put only the more
218;; complex forms. Basic data transfer is done later.
219
b5568f07 220(define_expand "zero_extend<mode>di2"
51b8fc2c 221 [(set (match_operand:DI 0 "gpc_reg_operand" "")
b5568f07 222 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
51b8fc2c
RK		 223 "TARGET_POWERPC64"
224 "")
225
b5568f07 226(define_insn "*zero_extend<mode>di2_internal1"
51b8fc2c 227 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
b5568f07 228 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
51b8fc2c
RK		 229 "TARGET_POWERPC64"
230 "@
b5568f07
DE		 231 l<wd>z%U1%X1 %0,%1
232 rldicl %0,%1,0,<dbits>"
51b8fc2c
RK		 233 [(set_attr "type" "load,*")])
234
b5568f07 235(define_insn "*zero_extend<mode>di2_internal2"
9ebbca7d 236 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
b5568f07 237 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
815cdc52 238 (const_int 0)))
9ebbca7d 239 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 240 "TARGET_64BIT"
9ebbca7d 241 "@
b5568f07 242 rldicl. %2,%1,0,<dbits>
9ebbca7d
GK		 243 #"
244 [(set_attr "type" "compare")
245 (set_attr "length" "4,8")])
246
247(define_split
248 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
b5568f07 249 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 250 (const_int 0)))
251 (clobber (match_scratch:DI 2 ""))]
252 "TARGET_POWERPC64 && reload_completed"
253 [(set (match_dup 2)
254 (zero_extend:DI (match_dup 1)))
255 (set (match_dup 0)
256 (compare:CC (match_dup 2)
257 (const_int 0)))]
258 "")
51b8fc2c 259
b5568f07 260(define_insn "*zero_extend<mode>di2_internal3"
9ebbca7d 261 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
b5568f07 262 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 263 (const_int 0)))
9ebbca7d 264 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 265 (zero_extend:DI (match_dup 1)))]
683bdff7 266 "TARGET_64BIT"
9ebbca7d 267 "@
b5568f07 268 rldicl. %0,%1,0,<dbits>
9ebbca7d
GK		 269 #"
270 [(set_attr "type" "compare")
271 (set_attr "length" "4,8")])
272
273(define_split
274 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
b5568f07 275 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 276 (const_int 0)))
277 (set (match_operand:DI 0 "gpc_reg_operand" "")
278 (zero_extend:DI (match_dup 1)))]
279 "TARGET_POWERPC64 && reload_completed"
280 [(set (match_dup 0)
281 (zero_extend:DI (match_dup 1)))
282 (set (match_dup 2)
283 (compare:CC (match_dup 0)
284 (const_int 0)))]
285 "")
51b8fc2c 286
2bee0449
RK		 287(define_insn "extendqidi2"
288 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
289 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 290 "TARGET_POWERPC64"
44cd321e
PS		 291 "extsb %0,%1"
292 [(set_attr "type" "exts")])
51b8fc2c
RK		 293
294(define_insn ""
9ebbca7d
GK		 295 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
296 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 297 (const_int 0)))
9ebbca7d 298 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 299 "TARGET_64BIT"
9ebbca7d
GK		 300 "@
301 extsb. %2,%1
302 #"
303 [(set_attr "type" "compare")
304 (set_attr "length" "4,8")])
305
306(define_split
307 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
308 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
309 (const_int 0)))
310 (clobber (match_scratch:DI 2 ""))]
311 "TARGET_POWERPC64 && reload_completed"
312 [(set (match_dup 2)
313 (sign_extend:DI (match_dup 1)))
314 (set (match_dup 0)
315 (compare:CC (match_dup 2)
316 (const_int 0)))]
317 "")
51b8fc2c
RK		 318
319(define_insn ""
9ebbca7d
GK		 320 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
321 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 322 (const_int 0)))
9ebbca7d 323 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 324 (sign_extend:DI (match_dup 1)))]
683bdff7 325 "TARGET_64BIT"
9ebbca7d
GK		 326 "@
327 extsb. %0,%1
328 #"
329 [(set_attr "type" "compare")
330 (set_attr "length" "4,8")])
331
332(define_split
333 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
334 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
335 (const_int 0)))
336 (set (match_operand:DI 0 "gpc_reg_operand" "")
337 (sign_extend:DI (match_dup 1)))]
338 "TARGET_POWERPC64 && reload_completed"
339 [(set (match_dup 0)
340 (sign_extend:DI (match_dup 1)))
341 (set (match_dup 2)
342 (compare:CC (match_dup 0)
343 (const_int 0)))]
344 "")
51b8fc2c 345
51b8fc2c
RK		 346(define_expand "extendhidi2"
347 [(set (match_operand:DI 0 "gpc_reg_operand" "")
348 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
349 "TARGET_POWERPC64"
350 "")
351
352(define_insn ""
353 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
354 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
355 "TARGET_POWERPC64"
356 "@
357 lha%U1%X1 %0,%1
358 extsh %0,%1"
44cd321e 359 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 360
361(define_insn ""
9ebbca7d
GK		 362 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
363 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 364 (const_int 0)))
9ebbca7d 365 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 366 "TARGET_64BIT"
9ebbca7d
GK		 367 "@
368 extsh. %2,%1
369 #"
370 [(set_attr "type" "compare")
371 (set_attr "length" "4,8")])
372
373(define_split
374 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
375 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
376 (const_int 0)))
377 (clobber (match_scratch:DI 2 ""))]
378 "TARGET_POWERPC64 && reload_completed"
379 [(set (match_dup 2)
380 (sign_extend:DI (match_dup 1)))
381 (set (match_dup 0)
382 (compare:CC (match_dup 2)
383 (const_int 0)))]
384 "")
51b8fc2c
RK		 385
386(define_insn ""
9ebbca7d
GK		 387 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
388 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 389 (const_int 0)))
9ebbca7d 390 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 391 (sign_extend:DI (match_dup 1)))]
683bdff7 392 "TARGET_64BIT"
9ebbca7d
GK		 393 "@
394 extsh. %0,%1
395 #"
396 [(set_attr "type" "compare")
397 (set_attr "length" "4,8")])
398
399(define_split
400 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
401 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
402 (const_int 0)))
403 (set (match_operand:DI 0 "gpc_reg_operand" "")
404 (sign_extend:DI (match_dup 1)))]
405 "TARGET_POWERPC64 && reload_completed"
406 [(set (match_dup 0)
407 (sign_extend:DI (match_dup 1)))
408 (set (match_dup 2)
409 (compare:CC (match_dup 0)
410 (const_int 0)))]
411 "")
51b8fc2c 412
51b8fc2c
RK		 413(define_expand "extendsidi2"
414 [(set (match_operand:DI 0 "gpc_reg_operand" "")
415 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
416 "TARGET_POWERPC64"
417 "")
418
419(define_insn ""
420 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 421 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
51b8fc2c
RK		 422 "TARGET_POWERPC64"
423 "@
424 lwa%U1%X1 %0,%1
425 extsw %0,%1"
44cd321e 426 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 427
428(define_insn ""
9ebbca7d
GK		 429 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
430 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 431 (const_int 0)))
9ebbca7d 432 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 433 "TARGET_64BIT"
9ebbca7d
GK		 434 "@
435 extsw. %2,%1
436 #"
437 [(set_attr "type" "compare")
438 (set_attr "length" "4,8")])
439
440(define_split
441 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
442 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
443 (const_int 0)))
444 (clobber (match_scratch:DI 2 ""))]
445 "TARGET_POWERPC64 && reload_completed"
446 [(set (match_dup 2)
447 (sign_extend:DI (match_dup 1)))
448 (set (match_dup 0)
449 (compare:CC (match_dup 2)
450 (const_int 0)))]
451 "")
51b8fc2c
RK		 452
453(define_insn ""
9ebbca7d
GK		 454 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
455 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 456 (const_int 0)))
9ebbca7d 457 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 458 (sign_extend:DI (match_dup 1)))]
683bdff7 459 "TARGET_64BIT"
9ebbca7d
GK		 460 "@
461 extsw. %0,%1
462 #"
463 [(set_attr "type" "compare")
464 (set_attr "length" "4,8")])
465
466(define_split
467 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
468 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
469 (const_int 0)))
470 (set (match_operand:DI 0 "gpc_reg_operand" "")
471 (sign_extend:DI (match_dup 1)))]
472 "TARGET_POWERPC64 && reload_completed"
473 [(set (match_dup 0)
474 (sign_extend:DI (match_dup 1)))
475 (set (match_dup 2)
476 (compare:CC (match_dup 0)
477 (const_int 0)))]
478 "")
51b8fc2c 479
1fd4e8c1 480(define_expand "zero_extendqisi2"
cd2b37d9
RK		 481 [(set (match_operand:SI 0 "gpc_reg_operand" "")
482 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 483 ""
484 "")
485
486(define_insn ""
cd2b37d9 487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 488 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
489 ""
490 "@
491 lbz%U1%X1 %0,%1
005a35b9 492 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 493 [(set_attr "type" "load,*")])
494
495(define_insn ""
9ebbca7d
GK		 496 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
497 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 498 (const_int 0)))
9ebbca7d 499 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 500 ""
9ebbca7d
GK		 501 "@
502 {andil.|andi.} %2,%1,0xff
503 #"
504 [(set_attr "type" "compare")
505 (set_attr "length" "4,8")])
506
507(define_split
508 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
509 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
510 (const_int 0)))
511 (clobber (match_scratch:SI 2 ""))]
512 "reload_completed"
513 [(set (match_dup 2)
514 (zero_extend:SI (match_dup 1)))
515 (set (match_dup 0)
516 (compare:CC (match_dup 2)
517 (const_int 0)))]
518 "")
1fd4e8c1
RK		 519
520(define_insn ""
9ebbca7d
GK		 521 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
522 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 523 (const_int 0)))
9ebbca7d 524 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 525 (zero_extend:SI (match_dup 1)))]
526 ""
9ebbca7d
GK		 527 "@
528 {andil.|andi.} %0,%1,0xff
529 #"
530 [(set_attr "type" "compare")
531 (set_attr "length" "4,8")])
532
533(define_split
534 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
535 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
536 (const_int 0)))
537 (set (match_operand:SI 0 "gpc_reg_operand" "")
538 (zero_extend:SI (match_dup 1)))]
539 "reload_completed"
540 [(set (match_dup 0)
541 (zero_extend:SI (match_dup 1)))
542 (set (match_dup 2)
543 (compare:CC (match_dup 0)
544 (const_int 0)))]
545 "")
1fd4e8c1 546
51b8fc2c
RK		 547(define_expand "extendqisi2"
548 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
549 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
550 ""
551 "
552{
553 if (TARGET_POWERPC)
554 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
555 else if (TARGET_POWER)
556 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
557 else
558 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
559 DONE;
560}")
561
562(define_insn "extendqisi2_ppc"
2bee0449
RK		 563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
564 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 565 "TARGET_POWERPC"
44cd321e
PS		 566 "extsb %0,%1"
567 [(set_attr "type" "exts")])
51b8fc2c
RK		 568
569(define_insn ""
9ebbca7d
GK		 570 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
571 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 572 (const_int 0)))
9ebbca7d 573 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 574 "TARGET_POWERPC"
9ebbca7d
GK		 575 "@
576 extsb. %2,%1
577 #"
578 [(set_attr "type" "compare")
579 (set_attr "length" "4,8")])
580
581(define_split
582 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
583 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
584 (const_int 0)))
585 (clobber (match_scratch:SI 2 ""))]
586 "TARGET_POWERPC && reload_completed"
587 [(set (match_dup 2)
588 (sign_extend:SI (match_dup 1)))
589 (set (match_dup 0)
590 (compare:CC (match_dup 2)
591 (const_int 0)))]
592 "")
51b8fc2c
RK		 593
594(define_insn ""
9ebbca7d
GK		 595 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
596 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 597 (const_int 0)))
9ebbca7d 598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 599 (sign_extend:SI (match_dup 1)))]
600 "TARGET_POWERPC"
9ebbca7d
GK		 601 "@
602 extsb. %0,%1
603 #"
604 [(set_attr "type" "compare")
605 (set_attr "length" "4,8")])
606
607(define_split
608 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
609 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
610 (const_int 0)))
611 (set (match_operand:SI 0 "gpc_reg_operand" "")
612 (sign_extend:SI (match_dup 1)))]
613 "TARGET_POWERPC && reload_completed"
614 [(set (match_dup 0)
615 (sign_extend:SI (match_dup 1)))
616 (set (match_dup 2)
617 (compare:CC (match_dup 0)
618 (const_int 0)))]
619 "")
51b8fc2c
RK		 620
621(define_expand "extendqisi2_power"
622 [(parallel [(set (match_dup 2)
623 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
624 (const_int 24)))
625 (clobber (scratch:SI))])
626 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
627 (ashiftrt:SI (match_dup 2)
628 (const_int 24)))
629 (clobber (scratch:SI))])]
630 "TARGET_POWER"
631 "
632{ operands[1] = gen_lowpart (SImode, operands[1]);
633 operands[2] = gen_reg_rtx (SImode); }")
634
635(define_expand "extendqisi2_no_power"
636 [(set (match_dup 2)
637 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
638 (const_int 24)))
639 (set (match_operand:SI 0 "gpc_reg_operand" "")
640 (ashiftrt:SI (match_dup 2)
641 (const_int 24)))]
642 "! TARGET_POWER && ! TARGET_POWERPC"
643 "
644{ operands[1] = gen_lowpart (SImode, operands[1]);
645 operands[2] = gen_reg_rtx (SImode); }")
646
1fd4e8c1 647(define_expand "zero_extendqihi2"
cd2b37d9
RK		 648 [(set (match_operand:HI 0 "gpc_reg_operand" "")
649 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 650 ""
651 "")
652
653(define_insn ""
cd2b37d9 654 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 655 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
656 ""
657 "@
658 lbz%U1%X1 %0,%1
005a35b9 659 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 660 [(set_attr "type" "load,*")])
661
662(define_insn ""
9ebbca7d
GK		 663 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
664 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 665 (const_int 0)))
9ebbca7d 666 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 667 ""
9ebbca7d
GK		 668 "@
669 {andil.|andi.} %2,%1,0xff
670 #"
671 [(set_attr "type" "compare")
672 (set_attr "length" "4,8")])
673
674(define_split
675 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
676 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
677 (const_int 0)))
678 (clobber (match_scratch:HI 2 ""))]
679 "reload_completed"
680 [(set (match_dup 2)
681 (zero_extend:HI (match_dup 1)))
682 (set (match_dup 0)
683 (compare:CC (match_dup 2)
684 (const_int 0)))]
685 "")
1fd4e8c1 686
51b8fc2c 687(define_insn ""
9ebbca7d
GK		 688 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
689 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 690 (const_int 0)))
9ebbca7d 691 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 692 (zero_extend:HI (match_dup 1)))]
693 ""
9ebbca7d
GK		 694 "@
695 {andil.|andi.} %0,%1,0xff
696 #"
697 [(set_attr "type" "compare")
698 (set_attr "length" "4,8")])
699
700(define_split
701 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
702 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
703 (const_int 0)))
704 (set (match_operand:HI 0 "gpc_reg_operand" "")
705 (zero_extend:HI (match_dup 1)))]
706 "reload_completed"
707 [(set (match_dup 0)
708 (zero_extend:HI (match_dup 1)))
709 (set (match_dup 2)
710 (compare:CC (match_dup 0)
711 (const_int 0)))]
712 "")
815cdc52
MM		 713
714(define_expand "extendqihi2"
715 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
716 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
717 ""
718 "
719{
720 if (TARGET_POWERPC)
721 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
722 else if (TARGET_POWER)
723 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
724 else
725 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
726 DONE;
727}")
728
729(define_insn "extendqihi2_ppc"
730 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
731 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
732 "TARGET_POWERPC"
44cd321e
PS		 733 "extsb %0,%1"
734 [(set_attr "type" "exts")])
815cdc52
MM		 735
736(define_insn ""
9ebbca7d
GK		 737 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
738 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 739 (const_int 0)))
9ebbca7d 740 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 741 "TARGET_POWERPC"
9ebbca7d
GK		 742 "@
743 extsb. %2,%1
744 #"
745 [(set_attr "type" "compare")
746 (set_attr "length" "4,8")])
747
748(define_split
749 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
750 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
751 (const_int 0)))
752 (clobber (match_scratch:HI 2 ""))]
753 "TARGET_POWERPC && reload_completed"
754 [(set (match_dup 2)
755 (sign_extend:HI (match_dup 1)))
756 (set (match_dup 0)
757 (compare:CC (match_dup 2)
758 (const_int 0)))]
759 "")
815cdc52
MM		 760
761(define_insn ""
9ebbca7d
GK		 762 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
763 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 764 (const_int 0)))
9ebbca7d 765 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 766 (sign_extend:HI (match_dup 1)))]
767 "TARGET_POWERPC"
9ebbca7d
GK		 768 "@
769 extsb. %0,%1
770 #"
771 [(set_attr "type" "compare")
772 (set_attr "length" "4,8")])
773
774(define_split
775 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
776 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
777 (const_int 0)))
778 (set (match_operand:HI 0 "gpc_reg_operand" "")
779 (sign_extend:HI (match_dup 1)))]
780 "TARGET_POWERPC && reload_completed"
781 [(set (match_dup 0)
782 (sign_extend:HI (match_dup 1)))
783 (set (match_dup 2)
784 (compare:CC (match_dup 0)
785 (const_int 0)))]
786 "")
51b8fc2c
RK		 787
788(define_expand "extendqihi2_power"
789 [(parallel [(set (match_dup 2)
790 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
791 (const_int 24)))
792 (clobber (scratch:SI))])
793 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
794 (ashiftrt:SI (match_dup 2)
795 (const_int 24)))
796 (clobber (scratch:SI))])]
797 "TARGET_POWER"
798 "
799{ operands[0] = gen_lowpart (SImode, operands[0]);
800 operands[1] = gen_lowpart (SImode, operands[1]);
801 operands[2] = gen_reg_rtx (SImode); }")
802
803(define_expand "extendqihi2_no_power"
804 [(set (match_dup 2)
805 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
806 (const_int 24)))
807 (set (match_operand:HI 0 "gpc_reg_operand" "")
808 (ashiftrt:SI (match_dup 2)
809 (const_int 24)))]
810 "! TARGET_POWER && ! TARGET_POWERPC"
811 "
812{ operands[0] = gen_lowpart (SImode, operands[0]);
813 operands[1] = gen_lowpart (SImode, operands[1]);
814 operands[2] = gen_reg_rtx (SImode); }")
815
1fd4e8c1 816(define_expand "zero_extendhisi2"
5f243543 817 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 818 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 819 ""
820 "")
821
822(define_insn ""
cd2b37d9 823 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 824 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
825 ""
826 "@
827 lhz%U1%X1 %0,%1
005a35b9 828 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 829 [(set_attr "type" "load,*")])
830
831(define_insn ""
9ebbca7d
GK		 832 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
833 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 834 (const_int 0)))
9ebbca7d 835 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 836 ""
9ebbca7d
GK		 837 "@
838 {andil.|andi.} %2,%1,0xffff
839 #"
840 [(set_attr "type" "compare")
841 (set_attr "length" "4,8")])
842
843(define_split
844 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
845 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
846 (const_int 0)))
847 (clobber (match_scratch:SI 2 ""))]
848 "reload_completed"
849 [(set (match_dup 2)
850 (zero_extend:SI (match_dup 1)))
851 (set (match_dup 0)
852 (compare:CC (match_dup 2)
853 (const_int 0)))]
854 "")
1fd4e8c1
RK		 855
856(define_insn ""
9ebbca7d
GK		 857 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
858 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 859 (const_int 0)))
9ebbca7d 860 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 861 (zero_extend:SI (match_dup 1)))]
862 ""
9ebbca7d
GK		 863 "@
864 {andil.|andi.} %0,%1,0xffff
865 #"
866 [(set_attr "type" "compare")
867 (set_attr "length" "4,8")])
868
869(define_split
870 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
871 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
872 (const_int 0)))
873 (set (match_operand:SI 0 "gpc_reg_operand" "")
874 (zero_extend:SI (match_dup 1)))]
875 "reload_completed"
876 [(set (match_dup 0)
877 (zero_extend:SI (match_dup 1)))
878 (set (match_dup 2)
879 (compare:CC (match_dup 0)
880 (const_int 0)))]
881 "")
1fd4e8c1
RK		 882
883(define_expand "extendhisi2"
cd2b37d9
RK		 884 [(set (match_operand:SI 0 "gpc_reg_operand" "")
885 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 886 ""
887 "")
888
889(define_insn ""
cd2b37d9 890 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 891 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
892 ""
893 "@
894 lha%U1%X1 %0,%1
ca7f5001 895 {exts|extsh} %0,%1"
44cd321e 896 [(set_attr "type" "load_ext,exts")])
1fd4e8c1
RK		 897
898(define_insn ""
9ebbca7d
GK		 899 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
900 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 901 (const_int 0)))
9ebbca7d 902 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 903 ""
9ebbca7d
GK		 904 "@
905 {exts.|extsh.} %2,%1
906 #"
907 [(set_attr "type" "compare")
908 (set_attr "length" "4,8")])
909
910(define_split
911 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
912 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
913 (const_int 0)))
914 (clobber (match_scratch:SI 2 ""))]
915 "reload_completed"
916 [(set (match_dup 2)
917 (sign_extend:SI (match_dup 1)))
918 (set (match_dup 0)
919 (compare:CC (match_dup 2)
920 (const_int 0)))]
921 "")
1fd4e8c1
RK		 922
923(define_insn ""
9ebbca7d
GK		 924 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
925 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 926 (const_int 0)))
9ebbca7d 927 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 928 (sign_extend:SI (match_dup 1)))]
929 ""
9ebbca7d
GK		 930 "@
931 {exts.|extsh.} %0,%1
932 #"
933 [(set_attr "type" "compare")
934 (set_attr "length" "4,8")])
1fd4e8c1 935\f
131aeb82
JM		 936;; IBM 405 and 440 half-word multiplication operations.
937
938(define_insn "*macchwc"
939 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
940 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
941 (match_operand:SI 2 "gpc_reg_operand" "r")
942 (const_int 16))
943 (sign_extend:SI
944 (match_operand:HI 1 "gpc_reg_operand" "r")))
945 (match_operand:SI 4 "gpc_reg_operand" "0"))
946 (const_int 0)))
947 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
948 (plus:SI (mult:SI (ashiftrt:SI
949 (match_dup 2)
950 (const_int 16))
951 (sign_extend:SI
952 (match_dup 1)))
953 (match_dup 4)))]
954 "TARGET_MULHW"
955 "macchw. %0, %1, %2"
956 [(set_attr "type" "imul3")])
957
958(define_insn "*macchw"
959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
960 (plus:SI (mult:SI (ashiftrt:SI
961 (match_operand:SI 2 "gpc_reg_operand" "r")
962 (const_int 16))
963 (sign_extend:SI
964 (match_operand:HI 1 "gpc_reg_operand" "r")))
965 (match_operand:SI 3 "gpc_reg_operand" "0")))]
966 "TARGET_MULHW"
967 "macchw %0, %1, %2"
968 [(set_attr "type" "imul3")])
969
970(define_insn "*macchwuc"
971 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
972 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
973 (match_operand:SI 2 "gpc_reg_operand" "r")
974 (const_int 16))
975 (zero_extend:SI
976 (match_operand:HI 1 "gpc_reg_operand" "r")))
977 (match_operand:SI 4 "gpc_reg_operand" "0"))
978 (const_int 0)))
979 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
980 (plus:SI (mult:SI (lshiftrt:SI
981 (match_dup 2)
982 (const_int 16))
983 (zero_extend:SI
984 (match_dup 1)))
985 (match_dup 4)))]
986 "TARGET_MULHW"
987 "macchwu. %0, %1, %2"
988 [(set_attr "type" "imul3")])
989
990(define_insn "*macchwu"
991 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
992 (plus:SI (mult:SI (lshiftrt:SI
993 (match_operand:SI 2 "gpc_reg_operand" "r")
994 (const_int 16))
995 (zero_extend:SI
996 (match_operand:HI 1 "gpc_reg_operand" "r")))
997 (match_operand:SI 3 "gpc_reg_operand" "0")))]
998 "TARGET_MULHW"
999 "macchwu %0, %1, %2"
1000 [(set_attr "type" "imul3")])
1001
1002(define_insn "*machhwc"
1003 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1004 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1005 (match_operand:SI 1 "gpc_reg_operand" "%r")
1006 (const_int 16))
1007 (ashiftrt:SI
1008 (match_operand:SI 2 "gpc_reg_operand" "r")
1009 (const_int 16)))
1010 (match_operand:SI 4 "gpc_reg_operand" "0"))
1011 (const_int 0)))
1012 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1013 (plus:SI (mult:SI (ashiftrt:SI
1014 (match_dup 1)
1015 (const_int 16))
1016 (ashiftrt:SI
1017 (match_dup 2)
1018 (const_int 16)))
1019 (match_dup 4)))]
1020 "TARGET_MULHW"
1021 "machhw. %0, %1, %2"
1022 [(set_attr "type" "imul3")])
1023
1024(define_insn "*machhw"
1025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1026 (plus:SI (mult:SI (ashiftrt:SI
1027 (match_operand:SI 1 "gpc_reg_operand" "%r")
1028 (const_int 16))
1029 (ashiftrt:SI
1030 (match_operand:SI 2 "gpc_reg_operand" "r")
1031 (const_int 16)))
1032 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1033 "TARGET_MULHW"
1034 "machhw %0, %1, %2"
1035 [(set_attr "type" "imul3")])
1036
1037(define_insn "*machhwuc"
1038 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1039 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1040 (match_operand:SI 1 "gpc_reg_operand" "%r")
1041 (const_int 16))
1042 (lshiftrt:SI
1043 (match_operand:SI 2 "gpc_reg_operand" "r")
1044 (const_int 16)))
1045 (match_operand:SI 4 "gpc_reg_operand" "0"))
1046 (const_int 0)))
1047 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1048 (plus:SI (mult:SI (lshiftrt:SI
1049 (match_dup 1)
1050 (const_int 16))
1051 (lshiftrt:SI
1052 (match_dup 2)
1053 (const_int 16)))
1054 (match_dup 4)))]
1055 "TARGET_MULHW"
1056 "machhwu. %0, %1, %2"
1057 [(set_attr "type" "imul3")])
1058
1059(define_insn "*machhwu"
1060 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1061 (plus:SI (mult:SI (lshiftrt:SI
1062 (match_operand:SI 1 "gpc_reg_operand" "%r")
1063 (const_int 16))
1064 (lshiftrt:SI
1065 (match_operand:SI 2 "gpc_reg_operand" "r")
1066 (const_int 16)))
1067 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1068 "TARGET_MULHW"
1069 "machhwu %0, %1, %2"
1070 [(set_attr "type" "imul3")])
1071
1072(define_insn "*maclhwc"
1073 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1074 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1075 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1076 (sign_extend:SI
1077 (match_operand:HI 2 "gpc_reg_operand" "r")))
1078 (match_operand:SI 4 "gpc_reg_operand" "0"))
1079 (const_int 0)))
1080 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1081 (plus:SI (mult:SI (sign_extend:SI
1082 (match_dup 1))
1083 (sign_extend:SI
1084 (match_dup 2)))
1085 (match_dup 4)))]
1086 "TARGET_MULHW"
1087 "maclhw. %0, %1, %2"
1088 [(set_attr "type" "imul3")])
1089
1090(define_insn "*maclhw"
1091 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1092 (plus:SI (mult:SI (sign_extend:SI
1093 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1094 (sign_extend:SI
1095 (match_operand:HI 2 "gpc_reg_operand" "r")))
1096 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1097 "TARGET_MULHW"
1098 "maclhw %0, %1, %2"
1099 [(set_attr "type" "imul3")])
1100
1101(define_insn "*maclhwuc"
1102 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1103 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1104 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1105 (zero_extend:SI
1106 (match_operand:HI 2 "gpc_reg_operand" "r")))
1107 (match_operand:SI 4 "gpc_reg_operand" "0"))
1108 (const_int 0)))
1109 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1110 (plus:SI (mult:SI (zero_extend:SI
1111 (match_dup 1))
1112 (zero_extend:SI
1113 (match_dup 2)))
1114 (match_dup 4)))]
1115 "TARGET_MULHW"
1116 "maclhwu. %0, %1, %2"
1117 [(set_attr "type" "imul3")])
1118
1119(define_insn "*maclhwu"
1120 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1121 (plus:SI (mult:SI (zero_extend:SI
1122 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1123 (zero_extend:SI
1124 (match_operand:HI 2 "gpc_reg_operand" "r")))
1125 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1126 "TARGET_MULHW"
1127 "maclhwu %0, %1, %2"
1128 [(set_attr "type" "imul3")])
1129
1130(define_insn "*nmacchwc"
1131 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1132 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1133 (mult:SI (ashiftrt:SI
1134 (match_operand:SI 2 "gpc_reg_operand" "r")
1135 (const_int 16))
1136 (sign_extend:SI
1137 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1138 (const_int 0)))
1139 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1140 (minus:SI (match_dup 4)
1141 (mult:SI (ashiftrt:SI
1142 (match_dup 2)
1143 (const_int 16))
1144 (sign_extend:SI
1145 (match_dup 1)))))]
1146 "TARGET_MULHW"
1147 "nmacchw. %0, %1, %2"
1148 [(set_attr "type" "imul3")])
1149
1150(define_insn "*nmacchw"
1151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1152 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1153 (mult:SI (ashiftrt:SI
1154 (match_operand:SI 2 "gpc_reg_operand" "r")
1155 (const_int 16))
1156 (sign_extend:SI
1157 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1158 "TARGET_MULHW"
1159 "nmacchw %0, %1, %2"
1160 [(set_attr "type" "imul3")])
1161
1162(define_insn "*nmachhwc"
1163 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1164 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1165 (mult:SI (ashiftrt:SI
1166 (match_operand:SI 1 "gpc_reg_operand" "%r")
1167 (const_int 16))
1168 (ashiftrt:SI
1169 (match_operand:SI 2 "gpc_reg_operand" "r")
1170 (const_int 16))))
1171 (const_int 0)))
1172 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1173 (minus:SI (match_dup 4)
1174 (mult:SI (ashiftrt:SI
1175 (match_dup 1)
1176 (const_int 16))
1177 (ashiftrt:SI
1178 (match_dup 2)
1179 (const_int 16)))))]
1180 "TARGET_MULHW"
1181 "nmachhw. %0, %1, %2"
1182 [(set_attr "type" "imul3")])
1183
1184(define_insn "*nmachhw"
1185 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1186 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1187 (mult:SI (ashiftrt:SI
1188 (match_operand:SI 1 "gpc_reg_operand" "%r")
1189 (const_int 16))
1190 (ashiftrt:SI
1191 (match_operand:SI 2 "gpc_reg_operand" "r")
1192 (const_int 16)))))]
1193 "TARGET_MULHW"
1194 "nmachhw %0, %1, %2"
1195 [(set_attr "type" "imul3")])
1196
1197(define_insn "*nmaclhwc"
1198 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1199 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1200 (mult:SI (sign_extend:SI
1201 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1202 (sign_extend:SI
1203 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1204 (const_int 0)))
1205 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1206 (minus:SI (match_dup 4)
1207 (mult:SI (sign_extend:SI
1208 (match_dup 1))
1209 (sign_extend:SI
1210 (match_dup 2)))))]
1211 "TARGET_MULHW"
1212 "nmaclhw. %0, %1, %2"
1213 [(set_attr "type" "imul3")])
1214
1215(define_insn "*nmaclhw"
1216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1217 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1218 (mult:SI (sign_extend:SI
1219 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1220 (sign_extend:SI
1221 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1222 "TARGET_MULHW"
1223 "nmaclhw %0, %1, %2"
1224 [(set_attr "type" "imul3")])
1225
1226(define_insn "*mulchwc"
1227 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1228 (compare:CC (mult:SI (ashiftrt:SI
1229 (match_operand:SI 2 "gpc_reg_operand" "r")
1230 (const_int 16))
1231 (sign_extend:SI
1232 (match_operand:HI 1 "gpc_reg_operand" "r")))
1233 (const_int 0)))
1234 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1235 (mult:SI (ashiftrt:SI
1236 (match_dup 2)
1237 (const_int 16))
1238 (sign_extend:SI
1239 (match_dup 1))))]
1240 "TARGET_MULHW"
1241 "mulchw. %0, %1, %2"
1242 [(set_attr "type" "imul3")])
1243
1244(define_insn "*mulchw"
1245 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1246 (mult:SI (ashiftrt:SI
1247 (match_operand:SI 2 "gpc_reg_operand" "r")
1248 (const_int 16))
1249 (sign_extend:SI
1250 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1251 "TARGET_MULHW"
1252 "mulchw %0, %1, %2"
1253 [(set_attr "type" "imul3")])
1254
1255(define_insn "*mulchwuc"
1256 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1257 (compare:CC (mult:SI (lshiftrt:SI
1258 (match_operand:SI 2 "gpc_reg_operand" "r")
1259 (const_int 16))
1260 (zero_extend:SI
1261 (match_operand:HI 1 "gpc_reg_operand" "r")))
1262 (const_int 0)))
1263 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1264 (mult:SI (lshiftrt:SI
1265 (match_dup 2)
1266 (const_int 16))
1267 (zero_extend:SI
1268 (match_dup 1))))]
1269 "TARGET_MULHW"
1270 "mulchwu. %0, %1, %2"
1271 [(set_attr "type" "imul3")])
1272
1273(define_insn "*mulchwu"
1274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 (mult:SI (lshiftrt:SI
1276 (match_operand:SI 2 "gpc_reg_operand" "r")
1277 (const_int 16))
1278 (zero_extend:SI
1279 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1280 "TARGET_MULHW"
1281 "mulchwu %0, %1, %2"
1282 [(set_attr "type" "imul3")])
1283
1284(define_insn "*mulhhwc"
1285 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1286 (compare:CC (mult:SI (ashiftrt:SI
1287 (match_operand:SI 1 "gpc_reg_operand" "%r")
1288 (const_int 16))
1289 (ashiftrt:SI
1290 (match_operand:SI 2 "gpc_reg_operand" "r")
1291 (const_int 16)))
1292 (const_int 0)))
1293 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1294 (mult:SI (ashiftrt:SI
1295 (match_dup 1)
1296 (const_int 16))
1297 (ashiftrt:SI
1298 (match_dup 2)
1299 (const_int 16))))]
1300 "TARGET_MULHW"
1301 "mulhhw. %0, %1, %2"
1302 [(set_attr "type" "imul3")])
1303
1304(define_insn "*mulhhw"
1305 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1306 (mult:SI (ashiftrt:SI
1307 (match_operand:SI 1 "gpc_reg_operand" "%r")
1308 (const_int 16))
1309 (ashiftrt:SI
1310 (match_operand:SI 2 "gpc_reg_operand" "r")
1311 (const_int 16))))]
1312 "TARGET_MULHW"
1313 "mulhhw %0, %1, %2"
1314 [(set_attr "type" "imul3")])
1315
1316(define_insn "*mulhhwuc"
1317 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1318 (compare:CC (mult:SI (lshiftrt:SI
1319 (match_operand:SI 1 "gpc_reg_operand" "%r")
1320 (const_int 16))
1321 (lshiftrt:SI
1322 (match_operand:SI 2 "gpc_reg_operand" "r")
1323 (const_int 16)))
1324 (const_int 0)))
1325 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1326 (mult:SI (lshiftrt:SI
1327 (match_dup 1)
1328 (const_int 16))
1329 (lshiftrt:SI
1330 (match_dup 2)
1331 (const_int 16))))]
1332 "TARGET_MULHW"
1333 "mulhhwu. %0, %1, %2"
1334 [(set_attr "type" "imul3")])
1335
1336(define_insn "*mulhhwu"
1337 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1338 (mult:SI (lshiftrt:SI
1339 (match_operand:SI 1 "gpc_reg_operand" "%r")
1340 (const_int 16))
1341 (lshiftrt:SI
1342 (match_operand:SI 2 "gpc_reg_operand" "r")
1343 (const_int 16))))]
1344 "TARGET_MULHW"
1345 "mulhhwu %0, %1, %2"
1346 [(set_attr "type" "imul3")])
1347
1348(define_insn "*mullhwc"
1349 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1350 (compare:CC (mult:SI (sign_extend:SI
1351 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1352 (sign_extend:SI
1353 (match_operand:HI 2 "gpc_reg_operand" "r")))
1354 (const_int 0)))
1355 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 (mult:SI (sign_extend:SI
1357 (match_dup 1))
1358 (sign_extend:SI
1359 (match_dup 2))))]
1360 "TARGET_MULHW"
1361 "mullhw. %0, %1, %2"
1362 [(set_attr "type" "imul3")])
1363
1364(define_insn "*mullhw"
1365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1366 (mult:SI (sign_extend:SI
1367 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1368 (sign_extend:SI
1369 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1370 "TARGET_MULHW"
1371 "mullhw %0, %1, %2"
1372 [(set_attr "type" "imul3")])
1373
1374(define_insn "*mullhwuc"
1375 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1376 (compare:CC (mult:SI (zero_extend:SI
1377 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1378 (zero_extend:SI
1379 (match_operand:HI 2 "gpc_reg_operand" "r")))
1380 (const_int 0)))
1381 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1382 (mult:SI (zero_extend:SI
1383 (match_dup 1))
1384 (zero_extend:SI
1385 (match_dup 2))))]
1386 "TARGET_MULHW"
1387 "mullhwu. %0, %1, %2"
1388 [(set_attr "type" "imul3")])
1389
1390(define_insn "*mullhwu"
1391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1392 (mult:SI (zero_extend:SI
1393 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1394 (zero_extend:SI
1395 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1396 "TARGET_MULHW"
1397 "mullhwu %0, %1, %2"
1398 [(set_attr "type" "imul3")])
1399\f
716019c0
JM		 1400;; IBM 405 and 440 string-search dlmzb instruction support.
1401(define_insn "dlmzb"
1402 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1403 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1404 (match_operand:SI 2 "gpc_reg_operand" "r")]
1405 UNSPEC_DLMZB_CR))
1406 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1407 (unspec:SI [(match_dup 1)
1408 (match_dup 2)]
1409 UNSPEC_DLMZB))]
1410 "TARGET_DLMZB"
1411 "dlmzb. %0, %1, %2")
1412
1413(define_expand "strlensi"
1414 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1415 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1416 (match_operand:QI 2 "const_int_operand" "")
1417 (match_operand 3 "const_int_operand" "")]
1418 UNSPEC_DLMZB_STRLEN))
1419 (clobber (match_scratch:CC 4 "=x"))]
1420 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1421{
1422 rtx result = operands[0];
1423 rtx src = operands[1];
1424 rtx search_char = operands[2];
1425 rtx align = operands[3];
1426 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1427 rtx loop_label, end_label, mem, cr0, cond;
1428 if (search_char != const0_rtx
1429 || GET_CODE (align) != CONST_INT
1430 || INTVAL (align) < 8)
1431 FAIL;
1432 word1 = gen_reg_rtx (SImode);
1433 word2 = gen_reg_rtx (SImode);
1434 scratch_dlmzb = gen_reg_rtx (SImode);
1435 scratch_string = gen_reg_rtx (Pmode);
1436 loop_label = gen_label_rtx ();
1437 end_label = gen_label_rtx ();
1438 addr = force_reg (Pmode, XEXP (src, 0));
1439 emit_move_insn (scratch_string, addr);
1440 emit_label (loop_label);
1441 mem = change_address (src, SImode, scratch_string);
1442 emit_move_insn (word1, mem);
1443 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1444 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1445 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1446 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1447 emit_jump_insn (gen_rtx_SET (VOIDmode,
1448 pc_rtx,
1449 gen_rtx_IF_THEN_ELSE (VOIDmode,
1450 cond,
1451 gen_rtx_LABEL_REF
1452 (VOIDmode,
1453 end_label),
1454 pc_rtx)));
1455 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1456 emit_jump_insn (gen_rtx_SET (VOIDmode,
1457 pc_rtx,
1458 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
ea5bd0d8 1459 emit_barrier ();
716019c0
JM		 1460 emit_label (end_label);
1461 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1462 emit_insn (gen_subsi3 (result, scratch_string, addr));
1463 emit_insn (gen_subsi3 (result, result, const1_rtx));
1464 DONE;
1465})
1466\f
9ebbca7d
GK		 1467(define_split
1468 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1469 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1470 (const_int 0)))
1471 (set (match_operand:SI 0 "gpc_reg_operand" "")
1472 (sign_extend:SI (match_dup 1)))]
1473 "reload_completed"
1474 [(set (match_dup 0)
1475 (sign_extend:SI (match_dup 1)))
1476 (set (match_dup 2)
1477 (compare:CC (match_dup 0)
1478 (const_int 0)))]
1479 "")
1480
1fd4e8c1 1481;; Fixed-point arithmetic insns.
deb9225a 1482
0354e5d8
GK		 1483(define_expand "add<mode>3"
1484 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1485 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
4ae234b0 1486 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
7cd5235b 1487 ""
7cd5235b 1488{
0354e5d8
GK		 1489 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1490 {
1491 if (non_short_cint_operand (operands[2], DImode))
1492 FAIL;
1493 }
1494 else if (GET_CODE (operands[2]) == CONST_INT
1495 && ! add_operand (operands[2], <MODE>mode))
7cd5235b 1496 {
b3a13419
ILT		 1497 rtx tmp = ((!can_create_pseudo_p ()
1498 || rtx_equal_p (operands[0], operands[1]))
0354e5d8 1499 ? operands[0] : gen_reg_rtx (<MODE>mode));
7cd5235b 1500
2bfcf297 1501 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1502 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8
GK		 1503 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1504
279bb624 1505 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1506 FAIL;
7cd5235b 1507
9ebbca7d
GK		 1508 /* The ordering here is important for the prolog expander.
1509 When space is allocated from the stack, adding 'low' first may
1510 produce a temporary deallocation (which would be bad). */
0354e5d8
GK		 1511 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1512 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
7cd5235b
MM		 1513 DONE;
1514 }
279bb624 1515})
7cd5235b 1516
0354e5d8
GK		 1517;; Discourage ai/addic because of carry but provide it in an alternative
1518;; allowing register zero as source.
1519(define_insn "*add<mode>3_internal1"
1520 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1521 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1522 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
7393f7f8 1523 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1fd4e8c1 1524 "@
deb9225a
RK		 1525 {cax|add} %0,%1,%2
1526 {cal %0,%2(%1)|addi %0,%1,%2}
1527 {ai|addic} %0,%1,%2
7cd5235b
MM		 1528 {cau|addis} %0,%1,%v2"
1529 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 1530
ee890fe2
SS		 1531(define_insn "addsi3_high"
1532 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1533 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1534 (high:SI (match_operand 2 "" ""))))]
1535 "TARGET_MACHO && !TARGET_64BIT"
1536 "{cau|addis} %0,%1,ha16(%2)"
1537 [(set_attr "length" "4")])
1538
0354e5d8 1539(define_insn "*add<mode>3_internal2"
cb8cc086 1540 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1541 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1542 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1543 (const_int 0)))
0354e5d8
GK		 1544 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1545 ""
deb9225a
RK		 1546 "@
1547 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1548 {ai.|addic.} %3,%1,%2
1549 #
1550 #"
a62bfff2 1551 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1552 (set_attr "length" "4,4,8,8")])
1553
1554(define_split
1555 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1556 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1557 (match_operand:GPR 2 "reg_or_short_operand" ""))
cb8cc086 1558 (const_int 0)))
0354e5d8
GK		 1559 (clobber (match_scratch:GPR 3 ""))]
1560 "reload_completed"
cb8cc086 1561 [(set (match_dup 3)
0354e5d8 1562 (plus:GPR (match_dup 1)
cb8cc086
MM		 1563 (match_dup 2)))
1564 (set (match_dup 0)
1565 (compare:CC (match_dup 3)
1566 (const_int 0)))]
1567 "")
7e69e155 1568
0354e5d8 1569(define_insn "*add<mode>3_internal3"
cb8cc086 1570 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1571 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1572 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1573 (const_int 0)))
0354e5d8
GK		 1574 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1575 (plus:P (match_dup 1)
1576 (match_dup 2)))]
1577 ""
deb9225a
RK		 1578 "@
1579 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1580 {ai.|addic.} %0,%1,%2
1581 #
1582 #"
a62bfff2 1583 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1584 (set_attr "length" "4,4,8,8")])
1585
1586(define_split
1587 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1588 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1589 (match_operand:P 2 "reg_or_short_operand" ""))
cb8cc086 1590 (const_int 0)))
0354e5d8
GK		 1591 (set (match_operand:P 0 "gpc_reg_operand" "")
1592 (plus:P (match_dup 1) (match_dup 2)))]
1593 "reload_completed"
cb8cc086 1594 [(set (match_dup 0)
0354e5d8
GK		 1595 (plus:P (match_dup 1)
1596 (match_dup 2)))
cb8cc086
MM		 1597 (set (match_dup 3)
1598 (compare:CC (match_dup 0)
1599 (const_int 0)))]
1600 "")
7e69e155 1601
f357808b
RK		 1602;; Split an add that we can't do in one insn into two insns, each of which
1603;; does one 16-bit part. This is used by combine. Note that the low-order
1604;; add should be last in case the result gets used in an address.
1605
1606(define_split
0354e5d8
GK		 1607 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1608 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1609 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1fd4e8c1 1610 ""
0354e5d8
GK		 1611 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1612 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1fd4e8c1 1613{
2bfcf297 1614 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1615 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8 1616 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1fd4e8c1 1617
e6ca2c17 1618 operands[4] = GEN_INT (low);
279bb624 1619 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1620 operands[3] = GEN_INT (rest);
b3a13419 1621 else if (can_create_pseudo_p ())
0354e5d8
GK		 1622 {
1623 operands[3] = gen_reg_rtx (DImode);
1624 emit_move_insn (operands[3], operands[2]);
1625 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1626 DONE;
1627 }
1628 else
1629 FAIL;
279bb624 1630})
1fd4e8c1 1631
0354e5d8
GK		 1632(define_insn "one_cmpl<mode>2"
1633 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1634 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1635 ""
ca7f5001
RK		 1636 "nor %0,%1,%1")
1637
1638(define_insn ""
52d3af72 1639 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 1640 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
ca7f5001 1641 (const_int 0)))
0354e5d8
GK		 1642 (clobber (match_scratch:P 2 "=r,r"))]
1643 ""
52d3af72
DE		 1644 "@
1645 nor. %2,%1,%1
1646 #"
1647 [(set_attr "type" "compare")
1648 (set_attr "length" "4,8")])
1649
1650(define_split
1651 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 1652 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1653 (const_int 0)))
0354e5d8
GK		 1654 (clobber (match_scratch:P 2 ""))]
1655 "reload_completed"
52d3af72 1656 [(set (match_dup 2)
0354e5d8 1657 (not:P (match_dup 1)))
52d3af72
DE		 1658 (set (match_dup 0)
1659 (compare:CC (match_dup 2)
1660 (const_int 0)))]
1661 "")
ca7f5001
RK		 1662
1663(define_insn ""
52d3af72 1664 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 1665 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 1666 (const_int 0)))
0354e5d8
GK		 1667 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1668 (not:P (match_dup 1)))]
1669 ""
52d3af72
DE		 1670 "@
1671 nor. %0,%1,%1
1672 #"
1673 [(set_attr "type" "compare")
1674 (set_attr "length" "4,8")])
1675
1676(define_split
1677 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 1678 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1679 (const_int 0)))
0354e5d8
GK		 1680 (set (match_operand:P 0 "gpc_reg_operand" "")
1681 (not:P (match_dup 1)))]
1682 "reload_completed"
52d3af72 1683 [(set (match_dup 0)
0354e5d8 1684 (not:P (match_dup 1)))
52d3af72
DE		 1685 (set (match_dup 2)
1686 (compare:CC (match_dup 0)
1687 (const_int 0)))]
1688 "")
1fd4e8c1
RK		 1689
1690(define_insn ""
3d91674b
RK		 1691 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1692 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1693 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1694 "! TARGET_POWERPC"
ca7f5001 1695 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1696
deb9225a 1697(define_insn ""
0354e5d8
GK		 1698 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1699 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1700 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
deb9225a
RK		 1701 "TARGET_POWERPC"
1702 "@
1703 subf %0,%2,%1
1704 subfic %0,%2,%1")
1705
1fd4e8c1 1706(define_insn ""
cb8cc086
MM		 1707 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1708 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1709 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1710 (const_int 0)))
cb8cc086 1711 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1712 "! TARGET_POWERPC"
cb8cc086
MM		 1713 "@
1714 {sf.|subfc.} %3,%2,%1
1715 #"
1716 [(set_attr "type" "compare")
1717 (set_attr "length" "4,8")])
1fd4e8c1 1718
deb9225a 1719(define_insn ""
cb8cc086 1720 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1721 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1722 (match_operand:P 2 "gpc_reg_operand" "r,r"))
deb9225a 1723 (const_int 0)))
0354e5d8
GK		 1724 (clobber (match_scratch:P 3 "=r,r"))]
1725 "TARGET_POWERPC"
cb8cc086
MM		 1726 "@
1727 subf. %3,%2,%1
1728 #"
a62bfff2 1729 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1730 (set_attr "length" "4,8")])
1731
1732(define_split
1733 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1734 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1735 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1736 (const_int 0)))
0354e5d8
GK		 1737 (clobber (match_scratch:P 3 ""))]
1738 "reload_completed"
cb8cc086 1739 [(set (match_dup 3)
0354e5d8 1740 (minus:P (match_dup 1)
cb8cc086
MM		 1741 (match_dup 2)))
1742 (set (match_dup 0)
1743 (compare:CC (match_dup 3)
1744 (const_int 0)))]
1745 "")
deb9225a 1746
1fd4e8c1 1747(define_insn ""
cb8cc086
MM		 1748 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1749 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1750 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1751 (const_int 0)))
cb8cc086 1752 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1753 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1754 "! TARGET_POWERPC"
cb8cc086
MM		 1755 "@
1756 {sf.|subfc.} %0,%2,%1
1757 #"
1758 [(set_attr "type" "compare")
1759 (set_attr "length" "4,8")])
815cdc52 1760
29ae5b89 1761(define_insn ""
cb8cc086 1762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1763 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1764 (match_operand:P 2 "gpc_reg_operand" "r,r"))
815cdc52 1765 (const_int 0)))
0354e5d8
GK		 1766 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1767 (minus:P (match_dup 1)
cb8cc086 1768 (match_dup 2)))]
0354e5d8 1769 "TARGET_POWERPC"
90612787
DE		 1770 "@
1771 subf. %0,%2,%1
1772 #"
a62bfff2 1773 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1774 (set_attr "length" "4,8")])
1775
1776(define_split
1777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1778 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1779 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1780 (const_int 0)))
0354e5d8
GK		 1781 (set (match_operand:P 0 "gpc_reg_operand" "")
1782 (minus:P (match_dup 1)
cb8cc086 1783 (match_dup 2)))]
0354e5d8 1784 "reload_completed"
cb8cc086 1785 [(set (match_dup 0)
0354e5d8 1786 (minus:P (match_dup 1)
cb8cc086
MM		 1787 (match_dup 2)))
1788 (set (match_dup 3)
1789 (compare:CC (match_dup 0)
1790 (const_int 0)))]
1791 "")
deb9225a 1792
0354e5d8
GK		 1793(define_expand "sub<mode>3"
1794 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1795 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
4ae234b0 1796 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1fd4e8c1 1797 ""
a0044fb1
RK		 1798 "
1799{
1800 if (GET_CODE (operands[2]) == CONST_INT)
1801 {
0354e5d8
GK		 1802 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1803 negate_rtx (<MODE>mode, operands[2])));
a0044fb1
RK		 1804 DONE;
1805 }
1806}")
1fd4e8c1
RK		 1807
1808;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1809;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1810;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1811;; combine.
1fd4e8c1
RK		 1812
1813(define_expand "sminsi3"
1814 [(set (match_dup 3)
cd2b37d9 1815 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1816 (match_operand:SI 2 "reg_or_short_operand" ""))
1817 (const_int 0)
1818 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1819 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1820 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1821 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1822 "
a3170dc6
AH		 1823{
1824 if (TARGET_ISEL)
1825 {
1826 operands[2] = force_reg (SImode, operands[2]);
1827 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1828 DONE;
1829 }
1830
1831 operands[3] = gen_reg_rtx (SImode);
1832}")
1fd4e8c1 1833
95ac8e67
RK		 1834(define_split
1835 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1836 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1837 (match_operand:SI 2 "reg_or_short_operand" "")))
1838 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1839 "TARGET_POWER"
95ac8e67
RK		 1840 [(set (match_dup 3)
1841 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1842 (const_int 0)
1843 (minus:SI (match_dup 2) (match_dup 1))))
1844 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1845 "")
1846
1fd4e8c1
RK		 1847(define_expand "smaxsi3"
1848 [(set (match_dup 3)
cd2b37d9 1849 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1850 (match_operand:SI 2 "reg_or_short_operand" ""))
1851 (const_int 0)
1852 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1853 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1854 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1855 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1856 "
a3170dc6
AH		 1857{
1858 if (TARGET_ISEL)
1859 {
1860 operands[2] = force_reg (SImode, operands[2]);
1861 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1862 DONE;
1863 }
1864 operands[3] = gen_reg_rtx (SImode);
1865}")
1fd4e8c1 1866
95ac8e67
RK		 1867(define_split
1868 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1869 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1870 (match_operand:SI 2 "reg_or_short_operand" "")))
1871 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1872 "TARGET_POWER"
95ac8e67
RK		 1873 [(set (match_dup 3)
1874 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1875 (const_int 0)
1876 (minus:SI (match_dup 2) (match_dup 1))))
1877 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1878 "")
1879
1fd4e8c1 1880(define_expand "uminsi3"
cd2b37d9 1881 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1882 (match_dup 5)))
cd2b37d9 1883 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1884 (match_dup 5)))
1fd4e8c1
RK		 1885 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1886 (const_int 0)
1887 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1888 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1889 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1890 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1891 "
bb68ff55 1892{
a3170dc6
AH		 1893 if (TARGET_ISEL)
1894 {
1895 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1896 DONE;
1897 }
bb68ff55
MM		 1898 operands[3] = gen_reg_rtx (SImode);
1899 operands[4] = gen_reg_rtx (SImode);
1900 operands[5] = GEN_INT (-2147483647 - 1);
1901}")
1fd4e8c1
RK		 1902
1903(define_expand "umaxsi3"
cd2b37d9 1904 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1905 (match_dup 5)))
cd2b37d9 1906 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1907 (match_dup 5)))
1fd4e8c1
RK		 1908 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1909 (const_int 0)
1910 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1911 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1912 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1913 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1914 "
bb68ff55 1915{
a3170dc6
AH		 1916 if (TARGET_ISEL)
1917 {
1918 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1919 DONE;
1920 }
bb68ff55
MM		 1921 operands[3] = gen_reg_rtx (SImode);
1922 operands[4] = gen_reg_rtx (SImode);
1923 operands[5] = GEN_INT (-2147483647 - 1);
1924}")
1fd4e8c1
RK		 1925
1926(define_insn ""
cd2b37d9
RK		 1927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1928 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1929 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1930 (const_int 0)
1931 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1932 "TARGET_POWER"
1fd4e8c1
RK		 1933 "doz%I2 %0,%1,%2")
1934
1935(define_insn ""
9ebbca7d 1936 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1937 (compare:CC
9ebbca7d
GK		 1938 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1939 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1940 (const_int 0)
1941 (minus:SI (match_dup 2) (match_dup 1)))
1942 (const_int 0)))
9ebbca7d 1943 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1944 "TARGET_POWER"
9ebbca7d
GK		 1945 "@
1946 doz%I2. %3,%1,%2
1947 #"
1948 [(set_attr "type" "delayed_compare")
1949 (set_attr "length" "4,8")])
1950
1951(define_split
1952 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1953 (compare:CC
1954 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1955 (match_operand:SI 2 "reg_or_short_operand" ""))
1956 (const_int 0)
1957 (minus:SI (match_dup 2) (match_dup 1)))
1958 (const_int 0)))
1959 (clobber (match_scratch:SI 3 ""))]
1960 "TARGET_POWER && reload_completed"
1961 [(set (match_dup 3)
1962 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1963 (const_int 0)
1964 (minus:SI (match_dup 2) (match_dup 1))))
1965 (set (match_dup 0)
1966 (compare:CC (match_dup 3)
1967 (const_int 0)))]
1968 "")
1fd4e8c1
RK		 1969
1970(define_insn ""
9ebbca7d 1971 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1972 (compare:CC
9ebbca7d
GK		 1973 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1974 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1975 (const_int 0)
1976 (minus:SI (match_dup 2) (match_dup 1)))
1977 (const_int 0)))
9ebbca7d 1978 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1979 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1980 (const_int 0)
1981 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1982 "TARGET_POWER"
9ebbca7d
GK		 1983 "@
1984 doz%I2. %0,%1,%2
1985 #"
1986 [(set_attr "type" "delayed_compare")
1987 (set_attr "length" "4,8")])
1988
1989(define_split
1990 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1991 (compare:CC
1992 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1993 (match_operand:SI 2 "reg_or_short_operand" ""))
1994 (const_int 0)
1995 (minus:SI (match_dup 2) (match_dup 1)))
1996 (const_int 0)))
1997 (set (match_operand:SI 0 "gpc_reg_operand" "")
1998 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1999 (const_int 0)
2000 (minus:SI (match_dup 2) (match_dup 1))))]
2001 "TARGET_POWER && reload_completed"
2002 [(set (match_dup 0)
2003 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2004 (const_int 0)
2005 (minus:SI (match_dup 2) (match_dup 1))))
2006 (set (match_dup 3)
2007 (compare:CC (match_dup 0)
2008 (const_int 0)))]
2009 "")
1fd4e8c1
RK		 2010
2011;; We don't need abs with condition code because such comparisons should
2012;; never be done.
ea9be077
MM		 2013(define_expand "abssi2"
2014 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2015 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2016 ""
2017 "
2018{
a3170dc6
AH		 2019 if (TARGET_ISEL)
2020 {
2021 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2022 DONE;
2023 }
2024 else if (! TARGET_POWER)
ea9be077
MM		 2025 {
2026 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2027 DONE;
2028 }
2029}")
2030
ea112fc4 2031(define_insn "*abssi2_power"
cd2b37d9
RK		 2032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2033 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 2034 "TARGET_POWER"
1fd4e8c1
RK		 2035 "abs %0,%1")
2036
a3170dc6
AH		 2037(define_insn_and_split "abssi2_isel"
2038 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2039 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 2040 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 2041 (clobber (match_scratch:CC 3 "=y"))]
2042 "TARGET_ISEL"
2043 "#"
2044 "&& reload_completed"
2045 [(set (match_dup 2) (neg:SI (match_dup 1)))
2046 (set (match_dup 3)
2047 (compare:CC (match_dup 1)
2048 (const_int 0)))
2049 (set (match_dup 0)
2050 (if_then_else:SI (ge (match_dup 3)
2051 (const_int 0))
2052 (match_dup 1)
2053 (match_dup 2)))]
2054 "")
2055
ea112fc4 2056(define_insn_and_split "abssi2_nopower"
ea9be077 2057 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2058 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 2059 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 2060 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 2061 "#"
2062 "&& reload_completed"
ea9be077
MM		 2063 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2064 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2065 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 2066 "")
2067
463b558b 2068(define_insn "*nabs_power"
cd2b37d9
RK		 2069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2070 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 2071 "TARGET_POWER"
1fd4e8c1
RK		 2072 "nabs %0,%1")
2073
ea112fc4 2074(define_insn_and_split "*nabs_nopower"
ea9be077 2075 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2076 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 2077 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 2078 "! TARGET_POWER"
ea112fc4
DE		 2079 "#"
2080 "&& reload_completed"
ea9be077
MM		 2081 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2082 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2083 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 2084 "")
2085
0354e5d8
GK		 2086(define_expand "neg<mode>2"
2087 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2088 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2089 ""
2090 "")
2091
2092(define_insn "*neg<mode>2_internal"
2093 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2094 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 2095 ""
2096 "neg %0,%1")
2097
2098(define_insn ""
9ebbca7d 2099 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 2100 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 2101 (const_int 0)))
0354e5d8
GK		 2102 (clobber (match_scratch:P 2 "=r,r"))]
2103 ""
9ebbca7d
GK		 2104 "@
2105 neg. %2,%1
2106 #"
a62bfff2 2107 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2108 (set_attr "length" "4,8")])
2109
2110(define_split
2111 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 2112 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2113 (const_int 0)))
0354e5d8
GK		 2114 (clobber (match_scratch:P 2 ""))]
2115 "reload_completed"
9ebbca7d 2116 [(set (match_dup 2)
0354e5d8 2117 (neg:P (match_dup 1)))
9ebbca7d
GK		 2118 (set (match_dup 0)
2119 (compare:CC (match_dup 2)
2120 (const_int 0)))]
2121 "")
1fd4e8c1
RK		 2122
2123(define_insn ""
9ebbca7d 2124 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 2125 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 2126 (const_int 0)))
0354e5d8
GK		 2127 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2128 (neg:P (match_dup 1)))]
2129 ""
9ebbca7d
GK		 2130 "@
2131 neg. %0,%1
2132 #"
a62bfff2 2133 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2134 (set_attr "length" "4,8")])
2135
2136(define_split
2137 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 2138 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2139 (const_int 0)))
0354e5d8
GK		 2140 (set (match_operand:P 0 "gpc_reg_operand" "")
2141 (neg:P (match_dup 1)))]
66859ace 2142 "reload_completed"
9ebbca7d 2143 [(set (match_dup 0)
0354e5d8 2144 (neg:P (match_dup 1)))
9ebbca7d
GK		 2145 (set (match_dup 2)
2146 (compare:CC (match_dup 0)
2147 (const_int 0)))]
2148 "")
1fd4e8c1 2149
0354e5d8
GK		 2150(define_insn "clz<mode>2"
2151 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2152 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1b1edcfa 2153 ""
44cd321e
PS		 2154 "{cntlz|cntlz<wd>} %0,%1"
2155 [(set_attr "type" "cntlz")])
1b1edcfa 2156
0354e5d8 2157(define_expand "ctz<mode>2"
4977bab6 2158 [(set (match_dup 2)
e42ac3de 2159 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2160 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2161 (match_dup 2)))
1b1edcfa 2162 (clobber (scratch:CC))])
0354e5d8 2163 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2164 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2165 (minus:GPR (match_dup 5) (match_dup 4)))]
1fd4e8c1 2166 ""
4977bab6 2167 {
0354e5d8
GK		 2168 operands[2] = gen_reg_rtx (<MODE>mode);
2169 operands[3] = gen_reg_rtx (<MODE>mode);
2170 operands[4] = gen_reg_rtx (<MODE>mode);
2171 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
4977bab6 2172 })
6ae08853 2173
0354e5d8 2174(define_expand "ffs<mode>2"
1b1edcfa 2175 [(set (match_dup 2)
e42ac3de 2176 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2177 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2178 (match_dup 2)))
1b1edcfa 2179 (clobber (scratch:CC))])
0354e5d8 2180 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2181 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2182 (minus:GPR (match_dup 5) (match_dup 4)))]
4977bab6 2183 ""
1b1edcfa 2184 {
0354e5d8
GK		 2185 operands[2] = gen_reg_rtx (<MODE>mode);
2186 operands[3] = gen_reg_rtx (<MODE>mode);
2187 operands[4] = gen_reg_rtx (<MODE>mode);
2188 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1b1edcfa 2189 })
6ae08853 2190
432218ba
DE		 2191(define_insn "popcntb<mode>2"
2192 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2193 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2194 UNSPEC_POPCNTB))]
2195 "TARGET_POPCNTB"
2196 "popcntb %0,%1")
2197
565ef4ba 2198(define_expand "popcount<mode>2"
e42ac3de
RS		 2199 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2200 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2201 "TARGET_POPCNTB"
2202 {
2203 rs6000_emit_popcount (operands[0], operands[1]);
2204 DONE;
2205 })
2206
2207(define_expand "parity<mode>2"
e42ac3de
RS		 2208 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2209 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2210 "TARGET_POPCNTB"
2211 {
2212 rs6000_emit_parity (operands[0], operands[1]);
2213 DONE;
2214 })
2215
03f79051
DE		 2216(define_insn "bswapsi2"
2217 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2218 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2219 ""
2220 "@
2221 {lbrx|lwbrx} %0,%y1
2222 {stbrx|stwbrx} %1,%y0
2223 #"
2224 [(set_attr "length" "4,4,12")])
2225
2226(define_split
2227 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2228 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2229 "reload_completed"
2230 [(set (match_dup 0)
2231 (rotate:SI (match_dup 1) (const_int 8)))
2232 (set (zero_extract:SI (match_dup 0)
2233 (const_int 8)
2234 (const_int 0))
2235 (match_dup 1))
2236 (set (zero_extract:SI (match_dup 0)
2237 (const_int 8)
2238 (const_int 16))
2239 (rotate:SI (match_dup 1)
2240 (const_int 16)))]
2241 "")
2242
ca7f5001
RK		 2243(define_expand "mulsi3"
2244 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2245 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2246 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2247 ""
2248 "
2249{
2250 if (TARGET_POWER)
68b40e7e 2251 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 2252 else
68b40e7e 2253 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 2254 DONE;
2255}")
2256
68b40e7e 2257(define_insn "mulsi3_mq"
cd2b37d9
RK		 2258 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2259 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 2260 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2261 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 2262 "TARGET_POWER"
2263 "@
2264 {muls|mullw} %0,%1,%2
2265 {muli|mulli} %0,%1,%2"
6ae08853 2266 [(set (attr "type")
c859cda6
DJ		 2267 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2268 (const_string "imul3")
6ae08853 2269 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2270 (const_string "imul2")]
2271 (const_string "imul")))])
ca7f5001 2272
68b40e7e 2273(define_insn "mulsi3_no_mq"
ca7f5001
RK		 2274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2275 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2276 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 2277 "! TARGET_POWER"
1fd4e8c1 2278 "@
d904e9ed
RK		 2279 {muls|mullw} %0,%1,%2
2280 {muli|mulli} %0,%1,%2"
6ae08853 2281 [(set (attr "type")
c859cda6
DJ		 2282 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2283 (const_string "imul3")
6ae08853 2284 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2285 (const_string "imul2")]
2286 (const_string "imul")))])
1fd4e8c1 2287
9259f3b0 2288(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 2289 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2290 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2291 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2292 (const_int 0)))
9ebbca7d
GK		 2293 (clobber (match_scratch:SI 3 "=r,r"))
2294 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2295 "TARGET_POWER"
9ebbca7d
GK		 2296 "@
2297 {muls.|mullw.} %3,%1,%2
2298 #"
9259f3b0 2299 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2300 (set_attr "length" "4,8")])
2301
2302(define_split
2303 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2304 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2305 (match_operand:SI 2 "gpc_reg_operand" ""))
2306 (const_int 0)))
2307 (clobber (match_scratch:SI 3 ""))
2308 (clobber (match_scratch:SI 4 ""))]
2309 "TARGET_POWER && reload_completed"
2310 [(parallel [(set (match_dup 3)
2311 (mult:SI (match_dup 1) (match_dup 2)))
2312 (clobber (match_dup 4))])
2313 (set (match_dup 0)
2314 (compare:CC (match_dup 3)
2315 (const_int 0)))]
2316 "")
ca7f5001 2317
9259f3b0 2318(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 2319 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2320 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2321 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2322 (const_int 0)))
9ebbca7d 2323 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 2324 "! TARGET_POWER"
9ebbca7d
GK		 2325 "@
2326 {muls.|mullw.} %3,%1,%2
2327 #"
9259f3b0 2328 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2329 (set_attr "length" "4,8")])
2330
2331(define_split
2332 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2333 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2334 (match_operand:SI 2 "gpc_reg_operand" ""))
2335 (const_int 0)))
2336 (clobber (match_scratch:SI 3 ""))]
2337 "! TARGET_POWER && reload_completed"
2338 [(set (match_dup 3)
2339 (mult:SI (match_dup 1) (match_dup 2)))
2340 (set (match_dup 0)
2341 (compare:CC (match_dup 3)
2342 (const_int 0)))]
2343 "")
1fd4e8c1 2344
9259f3b0 2345(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 2346 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2347 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2348 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2349 (const_int 0)))
9ebbca7d 2350 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 2351 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 2352 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2353 "TARGET_POWER"
9ebbca7d
GK		 2354 "@
2355 {muls.|mullw.} %0,%1,%2
2356 #"
9259f3b0 2357 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2358 (set_attr "length" "4,8")])
2359
2360(define_split
2361 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2362 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2363 (match_operand:SI 2 "gpc_reg_operand" ""))
2364 (const_int 0)))
2365 (set (match_operand:SI 0 "gpc_reg_operand" "")
2366 (mult:SI (match_dup 1) (match_dup 2)))
2367 (clobber (match_scratch:SI 4 ""))]
2368 "TARGET_POWER && reload_completed"
2369 [(parallel [(set (match_dup 0)
2370 (mult:SI (match_dup 1) (match_dup 2)))
2371 (clobber (match_dup 4))])
2372 (set (match_dup 3)
2373 (compare:CC (match_dup 0)
2374 (const_int 0)))]
2375 "")
ca7f5001 2376
9259f3b0 2377(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 2378 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2379 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2380 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2381 (const_int 0)))
9ebbca7d 2382 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 2383 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 2384 "! TARGET_POWER"
9ebbca7d
GK		 2385 "@
2386 {muls.|mullw.} %0,%1,%2
2387 #"
9259f3b0 2388 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2389 (set_attr "length" "4,8")])
2390
2391(define_split
2392 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2393 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2394 (match_operand:SI 2 "gpc_reg_operand" ""))
2395 (const_int 0)))
2396 (set (match_operand:SI 0 "gpc_reg_operand" "")
2397 (mult:SI (match_dup 1) (match_dup 2)))]
2398 "! TARGET_POWER && reload_completed"
2399 [(set (match_dup 0)
2400 (mult:SI (match_dup 1) (match_dup 2)))
2401 (set (match_dup 3)
2402 (compare:CC (match_dup 0)
2403 (const_int 0)))]
2404 "")
1fd4e8c1
RK		 2405
2406;; Operand 1 is divided by operand 2; quotient goes to operand
2407;; 0 and remainder to operand 3.
2408;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2409
8ffd9c51
RK		 2410(define_expand "divmodsi4"
2411 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2412 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2413 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 2414 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 2415 (mod:SI (match_dup 1) (match_dup 2)))])]
2416 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2417 "
2418{
2419 if (! TARGET_POWER && ! TARGET_POWERPC)
2420 {
39403d82
DE		 2421 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2422 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2423 emit_insn (gen_divss_call ());
39403d82
DE		 2424 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2425 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 2426 DONE;
2427 }
2428}")
deb9225a 2429
bb157ff4 2430(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 2431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2432 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2433 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 2434 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 2435 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 2436 "TARGET_POWER"
cfb557c4
RK		 2437 "divs %0,%1,%2"
2438 [(set_attr "type" "idiv")])
1fd4e8c1 2439
4ae234b0
GK		 2440(define_expand "udiv<mode>3"
2441 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2442 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2443 (match_operand:GPR 2 "gpc_reg_operand" "")))]
8ffd9c51
RK		 2444 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2445 "
2446{
2447 if (! TARGET_POWER && ! TARGET_POWERPC)
2448 {
39403d82
DE		 2449 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2450 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2451 emit_insn (gen_quous_call ());
39403d82 2452 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2453 DONE;
2454 }
f192bf8b
DE		 2455 else if (TARGET_POWER)
2456 {
2457 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2458 DONE;
2459 }
8ffd9c51 2460}")
deb9225a 2461
f192bf8b
DE		 2462(define_insn "udivsi3_mq"
2463 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2464 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2465 (match_operand:SI 2 "gpc_reg_operand" "r")))
2466 (clobber (match_scratch:SI 3 "=q"))]
2467 "TARGET_POWERPC && TARGET_POWER"
2468 "divwu %0,%1,%2"
2469 [(set_attr "type" "idiv")])
2470
2471(define_insn "*udivsi3_no_mq"
4ae234b0
GK		 2472 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2473 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2474 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2475 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2476 "div<wd>u %0,%1,%2"
44cd321e
PS		 2477 [(set (attr "type")
2478 (cond [(match_operand:SI 0 "" "")
2479 (const_string "idiv")]
2480 (const_string "ldiv")))])
2481
ca7f5001 2482
1fd4e8c1 2483;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 2484;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 2485;; used; for PowerPC, force operands into register and do a normal divide;
2486;; for AIX common-mode, use quoss call on register operands.
4ae234b0
GK		 2487(define_expand "div<mode>3"
2488 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2489 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2490 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1fd4e8c1
RK		 2491 ""
2492 "
2493{
ca7f5001 2494 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 2495 && INTVAL (operands[2]) > 0
ca7f5001
RK		 2496 && exact_log2 (INTVAL (operands[2])) >= 0)
2497 ;
b6c9286a 2498 else if (TARGET_POWERPC)
f192bf8b 2499 {
99e8e649 2500 operands[2] = force_reg (<MODE>mode, operands[2]);
f192bf8b
DE		 2501 if (TARGET_POWER)
2502 {
2503 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2504 DONE;
2505 }
2506 }
b6c9286a 2507 else if (TARGET_POWER)
1fd4e8c1 2508 FAIL;
405c5495 2509 else
8ffd9c51 2510 {
39403d82
DE		 2511 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2512 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2513 emit_insn (gen_quoss_call ());
39403d82 2514 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2515 DONE;
2516 }
1fd4e8c1
RK		 2517}")
2518
f192bf8b
DE		 2519(define_insn "divsi3_mq"
2520 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2521 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2522 (match_operand:SI 2 "gpc_reg_operand" "r")))
2523 (clobber (match_scratch:SI 3 "=q"))]
2524 "TARGET_POWERPC && TARGET_POWER"
2525 "divw %0,%1,%2"
2526 [(set_attr "type" "idiv")])
2527
4ae234b0
GK		 2528(define_insn "*div<mode>3_no_mq"
2529 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2530 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2531 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2532 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2533 "div<wd> %0,%1,%2"
44cd321e
PS		 2534 [(set (attr "type")
2535 (cond [(match_operand:SI 0 "" "")
2536 (const_string "idiv")]
2537 (const_string "ldiv")))])
f192bf8b 2538
4ae234b0
GK		 2539(define_expand "mod<mode>3"
2540 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2541 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2542 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
39b52ba2 2543 ""
1fd4e8c1
RK		 2544 "
2545{
481c7efa 2546 int i;
39b52ba2
RK		 2547 rtx temp1;
2548 rtx temp2;
2549
2bfcf297 2550 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 2551 || INTVAL (operands[2]) <= 0
2bfcf297 2552 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 2553 FAIL;
2554
4ae234b0
GK		 2555 temp1 = gen_reg_rtx (<MODE>mode);
2556 temp2 = gen_reg_rtx (<MODE>mode);
1fd4e8c1 2557
4ae234b0
GK		 2558 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2559 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2560 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
85644414 2561 DONE;
1fd4e8c1
RK		 2562}")
2563
2564(define_insn ""
4ae234b0
GK		 2565 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2566 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2567 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2bfcf297 2568 ""
4ae234b0 2569 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
943c15ed
DE		 2570 [(set_attr "type" "two")
2571 (set_attr "length" "8")])
1fd4e8c1
RK		 2572
2573(define_insn ""
9ebbca7d 2574 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2575 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2576 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2577 (const_int 0)))
4ae234b0 2578 (clobber (match_scratch:P 3 "=r,r"))]
2bfcf297 2579 ""
9ebbca7d 2580 "@
4ae234b0 2581 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
9ebbca7d 2582 #"
b19003d8 2583 [(set_attr "type" "compare")
9ebbca7d
GK		 2584 (set_attr "length" "8,12")])
2585
2586(define_split
2587 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2588 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2589 (match_operand:GPR 2 "exact_log2_cint_operand"
2590 ""))
9ebbca7d 2591 (const_int 0)))
4ae234b0 2592 (clobber (match_scratch:GPR 3 ""))]
2bfcf297 2593 "reload_completed"
9ebbca7d 2594 [(set (match_dup 3)
4ae234b0 2595 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2596 (set (match_dup 0)
2597 (compare:CC (match_dup 3)
2598 (const_int 0)))]
2599 "")
1fd4e8c1
RK		 2600
2601(define_insn ""
9ebbca7d 2602 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2603 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2604 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2605 (const_int 0)))
4ae234b0
GK		 2606 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2607 (div:P (match_dup 1) (match_dup 2)))]
2bfcf297 2608 ""
9ebbca7d 2609 "@
4ae234b0 2610 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
9ebbca7d 2611 #"
b19003d8 2612 [(set_attr "type" "compare")
9ebbca7d
GK		 2613 (set_attr "length" "8,12")])
2614
2615(define_split
2616 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2617 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2618 (match_operand:GPR 2 "exact_log2_cint_operand"
2619 ""))
9ebbca7d 2620 (const_int 0)))
4ae234b0
GK		 2621 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2622 (div:GPR (match_dup 1) (match_dup 2)))]
2bfcf297 2623 "reload_completed"
9ebbca7d 2624 [(set (match_dup 0)
4ae234b0 2625 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2626 (set (match_dup 3)
2627 (compare:CC (match_dup 0)
2628 (const_int 0)))]
2629 "")
1fd4e8c1
RK		 2630
2631(define_insn ""
cd2b37d9 2632 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2633 (udiv:SI
996a5f59 2634 (plus:DI (ashift:DI
cd2b37d9 2635 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2636 (const_int 32))
23a900dc 2637 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2638 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2639 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2640 (umod:SI
996a5f59 2641 (plus:DI (ashift:DI
1fd4e8c1 2642 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2643 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2644 (match_dup 3)))]
ca7f5001 2645 "TARGET_POWER"
cfb557c4
RK		 2646 "div %0,%1,%3"
2647 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2648
2649;; To do unsigned divide we handle the cases of the divisor looking like a
2650;; negative number. If it is a constant that is less than 2**31, we don't
2651;; have to worry about the branches. So make a few subroutines here.
2652;;
2653;; First comes the normal case.
2654(define_expand "udivmodsi4_normal"
2655 [(set (match_dup 4) (const_int 0))
2656 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2657 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2658 (const_int 32))
2659 (zero_extend:DI (match_operand:SI 1 "" "")))
2660 (match_operand:SI 2 "" "")))
2661 (set (match_operand:SI 3 "" "")
996a5f59 2662 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2663 (const_int 32))
2664 (zero_extend:DI (match_dup 1)))
2665 (match_dup 2)))])]
ca7f5001 2666 "TARGET_POWER"
1fd4e8c1
RK		 2667 "
2668{ operands[4] = gen_reg_rtx (SImode); }")
2669
2670;; This handles the branches.
2671(define_expand "udivmodsi4_tests"
2672 [(set (match_operand:SI 0 "" "") (const_int 0))
2673 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2674 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2675 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2676 (label_ref (match_operand:SI 4 "" "")) (pc)))
2677 (set (match_dup 0) (const_int 1))
2678 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2679 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2680 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2681 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2682 "TARGET_POWER"
1fd4e8c1
RK		 2683 "
2684{ operands[5] = gen_reg_rtx (CCUNSmode);
2685 operands[6] = gen_reg_rtx (CCmode);
2686}")
2687
2688(define_expand "udivmodsi4"
cd2b37d9
RK		 2689 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2690 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2691 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2692 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2693 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2694 ""
1fd4e8c1
RK		 2695 "
2696{
2697 rtx label = 0;
2698
8ffd9c51 2699 if (! TARGET_POWER)
c4d38ccb
MM		 2700 {
2701 if (! TARGET_POWERPC)
2702 {
39403d82
DE		 2703 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2704 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2705 emit_insn (gen_divus_call ());
39403d82
DE		 2706 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2707 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2708 DONE;
2709 }
2710 else
2711 FAIL;
2712 }
0081a354 2713
1fd4e8c1
RK		 2714 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2715 {
2716 operands[2] = force_reg (SImode, operands[2]);
2717 label = gen_label_rtx ();
2718 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2719 operands[3], label));
2720 }
2721 else
2722 operands[2] = force_reg (SImode, operands[2]);
2723
2724 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2725 operands[3]));
2726 if (label)
2727 emit_label (label);
2728
2729 DONE;
2730}")
0081a354 2731
fada905b
MM		 2732;; AIX architecture-independent common-mode multiply (DImode),
2733;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2734;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2735;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2736;; assumed unused if generating common-mode, so ignore.
2737(define_insn "mulh_call"
2738 [(set (reg:SI 3)
2739 (truncate:SI
2740 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2741 (sign_extend:DI (reg:SI 4)))
2742 (const_int 32))))
1de43f85 2743 (clobber (reg:SI LR_REGNO))]
fada905b 2744 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2745 "bla __mulh"
2746 [(set_attr "type" "imul")])
fada905b
MM		 2747
2748(define_insn "mull_call"
2749 [(set (reg:DI 3)
2750 (mult:DI (sign_extend:DI (reg:SI 3))
2751 (sign_extend:DI (reg:SI 4))))
1de43f85 2752 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2753 (clobber (reg:SI 0))]
2754 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2755 "bla __mull"
2756 [(set_attr "type" "imul")])
fada905b
MM		 2757
2758(define_insn "divss_call"
2759 [(set (reg:SI 3)
2760 (div:SI (reg:SI 3) (reg:SI 4)))
2761 (set (reg:SI 4)
2762 (mod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2763 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2764 (clobber (reg:SI 0))]
2765 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2766 "bla __divss"
2767 [(set_attr "type" "idiv")])
fada905b
MM		 2768
2769(define_insn "divus_call"
8ffd9c51
RK		 2770 [(set (reg:SI 3)
2771 (udiv:SI (reg:SI 3) (reg:SI 4)))
2772 (set (reg:SI 4)
2773 (umod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2774 (clobber (reg:SI LR_REGNO))
fada905b 2775 (clobber (reg:SI 0))
e65a3857 2776 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2777 (clobber (reg:CC CR1_REGNO))]
fada905b 2778 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2779 "bla __divus"
2780 [(set_attr "type" "idiv")])
fada905b
MM		 2781
2782(define_insn "quoss_call"
2783 [(set (reg:SI 3)
2784 (div:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2785 (clobber (reg:SI LR_REGNO))]
8ffd9c51 2786 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2787 "bla __quoss"
2788 [(set_attr "type" "idiv")])
0081a354 2789
fada905b
MM		 2790(define_insn "quous_call"
2791 [(set (reg:SI 3)
2792 (udiv:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2793 (clobber (reg:SI LR_REGNO))
fada905b 2794 (clobber (reg:SI 0))
e65a3857 2795 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2796 (clobber (reg:CC CR1_REGNO))]
fada905b 2797 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2798 "bla __quous"
2799 [(set_attr "type" "idiv")])
8ffd9c51 2800\f
bb21487f 2801;; Logical instructions
dfbdccdb
GK		 2802;; The logical instructions are mostly combined by using match_operator,
2803;; but the plain AND insns are somewhat different because there is no
2804;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2805;; those rotate-and-mask operations. Thus, the AND insns come first.
2806
29ae5b89
JL		 2807(define_insn "andsi3"
2808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2809 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2810 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2811 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1fd4e8c1
RK		 2812 ""
2813 "@
2814 and %0,%1,%2
ca7f5001
RK		 2815 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2816 {andil.|andi.} %0,%1,%b2
520308bc
DE		 2817 {andiu.|andis.} %0,%1,%u2"
2818 [(set_attr "type" "*,*,compare,compare")])
52d3af72
DE		 2819
2820;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2821;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2822;; machines causes an execution serialization
1fd4e8c1 2823
7cd5235b 2824(define_insn "*andsi3_internal2"
52d3af72
DE		 2825 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2826 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2827 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2828 (const_int 0)))
52d3af72
DE		 2829 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2830 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2831 "TARGET_32BIT"
1fd4e8c1
RK		 2832 "@
2833 and. %3,%1,%2
ca7f5001
RK		 2834 {andil.|andi.} %3,%1,%b2
2835 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2836 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2837 #
2838 #
2839 #
2840 #"
2841 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2842 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2843
0ba1b2ff
AM		 2844(define_insn "*andsi3_internal3"
2845 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2846 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2847 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2848 (const_int 0)))
2849 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2850 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2851 "TARGET_64BIT"
0ba1b2ff
AM		 2852 "@
2853 #
2854 {andil.|andi.} %3,%1,%b2
2855 {andiu.|andis.} %3,%1,%u2
2856 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2857 #
2858 #
2859 #
2860 #"
2861 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2862 (set_attr "length" "8,4,4,4,8,8,8,8")])
2863
52d3af72
DE		 2864(define_split
2865 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2866 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2867 (match_operand:GPR 2 "and_operand" ""))
1fd4e8c1 2868 (const_int 0)))
4ae234b0 2869 (clobber (match_scratch:GPR 3 ""))
52d3af72 2870 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2871 "reload_completed"
52d3af72 2872 [(parallel [(set (match_dup 3)
4ae234b0
GK		 2873 (and:<MODE> (match_dup 1)
2874 (match_dup 2)))
52d3af72
DE		 2875 (clobber (match_dup 4))])
2876 (set (match_dup 0)
2877 (compare:CC (match_dup 3)
2878 (const_int 0)))]
2879 "")
2880
0ba1b2ff
AM		 2881;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2882;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2883
2884(define_split
2885 [(set (match_operand:CC 0 "cc_reg_operand" "")
2886 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2887 (match_operand:SI 2 "gpc_reg_operand" ""))
2888 (const_int 0)))
2889 (clobber (match_scratch:SI 3 ""))
2890 (clobber (match_scratch:CC 4 ""))]
2891 "TARGET_POWERPC64 && reload_completed"
2892 [(parallel [(set (match_dup 3)
2893 (and:SI (match_dup 1)
2894 (match_dup 2)))
2895 (clobber (match_dup 4))])
2896 (set (match_dup 0)
2897 (compare:CC (match_dup 3)
2898 (const_int 0)))]
2899 "")
2900
2901(define_insn "*andsi3_internal4"
52d3af72
DE		 2902 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2903 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2904 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2905 (const_int 0)))
2906 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2907 (and:SI (match_dup 1)
2908 (match_dup 2)))
2909 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2910 "TARGET_32BIT"
1fd4e8c1
RK		 2911 "@
2912 and. %0,%1,%2
ca7f5001
RK		 2913 {andil.|andi.} %0,%1,%b2
2914 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2915 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2916 #
2917 #
2918 #
2919 #"
2920 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2921 (set_attr "length" "4,4,4,4,8,8,8,8")])
2922
0ba1b2ff
AM		 2923(define_insn "*andsi3_internal5"
2924 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2925 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2926 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2927 (const_int 0)))
2928 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2929 (and:SI (match_dup 1)
2930 (match_dup 2)))
2931 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2932 "TARGET_64BIT"
0ba1b2ff
AM		 2933 "@
2934 #
2935 {andil.|andi.} %0,%1,%b2
2936 {andiu.|andis.} %0,%1,%u2
2937 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2938 #
2939 #
2940 #
2941 #"
2942 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2943 (set_attr "length" "8,4,4,4,8,8,8,8")])
2944
52d3af72
DE		 2945(define_split
2946 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2947 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2948 (match_operand:SI 2 "and_operand" ""))
2949 (const_int 0)))
2950 (set (match_operand:SI 0 "gpc_reg_operand" "")
2951 (and:SI (match_dup 1)
2952 (match_dup 2)))
2953 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2954 "reload_completed"
52d3af72
DE		 2955 [(parallel [(set (match_dup 0)
2956 (and:SI (match_dup 1)
2957 (match_dup 2)))
2958 (clobber (match_dup 4))])
2959 (set (match_dup 3)
2960 (compare:CC (match_dup 0)
2961 (const_int 0)))]
2962 "")
1fd4e8c1 2963
0ba1b2ff
AM		 2964(define_split
2965 [(set (match_operand:CC 3 "cc_reg_operand" "")
2966 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2967 (match_operand:SI 2 "gpc_reg_operand" ""))
2968 (const_int 0)))
2969 (set (match_operand:SI 0 "gpc_reg_operand" "")
2970 (and:SI (match_dup 1)
2971 (match_dup 2)))
2972 (clobber (match_scratch:CC 4 ""))]
2973 "TARGET_POWERPC64 && reload_completed"
2974 [(parallel [(set (match_dup 0)
2975 (and:SI (match_dup 1)
2976 (match_dup 2)))
2977 (clobber (match_dup 4))])
2978 (set (match_dup 3)
2979 (compare:CC (match_dup 0)
2980 (const_int 0)))]
2981 "")
2982
2983;; Handle the PowerPC64 rlwinm corner case
2984
2985(define_insn_and_split "*andsi3_internal6"
2986 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2987 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2988 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2989 "TARGET_POWERPC64"
2990 "#"
2991 "TARGET_POWERPC64"
2992 [(set (match_dup 0)
2993 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2994 (match_dup 4)))
2995 (set (match_dup 0)
2996 (rotate:SI (match_dup 0) (match_dup 5)))]
2997 "
2998{
2999 int mb = extract_MB (operands[2]);
3000 int me = extract_ME (operands[2]);
3001 operands[3] = GEN_INT (me + 1);
3002 operands[5] = GEN_INT (32 - (me + 1));
3003 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3004}"
3005 [(set_attr "length" "8")])
3006
7cd5235b 3007(define_expand "iorsi3"
cd2b37d9 3008 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3009 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3010 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 3011 ""
f357808b
RK		 3012 "
3013{
7cd5235b 3014 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3015 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3016 {
3017 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3018 rtx tmp = ((!can_create_pseudo_p ()
3019 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3020 ? operands[0] : gen_reg_rtx (SImode));
3021
a260abc9
DE		 3022 emit_insn (gen_iorsi3 (tmp, operands[1],
3023 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3024 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3025 DONE;
3026 }
f357808b
RK		 3027}")
3028
7cd5235b 3029(define_expand "xorsi3"
cd2b37d9 3030 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3031 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3032 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 3033 ""
7cd5235b 3034 "
1fd4e8c1 3035{
7cd5235b 3036 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3037 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3038 {
3039 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3040 rtx tmp = ((!can_create_pseudo_p ()
3041 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3042 ? operands[0] : gen_reg_rtx (SImode));
3043
a260abc9
DE		 3044 emit_insn (gen_xorsi3 (tmp, operands[1],
3045 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3046 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3047 DONE;
3048 }
1fd4e8c1
RK		 3049}")
3050
dfbdccdb 3051(define_insn "*boolsi3_internal1"
7cd5235b 3052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 3053 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3054 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3055 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 3056 ""
3057 "@
dfbdccdb
GK		 3058 %q3 %0,%1,%2
3059 {%q3il|%q3i} %0,%1,%b2
3060 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 3061
dfbdccdb 3062(define_insn "*boolsi3_internal2"
52d3af72 3063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 3064 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 3065 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3066 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3067 (const_int 0)))
52d3af72 3068 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3069 "TARGET_32BIT"
52d3af72 3070 "@
dfbdccdb 3071 %q4. %3,%1,%2
52d3af72
DE		 3072 #"
3073 [(set_attr "type" "compare")
3074 (set_attr "length" "4,8")])
3075
3076(define_split
3077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3078 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3079 [(match_operand:SI 1 "gpc_reg_operand" "")
3080 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3081 (const_int 0)))
52d3af72 3082 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3083 "TARGET_32BIT && reload_completed"
dfbdccdb 3084 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3085 (set (match_dup 0)
3086 (compare:CC (match_dup 3)
3087 (const_int 0)))]
3088 "")
815cdc52 3089
dfbdccdb 3090(define_insn "*boolsi3_internal3"
52d3af72 3091 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3092 (compare:CC (match_operator:SI 4 "boolean_operator"
3093 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3094 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3095 (const_int 0)))
52d3af72 3096 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3097 (match_dup 4))]
4b8a63d6 3098 "TARGET_32BIT"
52d3af72 3099 "@
dfbdccdb 3100 %q4. %0,%1,%2
52d3af72
DE		 3101 #"
3102 [(set_attr "type" "compare")
3103 (set_attr "length" "4,8")])
3104
3105(define_split
e72247f4 3106 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3107 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3108 [(match_operand:SI 1 "gpc_reg_operand" "")
3109 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3110 (const_int 0)))
75540af0 3111 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3112 (match_dup 4))]
4b8a63d6 3113 "TARGET_32BIT && reload_completed"
dfbdccdb 3114 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3115 (set (match_dup 3)
3116 (compare:CC (match_dup 0)
3117 (const_int 0)))]
3118 "")
1fd4e8c1 3119
6ae08853 3120;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 3121;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 3122
3123(define_split
3124 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 3125 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3126 [(match_operand:SI 1 "gpc_reg_operand" "")
3127 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 3128 ""
dfbdccdb
GK		 3129 [(set (match_dup 0) (match_dup 4))
3130 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 3131"
3132{
dfbdccdb
GK		 3133 rtx i;
3134 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1c563bed 3135 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3136 operands[1], i);
dfbdccdb 3137 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
1c563bed 3138 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3139 operands[0], i);
a260abc9
DE		 3140}")
3141
dfbdccdb 3142(define_insn "*boolcsi3_internal1"
cd2b37d9 3143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3144 (match_operator:SI 3 "boolean_operator"
3145 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3146 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 3147 ""
dfbdccdb 3148 "%q3 %0,%2,%1")
1fd4e8c1 3149
dfbdccdb 3150(define_insn "*boolcsi3_internal2"
52d3af72 3151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3152 (compare:CC (match_operator:SI 4 "boolean_operator"
3153 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3154 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3155 (const_int 0)))
52d3af72 3156 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3157 "TARGET_32BIT"
52d3af72 3158 "@
dfbdccdb 3159 %q4. %3,%2,%1
52d3af72
DE		 3160 #"
3161 [(set_attr "type" "compare")
3162 (set_attr "length" "4,8")])
3163
3164(define_split
3165 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3166 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3167 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3168 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3169 (const_int 0)))
52d3af72 3170 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3171 "TARGET_32BIT && reload_completed"
dfbdccdb 3172 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3173 (set (match_dup 0)
3174 (compare:CC (match_dup 3)
3175 (const_int 0)))]
3176 "")
1fd4e8c1 3177
dfbdccdb 3178(define_insn "*boolcsi3_internal3"
52d3af72 3179 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3180 (compare:CC (match_operator:SI 4 "boolean_operator"
3181 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3182 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3183 (const_int 0)))
52d3af72 3184 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3185 (match_dup 4))]
4b8a63d6 3186 "TARGET_32BIT"
52d3af72 3187 "@
dfbdccdb 3188 %q4. %0,%2,%1
52d3af72
DE		 3189 #"
3190 [(set_attr "type" "compare")
3191 (set_attr "length" "4,8")])
3192
3193(define_split
e72247f4 3194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3195 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3196 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3197 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3198 (const_int 0)))
75540af0 3199 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3200 (match_dup 4))]
4b8a63d6 3201 "TARGET_32BIT && reload_completed"
dfbdccdb 3202 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3203 (set (match_dup 3)
3204 (compare:CC (match_dup 0)
3205 (const_int 0)))]
3206 "")
3207
dfbdccdb 3208(define_insn "*boolccsi3_internal1"
cd2b37d9 3209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3210 (match_operator:SI 3 "boolean_operator"
3211 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3212 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 3213 ""
dfbdccdb 3214 "%q3 %0,%1,%2")
1fd4e8c1 3215
dfbdccdb 3216(define_insn "*boolccsi3_internal2"
52d3af72 3217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3218 (compare:CC (match_operator:SI 4 "boolean_operator"
3219 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3220 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3221 (const_int 0)))
52d3af72 3222 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3223 "TARGET_32BIT"
52d3af72 3224 "@
dfbdccdb 3225 %q4. %3,%1,%2
52d3af72
DE		 3226 #"
3227 [(set_attr "type" "compare")
3228 (set_attr "length" "4,8")])
3229
3230(define_split
3231 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3232 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3233 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3234 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3235 (const_int 0)))
52d3af72 3236 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3237 "TARGET_32BIT && reload_completed"
dfbdccdb 3238 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3239 (set (match_dup 0)
3240 (compare:CC (match_dup 3)
3241 (const_int 0)))]
3242 "")
1fd4e8c1 3243
dfbdccdb 3244(define_insn "*boolccsi3_internal3"
52d3af72 3245 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3246 (compare:CC (match_operator:SI 4 "boolean_operator"
3247 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3248 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3249 (const_int 0)))
52d3af72 3250 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3251 (match_dup 4))]
4b8a63d6 3252 "TARGET_32BIT"
52d3af72 3253 "@
dfbdccdb 3254 %q4. %0,%1,%2
52d3af72
DE		 3255 #"
3256 [(set_attr "type" "compare")
3257 (set_attr "length" "4,8")])
3258
3259(define_split
e72247f4 3260 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3261 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3262 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3263 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3264 (const_int 0)))
75540af0 3265 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3266 (match_dup 4))]
4b8a63d6 3267 "TARGET_32BIT && reload_completed"
dfbdccdb 3268 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3269 (set (match_dup 3)
3270 (compare:CC (match_dup 0)
3271 (const_int 0)))]
3272 "")
1fd4e8c1
RK		 3273
3274;; maskir insn. We need four forms because things might be in arbitrary
3275;; orders. Don't define forms that only set CR fields because these
3276;; would modify an input register.
3277
7cd5235b 3278(define_insn "*maskir_internal1"
cd2b37d9 3279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3280 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3281 (match_operand:SI 1 "gpc_reg_operand" "0"))
3282 (and:SI (match_dup 2)
cd2b37d9 3283 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 3284 "TARGET_POWER"
01def764 3285 "maskir %0,%3,%2")
1fd4e8c1 3286
7cd5235b 3287(define_insn "*maskir_internal2"
242e8072 3288 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3289 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3290 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 3291 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 3292 (match_dup 2))))]
ca7f5001 3293 "TARGET_POWER"
01def764 3294 "maskir %0,%3,%2")
1fd4e8c1 3295
7cd5235b 3296(define_insn "*maskir_internal3"
cd2b37d9 3297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 3298 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 3299 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 3300 (and:SI (not:SI (match_dup 2))
3301 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3302 "TARGET_POWER"
01def764 3303 "maskir %0,%3,%2")
1fd4e8c1 3304
7cd5235b 3305(define_insn "*maskir_internal4"
cd2b37d9
RK		 3306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3307 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 3308 (match_operand:SI 2 "gpc_reg_operand" "r"))
3309 (and:SI (not:SI (match_dup 2))
3310 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3311 "TARGET_POWER"
01def764 3312 "maskir %0,%3,%2")
1fd4e8c1 3313
7cd5235b 3314(define_insn "*maskir_internal5"
9ebbca7d 3315 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3316 (compare:CC
9ebbca7d
GK		 3317 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3318 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 3319 (and:SI (match_dup 2)
9ebbca7d 3320 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 3321 (const_int 0)))
9ebbca7d 3322 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3323 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3324 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 3325 "TARGET_POWER"
9ebbca7d
GK		 3326 "@
3327 maskir. %0,%3,%2
3328 #"
3329 [(set_attr "type" "compare")
3330 (set_attr "length" "4,8")])
3331
3332(define_split
3333 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3334 (compare:CC
3335 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3336 (match_operand:SI 1 "gpc_reg_operand" ""))
3337 (and:SI (match_dup 2)
3338 (match_operand:SI 3 "gpc_reg_operand" "")))
3339 (const_int 0)))
3340 (set (match_operand:SI 0 "gpc_reg_operand" "")
3341 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3342 (and:SI (match_dup 2) (match_dup 3))))]
3343 "TARGET_POWER && reload_completed"
3344 [(set (match_dup 0)
3345 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3346 (and:SI (match_dup 2) (match_dup 3))))
3347 (set (match_dup 4)
3348 (compare:CC (match_dup 0)
3349 (const_int 0)))]
3350 "")
1fd4e8c1 3351
7cd5235b 3352(define_insn "*maskir_internal6"
9ebbca7d 3353 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3354 (compare:CC
9ebbca7d
GK		 3355 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3356 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3357 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 3358 (match_dup 2)))
1fd4e8c1 3359 (const_int 0)))
9ebbca7d 3360 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3361 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3362 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 3363 "TARGET_POWER"
9ebbca7d
GK		 3364 "@
3365 maskir. %0,%3,%2
3366 #"
3367 [(set_attr "type" "compare")
3368 (set_attr "length" "4,8")])
3369
3370(define_split
3371 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3372 (compare:CC
3373 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3374 (match_operand:SI 1 "gpc_reg_operand" ""))
3375 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3376 (match_dup 2)))
3377 (const_int 0)))
3378 (set (match_operand:SI 0 "gpc_reg_operand" "")
3379 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3380 (and:SI (match_dup 3) (match_dup 2))))]
3381 "TARGET_POWER && reload_completed"
3382 [(set (match_dup 0)
3383 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3384 (and:SI (match_dup 3) (match_dup 2))))
3385 (set (match_dup 4)
3386 (compare:CC (match_dup 0)
3387 (const_int 0)))]
3388 "")
1fd4e8c1 3389
7cd5235b 3390(define_insn "*maskir_internal7"
9ebbca7d 3391 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 3392 (compare:CC
9ebbca7d
GK		 3393 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3394 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 3395 (and:SI (not:SI (match_dup 2))
9ebbca7d 3396 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 3397 (const_int 0)))
9ebbca7d 3398 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 3399 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3400 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3401 "TARGET_POWER"
9ebbca7d
GK		 3402 "@
3403 maskir. %0,%3,%2
3404 #"
3405 [(set_attr "type" "compare")
3406 (set_attr "length" "4,8")])
3407
3408(define_split
3409 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3410 (compare:CC
3411 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3412 (match_operand:SI 3 "gpc_reg_operand" ""))
3413 (and:SI (not:SI (match_dup 2))
3414 (match_operand:SI 1 "gpc_reg_operand" "")))
3415 (const_int 0)))
3416 (set (match_operand:SI 0 "gpc_reg_operand" "")
3417 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3418 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3419 "TARGET_POWER && reload_completed"
3420 [(set (match_dup 0)
3421 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3422 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3423 (set (match_dup 4)
3424 (compare:CC (match_dup 0)
3425 (const_int 0)))]
3426 "")
1fd4e8c1 3427
7cd5235b 3428(define_insn "*maskir_internal8"
9ebbca7d 3429 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3430 (compare:CC
9ebbca7d
GK		 3431 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3432 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 3433 (and:SI (not:SI (match_dup 2))
9ebbca7d 3434 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 3435 (const_int 0)))
9ebbca7d 3436 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3437 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3438 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 3439 "TARGET_POWER"
9ebbca7d
GK		 3440 "@
3441 maskir. %0,%3,%2
3442 #"
3443 [(set_attr "type" "compare")
3444 (set_attr "length" "4,8")])
fcce224d 3445
9ebbca7d
GK		 3446(define_split
3447 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3448 (compare:CC
3449 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3450 (match_operand:SI 2 "gpc_reg_operand" ""))
3451 (and:SI (not:SI (match_dup 2))
3452 (match_operand:SI 1 "gpc_reg_operand" "")))
3453 (const_int 0)))
3454 (set (match_operand:SI 0 "gpc_reg_operand" "")
3455 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3456 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3457 "TARGET_POWER && reload_completed"
3458 [(set (match_dup 0)
3459 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3460 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3461 (set (match_dup 4)
3462 (compare:CC (match_dup 0)
3463 (const_int 0)))]
3464 "")
fcce224d 3465\f
1fd4e8c1
RK		 3466;; Rotate and shift insns, in all their variants. These support shifts,
3467;; field inserts and extracts, and various combinations thereof.
034c1be0 3468(define_expand "insv"
0ad91047
DE		 3469 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3470 (match_operand:SI 1 "const_int_operand" "")
3471 (match_operand:SI 2 "const_int_operand" ""))
3472 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 3473 ""
3474 "
3475{
3476 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3477 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
14502dad
JM		 3478 compiler if the address of the structure is taken later. Likewise, do
3479 not handle invalid E500 subregs. */
034c1be0 3480 if (GET_CODE (operands[0]) == SUBREG
14502dad
JM		 3481 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3482 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3483 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
034c1be0 3484 FAIL;
a78e33fc
DE		 3485
3486 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3487 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3488 else
3489 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3490 DONE;
034c1be0
MM		 3491}")
3492
a78e33fc 3493(define_insn "insvsi"
cd2b37d9 3494 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 3495 (match_operand:SI 1 "const_int_operand" "i")
3496 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 3497 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 3498 ""
3499 "*
3500{
3501 int start = INTVAL (operands[2]) & 31;
3502 int size = INTVAL (operands[1]) & 31;
3503
89e9f3a8
MM		 3504 operands[4] = GEN_INT (32 - start - size);
3505 operands[1] = GEN_INT (start + size - 1);
a66078ee 3506 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3507}"
3508 [(set_attr "type" "insert_word")])
1fd4e8c1 3509
a78e33fc 3510(define_insn "*insvsi_internal1"
d56d506a
RK		 3511 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3512 (match_operand:SI 1 "const_int_operand" "i")
3513 (match_operand:SI 2 "const_int_operand" "i"))
6d0a8091 3514 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
d56d506a 3515 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3516 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3517 "*
3518{
3519 int shift = INTVAL (operands[4]) & 31;
3520 int start = INTVAL (operands[2]) & 31;
3521 int size = INTVAL (operands[1]) & 31;
3522
89e9f3a8 3523 operands[4] = GEN_INT (shift - start - size);
6d0a8091 3524 operands[1] = GEN_INT (start + size - 1);
a66078ee 3525 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3526}"
3527 [(set_attr "type" "insert_word")])
d56d506a 3528
a78e33fc 3529(define_insn "*insvsi_internal2"
d56d506a
RK		 3530 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3531 (match_operand:SI 1 "const_int_operand" "i")
3532 (match_operand:SI 2 "const_int_operand" "i"))
3533 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3534 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3535 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3536 "*
3537{
3538 int shift = INTVAL (operands[4]) & 31;
3539 int start = INTVAL (operands[2]) & 31;
3540 int size = INTVAL (operands[1]) & 31;
3541
89e9f3a8
MM		 3542 operands[4] = GEN_INT (32 - shift - start - size);
3543 operands[1] = GEN_INT (start + size - 1);
a66078ee 3544 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3545}"
3546 [(set_attr "type" "insert_word")])
d56d506a 3547
a78e33fc 3548(define_insn "*insvsi_internal3"
d56d506a
RK		 3549 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3550 (match_operand:SI 1 "const_int_operand" "i")
3551 (match_operand:SI 2 "const_int_operand" "i"))
3552 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3553 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 3554 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3555 "*
3556{
3557 int shift = INTVAL (operands[4]) & 31;
3558 int start = INTVAL (operands[2]) & 31;
3559 int size = INTVAL (operands[1]) & 31;
3560
89e9f3a8
MM		 3561 operands[4] = GEN_INT (32 - shift - start - size);
3562 operands[1] = GEN_INT (start + size - 1);
a66078ee 3563 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3564}"
3565 [(set_attr "type" "insert_word")])
d56d506a 3566
a78e33fc 3567(define_insn "*insvsi_internal4"
d56d506a
RK		 3568 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3569 (match_operand:SI 1 "const_int_operand" "i")
3570 (match_operand:SI 2 "const_int_operand" "i"))
3571 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3572 (match_operand:SI 4 "const_int_operand" "i")
3573 (match_operand:SI 5 "const_int_operand" "i")))]
3574 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3575 "*
3576{
3577 int extract_start = INTVAL (operands[5]) & 31;
3578 int extract_size = INTVAL (operands[4]) & 31;
3579 int insert_start = INTVAL (operands[2]) & 31;
3580 int insert_size = INTVAL (operands[1]) & 31;
3581
3582/* Align extract field with insert field */
3a598fbe 3583 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3584 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3585 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 3586}"
3587 [(set_attr "type" "insert_word")])
d56d506a 3588
f241bf89
EC		 3589;; combine patterns for rlwimi
3590(define_insn "*insvsi_internal5"
3591 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3592 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3593 (match_operand:SI 1 "mask_operand" "i"))
3594 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3595 (match_operand:SI 2 "const_int_operand" "i"))
3596 (match_operand:SI 5 "mask_operand" "i"))))]
3597 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3598 "*
3599{
3600 int me = extract_ME(operands[5]);
3601 int mb = extract_MB(operands[5]);
3602 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3603 operands[2] = GEN_INT(mb);
3604 operands[1] = GEN_INT(me);
3605 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3606}"
3607 [(set_attr "type" "insert_word")])
3608
3609(define_insn "*insvsi_internal6"
3610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3611 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3612 (match_operand:SI 2 "const_int_operand" "i"))
3613 (match_operand:SI 5 "mask_operand" "i"))
3614 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3615 (match_operand:SI 1 "mask_operand" "i"))))]
3616 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3617 "*
3618{
3619 int me = extract_ME(operands[5]);
3620 int mb = extract_MB(operands[5]);
3621 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3622 operands[2] = GEN_INT(mb);
3623 operands[1] = GEN_INT(me);
3624 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3625}"
3626 [(set_attr "type" "insert_word")])
3627
a78e33fc 3628(define_insn "insvdi"
685f3906 3629 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3630 (match_operand:SI 1 "const_int_operand" "i")
3631 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3632 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3633 "TARGET_POWERPC64"
3634 "*
3635{
3636 int start = INTVAL (operands[2]) & 63;
3637 int size = INTVAL (operands[1]) & 63;
3638
a78e33fc
DE		 3639 operands[1] = GEN_INT (64 - start - size);
3640 return \"rldimi %0,%3,%H1,%H2\";
44cd321e
PS		 3641}"
3642 [(set_attr "type" "insert_dword")])
685f3906 3643
11ac38b2
DE		 3644(define_insn "*insvdi_internal2"
3645 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3646 (match_operand:SI 1 "const_int_operand" "i")
3647 (match_operand:SI 2 "const_int_operand" "i"))
3648 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3649 (match_operand:SI 4 "const_int_operand" "i")))]
3650 "TARGET_POWERPC64
3651 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3652 "*
3653{
3654 int shift = INTVAL (operands[4]) & 63;
3655 int start = (INTVAL (operands[2]) & 63) - 32;
3656 int size = INTVAL (operands[1]) & 63;
3657
3658 operands[4] = GEN_INT (64 - shift - start - size);
3659 operands[2] = GEN_INT (start);
3660 operands[1] = GEN_INT (start + size - 1);
3661 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3662}")
3663
3664(define_insn "*insvdi_internal3"
3665 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3666 (match_operand:SI 1 "const_int_operand" "i")
3667 (match_operand:SI 2 "const_int_operand" "i"))
3668 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3669 (match_operand:SI 4 "const_int_operand" "i")))]
3670 "TARGET_POWERPC64
3671 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3672 "*
3673{
3674 int shift = INTVAL (operands[4]) & 63;
3675 int start = (INTVAL (operands[2]) & 63) - 32;
3676 int size = INTVAL (operands[1]) & 63;
3677
3678 operands[4] = GEN_INT (64 - shift - start - size);
3679 operands[2] = GEN_INT (start);
3680 operands[1] = GEN_INT (start + size - 1);
3681 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3682}")
3683
034c1be0 3684(define_expand "extzv"
0ad91047
DE		 3685 [(set (match_operand 0 "gpc_reg_operand" "")
3686 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3687 (match_operand:SI 2 "const_int_operand" "")
3688 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3689 ""
3690 "
3691{
3692 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3693 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3694 compiler if the address of the structure is taken later. */
3695 if (GET_CODE (operands[0]) == SUBREG
3696 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3697 FAIL;
a78e33fc
DE		 3698
3699 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3700 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3701 else
3702 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3703 DONE;
034c1be0
MM		 3704}")
3705
a78e33fc 3706(define_insn "extzvsi"
cd2b37d9
RK		 3707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3708 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3709 (match_operand:SI 2 "const_int_operand" "i")
3710 (match_operand:SI 3 "const_int_operand" "i")))]
3711 ""
3712 "*
3713{
3714 int start = INTVAL (operands[3]) & 31;
3715 int size = INTVAL (operands[2]) & 31;
3716
3717 if (start + size >= 32)
3718 operands[3] = const0_rtx;
3719 else
89e9f3a8 3720 operands[3] = GEN_INT (start + size);
ca7f5001 3721 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3722}")
3723
a78e33fc 3724(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3726 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3727 (match_operand:SI 2 "const_int_operand" "i,i")
3728 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3729 (const_int 0)))
9ebbca7d 3730 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3731 ""
1fd4e8c1
RK		 3732 "*
3733{
3734 int start = INTVAL (operands[3]) & 31;
3735 int size = INTVAL (operands[2]) & 31;
3736
9ebbca7d
GK		 3737 /* Force split for non-cc0 compare. */
3738 if (which_alternative == 1)
3739 return \"#\";
3740
43a88a8c 3741 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3742 word, it is possible to use andiu. or andil. to test it. This is
3743 useful because the condition register set-use delay is smaller for
3744 andi[ul]. than for rlinm. This doesn't work when the starting bit
3745 position is 0 because the LT and GT bits may be set wrong. */
3746
3747 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3748 {
3a598fbe 3749 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3750 - (1 << (16 - (start & 15) - size))));
3751 if (start < 16)
ca7f5001 3752 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3753 else
ca7f5001 3754 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3755 }
7e69e155 3756
1fd4e8c1
RK		 3757 if (start + size >= 32)
3758 operands[3] = const0_rtx;
3759 else
89e9f3a8 3760 operands[3] = GEN_INT (start + size);
ca7f5001 3761 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3762}"
44cd321e 3763 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3764 (set_attr "length" "4,8")])
3765
3766(define_split
3767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3768 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3769 (match_operand:SI 2 "const_int_operand" "")
3770 (match_operand:SI 3 "const_int_operand" ""))
3771 (const_int 0)))
3772 (clobber (match_scratch:SI 4 ""))]
ce71f754 3773 "reload_completed"
9ebbca7d
GK		 3774 [(set (match_dup 4)
3775 (zero_extract:SI (match_dup 1) (match_dup 2)
3776 (match_dup 3)))
3777 (set (match_dup 0)
3778 (compare:CC (match_dup 4)
3779 (const_int 0)))]
3780 "")
1fd4e8c1 3781
a78e33fc 3782(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3783 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3784 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3785 (match_operand:SI 2 "const_int_operand" "i,i")
3786 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3787 (const_int 0)))
9ebbca7d 3788 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3789 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3790 ""
1fd4e8c1
RK		 3791 "*
3792{
3793 int start = INTVAL (operands[3]) & 31;
3794 int size = INTVAL (operands[2]) & 31;
3795
9ebbca7d
GK		 3796 /* Force split for non-cc0 compare. */
3797 if (which_alternative == 1)
3798 return \"#\";
3799
bc401279 3800 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3801 a shift. The bit-field must end at the LSB. */
bc401279 3802 if (start >= 16 && start + size == 32)
df031c43 3803 {
bc401279
AM		 3804 operands[3] = GEN_INT ((1 << size) - 1);
3805 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3806 }
7e69e155 3807
1fd4e8c1
RK		 3808 if (start + size >= 32)
3809 operands[3] = const0_rtx;
3810 else
89e9f3a8 3811 operands[3] = GEN_INT (start + size);
ca7f5001 3812 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3813}"
44cd321e 3814 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3815 (set_attr "length" "4,8")])
3816
3817(define_split
3818 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3819 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3820 (match_operand:SI 2 "const_int_operand" "")
3821 (match_operand:SI 3 "const_int_operand" ""))
3822 (const_int 0)))
3823 (set (match_operand:SI 0 "gpc_reg_operand" "")
3824 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3825 "reload_completed"
9ebbca7d
GK		 3826 [(set (match_dup 0)
3827 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3828 (set (match_dup 4)
3829 (compare:CC (match_dup 0)
3830 (const_int 0)))]
3831 "")
1fd4e8c1 3832
a78e33fc 3833(define_insn "extzvdi"
685f3906
DE		 3834 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3835 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3836 (match_operand:SI 2 "const_int_operand" "i")
3837 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3838 "TARGET_POWERPC64"
3839 "*
3840{
3841 int start = INTVAL (operands[3]) & 63;
3842 int size = INTVAL (operands[2]) & 63;
3843
3844 if (start + size >= 64)
3845 operands[3] = const0_rtx;
3846 else
89e9f3a8
MM		 3847 operands[3] = GEN_INT (start + size);
3848 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3849 return \"rldicl %0,%1,%3,%2\";
3850}")
3851
a78e33fc 3852(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3853 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3854 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3855 (match_operand:SI 2 "const_int_operand" "i")
3856 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3857 (const_int 0)))
29ae5b89 3858 (clobber (match_scratch:DI 4 "=r"))]
683bdff7 3859 "TARGET_64BIT"
685f3906
DE		 3860 "*
3861{
3862 int start = INTVAL (operands[3]) & 63;
3863 int size = INTVAL (operands[2]) & 63;
3864
3865 if (start + size >= 64)
3866 operands[3] = const0_rtx;
3867 else
89e9f3a8
MM		 3868 operands[3] = GEN_INT (start + size);
3869 operands[2] = GEN_INT (64 - size);
685f3906 3870 return \"rldicl. %4,%1,%3,%2\";
9a3c428b
DE		 3871}"
3872 [(set_attr "type" "compare")])
685f3906 3873
a78e33fc 3874(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3875 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3876 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3877 (match_operand:SI 2 "const_int_operand" "i")
3878 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3879 (const_int 0)))
29ae5b89 3880 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3881 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
683bdff7 3882 "TARGET_64BIT"
685f3906
DE		 3883 "*
3884{
3885 int start = INTVAL (operands[3]) & 63;
3886 int size = INTVAL (operands[2]) & 63;
3887
3888 if (start + size >= 64)
3889 operands[3] = const0_rtx;
3890 else
89e9f3a8
MM		 3891 operands[3] = GEN_INT (start + size);
3892 operands[2] = GEN_INT (64 - size);
685f3906 3893 return \"rldicl. %0,%1,%3,%2\";
9a3c428b
DE		 3894}"
3895 [(set_attr "type" "compare")])
685f3906 3896
1fd4e8c1 3897(define_insn "rotlsi3"
44cd321e
PS		 3898 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3899 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3900 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
1fd4e8c1 3901 ""
44cd321e
PS		 3902 "@
3903 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3904 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3905 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3906
a260abc9 3907(define_insn "*rotlsi3_internal2"
44cd321e
PS		 3908 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3909 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3910 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3911 (const_int 0)))
44cd321e 3912 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
ce71f754 3913 ""
9ebbca7d 3914 "@
44cd321e
PS		 3915 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3916 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3917 #
9ebbca7d 3918 #"
44cd321e
PS		 3919 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3920 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3921
3922(define_split
3923 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3924 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3925 (match_operand:SI 2 "reg_or_cint_operand" ""))
3926 (const_int 0)))
3927 (clobber (match_scratch:SI 3 ""))]
ce71f754 3928 "reload_completed"
9ebbca7d
GK		 3929 [(set (match_dup 3)
3930 (rotate:SI (match_dup 1) (match_dup 2)))
3931 (set (match_dup 0)
3932 (compare:CC (match_dup 3)
3933 (const_int 0)))]
3934 "")
1fd4e8c1 3935
a260abc9 3936(define_insn "*rotlsi3_internal3"
44cd321e
PS		 3937 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3938 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3939 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3940 (const_int 0)))
44cd321e 3941 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3942 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3943 ""
9ebbca7d 3944 "@
44cd321e
PS		 3945 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3946 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3947 #
9ebbca7d 3948 #"
44cd321e
PS		 3949 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3950 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3951
3952(define_split
3953 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3954 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3955 (match_operand:SI 2 "reg_or_cint_operand" ""))
3956 (const_int 0)))
3957 (set (match_operand:SI 0 "gpc_reg_operand" "")
3958 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3959 "reload_completed"
9ebbca7d
GK		 3960 [(set (match_dup 0)
3961 (rotate:SI (match_dup 1) (match_dup 2)))
3962 (set (match_dup 3)
3963 (compare:CC (match_dup 0)
3964 (const_int 0)))]
3965 "")
1fd4e8c1 3966
a260abc9 3967(define_insn "*rotlsi3_internal4"
44cd321e
PS		 3968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3969 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3970 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3971 (match_operand:SI 3 "mask_operand" "n,n")))]
1fd4e8c1 3972 ""
44cd321e
PS		 3973 "@
3974 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3975 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3976 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3977
a260abc9 3978(define_insn "*rotlsi3_internal5"
44cd321e 3979 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 3980 (compare:CC (and:SI
44cd321e
PS		 3981 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3982 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3983 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 3984 (const_int 0)))
44cd321e 3985 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
ce71f754 3986 ""
9ebbca7d 3987 "@
44cd321e
PS		 3988 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3989 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3990 #
9ebbca7d 3991 #"
44cd321e
PS		 3992 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3993 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3994
3995(define_split
3996 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3997 (compare:CC (and:SI
3998 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3999 (match_operand:SI 2 "reg_or_cint_operand" ""))
4000 (match_operand:SI 3 "mask_operand" ""))
4001 (const_int 0)))
4002 (clobber (match_scratch:SI 4 ""))]
ce71f754 4003 "reload_completed"
9ebbca7d
GK		 4004 [(set (match_dup 4)
4005 (and:SI (rotate:SI (match_dup 1)
4006 (match_dup 2))
4007 (match_dup 3)))
4008 (set (match_dup 0)
4009 (compare:CC (match_dup 4)
4010 (const_int 0)))]
4011 "")
1fd4e8c1 4012
a260abc9 4013(define_insn "*rotlsi3_internal6"
44cd321e 4014 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 4015 (compare:CC (and:SI
44cd321e
PS		 4016 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4017 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4018 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 4019 (const_int 0)))
44cd321e 4020 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4021 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4022 ""
9ebbca7d 4023 "@
44cd321e
PS		 4024 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4025 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4026 #
9ebbca7d 4027 #"
44cd321e
PS		 4028 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4029 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4030
4031(define_split
4032 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4033 (compare:CC (and:SI
4034 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4035 (match_operand:SI 2 "reg_or_cint_operand" ""))
4036 (match_operand:SI 3 "mask_operand" ""))
4037 (const_int 0)))
4038 (set (match_operand:SI 0 "gpc_reg_operand" "")
4039 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4040 "reload_completed"
9ebbca7d
GK		 4041 [(set (match_dup 0)
4042 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4043 (set (match_dup 4)
4044 (compare:CC (match_dup 0)
4045 (const_int 0)))]
4046 "")
1fd4e8c1 4047
a260abc9 4048(define_insn "*rotlsi3_internal7"
cd2b37d9 4049 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4050 (zero_extend:SI
4051 (subreg:QI
cd2b37d9 4052 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4053 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4054 ""
ca7f5001 4055 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1 4056
a260abc9 4057(define_insn "*rotlsi3_internal8"
44cd321e 4058 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4059 (compare:CC (zero_extend:SI
4060 (subreg:QI
44cd321e
PS		 4061 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4062 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4063 (const_int 0)))
44cd321e 4064 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4065 ""
9ebbca7d 4066 "@
44cd321e
PS		 4067 {rlnm.|rlwnm.} %3,%1,%2,0xff
4068 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4069 #
9ebbca7d 4070 #"
44cd321e
PS		 4071 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4072 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4073
4074(define_split
4075 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4076 (compare:CC (zero_extend:SI
4077 (subreg:QI
4078 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4079 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4080 (const_int 0)))
4081 (clobber (match_scratch:SI 3 ""))]
4082 "reload_completed"
4083 [(set (match_dup 3)
4084 (zero_extend:SI (subreg:QI
4085 (rotate:SI (match_dup 1)
4086 (match_dup 2)) 0)))
4087 (set (match_dup 0)
4088 (compare:CC (match_dup 3)
4089 (const_int 0)))]
4090 "")
1fd4e8c1 4091
a260abc9 4092(define_insn "*rotlsi3_internal9"
44cd321e 4093 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4094 (compare:CC (zero_extend:SI
4095 (subreg:QI
44cd321e
PS		 4096 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4097 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4098 (const_int 0)))
44cd321e 4099 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4100 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4101 ""
9ebbca7d 4102 "@
44cd321e
PS		 4103 {rlnm.|rlwnm.} %0,%1,%2,0xff
4104 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4105 #
9ebbca7d 4106 #"
44cd321e
PS		 4107 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4108 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4109
4110(define_split
4111 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4112 (compare:CC (zero_extend:SI
4113 (subreg:QI
4114 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4115 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4116 (const_int 0)))
4117 (set (match_operand:SI 0 "gpc_reg_operand" "")
4118 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4119 "reload_completed"
4120 [(set (match_dup 0)
4121 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4122 (set (match_dup 3)
4123 (compare:CC (match_dup 0)
4124 (const_int 0)))]
4125 "")
1fd4e8c1 4126
a260abc9 4127(define_insn "*rotlsi3_internal10"
44cd321e 4128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4129 (zero_extend:SI
4130 (subreg:HI
44cd321e
PS		 4131 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4132 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
1fd4e8c1 4133 ""
44cd321e
PS		 4134 "@
4135 {rlnm|rlwnm} %0,%1,%2,0xffff
4136 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4137 [(set_attr "type" "var_shift_rotate,integer")])
4138
1fd4e8c1 4139
a260abc9 4140(define_insn "*rotlsi3_internal11"
44cd321e 4141 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4142 (compare:CC (zero_extend:SI
4143 (subreg:HI
44cd321e
PS		 4144 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4145 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4146 (const_int 0)))
44cd321e 4147 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4148 ""
9ebbca7d 4149 "@
44cd321e
PS		 4150 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4151 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4152 #
9ebbca7d 4153 #"
44cd321e
PS		 4154 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4155 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4156
4157(define_split
4158 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4159 (compare:CC (zero_extend:SI
4160 (subreg:HI
4161 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4162 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4163 (const_int 0)))
4164 (clobber (match_scratch:SI 3 ""))]
4165 "reload_completed"
4166 [(set (match_dup 3)
4167 (zero_extend:SI (subreg:HI
4168 (rotate:SI (match_dup 1)
4169 (match_dup 2)) 0)))
4170 (set (match_dup 0)
4171 (compare:CC (match_dup 3)
4172 (const_int 0)))]
4173 "")
1fd4e8c1 4174
a260abc9 4175(define_insn "*rotlsi3_internal12"
44cd321e 4176 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4177 (compare:CC (zero_extend:SI
4178 (subreg:HI
44cd321e
PS		 4179 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4180 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4181 (const_int 0)))
44cd321e 4182 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4183 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4184 ""
9ebbca7d 4185 "@
44cd321e
PS		 4186 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4187 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4188 #
9ebbca7d 4189 #"
44cd321e
PS		 4190 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4191 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4192
4193(define_split
4194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4195 (compare:CC (zero_extend:SI
4196 (subreg:HI
4197 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4198 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4199 (const_int 0)))
4200 (set (match_operand:SI 0 "gpc_reg_operand" "")
4201 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4202 "reload_completed"
4203 [(set (match_dup 0)
4204 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4205 (set (match_dup 3)
4206 (compare:CC (match_dup 0)
4207 (const_int 0)))]
4208 "")
1fd4e8c1
RK		 4209
4210;; Note that we use "sle." instead of "sl." so that we can set
4211;; SHIFT_COUNT_TRUNCATED.
4212
ca7f5001
RK		 4213(define_expand "ashlsi3"
4214 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4215 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4216 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4217 ""
4218 "
4219{
4220 if (TARGET_POWER)
4221 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4222 else
25c341fa 4223 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4224 DONE;
4225}")
4226
4227(define_insn "ashlsi3_power"
cd2b37d9
RK		 4228 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4229 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4230 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4231 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4232 "TARGET_POWER"
1fd4e8c1
RK		 4233 "@
4234 sle %0,%1,%2
9ebbca7d 4235 {sli|slwi} %0,%1,%h2")
ca7f5001 4236
25c341fa 4237(define_insn "ashlsi3_no_power"
44cd321e
PS		 4238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4239 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4240 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4241 "! TARGET_POWER"
44cd321e
PS		 4242 "@
4243 {sl|slw} %0,%1,%2
4244 {sli|slwi} %0,%1,%h2"
4245 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4246
4247(define_insn ""
9ebbca7d
GK		 4248 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4249 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4250 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4251 (const_int 0)))
9ebbca7d
GK		 4252 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4253 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4254 "TARGET_POWER"
1fd4e8c1
RK		 4255 "@
4256 sle. %3,%1,%2
9ebbca7d
GK		 4257 {sli.|slwi.} %3,%1,%h2
4258 #
4259 #"
4260 [(set_attr "type" "delayed_compare")
4261 (set_attr "length" "4,4,8,8")])
4262
4263(define_split
4264 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4265 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4266 (match_operand:SI 2 "reg_or_cint_operand" ""))
4267 (const_int 0)))
4268 (clobber (match_scratch:SI 3 ""))
4269 (clobber (match_scratch:SI 4 ""))]
4270 "TARGET_POWER && reload_completed"
4271 [(parallel [(set (match_dup 3)
4272 (ashift:SI (match_dup 1) (match_dup 2)))
4273 (clobber (match_dup 4))])
4274 (set (match_dup 0)
4275 (compare:CC (match_dup 3)
4276 (const_int 0)))]
4277 "")
25c341fa 4278
ca7f5001 4279(define_insn ""
44cd321e
PS		 4280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4281 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4282 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4283 (const_int 0)))
44cd321e 4284 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4b8a63d6 4285 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4286 "@
44cd321e
PS		 4287 {sl.|slw.} %3,%1,%2
4288 {sli.|slwi.} %3,%1,%h2
4289 #
9ebbca7d 4290 #"
44cd321e
PS		 4291 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4292 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4293
4294(define_split
4295 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4296 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4297 (match_operand:SI 2 "reg_or_cint_operand" ""))
4298 (const_int 0)))
4299 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4300 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4301 [(set (match_dup 3)
4302 (ashift:SI (match_dup 1) (match_dup 2)))
4303 (set (match_dup 0)
4304 (compare:CC (match_dup 3)
4305 (const_int 0)))]
4306 "")
1fd4e8c1
RK		 4307
4308(define_insn ""
9ebbca7d
GK		 4309 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4310 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4311 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4312 (const_int 0)))
9ebbca7d 4313 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4314 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4315 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4316 "TARGET_POWER"
1fd4e8c1
RK		 4317 "@
4318 sle. %0,%1,%2
9ebbca7d
GK		 4319 {sli.|slwi.} %0,%1,%h2
4320 #
4321 #"
4322 [(set_attr "type" "delayed_compare")
4323 (set_attr "length" "4,4,8,8")])
4324
4325(define_split
4326 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4327 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4328 (match_operand:SI 2 "reg_or_cint_operand" ""))
4329 (const_int 0)))
4330 (set (match_operand:SI 0 "gpc_reg_operand" "")
4331 (ashift:SI (match_dup 1) (match_dup 2)))
4332 (clobber (match_scratch:SI 4 ""))]
4333 "TARGET_POWER && reload_completed"
4334 [(parallel [(set (match_dup 0)
4335 (ashift:SI (match_dup 1) (match_dup 2)))
4336 (clobber (match_dup 4))])
4337 (set (match_dup 3)
4338 (compare:CC (match_dup 0)
4339 (const_int 0)))]
4340 "")
25c341fa 4341
ca7f5001 4342(define_insn ""
44cd321e
PS		 4343 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4344 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4345 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4346 (const_int 0)))
44cd321e 4347 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 4348 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4349 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4350 "@
44cd321e
PS		 4351 {sl.|slw.} %0,%1,%2
4352 {sli.|slwi.} %0,%1,%h2
4353 #
9ebbca7d 4354 #"
44cd321e
PS		 4355 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4356 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4357
4358(define_split
4359 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4360 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4361 (match_operand:SI 2 "reg_or_cint_operand" ""))
4362 (const_int 0)))
4363 (set (match_operand:SI 0 "gpc_reg_operand" "")
4364 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4365 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4366 [(set (match_dup 0)
4367 (ashift:SI (match_dup 1) (match_dup 2)))
4368 (set (match_dup 3)
4369 (compare:CC (match_dup 0)
4370 (const_int 0)))]
4371 "")
1fd4e8c1 4372
915167f5 4373(define_insn "rlwinm"
cd2b37d9
RK		 4374 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4375 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4376 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4377 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4378 "includes_lshift_p (operands[2], operands[3])"
d56d506a 4379 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 4380
4381(define_insn ""
9ebbca7d 4382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4383 (compare:CC
9ebbca7d
GK		 4384 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4385 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4386 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4387 (const_int 0)))
9ebbca7d 4388 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4389 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4390 "@
4391 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4392 #"
4393 [(set_attr "type" "delayed_compare")
4394 (set_attr "length" "4,8")])
4395
4396(define_split
4397 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4398 (compare:CC
4399 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4400 (match_operand:SI 2 "const_int_operand" ""))
4401 (match_operand:SI 3 "mask_operand" ""))
4402 (const_int 0)))
4403 (clobber (match_scratch:SI 4 ""))]
ce71f754 4404 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4405 [(set (match_dup 4)
4406 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4407 (match_dup 3)))
4408 (set (match_dup 0)
4409 (compare:CC (match_dup 4)
4410 (const_int 0)))]
4411 "")
1fd4e8c1
RK		 4412
4413(define_insn ""
9ebbca7d 4414 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4415 (compare:CC
9ebbca7d
GK		 4416 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4417 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4418 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4419 (const_int 0)))
9ebbca7d 4420 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4421 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4422 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4423 "@
4424 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4425 #"
4426 [(set_attr "type" "delayed_compare")
4427 (set_attr "length" "4,8")])
4428
4429(define_split
4430 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4431 (compare:CC
4432 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4433 (match_operand:SI 2 "const_int_operand" ""))
4434 (match_operand:SI 3 "mask_operand" ""))
4435 (const_int 0)))
4436 (set (match_operand:SI 0 "gpc_reg_operand" "")
4437 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4438 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4439 [(set (match_dup 0)
4440 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4441 (set (match_dup 4)
4442 (compare:CC (match_dup 0)
4443 (const_int 0)))]
4444 "")
1fd4e8c1 4445
ca7f5001 4446;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 4447;; "sli x,x,0".
ca7f5001
RK		 4448(define_expand "lshrsi3"
4449 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4450 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4451 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4452 ""
4453 "
4454{
4455 if (TARGET_POWER)
4456 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4457 else
25c341fa 4458 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4459 DONE;
4460}")
4461
4462(define_insn "lshrsi3_power"
bdf423cb
MM		 4463 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4464 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4465 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4466 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 4467 "TARGET_POWER"
1fd4e8c1
RK		 4468 "@
4469 sre %0,%1,%2
bdf423cb 4470 mr %0,%1
ca7f5001
RK		 4471 {s%A2i|s%A2wi} %0,%1,%h2")
4472
25c341fa 4473(define_insn "lshrsi3_no_power"
44cd321e
PS		 4474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4475 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4476 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
25c341fa 4477 "! TARGET_POWER"
bdf423cb
MM		 4478 "@
4479 mr %0,%1
44cd321e
PS		 4480 {sr|srw} %0,%1,%2
4481 {sri|srwi} %0,%1,%h2"
4482 [(set_attr "type" "integer,var_shift_rotate,shift")])
1fd4e8c1
RK		 4483
4484(define_insn ""
9ebbca7d
GK		 4485 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4486 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4487 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4488 (const_int 0)))
9ebbca7d
GK		 4489 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4490 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4491 "TARGET_POWER"
1fd4e8c1 4492 "@
29ae5b89
JL		 4493 sre. %3,%1,%2
4494 mr. %1,%1
9ebbca7d
GK		 4495 {s%A2i.|s%A2wi.} %3,%1,%h2
4496 #
4497 #
4498 #"
4499 [(set_attr "type" "delayed_compare")
4500 (set_attr "length" "4,4,4,8,8,8")])
4501
4502(define_split
4503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4504 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4505 (match_operand:SI 2 "reg_or_cint_operand" ""))
4506 (const_int 0)))
4507 (clobber (match_scratch:SI 3 ""))
4508 (clobber (match_scratch:SI 4 ""))]
4509 "TARGET_POWER && reload_completed"
4510 [(parallel [(set (match_dup 3)
4511 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4512 (clobber (match_dup 4))])
4513 (set (match_dup 0)
4514 (compare:CC (match_dup 3)
4515 (const_int 0)))]
4516 "")
ca7f5001
RK		 4517
4518(define_insn ""
44cd321e
PS		 4519 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4520 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4521 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
ca7f5001 4522 (const_int 0)))
44cd321e 4523 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4b8a63d6 4524 "! TARGET_POWER && TARGET_32BIT"
bdf423cb
MM		 4525 "@
4526 mr. %1,%1
44cd321e
PS		 4527 {sr.|srw.} %3,%1,%2
4528 {sri.|srwi.} %3,%1,%h2
4529 #
9ebbca7d
GK		 4530 #
4531 #"
44cd321e
PS		 4532 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4533 (set_attr "length" "4,4,4,8,8,8")])
1fd4e8c1 4534
9ebbca7d
GK		 4535(define_split
4536 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4537 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4538 (match_operand:SI 2 "reg_or_cint_operand" ""))
4539 (const_int 0)))
4540 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4541 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4542 [(set (match_dup 3)
4543 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4544 (set (match_dup 0)
4545 (compare:CC (match_dup 3)
4546 (const_int 0)))]
4547 "")
4548
4549(define_insn ""
4550 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4551 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4552 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4553 (const_int 0)))
9ebbca7d 4554 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 4555 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4556 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4557 "TARGET_POWER"
1fd4e8c1 4558 "@
29ae5b89
JL		 4559 sre. %0,%1,%2
4560 mr. %0,%1
9ebbca7d
GK		 4561 {s%A2i.|s%A2wi.} %0,%1,%h2
4562 #
4563 #
4564 #"
4565 [(set_attr "type" "delayed_compare")
4566 (set_attr "length" "4,4,4,8,8,8")])
4567
4568(define_split
4569 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4570 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4571 (match_operand:SI 2 "reg_or_cint_operand" ""))
4572 (const_int 0)))
4573 (set (match_operand:SI 0 "gpc_reg_operand" "")
4574 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4575 (clobber (match_scratch:SI 4 ""))]
4576 "TARGET_POWER && reload_completed"
4577 [(parallel [(set (match_dup 0)
4578 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4579 (clobber (match_dup 4))])
4580 (set (match_dup 3)
4581 (compare:CC (match_dup 0)
4582 (const_int 0)))]
4583 "")
ca7f5001
RK		 4584
4585(define_insn ""
44cd321e
PS		 4586 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4587 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4588 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
815cdc52 4589 (const_int 0)))
44cd321e 4590 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
29ae5b89 4591 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4592 "! TARGET_POWER && TARGET_32BIT"
29ae5b89
JL		 4593 "@
4594 mr. %0,%1
44cd321e
PS		 4595 {sr.|srw.} %0,%1,%2
4596 {sri.|srwi.} %0,%1,%h2
4597 #
9ebbca7d
GK		 4598 #
4599 #"
44cd321e
PS		 4600 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4601 (set_attr "length" "4,4,4,8,8,8")])
9ebbca7d
GK		 4602
4603(define_split
4604 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4605 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4606 (match_operand:SI 2 "reg_or_cint_operand" ""))
4607 (const_int 0)))
4608 (set (match_operand:SI 0 "gpc_reg_operand" "")
4609 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4610 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4611 [(set (match_dup 0)
4612 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4613 (set (match_dup 3)
4614 (compare:CC (match_dup 0)
4615 (const_int 0)))]
4616 "")
1fd4e8c1
RK		 4617
4618(define_insn ""
cd2b37d9
RK		 4619 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4620 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4621 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4622 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4623 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 4624 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 4625
4626(define_insn ""
9ebbca7d 4627 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4628 (compare:CC
9ebbca7d
GK		 4629 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4630 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4631 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4632 (const_int 0)))
9ebbca7d 4633 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4634 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4635 "@
4636 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4637 #"
4638 [(set_attr "type" "delayed_compare")
4639 (set_attr "length" "4,8")])
4640
4641(define_split
4642 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4643 (compare:CC
4644 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4645 (match_operand:SI 2 "const_int_operand" ""))
4646 (match_operand:SI 3 "mask_operand" ""))
4647 (const_int 0)))
4648 (clobber (match_scratch:SI 4 ""))]
ce71f754 4649 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4650 [(set (match_dup 4)
4651 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4652 (match_dup 3)))
4653 (set (match_dup 0)
4654 (compare:CC (match_dup 4)
4655 (const_int 0)))]
4656 "")
1fd4e8c1
RK		 4657
4658(define_insn ""
9ebbca7d 4659 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4660 (compare:CC
9ebbca7d
GK		 4661 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4662 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4663 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4664 (const_int 0)))
9ebbca7d 4665 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4666 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4667 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4668 "@
4669 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4670 #"
4671 [(set_attr "type" "delayed_compare")
4672 (set_attr "length" "4,8")])
4673
4674(define_split
4675 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4676 (compare:CC
4677 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4678 (match_operand:SI 2 "const_int_operand" ""))
4679 (match_operand:SI 3 "mask_operand" ""))
4680 (const_int 0)))
4681 (set (match_operand:SI 0 "gpc_reg_operand" "")
4682 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4683 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4684 [(set (match_dup 0)
4685 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4686 (set (match_dup 4)
4687 (compare:CC (match_dup 0)
4688 (const_int 0)))]
4689 "")
1fd4e8c1
RK		 4690
4691(define_insn ""
cd2b37d9 4692 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4693 (zero_extend:SI
4694 (subreg:QI
cd2b37d9 4695 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4696 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4697 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4698 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4699
4700(define_insn ""
9ebbca7d 4701 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4702 (compare:CC
4703 (zero_extend:SI
4704 (subreg:QI
9ebbca7d
GK		 4705 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4706 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4707 (const_int 0)))
9ebbca7d 4708 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4709 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4710 "@
4711 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4712 #"
4713 [(set_attr "type" "delayed_compare")
4714 (set_attr "length" "4,8")])
4715
4716(define_split
4717 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4718 (compare:CC
4719 (zero_extend:SI
4720 (subreg:QI
4721 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4722 (match_operand:SI 2 "const_int_operand" "")) 0))
4723 (const_int 0)))
4724 (clobber (match_scratch:SI 3 ""))]
4725 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4726 [(set (match_dup 3)
4727 (zero_extend:SI (subreg:QI
4728 (lshiftrt:SI (match_dup 1)
4729 (match_dup 2)) 0)))
4730 (set (match_dup 0)
4731 (compare:CC (match_dup 3)
4732 (const_int 0)))]
4733 "")
1fd4e8c1
RK		 4734
4735(define_insn ""
9ebbca7d 4736 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4737 (compare:CC
4738 (zero_extend:SI
4739 (subreg:QI
9ebbca7d
GK		 4740 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4741 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4742 (const_int 0)))
9ebbca7d 4743 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4744 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4745 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4746 "@
4747 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4748 #"
4749 [(set_attr "type" "delayed_compare")
4750 (set_attr "length" "4,8")])
4751
4752(define_split
4753 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4754 (compare:CC
4755 (zero_extend:SI
4756 (subreg:QI
4757 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4758 (match_operand:SI 2 "const_int_operand" "")) 0))
4759 (const_int 0)))
4760 (set (match_operand:SI 0 "gpc_reg_operand" "")
4761 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4762 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4763 [(set (match_dup 0)
4764 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4765 (set (match_dup 3)
4766 (compare:CC (match_dup 0)
4767 (const_int 0)))]
4768 "")
1fd4e8c1
RK		 4769
4770(define_insn ""
cd2b37d9 4771 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4772 (zero_extend:SI
4773 (subreg:HI
cd2b37d9 4774 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4775 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4776 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4777 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4778
4779(define_insn ""
9ebbca7d 4780 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4781 (compare:CC
4782 (zero_extend:SI
4783 (subreg:HI
9ebbca7d
GK		 4784 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4785 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4786 (const_int 0)))
9ebbca7d 4787 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4788 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4789 "@
4790 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4791 #"
4792 [(set_attr "type" "delayed_compare")
4793 (set_attr "length" "4,8")])
4794
4795(define_split
4796 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4797 (compare:CC
4798 (zero_extend:SI
4799 (subreg:HI
4800 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4801 (match_operand:SI 2 "const_int_operand" "")) 0))
4802 (const_int 0)))
4803 (clobber (match_scratch:SI 3 ""))]
4804 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4805 [(set (match_dup 3)
4806 (zero_extend:SI (subreg:HI
4807 (lshiftrt:SI (match_dup 1)
4808 (match_dup 2)) 0)))
4809 (set (match_dup 0)
4810 (compare:CC (match_dup 3)
4811 (const_int 0)))]
4812 "")
1fd4e8c1
RK		 4813
4814(define_insn ""
9ebbca7d 4815 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4816 (compare:CC
4817 (zero_extend:SI
4818 (subreg:HI
9ebbca7d
GK		 4819 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4820 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4821 (const_int 0)))
9ebbca7d 4822 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4823 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4824 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4825 "@
4826 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4827 #"
4828 [(set_attr "type" "delayed_compare")
4829 (set_attr "length" "4,8")])
4830
4831(define_split
4832 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4833 (compare:CC
4834 (zero_extend:SI
4835 (subreg:HI
4836 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4837 (match_operand:SI 2 "const_int_operand" "")) 0))
4838 (const_int 0)))
4839 (set (match_operand:SI 0 "gpc_reg_operand" "")
4840 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4841 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4842 [(set (match_dup 0)
4843 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4844 (set (match_dup 3)
4845 (compare:CC (match_dup 0)
4846 (const_int 0)))]
4847 "")
1fd4e8c1
RK		 4848
4849(define_insn ""
cd2b37d9 4850 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4851 (const_int 1)
cd2b37d9
RK		 4852 (match_operand:SI 1 "gpc_reg_operand" "r"))
4853 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4854 (const_int 31)))]
ca7f5001 4855 "TARGET_POWER"
1fd4e8c1
RK		 4856 "rrib %0,%1,%2")
4857
4858(define_insn ""
cd2b37d9 4859 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4860 (const_int 1)
cd2b37d9
RK		 4861 (match_operand:SI 1 "gpc_reg_operand" "r"))
4862 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4863 (const_int 31)))]
ca7f5001 4864 "TARGET_POWER"
1fd4e8c1
RK		 4865 "rrib %0,%1,%2")
4866
4867(define_insn ""
cd2b37d9 4868 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4869 (const_int 1)
cd2b37d9
RK		 4870 (match_operand:SI 1 "gpc_reg_operand" "r"))
4871 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4872 (const_int 1)
4873 (const_int 0)))]
ca7f5001 4874 "TARGET_POWER"
1fd4e8c1
RK		 4875 "rrib %0,%1,%2")
4876
ca7f5001
RK		 4877(define_expand "ashrsi3"
4878 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4879 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4880 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4881 ""
4882 "
4883{
4884 if (TARGET_POWER)
4885 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4886 else
25c341fa 4887 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4888 DONE;
4889}")
4890
4891(define_insn "ashrsi3_power"
cd2b37d9
RK		 4892 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4893 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4894 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4895 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4896 "TARGET_POWER"
1fd4e8c1
RK		 4897 "@
4898 srea %0,%1,%2
44cd321e
PS		 4899 {srai|srawi} %0,%1,%h2"
4900 [(set_attr "type" "shift")])
ca7f5001 4901
25c341fa 4902(define_insn "ashrsi3_no_power"
44cd321e
PS		 4903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4904 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4905 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4906 "! TARGET_POWER"
44cd321e
PS		 4907 "@
4908 {sra|sraw} %0,%1,%2
4909 {srai|srawi} %0,%1,%h2"
4910 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4911
4912(define_insn ""
9ebbca7d
GK		 4913 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4914 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4915 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4916 (const_int 0)))
9ebbca7d
GK		 4917 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4918 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4919 "TARGET_POWER"
1fd4e8c1
RK		 4920 "@
4921 srea. %3,%1,%2
9ebbca7d
GK		 4922 {srai.|srawi.} %3,%1,%h2
4923 #
4924 #"
4925 [(set_attr "type" "delayed_compare")
4926 (set_attr "length" "4,4,8,8")])
4927
4928(define_split
4929 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4930 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4931 (match_operand:SI 2 "reg_or_cint_operand" ""))
4932 (const_int 0)))
4933 (clobber (match_scratch:SI 3 ""))
4934 (clobber (match_scratch:SI 4 ""))]
4935 "TARGET_POWER && reload_completed"
4936 [(parallel [(set (match_dup 3)
4937 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4938 (clobber (match_dup 4))])
4939 (set (match_dup 0)
4940 (compare:CC (match_dup 3)
4941 (const_int 0)))]
4942 "")
ca7f5001
RK		 4943
4944(define_insn ""
44cd321e
PS		 4945 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4946 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4947 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4948 (const_int 0)))
44cd321e 4949 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
25c341fa 4950 "! TARGET_POWER"
9ebbca7d 4951 "@
44cd321e
PS		 4952 {sra.|sraw.} %3,%1,%2
4953 {srai.|srawi.} %3,%1,%h2
4954 #
9ebbca7d 4955 #"
44cd321e
PS		 4956 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4957 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4958
4959(define_split
4960 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4961 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4962 (match_operand:SI 2 "reg_or_cint_operand" ""))
4963 (const_int 0)))
4964 (clobber (match_scratch:SI 3 ""))]
4965 "! TARGET_POWER && reload_completed"
4966 [(set (match_dup 3)
4967 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4968 (set (match_dup 0)
4969 (compare:CC (match_dup 3)
4970 (const_int 0)))]
4971 "")
1fd4e8c1
RK		 4972
4973(define_insn ""
9ebbca7d
GK		 4974 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4975 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4976 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4977 (const_int 0)))
9ebbca7d 4978 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4979 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4980 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4981 "TARGET_POWER"
1fd4e8c1
RK		 4982 "@
4983 srea. %0,%1,%2
9ebbca7d
GK		 4984 {srai.|srawi.} %0,%1,%h2
4985 #
4986 #"
4987 [(set_attr "type" "delayed_compare")
4988 (set_attr "length" "4,4,8,8")])
4989
4990(define_split
4991 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4992 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4993 (match_operand:SI 2 "reg_or_cint_operand" ""))
4994 (const_int 0)))
4995 (set (match_operand:SI 0 "gpc_reg_operand" "")
4996 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4997 (clobber (match_scratch:SI 4 ""))]
4998 "TARGET_POWER && reload_completed"
4999 [(parallel [(set (match_dup 0)
5000 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5001 (clobber (match_dup 4))])
5002 (set (match_dup 3)
5003 (compare:CC (match_dup 0)
5004 (const_int 0)))]
5005 "")
1fd4e8c1 5006
ca7f5001 5007(define_insn ""
44cd321e
PS		 5008 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5009 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5010 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 5011 (const_int 0)))
44cd321e 5012 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 5013 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 5014 "! TARGET_POWER"
9ebbca7d 5015 "@
44cd321e
PS		 5016 {sra.|sraw.} %0,%1,%2
5017 {srai.|srawi.} %0,%1,%h2
5018 #
9ebbca7d 5019 #"
44cd321e
PS		 5020 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5021 (set_attr "length" "4,4,8,8")])
1fd4e8c1 5022\f
9ebbca7d
GK		 5023(define_split
5024 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5025 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5026 (match_operand:SI 2 "reg_or_cint_operand" ""))
5027 (const_int 0)))
5028 (set (match_operand:SI 0 "gpc_reg_operand" "")
5029 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5030 "! TARGET_POWER && reload_completed"
5031 [(set (match_dup 0)
5032 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5033 (set (match_dup 3)
5034 (compare:CC (match_dup 0)
5035 (const_int 0)))]
5036 "")
5037
1fd4e8c1
RK		 5038;; Floating-point insns, excluding normal data motion.
5039;;
ca7f5001
RK		 5040;; PowerPC has a full set of single-precision floating point instructions.
5041;;
5042;; For the POWER architecture, we pretend that we have both SFmode and
5043;; DFmode insns, while, in fact, all fp insns are actually done in double.
5044;; The only conversions we will do will be when storing to memory. In that
5045;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 5046;;
5047;; Note that when we store into a single-precision memory location, we need to
5048;; use the frsp insn first. If the register being stored isn't dead, we
5049;; need a scratch register for the frsp. But this is difficult when the store
5050;; is done by reload. It is not incorrect to do the frsp on the register in
5051;; this case, we just lose precision that we would have otherwise gotten but
5052;; is not guaranteed. Perhaps this should be tightened up at some point.
5053
99176a91
AH		 5054(define_expand "extendsfdf2"
5055 [(set (match_operand:DF 0 "gpc_reg_operand" "")
97c54d9a 5056 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
99176a91
AH		 5057 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5058 "")
5059
5060(define_insn_and_split "*extendsfdf2_fpr"
97c54d9a
DE		 5061 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5062 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
a3170dc6 5063 "TARGET_HARD_FLOAT && TARGET_FPRS"
11ac38b2
DE		 5064 "@
5065 #
97c54d9a
DE		 5066 fmr %0,%1
5067 lfs%U1%X1 %0,%1"
d7b1468b 5068 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
11ac38b2 5069 [(const_int 0)]
5c30aff8 5070{
11ac38b2
DE		 5071 emit_note (NOTE_INSN_DELETED);
5072 DONE;
5073}
97c54d9a 5074 [(set_attr "type" "fp,fp,fpload")])
1fd4e8c1 5075
7a2f7870
AH		 5076(define_expand "truncdfsf2"
5077 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5078 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5079 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5080 "")
5081
99176a91 5082(define_insn "*truncdfsf2_fpr"
cd2b37d9
RK		 5083 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5084 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5085 "TARGET_HARD_FLOAT && TARGET_FPRS"
dcac138d 5086 "frsp %0,%1"
1fd4e8c1
RK		 5087 [(set_attr "type" "fp")])
5088
455350f4
RK		 5089(define_insn "aux_truncdfsf2"
5090 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 5091 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
a3170dc6 5092 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 5093 "frsp %0,%1"
5094 [(set_attr "type" "fp")])
5095
a3170dc6
AH		 5096(define_expand "negsf2"
5097 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5098 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5099 "TARGET_HARD_FLOAT"
5100 "")
5101
5102(define_insn "*negsf2"
cd2b37d9
RK		 5103 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5104 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5105 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5106 "fneg %0,%1"
5107 [(set_attr "type" "fp")])
5108
a3170dc6
AH		 5109(define_expand "abssf2"
5110 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5111 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5112 "TARGET_HARD_FLOAT"
5113 "")
5114
5115(define_insn "*abssf2"
cd2b37d9
RK		 5116 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5117 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5118 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5119 "fabs %0,%1"
5120 [(set_attr "type" "fp")])
5121
5122(define_insn ""
cd2b37d9
RK		 5123 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5124 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
a3170dc6 5125 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5126 "fnabs %0,%1"
5127 [(set_attr "type" "fp")])
5128
ca7f5001
RK		 5129(define_expand "addsf3"
5130 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5131 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5132 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5133 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5134 "")
5135
5136(define_insn ""
cd2b37d9
RK		 5137 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5138 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5139 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5140 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5141 "fadds %0,%1,%2"
ca7f5001
RK		 5142 [(set_attr "type" "fp")])
5143
5144(define_insn ""
5145 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5146 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5147 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5148 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5149 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 5150 [(set_attr "type" "fp")])
5151
5152(define_expand "subsf3"
5153 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5154 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5155 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5156 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5157 "")
5158
5159(define_insn ""
5160 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5161 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5162 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5163 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5164 "fsubs %0,%1,%2"
1fd4e8c1
RK		 5165 [(set_attr "type" "fp")])
5166
ca7f5001 5167(define_insn ""
cd2b37d9
RK		 5168 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5169 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5170 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5171 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5172 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 5173 [(set_attr "type" "fp")])
5174
5175(define_expand "mulsf3"
5176 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5177 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5178 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5179 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5180 "")
5181
5182(define_insn ""
5183 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5184 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5185 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5186 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5187 "fmuls %0,%1,%2"
1fd4e8c1
RK		 5188 [(set_attr "type" "fp")])
5189
ca7f5001 5190(define_insn ""
cd2b37d9
RK		 5191 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5192 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5193 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5194 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5195 "{fm|fmul} %0,%1,%2"
0780f386 5196 [(set_attr "type" "dmul")])
1fd4e8c1 5197
ef765ea9
DE		 5198(define_insn "fres"
5199 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5200 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5201 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5202 "fres %0,%1"
5203 [(set_attr "type" "fp")])
5204
ca7f5001
RK		 5205(define_expand "divsf3"
5206 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5207 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5208 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5209 "TARGET_HARD_FLOAT"
ef765ea9
DE		 5210{
5211 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5212 && flag_finite_math_only && !flag_trapping_math)
5213 {
5214 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5215 DONE;
5216 }
5217})
ca7f5001
RK		 5218
5219(define_insn ""
cd2b37d9
RK		 5220 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5221 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5222 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5223 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5224 "fdivs %0,%1,%2"
ca7f5001
RK		 5225 [(set_attr "type" "sdiv")])
5226
5227(define_insn ""
5228 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5229 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5230 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5231 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5232 "{fd|fdiv} %0,%1,%2"
0780f386 5233 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 5234
5235(define_insn ""
cd2b37d9
RK		 5236 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5237 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5238 (match_operand:SF 2 "gpc_reg_operand" "f"))
5239 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5240 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5241 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 5242 [(set_attr "type" "fp")])
5243
5244(define_insn ""
5245 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5246 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5247 (match_operand:SF 2 "gpc_reg_operand" "f"))
5248 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5249 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5250 "{fma|fmadd} %0,%1,%2,%3"
cf27b467 5251 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5252
5253(define_insn ""
cd2b37d9
RK		 5254 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5255 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5256 (match_operand:SF 2 "gpc_reg_operand" "f"))
5257 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5258 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5259 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 5260 [(set_attr "type" "fp")])
5261
5262(define_insn ""
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5265 (match_operand:SF 2 "gpc_reg_operand" "f"))
5266 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5267 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5268 "{fms|fmsub} %0,%1,%2,%3"
cf27b467 5269 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5270
5271(define_insn ""
cd2b37d9
RK		 5272 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5273 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5274 (match_operand:SF 2 "gpc_reg_operand" "f"))
5275 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5276 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5277 && HONOR_SIGNED_ZEROS (SFmode)"
5278 "fnmadds %0,%1,%2,%3"
5279 [(set_attr "type" "fp")])
5280
5281(define_insn ""
5282 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5283 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5284 (match_operand:SF 2 "gpc_reg_operand" "f"))
5285 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5286 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5287 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5288 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 5289 [(set_attr "type" "fp")])
5290
5291(define_insn ""
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5293 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5294 (match_operand:SF 2 "gpc_reg_operand" "f"))
5295 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 5296 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5297 "{fnma|fnmadd} %0,%1,%2,%3"
cf27b467 5298 [(set_attr "type" "dmul")])
1fd4e8c1 5299
16823694
GK		 5300(define_insn ""
5301 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5302 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5303 (match_operand:SF 2 "gpc_reg_operand" "f"))
5304 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5305 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5306 && ! HONOR_SIGNED_ZEROS (SFmode)"
5307 "{fnma|fnmadd} %0,%1,%2,%3"
5308 [(set_attr "type" "dmul")])
5309
1fd4e8c1 5310(define_insn ""
cd2b37d9
RK		 5311 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5312 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5313 (match_operand:SF 2 "gpc_reg_operand" "f"))
5314 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5315 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5316 && HONOR_SIGNED_ZEROS (SFmode)"
5317 "fnmsubs %0,%1,%2,%3"
5318 [(set_attr "type" "fp")])
5319
5320(define_insn ""
5321 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5322 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5323 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5324 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5325 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5326 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5327 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 5328 [(set_attr "type" "fp")])
5329
5330(define_insn ""
5331 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5332 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5333 (match_operand:SF 2 "gpc_reg_operand" "f"))
5334 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 5335 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5336 "{fnms|fnmsub} %0,%1,%2,%3"
cf27b467 5337 [(set_attr "type" "dmul")])
1fd4e8c1 5338
16823694
GK		 5339(define_insn ""
5340 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5341 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5342 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5343 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5344 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5345 && ! HONOR_SIGNED_ZEROS (SFmode)"
5346 "{fnms|fnmsub} %0,%1,%2,%3"
9c6fdb46 5347 [(set_attr "type" "dmul")])
16823694 5348
ca7f5001
RK		 5349(define_expand "sqrtsf2"
5350 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5351 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
a3170dc6 5352 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5353 "")
5354
5355(define_insn ""
5356 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5357 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5358 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5359 "fsqrts %0,%1"
5360 [(set_attr "type" "ssqrt")])
5361
5362(define_insn ""
5363 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5364 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5365 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5366 "fsqrt %0,%1"
5367 [(set_attr "type" "dsqrt")])
5368
0530bc70
AP		 5369(define_expand "copysignsf3"
5370 [(set (match_dup 3)
5371 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5372 (set (match_dup 4)
5373 (neg:SF (abs:SF (match_dup 1))))
5374 (set (match_operand:SF 0 "gpc_reg_operand" "")
5375 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5376 (match_dup 5))
5377 (match_dup 3)
5378 (match_dup 4)))]
5379 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
bb8df8a6 5380 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
0530bc70
AP		 5381 {
5382 operands[3] = gen_reg_rtx (SFmode);
5383 operands[4] = gen_reg_rtx (SFmode);
5384 operands[5] = CONST0_RTX (SFmode);
5385 })
5386
5387(define_expand "copysigndf3"
5388 [(set (match_dup 3)
5389 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5390 (set (match_dup 4)
5391 (neg:DF (abs:DF (match_dup 1))))
5392 (set (match_operand:DF 0 "gpc_reg_operand" "")
5393 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5394 (match_dup 5))
5395 (match_dup 3)
5396 (match_dup 4)))]
5397 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5398 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5399 {
5400 operands[3] = gen_reg_rtx (DFmode);
5401 operands[4] = gen_reg_rtx (DFmode);
5402 operands[5] = CONST0_RTX (DFmode);
5403 })
5404
94d7001a
RK		 5405;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5406;; fsel instruction and some auxiliary computations. Then we just have a
5407;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05 5408;; combine.
7ae4d8d4 5409(define_expand "smaxsf3"
8e871c05 5410 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5411 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5412 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5413 (match_dup 1)
5414 (match_dup 2)))]
89e73849 5415 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5416 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 5417
7ae4d8d4 5418(define_expand "sminsf3"
50a0b056
GK		 5419 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5420 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5421 (match_operand:SF 2 "gpc_reg_operand" ""))
5422 (match_dup 2)
5423 (match_dup 1)))]
89e73849 5424 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5425 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 5426
8e871c05
RK		 5427(define_split
5428 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5429 (match_operator:SF 3 "min_max_operator"
5430 [(match_operand:SF 1 "gpc_reg_operand" "")
5431 (match_operand:SF 2 "gpc_reg_operand" "")]))]
89e73849 5432 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5433 [(const_int 0)]
5434 "
6ae08853 5435{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5436 operands[1], operands[2]);
5437 DONE;
5438}")
2f607b94 5439
a3170dc6
AH		 5440(define_expand "movsicc"
5441 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5442 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5443 (match_operand:SI 2 "gpc_reg_operand" "")
5444 (match_operand:SI 3 "gpc_reg_operand" "")))]
5445 "TARGET_ISEL"
5446 "
5447{
5448 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5449 DONE;
5450 else
5451 FAIL;
5452}")
5453
5454;; We use the BASE_REGS for the isel input operands because, if rA is
5455;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5456;; because we may switch the operands and rB may end up being rA.
5457;;
5458;; We need 2 patterns: an unsigned and a signed pattern. We could
5459;; leave out the mode in operand 4 and use one pattern, but reload can
5460;; change the mode underneath our feet and then gets confused trying
5461;; to reload the value.
5462(define_insn "isel_signed"
5463 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5464 (if_then_else:SI
5465 (match_operator 1 "comparison_operator"
5466 [(match_operand:CC 4 "cc_reg_operand" "y")
5467 (const_int 0)])
5468 (match_operand:SI 2 "gpc_reg_operand" "b")
5469 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5470 "TARGET_ISEL"
5471 "*
5472{ return output_isel (operands); }"
5473 [(set_attr "length" "4")])
5474
5475(define_insn "isel_unsigned"
5476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5477 (if_then_else:SI
5478 (match_operator 1 "comparison_operator"
5479 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5480 (const_int 0)])
5481 (match_operand:SI 2 "gpc_reg_operand" "b")
5482 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5483 "TARGET_ISEL"
5484 "*
5485{ return output_isel (operands); }"
5486 [(set_attr "length" "4")])
5487
94d7001a 5488(define_expand "movsfcc"
0ad91047 5489 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 5490 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5491 (match_operand:SF 2 "gpc_reg_operand" "")
5492 (match_operand:SF 3 "gpc_reg_operand" "")))]
a3170dc6 5493 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5494 "
5495{
50a0b056
GK		 5496 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5497 DONE;
94d7001a 5498 else
50a0b056 5499 FAIL;
94d7001a 5500}")
d56d506a 5501
50a0b056 5502(define_insn "*fselsfsf4"
8e871c05
RK		 5503 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5504 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5505 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5506 (match_operand:SF 2 "gpc_reg_operand" "f")
5507 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5508 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5509 "fsel %0,%1,%2,%3"
5510 [(set_attr "type" "fp")])
2f607b94 5511
50a0b056 5512(define_insn "*fseldfsf4"
94d7001a
RK		 5513 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5514 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 5515 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5516 (match_operand:SF 2 "gpc_reg_operand" "f")
5517 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5518 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5519 "fsel %0,%1,%2,%3"
5520 [(set_attr "type" "fp")])
d56d506a 5521
7a2f7870
AH		 5522(define_expand "negdf2"
5523 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5524 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5525 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5526 "")
5527
99176a91 5528(define_insn "*negdf2_fpr"
cd2b37d9
RK		 5529 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5530 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5531 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5532 "fneg %0,%1"
5533 [(set_attr "type" "fp")])
5534
7a2f7870
AH		 5535(define_expand "absdf2"
5536 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5537 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5538 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5539 "")
5540
99176a91 5541(define_insn "*absdf2_fpr"
cd2b37d9
RK		 5542 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5543 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5544 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5545 "fabs %0,%1"
5546 [(set_attr "type" "fp")])
5547
99176a91 5548(define_insn "*nabsdf2_fpr"
cd2b37d9
RK		 5549 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5550 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
a3170dc6 5551 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5552 "fnabs %0,%1"
5553 [(set_attr "type" "fp")])
5554
7a2f7870
AH		 5555(define_expand "adddf3"
5556 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5557 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5558 (match_operand:DF 2 "gpc_reg_operand" "")))]
5559 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5560 "")
5561
99176a91 5562(define_insn "*adddf3_fpr"
cd2b37d9
RK		 5563 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5564 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5565 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5566 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5567 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 5568 [(set_attr "type" "fp")])
5569
7a2f7870
AH		 5570(define_expand "subdf3"
5571 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5572 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5573 (match_operand:DF 2 "gpc_reg_operand" "")))]
5574 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5575 "")
5576
99176a91 5577(define_insn "*subdf3_fpr"
cd2b37d9
RK		 5578 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5579 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5580 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5581 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5582 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 5583 [(set_attr "type" "fp")])
5584
7a2f7870
AH		 5585(define_expand "muldf3"
5586 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5587 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5588 (match_operand:DF 2 "gpc_reg_operand" "")))]
5589 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5590 "")
5591
99176a91 5592(define_insn "*muldf3_fpr"
cd2b37d9
RK		 5593 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5594 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5595 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5596 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5597 "{fm|fmul} %0,%1,%2"
cfb557c4 5598 [(set_attr "type" "dmul")])
1fd4e8c1 5599
ef765ea9
DE		 5600(define_insn "fred"
5601 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5602 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5603 "TARGET_POPCNTB && flag_finite_math_only"
5604 "fre %0,%1"
5605 [(set_attr "type" "fp")])
5606
7a2f7870
AH		 5607(define_expand "divdf3"
5608 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5609 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5610 (match_operand:DF 2 "gpc_reg_operand" "")))]
5611 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
ef765ea9
DE		 5612{
5613 if (swdiv && !optimize_size && TARGET_POPCNTB
5614 && flag_finite_math_only && !flag_trapping_math)
5615 {
5616 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5617 DONE;
5618 }
5619})
7a2f7870 5620
99176a91 5621(define_insn "*divdf3_fpr"
cd2b37d9
RK		 5622 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5623 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5624 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5625 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5626 "{fd|fdiv} %0,%1,%2"
cfb557c4 5627 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 5628
5629(define_insn ""
cd2b37d9
RK		 5630 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5631 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5632 (match_operand:DF 2 "gpc_reg_operand" "f"))
5633 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5634 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5635 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 5636 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5637
5638(define_insn ""
cd2b37d9
RK		 5639 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5640 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5641 (match_operand:DF 2 "gpc_reg_operand" "f"))
5642 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5643 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5644 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 5645 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5646
5647(define_insn ""
cd2b37d9
RK		 5648 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5649 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5650 (match_operand:DF 2 "gpc_reg_operand" "f"))
5651 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5652 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5653 && HONOR_SIGNED_ZEROS (DFmode)"
5654 "{fnma|fnmadd} %0,%1,%2,%3"
5655 [(set_attr "type" "dmul")])
5656
5657(define_insn ""
5658 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5659 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5660 (match_operand:DF 2 "gpc_reg_operand" "f"))
5661 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5662 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5663 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5664 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 5665 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5666
5667(define_insn ""
cd2b37d9
RK		 5668 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5669 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5670 (match_operand:DF 2 "gpc_reg_operand" "f"))
5671 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5672 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5673 && HONOR_SIGNED_ZEROS (DFmode)"
5674 "{fnms|fnmsub} %0,%1,%2,%3"
5675 [(set_attr "type" "dmul")])
5676
5677(define_insn ""
5678 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5679 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5680 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5681 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
6ae08853 5682 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5683 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5684 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 5685 [(set_attr "type" "dmul")])
ca7f5001
RK		 5686
5687(define_insn "sqrtdf2"
5688 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5689 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5690 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5691 "fsqrt %0,%1"
5692 [(set_attr "type" "dsqrt")])
b77dfefc 5693
50a0b056 5694;; The conditional move instructions allow us to perform max and min
6ae08853 5695;; operations even when
b77dfefc 5696
7ae4d8d4 5697(define_expand "smaxdf3"
8e871c05 5698 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5699 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5700 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5701 (match_dup 1)
5702 (match_dup 2)))]
89e73849 5703 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5704 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 5705
7ae4d8d4 5706(define_expand "smindf3"
50a0b056
GK		 5707 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5708 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5709 (match_operand:DF 2 "gpc_reg_operand" ""))
5710 (match_dup 2)
5711 (match_dup 1)))]
89e73849 5712 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5713 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 5714
8e871c05
RK		 5715(define_split
5716 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5717 (match_operator:DF 3 "min_max_operator"
5718 [(match_operand:DF 1 "gpc_reg_operand" "")
5719 (match_operand:DF 2 "gpc_reg_operand" "")]))]
89e73849 5720 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5721 [(const_int 0)]
5722 "
6ae08853 5723{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5724 operands[1], operands[2]);
5725 DONE;
5726}")
b77dfefc 5727
94d7001a 5728(define_expand "movdfcc"
0ad91047 5729 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 5730 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5731 (match_operand:DF 2 "gpc_reg_operand" "")
5732 (match_operand:DF 3 "gpc_reg_operand" "")))]
a3170dc6 5733 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5734 "
5735{
50a0b056
GK		 5736 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5737 DONE;
94d7001a 5738 else
50a0b056 5739 FAIL;
94d7001a 5740}")
d56d506a 5741
50a0b056 5742(define_insn "*fseldfdf4"
8e871c05
RK		 5743 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5744 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 5745 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5746 (match_operand:DF 2 "gpc_reg_operand" "f")
5747 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5748 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5749 "fsel %0,%1,%2,%3"
5750 [(set_attr "type" "fp")])
d56d506a 5751
50a0b056 5752(define_insn "*fselsfdf4"
94d7001a
RK		 5753 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5754 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5755 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5756 (match_operand:DF 2 "gpc_reg_operand" "f")
5757 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5758 "TARGET_PPC_GFXOPT"
5759 "fsel %0,%1,%2,%3"
5760 [(set_attr "type" "fp")])
1fd4e8c1 5761\f
d095928f
AH		 5762;; Conversions to and from floating-point.
5763
5764(define_expand "fixuns_truncsfsi2"
5765 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5766 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5767 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5768 "")
5769
5770(define_expand "fix_truncsfsi2"
5771 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5772 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5773 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5774 "")
5775
9ebbca7d
GK		 5776; For each of these conversions, there is a define_expand, a define_insn
5777; with a '#' template, and a define_split (with C code). The idea is
5778; to allow constant folding with the template of the define_insn,
5779; then to have the insns split later (between sched1 and final).
5780
1fd4e8c1 5781(define_expand "floatsidf2"
802a0058
MM		 5782 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5783 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5784 (use (match_dup 2))
5785 (use (match_dup 3))
208c89ce 5786 (clobber (match_dup 4))
a7df97e6 5787 (clobber (match_dup 5))
9ebbca7d 5788 (clobber (match_dup 6))])]
17caeff2 5789 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5790 "
5791{
99176a91
AH		 5792 if (TARGET_E500_DOUBLE)
5793 {
5794 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5795 DONE;
5796 }
44cd321e
PS		 5797 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5798 {
5799 rtx t1 = gen_reg_rtx (DImode);
5800 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5801 DONE;
5802 }
05d49501
AM		 5803 if (TARGET_POWERPC64)
5804 {
5805 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5806 rtx t1 = gen_reg_rtx (DImode);
5807 rtx t2 = gen_reg_rtx (DImode);
5808 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5809 DONE;
5810 }
5811
802a0058 5812 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5813 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5814 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5815 operands[5] = gen_reg_rtx (DFmode);
5816 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5817}")
5818
230215f5 5819(define_insn_and_split "*floatsidf2_internal"
802a0058
MM		 5820 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5821 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5822 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5823 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5824 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5
DJ		 5825 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5826 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
a3170dc6 5827 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5828 "#"
b3a13419 5829 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5830 [(pc)]
208c89ce
MM		 5831 "
5832{
9ebbca7d 5833 rtx lowword, highword;
230215f5
GK		 5834 gcc_assert (MEM_P (operands[4]));
5835 highword = adjust_address (operands[4], SImode, 0);
5836 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d
GK		 5837 if (! WORDS_BIG_ENDIAN)
5838 {
5839 rtx tmp;
5840 tmp = highword; highword = lowword; lowword = tmp;
5841 }
5842
6ae08853 5843 emit_insn (gen_xorsi3 (operands[6], operands[1],
9ebbca7d 5844 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
230215f5
GK		 5845 emit_move_insn (lowword, operands[6]);
5846 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5847 emit_move_insn (operands[5], operands[4]);
5848 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5849 DONE;
230215f5
GK		 5850}"
5851 [(set_attr "length" "24")])
802a0058 5852
a3170dc6
AH		 5853(define_expand "floatunssisf2"
5854 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5855 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5856 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5857 "")
5858
802a0058
MM		 5859(define_expand "floatunssidf2"
5860 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5861 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5862 (use (match_dup 2))
5863 (use (match_dup 3))
a7df97e6 5864 (clobber (match_dup 4))
9ebbca7d 5865 (clobber (match_dup 5))])]
99176a91 5866 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5867 "
5868{
99176a91
AH		 5869 if (TARGET_E500_DOUBLE)
5870 {
5871 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5872 DONE;
5873 }
05d49501
AM		 5874 if (TARGET_POWERPC64)
5875 {
5876 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5877 rtx t1 = gen_reg_rtx (DImode);
5878 rtx t2 = gen_reg_rtx (DImode);
5879 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5880 t1, t2));
5881 DONE;
5882 }
5883
802a0058 5884 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5885 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 5886 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5887 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 5888}")
5889
230215f5 5890(define_insn_and_split "*floatunssidf2_internal"
802a0058
MM		 5891 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5892 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5893 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5894 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5895 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5 5896 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
a3170dc6 5897 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5898 "#"
b3a13419 5899 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5900 [(pc)]
9ebbca7d 5901 "
802a0058 5902{
9ebbca7d 5903 rtx lowword, highword;
230215f5
GK		 5904 gcc_assert (MEM_P (operands[4]));
5905 highword = adjust_address (operands[4], SImode, 0);
5906 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d 5907 if (! WORDS_BIG_ENDIAN)
f6968f59 5908 {
9ebbca7d
GK		 5909 rtx tmp;
5910 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 5911 }
802a0058 5912
230215f5
GK		 5913 emit_move_insn (lowword, operands[1]);
5914 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5915 emit_move_insn (operands[5], operands[4]);
5916 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5917 DONE;
230215f5
GK		 5918}"
5919 [(set_attr "length" "20")])
1fd4e8c1 5920
1fd4e8c1 5921(define_expand "fix_truncdfsi2"
045a8eb3 5922 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
802a0058
MM		 5923 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5924 (clobber (match_dup 2))
9ebbca7d 5925 (clobber (match_dup 3))])]
99176a91
AH		 5926 "(TARGET_POWER2 || TARGET_POWERPC)
5927 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5928 "
5929{
99176a91
AH		 5930 if (TARGET_E500_DOUBLE)
5931 {
5932 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5933 DONE;
5934 }
802a0058 5935 operands[2] = gen_reg_rtx (DImode);
44cd321e
PS		 5936 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5937 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5938 {
5939 operands[3] = gen_reg_rtx (DImode);
5940 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5941 operands[2], operands[3]));
5942 DONE;
5943 }
da4c340c
GK		 5944 if (TARGET_PPC_GFXOPT)
5945 {
5946 rtx orig_dest = operands[0];
045a8eb3 5947 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
da4c340c
GK		 5948 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5949 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5950 operands[2]));
5951 if (operands[0] != orig_dest)
5952 emit_move_insn (orig_dest, operands[0]);
5953 DONE;
5954 }
9ebbca7d 5955 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 5956}")
5957
da4c340c 5958(define_insn_and_split "*fix_truncdfsi2_internal"
802a0058
MM		 5959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5960 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 5961 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
9ebbca7d 5962 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
a3170dc6 5963 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5964 "#"
b3a13419 5965 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
da4c340c 5966 [(pc)]
9ebbca7d 5967 "
802a0058 5968{
9ebbca7d 5969 rtx lowword;
230215f5
GK		 5970 gcc_assert (MEM_P (operands[3]));
5971 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
802a0058 5972
9ebbca7d
GK		 5973 emit_insn (gen_fctiwz (operands[2], operands[1]));
5974 emit_move_insn (operands[3], operands[2]);
230215f5 5975 emit_move_insn (operands[0], lowword);
9ebbca7d 5976 DONE;
da4c340c
GK		 5977}"
5978 [(set_attr "length" "16")])
5979
5980(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5981 [(set (match_operand:SI 0 "memory_operand" "=Z")
5982 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5983 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5984 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5985 && TARGET_PPC_GFXOPT"
5986 "#"
5987 "&& 1"
5988 [(pc)]
5989 "
5990{
5991 emit_insn (gen_fctiwz (operands[2], operands[1]));
5992 emit_insn (gen_stfiwx (operands[0], operands[2]));
5993 DONE;
5994}"
5995 [(set_attr "length" "16")])
802a0058 5996
44cd321e
PS		 5997(define_insn_and_split "fix_truncdfsi2_mfpgpr"
5998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5999 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6000 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6001 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6002 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6003 "#"
6004 "&& 1"
6005 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6006 (set (match_dup 3) (match_dup 2))
6007 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6008 ""
6009 [(set_attr "length" "12")])
6010
615158e2 6011; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 6012; rather than (set (subreg:SI (reg)) (fix:SI ...))
6013; because the first makes it clear that operand 0 is not live
6014; before the instruction.
6015(define_insn "fctiwz"
da4c340c 6016 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
615158e2
JJ		 6017 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6018 UNSPEC_FCTIWZ))]
a3170dc6 6019 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
a260abc9
DE		 6020 "{fcirz|fctiwz} %0,%1"
6021 [(set_attr "type" "fp")])
6022
9719f3b7
DE		 6023(define_insn "btruncdf2"
6024 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6025 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6026 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6027 "friz %0,%1"
6028 [(set_attr "type" "fp")])
6029
6030(define_insn "btruncsf2"
6031 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6032 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6033 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6034 "friz %0,%1"
9719f3b7
DE		 6035 [(set_attr "type" "fp")])
6036
6037(define_insn "ceildf2"
6038 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6039 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6040 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6041 "frip %0,%1"
6042 [(set_attr "type" "fp")])
6043
6044(define_insn "ceilsf2"
833126ad 6045 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9719f3b7
DE		 6046 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6047 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6048 "frip %0,%1"
9719f3b7
DE		 6049 [(set_attr "type" "fp")])
6050
6051(define_insn "floordf2"
6052 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6053 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6054 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6055 "frim %0,%1"
6056 [(set_attr "type" "fp")])
6057
6058(define_insn "floorsf2"
6059 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6060 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6061 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6062 "frim %0,%1"
9719f3b7
DE		 6063 [(set_attr "type" "fp")])
6064
6065(define_insn "rounddf2"
6066 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6067 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6068 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6069 "frin %0,%1"
6070 [(set_attr "type" "fp")])
6071
6072(define_insn "roundsf2"
6073 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6074 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6075 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6076 "frin %0,%1"
9719f3b7
DE		 6077 [(set_attr "type" "fp")])
6078
da4c340c
GK		 6079; An UNSPEC is used so we don't have to support SImode in FP registers.
6080(define_insn "stfiwx"
6081 [(set (match_operand:SI 0 "memory_operand" "=Z")
6082 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6083 UNSPEC_STFIWX))]
6084 "TARGET_PPC_GFXOPT"
6085 "stfiwx %1,%y0"
6086 [(set_attr "type" "fpstore")])
6087
a3170dc6
AH		 6088(define_expand "floatsisf2"
6089 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6090 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6091 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6092 "")
6093
a473029f
RK		 6094(define_insn "floatdidf2"
6095 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
61c07d3c 6096 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
a3170dc6 6097 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6098 "fcfid %0,%1"
6099 [(set_attr "type" "fp")])
6100
44cd321e
PS		 6101(define_insn_and_split "floatsidf_ppc64_mfpgpr"
6102 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6103 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6104 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6105 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6106 "#"
6107 "&& 1"
6108 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6109 (set (match_dup 0) (float:DF (match_dup 2)))]
6110 "")
6111
05d49501
AM		 6112(define_insn_and_split "floatsidf_ppc64"
6113 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6114 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6115 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6116 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6117 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
44cd321e 6118 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 6119 "#"
ecb62ae7 6120 "&& 1"
05d49501
AM		 6121 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6122 (set (match_dup 2) (match_dup 3))
6123 (set (match_dup 4) (match_dup 2))
6124 (set (match_dup 0) (float:DF (match_dup 4)))]
6125 "")
6126
6127(define_insn_and_split "floatunssidf_ppc64"
6128 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6129 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6130 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6131 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6132 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 6133 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 6134 "#"
ecb62ae7 6135 "&& 1"
05d49501
AM		 6136 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6137 (set (match_dup 2) (match_dup 3))
6138 (set (match_dup 4) (match_dup 2))
6139 (set (match_dup 0) (float:DF (match_dup 4)))]
6140 "")
6141
a473029f 6142(define_insn "fix_truncdfdi2"
61c07d3c 6143 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
a473029f 6144 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 6145 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6146 "fctidz %0,%1"
6147 [(set_attr "type" "fp")])
ea112fc4 6148
678b7733
AM		 6149(define_expand "floatdisf2"
6150 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6151 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
994cf173 6152 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6153 "
6154{
994cf173 6155 rtx val = operands[1];
678b7733
AM		 6156 if (!flag_unsafe_math_optimizations)
6157 {
6158 rtx label = gen_label_rtx ();
994cf173
AM		 6159 val = gen_reg_rtx (DImode);
6160 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
678b7733
AM		 6161 emit_label (label);
6162 }
994cf173 6163 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
678b7733
AM		 6164 DONE;
6165}")
6166
6167;; This is not IEEE compliant if rounding mode is "round to nearest".
6168;; If the DI->DF conversion is inexact, then it's possible to suffer
6169;; from double rounding.
6170(define_insn_and_split "floatdisf2_internal1"
ea112fc4 6171 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
61c07d3c 6172 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
ea112fc4 6173 (clobber (match_scratch:DF 2 "=f"))]
678b7733 6174 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
ea112fc4
DE		 6175 "#"
6176 "&& reload_completed"
6177 [(set (match_dup 2)
6178 (float:DF (match_dup 1)))
6179 (set (match_dup 0)
6180 (float_truncate:SF (match_dup 2)))]
6181 "")
678b7733
AM		 6182
6183;; Twiddles bits to avoid double rounding.
b6d08ca1 6184;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 6185;; by a bit that won't be lost at that stage, but is below the SFmode
6186;; rounding position.
6187(define_expand "floatdisf2_internal2"
994cf173
AM		 6188 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6189 (const_int 53)))
6190 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6191 (const_int 2047)))
6192 (clobber (scratch:CC))])
6193 (set (match_dup 3) (plus:DI (match_dup 3)
6194 (const_int 1)))
6195 (set (match_dup 0) (plus:DI (match_dup 0)
6196 (const_int 2047)))
6197 (set (match_dup 4) (compare:CCUNS (match_dup 3)
c22e62a6 6198 (const_int 2)))
994cf173
AM		 6199 (set (match_dup 0) (ior:DI (match_dup 0)
6200 (match_dup 1)))
6201 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6202 (const_int -2048)))
6203 (clobber (scratch:CC))])
6204 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6205 (label_ref (match_operand:DI 2 "" ""))
678b7733 6206 (pc)))
994cf173
AM		 6207 (set (match_dup 0) (match_dup 1))]
6208 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6209 "
6210{
678b7733 6211 operands[3] = gen_reg_rtx (DImode);
994cf173 6212 operands[4] = gen_reg_rtx (CCUNSmode);
678b7733 6213}")
1fd4e8c1
RK		 6214\f
6215;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 6216;; of instructions. The & constraints are to prevent the register
6217;; allocator from allocating registers that overlap with the inputs
6218;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 6219;; also allow for the output being the same as one of the inputs.
a6ec530c 6220
266eb58a 6221(define_insn "*adddi3_noppc64"
a6ec530c
RK		 6222 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6223 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6224 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 6225 "! TARGET_POWERPC64"
0f645302
MM		 6226 "*
6227{
6228 if (WORDS_BIG_ENDIAN)
6229 return (GET_CODE (operands[2])) != CONST_INT
6230 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6231 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6232 else
6233 return (GET_CODE (operands[2])) != CONST_INT
6234 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6235 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6236}"
943c15ed
DE		 6237 [(set_attr "type" "two")
6238 (set_attr "length" "8")])
1fd4e8c1 6239
266eb58a 6240(define_insn "*subdi3_noppc64"
e7e5df70
RK		 6241 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6242 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6243 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 6244 "! TARGET_POWERPC64"
5502823b
RK		 6245 "*
6246{
0f645302
MM		 6247 if (WORDS_BIG_ENDIAN)
6248 return (GET_CODE (operands[1]) != CONST_INT)
6249 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6250 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6251 else
6252 return (GET_CODE (operands[1]) != CONST_INT)
6253 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6254 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 6255}"
943c15ed
DE		 6256 [(set_attr "type" "two")
6257 (set_attr "length" "8")])
ca7f5001 6258
266eb58a 6259(define_insn "*negdi2_noppc64"
a6ec530c
RK		 6260 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6261 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 6262 "! TARGET_POWERPC64"
5502823b
RK		 6263 "*
6264{
6265 return (WORDS_BIG_ENDIAN)
6266 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6267 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6268}"
943c15ed
DE		 6269 [(set_attr "type" "two")
6270 (set_attr "length" "8")])
ca7f5001 6271
8ffd9c51
RK		 6272(define_expand "mulsidi3"
6273 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6274 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6275 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 6276 "! TARGET_POWERPC64"
8ffd9c51
RK		 6277 "
6278{
6279 if (! TARGET_POWER && ! TARGET_POWERPC)
6280 {
39403d82
DE		 6281 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6282 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6283 emit_insn (gen_mull_call ());
cf27b467 6284 if (WORDS_BIG_ENDIAN)
39403d82 6285 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 6286 else
6287 {
6288 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 6289 gen_rtx_REG (SImode, 3));
cf27b467 6290 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 6291 gen_rtx_REG (SImode, 4));
cf27b467 6292 }
8ffd9c51
RK		 6293 DONE;
6294 }
6295 else if (TARGET_POWER)
6296 {
6297 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6298 DONE;
6299 }
6300}")
deb9225a 6301
8ffd9c51 6302(define_insn "mulsidi3_mq"
cd2b37d9 6303 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 6304 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 6305 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 6306 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 6307 "TARGET_POWER"
b19003d8 6308 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 6309 [(set_attr "type" "imul")
6310 (set_attr "length" "8")])
deb9225a 6311
f192bf8b 6312(define_insn "*mulsidi3_no_mq"
425c176f 6313 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 6314 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6315 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6316 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 6317 "*
6318{
6319 return (WORDS_BIG_ENDIAN)
6320 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6321 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6322}"
8ffd9c51
RK		 6323 [(set_attr "type" "imul")
6324 (set_attr "length" "8")])
deb9225a 6325
ebedb4dd
MM		 6326(define_split
6327 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6328 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6329 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6330 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6331 [(set (match_dup 3)
6332 (truncate:SI
6333 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6334 (sign_extend:DI (match_dup 2)))
6335 (const_int 32))))
6336 (set (match_dup 4)
6337 (mult:SI (match_dup 1)
6338 (match_dup 2)))]
6339 "
6340{
6341 int endian = (WORDS_BIG_ENDIAN == 0);
6342 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6343 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6344}")
6345
f192bf8b
DE		 6346(define_expand "umulsidi3"
6347 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6348 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6349 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6350 "TARGET_POWERPC && ! TARGET_POWERPC64"
6351 "
6352{
6353 if (TARGET_POWER)
6354 {
6355 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6356 DONE;
6357 }
6358}")
6359
6360(define_insn "umulsidi3_mq"
6361 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6362 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6363 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6364 (clobber (match_scratch:SI 3 "=q"))]
6365 "TARGET_POWERPC && TARGET_POWER"
6366 "*
6367{
6368 return (WORDS_BIG_ENDIAN)
6369 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6370 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6371}"
6372 [(set_attr "type" "imul")
6373 (set_attr "length" "8")])
6374
6375(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 6376 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6377 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6378 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6379 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 6380 "*
6381{
6382 return (WORDS_BIG_ENDIAN)
6383 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6384 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6385}"
6386 [(set_attr "type" "imul")
6387 (set_attr "length" "8")])
6388
ebedb4dd
MM		 6389(define_split
6390 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6391 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6392 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6393 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6394 [(set (match_dup 3)
6395 (truncate:SI
6396 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6397 (zero_extend:DI (match_dup 2)))
6398 (const_int 32))))
6399 (set (match_dup 4)
6400 (mult:SI (match_dup 1)
6401 (match_dup 2)))]
6402 "
6403{
6404 int endian = (WORDS_BIG_ENDIAN == 0);
6405 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6406 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6407}")
6408
8ffd9c51
RK		 6409(define_expand "smulsi3_highpart"
6410 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6411 (truncate:SI
6412 (lshiftrt:DI (mult:DI (sign_extend:DI
e42ac3de 6413 (match_operand:SI 1 "gpc_reg_operand" ""))
8ffd9c51 6414 (sign_extend:DI
e42ac3de 6415 (match_operand:SI 2 "gpc_reg_operand" "")))
8ffd9c51
RK		 6416 (const_int 32))))]
6417 ""
6418 "
6419{
6420 if (! TARGET_POWER && ! TARGET_POWERPC)
6421 {
39403d82
DE		 6422 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6423 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6424 emit_insn (gen_mulh_call ());
39403d82 6425 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 6426 DONE;
6427 }
6428 else if (TARGET_POWER)
6429 {
6430 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6431 DONE;
6432 }
6433}")
deb9225a 6434
8ffd9c51
RK		 6435(define_insn "smulsi3_highpart_mq"
6436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6437 (truncate:SI
fada905b
MM		 6438 (lshiftrt:DI (mult:DI (sign_extend:DI
6439 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6440 (sign_extend:DI
6441 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 6442 (const_int 32))))
6443 (clobber (match_scratch:SI 3 "=q"))]
6444 "TARGET_POWER"
6445 "mul %0,%1,%2"
6446 [(set_attr "type" "imul")])
deb9225a 6447
f192bf8b 6448(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 6449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6450 (truncate:SI
fada905b
MM		 6451 (lshiftrt:DI (mult:DI (sign_extend:DI
6452 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6453 (sign_extend:DI
6454 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 6455 (const_int 32))))]
f192bf8b 6456 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 6457 "mulhw %0,%1,%2"
6458 [(set_attr "type" "imul")])
deb9225a 6459
f192bf8b
DE		 6460(define_expand "umulsi3_highpart"
6461 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6462 (truncate:SI
6463 (lshiftrt:DI (mult:DI (zero_extend:DI
6464 (match_operand:SI 1 "gpc_reg_operand" ""))
6465 (zero_extend:DI
6466 (match_operand:SI 2 "gpc_reg_operand" "")))
6467 (const_int 32))))]
6468 "TARGET_POWERPC"
6469 "
6470{
6471 if (TARGET_POWER)
6472 {
6473 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6474 DONE;
6475 }
6476}")
6477
6478(define_insn "umulsi3_highpart_mq"
6479 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6480 (truncate:SI
6481 (lshiftrt:DI (mult:DI (zero_extend:DI
6482 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6483 (zero_extend:DI
6484 (match_operand:SI 2 "gpc_reg_operand" "r")))
6485 (const_int 32))))
6486 (clobber (match_scratch:SI 3 "=q"))]
6487 "TARGET_POWERPC && TARGET_POWER"
6488 "mulhwu %0,%1,%2"
6489 [(set_attr "type" "imul")])
6490
6491(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 6492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6493 (truncate:SI
6494 (lshiftrt:DI (mult:DI (zero_extend:DI
6495 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6496 (zero_extend:DI
6497 (match_operand:SI 2 "gpc_reg_operand" "r")))
6498 (const_int 32))))]
f192bf8b 6499 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 6500 "mulhwu %0,%1,%2"
6501 [(set_attr "type" "imul")])
6502
6503;; If operands 0 and 2 are in the same register, we have a problem. But
6504;; operands 0 and 1 (the usual case) can be in the same register. That's
6505;; why we have the strange constraints below.
6506(define_insn "ashldi3_power"
6507 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6508 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6509 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6510 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6511 "TARGET_POWER"
6512 "@
6513 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6514 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6515 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6516 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6517 [(set_attr "length" "8")])
6518
6519(define_insn "lshrdi3_power"
47ad8c61 6520 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 6521 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6522 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6523 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6524 "TARGET_POWER"
6525 "@
47ad8c61 6526 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 6527 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6528 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6529 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6530 [(set_attr "length" "8")])
6531
6532;; Shift by a variable amount is too complex to be worth open-coding. We
6533;; just handle shifts by constants.
6534(define_insn "ashrdi3_power"
7093ddee 6535 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 6536 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6537 (match_operand:SI 2 "const_int_operand" "M,i")))
6538 (clobber (match_scratch:SI 3 "=X,q"))]
6539 "TARGET_POWER"
6540 "@
6541 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6542 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
44cd321e
PS		 6543 [(set_attr "type" "shift")
6544 (set_attr "length" "8")])
4aa74a4f
FS		 6545
6546(define_insn "ashrdi3_no_power"
6547 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6548 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6549 (match_operand:SI 2 "const_int_operand" "M,i")))]
97727e85 6550 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
4aa74a4f
FS		 6551 "@
6552 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6553 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
943c15ed
DE		 6554 [(set_attr "type" "two,three")
6555 (set_attr "length" "8,12")])
683bdff7
FJ		 6556
6557(define_insn "*ashrdisi3_noppc64"
6558 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 6559 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
683bdff7
FJ		 6560 (const_int 32)) 4))]
6561 "TARGET_32BIT && !TARGET_POWERPC64"
6562 "*
6563{
6564 if (REGNO (operands[0]) == REGNO (operands[1]))
6565 return \"\";
6566 else
6567 return \"mr %0,%1\";
6568}"
6ae08853 6569 [(set_attr "length" "4")])
683bdff7 6570
266eb58a
DE		 6571\f
6572;; PowerPC64 DImode operations.
6573
ea112fc4 6574(define_insn_and_split "absdi2"
266eb58a 6575 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6576 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 6577 (clobber (match_scratch:DI 2 "=&r,&r"))]
6578 "TARGET_POWERPC64"
ea112fc4
DE		 6579 "#"
6580 "&& reload_completed"
a260abc9 6581 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6582 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 6583 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 6584 "")
6585
ea112fc4 6586(define_insn_and_split "*nabsdi2"
266eb58a 6587 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6588 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 6589 (clobber (match_scratch:DI 2 "=&r,&r"))]
6590 "TARGET_POWERPC64"
ea112fc4
DE		 6591 "#"
6592 "&& reload_completed"
a260abc9 6593 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6594 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 6595 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 6596 "")
6597
266eb58a 6598(define_insn "muldi3"
c9692532
DE		 6599 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6600 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6601 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
266eb58a 6602 "TARGET_POWERPC64"
c9692532
DE		 6603 "@
6604 mulld %0,%1,%2
6605 mulli %0,%1,%2"
6606 [(set (attr "type")
6607 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6608 (const_string "imul3")
6609 (match_operand:SI 2 "short_cint_operand" "")
6610 (const_string "imul2")]
6611 (const_string "lmul")))])
266eb58a 6612
9259f3b0
DE		 6613(define_insn "*muldi3_internal1"
6614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6615 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6616 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6617 (const_int 0)))
6618 (clobber (match_scratch:DI 3 "=r,r"))]
6619 "TARGET_POWERPC64"
6620 "@
6621 mulld. %3,%1,%2
6622 #"
6623 [(set_attr "type" "lmul_compare")
6624 (set_attr "length" "4,8")])
6625
6626(define_split
6627 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6628 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6629 (match_operand:DI 2 "gpc_reg_operand" ""))
6630 (const_int 0)))
6631 (clobber (match_scratch:DI 3 ""))]
6632 "TARGET_POWERPC64 && reload_completed"
6633 [(set (match_dup 3)
6634 (mult:DI (match_dup 1) (match_dup 2)))
6635 (set (match_dup 0)
6636 (compare:CC (match_dup 3)
6637 (const_int 0)))]
6638 "")
6639
6640(define_insn "*muldi3_internal2"
6641 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6642 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6643 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6644 (const_int 0)))
6645 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6646 (mult:DI (match_dup 1) (match_dup 2)))]
6647 "TARGET_POWERPC64"
6648 "@
6649 mulld. %0,%1,%2
6650 #"
6651 [(set_attr "type" "lmul_compare")
6652 (set_attr "length" "4,8")])
6653
6654(define_split
6655 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6656 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6657 (match_operand:DI 2 "gpc_reg_operand" ""))
6658 (const_int 0)))
6659 (set (match_operand:DI 0 "gpc_reg_operand" "")
6660 (mult:DI (match_dup 1) (match_dup 2)))]
6661 "TARGET_POWERPC64 && reload_completed"
6662 [(set (match_dup 0)
6663 (mult:DI (match_dup 1) (match_dup 2)))
6664 (set (match_dup 3)
6665 (compare:CC (match_dup 0)
6666 (const_int 0)))]
6667 "")
6668
266eb58a
DE		 6669(define_insn "smuldi3_highpart"
6670 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6671 (truncate:DI
6672 (lshiftrt:TI (mult:TI (sign_extend:TI
6673 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6674 (sign_extend:TI
6675 (match_operand:DI 2 "gpc_reg_operand" "r")))
6676 (const_int 64))))]
6677 "TARGET_POWERPC64"
6678 "mulhd %0,%1,%2"
3cb999d8 6679 [(set_attr "type" "lmul")])
266eb58a
DE		 6680
6681(define_insn "umuldi3_highpart"
6682 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6683 (truncate:DI
6684 (lshiftrt:TI (mult:TI (zero_extend:TI
6685 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6686 (zero_extend:TI
6687 (match_operand:DI 2 "gpc_reg_operand" "r")))
6688 (const_int 64))))]
6689 "TARGET_POWERPC64"
6690 "mulhdu %0,%1,%2"
3cb999d8 6691 [(set_attr "type" "lmul")])
266eb58a 6692
266eb58a 6693(define_insn "rotldi3"
44cd321e
PS		 6694 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6695 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6696 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 6697 "TARGET_POWERPC64"
44cd321e
PS		 6698 "@
6699 rldcl %0,%1,%2,0
6700 rldicl %0,%1,%H2,0"
6701 [(set_attr "type" "var_shift_rotate,integer")])
266eb58a 6702
a260abc9 6703(define_insn "*rotldi3_internal2"
44cd321e
PS		 6704 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6705 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6706 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6707 (const_int 0)))
44cd321e 6708 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6709 "TARGET_64BIT"
9ebbca7d 6710 "@
44cd321e
PS		 6711 rldcl. %3,%1,%2,0
6712 rldicl. %3,%1,%H2,0
6713 #
9ebbca7d 6714 #"
44cd321e
PS		 6715 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6716 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6717
6718(define_split
6719 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6720 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6721 (match_operand:DI 2 "reg_or_cint_operand" ""))
6722 (const_int 0)))
6723 (clobber (match_scratch:DI 3 ""))]
6724 "TARGET_POWERPC64 && reload_completed"
6725 [(set (match_dup 3)
6726 (rotate:DI (match_dup 1) (match_dup 2)))
6727 (set (match_dup 0)
6728 (compare:CC (match_dup 3)
6729 (const_int 0)))]
6730 "")
266eb58a 6731
a260abc9 6732(define_insn "*rotldi3_internal3"
44cd321e
PS		 6733 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6734 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6735 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6736 (const_int 0)))
44cd321e 6737 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 6738 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 6739 "TARGET_64BIT"
9ebbca7d 6740 "@
44cd321e
PS		 6741 rldcl. %0,%1,%2,0
6742 rldicl. %0,%1,%H2,0
6743 #
9ebbca7d 6744 #"
44cd321e
PS		 6745 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6746 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6747
6748(define_split
6749 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6750 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6751 (match_operand:DI 2 "reg_or_cint_operand" ""))
6752 (const_int 0)))
6753 (set (match_operand:DI 0 "gpc_reg_operand" "")
6754 (rotate:DI (match_dup 1) (match_dup 2)))]
6755 "TARGET_POWERPC64 && reload_completed"
6756 [(set (match_dup 0)
6757 (rotate:DI (match_dup 1) (match_dup 2)))
6758 (set (match_dup 3)
6759 (compare:CC (match_dup 0)
6760 (const_int 0)))]
6761 "")
266eb58a 6762
a260abc9 6763(define_insn "*rotldi3_internal4"
44cd321e
PS		 6764 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6765 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6766 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6767 (match_operand:DI 3 "mask64_operand" "n,n")))]
a260abc9 6768 "TARGET_POWERPC64"
44cd321e
PS		 6769 "@
6770 rldc%B3 %0,%1,%2,%S3
6771 rldic%B3 %0,%1,%H2,%S3"
6772 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6773
6774(define_insn "*rotldi3_internal5"
44cd321e 6775 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6776 (compare:CC (and:DI
44cd321e
PS		 6777 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6778 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6779 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6780 (const_int 0)))
44cd321e 6781 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
683bdff7 6782 "TARGET_64BIT"
9ebbca7d 6783 "@
44cd321e
PS		 6784 rldc%B3. %4,%1,%2,%S3
6785 rldic%B3. %4,%1,%H2,%S3
6786 #
9ebbca7d 6787 #"
44cd321e
PS		 6788 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6789 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6790
6791(define_split
6792 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6793 (compare:CC (and:DI
6794 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6795 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6796 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6797 (const_int 0)))
6798 (clobber (match_scratch:DI 4 ""))]
6799 "TARGET_POWERPC64 && reload_completed"
6800 [(set (match_dup 4)
6801 (and:DI (rotate:DI (match_dup 1)
6802 (match_dup 2))
6803 (match_dup 3)))
6804 (set (match_dup 0)
6805 (compare:CC (match_dup 4)
6806 (const_int 0)))]
6807 "")
a260abc9
DE		 6808
6809(define_insn "*rotldi3_internal6"
44cd321e 6810 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6811 (compare:CC (and:DI
44cd321e
PS		 6812 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6813 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6814 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6815 (const_int 0)))
44cd321e 6816 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6817 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6818 "TARGET_64BIT"
9ebbca7d 6819 "@
44cd321e
PS		 6820 rldc%B3. %0,%1,%2,%S3
6821 rldic%B3. %0,%1,%H2,%S3
6822 #
9ebbca7d 6823 #"
44cd321e
PS		 6824 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6825 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6826
6827(define_split
6828 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6829 (compare:CC (and:DI
6830 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6831 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6832 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6833 (const_int 0)))
6834 (set (match_operand:DI 0 "gpc_reg_operand" "")
6835 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6836 "TARGET_POWERPC64 && reload_completed"
6837 [(set (match_dup 0)
6838 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6839 (set (match_dup 4)
6840 (compare:CC (match_dup 0)
6841 (const_int 0)))]
6842 "")
a260abc9
DE		 6843
6844(define_insn "*rotldi3_internal7"
44cd321e 6845 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6846 (zero_extend:DI
6847 (subreg:QI
44cd321e
PS		 6848 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6849 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6850 "TARGET_POWERPC64"
44cd321e
PS		 6851 "@
6852 rldcl %0,%1,%2,56
6853 rldicl %0,%1,%H2,56"
6854 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6855
6856(define_insn "*rotldi3_internal8"
44cd321e 6857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6858 (compare:CC (zero_extend:DI
6859 (subreg:QI
44cd321e
PS		 6860 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6861 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6862 (const_int 0)))
44cd321e 6863 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6864 "TARGET_64BIT"
9ebbca7d 6865 "@
44cd321e
PS		 6866 rldcl. %3,%1,%2,56
6867 rldicl. %3,%1,%H2,56
6868 #
9ebbca7d 6869 #"
44cd321e
PS		 6870 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6871 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6872
6873(define_split
6874 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6875 (compare:CC (zero_extend:DI
6876 (subreg:QI
6877 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6878 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6879 (const_int 0)))
6880 (clobber (match_scratch:DI 3 ""))]
6881 "TARGET_POWERPC64 && reload_completed"
6882 [(set (match_dup 3)
6883 (zero_extend:DI (subreg:QI
6884 (rotate:DI (match_dup 1)
6885 (match_dup 2)) 0)))
6886 (set (match_dup 0)
6887 (compare:CC (match_dup 3)
6888 (const_int 0)))]
6889 "")
a260abc9
DE		 6890
6891(define_insn "*rotldi3_internal9"
44cd321e 6892 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6893 (compare:CC (zero_extend:DI
6894 (subreg:QI
44cd321e
PS		 6895 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6896 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6897 (const_int 0)))
44cd321e 6898 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6899 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6900 "TARGET_64BIT"
9ebbca7d 6901 "@
44cd321e
PS		 6902 rldcl. %0,%1,%2,56
6903 rldicl. %0,%1,%H2,56
6904 #
9ebbca7d 6905 #"
44cd321e
PS		 6906 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6907 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6908
6909(define_split
6910 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6911 (compare:CC (zero_extend:DI
6912 (subreg:QI
6913 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6914 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6915 (const_int 0)))
6916 (set (match_operand:DI 0 "gpc_reg_operand" "")
6917 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6918 "TARGET_POWERPC64 && reload_completed"
6919 [(set (match_dup 0)
6920 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6921 (set (match_dup 3)
6922 (compare:CC (match_dup 0)
6923 (const_int 0)))]
6924 "")
a260abc9
DE		 6925
6926(define_insn "*rotldi3_internal10"
44cd321e 6927 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6928 (zero_extend:DI
6929 (subreg:HI
44cd321e
PS		 6930 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6931 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6932 "TARGET_POWERPC64"
44cd321e
PS		 6933 "@
6934 rldcl %0,%1,%2,48
6935 rldicl %0,%1,%H2,48"
6936 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6937
6938(define_insn "*rotldi3_internal11"
44cd321e 6939 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6940 (compare:CC (zero_extend:DI
6941 (subreg:HI
44cd321e
PS		 6942 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6943 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6944 (const_int 0)))
44cd321e 6945 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6946 "TARGET_64BIT"
9ebbca7d 6947 "@
44cd321e
PS		 6948 rldcl. %3,%1,%2,48
6949 rldicl. %3,%1,%H2,48
6950 #
9ebbca7d 6951 #"
44cd321e
PS		 6952 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6953 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6954
6955(define_split
6956 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6957 (compare:CC (zero_extend:DI
6958 (subreg:HI
6959 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6960 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6961 (const_int 0)))
6962 (clobber (match_scratch:DI 3 ""))]
6963 "TARGET_POWERPC64 && reload_completed"
6964 [(set (match_dup 3)
6965 (zero_extend:DI (subreg:HI
6966 (rotate:DI (match_dup 1)
6967 (match_dup 2)) 0)))
6968 (set (match_dup 0)
6969 (compare:CC (match_dup 3)
6970 (const_int 0)))]
6971 "")
a260abc9
DE		 6972
6973(define_insn "*rotldi3_internal12"
44cd321e 6974 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6975 (compare:CC (zero_extend:DI
6976 (subreg:HI
44cd321e
PS		 6977 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6978 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6979 (const_int 0)))
44cd321e 6980 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6981 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6982 "TARGET_64BIT"
9ebbca7d 6983 "@
44cd321e
PS		 6984 rldcl. %0,%1,%2,48
6985 rldicl. %0,%1,%H2,48
6986 #
9ebbca7d 6987 #"
44cd321e
PS		 6988 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6989 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6990
6991(define_split
6992 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6993 (compare:CC (zero_extend:DI
6994 (subreg:HI
6995 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6996 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6997 (const_int 0)))
6998 (set (match_operand:DI 0 "gpc_reg_operand" "")
6999 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7000 "TARGET_POWERPC64 && reload_completed"
7001 [(set (match_dup 0)
7002 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7003 (set (match_dup 3)
7004 (compare:CC (match_dup 0)
7005 (const_int 0)))]
7006 "")
a260abc9
DE		 7007
7008(define_insn "*rotldi3_internal13"
44cd321e 7009 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 7010 (zero_extend:DI
7011 (subreg:SI
44cd321e
PS		 7012 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7013 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 7014 "TARGET_POWERPC64"
44cd321e
PS		 7015 "@
7016 rldcl %0,%1,%2,32
7017 rldicl %0,%1,%H2,32"
7018 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 7019
7020(define_insn "*rotldi3_internal14"
44cd321e 7021 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7022 (compare:CC (zero_extend:DI
7023 (subreg:SI
44cd321e
PS		 7024 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7025 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7026 (const_int 0)))
44cd321e 7027 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7028 "TARGET_64BIT"
9ebbca7d 7029 "@
44cd321e
PS		 7030 rldcl. %3,%1,%2,32
7031 rldicl. %3,%1,%H2,32
7032 #
9ebbca7d 7033 #"
44cd321e
PS		 7034 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7035 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7036
7037(define_split
7038 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7039 (compare:CC (zero_extend:DI
7040 (subreg:SI
7041 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7042 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7043 (const_int 0)))
7044 (clobber (match_scratch:DI 3 ""))]
7045 "TARGET_POWERPC64 && reload_completed"
7046 [(set (match_dup 3)
7047 (zero_extend:DI (subreg:SI
7048 (rotate:DI (match_dup 1)
7049 (match_dup 2)) 0)))
7050 (set (match_dup 0)
7051 (compare:CC (match_dup 3)
7052 (const_int 0)))]
7053 "")
a260abc9
DE		 7054
7055(define_insn "*rotldi3_internal15"
44cd321e 7056 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7057 (compare:CC (zero_extend:DI
7058 (subreg:SI
44cd321e
PS		 7059 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7060 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7061 (const_int 0)))
44cd321e 7062 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7063 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7064 "TARGET_64BIT"
9ebbca7d 7065 "@
44cd321e
PS		 7066 rldcl. %0,%1,%2,32
7067 rldicl. %0,%1,%H2,32
7068 #
9ebbca7d 7069 #"
44cd321e
PS		 7070 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7071 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7072
7073(define_split
7074 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7075 (compare:CC (zero_extend:DI
7076 (subreg:SI
7077 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7078 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7079 (const_int 0)))
7080 (set (match_operand:DI 0 "gpc_reg_operand" "")
7081 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7082 "TARGET_POWERPC64 && reload_completed"
7083 [(set (match_dup 0)
7084 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7085 (set (match_dup 3)
7086 (compare:CC (match_dup 0)
7087 (const_int 0)))]
7088 "")
a260abc9 7089
266eb58a
DE		 7090(define_expand "ashldi3"
7091 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7092 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7093 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7094 "TARGET_POWERPC64 || TARGET_POWER"
7095 "
7096{
7097 if (TARGET_POWERPC64)
7098 ;
7099 else if (TARGET_POWER)
7100 {
7101 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7102 DONE;
7103 }
7104 else
7105 FAIL;
7106}")
7107
e2c953b6 7108(define_insn "*ashldi3_internal1"
44cd321e
PS		 7109 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7110 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7111 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7112 "TARGET_POWERPC64"
44cd321e
PS		 7113 "@
7114 sld %0,%1,%2
7115 sldi %0,%1,%H2"
7116 [(set_attr "type" "var_shift_rotate,shift")])
6ae08853 7117
e2c953b6 7118(define_insn "*ashldi3_internal2"
44cd321e
PS		 7119 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7120 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7121 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7122 (const_int 0)))
44cd321e 7123 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7124 "TARGET_64BIT"
9ebbca7d 7125 "@
44cd321e
PS		 7126 sld. %3,%1,%2
7127 sldi. %3,%1,%H2
7128 #
9ebbca7d 7129 #"
44cd321e
PS		 7130 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7131 (set_attr "length" "4,4,8,8")])
6ae08853 7132
9ebbca7d
GK		 7133(define_split
7134 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7135 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7136 (match_operand:SI 2 "reg_or_cint_operand" ""))
7137 (const_int 0)))
7138 (clobber (match_scratch:DI 3 ""))]
7139 "TARGET_POWERPC64 && reload_completed"
7140 [(set (match_dup 3)
7141 (ashift:DI (match_dup 1) (match_dup 2)))
7142 (set (match_dup 0)
7143 (compare:CC (match_dup 3)
7144 (const_int 0)))]
7145 "")
7146
e2c953b6 7147(define_insn "*ashldi3_internal3"
44cd321e
PS		 7148 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7149 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7150 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7151 (const_int 0)))
44cd321e 7152 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7153 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 7154 "TARGET_64BIT"
9ebbca7d 7155 "@
44cd321e
PS		 7156 sld. %0,%1,%2
7157 sldi. %0,%1,%H2
7158 #
9ebbca7d 7159 #"
44cd321e
PS		 7160 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7161 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7162
7163(define_split
7164 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7165 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7166 (match_operand:SI 2 "reg_or_cint_operand" ""))
7167 (const_int 0)))
7168 (set (match_operand:DI 0 "gpc_reg_operand" "")
7169 (ashift:DI (match_dup 1) (match_dup 2)))]
7170 "TARGET_POWERPC64 && reload_completed"
7171 [(set (match_dup 0)
7172 (ashift:DI (match_dup 1) (match_dup 2)))
7173 (set (match_dup 3)
7174 (compare:CC (match_dup 0)
7175 (const_int 0)))]
7176 "")
266eb58a 7177
e2c953b6 7178(define_insn "*ashldi3_internal4"
3cb999d8
DE		 7179 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7180 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7181 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 7182 (match_operand:DI 3 "const_int_operand" "n")))]
7183 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 7184 "rldic %0,%1,%H2,%W3")
3cb999d8 7185
e2c953b6 7186(define_insn "ashldi3_internal5"
9ebbca7d 7187 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 7188 (compare:CC
9ebbca7d
GK		 7189 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7190 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7191 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7192 (const_int 0)))
9ebbca7d 7193 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7194 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7195 "@
e2c953b6 7196 rldic. %4,%1,%H2,%W3
9ebbca7d 7197 #"
9c6fdb46 7198 [(set_attr "type" "compare")
9ebbca7d
GK		 7199 (set_attr "length" "4,8")])
7200
7201(define_split
7202 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7203 (compare:CC
7204 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7205 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7206 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7207 (const_int 0)))
7208 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 7209 "TARGET_POWERPC64 && reload_completed
7210 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 7211 [(set (match_dup 4)
7212 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 7213 (match_dup 3)))
9ebbca7d
GK		 7214 (set (match_dup 0)
7215 (compare:CC (match_dup 4)
7216 (const_int 0)))]
7217 "")
3cb999d8 7218
e2c953b6 7219(define_insn "*ashldi3_internal6"
9ebbca7d 7220 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 7221 (compare:CC
9ebbca7d
GK		 7222 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7223 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7224 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7225 (const_int 0)))
9ebbca7d 7226 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 7227 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7228 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7229 "@
e2c953b6 7230 rldic. %0,%1,%H2,%W3
9ebbca7d 7231 #"
9c6fdb46 7232 [(set_attr "type" "compare")
9ebbca7d
GK		 7233 (set_attr "length" "4,8")])
7234
7235(define_split
7236 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7237 (compare:CC
7238 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7239 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7240 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7241 (const_int 0)))
7242 (set (match_operand:DI 0 "gpc_reg_operand" "")
7243 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 7244 "TARGET_POWERPC64 && reload_completed
7245 && includes_rldic_lshift_p (operands[2], operands[3])"
7246 [(set (match_dup 0)
7247 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7248 (match_dup 3)))
7249 (set (match_dup 4)
7250 (compare:CC (match_dup 0)
7251 (const_int 0)))]
7252 "")
7253
7254(define_insn "*ashldi3_internal7"
7255 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7256 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7257 (match_operand:SI 2 "const_int_operand" "i"))
1990cd79 7258 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 7259 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7260 "rldicr %0,%1,%H2,%S3")
7261
7262(define_insn "ashldi3_internal8"
7263 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7264 (compare:CC
7265 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7266 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7267 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7268 (const_int 0)))
7269 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7270 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7271 "@
7272 rldicr. %4,%1,%H2,%S3
7273 #"
9c6fdb46 7274 [(set_attr "type" "compare")
c5059423
AM		 7275 (set_attr "length" "4,8")])
7276
7277(define_split
7278 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7279 (compare:CC
7280 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7281 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7282 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7283 (const_int 0)))
7284 (clobber (match_scratch:DI 4 ""))]
7285 "TARGET_POWERPC64 && reload_completed
7286 && includes_rldicr_lshift_p (operands[2], operands[3])"
7287 [(set (match_dup 4)
7288 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7289 (match_dup 3)))
7290 (set (match_dup 0)
7291 (compare:CC (match_dup 4)
7292 (const_int 0)))]
7293 "")
7294
7295(define_insn "*ashldi3_internal9"
7296 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7297 (compare:CC
7298 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7299 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7300 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7301 (const_int 0)))
7302 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7303 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7304 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7305 "@
7306 rldicr. %0,%1,%H2,%S3
7307 #"
9c6fdb46 7308 [(set_attr "type" "compare")
c5059423
AM		 7309 (set_attr "length" "4,8")])
7310
7311(define_split
7312 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7313 (compare:CC
7314 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7315 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7316 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7317 (const_int 0)))
7318 (set (match_operand:DI 0 "gpc_reg_operand" "")
7319 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7320 "TARGET_POWERPC64 && reload_completed
7321 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 7322 [(set (match_dup 0)
e2c953b6
DE		 7323 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7324 (match_dup 3)))
9ebbca7d
GK		 7325 (set (match_dup 4)
7326 (compare:CC (match_dup 0)
7327 (const_int 0)))]
7328 "")
7329
7330(define_expand "lshrdi3"
266eb58a
DE		 7331 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7332 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7333 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7334 "TARGET_POWERPC64 || TARGET_POWER"
7335 "
7336{
7337 if (TARGET_POWERPC64)
7338 ;
7339 else if (TARGET_POWER)
7340 {
7341 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7342 DONE;
7343 }
7344 else
7345 FAIL;
7346}")
7347
e2c953b6 7348(define_insn "*lshrdi3_internal1"
44cd321e
PS		 7349 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7350 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7351 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7352 "TARGET_POWERPC64"
44cd321e
PS		 7353 "@
7354 srd %0,%1,%2
7355 srdi %0,%1,%H2"
7356 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7357
e2c953b6 7358(define_insn "*lshrdi3_internal2"
44cd321e
PS		 7359 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7360 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7361 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
29ae5b89 7362 (const_int 0)))
44cd321e 7363 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7364 "TARGET_64BIT "
9ebbca7d 7365 "@
44cd321e
PS		 7366 srd. %3,%1,%2
7367 srdi. %3,%1,%H2
7368 #
9ebbca7d 7369 #"
44cd321e
PS		 7370 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7371 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7372
7373(define_split
7374 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7375 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7376 (match_operand:SI 2 "reg_or_cint_operand" ""))
7377 (const_int 0)))
7378 (clobber (match_scratch:DI 3 ""))]
7379 "TARGET_POWERPC64 && reload_completed"
7380 [(set (match_dup 3)
7381 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7382 (set (match_dup 0)
7383 (compare:CC (match_dup 3)
7384 (const_int 0)))]
7385 "")
266eb58a 7386
e2c953b6 7387(define_insn "*lshrdi3_internal3"
44cd321e
PS		 7388 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7389 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7390 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7391 (const_int 0)))
44cd321e 7392 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 7393 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7394 "TARGET_64BIT"
9ebbca7d 7395 "@
44cd321e
PS		 7396 srd. %0,%1,%2
7397 srdi. %0,%1,%H2
7398 #
9ebbca7d 7399 #"
44cd321e
PS		 7400 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7401 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7402
7403(define_split
7404 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7405 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7406 (match_operand:SI 2 "reg_or_cint_operand" ""))
7407 (const_int 0)))
7408 (set (match_operand:DI 0 "gpc_reg_operand" "")
7409 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7410 "TARGET_POWERPC64 && reload_completed"
7411 [(set (match_dup 0)
7412 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7413 (set (match_dup 3)
7414 (compare:CC (match_dup 0)
7415 (const_int 0)))]
7416 "")
266eb58a
DE		 7417
7418(define_expand "ashrdi3"
7419 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7420 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7421 (match_operand:SI 2 "reg_or_cint_operand" "")))]
97727e85 7422 "WORDS_BIG_ENDIAN"
266eb58a
DE		 7423 "
7424{
7425 if (TARGET_POWERPC64)
7426 ;
7427 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7428 {
7429 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7430 DONE;
7431 }
97727e85
AH		 7432 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7433 && WORDS_BIG_ENDIAN)
4aa74a4f
FS		 7434 {
7435 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7436 DONE;
7437 }
266eb58a
DE		 7438 else
7439 FAIL;
7440}")
7441
e2c953b6 7442(define_insn "*ashrdi3_internal1"
44cd321e
PS		 7443 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7444 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7445 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7446 "TARGET_POWERPC64"
44cd321e
PS		 7447 "@
7448 srad %0,%1,%2
7449 sradi %0,%1,%H2"
7450 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7451
e2c953b6 7452(define_insn "*ashrdi3_internal2"
44cd321e
PS		 7453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7454 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7455 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7456 (const_int 0)))
44cd321e 7457 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7458 "TARGET_64BIT"
9ebbca7d 7459 "@
44cd321e
PS		 7460 srad. %3,%1,%2
7461 sradi. %3,%1,%H2
7462 #
9ebbca7d 7463 #"
44cd321e
PS		 7464 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7465 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7466
7467(define_split
7468 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7469 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7470 (match_operand:SI 2 "reg_or_cint_operand" ""))
7471 (const_int 0)))
7472 (clobber (match_scratch:DI 3 ""))]
7473 "TARGET_POWERPC64 && reload_completed"
7474 [(set (match_dup 3)
7475 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7476 (set (match_dup 0)
7477 (compare:CC (match_dup 3)
7478 (const_int 0)))]
7479 "")
266eb58a 7480
e2c953b6 7481(define_insn "*ashrdi3_internal3"
44cd321e
PS		 7482 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7483 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7484 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7485 (const_int 0)))
44cd321e 7486 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7487 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7488 "TARGET_64BIT"
9ebbca7d 7489 "@
44cd321e
PS		 7490 srad. %0,%1,%2
7491 sradi. %0,%1,%H2
7492 #
9ebbca7d 7493 #"
44cd321e
PS		 7494 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7495 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7496
7497(define_split
7498 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7499 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7500 (match_operand:SI 2 "reg_or_cint_operand" ""))
7501 (const_int 0)))
7502 (set (match_operand:DI 0 "gpc_reg_operand" "")
7503 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7504 "TARGET_POWERPC64 && reload_completed"
7505 [(set (match_dup 0)
7506 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7507 (set (match_dup 3)
7508 (compare:CC (match_dup 0)
7509 (const_int 0)))]
7510 "")
815cdc52 7511
29ae5b89 7512(define_insn "anddi3"
e1e2e653
NS		 7513 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7514 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7515 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7516 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6ffc8580 7517 "TARGET_POWERPC64"
266eb58a
DE		 7518 "@
7519 and %0,%1,%2
29ae5b89 7520 rldic%B2 %0,%1,0,%S2
e1e2e653 7521 rlwinm %0,%1,0,%m2,%M2
29ae5b89 7522 andi. %0,%1,%b2
0ba1b2ff
AM		 7523 andis. %0,%1,%u2
7524 #"
e1e2e653
NS		 7525 [(set_attr "type" "*,*,*,compare,compare,*")
7526 (set_attr "length" "4,4,4,4,4,8")])
0ba1b2ff
AM		 7527
7528(define_split
7529 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7530 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7531 (match_operand:DI 2 "mask64_2_operand" "")))
7532 (clobber (match_scratch:CC 3 ""))]
7533 "TARGET_POWERPC64
7534 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7535 && !mask_operand (operands[2], DImode)
7536 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7537 [(set (match_dup 0)
7538 (and:DI (rotate:DI (match_dup 1)
7539 (match_dup 4))
7540 (match_dup 5)))
7541 (set (match_dup 0)
7542 (and:DI (rotate:DI (match_dup 0)
7543 (match_dup 6))
7544 (match_dup 7)))]
0ba1b2ff
AM		 7545{
7546 build_mask64_2_operands (operands[2], &operands[4]);
e1e2e653 7547})
266eb58a 7548
a260abc9 7549(define_insn "*anddi3_internal2"
1990cd79
AM		 7550 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7551 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7552 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7553 (const_int 0)))
1990cd79
AM		 7554 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7555 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7556 "TARGET_64BIT"
266eb58a
DE		 7557 "@
7558 and. %3,%1,%2
6c873122 7559 rldic%B2. %3,%1,0,%S2
1990cd79 7560 rlwinm. %3,%1,0,%m2,%M2
6ffc8580
MM		 7561 andi. %3,%1,%b2
7562 andis. %3,%1,%u2
9ebbca7d
GK		 7563 #
7564 #
7565 #
0ba1b2ff
AM		 7566 #
7567 #
1990cd79 7568 #
9ebbca7d 7569 #"
44cd321e 7570 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7571 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d 7572
0ba1b2ff
AM		 7573(define_split
7574 [(set (match_operand:CC 0 "cc_reg_operand" "")
7575 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7576 (match_operand:DI 2 "mask64_2_operand" ""))
7577 (const_int 0)))
7578 (clobber (match_scratch:DI 3 ""))
7579 (clobber (match_scratch:CC 4 ""))]
1990cd79 7580 "TARGET_64BIT && reload_completed
0ba1b2ff 7581 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7582 && !mask_operand (operands[2], DImode)
7583 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7584 [(set (match_dup 3)
7585 (and:DI (rotate:DI (match_dup 1)
7586 (match_dup 5))
7587 (match_dup 6)))
7588 (parallel [(set (match_dup 0)
7589 (compare:CC (and:DI (rotate:DI (match_dup 3)
7590 (match_dup 7))
7591 (match_dup 8))
7592 (const_int 0)))
7593 (clobber (match_dup 3))])]
7594 "
7595{
7596 build_mask64_2_operands (operands[2], &operands[5]);
7597}")
7598
a260abc9 7599(define_insn "*anddi3_internal3"
1990cd79
AM		 7600 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7601 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7602 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7603 (const_int 0)))
1990cd79 7604 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7605 (and:DI (match_dup 1) (match_dup 2)))
1990cd79 7606 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7607 "TARGET_64BIT"
266eb58a
DE		 7608 "@
7609 and. %0,%1,%2
6c873122 7610 rldic%B2. %0,%1,0,%S2
1990cd79 7611 rlwinm. %0,%1,0,%m2,%M2
6ffc8580
MM		 7612 andi. %0,%1,%b2
7613 andis. %0,%1,%u2
9ebbca7d
GK		 7614 #
7615 #
7616 #
0ba1b2ff
AM		 7617 #
7618 #
1990cd79 7619 #
9ebbca7d 7620 #"
44cd321e 7621 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7622 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d
GK		 7623
7624(define_split
7625 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7626 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
1990cd79 7627 (match_operand:DI 2 "and64_2_operand" ""))
9ebbca7d
GK		 7628 (const_int 0)))
7629 (set (match_operand:DI 0 "gpc_reg_operand" "")
7630 (and:DI (match_dup 1) (match_dup 2)))
7631 (clobber (match_scratch:CC 4 ""))]
1990cd79 7632 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 7633 [(parallel [(set (match_dup 0)
7634 (and:DI (match_dup 1) (match_dup 2)))
7635 (clobber (match_dup 4))])
7636 (set (match_dup 3)
7637 (compare:CC (match_dup 0)
7638 (const_int 0)))]
7639 "")
266eb58a 7640
0ba1b2ff
AM		 7641(define_split
7642 [(set (match_operand:CC 3 "cc_reg_operand" "")
7643 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7644 (match_operand:DI 2 "mask64_2_operand" ""))
7645 (const_int 0)))
7646 (set (match_operand:DI 0 "gpc_reg_operand" "")
7647 (and:DI (match_dup 1) (match_dup 2)))
7648 (clobber (match_scratch:CC 4 ""))]
1990cd79 7649 "TARGET_64BIT && reload_completed
0ba1b2ff 7650 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7651 && !mask_operand (operands[2], DImode)
7652 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7653 [(set (match_dup 0)
7654 (and:DI (rotate:DI (match_dup 1)
7655 (match_dup 5))
7656 (match_dup 6)))
7657 (parallel [(set (match_dup 3)
7658 (compare:CC (and:DI (rotate:DI (match_dup 0)
7659 (match_dup 7))
7660 (match_dup 8))
7661 (const_int 0)))
7662 (set (match_dup 0)
7663 (and:DI (rotate:DI (match_dup 0)
7664 (match_dup 7))
7665 (match_dup 8)))])]
7666 "
7667{
7668 build_mask64_2_operands (operands[2], &operands[5]);
7669}")
7670
a260abc9 7671(define_expand "iordi3"
266eb58a 7672 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7673 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7674 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7675 "TARGET_POWERPC64"
266eb58a
DE		 7676 "
7677{
dfbdccdb 7678 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7679 {
dfbdccdb 7680 HOST_WIDE_INT value;
b3a13419
ILT		 7681 rtx tmp = ((!can_create_pseudo_p ()
7682 || rtx_equal_p (operands[0], operands[1]))
a260abc9 7683 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7684
dfbdccdb
GK		 7685 if (GET_CODE (operands[2]) == CONST_INT)
7686 {
7687 value = INTVAL (operands[2]);
7688 emit_insn (gen_iordi3 (tmp, operands[1],
7689 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7690 }
e2c953b6 7691 else
dfbdccdb
GK		 7692 {
7693 value = CONST_DOUBLE_LOW (operands[2]);
7694 emit_insn (gen_iordi3 (tmp, operands[1],
7695 immed_double_const (value
7696 & (~ (HOST_WIDE_INT) 0xffff),
7697 0, DImode)));
7698 }
e2c953b6 7699
9ebbca7d
GK		 7700 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7701 DONE;
7702 }
266eb58a
DE		 7703}")
7704
a260abc9
DE		 7705(define_expand "xordi3"
7706 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7707 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7708 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7709 "TARGET_POWERPC64"
7710 "
7711{
dfbdccdb 7712 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7713 {
dfbdccdb 7714 HOST_WIDE_INT value;
b3a13419
ILT		 7715 rtx tmp = ((!can_create_pseudo_p ()
7716 || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7717 ? operands[0] : gen_reg_rtx (DImode));
7718
dfbdccdb
GK		 7719 if (GET_CODE (operands[2]) == CONST_INT)
7720 {
7721 value = INTVAL (operands[2]);
7722 emit_insn (gen_xordi3 (tmp, operands[1],
7723 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7724 }
e2c953b6 7725 else
dfbdccdb
GK		 7726 {
7727 value = CONST_DOUBLE_LOW (operands[2]);
7728 emit_insn (gen_xordi3 (tmp, operands[1],
7729 immed_double_const (value
7730 & (~ (HOST_WIDE_INT) 0xffff),
7731 0, DImode)));
7732 }
e2c953b6 7733
9ebbca7d
GK		 7734 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7735 DONE;
7736 }
a260abc9
DE		 7737}")
7738
dfbdccdb 7739(define_insn "*booldi3_internal1"
266eb58a 7740 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7741 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7742 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7743 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7744 "TARGET_POWERPC64"
1fd4e8c1 7745 "@
dfbdccdb
GK		 7746 %q3 %0,%1,%2
7747 %q3i %0,%1,%b2
7748 %q3is %0,%1,%u2")
1fd4e8c1 7749
dfbdccdb 7750(define_insn "*booldi3_internal2"
9ebbca7d 7751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7752 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7753 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7754 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7755 (const_int 0)))
9ebbca7d 7756 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7757 "TARGET_64BIT"
9ebbca7d 7758 "@
dfbdccdb 7759 %q4. %3,%1,%2
9ebbca7d
GK		 7760 #"
7761 [(set_attr "type" "compare")
7762 (set_attr "length" "4,8")])
7763
7764(define_split
7765 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7766 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7767 [(match_operand:DI 1 "gpc_reg_operand" "")
7768 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7769 (const_int 0)))
9ebbca7d
GK		 7770 (clobber (match_scratch:DI 3 ""))]
7771 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7772 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7773 (set (match_dup 0)
7774 (compare:CC (match_dup 3)
7775 (const_int 0)))]
7776 "")
1fd4e8c1 7777
dfbdccdb 7778(define_insn "*booldi3_internal3"
9ebbca7d 7779 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7780 (compare:CC (match_operator:DI 4 "boolean_operator"
7781 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7782 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7783 (const_int 0)))
9ebbca7d 7784 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7785 (match_dup 4))]
683bdff7 7786 "TARGET_64BIT"
9ebbca7d 7787 "@
dfbdccdb 7788 %q4. %0,%1,%2
9ebbca7d
GK		 7789 #"
7790 [(set_attr "type" "compare")
7791 (set_attr "length" "4,8")])
7792
7793(define_split
e72247f4 7794 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7795 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7796 [(match_operand:DI 1 "gpc_reg_operand" "")
7797 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7798 (const_int 0)))
75540af0 7799 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7800 (match_dup 4))]
9ebbca7d 7801 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7802 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7803 (set (match_dup 3)
7804 (compare:CC (match_dup 0)
7805 (const_int 0)))]
7806 "")
1fd4e8c1 7807
6ae08853 7808;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7809;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7810
7811(define_split
7812 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7813 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7814 [(match_operand:DI 1 "gpc_reg_operand" "")
7815 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7816 "TARGET_POWERPC64"
dfbdccdb
GK		 7817 [(set (match_dup 0) (match_dup 4))
7818 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7819"
7820{
dfbdccdb 7821 rtx i3,i4;
6ae08853 7822
9ebbca7d
GK		 7823 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7824 {
7825 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7826 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7827 0, DImode);
dfbdccdb 7828 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7829 }
7830 else
7831 {
dfbdccdb 7832 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7833 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7834 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7835 }
1c563bed 7836 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7837 operands[1], i3);
1c563bed 7838 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7839 operands[0], i4);
1fd4e8c1
RK		 7840}")
7841
dfbdccdb 7842(define_insn "*boolcdi3_internal1"
9ebbca7d 7843 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7844 (match_operator:DI 3 "boolean_operator"
7845 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7846 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7847 "TARGET_POWERPC64"
1d328b19 7848 "%q3 %0,%2,%1")
a473029f 7849
dfbdccdb 7850(define_insn "*boolcdi3_internal2"
9ebbca7d 7851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7852 (compare:CC (match_operator:DI 4 "boolean_operator"
7853 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7854 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7855 (const_int 0)))
9ebbca7d 7856 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7857 "TARGET_64BIT"
9ebbca7d 7858 "@
1d328b19 7859 %q4. %3,%2,%1
9ebbca7d
GK		 7860 #"
7861 [(set_attr "type" "compare")
7862 (set_attr "length" "4,8")])
7863
7864(define_split
7865 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7866 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7867 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7868 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7869 (const_int 0)))
9ebbca7d
GK		 7870 (clobber (match_scratch:DI 3 ""))]
7871 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7872 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7873 (set (match_dup 0)
7874 (compare:CC (match_dup 3)
7875 (const_int 0)))]
7876 "")
a473029f 7877
dfbdccdb 7878(define_insn "*boolcdi3_internal3"
9ebbca7d 7879 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7880 (compare:CC (match_operator:DI 4 "boolean_operator"
7881 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7882 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7883 (const_int 0)))
9ebbca7d 7884 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7885 (match_dup 4))]
683bdff7 7886 "TARGET_64BIT"
9ebbca7d 7887 "@
1d328b19 7888 %q4. %0,%2,%1
9ebbca7d
GK		 7889 #"
7890 [(set_attr "type" "compare")
7891 (set_attr "length" "4,8")])
7892
7893(define_split
e72247f4 7894 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7895 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7896 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7897 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7898 (const_int 0)))
75540af0 7899 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7900 (match_dup 4))]
9ebbca7d 7901 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7902 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7903 (set (match_dup 3)
7904 (compare:CC (match_dup 0)
7905 (const_int 0)))]
7906 "")
266eb58a 7907
dfbdccdb 7908(define_insn "*boolccdi3_internal1"
a473029f 7909 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7910 (match_operator:DI 3 "boolean_operator"
7911 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7912 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 7913 "TARGET_POWERPC64"
dfbdccdb 7914 "%q3 %0,%1,%2")
a473029f 7915
dfbdccdb 7916(define_insn "*boolccdi3_internal2"
9ebbca7d 7917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7918 (compare:CC (match_operator:DI 4 "boolean_operator"
7919 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7920 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7921 (const_int 0)))
9ebbca7d 7922 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7923 "TARGET_64BIT"
9ebbca7d 7924 "@
dfbdccdb 7925 %q4. %3,%1,%2
9ebbca7d
GK		 7926 #"
7927 [(set_attr "type" "compare")
7928 (set_attr "length" "4,8")])
7929
7930(define_split
7931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7932 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7933 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7934 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7935 (const_int 0)))
9ebbca7d
GK		 7936 (clobber (match_scratch:DI 3 ""))]
7937 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7938 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7939 (set (match_dup 0)
7940 (compare:CC (match_dup 3)
7941 (const_int 0)))]
7942 "")
266eb58a 7943
dfbdccdb 7944(define_insn "*boolccdi3_internal3"
9ebbca7d 7945 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7946 (compare:CC (match_operator:DI 4 "boolean_operator"
7947 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7948 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7949 (const_int 0)))
9ebbca7d 7950 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7951 (match_dup 4))]
683bdff7 7952 "TARGET_64BIT"
9ebbca7d 7953 "@
dfbdccdb 7954 %q4. %0,%1,%2
9ebbca7d
GK		 7955 #"
7956 [(set_attr "type" "compare")
7957 (set_attr "length" "4,8")])
7958
7959(define_split
e72247f4 7960 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7961 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7962 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7963 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7964 (const_int 0)))
75540af0 7965 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7966 (match_dup 4))]
9ebbca7d 7967 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7968 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7969 (set (match_dup 3)
7970 (compare:CC (match_dup 0)
7971 (const_int 0)))]
7972 "")
dfbdccdb 7973\f
1fd4e8c1 7974;; Now define ways of moving data around.
4697a36c 7975
766a866c
MM		 7976;; Set up a register with a value from the GOT table
7977
7978(define_expand "movsi_got"
52d3af72 7979 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7980 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 7981 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 7982 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7983 "
7984{
38c1f2d7
MM		 7985 if (GET_CODE (operands[1]) == CONST)
7986 {
7987 rtx offset = const0_rtx;
7988 HOST_WIDE_INT value;
7989
7990 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7991 value = INTVAL (offset);
7992 if (value != 0)
7993 {
b3a13419
ILT		 7994 rtx tmp = (!can_create_pseudo_p ()
7995 ? operands[0]
7996 : gen_reg_rtx (Pmode));
38c1f2d7
MM		 7997 emit_insn (gen_movsi_got (tmp, operands[1]));
7998 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7999 DONE;
8000 }
8001 }
8002
c4c40373 8003 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 8004}")
8005
84f414bc 8006(define_insn "*movsi_got_internal"
52d3af72 8007 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 8008 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8009 (match_operand:SI 2 "gpc_reg_operand" "b")]
8010 UNSPEC_MOVSI_GOT))]
f607bc57 8011 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 8012 "{l|lwz} %0,%a1@got(%2)"
8013 [(set_attr "type" "load")])
8014
b22b9b3e
JL		 8015;; Used by sched, shorten_branches and final when the GOT pseudo reg
8016;; didn't get allocated to a hard register.
6ae08853 8017(define_split
75540af0 8018 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8019 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8020 (match_operand:SI 2 "memory_operand" "")]
8021 UNSPEC_MOVSI_GOT))]
f607bc57 8022 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 8023 && flag_pic == 1
8024 && (reload_in_progress || reload_completed)"
8025 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 8026 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8027 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 8028 "")
8029
1fd4e8c1
RK		 8030;; For SI, we special-case integers that can't be loaded in one insn. We
8031;; do the load 16-bits at a time. We could do this by loading from memory,
8032;; and this is even supposed to be faster, but it is simpler not to get
8033;; integers in the TOC.
ee890fe2
SS		 8034(define_insn "movsi_low"
8035 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 8036 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 8037 (match_operand 2 "" ""))))]
8038 "TARGET_MACHO && ! TARGET_64BIT"
8039 "{l|lwz} %0,lo16(%2)(%1)"
8040 [(set_attr "type" "load")
8041 (set_attr "length" "4")])
8042
acad7ed3 8043(define_insn "*movsi_internal1"
165a5bad 8044 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
a004eb82 8045 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
19d5775a
RK		 8046 "gpc_reg_operand (operands[0], SImode)
8047 || gpc_reg_operand (operands[1], SImode)"
1fd4e8c1 8048 "@
deb9225a 8049 mr %0,%1
b9442c72 8050 {cal|la} %0,%a1
ca7f5001
RK		 8051 {l%U1%X1|lwz%U1%X1} %0,%1
8052 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 8053 {lil|li} %0,%1
802a0058 8054 {liu|lis} %0,%v1
beaec479 8055 #
aee86b38 8056 {cal|la} %0,%a1
1fd4e8c1 8057 mf%1 %0
5c23c401 8058 mt%0 %1
e76e75bb 8059 mt%0 %1
a004eb82 8060 mt%0 %1
e34eaae5 8061 {cror 0,0,0|nop}"
02ca7595 8062 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 8063 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 8064
77fa0940
RK		 8065;; Split a load of a large constant into the appropriate two-insn
8066;; sequence.
8067
8068(define_split
8069 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8070 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 8071 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 8072 && (INTVAL (operands[1]) & 0xffff) != 0"
8073 [(set (match_dup 0)
8074 (match_dup 2))
8075 (set (match_dup 0)
8076 (ior:SI (match_dup 0)
8077 (match_dup 3)))]
8078 "
af8cb5c5
DE		 8079{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8080
8081 if (tem == operands[0])
8082 DONE;
8083 else
8084 FAIL;
77fa0940
RK		 8085}")
8086
4ae234b0 8087(define_insn "*mov<mode>_internal2"
bb84cb12 8088 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
4ae234b0 8089 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 8090 (const_int 0)))
4ae234b0
GK		 8091 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8092 ""
9ebbca7d 8093 "@
4ae234b0 8094 {cmpi|cmp<wd>i} %2,%0,0
9ebbca7d
GK		 8095 mr. %0,%1
8096 #"
bb84cb12
DE		 8097 [(set_attr "type" "cmp,compare,cmp")
8098 (set_attr "length" "4,4,8")])
8099
9ebbca7d
GK		 8100(define_split
8101 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
4ae234b0 8102 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9ebbca7d 8103 (const_int 0)))
4ae234b0
GK		 8104 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8105 "reload_completed"
9ebbca7d
GK		 8106 [(set (match_dup 0) (match_dup 1))
8107 (set (match_dup 2)
8108 (compare:CC (match_dup 0)
8109 (const_int 0)))]
8110 "")
bb84cb12 8111\f
e34eaae5 8112(define_insn "*movhi_internal"
fb81d7ce
RK		 8113 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8114 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8115 "gpc_reg_operand (operands[0], HImode)
8116 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 8117 "@
deb9225a 8118 mr %0,%1
1fd4e8c1
RK		 8119 lhz%U1%X1 %0,%1
8120 sth%U0%X0 %1,%0
19d5775a 8121 {lil|li} %0,%w1
1fd4e8c1 8122 mf%1 %0
e76e75bb 8123 mt%0 %1
fb81d7ce 8124 mt%0 %1
e34eaae5 8125 {cror 0,0,0|nop}"
02ca7595 8126 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1 8127
4ae234b0
GK		 8128(define_expand "mov<mode>"
8129 [(set (match_operand:INT 0 "general_operand" "")
8130 (match_operand:INT 1 "any_operand" ""))]
1fd4e8c1 8131 ""
4ae234b0 8132 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
1fd4e8c1 8133
e34eaae5 8134(define_insn "*movqi_internal"
fb81d7ce
RK		 8135 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8136 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8137 "gpc_reg_operand (operands[0], QImode)
8138 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 8139 "@
deb9225a 8140 mr %0,%1
1fd4e8c1
RK		 8141 lbz%U1%X1 %0,%1
8142 stb%U0%X0 %1,%0
19d5775a 8143 {lil|li} %0,%1
1fd4e8c1 8144 mf%1 %0
e76e75bb 8145 mt%0 %1
fb81d7ce 8146 mt%0 %1
e34eaae5 8147 {cror 0,0,0|nop}"
02ca7595 8148 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 8149\f
8150;; Here is how to move condition codes around. When we store CC data in
8151;; an integer register or memory, we store just the high-order 4 bits.
8152;; This lets us not shift in the most common case of CR0.
8153(define_expand "movcc"
8154 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8155 (match_operand:CC 1 "nonimmediate_operand" ""))]
8156 ""
8157 "")
8158
a65c591c 8159(define_insn "*movcc_internal1"
4eb585a4
DE		 8160 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8161 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
1fd4e8c1
RK		 8162 "register_operand (operands[0], CCmode)
8163 || register_operand (operands[1], CCmode)"
8164 "@
8165 mcrf %0,%1
8166 mtcrf 128,%1
ca7f5001 8167 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
4eb585a4 8168 crxor %0,%0,%0
2c4a9cff
DE		 8169 mfcr %0%Q1
8170 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 8171 mr %0,%1
4eb585a4 8172 {lil|li} %0,%1
b54cf83a 8173 mf%1 %0
b991a865
GK		 8174 mt%0 %1
8175 mt%0 %1
ca7f5001
RK		 8176 {l%U1%X1|lwz%U1%X1} %0,%1
8177 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff 8178 [(set (attr "type")
4eb585a4 8179 (cond [(eq_attr "alternative" "0,3")
2c4a9cff
DE		 8180 (const_string "cr_logical")
8181 (eq_attr "alternative" "1,2")
8182 (const_string "mtcr")
4eb585a4 8183 (eq_attr "alternative" "6,7,9")
2c4a9cff 8184 (const_string "integer")
2c4a9cff 8185 (eq_attr "alternative" "8")
4eb585a4
DE		 8186 (const_string "mfjmpr")
8187 (eq_attr "alternative" "10")
2c4a9cff 8188 (const_string "mtjmpr")
4eb585a4 8189 (eq_attr "alternative" "11")
2c4a9cff 8190 (const_string "load")
4eb585a4 8191 (eq_attr "alternative" "12")
2c4a9cff
DE		 8192 (const_string "store")
8193 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8194 (const_string "mfcrf")
8195 ]
8196 (const_string "mfcr")))
4eb585a4 8197 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
1fd4e8c1 8198\f
e52e05ca
MM		 8199;; For floating-point, we normally deal with the floating-point registers
8200;; unless -msoft-float is used. The sole exception is that parameter passing
8201;; can produce floating-point values in fixed-point registers. Unless the
8202;; value is a simple constant or already in memory, we deal with this by
8203;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 8204(define_expand "movsf"
8205 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8206 (match_operand:SF 1 "any_operand" ""))]
8207 ""
fb4d4348 8208 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 8209
1fd4e8c1 8210(define_split
cd2b37d9 8211 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 8212 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 8213 "reload_completed
5ae4759c
MM		 8214 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8215 || (GET_CODE (operands[0]) == SUBREG
8216 && GET_CODE (SUBREG_REG (operands[0])) == REG
8217 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 8218 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 8219 "
8220{
8221 long l;
8222 REAL_VALUE_TYPE rv;
8223
8224 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8225 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 8226
f99f88e0
DE		 8227 if (! TARGET_POWERPC64)
8228 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8229 else
8230 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 8231
2496c7bd 8232 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 8233}")
8234
c4c40373 8235(define_insn "*movsf_hardfloat"
fb3249ef 8236 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
ae6669e7 8237 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
d14a6d05 8238 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8239 || gpc_reg_operand (operands[1], SFmode))
8240 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
1fd4e8c1 8241 "@
f99f88e0
DE		 8242 mr %0,%1
8243 {l%U1%X1|lwz%U1%X1} %0,%1
8244 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 8245 fmr %0,%1
8246 lfs%U1%X1 %0,%1
c4c40373 8247 stfs%U0%X0 %1,%0
b991a865
GK		 8248 mt%0 %1
8249 mt%0 %1
8250 mf%1 %0
e0740893 8251 {cror 0,0,0|nop}
c4c40373
MM		 8252 #
8253 #"
9c6fdb46 8254 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
ae6669e7 8255 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 8256
c4c40373 8257(define_insn "*movsf_softfloat"
dd0fbae2
MK		 8258 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8259 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 8260 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8261 || gpc_reg_operand (operands[1], SFmode))
8262 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 8263 "@
8264 mr %0,%1
b991a865
GK		 8265 mt%0 %1
8266 mt%0 %1
8267 mf%1 %0
d14a6d05
MM		 8268 {l%U1%X1|lwz%U1%X1} %0,%1
8269 {st%U0%X0|stw%U0%X0} %1,%0
8270 {lil|li} %0,%1
802a0058 8271 {liu|lis} %0,%v1
aee86b38 8272 {cal|la} %0,%a1
c4c40373 8273 #
dd0fbae2
MK		 8274 #
8275 {cror 0,0,0|nop}"
9c6fdb46 8276 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
dd0fbae2 8277 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 8278
1fd4e8c1
RK		 8279\f
8280(define_expand "movdf"
8281 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8282 (match_operand:DF 1 "any_operand" ""))]
8283 ""
fb4d4348 8284 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 8285
8286(define_split
cd2b37d9 8287 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 8288 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 8289 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8290 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8291 || (GET_CODE (operands[0]) == SUBREG
8292 && GET_CODE (SUBREG_REG (operands[0])) == REG
8293 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8294 [(set (match_dup 2) (match_dup 4))
8295 (set (match_dup 3) (match_dup 1))]
8296 "
8297{
5ae4759c 8298 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 8299 HOST_WIDE_INT value = INTVAL (operands[1]);
8300
5ae4759c
MM		 8301 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8302 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 8303#if HOST_BITS_PER_WIDE_INT == 32
8304 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8305#else
8306 operands[4] = GEN_INT (value >> 32);
a65c591c 8307 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 8308#endif
c4c40373
MM		 8309}")
8310
c4c40373
MM		 8311(define_split
8312 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8313 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8314 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8315 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8316 || (GET_CODE (operands[0]) == SUBREG
8317 && GET_CODE (SUBREG_REG (operands[0])) == REG
8318 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8319 [(set (match_dup 2) (match_dup 4))
8320 (set (match_dup 3) (match_dup 5))]
8321 "
8322{
5ae4759c 8323 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 8324 long l[2];
8325 REAL_VALUE_TYPE rv;
8326
8327 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8328 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8329
5ae4759c
MM		 8330 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8331 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 8332 operands[4] = gen_int_mode (l[endian], SImode);
8333 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 8334}")
8335
efc08378
DE		 8336(define_split
8337 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8308679f 8338 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8339 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8340 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8341 || (GET_CODE (operands[0]) == SUBREG
8342 && GET_CODE (SUBREG_REG (operands[0])) == REG
8343 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 8344 [(set (match_dup 2) (match_dup 3))]
5ae4759c 8345 "
a260abc9
DE		 8346{
8347 int endian = (WORDS_BIG_ENDIAN == 0);
8348 long l[2];
8349 REAL_VALUE_TYPE rv;
4977bab6 8350#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 8351 HOST_WIDE_INT val;
4977bab6 8352#endif
a260abc9
DE		 8353
8354 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8355 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8356
8357 operands[2] = gen_lowpart (DImode, operands[0]);
8358 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 8359#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8360 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8361 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 8362
f5264b52 8363 operands[3] = gen_int_mode (val, DImode);
5b029315 8364#else
a260abc9 8365 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 8366#endif
a260abc9 8367}")
efc08378 8368
4eae5fe1 8369;; Don't have reload use general registers to load a constant. First,
1427100a 8370;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 8371;; a non-offsettable memref, but also it is less efficient than loading
8372;; the constant into an FP register, since it will probably be used there.
8373;; The "??" is a kludge until we can figure out a more reasonable way
8374;; of handling these non-offsettable values.
c4c40373 8375(define_insn "*movdf_hardfloat32"
914a7297
DE		 8376 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8377 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
a3170dc6 8378 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8379 && (gpc_reg_operand (operands[0], DFmode)
8380 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 8381 "*
8382{
8383 switch (which_alternative)
8384 {
a260abc9 8385 default:
37409796 8386 gcc_unreachable ();
e7113111
RK		 8387 case 0:
8388 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 8389 the first register operand 0 is the same as the second register
8390 of operand 1, we must copy in the opposite order. */
e7113111 8391 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8392 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 8393 else
deb9225a 8394 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 8395 case 1:
d04b6e6e
EB		 8396 if (rs6000_offsettable_memref_p (operands[1])
8397 || (GET_CODE (operands[1]) == MEM
8398 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8399 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
6fb5fa3c
DB		 8400 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8401 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
000034eb
DE		 8402 {
8403 /* If the low-address word is used in the address, we must load
8404 it last. Otherwise, load it first. Note that we cannot have
8405 auto-increment in that case since the address register is
8406 known to be dead. */
8407 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8408 operands[1], 0))
8409 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8410 else
6fb5fa3c 8411 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
000034eb 8412 }
e7113111 8413 else
000034eb
DE		 8414 {
8415 rtx addreg;
8416
000034eb
DE		 8417 addreg = find_addr_reg (XEXP (operands[1], 0));
8418 if (refers_to_regno_p (REGNO (operands[0]),
8419 REGNO (operands[0]) + 1,
8420 operands[1], 0))
8421 {
8422 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8423 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb 8424 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2284bd2b 8425 return \"{l%X1|lwz%X1} %0,%1\";
000034eb
DE		 8426 }
8427 else
8428 {
2284bd2b 8429 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
000034eb 8430 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8431 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb
DE		 8432 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8433 return \"\";
8434 }
8435 }
e7113111 8436 case 2:
d04b6e6e
EB		 8437 if (rs6000_offsettable_memref_p (operands[0])
8438 || (GET_CODE (operands[0]) == MEM
8439 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8440 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
6fb5fa3c
DB		 8441 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8442 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8443 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
000034eb
DE		 8444 else
8445 {
8446 rtx addreg;
8447
000034eb 8448 addreg = find_addr_reg (XEXP (operands[0], 0));
2284bd2b 8449 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
000034eb 8450 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8451 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
000034eb
DE		 8452 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8453 return \"\";
8454 }
e7113111 8455 case 3:
914a7297 8456 return \"fmr %0,%1\";
e7113111 8457 case 4:
914a7297 8458 return \"lfd%U1%X1 %0,%1\";
e7113111 8459 case 5:
914a7297 8460 return \"stfd%U0%X0 %1,%0\";
e7113111 8461 case 6:
c4c40373 8462 case 7:
c4c40373 8463 case 8:
914a7297 8464 return \"#\";
e7113111
RK		 8465 }
8466}"
943c15ed 8467 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
914a7297 8468 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 8469
c4c40373 8470(define_insn "*movdf_softfloat32"
1427100a
DE		 8471 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8472 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7a2f7870 8473 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
52d3af72
DE		 8474 && (gpc_reg_operand (operands[0], DFmode)
8475 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8476 "*
8477{
8478 switch (which_alternative)
8479 {
a260abc9 8480 default:
37409796 8481 gcc_unreachable ();
dc4f83ca
MM		 8482 case 0:
8483 /* We normally copy the low-numbered register first. However, if
8484 the first register operand 0 is the same as the second register of
8485 operand 1, we must copy in the opposite order. */
8486 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8487 return \"mr %L0,%L1\;mr %0,%1\";
8488 else
8489 return \"mr %0,%1\;mr %L0,%L1\";
8490 case 1:
3cb999d8
DE		 8491 /* If the low-address word is used in the address, we must load
8492 it last. Otherwise, load it first. Note that we cannot have
8493 auto-increment in that case since the address register is
8494 known to be dead. */
dc4f83ca 8495 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8496 operands[1], 0))
dc4f83ca
MM		 8497 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8498 else
6fb5fa3c 8499 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
dc4f83ca 8500 case 2:
6fb5fa3c 8501 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
dc4f83ca 8502 case 3:
c4c40373
MM		 8503 case 4:
8504 case 5:
dc4f83ca
MM		 8505 return \"#\";
8506 }
8507}"
943c15ed 8508 [(set_attr "type" "two,load,store,*,*,*")
c4c40373 8509 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8510
44cd321e
PS		 8511; ld/std require word-aligned displacements -> 'Y' constraint.
8512; List Y->r and r->Y before r->r for reload.
8513(define_insn "*movdf_hardfloat64_mfpgpr"
8514 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8515 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8516 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8517 && (gpc_reg_operand (operands[0], DFmode)
8518 || gpc_reg_operand (operands[1], DFmode))"
8519 "@
8520 std%U0%X0 %1,%0
8521 ld%U1%X1 %0,%1
8522 mr %0,%1
8523 fmr %0,%1
8524 lfd%U1%X1 %0,%1
8525 stfd%U0%X0 %1,%0
8526 mt%0 %1
8527 mf%1 %0
8528 {cror 0,0,0|nop}
8529 #
8530 #
8531 #
8532 mftgpr %0,%1
8533 mffgpr %0,%1"
8534 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8535 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8536
d2288d5d
HP		 8537; ld/std require word-aligned displacements -> 'Y' constraint.
8538; List Y->r and r->Y before r->r for reload.
c4c40373 8539(define_insn "*movdf_hardfloat64"
fb3249ef 8540 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
ae6669e7 8541 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
44cd321e 8542 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8543 && (gpc_reg_operand (operands[0], DFmode)
8544 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8545 "@
96bb8ed3 8546 std%U0%X0 %1,%0
3364872d
FJ		 8547 ld%U1%X1 %0,%1
8548 mr %0,%1
3d5570cb 8549 fmr %0,%1
f63184ac 8550 lfd%U1%X1 %0,%1
914a7297
DE		 8551 stfd%U0%X0 %1,%0
8552 mt%0 %1
8553 mf%1 %0
e0740893 8554 {cror 0,0,0|nop}
914a7297
DE		 8555 #
8556 #
8557 #"
9c6fdb46 8558 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
ae6669e7 8559 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8560
c4c40373 8561(define_insn "*movdf_softfloat64"
d2288d5d
HP		 8562 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8563 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
a3170dc6 8564 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8565 && (gpc_reg_operand (operands[0], DFmode)
8566 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca 8567 "@
d2288d5d
HP		 8568 ld%U1%X1 %0,%1
8569 std%U0%X0 %1,%0
dc4f83ca 8570 mr %0,%1
914a7297
DE		 8571 mt%0 %1
8572 mf%1 %0
c4c40373
MM		 8573 #
8574 #
e2d0915c 8575 #
e0740893 8576 {cror 0,0,0|nop}"
9c6fdb46 8577 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
e2d0915c 8578 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 8579\f
06f4e019
DE		 8580(define_expand "movtf"
8581 [(set (match_operand:TF 0 "general_operand" "")
8582 (match_operand:TF 1 "any_operand" ""))]
8521c414 8583 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8584 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8585
a9baceb1
GK		 8586; It's important to list the o->f and f->o moves before f->f because
8587; otherwise reload, given m->f, will try to pick f->f and reload it,
409f61cd 8588; which doesn't make progress. Likewise r->Y must be before r->r.
a9baceb1 8589(define_insn_and_split "*movtf_internal"
409f61cd
AM		 8590 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8591 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
602ea4d3 8592 "!TARGET_IEEEQUAD
39e63627 8593 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8594 && (gpc_reg_operand (operands[0], TFmode)
8595 || gpc_reg_operand (operands[1], TFmode))"
a9baceb1 8596 "#"
ecb62ae7 8597 "&& reload_completed"
a9baceb1
GK		 8598 [(pc)]
8599{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
112ccb83 8600 [(set_attr "length" "8,8,8,20,20,16")])
06f4e019 8601
8521c414 8602(define_insn_and_split "*movtf_softfloat"
17caeff2 8603 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8521c414
JM		 8604 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8605 "!TARGET_IEEEQUAD
8606 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8607 && (gpc_reg_operand (operands[0], TFmode)
8608 || gpc_reg_operand (operands[1], TFmode))"
8609 "#"
8610 "&& reload_completed"
8611 [(pc)]
8612{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8613 [(set_attr "length" "20,20,16")])
8614
ecb62ae7 8615(define_expand "extenddftf2"
17caeff2
JM		 8616 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8617 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8618 "!TARGET_IEEEQUAD
8619 && TARGET_HARD_FLOAT
8620 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8621 && TARGET_LONG_DOUBLE_128"
8622{
8623 if (TARGET_E500_DOUBLE)
8624 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8625 else
8626 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8627 DONE;
8628})
8629
8630(define_expand "extenddftf2_fprs"
ecb62ae7
GK		 8631 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8632 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8633 (use (match_dup 2))])]
602ea4d3 8634 "!TARGET_IEEEQUAD
39e63627 8635 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8636{
ecb62ae7 8637 operands[2] = CONST0_RTX (DFmode);
aa9cf005
DE		 8638 /* Generate GOT reference early for SVR4 PIC. */
8639 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8640 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
ecb62ae7 8641})
06f4e019 8642
ecb62ae7
GK		 8643(define_insn_and_split "*extenddftf2_internal"
8644 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8645 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
97c54d9a 8646 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
602ea4d3 8647 "!TARGET_IEEEQUAD
39e63627 8648 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8649 "#"
8650 "&& reload_completed"
8651 [(pc)]
06f4e019 8652{
ecb62ae7
GK		 8653 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8654 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8655 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8656 operands[1]);
8657 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8658 operands[2]);
8659 DONE;
6ae08853 8660})
ecb62ae7
GK		 8661
8662(define_expand "extendsftf2"
8663 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8664 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
602ea4d3 8665 "!TARGET_IEEEQUAD
17caeff2
JM		 8666 && TARGET_HARD_FLOAT
8667 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8668 && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8669{
8670 rtx tmp = gen_reg_rtx (DFmode);
8671 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8672 emit_insn (gen_extenddftf2 (operands[0], tmp));
8673 DONE;
8674})
06f4e019 8675
8cb320b8 8676(define_expand "trunctfdf2"
589b3fda
DE		 8677 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8678 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8679 "!TARGET_IEEEQUAD
17caeff2
JM		 8680 && TARGET_HARD_FLOAT
8681 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8682 && TARGET_LONG_DOUBLE_128"
589b3fda 8683 "")
8cb320b8
DE		 8684
8685(define_insn_and_split "trunctfdf2_internal1"
8686 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8687 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
602ea4d3 8688 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8cb320b8
DE		 8689 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8690 "@
8691 #
8692 fmr %0,%1"
8693 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8694 [(const_int 0)]
8695{
8696 emit_note (NOTE_INSN_DELETED);
8697 DONE;
8698}
8699 [(set_attr "type" "fp")])
8700
8701(define_insn "trunctfdf2_internal2"
8702 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8703 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8704 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8cb320b8 8705 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8706 "fadd %0,%1,%L1"
8cb320b8 8707 [(set_attr "type" "fp")])
06f4e019 8708
17caeff2
JM		 8709(define_expand "trunctfsf2"
8710 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8711 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8712 "!TARGET_IEEEQUAD
8713 && TARGET_HARD_FLOAT
8714 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8715 && TARGET_LONG_DOUBLE_128"
8716{
8717 if (TARGET_E500_DOUBLE)
8718 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8719 else
8720 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8721 DONE;
8722})
8723
8724(define_insn_and_split "trunctfsf2_fprs"
06f4e019 8725 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 8726 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8727 (clobber (match_scratch:DF 2 "=f"))]
602ea4d3 8728 "!TARGET_IEEEQUAD
39e63627 8729 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8730 "#"
ea112fc4 8731 "&& reload_completed"
06f4e019
DE		 8732 [(set (match_dup 2)
8733 (float_truncate:DF (match_dup 1)))
8734 (set (match_dup 0)
8735 (float_truncate:SF (match_dup 2)))]
ea112fc4 8736 "")
06f4e019 8737
0c90aa3c 8738(define_expand "floatsitf2"
d29b7f64
DE		 8739 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8740 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
602ea4d3 8741 "!TARGET_IEEEQUAD
17caeff2
JM		 8742 && TARGET_HARD_FLOAT
8743 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8744 && TARGET_LONG_DOUBLE_128"
0c90aa3c
GK		 8745{
8746 rtx tmp = gen_reg_rtx (DFmode);
8747 expand_float (tmp, operands[1], false);
8748 emit_insn (gen_extenddftf2 (operands[0], tmp));
8749 DONE;
8750})
06f4e019 8751
ecb62ae7
GK		 8752; fadd, but rounding towards zero.
8753; This is probably not the optimal code sequence.
8754(define_insn "fix_trunc_helper"
8755 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8756 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8757 UNSPEC_FIX_TRUNC_TF))
8758 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8759 "TARGET_HARD_FLOAT && TARGET_FPRS"
8760 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8761 [(set_attr "type" "fp")
8762 (set_attr "length" "20")])
8763
0c90aa3c 8764(define_expand "fix_trunctfsi2"
17caeff2
JM		 8765 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8766 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8767 "!TARGET_IEEEQUAD
8768 && (TARGET_POWER2 || TARGET_POWERPC)
8769 && TARGET_HARD_FLOAT
8770 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8771 && TARGET_LONG_DOUBLE_128"
8772{
8773 if (TARGET_E500_DOUBLE)
8774 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8775 else
8776 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8777 DONE;
8778})
8779
8780(define_expand "fix_trunctfsi2_fprs"
ecb62ae7
GK		 8781 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8782 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8783 (clobber (match_dup 2))
8784 (clobber (match_dup 3))
8785 (clobber (match_dup 4))
8786 (clobber (match_dup 5))])]
602ea4d3 8787 "!TARGET_IEEEQUAD
ecb62ae7
GK		 8788 && (TARGET_POWER2 || TARGET_POWERPC)
8789 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8790{
8791 operands[2] = gen_reg_rtx (DFmode);
8792 operands[3] = gen_reg_rtx (DFmode);
8793 operands[4] = gen_reg_rtx (DImode);
8794 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8795})
8796
8797(define_insn_and_split "*fix_trunctfsi2_internal"
61c07d3c 8798 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
ecb62ae7
GK		 8799 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8800 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8801 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8802 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8803 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
602ea4d3 8804 "!TARGET_IEEEQUAD
39e63627 8805 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 8806 "#"
b3a13419 8807 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
ecb62ae7 8808 [(pc)]
0c90aa3c 8809{
ecb62ae7
GK		 8810 rtx lowword;
8811 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8812
230215f5
GK		 8813 gcc_assert (MEM_P (operands[5]));
8814 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
ecb62ae7
GK		 8815
8816 emit_insn (gen_fctiwz (operands[4], operands[2]));
8817 emit_move_insn (operands[5], operands[4]);
230215f5 8818 emit_move_insn (operands[0], lowword);
0c90aa3c
GK		 8819 DONE;
8820})
06f4e019 8821
17caeff2
JM		 8822(define_expand "negtf2"
8823 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8824 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8825 "!TARGET_IEEEQUAD
8826 && TARGET_HARD_FLOAT
8827 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8828 && TARGET_LONG_DOUBLE_128"
8829 "")
8830
8831(define_insn "negtf2_internal"
06f4e019
DE		 8832 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8833 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8834 "!TARGET_IEEEQUAD
39e63627 8835 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8836 "*
8837{
8838 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8839 return \"fneg %L0,%L1\;fneg %0,%1\";
8840 else
8841 return \"fneg %0,%1\;fneg %L0,%L1\";
8842}"
8843 [(set_attr "type" "fp")
8844 (set_attr "length" "8")])
8845
1a402dc1 8846(define_expand "abstf2"
17caeff2
JM		 8847 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8848 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8849 "!TARGET_IEEEQUAD
17caeff2
JM		 8850 && TARGET_HARD_FLOAT
8851 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8852 && TARGET_LONG_DOUBLE_128"
1a402dc1 8853 "
06f4e019 8854{
1a402dc1 8855 rtx label = gen_label_rtx ();
17caeff2
JM		 8856 if (TARGET_E500_DOUBLE)
8857 {
8858 if (flag_unsafe_math_optimizations)
8859 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8860 else
8861 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8862 }
8863 else
8864 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
1a402dc1
AM		 8865 emit_label (label);
8866 DONE;
8867}")
06f4e019 8868
1a402dc1 8869(define_expand "abstf2_internal"
e42ac3de
RS		 8870 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8871 (match_operand:TF 1 "gpc_reg_operand" ""))
1a402dc1
AM		 8872 (set (match_dup 3) (match_dup 5))
8873 (set (match_dup 5) (abs:DF (match_dup 5)))
8874 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8875 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8876 (label_ref (match_operand 2 "" ""))
8877 (pc)))
8878 (set (match_dup 6) (neg:DF (match_dup 6)))]
602ea4d3 8879 "!TARGET_IEEEQUAD
39e63627 8880 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
1a402dc1 8881 "
06f4e019 8882{
1a402dc1
AM		 8883 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8884 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8885 operands[3] = gen_reg_rtx (DFmode);
8886 operands[4] = gen_reg_rtx (CCFPmode);
8887 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8888 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8889}")
06f4e019 8890\f
1fd4e8c1
RK		 8891;; Next come the multi-word integer load and store and the load and store
8892;; multiple insns.
1fd4e8c1 8893
112ccb83
GK		 8894; List r->r after r->"o<>", otherwise reload will try to reload a
8895; non-offsettable address by using r->r which won't make progress.
acad7ed3 8896(define_insn "*movdi_internal32"
17caeff2 8897 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
112ccb83 8898 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
a260abc9 8899 "! TARGET_POWERPC64
4e74d8ec
MM		 8900 && (gpc_reg_operand (operands[0], DImode)
8901 || gpc_reg_operand (operands[1], DImode))"
112ccb83
GK		 8902 "@
8903 #
8904 #
8905 #
8906 fmr %0,%1
8907 lfd%U1%X1 %0,%1
8908 stfd%U0%X0 %1,%0
8909 #"
8910 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
4e74d8ec
MM		 8911
8912(define_split
8913 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8914 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 8915 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8916 [(set (match_dup 2) (match_dup 4))
8917 (set (match_dup 3) (match_dup 1))]
8918 "
8919{
5f59ecb7 8920 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 8921 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8922 DImode);
8923 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8924 DImode);
75d39459 8925#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 8926 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 8927#else
5f59ecb7 8928 operands[4] = GEN_INT (value >> 32);
a65c591c 8929 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 8930#endif
4e74d8ec
MM		 8931}")
8932
3a1f863f 8933(define_split
17caeff2 8934 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
3a1f863f 8935 (match_operand:DI 1 "input_operand" ""))]
6ae08853 8936 "reload_completed && !TARGET_POWERPC64
3a1f863f 8937 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 8938 [(pc)]
8939{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
3a1f863f 8940
44cd321e
PS		 8941(define_insn "*movdi_mfpgpr"
8942 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8943 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8944 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8945 && (gpc_reg_operand (operands[0], DImode)
8946 || gpc_reg_operand (operands[1], DImode))"
8947 "@
8948 mr %0,%1
8949 ld%U1%X1 %0,%1
8950 std%U0%X0 %1,%0
8951 li %0,%1
8952 lis %0,%v1
8953 #
8954 {cal|la} %0,%a1
8955 fmr %0,%1
8956 lfd%U1%X1 %0,%1
8957 stfd%U0%X0 %1,%0
8958 mf%1 %0
8959 mt%0 %1
8960 {cror 0,0,0|nop}
8961 mftgpr %0,%1
8962 mffgpr %0,%1"
8963 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8964 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8965
acad7ed3 8966(define_insn "*movdi_internal64"
343f6bbf 8967 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9615f239 8968 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
44cd321e 8969 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
4e74d8ec
MM		 8970 && (gpc_reg_operand (operands[0], DImode)
8971 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 8972 "@
3d5570cb
RK		 8973 mr %0,%1
8974 ld%U1%X1 %0,%1
96bb8ed3 8975 std%U0%X0 %1,%0
3d5570cb 8976 li %0,%1
802a0058 8977 lis %0,%v1
e6ca2c17 8978 #
aee86b38 8979 {cal|la} %0,%a1
3d5570cb
RK		 8980 fmr %0,%1
8981 lfd%U1%X1 %0,%1
8982 stfd%U0%X0 %1,%0
8983 mf%1 %0
08075ead 8984 mt%0 %1
e34eaae5 8985 {cror 0,0,0|nop}"
02ca7595 8986 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 8987 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8988
5f59ecb7 8989;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 8990(define_insn ""
8991 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8992 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 8993 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8994 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 8995 && num_insns_constant (operands[1], DImode) == 1"
8996 "*
8997{
8998 return ((unsigned HOST_WIDE_INT)
8999 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9000 ? \"li %0,%1\" : \"lis %0,%v1\";
9001}")
9002
a260abc9
DE		 9003;; Generate all one-bits and clear left or right.
9004;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9005(define_split
9006 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1990cd79 9007 (match_operand:DI 1 "mask64_operand" ""))]
a260abc9
DE		 9008 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9009 [(set (match_dup 0) (const_int -1))
e6ca2c17 9010 (set (match_dup 0)
a260abc9
DE		 9011 (and:DI (rotate:DI (match_dup 0)
9012 (const_int 0))
9013 (match_dup 1)))]
9014 "")
9015
9016;; Split a load of a large constant into the appropriate five-instruction
9017;; sequence. Handle anything in a constant number of insns.
9018;; When non-easy constants can go in the TOC, this should use
9019;; easy_fp_constant predicate.
9020(define_split
9021 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9022 (match_operand:DI 1 "const_int_operand" ""))]
9023 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9024 [(set (match_dup 0) (match_dup 2))
9025 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 9026 "
2bfcf297
DB		 9027{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9028
9029 if (tem == operands[0])
9030 DONE;
e8d791dd 9031 else
2bfcf297 9032 FAIL;
5f59ecb7 9033}")
e6ca2c17 9034
5f59ecb7
DE		 9035(define_split
9036 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9037 (match_operand:DI 1 "const_double_operand" ""))]
9038 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9039 [(set (match_dup 0) (match_dup 2))
9040 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 9041 "
2bfcf297
DB		 9042{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9043
9044 if (tem == operands[0])
9045 DONE;
9046 else
9047 FAIL;
e6ca2c17 9048}")
acad7ed3 9049\f
1fd4e8c1
RK		 9050;; TImode is similar, except that we usually want to compute the address into
9051;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 9052;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 9053
9054;; We say that MQ is clobbered in the last alternative because the first
9055;; alternative would never get used otherwise since it would need a reload
9056;; while the 2nd alternative would not. We put memory cases first so they
9057;; are preferred. Otherwise, we'd try to reload the output instead of
9058;; giving the SCRATCH mq.
3a1f863f 9059
a260abc9 9060(define_insn "*movti_power"
7f514158
AM		 9061 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9062 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9063 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
6ae08853 9064 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 9065 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 9066 "*
9067{
9068 switch (which_alternative)
9069 {
dc4f83ca 9070 default:
37409796 9071 gcc_unreachable ();
dc4f83ca 9072
1fd4e8c1 9073 case 0:
3a1f863f
DE		 9074 if (TARGET_STRING)
9075 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 9076 case 1:
1fd4e8c1 9077 case 2:
3a1f863f 9078 return \"#\";
1fd4e8c1
RK		 9079 case 3:
9080 /* If the address is not used in the output, we can use lsi. Otherwise,
9081 fall through to generating four loads. */
e876481c
DE		 9082 if (TARGET_STRING
9083 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 9084 return \"{lsi|lswi} %0,%P1,16\";
82e41834 9085 /* ... fall through ... */
1fd4e8c1 9086 case 4:
7f514158 9087 case 5:
3a1f863f 9088 return \"#\";
1fd4e8c1
RK		 9089 }
9090}"
7f514158 9091 [(set_attr "type" "store,store,*,load,load,*")])
51b8fc2c 9092
a260abc9 9093(define_insn "*movti_string"
7f514158
AM		 9094 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9095 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
3a1f863f 9096 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 9097 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9098 "*
9099{
9100 switch (which_alternative)
9101 {
9102 default:
37409796 9103 gcc_unreachable ();
dc4f83ca 9104 case 0:
3a1f863f
DE		 9105 if (TARGET_STRING)
9106 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 9107 case 1:
cd1d3445 9108 case 2:
3a1f863f 9109 return \"#\";
cd1d3445
DE		 9110 case 3:
9111 /* If the address is not used in the output, we can use lsi. Otherwise,
9112 fall through to generating four loads. */
6ae08853 9113 if (TARGET_STRING
3a1f863f 9114 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 9115 return \"{lsi|lswi} %0,%P1,16\";
9116 /* ... fall through ... */
9117 case 4:
7f514158 9118 case 5:
3a1f863f 9119 return \"#\";
dc4f83ca
MM		 9120 }
9121}"
9c6fdb46 9122 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
dc4f83ca 9123
a260abc9 9124(define_insn "*movti_ppc64"
112ccb83
GK		 9125 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9126 (match_operand:TI 1 "input_operand" "r,r,m"))]
51b8fc2c
RK		 9127 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9128 || gpc_reg_operand (operands[1], TImode))"
112ccb83 9129 "#"
3a1f863f
DE		 9130 [(set_attr "type" "*,load,store")])
9131
7f514158
AM		 9132(define_split
9133 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9134 (match_operand:TI 1 "const_double_operand" ""))]
9135 "TARGET_POWERPC64"
9136 [(set (match_dup 2) (match_dup 4))
9137 (set (match_dup 3) (match_dup 5))]
9138 "
9139{
9140 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9141 TImode);
9142 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9143 TImode);
9144 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9145 {
9146 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9147 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9148 }
9149 else if (GET_CODE (operands[1]) == CONST_INT)
9150 {
9151 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9152 operands[5] = operands[1];
9153 }
9154 else
9155 FAIL;
9156}")
9157
3a1f863f
DE		 9158(define_split
9159 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9160 (match_operand:TI 1 "input_operand" ""))]
a9baceb1 9161 "reload_completed
3a1f863f 9162 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 9163 [(pc)]
9164{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
1fd4e8c1
RK		 9165\f
9166(define_expand "load_multiple"
2f622005
RK		 9167 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9168 (match_operand:SI 1 "" ""))
9169 (use (match_operand:SI 2 "" ""))])]
09a625f7 9170 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9171 "
9172{
9173 int regno;
9174 int count;
792760b9 9175 rtx op1;
1fd4e8c1
RK		 9176 int i;
9177
9178 /* Support only loading a constant number of fixed-point registers from
9179 memory and only bother with this if more than two; the machine
9180 doesn't support more than eight. */
9181 if (GET_CODE (operands[2]) != CONST_INT
9182 || INTVAL (operands[2]) <= 2
9183 || INTVAL (operands[2]) > 8
9184 || GET_CODE (operands[1]) != MEM
9185 || GET_CODE (operands[0]) != REG
9186 || REGNO (operands[0]) >= 32)
9187 FAIL;
9188
9189 count = INTVAL (operands[2]);
9190 regno = REGNO (operands[0]);
9191
39403d82 9192 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 9193 op1 = replace_equiv_address (operands[1],
9194 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 9195
9196 for (i = 0; i < count; i++)
9197 XVECEXP (operands[3], 0, i)
39403d82 9198 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 9199 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 9200}")
9201
9caa3eb2 9202(define_insn "*ldmsi8"
1fd4e8c1 9203 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 9204 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9205 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9206 (set (match_operand:SI 3 "gpc_reg_operand" "")
9207 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9208 (set (match_operand:SI 4 "gpc_reg_operand" "")
9209 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9210 (set (match_operand:SI 5 "gpc_reg_operand" "")
9211 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9212 (set (match_operand:SI 6 "gpc_reg_operand" "")
9213 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9214 (set (match_operand:SI 7 "gpc_reg_operand" "")
9215 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9216 (set (match_operand:SI 8 "gpc_reg_operand" "")
9217 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9218 (set (match_operand:SI 9 "gpc_reg_operand" "")
9219 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9220 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 9221 "*
9caa3eb2 9222{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9223 [(set_attr "type" "load_ux")
9caa3eb2 9224 (set_attr "length" "32")])
1fd4e8c1 9225
9caa3eb2
DE		 9226(define_insn "*ldmsi7"
9227 [(match_parallel 0 "load_multiple_operation"
9228 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9229 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9230 (set (match_operand:SI 3 "gpc_reg_operand" "")
9231 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9232 (set (match_operand:SI 4 "gpc_reg_operand" "")
9233 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9234 (set (match_operand:SI 5 "gpc_reg_operand" "")
9235 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9236 (set (match_operand:SI 6 "gpc_reg_operand" "")
9237 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9238 (set (match_operand:SI 7 "gpc_reg_operand" "")
9239 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9240 (set (match_operand:SI 8 "gpc_reg_operand" "")
9241 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9242 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9243 "*
9244{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9245 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9246 (set_attr "length" "32")])
9247
9248(define_insn "*ldmsi6"
9249 [(match_parallel 0 "load_multiple_operation"
9250 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9251 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9252 (set (match_operand:SI 3 "gpc_reg_operand" "")
9253 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9254 (set (match_operand:SI 4 "gpc_reg_operand" "")
9255 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9256 (set (match_operand:SI 5 "gpc_reg_operand" "")
9257 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9258 (set (match_operand:SI 6 "gpc_reg_operand" "")
9259 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9260 (set (match_operand:SI 7 "gpc_reg_operand" "")
9261 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9262 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9263 "*
9264{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9265 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9266 (set_attr "length" "32")])
9267
9268(define_insn "*ldmsi5"
9269 [(match_parallel 0 "load_multiple_operation"
9270 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9271 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9272 (set (match_operand:SI 3 "gpc_reg_operand" "")
9273 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9274 (set (match_operand:SI 4 "gpc_reg_operand" "")
9275 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9276 (set (match_operand:SI 5 "gpc_reg_operand" "")
9277 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9278 (set (match_operand:SI 6 "gpc_reg_operand" "")
9279 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9280 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9281 "*
9282{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9283 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9284 (set_attr "length" "32")])
9285
9286(define_insn "*ldmsi4"
9287 [(match_parallel 0 "load_multiple_operation"
9288 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9289 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9290 (set (match_operand:SI 3 "gpc_reg_operand" "")
9291 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9292 (set (match_operand:SI 4 "gpc_reg_operand" "")
9293 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9294 (set (match_operand:SI 5 "gpc_reg_operand" "")
9295 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9296 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9297 "*
9298{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9299 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9300 (set_attr "length" "32")])
9301
9302(define_insn "*ldmsi3"
9303 [(match_parallel 0 "load_multiple_operation"
9304 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9305 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9306 (set (match_operand:SI 3 "gpc_reg_operand" "")
9307 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9308 (set (match_operand:SI 4 "gpc_reg_operand" "")
9309 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9310 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9311 "*
9312{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9313 [(set_attr "type" "load_ux")
e82ee4cc 9314 (set_attr "length" "32")])
b19003d8 9315
1fd4e8c1 9316(define_expand "store_multiple"
2f622005
RK		 9317 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9318 (match_operand:SI 1 "" ""))
9319 (clobber (scratch:SI))
9320 (use (match_operand:SI 2 "" ""))])]
09a625f7 9321 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9322 "
9323{
9324 int regno;
9325 int count;
9326 rtx to;
792760b9 9327 rtx op0;
1fd4e8c1
RK		 9328 int i;
9329
9330 /* Support only storing a constant number of fixed-point registers to
9331 memory and only bother with this if more than two; the machine
9332 doesn't support more than eight. */
9333 if (GET_CODE (operands[2]) != CONST_INT
9334 || INTVAL (operands[2]) <= 2
9335 || INTVAL (operands[2]) > 8
9336 || GET_CODE (operands[0]) != MEM
9337 || GET_CODE (operands[1]) != REG
9338 || REGNO (operands[1]) >= 32)
9339 FAIL;
9340
9341 count = INTVAL (operands[2]);
9342 regno = REGNO (operands[1]);
9343
39403d82 9344 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 9345 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 9346 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 9347
9348 XVECEXP (operands[3], 0, 0)
7ef788f0 9349 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 9350 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 9351 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 9352
9353 for (i = 1; i < count; i++)
9354 XVECEXP (operands[3], 0, i + 1)
39403d82 9355 = gen_rtx_SET (VOIDmode,
7ef788f0 9356 adjust_address_nv (op0, SImode, i * 4),
c5c76735 9357 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 9358}")
9359
e46e3130 9360(define_insn "*stmsi8"
d14a6d05 9361 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 9362 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9363 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9364 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9365 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9366 (match_operand:SI 4 "gpc_reg_operand" "r"))
9367 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9368 (match_operand:SI 5 "gpc_reg_operand" "r"))
9369 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9370 (match_operand:SI 6 "gpc_reg_operand" "r"))
9371 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9372 (match_operand:SI 7 "gpc_reg_operand" "r"))
9373 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9374 (match_operand:SI 8 "gpc_reg_operand" "r"))
9375 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9376 (match_operand:SI 9 "gpc_reg_operand" "r"))
9377 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9378 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9379 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9380 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9381 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9382
9383(define_insn "*stmsi7"
9384 [(match_parallel 0 "store_multiple_operation"
9385 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9386 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9387 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9388 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9389 (match_operand:SI 4 "gpc_reg_operand" "r"))
9390 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9391 (match_operand:SI 5 "gpc_reg_operand" "r"))
9392 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9393 (match_operand:SI 6 "gpc_reg_operand" "r"))
9394 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9395 (match_operand:SI 7 "gpc_reg_operand" "r"))
9396 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9397 (match_operand:SI 8 "gpc_reg_operand" "r"))
9398 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9399 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9400 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9401 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9402 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9403
9404(define_insn "*stmsi6"
9405 [(match_parallel 0 "store_multiple_operation"
9406 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9407 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9408 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9409 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9410 (match_operand:SI 4 "gpc_reg_operand" "r"))
9411 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9412 (match_operand:SI 5 "gpc_reg_operand" "r"))
9413 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9414 (match_operand:SI 6 "gpc_reg_operand" "r"))
9415 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9416 (match_operand:SI 7 "gpc_reg_operand" "r"))
9417 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9418 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9419 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9420 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9421 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9422
9423(define_insn "*stmsi5"
9424 [(match_parallel 0 "store_multiple_operation"
9425 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9426 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9427 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9428 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9429 (match_operand:SI 4 "gpc_reg_operand" "r"))
9430 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9431 (match_operand:SI 5 "gpc_reg_operand" "r"))
9432 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9433 (match_operand:SI 6 "gpc_reg_operand" "r"))
9434 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9435 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9436 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9437 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9438 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9439
9440(define_insn "*stmsi4"
9441 [(match_parallel 0 "store_multiple_operation"
9442 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9443 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9444 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9445 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9446 (match_operand:SI 4 "gpc_reg_operand" "r"))
9447 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9448 (match_operand:SI 5 "gpc_reg_operand" "r"))
9449 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9450 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9451 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82 9452 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9453 [(set_attr "type" "store_ux")])
7e69e155 9454
e46e3130
DJ		 9455(define_insn "*stmsi3"
9456 [(match_parallel 0 "store_multiple_operation"
9457 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9458 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9459 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9460 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9461 (match_operand:SI 4 "gpc_reg_operand" "r"))
9462 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9463 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9464 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9465 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9466 [(set_attr "type" "store_ux")])
d2894ab5
DE		 9467
9468(define_insn "*stmsi8_power"
9469 [(match_parallel 0 "store_multiple_operation"
9470 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9471 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9472 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9473 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9474 (match_operand:SI 4 "gpc_reg_operand" "r"))
9475 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9476 (match_operand:SI 5 "gpc_reg_operand" "r"))
9477 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9478 (match_operand:SI 6 "gpc_reg_operand" "r"))
9479 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9480 (match_operand:SI 7 "gpc_reg_operand" "r"))
9481 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9482 (match_operand:SI 8 "gpc_reg_operand" "r"))
9483 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9484 (match_operand:SI 9 "gpc_reg_operand" "r"))
9485 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9486 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9487 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9488 "{stsi|stswi} %2,%1,%O0"
9489 [(set_attr "type" "store_ux")])
9490
9491(define_insn "*stmsi7_power"
9492 [(match_parallel 0 "store_multiple_operation"
9493 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9494 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9495 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9496 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9497 (match_operand:SI 4 "gpc_reg_operand" "r"))
9498 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9499 (match_operand:SI 5 "gpc_reg_operand" "r"))
9500 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9501 (match_operand:SI 6 "gpc_reg_operand" "r"))
9502 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9503 (match_operand:SI 7 "gpc_reg_operand" "r"))
9504 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9505 (match_operand:SI 8 "gpc_reg_operand" "r"))
9506 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9507 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9508 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9509 "{stsi|stswi} %2,%1,%O0"
9510 [(set_attr "type" "store_ux")])
9511
9512(define_insn "*stmsi6_power"
9513 [(match_parallel 0 "store_multiple_operation"
9514 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9515 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9516 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9517 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9518 (match_operand:SI 4 "gpc_reg_operand" "r"))
9519 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9520 (match_operand:SI 5 "gpc_reg_operand" "r"))
9521 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9522 (match_operand:SI 6 "gpc_reg_operand" "r"))
9523 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9524 (match_operand:SI 7 "gpc_reg_operand" "r"))
9525 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9526 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9527 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9528 "{stsi|stswi} %2,%1,%O0"
9529 [(set_attr "type" "store_ux")])
9530
9531(define_insn "*stmsi5_power"
9532 [(match_parallel 0 "store_multiple_operation"
9533 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9534 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9535 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9536 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9537 (match_operand:SI 4 "gpc_reg_operand" "r"))
9538 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9539 (match_operand:SI 5 "gpc_reg_operand" "r"))
9540 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9541 (match_operand:SI 6 "gpc_reg_operand" "r"))
9542 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9543 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9544 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9545 "{stsi|stswi} %2,%1,%O0"
9546 [(set_attr "type" "store_ux")])
9547
9548(define_insn "*stmsi4_power"
9549 [(match_parallel 0 "store_multiple_operation"
9550 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9551 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9552 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9553 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9554 (match_operand:SI 4 "gpc_reg_operand" "r"))
9555 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9556 (match_operand:SI 5 "gpc_reg_operand" "r"))
9557 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9558 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9559 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9560 "{stsi|stswi} %2,%1,%O0"
9561 [(set_attr "type" "store_ux")])
9562
9563(define_insn "*stmsi3_power"
9564 [(match_parallel 0 "store_multiple_operation"
9565 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9566 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9567 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9568 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9569 (match_operand:SI 4 "gpc_reg_operand" "r"))
9570 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9571 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9572 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9573 "{stsi|stswi} %2,%1,%O0"
9574 [(set_attr "type" "store_ux")])
7e69e155 9575\f
57e84f18 9576(define_expand "setmemsi"
fba73eb1 9577 [(parallel [(set (match_operand:BLK 0 "" "")
98843c92 9578 (match_operand 2 "const_int_operand" ""))
fba73eb1 9579 (use (match_operand:SI 1 "" ""))
57e84f18 9580 (use (match_operand:SI 3 "" ""))])]
fba73eb1
DE		 9581 ""
9582 "
9583{
57e84f18 9584 /* If value to set is not zero, use the library routine. */
a05be2e0 9585 if (operands[2] != const0_rtx)
57e84f18
AS		 9586 FAIL;
9587
fba73eb1
DE		 9588 if (expand_block_clear (operands))
9589 DONE;
9590 else
9591 FAIL;
9592}")
9593
7e69e155
MM		 9594;; String/block move insn.
9595;; Argument 0 is the destination
9596;; Argument 1 is the source
9597;; Argument 2 is the length
9598;; Argument 3 is the alignment
9599
70128ad9 9600(define_expand "movmemsi"
b6c9286a
MM		 9601 [(parallel [(set (match_operand:BLK 0 "" "")
9602 (match_operand:BLK 1 "" ""))
9603 (use (match_operand:SI 2 "" ""))
9604 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9605 ""
9606 "
9607{
9608 if (expand_block_move (operands))
9609 DONE;
9610 else
9611 FAIL;
9612}")
9613
9614;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9615;; register allocator doesn't have a clue about allocating 8 word registers.
9616;; rD/rS = r5 is preferred, efficient form.
70128ad9 9617(define_expand "movmemsi_8reg"
b6c9286a
MM		 9618 [(parallel [(set (match_operand 0 "" "")
9619 (match_operand 1 "" ""))
9620 (use (match_operand 2 "" ""))
9621 (use (match_operand 3 "" ""))
7e69e155
MM		 9622 (clobber (reg:SI 5))
9623 (clobber (reg:SI 6))
9624 (clobber (reg:SI 7))
9625 (clobber (reg:SI 8))
9626 (clobber (reg:SI 9))
9627 (clobber (reg:SI 10))
9628 (clobber (reg:SI 11))
9629 (clobber (reg:SI 12))
3c67b673 9630 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9631 "TARGET_STRING"
9632 "")
9633
9634(define_insn ""
52d3af72
DE		 9635 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9636 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9637 (use (match_operand:SI 2 "immediate_operand" "i"))
9638 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9639 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9640 (clobber (reg:SI 6))
9641 (clobber (reg:SI 7))
9642 (clobber (reg:SI 8))
9643 (clobber (reg:SI 9))
9644 (clobber (reg:SI 10))
9645 (clobber (reg:SI 11))
9646 (clobber (reg:SI 12))
3c67b673 9647 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9648 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9649 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9650 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9651 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9652 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9653 && REGNO (operands[4]) == 5"
9654 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9655 [(set_attr "type" "store_ux")
b7ff3d82 9656 (set_attr "length" "8")])
7e69e155
MM		 9657
9658(define_insn ""
4ae234b0
GK		 9659 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9660 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9661 (use (match_operand:SI 2 "immediate_operand" "i"))
9662 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9663 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9664 (clobber (reg:SI 6))
9665 (clobber (reg:SI 7))
9666 (clobber (reg:SI 8))
9667 (clobber (reg:SI 9))
9668 (clobber (reg:SI 10))
9669 (clobber (reg:SI 11))
9670 (clobber (reg:SI 12))
edd54d25 9671 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9672 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9673 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9674 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9675 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9676 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9677 && REGNO (operands[4]) == 5"
9678 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9679 [(set_attr "type" "store_ux")
b7ff3d82 9680 (set_attr "length" "8")])
7e69e155
MM		 9681
9682;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9683;; register allocator doesn't have a clue about allocating 6 word registers.
9684;; rD/rS = r5 is preferred, efficient form.
70128ad9 9685(define_expand "movmemsi_6reg"
b6c9286a
MM		 9686 [(parallel [(set (match_operand 0 "" "")
9687 (match_operand 1 "" ""))
9688 (use (match_operand 2 "" ""))
9689 (use (match_operand 3 "" ""))
f9562f27
DE		 9690 (clobber (reg:SI 5))
9691 (clobber (reg:SI 6))
7e69e155
MM		 9692 (clobber (reg:SI 7))
9693 (clobber (reg:SI 8))
9694 (clobber (reg:SI 9))
9695 (clobber (reg:SI 10))
3c67b673 9696 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9697 "TARGET_STRING"
9698 "")
9699
9700(define_insn ""
52d3af72
DE		 9701 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9702 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9703 (use (match_operand:SI 2 "immediate_operand" "i"))
9704 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9705 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9706 (clobber (reg:SI 6))
9707 (clobber (reg:SI 7))
7e69e155
MM		 9708 (clobber (reg:SI 8))
9709 (clobber (reg:SI 9))
9710 (clobber (reg:SI 10))
3c67b673 9711 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9712 "TARGET_STRING && TARGET_POWER
9713 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9714 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9715 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9716 && REGNO (operands[4]) == 5"
3c67b673 9717 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9718 [(set_attr "type" "store_ux")
b7ff3d82 9719 (set_attr "length" "8")])
7e69e155
MM		 9720
9721(define_insn ""
4ae234b0
GK		 9722 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9723 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9724 (use (match_operand:SI 2 "immediate_operand" "i"))
9725 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9726 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9727 (clobber (reg:SI 6))
9728 (clobber (reg:SI 7))
7e69e155
MM		 9729 (clobber (reg:SI 8))
9730 (clobber (reg:SI 9))
9731 (clobber (reg:SI 10))
edd54d25 9732 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9733 "TARGET_STRING && ! TARGET_POWER
7e69e155 9734 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9735 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9736 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9737 && REGNO (operands[4]) == 5"
3c67b673 9738 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9739 [(set_attr "type" "store_ux")
b7ff3d82 9740 (set_attr "length" "8")])
7e69e155 9741
f9562f27
DE		 9742;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9743;; problems with TImode.
9744;; rD/rS = r5 is preferred, efficient form.
70128ad9 9745(define_expand "movmemsi_4reg"
b6c9286a
MM		 9746 [(parallel [(set (match_operand 0 "" "")
9747 (match_operand 1 "" ""))
9748 (use (match_operand 2 "" ""))
9749 (use (match_operand 3 "" ""))
f9562f27
DE		 9750 (clobber (reg:SI 5))
9751 (clobber (reg:SI 6))
9752 (clobber (reg:SI 7))
9753 (clobber (reg:SI 8))
3c67b673 9754 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9755 "TARGET_STRING"
9756 "")
9757
9758(define_insn ""
52d3af72
DE		 9759 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9760 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9761 (use (match_operand:SI 2 "immediate_operand" "i"))
9762 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9763 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9764 (clobber (reg:SI 6))
9765 (clobber (reg:SI 7))
9766 (clobber (reg:SI 8))
3c67b673 9767 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9768 "TARGET_STRING && TARGET_POWER
9769 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9770 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9771 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9772 && REGNO (operands[4]) == 5"
3c67b673 9773 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9774 [(set_attr "type" "store_ux")
b7ff3d82 9775 (set_attr "length" "8")])
7e69e155
MM		 9776
9777(define_insn ""
4ae234b0
GK		 9778 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9779 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9780 (use (match_operand:SI 2 "immediate_operand" "i"))
9781 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9782 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9783 (clobber (reg:SI 6))
9784 (clobber (reg:SI 7))
9785 (clobber (reg:SI 8))
edd54d25 9786 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9787 "TARGET_STRING && ! TARGET_POWER
7e69e155 9788 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9789 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9790 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9791 && REGNO (operands[4]) == 5"
3c67b673 9792 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9793 [(set_attr "type" "store_ux")
b7ff3d82 9794 (set_attr "length" "8")])
7e69e155
MM		 9795
9796;; Move up to 8 bytes at a time.
70128ad9 9797(define_expand "movmemsi_2reg"
b6c9286a
MM		 9798 [(parallel [(set (match_operand 0 "" "")
9799 (match_operand 1 "" ""))
9800 (use (match_operand 2 "" ""))
9801 (use (match_operand 3 "" ""))
3c67b673
RK		 9802 (clobber (match_scratch:DI 4 ""))
9803 (clobber (match_scratch:SI 5 ""))])]
f9562f27 9804 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 9805 "")
9806
9807(define_insn ""
52d3af72
DE		 9808 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9809 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9810 (use (match_operand:SI 2 "immediate_operand" "i"))
9811 (use (match_operand:SI 3 "immediate_operand" "i"))
9812 (clobber (match_scratch:DI 4 "=&r"))
9813 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 9814 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 9815 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9816 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9817 [(set_attr "type" "store_ux")
b7ff3d82 9818 (set_attr "length" "8")])
7e69e155
MM		 9819
9820(define_insn ""
52d3af72
DE		 9821 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9822 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9823 (use (match_operand:SI 2 "immediate_operand" "i"))
9824 (use (match_operand:SI 3 "immediate_operand" "i"))
9825 (clobber (match_scratch:DI 4 "=&r"))
edd54d25 9826 (clobber (match_scratch:SI 5 "=X"))]
f9562f27 9827 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 9828 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 9829 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9830 [(set_attr "type" "store_ux")
b7ff3d82 9831 (set_attr "length" "8")])
7e69e155
MM		 9832
9833;; Move up to 4 bytes at a time.
70128ad9 9834(define_expand "movmemsi_1reg"
b6c9286a
MM		 9835 [(parallel [(set (match_operand 0 "" "")
9836 (match_operand 1 "" ""))
9837 (use (match_operand 2 "" ""))
9838 (use (match_operand 3 "" ""))
3c67b673
RK		 9839 (clobber (match_scratch:SI 4 ""))
9840 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 9841 "TARGET_STRING"
9842 "")
9843
9844(define_insn ""
52d3af72
DE		 9845 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9846 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9847 (use (match_operand:SI 2 "immediate_operand" "i"))
9848 (use (match_operand:SI 3 "immediate_operand" "i"))
9849 (clobber (match_scratch:SI 4 "=&r"))
9850 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9851 "TARGET_STRING && TARGET_POWER
9852 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9853 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9854 [(set_attr "type" "store_ux")
b7ff3d82 9855 (set_attr "length" "8")])
7e69e155
MM		 9856
9857(define_insn ""
4ae234b0
GK		 9858 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9859 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9860 (use (match_operand:SI 2 "immediate_operand" "i"))
9861 (use (match_operand:SI 3 "immediate_operand" "i"))
9862 (clobber (match_scratch:SI 4 "=&r"))
edd54d25 9863 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9864 "TARGET_STRING && ! TARGET_POWER
7e69e155 9865 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7 9866 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9867 [(set_attr "type" "store_ux")
09a625f7 9868 (set_attr "length" "8")])
1fd4e8c1 9869\f
7e69e155 9870;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 9871;; get by using pre-decrement or pre-increment, but the hardware can also
9872;; do cases where the increment is not the size of the object.
9873;;
9874;; In all these cases, we use operands 0 and 1 for the register being
9875;; incremented because those are the operands that local-alloc will
9876;; tie and these are the pair most likely to be tieable (and the ones
9877;; that will benefit the most).
9878
38c1f2d7 9879(define_insn "*movdi_update1"
51b8fc2c 9880 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 9881 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9882 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 9883 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9884 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9885 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9886 "@
9887 ldux %3,%0,%2
9888 ldu %3,%2(%0)"
b54cf83a 9889 [(set_attr "type" "load_ux,load_u")])
287f13ff 9890
2e6c9641
FJ		 9891(define_insn "movdi_<mode>_update"
9892 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9893 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c 9894 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
2e6c9641
FJ		 9895 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9896 (plus:P (match_dup 1) (match_dup 2)))]
38c1f2d7 9897 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9898 "@
9899 stdux %3,%0,%2
b7ff3d82 9900 stdu %3,%2(%0)"
b54cf83a 9901 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 9902
38c1f2d7 9903(define_insn "*movsi_update1"
cd2b37d9
RK		 9904 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9905 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9906 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9907 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9908 (plus:SI (match_dup 1) (match_dup 2)))]
f7b3ab8a 9909 "TARGET_UPDATE"
1fd4e8c1 9910 "@
ca7f5001
RK		 9911 {lux|lwzux} %3,%0,%2
9912 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 9913 [(set_attr "type" "load_ux,load_u")])
9914
9915(define_insn "*movsi_update2"
9916 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9917 (sign_extend:DI
9918 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9919 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9920 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9921 (plus:DI (match_dup 1) (match_dup 2)))]
9922 "TARGET_POWERPC64"
9923 "lwaux %3,%0,%2"
9924 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 9925
4697a36c 9926(define_insn "movsi_update"
cd2b37d9 9927 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9928 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9929 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9930 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9931 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9932 "TARGET_UPDATE"
1fd4e8c1 9933 "@
ca7f5001 9934 {stux|stwux} %3,%0,%2
b7ff3d82 9935 {stu|stwu} %3,%2(%0)"
b54cf83a 9936 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9937
b54cf83a 9938(define_insn "*movhi_update1"
cd2b37d9
RK		 9939 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9940 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9941 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9942 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9943 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9944 "TARGET_UPDATE"
1fd4e8c1 9945 "@
5f243543
RK		 9946 lhzux %3,%0,%2
9947 lhzu %3,%2(%0)"
b54cf83a 9948 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9949
38c1f2d7 9950(define_insn "*movhi_update2"
cd2b37d9 9951 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9952 (zero_extend:SI
cd2b37d9 9953 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9954 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9955 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9956 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9957 "TARGET_UPDATE"
1fd4e8c1 9958 "@
5f243543
RK		 9959 lhzux %3,%0,%2
9960 lhzu %3,%2(%0)"
b54cf83a 9961 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9962
38c1f2d7 9963(define_insn "*movhi_update3"
cd2b37d9 9964 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9965 (sign_extend:SI
cd2b37d9 9966 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9967 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9968 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9969 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9970 "TARGET_UPDATE"
1fd4e8c1 9971 "@
5f243543
RK		 9972 lhaux %3,%0,%2
9973 lhau %3,%2(%0)"
b54cf83a 9974 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 9975
38c1f2d7 9976(define_insn "*movhi_update4"
cd2b37d9 9977 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9978 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9979 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9980 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9981 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9982 "TARGET_UPDATE"
1fd4e8c1 9983 "@
5f243543 9984 sthux %3,%0,%2
b7ff3d82 9985 sthu %3,%2(%0)"
b54cf83a 9986 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9987
38c1f2d7 9988(define_insn "*movqi_update1"
cd2b37d9
RK		 9989 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9990 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9991 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9992 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9993 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9994 "TARGET_UPDATE"
1fd4e8c1 9995 "@
5f243543
RK		 9996 lbzux %3,%0,%2
9997 lbzu %3,%2(%0)"
b54cf83a 9998 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9999
38c1f2d7 10000(define_insn "*movqi_update2"
cd2b37d9 10001 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10002 (zero_extend:SI
cd2b37d9 10003 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10004 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10005 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10006 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10007 "TARGET_UPDATE"
1fd4e8c1 10008 "@
5f243543
RK		 10009 lbzux %3,%0,%2
10010 lbzu %3,%2(%0)"
b54cf83a 10011 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10012
38c1f2d7 10013(define_insn "*movqi_update3"
cd2b37d9 10014 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10015 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10016 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10017 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10018 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10019 "TARGET_UPDATE"
1fd4e8c1 10020 "@
5f243543 10021 stbux %3,%0,%2
b7ff3d82 10022 stbu %3,%2(%0)"
b54cf83a 10023 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10024
38c1f2d7 10025(define_insn "*movsf_update1"
cd2b37d9 10026 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 10027 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10028 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10029 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10030 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10031 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10032 "@
5f243543
RK		 10033 lfsux %3,%0,%2
10034 lfsu %3,%2(%0)"
b54cf83a 10035 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10036
38c1f2d7 10037(define_insn "*movsf_update2"
cd2b37d9 10038 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10039 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10040 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10041 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10042 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10043 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10044 "@
85fff2f3 10045 stfsux %3,%0,%2
b7ff3d82 10046 stfsu %3,%2(%0)"
b54cf83a 10047 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 10048
38c1f2d7
MM		 10049(define_insn "*movsf_update3"
10050 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10051 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10052 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10053 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10054 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10055 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10056 "@
10057 {lux|lwzux} %3,%0,%2
10058 {lu|lwzu} %3,%2(%0)"
b54cf83a 10059 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 10060
10061(define_insn "*movsf_update4"
10062 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10063 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10064 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10065 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10066 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10067 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10068 "@
10069 {stux|stwux} %3,%0,%2
10070 {stu|stwu} %3,%2(%0)"
b54cf83a 10071 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 10072
10073(define_insn "*movdf_update1"
cd2b37d9
RK		 10074 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10075 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10076 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10077 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10078 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10079 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10080 "@
5f243543
RK		 10081 lfdux %3,%0,%2
10082 lfdu %3,%2(%0)"
b54cf83a 10083 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10084
38c1f2d7 10085(define_insn "*movdf_update2"
cd2b37d9 10086 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10087 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10088 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10089 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10090 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10091 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10092 "@
5f243543 10093 stfdux %3,%0,%2
b7ff3d82 10094 stfdu %3,%2(%0)"
b54cf83a 10095 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 10096
10097;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10098
90f81f99 10099(define_insn "*lfq_power2"
bb8df8a6
EC		 10100 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10101 (match_operand:V2DF 1 "memory_operand" ""))]
90f81f99
AP		 10102 "TARGET_POWER2
10103 && TARGET_HARD_FLOAT && TARGET_FPRS"
bb8df8a6 10104 "lfq%U1%X1 %0,%1")
90f81f99
AP		 10105
10106(define_peephole2
10107 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4c70a4f3 10108 (match_operand:DF 1 "memory_operand" ""))
90f81f99 10109 (set (match_operand:DF 2 "gpc_reg_operand" "")
4c70a4f3
RK		 10110 (match_operand:DF 3 "memory_operand" ""))]
10111 "TARGET_POWER2
a3170dc6 10112 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10113 && registers_ok_for_quad_peep (operands[0], operands[2])
90f81f99
AP		 10114 && mems_ok_for_quad_peep (operands[1], operands[3])"
10115 [(set (match_dup 0)
bb8df8a6
EC		 10116 (match_dup 1))]
10117 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10118 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
4c70a4f3 10119
90f81f99 10120(define_insn "*stfq_power2"
bb8df8a6
EC		 10121 [(set (match_operand:V2DF 0 "memory_operand" "")
10122 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
90f81f99
AP		 10123 "TARGET_POWER2
10124 && TARGET_HARD_FLOAT && TARGET_FPRS"
10125 "stfq%U0%X0 %1,%0")
10126
10127
10128(define_peephole2
4c70a4f3 10129 [(set (match_operand:DF 0 "memory_operand" "")
90f81f99 10130 (match_operand:DF 1 "gpc_reg_operand" ""))
4c70a4f3 10131 (set (match_operand:DF 2 "memory_operand" "")
90f81f99 10132 (match_operand:DF 3 "gpc_reg_operand" ""))]
4c70a4f3 10133 "TARGET_POWER2
a3170dc6 10134 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10135 && registers_ok_for_quad_peep (operands[1], operands[3])
90f81f99
AP		 10136 && mems_ok_for_quad_peep (operands[0], operands[2])"
10137 [(set (match_dup 0)
10138 (match_dup 1))]
bb8df8a6
EC		 10139 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10140 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
2f4d9502 10141
036aadfc 10142;; After inserting conditional returns we can sometimes have
2f4d9502
NS		 10143;; unnecessary register moves. Unfortunately we cannot have a
10144;; modeless peephole here, because some single SImode sets have early
10145;; clobber outputs. Although those sets expand to multi-ppc-insn
10146;; sequences, using get_attr_length here will smash the operands
10147;; array. Neither is there an early_cobbler_p predicate.
036aadfc 10148;; Disallow subregs for E500 so we don't munge frob_di_df_2.
2f4d9502
NS		 10149(define_peephole2
10150 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10151 (match_operand:DF 1 "any_operand" ""))
10152 (set (match_operand:DF 2 "gpc_reg_operand" "")
10153 (match_dup 0))]
036aadfc
AM		 10154 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10155 && peep2_reg_dead_p (2, operands[0])"
2f4d9502
NS		 10156 [(set (match_dup 2) (match_dup 1))])
10157
10158(define_peephole2
10159 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10160 (match_operand:SF 1 "any_operand" ""))
10161 (set (match_operand:SF 2 "gpc_reg_operand" "")
10162 (match_dup 0))]
10163 "peep2_reg_dead_p (2, operands[0])"
10164 [(set (match_dup 2) (match_dup 1))])
10165
1fd4e8c1 10166\f
c4501e62
JJ		 10167;; TLS support.
10168
10169;; "b" output constraint here and on tls_ld to support tls linker optimization.
10170(define_insn "tls_gd_32"
b150f4f3
DE		 10171 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10172 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10173 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10174 UNSPEC_TLSGD))]
10175 "HAVE_AS_TLS && !TARGET_64BIT"
10176 "addi %0,%1,%2@got@tlsgd")
10177
10178(define_insn "tls_gd_64"
b150f4f3
DE		 10179 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10180 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10181 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10182 UNSPEC_TLSGD))]
10183 "HAVE_AS_TLS && TARGET_64BIT"
10184 "addi %0,%1,%2@got@tlsgd")
10185
10186(define_insn "tls_ld_32"
b150f4f3
DE		 10187 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10188 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 10189 UNSPEC_TLSLD))]
10190 "HAVE_AS_TLS && !TARGET_64BIT"
10191 "addi %0,%1,%&@got@tlsld")
10192
10193(define_insn "tls_ld_64"
b150f4f3
DE		 10194 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10195 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 10196 UNSPEC_TLSLD))]
10197 "HAVE_AS_TLS && TARGET_64BIT"
10198 "addi %0,%1,%&@got@tlsld")
10199
10200(define_insn "tls_dtprel_32"
b150f4f3
DE		 10201 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10202 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10203 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10204 UNSPEC_TLSDTPREL))]
10205 "HAVE_AS_TLS && !TARGET_64BIT"
10206 "addi %0,%1,%2@dtprel")
10207
10208(define_insn "tls_dtprel_64"
b150f4f3
DE		 10209 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10210 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10211 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10212 UNSPEC_TLSDTPREL))]
10213 "HAVE_AS_TLS && TARGET_64BIT"
10214 "addi %0,%1,%2@dtprel")
10215
10216(define_insn "tls_dtprel_ha_32"
b150f4f3
DE		 10217 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10218 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10219 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10220 UNSPEC_TLSDTPRELHA))]
10221 "HAVE_AS_TLS && !TARGET_64BIT"
10222 "addis %0,%1,%2@dtprel@ha")
10223
10224(define_insn "tls_dtprel_ha_64"
b150f4f3
DE		 10225 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10226 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10227 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10228 UNSPEC_TLSDTPRELHA))]
10229 "HAVE_AS_TLS && TARGET_64BIT"
10230 "addis %0,%1,%2@dtprel@ha")
10231
10232(define_insn "tls_dtprel_lo_32"
b150f4f3
DE		 10233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10234 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10235 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10236 UNSPEC_TLSDTPRELLO))]
10237 "HAVE_AS_TLS && !TARGET_64BIT"
10238 "addi %0,%1,%2@dtprel@l")
10239
10240(define_insn "tls_dtprel_lo_64"
b150f4f3
DE		 10241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10242 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10243 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10244 UNSPEC_TLSDTPRELLO))]
10245 "HAVE_AS_TLS && TARGET_64BIT"
10246 "addi %0,%1,%2@dtprel@l")
10247
10248(define_insn "tls_got_dtprel_32"
b150f4f3
DE		 10249 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10250 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10251 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10252 UNSPEC_TLSGOTDTPREL))]
10253 "HAVE_AS_TLS && !TARGET_64BIT"
10254 "lwz %0,%2@got@dtprel(%1)")
10255
10256(define_insn "tls_got_dtprel_64"
b150f4f3
DE		 10257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10258 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10259 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10260 UNSPEC_TLSGOTDTPREL))]
10261 "HAVE_AS_TLS && TARGET_64BIT"
10262 "ld %0,%2@got@dtprel(%1)")
10263
10264(define_insn "tls_tprel_32"
b150f4f3
DE		 10265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10266 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10267 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10268 UNSPEC_TLSTPREL))]
10269 "HAVE_AS_TLS && !TARGET_64BIT"
10270 "addi %0,%1,%2@tprel")
10271
10272(define_insn "tls_tprel_64"
b150f4f3
DE		 10273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10274 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10275 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10276 UNSPEC_TLSTPREL))]
10277 "HAVE_AS_TLS && TARGET_64BIT"
10278 "addi %0,%1,%2@tprel")
10279
10280(define_insn "tls_tprel_ha_32"
b150f4f3
DE		 10281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10282 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10283 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10284 UNSPEC_TLSTPRELHA))]
10285 "HAVE_AS_TLS && !TARGET_64BIT"
10286 "addis %0,%1,%2@tprel@ha")
10287
10288(define_insn "tls_tprel_ha_64"
b150f4f3
DE		 10289 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10290 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10291 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10292 UNSPEC_TLSTPRELHA))]
10293 "HAVE_AS_TLS && TARGET_64BIT"
10294 "addis %0,%1,%2@tprel@ha")
10295
10296(define_insn "tls_tprel_lo_32"
b150f4f3
DE		 10297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10298 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10299 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10300 UNSPEC_TLSTPRELLO))]
10301 "HAVE_AS_TLS && !TARGET_64BIT"
10302 "addi %0,%1,%2@tprel@l")
10303
10304(define_insn "tls_tprel_lo_64"
b150f4f3
DE		 10305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10306 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10307 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10308 UNSPEC_TLSTPRELLO))]
10309 "HAVE_AS_TLS && TARGET_64BIT"
10310 "addi %0,%1,%2@tprel@l")
10311
c1207243 10312;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 10313;; optimization. The linker may edit the instructions emitted by a
10314;; tls_got_tprel/tls_tls pair to addis,addi.
10315(define_insn "tls_got_tprel_32"
b150f4f3
DE		 10316 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10317 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10318 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10319 UNSPEC_TLSGOTTPREL))]
10320 "HAVE_AS_TLS && !TARGET_64BIT"
10321 "lwz %0,%2@got@tprel(%1)")
10322
10323(define_insn "tls_got_tprel_64"
b150f4f3
DE		 10324 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10325 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10326 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10327 UNSPEC_TLSGOTTPREL))]
10328 "HAVE_AS_TLS && TARGET_64BIT"
10329 "ld %0,%2@got@tprel(%1)")
10330
10331(define_insn "tls_tls_32"
b150f4f3
DE		 10332 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10333 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10334 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10335 UNSPEC_TLSTLS))]
10336 "HAVE_AS_TLS && !TARGET_64BIT"
10337 "add %0,%1,%2@tls")
10338
10339(define_insn "tls_tls_64"
b150f4f3
DE		 10340 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10341 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10342 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10343 UNSPEC_TLSTLS))]
10344 "HAVE_AS_TLS && TARGET_64BIT"
10345 "add %0,%1,%2@tls")
10346\f
1fd4e8c1
RK		 10347;; Next come insns related to the calling sequence.
10348;;
10349;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 10350;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 10351
10352(define_expand "allocate_stack"
e42ac3de 10353 [(set (match_operand 0 "gpc_reg_operand" "")
a260abc9
DE		 10354 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10355 (set (reg 1)
10356 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 10357 ""
10358 "
4697a36c 10359{ rtx chain = gen_reg_rtx (Pmode);
39403d82 10360 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 10361 rtx neg_op0;
1fd4e8c1
RK		 10362
10363 emit_move_insn (chain, stack_bot);
4697a36c 10364
a157febd
GK		 10365 /* Check stack bounds if necessary. */
10366 if (current_function_limit_stack)
10367 {
10368 rtx available;
6ae08853 10369 available = expand_binop (Pmode, sub_optab,
a157febd
GK		 10370 stack_pointer_rtx, stack_limit_rtx,
10371 NULL_RTX, 1, OPTAB_WIDEN);
10372 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10373 }
10374
e9a25f70
JL		 10375 if (GET_CODE (operands[1]) != CONST_INT
10376 || INTVAL (operands[1]) < -32767
10377 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 10378 {
10379 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 10380 if (TARGET_32BIT)
e9a25f70 10381 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 10382 else
e9a25f70 10383 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 10384 }
10385 else
e9a25f70 10386 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 10387
38c1f2d7 10388 if (TARGET_UPDATE)
2e6c9641 10389 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
38c1f2d7 10390 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
4697a36c 10391
38c1f2d7
MM		 10392 else
10393 {
10394 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10395 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
39403d82 10396 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
38c1f2d7 10397 }
e9a25f70
JL		 10398
10399 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 10400 DONE;
10401}")
59257ff7
RK		 10402
10403;; These patterns say how to save and restore the stack pointer. We need not
10404;; save the stack pointer at function level since we are careful to
10405;; preserve the backchain. At block level, we have to restore the backchain
10406;; when we restore the stack pointer.
10407;;
10408;; For nonlocal gotos, we must save both the stack pointer and its
10409;; backchain and restore both. Note that in the nonlocal case, the
10410;; save area is a memory location.
10411
10412(define_expand "save_stack_function"
ff381587
MM		 10413 [(match_operand 0 "any_operand" "")
10414 (match_operand 1 "any_operand" "")]
59257ff7 10415 ""
ff381587 10416 "DONE;")
59257ff7
RK		 10417
10418(define_expand "restore_stack_function"
ff381587
MM		 10419 [(match_operand 0 "any_operand" "")
10420 (match_operand 1 "any_operand" "")]
59257ff7 10421 ""
ff381587 10422 "DONE;")
59257ff7 10423
2eef28ec
AM		 10424;; Adjust stack pointer (op0) to a new value (op1).
10425;; First copy old stack backchain to new location, and ensure that the
10426;; scheduler won't reorder the sp assignment before the backchain write.
59257ff7 10427(define_expand "restore_stack_block"
2eef28ec
AM		 10428 [(set (match_dup 2) (match_dup 3))
10429 (set (match_dup 4) (match_dup 2))
10430 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10431 (set (match_operand 0 "register_operand" "")
10432 (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10433 ""
10434 "
dfdfa60f
DE		 10435{
10436 operands[2] = gen_reg_rtx (Pmode);
2eef28ec
AM		 10437 operands[3] = gen_frame_mem (Pmode, operands[0]);
10438 operands[4] = gen_frame_mem (Pmode, operands[1]);
10439 operands[5] = gen_frame_mem (BLKmode, operands[0]);
dfdfa60f 10440}")
59257ff7
RK		 10441
10442(define_expand "save_stack_nonlocal"
2eef28ec
AM		 10443 [(set (match_dup 3) (match_dup 4))
10444 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10445 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10446 ""
10447 "
10448{
11b25716 10449 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10450
10451 /* Copy the backchain to the first word, sp to the second. */
2eef28ec
AM		 10452 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10453 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10454 operands[3] = gen_reg_rtx (Pmode);
10455 operands[4] = gen_frame_mem (Pmode, operands[1]);
59257ff7 10456}")
7e69e155 10457
59257ff7 10458(define_expand "restore_stack_nonlocal"
2eef28ec
AM		 10459 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10460 (set (match_dup 3) (match_dup 4))
10461 (set (match_dup 5) (match_dup 2))
10462 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10463 (set (match_operand 0 "register_operand" "") (match_dup 3))]
59257ff7
RK		 10464 ""
10465 "
10466{
11b25716 10467 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10468
10469 /* Restore the backchain from the first word, sp from the second. */
2eef28ec
AM		 10470 operands[2] = gen_reg_rtx (Pmode);
10471 operands[3] = gen_reg_rtx (Pmode);
10472 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10473 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10474 operands[5] = gen_frame_mem (Pmode, operands[3]);
10475 operands[6] = gen_frame_mem (BLKmode, operands[0]);
59257ff7 10476}")
9ebbca7d
GK		 10477\f
10478;; TOC register handling.
b6c9286a 10479
9ebbca7d 10480;; Code to initialize the TOC register...
f0f6a223 10481
9ebbca7d 10482(define_insn "load_toc_aix_si"
e72247f4 10483 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 10484 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10485 (use (reg:SI 2))])]
2bfcf297 10486 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 10487 "*
10488{
9ebbca7d
GK		 10489 char buf[30];
10490 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 10491 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10492 operands[2] = gen_rtx_REG (Pmode, 2);
10493 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 10494}"
10495 [(set_attr "type" "load")])
9ebbca7d
GK		 10496
10497(define_insn "load_toc_aix_di"
e72247f4 10498 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 10499 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10500 (use (reg:DI 2))])]
2bfcf297 10501 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 10502 "*
10503{
10504 char buf[30];
f585a356
DE		 10505#ifdef TARGET_RELOCATABLE
10506 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10507 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10508#else
9ebbca7d 10509 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 10510#endif
2bfcf297
DB		 10511 if (TARGET_ELF)
10512 strcat (buf, \"@toc\");
a8a05998 10513 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10514 operands[2] = gen_rtx_REG (Pmode, 2);
10515 return \"ld %0,%1(%2)\";
10516}"
10517 [(set_attr "type" "load")])
10518
10519(define_insn "load_toc_v4_pic_si"
1de43f85 10520 [(set (reg:SI LR_REGNO)
615158e2 10521 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 10522 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 10523 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10524 [(set_attr "type" "branch")
10525 (set_attr "length" "4")])
10526
9ebbca7d 10527(define_insn "load_toc_v4_PIC_1"
1de43f85 10528 [(set (reg:SI LR_REGNO)
e65a3857
DE		 10529 (match_operand:SI 0 "immediate_operand" "s"))
10530 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
7f970b70
AM		 10531 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10532 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
e65a3857 10533 "bcl 20,31,%0\\n%0:"
9ebbca7d
GK		 10534 [(set_attr "type" "branch")
10535 (set_attr "length" "4")])
10536
10537(define_insn "load_toc_v4_PIC_1b"
1de43f85 10538 [(set (reg:SI LR_REGNO)
e65a3857 10539 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
c4501e62 10540 UNSPEC_TOCPTR))]
20b71b17 10541 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
e65a3857 10542 "bcl 20,31,$+8\\n\\t.long %0-$"
9ebbca7d
GK		 10543 [(set_attr "type" "branch")
10544 (set_attr "length" "8")])
10545
10546(define_insn "load_toc_v4_PIC_2"
f585a356 10547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 10548 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 10549 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10550 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 10551 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 10552 "{l|lwz} %0,%2-%3(%1)"
10553 [(set_attr "type" "load")])
10554
7f970b70
AM		 10555(define_insn "load_toc_v4_PIC_3b"
10556 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10557 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10558 (high:SI
10559 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10560 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10561 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10562 "{cau|addis} %0,%1,%2-%3@ha")
10563
10564(define_insn "load_toc_v4_PIC_3c"
10565 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10566 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10567 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10568 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10569 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10570 "{cal|addi} %0,%1,%2-%3@l")
f51eee6a 10571
9ebbca7d
GK		 10572;; If the TOC is shared over a translation unit, as happens with all
10573;; the kinds of PIC that we support, we need to restore the TOC
10574;; pointer only when jumping over units of translation.
f51eee6a 10575;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 10576
10577(define_expand "builtin_setjmp_receiver"
10578 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 10579 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 10580 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10581 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 10582 "
10583{
84d7dd4a 10584#if TARGET_MACHO
f51eee6a
GK		 10585 if (DEFAULT_ABI == ABI_DARWIN)
10586 {
d24652ee 10587 const char *picbase = machopic_function_base_name ();
485bad26 10588 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
f51eee6a
GK		 10589 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10590 rtx tmplabrtx;
10591 char tmplab[20];
10592
10593 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10594 CODE_LABEL_NUMBER (operands[0]));
485bad26 10595 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a 10596
316fbf19 10597 emit_insn (gen_load_macho_picbase (tmplabrtx));
1de43f85 10598 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
b8a55285 10599 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
f51eee6a
GK		 10600 }
10601 else
84d7dd4a 10602#endif
f51eee6a 10603 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 10604 DONE;
10605}")
7f970b70
AM		 10606
10607;; Elf specific ways of loading addresses for non-PIC code.
10608;; The output of this could be r0, but we make a very strong
10609;; preference for a base register because it will usually
10610;; be needed there.
10611(define_insn "elf_high"
10612 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10613 (high:SI (match_operand 1 "" "")))]
10614 "TARGET_ELF && ! TARGET_64BIT"
10615 "{liu|lis} %0,%1@ha")
10616
10617(define_insn "elf_low"
10618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10619 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10620 (match_operand 2 "" "")))]
10621 "TARGET_ELF && ! TARGET_64BIT"
10622 "@
10623 {cal|la} %0,%2@l(%1)
10624 {ai|addic} %0,%1,%K2")
9ebbca7d
GK		 10625\f
10626;; A function pointer under AIX is a pointer to a data area whose first word
10627;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 10628;; pointer to its TOC, and whose third word contains a value to place in the
10629;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 10630;; "trampoline" need not have any executable code.
b6c9286a 10631
cccf3bdc
DE		 10632(define_expand "call_indirect_aix32"
10633 [(set (match_dup 2)
10634 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10635 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10636 (reg:SI 2))
10637 (set (reg:SI 2)
10638 (mem:SI (plus:SI (match_dup 0)
10639 (const_int 4))))
10640 (set (reg:SI 11)
10641 (mem:SI (plus:SI (match_dup 0)
10642 (const_int 8))))
10643 (parallel [(call (mem:SI (match_dup 2))
10644 (match_operand 1 "" ""))
10645 (use (reg:SI 2))
10646 (use (reg:SI 11))
10647 (set (reg:SI 2)
10648 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10649 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10650 "TARGET_32BIT"
10651 "
10652{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 10653
cccf3bdc
DE		 10654(define_expand "call_indirect_aix64"
10655 [(set (match_dup 2)
10656 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10657 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10658 (reg:DI 2))
10659 (set (reg:DI 2)
10660 (mem:DI (plus:DI (match_dup 0)
10661 (const_int 8))))
10662 (set (reg:DI 11)
10663 (mem:DI (plus:DI (match_dup 0)
10664 (const_int 16))))
10665 (parallel [(call (mem:SI (match_dup 2))
10666 (match_operand 1 "" ""))
10667 (use (reg:DI 2))
10668 (use (reg:DI 11))
10669 (set (reg:DI 2)
10670 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10671 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10672 "TARGET_64BIT"
10673 "
10674{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 10675
cccf3bdc
DE		 10676(define_expand "call_value_indirect_aix32"
10677 [(set (match_dup 3)
10678 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10679 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10680 (reg:SI 2))
10681 (set (reg:SI 2)
10682 (mem:SI (plus:SI (match_dup 1)
10683 (const_int 4))))
10684 (set (reg:SI 11)
10685 (mem:SI (plus:SI (match_dup 1)
10686 (const_int 8))))
10687 (parallel [(set (match_operand 0 "" "")
10688 (call (mem:SI (match_dup 3))
10689 (match_operand 2 "" "")))
10690 (use (reg:SI 2))
10691 (use (reg:SI 11))
10692 (set (reg:SI 2)
10693 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10694 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10695 "TARGET_32BIT"
10696 "
10697{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 10698
cccf3bdc
DE		 10699(define_expand "call_value_indirect_aix64"
10700 [(set (match_dup 3)
10701 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10702 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10703 (reg:DI 2))
10704 (set (reg:DI 2)
10705 (mem:DI (plus:DI (match_dup 1)
10706 (const_int 8))))
10707 (set (reg:DI 11)
10708 (mem:DI (plus:DI (match_dup 1)
10709 (const_int 16))))
10710 (parallel [(set (match_operand 0 "" "")
10711 (call (mem:SI (match_dup 3))
10712 (match_operand 2 "" "")))
10713 (use (reg:DI 2))
10714 (use (reg:DI 11))
10715 (set (reg:DI 2)
10716 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10717 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10718 "TARGET_64BIT"
10719 "
10720{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 10721
b6c9286a 10722;; Now the definitions for the call and call_value insns
1fd4e8c1 10723(define_expand "call"
a260abc9 10724 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 10725 (match_operand 1 "" ""))
4697a36c 10726 (use (match_operand 2 "" ""))
1de43f85 10727 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 10728 ""
10729 "
10730{
ee890fe2 10731#if TARGET_MACHO
ab82a49f 10732 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10733 operands[0] = machopic_indirect_call_target (operands[0]);
10734#endif
10735
37409796
NS		 10736 gcc_assert (GET_CODE (operands[0]) == MEM);
10737 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
1fd4e8c1
RK		 10738
10739 operands[0] = XEXP (operands[0], 0);
7509c759 10740
7f970b70
AM		 10741 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10742 && flag_pic
10743 && GET_CODE (operands[0]) == SYMBOL_REF
10744 && !SYMBOL_REF_LOCAL_P (operands[0]))
10745 {
10746 rtx call;
10747 rtvec tmp;
10748
10749 tmp = gen_rtvec (3,
10750 gen_rtx_CALL (VOIDmode,
10751 gen_rtx_MEM (SImode, operands[0]),
10752 operands[1]),
10753 gen_rtx_USE (VOIDmode, operands[2]),
ee05ef56 10754 gen_rtx_CLOBBER (VOIDmode,
1de43f85 10755 gen_rtx_REG (Pmode, LR_REGNO)));
7f970b70
AM		 10756 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10757 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10758 DONE;
10759 }
10760
6a4cee5f 10761 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 10762 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
efdba735 10763 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
1fd4e8c1 10764 {
6a4cee5f
MM		 10765 if (INTVAL (operands[2]) & CALL_LONG)
10766 operands[0] = rs6000_longcall_ref (operands[0]);
10767
37409796
NS		 10768 switch (DEFAULT_ABI)
10769 {
10770 case ABI_V4:
10771 case ABI_DARWIN:
10772 operands[0] = force_reg (Pmode, operands[0]);
10773 break;
1fd4e8c1 10774
37409796 10775 case ABI_AIX:
cccf3bdc
DE		 10776 /* AIX function pointers are really pointers to a three word
10777 area. */
10778 emit_call_insn (TARGET_32BIT
10779 ? gen_call_indirect_aix32 (force_reg (SImode,
10780 operands[0]),
10781 operands[1])
10782 : gen_call_indirect_aix64 (force_reg (DImode,
10783 operands[0]),
10784 operands[1]));
10785 DONE;
37409796
NS		 10786
10787 default:
10788 gcc_unreachable ();
b6c9286a 10789 }
1fd4e8c1
RK		 10790 }
10791}")
10792
10793(define_expand "call_value"
10794 [(parallel [(set (match_operand 0 "" "")
a260abc9 10795 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 10796 (match_operand 2 "" "")))
4697a36c 10797 (use (match_operand 3 "" ""))
1de43f85 10798 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 10799 ""
10800 "
10801{
ee890fe2 10802#if TARGET_MACHO
ab82a49f 10803 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10804 operands[1] = machopic_indirect_call_target (operands[1]);
10805#endif
10806
37409796
NS		 10807 gcc_assert (GET_CODE (operands[1]) == MEM);
10808 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
1fd4e8c1
RK		 10809
10810 operands[1] = XEXP (operands[1], 0);
7509c759 10811
7f970b70
AM		 10812 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10813 && flag_pic
10814 && GET_CODE (operands[1]) == SYMBOL_REF
10815 && !SYMBOL_REF_LOCAL_P (operands[1]))
10816 {
10817 rtx call;
10818 rtvec tmp;
10819
10820 tmp = gen_rtvec (3,
10821 gen_rtx_SET (VOIDmode,
10822 operands[0],
10823 gen_rtx_CALL (VOIDmode,
10824 gen_rtx_MEM (SImode,
10825 operands[1]),
10826 operands[2])),
10827 gen_rtx_USE (VOIDmode, operands[3]),
ee05ef56 10828 gen_rtx_CLOBBER (VOIDmode,
1de43f85 10829 gen_rtx_REG (Pmode, LR_REGNO)));
7f970b70
AM		 10830 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10831 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10832 DONE;
10833 }
10834
6a4cee5f 10835 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 10836 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
efdba735 10837 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
1fd4e8c1 10838 {
6756293c 10839 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 10840 operands[1] = rs6000_longcall_ref (operands[1]);
10841
37409796
NS		 10842 switch (DEFAULT_ABI)
10843 {
10844 case ABI_V4:
10845 case ABI_DARWIN:
10846 operands[1] = force_reg (Pmode, operands[1]);
10847 break;
1fd4e8c1 10848
37409796 10849 case ABI_AIX:
cccf3bdc
DE		 10850 /* AIX function pointers are really pointers to a three word
10851 area. */
10852 emit_call_insn (TARGET_32BIT
10853 ? gen_call_value_indirect_aix32 (operands[0],
10854 force_reg (SImode,
10855 operands[1]),
10856 operands[2])
10857 : gen_call_value_indirect_aix64 (operands[0],
10858 force_reg (DImode,
10859 operands[1]),
10860 operands[2]));
10861 DONE;
37409796
NS		 10862
10863 default:
10864 gcc_unreachable ();
b6c9286a 10865 }
1fd4e8c1
RK		 10866 }
10867}")
10868
04780ee7 10869;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 10870;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10871;; either the function was not prototyped, or it was prototyped as a
10872;; variable argument function. It is > 0 if FP registers were passed
10873;; and < 0 if they were not.
04780ee7 10874
a260abc9 10875(define_insn "*call_local32"
4697a36c
MM		 10876 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10877 (match_operand 1 "" "g,g"))
10878 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 10879 (clobber (reg:SI LR_REGNO))]
5a19791c 10880 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 10881 "*
10882{
6a4cee5f
MM		 10883 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10884 output_asm_insn (\"crxor 6,6,6\", operands);
10885
10886 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10887 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 10888
a226df46 10889 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 10890}"
b7ff3d82
DE		 10891 [(set_attr "type" "branch")
10892 (set_attr "length" "4,8")])
04780ee7 10893
a260abc9
DE		 10894(define_insn "*call_local64"
10895 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10896 (match_operand 1 "" "g,g"))
10897 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 10898 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10899 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10900 "*
10901{
10902 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10903 output_asm_insn (\"crxor 6,6,6\", operands);
10904
10905 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10906 output_asm_insn (\"creqv 6,6,6\", operands);
10907
10908 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10909}"
10910 [(set_attr "type" "branch")
10911 (set_attr "length" "4,8")])
10912
cccf3bdc 10913(define_insn "*call_value_local32"
d18dba68 10914 [(set (match_operand 0 "" "")
a260abc9
DE		 10915 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10916 (match_operand 2 "" "g,g")))
10917 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 10918 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10919 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10920 "*
10921{
10922 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10923 output_asm_insn (\"crxor 6,6,6\", operands);
10924
10925 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10926 output_asm_insn (\"creqv 6,6,6\", operands);
10927
10928 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10929}"
10930 [(set_attr "type" "branch")
10931 (set_attr "length" "4,8")])
10932
10933
cccf3bdc 10934(define_insn "*call_value_local64"
d18dba68 10935 [(set (match_operand 0 "" "")
a260abc9
DE		 10936 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10937 (match_operand 2 "" "g,g")))
10938 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 10939 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10940 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10941 "*
10942{
10943 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10944 output_asm_insn (\"crxor 6,6,6\", operands);
10945
10946 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10947 output_asm_insn (\"creqv 6,6,6\", operands);
10948
10949 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10950}"
10951 [(set_attr "type" "branch")
10952 (set_attr "length" "4,8")])
10953
04780ee7 10954;; Call to function which may be in another module. Restore the TOC
911f679c 10955;; pointer (r2) after the call unless this is System V.
a0ab749a 10956;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10957;; either the function was not prototyped, or it was prototyped as a
10958;; variable argument function. It is > 0 if FP registers were passed
10959;; and < 0 if they were not.
04780ee7 10960
cccf3bdc 10961(define_insn "*call_indirect_nonlocal_aix32"
70ae0191
DE		 10962 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10963 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 10964 (use (reg:SI 2))
10965 (use (reg:SI 11))
10966 (set (reg:SI 2)
10967 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10968 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10969 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10970 "b%T0l\;{l|lwz} 2,20(1)"
10971 [(set_attr "type" "jmpreg")
10972 (set_attr "length" "8")])
10973
a260abc9 10974(define_insn "*call_nonlocal_aix32"
cc4d5fec 10975 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10976 (match_operand 1 "" "g"))
10977 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 10978 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10979 "TARGET_32BIT
10980 && DEFAULT_ABI == ABI_AIX
5a19791c 10981 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10982 "bl %z0\;%."
b7ff3d82 10983 [(set_attr "type" "branch")
cccf3bdc
DE		 10984 (set_attr "length" "8")])
10985
10986(define_insn "*call_indirect_nonlocal_aix64"
70ae0191
DE		 10987 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10988 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 10989 (use (reg:DI 2))
10990 (use (reg:DI 11))
10991 (set (reg:DI 2)
10992 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10993 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10994 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10995 "b%T0l\;ld 2,40(1)"
10996 [(set_attr "type" "jmpreg")
10997 (set_attr "length" "8")])
59313e4e 10998
a260abc9 10999(define_insn "*call_nonlocal_aix64"
cc4d5fec 11000 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11001 (match_operand 1 "" "g"))
11002 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11003 (clobber (reg:SI LR_REGNO))]
6ae08853 11004 "TARGET_64BIT
9ebbca7d 11005 && DEFAULT_ABI == ABI_AIX
a260abc9 11006 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 11007 "bl %z0\;%."
a260abc9 11008 [(set_attr "type" "branch")
cccf3bdc 11009 (set_attr "length" "8")])
7509c759 11010
cccf3bdc 11011(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 11012 [(set (match_operand 0 "" "")
70ae0191
DE		 11013 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11014 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11015 (use (reg:SI 2))
11016 (use (reg:SI 11))
11017 (set (reg:SI 2)
11018 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11019 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11020 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11021 "b%T1l\;{l|lwz} 2,20(1)"
11022 [(set_attr "type" "jmpreg")
11023 (set_attr "length" "8")])
1fd4e8c1 11024
cccf3bdc 11025(define_insn "*call_value_nonlocal_aix32"
d18dba68 11026 [(set (match_operand 0 "" "")
cc4d5fec 11027 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11028 (match_operand 2 "" "g")))
11029 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11030 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11031 "TARGET_32BIT
11032 && DEFAULT_ABI == ABI_AIX
a260abc9 11033 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 11034 "bl %z1\;%."
b7ff3d82 11035 [(set_attr "type" "branch")
cccf3bdc 11036 (set_attr "length" "8")])
04780ee7 11037
cccf3bdc 11038(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 11039 [(set (match_operand 0 "" "")
70ae0191
DE		 11040 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11041 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11042 (use (reg:DI 2))
11043 (use (reg:DI 11))
11044 (set (reg:DI 2)
11045 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11046 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11047 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11048 "b%T1l\;ld 2,40(1)"
11049 [(set_attr "type" "jmpreg")
11050 (set_attr "length" "8")])
11051
11052(define_insn "*call_value_nonlocal_aix64"
d18dba68 11053 [(set (match_operand 0 "" "")
cc4d5fec 11054 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11055 (match_operand 2 "" "g")))
11056 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11057 (clobber (reg:SI LR_REGNO))]
6ae08853 11058 "TARGET_64BIT
9ebbca7d 11059 && DEFAULT_ABI == ABI_AIX
5a19791c 11060 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 11061 "bl %z1\;%."
11062 [(set_attr "type" "branch")
11063 (set_attr "length" "8")])
11064
11065;; A function pointer under System V is just a normal pointer
11066;; operands[0] is the function pointer
11067;; operands[1] is the stack size to clean up
11068;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11069;; which indicates how to set cr1
11070
9613eaff
SH		 11071(define_insn "*call_indirect_nonlocal_sysv<mode>"
11072 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11073 (match_operand 1 "" "g,g,g,g"))
11074 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
1de43f85 11075 (clobber (reg:SI LR_REGNO))]
50d440bc 11076 "DEFAULT_ABI == ABI_V4
f607bc57 11077 || DEFAULT_ABI == ABI_DARWIN"
911f679c 11078{
cccf3bdc 11079 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11080 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 11081
cccf3bdc 11082 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11083 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11084
a5c76ee6
ZW		 11085 return "b%T0l";
11086}
6d0a8091
DJ		 11087 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11088 (set_attr "length" "4,4,8,8")])
cccf3bdc 11089
9613eaff
SH		 11090(define_insn "*call_nonlocal_sysv<mode>"
11091 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11092 (match_operand 1 "" "g,g"))
11093 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11094 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11095 "(DEFAULT_ABI == ABI_DARWIN
11096 || (DEFAULT_ABI == ABI_V4
11097 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11098{
11099 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11100 output_asm_insn ("crxor 6,6,6", operands);
11101
11102 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11103 output_asm_insn ("creqv 6,6,6", operands);
11104
c989f2f7 11105#if TARGET_MACHO
efdba735
SH		 11106 return output_call(insn, operands, 0, 2);
11107#else
7f970b70
AM		 11108 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11109 {
11110 if (TARGET_SECURE_PLT && flag_pic == 2)
11111 /* The magic 32768 offset here and in the other sysv call insns
11112 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11113 See sysv4.h:toc_section. */
11114 return "bl %z0+32768@plt";
11115 else
11116 return "bl %z0@plt";
11117 }
11118 else
11119 return "bl %z0";
6ae08853 11120#endif
a5c76ee6
ZW		 11121}
11122 [(set_attr "type" "branch,branch")
11123 (set_attr "length" "4,8")])
11124
9613eaff 11125(define_insn "*call_value_indirect_nonlocal_sysv<mode>"
d18dba68 11126 [(set (match_operand 0 "" "")
9613eaff 11127 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11128 (match_operand 2 "" "g,g,g,g")))
11129 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
1de43f85 11130 (clobber (reg:SI LR_REGNO))]
50d440bc 11131 "DEFAULT_ABI == ABI_V4
f607bc57 11132 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 11133{
6a4cee5f 11134 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11135 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 11136
11137 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11138 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11139
a5c76ee6
ZW		 11140 return "b%T1l";
11141}
6d0a8091
DJ		 11142 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11143 (set_attr "length" "4,4,8,8")])
a5c76ee6 11144
9613eaff 11145(define_insn "*call_value_nonlocal_sysv<mode>"
a5c76ee6 11146 [(set (match_operand 0 "" "")
9613eaff 11147 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11148 (match_operand 2 "" "g,g")))
11149 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11150 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11151 "(DEFAULT_ABI == ABI_DARWIN
11152 || (DEFAULT_ABI == ABI_V4
11153 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11154{
11155 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11156 output_asm_insn ("crxor 6,6,6", operands);
11157
11158 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11159 output_asm_insn ("creqv 6,6,6", operands);
11160
c989f2f7 11161#if TARGET_MACHO
efdba735
SH		 11162 return output_call(insn, operands, 1, 3);
11163#else
7f970b70
AM		 11164 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11165 {
11166 if (TARGET_SECURE_PLT && flag_pic == 2)
11167 return "bl %z1+32768@plt";
11168 else
11169 return "bl %z1@plt";
11170 }
11171 else
11172 return "bl %z1";
6ae08853 11173#endif
a5c76ee6
ZW		 11174}
11175 [(set_attr "type" "branch,branch")
11176 (set_attr "length" "4,8")])
e6f948e3
RK		 11177
11178;; Call subroutine returning any type.
e6f948e3
RK		 11179(define_expand "untyped_call"
11180 [(parallel [(call (match_operand 0 "" "")
11181 (const_int 0))
11182 (match_operand 1 "" "")
11183 (match_operand 2 "" "")])]
11184 ""
11185 "
11186{
11187 int i;
11188
7d70b8b2 11189 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 11190
11191 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11192 {
11193 rtx set = XVECEXP (operands[2], 0, i);
11194 emit_move_insn (SET_DEST (set), SET_SRC (set));
11195 }
11196
11197 /* The optimizer does not know that the call sets the function value
11198 registers we stored in the result block. We avoid problems by
11199 claiming that all hard registers are used and clobbered at this
11200 point. */
11201 emit_insn (gen_blockage ());
11202
11203 DONE;
11204}")
11205
5e1bf043
DJ		 11206;; sibling call patterns
11207(define_expand "sibcall"
11208 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11209 (match_operand 1 "" ""))
11210 (use (match_operand 2 "" ""))
1de43f85 11211 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11212 (return)])]
11213 ""
11214 "
11215{
11216#if TARGET_MACHO
ab82a49f 11217 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11218 operands[0] = machopic_indirect_call_target (operands[0]);
11219#endif
11220
37409796
NS		 11221 gcc_assert (GET_CODE (operands[0]) == MEM);
11222 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5e1bf043
DJ		 11223
11224 operands[0] = XEXP (operands[0], 0);
5e1bf043
DJ		 11225}")
11226
11227;; this and similar patterns must be marked as using LR, otherwise
11228;; dataflow will try to delete the store into it. This is true
11229;; even when the actual reg to jump to is in CTR, when LR was
11230;; saved and restored around the PIC-setting BCL.
11231(define_insn "*sibcall_local32"
11232 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11233 (match_operand 1 "" "g,g"))
11234 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11235 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11236 (return)]
11237 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11238 "*
11239{
11240 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11241 output_asm_insn (\"crxor 6,6,6\", operands);
11242
11243 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11244 output_asm_insn (\"creqv 6,6,6\", operands);
11245
11246 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11247}"
11248 [(set_attr "type" "branch")
11249 (set_attr "length" "4,8")])
11250
11251(define_insn "*sibcall_local64"
11252 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11253 (match_operand 1 "" "g,g"))
11254 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11255 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11256 (return)]
11257 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11258 "*
11259{
11260 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11261 output_asm_insn (\"crxor 6,6,6\", operands);
11262
11263 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11264 output_asm_insn (\"creqv 6,6,6\", operands);
11265
11266 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11267}"
11268 [(set_attr "type" "branch")
11269 (set_attr "length" "4,8")])
11270
11271(define_insn "*sibcall_value_local32"
11272 [(set (match_operand 0 "" "")
11273 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11274 (match_operand 2 "" "g,g")))
11275 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11276 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11277 (return)]
11278 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11279 "*
11280{
11281 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11282 output_asm_insn (\"crxor 6,6,6\", operands);
11283
11284 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11285 output_asm_insn (\"creqv 6,6,6\", operands);
11286
11287 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11288}"
11289 [(set_attr "type" "branch")
11290 (set_attr "length" "4,8")])
11291
11292
11293(define_insn "*sibcall_value_local64"
11294 [(set (match_operand 0 "" "")
11295 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11296 (match_operand 2 "" "g,g")))
11297 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11298 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11299 (return)]
11300 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11301 "*
11302{
11303 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11304 output_asm_insn (\"crxor 6,6,6\", operands);
11305
11306 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11307 output_asm_insn (\"creqv 6,6,6\", operands);
11308
11309 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11310}"
11311 [(set_attr "type" "branch")
11312 (set_attr "length" "4,8")])
11313
11314(define_insn "*sibcall_nonlocal_aix32"
11315 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11316 (match_operand 1 "" "g"))
11317 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11318 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11319 (return)]
11320 "TARGET_32BIT
11321 && DEFAULT_ABI == ABI_AIX
11322 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11323 "b %z0"
11324 [(set_attr "type" "branch")
11325 (set_attr "length" "4")])
11326
11327(define_insn "*sibcall_nonlocal_aix64"
11328 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11329 (match_operand 1 "" "g"))
11330 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11331 (use (reg:SI LR_REGNO))
5e1bf043 11332 (return)]
6ae08853 11333 "TARGET_64BIT
5e1bf043
DJ		 11334 && DEFAULT_ABI == ABI_AIX
11335 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11336 "b %z0"
11337 [(set_attr "type" "branch")
11338 (set_attr "length" "4")])
11339
11340(define_insn "*sibcall_value_nonlocal_aix32"
11341 [(set (match_operand 0 "" "")
11342 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11343 (match_operand 2 "" "g")))
11344 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11345 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11346 (return)]
11347 "TARGET_32BIT
11348 && DEFAULT_ABI == ABI_AIX
11349 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11350 "b %z1"
11351 [(set_attr "type" "branch")
11352 (set_attr "length" "4")])
11353
11354(define_insn "*sibcall_value_nonlocal_aix64"
11355 [(set (match_operand 0 "" "")
11356 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11357 (match_operand 2 "" "g")))
11358 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11359 (use (reg:SI LR_REGNO))
5e1bf043 11360 (return)]
6ae08853 11361 "TARGET_64BIT
5e1bf043
DJ		 11362 && DEFAULT_ABI == ABI_AIX
11363 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11364 "b %z1"
11365 [(set_attr "type" "branch")
11366 (set_attr "length" "4")])
11367
9613eaff
SH		 11368(define_insn "*sibcall_nonlocal_sysv<mode>"
11369 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11370 (match_operand 1 "" ""))
11371 (use (match_operand 2 "immediate_operand" "O,n"))
1de43f85 11372 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11373 (return)]
11374 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11375 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11376 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11377 "*
11378{
11379 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11380 output_asm_insn (\"crxor 6,6,6\", operands);
11381
11382 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11383 output_asm_insn (\"creqv 6,6,6\", operands);
11384
7f970b70
AM		 11385 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11386 {
11387 if (TARGET_SECURE_PLT && flag_pic == 2)
11388 return \"b %z0+32768@plt\";
11389 else
11390 return \"b %z0@plt\";
11391 }
11392 else
11393 return \"b %z0\";
5e1bf043
DJ		 11394}"
11395 [(set_attr "type" "branch,branch")
11396 (set_attr "length" "4,8")])
11397
11398(define_expand "sibcall_value"
11399 [(parallel [(set (match_operand 0 "register_operand" "")
11400 (call (mem:SI (match_operand 1 "address_operand" ""))
11401 (match_operand 2 "" "")))
11402 (use (match_operand 3 "" ""))
1de43f85 11403 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11404 (return)])]
11405 ""
11406 "
11407{
11408#if TARGET_MACHO
ab82a49f 11409 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11410 operands[1] = machopic_indirect_call_target (operands[1]);
11411#endif
11412
37409796
NS		 11413 gcc_assert (GET_CODE (operands[1]) == MEM);
11414 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5e1bf043
DJ		 11415
11416 operands[1] = XEXP (operands[1], 0);
5e1bf043
DJ		 11417}")
11418
9613eaff 11419(define_insn "*sibcall_value_nonlocal_sysv<mode>"
5e1bf043 11420 [(set (match_operand 0 "" "")
9613eaff 11421 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11422 (match_operand 2 "" "")))
11423 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11424 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11425 (return)]
11426 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11427 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11428 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11429 "*
11430{
11431 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11432 output_asm_insn (\"crxor 6,6,6\", operands);
11433
11434 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11435 output_asm_insn (\"creqv 6,6,6\", operands);
11436
7f970b70
AM		 11437 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11438 {
11439 if (TARGET_SECURE_PLT && flag_pic == 2)
11440 return \"b %z1+32768@plt\";
11441 else
11442 return \"b %z1@plt\";
11443 }
11444 else
11445 return \"b %z1\";
5e1bf043
DJ		 11446}"
11447 [(set_attr "type" "branch,branch")
11448 (set_attr "length" "4,8")])
11449
11450(define_expand "sibcall_epilogue"
11451 [(use (const_int 0))]
11452 "TARGET_SCHED_PROLOG"
11453 "
11454{
11455 rs6000_emit_epilogue (TRUE);
11456 DONE;
11457}")
11458
e6f948e3
RK		 11459;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11460;; all of memory. This blocks insns from being moved across this point.
11461
11462(define_insn "blockage"
615158e2 11463 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 11464 ""
11465 "")
1fd4e8c1
RK		 11466\f
11467;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 11468;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 11469;;
11470;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11471;; insns, and branches. We store the operands of compares until we see
11472;; how it is used.
4ae234b0 11473(define_expand "cmp<mode>"
1fd4e8c1 11474 [(set (cc0)
4ae234b0
GK		 11475 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11476 (match_operand:GPR 1 "reg_or_short_operand" "")))]
1fd4e8c1
RK		 11477 ""
11478 "
11479{
11480 /* Take care of the possibility that operands[1] might be negative but
11481 this might be a logical operation. That insn doesn't exist. */
11482 if (GET_CODE (operands[1]) == CONST_INT
11483 && INTVAL (operands[1]) < 0)
4ae234b0 11484 operands[1] = force_reg (<MODE>mode, operands[1]);
1fd4e8c1
RK		 11485
11486 rs6000_compare_op0 = operands[0];
11487 rs6000_compare_op1 = operands[1];
11488 rs6000_compare_fp_p = 0;
11489 DONE;
11490}")
11491
4ae234b0
GK		 11492(define_expand "cmp<mode>"
11493 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11494 (match_operand:FP 1 "gpc_reg_operand" "")))]
11495 ""
d6f99ca4
DE		 11496 "
11497{
11498 rs6000_compare_op0 = operands[0];
11499 rs6000_compare_op1 = operands[1];
11500 rs6000_compare_fp_p = 1;
11501 DONE;
11502}")
11503
1fd4e8c1 11504(define_expand "beq"
39a10a29 11505 [(use (match_operand 0 "" ""))]
1fd4e8c1 11506 ""
39a10a29 11507 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11508
11509(define_expand "bne"
39a10a29 11510 [(use (match_operand 0 "" ""))]
1fd4e8c1 11511 ""
39a10a29 11512 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
1fd4e8c1 11513
39a10a29
GK		 11514(define_expand "bge"
11515 [(use (match_operand 0 "" ""))]
1fd4e8c1 11516 ""
39a10a29 11517 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
1fd4e8c1
RK		 11518
11519(define_expand "bgt"
39a10a29 11520 [(use (match_operand 0 "" ""))]
1fd4e8c1 11521 ""
39a10a29 11522 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
1fd4e8c1
RK		 11523
11524(define_expand "ble"
39a10a29 11525 [(use (match_operand 0 "" ""))]
1fd4e8c1 11526 ""
39a10a29 11527 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
1fd4e8c1 11528
39a10a29
GK		 11529(define_expand "blt"
11530 [(use (match_operand 0 "" ""))]
1fd4e8c1 11531 ""
39a10a29 11532 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
1fd4e8c1 11533
39a10a29
GK		 11534(define_expand "bgeu"
11535 [(use (match_operand 0 "" ""))]
1fd4e8c1 11536 ""
39a10a29 11537 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
1fd4e8c1 11538
39a10a29
GK		 11539(define_expand "bgtu"
11540 [(use (match_operand 0 "" ""))]
1fd4e8c1 11541 ""
39a10a29 11542 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
1fd4e8c1 11543
39a10a29
GK		 11544(define_expand "bleu"
11545 [(use (match_operand 0 "" ""))]
1fd4e8c1 11546 ""
39a10a29 11547 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
1fd4e8c1 11548
39a10a29
GK		 11549(define_expand "bltu"
11550 [(use (match_operand 0 "" ""))]
1fd4e8c1 11551 ""
39a10a29 11552 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
1fd4e8c1 11553
1c882ea4 11554(define_expand "bunordered"
39a10a29 11555 [(use (match_operand 0 "" ""))]
8ef65e3d 11556 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11557 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11558
11559(define_expand "bordered"
39a10a29 11560 [(use (match_operand 0 "" ""))]
8ef65e3d 11561 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11562 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11563
11564(define_expand "buneq"
39a10a29 11565 [(use (match_operand 0 "" ""))]
b26941b4 11566 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11567 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
1c882ea4
GK		 11568
11569(define_expand "bunge"
39a10a29 11570 [(use (match_operand 0 "" ""))]
b26941b4 11571 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11572 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
1c882ea4
GK		 11573
11574(define_expand "bungt"
39a10a29 11575 [(use (match_operand 0 "" ""))]
b26941b4 11576 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11577 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
1c882ea4
GK		 11578
11579(define_expand "bunle"
39a10a29 11580 [(use (match_operand 0 "" ""))]
b26941b4 11581 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11582 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
1c882ea4
GK		 11583
11584(define_expand "bunlt"
39a10a29 11585 [(use (match_operand 0 "" ""))]
b26941b4 11586 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11587 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
1c882ea4
GK		 11588
11589(define_expand "bltgt"
39a10a29 11590 [(use (match_operand 0 "" ""))]
1c882ea4 11591 ""
39a10a29 11592 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
1c882ea4 11593
1fd4e8c1
RK		 11594;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11595;; For SEQ, likewise, except that comparisons with zero should be done
11596;; with an scc insns. However, due to the order that combine see the
11597;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11598;; the cases we don't want to handle.
11599(define_expand "seq"
39a10a29 11600 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11601 ""
39a10a29 11602 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11603
11604(define_expand "sne"
39a10a29 11605 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11606 ""
11607 "
6ae08853 11608{
39a10a29 11609 if (! rs6000_compare_fp_p)
1fd4e8c1
RK		 11610 FAIL;
11611
6ae08853 11612 rs6000_emit_sCOND (NE, operands[0]);
39a10a29 11613 DONE;
1fd4e8c1
RK		 11614}")
11615
b7053a3f
GK		 11616;; A >= 0 is best done the portable way for A an integer.
11617(define_expand "sge"
39a10a29 11618 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11619 ""
11620 "
5638268e 11621{
e56d7409 11622 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11623 FAIL;
11624
b7053a3f 11625 rs6000_emit_sCOND (GE, operands[0]);
39a10a29 11626 DONE;
1fd4e8c1
RK		 11627}")
11628
b7053a3f
GK		 11629;; A > 0 is best done using the portable sequence, so fail in that case.
11630(define_expand "sgt"
39a10a29 11631 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11632 ""
11633 "
5638268e 11634{
e56d7409 11635 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11636 FAIL;
11637
6ae08853 11638 rs6000_emit_sCOND (GT, operands[0]);
39a10a29 11639 DONE;
1fd4e8c1
RK		 11640}")
11641
b7053a3f
GK		 11642;; A <= 0 is best done the portable way for A an integer.
11643(define_expand "sle"
39a10a29 11644 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11645 ""
5638268e
DE		 11646 "
11647{
e56d7409 11648 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5638268e
DE		 11649 FAIL;
11650
6ae08853 11651 rs6000_emit_sCOND (LE, operands[0]);
5638268e
DE		 11652 DONE;
11653}")
1fd4e8c1 11654
b7053a3f
GK		 11655;; A < 0 is best done in the portable way for A an integer.
11656(define_expand "slt"
39a10a29 11657 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11658 ""
11659 "
5638268e 11660{
e56d7409 11661 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11662 FAIL;
11663
6ae08853 11664 rs6000_emit_sCOND (LT, operands[0]);
39a10a29 11665 DONE;
1fd4e8c1
RK		 11666}")
11667
b7053a3f
GK		 11668(define_expand "sgeu"
11669 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11670 ""
11671 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11672
1fd4e8c1 11673(define_expand "sgtu"
39a10a29 11674 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11675 ""
39a10a29 11676 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
1fd4e8c1 11677
b7053a3f
GK		 11678(define_expand "sleu"
11679 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11680 ""
11681 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11682
1fd4e8c1 11683(define_expand "sltu"
39a10a29 11684 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11685 ""
39a10a29 11686 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
1fd4e8c1 11687
b7053a3f 11688(define_expand "sunordered"
39a10a29 11689 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11690 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f 11691 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
1fd4e8c1 11692
b7053a3f 11693(define_expand "sordered"
39a10a29 11694 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11695 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11696 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11697
11698(define_expand "suneq"
11699 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11700 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11701 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11702
11703(define_expand "sunge"
11704 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11705 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11706 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11707
11708(define_expand "sungt"
11709 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11710 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11711 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11712
11713(define_expand "sunle"
11714 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11715 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11716 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11717
11718(define_expand "sunlt"
11719 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11720 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11721 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11722
11723(define_expand "sltgt"
11724 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11725 ""
11726 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11727
3aebbe5f
JJ		 11728(define_expand "stack_protect_set"
11729 [(match_operand 0 "memory_operand" "")
11730 (match_operand 1 "memory_operand" "")]
11731 ""
11732{
77008252
JJ		 11733#ifdef TARGET_THREAD_SSP_OFFSET
11734 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11735 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11736 operands[1] = gen_rtx_MEM (Pmode, addr);
11737#endif
3aebbe5f
JJ		 11738 if (TARGET_64BIT)
11739 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11740 else
11741 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11742 DONE;
11743})
11744
11745(define_insn "stack_protect_setsi"
11746 [(set (match_operand:SI 0 "memory_operand" "=m")
11747 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11748 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11749 "TARGET_32BIT"
11750 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11751 [(set_attr "type" "three")
11752 (set_attr "length" "12")])
11753
11754(define_insn "stack_protect_setdi"
11755 [(set (match_operand:DI 0 "memory_operand" "=m")
11756 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11757 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11758 "TARGET_64BIT"
11759 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11760 [(set_attr "type" "three")
11761 (set_attr "length" "12")])
11762
11763(define_expand "stack_protect_test"
11764 [(match_operand 0 "memory_operand" "")
11765 (match_operand 1 "memory_operand" "")
11766 (match_operand 2 "" "")]
11767 ""
11768{
77008252
JJ		 11769#ifdef TARGET_THREAD_SSP_OFFSET
11770 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11771 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11772 operands[1] = gen_rtx_MEM (Pmode, addr);
11773#endif
3aebbe5f
JJ		 11774 rs6000_compare_op0 = operands[0];
11775 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11776 UNSPEC_SP_TEST);
11777 rs6000_compare_fp_p = 0;
11778 emit_jump_insn (gen_beq (operands[2]));
11779 DONE;
11780})
11781
11782(define_insn "stack_protect_testsi"
11783 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11784 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11785 (match_operand:SI 2 "memory_operand" "m,m")]
11786 UNSPEC_SP_TEST))
41f12ed0
JJ		 11787 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11788 (clobber (match_scratch:SI 3 "=&r,&r"))]
3aebbe5f
JJ		 11789 "TARGET_32BIT"
11790 "@
11791 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11792 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11793 [(set_attr "length" "16,20")])
11794
11795(define_insn "stack_protect_testdi"
11796 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11797 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11798 (match_operand:DI 2 "memory_operand" "m,m")]
11799 UNSPEC_SP_TEST))
41f12ed0
JJ		 11800 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11801 (clobber (match_scratch:DI 3 "=&r,&r"))]
3aebbe5f
JJ		 11802 "TARGET_64BIT"
11803 "@
11804 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11805 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11806 [(set_attr "length" "16,20")])
11807
1fd4e8c1
RK		 11808\f
11809;; Here are the actual compare insns.
4ae234b0 11810(define_insn "*cmp<mode>_internal1"
1fd4e8c1 11811 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
4ae234b0
GK		 11812 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11813 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
1fd4e8c1 11814 ""
4ae234b0 11815 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
b54cf83a 11816 [(set_attr "type" "cmp")])
266eb58a 11817
f357808b 11818;; If we are comparing a register for equality with a large constant,
28d0e143
PB		 11819;; we can do this with an XOR followed by a compare. But this is profitable
11820;; only if the large constant is only used for the comparison (and in this
11821;; case we already have a register to reuse as scratch).
130869aa
PB		 11822;;
11823;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11824;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
f357808b 11825
28d0e143 11826(define_peephole2
130869aa 11827 [(set (match_operand:SI 0 "register_operand")
410c459d 11828 (match_operand:SI 1 "logical_const_operand" ""))
130869aa 11829 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
28d0e143 11830 [(match_dup 0)
410c459d 11831 (match_operand:SI 2 "logical_const_operand" "")]))
28d0e143 11832 (set (match_operand:CC 4 "cc_reg_operand" "")
130869aa 11833 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
28d0e143
PB		 11834 (match_dup 0)))
11835 (set (pc)
11836 (if_then_else (match_operator 6 "equality_operator"
11837 [(match_dup 4) (const_int 0)])
11838 (match_operand 7 "" "")
11839 (match_operand 8 "" "")))]
130869aa
PB		 11840 "peep2_reg_dead_p (3, operands[0])
11841 && peep2_reg_dead_p (4, operands[4])"
11842 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
28d0e143
PB		 11843 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11844 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11845
11846{
11847 /* Get the constant we are comparing against, and see what it looks like
11848 when sign-extended from 16 to 32 bits. Then see what constant we could
11849 XOR with SEXTC to get the sign-extended value. */
11850 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
130869aa 11851 SImode,
28d0e143
PB		 11852 operands[1], operands[2]);
11853 HOST_WIDE_INT c = INTVAL (cnst);
a65c591c 11854 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 11855 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 11856
28d0e143
PB		 11857 operands[9] = GEN_INT (xorv);
11858 operands[10] = GEN_INT (sextc);
11859})
f357808b 11860
acad7ed3 11861(define_insn "*cmpsi_internal2"
1fd4e8c1 11862 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 11863 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 11864 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 11865 ""
e2c953b6 11866 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 11867 [(set_attr "type" "cmp")])
1fd4e8c1 11868
acad7ed3 11869(define_insn "*cmpdi_internal2"
266eb58a
DE		 11870 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11871 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 11872 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 11873 ""
e2c953b6 11874 "cmpld%I2 %0,%1,%b2"
b54cf83a 11875 [(set_attr "type" "cmp")])
266eb58a 11876
1fd4e8c1
RK		 11877;; The following two insns don't exist as single insns, but if we provide
11878;; them, we can swap an add and compare, which will enable us to overlap more
11879;; of the required delay between a compare and branch. We generate code for
11880;; them by splitting.
11881
11882(define_insn ""
11883 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 11884 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11885 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 11886 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11887 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11888 ""
baf97f86
RK		 11889 "#"
11890 [(set_attr "length" "8")])
7e69e155 11891
1fd4e8c1
RK		 11892(define_insn ""
11893 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 11894 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11895 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 11896 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11897 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11898 ""
baf97f86
RK		 11899 "#"
11900 [(set_attr "length" "8")])
7e69e155 11901
1fd4e8c1
RK		 11902(define_split
11903 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 11904 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11905 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 11906 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11907 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11908 ""
11909 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11910 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11911
11912(define_split
11913 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 11914 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11915 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 11916 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11917 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11918 ""
11919 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11920 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11921
acad7ed3 11922(define_insn "*cmpsf_internal1"
1fd4e8c1 11923 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11924 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11925 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 11926 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11927 "fcmpu %0,%1,%2"
11928 [(set_attr "type" "fpcompare")])
11929
acad7ed3 11930(define_insn "*cmpdf_internal1"
1fd4e8c1 11931 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11932 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11933 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 11934 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11935 "fcmpu %0,%1,%2"
11936 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 11937
11938;; Only need to compare second words if first words equal
11939(define_insn "*cmptf_internal1"
11940 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11941 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11942 (match_operand:TF 2 "gpc_reg_operand" "f")))]
602ea4d3 11943 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
39e63627 11944 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 11945 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 11946 [(set_attr "type" "fpcompare")
11947 (set_attr "length" "12")])
de17c25f
DE		 11948
11949(define_insn_and_split "*cmptf_internal2"
11950 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11951 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11952 (match_operand:TF 2 "gpc_reg_operand" "f")))
11953 (clobber (match_scratch:DF 3 "=f"))
11954 (clobber (match_scratch:DF 4 "=f"))
11955 (clobber (match_scratch:DF 5 "=f"))
11956 (clobber (match_scratch:DF 6 "=f"))
11957 (clobber (match_scratch:DF 7 "=f"))
11958 (clobber (match_scratch:DF 8 "=f"))
11959 (clobber (match_scratch:DF 9 "=f"))
11960 (clobber (match_scratch:DF 10 "=f"))]
602ea4d3 11961 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
de17c25f
DE		 11962 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11963 "#"
11964 "&& reload_completed"
11965 [(set (match_dup 3) (match_dup 13))
11966 (set (match_dup 4) (match_dup 14))
11967 (set (match_dup 9) (abs:DF (match_dup 5)))
11968 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11969 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11970 (label_ref (match_dup 11))
11971 (pc)))
11972 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11973 (set (pc) (label_ref (match_dup 12)))
11974 (match_dup 11)
11975 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11976 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11977 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11978 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11979 (match_dup 12)]
11980{
11981 REAL_VALUE_TYPE rv;
11982 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11983 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11984
11985 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11986 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11987 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11988 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11989 operands[11] = gen_label_rtx ();
11990 operands[12] = gen_label_rtx ();
11991 real_inf (&rv);
11992 operands[13] = force_const_mem (DFmode,
11993 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11994 operands[14] = force_const_mem (DFmode,
11995 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11996 DFmode));
11997 if (TARGET_TOC)
11998 {
11999 operands[13] = gen_const_mem (DFmode,
12000 create_TOC_reference (XEXP (operands[13], 0)));
12001 operands[14] = gen_const_mem (DFmode,
12002 create_TOC_reference (XEXP (operands[14], 0)));
12003 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12004 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12005 }
12006})
1fd4e8c1
RK		 12007\f
12008;; Now we have the scc insns. We can do some combinations because of the
12009;; way the machine works.
12010;;
12011;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 12012;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12013;; cases the insns below which don't use an intermediate CR field will
12014;; be used instead.
1fd4e8c1 12015(define_insn ""
cd2b37d9 12016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12017 (match_operator:SI 1 "scc_comparison_operator"
12018 [(match_operand 2 "cc_reg_operand" "y")
12019 (const_int 0)]))]
12020 ""
2c4a9cff
DE		 12021 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12022 [(set (attr "type")
12023 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12024 (const_string "mfcrf")
12025 ]
12026 (const_string "mfcr")))
c1618c0c 12027 (set_attr "length" "8")])
1fd4e8c1 12028
423c1189 12029;; Same as above, but get the GT bit.
64022b5d 12030(define_insn "move_from_CR_gt_bit"
423c1189 12031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
64022b5d 12032 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
423c1189 12033 "TARGET_E500"
64022b5d 12034 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
423c1189 12035 [(set_attr "type" "mfcr")
c1618c0c 12036 (set_attr "length" "8")])
423c1189 12037
a3170dc6
AH		 12038;; Same as above, but get the OV/ORDERED bit.
12039(define_insn "move_from_CR_ov_bit"
12040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 12041 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 12042 "TARGET_ISEL"
b7053a3f 12043 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a 12044 [(set_attr "type" "mfcr")
c1618c0c 12045 (set_attr "length" "8")])
a3170dc6 12046
1fd4e8c1 12047(define_insn ""
9ebbca7d
GK		 12048 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12049 (match_operator:DI 1 "scc_comparison_operator"
12050 [(match_operand 2 "cc_reg_operand" "y")
12051 (const_int 0)]))]
12052 "TARGET_POWERPC64"
2c4a9cff
DE		 12053 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12054 [(set (attr "type")
12055 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12056 (const_string "mfcrf")
12057 ]
12058 (const_string "mfcr")))
c1618c0c 12059 (set_attr "length" "8")])
9ebbca7d
GK		 12060
12061(define_insn ""
12062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12063 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12064 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 12065 (const_int 0)])
12066 (const_int 0)))
9ebbca7d 12067 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 12068 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12069 "TARGET_32BIT"
9ebbca7d 12070 "@
2c4a9cff 12071 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 12072 #"
b19003d8 12073 [(set_attr "type" "delayed_compare")
c1618c0c 12074 (set_attr "length" "8,16")])
9ebbca7d
GK		 12075
12076(define_split
12077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12078 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12079 [(match_operand 2 "cc_reg_operand" "")
12080 (const_int 0)])
12081 (const_int 0)))
12082 (set (match_operand:SI 3 "gpc_reg_operand" "")
12083 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12084 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12085 [(set (match_dup 3)
12086 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12087 (set (match_dup 0)
12088 (compare:CC (match_dup 3)
12089 (const_int 0)))]
12090 "")
1fd4e8c1
RK		 12091
12092(define_insn ""
cd2b37d9 12093 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12094 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12095 [(match_operand 2 "cc_reg_operand" "y")
12096 (const_int 0)])
12097 (match_operand:SI 3 "const_int_operand" "n")))]
12098 ""
12099 "*
12100{
12101 int is_bit = ccr_bit (operands[1], 1);
12102 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12103 int count;
12104
12105 if (is_bit >= put_bit)
12106 count = is_bit - put_bit;
12107 else
12108 count = 32 - (put_bit - is_bit);
12109
89e9f3a8
MM		 12110 operands[4] = GEN_INT (count);
12111 operands[5] = GEN_INT (put_bit);
1fd4e8c1 12112
2c4a9cff 12113 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 12114}"
2c4a9cff
DE		 12115 [(set (attr "type")
12116 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12117 (const_string "mfcrf")
12118 ]
12119 (const_string "mfcr")))
c1618c0c 12120 (set_attr "length" "8")])
1fd4e8c1
RK		 12121
12122(define_insn ""
9ebbca7d 12123 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12124 (compare:CC
12125 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12126 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 12127 (const_int 0)])
9ebbca7d 12128 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 12129 (const_int 0)))
9ebbca7d 12130 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12131 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12132 (match_dup 3)))]
ce71f754 12133 ""
1fd4e8c1
RK		 12134 "*
12135{
12136 int is_bit = ccr_bit (operands[1], 1);
12137 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12138 int count;
12139
9ebbca7d
GK		 12140 /* Force split for non-cc0 compare. */
12141 if (which_alternative == 1)
12142 return \"#\";
12143
1fd4e8c1
RK		 12144 if (is_bit >= put_bit)
12145 count = is_bit - put_bit;
12146 else
12147 count = 32 - (put_bit - is_bit);
12148
89e9f3a8
MM		 12149 operands[5] = GEN_INT (count);
12150 operands[6] = GEN_INT (put_bit);
1fd4e8c1 12151
2c4a9cff 12152 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 12153}"
b19003d8 12154 [(set_attr "type" "delayed_compare")
c1618c0c 12155 (set_attr "length" "8,16")])
9ebbca7d
GK		 12156
12157(define_split
12158 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12159 (compare:CC
12160 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12161 [(match_operand 2 "cc_reg_operand" "")
12162 (const_int 0)])
12163 (match_operand:SI 3 "const_int_operand" ""))
12164 (const_int 0)))
12165 (set (match_operand:SI 4 "gpc_reg_operand" "")
12166 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12167 (match_dup 3)))]
ce71f754 12168 "reload_completed"
9ebbca7d
GK		 12169 [(set (match_dup 4)
12170 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12171 (match_dup 3)))
12172 (set (match_dup 0)
12173 (compare:CC (match_dup 4)
12174 (const_int 0)))]
12175 "")
1fd4e8c1 12176
c5defebb
RK		 12177;; There is a 3 cycle delay between consecutive mfcr instructions
12178;; so it is useful to combine 2 scc instructions to use only one mfcr.
12179
12180(define_peephole
cd2b37d9 12181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 12182 (match_operator:SI 1 "scc_comparison_operator"
12183 [(match_operand 2 "cc_reg_operand" "y")
12184 (const_int 0)]))
cd2b37d9 12185 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 12186 (match_operator:SI 4 "scc_comparison_operator"
12187 [(match_operand 5 "cc_reg_operand" "y")
12188 (const_int 0)]))]
309323c2 12189 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12190 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12191 [(set_attr "type" "mfcr")
c1618c0c 12192 (set_attr "length" "12")])
c5defebb 12193
9ebbca7d
GK		 12194(define_peephole
12195 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12196 (match_operator:DI 1 "scc_comparison_operator"
12197 [(match_operand 2 "cc_reg_operand" "y")
12198 (const_int 0)]))
12199 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12200 (match_operator:DI 4 "scc_comparison_operator"
12201 [(match_operand 5 "cc_reg_operand" "y")
12202 (const_int 0)]))]
309323c2 12203 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12204 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12205 [(set_attr "type" "mfcr")
c1618c0c 12206 (set_attr "length" "12")])
9ebbca7d 12207
1fd4e8c1
RK		 12208;; There are some scc insns that can be done directly, without a compare.
12209;; These are faster because they don't involve the communications between
12210;; the FXU and branch units. In fact, we will be replacing all of the
12211;; integer scc insns here or in the portable methods in emit_store_flag.
12212;;
12213;; Also support (neg (scc ..)) since that construct is used to replace
12214;; branches, (plus (scc ..) ..) since that construct is common and
12215;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12216;; cases where it is no more expensive than (neg (scc ..)).
12217
12218;; Have reload force a constant into a register for the simple insns that
12219;; otherwise won't accept constants. We do this because it is faster than
12220;; the cmp/mfcr sequence we would otherwise generate.
12221
e9441276
DE		 12222(define_mode_attr scc_eq_op2 [(SI "rKLI")
12223 (DI "rKJI")])
a260abc9 12224
e9441276
DE		 12225(define_insn_and_split "*eq<mode>"
12226 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12227 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
d0515b39 12228 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
27f0fe7f 12229 "!TARGET_POWER"
e9441276 12230 "#"
27f0fe7f 12231 "!TARGET_POWER"
d0515b39
DE		 12232 [(set (match_dup 0)
12233 (clz:GPR (match_dup 3)))
70ae0191 12234 (set (match_dup 0)
d0515b39 12235 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
70ae0191 12236 {
e9441276
DE		 12237 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12238 {
d0515b39
DE		 12239 /* Use output operand as intermediate. */
12240 operands[3] = operands[0];
12241
e9441276 12242 if (logical_operand (operands[2], <MODE>mode))
d0515b39 12243 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12244 gen_rtx_XOR (<MODE>mode,
12245 operands[1], operands[2])));
12246 else
d0515b39 12247 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12248 gen_rtx_PLUS (<MODE>mode, operands[1],
12249 negate_rtx (<MODE>mode,
12250 operands[2]))));
12251 }
12252 else
d0515b39 12253 operands[3] = operands[1];
9ebbca7d 12254
d0515b39 12255 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
e9441276 12256 })
a260abc9 12257
e9441276 12258(define_insn_and_split "*eq<mode>_compare"
d0515b39 12259 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
70ae0191 12260 (compare:CC
1fa5c709
DE		 12261 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12262 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
70ae0191 12263 (const_int 0)))
1fa5c709 12264 (set (match_operand:P 0 "gpc_reg_operand" "=r")
d0515b39 12265 (eq:P (match_dup 1) (match_dup 2)))]
27f0fe7f 12266 "!TARGET_POWER && optimize_size"
e9441276 12267 "#"
27f0fe7f 12268 "!TARGET_POWER && optimize_size"
d0515b39 12269 [(set (match_dup 0)
1fa5c709 12270 (clz:P (match_dup 4)))
d0515b39
DE		 12271 (parallel [(set (match_dup 3)
12272 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
70ae0191
DE		 12273 (const_int 0)))
12274 (set (match_dup 0)
d0515b39 12275 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
70ae0191 12276 {
e9441276
DE		 12277 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12278 {
d0515b39
DE		 12279 /* Use output operand as intermediate. */
12280 operands[4] = operands[0];
12281
e9441276
DE		 12282 if (logical_operand (operands[2], <MODE>mode))
12283 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12284 gen_rtx_XOR (<MODE>mode,
12285 operands[1], operands[2])));
12286 else
12287 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12288 gen_rtx_PLUS (<MODE>mode, operands[1],
12289 negate_rtx (<MODE>mode,
12290 operands[2]))));
12291 }
12292 else
12293 operands[4] = operands[1];
12294
d0515b39 12295 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
70ae0191
DE		 12296 })
12297
05f68097
DE		 12298(define_insn "*eqsi_power"
12299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12300 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12301 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12302 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12303 "TARGET_POWER"
12304 "@
12305 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12306 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12307 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12308 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12309 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12310 [(set_attr "type" "three,two,three,three,three")
12311 (set_attr "length" "12,8,12,12,12")])
12312
b19003d8
RK		 12313;; We have insns of the form shown by the first define_insn below. If
12314;; there is something inside the comparison operation, we must split it.
12315(define_split
12316 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12317 (plus:SI (match_operator 1 "comparison_operator"
12318 [(match_operand:SI 2 "" "")
12319 (match_operand:SI 3
12320 "reg_or_cint_operand" "")])
12321 (match_operand:SI 4 "gpc_reg_operand" "")))
12322 (clobber (match_operand:SI 5 "register_operand" ""))]
12323 "! gpc_reg_operand (operands[2], SImode)"
12324 [(set (match_dup 5) (match_dup 2))
12325 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12326 (match_dup 4)))])
1fd4e8c1 12327
297abd0d 12328(define_insn "*plus_eqsi"
5276df18 12329 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 12330 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
56fc483e 12331 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
5276df18 12332 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
59d6560b 12333 "TARGET_32BIT"
1fd4e8c1 12334 "@
5276df18
DE		 12335 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12336 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12337 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12338 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12339 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
943c15ed
DE		 12340 [(set_attr "type" "three,two,three,three,three")
12341 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1 12342
297abd0d 12343(define_insn "*compare_plus_eqsi"
9ebbca7d 12344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12345 (compare:CC
1fd4e8c1 12346 (plus:SI
9ebbca7d 12347 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12348 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12349 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12350 (const_int 0)))
9ebbca7d 12351 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
297abd0d 12352 "TARGET_32BIT && optimize_size"
1fd4e8c1 12353 "@
ca7f5001 12354 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 12355 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 12356 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12357 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12358 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12359 #
12360 #
12361 #
12362 #
12363 #"
b19003d8 12364 [(set_attr "type" "compare")
9ebbca7d
GK		 12365 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12366
12367(define_split
12368 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12369 (compare:CC
12370 (plus:SI
12371 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12372 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12373 (match_operand:SI 3 "gpc_reg_operand" ""))
12374 (const_int 0)))
12375 (clobber (match_scratch:SI 4 ""))]
297abd0d 12376 "TARGET_32BIT && optimize_size && reload_completed"
9ebbca7d
GK		 12377 [(set (match_dup 4)
12378 (plus:SI (eq:SI (match_dup 1)
12379 (match_dup 2))
12380 (match_dup 3)))
12381 (set (match_dup 0)
12382 (compare:CC (match_dup 4)
12383 (const_int 0)))]
12384 "")
1fd4e8c1 12385
297abd0d 12386(define_insn "*plus_eqsi_compare"
0387639b 12387 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12388 (compare:CC
1fd4e8c1 12389 (plus:SI
9ebbca7d 12390 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12391 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12392 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12393 (const_int 0)))
0387639b
DE		 12394 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12395 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12396 "TARGET_32BIT && optimize_size"
1fd4e8c1 12397 "@
0387639b
DE		 12398 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12399 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12400 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12401 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12402 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12403 #
12404 #
12405 #
12406 #
12407 #"
12408 [(set_attr "type" "compare")
12409 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12410
12411(define_split
0387639b 12412 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12413 (compare:CC
12414 (plus:SI
12415 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12416 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12417 (match_operand:SI 3 "gpc_reg_operand" ""))
12418 (const_int 0)))
12419 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 12420 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12421 "TARGET_32BIT && optimize_size && reload_completed"
0387639b 12422 [(set (match_dup 0)
9ebbca7d 12423 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 12424 (set (match_dup 4)
9ebbca7d
GK		 12425 (compare:CC (match_dup 0)
12426 (const_int 0)))]
12427 "")
12428
d0515b39
DE		 12429(define_insn "*neg_eq0<mode>"
12430 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12431 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12432 (const_int 0))))]
59d6560b 12433 ""
d0515b39
DE		 12434 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12435 [(set_attr "type" "two")
12436 (set_attr "length" "8")])
12437
12438(define_insn_and_split "*neg_eq<mode>"
12439 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12440 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12441 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
59d6560b 12442 ""
d0515b39 12443 "#"
59d6560b 12444 ""
d0515b39
DE		 12445 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12446 {
12447 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12448 {
12449 /* Use output operand as intermediate. */
12450 operands[3] = operands[0];
12451
12452 if (logical_operand (operands[2], <MODE>mode))
12453 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12454 gen_rtx_XOR (<MODE>mode,
12455 operands[1], operands[2])));
12456 else
12457 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12458 gen_rtx_PLUS (<MODE>mode, operands[1],
12459 negate_rtx (<MODE>mode,
12460 operands[2]))));
12461 }
12462 else
12463 operands[3] = operands[1];
12464 })
1fd4e8c1 12465
ea9be077
MM		 12466;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12467;; since it nabs/sr is just as fast.
ce45ef46 12468(define_insn "*ne0si"
b4e95693 12469 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 12470 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12471 (const_int 31)))
12472 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 12473 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077 12474 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
943c15ed
DE		 12475 [(set_attr "type" "two")
12476 (set_attr "length" "8")])
ea9be077 12477
ce45ef46 12478(define_insn "*ne0di"
a260abc9
DE		 12479 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12480 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12481 (const_int 63)))
12482 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 12483 "TARGET_64BIT"
a260abc9 12484 "addic %2,%1,-1\;subfe %0,%2,%1"
943c15ed
DE		 12485 [(set_attr "type" "two")
12486 (set_attr "length" "8")])
a260abc9 12487
1fd4e8c1 12488;; This is what (plus (ne X (const_int 0)) Y) looks like.
297abd0d 12489(define_insn "*plus_ne0si"
cd2b37d9 12490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 12491 (plus:SI (lshiftrt:SI
cd2b37d9 12492 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 12493 (const_int 31))
cd2b37d9 12494 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 12495 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 12496 "TARGET_32BIT"
ca7f5001 12497 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
943c15ed
DE		 12498 [(set_attr "type" "two")
12499 (set_attr "length" "8")])
1fd4e8c1 12500
297abd0d 12501(define_insn "*plus_ne0di"
a260abc9
DE		 12502 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12503 (plus:DI (lshiftrt:DI
12504 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12505 (const_int 63))
12506 (match_operand:DI 2 "gpc_reg_operand" "r")))
12507 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 12508 "TARGET_64BIT"
a260abc9 12509 "addic %3,%1,-1\;addze %0,%2"
943c15ed
DE		 12510 [(set_attr "type" "two")
12511 (set_attr "length" "8")])
a260abc9 12512
297abd0d 12513(define_insn "*compare_plus_ne0si"
9ebbca7d 12514 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12515 (compare:CC
12516 (plus:SI (lshiftrt:SI
9ebbca7d 12517 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12518 (const_int 31))
9ebbca7d 12519 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12520 (const_int 0)))
889b90a1
GK		 12521 (clobber (match_scratch:SI 3 "=&r,&r"))
12522 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 12523 "TARGET_32BIT"
9ebbca7d
GK		 12524 "@
12525 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12526 #"
b19003d8 12527 [(set_attr "type" "compare")
9ebbca7d
GK		 12528 (set_attr "length" "8,12")])
12529
12530(define_split
12531 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12532 (compare:CC
12533 (plus:SI (lshiftrt:SI
12534 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12535 (const_int 31))
12536 (match_operand:SI 2 "gpc_reg_operand" ""))
12537 (const_int 0)))
889b90a1
GK		 12538 (clobber (match_scratch:SI 3 ""))
12539 (clobber (match_scratch:SI 4 ""))]
683bdff7 12540 "TARGET_32BIT && reload_completed"
889b90a1 12541 [(parallel [(set (match_dup 3)
ce71f754
AM		 12542 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12543 (const_int 31))
12544 (match_dup 2)))
889b90a1 12545 (clobber (match_dup 4))])
9ebbca7d
GK		 12546 (set (match_dup 0)
12547 (compare:CC (match_dup 3)
12548 (const_int 0)))]
12549 "")
1fd4e8c1 12550
297abd0d 12551(define_insn "*compare_plus_ne0di"
9ebbca7d 12552 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12553 (compare:CC
12554 (plus:DI (lshiftrt:DI
9ebbca7d 12555 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12556 (const_int 63))
9ebbca7d 12557 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12558 (const_int 0)))
9ebbca7d 12559 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12560 "TARGET_64BIT"
9ebbca7d
GK		 12561 "@
12562 addic %3,%1,-1\;addze. %3,%2
12563 #"
a260abc9 12564 [(set_attr "type" "compare")
9ebbca7d
GK		 12565 (set_attr "length" "8,12")])
12566
12567(define_split
12568 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12569 (compare:CC
12570 (plus:DI (lshiftrt:DI
12571 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12572 (const_int 63))
12573 (match_operand:DI 2 "gpc_reg_operand" ""))
12574 (const_int 0)))
12575 (clobber (match_scratch:DI 3 ""))]
683bdff7 12576 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12577 [(set (match_dup 3)
12578 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12579 (const_int 63))
12580 (match_dup 2)))
12581 (set (match_dup 0)
12582 (compare:CC (match_dup 3)
12583 (const_int 0)))]
12584 "")
a260abc9 12585
297abd0d 12586(define_insn "*plus_ne0si_compare"
9ebbca7d 12587 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12588 (compare:CC
12589 (plus:SI (lshiftrt:SI
9ebbca7d 12590 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12591 (const_int 31))
9ebbca7d 12592 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12593 (const_int 0)))
9ebbca7d 12594 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12595 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12596 (match_dup 2)))
9ebbca7d 12597 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 12598 "TARGET_32BIT"
9ebbca7d
GK		 12599 "@
12600 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12601 #"
b19003d8 12602 [(set_attr "type" "compare")
9ebbca7d
GK		 12603 (set_attr "length" "8,12")])
12604
12605(define_split
12606 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12607 (compare:CC
12608 (plus:SI (lshiftrt:SI
12609 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12610 (const_int 31))
12611 (match_operand:SI 2 "gpc_reg_operand" ""))
12612 (const_int 0)))
12613 (set (match_operand:SI 0 "gpc_reg_operand" "")
12614 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12615 (match_dup 2)))
12616 (clobber (match_scratch:SI 3 ""))]
683bdff7 12617 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12618 [(parallel [(set (match_dup 0)
12619 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12620 (match_dup 2)))
12621 (clobber (match_dup 3))])
12622 (set (match_dup 4)
12623 (compare:CC (match_dup 0)
12624 (const_int 0)))]
12625 "")
1fd4e8c1 12626
297abd0d 12627(define_insn "*plus_ne0di_compare"
9ebbca7d 12628 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12629 (compare:CC
12630 (plus:DI (lshiftrt:DI
9ebbca7d 12631 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12632 (const_int 63))
9ebbca7d 12633 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12634 (const_int 0)))
9ebbca7d 12635 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 12636 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12637 (match_dup 2)))
9ebbca7d 12638 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12639 "TARGET_64BIT"
9ebbca7d
GK		 12640 "@
12641 addic %3,%1,-1\;addze. %0,%2
12642 #"
a260abc9 12643 [(set_attr "type" "compare")
9ebbca7d
GK		 12644 (set_attr "length" "8,12")])
12645
12646(define_split
12647 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12648 (compare:CC
12649 (plus:DI (lshiftrt:DI
12650 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12651 (const_int 63))
12652 (match_operand:DI 2 "gpc_reg_operand" ""))
12653 (const_int 0)))
12654 (set (match_operand:DI 0 "gpc_reg_operand" "")
12655 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12656 (match_dup 2)))
12657 (clobber (match_scratch:DI 3 ""))]
683bdff7 12658 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12659 [(parallel [(set (match_dup 0)
12660 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12661 (match_dup 2)))
12662 (clobber (match_dup 3))])
12663 (set (match_dup 4)
12664 (compare:CC (match_dup 0)
12665 (const_int 0)))]
12666 "")
a260abc9 12667
1fd4e8c1 12668(define_insn ""
cd2b37d9
RK		 12669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12670 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 12671 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12672 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 12673 "TARGET_POWER"
1fd4e8c1 12674 "@
ca7f5001 12675 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 12676 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12677 [(set_attr "length" "12")])
1fd4e8c1
RK		 12678
12679(define_insn ""
9ebbca7d 12680 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12681 (compare:CC
9ebbca7d
GK		 12682 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12683 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 12684 (const_int 0)))
9ebbca7d 12685 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12686 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12687 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 12688 "TARGET_POWER"
1fd4e8c1 12689 "@
ca7f5001 12690 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 12691 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12692 #
12693 #"
12694 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12695 (set_attr "length" "12,12,16,16")])
12696
12697(define_split
12698 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12699 (compare:CC
12700 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12701 (match_operand:SI 2 "reg_or_short_operand" ""))
12702 (const_int 0)))
12703 (set (match_operand:SI 0 "gpc_reg_operand" "")
12704 (le:SI (match_dup 1) (match_dup 2)))
12705 (clobber (match_scratch:SI 3 ""))]
12706 "TARGET_POWER && reload_completed"
12707 [(parallel [(set (match_dup 0)
12708 (le:SI (match_dup 1) (match_dup 2)))
12709 (clobber (match_dup 3))])
12710 (set (match_dup 4)
12711 (compare:CC (match_dup 0)
12712 (const_int 0)))]
12713 "")
1fd4e8c1
RK		 12714
12715(define_insn ""
097657c3 12716 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12717 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12718 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 12719 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 12720 "TARGET_POWER"
1fd4e8c1 12721 "@
097657c3
AM		 12722 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12723 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 12724 [(set_attr "length" "12")])
1fd4e8c1
RK		 12725
12726(define_insn ""
9ebbca7d 12727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12728 (compare:CC
9ebbca7d
GK		 12729 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12730 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12731 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12732 (const_int 0)))
9ebbca7d 12733 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 12734 "TARGET_POWER"
1fd4e8c1 12735 "@
ca7f5001 12736 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12737 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12738 #
12739 #"
b19003d8 12740 [(set_attr "type" "compare")
9ebbca7d
GK		 12741 (set_attr "length" "12,12,16,16")])
12742
12743(define_split
12744 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12745 (compare:CC
12746 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12747 (match_operand:SI 2 "reg_or_short_operand" ""))
12748 (match_operand:SI 3 "gpc_reg_operand" ""))
12749 (const_int 0)))
12750 (clobber (match_scratch:SI 4 ""))]
12751 "TARGET_POWER && reload_completed"
12752 [(set (match_dup 4)
12753 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 12754 (match_dup 3)))
9ebbca7d
GK		 12755 (set (match_dup 0)
12756 (compare:CC (match_dup 4)
12757 (const_int 0)))]
12758 "")
1fd4e8c1
RK		 12759
12760(define_insn ""
097657c3 12761 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12762 (compare:CC
9ebbca7d
GK		 12763 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12764 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12765 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12766 (const_int 0)))
097657c3
AM		 12767 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12768 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12769 "TARGET_POWER"
1fd4e8c1 12770 "@
097657c3
AM		 12771 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12772 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12773 #
12774 #"
b19003d8 12775 [(set_attr "type" "compare")
9ebbca7d
GK		 12776 (set_attr "length" "12,12,16,16")])
12777
12778(define_split
097657c3 12779 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12780 (compare:CC
12781 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12782 (match_operand:SI 2 "reg_or_short_operand" ""))
12783 (match_operand:SI 3 "gpc_reg_operand" ""))
12784 (const_int 0)))
12785 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12786 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12787 "TARGET_POWER && reload_completed"
097657c3 12788 [(set (match_dup 0)
9ebbca7d 12789 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12790 (set (match_dup 4)
9ebbca7d
GK		 12791 (compare:CC (match_dup 0)
12792 (const_int 0)))]
12793 "")
1fd4e8c1
RK		 12794
12795(define_insn ""
cd2b37d9
RK		 12796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12797 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12798 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 12799 "TARGET_POWER"
1fd4e8c1 12800 "@
ca7f5001
RK		 12801 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12802 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12803 [(set_attr "length" "12")])
1fd4e8c1 12804
a2dba291
DE		 12805(define_insn "*leu<mode>"
12806 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12807 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12808 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12809 ""
ca7f5001 12810 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 12811 [(set_attr "type" "three")
12812 (set_attr "length" "12")])
1fd4e8c1 12813
a2dba291 12814(define_insn "*leu<mode>_compare"
9ebbca7d 12815 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12816 (compare:CC
a2dba291
DE		 12817 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12818 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12819 (const_int 0)))
a2dba291
DE		 12820 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12821 (leu:P (match_dup 1) (match_dup 2)))]
12822 ""
9ebbca7d
GK		 12823 "@
12824 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12825 #"
b19003d8 12826 [(set_attr "type" "compare")
9ebbca7d
GK		 12827 (set_attr "length" "12,16")])
12828
12829(define_split
12830 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12831 (compare:CC
a2dba291
DE		 12832 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12833 (match_operand:P 2 "reg_or_short_operand" ""))
9ebbca7d 12834 (const_int 0)))
a2dba291
DE		 12835 (set (match_operand:P 0 "gpc_reg_operand" "")
12836 (leu:P (match_dup 1) (match_dup 2)))]
12837 "reload_completed"
9ebbca7d 12838 [(set (match_dup 0)
a2dba291 12839 (leu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 12840 (set (match_dup 3)
12841 (compare:CC (match_dup 0)
12842 (const_int 0)))]
12843 "")
1fd4e8c1 12844
a2dba291
DE		 12845(define_insn "*plus_leu<mode>"
12846 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12847 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12848 (match_operand:P 2 "reg_or_short_operand" "rI"))
12849 (match_operand:P 3 "gpc_reg_operand" "r")))]
12850 ""
80103f96 12851 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
943c15ed
DE		 12852 [(set_attr "type" "two")
12853 (set_attr "length" "8")])
1fd4e8c1
RK		 12854
12855(define_insn ""
9ebbca7d 12856 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12857 (compare:CC
9ebbca7d
GK		 12858 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12859 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12860 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12861 (const_int 0)))
9ebbca7d 12862 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12863 "TARGET_32BIT"
9ebbca7d
GK		 12864 "@
12865 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12866 #"
b19003d8 12867 [(set_attr "type" "compare")
9ebbca7d
GK		 12868 (set_attr "length" "8,12")])
12869
12870(define_split
12871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12872 (compare:CC
12873 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12874 (match_operand:SI 2 "reg_or_short_operand" ""))
12875 (match_operand:SI 3 "gpc_reg_operand" ""))
12876 (const_int 0)))
12877 (clobber (match_scratch:SI 4 ""))]
683bdff7 12878 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12879 [(set (match_dup 4)
12880 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12881 (match_dup 3)))
12882 (set (match_dup 0)
12883 (compare:CC (match_dup 4)
12884 (const_int 0)))]
12885 "")
1fd4e8c1
RK		 12886
12887(define_insn ""
097657c3 12888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12889 (compare:CC
9ebbca7d
GK		 12890 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12891 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12892 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12893 (const_int 0)))
097657c3
AM		 12894 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12895 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12896 "TARGET_32BIT"
9ebbca7d 12897 "@
097657c3 12898 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 12899 #"
b19003d8 12900 [(set_attr "type" "compare")
9ebbca7d
GK		 12901 (set_attr "length" "8,12")])
12902
12903(define_split
097657c3 12904 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12905 (compare:CC
12906 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12907 (match_operand:SI 2 "reg_or_short_operand" ""))
12908 (match_operand:SI 3 "gpc_reg_operand" ""))
12909 (const_int 0)))
12910 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12911 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12912 "TARGET_32BIT && reload_completed"
097657c3 12913 [(set (match_dup 0)
9ebbca7d 12914 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12915 (set (match_dup 4)
9ebbca7d
GK		 12916 (compare:CC (match_dup 0)
12917 (const_int 0)))]
12918 "")
1fd4e8c1 12919
a2dba291
DE		 12920(define_insn "*neg_leu<mode>"
12921 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12922 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12923 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12924 ""
ca7f5001 12925 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
943c15ed
DE		 12926 [(set_attr "type" "three")
12927 (set_attr "length" "12")])
1fd4e8c1 12928
a2dba291
DE		 12929(define_insn "*and_neg_leu<mode>"
12930 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12931 (and:P (neg:P
12932 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12933 (match_operand:P 2 "reg_or_short_operand" "rI")))
12934 (match_operand:P 3 "gpc_reg_operand" "r")))]
12935 ""
097657c3 12936 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 12937 [(set_attr "type" "three")
12938 (set_attr "length" "12")])
1fd4e8c1
RK		 12939
12940(define_insn ""
9ebbca7d 12941 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12942 (compare:CC
12943 (and:SI (neg:SI
9ebbca7d
GK		 12944 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12945 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12946 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12947 (const_int 0)))
9ebbca7d 12948 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12949 "TARGET_32BIT"
9ebbca7d
GK		 12950 "@
12951 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12952 #"
12953 [(set_attr "type" "compare")
12954 (set_attr "length" "12,16")])
12955
12956(define_split
12957 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12958 (compare:CC
12959 (and:SI (neg:SI
12960 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12961 (match_operand:SI 2 "reg_or_short_operand" "")))
12962 (match_operand:SI 3 "gpc_reg_operand" ""))
12963 (const_int 0)))
12964 (clobber (match_scratch:SI 4 ""))]
683bdff7 12965 "TARGET_32BIT && reload_completed"
9ebbca7d 12966 [(set (match_dup 4)
097657c3
AM		 12967 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12968 (match_dup 3)))
9ebbca7d
GK		 12969 (set (match_dup 0)
12970 (compare:CC (match_dup 4)
12971 (const_int 0)))]
12972 "")
1fd4e8c1
RK		 12973
12974(define_insn ""
097657c3 12975 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12976 (compare:CC
12977 (and:SI (neg:SI
9ebbca7d
GK		 12978 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12979 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12980 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12981 (const_int 0)))
097657c3
AM		 12982 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12983 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12984 "TARGET_32BIT"
9ebbca7d 12985 "@
097657c3 12986 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 12987 #"
b19003d8 12988 [(set_attr "type" "compare")
9ebbca7d
GK		 12989 (set_attr "length" "12,16")])
12990
12991(define_split
097657c3 12992 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12993 (compare:CC
12994 (and:SI (neg:SI
12995 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12996 (match_operand:SI 2 "reg_or_short_operand" "")))
12997 (match_operand:SI 3 "gpc_reg_operand" ""))
12998 (const_int 0)))
12999 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13000 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13001 "TARGET_32BIT && reload_completed"
097657c3
AM		 13002 [(set (match_dup 0)
13003 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13004 (match_dup 3)))
13005 (set (match_dup 4)
9ebbca7d
GK		 13006 (compare:CC (match_dup 0)
13007 (const_int 0)))]
13008 "")
1fd4e8c1
RK		 13009
13010(define_insn ""
cd2b37d9
RK		 13011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13012 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13013 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 13014 "TARGET_POWER"
7f340546 13015 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13016 [(set_attr "length" "12")])
1fd4e8c1
RK		 13017
13018(define_insn ""
9ebbca7d 13019 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13020 (compare:CC
9ebbca7d
GK		 13021 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13022 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13023 (const_int 0)))
9ebbca7d 13024 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13025 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13026 "TARGET_POWER"
9ebbca7d
GK		 13027 "@
13028 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13029 #"
29ae5b89 13030 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13031 (set_attr "length" "12,16")])
13032
13033(define_split
13034 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13035 (compare:CC
13036 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13037 (match_operand:SI 2 "reg_or_short_operand" ""))
13038 (const_int 0)))
13039 (set (match_operand:SI 0 "gpc_reg_operand" "")
13040 (lt:SI (match_dup 1) (match_dup 2)))]
13041 "TARGET_POWER && reload_completed"
13042 [(set (match_dup 0)
13043 (lt:SI (match_dup 1) (match_dup 2)))
13044 (set (match_dup 3)
13045 (compare:CC (match_dup 0)
13046 (const_int 0)))]
13047 "")
1fd4e8c1
RK		 13048
13049(define_insn ""
097657c3 13050 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13051 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13052 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13053 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13054 "TARGET_POWER"
097657c3 13055 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13056 [(set_attr "length" "12")])
1fd4e8c1
RK		 13057
13058(define_insn ""
9ebbca7d 13059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13060 (compare:CC
9ebbca7d
GK		 13061 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13062 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13063 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13064 (const_int 0)))
9ebbca7d 13065 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13066 "TARGET_POWER"
9ebbca7d
GK		 13067 "@
13068 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13069 #"
b19003d8 13070 [(set_attr "type" "compare")
9ebbca7d
GK		 13071 (set_attr "length" "12,16")])
13072
13073(define_split
13074 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13075 (compare:CC
13076 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13077 (match_operand:SI 2 "reg_or_short_operand" ""))
13078 (match_operand:SI 3 "gpc_reg_operand" ""))
13079 (const_int 0)))
13080 (clobber (match_scratch:SI 4 ""))]
13081 "TARGET_POWER && reload_completed"
13082 [(set (match_dup 4)
13083 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 13084 (match_dup 3)))
9ebbca7d
GK		 13085 (set (match_dup 0)
13086 (compare:CC (match_dup 4)
13087 (const_int 0)))]
13088 "")
1fd4e8c1
RK		 13089
13090(define_insn ""
097657c3 13091 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13092 (compare:CC
9ebbca7d
GK		 13093 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13094 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13095 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13096 (const_int 0)))
097657c3
AM		 13097 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13098 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13099 "TARGET_POWER"
9ebbca7d 13100 "@
097657c3 13101 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13102 #"
b19003d8 13103 [(set_attr "type" "compare")
9ebbca7d
GK		 13104 (set_attr "length" "12,16")])
13105
13106(define_split
097657c3 13107 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13108 (compare:CC
13109 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13110 (match_operand:SI 2 "reg_or_short_operand" ""))
13111 (match_operand:SI 3 "gpc_reg_operand" ""))
13112 (const_int 0)))
13113 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13114 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13115 "TARGET_POWER && reload_completed"
097657c3 13116 [(set (match_dup 0)
9ebbca7d 13117 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13118 (set (match_dup 4)
9ebbca7d
GK		 13119 (compare:CC (match_dup 0)
13120 (const_int 0)))]
13121 "")
1fd4e8c1
RK		 13122
13123(define_insn ""
cd2b37d9
RK		 13124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13125 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13126 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13127 "TARGET_POWER"
13128 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13129 [(set_attr "length" "12")])
1fd4e8c1 13130
ce45ef46
DE		 13131(define_insn_and_split "*ltu<mode>"
13132 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13133 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13134 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13135 ""
c0600ecd 13136 "#"
ce45ef46
DE		 13137 ""
13138 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13139 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13140 "")
1fd4e8c1 13141
1e24ce83 13142(define_insn_and_split "*ltu<mode>_compare"
9ebbca7d 13143 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13144 (compare:CC
a2dba291
DE		 13145 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13146 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13147 (const_int 0)))
a2dba291
DE		 13148 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13149 (ltu:P (match_dup 1) (match_dup 2)))]
13150 ""
1e24ce83
DE		 13151 "#"
13152 ""
13153 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13154 (parallel [(set (match_dup 3)
13155 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13156 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13157 "")
1fd4e8c1 13158
a2dba291
DE		 13159(define_insn_and_split "*plus_ltu<mode>"
13160 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13161 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13162 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
1e24ce83 13163 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
a2dba291 13164 ""
c0600ecd 13165 "#"
04fa46cf 13166 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13167 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13168 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13169 "")
1fd4e8c1 13170
1e24ce83 13171(define_insn_and_split "*plus_ltu<mode>_compare"
097657c3 13172 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13173 (compare:CC
1e24ce83
DE		 13174 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13175 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13176 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13177 (const_int 0)))
1e24ce83
DE		 13178 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13179 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13180 ""
13181 "#"
13182 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13183 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13184 (parallel [(set (match_dup 4)
13185 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13186 (const_int 0)))
13187 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13188 "")
1fd4e8c1 13189
ce45ef46
DE		 13190(define_insn "*neg_ltu<mode>"
13191 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13192 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13193 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13194 ""
c0600ecd
DE		 13195 "@
13196 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13197 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
943c15ed 13198 [(set_attr "type" "two")
c0600ecd 13199 (set_attr "length" "8")])
1fd4e8c1
RK		 13200
13201(define_insn ""
cd2b37d9
RK		 13202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13203 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 13204 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13205 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 13206 "TARGET_POWER"
13207 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 13208 [(set_attr "length" "12")])
1fd4e8c1 13209
9ebbca7d
GK		 13210(define_insn ""
13211 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13212 (compare:CC
9ebbca7d
GK		 13213 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13214 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13215 (const_int 0)))
9ebbca7d 13216 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13217 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 13218 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 13219 "TARGET_POWER"
9ebbca7d
GK		 13220 "@
13221 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13222 #"
13223 [(set_attr "type" "compare")
13224 (set_attr "length" "12,16")])
13225
13226(define_split
13227 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13228 (compare:CC
13229 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13230 (match_operand:SI 2 "reg_or_short_operand" ""))
13231 (const_int 0)))
13232 (set (match_operand:SI 0 "gpc_reg_operand" "")
13233 (ge:SI (match_dup 1) (match_dup 2)))
13234 (clobber (match_scratch:SI 3 ""))]
13235 "TARGET_POWER && reload_completed"
13236 [(parallel [(set (match_dup 0)
097657c3
AM		 13237 (ge:SI (match_dup 1) (match_dup 2)))
13238 (clobber (match_dup 3))])
9ebbca7d
GK		 13239 (set (match_dup 4)
13240 (compare:CC (match_dup 0)
13241 (const_int 0)))]
13242 "")
13243
1fd4e8c1 13244(define_insn ""
097657c3 13245 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13246 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13247 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13248 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13249 "TARGET_POWER"
097657c3 13250 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 13251 [(set_attr "length" "12")])
1fd4e8c1
RK		 13252
13253(define_insn ""
9ebbca7d 13254 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13255 (compare:CC
9ebbca7d
GK		 13256 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13257 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13258 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13259 (const_int 0)))
9ebbca7d 13260 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13261 "TARGET_POWER"
9ebbca7d
GK		 13262 "@
13263 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13264 #"
b19003d8 13265 [(set_attr "type" "compare")
9ebbca7d
GK		 13266 (set_attr "length" "12,16")])
13267
13268(define_split
13269 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13270 (compare:CC
13271 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13272 (match_operand:SI 2 "reg_or_short_operand" ""))
13273 (match_operand:SI 3 "gpc_reg_operand" ""))
13274 (const_int 0)))
13275 (clobber (match_scratch:SI 4 ""))]
13276 "TARGET_POWER && reload_completed"
13277 [(set (match_dup 4)
13278 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 13279 (match_dup 3)))
9ebbca7d
GK		 13280 (set (match_dup 0)
13281 (compare:CC (match_dup 4)
13282 (const_int 0)))]
13283 "")
1fd4e8c1
RK		 13284
13285(define_insn ""
097657c3 13286 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13287 (compare:CC
9ebbca7d
GK		 13288 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13289 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13290 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13291 (const_int 0)))
097657c3
AM		 13292 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13293 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13294 "TARGET_POWER"
9ebbca7d 13295 "@
097657c3 13296 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 13297 #"
b19003d8 13298 [(set_attr "type" "compare")
9ebbca7d
GK		 13299 (set_attr "length" "12,16")])
13300
13301(define_split
097657c3 13302 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13303 (compare:CC
13304 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13305 (match_operand:SI 2 "reg_or_short_operand" ""))
13306 (match_operand:SI 3 "gpc_reg_operand" ""))
13307 (const_int 0)))
13308 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13309 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13310 "TARGET_POWER && reload_completed"
097657c3 13311 [(set (match_dup 0)
9ebbca7d 13312 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13313 (set (match_dup 4)
9ebbca7d
GK		 13314 (compare:CC (match_dup 0)
13315 (const_int 0)))]
13316 "")
1fd4e8c1
RK		 13317
13318(define_insn ""
cd2b37d9
RK		 13319 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13320 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13321 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13322 "TARGET_POWER"
13323 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 13324 [(set_attr "length" "12")])
1fd4e8c1 13325
a2dba291
DE		 13326(define_insn "*geu<mode>"
13327 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13328 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13329 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13330 ""
1fd4e8c1 13331 "@
ca7f5001
RK		 13332 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13333 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 13334 [(set_attr "type" "three")
13335 (set_attr "length" "12")])
1fd4e8c1 13336
a2dba291 13337(define_insn "*geu<mode>_compare"
9ebbca7d 13338 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13339 (compare:CC
a2dba291
DE		 13340 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13341 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13342 (const_int 0)))
a2dba291
DE		 13343 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13344 (geu:P (match_dup 1) (match_dup 2)))]
13345 ""
1fd4e8c1 13346 "@
ca7f5001 13347 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 13348 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13349 #
13350 #"
b19003d8 13351 [(set_attr "type" "compare")
9ebbca7d
GK		 13352 (set_attr "length" "12,12,16,16")])
13353
13354(define_split
13355 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13356 (compare:CC
a2dba291
DE		 13357 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13358 (match_operand:P 2 "reg_or_neg_short_operand" ""))
9ebbca7d 13359 (const_int 0)))
a2dba291
DE		 13360 (set (match_operand:P 0 "gpc_reg_operand" "")
13361 (geu:P (match_dup 1) (match_dup 2)))]
13362 "reload_completed"
9ebbca7d 13363 [(set (match_dup 0)
a2dba291 13364 (geu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 13365 (set (match_dup 3)
13366 (compare:CC (match_dup 0)
13367 (const_int 0)))]
13368 "")
f9562f27 13369
a2dba291
DE		 13370(define_insn "*plus_geu<mode>"
13371 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13372 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13373 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13374 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13375 ""
1fd4e8c1 13376 "@
80103f96
FS		 13377 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13378 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
943c15ed
DE		 13379 [(set_attr "type" "two")
13380 (set_attr "length" "8")])
1fd4e8c1
RK		 13381
13382(define_insn ""
9ebbca7d 13383 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13384 (compare:CC
9ebbca7d
GK		 13385 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13386 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13387 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13388 (const_int 0)))
9ebbca7d 13389 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13390 "TARGET_32BIT"
1fd4e8c1 13391 "@
ca7f5001 13392 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13393 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13394 #
13395 #"
b19003d8 13396 [(set_attr "type" "compare")
9ebbca7d
GK		 13397 (set_attr "length" "8,8,12,12")])
13398
13399(define_split
13400 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13401 (compare:CC
13402 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13403 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13404 (match_operand:SI 3 "gpc_reg_operand" ""))
13405 (const_int 0)))
13406 (clobber (match_scratch:SI 4 ""))]
683bdff7 13407 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13408 [(set (match_dup 4)
13409 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13410 (match_dup 3)))
13411 (set (match_dup 0)
13412 (compare:CC (match_dup 4)
13413 (const_int 0)))]
13414 "")
1fd4e8c1
RK		 13415
13416(define_insn ""
097657c3 13417 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13418 (compare:CC
9ebbca7d
GK		 13419 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13420 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13421 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13422 (const_int 0)))
097657c3
AM		 13423 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13424 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13425 "TARGET_32BIT"
1fd4e8c1 13426 "@
097657c3
AM		 13427 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13428 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 13429 #
13430 #"
b19003d8 13431 [(set_attr "type" "compare")
9ebbca7d
GK		 13432 (set_attr "length" "8,8,12,12")])
13433
13434(define_split
097657c3 13435 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13436 (compare:CC
13437 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13438 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13439 (match_operand:SI 3 "gpc_reg_operand" ""))
13440 (const_int 0)))
13441 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13442 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13443 "TARGET_32BIT && reload_completed"
097657c3 13444 [(set (match_dup 0)
9ebbca7d 13445 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13446 (set (match_dup 4)
9ebbca7d
GK		 13447 (compare:CC (match_dup 0)
13448 (const_int 0)))]
13449 "")
1fd4e8c1 13450
a2dba291
DE		 13451(define_insn "*neg_geu<mode>"
13452 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13453 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13454 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13455 ""
1fd4e8c1 13456 "@
ca7f5001 13457 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 13458 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
943c15ed
DE		 13459 [(set_attr "type" "three")
13460 (set_attr "length" "12")])
1fd4e8c1 13461
a2dba291
DE		 13462(define_insn "*and_neg_geu<mode>"
13463 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13464 (and:P (neg:P
13465 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13466 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13467 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13468 ""
1fd4e8c1 13469 "@
097657c3
AM		 13470 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13471 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 13472 [(set_attr "type" "three")
13473 (set_attr "length" "12")])
1fd4e8c1
RK		 13474
13475(define_insn ""
9ebbca7d 13476 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13477 (compare:CC
13478 (and:SI (neg:SI
9ebbca7d
GK		 13479 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13480 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13481 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13482 (const_int 0)))
9ebbca7d 13483 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13484 "TARGET_32BIT"
1fd4e8c1 13485 "@
ca7f5001 13486 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 13487 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13488 #
13489 #"
b19003d8 13490 [(set_attr "type" "compare")
9ebbca7d
GK		 13491 (set_attr "length" "12,12,16,16")])
13492
13493(define_split
13494 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13495 (compare:CC
13496 (and:SI (neg:SI
13497 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13498 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13499 (match_operand:SI 3 "gpc_reg_operand" ""))
13500 (const_int 0)))
13501 (clobber (match_scratch:SI 4 ""))]
683bdff7 13502 "TARGET_32BIT && reload_completed"
9ebbca7d 13503 [(set (match_dup 4)
097657c3
AM		 13504 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13505 (match_dup 3)))
9ebbca7d
GK		 13506 (set (match_dup 0)
13507 (compare:CC (match_dup 4)
13508 (const_int 0)))]
13509 "")
1fd4e8c1
RK		 13510
13511(define_insn ""
097657c3 13512 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13513 (compare:CC
13514 (and:SI (neg:SI
9ebbca7d
GK		 13515 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13516 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13517 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13518 (const_int 0)))
097657c3
AM		 13519 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13520 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13521 "TARGET_32BIT"
1fd4e8c1 13522 "@
097657c3
AM		 13523 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13524 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 13525 #
13526 #"
b19003d8 13527 [(set_attr "type" "compare")
9ebbca7d
GK		 13528 (set_attr "length" "12,12,16,16")])
13529
13530(define_split
097657c3 13531 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13532 (compare:CC
13533 (and:SI (neg:SI
13534 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13535 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13536 (match_operand:SI 3 "gpc_reg_operand" ""))
13537 (const_int 0)))
13538 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13539 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13540 "TARGET_32BIT && reload_completed"
097657c3 13541 [(set (match_dup 0)
9ebbca7d 13542 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 13543 (set (match_dup 4)
9ebbca7d
GK		 13544 (compare:CC (match_dup 0)
13545 (const_int 0)))]
13546 "")
1fd4e8c1 13547
1fd4e8c1 13548(define_insn ""
cd2b37d9
RK		 13549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13550 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13551 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 13552 "TARGET_POWER"
13553 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13554 [(set_attr "length" "12")])
1fd4e8c1
RK		 13555
13556(define_insn ""
9ebbca7d 13557 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13558 (compare:CC
9ebbca7d
GK		 13559 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13560 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 13561 (const_int 0)))
9ebbca7d 13562 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13563 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13564 "TARGET_POWER"
9ebbca7d
GK		 13565 "@
13566 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13567 #"
29ae5b89 13568 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13569 (set_attr "length" "12,16")])
13570
13571(define_split
13572 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13573 (compare:CC
13574 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13575 (match_operand:SI 2 "reg_or_short_operand" ""))
13576 (const_int 0)))
13577 (set (match_operand:SI 0 "gpc_reg_operand" "")
13578 (gt:SI (match_dup 1) (match_dup 2)))]
13579 "TARGET_POWER && reload_completed"
13580 [(set (match_dup 0)
13581 (gt:SI (match_dup 1) (match_dup 2)))
13582 (set (match_dup 3)
13583 (compare:CC (match_dup 0)
13584 (const_int 0)))]
13585 "")
1fd4e8c1 13586
d0515b39 13587(define_insn "*plus_gt0<mode>"
a2dba291
DE		 13588 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13589 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13590 (const_int 0))
13591 (match_operand:P 2 "gpc_reg_operand" "r")))]
13592 ""
80103f96 13593 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
943c15ed
DE		 13594 [(set_attr "type" "three")
13595 (set_attr "length" "12")])
1fd4e8c1
RK		 13596
13597(define_insn ""
9ebbca7d 13598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13599 (compare:CC
9ebbca7d 13600 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13601 (const_int 0))
9ebbca7d 13602 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 13603 (const_int 0)))
9ebbca7d 13604 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 13605 "TARGET_32BIT"
9ebbca7d
GK		 13606 "@
13607 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13608 #"
b19003d8 13609 [(set_attr "type" "compare")
9ebbca7d
GK		 13610 (set_attr "length" "12,16")])
13611
13612(define_split
13613 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13614 (compare:CC
13615 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13616 (const_int 0))
13617 (match_operand:SI 2 "gpc_reg_operand" ""))
13618 (const_int 0)))
13619 (clobber (match_scratch:SI 3 ""))]
683bdff7 13620 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13621 [(set (match_dup 3)
13622 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13623 (match_dup 2)))
13624 (set (match_dup 0)
13625 (compare:CC (match_dup 3)
13626 (const_int 0)))]
13627 "")
1fd4e8c1 13628
f9562f27 13629(define_insn ""
9ebbca7d 13630 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 13631 (compare:CC
9ebbca7d 13632 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13633 (const_int 0))
9ebbca7d 13634 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13635 (const_int 0)))
9ebbca7d 13636 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 13637 "TARGET_64BIT"
9ebbca7d
GK		 13638 "@
13639 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13640 #"
f9562f27 13641 [(set_attr "type" "compare")
9ebbca7d
GK		 13642 (set_attr "length" "12,16")])
13643
13644(define_split
13645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13646 (compare:CC
13647 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13648 (const_int 0))
13649 (match_operand:DI 2 "gpc_reg_operand" ""))
13650 (const_int 0)))
13651 (clobber (match_scratch:DI 3 ""))]
683bdff7 13652 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13653 [(set (match_dup 3)
13654 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 13655 (match_dup 2)))
9ebbca7d
GK		 13656 (set (match_dup 0)
13657 (compare:CC (match_dup 3)
13658 (const_int 0)))]
13659 "")
f9562f27 13660
1fd4e8c1 13661(define_insn ""
097657c3 13662 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 13663 (compare:CC
13664 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13665 (const_int 0))
13666 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13667 (const_int 0)))
097657c3
AM		 13668 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13669 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13670 "TARGET_32BIT"
9ebbca7d 13671 "@
097657c3 13672 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 13673 #"
13674 [(set_attr "type" "compare")
13675 (set_attr "length" "12,16")])
13676
13677(define_split
097657c3 13678 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 13679 (compare:CC
9ebbca7d 13680 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 13681 (const_int 0))
9ebbca7d 13682 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 13683 (const_int 0)))
9ebbca7d 13684 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13685 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13686 "TARGET_32BIT && reload_completed"
097657c3 13687 [(set (match_dup 0)
9ebbca7d 13688 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13689 (set (match_dup 3)
9ebbca7d
GK		 13690 (compare:CC (match_dup 0)
13691 (const_int 0)))]
13692 "")
1fd4e8c1 13693
f9562f27 13694(define_insn ""
097657c3 13695 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13696 (compare:CC
9ebbca7d 13697 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13698 (const_int 0))
9ebbca7d 13699 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13700 (const_int 0)))
097657c3
AM		 13701 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13702 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13703 "TARGET_64BIT"
9ebbca7d 13704 "@
097657c3 13705 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 13706 #"
f9562f27 13707 [(set_attr "type" "compare")
9ebbca7d
GK		 13708 (set_attr "length" "12,16")])
13709
13710(define_split
097657c3 13711 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13712 (compare:CC
13713 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13714 (const_int 0))
13715 (match_operand:DI 2 "gpc_reg_operand" ""))
13716 (const_int 0)))
13717 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13718 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13719 "TARGET_64BIT && reload_completed"
097657c3 13720 [(set (match_dup 0)
9ebbca7d 13721 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13722 (set (match_dup 3)
9ebbca7d
GK		 13723 (compare:CC (match_dup 0)
13724 (const_int 0)))]
13725 "")
f9562f27 13726
1fd4e8c1 13727(define_insn ""
097657c3 13728 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13729 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13730 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 13731 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13732 "TARGET_POWER"
097657c3 13733 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13734 [(set_attr "length" "12")])
1fd4e8c1
RK		 13735
13736(define_insn ""
9ebbca7d 13737 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13738 (compare:CC
9ebbca7d
GK		 13739 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13740 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13741 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13742 (const_int 0)))
9ebbca7d 13743 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13744 "TARGET_POWER"
9ebbca7d
GK		 13745 "@
13746 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13747 #"
b19003d8 13748 [(set_attr "type" "compare")
9ebbca7d
GK		 13749 (set_attr "length" "12,16")])
13750
13751(define_split
13752 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13753 (compare:CC
13754 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13755 (match_operand:SI 2 "reg_or_short_operand" ""))
13756 (match_operand:SI 3 "gpc_reg_operand" ""))
13757 (const_int 0)))
13758 (clobber (match_scratch:SI 4 ""))]
13759 "TARGET_POWER && reload_completed"
13760 [(set (match_dup 4)
097657c3 13761 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 13762 (set (match_dup 0)
13763 (compare:CC (match_dup 4)
13764 (const_int 0)))]
13765 "")
1fd4e8c1
RK		 13766
13767(define_insn ""
097657c3 13768 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13769 (compare:CC
9ebbca7d
GK		 13770 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13771 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13772 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13773 (const_int 0)))
097657c3
AM		 13774 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13775 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13776 "TARGET_POWER"
9ebbca7d 13777 "@
097657c3 13778 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13779 #"
b19003d8 13780 [(set_attr "type" "compare")
9ebbca7d
GK		 13781 (set_attr "length" "12,16")])
13782
13783(define_split
097657c3 13784 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13785 (compare:CC
13786 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13787 (match_operand:SI 2 "reg_or_short_operand" ""))
13788 (match_operand:SI 3 "gpc_reg_operand" ""))
13789 (const_int 0)))
13790 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13791 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13792 "TARGET_POWER && reload_completed"
097657c3 13793 [(set (match_dup 0)
9ebbca7d 13794 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13795 (set (match_dup 4)
9ebbca7d
GK		 13796 (compare:CC (match_dup 0)
13797 (const_int 0)))]
13798 "")
1fd4e8c1 13799
1fd4e8c1 13800(define_insn ""
cd2b37d9
RK		 13801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13802 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13803 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 13804 "TARGET_POWER"
13805 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13806 [(set_attr "length" "12")])
1fd4e8c1 13807
ce45ef46
DE		 13808(define_insn_and_split "*gtu<mode>"
13809 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13810 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13811 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13812 ""
c0600ecd 13813 "#"
ce45ef46
DE		 13814 ""
13815 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13816 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13817 "")
f9562f27 13818
1e24ce83 13819(define_insn_and_split "*gtu<mode>_compare"
9ebbca7d 13820 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13821 (compare:CC
a2dba291
DE		 13822 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13823 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13824 (const_int 0)))
a2dba291
DE		 13825 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13826 (gtu:P (match_dup 1) (match_dup 2)))]
13827 ""
1e24ce83
DE		 13828 "#"
13829 ""
13830 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13831 (parallel [(set (match_dup 3)
13832 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13833 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13834 "")
f9562f27 13835
1e24ce83 13836(define_insn_and_split "*plus_gtu<mode>"
a2dba291
DE		 13837 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13838 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13839 (match_operand:P 2 "reg_or_short_operand" "rI"))
13840 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13841 ""
c0600ecd 13842 "#"
04fa46cf 13843 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13844 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13845 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13846 "")
f9562f27 13847
1e24ce83 13848(define_insn_and_split "*plus_gtu<mode>_compare"
097657c3 13849 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13850 (compare:CC
1e24ce83
DE		 13851 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13852 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13853 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13854 (const_int 0)))
1e24ce83
DE		 13855 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13856 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13857 ""
13858 "#"
13859 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13860 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13861 (parallel [(set (match_dup 4)
13862 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13863 (const_int 0)))
13864 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13865 "")
f9562f27 13866
ce45ef46
DE		 13867(define_insn "*neg_gtu<mode>"
13868 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13869 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13870 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13871 ""
ca7f5001 13872 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
943c15ed 13873 [(set_attr "type" "two")
c0600ecd 13874 (set_attr "length" "8")])
f9562f27 13875
1fd4e8c1
RK		 13876\f
13877;; Define both directions of branch and return. If we need a reload
13878;; register, we'd rather use CR0 since it is much easier to copy a
13879;; register CC value to there.
13880
13881(define_insn ""
13882 [(set (pc)
13883 (if_then_else (match_operator 1 "branch_comparison_operator"
13884 [(match_operand 2
b54cf83a 13885 "cc_reg_operand" "y")
1fd4e8c1
RK		 13886 (const_int 0)])
13887 (label_ref (match_operand 0 "" ""))
13888 (pc)))]
13889 ""
b19003d8
RK		 13890 "*
13891{
12a4e8c5 13892 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 13893}"
13894 [(set_attr "type" "branch")])
13895
1fd4e8c1
RK		 13896(define_insn ""
13897 [(set (pc)
13898 (if_then_else (match_operator 0 "branch_comparison_operator"
13899 [(match_operand 1
b54cf83a 13900 "cc_reg_operand" "y")
1fd4e8c1
RK		 13901 (const_int 0)])
13902 (return)
13903 (pc)))]
13904 "direct_return ()"
12a4e8c5
GK		 13905 "*
13906{
13907 return output_cbranch (operands[0], NULL, 0, insn);
13908}"
9c6fdb46 13909 [(set_attr "type" "jmpreg")
39a10a29 13910 (set_attr "length" "4")])
1fd4e8c1
RK		 13911
13912(define_insn ""
13913 [(set (pc)
13914 (if_then_else (match_operator 1 "branch_comparison_operator"
13915 [(match_operand 2
b54cf83a 13916 "cc_reg_operand" "y")
1fd4e8c1
RK		 13917 (const_int 0)])
13918 (pc)
13919 (label_ref (match_operand 0 "" ""))))]
13920 ""
b19003d8
RK		 13921 "*
13922{
12a4e8c5 13923 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 13924}"
13925 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13926
13927(define_insn ""
13928 [(set (pc)
13929 (if_then_else (match_operator 0 "branch_comparison_operator"
13930 [(match_operand 1
b54cf83a 13931 "cc_reg_operand" "y")
1fd4e8c1
RK		 13932 (const_int 0)])
13933 (pc)
13934 (return)))]
13935 "direct_return ()"
12a4e8c5
GK		 13936 "*
13937{
13938 return output_cbranch (operands[0], NULL, 1, insn);
13939}"
9c6fdb46 13940 [(set_attr "type" "jmpreg")
39a10a29
GK		 13941 (set_attr "length" "4")])
13942
13943;; Logic on condition register values.
13944
13945; This pattern matches things like
13946; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13947; (eq:SI (reg:CCFP 68) (const_int 0)))
13948; (const_int 1)))
13949; which are generated by the branch logic.
b54cf83a 13950; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29 13951
423c1189 13952(define_insn "*cceq_ior_compare"
b54cf83a 13953 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13954 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 13955 [(match_operator:SI 2
39a10a29
GK		 13956 "branch_positive_comparison_operator"
13957 [(match_operand 3
b54cf83a 13958 "cc_reg_operand" "y,y")
39a10a29 13959 (const_int 0)])
b54cf83a 13960 (match_operator:SI 4
39a10a29
GK		 13961 "branch_positive_comparison_operator"
13962 [(match_operand 5
b54cf83a 13963 "cc_reg_operand" "0,y")
39a10a29
GK		 13964 (const_int 0)])])
13965 (const_int 1)))]
24fab1d3 13966 ""
39a10a29 13967 "cr%q1 %E0,%j2,%j4"
b54cf83a 13968 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13969
13970; Why is the constant -1 here, but 1 in the previous pattern?
13971; Because ~1 has all but the low bit set.
13972(define_insn ""
b54cf83a 13973 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13974 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 13975 [(not:SI (match_operator:SI 2
39a10a29
GK		 13976 "branch_positive_comparison_operator"
13977 [(match_operand 3
b54cf83a 13978 "cc_reg_operand" "y,y")
39a10a29
GK		 13979 (const_int 0)]))
13980 (match_operator:SI 4
13981 "branch_positive_comparison_operator"
13982 [(match_operand 5
b54cf83a 13983 "cc_reg_operand" "0,y")
39a10a29
GK		 13984 (const_int 0)])])
13985 (const_int -1)))]
13986 ""
13987 "cr%q1 %E0,%j2,%j4"
b54cf83a 13988 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29 13989
423c1189 13990(define_insn "*cceq_rev_compare"
b54cf83a 13991 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 13992 (compare:CCEQ (match_operator:SI 1
39a10a29 13993 "branch_positive_comparison_operator"
6c873122 13994 [(match_operand 2
b54cf83a 13995 "cc_reg_operand" "0,y")
39a10a29
GK		 13996 (const_int 0)])
13997 (const_int 0)))]
423c1189 13998 ""
251b3667 13999 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 14000 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 14001
14002;; If we are comparing the result of two comparisons, this can be done
14003;; using creqv or crxor.
14004
14005(define_insn_and_split ""
14006 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14007 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14008 [(match_operand 2 "cc_reg_operand" "y")
14009 (const_int 0)])
14010 (match_operator 3 "branch_comparison_operator"
14011 [(match_operand 4 "cc_reg_operand" "y")
14012 (const_int 0)])))]
14013 ""
14014 "#"
14015 ""
14016 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14017 (match_dup 5)))]
14018 "
14019{
14020 int positive_1, positive_2;
14021
364849ee
DE		 14022 positive_1 = branch_positive_comparison_operator (operands[1],
14023 GET_MODE (operands[1]));
14024 positive_2 = branch_positive_comparison_operator (operands[3],
14025 GET_MODE (operands[3]));
39a10a29
GK		 14026
14027 if (! positive_1)
1c563bed 14028 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
0f4c242b
KH		 14029 GET_CODE (operands[1])),
14030 SImode,
14031 operands[2], const0_rtx);
39a10a29 14032 else if (GET_MODE (operands[1]) != SImode)
0f4c242b
KH		 14033 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14034 operands[2], const0_rtx);
39a10a29
GK		 14035
14036 if (! positive_2)
1c563bed 14037 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
0f4c242b
KH		 14038 GET_CODE (operands[3])),
14039 SImode,
14040 operands[4], const0_rtx);
39a10a29 14041 else if (GET_MODE (operands[3]) != SImode)
0f4c242b
KH		 14042 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14043 operands[4], const0_rtx);
39a10a29
GK		 14044
14045 if (positive_1 == positive_2)
251b3667
DE		 14046 {
14047 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14048 operands[5] = constm1_rtx;
14049 }
14050 else
14051 {
14052 operands[5] = const1_rtx;
14053 }
39a10a29 14054}")
1fd4e8c1
RK		 14055
14056;; Unconditional branch and return.
14057
14058(define_insn "jump"
14059 [(set (pc)
14060 (label_ref (match_operand 0 "" "")))]
14061 ""
b7ff3d82
DE		 14062 "b %l0"
14063 [(set_attr "type" "branch")])
1fd4e8c1
RK		 14064
14065(define_insn "return"
14066 [(return)]
14067 "direct_return ()"
324e52cc
TG		 14068 "{br|blr}"
14069 [(set_attr "type" "jmpreg")])
1fd4e8c1 14070
0ad91047 14071(define_expand "indirect_jump"
4ae234b0 14072 [(set (pc) (match_operand 0 "register_operand" ""))])
0ad91047 14073
4ae234b0
GK		 14074(define_insn "*indirect_jump<mode>"
14075 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14076 ""
b92b324d
DE		 14077 "@
14078 bctr
14079 {br|blr}"
324e52cc 14080 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14081
14082;; Table jump for switch statements:
14083(define_expand "tablejump"
e6ca2c17
DE		 14084 [(use (match_operand 0 "" ""))
14085 (use (label_ref (match_operand 1 "" "")))]
14086 ""
14087 "
14088{
14089 if (TARGET_32BIT)
14090 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14091 else
14092 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14093 DONE;
14094}")
14095
14096(define_expand "tablejumpsi"
1fd4e8c1
RK		 14097 [(set (match_dup 3)
14098 (plus:SI (match_operand:SI 0 "" "")
14099 (match_dup 2)))
14100 (parallel [(set (pc) (match_dup 3))
14101 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14102 "TARGET_32BIT"
1fd4e8c1
RK		 14103 "
14104{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 14105 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 14106 operands[3] = gen_reg_rtx (SImode);
14107}")
14108
e6ca2c17 14109(define_expand "tablejumpdi"
6ae08853 14110 [(set (match_dup 4)
e42ac3de 14111 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
9ebbca7d
GK		 14112 (set (match_dup 3)
14113 (plus:DI (match_dup 4)
e6ca2c17
DE		 14114 (match_dup 2)))
14115 (parallel [(set (pc) (match_dup 3))
14116 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14117 "TARGET_64BIT"
e6ca2c17 14118 "
9ebbca7d 14119{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 14120 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 14121 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 14122}")
14123
ce45ef46 14124(define_insn "*tablejump<mode>_internal1"
1fd4e8c1 14125 [(set (pc)
4ae234b0 14126 (match_operand:P 0 "register_operand" "c,*l"))
1fd4e8c1 14127 (use (label_ref (match_operand 1 "" "")))]
4ae234b0 14128 ""
c859cda6
DJ		 14129 "@
14130 bctr
14131 {br|blr}"
a6845123 14132 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14133
14134(define_insn "nop"
14135 [(const_int 0)]
14136 ""
ca7f5001 14137 "{cror 0,0,0|nop}")
1fd4e8c1 14138\f
7e69e155 14139;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 14140;; so loop.c knows what to generate.
14141
5527bf14
RH		 14142(define_expand "doloop_end"
14143 [(use (match_operand 0 "" "")) ; loop pseudo
14144 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14145 (use (match_operand 2 "" "")) ; max iterations
14146 (use (match_operand 3 "" "")) ; loop level
14147 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 14148 ""
14149 "
14150{
5527bf14
RH		 14151 /* Only use this on innermost loops. */
14152 if (INTVAL (operands[3]) > 1)
14153 FAIL;
683bdff7 14154 if (TARGET_64BIT)
5527bf14
RH		 14155 {
14156 if (GET_MODE (operands[0]) != DImode)
14157 FAIL;
14158 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14159 }
0ad91047 14160 else
5527bf14
RH		 14161 {
14162 if (GET_MODE (operands[0]) != SImode)
14163 FAIL;
14164 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14165 }
0ad91047
DE		 14166 DONE;
14167}")
14168
4ae234b0 14169(define_expand "ctr<mode>"
3cb999d8 14170 [(parallel [(set (pc)
4ae234b0 14171 (if_then_else (ne (match_operand:P 0 "register_operand" "")
3cb999d8
DE		 14172 (const_int 1))
14173 (label_ref (match_operand 1 "" ""))
14174 (pc)))
b6c9286a 14175 (set (match_dup 0)
4ae234b0 14176 (plus:P (match_dup 0)
b6c9286a 14177 (const_int -1)))
5f81043f 14178 (clobber (match_scratch:CC 2 ""))
4ae234b0
GK		 14179 (clobber (match_scratch:P 3 ""))])]
14180 ""
61c07d3c 14181 "")
c225ba7b 14182
1fd4e8c1
RK		 14183;; We need to be able to do this for any operand, including MEM, or we
14184;; will cause reload to blow up since we don't allow output reloads on
7e69e155 14185;; JUMP_INSNs.
0ad91047 14186;; For the length attribute to be calculated correctly, the
5f81043f
RK		 14187;; label MUST be operand 0.
14188
4ae234b0 14189(define_insn "*ctr<mode>_internal1"
0ad91047 14190 [(set (pc)
4ae234b0 14191 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14192 (const_int 1))
14193 (label_ref (match_operand 0 "" ""))
14194 (pc)))
4ae234b0
GK		 14195 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14196 (plus:P (match_dup 1)
0ad91047 14197 (const_int -1)))
43b68ce5 14198 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14199 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14200 ""
0ad91047
DE		 14201 "*
14202{
14203 if (which_alternative != 0)
14204 return \"#\";
856a6884 14205 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14206 return \"{bdn|bdnz} %l0\";
14207 else
f607bc57 14208 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14209}"
14210 [(set_attr "type" "branch")
5a195cb5 14211 (set_attr "length" "*,12,16,16")])
0ad91047 14212
4ae234b0 14213(define_insn "*ctr<mode>_internal2"
0ad91047 14214 [(set (pc)
4ae234b0 14215 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14216 (const_int 1))
14217 (pc)
14218 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14219 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14220 (plus:P (match_dup 1)
0ad91047 14221 (const_int -1)))
43b68ce5 14222 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14223 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14224 ""
5f81043f
RK		 14225 "*
14226{
14227 if (which_alternative != 0)
14228 return \"#\";
856a6884 14229 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14230 return \"bdz %l0\";
14231 else
f607bc57 14232 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14233}"
14234 [(set_attr "type" "branch")
5a195cb5 14235 (set_attr "length" "*,12,16,16")])
5f81043f 14236
0ad91047
DE		 14237;; Similar but use EQ
14238
4ae234b0 14239(define_insn "*ctr<mode>_internal5"
5f81043f 14240 [(set (pc)
4ae234b0 14241 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14242 (const_int 1))
a6845123 14243 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14244 (pc)))
4ae234b0
GK		 14245 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14246 (plus:P (match_dup 1)
0ad91047 14247 (const_int -1)))
43b68ce5 14248 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14249 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14250 ""
0ad91047
DE		 14251 "*
14252{
14253 if (which_alternative != 0)
14254 return \"#\";
856a6884 14255 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14256 return \"bdz %l0\";
14257 else
f607bc57 14258 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14259}"
14260 [(set_attr "type" "branch")
5a195cb5 14261 (set_attr "length" "*,12,16,16")])
0ad91047 14262
4ae234b0 14263(define_insn "*ctr<mode>_internal6"
0ad91047 14264 [(set (pc)
4ae234b0 14265 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14266 (const_int 1))
14267 (pc)
14268 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14269 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14270 (plus:P (match_dup 1)
0ad91047 14271 (const_int -1)))
43b68ce5 14272 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14273 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14274 ""
5f81043f
RK		 14275 "*
14276{
14277 if (which_alternative != 0)
14278 return \"#\";
856a6884 14279 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14280 return \"{bdn|bdnz} %l0\";
14281 else
f607bc57 14282 return \"bdz $+8\;b %l0\";
5f81043f
RK		 14283}"
14284 [(set_attr "type" "branch")
5a195cb5 14285 (set_attr "length" "*,12,16,16")])
5f81043f 14286
0ad91047
DE		 14287;; Now the splitters if we could not allocate the CTR register
14288
1fd4e8c1
RK		 14289(define_split
14290 [(set (pc)
14291 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14292 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14293 (const_int 1)])
61c07d3c
DE		 14294 (match_operand 5 "" "")
14295 (match_operand 6 "" "")))
4ae234b0
GK		 14296 (set (match_operand:P 0 "gpc_reg_operand" "")
14297 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14298 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14299 (clobber (match_scratch:P 4 ""))]
14300 "reload_completed"
0ad91047 14301 [(parallel [(set (match_dup 3)
4ae234b0 14302 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14303 (const_int -1))
14304 (const_int 0)))
14305 (set (match_dup 0)
4ae234b0 14306 (plus:P (match_dup 1)
0ad91047 14307 (const_int -1)))])
61c07d3c
DE		 14308 (set (pc) (if_then_else (match_dup 7)
14309 (match_dup 5)
14310 (match_dup 6)))]
0ad91047 14311 "
0f4c242b
KH		 14312{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14313 operands[3], const0_rtx); }")
0ad91047
DE		 14314
14315(define_split
14316 [(set (pc)
14317 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14318 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14319 (const_int 1)])
61c07d3c
DE		 14320 (match_operand 5 "" "")
14321 (match_operand 6 "" "")))
4ae234b0
GK		 14322 (set (match_operand:P 0 "nonimmediate_operand" "")
14323 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14324 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14325 (clobber (match_scratch:P 4 ""))]
14326 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
0ad91047 14327 [(parallel [(set (match_dup 3)
4ae234b0 14328 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14329 (const_int -1))
14330 (const_int 0)))
14331 (set (match_dup 4)
4ae234b0 14332 (plus:P (match_dup 1)
0ad91047
DE		 14333 (const_int -1)))])
14334 (set (match_dup 0)
14335 (match_dup 4))
61c07d3c
DE		 14336 (set (pc) (if_then_else (match_dup 7)
14337 (match_dup 5)
14338 (match_dup 6)))]
0ad91047 14339 "
0f4c242b
KH		 14340{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14341 operands[3], const0_rtx); }")
e0cd0770
JC		 14342\f
14343(define_insn "trap"
14344 [(trap_if (const_int 1) (const_int 0))]
14345 ""
44cd321e
PS		 14346 "{t 31,0,0|trap}"
14347 [(set_attr "type" "trap")])
e0cd0770
JC		 14348
14349(define_expand "conditional_trap"
14350 [(trap_if (match_operator 0 "trap_comparison_operator"
14351 [(match_dup 2) (match_dup 3)])
14352 (match_operand 1 "const_int_operand" ""))]
14353 ""
14354 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14355 operands[2] = rs6000_compare_op0;
14356 operands[3] = rs6000_compare_op1;")
14357
14358(define_insn ""
14359 [(trap_if (match_operator 0 "trap_comparison_operator"
4ae234b0
GK		 14360 [(match_operand:GPR 1 "register_operand" "r")
14361 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
e0cd0770
JC		 14362 (const_int 0))]
14363 ""
44cd321e
PS		 14364 "{t|t<wd>}%V0%I2 %1,%2"
14365 [(set_attr "type" "trap")])
9ebbca7d
GK		 14366\f
14367;; Insns related to generating the function prologue and epilogue.
14368
14369(define_expand "prologue"
14370 [(use (const_int 0))]
14371 "TARGET_SCHED_PROLOG"
14372 "
14373{
14374 rs6000_emit_prologue ();
14375 DONE;
14376}")
14377
2c4a9cff
DE		 14378(define_insn "*movesi_from_cr_one"
14379 [(match_parallel 0 "mfcr_operation"
14380 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14381 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14382 (match_operand 3 "immediate_operand" "n")]
14383 UNSPEC_MOVESI_FROM_CR))])]
14384 "TARGET_MFCRF"
14385 "*
14386{
14387 int mask = 0;
14388 int i;
14389 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14390 {
14391 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14392 operands[4] = GEN_INT (mask);
14393 output_asm_insn (\"mfcr %1,%4\", operands);
14394 }
14395 return \"\";
14396}"
14397 [(set_attr "type" "mfcrf")])
14398
9ebbca7d
GK		 14399(define_insn "movesi_from_cr"
14400 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1de43f85
DE		 14401 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14402 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14403 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14404 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
615158e2 14405 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 14406 ""
309323c2 14407 "mfcr %0"
b54cf83a 14408 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14409
14410(define_insn "*stmw"
e033a023
DE		 14411 [(match_parallel 0 "stmw_operation"
14412 [(set (match_operand:SI 1 "memory_operand" "=m")
14413 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14414 "TARGET_MULTIPLE"
9c6fdb46
DE		 14415 "{stm|stmw} %2,%1"
14416 [(set_attr "type" "store_ux")])
6ae08853 14417
4ae234b0 14418(define_insn "*save_fpregs_<mode>"
85d346f1 14419 [(match_parallel 0 "any_parallel_operand"
e65a3857
DE		 14420 [(clobber (reg:P 65))
14421 (use (match_operand:P 1 "call_operand" "s"))
14422 (set (match_operand:DF 2 "memory_operand" "=m")
14423 (match_operand:DF 3 "gpc_reg_operand" "f"))])]
4ae234b0 14424 ""
e65a3857 14425 "bl %z1"
e033a023
DE		 14426 [(set_attr "type" "branch")
14427 (set_attr "length" "4")])
9ebbca7d
GK		 14428
14429; These are to explain that changes to the stack pointer should
14430; not be moved over stores to stack memory.
14431(define_insn "stack_tie"
14432 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 14433 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 14434 ""
14435 ""
14436 [(set_attr "length" "0")])
14437
14438
14439(define_expand "epilogue"
14440 [(use (const_int 0))]
14441 "TARGET_SCHED_PROLOG"
14442 "
14443{
14444 rs6000_emit_epilogue (FALSE);
14445 DONE;
14446}")
14447
14448; On some processors, doing the mtcrf one CC register at a time is
14449; faster (like on the 604e). On others, doing them all at once is
14450; faster; for instance, on the 601 and 750.
14451
14452(define_expand "movsi_to_cr_one"
e42ac3de
RS		 14453 [(set (match_operand:CC 0 "cc_reg_operand" "")
14454 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
615158e2 14455 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 14456 ""
14457 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14458
14459(define_insn "*movsi_to_cr"
35aba846
DE		 14460 [(match_parallel 0 "mtcrf_operation"
14461 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14462 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14463 (match_operand 3 "immediate_operand" "n")]
615158e2 14464 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 14465 ""
e35b9579
GK		 14466 "*
14467{
14468 int mask = 0;
14469 int i;
14470 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14471 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14472 operands[4] = GEN_INT (mask);
14473 return \"mtcrf %4,%2\";
309323c2 14474}"
b54cf83a 14475 [(set_attr "type" "mtcr")])
9ebbca7d 14476
b54cf83a 14477(define_insn "*mtcrfsi"
309323c2
DE		 14478 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14479 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 14480 (match_operand 2 "immediate_operand" "n")]
14481 UNSPEC_MOVESI_TO_CR))]
6ae08853 14482 "GET_CODE (operands[0]) == REG
309323c2
DE		 14483 && CR_REGNO_P (REGNO (operands[0]))
14484 && GET_CODE (operands[2]) == CONST_INT
14485 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14486 "mtcrf %R0,%1"
b54cf83a 14487 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14488
14489; The load-multiple instructions have similar properties.
14490; Note that "load_multiple" is a name known to the machine-independent
9c6fdb46 14491; code that actually corresponds to the PowerPC load-string.
9ebbca7d
GK		 14492
14493(define_insn "*lmw"
35aba846
DE		 14494 [(match_parallel 0 "lmw_operation"
14495 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14496 (match_operand:SI 2 "memory_operand" "m"))])]
14497 "TARGET_MULTIPLE"
9c6fdb46
DE		 14498 "{lm|lmw} %1,%2"
14499 [(set_attr "type" "load_ux")])
6ae08853 14500
4ae234b0 14501(define_insn "*return_internal_<mode>"
e35b9579 14502 [(return)
4ae234b0
GK		 14503 (use (match_operand:P 0 "register_operand" "lc"))]
14504 ""
cccf3bdc 14505 "b%T0"
9ebbca7d
GK		 14506 [(set_attr "type" "jmpreg")])
14507
14508; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
85d346f1 14509; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
9ebbca7d 14510
4ae234b0 14511(define_insn "*return_and_restore_fpregs_<mode>"
85d346f1 14512 [(match_parallel 0 "any_parallel_operand"
e35b9579 14513 [(return)
e65a3857
DE		 14514 (use (reg:P 65))
14515 (use (match_operand:P 1 "call_operand" "s"))
14516 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
14517 (match_operand:DF 3 "memory_operand" "m"))])]
4ae234b0 14518 ""
e65a3857 14519 "b %z1")
9ebbca7d 14520
83720594
RH		 14521; This is used in compiling the unwind routines.
14522(define_expand "eh_return"
34dc173c 14523 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 14524 ""
14525 "
14526{
83720594 14527 if (TARGET_32BIT)
34dc173c 14528 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 14529 else
34dc173c 14530 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 14531 DONE;
14532}")
14533
83720594 14534; We can't expand this before we know where the link register is stored.
4ae234b0
GK		 14535(define_insn "eh_set_lr_<mode>"
14536 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
615158e2 14537 UNSPECV_EH_RR)
4ae234b0
GK		 14538 (clobber (match_scratch:P 1 "=&b"))]
14539 ""
83720594 14540 "#")
9ebbca7d
GK		 14541
14542(define_split
615158e2 14543 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 14544 (clobber (match_scratch 1 ""))]
14545 "reload_completed"
14546 [(const_int 0)]
9ebbca7d
GK		 14547 "
14548{
d1d0c603 14549 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 14550 DONE;
14551}")
0ac081f6 14552
01a2ccd0 14553(define_insn "prefetch"
3256a76e 14554 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
6041bf2f
DE		 14555 (match_operand:SI 1 "const_int_operand" "n")
14556 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14557 "TARGET_POWERPC"
6041bf2f
DE		 14558 "*
14559{
01a2ccd0
DE		 14560 if (GET_CODE (operands[0]) == REG)
14561 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14562 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14563}"
14564 [(set_attr "type" "load")])
915167f5 14565\f
a3170dc6 14566
f565b0a1 14567(include "sync.md")
10ed84db 14568(include "altivec.md")
a3170dc6 14569(include "spe.md")
7393f7f8 14570(include "dfp.md")
Mirror of https://gcc.gnu.org/git/gcc.git