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1fd4e8c1 1;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
8e871c05
RK		 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994 Free Software Foundation, Inc.
3;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1
RK		 4
5;; This file is part of GNU CC.
6
7;; GNU CC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 2, or (at your option)
10;; any later version.
11
12;; GNU CC is distributed in the hope that it will be useful,
13;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15;; GNU General Public License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GNU CC; see the file COPYING. If not, write to
19;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22\f
23;; Define an insn type attribute. This is used in function unit delay
24;; computations.
324e52cc 25(define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
1fd4e8c1
RK		 26 (const_string "integer"))
27
b19003d8
RK		 28;; Length (in bytes).
29(define_attr "length" ""
30 (if_then_else (eq_attr "type" "branch")
31 (if_then_else (and (ge (minus (pc) (match_dup 0))
32 (const_int -32768))
33 (lt (minus (pc) (match_dup 0))
34 (const_int 32767)))
35 (const_int 8)
36 (const_int 12))
37 (const_int 4)))
38
cfb557c4
RK		 39;; Processor type -- this attribute must exactly match the processor_type
40;; enumeration in rs6000.h.
41
2661cdd9 42(define_attr "cpu" "rios1,rios2,ppc601,ppc603,ppc604,ppc620"
cfb557c4
RK		 43 (const (symbol_ref "rs6000_cpu_attr")))
44
45; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
46; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
47
48(define_function_unit "lsu" 1 0
49 (and (eq_attr "type" "load")
98c131c3 50 (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
cfb557c4
RK		 51 2 0)
52
53(define_function_unit "lsu" 1 0
54 (and (eq_attr "type" "fpload")
98c131c3 55 (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
cfb557c4
RK		 56 2 0)
57
58(define_function_unit "iu" 1 0
59 (and (eq_attr "type" "load")
3624a679 60 (eq_attr "cpu" "rios1,ppc601"))
cfb557c4
RK		 61 2 0)
62
63(define_function_unit "iu" 1 0
64 (and (eq_attr "type" "fpload")
3624a679 65 (eq_attr "cpu" "rios1,ppc601"))
cfb557c4
RK		 66 3 0)
67
68(define_function_unit "iu" 1 0
69 (and (eq_attr "type" "imul")
ca7f5001 70 (eq_attr "cpu" "rios1"))
cfb557c4
RK		 71 3 0)
72
73(define_function_unit "iu" 1 0
74 (and (eq_attr "type" "imul")
75 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
76 5 0)
77
78(define_function_unit "iu" 1 0
79 (and (eq_attr "type" "idiv")
ca7f5001 80 (eq_attr "cpu" "rios1"))
cfb557c4
RK		 81 19 0)
82
83(define_function_unit "iu" 1 0
84 (and (eq_attr "type" "idiv")
85 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
86 36 0)
87
88(define_function_unit "bpu" 1 0
89 (eq_attr "type" "compare")
90 4 0)
91
92(define_function_unit "bpu" 1 0
93 (eq_attr "type" "delayed_compare")
94 5 0)
95
96(define_function_unit "bpu" 1 0
97 (and (eq_attr "type" "fpcompare")
2661cdd9 98 (eq_attr "cpu" "rios1,rios2"))
cfb557c4
RK		 99 8 0)
100
101(define_function_unit "bpu" 1 0
102 (and (eq_attr "type" "fpcompare")
103 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
104 4 0)
105
106(define_function_unit "bpu" 1 0
324e52cc 107 (and (eq_attr "type" "mtjmpr")
2661cdd9 108 (eq_attr "cpu" "rios1,rios2"))
cfb557c4
RK		 109 5 0)
110
111(define_function_unit "bpu" 1 0
324e52cc 112 (and (eq_attr "type" "mtjmpr")
cfb557c4
RK		 113 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
114 4 0)
115
116(define_function_unit "fpu" 1 0
117 (and (eq_attr "type" "fp")
2661cdd9 118 (eq_attr "cpu" "rios1"))
cfb557c4
RK		 119 2 0)
120
121(define_function_unit "fpu" 1 0
122 (and (eq_attr "type" "fp")
123 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
124 4 0)
125
126(define_function_unit "fpu" 1 0
127 (and (eq_attr "type" "dmul")
2661cdd9 128 (eq_attr "cpu" "rios1"))
cfb557c4
RK		 129 2 0)
130
131(define_function_unit "fpu" 1 0
132 (and (eq_attr "type" "dmul")
133 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
134 5 0)
135
136(define_function_unit "fpu" 1 0
137 (and (eq_attr "type" "sdiv")
2661cdd9 138 (eq_attr "cpu" "rios1"))
cfb557c4
RK		 139 19 0)
140
141(define_function_unit "fpu" 1 0
142 (and (eq_attr "type" "sdiv")
143 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
144 17 0)
145
146(define_function_unit "fpu" 1 0
147 (and (eq_attr "type" "ddiv")
2661cdd9 148 (eq_attr "cpu" "rios1"))
cfb557c4
RK		 149 19 0)
150
151(define_function_unit "fpu" 1 0
152 (and (eq_attr "type" "ddiv")
153 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
154 31 0)
155
156(define_function_unit "fpu" 1 0
157 (and (eq_attr "type" "ssqrt")
158 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
159 31 0)
160
161(define_function_unit "fpu" 1 0
162 (and (eq_attr "type" "dsqrt")
163 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
164 31 0)
165
98c131c3
RK		 166(define_function_unit "iu2" 2 0
167 (and (eq_attr "type" "integer")
168 (eq_attr "cpu" "rios2"))
169 1 0
170 [(eq_attr "type" "imul,idiv")])
b73d04f2 171
98c131c3
RK		 172(define_function_unit "imuldiv" 1 0
173 (and (eq_attr "type" "imul")
174 (eq_attr "cpu" "rios2"))
175 2 0
176 [(eq_attr "type" "integer")])
b73d04f2 177
98c131c3
RK		 178(define_function_unit "imuldiv" 1 0
179 (and (eq_attr "type" "idiv")
180 (eq_attr "cpu" "rios2"))
181 13 0
182 [(eq_attr "type" "integer")])
b73d04f2 183
cfb557c4
RK		 184(define_function_unit "fpu2" 2 0
185 (and (eq_attr "type" "fp")
4652f1d4 186 (eq_attr "cpu" "rios2"))
cfb557c4
RK		 187 2 0)
188
189(define_function_unit "fpu2" 2 0
190 (and (eq_attr "type" "dmul")
191 (eq_attr "cpu" "rios2"))
192 2 0)
193
194(define_function_unit "fpu2" 2 0
195 (and (eq_attr "type" "sdiv")
196 (eq_attr "cpu" "rios2"))
ca7f5001 197 17 0)
cfb557c4
RK		 198
199(define_function_unit "fpu2" 2 0
200 (and (eq_attr "type" "ddiv")
201 (eq_attr "cpu" "rios2"))
ca7f5001
RK		 202 17 0)
203
204(define_function_unit "fpu2" 2 0
205 (and (eq_attr "type" "ssqrt")
206 (eq_attr "cpu" "rios2"))
207 26 0)
208
209(define_function_unit "fpu2" 2 0
210 (and (eq_attr "type" "dsqrt")
211 (eq_attr "cpu" "rios2"))
212 26 0)
1fd4e8c1
RK		 213\f
214;; Start with fixed-point load and store insns. Here we put only the more
215;; complex forms. Basic data transfer is done later.
216
217(define_expand "zero_extendqisi2"
cd2b37d9
RK		 218 [(set (match_operand:SI 0 "gpc_reg_operand" "")
219 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 220 ""
221 "")
222
223(define_insn ""
cd2b37d9 224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 225 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
226 ""
227 "@
228 lbz%U1%X1 %0,%1
ca7f5001 229 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 230 [(set_attr "type" "load,*")])
231
232(define_insn ""
233 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9 234 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 235 (const_int 0)))
236 (clobber (match_scratch:SI 2 "=r"))]
237 ""
ca7f5001 238 "{andil.|andi.} %2,%1,0xff"
1fd4e8c1
RK		 239 [(set_attr "type" "compare")])
240
241(define_insn ""
242 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
cd2b37d9 243 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
1fd4e8c1 244 (const_int 0)))
cd2b37d9 245 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 246 (zero_extend:SI (match_dup 1)))]
247 ""
ca7f5001 248 "{andil.|andi.} %0,%1,0xff"
1fd4e8c1
RK		 249 [(set_attr "type" "compare")])
250
251(define_expand "zero_extendqihi2"
cd2b37d9
RK		 252 [(set (match_operand:HI 0 "gpc_reg_operand" "")
253 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 254 ""
255 "")
256
257(define_insn ""
cd2b37d9 258 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 259 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
260 ""
261 "@
262 lbz%U1%X1 %0,%1
ca7f5001 263 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 264 [(set_attr "type" "load,*")])
265
266(define_expand "zero_extendhisi2"
5f243543 267 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 268 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 269 ""
270 "")
271
272(define_insn ""
cd2b37d9 273 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 274 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
275 ""
276 "@
277 lhz%U1%X1 %0,%1
ca7f5001 278 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 279 [(set_attr "type" "load,*")])
280
281(define_insn ""
282 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9 283 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 284 (const_int 0)))
285 (clobber (match_scratch:SI 2 "=r"))]
286 ""
ca7f5001 287 "{andil.|andi.} %2,%1,0xffff"
1fd4e8c1
RK		 288 [(set_attr "type" "compare")])
289
290(define_insn ""
291 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
cd2b37d9 292 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1fd4e8c1 293 (const_int 0)))
cd2b37d9 294 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 295 (zero_extend:SI (match_dup 1)))]
296 ""
ca7f5001 297 "{andil.|andi.} %0,%1,0xffff"
1fd4e8c1
RK		 298 [(set_attr "type" "compare")])
299
300(define_expand "extendhisi2"
cd2b37d9
RK		 301 [(set (match_operand:SI 0 "gpc_reg_operand" "")
302 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 303 ""
304 "")
305
306(define_insn ""
cd2b37d9 307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 308 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
309 ""
310 "@
311 lha%U1%X1 %0,%1
ca7f5001 312 {exts|extsh} %0,%1"
1fd4e8c1
RK		 313 [(set_attr "type" "load,*")])
314
315(define_insn ""
316 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9 317 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 318 (const_int 0)))
319 (clobber (match_scratch:SI 2 "=r"))]
320 ""
ca7f5001 321 "{exts.|extsh.} %2,%1"
1fd4e8c1
RK		 322 [(set_attr "type" "compare")])
323
324(define_insn ""
325 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
cd2b37d9 326 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
1fd4e8c1 327 (const_int 0)))
cd2b37d9 328 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 329 (sign_extend:SI (match_dup 1)))]
330 ""
ca7f5001 331 "{exts.|extsh.} %0,%1"
1fd4e8c1
RK		 332 [(set_attr "type" "compare")])
333\f
334;; Fixed-point arithmetic insns.
f357808b 335(define_insn "addsi3"
cd2b37d9
RK		 336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
337 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b")
1fd4e8c1
RK		 338 (match_operand:SI 2 "add_operand" "rI,J")))]
339 ""
340 "@
ca7f5001
RK		 341 {a%I2|add%I2c} %0,%1,%2
342 {cau|addis} %0,%1,%u2")
1fd4e8c1
RK		 343
344(define_insn ""
345 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9 346 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 347 (match_operand:SI 2 "reg_or_short_operand" "rI"))
348 (const_int 0)))
349 (clobber (match_scratch:SI 3 "=r"))]
350 ""
ca7f5001 351 "{a%I2.|add%I2c.} %3,%1,%2"
1fd4e8c1
RK		 352 [(set_attr "type" "compare")])
353
354(define_insn ""
355 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9 356 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 357 (match_operand:SI 2 "reg_or_short_operand" "rI"))
358 (const_int 0)))
cd2b37d9 359 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 360 (plus:SI (match_dup 1) (match_dup 2)))]
361 ""
ca7f5001 362 "{a%I2.|add%I2c.} %0,%1,%2"
1fd4e8c1
RK		 363 [(set_attr "type" "compare")])
364
f357808b
RK		 365;; Split an add that we can't do in one insn into two insns, each of which
366;; does one 16-bit part. This is used by combine. Note that the low-order
367;; add should be last in case the result gets used in an address.
368
369(define_split
cd2b37d9
RK		 370 [(set (match_operand:SI 0 "gpc_reg_operand" "")
371 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
f357808b 372 (match_operand:SI 2 "non_add_cint_operand" "")))]
1fd4e8c1 373 ""
f357808b
RK		 374 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
375 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
376"
1fd4e8c1 377{
f357808b
RK		 378 int low = INTVAL (operands[2]) & 0xffff;
379 int high = (unsigned) INTVAL (operands[2]) >> 16;
1fd4e8c1 380
f357808b
RK		 381 if (low & 0x8000)
382 high++, low |= 0xffff0000;
1fd4e8c1 383
f357808b
RK		 384 operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
385 operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
1fd4e8c1
RK		 386}")
387
ca7f5001 388(define_expand "one_cmplsi2"
cd2b37d9
RK		 389 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
390 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1fd4e8c1 391 ""
ca7f5001
RK		 392 "")
393
394(define_insn ""
395 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
396 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
397 "TARGET_POWER"
398 "{sfi|subfic} %0,%1,-1")
399
400(define_insn ""
401 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
402 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
403 "! TARGET_POWER"
404 "nor %0,%1,%1")
405
406(define_insn ""
407 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
408 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
409 (const_int 0)))
410 (clobber (match_scratch:SI 2 "=r"))]
411 ""
412 "nor. %2,%1,%1"
413 [(set_attr "type" "compare")])
414
415(define_insn ""
416 [(set (match_operand:CC 2 "cc_reg_operand" "=-x")
417 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
418 (const_int 0)))
419 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
420 (not:SI (match_dup 1)))]
421 ""
422 "nor. %0,%2,%1"
423 [(set_attr "type" "compare")])
1fd4e8c1
RK		 424
425(define_insn ""
3d91674b
RK		 426 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
427 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
428 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1fd4e8c1 429 ""
ca7f5001 430 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1
RK		 431
432(define_insn ""
433 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9
RK		 434 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
435 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 436 (const_int 0)))
437 (clobber (match_scratch:SI 3 "=r"))]
438 ""
ca7f5001 439 "{sf.|subfc.} %3,%2,%1"
1fd4e8c1
RK		 440 [(set_attr "type" "compare")])
441
442(define_insn ""
443 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9
RK		 444 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
445 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 446 (const_int 0)))
cd2b37d9 447 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 448 (minus:SI (match_dup 1) (match_dup 2)))]
449 ""
ca7f5001 450 "{sf.|subfc.} %0,%2,%1"
1fd4e8c1
RK		 451 [(set_attr "type" "compare")])
452
453(define_expand "subsi3"
cd2b37d9 454 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 455 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
456 (match_operand:SI 2 "reg_or_cint_operand" "")))]
457 ""
a0044fb1
RK		 458 "
459{
460 if (GET_CODE (operands[2]) == CONST_INT)
461 {
462 emit_insn (gen_addsi3 (operands[0], operands[1],
463 negate_rtx (SImode, operands[2])));
464 DONE;
465 }
466}")
1fd4e8c1
RK		 467
468;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
469;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 470;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
471;; combine.
1fd4e8c1
RK		 472
473(define_expand "sminsi3"
474 [(set (match_dup 3)
cd2b37d9 475 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 476 (match_operand:SI 2 "reg_or_short_operand" ""))
477 (const_int 0)
478 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 479 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 480 (minus:SI (match_dup 2) (match_dup 3)))]
ca7f5001 481 "TARGET_POWER"
1fd4e8c1
RK		 482 "
483{ operands[3] = gen_reg_rtx (SImode); }")
484
95ac8e67
RK		 485(define_split
486 [(set (match_operand:SI 0 "gpc_reg_operand" "")
487 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
488 (match_operand:SI 2 "reg_or_short_operand" "")))
489 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 490 "TARGET_POWER"
95ac8e67
RK		 491 [(set (match_dup 3)
492 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
493 (const_int 0)
494 (minus:SI (match_dup 2) (match_dup 1))))
495 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
496 "")
497
1fd4e8c1
RK		 498(define_expand "smaxsi3"
499 [(set (match_dup 3)
cd2b37d9 500 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 501 (match_operand:SI 2 "reg_or_short_operand" ""))
502 (const_int 0)
503 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 504 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 505 (plus:SI (match_dup 3) (match_dup 1)))]
ca7f5001 506 "TARGET_POWER"
1fd4e8c1
RK		 507 "
508{ operands[3] = gen_reg_rtx (SImode); }")
509
95ac8e67
RK		 510(define_split
511 [(set (match_operand:SI 0 "gpc_reg_operand" "")
512 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
513 (match_operand:SI 2 "reg_or_short_operand" "")))
514 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 515 "TARGET_POWER"
95ac8e67
RK		 516 [(set (match_dup 3)
517 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
518 (const_int 0)
519 (minus:SI (match_dup 2) (match_dup 1))))
520 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
521 "")
522
1fd4e8c1 523(define_expand "uminsi3"
cd2b37d9 524 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 525 (const_int -2147483648)))
cd2b37d9 526 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1fd4e8c1
RK		 527 (const_int -2147483648)))
528 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
529 (const_int 0)
530 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 531 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 532 (minus:SI (match_dup 2) (match_dup 3)))]
ca7f5001 533 "TARGET_POWER"
1fd4e8c1
RK		 534 "
535{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
536
537(define_expand "umaxsi3"
cd2b37d9 538 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 539 (const_int -2147483648)))
cd2b37d9 540 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1fd4e8c1
RK		 541 (const_int -2147483648)))
542 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
543 (const_int 0)
544 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 545 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 546 (plus:SI (match_dup 3) (match_dup 1)))]
ca7f5001 547 "TARGET_POWER"
1fd4e8c1
RK		 548 "
549{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
550
551(define_insn ""
cd2b37d9
RK		 552 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
553 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 554 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 555 (const_int 0)
556 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 557 "TARGET_POWER"
1fd4e8c1
RK		 558 "doz%I2 %0,%1,%2")
559
560(define_insn ""
561 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
562 (compare:CC
cd2b37d9 563 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 564 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 565 (const_int 0)
566 (minus:SI (match_dup 2) (match_dup 1)))
567 (const_int 0)))
568 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001 569 "TARGET_POWER"
1fd4e8c1
RK		 570 "doz%I2. %3,%1,%2"
571 [(set_attr "type" "delayed_compare")])
572
573(define_insn ""
574 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
575 (compare:CC
cd2b37d9 576 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 577 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 578 (const_int 0)
579 (minus:SI (match_dup 2) (match_dup 1)))
580 (const_int 0)))
cd2b37d9 581 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 582 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
583 (const_int 0)
584 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 585 "TARGET_POWER"
1fd4e8c1
RK		 586 "doz%I2. %0,%1,%2"
587 [(set_attr "type" "delayed_compare")])
588
589;; We don't need abs with condition code because such comparisons should
590;; never be done.
591(define_insn "abssi2"
cd2b37d9
RK		 592 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
593 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 594 "TARGET_POWER"
1fd4e8c1
RK		 595 "abs %0,%1")
596
597(define_insn ""
cd2b37d9
RK		 598 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
599 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 600 "TARGET_POWER"
1fd4e8c1
RK		 601 "nabs %0,%1")
602
603(define_insn "negsi2"
cd2b37d9
RK		 604 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
605 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 606 ""
607 "neg %0,%1")
608
609(define_insn ""
610 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9 611 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 612 (const_int 0)))
613 (clobber (match_scratch:SI 2 "=r"))]
614 ""
615 "neg. %2,%1"
616 [(set_attr "type" "compare")])
617
618(define_insn ""
619 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
cd2b37d9 620 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 621 (const_int 0)))
cd2b37d9 622 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 623 (neg:SI (match_dup 1)))]
624 ""
625 "neg. %0,%1"
626 [(set_attr "type" "compare")])
627
628(define_insn "ffssi2"
629 [(set (match_operand:SI 0 "register_operand" "=&r")
630 (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
631 ""
7f340546 632 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
b19003d8 633 [(set_attr "length" "16")])
1fd4e8c1 634
ca7f5001
RK		 635(define_expand "mulsi3"
636 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
637 (use (match_operand:SI 1 "gpc_reg_operand" ""))
638 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
639 ""
640 "
641{
642 if (TARGET_POWER)
68b40e7e 643 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 644 else
68b40e7e 645 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 646 DONE;
647}")
648
68b40e7e 649(define_insn "mulsi3_mq"
cd2b37d9
RK		 650 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
651 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 652 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
653 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 654 "TARGET_POWER"
655 "@
656 {muls|mullw} %0,%1,%2
657 {muli|mulli} %0,%1,%2"
658 [(set_attr "type" "imul")])
659
68b40e7e 660(define_insn "mulsi3_no_mq"
ca7f5001
RK		 661 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
662 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
663 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 664 "! TARGET_POWER"
1fd4e8c1 665 "@
ca7f5001
RK		 666 mullw %0,%1,%2
667 mulli %0,%1,%2"
cfb557c4 668 [(set_attr "type" "imul")])
1fd4e8c1
RK		 669
670(define_insn ""
671 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9
RK		 672 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
673 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 674 (const_int 0)))
675 (clobber (match_scratch:SI 3 "=r"))
676 (clobber (match_scratch:SI 4 "=q"))]
ca7f5001
RK		 677 "TARGET_POWER"
678 "{muls.|mullw.} %3,%1,%2"
679 [(set_attr "type" "delayed_compare")])
680
681(define_insn ""
682 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
683 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
684 (match_operand:SI 2 "gpc_reg_operand" "r"))
685 (const_int 0)))
686 (clobber (match_scratch:SI 3 "=r"))]
25c341fa 687 "! TARGET_POWER"
ca7f5001 688 "mullw. %3,%1,%2"
1fd4e8c1
RK		 689 [(set_attr "type" "delayed_compare")])
690
691(define_insn ""
692 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9
RK		 693 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
694 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 695 (const_int 0)))
cd2b37d9 696 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 697 (mult:SI (match_dup 1) (match_dup 2)))
698 (clobber (match_scratch:SI 4 "=q"))]
ca7f5001
RK		 699 "TARGET_POWER"
700 "{muls.|mullw.} %0,%1,%2"
701 [(set_attr "type" "delayed_compare")])
702
703(define_insn ""
704 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
705 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
706 (match_operand:SI 2 "gpc_reg_operand" "r"))
707 (const_int 0)))
708 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
709 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 710 "! TARGET_POWER"
ca7f5001 711 "mullw. %0,%1,%2"
1fd4e8c1
RK		 712 [(set_attr "type" "delayed_compare")])
713
714;; Operand 1 is divided by operand 2; quotient goes to operand
715;; 0 and remainder to operand 3.
716;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
717
718(define_insn "divmodsi4"
cd2b37d9
RK		 719 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
720 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
721 (match_operand:SI 2 "gpc_reg_operand" "r")))
722 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
1fd4e8c1 723 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 724 "TARGET_POWER"
cfb557c4
RK		 725 "divs %0,%1,%2"
726 [(set_attr "type" "idiv")])
1fd4e8c1 727
ca7f5001
RK		 728(define_insn ""
729 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
730 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
731 (match_operand:SI 2 "gpc_reg_operand" "r")))]
732 "TARGET_POWERPC"
733 "divw %0, %1, %2"
734 [(set_attr "type" "idiv")])
735
736(define_insn "udivsi3"
737 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
738 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
739 (match_operand:SI 2 "gpc_reg_operand" "r")))]
740 "TARGET_POWERPC"
741 "divwu %0, %1, %2"
742 [(set_attr "type" "idiv")])
743
1fd4e8c1 744;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001
RK		 745;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
746;; used; for PowerPC, force operands into register and do a normal divide.
1fd4e8c1 747(define_expand "divsi3"
cd2b37d9
RK		 748 [(set (match_operand:SI 0 "gpc_reg_operand" "")
749 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 750 (match_operand:SI 2 "reg_or_cint_operand" "")))]
751 ""
752 "
753{
ca7f5001
RK		 754 if (GET_CODE (operands[2]) == CONST_INT
755 && exact_log2 (INTVAL (operands[2])) >= 0)
756 ;
25c341fa 757 else if (! TARGET_POWERPC)
1fd4e8c1 758 FAIL;
405c5495
RK		 759 else
760 operands[2] = force_reg (SImode, operands[2]);
1fd4e8c1
RK		 761}")
762
763(define_expand "modsi3"
85644414
RK		 764 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
765 (use (match_operand:SI 1 "gpc_reg_operand" ""))
405c5495 766 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
39b52ba2 767 ""
1fd4e8c1
RK		 768 "
769{
39b52ba2
RK		 770 int i = exact_log2 (INTVAL (operands[2]));
771 rtx temp1;
772 rtx temp2;
773
405c5495 774 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
39b52ba2
RK		 775 FAIL;
776
777 temp1 = gen_reg_rtx (SImode);
778 temp2 = gen_reg_rtx (SImode);
1fd4e8c1 779
85644414 780 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
39b52ba2 781 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
85644414
RK		 782 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
783 DONE;
784
1fd4e8c1
RK		 785}")
786
787(define_insn ""
cd2b37d9
RK		 788 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
789 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 790 (match_operand:SI 2 "const_int_operand" "N")))]
791 "exact_log2 (INTVAL (operands[2])) >= 0"
ca7f5001 792 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
b19003d8 793 [(set_attr "length" "8")])
1fd4e8c1
RK		 794
795(define_insn ""
796 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9 797 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 798 (match_operand:SI 2 "const_int_operand" "N")))
799 (clobber (match_scratch:SI 3 "=r"))]
800 "exact_log2 (INTVAL (operands[2])) >= 0"
ca7f5001 801 "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3"
b19003d8
RK		 802 [(set_attr "type" "compare")
803 (set_attr "length" "8")])
1fd4e8c1
RK		 804
805(define_insn ""
806 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9 807 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 808 (match_operand:SI 2 "const_int_operand" "N")))
cd2b37d9 809 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 810 (div:SI (match_dup 1) (match_dup 2)))]
811 "exact_log2 (INTVAL (operands[2])) >= 0"
ca7f5001 812 "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0"
b19003d8
RK		 813 [(set_attr "type" "compare")
814 (set_attr "length" "8")])
1fd4e8c1
RK		 815
816(define_insn ""
cd2b37d9 817 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 818 (udiv:SI
819 (plus:DI (lshift:DI
cd2b37d9 820 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 821 (const_int 32))
23a900dc 822 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 823 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 824 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1
RK		 825 (umod:SI
826 (plus:DI (lshift:DI
827 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 828 (zero_extend:DI (match_dup 4)))
1fd4e8c1
RK		 829 (match_dup 3)))]
830
ca7f5001 831 "TARGET_POWER"
cfb557c4
RK		 832 "div %0,%1,%3"
833 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 834
835;; To do unsigned divide we handle the cases of the divisor looking like a
836;; negative number. If it is a constant that is less than 2**31, we don't
837;; have to worry about the branches. So make a few subroutines here.
838;;
839;; First comes the normal case.
840(define_expand "udivmodsi4_normal"
841 [(set (match_dup 4) (const_int 0))
842 (parallel [(set (match_operand:SI 0 "" "")
843 (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
844 (const_int 32))
845 (zero_extend:DI (match_operand:SI 1 "" "")))
846 (match_operand:SI 2 "" "")))
847 (set (match_operand:SI 3 "" "")
848 (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
849 (const_int 32))
850 (zero_extend:DI (match_dup 1)))
851 (match_dup 2)))])]
ca7f5001 852 "TARGET_POWER"
1fd4e8c1
RK		 853 "
854{ operands[4] = gen_reg_rtx (SImode); }")
855
856;; This handles the branches.
857(define_expand "udivmodsi4_tests"
858 [(set (match_operand:SI 0 "" "") (const_int 0))
859 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
860 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
861 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
862 (label_ref (match_operand:SI 4 "" "")) (pc)))
863 (set (match_dup 0) (const_int 1))
864 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
865 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
866 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
867 (label_ref (match_dup 4)) (pc)))]
ca7f5001 868 "TARGET_POWER"
1fd4e8c1
RK		 869 "
870{ operands[5] = gen_reg_rtx (CCUNSmode);
871 operands[6] = gen_reg_rtx (CCmode);
872}")
873
874(define_expand "udivmodsi4"
cd2b37d9
RK		 875 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
876 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 877 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 878 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 879 (umod:SI (match_dup 1) (match_dup 2)))])]
ca7f5001 880 "TARGET_POWER"
1fd4e8c1
RK		 881 "
882{
883 rtx label = 0;
884
885 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
886 {
887 operands[2] = force_reg (SImode, operands[2]);
888 label = gen_label_rtx ();
889 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
890 operands[3], label));
891 }
892 else
893 operands[2] = force_reg (SImode, operands[2]);
894
895 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
896 operands[3]));
897 if (label)
898 emit_label (label);
899
900 DONE;
901}")
902
903(define_insn "andsi3"
cd2b37d9
RK		 904 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
905 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1fd4e8c1
RK		 906 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
907 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
908 ""
909 "@
910 and %0,%1,%2
ca7f5001
RK		 911 {rlinm|rlwinm} %0,%1,0,%m2,%M2
912 {andil.|andi.} %0,%1,%b2
913 {andiu.|andis.} %0,%1,%u2")
1fd4e8c1
RK		 914
915(define_insn ""
916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
cd2b37d9 917 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1fd4e8c1
RK		 918 (match_operand:SI 2 "and_operand" "r,K,J,L"))
919 (const_int 0)))
920 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
921 ""
922 "@
923 and. %3,%1,%2
ca7f5001
RK		 924 {andil.|andi.} %3,%1,%b2
925 {andiu.|andis.} %3,%1,%u2
926 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2"
1fd4e8c1
RK		 927 [(set_attr "type" "compare,compare,compare,delayed_compare")])
928
929(define_insn ""
930 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
cd2b37d9 931 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1fd4e8c1
RK		 932 (match_operand:SI 2 "and_operand" "r,K,J,L"))
933 (const_int 0)))
cd2b37d9 934 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 935 (and:SI (match_dup 1) (match_dup 2)))]
936 ""
937 "@
938 and. %0,%1,%2
ca7f5001
RK		 939 {andil.|andi.} %0,%1,%b2
940 {andiu.|andis.} %0,%1,%u2
941 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2"
b19003d8 942 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1fd4e8c1 943
f357808b
RK		 944;; Take a AND with a constant that cannot be done in a single insn and try to
945;; split it into two insns. This does not verify that the insns are valid
946;; since this need not be done as combine will do it.
947
948(define_split
cd2b37d9
RK		 949 [(set (match_operand:SI 0 "gpc_reg_operand" "")
950 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
f357808b
RK		 951 (match_operand:SI 2 "non_and_cint_operand" "")))]
952 ""
953 [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
954 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
955 "
956{
957 int maskval = INTVAL (operands[2]);
958 int i, transitions, last_bit_value;
959 int orig = maskval, first_c = maskval, second_c;
960
961 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
962 the low-order bit and count for the third transition. When we get there,
963 make a first mask that has everything to the left of that position
964 a one. Then make the second mask to turn off whatever else is needed. */
965
966 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
967 {
968 if (((maskval >>= 1) & 1) != last_bit_value)
969 last_bit_value ^= 1, transitions++;
970
971 if (transitions > 2)
972 {
973 first_c |= (~0) << i;
974 break;
975 }
976 }
977
978 second_c = orig | ~ first_c;
979
980 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
981 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
982}")
983
984(define_insn "iorsi3"
cd2b37d9
RK		 985 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
986 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1fd4e8c1
RK		 987 (match_operand:SI 2 "logical_operand" "r,K,J")))]
988 ""
989 "@
990 or %0,%1,%2
ca7f5001
RK		 991 {oril|ori} %0,%1,%b2
992 {oriu|oris} %0,%1,%u2")
1fd4e8c1
RK		 993
994(define_insn ""
995 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9
RK		 996 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
997 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 998 (const_int 0)))
999 (clobber (match_scratch:SI 3 "=r"))]
1000 ""
1001 "or. %3,%1,%2"
1002 [(set_attr "type" "compare")])
1003
1004(define_insn ""
1005 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9
RK		 1006 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1007 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 1008 (const_int 0)))
cd2b37d9 1009 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1010 (ior:SI (match_dup 1) (match_dup 2)))]
1011 ""
1012 "or. %0,%1,%2"
1013 [(set_attr "type" "compare")])
1014
f357808b
RK		 1015;; Split an IOR that we can't do in one insn into two insns, each of which
1016;; does one 16-bit part. This is used by combine.
1017
1018(define_split
cd2b37d9
RK		 1019 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1020 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
f357808b 1021 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1fd4e8c1 1022 ""
f357808b
RK		 1023 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
1024 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
1025"
1fd4e8c1 1026{
f357808b
RK		 1027 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1028 INTVAL (operands[2]) & 0xffff0000);
1029 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1fd4e8c1
RK		 1030}")
1031
f357808b 1032(define_insn "xorsi3"
cd2b37d9
RK		 1033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1034 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1fd4e8c1
RK		 1035 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1036 ""
1037 "@
1038 xor %0,%1,%2
ca7f5001
RK		 1039 {xoril|xori} %0,%1,%b2
1040 {xoriu|xoris} %0,%1,%u2")
1fd4e8c1
RK		 1041
1042(define_insn ""
1043 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9
RK		 1044 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1045 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 1046 (const_int 0)))
1047 (clobber (match_scratch:SI 3 "=r"))]
1048 ""
1049 "xor. %3,%1,%2"
1050 [(set_attr "type" "compare")])
1051
1052(define_insn ""
1053 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9
RK		 1054 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1055 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 1056 (const_int 0)))
cd2b37d9 1057 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1058 (xor:SI (match_dup 1) (match_dup 2)))]
1059 ""
1060 "xor. %0,%1,%2"
1061 [(set_attr "type" "compare")])
1062
f357808b
RK		 1063;; Split an XOR that we can't do in one insn into two insns, each of which
1064;; does one 16-bit part. This is used by combine.
1065
1066(define_split
cd2b37d9
RK		 1067 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1068 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
f357808b 1069 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1fd4e8c1 1070 ""
f357808b
RK		 1071 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
1072 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
1073"
1fd4e8c1 1074{
f357808b
RK		 1075 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1076 INTVAL (operands[2]) & 0xffff0000);
1077 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1fd4e8c1
RK		 1078}")
1079
1080(define_insn ""
cd2b37d9
RK		 1081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1082 (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1083 (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1fd4e8c1
RK		 1084 ""
1085 "eqv %0,%1,%2")
1086
1087(define_insn ""
1088 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9
RK		 1089 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1090 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1
RK		 1091 (const_int 0)))
1092 (clobber (match_scratch:SI 3 "=r"))]
1093 ""
1094 "eqv. %3,%1,%2"
1095 [(set_attr "type" "compare")])
1096
1097(define_insn ""
1098 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9
RK		 1099 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1100 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 1101 (const_int 0)))
cd2b37d9 1102 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1103 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
1104 ""
1105 "eqv. %0,%1,%2"
1106 [(set_attr "type" "compare")])
1107
1108(define_insn ""
cd2b37d9
RK		 1109 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1110 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1111 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 1112 ""
1113 "andc %0,%2,%1")
1114
1115(define_insn ""
1116 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9
RK		 1117 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1118 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 1119 (const_int 0)))
1120 (clobber (match_scratch:SI 3 "=r"))]
1121 ""
1122 "andc. %3,%2,%1"
1123 [(set_attr "type" "compare")])
1124
1125(define_insn ""
1126 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9
RK		 1127 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1128 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 1129 (const_int 0)))
cd2b37d9 1130 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1131 (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
1132 ""
1133 "andc. %0,%2,%1"
1134 [(set_attr "type" "compare")])
1135
1136(define_insn ""
cd2b37d9
RK		 1137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1138 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1139 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 1140 ""
1141 "orc %0,%2,%1")
1142
1143(define_insn ""
1144 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9
RK		 1145 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1146 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 1147 (const_int 0)))
1148 (clobber (match_scratch:SI 3 "=r"))]
1149 ""
1150 "orc. %3,%2,%1"
1151 [(set_attr "type" "compare")])
1152
1153(define_insn ""
1154 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9
RK		 1155 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1156 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 1157 (const_int 0)))
cd2b37d9 1158 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1159 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
1160 ""
1161 "orc. %0,%2,%1"
1162 [(set_attr "type" "compare")])
1163
1164(define_insn ""
cd2b37d9
RK		 1165 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1167 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1fd4e8c1
RK		 1168 ""
1169 "nand %0,%1,%2")
1170
1171(define_insn ""
1172 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9
RK		 1173 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1174 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1
RK		 1175 (const_int 0)))
1176 (clobber (match_scratch:SI 3 "=r"))]
1177 ""
1178 "nand. %3,%1,%2"
1179 [(set_attr "type" "compare")])
1180
1181(define_insn ""
1182 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9
RK		 1183 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1184 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 1185 (const_int 0)))
cd2b37d9 1186 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1187 (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1188 ""
1189 "nand. %0,%1,%2"
1190 [(set_attr "type" "compare")])
1191
1192(define_insn ""
cd2b37d9
RK		 1193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1194 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1195 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1fd4e8c1
RK		 1196 ""
1197 "nor %0,%1,%2")
1198
1199(define_insn ""
1200 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9
RK		 1201 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1202 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1
RK		 1203 (const_int 0)))
1204 (clobber (match_scratch:SI 3 "=r"))]
1205 ""
1206 "nor. %3,%1,%2"
1207 [(set_attr "type" "compare")])
1208
1209(define_insn ""
1210 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9
RK		 1211 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1212 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 1213 (const_int 0)))
cd2b37d9 1214 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1215 (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1216 ""
1217 "nor. %0,%1,%2"
1218 [(set_attr "type" "compare")])
1219
1220;; maskir insn. We need four forms because things might be in arbitrary
1221;; orders. Don't define forms that only set CR fields because these
1222;; would modify an input register.
1223
1224(define_insn ""
cd2b37d9 1225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 1226 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1227 (match_operand:SI 1 "gpc_reg_operand" "0"))
1228 (and:SI (match_dup 2)
cd2b37d9 1229 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 1230 "TARGET_POWER"
01def764 1231 "maskir %0,%3,%2")
1fd4e8c1
RK		 1232
1233(define_insn ""
1234 [(set (match_operand:SI 0 "register_operand" "=r")
01def764
RK		 1235 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1236 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 1237 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 1238 (match_dup 2))))]
ca7f5001 1239 "TARGET_POWER"
01def764 1240 "maskir %0,%3,%2")
1fd4e8c1
RK		 1241
1242(define_insn ""
cd2b37d9 1243 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 1244 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 1245 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 1246 (and:SI (not:SI (match_dup 2))
1247 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 1248 "TARGET_POWER"
01def764 1249 "maskir %0,%3,%2")
1fd4e8c1
RK		 1250
1251(define_insn ""
cd2b37d9
RK		 1252 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1253 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 1254 (match_operand:SI 2 "gpc_reg_operand" "r"))
1255 (and:SI (not:SI (match_dup 2))
1256 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 1257 "TARGET_POWER"
01def764 1258 "maskir %0,%3,%2")
1fd4e8c1
RK		 1259
1260(define_insn ""
1261 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1262 (compare:CC
01def764
RK		 1263 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1264 (match_operand:SI 1 "gpc_reg_operand" "0"))
1265 (and:SI (match_dup 2)
cd2b37d9 1266 (match_operand:SI 3 "gpc_reg_operand" "r")))
1fd4e8c1 1267 (const_int 0)))
cd2b37d9 1268 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 1269 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
1270 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 1271 "TARGET_POWER"
01def764 1272 "maskir. %0,%3,%2"
1fd4e8c1
RK		 1273 [(set_attr "type" "compare")])
1274
1275(define_insn ""
1276 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1277 (compare:CC
01def764
RK		 1278 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1279 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 1280 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 1281 (match_dup 2)))
1fd4e8c1
RK		 1282 (const_int 0)))
1283 (set (match_operand:SI 0 "register_operand" "=r")
01def764
RK		 1284 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
1285 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 1286 "TARGET_POWER"
01def764 1287 "maskir. %0,%3,%2"
1fd4e8c1
RK		 1288 [(set_attr "type" "compare")])
1289
1290(define_insn ""
1291 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1292 (compare:CC
01def764 1293 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 1294 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 1295 (and:SI (not:SI (match_dup 2))
1296 (match_operand:SI 1 "gpc_reg_operand" "0")))
1fd4e8c1 1297 (const_int 0)))
cd2b37d9 1298 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 1299 (ior:SI (and:SI (match_dup 2) (match_dup 3))
1300 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 1301 "TARGET_POWER"
01def764 1302 "maskir. %0,%3,%2"
1fd4e8c1
RK		 1303 [(set_attr "type" "compare")])
1304
1305(define_insn ""
1306 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1307 (compare:CC
cd2b37d9 1308 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 1309 (match_operand:SI 2 "gpc_reg_operand" "r"))
1310 (and:SI (not:SI (match_dup 2))
1311 (match_operand:SI 1 "gpc_reg_operand" "0")))
1fd4e8c1 1312 (const_int 0)))
cd2b37d9 1313 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 1314 (ior:SI (and:SI (match_dup 3) (match_dup 2))
1315 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 1316 "TARGET_POWER"
01def764 1317 "maskir. %0,%3,%2"
1fd4e8c1
RK		 1318 [(set_attr "type" "compare")])
1319\f
1320;; Rotate and shift insns, in all their variants. These support shifts,
1321;; field inserts and extracts, and various combinations thereof.
1322(define_insn "insv"
cd2b37d9 1323 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 1324 (match_operand:SI 1 "const_int_operand" "i")
1325 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 1326 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 1327 ""
1328 "*
1329{
1330 int start = INTVAL (operands[2]) & 31;
1331 int size = INTVAL (operands[1]) & 31;
1332
1333 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
1334 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
ca7f5001 1335 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
1fd4e8c1
RK		 1336}")
1337
1338(define_insn "extzv"
cd2b37d9
RK		 1339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1340 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1341 (match_operand:SI 2 "const_int_operand" "i")
1342 (match_operand:SI 3 "const_int_operand" "i")))]
1343 ""
1344 "*
1345{
1346 int start = INTVAL (operands[3]) & 31;
1347 int size = INTVAL (operands[2]) & 31;
1348
1349 if (start + size >= 32)
1350 operands[3] = const0_rtx;
1351 else
1352 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
ca7f5001 1353 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 1354}")
1355
1356(define_insn ""
1357 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9 1358 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1359 (match_operand:SI 2 "const_int_operand" "i")
1360 (match_operand:SI 3 "const_int_operand" "i"))
1361 (const_int 0)))
1362 (clobber (match_scratch:SI 4 "=r"))]
1363 ""
1364 "*
1365{
1366 int start = INTVAL (operands[3]) & 31;
1367 int size = INTVAL (operands[2]) & 31;
1368
a7a975e1
RK		 1369 /* If the bitfield being tested fits in the upper or lower half of a
1370 word, it is possible to use andiu. or andil. to test it. This is
1371 useful because the condition register set-use delay is smaller for
1372 andi[ul]. than for rlinm. This doesn't work when the starting bit
1373 position is 0 because the LT and GT bits may be set wrong. */
1374
1375 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43
RK		 1376 {
1377 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1378 ((1 << (16 - (start & 15)))
1379 - (1 << (16 - (start & 15) - size))));
1380 if (start < 16)
ca7f5001 1381 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 1382 else
ca7f5001 1383 return \"{andil.|andi.} %4,%1,%3\";
df031c43
RK		 1384 }
1385
1fd4e8c1
RK		 1386 if (start + size >= 32)
1387 operands[3] = const0_rtx;
1388 else
1389 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
ca7f5001 1390 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1
RK		 1391}"
1392 [(set_attr "type" "compare")])
1393
1394(define_insn ""
1395 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
cd2b37d9 1396 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1397 (match_operand:SI 2 "const_int_operand" "i")
1398 (match_operand:SI 3 "const_int_operand" "i"))
1399 (const_int 0)))
cd2b37d9 1400 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1401 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
1402 ""
1403 "*
1404{
1405 int start = INTVAL (operands[3]) & 31;
1406 int size = INTVAL (operands[2]) & 31;
1407
a7a975e1 1408 if (start >= 16 && start + size == 32)
df031c43 1409 {
a7a975e1 1410 operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
ca7f5001 1411 return \"{andil.|andi.} %0,%1,%3\";
df031c43
RK		 1412 }
1413
1fd4e8c1
RK		 1414 if (start + size >= 32)
1415 operands[3] = const0_rtx;
1416 else
1417 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
ca7f5001 1418 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 1419}"
1420 [(set_attr "type" "delayed_compare")])
1421
1422(define_insn "rotlsi3"
cd2b37d9
RK		 1423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1424 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1425 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
1426 ""
ca7f5001 1427 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
1fd4e8c1
RK		 1428
1429(define_insn ""
1430 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
cd2b37d9 1431 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1432 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1433 (const_int 0)))
1434 (clobber (match_scratch:SI 3 "=r"))]
1435 ""
ca7f5001 1436 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
1fd4e8c1
RK		 1437 [(set_attr "type" "delayed_compare")])
1438
1439(define_insn ""
1440 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
cd2b37d9 1441 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1442 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1443 (const_int 0)))
cd2b37d9 1444 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1445 (rotate:SI (match_dup 1) (match_dup 2)))]
1446 ""
ca7f5001 1447 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff"
1fd4e8c1
RK		 1448 [(set_attr "type" "delayed_compare")])
1449
1450(define_insn ""
cd2b37d9
RK		 1451 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1452 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1453 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1454 (match_operand:SI 3 "mask_operand" "L")))]
1455 ""
ca7f5001 1456 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 1457
1458(define_insn ""
1459 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1460 (compare:CC (and:SI
cd2b37d9 1461 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1462 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1463 (match_operand:SI 3 "mask_operand" "L"))
1464 (const_int 0)))
1465 (clobber (match_scratch:SI 4 "=r"))]
1466 ""
ca7f5001 1467 "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3"
1fd4e8c1
RK		 1468 [(set_attr "type" "delayed_compare")])
1469
1470(define_insn ""
1471 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1472 (compare:CC (and:SI
cd2b37d9 1473 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1474 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1475 (match_operand:SI 3 "mask_operand" "L"))
1476 (const_int 0)))
cd2b37d9 1477 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1478 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1479 ""
ca7f5001 1480 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3"
1fd4e8c1
RK		 1481 [(set_attr "type" "delayed_compare")])
1482
1483(define_insn ""
cd2b37d9 1484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1485 (zero_extend:SI
1486 (subreg:QI
cd2b37d9 1487 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1488 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1489 ""
ca7f5001 1490 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1
RK		 1491
1492(define_insn ""
1493 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1494 (compare:CC (zero_extend:SI
1495 (subreg:QI
cd2b37d9 1496 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1497 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1498 (const_int 0)))
1499 (clobber (match_scratch:SI 3 "=r"))]
1500 ""
ca7f5001 1501 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff"
1fd4e8c1
RK		 1502 [(set_attr "type" "delayed_compare")])
1503
1504(define_insn ""
1505 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1506 (compare:CC (zero_extend:SI
1507 (subreg:QI
cd2b37d9 1508 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1509 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1510 (const_int 0)))
cd2b37d9 1511 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1512 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1513 ""
ca7f5001 1514 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff"
1fd4e8c1
RK		 1515 [(set_attr "type" "delayed_compare")])
1516
1517(define_insn ""
cd2b37d9 1518 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1519 (zero_extend:SI
1520 (subreg:HI
cd2b37d9 1521 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1522 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1523 ""
ca7f5001 1524 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
1fd4e8c1
RK		 1525
1526(define_insn ""
1527 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1528 (compare:CC (zero_extend:SI
1529 (subreg:HI
cd2b37d9 1530 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1531 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1532 (const_int 0)))
1533 (clobber (match_scratch:SI 3 "=r"))]
1534 ""
ca7f5001 1535 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff"
1fd4e8c1
RK		 1536 [(set_attr "type" "delayed_compare")])
1537
1538(define_insn ""
1539 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1540 (compare:CC (zero_extend:SI
1541 (subreg:HI
cd2b37d9 1542 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1543 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1544 (const_int 0)))
cd2b37d9 1545 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1546 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1547 ""
ca7f5001 1548 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff"
1fd4e8c1
RK		 1549 [(set_attr "type" "delayed_compare")])
1550
1551;; Note that we use "sle." instead of "sl." so that we can set
1552;; SHIFT_COUNT_TRUNCATED.
1553
ca7f5001
RK		 1554(define_expand "ashlsi3"
1555 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1556 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1557 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1558 ""
1559 "
1560{
1561 if (TARGET_POWER)
1562 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
1563 else
25c341fa 1564 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 1565 DONE;
1566}")
1567
1568(define_insn "ashlsi3_power"
cd2b37d9
RK		 1569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1570 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 1571 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1572 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 1573 "TARGET_POWER"
1fd4e8c1
RK		 1574 "@
1575 sle %0,%1,%2
ca7f5001
RK		 1576 {sli|slwi} %0,%1,%h2"
1577 [(set_attr "length" "8")])
1578
25c341fa 1579(define_insn "ashlsi3_no_power"
ca7f5001
RK		 1580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1581 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1582 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 1583 "! TARGET_POWER"
ca7f5001 1584 "slw%I2 %0,%1,%2"
b19003d8 1585 [(set_attr "length" "8")])
1fd4e8c1
RK		 1586
1587(define_insn ""
1588 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
cd2b37d9 1589 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 1590 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1591 (const_int 0)))
1592 (clobber (match_scratch:SI 3 "=r,r"))
1593 (clobber (match_scratch:SI 4 "=q,X"))]
ca7f5001 1594 "TARGET_POWER"
1fd4e8c1
RK		 1595 "@
1596 sle. %3,%1,%2
ca7f5001
RK		 1597 {sli.|slwi.} %3,%1,%h2"
1598 [(set_attr "type" "delayed_compare")])
25c341fa 1599
ca7f5001
RK		 1600(define_insn ""
1601 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1602 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1603 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1604 (const_int 0)))
1605 (clobber (match_scratch:SI 3 "=r"))]
1606 "TARGET_POWERPC"
1607 "slw%I2. %3,%1,%2"
1fd4e8c1
RK		 1608 [(set_attr "type" "delayed_compare")])
1609
1610(define_insn ""
1611 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
cd2b37d9 1612 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 1613 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1614 (const_int 0)))
cd2b37d9 1615 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1616 (ashift:SI (match_dup 1) (match_dup 2)))
1617 (clobber (match_scratch:SI 4 "=q,X"))]
ca7f5001 1618 "TARGET_POWER"
1fd4e8c1
RK		 1619 "@
1620 sle. %0,%1,%2
ca7f5001
RK		 1621 {sli.|slwi.} %0,%1,%h2"
1622 [(set_attr "type" "delayed_compare")])
25c341fa 1623
ca7f5001
RK		 1624(define_insn ""
1625 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1626 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1627 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1628 (const_int 0)))
1629 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1630 (ashift:SI (match_dup 1) (match_dup 2)))]
1631 "TARGET_POWERPC"
1632 "slw%I2. %0,%1,%2"
1fd4e8c1
RK		 1633 [(set_attr "type" "delayed_compare")])
1634
1635(define_insn ""
cd2b37d9
RK		 1636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1637 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1638 (match_operand:SI 2 "const_int_operand" "i"))
1639 (match_operand:SI 3 "mask_operand" "L")))]
1640 "includes_lshift_p (operands[2], operands[3])"
ca7f5001 1641 "{rlinm|rlwinm} %0,%h1,%h2,%m3,%M3")
1fd4e8c1
RK		 1642
1643(define_insn ""
1644 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1645 (compare:CC
cd2b37d9 1646 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1647 (match_operand:SI 2 "const_int_operand" "i"))
1648 (match_operand:SI 3 "mask_operand" "L"))
1649 (const_int 0)))
1650 (clobber (match_scratch:SI 4 "=r"))]
1651 "includes_lshift_p (operands[2], operands[3])"
ca7f5001 1652 "{rlinm.|rlwinm.} %4,%h1,%h2,%m3,%M3"
1fd4e8c1
RK		 1653 [(set_attr "type" "delayed_compare")])
1654
1655(define_insn ""
1656 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1657 (compare:CC
cd2b37d9 1658 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1659 (match_operand:SI 2 "const_int_operand" "i"))
1660 (match_operand:SI 3 "mask_operand" "L"))
1661 (const_int 0)))
cd2b37d9 1662 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1663 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1664 "includes_lshift_p (operands[2], operands[3])"
ca7f5001 1665 "{rlinm.|rlwinm.} %0,%h1,%h2,%m3,%M3"
1fd4e8c1
RK		 1666 [(set_attr "type" "delayed_compare")])
1667
ca7f5001 1668;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 1669;; "sli x,x,0".
ca7f5001
RK		 1670(define_expand "lshrsi3"
1671 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1672 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1673 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1674 ""
1675 "
1676{
1677 if (TARGET_POWER)
1678 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
1679 else
25c341fa 1680 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 1681 DONE;
1682}")
1683
1684(define_insn "lshrsi3_power"
cd2b37d9
RK		 1685 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1686 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 1687 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1688 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 1689 "TARGET_POWER"
1fd4e8c1
RK		 1690 "@
1691 sre %0,%1,%2
ca7f5001
RK		 1692 {s%A2i|s%A2wi} %0,%1,%h2")
1693
25c341fa 1694(define_insn "lshrsi3_no_power"
ca7f5001
RK		 1695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1696 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1697 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 1698 "! TARGET_POWER"
ca7f5001 1699 "srw%I2 %0,%1,%2")
1fd4e8c1
RK		 1700
1701(define_insn ""
1702 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
cd2b37d9 1703 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 1704 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1705 (const_int 0)))
1706 (clobber (match_scratch:SI 3 "=r,r"))
1707 (clobber (match_scratch:SI 4 "=q,X"))]
ca7f5001 1708 "TARGET_POWER"
1fd4e8c1
RK		 1709 "@
1710 sre. %3,%1,%2
ca7f5001
RK		 1711 {s%A2i.|s%A2wi.} %3,%1,%h2"
1712 [(set_attr "type" "delayed_compare")])
1713
1714(define_insn ""
1715 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1716 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1717 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1718 (const_int 0)))
1719 (clobber (match_scratch:SI 3 "=r"))]
25c341fa 1720 "! TARGET_POWER"
ca7f5001 1721 "srw%I2. %3,%1,%2"
1fd4e8c1
RK		 1722 [(set_attr "type" "delayed_compare")])
1723
1724(define_insn ""
1725 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
cd2b37d9 1726 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 1727 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1728 (const_int 0)))
cd2b37d9 1729 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1730 (lshiftrt:SI (match_dup 1) (match_dup 2)))
1731 (clobber (match_scratch:SI 4 "=q,X"))]
ca7f5001 1732 "TARGET_POWER"
1fd4e8c1
RK		 1733 "@
1734 sre. %0,%1,%2
ca7f5001
RK		 1735 {s%A2i.|s%A2wi.} %0,%1,%h2"
1736 [(set_attr "type" "delayed_compare")])
1737
1738(define_insn ""
1739 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1740 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1741 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1742 (const_int 0)))
1743 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1744 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 1745 "! TARGET_POWER"
ca7f5001 1746 "srw%I2. %0,%1,%2"
1fd4e8c1
RK		 1747 [(set_attr "type" "delayed_compare")])
1748
1749(define_insn ""
cd2b37d9
RK		 1750 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1751 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1752 (match_operand:SI 2 "const_int_operand" "i"))
1753 (match_operand:SI 3 "mask_operand" "L")))]
1754 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 1755 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 1756
1757(define_insn ""
1758 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1759 (compare:CC
cd2b37d9 1760 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1761 (match_operand:SI 2 "const_int_operand" "i"))
1762 (match_operand:SI 3 "mask_operand" "L"))
1763 (const_int 0)))
1764 (clobber (match_scratch:SI 4 "=r"))]
1765 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 1766 "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3"
1fd4e8c1
RK		 1767 [(set_attr "type" "delayed_compare")])
1768
1769(define_insn ""
1770 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1771 (compare:CC
cd2b37d9 1772 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1773 (match_operand:SI 2 "const_int_operand" "i"))
1774 (match_operand:SI 3 "mask_operand" "L"))
1775 (const_int 0)))
cd2b37d9 1776 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1777 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1778 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 1779 "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3"
1fd4e8c1
RK		 1780 [(set_attr "type" "delayed_compare")])
1781
1782(define_insn ""
cd2b37d9 1783 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1784 (zero_extend:SI
1785 (subreg:QI
cd2b37d9 1786 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1787 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1788 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
ca7f5001 1789 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 1790
1791(define_insn ""
1792 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1793 (compare:CC
1794 (zero_extend:SI
1795 (subreg:QI
cd2b37d9 1796 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1797 (match_operand:SI 2 "const_int_operand" "i")) 0))
1798 (const_int 0)))
1799 (clobber (match_scratch:SI 3 "=r"))]
1800 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
ca7f5001 1801 "{rlinm.|rlwinm.} %3,%1,%s2,0xff"
1fd4e8c1
RK		 1802 [(set_attr "type" "delayed_compare")])
1803
1804(define_insn ""
1805 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1806 (compare:CC
1807 (zero_extend:SI
1808 (subreg:QI
cd2b37d9 1809 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1810 (match_operand:SI 2 "const_int_operand" "i")) 0))
1811 (const_int 0)))
cd2b37d9 1812 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1813 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1814 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
ca7f5001 1815 "{rlinm.|rlwinm.} %0,%1,%s2,0xff"
1fd4e8c1
RK		 1816 [(set_attr "type" "delayed_compare")])
1817
1818(define_insn ""
cd2b37d9 1819 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1820 (zero_extend:SI
1821 (subreg:HI
cd2b37d9 1822 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1823 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1824 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
ca7f5001 1825 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 1826
1827(define_insn ""
1828 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1829 (compare:CC
1830 (zero_extend:SI
1831 (subreg:HI
cd2b37d9 1832 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1833 (match_operand:SI 2 "const_int_operand" "i")) 0))
1834 (const_int 0)))
1835 (clobber (match_scratch:SI 3 "=r"))]
1836 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
ca7f5001 1837 "{rlinm.|rlwinm.} %3,%1,%s2,0xffff"
1fd4e8c1
RK		 1838 [(set_attr "type" "delayed_compare")])
1839
1840(define_insn ""
1841 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1842 (compare:CC
1843 (zero_extend:SI
1844 (subreg:HI
cd2b37d9 1845 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1846 (match_operand:SI 2 "const_int_operand" "i")) 0))
1847 (const_int 0)))
cd2b37d9 1848 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 1849 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1850 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
ca7f5001 1851 "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
1fd4e8c1
RK		 1852 [(set_attr "type" "delayed_compare")])
1853
1854(define_insn ""
cd2b37d9 1855 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 1856 (const_int 1)
cd2b37d9
RK		 1857 (match_operand:SI 1 "gpc_reg_operand" "r"))
1858 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 1859 (const_int 31)))]
ca7f5001 1860 "TARGET_POWER"
1fd4e8c1
RK		 1861 "rrib %0,%1,%2")
1862
1863(define_insn ""
cd2b37d9 1864 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 1865 (const_int 1)
cd2b37d9
RK		 1866 (match_operand:SI 1 "gpc_reg_operand" "r"))
1867 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 1868 (const_int 31)))]
ca7f5001 1869 "TARGET_POWER"
1fd4e8c1
RK		 1870 "rrib %0,%1,%2")
1871
1872(define_insn ""
cd2b37d9 1873 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 1874 (const_int 1)
cd2b37d9
RK		 1875 (match_operand:SI 1 "gpc_reg_operand" "r"))
1876 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 1877 (const_int 1)
1878 (const_int 0)))]
ca7f5001 1879 "TARGET_POWER"
1fd4e8c1
RK		 1880 "rrib %0,%1,%2")
1881
ca7f5001
RK		 1882(define_expand "ashrsi3"
1883 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1884 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1885 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1886 ""
1887 "
1888{
1889 if (TARGET_POWER)
1890 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
1891 else
25c341fa 1892 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 1893 DONE;
1894}")
1895
1896(define_insn "ashrsi3_power"
cd2b37d9
RK		 1897 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1898 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 1899 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1900 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 1901 "TARGET_POWER"
1fd4e8c1
RK		 1902 "@
1903 srea %0,%1,%2
ca7f5001
RK		 1904 {srai|srawi} %0,%1,%h2")
1905
25c341fa 1906(define_insn "ashrsi3_no_power"
ca7f5001
RK		 1907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1908 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1909 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 1910 "! TARGET_POWER"
ca7f5001 1911 "sraw%I2 %0,%1,%2")
1fd4e8c1
RK		 1912
1913(define_insn ""
1914 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
cd2b37d9 1915 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 1916 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1917 (const_int 0)))
1918 (clobber (match_scratch:SI 3 "=r,r"))
1919 (clobber (match_scratch:SI 4 "=q,X"))]
ca7f5001 1920 "TARGET_POWER"
1fd4e8c1
RK		 1921 "@
1922 srea. %3,%1,%2
ca7f5001
RK		 1923 {srai.|srawi.} %3,%1,%h2"
1924 [(set_attr "type" "delayed_compare")])
1925
1926(define_insn ""
1927 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1928 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1929 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1930 (const_int 0)))
1931 (clobber (match_scratch:SI 3 "=r"))]
25c341fa 1932 "! TARGET_POWER"
ca7f5001 1933 "sraw%I2. %3,%1,%2"
1fd4e8c1
RK		 1934 [(set_attr "type" "delayed_compare")])
1935
1936(define_insn ""
1937 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
cd2b37d9 1938 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 1939 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1940 (const_int 0)))
cd2b37d9 1941 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1942 (ashiftrt:SI (match_dup 1) (match_dup 2)))
1943 (clobber (match_scratch:SI 4 "=q,X"))]
ca7f5001 1944 "TARGET_POWER"
1fd4e8c1
RK		 1945 "@
1946 srea. %0,%1,%2
7f340546 1947 {srai.|srawi.} %0,%1,%h2"
1fd4e8c1
RK		 1948 [(set_attr "type" "delayed_compare")])
1949
ca7f5001
RK		 1950(define_insn ""
1951 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1952 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1953 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1954 (const_int 0)))
1955 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1956 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 1957 "! TARGET_POWER"
ca7f5001
RK		 1958 "sraw%I2. %0,%1,%2"
1959 [(set_attr "type" "delayed_compare")])
1960
1fd4e8c1 1961(define_expand "extendqisi2"
ca7f5001
RK		 1962 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1963 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1964 ""
1965 "
1966{
1967 if (TARGET_POWER)
1968 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
1969 else
25c341fa 1970 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
ca7f5001
RK		 1971 DONE;
1972}")
1973
1974(define_expand "extendqisi2_power"
1fd4e8c1 1975 [(parallel [(set (match_dup 2)
cd2b37d9 1976 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1977 (const_int 24)))
1978 (clobber (scratch:SI))])
cd2b37d9 1979 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 1980 (ashiftrt:SI (match_dup 2)
1981 (const_int 24)))
1982 (clobber (scratch:SI))])]
ca7f5001
RK		 1983 "TARGET_POWER"
1984 "
1985{ operands[1] = gen_lowpart (SImode, operands[1]);
1986 operands[2] = gen_reg_rtx (SImode); }")
1987
25c341fa 1988(define_expand "extendqisi2_no_power"
ca7f5001
RK		 1989 [(set (match_dup 2)
1990 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1991 (const_int 24)))
1992 (set (match_operand:SI 0 "gpc_reg_operand" "")
1993 (ashiftrt:SI (match_dup 2)
1994 (const_int 24)))]
25c341fa 1995 "! TARGET_POWER"
1fd4e8c1
RK		 1996 "
1997{ operands[1] = gen_lowpart (SImode, operands[1]);
1998 operands[2] = gen_reg_rtx (SImode); }")
1999
2000(define_expand "extendqihi2"
ca7f5001
RK		 2001 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
2002 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
2003 ""
2004 "
2005{
2006 if (TARGET_POWER)
2007 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
2008 else
25c341fa 2009 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
ca7f5001
RK		 2010 DONE;
2011}")
2012
2013(define_expand "extendqihi2_power"
1fd4e8c1 2014 [(parallel [(set (match_dup 2)
cd2b37d9 2015 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 2016 (const_int 24)))
2017 (clobber (scratch:SI))])
cd2b37d9 2018 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 2019 (ashiftrt:SI (match_dup 2)
2020 (const_int 24)))
2021 (clobber (scratch:SI))])]
ca7f5001
RK		 2022 "TARGET_POWER"
2023 "
2024{ operands[0] = gen_lowpart (SImode, operands[0]);
2025 operands[1] = gen_lowpart (SImode, operands[1]);
2026 operands[2] = gen_reg_rtx (SImode); }")
2027
25c341fa 2028(define_expand "extendqihi2_no_power"
ca7f5001
RK		 2029 [(set (match_dup 2)
2030 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
2031 (const_int 24)))
2032 (set (match_operand:HI 0 "gpc_reg_operand" "")
2033 (ashiftrt:SI (match_dup 2)
2034 (const_int 24)))]
25c341fa 2035 "! TARGET_POWER"
1fd4e8c1
RK		 2036 "
2037{ operands[0] = gen_lowpart (SImode, operands[0]);
2038 operands[1] = gen_lowpart (SImode, operands[1]);
2039 operands[2] = gen_reg_rtx (SImode); }")
2040\f
2041;; Floating-point insns, excluding normal data motion.
2042;;
ca7f5001
RK		 2043;; PowerPC has a full set of single-precision floating point instructions.
2044;;
2045;; For the POWER architecture, we pretend that we have both SFmode and
2046;; DFmode insns, while, in fact, all fp insns are actually done in double.
2047;; The only conversions we will do will be when storing to memory. In that
2048;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 2049;;
2050;; Note that when we store into a single-precision memory location, we need to
2051;; use the frsp insn first. If the register being stored isn't dead, we
2052;; need a scratch register for the frsp. But this is difficult when the store
2053;; is done by reload. It is not incorrect to do the frsp on the register in
2054;; this case, we just lose precision that we would have otherwise gotten but
2055;; is not guaranteed. Perhaps this should be tightened up at some point.
2056
2057(define_insn "extendsfdf2"
cd2b37d9
RK		 2058 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2059 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1fd4e8c1
RK		 2060 ""
2061 "*
2062{
2063 if (REGNO (operands[0]) == REGNO (operands[1]))
2064 return \"\";
2065 else
2066 return \"fmr %0,%1\";
2067}"
2068 [(set_attr "type" "fp")])
2069
2070(define_insn "truncdfsf2"
cd2b37d9
RK		 2071 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2072 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1fd4e8c1 2073 ""
dcac138d 2074 "frsp %0,%1"
1fd4e8c1
RK		 2075 [(set_attr "type" "fp")])
2076
2077(define_insn "negsf2"
cd2b37d9
RK		 2078 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2079 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1fd4e8c1
RK		 2080 ""
2081 "fneg %0,%1"
2082 [(set_attr "type" "fp")])
2083
2084(define_insn "abssf2"
cd2b37d9
RK		 2085 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2086 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
1fd4e8c1
RK		 2087 ""
2088 "fabs %0,%1"
2089 [(set_attr "type" "fp")])
2090
2091(define_insn ""
cd2b37d9
RK		 2092 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2093 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
1fd4e8c1
RK		 2094 ""
2095 "fnabs %0,%1"
2096 [(set_attr "type" "fp")])
2097
ca7f5001
RK		 2098(define_expand "addsf3"
2099 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2100 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2101 (match_operand:SF 2 "gpc_reg_operand" "")))]
2102 ""
2103 "")
2104
2105(define_insn ""
cd2b37d9
RK		 2106 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2107 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2108 (match_operand:SF 2 "gpc_reg_operand" "f")))]
b26c8351
RK		 2109 "TARGET_POWERPC"
2110 "fadds %0,%1,%2"
ca7f5001
RK		 2111 [(set_attr "type" "fp")])
2112
2113(define_insn ""
2114 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2115 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2116 (match_operand:SF 2 "gpc_reg_operand" "f")))]
b26c8351
RK		 2117 "TARGET_POWER"
2118 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 2119 [(set_attr "type" "fp")])
2120
2121(define_expand "subsf3"
2122 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2123 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2124 (match_operand:SF 2 "gpc_reg_operand" "")))]
1fd4e8c1 2125 ""
ca7f5001
RK		 2126 "")
2127
2128(define_insn ""
2129 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2130 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2131 (match_operand:SF 2 "gpc_reg_operand" "f")))]
b26c8351
RK		 2132 "TARGET_POWERPC"
2133 "fsubs %0,%1,%2"
1fd4e8c1
RK		 2134 [(set_attr "type" "fp")])
2135
ca7f5001 2136(define_insn ""
cd2b37d9
RK		 2137 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2138 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2139 (match_operand:SF 2 "gpc_reg_operand" "f")))]
b26c8351
RK		 2140 "TARGET_POWER"
2141 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 2142 [(set_attr "type" "fp")])
2143
2144(define_expand "mulsf3"
2145 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2146 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
2147 (match_operand:SF 2 "gpc_reg_operand" "")))]
1fd4e8c1 2148 ""
ca7f5001
RK		 2149 "")
2150
2151(define_insn ""
2152 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2153 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2154 (match_operand:SF 2 "gpc_reg_operand" "f")))]
b26c8351
RK		 2155 "TARGET_POWERPC"
2156 "fmuls %0,%1,%2"
1fd4e8c1
RK		 2157 [(set_attr "type" "fp")])
2158
ca7f5001 2159(define_insn ""
cd2b37d9
RK		 2160 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2161 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2162 (match_operand:SF 2 "gpc_reg_operand" "f")))]
b26c8351
RK		 2163 "TARGET_POWER"
2164 "{fm|fmul} %0,%1,%2"
1fd4e8c1
RK		 2165 [(set_attr "type" "fp")])
2166
ca7f5001
RK		 2167(define_expand "divsf3"
2168 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2169 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
2170 (match_operand:SF 2 "gpc_reg_operand" "")))]
2171 ""
2172 "")
2173
2174(define_insn ""
cd2b37d9
RK		 2175 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2176 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2177 (match_operand:SF 2 "gpc_reg_operand" "f")))]
b26c8351
RK		 2178 "TARGET_POWERPC"
2179 "fdivs %0,%1,%2"
ca7f5001
RK		 2180 [(set_attr "type" "sdiv")])
2181
2182(define_insn ""
2183 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2184 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2185 (match_operand:SF 2 "gpc_reg_operand" "f")))]
b26c8351
RK		 2186 "TARGET_POWER"
2187 "{fd|fdiv} %0,%1,%2"
cfb557c4 2188 [(set_attr "type" "sdiv")])
1fd4e8c1
RK		 2189
2190(define_insn ""
cd2b37d9
RK		 2191 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2192 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2193 (match_operand:SF 2 "gpc_reg_operand" "f"))
2194 (match_operand:SF 3 "gpc_reg_operand" "f")))]
b26c8351
RK		 2195 "TARGET_POWERPC"
2196 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 2197 [(set_attr "type" "fp")])
2198
2199(define_insn ""
2200 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2201 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2202 (match_operand:SF 2 "gpc_reg_operand" "f"))
2203 (match_operand:SF 3 "gpc_reg_operand" "f")))]
b26c8351
RK		 2204 "TARGET_POWER"
2205 "{fma|fmadd} %0,%1,%2,%3"
1fd4e8c1
RK		 2206 [(set_attr "type" "fp")])
2207
2208(define_insn ""
cd2b37d9
RK		 2209 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2210 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2211 (match_operand:SF 2 "gpc_reg_operand" "f"))
2212 (match_operand:SF 3 "gpc_reg_operand" "f")))]
b26c8351
RK		 2213 "TARGET_POWERPC"
2214 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 2215 [(set_attr "type" "fp")])
2216
2217(define_insn ""
2218 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2219 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2220 (match_operand:SF 2 "gpc_reg_operand" "f"))
2221 (match_operand:SF 3 "gpc_reg_operand" "f")))]
b26c8351
RK		 2222 "TARGET_POWER"
2223 "{fms|fmsub} %0,%1,%2,%3"
1fd4e8c1
RK		 2224 [(set_attr "type" "fp")])
2225
2226(define_insn ""
cd2b37d9
RK		 2227 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2228 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2229 (match_operand:SF 2 "gpc_reg_operand" "f"))
2230 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
b26c8351
RK		 2231 "TARGET_POWERPC"
2232 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 2233 [(set_attr "type" "fp")])
2234
2235(define_insn ""
2236 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2237 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2238 (match_operand:SF 2 "gpc_reg_operand" "f"))
2239 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
b26c8351
RK		 2240 "TARGET_POWER"
2241 "{fnma|fnmadd} %0,%1,%2,%3"
1fd4e8c1
RK		 2242 [(set_attr "type" "fp")])
2243
2244(define_insn ""
cd2b37d9
RK		 2245 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2246 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2247 (match_operand:SF 2 "gpc_reg_operand" "f"))
2248 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
b26c8351
RK		 2249 "TARGET_POWERPC"
2250 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 2251 [(set_attr "type" "fp")])
2252
2253(define_insn ""
2254 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2255 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2256 (match_operand:SF 2 "gpc_reg_operand" "f"))
2257 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
b26c8351
RK		 2258 "TARGET_POWER"
2259 "{fnms|fnmsub} %0,%1,%2,%3"
1fd4e8c1
RK		 2260 [(set_attr "type" "fp")])
2261
ca7f5001
RK		 2262(define_expand "sqrtsf2"
2263 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2264 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
8e871c05 2265 "TARGET_PPCFPX || TARGET_POWER2"
ca7f5001
RK		 2266 "")
2267
2268(define_insn ""
2269 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2270 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
8e871c05 2271 "TARGET_PPCFPX"
ca7f5001
RK		 2272 "fsqrts %0,%1"
2273 [(set_attr "type" "ssqrt")])
2274
2275(define_insn ""
2276 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2277 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2278 "TARGET_POWER2"
2279 "fsqrt %0,%1"
2280 [(set_attr "type" "dsqrt")])
2281
8e871c05
RK		 2282;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel
2283;; instruction and some auxiliary computations. Then we just have a single
2284;; DEFINE_INSN for fsel and the define_splits to make them if made by
2285;; combine.
2286(define_expand "maxsf3"
2287 [(set (match_dup 3)
2288 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2289 (match_operand:SF 2 "gpc_reg_operand" "")))
2290 (set (match_operand:SF 0 "gpc_reg_operand" "")
2291 (if_then_else:SF (ge (match_dup 3)
2292 (const_int 0))
2293 (match_dup 1)
2294 (match_dup 2)))]
2295 "TARGET_PPCFPX"
2296 "
2297{ operands[3] = gen_reg_rtx (SFmode); }")
2f607b94 2298
8e871c05
RK		 2299(define_split
2300 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2301 (smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
2302 (match_operand:SF 2 "reg_or_short_operand" "")))
2303 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
2304 "TARGET_PPCFPX"
2305 [(set (match_dup 3)
2306 (minus:SF (match_dup 1) (match_dup 2)))
2307 (set (match_operand:SF 0 "gpc_reg_operand" "")
2308 (if_then_else:SF (ge (match_dup 3)
2309 (const_int 0))
2310 (match_dup 1)
2311 (match_dup 2)))]
2312 "")
2f607b94 2313
8e871c05
RK		 2314(define_expand "minsf3"
2315 [(set (match_dup 3)
2316 (minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
2317 (match_operand:SF 1 "gpc_reg_operand" "")))
2318 (set (match_operand:SF 0 "gpc_reg_operand" "")
2319 (if_then_else:SF (ge (match_dup 3)
2320 (const_int 0))
2321 (match_dup 1)
2322 (match_dup 2)))]
2323 "TARGET_PPCFPX"
2324 "
2325{ operands[3] = gen_reg_rtx (SFmode); }")
2f607b94 2326
8e871c05
RK		 2327(define_split
2328 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2329 (smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
2330 (match_operand:SF 2 "reg_or_short_operand" "")))
2331 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
2332 "TARGET_PPCFPX"
2333 [(set (match_dup 3)
2334 (minus:SF (match_dup 2) (match_dup 1)))
2335 (set (match_operand:SF 0 "gpc_reg_operand" "")
2336 (if_then_else:SF (ge (match_dup 3)
2337 (const_int 0))
2338 (match_dup 1)
2339 (match_dup 2)))]
2340 "")
2f607b94 2341
8e871c05
RK		 2342(define_insn ""
2343 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2344 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
2345 (const_int 0))
2346 (match_operand:SF 2 "gpc_reg_operand" "f")
2347 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2348 "TARGET_PPCFPX"
2349 "fsel %0,%1,%2,%3"
2350 [(set_attr "type" "fp")])
2f607b94 2351
1fd4e8c1 2352(define_insn "negdf2"
cd2b37d9
RK		 2353 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2354 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1fd4e8c1
RK		 2355 ""
2356 "fneg %0,%1"
2357 [(set_attr "type" "fp")])
2358
2359(define_insn "absdf2"
cd2b37d9
RK		 2360 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2361 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
1fd4e8c1
RK		 2362 ""
2363 "fabs %0,%1"
2364 [(set_attr "type" "fp")])
2365
2366(define_insn ""
cd2b37d9
RK		 2367 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2368 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
1fd4e8c1
RK		 2369 ""
2370 "fnabs %0,%1"
2371 [(set_attr "type" "fp")])
2372
2373(define_insn "adddf3"
cd2b37d9
RK		 2374 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2375 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
2376 (match_operand:DF 2 "gpc_reg_operand" "f")))]
1fd4e8c1 2377 ""
ca7f5001 2378 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 2379 [(set_attr "type" "fp")])
2380
2381(define_insn "subdf3"
cd2b37d9
RK		 2382 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2383 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
2384 (match_operand:DF 2 "gpc_reg_operand" "f")))]
1fd4e8c1 2385 ""
ca7f5001 2386 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 2387 [(set_attr "type" "fp")])
2388
2389(define_insn "muldf3"
cd2b37d9
RK		 2390 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2391 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
2392 (match_operand:DF 2 "gpc_reg_operand" "f")))]
1fd4e8c1 2393 ""
ca7f5001 2394 "{fm|fmul} %0,%1,%2"
cfb557c4 2395 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 2396
2397(define_insn "divdf3"
cd2b37d9
RK		 2398 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2399 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
2400 (match_operand:DF 2 "gpc_reg_operand" "f")))]
1fd4e8c1 2401 ""
ca7f5001 2402 "{fd|fdiv} %0,%1,%2"
cfb557c4 2403 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 2404
2405(define_insn ""
cd2b37d9
RK		 2406 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2407 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
2408 (match_operand:DF 2 "gpc_reg_operand" "f"))
2409 (match_operand:DF 3 "gpc_reg_operand" "f")))]
1fd4e8c1 2410 ""
ca7f5001 2411 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 2412 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 2413
2414(define_insn ""
cd2b37d9
RK		 2415 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2416 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
2417 (match_operand:DF 2 "gpc_reg_operand" "f"))
2418 (match_operand:DF 3 "gpc_reg_operand" "f")))]
1fd4e8c1 2419 ""
ca7f5001 2420 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 2421 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 2422
2423(define_insn ""
cd2b37d9
RK		 2424 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2425 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
2426 (match_operand:DF 2 "gpc_reg_operand" "f"))
2427 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
1fd4e8c1 2428 ""
ca7f5001 2429 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 2430 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 2431
2432(define_insn ""
cd2b37d9
RK		 2433 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2434 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
2435 (match_operand:DF 2 "gpc_reg_operand" "f"))
2436 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
1fd4e8c1 2437 ""
ca7f5001 2438 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 2439 [(set_attr "type" "dmul")])
ca7f5001
RK		 2440
2441(define_insn "sqrtdf2"
2442 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2443 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
8e871c05 2444 "TARGET_PPCFPX || TARGET_POWER2"
ca7f5001
RK		 2445 "fsqrt %0,%1"
2446 [(set_attr "type" "dsqrt")])
b77dfefc 2447
8e871c05
RK		 2448;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel
2449;; instruction and some auxiliary computations. Then we just have a single
2450;; DEFINE_INSN for fsel and the define_splits to make them if made by
2451;; combine.
b77dfefc 2452
8e871c05
RK		 2453(define_expand "maxdf3"
2454 [(set (match_dup 3)
2455 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
2456 (match_operand:DF 2 "gpc_reg_operand" "")))
2457 (set (match_operand:DF 0 "gpc_reg_operand" "")
2458 (if_then_else:DF (ge (match_dup 3)
2459 (const_int 0))
2460 (match_dup 1)
2461 (match_dup 2)))]
2462 "TARGET_PPCFPX"
2463 "
2464{ operands[3] = gen_reg_rtx (DFmode); }")
b77dfefc 2465
8e871c05
RK		 2466(define_split
2467 [(set (match_operand:DF 0 "gpc_reg_operand" "")
2468 (smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
2469 (match_operand:DF 2 "reg_or_short_operand" "")))
2470 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
2471 "TARGET_PPCFPX"
2472 [(set (match_dup 3)
2473 (minus:DF (match_dup 1) (match_dup 2)))
2474 (set (match_operand:DF 0 "gpc_reg_operand" "")
2475 (if_then_else:DF (ge (match_dup 3)
2476 (const_int 0))
2477 (match_dup 1)
2478 (match_dup 2)))]
2479 "")
b77dfefc 2480
8e871c05
RK		 2481(define_expand "mindf3"
2482 [(set (match_dup 3)
2483 (minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
2484 (match_operand:DF 1 "gpc_reg_operand" "")))
2485 (set (match_operand:DF 0 "gpc_reg_operand" "")
2486 (if_then_else:DF (ge (match_dup 3)
2487 (const_int 0))
2488 (match_dup 1)
2489 (match_dup 2)))]
2490 "TARGET_PPCFPX"
2491 "
2492{ operands[3] = gen_reg_rtx (DFmode); }")
b77dfefc 2493
8e871c05
RK		 2494(define_split
2495 [(set (match_operand:DF 0 "gpc_reg_operand" "")
2496 (smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
2497 (match_operand:DF 2 "reg_or_short_operand" "")))
2498 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
2499 "TARGET_PPCFPX"
2500 [(set (match_dup 3)
2501 (minus:DF (match_dup 2) (match_dup 1)))
2502 (set (match_operand:DF 0 "gpc_reg_operand" "")
2503 (if_then_else:DF (ge (match_dup 3)
2504 (const_int 0))
2505 (match_dup 1)
2506 (match_dup 2)))]
2507 "")
b77dfefc 2508
8e871c05
RK		 2509(define_insn ""
2510 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2511 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
2512 (const_int 0))
2513 (match_operand:DF 2 "gpc_reg_operand" "f")
2514 (match_operand:DF 3 "gpc_reg_operand" "f")))]
2515 "TARGET_PPCFPX"
2516 "fsel %0,%1,%2,%3"
2517 [(set_attr "type" "fp")])
1fd4e8c1
RK		 2518\f
2519;; Conversions to and from floating-point.
2520(define_expand "floatsidf2"
2521 [(set (match_dup 2)
2522 (plus:DI (zero_extend:DI
cd2b37d9 2523 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 2524 (match_dup 3)))
2525 (match_dup 4)))
cd2b37d9 2526 (set (match_operand:DF 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 2527 (minus:DF (subreg:DF (match_dup 2) 0)
2528 (match_dup 5)))]
2529 ""
2530 "
2531{
2532#if HOST_BITS_PER_INT != BITS_PER_WORD
2533 /* Maybe someone can figure out how to do this in that case. I don't
2534 want to right now. */
2535 abort ();
2536#endif
2537
2538 operands[2] = gen_reg_rtx (DImode);
2539 operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
2540 operands[4] = immed_double_const (0, 0x43300000, DImode);
2541 operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
2542 0x80000000, DFmode));
2543}")
2544
2545(define_expand "floatunssidf2"
2546 [(set (match_dup 2)
cd2b37d9 2547 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1fd4e8c1 2548 (match_dup 3)))
cd2b37d9 2549 (set (match_operand:DF 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 2550 (minus:DF (subreg:DF (match_dup 2) 0)
2551 (match_dup 4)))]
2552 ""
2553 "
2554{
2555#if HOST_BITS_PER_INT != BITS_PER_WORD
2556 /* Maybe someone can figure out how to do this in that case. I don't
2557 want to right now. */
2558 abort ();
2559#endif
2560
2561 operands[2] = gen_reg_rtx (DImode);
2562 operands[3] = immed_double_const (0, 0x43300000, DImode);
2563 operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
2564}")
2565
2566;; For the above two cases, we always split.
2567(define_split
cd2b37d9 2568 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1fd4e8c1 2569 (plus:DI (zero_extend:DI
cd2b37d9 2570 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 2571 (match_operand:SI 2 "logical_operand" "")))
2572 (match_operand:DI 3 "immediate_operand" "")))]
2573 "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
2574 && GET_CODE (operands[3]) == CONST_DOUBLE
2575 && CONST_DOUBLE_LOW (operands[3]) == 0"
2576 [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
2577 (set (match_dup 4) (match_dup 5))]
2578 "
2579{ operands[4] = operand_subword (operands[0], 0, 0, DImode);
2580 operands[5] = operand_subword (operands[3], 0, 0, DImode);
2581 operands[6] = operand_subword (operands[0], 1, 0, DImode);
2582}")
2583
2584(define_insn ""
cd2b37d9 2585 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2586 (plus:DI (zero_extend:DI
cd2b37d9 2587 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1fd4e8c1
RK		 2588 (match_operand:SI 2 "logical_operand" "rKJ")))
2589 (match_operand:DI 3 "immediate_operand" "n")))]
2590 "HOST_BITS_PER_INT == BITS_PER_WORD
2591 && GET_CODE (operands[3]) == CONST_DOUBLE
2592 && CONST_DOUBLE_LOW (operands[3]) == 0"
baf97f86
RK		 2593 "#"
2594 [(set_attr "length" "8")])
1fd4e8c1
RK		 2595
2596(define_split
cd2b37d9
RK		 2597 [(set (match_operand:DI 0 "gpc_reg_operand" "=")
2598 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1fd4e8c1
RK		 2599 (match_operand:DI 2 "immediate_operand" "")))]
2600 "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
2601 && GET_CODE (operands[2]) == CONST_DOUBLE
2602 && CONST_DOUBLE_LOW (operands[2]) == 0"
2603 [(set (match_dup 3) (match_dup 4))
2604 (set (match_dup 5) (match_dup 1))]
2605 "
2606{ operands[3] = operand_subword (operands[0], 0, 0, DImode);
2607 operands[4] = operand_subword (operands[2], 0, 0, DImode);
2608 operands[5] = operand_subword (operands[0], 1, 0, DImode);
2609
2610 if (rtx_equal_p (operands[1], operands[5]))
2611 {
2612 emit_move_insn (operands[3], operands[4]);
2613 DONE;
2614 }
c283c989
RK		 2615
2616 if (rtx_equal_p (operands[1], operands[3]))
2617 {
2618 rtx temp;
2619
2620 temp = operands[3]; operands[3] = operands[5]; operands[5] = temp;
2621 temp = operands[4]; operands[4] = operands[1]; operands[1] = temp;
2622 }
1fd4e8c1
RK		 2623}")
2624
2625(define_insn ""
cd2b37d9
RK		 2626 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2627 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 2628 (match_operand:DI 2 "immediate_operand" "n")))]
2629 "HOST_BITS_PER_INT == BITS_PER_WORD
2630 && GET_CODE (operands[2]) == CONST_DOUBLE
2631 && CONST_DOUBLE_LOW (operands[2]) == 0"
baf97f86
RK		 2632 "#"
2633 [(set_attr "length" "8")])
1fd4e8c1
RK		 2634
2635(define_expand "fix_truncdfsi2"
cd2b37d9 2636 [(set (match_operand:SI 0 "gpc_reg_operand" "")
b542afe9 2637 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 2638 ""
2639 "
2640{
2641 emit_insn (gen_trunc_call (operands[0], operands[1],
3c64f04b 2642 gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
1fd4e8c1
RK		 2643 DONE;
2644}")
2645
2646(define_expand "fixuns_truncdfsi2"
cd2b37d9 2647 [(set (match_operand:SI 0 "gpc_reg_operand" "")
b542afe9 2648 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 2649 ""
2650 "
2651{
2652 emit_insn (gen_trunc_call (operands[0], operands[1],
3c64f04b 2653 gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC)));
1fd4e8c1
RK		 2654 DONE;
2655}")
2656
2657
2658(define_expand "trunc_call"
2659 [(parallel [(set (match_operand:SI 0 "" "")
b542afe9 2660 (fix:SI (match_operand:DF 1 "" "")))
1fd4e8c1
RK		 2661 (use (match_operand:SI 2 "" ""))])]
2662 ""
2663 "
2664{
2665 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
2666 rtx first = XVECEXP (insns, 0, 0);
2667 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
2668
2669 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
2670 REG_NOTES (first));
2671 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
2672
2673 emit_insn (insns);
2674 DONE;
2675}")
2676
2677(define_expand "trunc_call_rtl"
cd2b37d9 2678 [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
1fd4e8c1
RK		 2679 (use (reg:DF 33))
2680 (parallel [(set (reg:SI 3)
2681 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
2682 (clobber (scratch:SI))])
cd2b37d9 2683 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 2684 (reg:SI 3))]
2685 ""
2686 "
2687{
2688 rs6000_trunc_used = 1;
2689}")
2690\f
2691;; Define the DImode operations that can be done in a small number
2692;; of instructions.
ca7f5001
RK		 2693(define_expand "adddi3"
2694 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2695 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
2696 (match_operand:DI 2 "reg_or_short_operand" "")))]
2697 ""
2698 "
2699{
25c341fa 2700 if (! TARGET_POWER
ca7f5001
RK		 2701 && short_cint_operand (operands[2], DImode))
2702 FAIL;
2703}")
2704
2705(define_insn ""
fa5679bb
RK		 2706 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
2707 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
2708 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
ca7f5001 2709 "TARGET_POWER"
fa5679bb 2710 "@
ca7f5001
RK		 2711 {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2
2712 {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1"
b19003d8 2713 [(set_attr "length" "8")])
1fd4e8c1 2714
ca7f5001
RK		 2715(define_insn ""
2716 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2717 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
2718 (match_operand:DI 2 "gpc_reg_operand" "r")))]
25c341fa 2719 "! TARGET_POWER"
ca7f5001
RK		 2720 "addc %L0,%L1,%L2\;adde %0,%1,%2"
2721 [(set_attr "length" "8")])
2722
2723(define_expand "subdi3"
fa5679bb
RK		 2724 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
2725 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
2726 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
1fd4e8c1 2727 ""
ca7f5001
RK		 2728 "
2729{
25c341fa 2730 if (! TARGET_POWER
ca7f5001
RK		 2731 && short_cint_operand (operands[1], DImode))
2732 FAIL;
2733}")
2734
2735(define_insn ""
2736 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
2737 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
2738 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
2739 "TARGET_POWER"
fa5679bb 2740 "@
ca7f5001
RK		 2741 {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
2742 {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2"
b19003d8 2743 [(set_attr "length" "8")])
1fd4e8c1 2744
ca7f5001
RK		 2745(define_insn ""
2746 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2747 (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2748 (match_operand:DI 2 "gpc_reg_operand" "r")))]
25c341fa 2749 "! TARGET_POWER"
ca7f5001
RK		 2750 "subfc %L0,%L2,%L1\;subfe %0,%2,%1"
2751 [(set_attr "length" "8")])
2752
2753(define_expand "negdi2"
cd2b37d9
RK		 2754 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2755 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
1fd4e8c1 2756 ""
ca7f5001
RK		 2757 "")
2758
2759(define_insn ""
2760 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2761 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
25c341fa 2762 ""
ca7f5001
RK		 2763 "{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1"
2764 [(set_attr "length" "8")])
2765
1fd4e8c1 2766(define_insn "mulsidi3"
cd2b37d9
RK		 2767 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2768 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2769 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 2770 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 2771 "TARGET_POWER"
b19003d8
RK		 2772 "mul %0,%1,%2\;mfmq %L0"
2773 [(set_attr "length" "8")])
1fd4e8c1
RK		 2774
2775;; If operands 0 and 2 are in the same register, we have a problem. But
2776;; operands 0 and 1 (the usual case) can be in the same register. That's
2777;; why we have the strange constraints below.
2778(define_insn "ashldi3"
cd2b37d9
RK		 2779 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
2780 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
1fd4e8c1
RK		 2781 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
2782 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
ca7f5001 2783 "TARGET_POWER"
1fd4e8c1 2784 "@
ca7f5001 2785 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
1fd4e8c1
RK		 2786 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
2787 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
b19003d8
RK		 2788 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
2789 [(set_attr "length" "8")])
1fd4e8c1
RK		 2790
2791(define_insn "lshrdi3"
cd2b37d9
RK		 2792 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
2793 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
1fd4e8c1
RK		 2794 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
2795 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
ca7f5001 2796 "TARGET_POWER"
1fd4e8c1 2797 "@
ca7f5001 2798 {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2
46a48c7f
RK		 2799 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
2800 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
b19003d8
RK		 2801 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
2802 [(set_attr "length" "8")])
1fd4e8c1
RK		 2803
2804;; Shift by a variable amount is too complex to be worth open-coding. We
2805;; just handle shifts by constants.
2806
2807(define_expand "ashrdi3"
cd2b37d9
RK		 2808 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=")
2809 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 2810 (match_operand:SI 2 "general_operand" "")))
2811 (clobber (match_scratch:SI 3 ""))])]
ca7f5001 2812 "TARGET_POWER"
1fd4e8c1
RK		 2813 "
2814{ if (GET_CODE (operands[2]) != CONST_INT)
2815 FAIL;
2816}")
2817
2818(define_insn ""
cd2b37d9
RK		 2819 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
2820 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 2821 (match_operand:SI 2 "const_int_operand" "M,i")))
2822 (clobber (match_scratch:SI 3 "=X,q"))]
ca7f5001 2823 "TARGET_POWER"
1fd4e8c1 2824 "@
ca7f5001 2825 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
b19003d8
RK		 2826 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
2827 [(set_attr "length" "8")])
1fd4e8c1
RK		 2828\f
2829;; Now define ways of moving data around.
2830;;
2831;; For SI, we special-case integers that can't be loaded in one insn. We
2832;; do the load 16-bits at a time. We could do this by loading from memory,
2833;; and this is even supposed to be faster, but it is simpler not to get
2834;; integers in the TOC.
2835(define_expand "movsi"
2836 [(set (match_operand:SI 0 "general_operand" "")
2837 (match_operand:SI 1 "any_operand" ""))]
2838 ""
2839 "
2840{
2841 if (GET_CODE (operands[0]) != REG)
2842 operands[1] = force_reg (SImode, operands[1]);
2843
78b8d850
RK		 2844 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT
2845 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
b45863ec 2846 {
30a4619d
RK		 2847 /* If we are to limit the number of things we put in the TOC and
2848 this is a symbol plus a constant we can add in one insn,
2849 just put the sumbol in the TOC and add the constant. Don't do
2850 this if reload is in progress. */
2851 if (GET_CODE (operands[1]) == CONST
2852 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
2853 && GET_CODE (XEXP (operands[1], 0)) == PLUS
2854 && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
2855 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
2856 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
2857 && ! side_effects_p (operands[0]))
2858 {
2859 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
2860 rtx other = XEXP (XEXP (operands[1], 0), 1);
2861
2862 emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
2863 DONE;
2864 }
2865
b45863ec
RK		 2866 operands[1] = force_const_mem (SImode, operands[1]);
2867 if (! memory_address_p (SImode, XEXP (operands[1], 0))
2868 && ! reload_in_progress)
2869 operands[1] = change_address (operands[1], SImode,
2870 XEXP (operands[1], 0));
2871 }
1fd4e8c1
RK		 2872
2873 if (GET_CODE (operands[1]) == CONST_INT
2874 && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
2875 && (INTVAL (operands[1]) & 0xffff) != 0)
2876 {
2877 emit_move_insn (operands[0],
2878 gen_rtx (CONST_INT, VOIDmode,
2879 INTVAL (operands[1]) & 0xffff0000));
2880 emit_insn (gen_iorsi3 (operands[0], operands[0],
2881 gen_rtx (CONST_INT, VOIDmode,
2882 INTVAL (operands[1]) & 0xffff)));
2883 DONE;
2884 }
2885}")
2886
2887(define_insn ""
324e52cc 2888 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*q,*c*l,*h")
e76e75bb 2889 (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r,0"))]
ca7f5001
RK		 2890 "TARGET_POWER && (gpc_reg_operand (operands[0], SImode)
2891 || gpc_reg_operand (operands[1], SImode))"
1fd4e8c1 2892 "@
ca7f5001
RK		 2893 {ai|addic} %0,%1,0
2894 {l%U1%X1|lwz%U1%X1} %0,%1
2895 {st%U0%X0|stw%U0%X0} %1,%0
2896 {cal %0,%1(0)|li %0,%1}
2897 {cau %0,0,%u1|lis %0,%u1}
1fd4e8c1 2898 mf%1 %0
5c23c401 2899 mt%0 %1
e76e75bb
RK		 2900 mt%0 %1
2901 cror 0,0,0"
324e52cc 2902 [(set_attr "type" "*,load,*,*,*,*,*,mtjmpr,*")])
1fd4e8c1 2903
ca7f5001
RK		 2904(define_insn ""
2905 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*h")
2906 (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r"))]
25c341fa 2907 "! TARGET_POWER && (gpc_reg_operand (operands[0], SImode)
ca7f5001
RK		 2908 || gpc_reg_operand (operands[1], SImode))"
2909 "@
2910 mr %0,%1
2911 lwz%U1%X1 %0,%1
2912 stw%U0%X0 %1,%0
2913 li %0,%1
2914 lis %0,%u1
2915 mf%1 %0
2916 mt%0 %1"
2917 [(set_attr "type" "*,load,*,*,*,*,*")])
2918
77fa0940
RK		 2919;; Split a load of a large constant into the appropriate two-insn
2920;; sequence.
2921
2922(define_split
2923 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2924 (match_operand:SI 1 "const_int_operand" ""))]
2925 "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
2926 && (INTVAL (operands[1]) & 0xffff) != 0"
2927 [(set (match_dup 0)
2928 (match_dup 2))
2929 (set (match_dup 0)
2930 (ior:SI (match_dup 0)
2931 (match_dup 3)))]
2932 "
2933{
2934 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2935 INTVAL (operands[1]) & 0xffff0000);
2936 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
2937}")
2938
1fd4e8c1
RK		 2939(define_insn ""
2940 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
cd2b37d9 2941 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 2942 (const_int 0)))
cd2b37d9 2943 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
1fd4e8c1 2944 ""
ca7f5001 2945 "{ai.|addic.} %0,%1,0"
1fd4e8c1
RK		 2946 [(set_attr "type" "compare")])
2947\f
2948(define_expand "movhi"
2949 [(set (match_operand:HI 0 "general_operand" "")
2950 (match_operand:HI 1 "any_operand" ""))]
2951 ""
2952 "
2953{
2954 if (GET_CODE (operands[0]) != REG)
2955 operands[1] = force_reg (HImode, operands[1]);
2956
2957 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
b45863ec
RK		 2958 {
2959 operands[1] = force_const_mem (HImode, operands[1]);
2960 if (! memory_address_p (HImode, XEXP (operands[1], 0))
2961 && ! reload_in_progress)
2962 operands[1] = change_address (operands[1], HImode,
2963 XEXP (operands[1], 0));
2964 }
1fd4e8c1
RK		 2965}")
2966
2967(define_insn ""
e76e75bb
RK		 2968 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
2969 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
ca7f5001
RK		 2970 "TARGET_POWER && (gpc_reg_operand (operands[0], HImode)
2971 || gpc_reg_operand (operands[1], HImode))"
1fd4e8c1 2972 "@
ca7f5001 2973 {oril|ori} %0,%1,0
1fd4e8c1
RK		 2974 lhz%U1%X1 %0,%1
2975 sth%U0%X0 %1,%0
ca7f5001 2976 {cal %0,%w1(0)|li %0,%w1}
1fd4e8c1 2977 mf%1 %0
e76e75bb
RK		 2978 mt%0 %1
2979 cror 0,0,0"
2980 [(set_attr "type" "*,load,*,*,*,*,*")])
1fd4e8c1 2981
ca7f5001
RK		 2982(define_insn ""
2983 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2984 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
25c341fa 2985 "! TARGET_POWER && (gpc_reg_operand (operands[0], HImode)
ca7f5001
RK		 2986 || gpc_reg_operand (operands[1], HImode))"
2987 "@
2988 ori %0,%1,0
2989 lhz%U1%X1 %0,%1
2990 sth%U0%X0 %1,%0
2991 li %0,%w1
2992 mf%1 %0
2993 mt%0 %1"
2994 [(set_attr "type" "*,load,*,*,*,*")])
2995
1fd4e8c1
RK		 2996(define_expand "movqi"
2997 [(set (match_operand:QI 0 "general_operand" "")
2998 (match_operand:QI 1 "any_operand" ""))]
2999 ""
3000 "
3001{
3002 if (GET_CODE (operands[0]) != REG)
3003 operands[1] = force_reg (QImode, operands[1]);
3004
3005 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
b45863ec
RK		 3006 {
3007 operands[1] = force_const_mem (QImode, operands[1]);
3008 if (! memory_address_p (QImode, XEXP (operands[1], 0))
3009 && ! reload_in_progress)
3010 operands[1] = change_address (operands[1], QImode,
3011 XEXP (operands[1], 0));
3012 }
1fd4e8c1
RK		 3013}")
3014
3015(define_insn ""
e76e75bb
RK		 3016 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
3017 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
ca7f5001
RK		 3018 "TARGET_POWER && (gpc_reg_operand (operands[0], QImode)
3019 || gpc_reg_operand (operands[1], QImode))"
1fd4e8c1 3020 "@
ca7f5001 3021 {oril|ori} %0,%1,0
1fd4e8c1
RK		 3022 lbz%U1%X1 %0,%1
3023 stb%U0%X0 %1,%0
ca7f5001 3024 {cal %0,%1(0)|li %0,%1}
1fd4e8c1 3025 mf%1 %0
e76e75bb
RK		 3026 mt%0 %1
3027 cror 0,0,0"
3028 [(set_attr "type" "*,load,*,*,*,*,*")])
ca7f5001
RK		 3029
3030(define_insn ""
3031 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
3032 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
25c341fa 3033 "! TARGET_POWER && (gpc_reg_operand (operands[0], QImode)
ca7f5001
RK		 3034 || gpc_reg_operand (operands[1], QImode))"
3035 "@
3036 mr %0,%1
3037 lbz%U1%X1 %0,%1
3038 stb%U0%X0 %1,%0
3039 li %0,%1
3040 mf%1 %0
3041 mt%0 %1"
3042 [(set_attr "type" "*,load,*,*,*,*")])
1fd4e8c1
RK		 3043\f
3044;; Here is how to move condition codes around. When we store CC data in
3045;; an integer register or memory, we store just the high-order 4 bits.
3046;; This lets us not shift in the most common case of CR0.
3047(define_expand "movcc"
3048 [(set (match_operand:CC 0 "nonimmediate_operand" "")
3049 (match_operand:CC 1 "nonimmediate_operand" ""))]
3050 ""
3051 "")
3052
3053(define_insn ""
3054 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
3055 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
3056 "register_operand (operands[0], CCmode)
3057 || register_operand (operands[1], CCmode)"
3058 "@
3059 mcrf %0,%1
3060 mtcrf 128,%1
ca7f5001 3061 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
1fd4e8c1 3062 mfcr %0
ca7f5001
RK		 3063 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
3064 {ai %0,%1,0|mr %0,%1}
3065 {l%U1%X1|lwz%U1%X1} %0,%1
3066 {st%U0%U1|stw%U0%U1} %1,%0"
b19003d8
RK		 3067 [(set_attr "type" "*,*,*,compare,*,*,load,*")
3068 (set_attr "length" "*,*,12,*,8,*,*,*")])
1fd4e8c1
RK		 3069\f
3070;; For floating-point, we normally deal with the floating-point registers.
3071;; The sole exception is that parameter passing can produce floating-point
3072;; values in fixed-point registers. Unless the value is a simple constant
3073;; or already in memory, we deal with this by allocating memory and copying
3074;; the value explicitly via that memory location.
3075(define_expand "movsf"
3076 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3077 (match_operand:SF 1 "any_operand" ""))]
3078 ""
3079 "
3080{
3081 /* If we are called from reload, we might be getting a SUBREG of a hard
3082 reg. So expand it. */
3083 if (GET_CODE (operands[0]) == SUBREG
3084 && GET_CODE (SUBREG_REG (operands[0])) == REG
3085 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
3086 operands[0] = alter_subreg (operands[0]);
3087 if (GET_CODE (operands[1]) == SUBREG
3088 && GET_CODE (SUBREG_REG (operands[1])) == REG
3089 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
3090 operands[1] = alter_subreg (operands[1]);
3091
785e6a26 3092 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
1fd4e8c1
RK		 3093 {
3094 rtx stack_slot;
3095
785e6a26
RK		 3096 /* If this is a store to memory or another integer register do the
3097 move directly. Otherwise store to a temporary stack slot and
3098 load from there into a floating point register. */
3099
1fd4e8c1
RK		 3100 if (GET_CODE (operands[0]) == MEM
3101 || (GET_CODE (operands[0]) == REG
3102 && (REGNO (operands[0]) < 32
785e6a26
RK		 3103 || (reload_in_progress
3104 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
1fd4e8c1
RK		 3105 {
3106 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
3107 operand_subword (operands[1], 0, 0, SFmode));
3108 DONE;
3109 }
3110
3111 stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4));
3112 emit_move_insn (stack_slot, operands[1]);
3113 emit_move_insn (operands[0], stack_slot);
3114 DONE;
3115 }
3116
3117 if (GET_CODE (operands[0]) == MEM)
3118 operands[1] = force_reg (SFmode, operands[1]);
3119
3120 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
3121 {
3122 rtx stack_slot;
3123
3124 if (GET_CODE (operands[1]) == MEM
3125#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
3126 || GET_CODE (operands[1]) == CONST_DOUBLE
3127#endif
3128 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
3129 || (reload_in_progress && GET_CODE (operands[1]) == REG
3130 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
3131 {
3132 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
3133 operand_subword (operands[1], 0, 0, SFmode));
3134 DONE;
3135 }
3136
3137 if (reload_in_progress)
3138 stack_slot = gen_rtx (MEM, SFmode,
3139 plus_constant (stack_pointer_rtx, 4));
3140 else
3141 stack_slot = assign_stack_temp (SFmode, 4, 0);
3142 emit_move_insn (stack_slot, operands[1]);
3143 emit_move_insn (operands[0], stack_slot);
3144 DONE;
3145 }
3146
3147 if (CONSTANT_P (operands[1]))
3148 {
3149 operands[1] = force_const_mem (SFmode, operands[1]);
3150 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
3151 && ! reload_in_progress)
3152 operands[1] = change_address (operands[1], SFmode,
3153 XEXP (operands[1], 0));
3154 }
3155}")
3156
1fd4e8c1 3157(define_split
cd2b37d9 3158 [(set (match_operand:SF 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 3159 (match_operand:SF 1 "easy_fp_constant" ""))]
3160 "reload_completed && REGNO (operands[0]) <= 31"
3161 [(set (match_dup 2) (match_dup 3))]
3162 "
3163{ operands[2] = operand_subword (operands[0], 0, 0, SFmode);
3164 operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
3165
3166(define_insn ""
3167 [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
3168 (match_operand:SF 1 "input_operand" "f,m,f"))]
cd2b37d9
RK		 3169 "gpc_reg_operand (operands[0], SFmode)
3170 || gpc_reg_operand (operands[1], SFmode)"
1fd4e8c1
RK		 3171 "@
3172 fmr %0,%1
3173 lfs%U1%X1 %0,%1
3174 frsp %1,%1\;stfs%U0%X0 %1,%0"
cfb557c4 3175 [(set_attr "type" "fp,fpload,*")
b19003d8 3176 (set_attr "length" "*,*,8")])
1fd4e8c1
RK		 3177\f
3178(define_expand "movdf"
3179 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3180 (match_operand:DF 1 "any_operand" ""))]
3181 ""
3182 "
3183{
e7113111 3184 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1fd4e8c1 3185 {
e7113111
RK		 3186 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3187 operand_subword_force (operands[1], 1, DFmode));
3188 emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
3189 operand_subword_force (operands[1], 0, DFmode));
1fd4e8c1
RK		 3190 DONE;
3191 }
3192
e7113111
RK		 3193 if (GET_CODE (operands[0]) != REG)
3194 operands[1] = force_reg (DFmode, operands[1]);
1fd4e8c1 3195
e7113111 3196 if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
1fd4e8c1
RK		 3197 {
3198 operands[1] = force_const_mem (DFmode, operands[1]);
3199 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
3200 && ! reload_in_progress)
3201 operands[1] = change_address (operands[1], DFmode,
3202 XEXP (operands[1], 0));
3203 }
e7113111 3204}")
1fd4e8c1
RK		 3205
3206(define_split
cd2b37d9 3207 [(set (match_operand:DF 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 3208 (match_operand:DF 1 "easy_fp_constant" ""))]
3209 "reload_completed && REGNO (operands[0]) <= 31"
3210 [(set (match_dup 2) (match_dup 3))
3211 (set (match_dup 4) (match_dup 5))]
3212 "
3213{ operands[2] = operand_subword (operands[0], 0, 0, DFmode);
3214 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
3215 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
3216 operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
e7113111 3217
4eae5fe1
RK		 3218;; Don't have reload use general registers to load a constant. First,
3219;; it might not work if the output operand has is the equivalent of
3220;; a non-offsettable memref, but also it is less efficient than loading
3221;; the constant into an FP register, since it will probably be used there.
3222;; The "??" is a kludge until we can figure out a more reasonable way
3223;; of handling these non-offsettable values.
3224(define_insn ""
3225 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
e7113111
RK		 3226 (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
3227 "register_operand (operands[0], DFmode)
3228 || register_operand (operands[1], DFmode)"
3229 "*
3230{
3231 switch (which_alternative)
3232 {
3233 case 0:
3234 /* We normally copy the low-numbered register first. However, if
3235 the first register operand 0 is the same as the second register of
3236 operand 1, we must copy in the opposite order. */
3237 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
ca7f5001 3238 return \"{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\";
e7113111 3239 else
ca7f5001 3240 return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\";
e7113111
RK		 3241 case 1:
3242 /* If the low-address word is used in the address, we must load it
3243 last. Otherwise, load it first. Note that we cannot have
3244 auto-increment in that case since the address register is known to be
3245 dead. */
3246 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3247 operands [1], 0))
ca7f5001 3248 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
e7113111 3249 else
ca7f5001 3250 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
e7113111 3251 case 2:
ca7f5001 3252 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
e7113111
RK		 3253 case 3:
3254 return \"#\";
3255 case 4:
3256 return \"fmr %0,%1\";
3257 case 5:
3258 return \"lfd%U1%X1 %0,%1\";
3259 case 6:
3260 return \"stfd%U0%X0 %1,%0\";
3261 }
3262}"
ca7f5001 3263 [(set_attr "type" "*,load,*,*,fp,fpload,*")
e7113111 3264 (set_attr "length" "8,8,8,8,*,*,*")])
1fd4e8c1
RK		 3265\f
3266;; Next come the multi-word integer load and store and the load and store
3267;; multiple insns.
3268(define_expand "movdi"
3269 [(set (match_operand:DI 0 "general_operand" "")
3270 (match_operand:DI 1 "general_operand" ""))]
3271 ""
3272 "
3273{
062284d8
RK		 3274 if (GET_CODE (operands[1]) == CONST_DOUBLE
3275 || GET_CODE (operands[1]) == CONST_INT)
1fd4e8c1
RK		 3276 {
3277 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
3278 operand_subword (operands[1], 0, 0, DImode));
3279 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
3280 operand_subword (operands[1], 1, 0, DImode));
3281 DONE;
3282 }
062284d8
RK		 3283
3284 if (GET_CODE (operands[0]) == MEM)
3285 operands[1] = force_reg (DImode, operands[1]);
1fd4e8c1
RK		 3286}")
3287
3288(define_insn ""
3289 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
3290 (match_operand:DI 1 "input_operand" "r,m,r"))]
cd2b37d9
RK		 3291 "gpc_reg_operand (operands[0], DImode)
3292 || gpc_reg_operand (operands[1], DImode)"
1fd4e8c1
RK		 3293 "*
3294{
3295 switch (which_alternative)
3296 {
3297 case 0:
3298 /* We normally copy the low-numbered register first. However, if
3299 the first register operand 0 is the same as the second register of
3300 operand 1, we must copy in the opposite order. */
3301 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
ca7f5001 3302 return \"{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\";
1fd4e8c1 3303 else
ca7f5001 3304 return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\";
1fd4e8c1
RK		 3305 case 1:
3306 /* If the low-address word is used in the address, we must load it
3307 last. Otherwise, load it first. Note that we cannot have
3308 auto-increment in that case since the address register is known to be
3309 dead. */
3310 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3311 operands [1], 0))
ca7f5001 3312 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
1fd4e8c1 3313 else
ca7f5001 3314 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
1fd4e8c1 3315 case 2:
ca7f5001 3316 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
1fd4e8c1
RK		 3317 }
3318}"
b19003d8
RK		 3319 [(set_attr "type" "*,load,*")
3320 (set_attr "length" "8")])
1fd4e8c1
RK		 3321\f
3322;; TImode is similar, except that we usually want to compute the address into
3323;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 3324;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 3325(define_expand "movti"
3326 [(parallel [(set (match_operand:TI 0 "general_operand" "")
3327 (match_operand:TI 1 "general_operand" ""))
3328 (clobber (scratch:SI))])]
ca7f5001 3329 "TARGET_POWER"
1fd4e8c1
RK		 3330 "
3331{
3332 if (GET_CODE (operands[0]) == MEM)
3333 operands[1] = force_reg (TImode, operands[1]);
3334
3335 if (GET_CODE (operands[0]) == MEM
3336 && GET_CODE (XEXP (operands[0], 0)) != REG
3337 && ! reload_in_progress)
3338 operands[0] = change_address (operands[0], TImode,
3339 copy_addr_to_reg (XEXP (operands[0], 0)));
3340
3341 if (GET_CODE (operands[1]) == MEM
3342 && GET_CODE (XEXP (operands[1], 0)) != REG
3343 && ! reload_in_progress)
3344 operands[1] = change_address (operands[1], TImode,
3345 copy_addr_to_reg (XEXP (operands[1], 0)));
3346}")
3347
3348;; We say that MQ is clobbered in the last alternative because the first
3349;; alternative would never get used otherwise since it would need a reload
3350;; while the 2nd alternative would not. We put memory cases first so they
3351;; are preferred. Otherwise, we'd try to reload the output instead of
3352;; giving the SCRATCH mq.
3353(define_insn ""
3354 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
3355 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
3356 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
ca7f5001
RK		 3357 "TARGET_POWER && (gpc_reg_operand (operands[0], TImode)
3358 || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 3359 "*
3360{
3361 switch (which_alternative)
3362 {
3363 case 0:
ca7f5001 3364 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1
RK		 3365
3366 case 1:
ca7f5001 3367 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
1fd4e8c1
RK		 3368
3369 case 2:
3370 /* Normally copy registers with lowest numbered register copied first.
3371 But copy in the other order if the first register of the output
3372 is the second, third, or fourth register in the input. */
3373 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
3374 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
ca7f5001 3375 return \"{oril %Z0,%Z1,0|mr %Z0,%Z1}\;{oril %Y0,%Y1,0|mr %Y0,%Y1}\;{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\";
1fd4e8c1 3376 else
ca7f5001 3377 return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\;{oril %Y0,%Y1,0|mr %Y0,%Y1}\;{oril %Z0,%Z1,0|mr %Z0,%Z1}\";
1fd4e8c1
RK		 3378 case 3:
3379 /* If the address is not used in the output, we can use lsi. Otherwise,
3380 fall through to generating four loads. */
3381 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 3382 return \"{lsi|lswi} %0,%P1,16\";
1fd4e8c1
RK		 3383 /* ... fall through ... */
3384 case 4:
3385 /* If the address register is the same as the register for the lowest-
3386 addressed word, load it last. Similarly for the next two words.
3387 Otherwise load lowest address to highest. */
3388 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3389 operands[1], 0))
ca7f5001 3390 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
1fd4e8c1
RK		 3391 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
3392 REGNO (operands[0]) + 2, operands[1], 0))
ca7f5001 3393 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
1fd4e8c1
RK		 3394 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
3395 REGNO (operands[0]) + 3, operands[1], 0))
ca7f5001 3396 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
1fd4e8c1 3397 else
ca7f5001 3398 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
1fd4e8c1
RK		 3399 }
3400}"
b19003d8
RK		 3401 [(set_attr "type" "*,load,load,*,*")
3402 (set_attr "length" "*,16,16,*,16")])
1fd4e8c1
RK		 3403\f
3404(define_expand "load_multiple"
2f622005
RK		 3405 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
3406 (match_operand:SI 1 "" ""))
3407 (use (match_operand:SI 2 "" ""))])]
ca7f5001 3408 "TARGET_POWER"
1fd4e8c1
RK		 3409 "
3410{
3411 int regno;
3412 int count;
3413 rtx from;
3414 int i;
3415
3416 /* Support only loading a constant number of fixed-point registers from
3417 memory and only bother with this if more than two; the machine
3418 doesn't support more than eight. */
3419 if (GET_CODE (operands[2]) != CONST_INT
3420 || INTVAL (operands[2]) <= 2
3421 || INTVAL (operands[2]) > 8
3422 || GET_CODE (operands[1]) != MEM
3423 || GET_CODE (operands[0]) != REG
3424 || REGNO (operands[0]) >= 32)
3425 FAIL;
3426
3427 count = INTVAL (operands[2]);
3428 regno = REGNO (operands[0]);
3429
3430 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
3431 from = force_reg (SImode, XEXP (operands[1], 0));
3432
3433 for (i = 0; i < count; i++)
3434 XVECEXP (operands[3], 0, i)
3435 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
3436 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
3437}")
3438
3439(define_insn ""
3440 [(match_parallel 0 "load_multiple_operation"
cd2b37d9 3441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
1fd4e8c1 3442 (match_operand:SI 2 "indirect_operand" "Q"))])]
ca7f5001 3443 "TARGET_POWER"
1fd4e8c1
RK		 3444 "*
3445{
3446 /* We have to handle the case where the pseudo used to contain the address
3447 is assigned to one of the output registers. In that case, do the
3448 lsi, but then load the correct value. This is a bit of a mess, but is
b19003d8
RK		 3449 the best we can do.
3450 We set the length attribute to the maximum possible size (8 bytes). */
1fd4e8c1
RK		 3451 static char result[100];
3452 char newload[40];
3453 int i;
3454
ca7f5001 3455 strcpy (result, \"{lsi|lswi} %1,%P2,%N0\");
1fd4e8c1
RK		 3456 for (i = 0; i < XVECLEN (operands[0], 0); i++)
3457 if (refers_to_regno_p (REGNO (operands[1]) + i,
3458 REGNO (operands[1]) + i + 1, operands[2], 0))
3459 {
ca7f5001 3460 sprintf (newload, \"\;{l|lwz} %d,%d(%d)\",
1fd4e8c1
RK		 3461 REGNO (operands[1]) + i,
3462 i * 4, REGNO (XEXP (operands[2], 0)));
3463 strcat (result, newload);
3464 }
3465
3466 return result;
3467}"
b19003d8
RK		 3468 [(set_attr "type" "load")
3469 (set_attr "length" "8")])
1fd4e8c1 3470\f
b19003d8 3471
1fd4e8c1 3472(define_expand "store_multiple"
2f622005
RK		 3473 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
3474 (match_operand:SI 1 "" ""))
3475 (clobber (scratch:SI))
3476 (use (match_operand:SI 2 "" ""))])]
ca7f5001 3477 "TARGET_POWER"
1fd4e8c1
RK		 3478 "
3479{
3480 int regno;
3481 int count;
3482 rtx to;
3483 int i;
3484
3485 /* Support only storing a constant number of fixed-point registers to
3486 memory and only bother with this if more than two; the machine
3487 doesn't support more than eight. */
3488 if (GET_CODE (operands[2]) != CONST_INT
3489 || INTVAL (operands[2]) <= 2
3490 || INTVAL (operands[2]) > 8
3491 || GET_CODE (operands[0]) != MEM
3492 || GET_CODE (operands[1]) != REG
3493 || REGNO (operands[1]) >= 32)
3494 FAIL;
3495
3496 count = INTVAL (operands[2]);
3497 regno = REGNO (operands[1]);
3498
3499 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
3500 to = force_reg (SImode, XEXP (operands[0], 0));
3501
3502 XVECEXP (operands[3], 0, 0)
3503 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
3504 XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
3505 gen_rtx (SCRATCH, SImode));
3506
3507 for (i = 1; i < count; i++)
3508 XVECEXP (operands[3], 0, i + 1)
3509 = gen_rtx (SET, VOIDmode,
3510 gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
3511 gen_rtx (REG, SImode, regno + i));
3512}")
3513
3514(define_insn ""
3515 [(match_parallel 0 "store_multiple_operation"
3516 [(set (match_operand:SI 1 "indirect_operand" "=Q")
cd2b37d9 3517 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 3518 (clobber (match_scratch:SI 3 "=q"))])]
ca7f5001
RK		 3519 "TARGET_POWER"
3520 "{stsi|stswi} %2,%P1,%O0")
1fd4e8c1
RK		 3521\f
3522;; Define insns that do load or store with update. Some of these we can
3523;; get by using pre-decrement or pre-increment, but the hardware can also
3524;; do cases where the increment is not the size of the object.
3525;;
3526;; In all these cases, we use operands 0 and 1 for the register being
3527;; incremented because those are the operands that local-alloc will
3528;; tie and these are the pair most likely to be tieable (and the ones
3529;; that will benefit the most).
3530
3531(define_insn ""
cd2b37d9
RK		 3532 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
3533 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3534 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 3535 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3536 (plus:SI (match_dup 1) (match_dup 2)))]
3537 ""
3538 "@
ca7f5001
RK		 3539 {lux|lwzux} %3,%0,%2
3540 {lu|lwzu} %3,%2(%0)"
cfb557c4 3541 [(set_attr "type" "load")])
1fd4e8c1
RK		 3542
3543(define_insn ""
cd2b37d9 3544 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3545 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 3546 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3547 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3548 (plus:SI (match_dup 1) (match_dup 2)))]
3549 ""
3550 "@
ca7f5001
RK		 3551 {stux|stwux} %3,%0,%2
3552 {stu|stwu} %3,%2(%0)")
1fd4e8c1
RK		 3553
3554(define_insn ""
cd2b37d9
RK		 3555 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
3556 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3557 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 3558 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3559 (plus:SI (match_dup 1) (match_dup 2)))]
3560 ""
3561 "@
5f243543
RK		 3562 lhzux %3,%0,%2
3563 lhzu %3,%2(%0)"
cfb557c4 3564 [(set_attr "type" "load")])
1fd4e8c1
RK		 3565
3566(define_insn ""
cd2b37d9 3567 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 3568 (zero_extend:SI
cd2b37d9 3569 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3570 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 3571 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3572 (plus:SI (match_dup 1) (match_dup 2)))]
3573 ""
3574 "@
5f243543
RK		 3575 lhzux %3,%0,%2
3576 lhzu %3,%2(%0)"
cfb557c4 3577 [(set_attr "type" "load")])
1fd4e8c1
RK		 3578
3579(define_insn ""
cd2b37d9 3580 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 3581 (sign_extend:SI
cd2b37d9 3582 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3583 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 3584 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3585 (plus:SI (match_dup 1) (match_dup 2)))]
3586 ""
3587 "@
5f243543
RK		 3588 lhaux %3,%0,%2
3589 lhau %3,%2(%0)"
cfb557c4 3590 [(set_attr "type" "load")])
1fd4e8c1
RK		 3591
3592(define_insn ""
cd2b37d9 3593 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3594 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 3595 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
3596 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3597 (plus:SI (match_dup 1) (match_dup 2)))]
3598 ""
3599 "@
5f243543 3600 sthux %3,%0,%2
cfb557c4 3601 sthu %3,%2(%0)")
1fd4e8c1
RK		 3602
3603(define_insn ""
cd2b37d9
RK		 3604 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
3605 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3606 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 3607 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3608 (plus:SI (match_dup 1) (match_dup 2)))]
3609 ""
3610 "@
5f243543
RK		 3611 lbzux %3,%0,%2
3612 lbzu %3,%2(%0)"
cfb557c4 3613 [(set_attr "type" "load")])
1fd4e8c1
RK		 3614
3615(define_insn ""
cd2b37d9 3616 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 3617 (zero_extend:SI
cd2b37d9 3618 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3619 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 3620 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3621 (plus:SI (match_dup 1) (match_dup 2)))]
3622 ""
3623 "@
5f243543
RK		 3624 lbzux %3,%0,%2
3625 lbzu %3,%2(%0)"
cfb557c4 3626 [(set_attr "type" "load")])
1fd4e8c1
RK		 3627
3628(define_insn ""
cd2b37d9 3629 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3630 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 3631 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
3632 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3633 (plus:SI (match_dup 1) (match_dup 2)))]
3634 ""
3635 "@
5f243543
RK		 3636 stbux %3,%0,%2
3637 stbu %3,%2(%0)")
1fd4e8c1
RK		 3638
3639(define_insn ""
cd2b37d9
RK		 3640 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
3641 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3642 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 3643 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3644 (plus:SI (match_dup 1) (match_dup 2)))]
3645 ""
3646 "@
5f243543
RK		 3647 lfsux %3,%0,%2
3648 lfsu %3,%2(%0)"
cfb557c4 3649 [(set_attr "type" "fpload")])
1fd4e8c1
RK		 3650
3651(define_insn ""
cd2b37d9 3652 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3653 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 3654 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
3655 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3656 (plus:SI (match_dup 1) (match_dup 2)))]
3657 ""
3658 "@
5f243543
RK		 3659 frsp %3,%3\;stfsux %3,%0,%2
3660 frsp %3,%3\;stfsu %3,%2(%0)")
1fd4e8c1
RK		 3661
3662(define_insn ""
cd2b37d9
RK		 3663 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
3664 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3665 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 3666 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3667 (plus:SI (match_dup 1) (match_dup 2)))]
3668 ""
3669 "@
5f243543
RK		 3670 lfdux %3,%0,%2
3671 lfdu %3,%2(%0)"
cfb557c4 3672 [(set_attr "type" "fpload")])
1fd4e8c1
RK		 3673
3674(define_insn ""
cd2b37d9 3675 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 3676 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 3677 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
3678 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1
RK		 3679 (plus:SI (match_dup 1) (match_dup 2)))]
3680 ""
3681 "@
5f243543
RK		 3682 stfdux %3,%0,%2
3683 stfdu %3,%2(%0)")
1fd4e8c1
RK		 3684\f
3685;; Next come insns related to the calling sequence.
3686;;
3687;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
59257ff7 3688;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 3689
3690(define_expand "allocate_stack"
3691 [(set (reg:SI 1)
01def764 3692 (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))]
1fd4e8c1
RK		 3693 ""
3694 "
3695{ rtx chain = gen_reg_rtx (SImode);
3696 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
3697
3698 emit_move_insn (chain, stack_bot);
a0044fb1 3699 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
1fd4e8c1
RK		 3700 emit_move_insn (stack_bot, chain);
3701 DONE;
3702}")
59257ff7
RK		 3703
3704;; These patterns say how to save and restore the stack pointer. We need not
3705;; save the stack pointer at function level since we are careful to
3706;; preserve the backchain. At block level, we have to restore the backchain
3707;; when we restore the stack pointer.
3708;;
3709;; For nonlocal gotos, we must save both the stack pointer and its
3710;; backchain and restore both. Note that in the nonlocal case, the
3711;; save area is a memory location.
3712
3713(define_expand "save_stack_function"
3714 [(use (const_int 0))]
3715 ""
3716 "")
3717
3718(define_expand "restore_stack_function"
3719 [(use (const_int 0))]
3720 ""
3721 "")
3722
3723(define_expand "restore_stack_block"
3724 [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" "")))
3725 (set (match_dup 0) (match_operand:SI 1 "register_operand" ""))
3726 (set (mem:SI (match_dup 0)) (match_dup 2))]
3727 ""
3728 "
3729{ operands[2] = gen_reg_rtx (SImode); }")
3730
3731(define_expand "save_stack_nonlocal"
3732 [(match_operand:DI 0 "memory_operand" "")
3733 (match_operand:SI 1 "register_operand" "")]
3734 ""
3735 "
3736{
3737 rtx temp = gen_reg_rtx (SImode);
3738
3739 /* Copy the backchain to the first word, sp to the second. */
3740 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1]));
3741 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp);
3742 emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
3743 DONE;
3744}")
3745
3746(define_expand "restore_stack_nonlocal"
3747 [(match_operand:SI 0 "register_operand" "")
3748 (match_operand:DI 1 "memory_operand" "")]
3749 ""
3750 "
3751{
3752 rtx temp = gen_reg_rtx (SImode);
3753
3754 /* Restore the backchain from the first word, sp from the second. */
3755 emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode));
3756 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode));
3757 emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
3758 DONE;
3759}")
1fd4e8c1
RK		 3760\f
3761;; A function pointer is a pointer to a data area whose first word contains
3762;; the actual address of the function, whose second word contains a pointer
3763;; to its TOC, and whose third word contains a value to place in the static
3764;; chain register (r11). Note that if we load the static chain, our
3765;; "trampoline" need not have any executable code.
3766;;
3767;; operands[0] is an SImode pseudo in which we place the address of the
3768;; function.
3769;; operands[1] is the address of data area of the function to call
3770
3771(define_expand "call_via_ptr"
cd2b37d9
RK		 3772 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3773 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
1fd4e8c1
RK		 3774 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
3775 (reg:SI 2))
3776 (set (reg:SI 2)
3777 (mem:SI (plus:SI (match_dup 1)
3778 (const_int 4))))
3779 (set (reg:SI 11)
3780 (mem:SI (plus:SI (match_dup 1)
3781 (const_int 8))))
3782 (use (reg:SI 2))
3783 (use (reg:SI 11))]
3784 ""
3785 "")
3786
3787(define_expand "call"
3788 [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
3789 (match_operand 1 "" ""))
3790 (clobber (scratch:SI))])]
3791 ""
3792 "
3793{
3794 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
3795 abort ();
3796
3797 operands[0] = XEXP (operands[0], 0);
3798 if (GET_CODE (operands[0]) != SYMBOL_REF)
3799 {
3800 rtx temp = gen_reg_rtx (SImode);
3801
3802 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
3803 operands[0] = temp;
3804 }
3805}")
3806
3807(define_expand "call_value"
3808 [(parallel [(set (match_operand 0 "" "")
3809 (call (mem:SI (match_operand:SI 1 "address_operand" ""))
3810 (match_operand 2 "" "")))
3811 (clobber (scratch:SI))])]
3812 ""
3813 "
3814{
3815 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
3816 abort ();
3817
3818 operands[1] = XEXP (operands[1], 0);
3819 if (GET_CODE (operands[1]) != SYMBOL_REF)
3820 {
3821 rtx temp = gen_reg_rtx (SImode);
3822
3823 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
3824 operands[1] = temp;
3825 }
3826}")
3827
04780ee7
RK		 3828;; Call to function in current module. No TOC pointer reload needed.
3829
3830(define_insn ""
3831 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s"))
3832 (match_operand 1 "" "g"))
3833 (clobber (match_scratch:SI 2 "=l"))]
3834 ""
3835 "bl %z0")
3836
3837;; Call to function which may be in another module. Restore the TOC
3838;; pointer (r2) after the call.
3839
1fd4e8c1
RK		 3840(define_insn ""
3841 [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
3842 (match_operand 1 "" "fg,fg"))
9482d6de 3843 (clobber (match_scratch:SI 2 "=l,l"))]
1fd4e8c1
RK		 3844 ""
3845 "@
ca7f5001 3846 {brl|blrl}\;{l|lwz} 2,20(1)
a0292f62 3847 bl %z0\;%."
b19003d8 3848 [(set_attr "length" "8")])
1fd4e8c1 3849
04780ee7
RK		 3850(define_insn ""
3851 [(set (match_operand 0 "" "=fg")
3852 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s"))
3853 (match_operand 2 "" "g")))
3854 (clobber (match_scratch:SI 3 "=l"))]
3855 ""
3856 "bl %z1")
3857
1fd4e8c1 3858(define_insn ""
5f243543 3859 [(set (match_operand 0 "" "=fg,fg")
1fd4e8c1
RK		 3860 (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
3861 (match_operand 2 "" "fg,fg")))
3862 (clobber (match_scratch:SI 3 "=l,l"))]
3863 ""
3864 "@
ca7f5001 3865 {brl|blrl}\;{l|lwz} 2,20(1)
a0292f62 3866 bl %z1\;%."
b19003d8 3867 [(set_attr "length" "8")])
e6f948e3
RK		 3868
3869;; Call subroutine returning any type.
3870
3871(define_expand "untyped_call"
3872 [(parallel [(call (match_operand 0 "" "")
3873 (const_int 0))
3874 (match_operand 1 "" "")
3875 (match_operand 2 "" "")])]
3876 ""
3877 "
3878{
3879 int i;
3880
3881 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
3882
3883 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3884 {
3885 rtx set = XVECEXP (operands[2], 0, i);
3886 emit_move_insn (SET_DEST (set), SET_SRC (set));
3887 }
3888
3889 /* The optimizer does not know that the call sets the function value
3890 registers we stored in the result block. We avoid problems by
3891 claiming that all hard registers are used and clobbered at this
3892 point. */
3893 emit_insn (gen_blockage ());
3894
3895 DONE;
3896}")
3897
3898;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3899;; all of memory. This blocks insns from being moved across this point.
3900
3901(define_insn "blockage"
3902 [(unspec_volatile [(const_int 0)] 0)]
3903 ""
3904 "")
1fd4e8c1
RK		 3905\f
3906;; Compare insns are next. Note that the RS/6000 has two types of compares,
3907;; signed & unsigned, and one type of branch.
3908;;
3909;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
3910;; insns, and branches. We store the operands of compares until we see
3911;; how it is used.
3912(define_expand "cmpsi"
3913 [(set (cc0)
cd2b37d9 3914 (compare (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 3915 (match_operand:SI 1 "reg_or_short_operand" "")))]
3916 ""
3917 "
3918{
3919 /* Take care of the possibility that operands[1] might be negative but
3920 this might be a logical operation. That insn doesn't exist. */
3921 if (GET_CODE (operands[1]) == CONST_INT
3922 && INTVAL (operands[1]) < 0)
3923 operands[1] = force_reg (SImode, operands[1]);
3924
3925 rs6000_compare_op0 = operands[0];
3926 rs6000_compare_op1 = operands[1];
3927 rs6000_compare_fp_p = 0;
3928 DONE;
3929}")
3930
3931(define_expand "cmpsf"
cd2b37d9
RK		 3932 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
3933 (match_operand:SF 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 3934 ""
3935 "
3936{
3937 rs6000_compare_op0 = operands[0];
3938 rs6000_compare_op1 = operands[1];
3939 rs6000_compare_fp_p = 1;
3940 DONE;
3941}")
3942
3943(define_expand "cmpdf"
cd2b37d9
RK		 3944 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
3945 (match_operand:DF 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 3946 ""
3947 "
3948{
3949 rs6000_compare_op0 = operands[0];
3950 rs6000_compare_op1 = operands[1];
3951 rs6000_compare_fp_p = 1;
3952 DONE;
3953}")
3954
3955(define_expand "beq"
3956 [(set (match_dup 2) (match_dup 1))
3957 (set (pc)
3958 (if_then_else (eq (match_dup 2)
3959 (const_int 0))
3960 (label_ref (match_operand 0 "" ""))
3961 (pc)))]
3962 ""
3963 "
3964{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3965 operands[1] = gen_rtx (COMPARE, mode,
3966 rs6000_compare_op0, rs6000_compare_op1);
3967 operands[2] = gen_reg_rtx (mode);
3968}")
3969
3970(define_expand "bne"
3971 [(set (match_dup 2) (match_dup 1))
3972 (set (pc)
3973 (if_then_else (ne (match_dup 2)
3974 (const_int 0))
3975 (label_ref (match_operand 0 "" ""))
3976 (pc)))]
3977 ""
3978 "
3979{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3980 operands[1] = gen_rtx (COMPARE, mode,
3981 rs6000_compare_op0, rs6000_compare_op1);
3982 operands[2] = gen_reg_rtx (mode);
3983}")
3984
3985(define_expand "blt"
3986 [(set (match_dup 2) (match_dup 1))
3987 (set (pc)
3988 (if_then_else (lt (match_dup 2)
3989 (const_int 0))
3990 (label_ref (match_operand 0 "" ""))
3991 (pc)))]
3992 ""
3993 "
3994{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3995 operands[1] = gen_rtx (COMPARE, mode,
3996 rs6000_compare_op0, rs6000_compare_op1);
3997 operands[2] = gen_reg_rtx (mode);
3998}")
3999
4000(define_expand "bgt"
4001 [(set (match_dup 2) (match_dup 1))
4002 (set (pc)
4003 (if_then_else (gt (match_dup 2)
4004 (const_int 0))
4005 (label_ref (match_operand 0 "" ""))
4006 (pc)))]
4007 ""
4008 "
4009{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
4010 operands[1] = gen_rtx (COMPARE, mode,
4011 rs6000_compare_op0, rs6000_compare_op1);
4012 operands[2] = gen_reg_rtx (mode);
4013}")
4014
4015(define_expand "ble"
4016 [(set (match_dup 2) (match_dup 1))
4017 (set (pc)
4018 (if_then_else (le (match_dup 2)
4019 (const_int 0))
4020 (label_ref (match_operand 0 "" ""))
4021 (pc)))]
4022 ""
4023 "
4024{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
4025 operands[1] = gen_rtx (COMPARE, mode,
4026 rs6000_compare_op0, rs6000_compare_op1);
4027 operands[2] = gen_reg_rtx (mode);
4028}")
4029
4030(define_expand "bge"
4031 [(set (match_dup 2) (match_dup 1))
4032 (set (pc)
4033 (if_then_else (ge (match_dup 2)
4034 (const_int 0))
4035 (label_ref (match_operand 0 "" ""))
4036 (pc)))]
4037 ""
4038 "
4039{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
4040 operands[1] = gen_rtx (COMPARE, mode,
4041 rs6000_compare_op0, rs6000_compare_op1);
4042 operands[2] = gen_reg_rtx (mode);
4043}")
4044
4045(define_expand "bgtu"
4046 [(set (match_dup 2) (match_dup 1))
4047 (set (pc)
4048 (if_then_else (gtu (match_dup 2)
4049 (const_int 0))
4050 (label_ref (match_operand 0 "" ""))
4051 (pc)))]
4052 ""
4053 "
4054{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
4055 rs6000_compare_op0, rs6000_compare_op1);
4056 operands[2] = gen_reg_rtx (CCUNSmode);
4057}")
4058
4059(define_expand "bltu"
4060 [(set (match_dup 2) (match_dup 1))
4061 (set (pc)
4062 (if_then_else (ltu (match_dup 2)
4063 (const_int 0))
4064 (label_ref (match_operand 0 "" ""))
4065 (pc)))]
4066 ""
4067 "
4068{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
4069 rs6000_compare_op0, rs6000_compare_op1);
4070 operands[2] = gen_reg_rtx (CCUNSmode);
4071}")
4072
4073(define_expand "bgeu"
4074 [(set (match_dup 2) (match_dup 1))
4075 (set (pc)
4076 (if_then_else (geu (match_dup 2)
4077 (const_int 0))
4078 (label_ref (match_operand 0 "" ""))
4079 (pc)))]
4080 ""
4081 "
4082{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
4083 rs6000_compare_op0, rs6000_compare_op1);
4084 operands[2] = gen_reg_rtx (CCUNSmode);
4085}")
4086
4087(define_expand "bleu"
4088 [(set (match_dup 2) (match_dup 1))
4089 (set (pc)
4090 (if_then_else (leu (match_dup 2)
4091 (const_int 0))
4092 (label_ref (match_operand 0 "" ""))
4093 (pc)))]
4094 ""
4095 "
4096{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
4097 rs6000_compare_op0, rs6000_compare_op1);
4098 operands[2] = gen_reg_rtx (CCUNSmode);
4099}")
4100
4101;; For SNE, we would prefer that the xor/abs sequence be used for integers.
4102;; For SEQ, likewise, except that comparisons with zero should be done
4103;; with an scc insns. However, due to the order that combine see the
4104;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
4105;; the cases we don't want to handle.
4106(define_expand "seq"
4107 [(set (match_dup 2) (match_dup 1))
cd2b37d9 4108 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4109 (eq:SI (match_dup 2) (const_int 0)))]
4110 ""
4111 "
4112{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
4113 operands[1] = gen_rtx (COMPARE, mode,
4114 rs6000_compare_op0, rs6000_compare_op1);
4115 operands[2] = gen_reg_rtx (mode);
4116}")
4117
4118(define_expand "sne"
4119 [(set (match_dup 2) (match_dup 1))
cd2b37d9 4120 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4121 (ne:SI (match_dup 2) (const_int 0)))]
4122 ""
4123 "
4124{ if (! rs6000_compare_fp_p)
4125 FAIL;
4126
4127 operands[1] = gen_rtx (COMPARE, CCFPmode,
4128 rs6000_compare_op0, rs6000_compare_op1);
4129 operands[2] = gen_reg_rtx (CCFPmode);
4130}")
4131
4132;; A > 0 is best done using the portable sequence, so fail in that case.
4133(define_expand "sgt"
4134 [(set (match_dup 2) (match_dup 1))
cd2b37d9 4135 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4136 (gt:SI (match_dup 2) (const_int 0)))]
4137 ""
4138 "
4139{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
4140
4141 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
4142 FAIL;
4143
4144 operands[1] = gen_rtx (COMPARE, mode,
4145 rs6000_compare_op0, rs6000_compare_op1);
4146 operands[2] = gen_reg_rtx (mode);
4147}")
4148
4149;; A < 0 is best done in the portable way for A an integer.
4150(define_expand "slt"
4151 [(set (match_dup 2) (match_dup 1))
cd2b37d9 4152 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4153 (lt:SI (match_dup 2) (const_int 0)))]
4154 ""
4155 "
4156{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
4157
4158 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
4159 FAIL;
4160
4161 operands[1] = gen_rtx (COMPARE, mode,
4162 rs6000_compare_op0, rs6000_compare_op1);
4163 operands[2] = gen_reg_rtx (mode);
4164}")
4165
4166(define_expand "sge"
4167 [(set (match_dup 2) (match_dup 1))
cd2b37d9 4168 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4169 (ge:SI (match_dup 2) (const_int 0)))]
4170 ""
4171 "
4172{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
4173 operands[1] = gen_rtx (COMPARE, mode,
4174 rs6000_compare_op0, rs6000_compare_op1);
4175 operands[2] = gen_reg_rtx (mode);
4176}")
4177
4178;; A <= 0 is best done the portable way for A an integer.
4179(define_expand "sle"
4180 [(set (match_dup 2) (match_dup 1))
cd2b37d9 4181 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4182 (le:SI (match_dup 2) (const_int 0)))]
4183 ""
4184 "
4185{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
4186
4187 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
4188 FAIL;
4189
4190 operands[1] = gen_rtx (COMPARE, mode,
4191 rs6000_compare_op0, rs6000_compare_op1);
4192 operands[2] = gen_reg_rtx (mode);
4193}")
4194
4195(define_expand "sgtu"
4196 [(set (match_dup 2) (match_dup 1))
cd2b37d9 4197 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4198 (gtu:SI (match_dup 2) (const_int 0)))]
4199 ""
4200 "
4201{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
4202 rs6000_compare_op0, rs6000_compare_op1);
4203 operands[2] = gen_reg_rtx (CCUNSmode);
4204}")
4205
4206(define_expand "sltu"
4207 [(set (match_dup 2) (match_dup 1))
cd2b37d9 4208 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4209 (ltu:SI (match_dup 2) (const_int 0)))]
4210 ""
4211 "
4212{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
4213 rs6000_compare_op0, rs6000_compare_op1);
4214 operands[2] = gen_reg_rtx (CCUNSmode);
4215}")
4216
4217(define_expand "sgeu"
4218 [(set (match_dup 2) (match_dup 1))
cd2b37d9 4219 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4220 (geu:SI (match_dup 2) (const_int 0)))]
4221 ""
4222 "
4223{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
4224 rs6000_compare_op0, rs6000_compare_op1);
4225 operands[2] = gen_reg_rtx (CCUNSmode);
4226}")
4227
4228(define_expand "sleu"
4229 [(set (match_dup 2) (match_dup 1))
cd2b37d9 4230 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4231 (leu:SI (match_dup 2) (const_int 0)))]
4232 ""
4233 "
4234{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
4235 rs6000_compare_op0, rs6000_compare_op1);
4236 operands[2] = gen_reg_rtx (CCUNSmode);
4237}")
4238\f
4239;; Here are the actual compare insns.
4240(define_insn ""
4241 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
cd2b37d9 4242 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4243 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4244 ""
7f340546 4245 "{cmp%I2|cmpw%I2} %0,%1,%2"
1fd4e8c1
RK		 4246 [(set_attr "type" "compare")])
4247
f357808b
RK		 4248;; If we are comparing a register for equality with a large constant,
4249;; we can do this with an XOR followed by a compare. But we need a scratch
4250;; register for the result of the XOR.
4251
4252(define_split
4253 [(set (match_operand:CC 0 "cc_reg_operand" "")
cd2b37d9 4254 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
f357808b 4255 (match_operand:SI 2 "non_short_cint_operand" "")))
cd2b37d9 4256 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
f357808b
RK		 4257 "find_single_use (operands[0], insn, 0)
4258 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
4259 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
4260 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
4261 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
4262 "
4263{
4264 /* Get the constant we are comparing against, C, and see what it looks like
4265 sign-extended to 16 bits. Then see what constant could be XOR'ed
4266 with C to get the sign-extended value. */
4267
4268 int c = INTVAL (operands[2]);
4269 int sextc = (c << 16) >> 16;
4270 int xorv = c ^ sextc;
4271
4272 operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
4273 operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
4274}")
4275
1fd4e8c1
RK		 4276(define_insn ""
4277 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 4278 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4279 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
4280 ""
7f340546 4281 "{cmpl%I2|cmplw%I2} %0,%1,%W2"
1fd4e8c1
RK		 4282 [(set_attr "type" "compare")])
4283
4284;; The following two insns don't exist as single insns, but if we provide
4285;; them, we can swap an add and compare, which will enable us to overlap more
4286;; of the required delay between a compare and branch. We generate code for
4287;; them by splitting.
4288
4289(define_insn ""
4290 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 4291 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4292 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 4293 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4294 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
4295 ""
baf97f86
RK		 4296 "#"
4297 [(set_attr "length" "8")])
1fd4e8c1
RK		 4298
4299(define_insn ""
4300 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 4301 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4302 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 4303 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4304 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
4305 ""
baf97f86
RK		 4306 "#"
4307 [(set_attr "length" "8")])
1fd4e8c1
RK		 4308
4309(define_split
4310 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 4311 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 4312 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 4313 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4314 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
4315 ""
4316 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
4317 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
4318
4319(define_split
4320 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 4321 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 4322 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 4323 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 4324 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
4325 ""
4326 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
4327 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
4328
4329(define_insn ""
4330 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 4331 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
4332 (match_operand:SF 2 "gpc_reg_operand" "f")))]
1fd4e8c1
RK		 4333 ""
4334 "fcmpu %0,%1,%2"
4335 [(set_attr "type" "fpcompare")])
4336
4337(define_insn ""
4338 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 4339 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
4340 (match_operand:DF 2 "gpc_reg_operand" "f")))]
1fd4e8c1
RK		 4341 ""
4342 "fcmpu %0,%1,%2"
4343 [(set_attr "type" "fpcompare")])
4344\f
4345;; Now we have the scc insns. We can do some combinations because of the
4346;; way the machine works.
4347;;
4348;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 4349;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
4350;; cases the insns below which don't use an intermediate CR field will
4351;; be used instead.
1fd4e8c1 4352(define_insn ""
cd2b37d9 4353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4354 (match_operator:SI 1 "scc_comparison_operator"
4355 [(match_operand 2 "cc_reg_operand" "y")
4356 (const_int 0)]))]
4357 ""
ca7f5001 4358 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
b19003d8 4359 [(set_attr "length" "12")])
1fd4e8c1
RK		 4360
4361(define_insn ""
4362 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4363 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
4364 [(match_operand 2 "cc_reg_operand" "y")
4365 (const_int 0)])
4366 (const_int 0)))
cd2b37d9 4367 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4368 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4369 ""
ca7f5001 4370 "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
b19003d8
RK		 4371 [(set_attr "type" "delayed_compare")
4372 (set_attr "length" "12")])
1fd4e8c1
RK		 4373
4374(define_insn ""
cd2b37d9 4375 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4376 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
4377 [(match_operand 2 "cc_reg_operand" "y")
4378 (const_int 0)])
4379 (match_operand:SI 3 "const_int_operand" "n")))]
4380 ""
4381 "*
4382{
4383 int is_bit = ccr_bit (operands[1], 1);
4384 int put_bit = 31 - (INTVAL (operands[3]) & 31);
4385 int count;
4386
4387 if (is_bit >= put_bit)
4388 count = is_bit - put_bit;
4389 else
4390 count = 32 - (put_bit - is_bit);
4391
4392 operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
4393 operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
4394
ca7f5001 4395 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8
RK		 4396}"
4397 [(set_attr "length" "12")])
1fd4e8c1
RK		 4398
4399(define_insn ""
4400 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4401 (compare:CC
4402 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
4403 [(match_operand 2 "cc_reg_operand" "y")
4404 (const_int 0)])
4405 (match_operand:SI 3 "const_int_operand" "n"))
4406 (const_int 0)))
cd2b37d9 4407 (set (match_operand:SI 4 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4408 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
4409 (match_dup 3)))]
4410 ""
4411 "*
4412{
4413 int is_bit = ccr_bit (operands[1], 1);
4414 int put_bit = 31 - (INTVAL (operands[3]) & 31);
4415 int count;
4416
4417 if (is_bit >= put_bit)
4418 count = is_bit - put_bit;
4419 else
4420 count = 32 - (put_bit - is_bit);
4421
4422 operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
4423 operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
4424
ca7f5001 4425 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 4426}"
b19003d8
RK		 4427 [(set_attr "type" "delayed_compare")
4428 (set_attr "length" "12")])
1fd4e8c1 4429
c5defebb
RK		 4430;; If we are comparing the result of two comparisons, this can be done
4431;; using creqv or crxor.
4432
4433(define_insn ""
4434 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
4435 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
4436 [(match_operand 2 "cc_reg_operand" "y")
4437 (const_int 0)])
4438 (match_operator 3 "scc_comparison_operator"
4439 [(match_operand 4 "cc_reg_operand" "y")
4440 (const_int 0)])))]
4441 "REGNO (operands[2]) != REGNO (operands[4])"
4442 "*
4443{
4444 enum rtx_code code1, code2;
4445
4446 code1 = GET_CODE (operands[1]);
4447 code2 = GET_CODE (operands[3]);
4448
4449 if ((code1 == EQ || code1 == LT || code1 == GT
4450 || code1 == LTU || code1 == GTU
4451 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
4452 !=
4453 (code2 == EQ || code2 == LT || code2 == GT
4454 || code2 == LTU || code2 == GTU
4455 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
4456 return \"%C1%C3crxor %E0,%j1,%j3\";
4457 else
4458 return \"%C1%C3creqv %E0,%j1,%j3\";
b19003d8
RK		 4459}"
4460 [(set_attr "length" "12")])
c5defebb
RK		 4461
4462;; There is a 3 cycle delay between consecutive mfcr instructions
4463;; so it is useful to combine 2 scc instructions to use only one mfcr.
4464
4465(define_peephole
cd2b37d9 4466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 4467 (match_operator:SI 1 "scc_comparison_operator"
4468 [(match_operand 2 "cc_reg_operand" "y")
4469 (const_int 0)]))
cd2b37d9 4470 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 4471 (match_operator:SI 4 "scc_comparison_operator"
4472 [(match_operand 5 "cc_reg_operand" "y")
4473 (const_int 0)]))]
4474 "REGNO (operands[2]) != REGNO (operands[5])"
ca7f5001 4475 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b19003d8 4476 [(set_attr "length" "20")])
c5defebb 4477
1fd4e8c1
RK		 4478;; There are some scc insns that can be done directly, without a compare.
4479;; These are faster because they don't involve the communications between
4480;; the FXU and branch units. In fact, we will be replacing all of the
4481;; integer scc insns here or in the portable methods in emit_store_flag.
4482;;
4483;; Also support (neg (scc ..)) since that construct is used to replace
4484;; branches, (plus (scc ..) ..) since that construct is common and
4485;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
4486;; cases where it is no more expensive than (neg (scc ..)).
4487
4488;; Have reload force a constant into a register for the simple insns that
4489;; otherwise won't accept constants. We do this because it is faster than
4490;; the cmp/mfcr sequence we would otherwise generate.
4491
4492(define_insn ""
cd2b37d9
RK		 4493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
4494 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1fd4e8c1
RK		 4495 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
4496 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
4497 ""
4498 "@
ca7f5001 4499 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
71d2371f 4500 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
ca7f5001
RK		 4501 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
4502 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
4503 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
b19003d8 4504 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1
RK		 4505
4506(define_insn ""
4507 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
4508 (compare:CC
cd2b37d9 4509 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1fd4e8c1
RK		 4510 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
4511 (const_int 0)))
cd2b37d9 4512 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
1fd4e8c1
RK		 4513 (eq:SI (match_dup 1) (match_dup 2)))
4514 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
4515 ""
4516 "@
ca7f5001
RK		 4517 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
4518 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
4519 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
4520 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
4521 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0"
b19003d8
RK		 4522 [(set_attr "type" "compare")
4523 (set_attr "length" "12,8,12,12,12")])
4524
4525;; We have insns of the form shown by the first define_insn below. If
4526;; there is something inside the comparison operation, we must split it.
4527(define_split
4528 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4529 (plus:SI (match_operator 1 "comparison_operator"
4530 [(match_operand:SI 2 "" "")
4531 (match_operand:SI 3
4532 "reg_or_cint_operand" "")])
4533 (match_operand:SI 4 "gpc_reg_operand" "")))
4534 (clobber (match_operand:SI 5 "register_operand" ""))]
4535 "! gpc_reg_operand (operands[2], SImode)"
4536 [(set (match_dup 5) (match_dup 2))
4537 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
4538 (match_dup 4)))])
1fd4e8c1
RK		 4539
4540(define_insn ""
cd2b37d9
RK		 4541 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
4542 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1fd4e8c1 4543 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
cd2b37d9 4544 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
1fd4e8c1
RK		 4545 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
4546 ""
4547 "@
ca7f5001
RK		 4548 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
4549 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
4550 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
4551 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
d9d934ef 4552 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
b19003d8 4553 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1
RK		 4554
4555(define_insn ""
4556 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
4557 (compare:CC
4558 (plus:SI
cd2b37d9 4559 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1fd4e8c1 4560 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
cd2b37d9 4561 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
1fd4e8c1
RK		 4562 (const_int 0)))
4563 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
4564 ""
4565 "@
ca7f5001
RK		 4566 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
4567 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
4568 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
4569 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
4570 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
b19003d8
RK		 4571 [(set_attr "type" "compare")
4572 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1
RK		 4573
4574(define_insn ""
4575 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
4576 (compare:CC
4577 (plus:SI
cd2b37d9 4578 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
1fd4e8c1 4579 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
cd2b37d9 4580 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
1fd4e8c1 4581 (const_int 0)))
cd2b37d9 4582 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
1fd4e8c1
RK		 4583 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4584 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
4585 ""
4586 "@
ca7f5001
RK		 4587 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
4588 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
4589 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
4590 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
4591 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
b19003d8
RK		 4592 [(set_attr "type" "compare")
4593 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1
RK		 4594
4595(define_insn ""
cd2b37d9
RK		 4596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
4597 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r")
1fd4e8c1
RK		 4598 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
4599 ""
4600 "@
ca7f5001
RK		 4601 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
4602 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
4603 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
4604 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
4605 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 4606 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1
RK		 4607
4608;; This is what (plus (ne X (const_int 0)) Y) looks like.
4609(define_insn ""
cd2b37d9 4610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 4611 (plus:SI (lshiftrt:SI
cd2b37d9 4612 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 4613 (const_int 31))
cd2b37d9 4614 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1
RK		 4615 (clobber (match_scratch:SI 3 "=&r"))]
4616 ""
ca7f5001 4617 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
b19003d8 4618 [(set_attr "length" "8")])
1fd4e8c1
RK		 4619
4620(define_insn ""
4621 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4622 (compare:CC
4623 (plus:SI (lshiftrt:SI
cd2b37d9 4624 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 4625 (const_int 31))
cd2b37d9 4626 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 4627 (const_int 0)))
4628 (clobber (match_scratch:SI 3 "=&r"))]
4629 ""
ca7f5001 4630 "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"
b19003d8
RK		 4631 [(set_attr "type" "compare")
4632 (set_attr "length" "8")])
1fd4e8c1
RK		 4633
4634(define_insn ""
4635 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4636 (compare:CC
4637 (plus:SI (lshiftrt:SI
cd2b37d9 4638 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 4639 (const_int 31))
cd2b37d9 4640 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 4641 (const_int 0)))
cd2b37d9 4642 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4643 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
4644 (match_dup 2)))
4645 (clobber (match_scratch:SI 3 "=&r"))]
4646 ""
ca7f5001 4647 "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"
b19003d8
RK		 4648 [(set_attr "type" "compare")
4649 (set_attr "length" "8")])
1fd4e8c1
RK		 4650
4651(define_insn ""
cd2b37d9
RK		 4652 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4653 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4654 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
4655 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 4656 "TARGET_POWER"
1fd4e8c1 4657 "@
ca7f5001 4658 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 4659 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 4660 [(set_attr "length" "12")])
1fd4e8c1
RK		 4661
4662(define_insn ""
4663 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
4664 (compare:CC
cd2b37d9 4665 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4666 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
4667 (const_int 0)))
cd2b37d9 4668 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4669 (le:SI (match_dup 1) (match_dup 2)))
4670 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 4671 "TARGET_POWER"
1fd4e8c1 4672 "@
ca7f5001 4673 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
7f340546 4674 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
b19003d8
RK		 4675 [(set_attr "type" "delayed_compare,compare")
4676 (set_attr "length" "12")])
1fd4e8c1
RK		 4677
4678(define_insn ""
cd2b37d9
RK		 4679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4680 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 4681 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
cd2b37d9 4682 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 4683 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 4684 "TARGET_POWER"
1fd4e8c1 4685 "@
ca7f5001
RK		 4686 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
4687 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
b19003d8 4688 [(set_attr "length" "12")])
1fd4e8c1
RK		 4689
4690(define_insn ""
4691 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4692 (compare:CC
cd2b37d9 4693 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 4694 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
cd2b37d9 4695 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1
RK		 4696 (const_int 0)))
4697 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 4698 "TARGET_POWER"
1fd4e8c1 4699 "@
ca7f5001
RK		 4700 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
4701 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3"
b19003d8
RK		 4702 [(set_attr "type" "compare")
4703 (set_attr "length" "12")])
1fd4e8c1
RK		 4704
4705(define_insn ""
4706 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4707 (compare:CC
cd2b37d9 4708 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 4709 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
cd2b37d9 4710 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 4711 (const_int 0)))
cd2b37d9 4712 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4713 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4714 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 4715 "TARGET_POWER"
1fd4e8c1 4716 "@
ca7f5001
RK		 4717 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
4718 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3"
b19003d8
RK		 4719 [(set_attr "type" "compare")
4720 (set_attr "length" "12")])
1fd4e8c1
RK		 4721
4722(define_insn ""
cd2b37d9
RK		 4723 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4724 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 4725 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 4726 "TARGET_POWER"
1fd4e8c1 4727 "@
ca7f5001
RK		 4728 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
4729 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 4730 [(set_attr "length" "12")])
1fd4e8c1
RK		 4731
4732(define_insn ""
cd2b37d9
RK		 4733 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4734 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4735 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4736 ""
ca7f5001 4737 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
b19003d8 4738 [(set_attr "length" "12")])
1fd4e8c1
RK		 4739
4740(define_insn ""
4741 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4742 (compare:CC
cd2b37d9 4743 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4744 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4745 (const_int 0)))
cd2b37d9 4746 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4747 (leu:SI (match_dup 1) (match_dup 2)))]
4748 ""
ca7f5001 4749 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
b19003d8
RK		 4750 [(set_attr "type" "compare")
4751 (set_attr "length" "12")])
1fd4e8c1
RK		 4752
4753(define_insn ""
cd2b37d9
RK		 4754 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4755 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4756 (match_operand:SI 2 "reg_or_short_operand" "rI"))
cd2b37d9 4757 (match_operand:SI 3 "gpc_reg_operand" "r")))
1fd4e8c1
RK		 4758 (clobber (match_scratch:SI 4 "=&r"))]
4759 ""
ca7f5001 4760 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
b19003d8 4761 [(set_attr "length" "8")])
1fd4e8c1
RK		 4762
4763(define_insn ""
4764 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4765 (compare:CC
cd2b37d9 4766 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4767 (match_operand:SI 2 "reg_or_short_operand" "rI"))
cd2b37d9 4768 (match_operand:SI 3 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 4769 (const_int 0)))
4770 (clobber (match_scratch:SI 4 "=&r"))]
4771 ""
ca7f5001 4772 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"
b19003d8
RK		 4773 [(set_attr "type" "compare")
4774 (set_attr "length" "8")])
1fd4e8c1
RK		 4775
4776(define_insn ""
4777 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4778 (compare:CC
cd2b37d9 4779 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4780 (match_operand:SI 2 "reg_or_short_operand" "rI"))
cd2b37d9 4781 (match_operand:SI 3 "gpc_reg_operand" "r"))
1fd4e8c1 4782 (const_int 0)))
cd2b37d9 4783 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4784 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4785 (clobber (match_scratch:SI 4 "=&r"))]
4786 ""
ca7f5001 4787 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"
b19003d8
RK		 4788 [(set_attr "type" "compare")
4789 (set_attr "length" "8")])
1fd4e8c1
RK		 4790
4791(define_insn ""
cd2b37d9
RK		 4792 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4793 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4794 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4795 ""
ca7f5001 4796 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
b19003d8 4797 [(set_attr "length" "12")])
1fd4e8c1
RK		 4798
4799(define_insn ""
cd2b37d9 4800 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 4801 (and:SI (neg:SI
cd2b37d9 4802 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4803 (match_operand:SI 2 "reg_or_short_operand" "rI")))
cd2b37d9 4804 (match_operand:SI 3 "gpc_reg_operand" "r")))
1fd4e8c1
RK		 4805 (clobber (match_scratch:SI 4 "=&r"))]
4806 ""
ca7f5001 4807 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
b19003d8 4808 [(set_attr "length" "12")])
1fd4e8c1
RK		 4809
4810(define_insn ""
4811 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4812 (compare:CC
4813 (and:SI (neg:SI
cd2b37d9 4814 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4815 (match_operand:SI 2 "reg_or_short_operand" "rI")))
cd2b37d9 4816 (match_operand:SI 3 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 4817 (const_int 0)))
4818 (clobber (match_scratch:SI 4 "=&r"))]
4819 ""
ca7f5001 4820 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
b19003d8
RK		 4821 [(set_attr "type" "compare")
4822 (set_attr "length" "12")])
1fd4e8c1
RK		 4823
4824(define_insn ""
4825 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4826 (compare:CC
4827 (and:SI (neg:SI
cd2b37d9 4828 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4829 (match_operand:SI 2 "reg_or_short_operand" "rI")))
cd2b37d9 4830 (match_operand:SI 3 "gpc_reg_operand" "r"))
1fd4e8c1 4831 (const_int 0)))
cd2b37d9 4832 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4833 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
4834 (clobber (match_scratch:SI 4 "=&r"))]
4835 ""
ca7f5001 4836 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
b19003d8
RK		 4837 [(set_attr "type" "compare")
4838 (set_attr "length" "12")])
1fd4e8c1
RK		 4839
4840(define_insn ""
cd2b37d9
RK		 4841 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4842 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4843 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 4844 "TARGET_POWER"
7f340546 4845 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 4846 [(set_attr "length" "12")])
1fd4e8c1
RK		 4847
4848(define_insn ""
4849 [(set (match_operand:SI 3 "cc_reg_operand" "=x")
4850 (compare:CC
cd2b37d9 4851 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4852 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4853 (const_int 0)))
cd2b37d9 4854 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 4855 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 4856 "TARGET_POWER"
7f340546 4857 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
b19003d8
RK		 4858 [(set_attr "type" "delayed_compare")
4859 (set_attr "length" "12")])
1fd4e8c1
RK		 4860
4861(define_insn ""
cd2b37d9
RK		 4862 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4863 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4864 (match_operand:SI 2 "reg_or_short_operand" "rI"))
cd2b37d9 4865 (match_operand:SI 3 "gpc_reg_operand" "r")))
1fd4e8c1 4866 (clobber (match_scratch:SI 4 "=&r"))]
ca7f5001
RK		 4867 "TARGET_POWER"
4868 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
b19003d8 4869 [(set_attr "length" "12")])
1fd4e8c1
RK		 4870
4871(define_insn ""
4872 [(set (match_operand:SI 0 "cc_reg_operand" "=x")
4873 (compare:CC
cd2b37d9 4874 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4875 (match_operand:SI 2 "reg_or_short_operand" "rI"))
cd2b37d9 4876 (match_operand:SI 3 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 4877 (const_int 0)))
4878 (clobber (match_scratch:SI 4 "=&r"))]
ca7f5001
RK		 4879 "TARGET_POWER"
4880 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
b19003d8
RK		 4881 [(set_attr "type" "compare")
4882 (set_attr "length" "12")])
1fd4e8c1
RK		 4883
4884(define_insn ""
4885 [(set (match_operand:SI 5 "cc_reg_operand" "=x")
4886 (compare:CC
cd2b37d9 4887 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4888 (match_operand:SI 2 "reg_or_short_operand" "rI"))
cd2b37d9 4889 (match_operand:SI 3 "gpc_reg_operand" "r"))
1fd4e8c1 4890 (const_int 0)))
cd2b37d9 4891 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4892 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4893 (clobber (match_scratch:SI 4 "=&r"))]
ca7f5001
RK		 4894 "TARGET_POWER"
4895 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
b19003d8
RK		 4896 [(set_attr "type" "compare")
4897 (set_attr "length" "12")])
1fd4e8c1
RK		 4898
4899(define_insn ""
cd2b37d9
RK		 4900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4901 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4902 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 4903 "TARGET_POWER"
4904 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 4905 [(set_attr "length" "12")])
1fd4e8c1
RK		 4906
4907(define_insn ""
cd2b37d9
RK		 4908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4909 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4910 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
4911 ""
4912 "@
ca7f5001
RK		 4913 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
4914 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
b19003d8 4915 [(set_attr "length" "12")])
1fd4e8c1
RK		 4916
4917(define_insn ""
4918 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4919 (compare:CC
cd2b37d9 4920 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4921 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4922 (const_int 0)))
cd2b37d9 4923 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4924 (ltu:SI (match_dup 1) (match_dup 2)))]
4925 ""
4926 "@
ca7f5001
RK		 4927 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
4928 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
b19003d8
RK		 4929 [(set_attr "type" "compare")
4930 (set_attr "length" "12")])
1fd4e8c1
RK		 4931
4932(define_insn ""
cd2b37d9
RK		 4933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4934 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
1fd4e8c1
RK		 4935 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
4936 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
4937 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
4938 ""
4939 "@
ca7f5001
RK		 4940 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
4941 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
4942 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
4943 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
b19003d8 4944 [(set_attr "length" "12")])
1fd4e8c1
RK		 4945
4946(define_insn ""
3d91674b 4947 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1fd4e8c1 4948 (compare:CC
3d91674b
RK		 4949 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4950 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4951 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 4952 (const_int 0)))
3d91674b 4953 (clobber (match_scratch:SI 4 "=&r,&r"))]
1fd4e8c1
RK		 4954 ""
4955 "@
ca7f5001
RK		 4956 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
4957 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
b19003d8
RK		 4958 [(set_attr "type" "compare")
4959 (set_attr "length" "12")])
1fd4e8c1
RK		 4960
4961(define_insn ""
3d91674b 4962 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
1fd4e8c1 4963 (compare:CC
3d91674b
RK		 4964 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4965 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4966 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 4967 (const_int 0)))
3d91674b 4968 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4969 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3d91674b 4970 (clobber (match_scratch:SI 4 "=&r,&r"))]
1fd4e8c1
RK		 4971 ""
4972 "@
ca7f5001
RK		 4973 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
4974 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
b19003d8
RK		 4975 [(set_attr "type" "compare")
4976 (set_attr "length" "12")])
1fd4e8c1
RK		 4977
4978(define_insn ""
cd2b37d9
RK		 4979 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4980 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4981 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
4982 ""
4983 "@
ca7f5001
RK		 4984 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
4985 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
b19003d8 4986 [(set_attr "length" "8")])
1fd4e8c1
RK		 4987
4988(define_insn ""
cd2b37d9
RK		 4989 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4990 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4991 (match_operand:SI 2 "reg_or_short_operand" "rI")))
4992 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 4993 "TARGET_POWER"
4994 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 4995 [(set_attr "length" "12")])
1fd4e8c1
RK		 4996
4997(define_insn ""
4998 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4999 (compare:CC
cd2b37d9 5000 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 5001 (match_operand:SI 2 "reg_or_short_operand" "rI"))
5002 (const_int 0)))
cd2b37d9 5003 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 5004 (ge:SI (match_dup 1) (match_dup 2)))
5005 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 5006 "TARGET_POWER"
5007 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3"
b19003d8
RK		 5008 [(set_attr "type" "compare")
5009 (set_attr "length" "12")])
1fd4e8c1
RK		 5010
5011(define_insn ""
cd2b37d9
RK		 5012 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5013 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5014 (match_operand:SI 2 "reg_or_short_operand" "rI"))
cd2b37d9 5015 (match_operand:SI 3 "gpc_reg_operand" "r")))
1fd4e8c1 5016 (clobber (match_scratch:SI 4 "=&r"))]
ca7f5001
RK		 5017 "TARGET_POWER"
5018 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
b19003d8 5019 [(set_attr "length" "12")])
1fd4e8c1
RK		 5020
5021(define_insn ""
5022 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5023 (compare:CC
cd2b37d9 5024 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5025 (match_operand:SI 2 "reg_or_short_operand" "rI"))
cd2b37d9 5026 (match_operand:SI 3 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 5027 (const_int 0)))
5028 (clobber (match_scratch:SI 4 "=&r"))]
ca7f5001
RK		 5029 "TARGET_POWER"
5030 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
b19003d8
RK		 5031 [(set_attr "type" "compare")
5032 (set_attr "length" "12")])
1fd4e8c1
RK		 5033
5034(define_insn ""
5035 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
5036 (compare:CC
cd2b37d9 5037 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5038 (match_operand:SI 2 "reg_or_short_operand" "rI"))
cd2b37d9 5039 (match_operand:SI 3 "gpc_reg_operand" "r"))
1fd4e8c1 5040 (const_int 0)))
cd2b37d9 5041 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 5042 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5043 (clobber (match_scratch:SI 4 "=&r"))]
ca7f5001
RK		 5044 "TARGET_POWER"
5045 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
b19003d8
RK		 5046 [(set_attr "type" "compare")
5047 (set_attr "length" "12")])
1fd4e8c1
RK		 5048
5049(define_insn ""
cd2b37d9
RK		 5050 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5051 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5052 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 5053 "TARGET_POWER"
5054 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 5055 [(set_attr "length" "12")])
1fd4e8c1
RK		 5056
5057;; This is (and (neg (ge X (const_int 0))) Y).
5058(define_insn ""
cd2b37d9 5059 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 5060 (and:SI (neg:SI
5061 (lshiftrt:SI
cd2b37d9 5062 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 5063 (const_int 31)))
cd2b37d9 5064 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1
RK		 5065 (clobber (match_scratch:SI 3 "=&r"))]
5066 ""
ca7f5001 5067 "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
b19003d8 5068 [(set_attr "length" "8")])
1fd4e8c1
RK		 5069
5070(define_insn ""
5071 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5072 (compare:CC
5073 (and:SI (neg:SI
5074 (lshiftrt:SI
cd2b37d9 5075 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 5076 (const_int 31)))
cd2b37d9 5077 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 5078 (const_int 0)))
5079 (clobber (match_scratch:SI 3 "=&r"))]
5080 ""
ca7f5001 5081 "{srai|srawi} %3,%1,31\;andc. %3,%2,%3"
b19003d8
RK		 5082 [(set_attr "type" "compare")
5083 (set_attr "length" "8")])
1fd4e8c1
RK		 5084
5085(define_insn ""
5086 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
5087 (compare:CC
5088 (and:SI (neg:SI
5089 (lshiftrt:SI
cd2b37d9 5090 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 5091 (const_int 31)))
cd2b37d9 5092 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 5093 (const_int 0)))
cd2b37d9 5094 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 5095 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
5096 (const_int 31)))
5097 (match_dup 2)))
5098 (clobber (match_scratch:SI 3 "=&r"))]
5099 ""
ca7f5001 5100 "{srai|srawi} %3,%1,31\;andc. %0,%2,%3"
b19003d8
RK		 5101 [(set_attr "type" "compare")
5102 (set_attr "length" "8")])
1fd4e8c1
RK		 5103
5104(define_insn ""
cd2b37d9
RK		 5105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5106 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 5107 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
5108 ""
5109 "@
ca7f5001
RK		 5110 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
5111 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
b19003d8 5112 [(set_attr "length" "12")])
1fd4e8c1
RK		 5113
5114(define_insn ""
5115 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
5116 (compare:CC
cd2b37d9 5117 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 5118 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
5119 (const_int 0)))
cd2b37d9 5120 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 5121 (geu:SI (match_dup 1) (match_dup 2)))]
5122 ""
5123 "@
ca7f5001
RK		 5124 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
5125 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
b19003d8
RK		 5126 [(set_attr "type" "compare")
5127 (set_attr "length" "12")])
1fd4e8c1
RK		 5128
5129(define_insn ""
cd2b37d9
RK		 5130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5131 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 5132 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
cd2b37d9 5133 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1
RK		 5134 (clobber (match_scratch:SI 4 "=&r,&r"))]
5135 ""
5136 "@
ca7f5001
RK		 5137 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
5138 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
b19003d8 5139 [(set_attr "length" "8")])
1fd4e8c1
RK		 5140
5141(define_insn ""
5142 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
5143 (compare:CC
cd2b37d9 5144 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 5145 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
cd2b37d9 5146 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1
RK		 5147 (const_int 0)))
5148 (clobber (match_scratch:SI 4 "=&r,&r"))]
5149 ""
5150 "@
ca7f5001
RK		 5151 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
5152 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
b19003d8
RK		 5153 [(set_attr "type" "compare")
5154 (set_attr "length" "8")])
1fd4e8c1
RK		 5155
5156(define_insn ""
5157 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
5158 (compare:CC
cd2b37d9 5159 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 5160 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
cd2b37d9 5161 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 5162 (const_int 0)))
cd2b37d9 5163 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 5164 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5165 (clobber (match_scratch:SI 4 "=&r,&r"))]
5166 ""
5167 "@
ca7f5001
RK		 5168 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
5169 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
b19003d8
RK		 5170 [(set_attr "type" "compare")
5171 (set_attr "length" "8")])
1fd4e8c1
RK		 5172
5173(define_insn ""
cd2b37d9
RK		 5174 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5175 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 5176 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
5177 ""
5178 "@
ca7f5001
RK		 5179 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
5180 {sfi|subfic} %0,%1,-1\;a%I2 %0,%0,%2\;{sfe|subfe} %0,%0,%0"
b19003d8 5181 [(set_attr "length" "12")])
1fd4e8c1
RK		 5182
5183(define_insn ""
cd2b37d9 5184 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 5185 (and:SI (neg:SI
cd2b37d9 5186 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 5187 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
cd2b37d9 5188 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1
RK		 5189 (clobber (match_scratch:SI 4 "=&r,&r"))]
5190 ""
5191 "@
ca7f5001
RK		 5192 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
5193 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
b19003d8 5194 [(set_attr "length" "12")])
1fd4e8c1
RK		 5195
5196(define_insn ""
5197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
5198 (compare:CC
5199 (and:SI (neg:SI
cd2b37d9 5200 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 5201 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
cd2b37d9 5202 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1
RK		 5203 (const_int 0)))
5204 (clobber (match_scratch:SI 4 "=&r,&r"))]
5205 ""
5206 "@
ca7f5001
RK		 5207 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
5208 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
b19003d8
RK		 5209 [(set_attr "type" "compare")
5210 (set_attr "length" "12")])
1fd4e8c1
RK		 5211
5212(define_insn ""
5213 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
5214 (compare:CC
5215 (and:SI (neg:SI
cd2b37d9 5216 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 5217 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
cd2b37d9 5218 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 5219 (const_int 0)))
cd2b37d9 5220 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 5221 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
5222 (clobber (match_scratch:SI 4 "=&r,&r"))]
5223 ""
5224 "@
ca7f5001
RK		 5225 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
5226 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
b19003d8
RK		 5227 [(set_attr "type" "compare")
5228 (set_attr "length" "12")])
1fd4e8c1
RK		 5229
5230(define_insn ""
cd2b37d9
RK		 5231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5232 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 5233 (const_int 0)))]
5234 ""
ca7f5001 5235 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 5236 [(set_attr "length" "12")])
1fd4e8c1
RK		 5237
5238(define_insn ""
5239 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
5240 (compare:CC
cd2b37d9 5241 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 5242 (const_int 0))
5243 (const_int 0)))
cd2b37d9 5244 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 5245 (gt:SI (match_dup 1) (const_int 0)))]
5246 ""
ca7f5001 5247 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"
b19003d8
RK		 5248 [(set_attr "type" "delayed_compare")
5249 (set_attr "length" "12")])
1fd4e8c1
RK		 5250
5251(define_insn ""
cd2b37d9
RK		 5252 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5253 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5254 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 5255 "TARGET_POWER"
5256 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 5257 [(set_attr "length" "12")])
1fd4e8c1
RK		 5258
5259(define_insn ""
5260 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5261 (compare:CC
cd2b37d9 5262 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 5263 (match_operand:SI 2 "reg_or_short_operand" "r"))
5264 (const_int 0)))
cd2b37d9 5265 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 5266 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001
RK		 5267 "TARGET_POWER"
5268 "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
b19003d8
RK		 5269 [(set_attr "type" "delayed_compare")
5270 (set_attr "length" "12")])
1fd4e8c1
RK		 5271
5272(define_insn ""
cd2b37d9
RK		 5273 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5274 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5275 (const_int 0))
cd2b37d9 5276 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1
RK		 5277 (clobber (match_scratch:SI 3 "=&r"))]
5278 ""
ca7f5001 5279 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
b19003d8 5280 [(set_attr "length" "12")])
1fd4e8c1
RK		 5281
5282(define_insn ""
5283 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5284 (compare:CC
cd2b37d9 5285 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5286 (const_int 0))
cd2b37d9 5287 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 5288 (const_int 0)))
5289 (clobber (match_scratch:SI 3 "=&r"))]
5290 ""
ca7f5001 5291 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
b19003d8
RK		 5292 [(set_attr "type" "compare")
5293 (set_attr "length" "12")])
1fd4e8c1
RK		 5294
5295(define_insn ""
5296 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
5297 (compare:CC
cd2b37d9 5298 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5299 (const_int 0))
cd2b37d9 5300 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 5301 (const_int 0)))
cd2b37d9 5302 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 5303 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
5304 (clobber (match_scratch:SI 3 "=&r"))]
5305 ""
ca7f5001 5306 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
b19003d8
RK		 5307 [(set_attr "type" "compare")
5308 (set_attr "length" "12")])
1fd4e8c1
RK		 5309
5310(define_insn ""
cd2b37d9
RK		 5311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5312 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5313 (match_operand:SI 2 "reg_or_short_operand" "r"))
cd2b37d9 5314 (match_operand:SI 3 "gpc_reg_operand" "r")))
1fd4e8c1 5315 (clobber (match_scratch:SI 4 "=&r"))]
ca7f5001
RK		 5316 "TARGET_POWER"
5317 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
b19003d8 5318 [(set_attr "length" "12")])
1fd4e8c1
RK		 5319
5320(define_insn ""
5321 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5322 (compare:CC
cd2b37d9 5323 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5324 (match_operand:SI 2 "reg_or_short_operand" "r"))
cd2b37d9 5325 (match_operand:SI 3 "gpc_reg_operand" "r"))
1fd4e8c1
RK		 5326 (const_int 0)))
5327 (clobber (match_scratch:SI 4 "=&r"))]
ca7f5001
RK		 5328 "TARGET_POWER"
5329 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
b19003d8
RK		 5330 [(set_attr "type" "compare")
5331 (set_attr "length" "12")])
1fd4e8c1
RK		 5332
5333(define_insn ""
5334 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
5335 (compare:CC
cd2b37d9 5336 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5337 (match_operand:SI 2 "reg_or_short_operand" "r"))
cd2b37d9 5338 (match_operand:SI 3 "gpc_reg_operand" "r"))
1fd4e8c1 5339 (const_int 0)))
cd2b37d9 5340 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 5341 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5342 (clobber (match_scratch:SI 4 "=&r"))]
ca7f5001
RK		 5343 "TARGET_POWER"
5344 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
b19003d8
RK		 5345 [(set_attr "type" "compare")
5346 (set_attr "length" "12")])
1fd4e8c1
RK		 5347
5348(define_insn ""
cd2b37d9
RK		 5349 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5350 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 5351 (const_int 0))))]
5352 ""
ca7f5001 5353 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 5354 [(set_attr "length" "12")])
1fd4e8c1
RK		 5355
5356(define_insn ""
cd2b37d9
RK		 5357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5358 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 5359 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 5360 "TARGET_POWER"
5361 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 5362 [(set_attr "length" "12")])
1fd4e8c1
RK		 5363
5364(define_insn ""
cd2b37d9
RK		 5365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5366 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 5367 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
5368 ""
ca7f5001 5369 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
b19003d8 5370 [(set_attr "length" "12")])
1fd4e8c1
RK		 5371
5372(define_insn ""
5373 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5374 (compare:CC
cd2b37d9 5375 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 5376 (match_operand:SI 2 "reg_or_short_operand" "rI"))
5377 (const_int 0)))
cd2b37d9 5378 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 5379 (gtu:SI (match_dup 1) (match_dup 2)))]
5380 ""
ca7f5001 5381 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
b19003d8
RK		 5382 [(set_attr "type" "compare")
5383 (set_attr "length" "12")])
1fd4e8c1
RK		 5384
5385(define_insn ""
00751805
RK		 5386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5387 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5388 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
5389 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
5390 (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
1fd4e8c1 5391 ""
00751805 5392 "@
ca7f5001
RK		 5393 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
5394 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
5395 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
b19003d8 5396 [(set_attr "length" "8,12,12")])
1fd4e8c1
RK		 5397
5398(define_insn ""
3d91674b 5399 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1fd4e8c1 5400 (compare:CC
3d91674b
RK		 5401 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5402 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
5403 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 5404 (const_int 0)))
3d91674b 5405 (clobber (match_scratch:SI 4 "=&r,&r"))]
1fd4e8c1 5406 ""
00751805 5407 "@
ca7f5001
RK		 5408 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
5409 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
b19003d8 5410 [(set_attr "type" "compare")
3d91674b 5411 (set_attr "length" "8,12")])
1fd4e8c1
RK		 5412
5413(define_insn ""
3d91674b 5414 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
1fd4e8c1 5415 (compare:CC
3d91674b
RK		 5416 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5417 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
5418 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 5419 (const_int 0)))
3d91674b 5420 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 5421 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3d91674b 5422 (clobber (match_scratch:SI 4 "=&r,&r"))]
1fd4e8c1 5423 ""
00751805 5424 "@
ca7f5001
RK		 5425 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
5426 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
b19003d8 5427 [(set_attr "type" "compare")
3d91674b 5428 (set_attr "length" "8,12")])
1fd4e8c1
RK		 5429
5430(define_insn ""
cd2b37d9
RK		 5431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5432 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 5433 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
5434 ""
ca7f5001 5435 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
b19003d8 5436 [(set_attr "length" "8")])
1fd4e8c1
RK		 5437\f
5438;; Define both directions of branch and return. If we need a reload
5439;; register, we'd rather use CR0 since it is much easier to copy a
5440;; register CC value to there.
5441
5442(define_insn ""
5443 [(set (pc)
5444 (if_then_else (match_operator 1 "branch_comparison_operator"
5445 [(match_operand 2
5446 "cc_reg_operand" "x,?y")
5447 (const_int 0)])
5448 (label_ref (match_operand 0 "" ""))
5449 (pc)))]
5450 ""
b19003d8
RK		 5451 "*
5452{
5453 if (get_attr_length (insn) == 8)
5454 return \"%C1bc %t1,%j1,%l0\";
5455 else
5456 return \"%C1bc %T1,%j1,$+8\;b %l0\";
5457}"
5458 [(set_attr "type" "branch")])
5459
1fd4e8c1
RK		 5460
5461(define_insn ""
5462 [(set (pc)
5463 (if_then_else (match_operator 0 "branch_comparison_operator"
5464 [(match_operand 1
5465 "cc_reg_operand" "x,?y")
5466 (const_int 0)])
5467 (return)
5468 (pc)))]
5469 "direct_return ()"
ca7f5001 5470 "{%C0bcr|%C0bclr} %t0,%j0"
b19003d8 5471 [(set_attr "length" "8")])
1fd4e8c1
RK		 5472
5473(define_insn ""
5474 [(set (pc)
5475 (if_then_else (match_operator 1 "branch_comparison_operator"
5476 [(match_operand 2
5477 "cc_reg_operand" "x,?y")
5478 (const_int 0)])
5479 (pc)
5480 (label_ref (match_operand 0 "" ""))))]
5481 ""
b19003d8
RK		 5482 "*
5483{
5484 if (get_attr_length (insn) == 8)
5485 return \"%C1bc %T1,%j1,%l0\";
5486 else
5487 return \"%C1bc %t1,%j1,$+8\;b %l0\";
5488}"
5489 [(set_attr "type" "branch")])
1fd4e8c1
RK		 5490
5491(define_insn ""
5492 [(set (pc)
5493 (if_then_else (match_operator 0 "branch_comparison_operator"
5494 [(match_operand 1
5495 "cc_reg_operand" "x,?y")
5496 (const_int 0)])
5497 (pc)
5498 (return)))]
5499 "direct_return ()"
ca7f5001 5500 "{%C0bcr|%C0bclr} %T0,%j0"
b19003d8 5501 [(set_attr "length" "8")])
1fd4e8c1
RK		 5502
5503;; Unconditional branch and return.
5504
5505(define_insn "jump"
5506 [(set (pc)
5507 (label_ref (match_operand 0 "" "")))]
5508 ""
5509 "b %l0")
5510
5511(define_insn "return"
5512 [(return)]
5513 "direct_return ()"
324e52cc
TG		 5514 "{br|blr}"
5515 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 5516
5517(define_insn "indirect_jump"
5518 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
5519 ""
5520 "@
5521 bctr
324e52cc
TG		 5522 {br|blr}"
5523 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 5524
5525;; Table jump for switch statements:
5526(define_expand "tablejump"
5527 [(set (match_dup 3)
5528 (plus:SI (match_operand:SI 0 "" "")
5529 (match_dup 2)))
5530 (parallel [(set (pc) (match_dup 3))
5531 (use (label_ref (match_operand 1 "" "")))])]
5532 ""
5533 "
5534{ operands[0] = force_reg (SImode, operands[0]);
5535 operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
5536 operands[3] = gen_reg_rtx (SImode);
5537}")
5538
5539(define_insn ""
5540 [(set (pc)
740ab4a2 5541 (match_operand:SI 0 "register_operand" "c,l"))
1fd4e8c1
RK		 5542 (use (label_ref (match_operand 1 "" "")))]
5543 ""
5544 "@
5545 bctr
ca7f5001 5546 {br|blr}")
1fd4e8c1
RK		 5547
5548(define_insn "nop"
5549 [(const_int 0)]
5550 ""
ca7f5001 5551 "{cror 0,0,0|nop}")
1fd4e8c1 5552\f
c225ba7b
RK		 5553;; Define the subtract-one-and-jump insns, starting with the template
5554;; so loop.c knows what to generate.
5555
5556(define_expand "decrement_and_branchsi"
5557 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "c")
5558 (const_int 1))
5559 (label_ref (match_operand 1 "" ""))
5560 (pc)))
5561 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])]
5562 ""
5563 "")
5564
1fd4e8c1
RK		 5565;; We need to be able to do this for any operand, including MEM, or we
5566;; will cause reload to blow up since we don't allow output reloads on
5567;; JUMP_INSNs.
5568(define_insn ""
5569 [(set (pc)
5570 (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
5571 (const_int 1))
5572 (label_ref (match_operand 2 "" ""))
5573 (pc)))
5574 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
5575 (plus:SI (match_dup 1) (const_int -1)))
5576 (clobber (match_scratch:CC 3 "=X,&x,&x"))
5577 (clobber (match_scratch:SI 4 "=X,X,r"))]
5578 ""
b19003d8
RK		 5579 "*
5580{
af87a13e 5581 if (which_alternative != 0)
b19003d8
RK		 5582 return \"#\";
5583 else if (get_attr_length (insn) == 8)
ca7f5001 5584 return \"{bdn|bdnz} %l2\";
b19003d8
RK		 5585 else
5586 return \"bdz $+8\;b %l2\";
5587}"
baf97f86
RK		 5588 [(set_attr "type" "branch")
5589 (set_attr "length" "*,12,16")])
1fd4e8c1 5590
c225ba7b 5591;; Similar, but we can use GE since we have a REG_NONNEG.
1fd4e8c1
RK		 5592(define_insn ""
5593 [(set (pc)
5594 (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
5595 (const_int 0))
5596 (label_ref (match_operand 2 "" ""))
5597 (pc)))
5598 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
5599 (plus:SI (match_dup 1) (const_int -1)))
5600 (clobber (match_scratch:CC 3 "=X,&x,&X"))
5601 (clobber (match_scratch:SI 4 "=X,X,r"))]
5602 "find_reg_note (insn, REG_NONNEG, 0)"
b19003d8
RK		 5603 "*
5604{
af87a13e 5605 if (which_alternative != 0)
b19003d8
RK		 5606 return \"#\";
5607 else if (get_attr_length (insn) == 8)
ca7f5001 5608 return \"{bdn|bdnz} %l2\";
b19003d8
RK		 5609 else
5610 return \"bdz $+8\;b %l2\";
5611}"
baf97f86
RK		 5612 [(set_attr "type" "branch")
5613 (set_attr "length" "*,12,16")])
1fd4e8c1
RK		 5614
5615(define_insn ""
5616 [(set (pc)
5617 (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
5618 (const_int 1))
5619 (label_ref (match_operand 2 "" ""))
5620 (pc)))
5621 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
5622 (plus:SI (match_dup 1) (const_int -1)))
5623 (clobber (match_scratch:CC 3 "=X,&x,&x"))
5624 (clobber (match_scratch:SI 4 "=X,X,r"))]
5625 ""
b19003d8
RK		 5626 "*
5627{
af87a13e 5628 if (which_alternative != 0)
b19003d8
RK		 5629 return \"#\";
5630 else if (get_attr_length (insn) == 8)
5631 return \"bdz %l2\";
5632 else
ca7f5001 5633 return \"{bdn|bdnz} $+8\;b %l2\";
b19003d8 5634}"
baf97f86
RK		 5635 [(set_attr "type" "branch")
5636 (set_attr "length" "*,12,16")])
1fd4e8c1
RK		 5637
5638(define_split
5639 [(set (pc)
5640 (if_then_else (match_operator 2 "comparison_operator"
cd2b37d9 5641 [(match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 5642 (const_int 1)])
5643 (match_operand 5 "" "")
5644 (match_operand 6 "" "")))
cd2b37d9 5645 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 5646 (plus:SI (match_dup 1) (const_int -1)))
5647 (clobber (match_scratch:CC 3 ""))
5648 (clobber (match_scratch:SI 4 ""))]
5649 "reload_completed"
5650 [(parallel [(set (match_dup 3)
5651 (compare:CC (plus:SI (match_dup 1) (const_int -1))
5652 (const_int 0)))
5653 (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
5654 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
5655 "
5656{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
5657 const0_rtx); }")
5658
5659(define_split
5660 [(set (pc)
5661 (if_then_else (match_operator 2 "comparison_operator"
cd2b37d9 5662 [(match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 5663 (const_int 1)])
5664 (match_operand 5 "" "")
5665 (match_operand 6 "" "")))
5666 (set (match_operand:SI 0 "general_operand" "")
5667 (plus:SI (match_dup 1) (const_int -1)))
5668 (clobber (match_scratch:CC 3 ""))
5669 (clobber (match_scratch:SI 4 ""))]
cd2b37d9 5670 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
1fd4e8c1
RK		 5671 [(parallel [(set (match_dup 3)
5672 (compare:CC (plus:SI (match_dup 1) (const_int -1))
5673 (const_int 0)))
5674 (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
5675 (set (match_dup 0) (match_dup 4))
5676 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
5677 "
5678{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
5679 const0_rtx); }")
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