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996a5f59 RK |
1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994 Free Software Foundation, Inc. | |
3 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) | |
1fd4e8c1 RK |
4 | |
5 | ;; This file is part of GNU CC. | |
6 | ||
7 | ;; GNU CC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 2, or (at your option) | |
10 | ;; any later version. | |
11 | ||
12 | ;; GNU CC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GNU CC; see the file COPYING. If not, write to | |
19 | ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | ||
21 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
22 | \f | |
23 | ;; Define an insn type attribute. This is used in function unit delay | |
24 | ;; computations. | |
324e52cc | 25 | (define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" |
1fd4e8c1 RK |
26 | (const_string "integer")) |
27 | ||
b19003d8 RK |
28 | ;; Length (in bytes). |
29 | (define_attr "length" "" | |
30 | (if_then_else (eq_attr "type" "branch") | |
31 | (if_then_else (and (ge (minus (pc) (match_dup 0)) | |
32 | (const_int -32768)) | |
33 | (lt (minus (pc) (match_dup 0)) | |
34 | (const_int 32767))) | |
35 | (const_int 8) | |
36 | (const_int 12)) | |
37 | (const_int 4))) | |
38 | ||
cfb557c4 RK |
39 | ;; Processor type -- this attribute must exactly match the processor_type |
40 | ;; enumeration in rs6000.h. | |
41 | ||
2661cdd9 | 42 | (define_attr "cpu" "rios1,rios2,ppc601,ppc603,ppc604,ppc620" |
cfb557c4 RK |
43 | (const (symbol_ref "rs6000_cpu_attr"))) |
44 | ||
45 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
46 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
47 | ||
51b8fc2c RK |
48 | ; Load/Store Unit -- POWER/2 and pure PowerPC only |
49 | ; (POWER and 601 use Integer Unit) | |
cfb557c4 RK |
50 | (define_function_unit "lsu" 1 0 |
51 | (and (eq_attr "type" "load") | |
98c131c3 | 52 | (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620")) |
cfb557c4 RK |
53 | 2 0) |
54 | ||
55 | (define_function_unit "lsu" 1 0 | |
56 | (and (eq_attr "type" "fpload") | |
98c131c3 | 57 | (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620")) |
cfb557c4 RK |
58 | 2 0) |
59 | ||
60 | (define_function_unit "iu" 1 0 | |
61 | (and (eq_attr "type" "load") | |
3624a679 | 62 | (eq_attr "cpu" "rios1,ppc601")) |
cfb557c4 RK |
63 | 2 0) |
64 | ||
65 | (define_function_unit "iu" 1 0 | |
66 | (and (eq_attr "type" "fpload") | |
3624a679 | 67 | (eq_attr "cpu" "rios1,ppc601")) |
cfb557c4 RK |
68 | 3 0) |
69 | ||
51b8fc2c RK |
70 | ; Integer Unit (RIOS1, PPC601, PPC603) |
71 | ; Trivial operations take one cycle which need not be listed here. | |
cfb557c4 RK |
72 | (define_function_unit "iu" 1 0 |
73 | (and (eq_attr "type" "imul") | |
ca7f5001 | 74 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 75 | 3 3) |
cfb557c4 RK |
76 | |
77 | (define_function_unit "iu" 1 0 | |
78 | (and (eq_attr "type" "imul") | |
51b8fc2c RK |
79 | (eq_attr "cpu" "ppc601,ppc603")) |
80 | 5 5) | |
cfb557c4 RK |
81 | |
82 | (define_function_unit "iu" 1 0 | |
83 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 84 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 85 | 19 19) |
cfb557c4 RK |
86 | |
87 | (define_function_unit "iu" 1 0 | |
88 | (and (eq_attr "type" "idiv") | |
51b8fc2c RK |
89 | (eq_attr "cpu" "ppc601")) |
90 | 36 36) | |
91 | ||
92 | (define_function_unit "iu" 1 0 | |
93 | (and (eq_attr "type" "idiv") | |
94 | (eq_attr "cpu" "ppc603")) | |
95 | 37 36) | |
96 | ||
97 | ; RIOS2 has two integer units: a primary one which can perform all | |
98 | ; operations and a secondary one which is fed in lock step with the first | |
99 | ; and can perform "simple" integer operations. | |
100 | (define_function_unit "iu2" 2 0 | |
101 | (and (eq_attr "type" "integer") | |
102 | (eq_attr "cpu" "rios2")) | |
103 | 1 0 | |
104 | [(eq_attr "type" "imul,idiv")]) | |
105 | ||
106 | (define_function_unit "imuldiv" 1 0 | |
107 | (and (eq_attr "type" "imul") | |
108 | (eq_attr "cpu" "rios2")) | |
109 | 2 2 | |
110 | [(eq_attr "type" "integer")]) | |
111 | ||
112 | (define_function_unit "imuldiv" 1 0 | |
113 | (and (eq_attr "type" "idiv") | |
114 | (eq_attr "cpu" "rios2")) | |
115 | 13 13 | |
116 | [(eq_attr "type" "integer")]) | |
117 | ||
118 | ; PPC604 has three integer units: one primary and two secondary. | |
119 | (define_function_unit "iu3" 3 0 | |
120 | (and (eq_attr "type" "integer") | |
121 | (eq_attr "cpu" "ppc604,ppc620")) | |
122 | 1 0 | |
123 | [(eq_attr "type" "imul,idiv")]) | |
124 | ||
125 | (define_function_unit "imuldiv" 1 0 | |
126 | (and (eq_attr "type" "imul") | |
127 | (eq_attr "cpu" "ppc604,ppc620")) | |
128 | 4 2 | |
129 | [(eq_attr "type" "integer")]) | |
130 | ||
131 | (define_function_unit "imuldiv" 1 0 | |
132 | (and (eq_attr "type" "idiv") | |
133 | (eq_attr "cpu" "ppc604,ppc620")) | |
134 | 20 19 | |
135 | [(eq_attr "type" "integer")]) | |
cfb557c4 | 136 | |
51b8fc2c | 137 | ; Branch Processing Unit |
cfb557c4 RK |
138 | (define_function_unit "bpu" 1 0 |
139 | (eq_attr "type" "compare") | |
140 | 4 0) | |
141 | ||
142 | (define_function_unit "bpu" 1 0 | |
143 | (eq_attr "type" "delayed_compare") | |
144 | 5 0) | |
145 | ||
146 | (define_function_unit "bpu" 1 0 | |
147 | (and (eq_attr "type" "fpcompare") | |
2661cdd9 | 148 | (eq_attr "cpu" "rios1,rios2")) |
cfb557c4 RK |
149 | 8 0) |
150 | ||
151 | (define_function_unit "bpu" 1 0 | |
152 | (and (eq_attr "type" "fpcompare") | |
153 | (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) | |
154 | 4 0) | |
155 | ||
156 | (define_function_unit "bpu" 1 0 | |
324e52cc | 157 | (and (eq_attr "type" "mtjmpr") |
2661cdd9 | 158 | (eq_attr "cpu" "rios1,rios2")) |
cfb557c4 RK |
159 | 5 0) |
160 | ||
161 | (define_function_unit "bpu" 1 0 | |
324e52cc | 162 | (and (eq_attr "type" "mtjmpr") |
cfb557c4 RK |
163 | (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) |
164 | 4 0) | |
165 | ||
51b8fc2c | 166 | ; Floating Point Unit (RIOS1, PPC601, PPC603, PPC604). |
cfb557c4 | 167 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 168 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 169 | (eq_attr "cpu" "rios1")) |
cfb557c4 RK |
170 | 2 0) |
171 | ||
172 | (define_function_unit "fpu" 1 0 | |
173 | (and (eq_attr "type" "fp") | |
51b8fc2c | 174 | (eq_attr "cpu" "ppc601")) |
cfb557c4 RK |
175 | 4 0) |
176 | ||
51b8fc2c RK |
177 | (define_function_unit "fpu" 1 0 |
178 | (and (eq_attr "type" "fp") | |
179 | (eq_attr "cpu" "ppc603,ppc604,ppc620")) | |
180 | 3 0) | |
181 | ||
cfb557c4 RK |
182 | (define_function_unit "fpu" 1 0 |
183 | (and (eq_attr "type" "dmul") | |
51b8fc2c RK |
184 | (eq_attr "cpu" "ppc601")) |
185 | 5 5) | |
cfb557c4 RK |
186 | |
187 | (define_function_unit "fpu" 1 0 | |
188 | (and (eq_attr "type" "dmul") | |
51b8fc2c RK |
189 | (eq_attr "cpu" "ppc603")) |
190 | 4 2) | |
cfb557c4 RK |
191 | |
192 | (define_function_unit "fpu" 1 0 | |
51b8fc2c RK |
193 | (and (eq_attr "type" "dmul") |
194 | (eq_attr "cpu" "ppc604,ppc620")) | |
195 | 3 0) | |
196 | ||
197 | (define_function_unit "fpu" 1 0 | |
198 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 199 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 200 | 19 19) |
cfb557c4 RK |
201 | |
202 | (define_function_unit "fpu" 1 0 | |
203 | (and (eq_attr "type" "sdiv") | |
51b8fc2c RK |
204 | (eq_attr "cpu" "ppc601")) |
205 | 17 17) | |
206 | ||
207 | (define_function_unit "fpu" 1 0 | |
208 | (and (eq_attr "type" "sdiv") | |
209 | (eq_attr "cpu" "ppc603,ppc604,ppc620")) | |
210 | 18 18) | |
cfb557c4 RK |
211 | |
212 | (define_function_unit "fpu" 1 0 | |
213 | (and (eq_attr "type" "ddiv") | |
51b8fc2c RK |
214 | (eq_attr "cpu" "ppc601,ppc604,ppc620")) |
215 | 31 31) | |
cfb557c4 RK |
216 | |
217 | (define_function_unit "fpu" 1 0 | |
218 | (and (eq_attr "type" "ddiv") | |
51b8fc2c RK |
219 | (eq_attr "cpu" "ppc603")) |
220 | 33 33) | |
cfb557c4 RK |
221 | |
222 | (define_function_unit "fpu" 1 0 | |
223 | (and (eq_attr "type" "ssqrt") | |
a473029f | 224 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 225 | 31 31) |
cfb557c4 RK |
226 | |
227 | (define_function_unit "fpu" 1 0 | |
228 | (and (eq_attr "type" "dsqrt") | |
a473029f | 229 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 230 | 31 31) |
b73d04f2 | 231 | |
51b8fc2c | 232 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 RK |
233 | (define_function_unit "fpu2" 2 0 |
234 | (and (eq_attr "type" "fp") | |
4652f1d4 | 235 | (eq_attr "cpu" "rios2")) |
cfb557c4 RK |
236 | 2 0) |
237 | ||
238 | (define_function_unit "fpu2" 2 0 | |
239 | (and (eq_attr "type" "dmul") | |
240 | (eq_attr "cpu" "rios2")) | |
241 | 2 0) | |
242 | ||
243 | (define_function_unit "fpu2" 2 0 | |
51b8fc2c | 244 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 245 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 246 | 17 17) |
ca7f5001 RK |
247 | |
248 | (define_function_unit "fpu2" 2 0 | |
51b8fc2c | 249 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 250 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 251 | 26 26) |
1fd4e8c1 RK |
252 | \f |
253 | ;; Start with fixed-point load and store insns. Here we put only the more | |
254 | ;; complex forms. Basic data transfer is done later. | |
255 | ||
51b8fc2c RK |
256 | (define_expand "zero_extendqidi2" |
257 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
258 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
259 | "TARGET_POWERPC64" | |
260 | "") | |
261 | ||
262 | (define_insn "" | |
263 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
264 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
265 | "TARGET_POWERPC64" | |
266 | "@ | |
267 | lbz%U1%X1 %0,%1 | |
4371f8af | 268 | rldicl %0,%1,0,56" |
51b8fc2c RK |
269 | [(set_attr "type" "load,*")]) |
270 | ||
271 | (define_insn "" | |
272 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
273 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
274 | (const_int 0))) | |
275 | (clobber (match_scratch:DI 2 "=r"))] | |
58e09803 | 276 | "TARGET_POWERPC64" |
4371f8af | 277 | "rldicl. %2,%1,0,56" |
51b8fc2c RK |
278 | [(set_attr "type" "compare")]) |
279 | ||
280 | (define_insn "" | |
281 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
282 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
283 | (const_int 0))) | |
284 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
285 | (zero_extend:DI (match_dup 1)))] | |
58e09803 | 286 | "TARGET_POWERPC64" |
4371f8af | 287 | "rldicl. %0,%1,0,56" |
51b8fc2c RK |
288 | [(set_attr "type" "compare")]) |
289 | ||
2bee0449 RK |
290 | (define_insn "extendqidi2" |
291 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
292 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 293 | "TARGET_POWERPC64" |
2bee0449 | 294 | "extsb %0,%1") |
51b8fc2c RK |
295 | |
296 | (define_insn "" | |
297 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
298 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
299 | (const_int 0))) | |
300 | (clobber (match_scratch:DI 2 "=r"))] | |
301 | "TARGET_POWERPC64" | |
302 | "extsb. %2,%1" | |
303 | [(set_attr "type" "compare")]) | |
304 | ||
305 | (define_insn "" | |
306 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
307 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
308 | (const_int 0))) | |
309 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
310 | (sign_extend:DI (match_dup 1)))] | |
311 | "TARGET_POWERPC64" | |
312 | "extsb. %0,%1" | |
313 | [(set_attr "type" "compare")]) | |
314 | ||
315 | (define_expand "zero_extendhidi2" | |
316 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
317 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
318 | "TARGET_POWERPC64" | |
319 | "") | |
320 | ||
321 | (define_insn "" | |
322 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
323 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
324 | "TARGET_POWERPC64" | |
325 | "@ | |
326 | lhz%U1%X1 %0,%1 | |
4371f8af | 327 | rldicl %0,%1,0,48" |
51b8fc2c RK |
328 | [(set_attr "type" "load,*")]) |
329 | ||
330 | (define_insn "" | |
331 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
332 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
333 | (const_int 0))) | |
334 | (clobber (match_scratch:DI 2 "=r"))] | |
335 | "TARGET_POWERPC64" | |
4371f8af | 336 | "rldicl. %2,%1,0,48" |
51b8fc2c RK |
337 | [(set_attr "type" "compare")]) |
338 | ||
339 | (define_insn "" | |
340 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
341 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
342 | (const_int 0))) | |
343 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
344 | (zero_extend:DI (match_dup 1)))] | |
345 | "TARGET_POWERPC64" | |
4371f8af | 346 | "rldicl. %0,%1,0,48" |
51b8fc2c RK |
347 | [(set_attr "type" "compare")]) |
348 | ||
349 | (define_expand "extendhidi2" | |
350 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
351 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
352 | "TARGET_POWERPC64" | |
353 | "") | |
354 | ||
355 | (define_insn "" | |
356 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
357 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
358 | "TARGET_POWERPC64" | |
359 | "@ | |
360 | lha%U1%X1 %0,%1 | |
361 | extsh %0,%1" | |
362 | [(set_attr "type" "load,*")]) | |
363 | ||
364 | (define_insn "" | |
365 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
366 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
367 | (const_int 0))) | |
368 | (clobber (match_scratch:DI 2 "=r"))] | |
369 | "TARGET_POWERPC64" | |
370 | "extsh. %2,%1" | |
371 | [(set_attr "type" "compare")]) | |
372 | ||
373 | (define_insn "" | |
374 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
375 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
376 | (const_int 0))) | |
377 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
378 | (sign_extend:DI (match_dup 1)))] | |
379 | "TARGET_POWERPC64" | |
380 | "extsh. %0,%1" | |
381 | [(set_attr "type" "compare")]) | |
382 | ||
383 | (define_expand "zero_extendsidi2" | |
384 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
385 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
386 | "TARGET_POWERPC64" | |
387 | "") | |
388 | ||
389 | (define_insn "" | |
390 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
391 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
392 | "TARGET_POWERPC64" | |
393 | "@ | |
394 | lwz%U1%X1 %0,%1 | |
395 | rldicl %0,%1,0,32" | |
396 | [(set_attr "type" "load,*")]) | |
397 | ||
398 | (define_insn "" | |
399 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
400 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
401 | (const_int 0))) | |
402 | (clobber (match_scratch:DI 2 "=r"))] | |
403 | "TARGET_POWERPC64" | |
404 | "rldicl. %2,%1,0,32" | |
405 | [(set_attr "type" "compare")]) | |
406 | ||
407 | (define_insn "" | |
408 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
409 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
410 | (const_int 0))) | |
411 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
412 | (zero_extend:DI (match_dup 1)))] | |
413 | "TARGET_POWERPC64" | |
414 | "rldicl. %0,%1,0,32" | |
415 | [(set_attr "type" "compare")]) | |
416 | ||
417 | (define_expand "extendsidi2" | |
418 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
419 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
420 | "TARGET_POWERPC64" | |
421 | "") | |
422 | ||
423 | (define_insn "" | |
424 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
425 | (sign_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
426 | "TARGET_POWERPC64" | |
427 | "@ | |
428 | lwa%U1%X1 %0,%1 | |
429 | extsw %0,%1" | |
430 | [(set_attr "type" "load,*")]) | |
431 | ||
432 | (define_insn "" | |
433 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
434 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
435 | (const_int 0))) | |
436 | (clobber (match_scratch:DI 2 "=r"))] | |
437 | "TARGET_POWERPC64" | |
438 | "extsw. %2,%1" | |
439 | [(set_attr "type" "compare")]) | |
440 | ||
441 | (define_insn "" | |
442 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
443 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
444 | (const_int 0))) | |
445 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
446 | (sign_extend:DI (match_dup 1)))] | |
447 | "TARGET_POWERPC64" | |
448 | "extsw. %0,%1" | |
449 | [(set_attr "type" "compare")]) | |
450 | ||
1fd4e8c1 | 451 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
452 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
453 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
454 | "" |
455 | "") | |
456 | ||
457 | (define_insn "" | |
cd2b37d9 | 458 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
459 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
460 | "" | |
461 | "@ | |
462 | lbz%U1%X1 %0,%1 | |
005a35b9 | 463 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
464 | [(set_attr "type" "load,*")]) |
465 | ||
466 | (define_insn "" | |
467 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 468 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
469 | (const_int 0))) |
470 | (clobber (match_scratch:SI 2 "=r"))] | |
471 | "" | |
ca7f5001 | 472 | "{andil.|andi.} %2,%1,0xff" |
1fd4e8c1 RK |
473 | [(set_attr "type" "compare")]) |
474 | ||
475 | (define_insn "" | |
476 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
cd2b37d9 | 477 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 478 | (const_int 0))) |
cd2b37d9 | 479 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
480 | (zero_extend:SI (match_dup 1)))] |
481 | "" | |
ca7f5001 | 482 | "{andil.|andi.} %0,%1,0xff" |
1fd4e8c1 RK |
483 | [(set_attr "type" "compare")]) |
484 | ||
51b8fc2c RK |
485 | (define_expand "extendqisi2" |
486 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
487 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
488 | "" | |
489 | " | |
490 | { | |
491 | if (TARGET_POWERPC) | |
492 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
493 | else if (TARGET_POWER) | |
494 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
495 | else | |
496 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
497 | DONE; | |
498 | }") | |
499 | ||
500 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
501 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
502 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 503 | "TARGET_POWERPC" |
2bee0449 | 504 | "extsb %0,%1") |
51b8fc2c RK |
505 | |
506 | (define_insn "" | |
507 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
508 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
509 | (const_int 0))) | |
510 | (clobber (match_scratch:SI 2 "=r"))] | |
511 | "TARGET_POWERPC" | |
512 | "extsb. %2,%1" | |
513 | [(set_attr "type" "compare")]) | |
514 | ||
515 | (define_insn "" | |
516 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
517 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
518 | (const_int 0))) | |
519 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
520 | (sign_extend:SI (match_dup 1)))] | |
521 | "TARGET_POWERPC" | |
522 | "extsb. %0,%1" | |
523 | [(set_attr "type" "compare")]) | |
524 | ||
525 | (define_expand "extendqisi2_power" | |
526 | [(parallel [(set (match_dup 2) | |
527 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
528 | (const_int 24))) | |
529 | (clobber (scratch:SI))]) | |
530 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
531 | (ashiftrt:SI (match_dup 2) | |
532 | (const_int 24))) | |
533 | (clobber (scratch:SI))])] | |
534 | "TARGET_POWER" | |
535 | " | |
536 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
537 | operands[2] = gen_reg_rtx (SImode); }") | |
538 | ||
539 | (define_expand "extendqisi2_no_power" | |
540 | [(set (match_dup 2) | |
541 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
542 | (const_int 24))) | |
543 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
544 | (ashiftrt:SI (match_dup 2) | |
545 | (const_int 24)))] | |
546 | "! TARGET_POWER && ! TARGET_POWERPC" | |
547 | " | |
548 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
549 | operands[2] = gen_reg_rtx (SImode); }") | |
550 | ||
1fd4e8c1 | 551 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
552 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
553 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
554 | "" |
555 | "") | |
556 | ||
557 | (define_insn "" | |
cd2b37d9 | 558 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
559 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
560 | "" | |
561 | "@ | |
562 | lbz%U1%X1 %0,%1 | |
005a35b9 | 563 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
564 | [(set_attr "type" "load,*")]) |
565 | ||
566 | (define_insn "" | |
567 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
568 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
569 | (const_int 0))) | |
570 | (clobber (match_scratch:HI 2 "=r"))] | |
571 | "" | |
572 | "{andil.|andi.} %2,%1,0xff" | |
573 | [(set_attr "type" "compare")]) | |
574 | ||
575 | (define_insn "" | |
576 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
577 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
578 | (const_int 0))) | |
579 | (set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
580 | (zero_extend:HI (match_dup 1)))] | |
581 | "" | |
582 | "{andil.|andi.} %0,%1,0xff" | |
583 | [(set_attr "type" "compare")]) | |
584 | ||
585 | (define_expand "extendqihi2" | |
586 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
587 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
588 | "" | |
589 | " | |
590 | { | |
591 | if (TARGET_POWERPC) | |
592 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
593 | else if (TARGET_POWER) | |
594 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
595 | else | |
596 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
597 | DONE; | |
598 | }") | |
599 | ||
600 | (define_insn "extendqihi2_ppc" | |
2bee0449 RK |
601 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") |
602 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 603 | "TARGET_POWERPC" |
2bee0449 | 604 | "extsb %0,%1") |
1fd4e8c1 | 605 | |
51b8fc2c RK |
606 | (define_insn "" |
607 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
608 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
609 | (const_int 0))) | |
610 | (clobber (match_scratch:HI 2 "=r"))] | |
611 | "TARGET_POWERPC" | |
612 | "extsb. %2,%1" | |
613 | [(set_attr "type" "compare")]) | |
614 | ||
615 | (define_insn "" | |
616 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
617 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
618 | (const_int 0))) | |
619 | (set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
620 | (sign_extend:HI (match_dup 1)))] | |
621 | "TARGET_POWERPC" | |
622 | "extsb. %0,%1" | |
623 | [(set_attr "type" "compare")]) | |
624 | ||
625 | (define_expand "extendqihi2_power" | |
626 | [(parallel [(set (match_dup 2) | |
627 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
628 | (const_int 24))) | |
629 | (clobber (scratch:SI))]) | |
630 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
631 | (ashiftrt:SI (match_dup 2) | |
632 | (const_int 24))) | |
633 | (clobber (scratch:SI))])] | |
634 | "TARGET_POWER" | |
635 | " | |
636 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
637 | operands[1] = gen_lowpart (SImode, operands[1]); | |
638 | operands[2] = gen_reg_rtx (SImode); }") | |
639 | ||
640 | (define_expand "extendqihi2_no_power" | |
641 | [(set (match_dup 2) | |
642 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
643 | (const_int 24))) | |
644 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
645 | (ashiftrt:SI (match_dup 2) | |
646 | (const_int 24)))] | |
647 | "! TARGET_POWER && ! TARGET_POWERPC" | |
648 | " | |
649 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
650 | operands[1] = gen_lowpart (SImode, operands[1]); | |
651 | operands[2] = gen_reg_rtx (SImode); }") | |
652 | ||
1fd4e8c1 | 653 | (define_expand "zero_extendhisi2" |
5f243543 | 654 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 655 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
656 | "" |
657 | "") | |
658 | ||
659 | (define_insn "" | |
cd2b37d9 | 660 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
661 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
662 | "" | |
663 | "@ | |
664 | lhz%U1%X1 %0,%1 | |
005a35b9 | 665 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
666 | [(set_attr "type" "load,*")]) |
667 | ||
668 | (define_insn "" | |
669 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 670 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
671 | (const_int 0))) |
672 | (clobber (match_scratch:SI 2 "=r"))] | |
673 | "" | |
ca7f5001 | 674 | "{andil.|andi.} %2,%1,0xffff" |
1fd4e8c1 RK |
675 | [(set_attr "type" "compare")]) |
676 | ||
677 | (define_insn "" | |
678 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
cd2b37d9 | 679 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 680 | (const_int 0))) |
cd2b37d9 | 681 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
682 | (zero_extend:SI (match_dup 1)))] |
683 | "" | |
ca7f5001 | 684 | "{andil.|andi.} %0,%1,0xffff" |
1fd4e8c1 RK |
685 | [(set_attr "type" "compare")]) |
686 | ||
687 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
688 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
689 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
690 | "" |
691 | "") | |
692 | ||
693 | (define_insn "" | |
cd2b37d9 | 694 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
695 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
696 | "" | |
697 | "@ | |
698 | lha%U1%X1 %0,%1 | |
ca7f5001 | 699 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
700 | [(set_attr "type" "load,*")]) |
701 | ||
702 | (define_insn "" | |
703 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 704 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
705 | (const_int 0))) |
706 | (clobber (match_scratch:SI 2 "=r"))] | |
707 | "" | |
ca7f5001 | 708 | "{exts.|extsh.} %2,%1" |
1fd4e8c1 RK |
709 | [(set_attr "type" "compare")]) |
710 | ||
711 | (define_insn "" | |
712 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
cd2b37d9 | 713 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 714 | (const_int 0))) |
cd2b37d9 | 715 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
716 | (sign_extend:SI (match_dup 1)))] |
717 | "" | |
ca7f5001 | 718 | "{exts.|extsh.} %0,%1" |
1fd4e8c1 RK |
719 | [(set_attr "type" "compare")]) |
720 | \f | |
721 | ;; Fixed-point arithmetic insns. | |
deb9225a RK |
722 | |
723 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
724 | ;; allowing register zero as source. | |
f357808b | 725 | (define_insn "addsi3" |
deb9225a RK |
726 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") |
727 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
728 | (match_operand:SI 2 "add_operand" "r,I,I,J")))] | |
1fd4e8c1 RK |
729 | "" |
730 | "@ | |
deb9225a RK |
731 | {cax|add} %0,%1,%2 |
732 | {cal %0,%2(%1)|addi %0,%1,%2} | |
733 | {ai|addic} %0,%1,%2 | |
ca7f5001 | 734 | {cau|addis} %0,%1,%u2") |
1fd4e8c1 RK |
735 | |
736 | (define_insn "" | |
deb9225a RK |
737 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
738 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
739 | (match_operand:SI 2 "reg_or_short_operand" "r,I")) | |
1fd4e8c1 | 740 | (const_int 0))) |
deb9225a | 741 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 742 | "" |
deb9225a RK |
743 | "@ |
744 | {cax.|add.} %3,%1,%2 | |
745 | {ai.|addic.} %3,%1,%2" | |
1fd4e8c1 RK |
746 | [(set_attr "type" "compare")]) |
747 | ||
748 | (define_insn "" | |
deb9225a RK |
749 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
750 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
751 | (match_operand:SI 2 "reg_or_short_operand" "r,I")) | |
1fd4e8c1 | 752 | (const_int 0))) |
deb9225a | 753 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
754 | (plus:SI (match_dup 1) (match_dup 2)))] |
755 | "" | |
deb9225a RK |
756 | "@ |
757 | {cax.|add.} %0,%1,%2 | |
758 | {ai.|addic.} %0,%1,%2" | |
1fd4e8c1 RK |
759 | [(set_attr "type" "compare")]) |
760 | ||
f357808b RK |
761 | ;; Split an add that we can't do in one insn into two insns, each of which |
762 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
763 | ;; add should be last in case the result gets used in an address. | |
764 | ||
765 | (define_split | |
cd2b37d9 RK |
766 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
767 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 768 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 769 | "" |
f357808b RK |
770 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
771 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
772 | " | |
1fd4e8c1 | 773 | { |
f357808b RK |
774 | int low = INTVAL (operands[2]) & 0xffff; |
775 | int high = (unsigned) INTVAL (operands[2]) >> 16; | |
1fd4e8c1 | 776 | |
f357808b RK |
777 | if (low & 0x8000) |
778 | high++, low |= 0xffff0000; | |
1fd4e8c1 | 779 | |
f357808b RK |
780 | operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); |
781 | operands[4] = gen_rtx (CONST_INT, VOIDmode, low); | |
1fd4e8c1 RK |
782 | }") |
783 | ||
8de2a197 | 784 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
785 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
786 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 787 | "" |
ca7f5001 RK |
788 | "nor %0,%1,%1") |
789 | ||
790 | (define_insn "" | |
791 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
792 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
793 | (const_int 0))) | |
794 | (clobber (match_scratch:SI 2 "=r"))] | |
795 | "" | |
796 | "nor. %2,%1,%1" | |
797 | [(set_attr "type" "compare")]) | |
798 | ||
799 | (define_insn "" | |
8de2a197 | 800 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
ca7f5001 RK |
801 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
802 | (const_int 0))) | |
803 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
804 | (not:SI (match_dup 1)))] | |
805 | "" | |
806 | "nor. %0,%2,%1" | |
807 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
808 | |
809 | (define_insn "" | |
3d91674b RK |
810 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
811 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
812 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 813 | "! TARGET_POWERPC" |
ca7f5001 | 814 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 815 | |
deb9225a RK |
816 | (define_insn "" |
817 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
818 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
819 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
820 | "TARGET_POWERPC" | |
821 | "@ | |
822 | subf %0,%2,%1 | |
823 | subfic %0,%2,%1") | |
824 | ||
1fd4e8c1 RK |
825 | (define_insn "" |
826 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
827 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
828 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
829 | (const_int 0))) |
830 | (clobber (match_scratch:SI 3 "=r"))] | |
deb9225a | 831 | "! TARGET_POWERPC" |
ca7f5001 | 832 | "{sf.|subfc.} %3,%2,%1" |
1fd4e8c1 RK |
833 | [(set_attr "type" "compare")]) |
834 | ||
deb9225a RK |
835 | (define_insn "" |
836 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
837 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
838 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
839 | (const_int 0))) | |
840 | (clobber (match_scratch:SI 3 "=r"))] | |
841 | "TARGET_POWERPC" | |
842 | "subf. %3,%2,%1" | |
843 | [(set_attr "type" "compare")]) | |
844 | ||
1fd4e8c1 RK |
845 | (define_insn "" |
846 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
847 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
848 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 849 | (const_int 0))) |
cd2b37d9 | 850 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 851 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 852 | "! TARGET_POWERPC" |
ca7f5001 | 853 | "{sf.|subfc.} %0,%2,%1" |
1fd4e8c1 RK |
854 | [(set_attr "type" "compare")]) |
855 | ||
deb9225a RK |
856 | (define_insn "" |
857 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
858 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
859 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
860 | (const_int 0))) | |
861 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
862 | (minus:SI (match_dup 1) (match_dup 2)))] | |
863 | "TARGET_POWERPC" | |
864 | "subf. %0,%2,%1" | |
865 | [(set_attr "type" "compare")]) | |
866 | ||
1fd4e8c1 | 867 | (define_expand "subsi3" |
cd2b37d9 | 868 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
869 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
870 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
871 | "" | |
a0044fb1 RK |
872 | " |
873 | { | |
874 | if (GET_CODE (operands[2]) == CONST_INT) | |
875 | { | |
876 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
877 | negate_rtx (SImode, operands[2]))); | |
878 | DONE; | |
879 | } | |
880 | }") | |
1fd4e8c1 RK |
881 | |
882 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
883 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
884 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
885 | ;; combine. | |
1fd4e8c1 RK |
886 | |
887 | (define_expand "sminsi3" | |
888 | [(set (match_dup 3) | |
cd2b37d9 | 889 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
890 | (match_operand:SI 2 "reg_or_short_operand" "")) |
891 | (const_int 0) | |
892 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 893 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 894 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 895 | "TARGET_POWER" |
1fd4e8c1 RK |
896 | " |
897 | { operands[3] = gen_reg_rtx (SImode); }") | |
898 | ||
95ac8e67 RK |
899 | (define_split |
900 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
901 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
902 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
903 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 904 | "TARGET_POWER" |
95ac8e67 RK |
905 | [(set (match_dup 3) |
906 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
907 | (const_int 0) | |
908 | (minus:SI (match_dup 2) (match_dup 1)))) | |
909 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
910 | "") | |
911 | ||
1fd4e8c1 RK |
912 | (define_expand "smaxsi3" |
913 | [(set (match_dup 3) | |
cd2b37d9 | 914 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
915 | (match_operand:SI 2 "reg_or_short_operand" "")) |
916 | (const_int 0) | |
917 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 918 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 919 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 920 | "TARGET_POWER" |
1fd4e8c1 RK |
921 | " |
922 | { operands[3] = gen_reg_rtx (SImode); }") | |
923 | ||
95ac8e67 RK |
924 | (define_split |
925 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
926 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
927 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
928 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 929 | "TARGET_POWER" |
95ac8e67 RK |
930 | [(set (match_dup 3) |
931 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
932 | (const_int 0) | |
933 | (minus:SI (match_dup 2) (match_dup 1)))) | |
934 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
935 | "") | |
936 | ||
1fd4e8c1 | 937 | (define_expand "uminsi3" |
cd2b37d9 | 938 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 939 | (const_int -2147483648))) |
cd2b37d9 | 940 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
1fd4e8c1 RK |
941 | (const_int -2147483648))) |
942 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) | |
943 | (const_int 0) | |
944 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 945 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 946 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 947 | "TARGET_POWER" |
1fd4e8c1 RK |
948 | " |
949 | { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") | |
950 | ||
951 | (define_expand "umaxsi3" | |
cd2b37d9 | 952 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 953 | (const_int -2147483648))) |
cd2b37d9 | 954 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
1fd4e8c1 RK |
955 | (const_int -2147483648))) |
956 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) | |
957 | (const_int 0) | |
958 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 959 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 960 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 961 | "TARGET_POWER" |
1fd4e8c1 RK |
962 | " |
963 | { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") | |
964 | ||
965 | (define_insn "" | |
cd2b37d9 RK |
966 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
967 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 968 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
969 | (const_int 0) |
970 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 971 | "TARGET_POWER" |
1fd4e8c1 RK |
972 | "doz%I2 %0,%1,%2") |
973 | ||
974 | (define_insn "" | |
975 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
976 | (compare:CC | |
cd2b37d9 | 977 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") |
5c23c401 | 978 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
979 | (const_int 0) |
980 | (minus:SI (match_dup 2) (match_dup 1))) | |
981 | (const_int 0))) | |
982 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 | 983 | "TARGET_POWER" |
1fd4e8c1 RK |
984 | "doz%I2. %3,%1,%2" |
985 | [(set_attr "type" "delayed_compare")]) | |
986 | ||
987 | (define_insn "" | |
988 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
989 | (compare:CC | |
cd2b37d9 | 990 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") |
5c23c401 | 991 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
992 | (const_int 0) |
993 | (minus:SI (match_dup 2) (match_dup 1))) | |
994 | (const_int 0))) | |
cd2b37d9 | 995 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
996 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
997 | (const_int 0) | |
998 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 999 | "TARGET_POWER" |
1fd4e8c1 RK |
1000 | "doz%I2. %0,%1,%2" |
1001 | [(set_attr "type" "delayed_compare")]) | |
1002 | ||
1003 | ;; We don't need abs with condition code because such comparisons should | |
1004 | ;; never be done. | |
1005 | (define_insn "abssi2" | |
cd2b37d9 RK |
1006 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1007 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1008 | "TARGET_POWER" |
1fd4e8c1 RK |
1009 | "abs %0,%1") |
1010 | ||
1011 | (define_insn "" | |
cd2b37d9 RK |
1012 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1013 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1014 | "TARGET_POWER" |
1fd4e8c1 RK |
1015 | "nabs %0,%1") |
1016 | ||
1017 | (define_insn "negsi2" | |
cd2b37d9 RK |
1018 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1019 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1020 | "" |
1021 | "neg %0,%1") | |
1022 | ||
1023 | (define_insn "" | |
1024 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 1025 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
1026 | (const_int 0))) |
1027 | (clobber (match_scratch:SI 2 "=r"))] | |
1028 | "" | |
1029 | "neg. %2,%1" | |
1030 | [(set_attr "type" "compare")]) | |
1031 | ||
1032 | (define_insn "" | |
1033 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
cd2b37d9 | 1034 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 1035 | (const_int 0))) |
cd2b37d9 | 1036 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1037 | (neg:SI (match_dup 1)))] |
1038 | "" | |
1039 | "neg. %0,%1" | |
1040 | [(set_attr "type" "compare")]) | |
1041 | ||
1042 | (define_insn "ffssi2" | |
1043 | [(set (match_operand:SI 0 "register_operand" "=&r") | |
1044 | (ffs:SI (match_operand:SI 1 "register_operand" "r")))] | |
1045 | "" | |
7f340546 | 1046 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 1047 | [(set_attr "length" "16")]) |
1fd4e8c1 | 1048 | |
ca7f5001 RK |
1049 | (define_expand "mulsi3" |
1050 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1051 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1052 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1053 | "" | |
1054 | " | |
1055 | { | |
1056 | if (TARGET_POWER) | |
68b40e7e | 1057 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1058 | else |
68b40e7e | 1059 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1060 | DONE; |
1061 | }") | |
1062 | ||
68b40e7e | 1063 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1064 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1065 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1066 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1067 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1068 | "TARGET_POWER" |
1069 | "@ | |
1070 | {muls|mullw} %0,%1,%2 | |
1071 | {muli|mulli} %0,%1,%2" | |
1072 | [(set_attr "type" "imul")]) | |
1073 | ||
68b40e7e | 1074 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1075 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1076 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1077 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1078 | "! TARGET_POWER" |
1fd4e8c1 | 1079 | "@ |
ca7f5001 RK |
1080 | mullw %0,%1,%2 |
1081 | mulli %0,%1,%2" | |
cfb557c4 | 1082 | [(set_attr "type" "imul")]) |
1fd4e8c1 RK |
1083 | |
1084 | (define_insn "" | |
1085 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
deb9225a | 1086 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
cd2b37d9 | 1087 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
1088 | (const_int 0))) |
1089 | (clobber (match_scratch:SI 3 "=r")) | |
1090 | (clobber (match_scratch:SI 4 "=q"))] | |
ca7f5001 RK |
1091 | "TARGET_POWER" |
1092 | "{muls.|mullw.} %3,%1,%2" | |
1093 | [(set_attr "type" "delayed_compare")]) | |
1094 | ||
1095 | (define_insn "" | |
1096 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
deb9225a | 1097 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
ca7f5001 RK |
1098 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1099 | (const_int 0))) | |
1100 | (clobber (match_scratch:SI 3 "=r"))] | |
25c341fa | 1101 | "! TARGET_POWER" |
ca7f5001 | 1102 | "mullw. %3,%1,%2" |
1fd4e8c1 RK |
1103 | [(set_attr "type" "delayed_compare")]) |
1104 | ||
1105 | (define_insn "" | |
1106 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
deb9225a | 1107 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
cd2b37d9 | 1108 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 1109 | (const_int 0))) |
cd2b37d9 | 1110 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1111 | (mult:SI (match_dup 1) (match_dup 2))) |
1112 | (clobber (match_scratch:SI 4 "=q"))] | |
ca7f5001 RK |
1113 | "TARGET_POWER" |
1114 | "{muls.|mullw.} %0,%1,%2" | |
1115 | [(set_attr "type" "delayed_compare")]) | |
1116 | ||
1117 | (define_insn "" | |
1118 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
deb9225a | 1119 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
ca7f5001 RK |
1120 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1121 | (const_int 0))) | |
1122 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1123 | (mult:SI (match_dup 1) (match_dup 2)))] | |
25c341fa | 1124 | "! TARGET_POWER" |
ca7f5001 | 1125 | "mullw. %0,%1,%2" |
1fd4e8c1 RK |
1126 | [(set_attr "type" "delayed_compare")]) |
1127 | ||
1128 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1129 | ;; 0 and remainder to operand 3. | |
1130 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1131 | ||
8ffd9c51 RK |
1132 | (define_expand "divmodsi4" |
1133 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1134 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1135 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
1136 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
1137 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
1138 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1139 | " | |
1140 | { | |
1141 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1142 | { | |
1143 | emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); | |
1144 | emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); | |
1145 | emit_insn (gen_divss_call ()); | |
1146 | emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); | |
1147 | emit_move_insn (operands[3], gen_rtx (REG, SImode, 4)); | |
1148 | DONE; | |
1149 | } | |
1150 | }") | |
deb9225a | 1151 | |
8ffd9c51 | 1152 | (define_insn "" |
cd2b37d9 RK |
1153 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1154 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1155 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1156 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 1157 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1158 | "TARGET_POWER" |
cfb557c4 RK |
1159 | "divs %0,%1,%2" |
1160 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1161 | |
ca7f5001 RK |
1162 | (define_insn "" |
1163 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1164 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1165 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1166 | "TARGET_POWERPC" | |
a473029f | 1167 | "divw %0,%1,%2" |
ca7f5001 RK |
1168 | [(set_attr "type" "idiv")]) |
1169 | ||
8ffd9c51 RK |
1170 | (define_expand "udivsi3" |
1171 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1172 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1173 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1174 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1175 | " | |
1176 | { | |
1177 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1178 | { | |
1179 | emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); | |
1180 | emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); | |
1181 | emit_insn (gen_quous_call ()); | |
1182 | emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); | |
1183 | DONE; | |
1184 | } | |
1185 | }") | |
deb9225a | 1186 | |
8ffd9c51 | 1187 | (define_insn "" |
ca7f5001 RK |
1188 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1189 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1190 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1191 | "TARGET_POWERPC" | |
a473029f | 1192 | "divwu %0,%1,%2" |
ca7f5001 RK |
1193 | [(set_attr "type" "idiv")]) |
1194 | ||
1fd4e8c1 | 1195 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1196 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1197 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1198 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1199 | (define_expand "divsi3" |
cd2b37d9 RK |
1200 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1201 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1202 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1203 | "" | |
1204 | " | |
1205 | { | |
ca7f5001 RK |
1206 | if (GET_CODE (operands[2]) == CONST_INT |
1207 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
1208 | ; | |
8ffd9c51 | 1209 | else if (TARGET_POWER && ! TARGET_POWERPC) |
1fd4e8c1 | 1210 | FAIL; |
405c5495 RK |
1211 | else |
1212 | operands[2] = force_reg (SImode, operands[2]); | |
f63184ac | 1213 | |
8ffd9c51 RK |
1214 | if (! TARGET_POWER && ! TARGET_POWERPC) |
1215 | { | |
1216 | emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); | |
1217 | emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); | |
1218 | emit_insn (gen_quoss_call ()); | |
1219 | emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); | |
1220 | DONE; | |
1221 | } | |
1fd4e8c1 RK |
1222 | }") |
1223 | ||
1224 | (define_expand "modsi3" | |
85644414 RK |
1225 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1226 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1227 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1228 | "" |
1fd4e8c1 RK |
1229 | " |
1230 | { | |
39b52ba2 RK |
1231 | int i = exact_log2 (INTVAL (operands[2])); |
1232 | rtx temp1; | |
1233 | rtx temp2; | |
1234 | ||
405c5495 | 1235 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) |
39b52ba2 RK |
1236 | FAIL; |
1237 | ||
1238 | temp1 = gen_reg_rtx (SImode); | |
1239 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1240 | |
85644414 | 1241 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1242 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1243 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1244 | DONE; | |
1fd4e8c1 RK |
1245 | }") |
1246 | ||
1247 | (define_insn "" | |
cd2b37d9 RK |
1248 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1249 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1250 | (match_operand:SI 2 "const_int_operand" "N")))] |
1251 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
ca7f5001 | 1252 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 1253 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
1254 | |
1255 | (define_insn "" | |
1256 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
b6b12107 RK |
1257 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1258 | (match_operand:SI 2 "const_int_operand" "N")) | |
1259 | (const_int 0))) | |
1fd4e8c1 RK |
1260 | (clobber (match_scratch:SI 3 "=r"))] |
1261 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
ca7f5001 | 1262 | "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3" |
b19003d8 RK |
1263 | [(set_attr "type" "compare") |
1264 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
1265 | |
1266 | (define_insn "" | |
1267 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
b6b12107 RK |
1268 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1269 | (match_operand:SI 2 "const_int_operand" "N")) | |
1270 | (const_int 0))) | |
cd2b37d9 | 1271 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1272 | (div:SI (match_dup 1) (match_dup 2)))] |
1273 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
ca7f5001 | 1274 | "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0" |
b19003d8 RK |
1275 | [(set_attr "type" "compare") |
1276 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
1277 | |
1278 | (define_insn "" | |
cd2b37d9 | 1279 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 1280 | (udiv:SI |
996a5f59 | 1281 | (plus:DI (ashift:DI |
cd2b37d9 | 1282 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 1283 | (const_int 32)) |
23a900dc | 1284 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 1285 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 1286 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 1287 | (umod:SI |
996a5f59 | 1288 | (plus:DI (ashift:DI |
1fd4e8c1 | 1289 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 1290 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 RK |
1291 | (match_dup 3)))] |
1292 | ||
ca7f5001 | 1293 | "TARGET_POWER" |
cfb557c4 RK |
1294 | "div %0,%1,%3" |
1295 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
1296 | |
1297 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
1298 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
1299 | ;; have to worry about the branches. So make a few subroutines here. | |
1300 | ;; | |
1301 | ;; First comes the normal case. | |
1302 | (define_expand "udivmodsi4_normal" | |
1303 | [(set (match_dup 4) (const_int 0)) | |
1304 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 1305 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
1306 | (const_int 32)) |
1307 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
1308 | (match_operand:SI 2 "" ""))) | |
1309 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 1310 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
1311 | (const_int 32)) |
1312 | (zero_extend:DI (match_dup 1))) | |
1313 | (match_dup 2)))])] | |
ca7f5001 | 1314 | "TARGET_POWER" |
1fd4e8c1 RK |
1315 | " |
1316 | { operands[4] = gen_reg_rtx (SImode); }") | |
1317 | ||
1318 | ;; This handles the branches. | |
1319 | (define_expand "udivmodsi4_tests" | |
1320 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
1321 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
1322 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
1323 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
1324 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
1325 | (set (match_dup 0) (const_int 1)) | |
1326 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
1327 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
1328 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
1329 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 1330 | "TARGET_POWER" |
1fd4e8c1 RK |
1331 | " |
1332 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
1333 | operands[6] = gen_reg_rtx (CCmode); | |
1334 | }") | |
1335 | ||
1336 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
1337 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1338 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 1339 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 1340 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 1341 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 1342 | "" |
1fd4e8c1 RK |
1343 | " |
1344 | { | |
1345 | rtx label = 0; | |
1346 | ||
8ffd9c51 RK |
1347 | if (! TARGET_POWER) |
1348 | if (! TARGET_POWERPC) | |
1349 | { | |
1350 | emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); | |
1351 | emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); | |
1352 | emit_insn (gen_divus_call ()); | |
1353 | emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); | |
1354 | emit_move_insn (operands[3], gen_rtx (REG, SImode, 4)); | |
1355 | DONE; | |
1356 | } | |
1357 | else | |
1358 | FAIL; | |
0081a354 | 1359 | |
1fd4e8c1 RK |
1360 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
1361 | { | |
1362 | operands[2] = force_reg (SImode, operands[2]); | |
1363 | label = gen_label_rtx (); | |
1364 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
1365 | operands[3], label)); | |
1366 | } | |
1367 | else | |
1368 | operands[2] = force_reg (SImode, operands[2]); | |
1369 | ||
1370 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
1371 | operands[3])); | |
1372 | if (label) | |
1373 | emit_label (label); | |
1374 | ||
1375 | DONE; | |
1376 | }") | |
0081a354 | 1377 | |
8ffd9c51 RK |
1378 | ;; AIX architecture-independent common-mode multiply (DImode), |
1379 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
1380 | ;; R4; results in R3 and somtimes R4; link register always clobbered by bla | |
1381 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
1382 | ;; assumed unused if generating common-mode, so ignore. | |
1383 | (define_insn "mulh_call" | |
1384 | [(set (reg:SI 3) | |
1385 | (truncate:SI | |
1386 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
1387 | (sign_extend:DI (reg:SI 4))) | |
1388 | (const_int 32)))) | |
1389 | (clobber (match_scratch:SI 0 "=l"))] | |
1390 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1391 | "bla __mulh") | |
0081a354 | 1392 | |
8ffd9c51 RK |
1393 | (define_insn "mull_call" |
1394 | [(set (reg:DI 3) | |
1395 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
1396 | (sign_extend:DI (reg:SI 4)))) | |
1397 | (clobber (match_scratch:SI 0 "=l")) | |
1398 | (clobber (reg:SI 0))] | |
1399 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1400 | "bla __mull") | |
0081a354 | 1401 | |
8ffd9c51 RK |
1402 | (define_insn "divss_call" |
1403 | [(set (reg:SI 3) | |
1404 | (div:SI (reg:SI 3) (reg:SI 4))) | |
1405 | (set (reg:SI 4) | |
1406 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
1407 | (clobber (match_scratch:SI 0 "=l")) | |
1408 | (clobber (reg:SI 0))] | |
1409 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1410 | "bla __divss") | |
0081a354 | 1411 | |
8ffd9c51 RK |
1412 | (define_insn "divus_call" |
1413 | [(set (reg:SI 3) | |
1414 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
1415 | (set (reg:SI 4) | |
1416 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
1417 | (clobber (match_scratch:SI 0 "=l")) | |
1418 | (clobber (reg:SI 0))] | |
1419 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1420 | "bla __divus") | |
0081a354 | 1421 | |
8ffd9c51 RK |
1422 | (define_insn "quoss_call" |
1423 | [(set (reg:SI 3) | |
1424 | (div:SI (reg:SI 3) (reg:SI 4))) | |
1425 | (clobber (match_scratch:SI 0 "=l"))] | |
1426 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1427 | "bla __quoss") | |
0081a354 | 1428 | |
8ffd9c51 RK |
1429 | (define_insn "quous_call" |
1430 | [(set (reg:SI 3) | |
1431 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
1432 | (clobber (match_scratch:SI 0 "=l")) | |
1433 | (clobber (reg:SI 0))] | |
1434 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1435 | "bla __quous") | |
1436 | \f | |
1fd4e8c1 | 1437 | (define_insn "andsi3" |
cd2b37d9 RK |
1438 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1439 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1fd4e8c1 RK |
1440 | (match_operand:SI 2 "and_operand" "?r,L,K,J"))) |
1441 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
1442 | "" | |
1443 | "@ | |
1444 | and %0,%1,%2 | |
ca7f5001 RK |
1445 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
1446 | {andil.|andi.} %0,%1,%b2 | |
1447 | {andiu.|andis.} %0,%1,%u2") | |
1fd4e8c1 RK |
1448 | |
1449 | (define_insn "" | |
1450 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") | |
cd2b37d9 | 1451 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") |
1fd4e8c1 RK |
1452 | (match_operand:SI 2 "and_operand" "r,K,J,L")) |
1453 | (const_int 0))) | |
1454 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] | |
1455 | "" | |
1456 | "@ | |
1457 | and. %3,%1,%2 | |
ca7f5001 RK |
1458 | {andil.|andi.} %3,%1,%b2 |
1459 | {andiu.|andis.} %3,%1,%u2 | |
1460 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2" | |
1fd4e8c1 RK |
1461 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) |
1462 | ||
1463 | (define_insn "" | |
1464 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") | |
cd2b37d9 | 1465 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") |
1fd4e8c1 RK |
1466 | (match_operand:SI 2 "and_operand" "r,K,J,L")) |
1467 | (const_int 0))) | |
cd2b37d9 | 1468 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 RK |
1469 | (and:SI (match_dup 1) (match_dup 2)))] |
1470 | "" | |
1471 | "@ | |
1472 | and. %0,%1,%2 | |
ca7f5001 RK |
1473 | {andil.|andi.} %0,%1,%b2 |
1474 | {andiu.|andis.} %0,%1,%u2 | |
1475 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2" | |
b19003d8 | 1476 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) |
1fd4e8c1 | 1477 | |
f357808b RK |
1478 | ;; Take a AND with a constant that cannot be done in a single insn and try to |
1479 | ;; split it into two insns. This does not verify that the insns are valid | |
1480 | ;; since this need not be done as combine will do it. | |
1481 | ||
1482 | (define_split | |
cd2b37d9 RK |
1483 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1484 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b RK |
1485 | (match_operand:SI 2 "non_and_cint_operand" "")))] |
1486 | "" | |
1487 | [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3))) | |
1488 | (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))] | |
1489 | " | |
1490 | { | |
1491 | int maskval = INTVAL (operands[2]); | |
1492 | int i, transitions, last_bit_value; | |
1493 | int orig = maskval, first_c = maskval, second_c; | |
1494 | ||
1495 | /* We know that MASKVAL must have more than 2 bit-transitions. Start at | |
1496 | the low-order bit and count for the third transition. When we get there, | |
1497 | make a first mask that has everything to the left of that position | |
1498 | a one. Then make the second mask to turn off whatever else is needed. */ | |
1499 | ||
1500 | for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++) | |
1501 | { | |
1502 | if (((maskval >>= 1) & 1) != last_bit_value) | |
1503 | last_bit_value ^= 1, transitions++; | |
1504 | ||
1505 | if (transitions > 2) | |
1506 | { | |
1507 | first_c |= (~0) << i; | |
1508 | break; | |
1509 | } | |
1510 | } | |
1511 | ||
1512 | second_c = orig | ~ first_c; | |
1513 | ||
1514 | operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c); | |
1515 | operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c); | |
1516 | }") | |
1517 | ||
1518 | (define_insn "iorsi3" | |
cd2b37d9 RK |
1519 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1520 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
1fd4e8c1 RK |
1521 | (match_operand:SI 2 "logical_operand" "r,K,J")))] |
1522 | "" | |
1523 | "@ | |
1524 | or %0,%1,%2 | |
ca7f5001 RK |
1525 | {oril|ori} %0,%1,%b2 |
1526 | {oriu|oris} %0,%1,%u2") | |
1fd4e8c1 RK |
1527 | |
1528 | (define_insn "" | |
1529 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
deb9225a | 1530 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
cd2b37d9 | 1531 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
1532 | (const_int 0))) |
1533 | (clobber (match_scratch:SI 3 "=r"))] | |
1534 | "" | |
1535 | "or. %3,%1,%2" | |
1536 | [(set_attr "type" "compare")]) | |
1537 | ||
1538 | (define_insn "" | |
1539 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
deb9225a | 1540 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
cd2b37d9 | 1541 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 1542 | (const_int 0))) |
cd2b37d9 | 1543 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1544 | (ior:SI (match_dup 1) (match_dup 2)))] |
1545 | "" | |
1546 | "or. %0,%1,%2" | |
1547 | [(set_attr "type" "compare")]) | |
1548 | ||
f357808b RK |
1549 | ;; Split an IOR that we can't do in one insn into two insns, each of which |
1550 | ;; does one 16-bit part. This is used by combine. | |
1551 | ||
1552 | (define_split | |
cd2b37d9 RK |
1553 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1554 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1555 | (match_operand:SI 2 "non_logical_cint_operand" "")))] |
1fd4e8c1 | 1556 | "" |
f357808b RK |
1557 | [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) |
1558 | (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] | |
1559 | " | |
1fd4e8c1 | 1560 | { |
f357808b RK |
1561 | operands[3] = gen_rtx (CONST_INT, VOIDmode, |
1562 | INTVAL (operands[2]) & 0xffff0000); | |
1563 | operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); | |
1fd4e8c1 RK |
1564 | }") |
1565 | ||
f357808b | 1566 | (define_insn "xorsi3" |
cd2b37d9 RK |
1567 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1568 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
1fd4e8c1 RK |
1569 | (match_operand:SI 2 "logical_operand" "r,K,J")))] |
1570 | "" | |
1571 | "@ | |
1572 | xor %0,%1,%2 | |
ca7f5001 RK |
1573 | {xoril|xori} %0,%1,%b2 |
1574 | {xoriu|xoris} %0,%1,%u2") | |
1fd4e8c1 RK |
1575 | |
1576 | (define_insn "" | |
1577 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
deb9225a | 1578 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
cd2b37d9 | 1579 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
1580 | (const_int 0))) |
1581 | (clobber (match_scratch:SI 3 "=r"))] | |
1582 | "" | |
1583 | "xor. %3,%1,%2" | |
1584 | [(set_attr "type" "compare")]) | |
1585 | ||
1586 | (define_insn "" | |
1587 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
deb9225a | 1588 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
cd2b37d9 | 1589 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 1590 | (const_int 0))) |
cd2b37d9 | 1591 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1592 | (xor:SI (match_dup 1) (match_dup 2)))] |
1593 | "" | |
1594 | "xor. %0,%1,%2" | |
1595 | [(set_attr "type" "compare")]) | |
1596 | ||
f357808b RK |
1597 | ;; Split an XOR that we can't do in one insn into two insns, each of which |
1598 | ;; does one 16-bit part. This is used by combine. | |
1599 | ||
1600 | (define_split | |
cd2b37d9 RK |
1601 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1602 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1603 | (match_operand:SI 2 "non_logical_cint_operand" "")))] |
1fd4e8c1 | 1604 | "" |
f357808b RK |
1605 | [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) |
1606 | (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] | |
1607 | " | |
1fd4e8c1 | 1608 | { |
f357808b RK |
1609 | operands[3] = gen_rtx (CONST_INT, VOIDmode, |
1610 | INTVAL (operands[2]) & 0xffff0000); | |
1611 | operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); | |
1fd4e8c1 RK |
1612 | }") |
1613 | ||
1614 | (define_insn "" | |
cd2b37d9 RK |
1615 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1616 | (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1617 | (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
1fd4e8c1 RK |
1618 | "" |
1619 | "eqv %0,%1,%2") | |
1620 | ||
1621 | (define_insn "" | |
1622 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
1623 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
1624 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 RK |
1625 | (const_int 0))) |
1626 | (clobber (match_scratch:SI 3 "=r"))] | |
1627 | "" | |
1628 | "eqv. %3,%1,%2" | |
1629 | [(set_attr "type" "compare")]) | |
1630 | ||
1631 | (define_insn "" | |
1632 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
1633 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
1634 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 | 1635 | (const_int 0))) |
cd2b37d9 | 1636 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1637 | (not:SI (xor:SI (match_dup 1) (match_dup 2))))] |
1638 | "" | |
1639 | "eqv. %0,%1,%2" | |
1640 | [(set_attr "type" "compare")]) | |
1641 | ||
1642 | (define_insn "" | |
cd2b37d9 RK |
1643 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1644 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
1645 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1646 | "" |
1647 | "andc %0,%2,%1") | |
1648 | ||
1649 | (define_insn "" | |
1650 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
1651 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1652 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
1653 | (const_int 0))) |
1654 | (clobber (match_scratch:SI 3 "=r"))] | |
1655 | "" | |
1656 | "andc. %3,%2,%1" | |
1657 | [(set_attr "type" "compare")]) | |
1658 | ||
1659 | (define_insn "" | |
1660 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
1661 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1662 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1663 | (const_int 0))) |
cd2b37d9 | 1664 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1665 | (and:SI (not:SI (match_dup 1)) (match_dup 2)))] |
1666 | "" | |
1667 | "andc. %0,%2,%1" | |
1668 | [(set_attr "type" "compare")]) | |
1669 | ||
1670 | (define_insn "" | |
cd2b37d9 RK |
1671 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1672 | (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
1673 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1674 | "" |
1675 | "orc %0,%2,%1") | |
1676 | ||
1677 | (define_insn "" | |
1678 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
1679 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1680 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
1681 | (const_int 0))) |
1682 | (clobber (match_scratch:SI 3 "=r"))] | |
1683 | "" | |
1684 | "orc. %3,%2,%1" | |
1685 | [(set_attr "type" "compare")]) | |
1686 | ||
1687 | (define_insn "" | |
1688 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
1689 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1690 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1691 | (const_int 0))) |
cd2b37d9 | 1692 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1693 | (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] |
1694 | "" | |
1695 | "orc. %0,%2,%1" | |
1696 | [(set_attr "type" "compare")]) | |
1697 | ||
1698 | (define_insn "" | |
cd2b37d9 | 1699 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
deb9225a | 1700 | (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 1701 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] |
1fd4e8c1 RK |
1702 | "" |
1703 | "nand %0,%1,%2") | |
1704 | ||
1705 | (define_insn "" | |
1706 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
deb9225a | 1707 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 1708 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
1709 | (const_int 0))) |
1710 | (clobber (match_scratch:SI 3 "=r"))] | |
1711 | "" | |
1712 | "nand. %3,%1,%2" | |
1713 | [(set_attr "type" "compare")]) | |
1714 | ||
1715 | (define_insn "" | |
1716 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
deb9225a | 1717 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 1718 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 1719 | (const_int 0))) |
cd2b37d9 | 1720 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1721 | (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] |
1722 | "" | |
1723 | "nand. %0,%1,%2" | |
1724 | [(set_attr "type" "compare")]) | |
1725 | ||
1726 | (define_insn "" | |
cd2b37d9 | 1727 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
deb9225a | 1728 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 1729 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] |
1fd4e8c1 RK |
1730 | "" |
1731 | "nor %0,%1,%2") | |
1732 | ||
1733 | (define_insn "" | |
1734 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
deb9225a | 1735 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 1736 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
1737 | (const_int 0))) |
1738 | (clobber (match_scratch:SI 3 "=r"))] | |
1739 | "" | |
1740 | "nor. %3,%1,%2" | |
1741 | [(set_attr "type" "compare")]) | |
1742 | ||
1743 | (define_insn "" | |
1744 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
deb9225a | 1745 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 1746 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 1747 | (const_int 0))) |
cd2b37d9 | 1748 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1749 | (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] |
1750 | "" | |
1751 | "nor. %0,%1,%2" | |
1752 | [(set_attr "type" "compare")]) | |
1753 | ||
1754 | ;; maskir insn. We need four forms because things might be in arbitrary | |
1755 | ;; orders. Don't define forms that only set CR fields because these | |
1756 | ;; would modify an input register. | |
1757 | ||
1758 | (define_insn "" | |
cd2b37d9 | 1759 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
1760 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
1761 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
1762 | (and:SI (match_dup 2) | |
cd2b37d9 | 1763 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 1764 | "TARGET_POWER" |
01def764 | 1765 | "maskir %0,%3,%2") |
1fd4e8c1 RK |
1766 | |
1767 | (define_insn "" | |
1768 | [(set (match_operand:SI 0 "register_operand" "=r") | |
01def764 RK |
1769 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
1770 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 1771 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 1772 | (match_dup 2))))] |
ca7f5001 | 1773 | "TARGET_POWER" |
01def764 | 1774 | "maskir %0,%3,%2") |
1fd4e8c1 RK |
1775 | |
1776 | (define_insn "" | |
cd2b37d9 | 1777 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 1778 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 1779 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
1780 | (and:SI (not:SI (match_dup 2)) |
1781 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 1782 | "TARGET_POWER" |
01def764 | 1783 | "maskir %0,%3,%2") |
1fd4e8c1 RK |
1784 | |
1785 | (define_insn "" | |
cd2b37d9 RK |
1786 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1787 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
1788 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1789 | (and:SI (not:SI (match_dup 2)) | |
1790 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 1791 | "TARGET_POWER" |
01def764 | 1792 | "maskir %0,%3,%2") |
1fd4e8c1 RK |
1793 | |
1794 | (define_insn "" | |
1795 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
1796 | (compare:CC | |
01def764 RK |
1797 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
1798 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
1799 | (and:SI (match_dup 2) | |
cd2b37d9 | 1800 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 1801 | (const_int 0))) |
cd2b37d9 | 1802 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
1803 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
1804 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 1805 | "TARGET_POWER" |
01def764 | 1806 | "maskir. %0,%3,%2" |
1fd4e8c1 RK |
1807 | [(set_attr "type" "compare")]) |
1808 | ||
1809 | (define_insn "" | |
1810 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
1811 | (compare:CC | |
01def764 RK |
1812 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
1813 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 1814 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 1815 | (match_dup 2))) |
1fd4e8c1 RK |
1816 | (const_int 0))) |
1817 | (set (match_operand:SI 0 "register_operand" "=r") | |
01def764 RK |
1818 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
1819 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 1820 | "TARGET_POWER" |
01def764 | 1821 | "maskir. %0,%3,%2" |
1fd4e8c1 RK |
1822 | [(set_attr "type" "compare")]) |
1823 | ||
1824 | (define_insn "" | |
1825 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
1826 | (compare:CC | |
01def764 | 1827 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 1828 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
1829 | (and:SI (not:SI (match_dup 2)) |
1830 | (match_operand:SI 1 "gpc_reg_operand" "0"))) | |
1fd4e8c1 | 1831 | (const_int 0))) |
cd2b37d9 | 1832 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
1833 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
1834 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 1835 | "TARGET_POWER" |
01def764 | 1836 | "maskir. %0,%3,%2" |
1fd4e8c1 RK |
1837 | [(set_attr "type" "compare")]) |
1838 | ||
1839 | (define_insn "" | |
1840 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
1841 | (compare:CC | |
cd2b37d9 | 1842 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 RK |
1843 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1844 | (and:SI (not:SI (match_dup 2)) | |
1845 | (match_operand:SI 1 "gpc_reg_operand" "0"))) | |
1fd4e8c1 | 1846 | (const_int 0))) |
cd2b37d9 | 1847 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
1848 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
1849 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 1850 | "TARGET_POWER" |
01def764 | 1851 | "maskir. %0,%3,%2" |
1fd4e8c1 RK |
1852 | [(set_attr "type" "compare")]) |
1853 | \f | |
1854 | ;; Rotate and shift insns, in all their variants. These support shifts, | |
1855 | ;; field inserts and extracts, and various combinations thereof. | |
1856 | (define_insn "insv" | |
cd2b37d9 | 1857 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
1858 | (match_operand:SI 1 "const_int_operand" "i") |
1859 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 1860 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
1861 | "" |
1862 | "* | |
1863 | { | |
1864 | int start = INTVAL (operands[2]) & 31; | |
1865 | int size = INTVAL (operands[1]) & 31; | |
1866 | ||
1867 | operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size); | |
1868 | operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); | |
ca7f5001 | 1869 | return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; |
1fd4e8c1 RK |
1870 | }") |
1871 | ||
1872 | (define_insn "extzv" | |
cd2b37d9 RK |
1873 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1874 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1875 | (match_operand:SI 2 "const_int_operand" "i") |
1876 | (match_operand:SI 3 "const_int_operand" "i")))] | |
1877 | "" | |
1878 | "* | |
1879 | { | |
1880 | int start = INTVAL (operands[3]) & 31; | |
1881 | int size = INTVAL (operands[2]) & 31; | |
1882 | ||
1883 | if (start + size >= 32) | |
1884 | operands[3] = const0_rtx; | |
1885 | else | |
1886 | operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); | |
ca7f5001 | 1887 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
1888 | }") |
1889 | ||
1890 | (define_insn "" | |
1891 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 1892 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1893 | (match_operand:SI 2 "const_int_operand" "i") |
1894 | (match_operand:SI 3 "const_int_operand" "i")) | |
1895 | (const_int 0))) | |
1896 | (clobber (match_scratch:SI 4 "=r"))] | |
1897 | "" | |
1898 | "* | |
1899 | { | |
1900 | int start = INTVAL (operands[3]) & 31; | |
1901 | int size = INTVAL (operands[2]) & 31; | |
1902 | ||
a7a975e1 RK |
1903 | /* If the bitfield being tested fits in the upper or lower half of a |
1904 | word, it is possible to use andiu. or andil. to test it. This is | |
1905 | useful because the condition register set-use delay is smaller for | |
1906 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
1907 | position is 0 because the LT and GT bits may be set wrong. */ | |
1908 | ||
1909 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 RK |
1910 | { |
1911 | operands[3] = gen_rtx (CONST_INT, VOIDmode, | |
1912 | ((1 << (16 - (start & 15))) | |
1913 | - (1 << (16 - (start & 15) - size)))); | |
1914 | if (start < 16) | |
ca7f5001 | 1915 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 1916 | else |
ca7f5001 | 1917 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 RK |
1918 | } |
1919 | ||
1fd4e8c1 RK |
1920 | if (start + size >= 32) |
1921 | operands[3] = const0_rtx; | |
1922 | else | |
1923 | operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); | |
ca7f5001 | 1924 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
1925 | }" |
1926 | [(set_attr "type" "compare")]) | |
1927 | ||
1928 | (define_insn "" | |
1929 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
cd2b37d9 | 1930 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1931 | (match_operand:SI 2 "const_int_operand" "i") |
1932 | (match_operand:SI 3 "const_int_operand" "i")) | |
1933 | (const_int 0))) | |
cd2b37d9 | 1934 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1935 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
1936 | "" | |
1937 | "* | |
1938 | { | |
1939 | int start = INTVAL (operands[3]) & 31; | |
1940 | int size = INTVAL (operands[2]) & 31; | |
1941 | ||
a7a975e1 | 1942 | if (start >= 16 && start + size == 32) |
df031c43 | 1943 | { |
a7a975e1 | 1944 | operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1); |
ca7f5001 | 1945 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 RK |
1946 | } |
1947 | ||
1fd4e8c1 RK |
1948 | if (start + size >= 32) |
1949 | operands[3] = const0_rtx; | |
1950 | else | |
1951 | operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); | |
ca7f5001 | 1952 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
1953 | }" |
1954 | [(set_attr "type" "delayed_compare")]) | |
1955 | ||
1956 | (define_insn "rotlsi3" | |
cd2b37d9 RK |
1957 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1958 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1959 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
1960 | "" | |
ca7f5001 | 1961 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 RK |
1962 | |
1963 | (define_insn "" | |
1964 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 1965 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1966 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
1967 | (const_int 0))) | |
1968 | (clobber (match_scratch:SI 3 "=r"))] | |
1969 | "" | |
ca7f5001 | 1970 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff" |
1fd4e8c1 RK |
1971 | [(set_attr "type" "delayed_compare")]) |
1972 | ||
1973 | (define_insn "" | |
1974 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 | 1975 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1976 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
1977 | (const_int 0))) | |
cd2b37d9 | 1978 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1979 | (rotate:SI (match_dup 1) (match_dup 2)))] |
1980 | "" | |
ca7f5001 | 1981 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff" |
1fd4e8c1 RK |
1982 | [(set_attr "type" "delayed_compare")]) |
1983 | ||
1984 | (define_insn "" | |
cd2b37d9 RK |
1985 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1986 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1987 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
1988 | (match_operand:SI 3 "mask_operand" "L")))] | |
1989 | "" | |
ca7f5001 | 1990 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
1991 | |
1992 | (define_insn "" | |
1993 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
1994 | (compare:CC (and:SI | |
cd2b37d9 | 1995 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1996 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
1997 | (match_operand:SI 3 "mask_operand" "L")) | |
1998 | (const_int 0))) | |
1999 | (clobber (match_scratch:SI 4 "=r"))] | |
2000 | "" | |
ca7f5001 | 2001 | "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3" |
1fd4e8c1 RK |
2002 | [(set_attr "type" "delayed_compare")]) |
2003 | ||
2004 | (define_insn "" | |
2005 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
2006 | (compare:CC (and:SI | |
cd2b37d9 | 2007 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2008 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
2009 | (match_operand:SI 3 "mask_operand" "L")) | |
2010 | (const_int 0))) | |
cd2b37d9 | 2011 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2012 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
2013 | "" | |
ca7f5001 | 2014 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3" |
1fd4e8c1 RK |
2015 | [(set_attr "type" "delayed_compare")]) |
2016 | ||
2017 | (define_insn "" | |
cd2b37d9 | 2018 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2019 | (zero_extend:SI |
2020 | (subreg:QI | |
cd2b37d9 | 2021 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2022 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
2023 | "" | |
ca7f5001 | 2024 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 RK |
2025 | |
2026 | (define_insn "" | |
2027 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
2028 | (compare:CC (zero_extend:SI | |
2029 | (subreg:QI | |
cd2b37d9 | 2030 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2031 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) |
2032 | (const_int 0))) | |
2033 | (clobber (match_scratch:SI 3 "=r"))] | |
2034 | "" | |
ca7f5001 | 2035 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff" |
1fd4e8c1 RK |
2036 | [(set_attr "type" "delayed_compare")]) |
2037 | ||
2038 | (define_insn "" | |
2039 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
2040 | (compare:CC (zero_extend:SI | |
2041 | (subreg:QI | |
cd2b37d9 | 2042 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2043 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) |
2044 | (const_int 0))) | |
cd2b37d9 | 2045 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2046 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
2047 | "" | |
ca7f5001 | 2048 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff" |
1fd4e8c1 RK |
2049 | [(set_attr "type" "delayed_compare")]) |
2050 | ||
2051 | (define_insn "" | |
cd2b37d9 | 2052 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2053 | (zero_extend:SI |
2054 | (subreg:HI | |
cd2b37d9 | 2055 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2056 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
2057 | "" | |
ca7f5001 | 2058 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 RK |
2059 | |
2060 | (define_insn "" | |
2061 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
2062 | (compare:CC (zero_extend:SI | |
2063 | (subreg:HI | |
cd2b37d9 | 2064 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2065 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) |
2066 | (const_int 0))) | |
2067 | (clobber (match_scratch:SI 3 "=r"))] | |
2068 | "" | |
ca7f5001 | 2069 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff" |
1fd4e8c1 RK |
2070 | [(set_attr "type" "delayed_compare")]) |
2071 | ||
2072 | (define_insn "" | |
2073 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
2074 | (compare:CC (zero_extend:SI | |
2075 | (subreg:HI | |
cd2b37d9 | 2076 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2077 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) |
2078 | (const_int 0))) | |
cd2b37d9 | 2079 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2080 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
2081 | "" | |
ca7f5001 | 2082 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff" |
1fd4e8c1 RK |
2083 | [(set_attr "type" "delayed_compare")]) |
2084 | ||
2085 | ;; Note that we use "sle." instead of "sl." so that we can set | |
2086 | ;; SHIFT_COUNT_TRUNCATED. | |
2087 | ||
ca7f5001 RK |
2088 | (define_expand "ashlsi3" |
2089 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2090 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2091 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
2092 | "" | |
2093 | " | |
2094 | { | |
2095 | if (TARGET_POWER) | |
2096 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
2097 | else | |
25c341fa | 2098 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2099 | DONE; |
2100 | }") | |
2101 | ||
2102 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
2103 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2104 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
2105 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
2106 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 2107 | "TARGET_POWER" |
1fd4e8c1 RK |
2108 | "@ |
2109 | sle %0,%1,%2 | |
ca7f5001 RK |
2110 | {sli|slwi} %0,%1,%h2" |
2111 | [(set_attr "length" "8")]) | |
2112 | ||
25c341fa | 2113 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
2114 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2115 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2116 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 2117 | "! TARGET_POWER" |
ca7f5001 | 2118 | "slw%I2 %0,%1,%2" |
b19003d8 | 2119 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
2120 | |
2121 | (define_insn "" | |
2122 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 2123 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
2124 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
2125 | (const_int 0))) | |
2126 | (clobber (match_scratch:SI 3 "=r,r")) | |
2127 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 2128 | "TARGET_POWER" |
1fd4e8c1 RK |
2129 | "@ |
2130 | sle. %3,%1,%2 | |
ca7f5001 RK |
2131 | {sli.|slwi.} %3,%1,%h2" |
2132 | [(set_attr "type" "delayed_compare")]) | |
25c341fa | 2133 | |
ca7f5001 RK |
2134 | (define_insn "" |
2135 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
2136 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2137 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
2138 | (const_int 0))) | |
2139 | (clobber (match_scratch:SI 3 "=r"))] | |
8ffd9c51 | 2140 | "! TARGET_POWER" |
ca7f5001 | 2141 | "slw%I2. %3,%1,%2" |
1fd4e8c1 RK |
2142 | [(set_attr "type" "delayed_compare")]) |
2143 | ||
2144 | (define_insn "" | |
2145 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 2146 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
2147 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
2148 | (const_int 0))) | |
cd2b37d9 | 2149 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
2150 | (ashift:SI (match_dup 1) (match_dup 2))) |
2151 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 2152 | "TARGET_POWER" |
1fd4e8c1 RK |
2153 | "@ |
2154 | sle. %0,%1,%2 | |
ca7f5001 RK |
2155 | {sli.|slwi.} %0,%1,%h2" |
2156 | [(set_attr "type" "delayed_compare")]) | |
25c341fa | 2157 | |
ca7f5001 RK |
2158 | (define_insn "" |
2159 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
2160 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2161 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
2162 | (const_int 0))) | |
2163 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2164 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
8ffd9c51 | 2165 | "! TARGET_POWER" |
ca7f5001 | 2166 | "slw%I2. %0,%1,%2" |
1fd4e8c1 RK |
2167 | [(set_attr "type" "delayed_compare")]) |
2168 | ||
2169 | (define_insn "" | |
cd2b37d9 RK |
2170 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2171 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2172 | (match_operand:SI 2 "const_int_operand" "i")) |
2173 | (match_operand:SI 3 "mask_operand" "L")))] | |
2174 | "includes_lshift_p (operands[2], operands[3])" | |
ca7f5001 | 2175 | "{rlinm|rlwinm} %0,%h1,%h2,%m3,%M3") |
1fd4e8c1 RK |
2176 | |
2177 | (define_insn "" | |
2178 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
2179 | (compare:CC | |
cd2b37d9 | 2180 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2181 | (match_operand:SI 2 "const_int_operand" "i")) |
2182 | (match_operand:SI 3 "mask_operand" "L")) | |
2183 | (const_int 0))) | |
2184 | (clobber (match_scratch:SI 4 "=r"))] | |
2185 | "includes_lshift_p (operands[2], operands[3])" | |
ca7f5001 | 2186 | "{rlinm.|rlwinm.} %4,%h1,%h2,%m3,%M3" |
1fd4e8c1 RK |
2187 | [(set_attr "type" "delayed_compare")]) |
2188 | ||
2189 | (define_insn "" | |
2190 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
2191 | (compare:CC | |
cd2b37d9 | 2192 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2193 | (match_operand:SI 2 "const_int_operand" "i")) |
2194 | (match_operand:SI 3 "mask_operand" "L")) | |
2195 | (const_int 0))) | |
cd2b37d9 | 2196 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2197 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
2198 | "includes_lshift_p (operands[2], operands[3])" | |
ca7f5001 | 2199 | "{rlinm.|rlwinm.} %0,%h1,%h2,%m3,%M3" |
1fd4e8c1 RK |
2200 | [(set_attr "type" "delayed_compare")]) |
2201 | ||
ca7f5001 | 2202 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 2203 | ;; "sli x,x,0". |
ca7f5001 RK |
2204 | (define_expand "lshrsi3" |
2205 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2206 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2207 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
2208 | "" | |
2209 | " | |
2210 | { | |
2211 | if (TARGET_POWER) | |
2212 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
2213 | else | |
25c341fa | 2214 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2215 | DONE; |
2216 | }") | |
2217 | ||
2218 | (define_insn "lshrsi3_power" | |
cd2b37d9 RK |
2219 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2220 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
2221 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
2222 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 2223 | "TARGET_POWER" |
1fd4e8c1 RK |
2224 | "@ |
2225 | sre %0,%1,%2 | |
ca7f5001 RK |
2226 | {s%A2i|s%A2wi} %0,%1,%h2") |
2227 | ||
25c341fa | 2228 | (define_insn "lshrsi3_no_power" |
ca7f5001 RK |
2229 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2230 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2231 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 2232 | "! TARGET_POWER" |
ca7f5001 | 2233 | "srw%I2 %0,%1,%2") |
1fd4e8c1 RK |
2234 | |
2235 | (define_insn "" | |
2236 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 2237 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
2238 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
2239 | (const_int 0))) | |
2240 | (clobber (match_scratch:SI 3 "=r,r")) | |
2241 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 2242 | "TARGET_POWER" |
1fd4e8c1 RK |
2243 | "@ |
2244 | sre. %3,%1,%2 | |
ca7f5001 RK |
2245 | {s%A2i.|s%A2wi.} %3,%1,%h2" |
2246 | [(set_attr "type" "delayed_compare")]) | |
2247 | ||
2248 | (define_insn "" | |
2249 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
2250 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2251 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
2252 | (const_int 0))) | |
2253 | (clobber (match_scratch:SI 3 "=r"))] | |
25c341fa | 2254 | "! TARGET_POWER" |
ca7f5001 | 2255 | "srw%I2. %3,%1,%2" |
1fd4e8c1 RK |
2256 | [(set_attr "type" "delayed_compare")]) |
2257 | ||
2258 | (define_insn "" | |
2259 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 2260 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
2261 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
2262 | (const_int 0))) | |
cd2b37d9 | 2263 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
2264 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
2265 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 2266 | "TARGET_POWER" |
1fd4e8c1 RK |
2267 | "@ |
2268 | sre. %0,%1,%2 | |
ca7f5001 RK |
2269 | {s%A2i.|s%A2wi.} %0,%1,%h2" |
2270 | [(set_attr "type" "delayed_compare")]) | |
2271 | ||
2272 | (define_insn "" | |
2273 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
2274 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2275 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
2276 | (const_int 0))) | |
2277 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2278 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
25c341fa | 2279 | "! TARGET_POWER" |
ca7f5001 | 2280 | "srw%I2. %0,%1,%2" |
1fd4e8c1 RK |
2281 | [(set_attr "type" "delayed_compare")]) |
2282 | ||
2283 | (define_insn "" | |
cd2b37d9 RK |
2284 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2285 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2286 | (match_operand:SI 2 "const_int_operand" "i")) |
2287 | (match_operand:SI 3 "mask_operand" "L")))] | |
2288 | "includes_rshift_p (operands[2], operands[3])" | |
ca7f5001 | 2289 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
2290 | |
2291 | (define_insn "" | |
2292 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
2293 | (compare:CC | |
cd2b37d9 | 2294 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2295 | (match_operand:SI 2 "const_int_operand" "i")) |
2296 | (match_operand:SI 3 "mask_operand" "L")) | |
2297 | (const_int 0))) | |
2298 | (clobber (match_scratch:SI 4 "=r"))] | |
2299 | "includes_rshift_p (operands[2], operands[3])" | |
ca7f5001 | 2300 | "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3" |
1fd4e8c1 RK |
2301 | [(set_attr "type" "delayed_compare")]) |
2302 | ||
2303 | (define_insn "" | |
2304 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
2305 | (compare:CC | |
cd2b37d9 | 2306 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2307 | (match_operand:SI 2 "const_int_operand" "i")) |
2308 | (match_operand:SI 3 "mask_operand" "L")) | |
2309 | (const_int 0))) | |
cd2b37d9 | 2310 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2311 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
2312 | "includes_rshift_p (operands[2], operands[3])" | |
ca7f5001 | 2313 | "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3" |
1fd4e8c1 RK |
2314 | [(set_attr "type" "delayed_compare")]) |
2315 | ||
2316 | (define_insn "" | |
cd2b37d9 | 2317 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2318 | (zero_extend:SI |
2319 | (subreg:QI | |
cd2b37d9 | 2320 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2321 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
2322 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" | |
ca7f5001 | 2323 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
2324 | |
2325 | (define_insn "" | |
2326 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
2327 | (compare:CC | |
2328 | (zero_extend:SI | |
2329 | (subreg:QI | |
cd2b37d9 | 2330 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2331 | (match_operand:SI 2 "const_int_operand" "i")) 0)) |
2332 | (const_int 0))) | |
2333 | (clobber (match_scratch:SI 3 "=r"))] | |
2334 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" | |
ca7f5001 | 2335 | "{rlinm.|rlwinm.} %3,%1,%s2,0xff" |
1fd4e8c1 RK |
2336 | [(set_attr "type" "delayed_compare")]) |
2337 | ||
2338 | (define_insn "" | |
2339 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
2340 | (compare:CC | |
2341 | (zero_extend:SI | |
2342 | (subreg:QI | |
cd2b37d9 | 2343 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2344 | (match_operand:SI 2 "const_int_operand" "i")) 0)) |
2345 | (const_int 0))) | |
cd2b37d9 | 2346 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2347 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
2348 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" | |
ca7f5001 | 2349 | "{rlinm.|rlwinm.} %0,%1,%s2,0xff" |
1fd4e8c1 RK |
2350 | [(set_attr "type" "delayed_compare")]) |
2351 | ||
2352 | (define_insn "" | |
cd2b37d9 | 2353 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2354 | (zero_extend:SI |
2355 | (subreg:HI | |
cd2b37d9 | 2356 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2357 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
2358 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" | |
ca7f5001 | 2359 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
2360 | |
2361 | (define_insn "" | |
2362 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
2363 | (compare:CC | |
2364 | (zero_extend:SI | |
2365 | (subreg:HI | |
cd2b37d9 | 2366 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2367 | (match_operand:SI 2 "const_int_operand" "i")) 0)) |
2368 | (const_int 0))) | |
2369 | (clobber (match_scratch:SI 3 "=r"))] | |
2370 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" | |
ca7f5001 | 2371 | "{rlinm.|rlwinm.} %3,%1,%s2,0xffff" |
1fd4e8c1 RK |
2372 | [(set_attr "type" "delayed_compare")]) |
2373 | ||
2374 | (define_insn "" | |
2375 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
2376 | (compare:CC | |
2377 | (zero_extend:SI | |
2378 | (subreg:HI | |
cd2b37d9 | 2379 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2380 | (match_operand:SI 2 "const_int_operand" "i")) 0)) |
2381 | (const_int 0))) | |
cd2b37d9 | 2382 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2383 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
2384 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" | |
ca7f5001 | 2385 | "{rlinm.|rlwinm.} %0,%1,%s2,0xffff" |
1fd4e8c1 RK |
2386 | [(set_attr "type" "delayed_compare")]) |
2387 | ||
2388 | (define_insn "" | |
cd2b37d9 | 2389 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 2390 | (const_int 1) |
cd2b37d9 RK |
2391 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
2392 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 2393 | (const_int 31)))] |
ca7f5001 | 2394 | "TARGET_POWER" |
1fd4e8c1 RK |
2395 | "rrib %0,%1,%2") |
2396 | ||
2397 | (define_insn "" | |
cd2b37d9 | 2398 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 2399 | (const_int 1) |
cd2b37d9 RK |
2400 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
2401 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 2402 | (const_int 31)))] |
ca7f5001 | 2403 | "TARGET_POWER" |
1fd4e8c1 RK |
2404 | "rrib %0,%1,%2") |
2405 | ||
2406 | (define_insn "" | |
cd2b37d9 | 2407 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 2408 | (const_int 1) |
cd2b37d9 RK |
2409 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
2410 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2411 | (const_int 1) |
2412 | (const_int 0)))] | |
ca7f5001 | 2413 | "TARGET_POWER" |
1fd4e8c1 RK |
2414 | "rrib %0,%1,%2") |
2415 | ||
ca7f5001 RK |
2416 | (define_expand "ashrsi3" |
2417 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2418 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2419 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
2420 | "" | |
2421 | " | |
2422 | { | |
2423 | if (TARGET_POWER) | |
2424 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
2425 | else | |
25c341fa | 2426 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2427 | DONE; |
2428 | }") | |
2429 | ||
2430 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
2431 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2432 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
2433 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
2434 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 2435 | "TARGET_POWER" |
1fd4e8c1 RK |
2436 | "@ |
2437 | srea %0,%1,%2 | |
ca7f5001 RK |
2438 | {srai|srawi} %0,%1,%h2") |
2439 | ||
25c341fa | 2440 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
2441 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2442 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2443 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 2444 | "! TARGET_POWER" |
ca7f5001 | 2445 | "sraw%I2 %0,%1,%2") |
1fd4e8c1 RK |
2446 | |
2447 | (define_insn "" | |
2448 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 2449 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
2450 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
2451 | (const_int 0))) | |
2452 | (clobber (match_scratch:SI 3 "=r,r")) | |
2453 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 2454 | "TARGET_POWER" |
1fd4e8c1 RK |
2455 | "@ |
2456 | srea. %3,%1,%2 | |
ca7f5001 RK |
2457 | {srai.|srawi.} %3,%1,%h2" |
2458 | [(set_attr "type" "delayed_compare")]) | |
2459 | ||
2460 | (define_insn "" | |
2461 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
2462 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2463 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
2464 | (const_int 0))) | |
2465 | (clobber (match_scratch:SI 3 "=r"))] | |
25c341fa | 2466 | "! TARGET_POWER" |
ca7f5001 | 2467 | "sraw%I2. %3,%1,%2" |
1fd4e8c1 RK |
2468 | [(set_attr "type" "delayed_compare")]) |
2469 | ||
2470 | (define_insn "" | |
2471 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 2472 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
2473 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
2474 | (const_int 0))) | |
cd2b37d9 | 2475 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
2476 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
2477 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 2478 | "TARGET_POWER" |
1fd4e8c1 RK |
2479 | "@ |
2480 | srea. %0,%1,%2 | |
7f340546 | 2481 | {srai.|srawi.} %0,%1,%h2" |
1fd4e8c1 RK |
2482 | [(set_attr "type" "delayed_compare")]) |
2483 | ||
ca7f5001 RK |
2484 | (define_insn "" |
2485 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
2486 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2487 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
2488 | (const_int 0))) | |
2489 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2490 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
25c341fa | 2491 | "! TARGET_POWER" |
ca7f5001 RK |
2492 | "sraw%I2. %0,%1,%2" |
2493 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
2494 | \f |
2495 | ;; Floating-point insns, excluding normal data motion. | |
2496 | ;; | |
ca7f5001 RK |
2497 | ;; PowerPC has a full set of single-precision floating point instructions. |
2498 | ;; | |
2499 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
2500 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
2501 | ;; The only conversions we will do will be when storing to memory. In that | |
2502 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
2503 | ;; |
2504 | ;; Note that when we store into a single-precision memory location, we need to | |
2505 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
2506 | ;; need a scratch register for the frsp. But this is difficult when the store | |
2507 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
2508 | ;; this case, we just lose precision that we would have otherwise gotten but | |
2509 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
2510 | ||
2511 | (define_insn "extendsfdf2" | |
cd2b37d9 RK |
2512 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2513 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
2514 | "" |
2515 | "* | |
2516 | { | |
2517 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
2518 | return \"\"; | |
2519 | else | |
2520 | return \"fmr %0,%1\"; | |
2521 | }" | |
2522 | [(set_attr "type" "fp")]) | |
2523 | ||
2524 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
2525 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2526 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 | 2527 | "" |
dcac138d | 2528 | "frsp %0,%1" |
1fd4e8c1 RK |
2529 | [(set_attr "type" "fp")]) |
2530 | ||
2531 | (define_insn "negsf2" | |
cd2b37d9 RK |
2532 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2533 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
2534 | "" |
2535 | "fneg %0,%1" | |
2536 | [(set_attr "type" "fp")]) | |
2537 | ||
2538 | (define_insn "abssf2" | |
cd2b37d9 RK |
2539 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2540 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
2541 | "" |
2542 | "fabs %0,%1" | |
2543 | [(set_attr "type" "fp")]) | |
2544 | ||
2545 | (define_insn "" | |
cd2b37d9 RK |
2546 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2547 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
1fd4e8c1 RK |
2548 | "" |
2549 | "fnabs %0,%1" | |
2550 | [(set_attr "type" "fp")]) | |
2551 | ||
ca7f5001 RK |
2552 | (define_expand "addsf3" |
2553 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
2554 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
2555 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
2556 | "" | |
2557 | "") | |
2558 | ||
2559 | (define_insn "" | |
cd2b37d9 RK |
2560 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2561 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2562 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
b26c8351 RK |
2563 | "TARGET_POWERPC" |
2564 | "fadds %0,%1,%2" | |
ca7f5001 RK |
2565 | [(set_attr "type" "fp")]) |
2566 | ||
2567 | (define_insn "" | |
2568 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2569 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2570 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
8ffd9c51 | 2571 | "! TARGET_POWERPC" |
b26c8351 | 2572 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
2573 | [(set_attr "type" "fp")]) |
2574 | ||
2575 | (define_expand "subsf3" | |
2576 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
2577 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
2578 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
1fd4e8c1 | 2579 | "" |
ca7f5001 RK |
2580 | "") |
2581 | ||
2582 | (define_insn "" | |
2583 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2584 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
2585 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
b26c8351 RK |
2586 | "TARGET_POWERPC" |
2587 | "fsubs %0,%1,%2" | |
1fd4e8c1 RK |
2588 | [(set_attr "type" "fp")]) |
2589 | ||
ca7f5001 | 2590 | (define_insn "" |
cd2b37d9 RK |
2591 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2592 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
2593 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
8ffd9c51 | 2594 | "! TARGET_POWERPC" |
b26c8351 | 2595 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
2596 | [(set_attr "type" "fp")]) |
2597 | ||
2598 | (define_expand "mulsf3" | |
2599 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
2600 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
2601 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
1fd4e8c1 | 2602 | "" |
ca7f5001 RK |
2603 | "") |
2604 | ||
2605 | (define_insn "" | |
2606 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2607 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2608 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
b26c8351 RK |
2609 | "TARGET_POWERPC" |
2610 | "fmuls %0,%1,%2" | |
1fd4e8c1 RK |
2611 | [(set_attr "type" "fp")]) |
2612 | ||
ca7f5001 | 2613 | (define_insn "" |
cd2b37d9 RK |
2614 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2615 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2616 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
8ffd9c51 | 2617 | "! TARGET_POWERPC" |
b26c8351 | 2618 | "{fm|fmul} %0,%1,%2" |
1fd4e8c1 RK |
2619 | [(set_attr "type" "fp")]) |
2620 | ||
ca7f5001 RK |
2621 | (define_expand "divsf3" |
2622 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
2623 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
2624 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
2625 | "" | |
2626 | "") | |
2627 | ||
2628 | (define_insn "" | |
cd2b37d9 RK |
2629 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2630 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
2631 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
b26c8351 RK |
2632 | "TARGET_POWERPC" |
2633 | "fdivs %0,%1,%2" | |
ca7f5001 RK |
2634 | [(set_attr "type" "sdiv")]) |
2635 | ||
2636 | (define_insn "" | |
2637 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2638 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
2639 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
8ffd9c51 | 2640 | "! TARGET_POWERPC" |
b26c8351 | 2641 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 2642 | [(set_attr "type" "sdiv")]) |
1fd4e8c1 RK |
2643 | |
2644 | (define_insn "" | |
cd2b37d9 RK |
2645 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2646 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2647 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
2648 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
b26c8351 RK |
2649 | "TARGET_POWERPC" |
2650 | "fmadds %0,%1,%2,%3" | |
ca7f5001 RK |
2651 | [(set_attr "type" "fp")]) |
2652 | ||
2653 | (define_insn "" | |
2654 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2655 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2656 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
2657 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
8ffd9c51 | 2658 | "! TARGET_POWERPC" |
b26c8351 | 2659 | "{fma|fmadd} %0,%1,%2,%3" |
1fd4e8c1 RK |
2660 | [(set_attr "type" "fp")]) |
2661 | ||
2662 | (define_insn "" | |
cd2b37d9 RK |
2663 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2664 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2665 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
2666 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
b26c8351 RK |
2667 | "TARGET_POWERPC" |
2668 | "fmsubs %0,%1,%2,%3" | |
ca7f5001 RK |
2669 | [(set_attr "type" "fp")]) |
2670 | ||
2671 | (define_insn "" | |
2672 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2673 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2674 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
2675 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
8ffd9c51 | 2676 | "! TARGET_POWERPC" |
b26c8351 | 2677 | "{fms|fmsub} %0,%1,%2,%3" |
1fd4e8c1 RK |
2678 | [(set_attr "type" "fp")]) |
2679 | ||
2680 | (define_insn "" | |
cd2b37d9 RK |
2681 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2682 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2683 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
2684 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
b26c8351 RK |
2685 | "TARGET_POWERPC" |
2686 | "fnmadds %0,%1,%2,%3" | |
ca7f5001 RK |
2687 | [(set_attr "type" "fp")]) |
2688 | ||
2689 | (define_insn "" | |
2690 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2691 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2692 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
2693 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
8ffd9c51 | 2694 | "! TARGET_POWERPC" |
b26c8351 | 2695 | "{fnma|fnmadd} %0,%1,%2,%3" |
1fd4e8c1 RK |
2696 | [(set_attr "type" "fp")]) |
2697 | ||
2698 | (define_insn "" | |
cd2b37d9 RK |
2699 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
2700 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2701 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
2702 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
b26c8351 RK |
2703 | "TARGET_POWERPC" |
2704 | "fnmsubs %0,%1,%2,%3" | |
ca7f5001 RK |
2705 | [(set_attr "type" "fp")]) |
2706 | ||
2707 | (define_insn "" | |
2708 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2709 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
2710 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
2711 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
8ffd9c51 | 2712 | "! TARGET_POWERPC" |
b26c8351 | 2713 | "{fnms|fnmsub} %0,%1,%2,%3" |
1fd4e8c1 RK |
2714 | [(set_attr "type" "fp")]) |
2715 | ||
ca7f5001 RK |
2716 | (define_expand "sqrtsf2" |
2717 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
2718 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a473029f | 2719 | "TARGET_PPC_GPOPT || TARGET_POWER2" |
ca7f5001 RK |
2720 | "") |
2721 | ||
2722 | (define_insn "" | |
2723 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2724 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a473029f | 2725 | "TARGET_PPC_GPOPT" |
ca7f5001 RK |
2726 | "fsqrts %0,%1" |
2727 | [(set_attr "type" "ssqrt")]) | |
2728 | ||
2729 | (define_insn "" | |
2730 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2731 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
2732 | "TARGET_POWER2" | |
2733 | "fsqrt %0,%1" | |
2734 | [(set_attr "type" "dsqrt")]) | |
2735 | ||
8e871c05 RK |
2736 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel |
2737 | ;; instruction and some auxiliary computations. Then we just have a single | |
2738 | ;; DEFINE_INSN for fsel and the define_splits to make them if made by | |
2739 | ;; combine. | |
2740 | (define_expand "maxsf3" | |
2741 | [(set (match_dup 3) | |
2742 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
2743 | (match_operand:SF 2 "gpc_reg_operand" ""))) | |
2744 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
2745 | (if_then_else:SF (ge (match_dup 3) | |
2746 | (const_int 0)) | |
2747 | (match_dup 1) | |
2748 | (match_dup 2)))] | |
a473029f | 2749 | "TARGET_PPC_GFXOPT" |
8e871c05 RK |
2750 | " |
2751 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 2752 | |
8e871c05 RK |
2753 | (define_split |
2754 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
2755 | (smax:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 2756 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 2757 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
a473029f | 2758 | "TARGET_PPC_GFXOPT" |
8e871c05 RK |
2759 | [(set (match_dup 3) |
2760 | (minus:SF (match_dup 1) (match_dup 2))) | |
2761 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
2762 | (if_then_else:SF (ge (match_dup 3) | |
2763 | (const_int 0)) | |
2764 | (match_dup 1) | |
2765 | (match_dup 2)))] | |
2766 | "") | |
2f607b94 | 2767 | |
8e871c05 RK |
2768 | (define_expand "minsf3" |
2769 | [(set (match_dup 3) | |
2770 | (minus:SF (match_operand:SF 2 "gpc_reg_operand" "") | |
2771 | (match_operand:SF 1 "gpc_reg_operand" ""))) | |
2772 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
2773 | (if_then_else:SF (ge (match_dup 3) | |
2774 | (const_int 0)) | |
2775 | (match_dup 1) | |
2776 | (match_dup 2)))] | |
a473029f | 2777 | "TARGET_PPC_GFXOPT" |
8e871c05 RK |
2778 | " |
2779 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 2780 | |
8e871c05 RK |
2781 | (define_split |
2782 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
2783 | (smin:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 2784 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 2785 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
a473029f | 2786 | "TARGET_PPC_GFXOPT" |
8e871c05 RK |
2787 | [(set (match_dup 3) |
2788 | (minus:SF (match_dup 2) (match_dup 1))) | |
2789 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
2790 | (if_then_else:SF (ge (match_dup 3) | |
2791 | (const_int 0)) | |
2792 | (match_dup 1) | |
2793 | (match_dup 2)))] | |
2794 | "") | |
2f607b94 | 2795 | |
8e871c05 RK |
2796 | (define_insn "" |
2797 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
2798 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
2799 | (const_int 0)) | |
2800 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
2801 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a473029f | 2802 | "TARGET_PPC_GFXOPT" |
8e871c05 RK |
2803 | "fsel %0,%1,%2,%3" |
2804 | [(set_attr "type" "fp")]) | |
2f607b94 | 2805 | |
1fd4e8c1 | 2806 | (define_insn "negdf2" |
cd2b37d9 RK |
2807 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2808 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
2809 | "" |
2810 | "fneg %0,%1" | |
2811 | [(set_attr "type" "fp")]) | |
2812 | ||
2813 | (define_insn "absdf2" | |
cd2b37d9 RK |
2814 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2815 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
2816 | "" |
2817 | "fabs %0,%1" | |
2818 | [(set_attr "type" "fp")]) | |
2819 | ||
2820 | (define_insn "" | |
cd2b37d9 RK |
2821 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2822 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
1fd4e8c1 RK |
2823 | "" |
2824 | "fnabs %0,%1" | |
2825 | [(set_attr "type" "fp")]) | |
2826 | ||
2827 | (define_insn "adddf3" | |
cd2b37d9 RK |
2828 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2829 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
2830 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 | 2831 | "" |
ca7f5001 | 2832 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
2833 | [(set_attr "type" "fp")]) |
2834 | ||
2835 | (define_insn "subdf3" | |
cd2b37d9 RK |
2836 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2837 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
2838 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 | 2839 | "" |
ca7f5001 | 2840 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
2841 | [(set_attr "type" "fp")]) |
2842 | ||
2843 | (define_insn "muldf3" | |
cd2b37d9 RK |
2844 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2845 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
2846 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 | 2847 | "" |
ca7f5001 | 2848 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 2849 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
2850 | |
2851 | (define_insn "divdf3" | |
cd2b37d9 RK |
2852 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2853 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
2854 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 | 2855 | "" |
ca7f5001 | 2856 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 2857 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
2858 | |
2859 | (define_insn "" | |
cd2b37d9 RK |
2860 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2861 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
2862 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
2863 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
1fd4e8c1 | 2864 | "" |
ca7f5001 | 2865 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 2866 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
2867 | |
2868 | (define_insn "" | |
cd2b37d9 RK |
2869 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2870 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
2871 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
2872 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
1fd4e8c1 | 2873 | "" |
ca7f5001 | 2874 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 2875 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
2876 | |
2877 | (define_insn "" | |
cd2b37d9 RK |
2878 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2879 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
2880 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
2881 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
1fd4e8c1 | 2882 | "" |
ca7f5001 | 2883 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 2884 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
2885 | |
2886 | (define_insn "" | |
cd2b37d9 RK |
2887 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
2888 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
2889 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
2890 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
1fd4e8c1 | 2891 | "" |
ca7f5001 | 2892 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 2893 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
2894 | |
2895 | (define_insn "sqrtdf2" | |
2896 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
2897 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a473029f | 2898 | "TARGET_PPC_GPOPT || TARGET_POWER2" |
ca7f5001 RK |
2899 | "fsqrt %0,%1" |
2900 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 2901 | |
8e871c05 RK |
2902 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a fsel |
2903 | ;; instruction and some auxiliary computations. Then we just have a single | |
2904 | ;; DEFINE_INSN for fsel and the define_splits to make them if made by | |
2905 | ;; combine. | |
b77dfefc | 2906 | |
8e871c05 RK |
2907 | (define_expand "maxdf3" |
2908 | [(set (match_dup 3) | |
2909 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
2910 | (match_operand:DF 2 "gpc_reg_operand" ""))) | |
2911 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
2912 | (if_then_else:DF (ge (match_dup 3) | |
2913 | (const_int 0)) | |
2914 | (match_dup 1) | |
2915 | (match_dup 2)))] | |
a473029f | 2916 | "TARGET_PPC_GFXOPT" |
8e871c05 RK |
2917 | " |
2918 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 2919 | |
8e871c05 RK |
2920 | (define_split |
2921 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
2922 | (smax:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 2923 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 2924 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
a473029f | 2925 | "TARGET_PPC_GFXOPT" |
8e871c05 RK |
2926 | [(set (match_dup 3) |
2927 | (minus:DF (match_dup 1) (match_dup 2))) | |
2928 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
2929 | (if_then_else:DF (ge (match_dup 3) | |
2930 | (const_int 0)) | |
2931 | (match_dup 1) | |
2932 | (match_dup 2)))] | |
2933 | "") | |
b77dfefc | 2934 | |
8e871c05 RK |
2935 | (define_expand "mindf3" |
2936 | [(set (match_dup 3) | |
2937 | (minus:DF (match_operand:DF 2 "gpc_reg_operand" "") | |
2938 | (match_operand:DF 1 "gpc_reg_operand" ""))) | |
2939 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
2940 | (if_then_else:DF (ge (match_dup 3) | |
2941 | (const_int 0)) | |
2942 | (match_dup 1) | |
2943 | (match_dup 2)))] | |
a473029f | 2944 | "TARGET_PPC_GFXOPT" |
8e871c05 RK |
2945 | " |
2946 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 2947 | |
8e871c05 RK |
2948 | (define_split |
2949 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
2950 | (smin:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 2951 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 2952 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
a473029f | 2953 | "TARGET_PPC_GFXOPT" |
8e871c05 RK |
2954 | [(set (match_dup 3) |
2955 | (minus:DF (match_dup 2) (match_dup 1))) | |
2956 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
2957 | (if_then_else:DF (ge (match_dup 3) | |
2958 | (const_int 0)) | |
2959 | (match_dup 1) | |
2960 | (match_dup 2)))] | |
2961 | "") | |
b77dfefc | 2962 | |
8e871c05 RK |
2963 | (define_insn "" |
2964 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
2965 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
2966 | (const_int 0)) | |
2967 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
2968 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a473029f | 2969 | "TARGET_PPC_GFXOPT" |
8e871c05 RK |
2970 | "fsel %0,%1,%2,%3" |
2971 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
2972 | \f |
2973 | ;; Conversions to and from floating-point. | |
2974 | (define_expand "floatsidf2" | |
2975 | [(set (match_dup 2) | |
2976 | (plus:DI (zero_extend:DI | |
cd2b37d9 | 2977 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
2978 | (match_dup 3))) |
2979 | (match_dup 4))) | |
cd2b37d9 | 2980 | (set (match_operand:DF 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
2981 | (minus:DF (subreg:DF (match_dup 2) 0) |
2982 | (match_dup 5)))] | |
2983 | "" | |
2984 | " | |
2985 | { | |
2986 | #if HOST_BITS_PER_INT != BITS_PER_WORD | |
2987 | /* Maybe someone can figure out how to do this in that case. I don't | |
2988 | want to right now. */ | |
2989 | abort (); | |
2990 | #endif | |
2991 | ||
2992 | operands[2] = gen_reg_rtx (DImode); | |
2993 | operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000); | |
2994 | operands[4] = immed_double_const (0, 0x43300000, DImode); | |
2995 | operands[5] = force_reg (DFmode, immed_double_const (0x43300000, | |
2996 | 0x80000000, DFmode)); | |
2997 | }") | |
2998 | ||
2999 | (define_expand "floatunssidf2" | |
3000 | [(set (match_dup 2) | |
cd2b37d9 | 3001 | (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) |
1fd4e8c1 | 3002 | (match_dup 3))) |
cd2b37d9 | 3003 | (set (match_operand:DF 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3004 | (minus:DF (subreg:DF (match_dup 2) 0) |
3005 | (match_dup 4)))] | |
3006 | "" | |
3007 | " | |
3008 | { | |
3009 | #if HOST_BITS_PER_INT != BITS_PER_WORD | |
3010 | /* Maybe someone can figure out how to do this in that case. I don't | |
3011 | want to right now. */ | |
3012 | abort (); | |
3013 | #endif | |
3014 | ||
3015 | operands[2] = gen_reg_rtx (DImode); | |
3016 | operands[3] = immed_double_const (0, 0x43300000, DImode); | |
3017 | operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode)); | |
3018 | }") | |
3019 | ||
3020 | ;; For the above two cases, we always split. | |
3021 | (define_split | |
cd2b37d9 | 3022 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 3023 | (plus:DI (zero_extend:DI |
cd2b37d9 | 3024 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3025 | (match_operand:SI 2 "logical_operand" ""))) |
3026 | (match_operand:DI 3 "immediate_operand" "")))] | |
3027 | "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD | |
3028 | && GET_CODE (operands[3]) == CONST_DOUBLE | |
3029 | && CONST_DOUBLE_LOW (operands[3]) == 0" | |
3030 | [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2))) | |
3031 | (set (match_dup 4) (match_dup 5))] | |
3032 | " | |
3033 | { operands[4] = operand_subword (operands[0], 0, 0, DImode); | |
3034 | operands[5] = operand_subword (operands[3], 0, 0, DImode); | |
3035 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3036 | }") | |
3037 | ||
3038 | (define_insn "" | |
cd2b37d9 | 3039 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 3040 | (plus:DI (zero_extend:DI |
cd2b37d9 | 3041 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
1fd4e8c1 RK |
3042 | (match_operand:SI 2 "logical_operand" "rKJ"))) |
3043 | (match_operand:DI 3 "immediate_operand" "n")))] | |
3044 | "HOST_BITS_PER_INT == BITS_PER_WORD | |
3045 | && GET_CODE (operands[3]) == CONST_DOUBLE | |
3046 | && CONST_DOUBLE_LOW (operands[3]) == 0" | |
baf97f86 RK |
3047 | "#" |
3048 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
3049 | |
3050 | (define_split | |
cd2b37d9 RK |
3051 | [(set (match_operand:DI 0 "gpc_reg_operand" "=") |
3052 | (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1fd4e8c1 RK |
3053 | (match_operand:DI 2 "immediate_operand" "")))] |
3054 | "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD | |
3055 | && GET_CODE (operands[2]) == CONST_DOUBLE | |
3056 | && CONST_DOUBLE_LOW (operands[2]) == 0" | |
3057 | [(set (match_dup 3) (match_dup 4)) | |
3058 | (set (match_dup 5) (match_dup 1))] | |
3059 | " | |
3060 | { operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3061 | operands[4] = operand_subword (operands[2], 0, 0, DImode); | |
3062 | operands[5] = operand_subword (operands[0], 1, 0, DImode); | |
3063 | ||
3064 | if (rtx_equal_p (operands[1], operands[5])) | |
3065 | { | |
3066 | emit_move_insn (operands[3], operands[4]); | |
3067 | DONE; | |
3068 | } | |
c283c989 RK |
3069 | |
3070 | if (rtx_equal_p (operands[1], operands[3])) | |
3071 | { | |
3072 | rtx temp; | |
3073 | ||
3074 | temp = operands[3]; operands[3] = operands[5]; operands[5] = temp; | |
3075 | temp = operands[4]; operands[4] = operands[1]; operands[1] = temp; | |
3076 | } | |
1fd4e8c1 RK |
3077 | }") |
3078 | ||
3079 | (define_insn "" | |
cd2b37d9 RK |
3080 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3081 | (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
3082 | (match_operand:DI 2 "immediate_operand" "n")))] |
3083 | "HOST_BITS_PER_INT == BITS_PER_WORD | |
3084 | && GET_CODE (operands[2]) == CONST_DOUBLE | |
3085 | && CONST_DOUBLE_LOW (operands[2]) == 0" | |
baf97f86 RK |
3086 | "#" |
3087 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
3088 | |
3089 | (define_expand "fix_truncdfsi2" | |
cd2b37d9 | 3090 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
b542afe9 | 3091 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
3092 | "" |
3093 | " | |
3094 | { | |
8ffd9c51 RK |
3095 | if (TARGET_POWER2 || TARGET_POWERPC) |
3096 | { | |
3097 | rtx stack_slot, temp = gen_reg_rtx (DImode); | |
3098 | emit_insn (gen_fpcvtsi (temp, operands[1])); | |
3099 | stack_slot = gen_rtx (MEM, DImode, | |
3100 | plus_constant (stack_pointer_rtx, 8)); | |
3101 | emit_move_insn (stack_slot, temp); | |
3102 | emit_move_insn (operands[0], | |
3103 | operand_subword (stack_slot, 1, 0, DImode)); | |
3104 | DONE; | |
3105 | } | |
3106 | else | |
3107 | { | |
3108 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
3109 | gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC))); | |
3110 | DONE; | |
3111 | } | |
1fd4e8c1 RK |
3112 | }") |
3113 | ||
8ffd9c51 RK |
3114 | (define_insn "fpcvtsi" |
3115 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
3116 | (sign_extend:DI | |
3117 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
3118 | "TARGET_POWER2 || TARGET_POWERPC" | |
3119 | "{fcirz|fctiwz} %0,%1" | |
3120 | [(set_attr "type" "fp")]) | |
deb9225a | 3121 | |
1fd4e8c1 | 3122 | (define_expand "fixuns_truncdfsi2" |
cd2b37d9 | 3123 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
b542afe9 | 3124 | (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] |
8ffd9c51 | 3125 | "! TARGET_POWER2 && ! TARGET_POWERPC" |
1fd4e8c1 RK |
3126 | " |
3127 | { | |
3128 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
3c64f04b | 3129 | gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC))); |
1fd4e8c1 RK |
3130 | DONE; |
3131 | }") | |
3132 | ||
1fd4e8c1 RK |
3133 | (define_expand "trunc_call" |
3134 | [(parallel [(set (match_operand:SI 0 "" "") | |
b542afe9 | 3135 | (fix:SI (match_operand:DF 1 "" ""))) |
1fd4e8c1 RK |
3136 | (use (match_operand:SI 2 "" ""))])] |
3137 | "" | |
3138 | " | |
3139 | { | |
3140 | rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); | |
3141 | rtx first = XVECEXP (insns, 0, 0); | |
3142 | rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); | |
3143 | ||
3144 | REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last, | |
3145 | REG_NOTES (first)); | |
3146 | REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last)); | |
3147 | ||
3148 | emit_insn (insns); | |
3149 | DONE; | |
3150 | }") | |
3151 | ||
3152 | (define_expand "trunc_call_rtl" | |
cd2b37d9 | 3153 | [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) |
1fd4e8c1 RK |
3154 | (use (reg:DF 33)) |
3155 | (parallel [(set (reg:SI 3) | |
3156 | (call (mem:SI (match_operand 2 "" "")) (const_int 0))) | |
3157 | (clobber (scratch:SI))]) | |
cd2b37d9 | 3158 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3159 | (reg:SI 3))] |
3160 | "" | |
3161 | " | |
3162 | { | |
3163 | rs6000_trunc_used = 1; | |
3164 | }") | |
a473029f RK |
3165 | |
3166 | (define_insn "floatdidf2" | |
3167 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
3168 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] | |
3169 | "TARGET_POWERPC64" | |
3170 | "fcfid %0,%1" | |
3171 | [(set_attr "type" "fp")]) | |
3172 | ||
3173 | (define_insn "fix_truncdfdi2" | |
3174 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
3175 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
3176 | "TARGET_POWERPC64" | |
3177 | "fctidz %0,%1" | |
3178 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
3179 | \f |
3180 | ;; Define the DImode operations that can be done in a small number | |
3181 | ;; of instructions. | |
ca7f5001 RK |
3182 | (define_expand "adddi3" |
3183 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
3184 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
3185 | (match_operand:DI 2 "reg_or_short_operand" "")))] | |
3186 | "" | |
3187 | " | |
3188 | { | |
51b8fc2c | 3189 | if (! TARGET_POWER && ! TARGET_POWERPC64 |
ca7f5001 RK |
3190 | && short_cint_operand (operands[2], DImode)) |
3191 | FAIL; | |
3192 | }") | |
3193 | ||
3194 | (define_insn "" | |
fa5679bb RK |
3195 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3196 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
3197 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))] | |
51b8fc2c | 3198 | "TARGET_POWER && ! TARGET_POWERPC64" |
fa5679bb | 3199 | "@ |
ca7f5001 RK |
3200 | {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2 |
3201 | {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1" | |
b19003d8 | 3202 | [(set_attr "length" "8")]) |
1fd4e8c1 | 3203 | |
ca7f5001 RK |
3204 | (define_insn "" |
3205 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3206 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
3207 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
51b8fc2c | 3208 | "! TARGET_POWER && ! TARGET_POWERPC64" |
ca7f5001 RK |
3209 | "addc %L0,%L1,%L2\;adde %0,%1,%2" |
3210 | [(set_attr "length" "8")]) | |
3211 | ||
3212 | (define_expand "subdi3" | |
fa5679bb RK |
3213 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3214 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
3215 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
1fd4e8c1 | 3216 | "" |
ca7f5001 RK |
3217 | " |
3218 | { | |
51b8fc2c | 3219 | if (! TARGET_POWER && ! TARGET_POWERPC64 |
ca7f5001 RK |
3220 | && short_cint_operand (operands[1], DImode)) |
3221 | FAIL; | |
3222 | }") | |
3223 | ||
3224 | (define_insn "" | |
3225 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
3226 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
3227 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
51b8fc2c | 3228 | "TARGET_POWER && ! TARGET_POWERPC64" |
fa5679bb | 3229 | "@ |
ca7f5001 RK |
3230 | {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 |
3231 | {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2" | |
b19003d8 | 3232 | [(set_attr "length" "8")]) |
1fd4e8c1 | 3233 | |
ca7f5001 RK |
3234 | (define_insn "" |
3235 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3236 | (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
3237 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
51b8fc2c | 3238 | "! TARGET_POWER && ! TARGET_POWERPC64" |
ca7f5001 RK |
3239 | "subfc %L0,%L2,%L1\;subfe %0,%2,%1" |
3240 | [(set_attr "length" "8")]) | |
3241 | ||
3242 | (define_expand "negdi2" | |
cd2b37d9 RK |
3243 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3244 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 3245 | "" |
ca7f5001 RK |
3246 | "") |
3247 | ||
3248 | (define_insn "" | |
3249 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3250 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 3251 | "! TARGET_POWERPC64" |
ca7f5001 RK |
3252 | "{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1" |
3253 | [(set_attr "length" "8")]) | |
3254 | ||
8ffd9c51 RK |
3255 | (define_expand "mulsidi3" |
3256 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
3257 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
3258 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
3259 | "" | |
3260 | " | |
3261 | { | |
3262 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
3263 | { | |
3264 | emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); | |
3265 | emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); | |
3266 | emit_insn (gen_mull_call ()); | |
3267 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
3268 | gen_rtx (REG, SImode, 3)); | |
3269 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), | |
3270 | gen_rtx (REG, SImode, 4)); | |
3271 | DONE; | |
3272 | } | |
3273 | else if (TARGET_POWER) | |
3274 | { | |
3275 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
3276 | DONE; | |
3277 | } | |
3278 | }") | |
deb9225a | 3279 | |
8ffd9c51 | 3280 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 3281 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 3282 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 3283 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 3284 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 3285 | "TARGET_POWER" |
b19003d8 | 3286 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
3287 | [(set_attr "type" "imul") |
3288 | (set_attr "length" "8")]) | |
deb9225a | 3289 | |
8ffd9c51 RK |
3290 | (define_insn "" |
3291 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3292 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
3293 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
3294 | "TARGET_POWERPC" | |
3295 | "mulhw %0,%1,%2\;mullw %L0,%1,%2" | |
3296 | [(set_attr "type" "imul") | |
3297 | (set_attr "length" "8")]) | |
deb9225a | 3298 | |
8ffd9c51 RK |
3299 | (define_expand "smulsi3_highpart" |
3300 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
3301 | (truncate:SI | |
3302 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
3303 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
3304 | (sign_extend:DI | |
3305 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
3306 | (const_int 32))))] | |
3307 | "" | |
3308 | " | |
3309 | { | |
3310 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
3311 | { | |
3312 | emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]); | |
3313 | emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]); | |
3314 | emit_insn (gen_mulh_call ()); | |
3315 | emit_move_insn (operands[0], gen_rtx (REG, SImode, 3)); | |
3316 | DONE; | |
3317 | } | |
3318 | else if (TARGET_POWER) | |
3319 | { | |
3320 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
3321 | DONE; | |
3322 | } | |
3323 | }") | |
deb9225a | 3324 | |
8ffd9c51 RK |
3325 | (define_insn "smulsi3_highpart_mq" |
3326 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3327 | (truncate:SI | |
3328 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
3329 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
3330 | (sign_extend:DI | |
3331 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
3332 | (const_int 32)))) | |
3333 | (clobber (match_scratch:SI 3 "=q"))] | |
3334 | "TARGET_POWER" | |
3335 | "mul %0,%1,%2" | |
3336 | [(set_attr "type" "imul")]) | |
deb9225a | 3337 | |
8ffd9c51 RK |
3338 | (define_insn "" |
3339 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3340 | (truncate:SI | |
3341 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
3342 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
3343 | (sign_extend:DI | |
3344 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
3345 | (const_int 32))))] | |
3346 | "TARGET_POWERPC" | |
3347 | "mulhw %0,%1,%2" | |
3348 | [(set_attr "type" "imul")]) | |
deb9225a | 3349 | |
8ffd9c51 RK |
3350 | (define_insn "umulsi3_highpart" |
3351 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3352 | (truncate:SI | |
3353 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
3354 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
3355 | (zero_extend:DI | |
3356 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
3357 | (const_int 32))))] | |
3358 | "TARGET_POWERPC" | |
3359 | "mulhwu %0,%1,%2" | |
3360 | [(set_attr "type" "imul")]) | |
1fd4e8c1 RK |
3361 | |
3362 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
3363 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
3364 | ;; why we have the strange constraints below. | |
3365 | (define_insn "ashldi3" | |
cd2b37d9 RK |
3366 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
3367 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
1fd4e8c1 RK |
3368 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) |
3369 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
ca7f5001 | 3370 | "TARGET_POWER" |
1fd4e8c1 | 3371 | "@ |
ca7f5001 | 3372 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} |
1fd4e8c1 RK |
3373 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 |
3374 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
b19003d8 RK |
3375 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" |
3376 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
3377 | |
3378 | (define_insn "lshrdi3" | |
cd2b37d9 RK |
3379 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r") |
3380 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
1fd4e8c1 RK |
3381 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) |
3382 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
ca7f5001 | 3383 | "TARGET_POWER" |
1fd4e8c1 | 3384 | "@ |
ca7f5001 | 3385 | {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2 |
46a48c7f RK |
3386 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
3387 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
b19003d8 RK |
3388 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" |
3389 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
3390 | |
3391 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
3392 | ;; just handle shifts by constants. | |
3393 | ||
3394 | (define_expand "ashrdi3" | |
a473029f | 3395 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "") |
2bee0449 RK |
3396 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") |
3397 | (match_operand:SI 2 "general_operand" ""))) | |
3398 | (clobber (match_scratch:SI 3 ""))])] | |
3399 | "TARGET_POWER" | |
1fd4e8c1 | 3400 | " |
2bee0449 | 3401 | { if (GET_CODE (operands[2]) != CONST_INT) |
1fd4e8c1 RK |
3402 | FAIL; |
3403 | }") | |
3404 | ||
2bee0449 | 3405 | (define_insn "" |
cd2b37d9 RK |
3406 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3407 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3408 | (match_operand:SI 2 "const_int_operand" "M,i"))) |
3409 | (clobber (match_scratch:SI 3 "=X,q"))] | |
ca7f5001 | 3410 | "TARGET_POWER" |
1fd4e8c1 | 3411 | "@ |
ca7f5001 | 3412 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 |
b19003d8 RK |
3413 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" |
3414 | [(set_attr "length" "8")]) | |
1fd4e8c1 | 3415 | \f |
a473029f RK |
3416 | ;; PowerPC64 DImode operations. |
3417 | ||
3418 | (define_insn "ffsdi2" | |
3419 | [(set (match_operand:DI 0 "register_operand" "=&r") | |
3420 | (ffs:DI (match_operand:DI 1 "register_operand" "r")))] | |
3421 | "TARGET_POWERPC64" | |
3422 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
3423 | [(set_attr "length" "16")]) | |
3424 | ||
3425 | (define_insn "muldi3" | |
3426 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3427 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
f63184ac | 3428 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
a473029f RK |
3429 | "TARGET_POWERPC64" |
3430 | "mulld %0,%1,%2" | |
3431 | [(set_attr "type" "imul")]) | |
3432 | ||
3433 | (define_insn "smuldi3_highpart" | |
3434 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3435 | (truncate:DI | |
3436 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
3437 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
3438 | (sign_extend:TI | |
3439 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
3440 | (const_int 64))))] | |
3441 | "TARGET_POWERPC64" | |
3442 | "mulhd %0,%1,%2" | |
3443 | [(set_attr "type" "imul")]) | |
3444 | ||
3445 | (define_insn "umuldi3_highpart" | |
3446 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3447 | (truncate:DI | |
3448 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
3449 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
3450 | (zero_extend:TI | |
3451 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
3452 | (const_int 64))))] | |
3453 | "TARGET_POWERPC64" | |
3454 | "mulhdu %0,%1,%2" | |
3455 | [(set_attr "type" "imul")]) | |
3456 | ||
3457 | (define_insn "divdi3" | |
3458 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3459 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
3460 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
3461 | "TARGET_POWERPC64" | |
3462 | "divd %0,%1,%2" | |
3463 | [(set_attr "type" "idiv")]) | |
3464 | ||
3465 | (define_insn "udivdi3" | |
3466 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3467 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
3468 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
3469 | "TARGET_POWERPC64" | |
3470 | "divdu %0,%1,%2" | |
3471 | [(set_attr "type" "idiv")]) | |
3472 | ||
3473 | (define_insn "rotldi3" | |
3474 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3475 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
3476 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
3477 | "TARGET_POWERPC64" | |
3478 | "rld%I2cl %0,%1,%h2,0") | |
3479 | ||
3480 | (define_insn "" | |
3481 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
3482 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
3483 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
3484 | (const_int 0))) | |
3485 | (clobber (match_scratch:DI 3 "=r"))] | |
3486 | "TARGET_POWERPC64" | |
3487 | "rld%I2cl. %3,%1,%h2,0" | |
3488 | [(set_attr "type" "delayed_compare")]) | |
3489 | ||
3490 | (define_insn "" | |
3491 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
3492 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
3493 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
3494 | (const_int 0))) | |
3495 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
3496 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
3497 | "TARGET_POWERPC64" | |
3498 | "rld%I2cl. %0,%1,%h2,0" | |
3499 | [(set_attr "type" "delayed_compare")]) | |
3500 | \f | |
1fd4e8c1 RK |
3501 | ;; Now define ways of moving data around. |
3502 | ;; | |
3503 | ;; For SI, we special-case integers that can't be loaded in one insn. We | |
3504 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
3505 | ;; and this is even supposed to be faster, but it is simpler not to get | |
3506 | ;; integers in the TOC. | |
3507 | (define_expand "movsi" | |
3508 | [(set (match_operand:SI 0 "general_operand" "") | |
3509 | (match_operand:SI 1 "any_operand" ""))] | |
3510 | "" | |
3511 | " | |
3512 | { | |
3513 | if (GET_CODE (operands[0]) != REG) | |
3514 | operands[1] = force_reg (SImode, operands[1]); | |
3515 | ||
78b8d850 RK |
3516 | if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT |
3517 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) | |
b45863ec | 3518 | { |
30a4619d RK |
3519 | /* If we are to limit the number of things we put in the TOC and |
3520 | this is a symbol plus a constant we can add in one insn, | |
3521 | just put the sumbol in the TOC and add the constant. Don't do | |
3522 | this if reload is in progress. */ | |
3523 | if (GET_CODE (operands[1]) == CONST | |
3524 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
3525 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
3526 | && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode) | |
3527 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF | |
3528 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
3529 | && ! side_effects_p (operands[0])) | |
3530 | { | |
3531 | rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0)); | |
3532 | rtx other = XEXP (XEXP (operands[1], 0), 1); | |
3533 | ||
3534 | emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other)); | |
3535 | DONE; | |
3536 | } | |
3537 | ||
b45863ec RK |
3538 | operands[1] = force_const_mem (SImode, operands[1]); |
3539 | if (! memory_address_p (SImode, XEXP (operands[1], 0)) | |
3540 | && ! reload_in_progress) | |
3541 | operands[1] = change_address (operands[1], SImode, | |
3542 | XEXP (operands[1], 0)); | |
3543 | } | |
1fd4e8c1 RK |
3544 | |
3545 | if (GET_CODE (operands[1]) == CONST_INT | |
3546 | && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 | |
3547 | && (INTVAL (operands[1]) & 0xffff) != 0) | |
3548 | { | |
3549 | emit_move_insn (operands[0], | |
3550 | gen_rtx (CONST_INT, VOIDmode, | |
3551 | INTVAL (operands[1]) & 0xffff0000)); | |
3552 | emit_insn (gen_iorsi3 (operands[0], operands[0], | |
3553 | gen_rtx (CONST_INT, VOIDmode, | |
3554 | INTVAL (operands[1]) & 0xffff))); | |
3555 | DONE; | |
3556 | } | |
3557 | }") | |
3558 | ||
3559 | (define_insn "" | |
324e52cc | 3560 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*q,*c*l,*h") |
e76e75bb | 3561 | (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r,0"))] |
ca7f5001 RK |
3562 | "TARGET_POWER && (gpc_reg_operand (operands[0], SImode) |
3563 | || gpc_reg_operand (operands[1], SImode))" | |
1fd4e8c1 | 3564 | "@ |
deb9225a | 3565 | mr %0,%1 |
ca7f5001 RK |
3566 | {l%U1%X1|lwz%U1%X1} %0,%1 |
3567 | {st%U0%X0|stw%U0%X0} %1,%0 | |
3568 | {cal %0,%1(0)|li %0,%1} | |
3569 | {cau %0,0,%u1|lis %0,%u1} | |
1fd4e8c1 | 3570 | mf%1 %0 |
5c23c401 | 3571 | mt%0 %1 |
e76e75bb RK |
3572 | mt%0 %1 |
3573 | cror 0,0,0" | |
324e52cc | 3574 | [(set_attr "type" "*,load,*,*,*,*,*,mtjmpr,*")]) |
1fd4e8c1 | 3575 | |
ca7f5001 RK |
3576 | (define_insn "" |
3577 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*h") | |
3578 | (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r"))] | |
25c341fa | 3579 | "! TARGET_POWER && (gpc_reg_operand (operands[0], SImode) |
ca7f5001 RK |
3580 | || gpc_reg_operand (operands[1], SImode))" |
3581 | "@ | |
3582 | mr %0,%1 | |
3583 | lwz%U1%X1 %0,%1 | |
3584 | stw%U0%X0 %1,%0 | |
3585 | li %0,%1 | |
3586 | lis %0,%u1 | |
3587 | mf%1 %0 | |
3588 | mt%0 %1" | |
8ffd9c51 | 3589 | [(set_attr "type" "*,load,*,*,*,*,mtjmpr")]) |
ca7f5001 | 3590 | |
77fa0940 RK |
3591 | ;; Split a load of a large constant into the appropriate two-insn |
3592 | ;; sequence. | |
3593 | ||
3594 | (define_split | |
3595 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
3596 | (match_operand:SI 1 "const_int_operand" ""))] | |
3597 | "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 | |
3598 | && (INTVAL (operands[1]) & 0xffff) != 0" | |
3599 | [(set (match_dup 0) | |
3600 | (match_dup 2)) | |
3601 | (set (match_dup 0) | |
3602 | (ior:SI (match_dup 0) | |
3603 | (match_dup 3)))] | |
3604 | " | |
3605 | { | |
3606 | operands[2] = gen_rtx (CONST_INT, VOIDmode, | |
3607 | INTVAL (operands[1]) & 0xffff0000); | |
3608 | operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff); | |
3609 | }") | |
3610 | ||
1fd4e8c1 RK |
3611 | (define_insn "" |
3612 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
cd2b37d9 | 3613 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3614 | (const_int 0))) |
cd2b37d9 | 3615 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] |
1fd4e8c1 | 3616 | "" |
deb9225a | 3617 | "mr. %0,%1" |
1fd4e8c1 RK |
3618 | [(set_attr "type" "compare")]) |
3619 | \f | |
3620 | (define_expand "movhi" | |
3621 | [(set (match_operand:HI 0 "general_operand" "") | |
3622 | (match_operand:HI 1 "any_operand" ""))] | |
3623 | "" | |
3624 | " | |
3625 | { | |
3626 | if (GET_CODE (operands[0]) != REG) | |
3627 | operands[1] = force_reg (HImode, operands[1]); | |
3628 | ||
3629 | if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) | |
b45863ec RK |
3630 | { |
3631 | operands[1] = force_const_mem (HImode, operands[1]); | |
3632 | if (! memory_address_p (HImode, XEXP (operands[1], 0)) | |
3633 | && ! reload_in_progress) | |
3634 | operands[1] = change_address (operands[1], HImode, | |
3635 | XEXP (operands[1], 0)); | |
3636 | } | |
1fd4e8c1 RK |
3637 | }") |
3638 | ||
3639 | (define_insn "" | |
e76e75bb RK |
3640 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h") |
3641 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))] | |
ca7f5001 RK |
3642 | "TARGET_POWER && (gpc_reg_operand (operands[0], HImode) |
3643 | || gpc_reg_operand (operands[1], HImode))" | |
1fd4e8c1 | 3644 | "@ |
deb9225a | 3645 | mr %0,%1 |
1fd4e8c1 RK |
3646 | lhz%U1%X1 %0,%1 |
3647 | sth%U0%X0 %1,%0 | |
ca7f5001 | 3648 | {cal %0,%w1(0)|li %0,%w1} |
1fd4e8c1 | 3649 | mf%1 %0 |
e76e75bb RK |
3650 | mt%0 %1 |
3651 | cror 0,0,0" | |
3652 | [(set_attr "type" "*,load,*,*,*,*,*")]) | |
1fd4e8c1 | 3653 | |
ca7f5001 RK |
3654 | (define_insn "" |
3655 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h") | |
3656 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))] | |
25c341fa | 3657 | "! TARGET_POWER && (gpc_reg_operand (operands[0], HImode) |
ca7f5001 RK |
3658 | || gpc_reg_operand (operands[1], HImode))" |
3659 | "@ | |
deb9225a | 3660 | mr %0,%1 |
ca7f5001 RK |
3661 | lhz%U1%X1 %0,%1 |
3662 | sth%U0%X0 %1,%0 | |
3663 | li %0,%w1 | |
3664 | mf%1 %0 | |
3665 | mt%0 %1" | |
3666 | [(set_attr "type" "*,load,*,*,*,*")]) | |
3667 | ||
1fd4e8c1 RK |
3668 | (define_expand "movqi" |
3669 | [(set (match_operand:QI 0 "general_operand" "") | |
3670 | (match_operand:QI 1 "any_operand" ""))] | |
3671 | "" | |
3672 | " | |
3673 | { | |
3674 | if (GET_CODE (operands[0]) != REG) | |
3675 | operands[1] = force_reg (QImode, operands[1]); | |
3676 | ||
3677 | if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) | |
b45863ec RK |
3678 | { |
3679 | operands[1] = force_const_mem (QImode, operands[1]); | |
3680 | if (! memory_address_p (QImode, XEXP (operands[1], 0)) | |
3681 | && ! reload_in_progress) | |
3682 | operands[1] = change_address (operands[1], QImode, | |
3683 | XEXP (operands[1], 0)); | |
3684 | } | |
1fd4e8c1 RK |
3685 | }") |
3686 | ||
3687 | (define_insn "" | |
e76e75bb RK |
3688 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h") |
3689 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))] | |
ca7f5001 RK |
3690 | "TARGET_POWER && (gpc_reg_operand (operands[0], QImode) |
3691 | || gpc_reg_operand (operands[1], QImode))" | |
1fd4e8c1 | 3692 | "@ |
deb9225a | 3693 | mr %0,%1 |
1fd4e8c1 RK |
3694 | lbz%U1%X1 %0,%1 |
3695 | stb%U0%X0 %1,%0 | |
ca7f5001 | 3696 | {cal %0,%1(0)|li %0,%1} |
1fd4e8c1 | 3697 | mf%1 %0 |
e76e75bb RK |
3698 | mt%0 %1 |
3699 | cror 0,0,0" | |
3700 | [(set_attr "type" "*,load,*,*,*,*,*")]) | |
ca7f5001 RK |
3701 | |
3702 | (define_insn "" | |
3703 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h") | |
3704 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))] | |
25c341fa | 3705 | "! TARGET_POWER && (gpc_reg_operand (operands[0], QImode) |
ca7f5001 RK |
3706 | || gpc_reg_operand (operands[1], QImode))" |
3707 | "@ | |
3708 | mr %0,%1 | |
3709 | lbz%U1%X1 %0,%1 | |
3710 | stb%U0%X0 %1,%0 | |
3711 | li %0,%1 | |
3712 | mf%1 %0 | |
3713 | mt%0 %1" | |
3714 | [(set_attr "type" "*,load,*,*,*,*")]) | |
1fd4e8c1 RK |
3715 | \f |
3716 | ;; Here is how to move condition codes around. When we store CC data in | |
3717 | ;; an integer register or memory, we store just the high-order 4 bits. | |
3718 | ;; This lets us not shift in the most common case of CR0. | |
3719 | (define_expand "movcc" | |
3720 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
3721 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
3722 | "" | |
3723 | "") | |
3724 | ||
3725 | (define_insn "" | |
3726 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") | |
3727 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
3728 | "register_operand (operands[0], CCmode) | |
3729 | || register_operand (operands[1], CCmode)" | |
3730 | "@ | |
3731 | mcrf %0,%1 | |
3732 | mtcrf 128,%1 | |
ca7f5001 | 3733 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 3734 | mfcr %0 |
ca7f5001 | 3735 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 3736 | mr %0,%1 |
ca7f5001 RK |
3737 | {l%U1%X1|lwz%U1%X1} %0,%1 |
3738 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b19003d8 RK |
3739 | [(set_attr "type" "*,*,*,compare,*,*,load,*") |
3740 | (set_attr "length" "*,*,12,*,8,*,*,*")]) | |
1fd4e8c1 RK |
3741 | \f |
3742 | ;; For floating-point, we normally deal with the floating-point registers. | |
3743 | ;; The sole exception is that parameter passing can produce floating-point | |
3744 | ;; values in fixed-point registers. Unless the value is a simple constant | |
3745 | ;; or already in memory, we deal with this by allocating memory and copying | |
3746 | ;; the value explicitly via that memory location. | |
3747 | (define_expand "movsf" | |
3748 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
3749 | (match_operand:SF 1 "any_operand" ""))] | |
3750 | "" | |
3751 | " | |
3752 | { | |
3753 | /* If we are called from reload, we might be getting a SUBREG of a hard | |
3754 | reg. So expand it. */ | |
3755 | if (GET_CODE (operands[0]) == SUBREG | |
3756 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
3757 | && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) | |
3758 | operands[0] = alter_subreg (operands[0]); | |
3759 | if (GET_CODE (operands[1]) == SUBREG | |
3760 | && GET_CODE (SUBREG_REG (operands[1])) == REG | |
3761 | && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) | |
3762 | operands[1] = alter_subreg (operands[1]); | |
3763 | ||
785e6a26 | 3764 | if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) |
1fd4e8c1 RK |
3765 | { |
3766 | rtx stack_slot; | |
3767 | ||
785e6a26 RK |
3768 | /* If this is a store to memory or another integer register do the |
3769 | move directly. Otherwise store to a temporary stack slot and | |
3770 | load from there into a floating point register. */ | |
3771 | ||
1fd4e8c1 RK |
3772 | if (GET_CODE (operands[0]) == MEM |
3773 | || (GET_CODE (operands[0]) == REG | |
3774 | && (REGNO (operands[0]) < 32 | |
785e6a26 RK |
3775 | || (reload_in_progress |
3776 | && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))) | |
1fd4e8c1 RK |
3777 | { |
3778 | emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), | |
3779 | operand_subword (operands[1], 0, 0, SFmode)); | |
3780 | DONE; | |
3781 | } | |
3782 | ||
3783 | stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4)); | |
3784 | emit_move_insn (stack_slot, operands[1]); | |
3785 | emit_move_insn (operands[0], stack_slot); | |
3786 | DONE; | |
3787 | } | |
3788 | ||
3789 | if (GET_CODE (operands[0]) == MEM) | |
3790 | operands[1] = force_reg (SFmode, operands[1]); | |
3791 | ||
3792 | if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) | |
3793 | { | |
3794 | rtx stack_slot; | |
3795 | ||
3796 | if (GET_CODE (operands[1]) == MEM | |
3797 | #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE) | |
3798 | || GET_CODE (operands[1]) == CONST_DOUBLE | |
3799 | #endif | |
8ffd9c51 RK |
3800 | || (GET_CODE (operands[1]) == REG |
3801 | && (REGNO (operands[1]) < 32 | |
3802 | || (reload_in_progress | |
3803 | && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)))) | |
1fd4e8c1 RK |
3804 | { |
3805 | emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), | |
3806 | operand_subword (operands[1], 0, 0, SFmode)); | |
3807 | DONE; | |
3808 | } | |
3809 | ||
3810 | if (reload_in_progress) | |
3811 | stack_slot = gen_rtx (MEM, SFmode, | |
3812 | plus_constant (stack_pointer_rtx, 4)); | |
3813 | else | |
3814 | stack_slot = assign_stack_temp (SFmode, 4, 0); | |
3815 | emit_move_insn (stack_slot, operands[1]); | |
3816 | emit_move_insn (operands[0], stack_slot); | |
3817 | DONE; | |
3818 | } | |
3819 | ||
3820 | if (CONSTANT_P (operands[1])) | |
3821 | { | |
3822 | operands[1] = force_const_mem (SFmode, operands[1]); | |
3823 | if (! memory_address_p (SFmode, XEXP (operands[1], 0)) | |
3824 | && ! reload_in_progress) | |
3825 | operands[1] = change_address (operands[1], SFmode, | |
3826 | XEXP (operands[1], 0)); | |
3827 | } | |
3828 | }") | |
3829 | ||
1fd4e8c1 | 3830 | (define_split |
cd2b37d9 | 3831 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3832 | (match_operand:SF 1 "easy_fp_constant" ""))] |
3833 | "reload_completed && REGNO (operands[0]) <= 31" | |
3834 | [(set (match_dup 2) (match_dup 3))] | |
3835 | " | |
3836 | { operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
3837 | operands[3] = operand_subword (operands[1], 0, 0, SFmode); }") | |
3838 | ||
3839 | (define_insn "" | |
3840 | [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m") | |
3841 | (match_operand:SF 1 "input_operand" "f,m,f"))] | |
cd2b37d9 RK |
3842 | "gpc_reg_operand (operands[0], SFmode) |
3843 | || gpc_reg_operand (operands[1], SFmode)" | |
1fd4e8c1 RK |
3844 | "@ |
3845 | fmr %0,%1 | |
3846 | lfs%U1%X1 %0,%1 | |
3847 | frsp %1,%1\;stfs%U0%X0 %1,%0" | |
cfb557c4 | 3848 | [(set_attr "type" "fp,fpload,*") |
b19003d8 | 3849 | (set_attr "length" "*,*,8")]) |
1fd4e8c1 RK |
3850 | \f |
3851 | (define_expand "movdf" | |
3852 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
3853 | (match_operand:DF 1 "any_operand" ""))] | |
3854 | "" | |
3855 | " | |
3856 | { | |
e7113111 | 3857 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
1fd4e8c1 | 3858 | { |
e7113111 RK |
3859 | emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), |
3860 | operand_subword_force (operands[1], 1, DFmode)); | |
3861 | emit_move_insn (operand_subword (operands[0], 0, 1, DFmode), | |
3862 | operand_subword_force (operands[1], 0, DFmode)); | |
1fd4e8c1 RK |
3863 | DONE; |
3864 | } | |
3865 | ||
e7113111 RK |
3866 | if (GET_CODE (operands[0]) != REG) |
3867 | operands[1] = force_reg (DFmode, operands[1]); | |
1fd4e8c1 | 3868 | |
e7113111 | 3869 | if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode)) |
1fd4e8c1 RK |
3870 | { |
3871 | operands[1] = force_const_mem (DFmode, operands[1]); | |
3872 | if (! memory_address_p (DFmode, XEXP (operands[1], 0)) | |
3873 | && ! reload_in_progress) | |
3874 | operands[1] = change_address (operands[1], DFmode, | |
3875 | XEXP (operands[1], 0)); | |
3876 | } | |
e7113111 | 3877 | }") |
1fd4e8c1 RK |
3878 | |
3879 | (define_split | |
cd2b37d9 | 3880 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3881 | (match_operand:DF 1 "easy_fp_constant" ""))] |
3882 | "reload_completed && REGNO (operands[0]) <= 31" | |
3883 | [(set (match_dup 2) (match_dup 3)) | |
3884 | (set (match_dup 4) (match_dup 5))] | |
3885 | " | |
3886 | { operands[2] = operand_subword (operands[0], 0, 0, DFmode); | |
3887 | operands[3] = operand_subword (operands[1], 0, 0, DFmode); | |
3888 | operands[4] = operand_subword (operands[0], 1, 0, DFmode); | |
3889 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); }") | |
e7113111 | 3890 | |
4eae5fe1 RK |
3891 | ;; Don't have reload use general registers to load a constant. First, |
3892 | ;; it might not work if the output operand has is the equivalent of | |
3893 | ;; a non-offsettable memref, but also it is less efficient than loading | |
3894 | ;; the constant into an FP register, since it will probably be used there. | |
3895 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
3896 | ;; of handling these non-offsettable values. | |
3897 | (define_insn "" | |
3898 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m") | |
e7113111 | 3899 | (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))] |
51b8fc2c RK |
3900 | "! TARGET_POWERPC64 && (register_operand (operands[0], DFmode) |
3901 | || register_operand (operands[1], DFmode))" | |
e7113111 RK |
3902 | "* |
3903 | { | |
3904 | switch (which_alternative) | |
3905 | { | |
3906 | case 0: | |
3907 | /* We normally copy the low-numbered register first. However, if | |
3908 | the first register operand 0 is the same as the second register of | |
3909 | operand 1, we must copy in the opposite order. */ | |
3910 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 3911 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 3912 | else |
deb9225a | 3913 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 RK |
3914 | case 1: |
3915 | /* If the low-address word is used in the address, we must load it | |
3916 | last. Otherwise, load it first. Note that we cannot have | |
3917 | auto-increment in that case since the address register is known to be | |
3918 | dead. */ | |
3919 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3920 | operands [1], 0)) | |
ca7f5001 | 3921 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
e7113111 | 3922 | else |
ca7f5001 | 3923 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
e7113111 | 3924 | case 2: |
ca7f5001 | 3925 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
e7113111 RK |
3926 | case 3: |
3927 | return \"#\"; | |
3928 | case 4: | |
3929 | return \"fmr %0,%1\"; | |
3930 | case 5: | |
3931 | return \"lfd%U1%X1 %0,%1\"; | |
3932 | case 6: | |
3933 | return \"stfd%U0%X0 %1,%0\"; | |
3934 | } | |
3935 | }" | |
ca7f5001 | 3936 | [(set_attr "type" "*,load,*,*,fp,fpload,*") |
e7113111 | 3937 | (set_attr "length" "8,8,8,8,*,*,*")]) |
51b8fc2c RK |
3938 | |
3939 | (define_insn "" | |
3940 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m") | |
3941 | (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))] | |
3942 | "TARGET_POWERPC64 && (register_operand (operands[0], DFmode) | |
3943 | || register_operand (operands[1], DFmode))" | |
3944 | "@ | |
3d5570cb RK |
3945 | mr %0,%1 |
3946 | ld%U1%X1 %0,%1 | |
3947 | sd%U0%X0 %1,%0 | |
3948 | # | |
3949 | fmr %0,%1 | |
f63184ac | 3950 | lfd%U1%X1 %0,%1 |
3d5570cb | 3951 | stfd%U0%X0 %1,%0" |
51b8fc2c | 3952 | [(set_attr "type" "*,load,*,*,fp,fpload,*")]) |
1fd4e8c1 RK |
3953 | \f |
3954 | ;; Next come the multi-word integer load and store and the load and store | |
3955 | ;; multiple insns. | |
3956 | (define_expand "movdi" | |
3957 | [(set (match_operand:DI 0 "general_operand" "") | |
3958 | (match_operand:DI 1 "general_operand" ""))] | |
3959 | "" | |
3960 | " | |
3961 | { | |
062284d8 RK |
3962 | if (GET_CODE (operands[1]) == CONST_DOUBLE |
3963 | || GET_CODE (operands[1]) == CONST_INT) | |
1fd4e8c1 RK |
3964 | { |
3965 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
3966 | operand_subword (operands[1], 0, 0, DImode)); | |
3967 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), | |
3968 | operand_subword (operands[1], 1, 0, DImode)); | |
3969 | DONE; | |
3970 | } | |
062284d8 RK |
3971 | |
3972 | if (GET_CODE (operands[0]) == MEM) | |
3973 | operands[1] = force_reg (DImode, operands[1]); | |
a473029f RK |
3974 | |
3975 | /* Stores between FPR and any non-FPR registers must go through a | |
3976 | temporary stack slot. */ | |
3977 | ||
3978 | if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG | |
3979 | && ((FP_REGNO_P (REGNO (operands[0])) | |
3980 | && ! FP_REGNO_P (REGNO (operands[1]))) | |
3981 | || (FP_REGNO_P (REGNO (operands[1])) | |
3982 | && ! FP_REGNO_P (REGNO (operands[0]))))) | |
3983 | { | |
3984 | rtx stack_slot; | |
3985 | ||
3986 | if (reload_in_progress) | |
3987 | stack_slot = gen_rtx (MEM, DImode, | |
3988 | plus_constant (stack_pointer_rtx, 8)); | |
3989 | else | |
3990 | stack_slot = assign_stack_temp (DImode, 8, 0); | |
3991 | emit_move_insn (stack_slot, operands[1]); | |
3992 | emit_move_insn (operands[0], stack_slot); | |
3993 | DONE; | |
3994 | } | |
1fd4e8c1 RK |
3995 | }") |
3996 | ||
3997 | (define_insn "" | |
8ffd9c51 RK |
3998 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m") |
3999 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f"))] | |
51b8fc2c RK |
4000 | "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) |
4001 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
4002 | "* |
4003 | { | |
4004 | switch (which_alternative) | |
4005 | { | |
4006 | case 0: | |
4007 | /* We normally copy the low-numbered register first. However, if | |
4008 | the first register operand 0 is the same as the second register of | |
4009 | operand 1, we must copy in the opposite order. */ | |
4010 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 4011 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 4012 | else |
deb9225a | 4013 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
4014 | case 1: |
4015 | /* If the low-address word is used in the address, we must load it | |
4016 | last. Otherwise, load it first. Note that we cannot have | |
4017 | auto-increment in that case since the address register is known to be | |
4018 | dead. */ | |
4019 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
4020 | operands [1], 0)) | |
ca7f5001 | 4021 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 4022 | else |
ca7f5001 | 4023 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 4024 | case 2: |
ca7f5001 | 4025 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
4026 | case 3: |
4027 | return \"fmr %0,%1\"; | |
4028 | case 4: | |
4029 | return \"lfd%U1%X1 %0,%1\"; | |
4030 | case 5: | |
4031 | return \"stfd%U0%X0 %1,%0\"; | |
1fd4e8c1 RK |
4032 | } |
4033 | }" | |
8ffd9c51 RK |
4034 | [(set_attr "type" "*,load,*,fp,fpload,*") |
4035 | (set_attr "length" "8,8,8,*,*,*")]) | |
51b8fc2c RK |
4036 | |
4037 | (define_insn "" | |
4038 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,f,f,m,r,*h") | |
4039 | (match_operand:DI 1 "input_operand" "r,m,r,I,J,f,m,f,*h,r"))] | |
4040 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) | |
4041 | || gpc_reg_operand (operands[1], DImode))" | |
4042 | "@ | |
3d5570cb RK |
4043 | mr %0,%1 |
4044 | ld%U1%X1 %0,%1 | |
4045 | sd%U0%X0 %1,%0 | |
4046 | li %0,%1 | |
4047 | lis %0,%u1 | |
4048 | fmr %0,%1 | |
4049 | lfd%U1%X1 %0,%1 | |
4050 | stfd%U0%X0 %1,%0 | |
4051 | mf%1 %0 | |
4052 | mt%0 %1" | |
51b8fc2c | 4053 | [(set_attr "type" "*,load,*,*,*,fp,fpload,*,*,mtjmpr")]) |
1fd4e8c1 RK |
4054 | \f |
4055 | ;; TImode is similar, except that we usually want to compute the address into | |
4056 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 4057 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
4058 | (define_expand "movti" |
4059 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
4060 | (match_operand:TI 1 "general_operand" "")) | |
4061 | (clobber (scratch:SI))])] | |
51b8fc2c | 4062 | "TARGET_POWER || TARGET_POWERPC64" |
1fd4e8c1 RK |
4063 | " |
4064 | { | |
4065 | if (GET_CODE (operands[0]) == MEM) | |
4066 | operands[1] = force_reg (TImode, operands[1]); | |
4067 | ||
4068 | if (GET_CODE (operands[0]) == MEM | |
4069 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
4070 | && ! reload_in_progress) | |
4071 | operands[0] = change_address (operands[0], TImode, | |
4072 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
4073 | ||
4074 | if (GET_CODE (operands[1]) == MEM | |
4075 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
4076 | && ! reload_in_progress) | |
4077 | operands[1] = change_address (operands[1], TImode, | |
4078 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
4079 | }") | |
4080 | ||
4081 | ;; We say that MQ is clobbered in the last alternative because the first | |
4082 | ;; alternative would never get used otherwise since it would need a reload | |
4083 | ;; while the 2nd alternative would not. We put memory cases first so they | |
4084 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
4085 | ;; giving the SCRATCH mq. | |
4086 | (define_insn "" | |
e1469d0d | 4087 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
4088 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
4089 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
51b8fc2c | 4090 | "TARGET_POWER && ! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) |
ca7f5001 | 4091 | || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
4092 | "* |
4093 | { | |
4094 | switch (which_alternative) | |
4095 | { | |
4096 | case 0: | |
ca7f5001 | 4097 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
4098 | |
4099 | case 1: | |
ca7f5001 | 4100 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
4101 | |
4102 | case 2: | |
4103 | /* Normally copy registers with lowest numbered register copied first. | |
4104 | But copy in the other order if the first register of the output | |
4105 | is the second, third, or fourth register in the input. */ | |
4106 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
4107 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 4108 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 4109 | else |
deb9225a | 4110 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
4111 | case 3: |
4112 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
4113 | fall through to generating four loads. */ | |
4114 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 4115 | return \"{lsi|lswi} %0,%P1,16\"; |
1fd4e8c1 RK |
4116 | /* ... fall through ... */ |
4117 | case 4: | |
4118 | /* If the address register is the same as the register for the lowest- | |
4119 | addressed word, load it last. Similarly for the next two words. | |
4120 | Otherwise load lowest address to highest. */ | |
4121 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
4122 | operands[1], 0)) | |
ca7f5001 | 4123 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
4124 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
4125 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 4126 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
4127 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
4128 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 4129 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 4130 | else |
ca7f5001 | 4131 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
4132 | } |
4133 | }" | |
b19003d8 RK |
4134 | [(set_attr "type" "*,load,load,*,*") |
4135 | (set_attr "length" "*,16,16,*,16")]) | |
51b8fc2c RK |
4136 | |
4137 | (define_insn "" | |
4138 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") | |
4139 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
4140 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
4141 | || gpc_reg_operand (operands[1], TImode))" | |
4142 | "* | |
4143 | { | |
4144 | switch (which_alternative) | |
4145 | { | |
4146 | case 0: | |
4147 | /* We normally copy the low-numbered register first. However, if | |
4148 | the first register operand 0 is the same as the second register of | |
4149 | operand 1, we must copy in the opposite order. */ | |
4150 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
4151 | return \"mr %L0,%L1\;mr %0,%1\"; | |
4152 | else | |
4153 | return \"mr %0,%1\;mr %L0,%L1\"; | |
4154 | case 1: | |
4155 | /* If the low-address word is used in the address, we must load it | |
4156 | last. Otherwise, load it first. Note that we cannot have | |
4157 | auto-increment in that case since the address register is known to be | |
4158 | dead. */ | |
4159 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
4160 | operands [1], 0)) | |
4161 | return \"ld %L0,%L1\;ld %0,%1\"; | |
4162 | else | |
4163 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
4164 | case 2: | |
4165 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
4166 | } | |
4167 | }" | |
4168 | [(set_attr "type" "*,load,*") | |
4169 | (set_attr "length" "8,8,8")]) | |
1fd4e8c1 RK |
4170 | \f |
4171 | (define_expand "load_multiple" | |
2f622005 RK |
4172 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
4173 | (match_operand:SI 1 "" "")) | |
4174 | (use (match_operand:SI 2 "" ""))])] | |
ca7f5001 | 4175 | "TARGET_POWER" |
1fd4e8c1 RK |
4176 | " |
4177 | { | |
4178 | int regno; | |
4179 | int count; | |
4180 | rtx from; | |
4181 | int i; | |
4182 | ||
4183 | /* Support only loading a constant number of fixed-point registers from | |
4184 | memory and only bother with this if more than two; the machine | |
4185 | doesn't support more than eight. */ | |
4186 | if (GET_CODE (operands[2]) != CONST_INT | |
4187 | || INTVAL (operands[2]) <= 2 | |
4188 | || INTVAL (operands[2]) > 8 | |
4189 | || GET_CODE (operands[1]) != MEM | |
4190 | || GET_CODE (operands[0]) != REG | |
4191 | || REGNO (operands[0]) >= 32) | |
4192 | FAIL; | |
4193 | ||
4194 | count = INTVAL (operands[2]); | |
4195 | regno = REGNO (operands[0]); | |
4196 | ||
4197 | operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count)); | |
4198 | from = force_reg (SImode, XEXP (operands[1], 0)); | |
4199 | ||
4200 | for (i = 0; i < count; i++) | |
4201 | XVECEXP (operands[3], 0, i) | |
4202 | = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), | |
4203 | gen_rtx (MEM, SImode, plus_constant (from, i * 4))); | |
4204 | }") | |
4205 | ||
4206 | (define_insn "" | |
4207 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 4208 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
1fd4e8c1 | 4209 | (match_operand:SI 2 "indirect_operand" "Q"))])] |
ca7f5001 | 4210 | "TARGET_POWER" |
1fd4e8c1 RK |
4211 | "* |
4212 | { | |
4213 | /* We have to handle the case where the pseudo used to contain the address | |
4214 | is assigned to one of the output registers. In that case, do the | |
4215 | lsi, but then load the correct value. This is a bit of a mess, but is | |
b19003d8 RK |
4216 | the best we can do. |
4217 | We set the length attribute to the maximum possible size (8 bytes). */ | |
1fd4e8c1 RK |
4218 | static char result[100]; |
4219 | char newload[40]; | |
4220 | int i; | |
4221 | ||
ca7f5001 | 4222 | strcpy (result, \"{lsi|lswi} %1,%P2,%N0\"); |
1fd4e8c1 RK |
4223 | for (i = 0; i < XVECLEN (operands[0], 0); i++) |
4224 | if (refers_to_regno_p (REGNO (operands[1]) + i, | |
4225 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
4226 | { | |
ca7f5001 | 4227 | sprintf (newload, \"\;{l|lwz} %d,%d(%d)\", |
1fd4e8c1 RK |
4228 | REGNO (operands[1]) + i, |
4229 | i * 4, REGNO (XEXP (operands[2], 0))); | |
4230 | strcat (result, newload); | |
4231 | } | |
4232 | ||
4233 | return result; | |
4234 | }" | |
b19003d8 RK |
4235 | [(set_attr "type" "load") |
4236 | (set_attr "length" "8")]) | |
1fd4e8c1 | 4237 | \f |
b19003d8 | 4238 | |
1fd4e8c1 | 4239 | (define_expand "store_multiple" |
2f622005 RK |
4240 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
4241 | (match_operand:SI 1 "" "")) | |
4242 | (clobber (scratch:SI)) | |
4243 | (use (match_operand:SI 2 "" ""))])] | |
ca7f5001 | 4244 | "TARGET_POWER" |
1fd4e8c1 RK |
4245 | " |
4246 | { | |
4247 | int regno; | |
4248 | int count; | |
4249 | rtx to; | |
4250 | int i; | |
4251 | ||
4252 | /* Support only storing a constant number of fixed-point registers to | |
4253 | memory and only bother with this if more than two; the machine | |
4254 | doesn't support more than eight. */ | |
4255 | if (GET_CODE (operands[2]) != CONST_INT | |
4256 | || INTVAL (operands[2]) <= 2 | |
4257 | || INTVAL (operands[2]) > 8 | |
4258 | || GET_CODE (operands[0]) != MEM | |
4259 | || GET_CODE (operands[1]) != REG | |
4260 | || REGNO (operands[1]) >= 32) | |
4261 | FAIL; | |
4262 | ||
4263 | count = INTVAL (operands[2]); | |
4264 | regno = REGNO (operands[1]); | |
4265 | ||
4266 | operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); | |
4267 | to = force_reg (SImode, XEXP (operands[0], 0)); | |
4268 | ||
4269 | XVECEXP (operands[3], 0, 0) | |
4270 | = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]); | |
4271 | XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode, | |
4272 | gen_rtx (SCRATCH, SImode)); | |
4273 | ||
4274 | for (i = 1; i < count; i++) | |
4275 | XVECEXP (operands[3], 0, i + 1) | |
4276 | = gen_rtx (SET, VOIDmode, | |
4277 | gen_rtx (MEM, SImode, plus_constant (to, i * 4)), | |
4278 | gen_rtx (REG, SImode, regno + i)); | |
4279 | }") | |
4280 | ||
4281 | (define_insn "" | |
4282 | [(match_parallel 0 "store_multiple_operation" | |
4283 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 4284 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 4285 | (clobber (match_scratch:SI 3 "=q"))])] |
ca7f5001 RK |
4286 | "TARGET_POWER" |
4287 | "{stsi|stswi} %2,%P1,%O0") | |
1fd4e8c1 RK |
4288 | \f |
4289 | ;; Define insns that do load or store with update. Some of these we can | |
4290 | ;; get by using pre-decrement or pre-increment, but the hardware can also | |
4291 | ;; do cases where the increment is not the size of the object. | |
4292 | ;; | |
4293 | ;; In all these cases, we use operands 0 and 1 for the register being | |
4294 | ;; incremented because those are the operands that local-alloc will | |
4295 | ;; tie and these are the pair most likely to be tieable (and the ones | |
4296 | ;; that will benefit the most). | |
4297 | ||
51b8fc2c RK |
4298 | (define_insn "" |
4299 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") | |
4300 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") | |
4301 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))) | |
4302 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
4303 | (plus:DI (match_dup 1) (match_dup 2)))] | |
4304 | "TARGET_POWERPC64" | |
4305 | "@ | |
4306 | ldux %3,%0,%2 | |
4307 | ldu %3,%2(%0)" | |
4308 | [(set_attr "type" "load")]) | |
4309 | ||
4310 | (define_insn "" | |
4311 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") | |
4312 | (match_operand:DI 2 "reg_or_short_operand" "r,I"))) | |
4313 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) | |
4314 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
4315 | (plus:DI (match_dup 1) (match_dup 2)))] | |
4316 | "TARGET_POWERPC64" | |
4317 | "@ | |
4318 | stdux %3,%0,%2 | |
4319 | stdu %3,%2(%0)") | |
4320 | ||
1fd4e8c1 | 4321 | (define_insn "" |
cd2b37d9 RK |
4322 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
4323 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 4324 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 4325 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
4326 | (plus:SI (match_dup 1) (match_dup 2)))] |
4327 | "" | |
4328 | "@ | |
ca7f5001 RK |
4329 | {lux|lwzux} %3,%0,%2 |
4330 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 4331 | [(set_attr "type" "load")]) |
1fd4e8c1 RK |
4332 | |
4333 | (define_insn "" | |
cd2b37d9 | 4334 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 4335 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
4336 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
4337 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 RK |
4338 | (plus:SI (match_dup 1) (match_dup 2)))] |
4339 | "" | |
4340 | "@ | |
ca7f5001 RK |
4341 | {stux|stwux} %3,%0,%2 |
4342 | {stu|stwu} %3,%2(%0)") | |
1fd4e8c1 RK |
4343 | |
4344 | (define_insn "" | |
cd2b37d9 RK |
4345 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
4346 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 4347 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 4348 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
4349 | (plus:SI (match_dup 1) (match_dup 2)))] |
4350 | "" | |
4351 | "@ | |
5f243543 RK |
4352 | lhzux %3,%0,%2 |
4353 | lhzu %3,%2(%0)" | |
cfb557c4 | 4354 | [(set_attr "type" "load")]) |
1fd4e8c1 RK |
4355 | |
4356 | (define_insn "" | |
cd2b37d9 | 4357 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4358 | (zero_extend:SI |
cd2b37d9 | 4359 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 4360 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 4361 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
4362 | (plus:SI (match_dup 1) (match_dup 2)))] |
4363 | "" | |
4364 | "@ | |
5f243543 RK |
4365 | lhzux %3,%0,%2 |
4366 | lhzu %3,%2(%0)" | |
cfb557c4 | 4367 | [(set_attr "type" "load")]) |
1fd4e8c1 RK |
4368 | |
4369 | (define_insn "" | |
cd2b37d9 | 4370 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4371 | (sign_extend:SI |
cd2b37d9 | 4372 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 4373 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 4374 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
4375 | (plus:SI (match_dup 1) (match_dup 2)))] |
4376 | "" | |
4377 | "@ | |
5f243543 RK |
4378 | lhaux %3,%0,%2 |
4379 | lhau %3,%2(%0)" | |
cfb557c4 | 4380 | [(set_attr "type" "load")]) |
1fd4e8c1 RK |
4381 | |
4382 | (define_insn "" | |
cd2b37d9 | 4383 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 4384 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
4385 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
4386 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 RK |
4387 | (plus:SI (match_dup 1) (match_dup 2)))] |
4388 | "" | |
4389 | "@ | |
5f243543 | 4390 | sthux %3,%0,%2 |
cfb557c4 | 4391 | sthu %3,%2(%0)") |
1fd4e8c1 RK |
4392 | |
4393 | (define_insn "" | |
cd2b37d9 RK |
4394 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
4395 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 4396 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 4397 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
4398 | (plus:SI (match_dup 1) (match_dup 2)))] |
4399 | "" | |
4400 | "@ | |
5f243543 RK |
4401 | lbzux %3,%0,%2 |
4402 | lbzu %3,%2(%0)" | |
cfb557c4 | 4403 | [(set_attr "type" "load")]) |
1fd4e8c1 RK |
4404 | |
4405 | (define_insn "" | |
cd2b37d9 | 4406 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4407 | (zero_extend:SI |
cd2b37d9 | 4408 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 4409 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 4410 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
4411 | (plus:SI (match_dup 1) (match_dup 2)))] |
4412 | "" | |
4413 | "@ | |
5f243543 RK |
4414 | lbzux %3,%0,%2 |
4415 | lbzu %3,%2(%0)" | |
cfb557c4 | 4416 | [(set_attr "type" "load")]) |
1fd4e8c1 RK |
4417 | |
4418 | (define_insn "" | |
cd2b37d9 | 4419 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 4420 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
4421 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
4422 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 RK |
4423 | (plus:SI (match_dup 1) (match_dup 2)))] |
4424 | "" | |
4425 | "@ | |
5f243543 RK |
4426 | stbux %3,%0,%2 |
4427 | stbu %3,%2(%0)") | |
1fd4e8c1 RK |
4428 | |
4429 | (define_insn "" | |
cd2b37d9 RK |
4430 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
4431 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 4432 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 4433 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
4434 | (plus:SI (match_dup 1) (match_dup 2)))] |
4435 | "" | |
4436 | "@ | |
5f243543 RK |
4437 | lfsux %3,%0,%2 |
4438 | lfsu %3,%2(%0)" | |
cfb557c4 | 4439 | [(set_attr "type" "fpload")]) |
1fd4e8c1 RK |
4440 | |
4441 | (define_insn "" | |
cd2b37d9 | 4442 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 4443 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
4444 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
4445 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 RK |
4446 | (plus:SI (match_dup 1) (match_dup 2)))] |
4447 | "" | |
4448 | "@ | |
5f243543 RK |
4449 | frsp %3,%3\;stfsux %3,%0,%2 |
4450 | frsp %3,%3\;stfsu %3,%2(%0)") | |
1fd4e8c1 RK |
4451 | |
4452 | (define_insn "" | |
cd2b37d9 RK |
4453 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
4454 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 4455 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 4456 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
4457 | (plus:SI (match_dup 1) (match_dup 2)))] |
4458 | "" | |
4459 | "@ | |
5f243543 RK |
4460 | lfdux %3,%0,%2 |
4461 | lfdu %3,%2(%0)" | |
cfb557c4 | 4462 | [(set_attr "type" "fpload")]) |
1fd4e8c1 RK |
4463 | |
4464 | (define_insn "" | |
cd2b37d9 | 4465 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 4466 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
4467 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
4468 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 RK |
4469 | (plus:SI (match_dup 1) (match_dup 2)))] |
4470 | "" | |
4471 | "@ | |
5f243543 RK |
4472 | stfdux %3,%0,%2 |
4473 | stfdu %3,%2(%0)") | |
1fd4e8c1 RK |
4474 | \f |
4475 | ;; Next come insns related to the calling sequence. | |
4476 | ;; | |
4477 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
59257ff7 | 4478 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
4479 | |
4480 | (define_expand "allocate_stack" | |
4481 | [(set (reg:SI 1) | |
01def764 | 4482 | (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))] |
1fd4e8c1 RK |
4483 | "" |
4484 | " | |
4485 | { rtx chain = gen_reg_rtx (SImode); | |
4486 | rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx); | |
4487 | ||
4488 | emit_move_insn (chain, stack_bot); | |
a0044fb1 | 4489 | emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0])); |
1fd4e8c1 RK |
4490 | emit_move_insn (stack_bot, chain); |
4491 | DONE; | |
4492 | }") | |
59257ff7 RK |
4493 | |
4494 | ;; These patterns say how to save and restore the stack pointer. We need not | |
4495 | ;; save the stack pointer at function level since we are careful to | |
4496 | ;; preserve the backchain. At block level, we have to restore the backchain | |
4497 | ;; when we restore the stack pointer. | |
4498 | ;; | |
4499 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
4500 | ;; backchain and restore both. Note that in the nonlocal case, the | |
4501 | ;; save area is a memory location. | |
4502 | ||
4503 | (define_expand "save_stack_function" | |
4504 | [(use (const_int 0))] | |
4505 | "" | |
4506 | "") | |
4507 | ||
4508 | (define_expand "restore_stack_function" | |
4509 | [(use (const_int 0))] | |
4510 | "" | |
4511 | "") | |
4512 | ||
4513 | (define_expand "restore_stack_block" | |
4514 | [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" ""))) | |
4515 | (set (match_dup 0) (match_operand:SI 1 "register_operand" "")) | |
4516 | (set (mem:SI (match_dup 0)) (match_dup 2))] | |
4517 | "" | |
4518 | " | |
4519 | { operands[2] = gen_reg_rtx (SImode); }") | |
4520 | ||
4521 | (define_expand "save_stack_nonlocal" | |
4522 | [(match_operand:DI 0 "memory_operand" "") | |
4523 | (match_operand:SI 1 "register_operand" "")] | |
4524 | "" | |
4525 | " | |
4526 | { | |
4527 | rtx temp = gen_reg_rtx (SImode); | |
4528 | ||
4529 | /* Copy the backchain to the first word, sp to the second. */ | |
4530 | emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1])); | |
4531 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp); | |
4532 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]); | |
4533 | DONE; | |
4534 | }") | |
4535 | ||
4536 | (define_expand "restore_stack_nonlocal" | |
4537 | [(match_operand:SI 0 "register_operand" "") | |
4538 | (match_operand:DI 1 "memory_operand" "")] | |
4539 | "" | |
4540 | " | |
4541 | { | |
4542 | rtx temp = gen_reg_rtx (SImode); | |
4543 | ||
4544 | /* Restore the backchain from the first word, sp from the second. */ | |
4545 | emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode)); | |
4546 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode)); | |
4547 | emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp); | |
4548 | DONE; | |
4549 | }") | |
1fd4e8c1 RK |
4550 | \f |
4551 | ;; A function pointer is a pointer to a data area whose first word contains | |
4552 | ;; the actual address of the function, whose second word contains a pointer | |
4553 | ;; to its TOC, and whose third word contains a value to place in the static | |
4554 | ;; chain register (r11). Note that if we load the static chain, our | |
4555 | ;; "trampoline" need not have any executable code. | |
4556 | ;; | |
4557 | ;; operands[0] is an SImode pseudo in which we place the address of the | |
4558 | ;; function. | |
4559 | ;; operands[1] is the address of data area of the function to call | |
4560 | ||
4561 | (define_expand "call_via_ptr" | |
cd2b37d9 RK |
4562 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
4563 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
1fd4e8c1 RK |
4564 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) |
4565 | (reg:SI 2)) | |
4566 | (set (reg:SI 2) | |
4567 | (mem:SI (plus:SI (match_dup 1) | |
4568 | (const_int 4)))) | |
4569 | (set (reg:SI 11) | |
4570 | (mem:SI (plus:SI (match_dup 1) | |
4571 | (const_int 8)))) | |
4572 | (use (reg:SI 2)) | |
4573 | (use (reg:SI 11))] | |
4574 | "" | |
4575 | "") | |
4576 | ||
4577 | (define_expand "call" | |
4578 | [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" "")) | |
4579 | (match_operand 1 "" "")) | |
4580 | (clobber (scratch:SI))])] | |
4581 | "" | |
4582 | " | |
4583 | { | |
4584 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
4585 | abort (); | |
4586 | ||
4587 | operands[0] = XEXP (operands[0], 0); | |
4588 | if (GET_CODE (operands[0]) != SYMBOL_REF) | |
4589 | { | |
4590 | rtx temp = gen_reg_rtx (SImode); | |
4591 | ||
4592 | emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0]))); | |
4593 | operands[0] = temp; | |
4594 | } | |
4595 | }") | |
4596 | ||
4597 | (define_expand "call_value" | |
4598 | [(parallel [(set (match_operand 0 "" "") | |
4599 | (call (mem:SI (match_operand:SI 1 "address_operand" "")) | |
4600 | (match_operand 2 "" ""))) | |
4601 | (clobber (scratch:SI))])] | |
4602 | "" | |
4603 | " | |
4604 | { | |
4605 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
4606 | abort (); | |
4607 | ||
4608 | operands[1] = XEXP (operands[1], 0); | |
4609 | if (GET_CODE (operands[1]) != SYMBOL_REF) | |
4610 | { | |
4611 | rtx temp = gen_reg_rtx (SImode); | |
4612 | ||
4613 | emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1]))); | |
4614 | operands[1] = temp; | |
4615 | } | |
4616 | }") | |
4617 | ||
04780ee7 RK |
4618 | ;; Call to function in current module. No TOC pointer reload needed. |
4619 | ||
4620 | (define_insn "" | |
4621 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s")) | |
4622 | (match_operand 1 "" "g")) | |
4623 | (clobber (match_scratch:SI 2 "=l"))] | |
4624 | "" | |
4625 | "bl %z0") | |
4626 | ||
4627 | ;; Call to function which may be in another module. Restore the TOC | |
4628 | ;; pointer (r2) after the call. | |
4629 | ||
1fd4e8c1 RK |
4630 | (define_insn "" |
4631 | [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s")) | |
4632 | (match_operand 1 "" "fg,fg")) | |
9482d6de | 4633 | (clobber (match_scratch:SI 2 "=l,l"))] |
1fd4e8c1 RK |
4634 | "" |
4635 | "@ | |
ca7f5001 | 4636 | {brl|blrl}\;{l|lwz} 2,20(1) |
a0292f62 | 4637 | bl %z0\;%." |
b19003d8 | 4638 | [(set_attr "length" "8")]) |
1fd4e8c1 | 4639 | |
04780ee7 RK |
4640 | (define_insn "" |
4641 | [(set (match_operand 0 "" "=fg") | |
4642 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s")) | |
4643 | (match_operand 2 "" "g"))) | |
4644 | (clobber (match_scratch:SI 3 "=l"))] | |
4645 | "" | |
4646 | "bl %z1") | |
4647 | ||
1fd4e8c1 | 4648 | (define_insn "" |
5f243543 | 4649 | [(set (match_operand 0 "" "=fg,fg") |
1fd4e8c1 RK |
4650 | (call (mem:SI (match_operand:SI 1 "call_operand" "l,s")) |
4651 | (match_operand 2 "" "fg,fg"))) | |
4652 | (clobber (match_scratch:SI 3 "=l,l"))] | |
4653 | "" | |
4654 | "@ | |
ca7f5001 | 4655 | {brl|blrl}\;{l|lwz} 2,20(1) |
a0292f62 | 4656 | bl %z1\;%." |
b19003d8 | 4657 | [(set_attr "length" "8")]) |
e6f948e3 RK |
4658 | |
4659 | ;; Call subroutine returning any type. | |
4660 | ||
4661 | (define_expand "untyped_call" | |
4662 | [(parallel [(call (match_operand 0 "" "") | |
4663 | (const_int 0)) | |
4664 | (match_operand 1 "" "") | |
4665 | (match_operand 2 "" "")])] | |
4666 | "" | |
4667 | " | |
4668 | { | |
4669 | int i; | |
4670 | ||
4671 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
4672 | ||
4673 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
4674 | { | |
4675 | rtx set = XVECEXP (operands[2], 0, i); | |
4676 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
4677 | } | |
4678 | ||
4679 | /* The optimizer does not know that the call sets the function value | |
4680 | registers we stored in the result block. We avoid problems by | |
4681 | claiming that all hard registers are used and clobbered at this | |
4682 | point. */ | |
4683 | emit_insn (gen_blockage ()); | |
4684 | ||
4685 | DONE; | |
4686 | }") | |
4687 | ||
4688 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
4689 | ;; all of memory. This blocks insns from being moved across this point. | |
4690 | ||
4691 | (define_insn "blockage" | |
4692 | [(unspec_volatile [(const_int 0)] 0)] | |
4693 | "" | |
4694 | "") | |
1fd4e8c1 RK |
4695 | \f |
4696 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
4697 | ;; signed & unsigned, and one type of branch. | |
4698 | ;; | |
4699 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
4700 | ;; insns, and branches. We store the operands of compares until we see | |
4701 | ;; how it is used. | |
4702 | (define_expand "cmpsi" | |
4703 | [(set (cc0) | |
cd2b37d9 | 4704 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4705 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
4706 | "" | |
4707 | " | |
4708 | { | |
4709 | /* Take care of the possibility that operands[1] might be negative but | |
4710 | this might be a logical operation. That insn doesn't exist. */ | |
4711 | if (GET_CODE (operands[1]) == CONST_INT | |
4712 | && INTVAL (operands[1]) < 0) | |
4713 | operands[1] = force_reg (SImode, operands[1]); | |
4714 | ||
4715 | rs6000_compare_op0 = operands[0]; | |
4716 | rs6000_compare_op1 = operands[1]; | |
4717 | rs6000_compare_fp_p = 0; | |
4718 | DONE; | |
4719 | }") | |
4720 | ||
4721 | (define_expand "cmpsf" | |
cd2b37d9 RK |
4722 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
4723 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
4724 | "" |
4725 | " | |
4726 | { | |
4727 | rs6000_compare_op0 = operands[0]; | |
4728 | rs6000_compare_op1 = operands[1]; | |
4729 | rs6000_compare_fp_p = 1; | |
4730 | DONE; | |
4731 | }") | |
4732 | ||
4733 | (define_expand "cmpdf" | |
cd2b37d9 RK |
4734 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
4735 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
4736 | "" |
4737 | " | |
4738 | { | |
4739 | rs6000_compare_op0 = operands[0]; | |
4740 | rs6000_compare_op1 = operands[1]; | |
4741 | rs6000_compare_fp_p = 1; | |
4742 | DONE; | |
4743 | }") | |
4744 | ||
4745 | (define_expand "beq" | |
4746 | [(set (match_dup 2) (match_dup 1)) | |
4747 | (set (pc) | |
4748 | (if_then_else (eq (match_dup 2) | |
4749 | (const_int 0)) | |
4750 | (label_ref (match_operand 0 "" "")) | |
4751 | (pc)))] | |
4752 | "" | |
4753 | " | |
4754 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4755 | operands[1] = gen_rtx (COMPARE, mode, | |
4756 | rs6000_compare_op0, rs6000_compare_op1); | |
4757 | operands[2] = gen_reg_rtx (mode); | |
4758 | }") | |
4759 | ||
4760 | (define_expand "bne" | |
4761 | [(set (match_dup 2) (match_dup 1)) | |
4762 | (set (pc) | |
4763 | (if_then_else (ne (match_dup 2) | |
4764 | (const_int 0)) | |
4765 | (label_ref (match_operand 0 "" "")) | |
4766 | (pc)))] | |
4767 | "" | |
4768 | " | |
4769 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4770 | operands[1] = gen_rtx (COMPARE, mode, | |
4771 | rs6000_compare_op0, rs6000_compare_op1); | |
4772 | operands[2] = gen_reg_rtx (mode); | |
4773 | }") | |
4774 | ||
4775 | (define_expand "blt" | |
4776 | [(set (match_dup 2) (match_dup 1)) | |
4777 | (set (pc) | |
4778 | (if_then_else (lt (match_dup 2) | |
4779 | (const_int 0)) | |
4780 | (label_ref (match_operand 0 "" "")) | |
4781 | (pc)))] | |
4782 | "" | |
4783 | " | |
4784 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4785 | operands[1] = gen_rtx (COMPARE, mode, | |
4786 | rs6000_compare_op0, rs6000_compare_op1); | |
4787 | operands[2] = gen_reg_rtx (mode); | |
4788 | }") | |
4789 | ||
4790 | (define_expand "bgt" | |
4791 | [(set (match_dup 2) (match_dup 1)) | |
4792 | (set (pc) | |
4793 | (if_then_else (gt (match_dup 2) | |
4794 | (const_int 0)) | |
4795 | (label_ref (match_operand 0 "" "")) | |
4796 | (pc)))] | |
4797 | "" | |
4798 | " | |
4799 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4800 | operands[1] = gen_rtx (COMPARE, mode, | |
4801 | rs6000_compare_op0, rs6000_compare_op1); | |
4802 | operands[2] = gen_reg_rtx (mode); | |
4803 | }") | |
4804 | ||
4805 | (define_expand "ble" | |
4806 | [(set (match_dup 2) (match_dup 1)) | |
4807 | (set (pc) | |
4808 | (if_then_else (le (match_dup 2) | |
4809 | (const_int 0)) | |
4810 | (label_ref (match_operand 0 "" "")) | |
4811 | (pc)))] | |
4812 | "" | |
4813 | " | |
4814 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4815 | operands[1] = gen_rtx (COMPARE, mode, | |
4816 | rs6000_compare_op0, rs6000_compare_op1); | |
4817 | operands[2] = gen_reg_rtx (mode); | |
4818 | }") | |
4819 | ||
4820 | (define_expand "bge" | |
4821 | [(set (match_dup 2) (match_dup 1)) | |
4822 | (set (pc) | |
4823 | (if_then_else (ge (match_dup 2) | |
4824 | (const_int 0)) | |
4825 | (label_ref (match_operand 0 "" "")) | |
4826 | (pc)))] | |
4827 | "" | |
4828 | " | |
4829 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4830 | operands[1] = gen_rtx (COMPARE, mode, | |
4831 | rs6000_compare_op0, rs6000_compare_op1); | |
4832 | operands[2] = gen_reg_rtx (mode); | |
4833 | }") | |
4834 | ||
4835 | (define_expand "bgtu" | |
4836 | [(set (match_dup 2) (match_dup 1)) | |
4837 | (set (pc) | |
4838 | (if_then_else (gtu (match_dup 2) | |
4839 | (const_int 0)) | |
4840 | (label_ref (match_operand 0 "" "")) | |
4841 | (pc)))] | |
4842 | "" | |
4843 | " | |
4844 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
4845 | rs6000_compare_op0, rs6000_compare_op1); | |
4846 | operands[2] = gen_reg_rtx (CCUNSmode); | |
4847 | }") | |
4848 | ||
4849 | (define_expand "bltu" | |
4850 | [(set (match_dup 2) (match_dup 1)) | |
4851 | (set (pc) | |
4852 | (if_then_else (ltu (match_dup 2) | |
4853 | (const_int 0)) | |
4854 | (label_ref (match_operand 0 "" "")) | |
4855 | (pc)))] | |
4856 | "" | |
4857 | " | |
4858 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
4859 | rs6000_compare_op0, rs6000_compare_op1); | |
4860 | operands[2] = gen_reg_rtx (CCUNSmode); | |
4861 | }") | |
4862 | ||
4863 | (define_expand "bgeu" | |
4864 | [(set (match_dup 2) (match_dup 1)) | |
4865 | (set (pc) | |
4866 | (if_then_else (geu (match_dup 2) | |
4867 | (const_int 0)) | |
4868 | (label_ref (match_operand 0 "" "")) | |
4869 | (pc)))] | |
4870 | "" | |
4871 | " | |
4872 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
4873 | rs6000_compare_op0, rs6000_compare_op1); | |
4874 | operands[2] = gen_reg_rtx (CCUNSmode); | |
4875 | }") | |
4876 | ||
4877 | (define_expand "bleu" | |
4878 | [(set (match_dup 2) (match_dup 1)) | |
4879 | (set (pc) | |
4880 | (if_then_else (leu (match_dup 2) | |
4881 | (const_int 0)) | |
4882 | (label_ref (match_operand 0 "" "")) | |
4883 | (pc)))] | |
4884 | "" | |
4885 | " | |
4886 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
4887 | rs6000_compare_op0, rs6000_compare_op1); | |
4888 | operands[2] = gen_reg_rtx (CCUNSmode); | |
4889 | }") | |
4890 | ||
4891 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. | |
4892 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
4893 | ;; with an scc insns. However, due to the order that combine see the | |
4894 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
4895 | ;; the cases we don't want to handle. | |
4896 | (define_expand "seq" | |
4897 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 4898 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4899 | (eq:SI (match_dup 2) (const_int 0)))] |
4900 | "" | |
4901 | " | |
4902 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4903 | operands[1] = gen_rtx (COMPARE, mode, | |
4904 | rs6000_compare_op0, rs6000_compare_op1); | |
4905 | operands[2] = gen_reg_rtx (mode); | |
4906 | }") | |
4907 | ||
4908 | (define_expand "sne" | |
4909 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 4910 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4911 | (ne:SI (match_dup 2) (const_int 0)))] |
4912 | "" | |
4913 | " | |
4914 | { if (! rs6000_compare_fp_p) | |
4915 | FAIL; | |
4916 | ||
4917 | operands[1] = gen_rtx (COMPARE, CCFPmode, | |
4918 | rs6000_compare_op0, rs6000_compare_op1); | |
4919 | operands[2] = gen_reg_rtx (CCFPmode); | |
4920 | }") | |
4921 | ||
4922 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
4923 | (define_expand "sgt" | |
4924 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 4925 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4926 | (gt:SI (match_dup 2) (const_int 0)))] |
4927 | "" | |
4928 | " | |
4929 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4930 | ||
4931 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
4932 | FAIL; | |
4933 | ||
4934 | operands[1] = gen_rtx (COMPARE, mode, | |
4935 | rs6000_compare_op0, rs6000_compare_op1); | |
4936 | operands[2] = gen_reg_rtx (mode); | |
4937 | }") | |
4938 | ||
4939 | ;; A < 0 is best done in the portable way for A an integer. | |
4940 | (define_expand "slt" | |
4941 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 4942 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4943 | (lt:SI (match_dup 2) (const_int 0)))] |
4944 | "" | |
4945 | " | |
4946 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4947 | ||
4948 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
4949 | FAIL; | |
4950 | ||
4951 | operands[1] = gen_rtx (COMPARE, mode, | |
4952 | rs6000_compare_op0, rs6000_compare_op1); | |
4953 | operands[2] = gen_reg_rtx (mode); | |
4954 | }") | |
4955 | ||
4956 | (define_expand "sge" | |
4957 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 4958 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4959 | (ge:SI (match_dup 2) (const_int 0)))] |
4960 | "" | |
4961 | " | |
4962 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4963 | operands[1] = gen_rtx (COMPARE, mode, | |
4964 | rs6000_compare_op0, rs6000_compare_op1); | |
4965 | operands[2] = gen_reg_rtx (mode); | |
4966 | }") | |
4967 | ||
4968 | ;; A <= 0 is best done the portable way for A an integer. | |
4969 | (define_expand "sle" | |
4970 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 4971 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4972 | (le:SI (match_dup 2) (const_int 0)))] |
4973 | "" | |
4974 | " | |
4975 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
4976 | ||
4977 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
4978 | FAIL; | |
4979 | ||
4980 | operands[1] = gen_rtx (COMPARE, mode, | |
4981 | rs6000_compare_op0, rs6000_compare_op1); | |
4982 | operands[2] = gen_reg_rtx (mode); | |
4983 | }") | |
4984 | ||
4985 | (define_expand "sgtu" | |
4986 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 4987 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4988 | (gtu:SI (match_dup 2) (const_int 0)))] |
4989 | "" | |
4990 | " | |
4991 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
4992 | rs6000_compare_op0, rs6000_compare_op1); | |
4993 | operands[2] = gen_reg_rtx (CCUNSmode); | |
4994 | }") | |
4995 | ||
4996 | (define_expand "sltu" | |
4997 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 4998 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4999 | (ltu:SI (match_dup 2) (const_int 0)))] |
5000 | "" | |
5001 | " | |
5002 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
5003 | rs6000_compare_op0, rs6000_compare_op1); | |
5004 | operands[2] = gen_reg_rtx (CCUNSmode); | |
5005 | }") | |
5006 | ||
5007 | (define_expand "sgeu" | |
5008 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 5009 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
5010 | (geu:SI (match_dup 2) (const_int 0)))] |
5011 | "" | |
5012 | " | |
5013 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
5014 | rs6000_compare_op0, rs6000_compare_op1); | |
5015 | operands[2] = gen_reg_rtx (CCUNSmode); | |
5016 | }") | |
5017 | ||
5018 | (define_expand "sleu" | |
5019 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 5020 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
5021 | (leu:SI (match_dup 2) (const_int 0)))] |
5022 | "" | |
5023 | " | |
5024 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
5025 | rs6000_compare_op0, rs6000_compare_op1); | |
5026 | operands[2] = gen_reg_rtx (CCUNSmode); | |
5027 | }") | |
5028 | \f | |
5029 | ;; Here are the actual compare insns. | |
5030 | (define_insn "" | |
5031 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
cd2b37d9 | 5032 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
5033 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
5034 | "" | |
7f340546 | 5035 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
5036 | [(set_attr "type" "compare")]) |
5037 | ||
f357808b RK |
5038 | ;; If we are comparing a register for equality with a large constant, |
5039 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
5040 | ;; register for the result of the XOR. | |
5041 | ||
5042 | (define_split | |
5043 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 5044 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 5045 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 5046 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
5047 | "find_single_use (operands[0], insn, 0) |
5048 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
5049 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
5050 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
5051 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
5052 | " | |
5053 | { | |
5054 | /* Get the constant we are comparing against, C, and see what it looks like | |
5055 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
5056 | with C to get the sign-extended value. */ | |
5057 | ||
5058 | int c = INTVAL (operands[2]); | |
5059 | int sextc = (c << 16) >> 16; | |
5060 | int xorv = c ^ sextc; | |
5061 | ||
5062 | operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); | |
5063 | operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); | |
5064 | }") | |
5065 | ||
1fd4e8c1 RK |
5066 | (define_insn "" |
5067 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") | |
cd2b37d9 | 5068 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
5069 | (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] |
5070 | "" | |
7f340546 | 5071 | "{cmpl%I2|cmplw%I2} %0,%1,%W2" |
1fd4e8c1 RK |
5072 | [(set_attr "type" "compare")]) |
5073 | ||
5074 | ;; The following two insns don't exist as single insns, but if we provide | |
5075 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
5076 | ;; of the required delay between a compare and branch. We generate code for | |
5077 | ;; them by splitting. | |
5078 | ||
5079 | (define_insn "" | |
5080 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 5081 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5082 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 5083 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5084 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
5085 | "" | |
baf97f86 RK |
5086 | "#" |
5087 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
5088 | |
5089 | (define_insn "" | |
5090 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 5091 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5092 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 5093 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5094 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
5095 | "" | |
baf97f86 RK |
5096 | "#" |
5097 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
5098 | |
5099 | (define_split | |
5100 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 5101 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 5102 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 5103 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
5104 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
5105 | "" | |
5106 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
5107 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
5108 | ||
5109 | (define_split | |
5110 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 5111 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 5112 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 5113 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
5114 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
5115 | "" | |
5116 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
5117 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
5118 | ||
5119 | (define_insn "" | |
5120 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
cd2b37d9 RK |
5121 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
5122 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
5123 | "" |
5124 | "fcmpu %0,%1,%2" | |
5125 | [(set_attr "type" "fpcompare")]) | |
5126 | ||
5127 | (define_insn "" | |
5128 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
cd2b37d9 RK |
5129 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
5130 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
5131 | "" |
5132 | "fcmpu %0,%1,%2" | |
5133 | [(set_attr "type" "fpcompare")]) | |
5134 | \f | |
5135 | ;; Now we have the scc insns. We can do some combinations because of the | |
5136 | ;; way the machine works. | |
5137 | ;; | |
5138 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
5139 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
5140 | ;; cases the insns below which don't use an intermediate CR field will | |
5141 | ;; be used instead. | |
1fd4e8c1 | 5142 | (define_insn "" |
cd2b37d9 | 5143 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5144 | (match_operator:SI 1 "scc_comparison_operator" |
5145 | [(match_operand 2 "cc_reg_operand" "y") | |
5146 | (const_int 0)]))] | |
5147 | "" | |
ca7f5001 | 5148 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b19003d8 | 5149 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5150 | |
5151 | (define_insn "" | |
5152 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5153 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
5154 | [(match_operand 2 "cc_reg_operand" "y") | |
5155 | (const_int 0)]) | |
5156 | (const_int 0))) | |
cd2b37d9 | 5157 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5158 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
5159 | "" | |
ca7f5001 | 5160 | "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1" |
b19003d8 RK |
5161 | [(set_attr "type" "delayed_compare") |
5162 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5163 | |
5164 | (define_insn "" | |
cd2b37d9 | 5165 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5166 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
5167 | [(match_operand 2 "cc_reg_operand" "y") | |
5168 | (const_int 0)]) | |
5169 | (match_operand:SI 3 "const_int_operand" "n")))] | |
5170 | "" | |
5171 | "* | |
5172 | { | |
5173 | int is_bit = ccr_bit (operands[1], 1); | |
5174 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
5175 | int count; | |
5176 | ||
5177 | if (is_bit >= put_bit) | |
5178 | count = is_bit - put_bit; | |
5179 | else | |
5180 | count = 32 - (put_bit - is_bit); | |
5181 | ||
5182 | operands[4] = gen_rtx (CONST_INT, VOIDmode, count); | |
5183 | operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit); | |
5184 | ||
ca7f5001 | 5185 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 RK |
5186 | }" |
5187 | [(set_attr "length" "12")]) | |
1fd4e8c1 RK |
5188 | |
5189 | (define_insn "" | |
5190 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5191 | (compare:CC | |
5192 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
5193 | [(match_operand 2 "cc_reg_operand" "y") | |
5194 | (const_int 0)]) | |
5195 | (match_operand:SI 3 "const_int_operand" "n")) | |
5196 | (const_int 0))) | |
cd2b37d9 | 5197 | (set (match_operand:SI 4 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5198 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
5199 | (match_dup 3)))] | |
5200 | "" | |
5201 | "* | |
5202 | { | |
5203 | int is_bit = ccr_bit (operands[1], 1); | |
5204 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
5205 | int count; | |
5206 | ||
5207 | if (is_bit >= put_bit) | |
5208 | count = is_bit - put_bit; | |
5209 | else | |
5210 | count = 32 - (put_bit - is_bit); | |
5211 | ||
5212 | operands[5] = gen_rtx (CONST_INT, VOIDmode, count); | |
5213 | operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit); | |
5214 | ||
ca7f5001 | 5215 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 5216 | }" |
b19003d8 RK |
5217 | [(set_attr "type" "delayed_compare") |
5218 | (set_attr "length" "12")]) | |
1fd4e8c1 | 5219 | |
c5defebb RK |
5220 | ;; If we are comparing the result of two comparisons, this can be done |
5221 | ;; using creqv or crxor. | |
5222 | ||
5223 | (define_insn "" | |
5224 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
5225 | (compare:CCEQ (match_operator 1 "scc_comparison_operator" | |
5226 | [(match_operand 2 "cc_reg_operand" "y") | |
5227 | (const_int 0)]) | |
5228 | (match_operator 3 "scc_comparison_operator" | |
5229 | [(match_operand 4 "cc_reg_operand" "y") | |
5230 | (const_int 0)])))] | |
5231 | "REGNO (operands[2]) != REGNO (operands[4])" | |
5232 | "* | |
5233 | { | |
5234 | enum rtx_code code1, code2; | |
5235 | ||
5236 | code1 = GET_CODE (operands[1]); | |
5237 | code2 = GET_CODE (operands[3]); | |
5238 | ||
5239 | if ((code1 == EQ || code1 == LT || code1 == GT | |
5240 | || code1 == LTU || code1 == GTU | |
5241 | || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) | |
5242 | != | |
5243 | (code2 == EQ || code2 == LT || code2 == GT | |
5244 | || code2 == LTU || code2 == GTU | |
5245 | || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) | |
5246 | return \"%C1%C3crxor %E0,%j1,%j3\"; | |
5247 | else | |
5248 | return \"%C1%C3creqv %E0,%j1,%j3\"; | |
b19003d8 RK |
5249 | }" |
5250 | [(set_attr "length" "12")]) | |
c5defebb RK |
5251 | |
5252 | ;; There is a 3 cycle delay between consecutive mfcr instructions | |
5253 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
5254 | ||
5255 | (define_peephole | |
cd2b37d9 | 5256 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
5257 | (match_operator:SI 1 "scc_comparison_operator" |
5258 | [(match_operand 2 "cc_reg_operand" "y") | |
5259 | (const_int 0)])) | |
cd2b37d9 | 5260 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
5261 | (match_operator:SI 4 "scc_comparison_operator" |
5262 | [(match_operand 5 "cc_reg_operand" "y") | |
5263 | (const_int 0)]))] | |
5264 | "REGNO (operands[2]) != REGNO (operands[5])" | |
ca7f5001 | 5265 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b19003d8 | 5266 | [(set_attr "length" "20")]) |
c5defebb | 5267 | |
1fd4e8c1 RK |
5268 | ;; There are some scc insns that can be done directly, without a compare. |
5269 | ;; These are faster because they don't involve the communications between | |
5270 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
5271 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
5272 | ;; | |
5273 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
5274 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
5275 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
5276 | ;; cases where it is no more expensive than (neg (scc ..)). | |
5277 | ||
5278 | ;; Have reload force a constant into a register for the simple insns that | |
5279 | ;; otherwise won't accept constants. We do this because it is faster than | |
5280 | ;; the cmp/mfcr sequence we would otherwise generate. | |
5281 | ||
5282 | (define_insn "" | |
cd2b37d9 RK |
5283 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
5284 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
1fd4e8c1 RK |
5285 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) |
5286 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] | |
5287 | "" | |
5288 | "@ | |
ca7f5001 | 5289 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 5290 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
5291 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
5292 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
5293 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 5294 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
5295 | |
5296 | (define_insn "" | |
5297 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") | |
5298 | (compare:CC | |
cd2b37d9 | 5299 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
1fd4e8c1 RK |
5300 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) |
5301 | (const_int 0))) | |
cd2b37d9 | 5302 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
1fd4e8c1 RK |
5303 | (eq:SI (match_dup 1) (match_dup 2))) |
5304 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] | |
5305 | "" | |
5306 | "@ | |
ca7f5001 RK |
5307 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
5308 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
5309 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
5310 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
5311 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0" | |
b19003d8 RK |
5312 | [(set_attr "type" "compare") |
5313 | (set_attr "length" "12,8,12,12,12")]) | |
5314 | ||
5315 | ;; We have insns of the form shown by the first define_insn below. If | |
5316 | ;; there is something inside the comparison operation, we must split it. | |
5317 | (define_split | |
5318 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5319 | (plus:SI (match_operator 1 "comparison_operator" | |
5320 | [(match_operand:SI 2 "" "") | |
5321 | (match_operand:SI 3 | |
5322 | "reg_or_cint_operand" "")]) | |
5323 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
5324 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
5325 | "! gpc_reg_operand (operands[2], SImode)" | |
5326 | [(set (match_dup 5) (match_dup 2)) | |
5327 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
5328 | (match_dup 4)))]) | |
1fd4e8c1 RK |
5329 | |
5330 | (define_insn "" | |
cd2b37d9 RK |
5331 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
5332 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
1fd4e8c1 | 5333 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) |
cd2b37d9 | 5334 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) |
1fd4e8c1 RK |
5335 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
5336 | "" | |
5337 | "@ | |
ca7f5001 RK |
5338 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
5339 | {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 | |
5340 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
5341 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
d9d934ef | 5342 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" |
b19003d8 | 5343 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
5344 | |
5345 | (define_insn "" | |
5346 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") | |
5347 | (compare:CC | |
5348 | (plus:SI | |
cd2b37d9 | 5349 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
1fd4e8c1 | 5350 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) |
cd2b37d9 | 5351 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) |
1fd4e8c1 RK |
5352 | (const_int 0))) |
5353 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] | |
5354 | "" | |
5355 | "@ | |
ca7f5001 RK |
5356 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
5357 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 | |
5358 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
5359 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
5360 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" | |
b19003d8 RK |
5361 | [(set_attr "type" "compare") |
5362 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 RK |
5363 | |
5364 | (define_insn "" | |
5365 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") | |
5366 | (compare:CC | |
5367 | (plus:SI | |
cd2b37d9 | 5368 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
1fd4e8c1 | 5369 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) |
cd2b37d9 | 5370 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) |
1fd4e8c1 | 5371 | (const_int 0))) |
cd2b37d9 | 5372 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
1fd4e8c1 RK |
5373 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
5374 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] | |
5375 | "" | |
5376 | "@ | |
ca7f5001 RK |
5377 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
5378 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 | |
5379 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
5380 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
5381 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" | |
b19003d8 RK |
5382 | [(set_attr "type" "compare") |
5383 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 RK |
5384 | |
5385 | (define_insn "" | |
cd2b37d9 | 5386 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 5387 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
1fd4e8c1 RK |
5388 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] |
5389 | "" | |
5390 | "@ | |
ca7f5001 RK |
5391 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
5392 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
5393 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
5394 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
5395 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 5396 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
5397 | |
5398 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. | |
5399 | (define_insn "" | |
cd2b37d9 | 5400 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 5401 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 5402 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 5403 | (const_int 31)) |
cd2b37d9 | 5404 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
5405 | (clobber (match_scratch:SI 3 "=&r"))] |
5406 | "" | |
ca7f5001 | 5407 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 5408 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
5409 | |
5410 | (define_insn "" | |
5411 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5412 | (compare:CC | |
5413 | (plus:SI (lshiftrt:SI | |
cd2b37d9 | 5414 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 5415 | (const_int 31)) |
cd2b37d9 | 5416 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
5417 | (const_int 0))) |
5418 | (clobber (match_scratch:SI 3 "=&r"))] | |
5419 | "" | |
ca7f5001 | 5420 | "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2" |
b19003d8 RK |
5421 | [(set_attr "type" "compare") |
5422 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
5423 | |
5424 | (define_insn "" | |
5425 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
5426 | (compare:CC | |
5427 | (plus:SI (lshiftrt:SI | |
cd2b37d9 | 5428 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 5429 | (const_int 31)) |
cd2b37d9 | 5430 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 5431 | (const_int 0))) |
cd2b37d9 | 5432 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5433 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
5434 | (match_dup 2))) | |
5435 | (clobber (match_scratch:SI 3 "=&r"))] | |
5436 | "" | |
ca7f5001 | 5437 | "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2" |
b19003d8 RK |
5438 | [(set_attr "type" "compare") |
5439 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
5440 | |
5441 | (define_insn "" | |
cd2b37d9 RK |
5442 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
5443 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
5444 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
5445 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 5446 | "TARGET_POWER" |
1fd4e8c1 | 5447 | "@ |
ca7f5001 | 5448 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 5449 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 5450 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5451 | |
5452 | (define_insn "" | |
5453 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") | |
5454 | (compare:CC | |
cd2b37d9 | 5455 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
5456 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
5457 | (const_int 0))) | |
cd2b37d9 | 5458 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
5459 | (le:SI (match_dup 1) (match_dup 2))) |
5460 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 5461 | "TARGET_POWER" |
1fd4e8c1 | 5462 | "@ |
ca7f5001 | 5463 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
7f340546 | 5464 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31" |
a473029f | 5465 | [(set_attr "type" "compare,delayed_compare") |
b19003d8 | 5466 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
5467 | |
5468 | (define_insn "" | |
cd2b37d9 RK |
5469 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
5470 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 5471 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 5472 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 5473 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 5474 | "TARGET_POWER" |
1fd4e8c1 | 5475 | "@ |
ca7f5001 RK |
5476 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
5477 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" | |
b19003d8 | 5478 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5479 | |
5480 | (define_insn "" | |
5481 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
5482 | (compare:CC | |
cd2b37d9 | 5483 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 5484 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 5485 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 RK |
5486 | (const_int 0))) |
5487 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
ca7f5001 | 5488 | "TARGET_POWER" |
1fd4e8c1 | 5489 | "@ |
ca7f5001 RK |
5490 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
5491 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3" | |
b19003d8 RK |
5492 | [(set_attr "type" "compare") |
5493 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5494 | |
5495 | (define_insn "" | |
5496 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") | |
5497 | (compare:CC | |
cd2b37d9 | 5498 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 5499 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 5500 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 5501 | (const_int 0))) |
cd2b37d9 | 5502 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
5503 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
5504 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
ca7f5001 | 5505 | "TARGET_POWER" |
1fd4e8c1 | 5506 | "@ |
ca7f5001 RK |
5507 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
5508 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3" | |
b19003d8 RK |
5509 | [(set_attr "type" "compare") |
5510 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5511 | |
5512 | (define_insn "" | |
cd2b37d9 RK |
5513 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
5514 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 5515 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 5516 | "TARGET_POWER" |
1fd4e8c1 | 5517 | "@ |
ca7f5001 RK |
5518 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
5519 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 5520 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5521 | |
5522 | (define_insn "" | |
cd2b37d9 RK |
5523 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5524 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
5525 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
5526 | "" | |
ca7f5001 | 5527 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 5528 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5529 | |
5530 | (define_insn "" | |
5531 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
5532 | (compare:CC | |
cd2b37d9 | 5533 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
5534 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
5535 | (const_int 0))) | |
cd2b37d9 | 5536 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5537 | (leu:SI (match_dup 1) (match_dup 2)))] |
5538 | "" | |
ca7f5001 | 5539 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" |
b19003d8 RK |
5540 | [(set_attr "type" "compare") |
5541 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5542 | |
5543 | (define_insn "" | |
cd2b37d9 RK |
5544 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5545 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 5546 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 5547 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
5548 | (clobber (match_scratch:SI 4 "=&r"))] |
5549 | "" | |
ca7f5001 | 5550 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 5551 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
5552 | |
5553 | (define_insn "" | |
5554 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5555 | (compare:CC | |
cd2b37d9 | 5556 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5557 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 5558 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
5559 | (const_int 0))) |
5560 | (clobber (match_scratch:SI 4 "=&r"))] | |
5561 | "" | |
ca7f5001 | 5562 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3" |
b19003d8 RK |
5563 | [(set_attr "type" "compare") |
5564 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
5565 | |
5566 | (define_insn "" | |
5567 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") | |
5568 | (compare:CC | |
cd2b37d9 | 5569 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5570 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 5571 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 | 5572 | (const_int 0))) |
cd2b37d9 | 5573 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5574 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
5575 | (clobber (match_scratch:SI 4 "=&r"))] | |
5576 | "" | |
ca7f5001 | 5577 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3" |
b19003d8 RK |
5578 | [(set_attr "type" "compare") |
5579 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
5580 | |
5581 | (define_insn "" | |
cd2b37d9 RK |
5582 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5583 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
5584 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
5585 | "" | |
ca7f5001 | 5586 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 5587 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5588 | |
5589 | (define_insn "" | |
cd2b37d9 | 5590 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 5591 | (and:SI (neg:SI |
cd2b37d9 | 5592 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5593 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 5594 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
5595 | (clobber (match_scratch:SI 4 "=&r"))] |
5596 | "" | |
ca7f5001 | 5597 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" |
b19003d8 | 5598 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5599 | |
5600 | (define_insn "" | |
5601 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5602 | (compare:CC | |
5603 | (and:SI (neg:SI | |
cd2b37d9 | 5604 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5605 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 5606 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
5607 | (const_int 0))) |
5608 | (clobber (match_scratch:SI 4 "=&r"))] | |
5609 | "" | |
ca7f5001 | 5610 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" |
b19003d8 RK |
5611 | [(set_attr "type" "compare") |
5612 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5613 | |
5614 | (define_insn "" | |
5615 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") | |
5616 | (compare:CC | |
5617 | (and:SI (neg:SI | |
cd2b37d9 | 5618 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5619 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 5620 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 | 5621 | (const_int 0))) |
cd2b37d9 | 5622 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5623 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
5624 | (clobber (match_scratch:SI 4 "=&r"))] | |
5625 | "" | |
ca7f5001 | 5626 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" |
b19003d8 RK |
5627 | [(set_attr "type" "compare") |
5628 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5629 | |
5630 | (define_insn "" | |
cd2b37d9 RK |
5631 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5632 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 5633 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 5634 | "TARGET_POWER" |
7f340546 | 5635 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 5636 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5637 | |
5638 | (define_insn "" | |
5639 | [(set (match_operand:SI 3 "cc_reg_operand" "=x") | |
5640 | (compare:CC | |
cd2b37d9 | 5641 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
5642 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
5643 | (const_int 0))) | |
cd2b37d9 | 5644 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 5645 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 5646 | "TARGET_POWER" |
7f340546 | 5647 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" |
b19003d8 RK |
5648 | [(set_attr "type" "delayed_compare") |
5649 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5650 | |
5651 | (define_insn "" | |
cd2b37d9 RK |
5652 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5653 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 5654 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 5655 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 5656 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
5657 | "TARGET_POWER" |
5658 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 5659 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5660 | |
5661 | (define_insn "" | |
5662 | [(set (match_operand:SI 0 "cc_reg_operand" "=x") | |
5663 | (compare:CC | |
cd2b37d9 | 5664 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5665 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 5666 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
5667 | (const_int 0))) |
5668 | (clobber (match_scratch:SI 4 "=&r"))] | |
ca7f5001 RK |
5669 | "TARGET_POWER" |
5670 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" | |
b19003d8 RK |
5671 | [(set_attr "type" "compare") |
5672 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5673 | |
5674 | (define_insn "" | |
5675 | [(set (match_operand:SI 5 "cc_reg_operand" "=x") | |
5676 | (compare:CC | |
cd2b37d9 | 5677 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5678 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 5679 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 | 5680 | (const_int 0))) |
cd2b37d9 | 5681 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5682 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
5683 | (clobber (match_scratch:SI 4 "=&r"))] | |
ca7f5001 RK |
5684 | "TARGET_POWER" |
5685 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" | |
b19003d8 RK |
5686 | [(set_attr "type" "compare") |
5687 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5688 | |
5689 | (define_insn "" | |
cd2b37d9 RK |
5690 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5691 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 5692 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
5693 | "TARGET_POWER" |
5694 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 5695 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5696 | |
5697 | (define_insn "" | |
cd2b37d9 RK |
5698 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
5699 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
5700 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
5701 | "" | |
5702 | "@ | |
ca7f5001 RK |
5703 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
5704 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 5705 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5706 | |
5707 | (define_insn "" | |
5708 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") | |
5709 | (compare:CC | |
cd2b37d9 | 5710 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
5711 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
5712 | (const_int 0))) | |
cd2b37d9 | 5713 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
5714 | (ltu:SI (match_dup 1) (match_dup 2)))] |
5715 | "" | |
5716 | "@ | |
ca7f5001 RK |
5717 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
5718 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" | |
b19003d8 RK |
5719 | [(set_attr "type" "compare") |
5720 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5721 | |
5722 | (define_insn "" | |
cd2b37d9 RK |
5723 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
5724 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
1fd4e8c1 RK |
5725 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) |
5726 | (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))) | |
5727 | (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] | |
5728 | "" | |
5729 | "@ | |
ca7f5001 RK |
5730 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 |
5731 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 | |
5732 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 | |
5733 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" | |
b19003d8 | 5734 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5735 | |
5736 | (define_insn "" | |
3d91674b | 5737 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 5738 | (compare:CC |
3d91674b RK |
5739 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
5740 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
5741 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 5742 | (const_int 0))) |
3d91674b | 5743 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
5744 | "" |
5745 | "@ | |
ca7f5001 RK |
5746 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
5747 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" | |
b19003d8 RK |
5748 | [(set_attr "type" "compare") |
5749 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5750 | |
5751 | (define_insn "" | |
3d91674b | 5752 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 5753 | (compare:CC |
3d91674b RK |
5754 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
5755 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
5756 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 5757 | (const_int 0))) |
3d91674b | 5758 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 5759 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
3d91674b | 5760 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
5761 | "" |
5762 | "@ | |
ca7f5001 RK |
5763 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
5764 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" | |
b19003d8 RK |
5765 | [(set_attr "type" "compare") |
5766 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5767 | |
5768 | (define_insn "" | |
cd2b37d9 RK |
5769 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
5770 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
5771 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
5772 | "" | |
5773 | "@ | |
ca7f5001 RK |
5774 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
5775 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 5776 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
5777 | |
5778 | (define_insn "" | |
cd2b37d9 RK |
5779 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5780 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
5781 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
5782 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
5783 | "TARGET_POWER" |
5784 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 5785 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5786 | |
5787 | (define_insn "" | |
5788 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
5789 | (compare:CC | |
cd2b37d9 | 5790 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
5791 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
5792 | (const_int 0))) | |
cd2b37d9 | 5793 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5794 | (ge:SI (match_dup 1) (match_dup 2))) |
5795 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
5796 | "TARGET_POWER" |
5797 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3" | |
b19003d8 RK |
5798 | [(set_attr "type" "compare") |
5799 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5800 | |
5801 | (define_insn "" | |
cd2b37d9 RK |
5802 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5803 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 5804 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 5805 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 5806 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
5807 | "TARGET_POWER" |
5808 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" | |
b19003d8 | 5809 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5810 | |
5811 | (define_insn "" | |
5812 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5813 | (compare:CC | |
cd2b37d9 | 5814 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5815 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 5816 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
5817 | (const_int 0))) |
5818 | (clobber (match_scratch:SI 4 "=&r"))] | |
ca7f5001 RK |
5819 | "TARGET_POWER" |
5820 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" | |
b19003d8 RK |
5821 | [(set_attr "type" "compare") |
5822 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5823 | |
5824 | (define_insn "" | |
5825 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") | |
5826 | (compare:CC | |
cd2b37d9 | 5827 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 5828 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 5829 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 | 5830 | (const_int 0))) |
cd2b37d9 | 5831 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5832 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
5833 | (clobber (match_scratch:SI 4 "=&r"))] | |
ca7f5001 RK |
5834 | "TARGET_POWER" |
5835 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" | |
b19003d8 RK |
5836 | [(set_attr "type" "compare") |
5837 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5838 | |
5839 | (define_insn "" | |
cd2b37d9 RK |
5840 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5841 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 5842 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
5843 | "TARGET_POWER" |
5844 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 5845 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5846 | |
5847 | ;; This is (and (neg (ge X (const_int 0))) Y). | |
5848 | (define_insn "" | |
cd2b37d9 | 5849 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5850 | (and:SI (neg:SI |
5851 | (lshiftrt:SI | |
cd2b37d9 | 5852 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 5853 | (const_int 31))) |
cd2b37d9 | 5854 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
5855 | (clobber (match_scratch:SI 3 "=&r"))] |
5856 | "" | |
ca7f5001 | 5857 | "{srai|srawi} %3,%1,31\;andc %0,%2,%3" |
b19003d8 | 5858 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
5859 | |
5860 | (define_insn "" | |
5861 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5862 | (compare:CC | |
5863 | (and:SI (neg:SI | |
5864 | (lshiftrt:SI | |
cd2b37d9 | 5865 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 5866 | (const_int 31))) |
cd2b37d9 | 5867 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
5868 | (const_int 0))) |
5869 | (clobber (match_scratch:SI 3 "=&r"))] | |
5870 | "" | |
ca7f5001 | 5871 | "{srai|srawi} %3,%1,31\;andc. %3,%2,%3" |
b19003d8 RK |
5872 | [(set_attr "type" "compare") |
5873 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
5874 | |
5875 | (define_insn "" | |
5876 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
5877 | (compare:CC | |
5878 | (and:SI (neg:SI | |
5879 | (lshiftrt:SI | |
cd2b37d9 | 5880 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 5881 | (const_int 31))) |
cd2b37d9 | 5882 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 5883 | (const_int 0))) |
cd2b37d9 | 5884 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
5885 | (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) |
5886 | (const_int 31))) | |
5887 | (match_dup 2))) | |
5888 | (clobber (match_scratch:SI 3 "=&r"))] | |
5889 | "" | |
ca7f5001 | 5890 | "{srai|srawi} %3,%1,31\;andc. %0,%2,%3" |
b19003d8 RK |
5891 | [(set_attr "type" "compare") |
5892 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
5893 | |
5894 | (define_insn "" | |
cd2b37d9 RK |
5895 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
5896 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
5897 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
5898 | "" | |
5899 | "@ | |
ca7f5001 RK |
5900 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
5901 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 5902 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5903 | |
5904 | (define_insn "" | |
5905 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") | |
5906 | (compare:CC | |
cd2b37d9 | 5907 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
5908 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
5909 | (const_int 0))) | |
cd2b37d9 | 5910 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
5911 | (geu:SI (match_dup 1) (match_dup 2)))] |
5912 | "" | |
5913 | "@ | |
ca7f5001 RK |
5914 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
5915 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" | |
b19003d8 RK |
5916 | [(set_attr "type" "compare") |
5917 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
5918 | |
5919 | (define_insn "" | |
cd2b37d9 RK |
5920 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
5921 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 5922 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 5923 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
5924 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
5925 | "" | |
5926 | "@ | |
ca7f5001 RK |
5927 | {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 |
5928 | {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 5929 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
5930 | |
5931 | (define_insn "" | |
5932 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
5933 | (compare:CC | |
cd2b37d9 | 5934 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 5935 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 5936 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 RK |
5937 | (const_int 0))) |
5938 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
5939 | "" | |
5940 | "@ | |
ca7f5001 RK |
5941 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
5942 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" | |
b19003d8 RK |
5943 | [(set_attr "type" "compare") |
5944 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
5945 | |
5946 | (define_insn "" | |
5947 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") | |
5948 | (compare:CC | |
cd2b37d9 | 5949 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 5950 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 5951 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 5952 | (const_int 0))) |
cd2b37d9 | 5953 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
5954 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
5955 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
5956 | "" | |
5957 | "@ | |
ca7f5001 RK |
5958 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 |
5959 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" | |
b19003d8 RK |
5960 | [(set_attr "type" "compare") |
5961 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
5962 | |
5963 | (define_insn "" | |
cd2b37d9 RK |
5964 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
5965 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
5966 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
5967 | "" | |
5968 | "@ | |
ca7f5001 RK |
5969 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
5970 | {sfi|subfic} %0,%1,-1\;a%I2 %0,%0,%2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 5971 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5972 | |
5973 | (define_insn "" | |
cd2b37d9 | 5974 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 5975 | (and:SI (neg:SI |
cd2b37d9 | 5976 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 5977 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 5978 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
5979 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
5980 | "" | |
5981 | "@ | |
ca7f5001 RK |
5982 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 |
5983 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" | |
b19003d8 | 5984 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
5985 | |
5986 | (define_insn "" | |
5987 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
5988 | (compare:CC | |
5989 | (and:SI (neg:SI | |
cd2b37d9 | 5990 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 5991 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 5992 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 RK |
5993 | (const_int 0))) |
5994 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
5995 | "" | |
5996 | "@ | |
ca7f5001 RK |
5997 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
5998 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" | |
b19003d8 RK |
5999 | [(set_attr "type" "compare") |
6000 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
6001 | |
6002 | (define_insn "" | |
6003 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") | |
6004 | (compare:CC | |
6005 | (and:SI (neg:SI | |
cd2b37d9 | 6006 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 6007 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 6008 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 6009 | (const_int 0))) |
cd2b37d9 | 6010 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
6011 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
6012 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
6013 | "" | |
6014 | "@ | |
ca7f5001 RK |
6015 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
6016 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" | |
b19003d8 RK |
6017 | [(set_attr "type" "compare") |
6018 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
6019 | |
6020 | (define_insn "" | |
cd2b37d9 RK |
6021 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6022 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
6023 | (const_int 0)))] |
6024 | "" | |
ca7f5001 | 6025 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 6026 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
6027 | |
6028 | (define_insn "" | |
6029 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
6030 | (compare:CC | |
cd2b37d9 | 6031 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
6032 | (const_int 0)) |
6033 | (const_int 0))) | |
cd2b37d9 | 6034 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
6035 | (gt:SI (match_dup 1) (const_int 0)))] |
6036 | "" | |
ca7f5001 | 6037 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31" |
b19003d8 RK |
6038 | [(set_attr "type" "delayed_compare") |
6039 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
6040 | |
6041 | (define_insn "" | |
cd2b37d9 RK |
6042 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6043 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 6044 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
6045 | "TARGET_POWER" |
6046 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 6047 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
6048 | |
6049 | (define_insn "" | |
6050 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
6051 | (compare:CC | |
cd2b37d9 | 6052 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
6053 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
6054 | (const_int 0))) | |
cd2b37d9 | 6055 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 6056 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 RK |
6057 | "TARGET_POWER" |
6058 | "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" | |
b19003d8 RK |
6059 | [(set_attr "type" "delayed_compare") |
6060 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
6061 | |
6062 | (define_insn "" | |
cd2b37d9 RK |
6063 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6064 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 6065 | (const_int 0)) |
cd2b37d9 | 6066 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
6067 | (clobber (match_scratch:SI 3 "=&r"))] |
6068 | "" | |
ca7f5001 | 6069 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" |
b19003d8 | 6070 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
6071 | |
6072 | (define_insn "" | |
6073 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
6074 | (compare:CC | |
cd2b37d9 | 6075 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 6076 | (const_int 0)) |
cd2b37d9 | 6077 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
6078 | (const_int 0))) |
6079 | (clobber (match_scratch:SI 3 "=&r"))] | |
6080 | "" | |
ca7f5001 | 6081 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2" |
b19003d8 RK |
6082 | [(set_attr "type" "compare") |
6083 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
6084 | |
6085 | (define_insn "" | |
6086 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
6087 | (compare:CC | |
cd2b37d9 | 6088 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 6089 | (const_int 0)) |
cd2b37d9 | 6090 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 6091 | (const_int 0))) |
cd2b37d9 | 6092 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
6093 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
6094 | (clobber (match_scratch:SI 3 "=&r"))] | |
6095 | "" | |
ca7f5001 | 6096 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2" |
b19003d8 RK |
6097 | [(set_attr "type" "compare") |
6098 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
6099 | |
6100 | (define_insn "" | |
cd2b37d9 RK |
6101 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6102 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 6103 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 6104 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 6105 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
6106 | "TARGET_POWER" |
6107 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 6108 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
6109 | |
6110 | (define_insn "" | |
6111 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
6112 | (compare:CC | |
cd2b37d9 | 6113 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 6114 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 6115 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
6116 | (const_int 0))) |
6117 | (clobber (match_scratch:SI 4 "=&r"))] | |
ca7f5001 RK |
6118 | "TARGET_POWER" |
6119 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" | |
b19003d8 RK |
6120 | [(set_attr "type" "compare") |
6121 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
6122 | |
6123 | (define_insn "" | |
6124 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") | |
6125 | (compare:CC | |
cd2b37d9 | 6126 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 6127 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 6128 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 | 6129 | (const_int 0))) |
cd2b37d9 | 6130 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
6131 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
6132 | (clobber (match_scratch:SI 4 "=&r"))] | |
ca7f5001 RK |
6133 | "TARGET_POWER" |
6134 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" | |
b19003d8 RK |
6135 | [(set_attr "type" "compare") |
6136 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
6137 | |
6138 | (define_insn "" | |
cd2b37d9 RK |
6139 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6140 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
6141 | (const_int 0))))] |
6142 | "" | |
ca7f5001 | 6143 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 6144 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
6145 | |
6146 | (define_insn "" | |
cd2b37d9 RK |
6147 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6148 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 6149 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
6150 | "TARGET_POWER" |
6151 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 6152 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
6153 | |
6154 | (define_insn "" | |
cd2b37d9 RK |
6155 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6156 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
6157 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
6158 | "" | |
ca7f5001 | 6159 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 6160 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
6161 | |
6162 | (define_insn "" | |
6163 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
6164 | (compare:CC | |
cd2b37d9 | 6165 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
6166 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
6167 | (const_int 0))) | |
cd2b37d9 | 6168 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
6169 | (gtu:SI (match_dup 1) (match_dup 2)))] |
6170 | "" | |
ca7f5001 | 6171 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" |
b19003d8 RK |
6172 | [(set_attr "type" "compare") |
6173 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
6174 | |
6175 | (define_insn "" | |
00751805 RK |
6176 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
6177 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
6178 | (match_operand:SI 2 "reg_or_short_operand" "I,r,rI")) | |
6179 | (match_operand:SI 3 "reg_or_short_operand" "r,r,I"))) | |
6180 | (clobber (match_scratch:SI 4 "=&r,&r,&r"))] | |
1fd4e8c1 | 6181 | "" |
00751805 | 6182 | "@ |
ca7f5001 RK |
6183 | {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 |
6184 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 | |
6185 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" | |
b19003d8 | 6186 | [(set_attr "length" "8,12,12")]) |
1fd4e8c1 RK |
6187 | |
6188 | (define_insn "" | |
3d91674b | 6189 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 6190 | (compare:CC |
3d91674b RK |
6191 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
6192 | (match_operand:SI 2 "reg_or_short_operand" "I,r")) | |
6193 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 6194 | (const_int 0))) |
3d91674b | 6195 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 | 6196 | "" |
00751805 | 6197 | "@ |
ca7f5001 RK |
6198 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
6199 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" | |
b19003d8 | 6200 | [(set_attr "type" "compare") |
3d91674b | 6201 | (set_attr "length" "8,12")]) |
1fd4e8c1 RK |
6202 | |
6203 | (define_insn "" | |
3d91674b | 6204 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 6205 | (compare:CC |
3d91674b RK |
6206 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
6207 | (match_operand:SI 2 "reg_or_short_operand" "I,r")) | |
6208 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 6209 | (const_int 0))) |
3d91674b | 6210 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 6211 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
3d91674b | 6212 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 | 6213 | "" |
00751805 | 6214 | "@ |
ca7f5001 RK |
6215 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
6216 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" | |
b19003d8 | 6217 | [(set_attr "type" "compare") |
3d91674b | 6218 | (set_attr "length" "8,12")]) |
1fd4e8c1 RK |
6219 | |
6220 | (define_insn "" | |
cd2b37d9 RK |
6221 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6222 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
6223 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
6224 | "" | |
ca7f5001 | 6225 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 6226 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
6227 | \f |
6228 | ;; Define both directions of branch and return. If we need a reload | |
6229 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
6230 | ;; register CC value to there. | |
6231 | ||
6232 | (define_insn "" | |
6233 | [(set (pc) | |
6234 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
6235 | [(match_operand 2 | |
6236 | "cc_reg_operand" "x,?y") | |
6237 | (const_int 0)]) | |
6238 | (label_ref (match_operand 0 "" "")) | |
6239 | (pc)))] | |
6240 | "" | |
b19003d8 RK |
6241 | "* |
6242 | { | |
6243 | if (get_attr_length (insn) == 8) | |
6244 | return \"%C1bc %t1,%j1,%l0\"; | |
6245 | else | |
6246 | return \"%C1bc %T1,%j1,$+8\;b %l0\"; | |
6247 | }" | |
6248 | [(set_attr "type" "branch")]) | |
6249 | ||
1fd4e8c1 RK |
6250 | (define_insn "" |
6251 | [(set (pc) | |
6252 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
6253 | [(match_operand 1 | |
6254 | "cc_reg_operand" "x,?y") | |
6255 | (const_int 0)]) | |
6256 | (return) | |
6257 | (pc)))] | |
6258 | "direct_return ()" | |
ca7f5001 | 6259 | "{%C0bcr|%C0bclr} %t0,%j0" |
b19003d8 | 6260 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
6261 | |
6262 | (define_insn "" | |
6263 | [(set (pc) | |
6264 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
6265 | [(match_operand 2 | |
6266 | "cc_reg_operand" "x,?y") | |
6267 | (const_int 0)]) | |
6268 | (pc) | |
6269 | (label_ref (match_operand 0 "" ""))))] | |
6270 | "" | |
b19003d8 RK |
6271 | "* |
6272 | { | |
6273 | if (get_attr_length (insn) == 8) | |
6274 | return \"%C1bc %T1,%j1,%l0\"; | |
6275 | else | |
6276 | return \"%C1bc %t1,%j1,$+8\;b %l0\"; | |
6277 | }" | |
6278 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
6279 | |
6280 | (define_insn "" | |
6281 | [(set (pc) | |
6282 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
6283 | [(match_operand 1 | |
6284 | "cc_reg_operand" "x,?y") | |
6285 | (const_int 0)]) | |
6286 | (pc) | |
6287 | (return)))] | |
6288 | "direct_return ()" | |
ca7f5001 | 6289 | "{%C0bcr|%C0bclr} %T0,%j0" |
b19003d8 | 6290 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
6291 | |
6292 | ;; Unconditional branch and return. | |
6293 | ||
6294 | (define_insn "jump" | |
6295 | [(set (pc) | |
6296 | (label_ref (match_operand 0 "" "")))] | |
6297 | "" | |
6298 | "b %l0") | |
6299 | ||
6300 | (define_insn "return" | |
6301 | [(return)] | |
6302 | "direct_return ()" | |
324e52cc TG |
6303 | "{br|blr}" |
6304 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 RK |
6305 | |
6306 | (define_insn "indirect_jump" | |
6307 | [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] | |
6308 | "" | |
6309 | "@ | |
6310 | bctr | |
324e52cc TG |
6311 | {br|blr}" |
6312 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 RK |
6313 | |
6314 | ;; Table jump for switch statements: | |
6315 | (define_expand "tablejump" | |
6316 | [(set (match_dup 3) | |
6317 | (plus:SI (match_operand:SI 0 "" "") | |
6318 | (match_dup 2))) | |
6319 | (parallel [(set (pc) (match_dup 3)) | |
6320 | (use (label_ref (match_operand 1 "" "")))])] | |
6321 | "" | |
6322 | " | |
6323 | { operands[0] = force_reg (SImode, operands[0]); | |
6324 | operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1])); | |
6325 | operands[3] = gen_reg_rtx (SImode); | |
6326 | }") | |
6327 | ||
6328 | (define_insn "" | |
6329 | [(set (pc) | |
740ab4a2 | 6330 | (match_operand:SI 0 "register_operand" "c,l")) |
1fd4e8c1 RK |
6331 | (use (label_ref (match_operand 1 "" "")))] |
6332 | "" | |
6333 | "@ | |
6334 | bctr | |
ca7f5001 | 6335 | {br|blr}") |
1fd4e8c1 RK |
6336 | |
6337 | (define_insn "nop" | |
6338 | [(const_int 0)] | |
6339 | "" | |
ca7f5001 | 6340 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 6341 | \f |
c225ba7b RK |
6342 | ;; Define the subtract-one-and-jump insns, starting with the template |
6343 | ;; so loop.c knows what to generate. | |
6344 | ||
6345 | (define_expand "decrement_and_branchsi" | |
6346 | [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "c") | |
6347 | (const_int 1)) | |
6348 | (label_ref (match_operand 1 "" "")) | |
6349 | (pc))) | |
6350 | (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])] | |
6351 | "" | |
6352 | "") | |
6353 | ||
1fd4e8c1 RK |
6354 | ;; We need to be able to do this for any operand, including MEM, or we |
6355 | ;; will cause reload to blow up since we don't allow output reloads on | |
6356 | ;; JUMP_INSNs. | |
6357 | (define_insn "" | |
6358 | [(set (pc) | |
6359 | (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r") | |
6360 | (const_int 1)) | |
6361 | (label_ref (match_operand 2 "" "")) | |
6362 | (pc))) | |
6363 | (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") | |
6364 | (plus:SI (match_dup 1) (const_int -1))) | |
6365 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
6366 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
6367 | "" | |
b19003d8 RK |
6368 | "* |
6369 | { | |
af87a13e | 6370 | if (which_alternative != 0) |
b19003d8 RK |
6371 | return \"#\"; |
6372 | else if (get_attr_length (insn) == 8) | |
ca7f5001 | 6373 | return \"{bdn|bdnz} %l2\"; |
b19003d8 RK |
6374 | else |
6375 | return \"bdz $+8\;b %l2\"; | |
6376 | }" | |
baf97f86 RK |
6377 | [(set_attr "type" "branch") |
6378 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 6379 | |
c225ba7b | 6380 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
1fd4e8c1 RK |
6381 | (define_insn "" |
6382 | [(set (pc) | |
6383 | (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r") | |
6384 | (const_int 0)) | |
6385 | (label_ref (match_operand 2 "" "")) | |
6386 | (pc))) | |
6387 | (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") | |
6388 | (plus:SI (match_dup 1) (const_int -1))) | |
6389 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
6390 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
6391 | "find_reg_note (insn, REG_NONNEG, 0)" | |
b19003d8 RK |
6392 | "* |
6393 | { | |
af87a13e | 6394 | if (which_alternative != 0) |
b19003d8 RK |
6395 | return \"#\"; |
6396 | else if (get_attr_length (insn) == 8) | |
ca7f5001 | 6397 | return \"{bdn|bdnz} %l2\"; |
b19003d8 RK |
6398 | else |
6399 | return \"bdz $+8\;b %l2\"; | |
6400 | }" | |
baf97f86 RK |
6401 | [(set_attr "type" "branch") |
6402 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 RK |
6403 | |
6404 | (define_insn "" | |
6405 | [(set (pc) | |
6406 | (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r") | |
6407 | (const_int 1)) | |
6408 | (label_ref (match_operand 2 "" "")) | |
6409 | (pc))) | |
6410 | (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") | |
6411 | (plus:SI (match_dup 1) (const_int -1))) | |
6412 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
6413 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
6414 | "" | |
b19003d8 RK |
6415 | "* |
6416 | { | |
af87a13e | 6417 | if (which_alternative != 0) |
b19003d8 RK |
6418 | return \"#\"; |
6419 | else if (get_attr_length (insn) == 8) | |
6420 | return \"bdz %l2\"; | |
6421 | else | |
ca7f5001 | 6422 | return \"{bdn|bdnz} $+8\;b %l2\"; |
b19003d8 | 6423 | }" |
baf97f86 RK |
6424 | [(set_attr "type" "branch") |
6425 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 RK |
6426 | |
6427 | (define_split | |
6428 | [(set (pc) | |
6429 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 6430 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
6431 | (const_int 1)]) |
6432 | (match_operand 5 "" "") | |
6433 | (match_operand 6 "" ""))) | |
cd2b37d9 | 6434 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
6435 | (plus:SI (match_dup 1) (const_int -1))) |
6436 | (clobber (match_scratch:CC 3 "")) | |
6437 | (clobber (match_scratch:SI 4 ""))] | |
6438 | "reload_completed" | |
6439 | [(parallel [(set (match_dup 3) | |
6440 | (compare:CC (plus:SI (match_dup 1) (const_int -1)) | |
6441 | (const_int 0))) | |
6442 | (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))]) | |
6443 | (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))] | |
6444 | " | |
6445 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
6446 | const0_rtx); }") | |
6447 | ||
6448 | (define_split | |
6449 | [(set (pc) | |
6450 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 6451 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
6452 | (const_int 1)]) |
6453 | (match_operand 5 "" "") | |
6454 | (match_operand 6 "" ""))) | |
6455 | (set (match_operand:SI 0 "general_operand" "") | |
6456 | (plus:SI (match_dup 1) (const_int -1))) | |
6457 | (clobber (match_scratch:CC 3 "")) | |
6458 | (clobber (match_scratch:SI 4 ""))] | |
cd2b37d9 | 6459 | "reload_completed && ! gpc_reg_operand (operands[0], SImode)" |
1fd4e8c1 RK |
6460 | [(parallel [(set (match_dup 3) |
6461 | (compare:CC (plus:SI (match_dup 1) (const_int -1)) | |
6462 | (const_int 0))) | |
6463 | (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))]) | |
6464 | (set (match_dup 0) (match_dup 4)) | |
6465 | (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))] | |
6466 | " | |
6467 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
6468 | const0_rtx); }") |