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996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
66647d44 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
602ea4d3 4;; Free Software Foundation, Inc.
996a5f59 5;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 6
5de601cf 7;; This file is part of GCC.
1fd4e8c1 8
5de601cf
NC		 9;; GCC is free software; you can redistribute it and/or modify it
10;; under the terms of the GNU General Public License as published
2f83c7d6 11;; by the Free Software Foundation; either version 3, or (at your
5de601cf 12;; option) any later version.
1fd4e8c1 13
5de601cf
NC		 14;; GCC is distributed in the hope that it will be useful, but WITHOUT
15;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17;; License for more details.
1fd4e8c1
RK		 18
19;; You should have received a copy of the GNU General Public License
2f83c7d6
NC		 20;; along with GCC; see the file COPYING3. If not see
21;; <http://www.gnu.org/licenses/>.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 24
1de43f85
DE		 25;;
26;; REGNOS
27;;
28
29(define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
615158e2
JJ		 52;;
53;; UNSPEC usage
54;;
55
56(define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
9719f3b7
DE		 64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
615158e2
JJ		 68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
ecb62ae7 83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
cef6b86c 84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
da4c340c 85 (UNSPEC_STFIWX 32)
9f0076e5
DE		 86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
716019c0
JM		 98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
9c78b944 101 (UNSPEC_RSQRT 48)
2e4316da 102 (UNSPEC_TOCREL 49)
08a6a74b 103 (UNSPEC_MACHOPIC_OFFSET 50)
615158e2
JJ		 104 ])
105
106;;
107;; UNSPEC_VOLATILE usage
108;;
109
110(define_constants
111 [(UNSPECV_BLOCK 0)
b52110d4
DE		 112 (UNSPECV_LL 1) ; load-locked
113 (UNSPECV_SC 2) ; store-conditional
615158e2
JJ		 114 (UNSPECV_EH_RR 9) ; eh_reg_restore
115 ])
1fd4e8c1
RK		 116\f
117;; Define an insn type attribute. This is used in function unit delay
118;; computations.
44cd321e 119(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
1fd4e8c1
RK		 120 (const_string "integer"))
121
0bb7b92e
ME		 122;; Define floating point instruction sub-types for use with Xfpu.md
123(define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
124
b19003d8 125;; Length (in bytes).
6ae08853 126; '(pc)' in the following doesn't include the instruction itself; it is
6cbadf36 127; calculated as if the instruction had zero size.
b19003d8
RK		 128(define_attr "length" ""
129 (if_then_else (eq_attr "type" "branch")
6cbadf36 130 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 131 (const_int -32768))
6cbadf36
GK		 132 (lt (minus (match_dup 0) (pc))
133 (const_int 32764)))
39a10a29
GK		 134 (const_int 4)
135 (const_int 8))
b19003d8
RK		 136 (const_int 4)))
137
cfb557c4
RK		 138;; Processor type -- this attribute must exactly match the processor_type
139;; enumeration in rs6000.h.
140
edae5fe3 141(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell"
cfb557c4
RK		 142 (const (symbol_ref "rs6000_cpu_attr")))
143
d296e02e
AP		 144
145;; If this instruction is microcoded on the CELL processor
c921bad8 146; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
d296e02e 147(define_attr "cell_micro" "not,conditional,always"
f8f49aea
BE		 148 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
149 (const_string "always")
150 (const_string "not")))
d296e02e 151
b54cf83a
DE		 152(automata_option "ndfa")
153
154(include "rios1.md")
155(include "rios2.md")
156(include "rs64.md")
157(include "mpc.md")
158(include "40x.md")
02ca7595 159(include "440.md")
b54cf83a
DE		 160(include "603.md")
161(include "6xx.md")
162(include "7xx.md")
163(include "7450.md")
5e8006fa 164(include "8540.md")
fa41c305 165(include "e300c2c3.md")
edae5fe3 166(include "e500mc.md")
b54cf83a 167(include "power4.md")
ec507f2d 168(include "power5.md")
44cd321e 169(include "power6.md")
d296e02e 170(include "cell.md")
0bb7b92e 171(include "xfpu.md")
48d72335
DE		 172
173(include "predicates.md")
279bb624 174(include "constraints.md")
48d72335 175
ac9e2cff 176(include "darwin.md")
309323c2 177
1fd4e8c1 178\f
3abcb3a7 179;; Mode iterators
915167f5 180
3abcb3a7 181; This mode iterator allows :GPR to be used to indicate the allowable size
915167f5 182; of whole values in GPRs.
3abcb3a7 183(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
915167f5 184
0354e5d8 185; Any supported integer mode.
3abcb3a7 186(define_mode_iterator INT [QI HI SI DI TI])
915167f5 187
0354e5d8 188; Any supported integer mode that fits in one register.
3abcb3a7 189(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
915167f5 190
b5568f07 191; extend modes for DImode
3abcb3a7 192(define_mode_iterator QHSI [QI HI SI])
b5568f07 193
0354e5d8 194; SImode or DImode, even if DImode doesn't fit in GPRs.
3abcb3a7 195(define_mode_iterator SDI [SI DI])
0354e5d8
GK		 196
197; The size of a pointer. Also, the size of the value that a record-condition
198; (one with a '.') will compare.
3abcb3a7 199(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
2e6c9641 200
4ae234b0 201; Any hardware-supported floating-point mode
696e45ba
ME		 202(define_mode_iterator FP [
203 (SF "TARGET_HARD_FLOAT
204 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
205 (DF "TARGET_HARD_FLOAT
206 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
602ea4d3 207 (TF "!TARGET_IEEEQUAD
17caeff2
JM		 208 && TARGET_HARD_FLOAT
209 && (TARGET_FPRS || TARGET_E500_DOUBLE)
6ef9a246
JJ		 210 && TARGET_LONG_DOUBLE_128")
211 (DD "TARGET_DFP")
212 (TD "TARGET_DFP")])
4ae234b0 213
915167f5 214; Various instructions that come in SI and DI forms.
0354e5d8 215; A generic w/d attribute, for things like cmpw/cmpd.
b5568f07
DE		 216(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
217
218; DImode bits
219(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
915167f5
GK		 220
221\f
1fd4e8c1
RK		 222;; Start with fixed-point load and store insns. Here we put only the more
223;; complex forms. Basic data transfer is done later.
224
b5568f07 225(define_expand "zero_extend<mode>di2"
51b8fc2c 226 [(set (match_operand:DI 0 "gpc_reg_operand" "")
b5568f07 227 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
51b8fc2c
RK		 228 "TARGET_POWERPC64"
229 "")
230
b5568f07 231(define_insn "*zero_extend<mode>di2_internal1"
51b8fc2c 232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
b5568f07 233 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
51b8fc2c
RK		 234 "TARGET_POWERPC64"
235 "@
b5568f07
DE		 236 l<wd>z%U1%X1 %0,%1
237 rldicl %0,%1,0,<dbits>"
51b8fc2c
RK		 238 [(set_attr "type" "load,*")])
239
b5568f07 240(define_insn "*zero_extend<mode>di2_internal2"
9ebbca7d 241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
b5568f07 242 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
815cdc52 243 (const_int 0)))
9ebbca7d 244 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 245 "TARGET_64BIT"
9ebbca7d 246 "@
b5568f07 247 rldicl. %2,%1,0,<dbits>
9ebbca7d
GK		 248 #"
249 [(set_attr "type" "compare")
250 (set_attr "length" "4,8")])
251
252(define_split
c921bad8 253 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
b5568f07 254 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 255 (const_int 0)))
256 (clobber (match_scratch:DI 2 ""))]
257 "TARGET_POWERPC64 && reload_completed"
258 [(set (match_dup 2)
259 (zero_extend:DI (match_dup 1)))
260 (set (match_dup 0)
261 (compare:CC (match_dup 2)
262 (const_int 0)))]
263 "")
51b8fc2c 264
b5568f07 265(define_insn "*zero_extend<mode>di2_internal3"
9ebbca7d 266 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
b5568f07 267 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 268 (const_int 0)))
9ebbca7d 269 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 270 (zero_extend:DI (match_dup 1)))]
683bdff7 271 "TARGET_64BIT"
9ebbca7d 272 "@
b5568f07 273 rldicl. %0,%1,0,<dbits>
9ebbca7d
GK		 274 #"
275 [(set_attr "type" "compare")
276 (set_attr "length" "4,8")])
277
278(define_split
c921bad8 279 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
b5568f07 280 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 281 (const_int 0)))
282 (set (match_operand:DI 0 "gpc_reg_operand" "")
283 (zero_extend:DI (match_dup 1)))]
284 "TARGET_POWERPC64 && reload_completed"
285 [(set (match_dup 0)
286 (zero_extend:DI (match_dup 1)))
287 (set (match_dup 2)
288 (compare:CC (match_dup 0)
289 (const_int 0)))]
290 "")
51b8fc2c 291
2bee0449
RK		 292(define_insn "extendqidi2"
293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
294 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 295 "TARGET_POWERPC64"
44cd321e
PS		 296 "extsb %0,%1"
297 [(set_attr "type" "exts")])
51b8fc2c
RK		 298
299(define_insn ""
9ebbca7d
GK		 300 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
301 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 302 (const_int 0)))
9ebbca7d 303 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 304 "TARGET_64BIT"
9ebbca7d
GK		 305 "@
306 extsb. %2,%1
307 #"
308 [(set_attr "type" "compare")
309 (set_attr "length" "4,8")])
310
311(define_split
c921bad8 312 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 313 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
314 (const_int 0)))
315 (clobber (match_scratch:DI 2 ""))]
316 "TARGET_POWERPC64 && reload_completed"
317 [(set (match_dup 2)
318 (sign_extend:DI (match_dup 1)))
319 (set (match_dup 0)
320 (compare:CC (match_dup 2)
321 (const_int 0)))]
322 "")
51b8fc2c
RK		 323
324(define_insn ""
9ebbca7d
GK		 325 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
326 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 327 (const_int 0)))
9ebbca7d 328 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 329 (sign_extend:DI (match_dup 1)))]
683bdff7 330 "TARGET_64BIT"
9ebbca7d
GK		 331 "@
332 extsb. %0,%1
333 #"
334 [(set_attr "type" "compare")
335 (set_attr "length" "4,8")])
336
337(define_split
c921bad8 338 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 339 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
340 (const_int 0)))
341 (set (match_operand:DI 0 "gpc_reg_operand" "")
342 (sign_extend:DI (match_dup 1)))]
343 "TARGET_POWERPC64 && reload_completed"
344 [(set (match_dup 0)
345 (sign_extend:DI (match_dup 1)))
346 (set (match_dup 2)
347 (compare:CC (match_dup 0)
348 (const_int 0)))]
349 "")
51b8fc2c 350
51b8fc2c
RK		 351(define_expand "extendhidi2"
352 [(set (match_operand:DI 0 "gpc_reg_operand" "")
353 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
354 "TARGET_POWERPC64"
355 "")
356
357(define_insn ""
358 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
359 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
c921bad8 360 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
51b8fc2c
RK		 361 "@
362 lha%U1%X1 %0,%1
363 extsh %0,%1"
44cd321e 364 [(set_attr "type" "load_ext,exts")])
51b8fc2c 365
c921bad8
AP		 366(define_insn ""
367 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
368 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
369 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
370 "extsh %0,%1"
371 [(set_attr "type" "exts")])
372
51b8fc2c 373(define_insn ""
9ebbca7d
GK		 374 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
375 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 376 (const_int 0)))
9ebbca7d 377 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 378 "TARGET_64BIT"
9ebbca7d
GK		 379 "@
380 extsh. %2,%1
381 #"
382 [(set_attr "type" "compare")
383 (set_attr "length" "4,8")])
384
385(define_split
c921bad8 386 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 387 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
388 (const_int 0)))
389 (clobber (match_scratch:DI 2 ""))]
390 "TARGET_POWERPC64 && reload_completed"
391 [(set (match_dup 2)
392 (sign_extend:DI (match_dup 1)))
393 (set (match_dup 0)
394 (compare:CC (match_dup 2)
395 (const_int 0)))]
396 "")
51b8fc2c
RK		 397
398(define_insn ""
9ebbca7d
GK		 399 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
400 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 401 (const_int 0)))
9ebbca7d 402 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 403 (sign_extend:DI (match_dup 1)))]
683bdff7 404 "TARGET_64BIT"
9ebbca7d
GK		 405 "@
406 extsh. %0,%1
407 #"
408 [(set_attr "type" "compare")
409 (set_attr "length" "4,8")])
410
411(define_split
c921bad8 412 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 413 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
414 (const_int 0)))
415 (set (match_operand:DI 0 "gpc_reg_operand" "")
416 (sign_extend:DI (match_dup 1)))]
417 "TARGET_POWERPC64 && reload_completed"
418 [(set (match_dup 0)
419 (sign_extend:DI (match_dup 1)))
420 (set (match_dup 2)
421 (compare:CC (match_dup 0)
422 (const_int 0)))]
423 "")
51b8fc2c 424
51b8fc2c
RK		 425(define_expand "extendsidi2"
426 [(set (match_operand:DI 0 "gpc_reg_operand" "")
427 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
428 "TARGET_POWERPC64"
429 "")
430
431(define_insn ""
432 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 433 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
c921bad8 434 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
51b8fc2c
RK		 435 "@
436 lwa%U1%X1 %0,%1
437 extsw %0,%1"
44cd321e 438 [(set_attr "type" "load_ext,exts")])
51b8fc2c 439
c921bad8
AP		 440(define_insn ""
441 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
442 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
443 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
444 "extsw %0,%1"
445 [(set_attr "type" "exts")])
446
51b8fc2c 447(define_insn ""
9ebbca7d
GK		 448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
449 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 450 (const_int 0)))
9ebbca7d 451 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 452 "TARGET_64BIT"
9ebbca7d
GK		 453 "@
454 extsw. %2,%1
455 #"
456 [(set_attr "type" "compare")
457 (set_attr "length" "4,8")])
458
459(define_split
c921bad8 460 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 461 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
462 (const_int 0)))
463 (clobber (match_scratch:DI 2 ""))]
464 "TARGET_POWERPC64 && reload_completed"
465 [(set (match_dup 2)
466 (sign_extend:DI (match_dup 1)))
467 (set (match_dup 0)
468 (compare:CC (match_dup 2)
469 (const_int 0)))]
470 "")
51b8fc2c
RK		 471
472(define_insn ""
9ebbca7d
GK		 473 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
474 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 475 (const_int 0)))
9ebbca7d 476 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 477 (sign_extend:DI (match_dup 1)))]
683bdff7 478 "TARGET_64BIT"
9ebbca7d
GK		 479 "@
480 extsw. %0,%1
481 #"
482 [(set_attr "type" "compare")
483 (set_attr "length" "4,8")])
484
485(define_split
c921bad8 486 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 487 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
488 (const_int 0)))
489 (set (match_operand:DI 0 "gpc_reg_operand" "")
490 (sign_extend:DI (match_dup 1)))]
491 "TARGET_POWERPC64 && reload_completed"
492 [(set (match_dup 0)
493 (sign_extend:DI (match_dup 1)))
494 (set (match_dup 2)
495 (compare:CC (match_dup 0)
496 (const_int 0)))]
497 "")
51b8fc2c 498
1fd4e8c1 499(define_expand "zero_extendqisi2"
cd2b37d9
RK		 500 [(set (match_operand:SI 0 "gpc_reg_operand" "")
501 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 502 ""
503 "")
504
505(define_insn ""
cd2b37d9 506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 507 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
508 ""
509 "@
510 lbz%U1%X1 %0,%1
005a35b9 511 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 512 [(set_attr "type" "load,*")])
513
514(define_insn ""
9ebbca7d
GK		 515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
516 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 517 (const_int 0)))
9ebbca7d 518 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 519 ""
9ebbca7d
GK		 520 "@
521 {andil.|andi.} %2,%1,0xff
522 #"
523 [(set_attr "type" "compare")
524 (set_attr "length" "4,8")])
525
526(define_split
c921bad8 527 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 528 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
529 (const_int 0)))
530 (clobber (match_scratch:SI 2 ""))]
531 "reload_completed"
532 [(set (match_dup 2)
533 (zero_extend:SI (match_dup 1)))
534 (set (match_dup 0)
535 (compare:CC (match_dup 2)
536 (const_int 0)))]
537 "")
1fd4e8c1
RK		 538
539(define_insn ""
9ebbca7d
GK		 540 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
541 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 542 (const_int 0)))
9ebbca7d 543 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 544 (zero_extend:SI (match_dup 1)))]
545 ""
9ebbca7d
GK		 546 "@
547 {andil.|andi.} %0,%1,0xff
548 #"
549 [(set_attr "type" "compare")
550 (set_attr "length" "4,8")])
551
552(define_split
c921bad8 553 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 554 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
555 (const_int 0)))
556 (set (match_operand:SI 0 "gpc_reg_operand" "")
557 (zero_extend:SI (match_dup 1)))]
558 "reload_completed"
559 [(set (match_dup 0)
560 (zero_extend:SI (match_dup 1)))
561 (set (match_dup 2)
562 (compare:CC (match_dup 0)
563 (const_int 0)))]
564 "")
1fd4e8c1 565
51b8fc2c
RK		 566(define_expand "extendqisi2"
567 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
568 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
569 ""
570 "
571{
572 if (TARGET_POWERPC)
573 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
574 else if (TARGET_POWER)
575 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
576 else
577 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
578 DONE;
579}")
580
581(define_insn "extendqisi2_ppc"
2bee0449
RK		 582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
583 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 584 "TARGET_POWERPC"
44cd321e
PS		 585 "extsb %0,%1"
586 [(set_attr "type" "exts")])
51b8fc2c
RK		 587
588(define_insn ""
9ebbca7d
GK		 589 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
590 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 591 (const_int 0)))
9ebbca7d 592 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 593 "TARGET_POWERPC"
9ebbca7d
GK		 594 "@
595 extsb. %2,%1
596 #"
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
599
600(define_split
c921bad8 601 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 602 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
603 (const_int 0)))
604 (clobber (match_scratch:SI 2 ""))]
605 "TARGET_POWERPC && reload_completed"
606 [(set (match_dup 2)
607 (sign_extend:SI (match_dup 1)))
608 (set (match_dup 0)
609 (compare:CC (match_dup 2)
610 (const_int 0)))]
611 "")
51b8fc2c
RK		 612
613(define_insn ""
9ebbca7d
GK		 614 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
615 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 616 (const_int 0)))
9ebbca7d 617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 618 (sign_extend:SI (match_dup 1)))]
619 "TARGET_POWERPC"
9ebbca7d
GK		 620 "@
621 extsb. %0,%1
622 #"
623 [(set_attr "type" "compare")
624 (set_attr "length" "4,8")])
625
626(define_split
c921bad8 627 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 628 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
629 (const_int 0)))
630 (set (match_operand:SI 0 "gpc_reg_operand" "")
631 (sign_extend:SI (match_dup 1)))]
632 "TARGET_POWERPC && reload_completed"
633 [(set (match_dup 0)
634 (sign_extend:SI (match_dup 1)))
635 (set (match_dup 2)
636 (compare:CC (match_dup 0)
637 (const_int 0)))]
638 "")
51b8fc2c
RK		 639
640(define_expand "extendqisi2_power"
641 [(parallel [(set (match_dup 2)
642 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
643 (const_int 24)))
644 (clobber (scratch:SI))])
645 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
646 (ashiftrt:SI (match_dup 2)
647 (const_int 24)))
648 (clobber (scratch:SI))])]
649 "TARGET_POWER"
650 "
651{ operands[1] = gen_lowpart (SImode, operands[1]);
652 operands[2] = gen_reg_rtx (SImode); }")
653
654(define_expand "extendqisi2_no_power"
655 [(set (match_dup 2)
656 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
657 (const_int 24)))
658 (set (match_operand:SI 0 "gpc_reg_operand" "")
659 (ashiftrt:SI (match_dup 2)
660 (const_int 24)))]
661 "! TARGET_POWER && ! TARGET_POWERPC"
662 "
663{ operands[1] = gen_lowpart (SImode, operands[1]);
664 operands[2] = gen_reg_rtx (SImode); }")
665
1fd4e8c1 666(define_expand "zero_extendqihi2"
cd2b37d9
RK		 667 [(set (match_operand:HI 0 "gpc_reg_operand" "")
668 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 669 ""
670 "")
671
672(define_insn ""
cd2b37d9 673 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 674 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
675 ""
676 "@
677 lbz%U1%X1 %0,%1
005a35b9 678 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 679 [(set_attr "type" "load,*")])
680
681(define_insn ""
9ebbca7d
GK		 682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
683 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 684 (const_int 0)))
9ebbca7d 685 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 686 ""
9ebbca7d
GK		 687 "@
688 {andil.|andi.} %2,%1,0xff
689 #"
690 [(set_attr "type" "compare")
691 (set_attr "length" "4,8")])
692
693(define_split
c921bad8 694 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 695 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
696 (const_int 0)))
697 (clobber (match_scratch:HI 2 ""))]
698 "reload_completed"
699 [(set (match_dup 2)
700 (zero_extend:HI (match_dup 1)))
701 (set (match_dup 0)
702 (compare:CC (match_dup 2)
703 (const_int 0)))]
704 "")
1fd4e8c1 705
51b8fc2c 706(define_insn ""
9ebbca7d
GK		 707 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
708 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 709 (const_int 0)))
9ebbca7d 710 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 711 (zero_extend:HI (match_dup 1)))]
712 ""
9ebbca7d
GK		 713 "@
714 {andil.|andi.} %0,%1,0xff
715 #"
716 [(set_attr "type" "compare")
717 (set_attr "length" "4,8")])
718
719(define_split
c921bad8 720 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 721 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
722 (const_int 0)))
723 (set (match_operand:HI 0 "gpc_reg_operand" "")
724 (zero_extend:HI (match_dup 1)))]
725 "reload_completed"
726 [(set (match_dup 0)
727 (zero_extend:HI (match_dup 1)))
728 (set (match_dup 2)
729 (compare:CC (match_dup 0)
730 (const_int 0)))]
731 "")
815cdc52
MM		 732
733(define_expand "extendqihi2"
734 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
735 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
736 ""
737 "
738{
739 if (TARGET_POWERPC)
740 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
741 else if (TARGET_POWER)
742 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
743 else
744 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
745 DONE;
746}")
747
748(define_insn "extendqihi2_ppc"
749 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
750 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
751 "TARGET_POWERPC"
44cd321e
PS		 752 "extsb %0,%1"
753 [(set_attr "type" "exts")])
815cdc52
MM		 754
755(define_insn ""
9ebbca7d
GK		 756 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
757 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 758 (const_int 0)))
9ebbca7d 759 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 760 "TARGET_POWERPC"
9ebbca7d
GK		 761 "@
762 extsb. %2,%1
763 #"
764 [(set_attr "type" "compare")
765 (set_attr "length" "4,8")])
766
767(define_split
c921bad8 768 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 769 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
770 (const_int 0)))
771 (clobber (match_scratch:HI 2 ""))]
772 "TARGET_POWERPC && reload_completed"
773 [(set (match_dup 2)
774 (sign_extend:HI (match_dup 1)))
775 (set (match_dup 0)
776 (compare:CC (match_dup 2)
777 (const_int 0)))]
778 "")
815cdc52
MM		 779
780(define_insn ""
9ebbca7d
GK		 781 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
782 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 783 (const_int 0)))
9ebbca7d 784 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 785 (sign_extend:HI (match_dup 1)))]
786 "TARGET_POWERPC"
9ebbca7d
GK		 787 "@
788 extsb. %0,%1
789 #"
790 [(set_attr "type" "compare")
791 (set_attr "length" "4,8")])
792
793(define_split
c921bad8 794 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 795 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
796 (const_int 0)))
797 (set (match_operand:HI 0 "gpc_reg_operand" "")
798 (sign_extend:HI (match_dup 1)))]
799 "TARGET_POWERPC && reload_completed"
800 [(set (match_dup 0)
801 (sign_extend:HI (match_dup 1)))
802 (set (match_dup 2)
803 (compare:CC (match_dup 0)
804 (const_int 0)))]
805 "")
51b8fc2c
RK		 806
807(define_expand "extendqihi2_power"
808 [(parallel [(set (match_dup 2)
809 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
810 (const_int 24)))
811 (clobber (scratch:SI))])
812 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
813 (ashiftrt:SI (match_dup 2)
814 (const_int 24)))
815 (clobber (scratch:SI))])]
816 "TARGET_POWER"
817 "
818{ operands[0] = gen_lowpart (SImode, operands[0]);
819 operands[1] = gen_lowpart (SImode, operands[1]);
820 operands[2] = gen_reg_rtx (SImode); }")
821
822(define_expand "extendqihi2_no_power"
823 [(set (match_dup 2)
824 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
825 (const_int 24)))
826 (set (match_operand:HI 0 "gpc_reg_operand" "")
827 (ashiftrt:SI (match_dup 2)
828 (const_int 24)))]
829 "! TARGET_POWER && ! TARGET_POWERPC"
830 "
831{ operands[0] = gen_lowpart (SImode, operands[0]);
832 operands[1] = gen_lowpart (SImode, operands[1]);
833 operands[2] = gen_reg_rtx (SImode); }")
834
1fd4e8c1 835(define_expand "zero_extendhisi2"
5f243543 836 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 837 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 838 ""
839 "")
840
841(define_insn ""
cd2b37d9 842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 843 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
844 ""
845 "@
846 lhz%U1%X1 %0,%1
005a35b9 847 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 848 [(set_attr "type" "load,*")])
849
850(define_insn ""
9ebbca7d
GK		 851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
852 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 853 (const_int 0)))
9ebbca7d 854 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 855 ""
9ebbca7d
GK		 856 "@
857 {andil.|andi.} %2,%1,0xffff
858 #"
859 [(set_attr "type" "compare")
860 (set_attr "length" "4,8")])
861
862(define_split
c921bad8 863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 864 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
865 (const_int 0)))
866 (clobber (match_scratch:SI 2 ""))]
867 "reload_completed"
868 [(set (match_dup 2)
869 (zero_extend:SI (match_dup 1)))
870 (set (match_dup 0)
871 (compare:CC (match_dup 2)
872 (const_int 0)))]
873 "")
1fd4e8c1
RK		 874
875(define_insn ""
9ebbca7d
GK		 876 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 878 (const_int 0)))
9ebbca7d 879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 880 (zero_extend:SI (match_dup 1)))]
881 ""
9ebbca7d
GK		 882 "@
883 {andil.|andi.} %0,%1,0xffff
884 #"
885 [(set_attr "type" "compare")
886 (set_attr "length" "4,8")])
887
888(define_split
c921bad8 889 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
891 (const_int 0)))
892 (set (match_operand:SI 0 "gpc_reg_operand" "")
893 (zero_extend:SI (match_dup 1)))]
894 "reload_completed"
895 [(set (match_dup 0)
896 (zero_extend:SI (match_dup 1)))
897 (set (match_dup 2)
898 (compare:CC (match_dup 0)
899 (const_int 0)))]
900 "")
1fd4e8c1
RK		 901
902(define_expand "extendhisi2"
cd2b37d9
RK		 903 [(set (match_operand:SI 0 "gpc_reg_operand" "")
904 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 905 ""
906 "")
907
908(define_insn ""
cd2b37d9 909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 910 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
c921bad8 911 "rs6000_gen_cell_microcode"
1fd4e8c1
RK		 912 "@
913 lha%U1%X1 %0,%1
ca7f5001 914 {exts|extsh} %0,%1"
44cd321e 915 [(set_attr "type" "load_ext,exts")])
1fd4e8c1 916
c921bad8
AP		 917(define_insn ""
918 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
919 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
920 "!rs6000_gen_cell_microcode"
921 "{exts|extsh} %0,%1"
922 [(set_attr "type" "exts")])
923
1fd4e8c1 924(define_insn ""
9ebbca7d
GK		 925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
926 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 927 (const_int 0)))
9ebbca7d 928 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 929 ""
9ebbca7d
GK		 930 "@
931 {exts.|extsh.} %2,%1
932 #"
933 [(set_attr "type" "compare")
934 (set_attr "length" "4,8")])
935
936(define_split
c921bad8 937 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 938 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
939 (const_int 0)))
940 (clobber (match_scratch:SI 2 ""))]
941 "reload_completed"
942 [(set (match_dup 2)
943 (sign_extend:SI (match_dup 1)))
944 (set (match_dup 0)
945 (compare:CC (match_dup 2)
946 (const_int 0)))]
947 "")
1fd4e8c1
RK		 948
949(define_insn ""
9ebbca7d
GK		 950 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
951 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 952 (const_int 0)))
9ebbca7d 953 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 954 (sign_extend:SI (match_dup 1)))]
955 ""
9ebbca7d
GK		 956 "@
957 {exts.|extsh.} %0,%1
958 #"
959 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")])
1fd4e8c1 961\f
4adf8008 962;; IBM 405, 440 and 464 half-word multiplication operations.
131aeb82
JM		 963
964(define_insn "*macchwc"
965 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
966 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
967 (match_operand:SI 2 "gpc_reg_operand" "r")
968 (const_int 16))
969 (sign_extend:SI
970 (match_operand:HI 1 "gpc_reg_operand" "r")))
971 (match_operand:SI 4 "gpc_reg_operand" "0"))
972 (const_int 0)))
973 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
974 (plus:SI (mult:SI (ashiftrt:SI
975 (match_dup 2)
976 (const_int 16))
977 (sign_extend:SI
978 (match_dup 1)))
979 (match_dup 4)))]
980 "TARGET_MULHW"
981 "macchw. %0, %1, %2"
982 [(set_attr "type" "imul3")])
983
984(define_insn "*macchw"
985 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
986 (plus:SI (mult:SI (ashiftrt:SI
987 (match_operand:SI 2 "gpc_reg_operand" "r")
988 (const_int 16))
989 (sign_extend:SI
990 (match_operand:HI 1 "gpc_reg_operand" "r")))
991 (match_operand:SI 3 "gpc_reg_operand" "0")))]
992 "TARGET_MULHW"
993 "macchw %0, %1, %2"
994 [(set_attr "type" "imul3")])
995
996(define_insn "*macchwuc"
997 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
998 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
999 (match_operand:SI 2 "gpc_reg_operand" "r")
1000 (const_int 16))
1001 (zero_extend:SI
1002 (match_operand:HI 1 "gpc_reg_operand" "r")))
1003 (match_operand:SI 4 "gpc_reg_operand" "0"))
1004 (const_int 0)))
1005 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1006 (plus:SI (mult:SI (lshiftrt:SI
1007 (match_dup 2)
1008 (const_int 16))
1009 (zero_extend:SI
1010 (match_dup 1)))
1011 (match_dup 4)))]
1012 "TARGET_MULHW"
1013 "macchwu. %0, %1, %2"
1014 [(set_attr "type" "imul3")])
1015
1016(define_insn "*macchwu"
1017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1018 (plus:SI (mult:SI (lshiftrt:SI
1019 (match_operand:SI 2 "gpc_reg_operand" "r")
1020 (const_int 16))
1021 (zero_extend:SI
1022 (match_operand:HI 1 "gpc_reg_operand" "r")))
1023 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1024 "TARGET_MULHW"
1025 "macchwu %0, %1, %2"
1026 [(set_attr "type" "imul3")])
1027
1028(define_insn "*machhwc"
1029 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1030 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1031 (match_operand:SI 1 "gpc_reg_operand" "%r")
1032 (const_int 16))
1033 (ashiftrt:SI
1034 (match_operand:SI 2 "gpc_reg_operand" "r")
1035 (const_int 16)))
1036 (match_operand:SI 4 "gpc_reg_operand" "0"))
1037 (const_int 0)))
1038 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1039 (plus:SI (mult:SI (ashiftrt:SI
1040 (match_dup 1)
1041 (const_int 16))
1042 (ashiftrt:SI
1043 (match_dup 2)
1044 (const_int 16)))
1045 (match_dup 4)))]
1046 "TARGET_MULHW"
1047 "machhw. %0, %1, %2"
1048 [(set_attr "type" "imul3")])
1049
1050(define_insn "*machhw"
1051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (ashiftrt:SI
1053 (match_operand:SI 1 "gpc_reg_operand" "%r")
1054 (const_int 16))
1055 (ashiftrt:SI
1056 (match_operand:SI 2 "gpc_reg_operand" "r")
1057 (const_int 16)))
1058 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1059 "TARGET_MULHW"
1060 "machhw %0, %1, %2"
1061 [(set_attr "type" "imul3")])
1062
1063(define_insn "*machhwuc"
1064 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1065 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1066 (match_operand:SI 1 "gpc_reg_operand" "%r")
1067 (const_int 16))
1068 (lshiftrt:SI
1069 (match_operand:SI 2 "gpc_reg_operand" "r")
1070 (const_int 16)))
1071 (match_operand:SI 4 "gpc_reg_operand" "0"))
1072 (const_int 0)))
1073 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1074 (plus:SI (mult:SI (lshiftrt:SI
1075 (match_dup 1)
1076 (const_int 16))
1077 (lshiftrt:SI
1078 (match_dup 2)
1079 (const_int 16)))
1080 (match_dup 4)))]
1081 "TARGET_MULHW"
1082 "machhwu. %0, %1, %2"
1083 [(set_attr "type" "imul3")])
1084
1085(define_insn "*machhwu"
1086 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1087 (plus:SI (mult:SI (lshiftrt:SI
1088 (match_operand:SI 1 "gpc_reg_operand" "%r")
1089 (const_int 16))
1090 (lshiftrt:SI
1091 (match_operand:SI 2 "gpc_reg_operand" "r")
1092 (const_int 16)))
1093 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1094 "TARGET_MULHW"
1095 "machhwu %0, %1, %2"
1096 [(set_attr "type" "imul3")])
1097
1098(define_insn "*maclhwc"
1099 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1100 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1101 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1102 (sign_extend:SI
1103 (match_operand:HI 2 "gpc_reg_operand" "r")))
1104 (match_operand:SI 4 "gpc_reg_operand" "0"))
1105 (const_int 0)))
1106 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1107 (plus:SI (mult:SI (sign_extend:SI
1108 (match_dup 1))
1109 (sign_extend:SI
1110 (match_dup 2)))
1111 (match_dup 4)))]
1112 "TARGET_MULHW"
1113 "maclhw. %0, %1, %2"
1114 [(set_attr "type" "imul3")])
1115
1116(define_insn "*maclhw"
1117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1118 (plus:SI (mult:SI (sign_extend:SI
1119 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1120 (sign_extend:SI
1121 (match_operand:HI 2 "gpc_reg_operand" "r")))
1122 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1123 "TARGET_MULHW"
1124 "maclhw %0, %1, %2"
1125 [(set_attr "type" "imul3")])
1126
1127(define_insn "*maclhwuc"
1128 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1129 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1130 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1131 (zero_extend:SI
1132 (match_operand:HI 2 "gpc_reg_operand" "r")))
1133 (match_operand:SI 4 "gpc_reg_operand" "0"))
1134 (const_int 0)))
1135 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1136 (plus:SI (mult:SI (zero_extend:SI
1137 (match_dup 1))
1138 (zero_extend:SI
1139 (match_dup 2)))
1140 (match_dup 4)))]
1141 "TARGET_MULHW"
1142 "maclhwu. %0, %1, %2"
1143 [(set_attr "type" "imul3")])
1144
1145(define_insn "*maclhwu"
1146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1147 (plus:SI (mult:SI (zero_extend:SI
1148 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1149 (zero_extend:SI
1150 (match_operand:HI 2 "gpc_reg_operand" "r")))
1151 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1152 "TARGET_MULHW"
1153 "maclhwu %0, %1, %2"
1154 [(set_attr "type" "imul3")])
1155
1156(define_insn "*nmacchwc"
1157 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1158 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1159 (mult:SI (ashiftrt:SI
1160 (match_operand:SI 2 "gpc_reg_operand" "r")
1161 (const_int 16))
1162 (sign_extend:SI
1163 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1164 (const_int 0)))
1165 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166 (minus:SI (match_dup 4)
1167 (mult:SI (ashiftrt:SI
1168 (match_dup 2)
1169 (const_int 16))
1170 (sign_extend:SI
1171 (match_dup 1)))))]
1172 "TARGET_MULHW"
1173 "nmacchw. %0, %1, %2"
1174 [(set_attr "type" "imul3")])
1175
1176(define_insn "*nmacchw"
1177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1178 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1179 (mult:SI (ashiftrt:SI
1180 (match_operand:SI 2 "gpc_reg_operand" "r")
1181 (const_int 16))
1182 (sign_extend:SI
1183 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1184 "TARGET_MULHW"
1185 "nmacchw %0, %1, %2"
1186 [(set_attr "type" "imul3")])
1187
1188(define_insn "*nmachhwc"
1189 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1190 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1191 (mult:SI (ashiftrt:SI
1192 (match_operand:SI 1 "gpc_reg_operand" "%r")
1193 (const_int 16))
1194 (ashiftrt:SI
1195 (match_operand:SI 2 "gpc_reg_operand" "r")
1196 (const_int 16))))
1197 (const_int 0)))
1198 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1199 (minus:SI (match_dup 4)
1200 (mult:SI (ashiftrt:SI
1201 (match_dup 1)
1202 (const_int 16))
1203 (ashiftrt:SI
1204 (match_dup 2)
1205 (const_int 16)))))]
1206 "TARGET_MULHW"
1207 "nmachhw. %0, %1, %2"
1208 [(set_attr "type" "imul3")])
1209
1210(define_insn "*nmachhw"
1211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1212 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1213 (mult:SI (ashiftrt:SI
1214 (match_operand:SI 1 "gpc_reg_operand" "%r")
1215 (const_int 16))
1216 (ashiftrt:SI
1217 (match_operand:SI 2 "gpc_reg_operand" "r")
1218 (const_int 16)))))]
1219 "TARGET_MULHW"
1220 "nmachhw %0, %1, %2"
1221 [(set_attr "type" "imul3")])
1222
1223(define_insn "*nmaclhwc"
1224 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1225 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1226 (mult:SI (sign_extend:SI
1227 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1228 (sign_extend:SI
1229 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1230 (const_int 0)))
1231 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1232 (minus:SI (match_dup 4)
1233 (mult:SI (sign_extend:SI
1234 (match_dup 1))
1235 (sign_extend:SI
1236 (match_dup 2)))))]
1237 "TARGET_MULHW"
1238 "nmaclhw. %0, %1, %2"
1239 [(set_attr "type" "imul3")])
1240
1241(define_insn "*nmaclhw"
1242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1243 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1244 (mult:SI (sign_extend:SI
1245 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1246 (sign_extend:SI
1247 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1248 "TARGET_MULHW"
1249 "nmaclhw %0, %1, %2"
1250 [(set_attr "type" "imul3")])
1251
1252(define_insn "*mulchwc"
1253 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1254 (compare:CC (mult:SI (ashiftrt:SI
1255 (match_operand:SI 2 "gpc_reg_operand" "r")
1256 (const_int 16))
1257 (sign_extend:SI
1258 (match_operand:HI 1 "gpc_reg_operand" "r")))
1259 (const_int 0)))
1260 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1261 (mult:SI (ashiftrt:SI
1262 (match_dup 2)
1263 (const_int 16))
1264 (sign_extend:SI
1265 (match_dup 1))))]
1266 "TARGET_MULHW"
1267 "mulchw. %0, %1, %2"
1268 [(set_attr "type" "imul3")])
1269
1270(define_insn "*mulchw"
1271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1272 (mult:SI (ashiftrt:SI
1273 (match_operand:SI 2 "gpc_reg_operand" "r")
1274 (const_int 16))
1275 (sign_extend:SI
1276 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1277 "TARGET_MULHW"
1278 "mulchw %0, %1, %2"
1279 [(set_attr "type" "imul3")])
1280
1281(define_insn "*mulchwuc"
1282 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1283 (compare:CC (mult:SI (lshiftrt:SI
1284 (match_operand:SI 2 "gpc_reg_operand" "r")
1285 (const_int 16))
1286 (zero_extend:SI
1287 (match_operand:HI 1 "gpc_reg_operand" "r")))
1288 (const_int 0)))
1289 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1290 (mult:SI (lshiftrt:SI
1291 (match_dup 2)
1292 (const_int 16))
1293 (zero_extend:SI
1294 (match_dup 1))))]
1295 "TARGET_MULHW"
1296 "mulchwu. %0, %1, %2"
1297 [(set_attr "type" "imul3")])
1298
1299(define_insn "*mulchwu"
1300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1301 (mult:SI (lshiftrt:SI
1302 (match_operand:SI 2 "gpc_reg_operand" "r")
1303 (const_int 16))
1304 (zero_extend:SI
1305 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1306 "TARGET_MULHW"
1307 "mulchwu %0, %1, %2"
1308 [(set_attr "type" "imul3")])
1309
1310(define_insn "*mulhhwc"
1311 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1312 (compare:CC (mult:SI (ashiftrt:SI
1313 (match_operand:SI 1 "gpc_reg_operand" "%r")
1314 (const_int 16))
1315 (ashiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16)))
1318 (const_int 0)))
1319 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1320 (mult:SI (ashiftrt:SI
1321 (match_dup 1)
1322 (const_int 16))
1323 (ashiftrt:SI
1324 (match_dup 2)
1325 (const_int 16))))]
1326 "TARGET_MULHW"
1327 "mulhhw. %0, %1, %2"
1328 [(set_attr "type" "imul3")])
1329
1330(define_insn "*mulhhw"
1331 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1332 (mult:SI (ashiftrt:SI
1333 (match_operand:SI 1 "gpc_reg_operand" "%r")
1334 (const_int 16))
1335 (ashiftrt:SI
1336 (match_operand:SI 2 "gpc_reg_operand" "r")
1337 (const_int 16))))]
1338 "TARGET_MULHW"
1339 "mulhhw %0, %1, %2"
1340 [(set_attr "type" "imul3")])
1341
1342(define_insn "*mulhhwuc"
1343 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1344 (compare:CC (mult:SI (lshiftrt:SI
1345 (match_operand:SI 1 "gpc_reg_operand" "%r")
1346 (const_int 16))
1347 (lshiftrt:SI
1348 (match_operand:SI 2 "gpc_reg_operand" "r")
1349 (const_int 16)))
1350 (const_int 0)))
1351 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1352 (mult:SI (lshiftrt:SI
1353 (match_dup 1)
1354 (const_int 16))
1355 (lshiftrt:SI
1356 (match_dup 2)
1357 (const_int 16))))]
1358 "TARGET_MULHW"
1359 "mulhhwu. %0, %1, %2"
1360 [(set_attr "type" "imul3")])
1361
1362(define_insn "*mulhhwu"
1363 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1364 (mult:SI (lshiftrt:SI
1365 (match_operand:SI 1 "gpc_reg_operand" "%r")
1366 (const_int 16))
1367 (lshiftrt:SI
1368 (match_operand:SI 2 "gpc_reg_operand" "r")
1369 (const_int 16))))]
1370 "TARGET_MULHW"
1371 "mulhhwu %0, %1, %2"
1372 [(set_attr "type" "imul3")])
1373
1374(define_insn "*mullhwc"
1375 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1376 (compare:CC (mult:SI (sign_extend:SI
1377 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1378 (sign_extend:SI
1379 (match_operand:HI 2 "gpc_reg_operand" "r")))
1380 (const_int 0)))
1381 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1382 (mult:SI (sign_extend:SI
1383 (match_dup 1))
1384 (sign_extend:SI
1385 (match_dup 2))))]
1386 "TARGET_MULHW"
1387 "mullhw. %0, %1, %2"
1388 [(set_attr "type" "imul3")])
1389
1390(define_insn "*mullhw"
1391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1392 (mult:SI (sign_extend:SI
1393 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1394 (sign_extend:SI
1395 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1396 "TARGET_MULHW"
1397 "mullhw %0, %1, %2"
1398 [(set_attr "type" "imul3")])
1399
1400(define_insn "*mullhwuc"
1401 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1402 (compare:CC (mult:SI (zero_extend:SI
1403 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1404 (zero_extend:SI
1405 (match_operand:HI 2 "gpc_reg_operand" "r")))
1406 (const_int 0)))
1407 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1408 (mult:SI (zero_extend:SI
1409 (match_dup 1))
1410 (zero_extend:SI
1411 (match_dup 2))))]
1412 "TARGET_MULHW"
1413 "mullhwu. %0, %1, %2"
1414 [(set_attr "type" "imul3")])
1415
1416(define_insn "*mullhwu"
1417 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1418 (mult:SI (zero_extend:SI
1419 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1420 (zero_extend:SI
1421 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1422 "TARGET_MULHW"
1423 "mullhwu %0, %1, %2"
1424 [(set_attr "type" "imul3")])
1425\f
4adf8008 1426;; IBM 405, 440 and 464 string-search dlmzb instruction support.
716019c0
JM		 1427(define_insn "dlmzb"
1428 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1429 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1430 (match_operand:SI 2 "gpc_reg_operand" "r")]
1431 UNSPEC_DLMZB_CR))
1432 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1433 (unspec:SI [(match_dup 1)
1434 (match_dup 2)]
1435 UNSPEC_DLMZB))]
1436 "TARGET_DLMZB"
1437 "dlmzb. %0, %1, %2")
1438
1439(define_expand "strlensi"
1440 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1441 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1442 (match_operand:QI 2 "const_int_operand" "")
1443 (match_operand 3 "const_int_operand" "")]
1444 UNSPEC_DLMZB_STRLEN))
1445 (clobber (match_scratch:CC 4 "=x"))]
1446 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1447{
1448 rtx result = operands[0];
1449 rtx src = operands[1];
1450 rtx search_char = operands[2];
1451 rtx align = operands[3];
1452 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1453 rtx loop_label, end_label, mem, cr0, cond;
1454 if (search_char != const0_rtx
1455 || GET_CODE (align) != CONST_INT
1456 || INTVAL (align) < 8)
1457 FAIL;
1458 word1 = gen_reg_rtx (SImode);
1459 word2 = gen_reg_rtx (SImode);
1460 scratch_dlmzb = gen_reg_rtx (SImode);
1461 scratch_string = gen_reg_rtx (Pmode);
1462 loop_label = gen_label_rtx ();
1463 end_label = gen_label_rtx ();
1464 addr = force_reg (Pmode, XEXP (src, 0));
1465 emit_move_insn (scratch_string, addr);
1466 emit_label (loop_label);
1467 mem = change_address (src, SImode, scratch_string);
1468 emit_move_insn (word1, mem);
1469 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1470 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1471 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1472 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1473 emit_jump_insn (gen_rtx_SET (VOIDmode,
1474 pc_rtx,
1475 gen_rtx_IF_THEN_ELSE (VOIDmode,
1476 cond,
1477 gen_rtx_LABEL_REF
1478 (VOIDmode,
1479 end_label),
1480 pc_rtx)));
1481 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1482 emit_jump_insn (gen_rtx_SET (VOIDmode,
1483 pc_rtx,
1484 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
ea5bd0d8 1485 emit_barrier ();
716019c0
JM		 1486 emit_label (end_label);
1487 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1488 emit_insn (gen_subsi3 (result, scratch_string, addr));
1489 emit_insn (gen_subsi3 (result, result, const1_rtx));
1490 DONE;
1491})
1492\f
9ebbca7d 1493(define_split
c921bad8 1494 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 1495 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1496 (const_int 0)))
1497 (set (match_operand:SI 0 "gpc_reg_operand" "")
1498 (sign_extend:SI (match_dup 1)))]
1499 "reload_completed"
1500 [(set (match_dup 0)
1501 (sign_extend:SI (match_dup 1)))
1502 (set (match_dup 2)
1503 (compare:CC (match_dup 0)
1504 (const_int 0)))]
1505 "")
1506
1fd4e8c1 1507;; Fixed-point arithmetic insns.
deb9225a 1508
0354e5d8
GK		 1509(define_expand "add<mode>3"
1510 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1511 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
4ae234b0 1512 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
7cd5235b 1513 ""
7cd5235b 1514{
0354e5d8
GK		 1515 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1516 {
1517 if (non_short_cint_operand (operands[2], DImode))
1518 FAIL;
1519 }
1520 else if (GET_CODE (operands[2]) == CONST_INT
1521 && ! add_operand (operands[2], <MODE>mode))
7cd5235b 1522 {
b3a13419
ILT		 1523 rtx tmp = ((!can_create_pseudo_p ()
1524 || rtx_equal_p (operands[0], operands[1]))
0354e5d8 1525 ? operands[0] : gen_reg_rtx (<MODE>mode));
7cd5235b 1526
2bfcf297 1527 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1528 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8
GK		 1529 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1530
279bb624 1531 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1532 FAIL;
7cd5235b 1533
9ebbca7d
GK		 1534 /* The ordering here is important for the prolog expander.
1535 When space is allocated from the stack, adding 'low' first may
1536 produce a temporary deallocation (which would be bad). */
0354e5d8
GK		 1537 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1538 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
7cd5235b
MM		 1539 DONE;
1540 }
279bb624 1541})
7cd5235b 1542
0354e5d8
GK		 1543;; Discourage ai/addic because of carry but provide it in an alternative
1544;; allowing register zero as source.
1545(define_insn "*add<mode>3_internal1"
1546 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1547 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1548 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
7393f7f8 1549 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1fd4e8c1 1550 "@
deb9225a
RK		 1551 {cax|add} %0,%1,%2
1552 {cal %0,%2(%1)|addi %0,%1,%2}
1553 {ai|addic} %0,%1,%2
7cd5235b
MM		 1554 {cau|addis} %0,%1,%v2"
1555 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 1556
ee890fe2
SS		 1557(define_insn "addsi3_high"
1558 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1559 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1560 (high:SI (match_operand 2 "" ""))))]
1561 "TARGET_MACHO && !TARGET_64BIT"
1562 "{cau|addis} %0,%1,ha16(%2)"
1563 [(set_attr "length" "4")])
1564
0354e5d8 1565(define_insn "*add<mode>3_internal2"
cb8cc086 1566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1567 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1568 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1569 (const_int 0)))
0354e5d8
GK		 1570 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1571 ""
deb9225a
RK		 1572 "@
1573 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1574 {ai.|addic.} %3,%1,%2
1575 #
1576 #"
a62bfff2 1577 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1578 (set_attr "length" "4,4,8,8")])
1579
1580(define_split
1581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1582 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1583 (match_operand:GPR 2 "reg_or_short_operand" ""))
cb8cc086 1584 (const_int 0)))
0354e5d8
GK		 1585 (clobber (match_scratch:GPR 3 ""))]
1586 "reload_completed"
cb8cc086 1587 [(set (match_dup 3)
0354e5d8 1588 (plus:GPR (match_dup 1)
cb8cc086
MM		 1589 (match_dup 2)))
1590 (set (match_dup 0)
1591 (compare:CC (match_dup 3)
1592 (const_int 0)))]
1593 "")
7e69e155 1594
0354e5d8 1595(define_insn "*add<mode>3_internal3"
cb8cc086 1596 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1597 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1598 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1599 (const_int 0)))
0354e5d8
GK		 1600 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1601 (plus:P (match_dup 1)
1602 (match_dup 2)))]
1603 ""
deb9225a
RK		 1604 "@
1605 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1606 {ai.|addic.} %0,%1,%2
1607 #
1608 #"
a62bfff2 1609 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1610 (set_attr "length" "4,4,8,8")])
1611
1612(define_split
1613 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1614 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1615 (match_operand:P 2 "reg_or_short_operand" ""))
cb8cc086 1616 (const_int 0)))
0354e5d8
GK		 1617 (set (match_operand:P 0 "gpc_reg_operand" "")
1618 (plus:P (match_dup 1) (match_dup 2)))]
1619 "reload_completed"
cb8cc086 1620 [(set (match_dup 0)
0354e5d8
GK		 1621 (plus:P (match_dup 1)
1622 (match_dup 2)))
cb8cc086
MM		 1623 (set (match_dup 3)
1624 (compare:CC (match_dup 0)
1625 (const_int 0)))]
1626 "")
7e69e155 1627
f357808b
RK		 1628;; Split an add that we can't do in one insn into two insns, each of which
1629;; does one 16-bit part. This is used by combine. Note that the low-order
1630;; add should be last in case the result gets used in an address.
1631
1632(define_split
0354e5d8
GK		 1633 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1634 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1635 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1fd4e8c1 1636 ""
0354e5d8
GK		 1637 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1638 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1fd4e8c1 1639{
2bfcf297 1640 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1641 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8 1642 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1fd4e8c1 1643
e6ca2c17 1644 operands[4] = GEN_INT (low);
279bb624 1645 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1646 operands[3] = GEN_INT (rest);
b3a13419 1647 else if (can_create_pseudo_p ())
0354e5d8
GK		 1648 {
1649 operands[3] = gen_reg_rtx (DImode);
1650 emit_move_insn (operands[3], operands[2]);
1651 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1652 DONE;
1653 }
1654 else
1655 FAIL;
279bb624 1656})
1fd4e8c1 1657
0354e5d8
GK		 1658(define_insn "one_cmpl<mode>2"
1659 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1660 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1661 ""
ca7f5001
RK		 1662 "nor %0,%1,%1")
1663
1664(define_insn ""
52d3af72 1665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 1666 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
ca7f5001 1667 (const_int 0)))
0354e5d8
GK		 1668 (clobber (match_scratch:P 2 "=r,r"))]
1669 ""
52d3af72
DE		 1670 "@
1671 nor. %2,%1,%1
1672 #"
1673 [(set_attr "type" "compare")
1674 (set_attr "length" "4,8")])
1675
1676(define_split
c921bad8 1677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
0354e5d8 1678 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1679 (const_int 0)))
0354e5d8
GK		 1680 (clobber (match_scratch:P 2 ""))]
1681 "reload_completed"
52d3af72 1682 [(set (match_dup 2)
0354e5d8 1683 (not:P (match_dup 1)))
52d3af72
DE		 1684 (set (match_dup 0)
1685 (compare:CC (match_dup 2)
1686 (const_int 0)))]
1687 "")
ca7f5001
RK		 1688
1689(define_insn ""
52d3af72 1690 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 1691 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 1692 (const_int 0)))
0354e5d8
GK		 1693 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1694 (not:P (match_dup 1)))]
1695 ""
52d3af72
DE		 1696 "@
1697 nor. %0,%1,%1
1698 #"
1699 [(set_attr "type" "compare")
1700 (set_attr "length" "4,8")])
1701
1702(define_split
c921bad8 1703 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
0354e5d8 1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1705 (const_int 0)))
0354e5d8
GK		 1706 (set (match_operand:P 0 "gpc_reg_operand" "")
1707 (not:P (match_dup 1)))]
1708 "reload_completed"
52d3af72 1709 [(set (match_dup 0)
0354e5d8 1710 (not:P (match_dup 1)))
52d3af72
DE		 1711 (set (match_dup 2)
1712 (compare:CC (match_dup 0)
1713 (const_int 0)))]
1714 "")
1fd4e8c1
RK		 1715
1716(define_insn ""
3d91674b
RK		 1717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1718 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1719 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1720 "! TARGET_POWERPC"
ca7f5001 1721 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1722
deb9225a 1723(define_insn ""
0354e5d8
GK		 1724 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1725 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1726 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
deb9225a
RK		 1727 "TARGET_POWERPC"
1728 "@
1729 subf %0,%2,%1
1730 subfic %0,%2,%1")
1731
1fd4e8c1 1732(define_insn ""
cb8cc086
MM		 1733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1734 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1735 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1736 (const_int 0)))
cb8cc086 1737 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1738 "! TARGET_POWERPC"
cb8cc086
MM		 1739 "@
1740 {sf.|subfc.} %3,%2,%1
1741 #"
1742 [(set_attr "type" "compare")
1743 (set_attr "length" "4,8")])
1fd4e8c1 1744
deb9225a 1745(define_insn ""
cb8cc086 1746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1747 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1748 (match_operand:P 2 "gpc_reg_operand" "r,r"))
deb9225a 1749 (const_int 0)))
0354e5d8
GK		 1750 (clobber (match_scratch:P 3 "=r,r"))]
1751 "TARGET_POWERPC"
cb8cc086
MM		 1752 "@
1753 subf. %3,%2,%1
1754 #"
a62bfff2 1755 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1756 (set_attr "length" "4,8")])
1757
1758(define_split
1759 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1760 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1761 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1762 (const_int 0)))
0354e5d8
GK		 1763 (clobber (match_scratch:P 3 ""))]
1764 "reload_completed"
cb8cc086 1765 [(set (match_dup 3)
0354e5d8 1766 (minus:P (match_dup 1)
cb8cc086
MM		 1767 (match_dup 2)))
1768 (set (match_dup 0)
1769 (compare:CC (match_dup 3)
1770 (const_int 0)))]
1771 "")
deb9225a 1772
1fd4e8c1 1773(define_insn ""
cb8cc086
MM		 1774 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1775 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1776 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1777 (const_int 0)))
cb8cc086 1778 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1779 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1780 "! TARGET_POWERPC"
cb8cc086
MM		 1781 "@
1782 {sf.|subfc.} %0,%2,%1
1783 #"
1784 [(set_attr "type" "compare")
1785 (set_attr "length" "4,8")])
815cdc52 1786
29ae5b89 1787(define_insn ""
cb8cc086 1788 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1789 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1790 (match_operand:P 2 "gpc_reg_operand" "r,r"))
815cdc52 1791 (const_int 0)))
0354e5d8
GK		 1792 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1793 (minus:P (match_dup 1)
cb8cc086 1794 (match_dup 2)))]
0354e5d8 1795 "TARGET_POWERPC"
90612787
DE		 1796 "@
1797 subf. %0,%2,%1
1798 #"
a62bfff2 1799 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1800 (set_attr "length" "4,8")])
1801
1802(define_split
1803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1804 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1805 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1806 (const_int 0)))
0354e5d8
GK		 1807 (set (match_operand:P 0 "gpc_reg_operand" "")
1808 (minus:P (match_dup 1)
cb8cc086 1809 (match_dup 2)))]
0354e5d8 1810 "reload_completed"
cb8cc086 1811 [(set (match_dup 0)
0354e5d8 1812 (minus:P (match_dup 1)
cb8cc086
MM		 1813 (match_dup 2)))
1814 (set (match_dup 3)
1815 (compare:CC (match_dup 0)
1816 (const_int 0)))]
1817 "")
deb9225a 1818
0354e5d8
GK		 1819(define_expand "sub<mode>3"
1820 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1821 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
4ae234b0 1822 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1fd4e8c1 1823 ""
a0044fb1
RK		 1824 "
1825{
1826 if (GET_CODE (operands[2]) == CONST_INT)
1827 {
0354e5d8
GK		 1828 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1829 negate_rtx (<MODE>mode, operands[2])));
a0044fb1
RK		 1830 DONE;
1831 }
1832}")
1fd4e8c1
RK		 1833
1834;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1835;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1836;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1837;; combine.
1fd4e8c1
RK		 1838
1839(define_expand "sminsi3"
1840 [(set (match_dup 3)
cd2b37d9 1841 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1842 (match_operand:SI 2 "reg_or_short_operand" ""))
1843 (const_int 0)
1844 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1845 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1846 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1847 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1848 "
a3170dc6
AH		 1849{
1850 if (TARGET_ISEL)
1851 {
1852 operands[2] = force_reg (SImode, operands[2]);
1853 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1854 DONE;
1855 }
1856
1857 operands[3] = gen_reg_rtx (SImode);
1858}")
1fd4e8c1 1859
95ac8e67
RK		 1860(define_split
1861 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1862 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1863 (match_operand:SI 2 "reg_or_short_operand" "")))
1864 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1865 "TARGET_POWER"
95ac8e67
RK		 1866 [(set (match_dup 3)
1867 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1868 (const_int 0)
1869 (minus:SI (match_dup 2) (match_dup 1))))
1870 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1871 "")
1872
1fd4e8c1
RK		 1873(define_expand "smaxsi3"
1874 [(set (match_dup 3)
cd2b37d9 1875 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1876 (match_operand:SI 2 "reg_or_short_operand" ""))
1877 (const_int 0)
1878 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1879 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1880 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1881 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1882 "
a3170dc6
AH		 1883{
1884 if (TARGET_ISEL)
1885 {
1886 operands[2] = force_reg (SImode, operands[2]);
1887 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1888 DONE;
1889 }
1890 operands[3] = gen_reg_rtx (SImode);
1891}")
1fd4e8c1 1892
95ac8e67
RK		 1893(define_split
1894 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1895 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1896 (match_operand:SI 2 "reg_or_short_operand" "")))
1897 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1898 "TARGET_POWER"
95ac8e67
RK		 1899 [(set (match_dup 3)
1900 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1901 (const_int 0)
1902 (minus:SI (match_dup 2) (match_dup 1))))
1903 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1904 "")
1905
1fd4e8c1 1906(define_expand "uminsi3"
cd2b37d9 1907 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1908 (match_dup 5)))
cd2b37d9 1909 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1910 (match_dup 5)))
1fd4e8c1
RK		 1911 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1912 (const_int 0)
1913 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1914 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1915 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1916 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1917 "
bb68ff55 1918{
a3170dc6
AH		 1919 if (TARGET_ISEL)
1920 {
1921 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1922 DONE;
1923 }
bb68ff55
MM		 1924 operands[3] = gen_reg_rtx (SImode);
1925 operands[4] = gen_reg_rtx (SImode);
1926 operands[5] = GEN_INT (-2147483647 - 1);
1927}")
1fd4e8c1
RK		 1928
1929(define_expand "umaxsi3"
cd2b37d9 1930 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1931 (match_dup 5)))
cd2b37d9 1932 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1933 (match_dup 5)))
1fd4e8c1
RK		 1934 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1935 (const_int 0)
1936 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1937 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1938 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1939 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1940 "
bb68ff55 1941{
a3170dc6
AH		 1942 if (TARGET_ISEL)
1943 {
1944 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1945 DONE;
1946 }
bb68ff55
MM		 1947 operands[3] = gen_reg_rtx (SImode);
1948 operands[4] = gen_reg_rtx (SImode);
1949 operands[5] = GEN_INT (-2147483647 - 1);
1950}")
1fd4e8c1
RK		 1951
1952(define_insn ""
cd2b37d9
RK		 1953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1954 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1955 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1956 (const_int 0)
1957 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1958 "TARGET_POWER"
1fd4e8c1
RK		 1959 "doz%I2 %0,%1,%2")
1960
1961(define_insn ""
9ebbca7d 1962 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1963 (compare:CC
9ebbca7d
GK		 1964 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1965 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1966 (const_int 0)
1967 (minus:SI (match_dup 2) (match_dup 1)))
1968 (const_int 0)))
9ebbca7d 1969 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1970 "TARGET_POWER"
9ebbca7d
GK		 1971 "@
1972 doz%I2. %3,%1,%2
1973 #"
1974 [(set_attr "type" "delayed_compare")
1975 (set_attr "length" "4,8")])
1976
1977(define_split
1978 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1979 (compare:CC
1980 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1981 (match_operand:SI 2 "reg_or_short_operand" ""))
1982 (const_int 0)
1983 (minus:SI (match_dup 2) (match_dup 1)))
1984 (const_int 0)))
1985 (clobber (match_scratch:SI 3 ""))]
1986 "TARGET_POWER && reload_completed"
1987 [(set (match_dup 3)
1988 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1989 (const_int 0)
1990 (minus:SI (match_dup 2) (match_dup 1))))
1991 (set (match_dup 0)
1992 (compare:CC (match_dup 3)
1993 (const_int 0)))]
1994 "")
1fd4e8c1
RK		 1995
1996(define_insn ""
9ebbca7d 1997 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1998 (compare:CC
9ebbca7d
GK		 1999 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2000 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 2001 (const_int 0)
2002 (minus:SI (match_dup 2) (match_dup 1)))
2003 (const_int 0)))
9ebbca7d 2004 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 2005 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2006 (const_int 0)
2007 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 2008 "TARGET_POWER"
9ebbca7d
GK		 2009 "@
2010 doz%I2. %0,%1,%2
2011 #"
2012 [(set_attr "type" "delayed_compare")
2013 (set_attr "length" "4,8")])
2014
2015(define_split
2016 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2017 (compare:CC
2018 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2019 (match_operand:SI 2 "reg_or_short_operand" ""))
2020 (const_int 0)
2021 (minus:SI (match_dup 2) (match_dup 1)))
2022 (const_int 0)))
2023 (set (match_operand:SI 0 "gpc_reg_operand" "")
2024 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2025 (const_int 0)
2026 (minus:SI (match_dup 2) (match_dup 1))))]
2027 "TARGET_POWER && reload_completed"
2028 [(set (match_dup 0)
2029 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2030 (const_int 0)
2031 (minus:SI (match_dup 2) (match_dup 1))))
2032 (set (match_dup 3)
2033 (compare:CC (match_dup 0)
2034 (const_int 0)))]
2035 "")
1fd4e8c1
RK		 2036
2037;; We don't need abs with condition code because such comparisons should
2038;; never be done.
ea9be077
MM		 2039(define_expand "abssi2"
2040 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2041 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2042 ""
2043 "
2044{
a3170dc6
AH		 2045 if (TARGET_ISEL)
2046 {
2047 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2048 DONE;
2049 }
2050 else if (! TARGET_POWER)
ea9be077
MM		 2051 {
2052 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2053 DONE;
2054 }
2055}")
2056
ea112fc4 2057(define_insn "*abssi2_power"
cd2b37d9
RK		 2058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2059 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 2060 "TARGET_POWER"
1fd4e8c1
RK		 2061 "abs %0,%1")
2062
a3170dc6
AH		 2063(define_insn_and_split "abssi2_isel"
2064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2065 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 2066 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 2067 (clobber (match_scratch:CC 3 "=y"))]
2068 "TARGET_ISEL"
2069 "#"
2070 "&& reload_completed"
2071 [(set (match_dup 2) (neg:SI (match_dup 1)))
2072 (set (match_dup 3)
2073 (compare:CC (match_dup 1)
2074 (const_int 0)))
2075 (set (match_dup 0)
2076 (if_then_else:SI (ge (match_dup 3)
2077 (const_int 0))
2078 (match_dup 1)
2079 (match_dup 2)))]
2080 "")
2081
ea112fc4 2082(define_insn_and_split "abssi2_nopower"
ea9be077 2083 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2084 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 2085 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 2086 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 2087 "#"
2088 "&& reload_completed"
ea9be077
MM		 2089 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2090 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2091 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 2092 "")
2093
463b558b 2094(define_insn "*nabs_power"
cd2b37d9
RK		 2095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2096 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 2097 "TARGET_POWER"
1fd4e8c1
RK		 2098 "nabs %0,%1")
2099
ea112fc4 2100(define_insn_and_split "*nabs_nopower"
ea9be077 2101 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2102 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 2103 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 2104 "! TARGET_POWER"
ea112fc4
DE		 2105 "#"
2106 "&& reload_completed"
ea9be077
MM		 2107 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2108 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2109 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 2110 "")
2111
0354e5d8
GK		 2112(define_expand "neg<mode>2"
2113 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2114 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2115 ""
2116 "")
2117
2118(define_insn "*neg<mode>2_internal"
2119 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2120 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 2121 ""
2122 "neg %0,%1")
2123
2124(define_insn ""
9ebbca7d 2125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 2126 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 2127 (const_int 0)))
0354e5d8
GK		 2128 (clobber (match_scratch:P 2 "=r,r"))]
2129 ""
9ebbca7d
GK		 2130 "@
2131 neg. %2,%1
2132 #"
a62bfff2 2133 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2134 (set_attr "length" "4,8")])
2135
2136(define_split
2137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 2138 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2139 (const_int 0)))
0354e5d8
GK		 2140 (clobber (match_scratch:P 2 ""))]
2141 "reload_completed"
9ebbca7d 2142 [(set (match_dup 2)
0354e5d8 2143 (neg:P (match_dup 1)))
9ebbca7d
GK		 2144 (set (match_dup 0)
2145 (compare:CC (match_dup 2)
2146 (const_int 0)))]
2147 "")
1fd4e8c1
RK		 2148
2149(define_insn ""
9ebbca7d 2150 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 2151 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 2152 (const_int 0)))
0354e5d8
GK		 2153 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2154 (neg:P (match_dup 1)))]
2155 ""
9ebbca7d
GK		 2156 "@
2157 neg. %0,%1
2158 #"
a62bfff2 2159 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2160 (set_attr "length" "4,8")])
2161
2162(define_split
2163 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 2164 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2165 (const_int 0)))
0354e5d8
GK		 2166 (set (match_operand:P 0 "gpc_reg_operand" "")
2167 (neg:P (match_dup 1)))]
66859ace 2168 "reload_completed"
9ebbca7d 2169 [(set (match_dup 0)
0354e5d8 2170 (neg:P (match_dup 1)))
9ebbca7d
GK		 2171 (set (match_dup 2)
2172 (compare:CC (match_dup 0)
2173 (const_int 0)))]
2174 "")
1fd4e8c1 2175
0354e5d8
GK		 2176(define_insn "clz<mode>2"
2177 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2178 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1b1edcfa 2179 ""
44cd321e
PS		 2180 "{cntlz|cntlz<wd>} %0,%1"
2181 [(set_attr "type" "cntlz")])
1b1edcfa 2182
0354e5d8 2183(define_expand "ctz<mode>2"
4977bab6 2184 [(set (match_dup 2)
e42ac3de 2185 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2186 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2187 (match_dup 2)))
1b1edcfa 2188 (clobber (scratch:CC))])
0354e5d8 2189 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2190 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2191 (minus:GPR (match_dup 5) (match_dup 4)))]
1fd4e8c1 2192 ""
4977bab6 2193 {
0354e5d8
GK		 2194 operands[2] = gen_reg_rtx (<MODE>mode);
2195 operands[3] = gen_reg_rtx (<MODE>mode);
2196 operands[4] = gen_reg_rtx (<MODE>mode);
2197 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
4977bab6 2198 })
6ae08853 2199
0354e5d8 2200(define_expand "ffs<mode>2"
1b1edcfa 2201 [(set (match_dup 2)
e42ac3de 2202 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2203 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2204 (match_dup 2)))
1b1edcfa 2205 (clobber (scratch:CC))])
0354e5d8 2206 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2207 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2208 (minus:GPR (match_dup 5) (match_dup 4)))]
4977bab6 2209 ""
1b1edcfa 2210 {
0354e5d8
GK		 2211 operands[2] = gen_reg_rtx (<MODE>mode);
2212 operands[3] = gen_reg_rtx (<MODE>mode);
2213 operands[4] = gen_reg_rtx (<MODE>mode);
2214 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1b1edcfa 2215 })
6ae08853 2216
432218ba
DE		 2217(define_insn "popcntb<mode>2"
2218 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2219 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2220 UNSPEC_POPCNTB))]
2221 "TARGET_POPCNTB"
2222 "popcntb %0,%1")
2223
565ef4ba 2224(define_expand "popcount<mode>2"
e42ac3de
RS		 2225 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2226 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2227 "TARGET_POPCNTB"
2228 {
2229 rs6000_emit_popcount (operands[0], operands[1]);
2230 DONE;
2231 })
2232
2233(define_expand "parity<mode>2"
e42ac3de
RS		 2234 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2235 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2236 "TARGET_POPCNTB"
2237 {
2238 rs6000_emit_parity (operands[0], operands[1]);
2239 DONE;
2240 })
2241
03f79051
DE		 2242(define_insn "bswapsi2"
2243 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2244 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2245 ""
2246 "@
2247 {lbrx|lwbrx} %0,%y1
2248 {stbrx|stwbrx} %1,%y0
2249 #"
2250 [(set_attr "length" "4,4,12")])
2251
2252(define_split
2253 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2254 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2255 "reload_completed"
2256 [(set (match_dup 0)
2257 (rotate:SI (match_dup 1) (const_int 8)))
2258 (set (zero_extract:SI (match_dup 0)
2259 (const_int 8)
2260 (const_int 0))
2261 (match_dup 1))
2262 (set (zero_extract:SI (match_dup 0)
2263 (const_int 8)
2264 (const_int 16))
2265 (rotate:SI (match_dup 1)
2266 (const_int 16)))]
2267 "")
2268
ca7f5001
RK		 2269(define_expand "mulsi3"
2270 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2271 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2272 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2273 ""
2274 "
2275{
2276 if (TARGET_POWER)
68b40e7e 2277 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 2278 else
68b40e7e 2279 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 2280 DONE;
2281}")
2282
68b40e7e 2283(define_insn "mulsi3_mq"
cd2b37d9
RK		 2284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2285 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 2286 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2287 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 2288 "TARGET_POWER"
2289 "@
2290 {muls|mullw} %0,%1,%2
2291 {muli|mulli} %0,%1,%2"
6ae08853 2292 [(set (attr "type")
c859cda6
DJ		 2293 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2294 (const_string "imul3")
6ae08853 2295 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2296 (const_string "imul2")]
2297 (const_string "imul")))])
ca7f5001 2298
68b40e7e 2299(define_insn "mulsi3_no_mq"
ca7f5001
RK		 2300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2301 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2302 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 2303 "! TARGET_POWER"
1fd4e8c1 2304 "@
d904e9ed
RK		 2305 {muls|mullw} %0,%1,%2
2306 {muli|mulli} %0,%1,%2"
6ae08853 2307 [(set (attr "type")
c859cda6
DJ		 2308 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2309 (const_string "imul3")
6ae08853 2310 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2311 (const_string "imul2")]
2312 (const_string "imul")))])
1fd4e8c1 2313
9259f3b0 2314(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 2315 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2316 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2317 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2318 (const_int 0)))
9ebbca7d
GK		 2319 (clobber (match_scratch:SI 3 "=r,r"))
2320 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2321 "TARGET_POWER"
9ebbca7d
GK		 2322 "@
2323 {muls.|mullw.} %3,%1,%2
2324 #"
9259f3b0 2325 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2326 (set_attr "length" "4,8")])
2327
2328(define_split
2329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2330 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2331 (match_operand:SI 2 "gpc_reg_operand" ""))
2332 (const_int 0)))
2333 (clobber (match_scratch:SI 3 ""))
2334 (clobber (match_scratch:SI 4 ""))]
2335 "TARGET_POWER && reload_completed"
2336 [(parallel [(set (match_dup 3)
2337 (mult:SI (match_dup 1) (match_dup 2)))
2338 (clobber (match_dup 4))])
2339 (set (match_dup 0)
2340 (compare:CC (match_dup 3)
2341 (const_int 0)))]
2342 "")
ca7f5001 2343
9259f3b0 2344(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 2345 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2346 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2347 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2348 (const_int 0)))
9ebbca7d 2349 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 2350 "! TARGET_POWER"
9ebbca7d
GK		 2351 "@
2352 {muls.|mullw.} %3,%1,%2
2353 #"
9259f3b0 2354 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2355 (set_attr "length" "4,8")])
2356
2357(define_split
c921bad8 2358 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 2359 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2360 (match_operand:SI 2 "gpc_reg_operand" ""))
2361 (const_int 0)))
2362 (clobber (match_scratch:SI 3 ""))]
2363 "! TARGET_POWER && reload_completed"
2364 [(set (match_dup 3)
2365 (mult:SI (match_dup 1) (match_dup 2)))
2366 (set (match_dup 0)
2367 (compare:CC (match_dup 3)
2368 (const_int 0)))]
2369 "")
1fd4e8c1 2370
9259f3b0 2371(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 2372 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2373 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2374 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2375 (const_int 0)))
9ebbca7d 2376 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 2377 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 2378 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2379 "TARGET_POWER"
9ebbca7d
GK		 2380 "@
2381 {muls.|mullw.} %0,%1,%2
2382 #"
9259f3b0 2383 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2384 (set_attr "length" "4,8")])
2385
2386(define_split
2387 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2388 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2389 (match_operand:SI 2 "gpc_reg_operand" ""))
2390 (const_int 0)))
2391 (set (match_operand:SI 0 "gpc_reg_operand" "")
2392 (mult:SI (match_dup 1) (match_dup 2)))
2393 (clobber (match_scratch:SI 4 ""))]
2394 "TARGET_POWER && reload_completed"
2395 [(parallel [(set (match_dup 0)
2396 (mult:SI (match_dup 1) (match_dup 2)))
2397 (clobber (match_dup 4))])
2398 (set (match_dup 3)
2399 (compare:CC (match_dup 0)
2400 (const_int 0)))]
2401 "")
ca7f5001 2402
9259f3b0 2403(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 2404 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2405 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2406 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2407 (const_int 0)))
9ebbca7d 2408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 2409 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 2410 "! TARGET_POWER"
9ebbca7d
GK		 2411 "@
2412 {muls.|mullw.} %0,%1,%2
2413 #"
9259f3b0 2414 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2415 (set_attr "length" "4,8")])
2416
2417(define_split
c921bad8 2418 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 2419 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2420 (match_operand:SI 2 "gpc_reg_operand" ""))
2421 (const_int 0)))
2422 (set (match_operand:SI 0 "gpc_reg_operand" "")
2423 (mult:SI (match_dup 1) (match_dup 2)))]
2424 "! TARGET_POWER && reload_completed"
2425 [(set (match_dup 0)
2426 (mult:SI (match_dup 1) (match_dup 2)))
2427 (set (match_dup 3)
2428 (compare:CC (match_dup 0)
2429 (const_int 0)))]
2430 "")
1fd4e8c1
RK		 2431
2432;; Operand 1 is divided by operand 2; quotient goes to operand
2433;; 0 and remainder to operand 3.
2434;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2435
8ffd9c51
RK		 2436(define_expand "divmodsi4"
2437 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2438 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2439 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 2440 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 2441 (mod:SI (match_dup 1) (match_dup 2)))])]
2442 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2443 "
2444{
2445 if (! TARGET_POWER && ! TARGET_POWERPC)
2446 {
39403d82
DE		 2447 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2448 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2449 emit_insn (gen_divss_call ());
39403d82
DE		 2450 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2451 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 2452 DONE;
2453 }
2454}")
deb9225a 2455
bb157ff4 2456(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 2457 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2458 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2459 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 2460 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 2461 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 2462 "TARGET_POWER"
cfb557c4
RK		 2463 "divs %0,%1,%2"
2464 [(set_attr "type" "idiv")])
1fd4e8c1 2465
4ae234b0
GK		 2466(define_expand "udiv<mode>3"
2467 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2468 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2469 (match_operand:GPR 2 "gpc_reg_operand" "")))]
8ffd9c51
RK		 2470 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2471 "
2472{
2473 if (! TARGET_POWER && ! TARGET_POWERPC)
2474 {
39403d82
DE		 2475 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2476 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2477 emit_insn (gen_quous_call ());
39403d82 2478 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2479 DONE;
2480 }
f192bf8b
DE		 2481 else if (TARGET_POWER)
2482 {
2483 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2484 DONE;
2485 }
8ffd9c51 2486}")
deb9225a 2487
f192bf8b
DE		 2488(define_insn "udivsi3_mq"
2489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2490 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2491 (match_operand:SI 2 "gpc_reg_operand" "r")))
2492 (clobber (match_scratch:SI 3 "=q"))]
2493 "TARGET_POWERPC && TARGET_POWER"
2494 "divwu %0,%1,%2"
2495 [(set_attr "type" "idiv")])
2496
2497(define_insn "*udivsi3_no_mq"
4ae234b0
GK		 2498 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2499 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2500 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2501 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2502 "div<wd>u %0,%1,%2"
44cd321e
PS		 2503 [(set (attr "type")
2504 (cond [(match_operand:SI 0 "" "")
2505 (const_string "idiv")]
2506 (const_string "ldiv")))])
2507
ca7f5001 2508
1fd4e8c1 2509;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 2510;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 2511;; used; for PowerPC, force operands into register and do a normal divide;
2512;; for AIX common-mode, use quoss call on register operands.
4ae234b0
GK		 2513(define_expand "div<mode>3"
2514 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2515 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2516 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1fd4e8c1
RK		 2517 ""
2518 "
2519{
ca7f5001 2520 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 2521 && INTVAL (operands[2]) > 0
ca7f5001
RK		 2522 && exact_log2 (INTVAL (operands[2])) >= 0)
2523 ;
b6c9286a 2524 else if (TARGET_POWERPC)
f192bf8b 2525 {
99e8e649 2526 operands[2] = force_reg (<MODE>mode, operands[2]);
f192bf8b
DE		 2527 if (TARGET_POWER)
2528 {
2529 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2530 DONE;
2531 }
2532 }
b6c9286a 2533 else if (TARGET_POWER)
1fd4e8c1 2534 FAIL;
405c5495 2535 else
8ffd9c51 2536 {
39403d82
DE		 2537 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2538 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2539 emit_insn (gen_quoss_call ());
39403d82 2540 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2541 DONE;
2542 }
1fd4e8c1
RK		 2543}")
2544
f192bf8b
DE		 2545(define_insn "divsi3_mq"
2546 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2547 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2548 (match_operand:SI 2 "gpc_reg_operand" "r")))
2549 (clobber (match_scratch:SI 3 "=q"))]
2550 "TARGET_POWERPC && TARGET_POWER"
2551 "divw %0,%1,%2"
2552 [(set_attr "type" "idiv")])
2553
4ae234b0
GK		 2554(define_insn "*div<mode>3_no_mq"
2555 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2556 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2557 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2558 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2559 "div<wd> %0,%1,%2"
44cd321e
PS		 2560 [(set (attr "type")
2561 (cond [(match_operand:SI 0 "" "")
2562 (const_string "idiv")]
2563 (const_string "ldiv")))])
f192bf8b 2564
4ae234b0
GK		 2565(define_expand "mod<mode>3"
2566 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2567 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2568 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
39b52ba2 2569 ""
1fd4e8c1
RK		 2570 "
2571{
481c7efa 2572 int i;
39b52ba2
RK		 2573 rtx temp1;
2574 rtx temp2;
2575
2bfcf297 2576 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 2577 || INTVAL (operands[2]) <= 0
2bfcf297 2578 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 2579 FAIL;
2580
4ae234b0
GK		 2581 temp1 = gen_reg_rtx (<MODE>mode);
2582 temp2 = gen_reg_rtx (<MODE>mode);
1fd4e8c1 2583
4ae234b0
GK		 2584 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2585 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2586 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
85644414 2587 DONE;
1fd4e8c1
RK		 2588}")
2589
2590(define_insn ""
4ae234b0
GK		 2591 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2592 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2593 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2bfcf297 2594 ""
4ae234b0 2595 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
943c15ed
DE		 2596 [(set_attr "type" "two")
2597 (set_attr "length" "8")])
1fd4e8c1
RK		 2598
2599(define_insn ""
9ebbca7d 2600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2601 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2602 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2603 (const_int 0)))
4ae234b0 2604 (clobber (match_scratch:P 3 "=r,r"))]
2bfcf297 2605 ""
9ebbca7d 2606 "@
4ae234b0 2607 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
9ebbca7d 2608 #"
b19003d8 2609 [(set_attr "type" "compare")
c921bad8
AP		 2610 (set_attr "length" "8,12")
2611 (set_attr "cell_micro" "not")])
9ebbca7d
GK		 2612
2613(define_split
2614 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2615 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2616 (match_operand:GPR 2 "exact_log2_cint_operand"
2617 ""))
9ebbca7d 2618 (const_int 0)))
4ae234b0 2619 (clobber (match_scratch:GPR 3 ""))]
2bfcf297 2620 "reload_completed"
9ebbca7d 2621 [(set (match_dup 3)
4ae234b0 2622 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2623 (set (match_dup 0)
2624 (compare:CC (match_dup 3)
2625 (const_int 0)))]
2626 "")
1fd4e8c1
RK		 2627
2628(define_insn ""
9ebbca7d 2629 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2630 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2631 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2632 (const_int 0)))
4ae234b0
GK		 2633 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2634 (div:P (match_dup 1) (match_dup 2)))]
2bfcf297 2635 ""
9ebbca7d 2636 "@
4ae234b0 2637 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
9ebbca7d 2638 #"
b19003d8 2639 [(set_attr "type" "compare")
c921bad8
AP		 2640 (set_attr "length" "8,12")
2641 (set_attr "cell_micro" "not")])
9ebbca7d
GK		 2642
2643(define_split
2644 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2645 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2646 (match_operand:GPR 2 "exact_log2_cint_operand"
2647 ""))
9ebbca7d 2648 (const_int 0)))
4ae234b0
GK		 2649 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2650 (div:GPR (match_dup 1) (match_dup 2)))]
2bfcf297 2651 "reload_completed"
9ebbca7d 2652 [(set (match_dup 0)
4ae234b0 2653 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2654 (set (match_dup 3)
2655 (compare:CC (match_dup 0)
2656 (const_int 0)))]
2657 "")
1fd4e8c1
RK		 2658
2659(define_insn ""
cd2b37d9 2660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2661 (udiv:SI
996a5f59 2662 (plus:DI (ashift:DI
cd2b37d9 2663 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2664 (const_int 32))
23a900dc 2665 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2666 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2667 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2668 (umod:SI
996a5f59 2669 (plus:DI (ashift:DI
1fd4e8c1 2670 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2671 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2672 (match_dup 3)))]
ca7f5001 2673 "TARGET_POWER"
cfb557c4
RK		 2674 "div %0,%1,%3"
2675 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2676
2677;; To do unsigned divide we handle the cases of the divisor looking like a
2678;; negative number. If it is a constant that is less than 2**31, we don't
2679;; have to worry about the branches. So make a few subroutines here.
2680;;
2681;; First comes the normal case.
2682(define_expand "udivmodsi4_normal"
2683 [(set (match_dup 4) (const_int 0))
2684 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2685 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2686 (const_int 32))
2687 (zero_extend:DI (match_operand:SI 1 "" "")))
2688 (match_operand:SI 2 "" "")))
2689 (set (match_operand:SI 3 "" "")
996a5f59 2690 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2691 (const_int 32))
2692 (zero_extend:DI (match_dup 1)))
2693 (match_dup 2)))])]
ca7f5001 2694 "TARGET_POWER"
1fd4e8c1
RK		 2695 "
2696{ operands[4] = gen_reg_rtx (SImode); }")
2697
2698;; This handles the branches.
2699(define_expand "udivmodsi4_tests"
2700 [(set (match_operand:SI 0 "" "") (const_int 0))
2701 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2702 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2703 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2704 (label_ref (match_operand:SI 4 "" "")) (pc)))
2705 (set (match_dup 0) (const_int 1))
2706 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2707 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2708 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2709 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2710 "TARGET_POWER"
1fd4e8c1
RK		 2711 "
2712{ operands[5] = gen_reg_rtx (CCUNSmode);
2713 operands[6] = gen_reg_rtx (CCmode);
2714}")
2715
2716(define_expand "udivmodsi4"
cd2b37d9
RK		 2717 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2718 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2719 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2720 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2721 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2722 ""
1fd4e8c1
RK		 2723 "
2724{
2725 rtx label = 0;
2726
8ffd9c51 2727 if (! TARGET_POWER)
c4d38ccb
MM		 2728 {
2729 if (! TARGET_POWERPC)
2730 {
39403d82
DE		 2731 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2732 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2733 emit_insn (gen_divus_call ());
39403d82
DE		 2734 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2735 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2736 DONE;
2737 }
2738 else
2739 FAIL;
2740 }
0081a354 2741
1fd4e8c1
RK		 2742 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2743 {
2744 operands[2] = force_reg (SImode, operands[2]);
2745 label = gen_label_rtx ();
2746 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2747 operands[3], label));
2748 }
2749 else
2750 operands[2] = force_reg (SImode, operands[2]);
2751
2752 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2753 operands[3]));
2754 if (label)
2755 emit_label (label);
2756
2757 DONE;
2758}")
0081a354 2759
fada905b
MM		 2760;; AIX architecture-independent common-mode multiply (DImode),
2761;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2762;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2763;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2764;; assumed unused if generating common-mode, so ignore.
2765(define_insn "mulh_call"
2766 [(set (reg:SI 3)
2767 (truncate:SI
2768 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2769 (sign_extend:DI (reg:SI 4)))
2770 (const_int 32))))
1de43f85 2771 (clobber (reg:SI LR_REGNO))]
fada905b 2772 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2773 "bla __mulh"
2774 [(set_attr "type" "imul")])
fada905b
MM		 2775
2776(define_insn "mull_call"
2777 [(set (reg:DI 3)
2778 (mult:DI (sign_extend:DI (reg:SI 3))
2779 (sign_extend:DI (reg:SI 4))))
1de43f85 2780 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2781 (clobber (reg:SI 0))]
2782 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2783 "bla __mull"
2784 [(set_attr "type" "imul")])
fada905b
MM		 2785
2786(define_insn "divss_call"
2787 [(set (reg:SI 3)
2788 (div:SI (reg:SI 3) (reg:SI 4)))
2789 (set (reg:SI 4)
2790 (mod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2791 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2792 (clobber (reg:SI 0))]
2793 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2794 "bla __divss"
2795 [(set_attr "type" "idiv")])
fada905b
MM		 2796
2797(define_insn "divus_call"
8ffd9c51
RK		 2798 [(set (reg:SI 3)
2799 (udiv:SI (reg:SI 3) (reg:SI 4)))
2800 (set (reg:SI 4)
2801 (umod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2802 (clobber (reg:SI LR_REGNO))
fada905b 2803 (clobber (reg:SI 0))
e65a3857 2804 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2805 (clobber (reg:CC CR1_REGNO))]
fada905b 2806 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2807 "bla __divus"
2808 [(set_attr "type" "idiv")])
fada905b
MM		 2809
2810(define_insn "quoss_call"
2811 [(set (reg:SI 3)
2812 (div:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2813 (clobber (reg:SI LR_REGNO))]
8ffd9c51 2814 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2815 "bla __quoss"
2816 [(set_attr "type" "idiv")])
0081a354 2817
fada905b
MM		 2818(define_insn "quous_call"
2819 [(set (reg:SI 3)
2820 (udiv:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2821 (clobber (reg:SI LR_REGNO))
fada905b 2822 (clobber (reg:SI 0))
e65a3857 2823 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2824 (clobber (reg:CC CR1_REGNO))]
fada905b 2825 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2826 "bla __quous"
2827 [(set_attr "type" "idiv")])
8ffd9c51 2828\f
bb21487f 2829;; Logical instructions
dfbdccdb
GK		 2830;; The logical instructions are mostly combined by using match_operator,
2831;; but the plain AND insns are somewhat different because there is no
2832;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2833;; those rotate-and-mask operations. Thus, the AND insns come first.
2834
c921bad8
AP		 2835(define_expand "andsi3"
2836 [(parallel
2837 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2838 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2839 (match_operand:SI 2 "and_operand" "")))
2840 (clobber (match_scratch:CC 3 ""))])]
2841 ""
2842 "")
2843
2844(define_insn "andsi3_mc"
29ae5b89
JL		 2845 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2846 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2847 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2848 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
c921bad8 2849 "rs6000_gen_cell_microcode"
1fd4e8c1
RK		 2850 "@
2851 and %0,%1,%2
ca7f5001
RK		 2852 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2853 {andil.|andi.} %0,%1,%b2
520308bc
DE		 2854 {andiu.|andis.} %0,%1,%u2"
2855 [(set_attr "type" "*,*,compare,compare")])
52d3af72 2856
c921bad8
AP		 2857(define_insn "andsi3_nomc"
2858 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2859 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2860 (match_operand:SI 2 "and_operand" "?r,T")))
2861 (clobber (match_scratch:CC 3 "=X,X"))]
2862 "!rs6000_gen_cell_microcode"
2863 "@
2864 and %0,%1,%2
2865 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
2866
2867(define_insn "andsi3_internal0_nomc"
2868 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2869 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2870 (match_operand:SI 2 "and_operand" "?r,T")))]
2871 "!rs6000_gen_cell_microcode"
2872 "@
2873 and %0,%1,%2
2874 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
2875
2876
52d3af72 2877;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2878;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2879;; machines causes an execution serialization
1fd4e8c1 2880
c921bad8 2881(define_insn "*andsi3_internal2_mc"
52d3af72
DE		 2882 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2883 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2884 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2885 (const_int 0)))
52d3af72
DE		 2886 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2887 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
c921bad8 2888 "TARGET_32BIT && rs6000_gen_cell_microcode"
1fd4e8c1
RK		 2889 "@
2890 and. %3,%1,%2
ca7f5001
RK		 2891 {andil.|andi.} %3,%1,%b2
2892 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2893 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2894 #
2895 #
2896 #
2897 #"
2898 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2899 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2900
c921bad8 2901(define_insn "*andsi3_internal3_mc"
0ba1b2ff
AM		 2902 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2903 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2904 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2905 (const_int 0)))
2906 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2907 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
c921bad8 2908 "TARGET_64BIT && rs6000_gen_cell_microcode"
0ba1b2ff
AM		 2909 "@
2910 #
2911 {andil.|andi.} %3,%1,%b2
2912 {andiu.|andis.} %3,%1,%u2
2913 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2914 #
2915 #
2916 #
2917 #"
2918 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2919 (set_attr "length" "8,4,4,4,8,8,8,8")])
2920
52d3af72 2921(define_split
c921bad8 2922 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4ae234b0
GK		 2923 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2924 (match_operand:GPR 2 "and_operand" ""))
1fd4e8c1 2925 (const_int 0)))
4ae234b0 2926 (clobber (match_scratch:GPR 3 ""))
52d3af72 2927 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2928 "reload_completed"
52d3af72 2929 [(parallel [(set (match_dup 3)
4ae234b0
GK		 2930 (and:<MODE> (match_dup 1)
2931 (match_dup 2)))
52d3af72
DE		 2932 (clobber (match_dup 4))])
2933 (set (match_dup 0)
2934 (compare:CC (match_dup 3)
2935 (const_int 0)))]
2936 "")
2937
0ba1b2ff
AM		 2938;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2939;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2940
2941(define_split
2942 [(set (match_operand:CC 0 "cc_reg_operand" "")
2943 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2944 (match_operand:SI 2 "gpc_reg_operand" ""))
2945 (const_int 0)))
2946 (clobber (match_scratch:SI 3 ""))
2947 (clobber (match_scratch:CC 4 ""))]
2948 "TARGET_POWERPC64 && reload_completed"
2949 [(parallel [(set (match_dup 3)
2950 (and:SI (match_dup 1)
2951 (match_dup 2)))
2952 (clobber (match_dup 4))])
2953 (set (match_dup 0)
2954 (compare:CC (match_dup 3)
2955 (const_int 0)))]
2956 "")
2957
2958(define_insn "*andsi3_internal4"
52d3af72
DE		 2959 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2960 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2961 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2962 (const_int 0)))
2963 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2964 (and:SI (match_dup 1)
2965 (match_dup 2)))
2966 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
c921bad8 2967 "TARGET_32BIT && rs6000_gen_cell_microcode"
1fd4e8c1
RK		 2968 "@
2969 and. %0,%1,%2
ca7f5001
RK		 2970 {andil.|andi.} %0,%1,%b2
2971 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2972 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2973 #
2974 #
2975 #
2976 #"
2977 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2978 (set_attr "length" "4,4,4,4,8,8,8,8")])
2979
c921bad8 2980(define_insn "*andsi3_internal5_mc"
0ba1b2ff
AM		 2981 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2982 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2983 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2984 (const_int 0)))
2985 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2986 (and:SI (match_dup 1)
2987 (match_dup 2)))
2988 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
c921bad8 2989 "TARGET_64BIT && rs6000_gen_cell_microcode"
0ba1b2ff
AM		 2990 "@
2991 #
2992 {andil.|andi.} %0,%1,%b2
2993 {andiu.|andis.} %0,%1,%u2
2994 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2995 #
2996 #
2997 #
2998 #"
2999 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
3000 (set_attr "length" "8,4,4,4,8,8,8,8")])
3001
52d3af72 3002(define_split
c921bad8 3003 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
52d3af72
DE		 3004 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3005 (match_operand:SI 2 "and_operand" ""))
3006 (const_int 0)))
3007 (set (match_operand:SI 0 "gpc_reg_operand" "")
3008 (and:SI (match_dup 1)
3009 (match_dup 2)))
3010 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 3011 "reload_completed"
52d3af72
DE		 3012 [(parallel [(set (match_dup 0)
3013 (and:SI (match_dup 1)
3014 (match_dup 2)))
3015 (clobber (match_dup 4))])
3016 (set (match_dup 3)
3017 (compare:CC (match_dup 0)
3018 (const_int 0)))]
3019 "")
1fd4e8c1 3020
0ba1b2ff
AM		 3021(define_split
3022 [(set (match_operand:CC 3 "cc_reg_operand" "")
3023 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3024 (match_operand:SI 2 "gpc_reg_operand" ""))
3025 (const_int 0)))
3026 (set (match_operand:SI 0 "gpc_reg_operand" "")
3027 (and:SI (match_dup 1)
3028 (match_dup 2)))
3029 (clobber (match_scratch:CC 4 ""))]
3030 "TARGET_POWERPC64 && reload_completed"
3031 [(parallel [(set (match_dup 0)
3032 (and:SI (match_dup 1)
3033 (match_dup 2)))
3034 (clobber (match_dup 4))])
3035 (set (match_dup 3)
3036 (compare:CC (match_dup 0)
3037 (const_int 0)))]
3038 "")
3039
3040;; Handle the PowerPC64 rlwinm corner case
3041
3042(define_insn_and_split "*andsi3_internal6"
3043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3044 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3045 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3046 "TARGET_POWERPC64"
3047 "#"
3048 "TARGET_POWERPC64"
3049 [(set (match_dup 0)
3050 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3051 (match_dup 4)))
3052 (set (match_dup 0)
3053 (rotate:SI (match_dup 0) (match_dup 5)))]
3054 "
3055{
3056 int mb = extract_MB (operands[2]);
3057 int me = extract_ME (operands[2]);
3058 operands[3] = GEN_INT (me + 1);
3059 operands[5] = GEN_INT (32 - (me + 1));
3060 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3061}"
3062 [(set_attr "length" "8")])
3063
7cd5235b 3064(define_expand "iorsi3"
cd2b37d9 3065 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3066 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3067 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 3068 ""
f357808b
RK		 3069 "
3070{
7cd5235b 3071 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3072 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3073 {
3074 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3075 rtx tmp = ((!can_create_pseudo_p ()
3076 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3077 ? operands[0] : gen_reg_rtx (SImode));
3078
a260abc9
DE		 3079 emit_insn (gen_iorsi3 (tmp, operands[1],
3080 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3081 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3082 DONE;
3083 }
f357808b
RK		 3084}")
3085
7cd5235b 3086(define_expand "xorsi3"
cd2b37d9 3087 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3088 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3089 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 3090 ""
7cd5235b 3091 "
1fd4e8c1 3092{
7cd5235b 3093 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3094 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3095 {
3096 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3097 rtx tmp = ((!can_create_pseudo_p ()
3098 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3099 ? operands[0] : gen_reg_rtx (SImode));
3100
a260abc9
DE		 3101 emit_insn (gen_xorsi3 (tmp, operands[1],
3102 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3103 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3104 DONE;
3105 }
1fd4e8c1
RK		 3106}")
3107
dfbdccdb 3108(define_insn "*boolsi3_internal1"
7cd5235b 3109 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 3110 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3111 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3112 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 3113 ""
3114 "@
dfbdccdb
GK		 3115 %q3 %0,%1,%2
3116 {%q3il|%q3i} %0,%1,%b2
3117 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 3118
dfbdccdb 3119(define_insn "*boolsi3_internal2"
52d3af72 3120 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 3121 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 3122 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3123 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3124 (const_int 0)))
52d3af72 3125 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3126 "TARGET_32BIT"
52d3af72 3127 "@
dfbdccdb 3128 %q4. %3,%1,%2
52d3af72
DE		 3129 #"
3130 [(set_attr "type" "compare")
3131 (set_attr "length" "4,8")])
3132
3133(define_split
c921bad8 3134 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3135 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3136 [(match_operand:SI 1 "gpc_reg_operand" "")
3137 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3138 (const_int 0)))
52d3af72 3139 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3140 "TARGET_32BIT && reload_completed"
dfbdccdb 3141 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3142 (set (match_dup 0)
3143 (compare:CC (match_dup 3)
3144 (const_int 0)))]
3145 "")
815cdc52 3146
dfbdccdb 3147(define_insn "*boolsi3_internal3"
52d3af72 3148 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3149 (compare:CC (match_operator:SI 4 "boolean_operator"
3150 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3151 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3152 (const_int 0)))
52d3af72 3153 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3154 (match_dup 4))]
4b8a63d6 3155 "TARGET_32BIT"
52d3af72 3156 "@
dfbdccdb 3157 %q4. %0,%1,%2
52d3af72
DE		 3158 #"
3159 [(set_attr "type" "compare")
3160 (set_attr "length" "4,8")])
3161
3162(define_split
c921bad8 3163 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3164 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3165 [(match_operand:SI 1 "gpc_reg_operand" "")
3166 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3167 (const_int 0)))
75540af0 3168 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3169 (match_dup 4))]
4b8a63d6 3170 "TARGET_32BIT && reload_completed"
dfbdccdb 3171 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3172 (set (match_dup 3)
3173 (compare:CC (match_dup 0)
3174 (const_int 0)))]
3175 "")
1fd4e8c1 3176
6ae08853 3177;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 3178;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 3179
3180(define_split
3181 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 3182 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3183 [(match_operand:SI 1 "gpc_reg_operand" "")
3184 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 3185 ""
dfbdccdb
GK		 3186 [(set (match_dup 0) (match_dup 4))
3187 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 3188"
3189{
dfbdccdb
GK		 3190 rtx i;
3191 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1c563bed 3192 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3193 operands[1], i);
dfbdccdb 3194 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
1c563bed 3195 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3196 operands[0], i);
a260abc9
DE		 3197}")
3198
dfbdccdb 3199(define_insn "*boolcsi3_internal1"
cd2b37d9 3200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3201 (match_operator:SI 3 "boolean_operator"
3202 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3203 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 3204 ""
dfbdccdb 3205 "%q3 %0,%2,%1")
1fd4e8c1 3206
dfbdccdb 3207(define_insn "*boolcsi3_internal2"
52d3af72 3208 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3209 (compare:CC (match_operator:SI 4 "boolean_operator"
3210 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3211 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3212 (const_int 0)))
52d3af72 3213 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3214 "TARGET_32BIT"
52d3af72 3215 "@
dfbdccdb 3216 %q4. %3,%2,%1
52d3af72
DE		 3217 #"
3218 [(set_attr "type" "compare")
3219 (set_attr "length" "4,8")])
3220
3221(define_split
c921bad8 3222 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3223 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3224 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3225 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3226 (const_int 0)))
52d3af72 3227 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3228 "TARGET_32BIT && reload_completed"
dfbdccdb 3229 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3230 (set (match_dup 0)
3231 (compare:CC (match_dup 3)
3232 (const_int 0)))]
3233 "")
1fd4e8c1 3234
dfbdccdb 3235(define_insn "*boolcsi3_internal3"
52d3af72 3236 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3237 (compare:CC (match_operator:SI 4 "boolean_operator"
3238 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3239 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3240 (const_int 0)))
52d3af72 3241 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3242 (match_dup 4))]
4b8a63d6 3243 "TARGET_32BIT"
52d3af72 3244 "@
dfbdccdb 3245 %q4. %0,%2,%1
52d3af72
DE		 3246 #"
3247 [(set_attr "type" "compare")
3248 (set_attr "length" "4,8")])
3249
3250(define_split
c921bad8 3251 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3252 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3253 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3254 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3255 (const_int 0)))
75540af0 3256 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3257 (match_dup 4))]
4b8a63d6 3258 "TARGET_32BIT && reload_completed"
dfbdccdb 3259 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3260 (set (match_dup 3)
3261 (compare:CC (match_dup 0)
3262 (const_int 0)))]
3263 "")
3264
dfbdccdb 3265(define_insn "*boolccsi3_internal1"
cd2b37d9 3266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3267 (match_operator:SI 3 "boolean_operator"
3268 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3269 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 3270 ""
dfbdccdb 3271 "%q3 %0,%1,%2")
1fd4e8c1 3272
dfbdccdb 3273(define_insn "*boolccsi3_internal2"
52d3af72 3274 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3275 (compare:CC (match_operator:SI 4 "boolean_operator"
3276 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3277 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3278 (const_int 0)))
52d3af72 3279 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3280 "TARGET_32BIT"
52d3af72 3281 "@
dfbdccdb 3282 %q4. %3,%1,%2
52d3af72
DE		 3283 #"
3284 [(set_attr "type" "compare")
3285 (set_attr "length" "4,8")])
3286
3287(define_split
c921bad8 3288 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3289 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3290 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3291 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3292 (const_int 0)))
52d3af72 3293 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3294 "TARGET_32BIT && reload_completed"
dfbdccdb 3295 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3296 (set (match_dup 0)
3297 (compare:CC (match_dup 3)
3298 (const_int 0)))]
3299 "")
1fd4e8c1 3300
dfbdccdb 3301(define_insn "*boolccsi3_internal3"
52d3af72 3302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3303 (compare:CC (match_operator:SI 4 "boolean_operator"
3304 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3305 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3306 (const_int 0)))
52d3af72 3307 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3308 (match_dup 4))]
4b8a63d6 3309 "TARGET_32BIT"
52d3af72 3310 "@
dfbdccdb 3311 %q4. %0,%1,%2
52d3af72
DE		 3312 #"
3313 [(set_attr "type" "compare")
3314 (set_attr "length" "4,8")])
3315
3316(define_split
c921bad8 3317 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3318 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3319 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3320 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3321 (const_int 0)))
75540af0 3322 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3323 (match_dup 4))]
4b8a63d6 3324 "TARGET_32BIT && reload_completed"
dfbdccdb 3325 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3326 (set (match_dup 3)
3327 (compare:CC (match_dup 0)
3328 (const_int 0)))]
3329 "")
1fd4e8c1
RK		 3330
3331;; maskir insn. We need four forms because things might be in arbitrary
3332;; orders. Don't define forms that only set CR fields because these
3333;; would modify an input register.
3334
7cd5235b 3335(define_insn "*maskir_internal1"
cd2b37d9 3336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3337 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3338 (match_operand:SI 1 "gpc_reg_operand" "0"))
3339 (and:SI (match_dup 2)
cd2b37d9 3340 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 3341 "TARGET_POWER"
01def764 3342 "maskir %0,%3,%2")
1fd4e8c1 3343
7cd5235b 3344(define_insn "*maskir_internal2"
242e8072 3345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3346 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3347 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 3348 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 3349 (match_dup 2))))]
ca7f5001 3350 "TARGET_POWER"
01def764 3351 "maskir %0,%3,%2")
1fd4e8c1 3352
7cd5235b 3353(define_insn "*maskir_internal3"
cd2b37d9 3354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 3355 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 3356 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 3357 (and:SI (not:SI (match_dup 2))
3358 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3359 "TARGET_POWER"
01def764 3360 "maskir %0,%3,%2")
1fd4e8c1 3361
7cd5235b 3362(define_insn "*maskir_internal4"
cd2b37d9
RK		 3363 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3364 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 3365 (match_operand:SI 2 "gpc_reg_operand" "r"))
3366 (and:SI (not:SI (match_dup 2))
3367 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3368 "TARGET_POWER"
01def764 3369 "maskir %0,%3,%2")
1fd4e8c1 3370
7cd5235b 3371(define_insn "*maskir_internal5"
9ebbca7d 3372 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3373 (compare:CC
9ebbca7d
GK		 3374 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3375 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 3376 (and:SI (match_dup 2)
9ebbca7d 3377 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 3378 (const_int 0)))
9ebbca7d 3379 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3380 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3381 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 3382 "TARGET_POWER"
9ebbca7d
GK		 3383 "@
3384 maskir. %0,%3,%2
3385 #"
3386 [(set_attr "type" "compare")
3387 (set_attr "length" "4,8")])
3388
3389(define_split
3390 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3391 (compare:CC
3392 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3393 (match_operand:SI 1 "gpc_reg_operand" ""))
3394 (and:SI (match_dup 2)
3395 (match_operand:SI 3 "gpc_reg_operand" "")))
3396 (const_int 0)))
3397 (set (match_operand:SI 0 "gpc_reg_operand" "")
3398 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3399 (and:SI (match_dup 2) (match_dup 3))))]
3400 "TARGET_POWER && reload_completed"
3401 [(set (match_dup 0)
3402 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3403 (and:SI (match_dup 2) (match_dup 3))))
3404 (set (match_dup 4)
3405 (compare:CC (match_dup 0)
3406 (const_int 0)))]
3407 "")
1fd4e8c1 3408
7cd5235b 3409(define_insn "*maskir_internal6"
9ebbca7d 3410 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3411 (compare:CC
9ebbca7d
GK		 3412 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3413 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3414 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 3415 (match_dup 2)))
1fd4e8c1 3416 (const_int 0)))
9ebbca7d 3417 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3418 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3419 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 3420 "TARGET_POWER"
9ebbca7d
GK		 3421 "@
3422 maskir. %0,%3,%2
3423 #"
3424 [(set_attr "type" "compare")
3425 (set_attr "length" "4,8")])
3426
3427(define_split
3428 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3429 (compare:CC
3430 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3431 (match_operand:SI 1 "gpc_reg_operand" ""))
3432 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3433 (match_dup 2)))
3434 (const_int 0)))
3435 (set (match_operand:SI 0 "gpc_reg_operand" "")
3436 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3437 (and:SI (match_dup 3) (match_dup 2))))]
3438 "TARGET_POWER && reload_completed"
3439 [(set (match_dup 0)
3440 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3441 (and:SI (match_dup 3) (match_dup 2))))
3442 (set (match_dup 4)
3443 (compare:CC (match_dup 0)
3444 (const_int 0)))]
3445 "")
1fd4e8c1 3446
7cd5235b 3447(define_insn "*maskir_internal7"
9ebbca7d 3448 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 3449 (compare:CC
9ebbca7d
GK		 3450 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3451 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 3452 (and:SI (not:SI (match_dup 2))
9ebbca7d 3453 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 3454 (const_int 0)))
9ebbca7d 3455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 3456 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3457 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3458 "TARGET_POWER"
9ebbca7d
GK		 3459 "@
3460 maskir. %0,%3,%2
3461 #"
3462 [(set_attr "type" "compare")
3463 (set_attr "length" "4,8")])
3464
3465(define_split
3466 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3467 (compare:CC
3468 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3469 (match_operand:SI 3 "gpc_reg_operand" ""))
3470 (and:SI (not:SI (match_dup 2))
3471 (match_operand:SI 1 "gpc_reg_operand" "")))
3472 (const_int 0)))
3473 (set (match_operand:SI 0 "gpc_reg_operand" "")
3474 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3475 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3476 "TARGET_POWER && reload_completed"
3477 [(set (match_dup 0)
3478 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3479 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3480 (set (match_dup 4)
3481 (compare:CC (match_dup 0)
3482 (const_int 0)))]
3483 "")
1fd4e8c1 3484
7cd5235b 3485(define_insn "*maskir_internal8"
9ebbca7d 3486 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3487 (compare:CC
9ebbca7d
GK		 3488 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3489 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 3490 (and:SI (not:SI (match_dup 2))
9ebbca7d 3491 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 3492 (const_int 0)))
9ebbca7d 3493 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3494 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3495 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 3496 "TARGET_POWER"
9ebbca7d
GK		 3497 "@
3498 maskir. %0,%3,%2
3499 #"
3500 [(set_attr "type" "compare")
3501 (set_attr "length" "4,8")])
fcce224d 3502
9ebbca7d
GK		 3503(define_split
3504 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3505 (compare:CC
3506 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3507 (match_operand:SI 2 "gpc_reg_operand" ""))
3508 (and:SI (not:SI (match_dup 2))
3509 (match_operand:SI 1 "gpc_reg_operand" "")))
3510 (const_int 0)))
3511 (set (match_operand:SI 0 "gpc_reg_operand" "")
3512 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3513 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3514 "TARGET_POWER && reload_completed"
3515 [(set (match_dup 0)
3516 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3517 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3518 (set (match_dup 4)
3519 (compare:CC (match_dup 0)
3520 (const_int 0)))]
3521 "")
fcce224d 3522\f
1fd4e8c1
RK		 3523;; Rotate and shift insns, in all their variants. These support shifts,
3524;; field inserts and extracts, and various combinations thereof.
034c1be0 3525(define_expand "insv"
0ad91047
DE		 3526 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3527 (match_operand:SI 1 "const_int_operand" "")
3528 (match_operand:SI 2 "const_int_operand" ""))
3529 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 3530 ""
3531 "
3532{
3533 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3534 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
14502dad
JM		 3535 compiler if the address of the structure is taken later. Likewise, do
3536 not handle invalid E500 subregs. */
034c1be0 3537 if (GET_CODE (operands[0]) == SUBREG
14502dad
JM		 3538 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3539 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3540 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
034c1be0 3541 FAIL;
a78e33fc
DE		 3542
3543 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3544 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3545 else
3546 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3547 DONE;
034c1be0
MM		 3548}")
3549
a78e33fc 3550(define_insn "insvsi"
cd2b37d9 3551 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 3552 (match_operand:SI 1 "const_int_operand" "i")
3553 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 3554 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 3555 ""
3556 "*
3557{
3558 int start = INTVAL (operands[2]) & 31;
3559 int size = INTVAL (operands[1]) & 31;
3560
89e9f3a8
MM		 3561 operands[4] = GEN_INT (32 - start - size);
3562 operands[1] = GEN_INT (start + size - 1);
a66078ee 3563 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3564}"
3565 [(set_attr "type" "insert_word")])
1fd4e8c1 3566
a78e33fc 3567(define_insn "*insvsi_internal1"
d56d506a
RK		 3568 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3569 (match_operand:SI 1 "const_int_operand" "i")
3570 (match_operand:SI 2 "const_int_operand" "i"))
6d0a8091 3571 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
d56d506a 3572 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3573 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3574 "*
3575{
3576 int shift = INTVAL (operands[4]) & 31;
3577 int start = INTVAL (operands[2]) & 31;
3578 int size = INTVAL (operands[1]) & 31;
3579
89e9f3a8 3580 operands[4] = GEN_INT (shift - start - size);
6d0a8091 3581 operands[1] = GEN_INT (start + size - 1);
a66078ee 3582 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3583}"
3584 [(set_attr "type" "insert_word")])
d56d506a 3585
a78e33fc 3586(define_insn "*insvsi_internal2"
d56d506a
RK		 3587 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3588 (match_operand:SI 1 "const_int_operand" "i")
3589 (match_operand:SI 2 "const_int_operand" "i"))
3590 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3591 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3592 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3593 "*
3594{
3595 int shift = INTVAL (operands[4]) & 31;
3596 int start = INTVAL (operands[2]) & 31;
3597 int size = INTVAL (operands[1]) & 31;
3598
89e9f3a8
MM		 3599 operands[4] = GEN_INT (32 - shift - start - size);
3600 operands[1] = GEN_INT (start + size - 1);
a66078ee 3601 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3602}"
3603 [(set_attr "type" "insert_word")])
d56d506a 3604
a78e33fc 3605(define_insn "*insvsi_internal3"
d56d506a
RK		 3606 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3607 (match_operand:SI 1 "const_int_operand" "i")
3608 (match_operand:SI 2 "const_int_operand" "i"))
3609 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3610 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 3611 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3612 "*
3613{
3614 int shift = INTVAL (operands[4]) & 31;
3615 int start = INTVAL (operands[2]) & 31;
3616 int size = INTVAL (operands[1]) & 31;
3617
89e9f3a8
MM		 3618 operands[4] = GEN_INT (32 - shift - start - size);
3619 operands[1] = GEN_INT (start + size - 1);
a66078ee 3620 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3621}"
3622 [(set_attr "type" "insert_word")])
d56d506a 3623
a78e33fc 3624(define_insn "*insvsi_internal4"
d56d506a
RK		 3625 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3626 (match_operand:SI 1 "const_int_operand" "i")
3627 (match_operand:SI 2 "const_int_operand" "i"))
3628 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3629 (match_operand:SI 4 "const_int_operand" "i")
3630 (match_operand:SI 5 "const_int_operand" "i")))]
3631 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3632 "*
3633{
3634 int extract_start = INTVAL (operands[5]) & 31;
3635 int extract_size = INTVAL (operands[4]) & 31;
3636 int insert_start = INTVAL (operands[2]) & 31;
3637 int insert_size = INTVAL (operands[1]) & 31;
3638
3639/* Align extract field with insert field */
3a598fbe 3640 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3641 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3642 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 3643}"
3644 [(set_attr "type" "insert_word")])
d56d506a 3645
f241bf89
EC		 3646;; combine patterns for rlwimi
3647(define_insn "*insvsi_internal5"
3648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3649 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3650 (match_operand:SI 1 "mask_operand" "i"))
3651 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3652 (match_operand:SI 2 "const_int_operand" "i"))
3653 (match_operand:SI 5 "mask_operand" "i"))))]
3654 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3655 "*
3656{
3657 int me = extract_ME(operands[5]);
3658 int mb = extract_MB(operands[5]);
3659 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3660 operands[2] = GEN_INT(mb);
3661 operands[1] = GEN_INT(me);
3662 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3663}"
3664 [(set_attr "type" "insert_word")])
3665
3666(define_insn "*insvsi_internal6"
3667 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3668 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3669 (match_operand:SI 2 "const_int_operand" "i"))
3670 (match_operand:SI 5 "mask_operand" "i"))
3671 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3672 (match_operand:SI 1 "mask_operand" "i"))))]
3673 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3674 "*
3675{
3676 int me = extract_ME(operands[5]);
3677 int mb = extract_MB(operands[5]);
3678 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3679 operands[2] = GEN_INT(mb);
3680 operands[1] = GEN_INT(me);
3681 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3682}"
3683 [(set_attr "type" "insert_word")])
3684
a78e33fc 3685(define_insn "insvdi"
685f3906 3686 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3687 (match_operand:SI 1 "const_int_operand" "i")
3688 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3689 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3690 "TARGET_POWERPC64"
3691 "*
3692{
3693 int start = INTVAL (operands[2]) & 63;
3694 int size = INTVAL (operands[1]) & 63;
3695
a78e33fc
DE		 3696 operands[1] = GEN_INT (64 - start - size);
3697 return \"rldimi %0,%3,%H1,%H2\";
44cd321e
PS		 3698}"
3699 [(set_attr "type" "insert_dword")])
685f3906 3700
11ac38b2
DE		 3701(define_insn "*insvdi_internal2"
3702 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3703 (match_operand:SI 1 "const_int_operand" "i")
3704 (match_operand:SI 2 "const_int_operand" "i"))
3705 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3706 (match_operand:SI 4 "const_int_operand" "i")))]
3707 "TARGET_POWERPC64
3708 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3709 "*
3710{
3711 int shift = INTVAL (operands[4]) & 63;
3712 int start = (INTVAL (operands[2]) & 63) - 32;
3713 int size = INTVAL (operands[1]) & 63;
3714
3715 operands[4] = GEN_INT (64 - shift - start - size);
3716 operands[2] = GEN_INT (start);
3717 operands[1] = GEN_INT (start + size - 1);
3718 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3719}")
3720
3721(define_insn "*insvdi_internal3"
3722 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3723 (match_operand:SI 1 "const_int_operand" "i")
3724 (match_operand:SI 2 "const_int_operand" "i"))
3725 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3726 (match_operand:SI 4 "const_int_operand" "i")))]
3727 "TARGET_POWERPC64
3728 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3729 "*
3730{
3731 int shift = INTVAL (operands[4]) & 63;
3732 int start = (INTVAL (operands[2]) & 63) - 32;
3733 int size = INTVAL (operands[1]) & 63;
3734
3735 operands[4] = GEN_INT (64 - shift - start - size);
3736 operands[2] = GEN_INT (start);
3737 operands[1] = GEN_INT (start + size - 1);
3738 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3739}")
3740
034c1be0 3741(define_expand "extzv"
0ad91047
DE		 3742 [(set (match_operand 0 "gpc_reg_operand" "")
3743 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3744 (match_operand:SI 2 "const_int_operand" "")
3745 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3746 ""
3747 "
3748{
3749 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3750 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3751 compiler if the address of the structure is taken later. */
3752 if (GET_CODE (operands[0]) == SUBREG
3753 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3754 FAIL;
a78e33fc
DE		 3755
3756 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3757 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3758 else
3759 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3760 DONE;
034c1be0
MM		 3761}")
3762
a78e33fc 3763(define_insn "extzvsi"
cd2b37d9
RK		 3764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3765 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3766 (match_operand:SI 2 "const_int_operand" "i")
3767 (match_operand:SI 3 "const_int_operand" "i")))]
3768 ""
3769 "*
3770{
3771 int start = INTVAL (operands[3]) & 31;
3772 int size = INTVAL (operands[2]) & 31;
3773
3774 if (start + size >= 32)
3775 operands[3] = const0_rtx;
3776 else
89e9f3a8 3777 operands[3] = GEN_INT (start + size);
ca7f5001 3778 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3779}")
3780
a78e33fc 3781(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3782 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3783 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3784 (match_operand:SI 2 "const_int_operand" "i,i")
3785 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3786 (const_int 0)))
9ebbca7d 3787 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3788 ""
1fd4e8c1
RK		 3789 "*
3790{
3791 int start = INTVAL (operands[3]) & 31;
3792 int size = INTVAL (operands[2]) & 31;
3793
9ebbca7d
GK		 3794 /* Force split for non-cc0 compare. */
3795 if (which_alternative == 1)
3796 return \"#\";
3797
43a88a8c 3798 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3799 word, it is possible to use andiu. or andil. to test it. This is
3800 useful because the condition register set-use delay is smaller for
3801 andi[ul]. than for rlinm. This doesn't work when the starting bit
3802 position is 0 because the LT and GT bits may be set wrong. */
3803
3804 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3805 {
3a598fbe 3806 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3807 - (1 << (16 - (start & 15) - size))));
3808 if (start < 16)
ca7f5001 3809 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3810 else
ca7f5001 3811 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3812 }
7e69e155 3813
1fd4e8c1
RK		 3814 if (start + size >= 32)
3815 operands[3] = const0_rtx;
3816 else
89e9f3a8 3817 operands[3] = GEN_INT (start + size);
ca7f5001 3818 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3819}"
44cd321e 3820 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3821 (set_attr "length" "4,8")])
3822
3823(define_split
c921bad8 3824 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 3825 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3826 (match_operand:SI 2 "const_int_operand" "")
3827 (match_operand:SI 3 "const_int_operand" ""))
3828 (const_int 0)))
3829 (clobber (match_scratch:SI 4 ""))]
ce71f754 3830 "reload_completed"
9ebbca7d
GK		 3831 [(set (match_dup 4)
3832 (zero_extract:SI (match_dup 1) (match_dup 2)
3833 (match_dup 3)))
3834 (set (match_dup 0)
3835 (compare:CC (match_dup 4)
3836 (const_int 0)))]
3837 "")
1fd4e8c1 3838
a78e33fc 3839(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3840 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3841 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3842 (match_operand:SI 2 "const_int_operand" "i,i")
3843 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3844 (const_int 0)))
9ebbca7d 3845 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3846 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3847 ""
1fd4e8c1
RK		 3848 "*
3849{
3850 int start = INTVAL (operands[3]) & 31;
3851 int size = INTVAL (operands[2]) & 31;
3852
9ebbca7d
GK		 3853 /* Force split for non-cc0 compare. */
3854 if (which_alternative == 1)
3855 return \"#\";
3856
bc401279 3857 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3858 a shift. The bit-field must end at the LSB. */
bc401279 3859 if (start >= 16 && start + size == 32)
df031c43 3860 {
bc401279
AM		 3861 operands[3] = GEN_INT ((1 << size) - 1);
3862 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3863 }
7e69e155 3864
1fd4e8c1
RK		 3865 if (start + size >= 32)
3866 operands[3] = const0_rtx;
3867 else
89e9f3a8 3868 operands[3] = GEN_INT (start + size);
ca7f5001 3869 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3870}"
44cd321e 3871 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3872 (set_attr "length" "4,8")])
3873
3874(define_split
c921bad8 3875 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 3876 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3877 (match_operand:SI 2 "const_int_operand" "")
3878 (match_operand:SI 3 "const_int_operand" ""))
3879 (const_int 0)))
3880 (set (match_operand:SI 0 "gpc_reg_operand" "")
3881 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3882 "reload_completed"
9ebbca7d
GK		 3883 [(set (match_dup 0)
3884 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3885 (set (match_dup 4)
3886 (compare:CC (match_dup 0)
3887 (const_int 0)))]
3888 "")
1fd4e8c1 3889
a78e33fc 3890(define_insn "extzvdi"
685f3906
DE		 3891 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3892 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3893 (match_operand:SI 2 "const_int_operand" "i")
3894 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3895 "TARGET_POWERPC64"
3896 "*
3897{
3898 int start = INTVAL (operands[3]) & 63;
3899 int size = INTVAL (operands[2]) & 63;
3900
3901 if (start + size >= 64)
3902 operands[3] = const0_rtx;
3903 else
89e9f3a8
MM		 3904 operands[3] = GEN_INT (start + size);
3905 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3906 return \"rldicl %0,%1,%3,%2\";
3907}")
3908
a78e33fc 3909(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3910 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3911 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3912 (match_operand:SI 2 "const_int_operand" "i")
3913 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3914 (const_int 0)))
29ae5b89 3915 (clobber (match_scratch:DI 4 "=r"))]
c921bad8 3916 "TARGET_64BIT && rs6000_gen_cell_microcode"
685f3906
DE		 3917 "*
3918{
3919 int start = INTVAL (operands[3]) & 63;
3920 int size = INTVAL (operands[2]) & 63;
3921
3922 if (start + size >= 64)
3923 operands[3] = const0_rtx;
3924 else
89e9f3a8
MM		 3925 operands[3] = GEN_INT (start + size);
3926 operands[2] = GEN_INT (64 - size);
685f3906 3927 return \"rldicl. %4,%1,%3,%2\";
9a3c428b
DE		 3928}"
3929 [(set_attr "type" "compare")])
685f3906 3930
a78e33fc 3931(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3932 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3933 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3934 (match_operand:SI 2 "const_int_operand" "i")
3935 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3936 (const_int 0)))
29ae5b89 3937 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3938 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
c921bad8 3939 "TARGET_64BIT && rs6000_gen_cell_microcode"
685f3906
DE		 3940 "*
3941{
3942 int start = INTVAL (operands[3]) & 63;
3943 int size = INTVAL (operands[2]) & 63;
3944
3945 if (start + size >= 64)
3946 operands[3] = const0_rtx;
3947 else
89e9f3a8
MM		 3948 operands[3] = GEN_INT (start + size);
3949 operands[2] = GEN_INT (64 - size);
685f3906 3950 return \"rldicl. %0,%1,%3,%2\";
9a3c428b
DE		 3951}"
3952 [(set_attr "type" "compare")])
685f3906 3953
1fd4e8c1 3954(define_insn "rotlsi3"
44cd321e
PS		 3955 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3956 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3957 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
1fd4e8c1 3958 ""
44cd321e
PS		 3959 "@
3960 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3961 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3962 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3963
a260abc9 3964(define_insn "*rotlsi3_internal2"
44cd321e
PS		 3965 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3966 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3967 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3968 (const_int 0)))
44cd321e 3969 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
ce71f754 3970 ""
9ebbca7d 3971 "@
44cd321e
PS		 3972 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3973 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3974 #
9ebbca7d 3975 #"
44cd321e
PS		 3976 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3977 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3978
3979(define_split
c921bad8 3980 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 3981 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3982 (match_operand:SI 2 "reg_or_cint_operand" ""))
3983 (const_int 0)))
3984 (clobber (match_scratch:SI 3 ""))]
ce71f754 3985 "reload_completed"
9ebbca7d
GK		 3986 [(set (match_dup 3)
3987 (rotate:SI (match_dup 1) (match_dup 2)))
3988 (set (match_dup 0)
3989 (compare:CC (match_dup 3)
3990 (const_int 0)))]
3991 "")
1fd4e8c1 3992
a260abc9 3993(define_insn "*rotlsi3_internal3"
44cd321e
PS		 3994 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3995 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3996 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3997 (const_int 0)))
44cd321e 3998 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3999 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 4000 ""
9ebbca7d 4001 "@
44cd321e
PS		 4002 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4003 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4004 #
9ebbca7d 4005 #"
44cd321e
PS		 4006 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4007 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4008
4009(define_split
c921bad8 4010 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4011 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4012 (match_operand:SI 2 "reg_or_cint_operand" ""))
4013 (const_int 0)))
4014 (set (match_operand:SI 0 "gpc_reg_operand" "")
4015 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 4016 "reload_completed"
9ebbca7d
GK		 4017 [(set (match_dup 0)
4018 (rotate:SI (match_dup 1) (match_dup 2)))
4019 (set (match_dup 3)
4020 (compare:CC (match_dup 0)
4021 (const_int 0)))]
4022 "")
1fd4e8c1 4023
a260abc9 4024(define_insn "*rotlsi3_internal4"
44cd321e
PS		 4025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4026 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4027 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4028 (match_operand:SI 3 "mask_operand" "n,n")))]
1fd4e8c1 4029 ""
44cd321e
PS		 4030 "@
4031 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4032 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4033 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 4034
a260abc9 4035(define_insn "*rotlsi3_internal5"
44cd321e 4036 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 4037 (compare:CC (and:SI
44cd321e
PS		 4038 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4039 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4040 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 4041 (const_int 0)))
44cd321e 4042 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
ce71f754 4043 ""
9ebbca7d 4044 "@
44cd321e
PS		 4045 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4046 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4047 #
9ebbca7d 4048 #"
44cd321e
PS		 4049 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4050 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4051
4052(define_split
c921bad8 4053 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4054 (compare:CC (and:SI
4055 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4056 (match_operand:SI 2 "reg_or_cint_operand" ""))
4057 (match_operand:SI 3 "mask_operand" ""))
4058 (const_int 0)))
4059 (clobber (match_scratch:SI 4 ""))]
ce71f754 4060 "reload_completed"
9ebbca7d
GK		 4061 [(set (match_dup 4)
4062 (and:SI (rotate:SI (match_dup 1)
4063 (match_dup 2))
4064 (match_dup 3)))
4065 (set (match_dup 0)
4066 (compare:CC (match_dup 4)
4067 (const_int 0)))]
4068 "")
1fd4e8c1 4069
a260abc9 4070(define_insn "*rotlsi3_internal6"
44cd321e 4071 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 4072 (compare:CC (and:SI
44cd321e
PS		 4073 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4074 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4075 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 4076 (const_int 0)))
44cd321e 4077 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4078 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4079 ""
9ebbca7d 4080 "@
44cd321e
PS		 4081 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4082 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4083 #
9ebbca7d 4084 #"
44cd321e
PS		 4085 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4086 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4087
4088(define_split
c921bad8 4089 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4090 (compare:CC (and:SI
4091 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4092 (match_operand:SI 2 "reg_or_cint_operand" ""))
4093 (match_operand:SI 3 "mask_operand" ""))
4094 (const_int 0)))
4095 (set (match_operand:SI 0 "gpc_reg_operand" "")
4096 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4097 "reload_completed"
9ebbca7d
GK		 4098 [(set (match_dup 0)
4099 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4100 (set (match_dup 4)
4101 (compare:CC (match_dup 0)
4102 (const_int 0)))]
4103 "")
1fd4e8c1 4104
a260abc9 4105(define_insn "*rotlsi3_internal7"
cd2b37d9 4106 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4107 (zero_extend:SI
4108 (subreg:QI
cd2b37d9 4109 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4110 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4111 ""
c921bad8
AP		 4112 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4113 [(set (attr "cell_micro")
4114 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4115 (const_string "not")
4116 (const_string "always")))])
1fd4e8c1 4117
a260abc9 4118(define_insn "*rotlsi3_internal8"
44cd321e 4119 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4120 (compare:CC (zero_extend:SI
4121 (subreg:QI
44cd321e
PS		 4122 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4123 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4124 (const_int 0)))
44cd321e 4125 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4126 ""
9ebbca7d 4127 "@
44cd321e
PS		 4128 {rlnm.|rlwnm.} %3,%1,%2,0xff
4129 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4130 #
9ebbca7d 4131 #"
44cd321e
PS		 4132 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4133 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4134
4135(define_split
c921bad8 4136 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4137 (compare:CC (zero_extend:SI
4138 (subreg:QI
4139 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4140 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4141 (const_int 0)))
4142 (clobber (match_scratch:SI 3 ""))]
4143 "reload_completed"
4144 [(set (match_dup 3)
4145 (zero_extend:SI (subreg:QI
4146 (rotate:SI (match_dup 1)
4147 (match_dup 2)) 0)))
4148 (set (match_dup 0)
4149 (compare:CC (match_dup 3)
4150 (const_int 0)))]
4151 "")
1fd4e8c1 4152
a260abc9 4153(define_insn "*rotlsi3_internal9"
44cd321e 4154 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4155 (compare:CC (zero_extend:SI
4156 (subreg:QI
44cd321e
PS		 4157 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4158 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4159 (const_int 0)))
44cd321e 4160 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4161 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4162 ""
9ebbca7d 4163 "@
44cd321e
PS		 4164 {rlnm.|rlwnm.} %0,%1,%2,0xff
4165 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4166 #
9ebbca7d 4167 #"
44cd321e
PS		 4168 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4169 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4170
4171(define_split
c921bad8 4172 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4173 (compare:CC (zero_extend:SI
4174 (subreg:QI
4175 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4176 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4177 (const_int 0)))
4178 (set (match_operand:SI 0 "gpc_reg_operand" "")
4179 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4180 "reload_completed"
4181 [(set (match_dup 0)
4182 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4183 (set (match_dup 3)
4184 (compare:CC (match_dup 0)
4185 (const_int 0)))]
4186 "")
1fd4e8c1 4187
a260abc9 4188(define_insn "*rotlsi3_internal10"
44cd321e 4189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4190 (zero_extend:SI
4191 (subreg:HI
44cd321e
PS		 4192 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4193 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
1fd4e8c1 4194 ""
44cd321e
PS		 4195 "@
4196 {rlnm|rlwnm} %0,%1,%2,0xffff
4197 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4198 [(set_attr "type" "var_shift_rotate,integer")])
4199
1fd4e8c1 4200
a260abc9 4201(define_insn "*rotlsi3_internal11"
44cd321e 4202 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4203 (compare:CC (zero_extend:SI
4204 (subreg:HI
44cd321e
PS		 4205 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4206 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4207 (const_int 0)))
44cd321e 4208 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4209 ""
9ebbca7d 4210 "@
44cd321e
PS		 4211 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4212 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4213 #
9ebbca7d 4214 #"
44cd321e
PS		 4215 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4216 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4217
4218(define_split
c921bad8 4219 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4220 (compare:CC (zero_extend:SI
4221 (subreg:HI
4222 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4223 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4224 (const_int 0)))
4225 (clobber (match_scratch:SI 3 ""))]
4226 "reload_completed"
4227 [(set (match_dup 3)
4228 (zero_extend:SI (subreg:HI
4229 (rotate:SI (match_dup 1)
4230 (match_dup 2)) 0)))
4231 (set (match_dup 0)
4232 (compare:CC (match_dup 3)
4233 (const_int 0)))]
4234 "")
1fd4e8c1 4235
a260abc9 4236(define_insn "*rotlsi3_internal12"
44cd321e 4237 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4238 (compare:CC (zero_extend:SI
4239 (subreg:HI
44cd321e
PS		 4240 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4241 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4242 (const_int 0)))
44cd321e 4243 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4244 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4245 ""
9ebbca7d 4246 "@
44cd321e
PS		 4247 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4248 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4249 #
9ebbca7d 4250 #"
44cd321e
PS		 4251 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4252 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4253
4254(define_split
c921bad8 4255 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4256 (compare:CC (zero_extend:SI
4257 (subreg:HI
4258 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4259 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4260 (const_int 0)))
4261 (set (match_operand:SI 0 "gpc_reg_operand" "")
4262 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4263 "reload_completed"
4264 [(set (match_dup 0)
4265 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4266 (set (match_dup 3)
4267 (compare:CC (match_dup 0)
4268 (const_int 0)))]
4269 "")
1fd4e8c1
RK		 4270
4271;; Note that we use "sle." instead of "sl." so that we can set
4272;; SHIFT_COUNT_TRUNCATED.
4273
ca7f5001
RK		 4274(define_expand "ashlsi3"
4275 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4276 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4277 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4278 ""
4279 "
4280{
4281 if (TARGET_POWER)
4282 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4283 else
25c341fa 4284 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4285 DONE;
4286}")
4287
4288(define_insn "ashlsi3_power"
cd2b37d9
RK		 4289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4290 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4291 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4292 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4293 "TARGET_POWER"
1fd4e8c1
RK		 4294 "@
4295 sle %0,%1,%2
9ebbca7d 4296 {sli|slwi} %0,%1,%h2")
ca7f5001 4297
25c341fa 4298(define_insn "ashlsi3_no_power"
44cd321e
PS		 4299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4300 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4301 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4302 "! TARGET_POWER"
44cd321e
PS		 4303 "@
4304 {sl|slw} %0,%1,%2
4305 {sli|slwi} %0,%1,%h2"
4306 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4307
4308(define_insn ""
9ebbca7d
GK		 4309 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4310 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4311 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4312 (const_int 0)))
9ebbca7d
GK		 4313 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4314 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4315 "TARGET_POWER"
1fd4e8c1
RK		 4316 "@
4317 sle. %3,%1,%2
9ebbca7d
GK		 4318 {sli.|slwi.} %3,%1,%h2
4319 #
4320 #"
4321 [(set_attr "type" "delayed_compare")
4322 (set_attr "length" "4,4,8,8")])
4323
4324(define_split
4325 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4326 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4327 (match_operand:SI 2 "reg_or_cint_operand" ""))
4328 (const_int 0)))
4329 (clobber (match_scratch:SI 3 ""))
4330 (clobber (match_scratch:SI 4 ""))]
4331 "TARGET_POWER && reload_completed"
4332 [(parallel [(set (match_dup 3)
4333 (ashift:SI (match_dup 1) (match_dup 2)))
4334 (clobber (match_dup 4))])
4335 (set (match_dup 0)
4336 (compare:CC (match_dup 3)
4337 (const_int 0)))]
4338 "")
25c341fa 4339
ca7f5001 4340(define_insn ""
44cd321e
PS		 4341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4342 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4343 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4344 (const_int 0)))
44cd321e 4345 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4b8a63d6 4346 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4347 "@
44cd321e
PS		 4348 {sl.|slw.} %3,%1,%2
4349 {sli.|slwi.} %3,%1,%h2
4350 #
9ebbca7d 4351 #"
44cd321e
PS		 4352 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4353 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4354
4355(define_split
4356 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4357 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4358 (match_operand:SI 2 "reg_or_cint_operand" ""))
4359 (const_int 0)))
4360 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4361 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4362 [(set (match_dup 3)
4363 (ashift:SI (match_dup 1) (match_dup 2)))
4364 (set (match_dup 0)
4365 (compare:CC (match_dup 3)
4366 (const_int 0)))]
4367 "")
1fd4e8c1
RK		 4368
4369(define_insn ""
9ebbca7d
GK		 4370 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4371 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4372 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4373 (const_int 0)))
9ebbca7d 4374 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4375 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4376 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4377 "TARGET_POWER"
1fd4e8c1
RK		 4378 "@
4379 sle. %0,%1,%2
9ebbca7d
GK		 4380 {sli.|slwi.} %0,%1,%h2
4381 #
4382 #"
4383 [(set_attr "type" "delayed_compare")
4384 (set_attr "length" "4,4,8,8")])
4385
4386(define_split
4387 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4388 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4389 (match_operand:SI 2 "reg_or_cint_operand" ""))
4390 (const_int 0)))
4391 (set (match_operand:SI 0 "gpc_reg_operand" "")
4392 (ashift:SI (match_dup 1) (match_dup 2)))
4393 (clobber (match_scratch:SI 4 ""))]
4394 "TARGET_POWER && reload_completed"
4395 [(parallel [(set (match_dup 0)
4396 (ashift:SI (match_dup 1) (match_dup 2)))
4397 (clobber (match_dup 4))])
4398 (set (match_dup 3)
4399 (compare:CC (match_dup 0)
4400 (const_int 0)))]
4401 "")
25c341fa 4402
ca7f5001 4403(define_insn ""
44cd321e
PS		 4404 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4405 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4406 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4407 (const_int 0)))
44cd321e 4408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 4409 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4410 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4411 "@
44cd321e
PS		 4412 {sl.|slw.} %0,%1,%2
4413 {sli.|slwi.} %0,%1,%h2
4414 #
9ebbca7d 4415 #"
44cd321e
PS		 4416 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4417 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4418
4419(define_split
4420 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4421 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4422 (match_operand:SI 2 "reg_or_cint_operand" ""))
4423 (const_int 0)))
4424 (set (match_operand:SI 0 "gpc_reg_operand" "")
4425 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4426 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4427 [(set (match_dup 0)
4428 (ashift:SI (match_dup 1) (match_dup 2)))
4429 (set (match_dup 3)
4430 (compare:CC (match_dup 0)
4431 (const_int 0)))]
4432 "")
1fd4e8c1 4433
915167f5 4434(define_insn "rlwinm"
cd2b37d9
RK		 4435 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4436 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4437 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4438 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4439 "includes_lshift_p (operands[2], operands[3])"
d56d506a 4440 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 4441
4442(define_insn ""
9ebbca7d 4443 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4444 (compare:CC
9ebbca7d
GK		 4445 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4446 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4447 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4448 (const_int 0)))
9ebbca7d 4449 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4450 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4451 "@
4452 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4453 #"
4454 [(set_attr "type" "delayed_compare")
4455 (set_attr "length" "4,8")])
4456
4457(define_split
c921bad8 4458 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4459 (compare:CC
4460 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4461 (match_operand:SI 2 "const_int_operand" ""))
4462 (match_operand:SI 3 "mask_operand" ""))
4463 (const_int 0)))
4464 (clobber (match_scratch:SI 4 ""))]
ce71f754 4465 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4466 [(set (match_dup 4)
4467 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4468 (match_dup 3)))
4469 (set (match_dup 0)
4470 (compare:CC (match_dup 4)
4471 (const_int 0)))]
4472 "")
1fd4e8c1
RK		 4473
4474(define_insn ""
9ebbca7d 4475 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4476 (compare:CC
9ebbca7d
GK		 4477 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4478 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4479 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4480 (const_int 0)))
9ebbca7d 4481 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4482 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4483 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4484 "@
4485 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4486 #"
4487 [(set_attr "type" "delayed_compare")
4488 (set_attr "length" "4,8")])
4489
4490(define_split
c921bad8 4491 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4492 (compare:CC
4493 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4494 (match_operand:SI 2 "const_int_operand" ""))
4495 (match_operand:SI 3 "mask_operand" ""))
4496 (const_int 0)))
4497 (set (match_operand:SI 0 "gpc_reg_operand" "")
4498 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4499 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4500 [(set (match_dup 0)
4501 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4502 (set (match_dup 4)
4503 (compare:CC (match_dup 0)
4504 (const_int 0)))]
4505 "")
1fd4e8c1 4506
ca7f5001 4507;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 4508;; "sli x,x,0".
ca7f5001
RK		 4509(define_expand "lshrsi3"
4510 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4511 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4512 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4513 ""
4514 "
4515{
4516 if (TARGET_POWER)
4517 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4518 else
25c341fa 4519 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4520 DONE;
4521}")
4522
4523(define_insn "lshrsi3_power"
bdf423cb
MM		 4524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4525 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4526 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4527 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 4528 "TARGET_POWER"
1fd4e8c1
RK		 4529 "@
4530 sre %0,%1,%2
bdf423cb 4531 mr %0,%1
ca7f5001
RK		 4532 {s%A2i|s%A2wi} %0,%1,%h2")
4533
25c341fa 4534(define_insn "lshrsi3_no_power"
44cd321e
PS		 4535 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4536 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4537 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
25c341fa 4538 "! TARGET_POWER"
bdf423cb
MM		 4539 "@
4540 mr %0,%1
44cd321e
PS		 4541 {sr|srw} %0,%1,%2
4542 {sri|srwi} %0,%1,%h2"
4543 [(set_attr "type" "integer,var_shift_rotate,shift")])
1fd4e8c1
RK		 4544
4545(define_insn ""
9ebbca7d
GK		 4546 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4547 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4548 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4549 (const_int 0)))
9ebbca7d
GK		 4550 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4551 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4552 "TARGET_POWER"
1fd4e8c1 4553 "@
29ae5b89
JL		 4554 sre. %3,%1,%2
4555 mr. %1,%1
9ebbca7d
GK		 4556 {s%A2i.|s%A2wi.} %3,%1,%h2
4557 #
4558 #
4559 #"
4560 [(set_attr "type" "delayed_compare")
4561 (set_attr "length" "4,4,4,8,8,8")])
4562
4563(define_split
4564 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4565 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4566 (match_operand:SI 2 "reg_or_cint_operand" ""))
4567 (const_int 0)))
4568 (clobber (match_scratch:SI 3 ""))
4569 (clobber (match_scratch:SI 4 ""))]
4570 "TARGET_POWER && reload_completed"
4571 [(parallel [(set (match_dup 3)
4572 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4573 (clobber (match_dup 4))])
4574 (set (match_dup 0)
4575 (compare:CC (match_dup 3)
4576 (const_int 0)))]
4577 "")
ca7f5001
RK		 4578
4579(define_insn ""
44cd321e
PS		 4580 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4581 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4582 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
ca7f5001 4583 (const_int 0)))
44cd321e 4584 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4b8a63d6 4585 "! TARGET_POWER && TARGET_32BIT"
bdf423cb
MM		 4586 "@
4587 mr. %1,%1
44cd321e
PS		 4588 {sr.|srw.} %3,%1,%2
4589 {sri.|srwi.} %3,%1,%h2
4590 #
9ebbca7d
GK		 4591 #
4592 #"
44cd321e
PS		 4593 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4594 (set_attr "length" "4,4,4,8,8,8")])
1fd4e8c1 4595
9ebbca7d
GK		 4596(define_split
4597 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4598 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4599 (match_operand:SI 2 "reg_or_cint_operand" ""))
4600 (const_int 0)))
4601 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4602 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4603 [(set (match_dup 3)
4604 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4605 (set (match_dup 0)
4606 (compare:CC (match_dup 3)
4607 (const_int 0)))]
4608 "")
4609
4610(define_insn ""
4611 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4612 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4613 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4614 (const_int 0)))
9ebbca7d 4615 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 4616 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4617 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4618 "TARGET_POWER"
1fd4e8c1 4619 "@
29ae5b89
JL		 4620 sre. %0,%1,%2
4621 mr. %0,%1
9ebbca7d
GK		 4622 {s%A2i.|s%A2wi.} %0,%1,%h2
4623 #
4624 #
4625 #"
4626 [(set_attr "type" "delayed_compare")
4627 (set_attr "length" "4,4,4,8,8,8")])
4628
4629(define_split
4630 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4631 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4632 (match_operand:SI 2 "reg_or_cint_operand" ""))
4633 (const_int 0)))
4634 (set (match_operand:SI 0 "gpc_reg_operand" "")
4635 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4636 (clobber (match_scratch:SI 4 ""))]
4637 "TARGET_POWER && reload_completed"
4638 [(parallel [(set (match_dup 0)
4639 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4640 (clobber (match_dup 4))])
4641 (set (match_dup 3)
4642 (compare:CC (match_dup 0)
4643 (const_int 0)))]
4644 "")
ca7f5001
RK		 4645
4646(define_insn ""
44cd321e
PS		 4647 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4648 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4649 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
815cdc52 4650 (const_int 0)))
44cd321e 4651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
29ae5b89 4652 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4653 "! TARGET_POWER && TARGET_32BIT"
29ae5b89
JL		 4654 "@
4655 mr. %0,%1
44cd321e
PS		 4656 {sr.|srw.} %0,%1,%2
4657 {sri.|srwi.} %0,%1,%h2
4658 #
9ebbca7d
GK		 4659 #
4660 #"
44cd321e
PS		 4661 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4662 (set_attr "length" "4,4,4,8,8,8")])
9ebbca7d
GK		 4663
4664(define_split
4665 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4666 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4667 (match_operand:SI 2 "reg_or_cint_operand" ""))
4668 (const_int 0)))
4669 (set (match_operand:SI 0 "gpc_reg_operand" "")
4670 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4671 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4672 [(set (match_dup 0)
4673 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4674 (set (match_dup 3)
4675 (compare:CC (match_dup 0)
4676 (const_int 0)))]
4677 "")
1fd4e8c1
RK		 4678
4679(define_insn ""
cd2b37d9
RK		 4680 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4681 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4682 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4683 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4684 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 4685 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 4686
4687(define_insn ""
9ebbca7d 4688 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4689 (compare:CC
9ebbca7d
GK		 4690 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4691 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4692 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4693 (const_int 0)))
9ebbca7d 4694 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4695 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4696 "@
4697 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4698 #"
4699 [(set_attr "type" "delayed_compare")
4700 (set_attr "length" "4,8")])
4701
4702(define_split
c921bad8 4703 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4704 (compare:CC
4705 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4706 (match_operand:SI 2 "const_int_operand" ""))
4707 (match_operand:SI 3 "mask_operand" ""))
4708 (const_int 0)))
4709 (clobber (match_scratch:SI 4 ""))]
ce71f754 4710 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4711 [(set (match_dup 4)
4712 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4713 (match_dup 3)))
4714 (set (match_dup 0)
4715 (compare:CC (match_dup 4)
4716 (const_int 0)))]
4717 "")
1fd4e8c1
RK		 4718
4719(define_insn ""
9ebbca7d 4720 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4721 (compare:CC
9ebbca7d
GK		 4722 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4723 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4724 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4725 (const_int 0)))
9ebbca7d 4726 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4727 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4728 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4729 "@
4730 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4731 #"
4732 [(set_attr "type" "delayed_compare")
4733 (set_attr "length" "4,8")])
4734
4735(define_split
c921bad8 4736 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4737 (compare:CC
4738 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4739 (match_operand:SI 2 "const_int_operand" ""))
4740 (match_operand:SI 3 "mask_operand" ""))
4741 (const_int 0)))
4742 (set (match_operand:SI 0 "gpc_reg_operand" "")
4743 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4744 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4745 [(set (match_dup 0)
4746 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4747 (set (match_dup 4)
4748 (compare:CC (match_dup 0)
4749 (const_int 0)))]
4750 "")
1fd4e8c1
RK		 4751
4752(define_insn ""
cd2b37d9 4753 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4754 (zero_extend:SI
4755 (subreg:QI
cd2b37d9 4756 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4757 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4758 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4759 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4760
4761(define_insn ""
9ebbca7d 4762 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4763 (compare:CC
4764 (zero_extend:SI
4765 (subreg:QI
9ebbca7d
GK		 4766 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4767 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4768 (const_int 0)))
9ebbca7d 4769 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4770 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4771 "@
4772 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4773 #"
4774 [(set_attr "type" "delayed_compare")
4775 (set_attr "length" "4,8")])
4776
4777(define_split
c921bad8 4778 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4779 (compare:CC
4780 (zero_extend:SI
4781 (subreg:QI
4782 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4783 (match_operand:SI 2 "const_int_operand" "")) 0))
4784 (const_int 0)))
4785 (clobber (match_scratch:SI 3 ""))]
4786 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4787 [(set (match_dup 3)
4788 (zero_extend:SI (subreg:QI
4789 (lshiftrt:SI (match_dup 1)
4790 (match_dup 2)) 0)))
4791 (set (match_dup 0)
4792 (compare:CC (match_dup 3)
4793 (const_int 0)))]
4794 "")
1fd4e8c1
RK		 4795
4796(define_insn ""
9ebbca7d 4797 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4798 (compare:CC
4799 (zero_extend:SI
4800 (subreg:QI
9ebbca7d
GK		 4801 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4802 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4803 (const_int 0)))
9ebbca7d 4804 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4805 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4806 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4807 "@
4808 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4809 #"
4810 [(set_attr "type" "delayed_compare")
4811 (set_attr "length" "4,8")])
4812
4813(define_split
c921bad8 4814 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4815 (compare:CC
4816 (zero_extend:SI
4817 (subreg:QI
4818 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4819 (match_operand:SI 2 "const_int_operand" "")) 0))
4820 (const_int 0)))
4821 (set (match_operand:SI 0 "gpc_reg_operand" "")
4822 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4823 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4824 [(set (match_dup 0)
4825 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4826 (set (match_dup 3)
4827 (compare:CC (match_dup 0)
4828 (const_int 0)))]
4829 "")
1fd4e8c1
RK		 4830
4831(define_insn ""
cd2b37d9 4832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4833 (zero_extend:SI
4834 (subreg:HI
cd2b37d9 4835 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4836 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4837 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4838 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4839
4840(define_insn ""
9ebbca7d 4841 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4842 (compare:CC
4843 (zero_extend:SI
4844 (subreg:HI
9ebbca7d
GK		 4845 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4846 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4847 (const_int 0)))
9ebbca7d 4848 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4849 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4850 "@
4851 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4852 #"
4853 [(set_attr "type" "delayed_compare")
4854 (set_attr "length" "4,8")])
4855
4856(define_split
c921bad8 4857 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4858 (compare:CC
4859 (zero_extend:SI
4860 (subreg:HI
4861 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4862 (match_operand:SI 2 "const_int_operand" "")) 0))
4863 (const_int 0)))
4864 (clobber (match_scratch:SI 3 ""))]
4865 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4866 [(set (match_dup 3)
4867 (zero_extend:SI (subreg:HI
4868 (lshiftrt:SI (match_dup 1)
4869 (match_dup 2)) 0)))
4870 (set (match_dup 0)
4871 (compare:CC (match_dup 3)
4872 (const_int 0)))]
4873 "")
1fd4e8c1
RK		 4874
4875(define_insn ""
9ebbca7d 4876 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4877 (compare:CC
4878 (zero_extend:SI
4879 (subreg:HI
9ebbca7d
GK		 4880 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4881 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4882 (const_int 0)))
9ebbca7d 4883 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4884 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4885 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4886 "@
4887 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4888 #"
4889 [(set_attr "type" "delayed_compare")
4890 (set_attr "length" "4,8")])
4891
4892(define_split
c921bad8 4893 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4894 (compare:CC
4895 (zero_extend:SI
4896 (subreg:HI
4897 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4898 (match_operand:SI 2 "const_int_operand" "")) 0))
4899 (const_int 0)))
4900 (set (match_operand:SI 0 "gpc_reg_operand" "")
4901 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4902 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4903 [(set (match_dup 0)
4904 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4905 (set (match_dup 3)
4906 (compare:CC (match_dup 0)
4907 (const_int 0)))]
4908 "")
1fd4e8c1
RK		 4909
4910(define_insn ""
cd2b37d9 4911 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4912 (const_int 1)
cd2b37d9
RK		 4913 (match_operand:SI 1 "gpc_reg_operand" "r"))
4914 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4915 (const_int 31)))]
ca7f5001 4916 "TARGET_POWER"
1fd4e8c1
RK		 4917 "rrib %0,%1,%2")
4918
4919(define_insn ""
cd2b37d9 4920 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4921 (const_int 1)
cd2b37d9
RK		 4922 (match_operand:SI 1 "gpc_reg_operand" "r"))
4923 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4924 (const_int 31)))]
ca7f5001 4925 "TARGET_POWER"
1fd4e8c1
RK		 4926 "rrib %0,%1,%2")
4927
4928(define_insn ""
cd2b37d9 4929 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4930 (const_int 1)
cd2b37d9
RK		 4931 (match_operand:SI 1 "gpc_reg_operand" "r"))
4932 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4933 (const_int 1)
4934 (const_int 0)))]
ca7f5001 4935 "TARGET_POWER"
1fd4e8c1
RK		 4936 "rrib %0,%1,%2")
4937
ca7f5001
RK		 4938(define_expand "ashrsi3"
4939 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4940 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4941 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4942 ""
4943 "
4944{
4945 if (TARGET_POWER)
4946 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4947 else
25c341fa 4948 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4949 DONE;
4950}")
4951
4952(define_insn "ashrsi3_power"
cd2b37d9
RK		 4953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4954 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4955 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4956 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4957 "TARGET_POWER"
1fd4e8c1
RK		 4958 "@
4959 srea %0,%1,%2
44cd321e
PS		 4960 {srai|srawi} %0,%1,%h2"
4961 [(set_attr "type" "shift")])
ca7f5001 4962
25c341fa 4963(define_insn "ashrsi3_no_power"
44cd321e
PS		 4964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4965 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4966 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4967 "! TARGET_POWER"
44cd321e
PS		 4968 "@
4969 {sra|sraw} %0,%1,%2
4970 {srai|srawi} %0,%1,%h2"
4971 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4972
4973(define_insn ""
9ebbca7d
GK		 4974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4975 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4976 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4977 (const_int 0)))
9ebbca7d
GK		 4978 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4979 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4980 "TARGET_POWER"
1fd4e8c1
RK		 4981 "@
4982 srea. %3,%1,%2
9ebbca7d
GK		 4983 {srai.|srawi.} %3,%1,%h2
4984 #
4985 #"
4986 [(set_attr "type" "delayed_compare")
4987 (set_attr "length" "4,4,8,8")])
4988
4989(define_split
4990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4991 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4992 (match_operand:SI 2 "reg_or_cint_operand" ""))
4993 (const_int 0)))
4994 (clobber (match_scratch:SI 3 ""))
4995 (clobber (match_scratch:SI 4 ""))]
4996 "TARGET_POWER && reload_completed"
4997 [(parallel [(set (match_dup 3)
4998 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4999 (clobber (match_dup 4))])
5000 (set (match_dup 0)
5001 (compare:CC (match_dup 3)
5002 (const_int 0)))]
5003 "")
ca7f5001
RK		 5004
5005(define_insn ""
44cd321e
PS		 5006 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5007 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5008 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 5009 (const_int 0)))
44cd321e 5010 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
25c341fa 5011 "! TARGET_POWER"
9ebbca7d 5012 "@
44cd321e
PS		 5013 {sra.|sraw.} %3,%1,%2
5014 {srai.|srawi.} %3,%1,%h2
5015 #
9ebbca7d 5016 #"
44cd321e
PS		 5017 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5018 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 5019
5020(define_split
c921bad8 5021 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 5022 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5023 (match_operand:SI 2 "reg_or_cint_operand" ""))
5024 (const_int 0)))
5025 (clobber (match_scratch:SI 3 ""))]
5026 "! TARGET_POWER && reload_completed"
5027 [(set (match_dup 3)
5028 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5029 (set (match_dup 0)
5030 (compare:CC (match_dup 3)
5031 (const_int 0)))]
5032 "")
1fd4e8c1
RK		 5033
5034(define_insn ""
9ebbca7d
GK		 5035 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5036 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5037 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 5038 (const_int 0)))
9ebbca7d 5039 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 5040 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 5041 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 5042 "TARGET_POWER"
1fd4e8c1
RK		 5043 "@
5044 srea. %0,%1,%2
9ebbca7d
GK		 5045 {srai.|srawi.} %0,%1,%h2
5046 #
5047 #"
5048 [(set_attr "type" "delayed_compare")
5049 (set_attr "length" "4,4,8,8")])
5050
5051(define_split
5052 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5053 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5054 (match_operand:SI 2 "reg_or_cint_operand" ""))
5055 (const_int 0)))
5056 (set (match_operand:SI 0 "gpc_reg_operand" "")
5057 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5058 (clobber (match_scratch:SI 4 ""))]
5059 "TARGET_POWER && reload_completed"
5060 [(parallel [(set (match_dup 0)
5061 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5062 (clobber (match_dup 4))])
5063 (set (match_dup 3)
5064 (compare:CC (match_dup 0)
5065 (const_int 0)))]
5066 "")
1fd4e8c1 5067
ca7f5001 5068(define_insn ""
44cd321e
PS		 5069 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5070 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5071 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 5072 (const_int 0)))
44cd321e 5073 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 5074 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 5075 "! TARGET_POWER"
9ebbca7d 5076 "@
44cd321e
PS		 5077 {sra.|sraw.} %0,%1,%2
5078 {srai.|srawi.} %0,%1,%h2
5079 #
9ebbca7d 5080 #"
44cd321e
PS		 5081 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5082 (set_attr "length" "4,4,8,8")])
1fd4e8c1 5083\f
9ebbca7d 5084(define_split
c921bad8 5085 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 5086 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5087 (match_operand:SI 2 "reg_or_cint_operand" ""))
5088 (const_int 0)))
5089 (set (match_operand:SI 0 "gpc_reg_operand" "")
5090 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5091 "! TARGET_POWER && reload_completed"
5092 [(set (match_dup 0)
5093 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5094 (set (match_dup 3)
5095 (compare:CC (match_dup 0)
5096 (const_int 0)))]
5097 "")
5098
1fd4e8c1
RK		 5099;; Floating-point insns, excluding normal data motion.
5100;;
ca7f5001
RK		 5101;; PowerPC has a full set of single-precision floating point instructions.
5102;;
5103;; For the POWER architecture, we pretend that we have both SFmode and
5104;; DFmode insns, while, in fact, all fp insns are actually done in double.
5105;; The only conversions we will do will be when storing to memory. In that
5106;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 5107;;
5108;; Note that when we store into a single-precision memory location, we need to
5109;; use the frsp insn first. If the register being stored isn't dead, we
5110;; need a scratch register for the frsp. But this is difficult when the store
5111;; is done by reload. It is not incorrect to do the frsp on the register in
5112;; this case, we just lose precision that we would have otherwise gotten but
5113;; is not guaranteed. Perhaps this should be tightened up at some point.
5114
99176a91
AH		 5115(define_expand "extendsfdf2"
5116 [(set (match_operand:DF 0 "gpc_reg_operand" "")
97c54d9a 5117 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
696e45ba 5118 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
99176a91
AH		 5119 "")
5120
5121(define_insn_and_split "*extendsfdf2_fpr"
97c54d9a
DE		 5122 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5123 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
696e45ba 5124 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
11ac38b2
DE		 5125 "@
5126 #
97c54d9a
DE		 5127 fmr %0,%1
5128 lfs%U1%X1 %0,%1"
d7b1468b 5129 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
11ac38b2 5130 [(const_int 0)]
5c30aff8 5131{
11ac38b2
DE		 5132 emit_note (NOTE_INSN_DELETED);
5133 DONE;
5134}
97c54d9a 5135 [(set_attr "type" "fp,fp,fpload")])
1fd4e8c1 5136
7a2f7870
AH		 5137(define_expand "truncdfsf2"
5138 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5139 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
696e45ba 5140 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5141 "")
5142
99176a91 5143(define_insn "*truncdfsf2_fpr"
cd2b37d9
RK		 5144 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5145 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
696e45ba 5146 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
dcac138d 5147 "frsp %0,%1"
1fd4e8c1
RK		 5148 [(set_attr "type" "fp")])
5149
455350f4
RK		 5150(define_insn "aux_truncdfsf2"
5151 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 5152 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
e47911ce 5153 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 5154 "frsp %0,%1"
5155 [(set_attr "type" "fp")])
5156
a3170dc6
AH		 5157(define_expand "negsf2"
5158 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5159 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
696e45ba 5160 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
a3170dc6
AH		 5161 "")
5162
5163(define_insn "*negsf2"
cd2b37d9
RK		 5164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5165 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
696e45ba 5166 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
1fd4e8c1
RK		 5167 "fneg %0,%1"
5168 [(set_attr "type" "fp")])
5169
a3170dc6
AH		 5170(define_expand "abssf2"
5171 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5172 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
696e45ba 5173 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
a3170dc6
AH		 5174 "")
5175
5176(define_insn "*abssf2"
cd2b37d9
RK		 5177 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5178 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
696e45ba 5179 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
1fd4e8c1
RK		 5180 "fabs %0,%1"
5181 [(set_attr "type" "fp")])
5182
5183(define_insn ""
cd2b37d9
RK		 5184 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5185 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
696e45ba 5186 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
1fd4e8c1
RK		 5187 "fnabs %0,%1"
5188 [(set_attr "type" "fp")])
5189
ca7f5001
RK		 5190(define_expand "addsf3"
5191 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5192 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5193 (match_operand:SF 2 "gpc_reg_operand" "")))]
696e45ba 5194 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
ca7f5001
RK		 5195 "")
5196
5197(define_insn ""
cd2b37d9
RK		 5198 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5199 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5200 (match_operand:SF 2 "gpc_reg_operand" "f")))]
e47911ce 5201 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
b26c8351 5202 "fadds %0,%1,%2"
0bb7b92e
ME		 5203 [(set_attr "type" "fp")
5204 (set_attr "fp_type" "fp_addsub_s")])
ca7f5001
RK		 5205
5206(define_insn ""
5207 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5208 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5209 (match_operand:SF 2 "gpc_reg_operand" "f")))]
e47911ce 5210 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5211 "{fa|fadd} %0,%1,%2"
e47911ce 5212 [(set_attr "type" "fp")])
ca7f5001
RK		 5213
5214(define_expand "subsf3"
5215 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5216 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5217 (match_operand:SF 2 "gpc_reg_operand" "")))]
696e45ba 5218 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
ca7f5001
RK		 5219 "")
5220
5221(define_insn ""
5222 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5223 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5224 (match_operand:SF 2 "gpc_reg_operand" "f")))]
696e45ba 5225 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
b26c8351 5226 "fsubs %0,%1,%2"
0bb7b92e
ME		 5227 [(set_attr "type" "fp")
5228 (set_attr "fp_type" "fp_addsub_s")])
1fd4e8c1 5229
ca7f5001 5230(define_insn ""
cd2b37d9
RK		 5231 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5232 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5233 (match_operand:SF 2 "gpc_reg_operand" "f")))]
e47911ce 5234 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5235 "{fs|fsub} %0,%1,%2"
e47911ce 5236 [(set_attr "type" "fp")])
ca7f5001
RK		 5237
5238(define_expand "mulsf3"
5239 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5240 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5241 (match_operand:SF 2 "gpc_reg_operand" "")))]
696e45ba 5242 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
ca7f5001
RK		 5243 "")
5244
5245(define_insn ""
5246 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5247 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5248 (match_operand:SF 2 "gpc_reg_operand" "f")))]
696e45ba 5249 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
b26c8351 5250 "fmuls %0,%1,%2"
0bb7b92e
ME		 5251 [(set_attr "type" "fp")
5252 (set_attr "fp_type" "fp_mul_s")])
1fd4e8c1 5253
ca7f5001 5254(define_insn ""
cd2b37d9
RK		 5255 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5256 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5257 (match_operand:SF 2 "gpc_reg_operand" "f")))]
e47911ce 5258 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5259 "{fm|fmul} %0,%1,%2"
e47911ce 5260 [(set_attr "type" "dmul")])
1fd4e8c1 5261
ca7f5001
RK		 5262(define_expand "divsf3"
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5264 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5265 (match_operand:SF 2 "gpc_reg_operand" "")))]
696e45ba 5266 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
9c78b944 5267 "")
ca7f5001
RK		 5268
5269(define_insn ""
cd2b37d9
RK		 5270 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5271 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5272 (match_operand:SF 2 "gpc_reg_operand" "f")))]
696e45ba
ME		 5273 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5274 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
b26c8351 5275 "fdivs %0,%1,%2"
ca7f5001
RK		 5276 [(set_attr "type" "sdiv")])
5277
5278(define_insn ""
5279 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5280 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5281 (match_operand:SF 2 "gpc_reg_operand" "f")))]
696e45ba
ME		 5282 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5283 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
b26c8351 5284 "{fd|fdiv} %0,%1,%2"
0780f386 5285 [(set_attr "type" "ddiv")])
1fd4e8c1 5286
9c78b944
DE		 5287(define_expand "recipsf3"
5288 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5289 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5290 (match_operand:SF 2 "gpc_reg_operand" "f")]
5291 UNSPEC_FRES))]
5292 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5293 && flag_finite_math_only && !flag_trapping_math"
5294{
5295 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5296 DONE;
5297})
5298
5299(define_insn "fres"
5300 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5301 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5302 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5303 "fres %0,%1"
5304 [(set_attr "type" "fp")])
5305
1fd4e8c1 5306(define_insn ""
cd2b37d9
RK		 5307 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5308 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5309 (match_operand:SF 2 "gpc_reg_operand" "f"))
5310 (match_operand:SF 3 "gpc_reg_operand" "f")))]
e47911ce 5311 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
696e45ba 5312 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
b26c8351 5313 "fmadds %0,%1,%2,%3"
0bb7b92e
ME		 5314 [(set_attr "type" "fp")
5315 (set_attr "fp_type" "fp_maddsub_s")])
ca7f5001
RK		 5316
5317(define_insn ""
5318 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5319 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5320 (match_operand:SF 2 "gpc_reg_operand" "f"))
5321 (match_operand:SF 3 "gpc_reg_operand" "f")))]
e47911ce 5322 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5323 "{fma|fmadd} %0,%1,%2,%3"
e47911ce 5324 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5325
5326(define_insn ""
cd2b37d9
RK		 5327 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5328 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5329 (match_operand:SF 2 "gpc_reg_operand" "f"))
5330 (match_operand:SF 3 "gpc_reg_operand" "f")))]
e47911ce 5331 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
696e45ba 5332 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
b26c8351 5333 "fmsubs %0,%1,%2,%3"
0bb7b92e
ME		 5334 [(set_attr "type" "fp")
5335 (set_attr "fp_type" "fp_maddsub_s")])
ca7f5001
RK		 5336
5337(define_insn ""
5338 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5339 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5340 (match_operand:SF 2 "gpc_reg_operand" "f"))
5341 (match_operand:SF 3 "gpc_reg_operand" "f")))]
e47911ce 5342 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5343 "{fms|fmsub} %0,%1,%2,%3"
e47911ce 5344 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5345
5346(define_insn ""
cd2b37d9
RK		 5347 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5348 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5349 (match_operand:SF 2 "gpc_reg_operand" "f"))
5350 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694 5351 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
1847ea4d 5352 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
16823694 5353 "fnmadds %0,%1,%2,%3"
0bb7b92e
ME		 5354 [(set_attr "type" "fp")
5355 (set_attr "fp_type" "fp_maddsub_s")])
16823694
GK		 5356
5357(define_insn ""
5358 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5359 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5360 (match_operand:SF 2 "gpc_reg_operand" "f"))
5361 (match_operand:SF 3 "gpc_reg_operand" "f")))]
696e45ba 5362 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5363 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5364 "fnmadds %0,%1,%2,%3"
0bb7b92e
ME		 5365 [(set_attr "type" "fp")
5366 (set_attr "fp_type" "fp_maddsub_s")])
ca7f5001
RK		 5367
5368(define_insn ""
5369 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5370 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5371 (match_operand:SF 2 "gpc_reg_operand" "f"))
5372 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
e47911ce 5373 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5374 "{fnma|fnmadd} %0,%1,%2,%3"
e47911ce 5375 [(set_attr "type" "dmul")])
1fd4e8c1 5376
16823694
GK		 5377(define_insn ""
5378 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5379 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5380 (match_operand:SF 2 "gpc_reg_operand" "f"))
5381 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5382 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
e47911ce 5383 && ! HONOR_SIGNED_ZEROS (SFmode)"
16823694 5384 "{fnma|fnmadd} %0,%1,%2,%3"
e47911ce 5385 [(set_attr "type" "dmul")])
16823694 5386
1fd4e8c1 5387(define_insn ""
cd2b37d9
RK		 5388 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5389 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5390 (match_operand:SF 2 "gpc_reg_operand" "f"))
5391 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694 5392 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
696e45ba 5393 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
16823694 5394 "fnmsubs %0,%1,%2,%3"
0bb7b92e
ME		 5395 [(set_attr "type" "fp")
5396 (set_attr "fp_type" "fp_maddsub_s")])
16823694
GK		 5397
5398(define_insn ""
5399 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5400 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5401 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5402 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5403 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
696e45ba 5404 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5405 "fnmsubs %0,%1,%2,%3"
0bb7b92e
ME		 5406 [(set_attr "type" "fp")
5407 (set_attr "fp_type" "fp_maddsub_s")])
ca7f5001
RK		 5408
5409(define_insn ""
5410 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5411 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5412 (match_operand:SF 2 "gpc_reg_operand" "f"))
5413 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
e47911ce 5414 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5415 "{fnms|fnmsub} %0,%1,%2,%3"
e47911ce 5416 [(set_attr "type" "dmul")])
1fd4e8c1 5417
16823694
GK		 5418(define_insn ""
5419 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5420 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5421 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5422 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5423 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
e47911ce 5424 && ! HONOR_SIGNED_ZEROS (SFmode)"
16823694 5425 "{fnms|fnmsub} %0,%1,%2,%3"
9c6fdb46 5426 [(set_attr "type" "dmul")])
16823694 5427
ca7f5001
RK		 5428(define_expand "sqrtsf2"
5429 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5430 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
e47911ce
DE		 5431 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5432 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
696e45ba 5433 && !TARGET_SIMPLE_FPU"
ca7f5001
RK		 5434 "")
5435
5436(define_insn ""
5437 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5438 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
e47911ce 5439 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
696e45ba 5440 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
ca7f5001
RK		 5441 "fsqrts %0,%1"
5442 [(set_attr "type" "ssqrt")])
5443
5444(define_insn ""
5445 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5446 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
696e45ba
ME		 5447 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5448 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
ca7f5001
RK		 5449 "fsqrt %0,%1"
5450 [(set_attr "type" "dsqrt")])
5451
9c78b944
DE		 5452(define_expand "rsqrtsf2"
5453 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5454 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5455 UNSPEC_RSQRT))]
5456 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5457 && flag_finite_math_only && !flag_trapping_math"
5458{
5459 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5460 DONE;
5461})
5462
5463(define_insn "*rsqrt_internal1"
5464 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5465 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5466 UNSPEC_RSQRT))]
5467 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5468 "frsqrte %0,%1"
5469 [(set_attr "type" "fp")])
5470
0530bc70
AP		 5471(define_expand "copysignsf3"
5472 [(set (match_dup 3)
5473 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5474 (set (match_dup 4)
5475 (neg:SF (abs:SF (match_dup 1))))
5476 (set (match_operand:SF 0 "gpc_reg_operand" "")
5477 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5478 (match_dup 5))
5479 (match_dup 3)
5480 (match_dup 4)))]
696e45ba 5481 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
bb8df8a6 5482 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
0530bc70
AP		 5483 {
5484 operands[3] = gen_reg_rtx (SFmode);
5485 operands[4] = gen_reg_rtx (SFmode);
5486 operands[5] = CONST0_RTX (SFmode);
5487 })
5488
5489(define_expand "copysigndf3"
5490 [(set (match_dup 3)
5491 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5492 (set (match_dup 4)
5493 (neg:DF (abs:DF (match_dup 1))))
5494 (set (match_operand:DF 0 "gpc_reg_operand" "")
5495 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5496 (match_dup 5))
5497 (match_dup 3)
5498 (match_dup 4)))]
696e45ba 5499 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
0530bc70
AP		 5500 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5501 {
5502 operands[3] = gen_reg_rtx (DFmode);
5503 operands[4] = gen_reg_rtx (DFmode);
5504 operands[5] = CONST0_RTX (DFmode);
5505 })
5506
94d7001a
RK		 5507;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5508;; fsel instruction and some auxiliary computations. Then we just have a
5509;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05 5510;; combine.
7ae4d8d4 5511(define_expand "smaxsf3"
8e871c05 5512 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5513 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5514 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5515 (match_dup 1)
5516 (match_dup 2)))]
696e45ba
ME		 5517 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5518 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
50a0b056 5519 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 5520
7ae4d8d4 5521(define_expand "sminsf3"
50a0b056
GK		 5522 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5523 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5524 (match_operand:SF 2 "gpc_reg_operand" ""))
5525 (match_dup 2)
5526 (match_dup 1)))]
696e45ba
ME		 5527 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5528 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
50a0b056 5529 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 5530
8e871c05
RK		 5531(define_split
5532 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5533 (match_operator:SF 3 "min_max_operator"
5534 [(match_operand:SF 1 "gpc_reg_operand" "")
5535 (match_operand:SF 2 "gpc_reg_operand" "")]))]
696e45ba
ME		 5536 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5537 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
50a0b056
GK		 5538 [(const_int 0)]
5539 "
6ae08853 5540{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5541 operands[1], operands[2]);
5542 DONE;
5543}")
2f607b94 5544
a3170dc6
AH		 5545(define_expand "movsicc"
5546 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5547 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5548 (match_operand:SI 2 "gpc_reg_operand" "")
5549 (match_operand:SI 3 "gpc_reg_operand" "")))]
5550 "TARGET_ISEL"
5551 "
5552{
5553 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5554 DONE;
5555 else
5556 FAIL;
5557}")
5558
5559;; We use the BASE_REGS for the isel input operands because, if rA is
5560;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5561;; because we may switch the operands and rB may end up being rA.
5562;;
5563;; We need 2 patterns: an unsigned and a signed pattern. We could
5564;; leave out the mode in operand 4 and use one pattern, but reload can
5565;; change the mode underneath our feet and then gets confused trying
5566;; to reload the value.
5567(define_insn "isel_signed"
5568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5569 (if_then_else:SI
5570 (match_operator 1 "comparison_operator"
5571 [(match_operand:CC 4 "cc_reg_operand" "y")
5572 (const_int 0)])
5573 (match_operand:SI 2 "gpc_reg_operand" "b")
5574 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5575 "TARGET_ISEL"
5576 "*
5577{ return output_isel (operands); }"
5578 [(set_attr "length" "4")])
5579
5580(define_insn "isel_unsigned"
5581 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5582 (if_then_else:SI
5583 (match_operator 1 "comparison_operator"
5584 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5585 (const_int 0)])
5586 (match_operand:SI 2 "gpc_reg_operand" "b")
5587 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5588 "TARGET_ISEL"
5589 "*
5590{ return output_isel (operands); }"
5591 [(set_attr "length" "4")])
5592
94d7001a 5593(define_expand "movsfcc"
0ad91047 5594 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 5595 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5596 (match_operand:SF 2 "gpc_reg_operand" "")
5597 (match_operand:SF 3 "gpc_reg_operand" "")))]
696e45ba 5598 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
94d7001a
RK		 5599 "
5600{
50a0b056
GK		 5601 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5602 DONE;
94d7001a 5603 else
50a0b056 5604 FAIL;
94d7001a 5605}")
d56d506a 5606
50a0b056 5607(define_insn "*fselsfsf4"
8e871c05
RK		 5608 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5609 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5610 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5611 (match_operand:SF 2 "gpc_reg_operand" "f")
5612 (match_operand:SF 3 "gpc_reg_operand" "f")))]
696e45ba 5613 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
8e871c05
RK		 5614 "fsel %0,%1,%2,%3"
5615 [(set_attr "type" "fp")])
2f607b94 5616
50a0b056 5617(define_insn "*fseldfsf4"
94d7001a
RK		 5618 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5619 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 5620 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5621 (match_operand:SF 2 "gpc_reg_operand" "f")
5622 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3a86d13b 5623 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
94d7001a
RK		 5624 "fsel %0,%1,%2,%3"
5625 [(set_attr "type" "fp")])
d56d506a 5626
7a2f7870
AH		 5627(define_expand "negdf2"
5628 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5629 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
696e45ba 5630 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5631 "")
5632
99176a91 5633(define_insn "*negdf2_fpr"
cd2b37d9
RK		 5634 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5635 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
696e45ba 5636 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
1fd4e8c1
RK		 5637 "fneg %0,%1"
5638 [(set_attr "type" "fp")])
5639
7a2f7870
AH		 5640(define_expand "absdf2"
5641 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5642 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
696e45ba 5643 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5644 "")
5645
99176a91 5646(define_insn "*absdf2_fpr"
cd2b37d9
RK		 5647 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5648 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
696e45ba 5649 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
1fd4e8c1
RK		 5650 "fabs %0,%1"
5651 [(set_attr "type" "fp")])
5652
99176a91 5653(define_insn "*nabsdf2_fpr"
cd2b37d9
RK		 5654 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5655 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
696e45ba 5656 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
1fd4e8c1
RK		 5657 "fnabs %0,%1"
5658 [(set_attr "type" "fp")])
5659
7a2f7870
AH		 5660(define_expand "adddf3"
5661 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5662 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5663 (match_operand:DF 2 "gpc_reg_operand" "")))]
696e45ba 5664 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5665 "")
5666
99176a91 5667(define_insn "*adddf3_fpr"
cd2b37d9
RK		 5668 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5669 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5670 (match_operand:DF 2 "gpc_reg_operand" "f")))]
696e45ba 5671 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
ca7f5001 5672 "{fa|fadd} %0,%1,%2"
0bb7b92e
ME		 5673 [(set_attr "type" "fp")
5674 (set_attr "fp_type" "fp_addsub_d")])
1fd4e8c1 5675
7a2f7870
AH		 5676(define_expand "subdf3"
5677 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5678 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5679 (match_operand:DF 2 "gpc_reg_operand" "")))]
696e45ba 5680 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5681 "")
5682
99176a91 5683(define_insn "*subdf3_fpr"
cd2b37d9
RK		 5684 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5685 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5686 (match_operand:DF 2 "gpc_reg_operand" "f")))]
696e45ba 5687 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
ca7f5001 5688 "{fs|fsub} %0,%1,%2"
0bb7b92e
ME		 5689 [(set_attr "type" "fp")
5690 (set_attr "fp_type" "fp_addsub_d")])
1fd4e8c1 5691
7a2f7870
AH		 5692(define_expand "muldf3"
5693 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5694 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5695 (match_operand:DF 2 "gpc_reg_operand" "")))]
696e45ba 5696 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5697 "")
5698
99176a91 5699(define_insn "*muldf3_fpr"
cd2b37d9
RK		 5700 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5701 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5702 (match_operand:DF 2 "gpc_reg_operand" "f")))]
696e45ba 5703 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
ca7f5001 5704 "{fm|fmul} %0,%1,%2"
0bb7b92e
ME		 5705 [(set_attr "type" "dmul")
5706 (set_attr "fp_type" "fp_mul_d")])
5707
7a2f7870
AH		 5708(define_expand "divdf3"
5709 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5710 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5711 (match_operand:DF 2 "gpc_reg_operand" "")))]
e47911ce
DE		 5712 "TARGET_HARD_FLOAT
5713 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5714 && !TARGET_SIMPLE_FPU"
9c78b944 5715 "")
7a2f7870 5716
99176a91 5717(define_insn "*divdf3_fpr"
cd2b37d9
RK		 5718 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5719 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5720 (match_operand:DF 2 "gpc_reg_operand" "f")))]
696e45ba 5721 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
ca7f5001 5722 "{fd|fdiv} %0,%1,%2"
cfb557c4 5723 [(set_attr "type" "ddiv")])
1fd4e8c1 5724
9c78b944
DE		 5725(define_expand "recipdf3"
5726 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5727 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5728 (match_operand:DF 2 "gpc_reg_operand" "f")]
5729 UNSPEC_FRES))]
5730 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5731 && flag_finite_math_only && !flag_trapping_math"
5732{
5733 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5734 DONE;
5735})
5736
5737(define_insn "fred"
5738 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5739 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5740 "TARGET_POPCNTB && flag_finite_math_only"
5741 "fre %0,%1"
5742 [(set_attr "type" "fp")])
5743
1fd4e8c1 5744(define_insn ""
cd2b37d9
RK		 5745 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5746 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5747 (match_operand:DF 2 "gpc_reg_operand" "f"))
5748 (match_operand:DF 3 "gpc_reg_operand" "f")))]
696e45ba 5749 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
ca7f5001 5750 "{fma|fmadd} %0,%1,%2,%3"
0bb7b92e
ME		 5751 [(set_attr "type" "dmul")
5752 (set_attr "fp_type" "fp_maddsub_d")])
1fd4e8c1
RK		 5753
5754(define_insn ""
cd2b37d9
RK		 5755 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5756 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5757 (match_operand:DF 2 "gpc_reg_operand" "f"))
5758 (match_operand:DF 3 "gpc_reg_operand" "f")))]
696e45ba 5759 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
ca7f5001 5760 "{fms|fmsub} %0,%1,%2,%3"
0bb7b92e
ME		 5761 [(set_attr "type" "dmul")
5762 (set_attr "fp_type" "fp_maddsub_d")])
1fd4e8c1
RK		 5763
5764(define_insn ""
cd2b37d9
RK		 5765 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5766 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5767 (match_operand:DF 2 "gpc_reg_operand" "f"))
5768 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
696e45ba 5769 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
16823694
GK		 5770 && HONOR_SIGNED_ZEROS (DFmode)"
5771 "{fnma|fnmadd} %0,%1,%2,%3"
0bb7b92e
ME		 5772 [(set_attr "type" "dmul")
5773 (set_attr "fp_type" "fp_maddsub_d")])
16823694
GK		 5774
5775(define_insn ""
5776 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5777 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5778 (match_operand:DF 2 "gpc_reg_operand" "f"))
5779 (match_operand:DF 3 "gpc_reg_operand" "f")))]
696e45ba 5780 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
16823694 5781 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5782 "{fnma|fnmadd} %0,%1,%2,%3"
0bb7b92e
ME		 5783 [(set_attr "type" "dmul")
5784 (set_attr "fp_type" "fp_maddsub_d")])
1fd4e8c1
RK		 5785
5786(define_insn ""
cd2b37d9
RK		 5787 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5788 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5789 (match_operand:DF 2 "gpc_reg_operand" "f"))
5790 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
696e45ba 5791 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
16823694
GK		 5792 && HONOR_SIGNED_ZEROS (DFmode)"
5793 "{fnms|fnmsub} %0,%1,%2,%3"
0bb7b92e
ME		 5794 [(set_attr "type" "dmul")
5795 (set_attr "fp_type" "fp_maddsub_d")])
16823694
GK		 5796
5797(define_insn ""
5798 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5799 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5800 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5801 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
696e45ba 5802 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
16823694 5803 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5804 "{fnms|fnmsub} %0,%1,%2,%3"
0bb7b92e
ME		 5805 [(set_attr "type" "dmul")
5806 (set_attr "fp_type" "fp_maddsub_d")])
ca7f5001
RK		 5807
5808(define_insn "sqrtdf2"
5809 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5810 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
696e45ba
ME		 5811 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
5812 && TARGET_DOUBLE_FLOAT"
ca7f5001
RK		 5813 "fsqrt %0,%1"
5814 [(set_attr "type" "dsqrt")])
b77dfefc 5815
50a0b056 5816;; The conditional move instructions allow us to perform max and min
6ae08853 5817;; operations even when
b77dfefc 5818
7ae4d8d4 5819(define_expand "smaxdf3"
8e871c05 5820 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5821 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5822 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5823 (match_dup 1)
5824 (match_dup 2)))]
696e45ba
ME		 5825 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5826 && !flag_trapping_math"
50a0b056 5827 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 5828
7ae4d8d4 5829(define_expand "smindf3"
50a0b056
GK		 5830 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5831 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5832 (match_operand:DF 2 "gpc_reg_operand" ""))
5833 (match_dup 2)
5834 (match_dup 1)))]
696e45ba
ME		 5835 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5836 && !flag_trapping_math"
50a0b056 5837 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 5838
8e871c05
RK		 5839(define_split
5840 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5841 (match_operator:DF 3 "min_max_operator"
5842 [(match_operand:DF 1 "gpc_reg_operand" "")
5843 (match_operand:DF 2 "gpc_reg_operand" "")]))]
696e45ba
ME		 5844 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5845 && !flag_trapping_math"
50a0b056
GK		 5846 [(const_int 0)]
5847 "
6ae08853 5848{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5849 operands[1], operands[2]);
5850 DONE;
5851}")
b77dfefc 5852
94d7001a 5853(define_expand "movdfcc"
0ad91047 5854 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 5855 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5856 (match_operand:DF 2 "gpc_reg_operand" "")
5857 (match_operand:DF 3 "gpc_reg_operand" "")))]
696e45ba 5858 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
94d7001a
RK		 5859 "
5860{
50a0b056
GK		 5861 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5862 DONE;
94d7001a 5863 else
50a0b056 5864 FAIL;
94d7001a 5865}")
d56d506a 5866
50a0b056 5867(define_insn "*fseldfdf4"
8e871c05
RK		 5868 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5869 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 5870 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5871 (match_operand:DF 2 "gpc_reg_operand" "f")
5872 (match_operand:DF 3 "gpc_reg_operand" "f")))]
696e45ba 5873 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8e871c05
RK		 5874 "fsel %0,%1,%2,%3"
5875 [(set_attr "type" "fp")])
d56d506a 5876
50a0b056 5877(define_insn "*fselsfdf4"
94d7001a
RK		 5878 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5879 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5880 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5881 (match_operand:DF 2 "gpc_reg_operand" "f")
5882 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3a86d13b 5883 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
94d7001a
RK		 5884 "fsel %0,%1,%2,%3"
5885 [(set_attr "type" "fp")])
1fd4e8c1 5886\f
d095928f
AH		 5887;; Conversions to and from floating-point.
5888
5889(define_expand "fixuns_truncsfsi2"
5890 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5891 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
696e45ba 5892 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
d095928f
AH		 5893 "")
5894
5895(define_expand "fix_truncsfsi2"
0bb7b92e
ME		 5896 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5897 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5898 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5899 "")
d095928f 5900
9ebbca7d
GK		 5901; For each of these conversions, there is a define_expand, a define_insn
5902; with a '#' template, and a define_split (with C code). The idea is
5903; to allow constant folding with the template of the define_insn,
5904; then to have the insns split later (between sched1 and final).
5905
1fd4e8c1 5906(define_expand "floatsidf2"
802a0058
MM		 5907 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5908 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5909 (use (match_dup 2))
5910 (use (match_dup 3))
208c89ce 5911 (clobber (match_dup 4))
a7df97e6 5912 (clobber (match_dup 5))
9ebbca7d 5913 (clobber (match_dup 6))])]
696e45ba
ME		 5914 "TARGET_HARD_FLOAT
5915 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5916 "
5917{
99176a91
AH		 5918 if (TARGET_E500_DOUBLE)
5919 {
5920 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5921 DONE;
5922 }
05d49501
AM		 5923 if (TARGET_POWERPC64)
5924 {
f369bbb1
AP		 5925 rtx x = convert_to_mode (DImode, operands[1], 0);
5926 emit_insn (gen_floatdidf2 (operands[0], x));
05d49501
AM		 5927 DONE;
5928 }
5929
802a0058 5930 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5931 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5932 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5933 operands[5] = gen_reg_rtx (DFmode);
5934 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5935}")
5936
230215f5 5937(define_insn_and_split "*floatsidf2_internal"
802a0058
MM		 5938 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5939 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5940 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5941 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
b0d6c7d8 5942 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6f9c81f5
DJ		 5943 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5944 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
696e45ba 5945 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
802a0058 5946 "#"
b3a13419 5947 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5948 [(pc)]
208c89ce
MM		 5949 "
5950{
9ebbca7d 5951 rtx lowword, highword;
230215f5
GK		 5952 gcc_assert (MEM_P (operands[4]));
5953 highword = adjust_address (operands[4], SImode, 0);
5954 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d
GK		 5955 if (! WORDS_BIG_ENDIAN)
5956 {
5957 rtx tmp;
5958 tmp = highword; highword = lowword; lowword = tmp;
5959 }
5960
6ae08853 5961 emit_insn (gen_xorsi3 (operands[6], operands[1],
9ebbca7d 5962 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
230215f5
GK		 5963 emit_move_insn (lowword, operands[6]);
5964 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5965 emit_move_insn (operands[5], operands[4]);
5966 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5967 DONE;
230215f5
GK		 5968}"
5969 [(set_attr "length" "24")])
802a0058 5970
a3170dc6
AH		 5971(define_expand "floatunssisf2"
5972 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5973 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
696e45ba 5974 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
a3170dc6
AH		 5975 "")
5976
802a0058
MM		 5977(define_expand "floatunssidf2"
5978 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5979 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5980 (use (match_dup 2))
5981 (use (match_dup 3))
a7df97e6 5982 (clobber (match_dup 4))
9ebbca7d 5983 (clobber (match_dup 5))])]
696e45ba 5984 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5985 "
5986{
99176a91
AH		 5987 if (TARGET_E500_DOUBLE)
5988 {
5989 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5990 DONE;
5991 }
05d49501
AM		 5992 if (TARGET_POWERPC64)
5993 {
f369bbb1
AP		 5994 rtx x = convert_to_mode (DImode, operands[1], 1);
5995 emit_insn (gen_floatdidf2 (operands[0], x));
05d49501
AM		 5996 DONE;
5997 }
5998
802a0058 5999 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 6000 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 6001 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6002 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 6003}")
6004
230215f5 6005(define_insn_and_split "*floatunssidf2_internal"
802a0058
MM		 6006 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
6007 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6008 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6009 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
b0d6c7d8 6010 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6f9c81f5 6011 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
696e45ba 6012 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
802a0058 6013 "#"
b3a13419 6014 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 6015 [(pc)]
9ebbca7d 6016 "
802a0058 6017{
9ebbca7d 6018 rtx lowword, highword;
230215f5
GK		 6019 gcc_assert (MEM_P (operands[4]));
6020 highword = adjust_address (operands[4], SImode, 0);
6021 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d 6022 if (! WORDS_BIG_ENDIAN)
f6968f59 6023 {
9ebbca7d
GK		 6024 rtx tmp;
6025 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 6026 }
802a0058 6027
230215f5
GK		 6028 emit_move_insn (lowword, operands[1]);
6029 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 6030 emit_move_insn (operands[5], operands[4]);
6031 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6032 DONE;
230215f5
GK		 6033}"
6034 [(set_attr "length" "20")])
1fd4e8c1 6035
1fd4e8c1 6036(define_expand "fix_truncdfsi2"
045a8eb3 6037 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
802a0058
MM		 6038 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6039 (clobber (match_dup 2))
9ebbca7d 6040 (clobber (match_dup 3))])]
99176a91 6041 "(TARGET_POWER2 || TARGET_POWERPC)
696e45ba 6042 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 6043 "
6044{
99176a91
AH		 6045 if (TARGET_E500_DOUBLE)
6046 {
6047 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6048 DONE;
6049 }
802a0058 6050 operands[2] = gen_reg_rtx (DImode);
44cd321e
PS		 6051 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6052 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6053 {
6054 operands[3] = gen_reg_rtx (DImode);
6055 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6056 operands[2], operands[3]));
6057 DONE;
6058 }
da4c340c
GK		 6059 if (TARGET_PPC_GFXOPT)
6060 {
6061 rtx orig_dest = operands[0];
045a8eb3 6062 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
da4c340c
GK		 6063 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6064 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6065 operands[2]));
6066 if (operands[0] != orig_dest)
6067 emit_move_insn (orig_dest, operands[0]);
6068 DONE;
6069 }
9ebbca7d 6070 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 6071}")
6072
da4c340c 6073(define_insn_and_split "*fix_truncdfsi2_internal"
802a0058
MM		 6074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6075 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 6076 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
b0d6c7d8 6077 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
696e45ba
ME		 6078 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6079 && TARGET_DOUBLE_FLOAT"
802a0058 6080 "#"
b3a13419 6081 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
da4c340c 6082 [(pc)]
9ebbca7d 6083 "
802a0058 6084{
9ebbca7d 6085 rtx lowword;
230215f5
GK		 6086 gcc_assert (MEM_P (operands[3]));
6087 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
802a0058 6088
9ebbca7d
GK		 6089 emit_insn (gen_fctiwz (operands[2], operands[1]));
6090 emit_move_insn (operands[3], operands[2]);
230215f5 6091 emit_move_insn (operands[0], lowword);
9ebbca7d 6092 DONE;
da4c340c
GK		 6093}"
6094 [(set_attr "length" "16")])
6095
6096(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6097 [(set (match_operand:SI 0 "memory_operand" "=Z")
6098 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6099 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
696e45ba
ME		 6100 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6101 && TARGET_DOUBLE_FLOAT
da4c340c
GK		 6102 && TARGET_PPC_GFXOPT"
6103 "#"
6104 "&& 1"
6105 [(pc)]
6106 "
6107{
6108 emit_insn (gen_fctiwz (operands[2], operands[1]));
6109 emit_insn (gen_stfiwx (operands[0], operands[2]));
6110 DONE;
6111}"
6112 [(set_attr "length" "16")])
802a0058 6113
44cd321e
PS		 6114(define_insn_and_split "fix_truncdfsi2_mfpgpr"
6115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6116 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6117 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6118 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
696e45ba
ME		 6119 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6120 && TARGET_DOUBLE_FLOAT"
44cd321e
PS		 6121 "#"
6122 "&& 1"
6123 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6124 (set (match_dup 3) (match_dup 2))
6125 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6126 ""
6127 [(set_attr "length" "12")])
6128
615158e2 6129; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 6130; rather than (set (subreg:SI (reg)) (fix:SI ...))
6131; because the first makes it clear that operand 0 is not live
6132; before the instruction.
6133(define_insn "fctiwz"
da4c340c 6134 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
615158e2
JJ		 6135 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6136 UNSPEC_FCTIWZ))]
696e45ba
ME		 6137 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6138 && TARGET_DOUBLE_FLOAT"
a260abc9
DE		 6139 "{fcirz|fctiwz} %0,%1"
6140 [(set_attr "type" "fp")])
6141
9719f3b7
DE		 6142(define_insn "btruncdf2"
6143 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6144 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
696e45ba 6145 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9719f3b7
DE		 6146 "friz %0,%1"
6147 [(set_attr "type" "fp")])
6148
6149(define_insn "btruncsf2"
6150 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6151 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
696e45ba 6152 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
833126ad 6153 "friz %0,%1"
9719f3b7
DE		 6154 [(set_attr "type" "fp")])
6155
6156(define_insn "ceildf2"
6157 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6158 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
696e45ba 6159 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9719f3b7
DE		 6160 "frip %0,%1"
6161 [(set_attr "type" "fp")])
6162
6163(define_insn "ceilsf2"
833126ad 6164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9719f3b7 6165 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
696e45ba 6166 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
833126ad 6167 "frip %0,%1"
9719f3b7
DE		 6168 [(set_attr "type" "fp")])
6169
6170(define_insn "floordf2"
6171 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6172 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
696e45ba 6173 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9719f3b7
DE		 6174 "frim %0,%1"
6175 [(set_attr "type" "fp")])
6176
6177(define_insn "floorsf2"
6178 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6179 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
696e45ba 6180 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
833126ad 6181 "frim %0,%1"
9719f3b7
DE		 6182 [(set_attr "type" "fp")])
6183
6184(define_insn "rounddf2"
6185 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6186 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
696e45ba 6187 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9719f3b7
DE		 6188 "frin %0,%1"
6189 [(set_attr "type" "fp")])
6190
6191(define_insn "roundsf2"
6192 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6193 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
696e45ba 6194 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
833126ad 6195 "frin %0,%1"
9719f3b7
DE		 6196 [(set_attr "type" "fp")])
6197
da4c340c
GK		 6198; An UNSPEC is used so we don't have to support SImode in FP registers.
6199(define_insn "stfiwx"
6200 [(set (match_operand:SI 0 "memory_operand" "=Z")
6201 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6202 UNSPEC_STFIWX))]
6203 "TARGET_PPC_GFXOPT"
6204 "stfiwx %1,%y0"
6205 [(set_attr "type" "fpstore")])
6206
a3170dc6
AH		 6207(define_expand "floatsisf2"
6208 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6209 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
0bb7b92e 6210 "TARGET_HARD_FLOAT && !TARGET_FPRS"
a3170dc6
AH		 6211 "")
6212
a473029f
RK		 6213(define_insn "floatdidf2"
6214 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
94e98316 6215 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
0bb7b92e 6216 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
a473029f
RK		 6217 "fcfid %0,%1"
6218 [(set_attr "type" "fp")])
6219
6220(define_insn "fix_truncdfdi2"
94e98316 6221 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
a473029f 6222 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
0bb7b92e 6223 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
a473029f
RK		 6224 "fctidz %0,%1"
6225 [(set_attr "type" "fp")])
ea112fc4 6226
678b7733
AM		 6227(define_expand "floatdisf2"
6228 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6229 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
696e45ba 6230 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
678b7733
AM		 6231 "
6232{
994cf173 6233 rtx val = operands[1];
678b7733
AM		 6234 if (!flag_unsafe_math_optimizations)
6235 {
6236 rtx label = gen_label_rtx ();
994cf173
AM		 6237 val = gen_reg_rtx (DImode);
6238 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
678b7733
AM		 6239 emit_label (label);
6240 }
994cf173 6241 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
678b7733
AM		 6242 DONE;
6243}")
6244
6245;; This is not IEEE compliant if rounding mode is "round to nearest".
6246;; If the DI->DF conversion is inexact, then it's possible to suffer
6247;; from double rounding.
6248(define_insn_and_split "floatdisf2_internal1"
ea112fc4 6249 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
94e98316 6250 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
ea112fc4 6251 (clobber (match_scratch:DF 2 "=f"))]
696e45ba 6252 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
ea112fc4
DE		 6253 "#"
6254 "&& reload_completed"
6255 [(set (match_dup 2)
6256 (float:DF (match_dup 1)))
6257 (set (match_dup 0)
6258 (float_truncate:SF (match_dup 2)))]
6259 "")
678b7733
AM		 6260
6261;; Twiddles bits to avoid double rounding.
b6d08ca1 6262;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 6263;; by a bit that won't be lost at that stage, but is below the SFmode
6264;; rounding position.
6265(define_expand "floatdisf2_internal2"
994cf173
AM		 6266 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6267 (const_int 53)))
6268 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6269 (const_int 2047)))
6270 (clobber (scratch:CC))])
6271 (set (match_dup 3) (plus:DI (match_dup 3)
6272 (const_int 1)))
6273 (set (match_dup 0) (plus:DI (match_dup 0)
6274 (const_int 2047)))
6275 (set (match_dup 4) (compare:CCUNS (match_dup 3)
c22e62a6 6276 (const_int 2)))
994cf173
AM		 6277 (set (match_dup 0) (ior:DI (match_dup 0)
6278 (match_dup 1)))
6279 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6280 (const_int -2048)))
6281 (clobber (scratch:CC))])
6282 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6283 (label_ref (match_operand:DI 2 "" ""))
678b7733 6284 (pc)))
994cf173 6285 (set (match_dup 0) (match_dup 1))]
696e45ba 6286 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
678b7733
AM		 6287 "
6288{
678b7733 6289 operands[3] = gen_reg_rtx (DImode);
994cf173 6290 operands[4] = gen_reg_rtx (CCUNSmode);
678b7733 6291}")
1fd4e8c1
RK		 6292\f
6293;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 6294;; of instructions. The & constraints are to prevent the register
6295;; allocator from allocating registers that overlap with the inputs
6296;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 6297;; also allow for the output being the same as one of the inputs.
a6ec530c 6298
266eb58a 6299(define_insn "*adddi3_noppc64"
a6ec530c
RK		 6300 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6301 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6302 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 6303 "! TARGET_POWERPC64"
0f645302
MM		 6304 "*
6305{
6306 if (WORDS_BIG_ENDIAN)
6307 return (GET_CODE (operands[2])) != CONST_INT
6308 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6309 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6310 else
6311 return (GET_CODE (operands[2])) != CONST_INT
6312 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6313 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6314}"
943c15ed
DE		 6315 [(set_attr "type" "two")
6316 (set_attr "length" "8")])
1fd4e8c1 6317
266eb58a 6318(define_insn "*subdi3_noppc64"
e7e5df70
RK		 6319 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6320 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6321 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 6322 "! TARGET_POWERPC64"
5502823b
RK		 6323 "*
6324{
0f645302
MM		 6325 if (WORDS_BIG_ENDIAN)
6326 return (GET_CODE (operands[1]) != CONST_INT)
6327 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6328 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6329 else
6330 return (GET_CODE (operands[1]) != CONST_INT)
6331 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6332 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 6333}"
943c15ed
DE		 6334 [(set_attr "type" "two")
6335 (set_attr "length" "8")])
ca7f5001 6336
266eb58a 6337(define_insn "*negdi2_noppc64"
a6ec530c
RK		 6338 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6339 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 6340 "! TARGET_POWERPC64"
5502823b
RK		 6341 "*
6342{
6343 return (WORDS_BIG_ENDIAN)
6344 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6345 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6346}"
943c15ed
DE		 6347 [(set_attr "type" "two")
6348 (set_attr "length" "8")])
ca7f5001 6349
8ffd9c51
RK		 6350(define_expand "mulsidi3"
6351 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6352 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6353 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 6354 "! TARGET_POWERPC64"
8ffd9c51
RK		 6355 "
6356{
6357 if (! TARGET_POWER && ! TARGET_POWERPC)
6358 {
39403d82
DE		 6359 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6360 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6361 emit_insn (gen_mull_call ());
cf27b467 6362 if (WORDS_BIG_ENDIAN)
39403d82 6363 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 6364 else
6365 {
6366 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 6367 gen_rtx_REG (SImode, 3));
cf27b467 6368 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 6369 gen_rtx_REG (SImode, 4));
cf27b467 6370 }
8ffd9c51
RK		 6371 DONE;
6372 }
6373 else if (TARGET_POWER)
6374 {
6375 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6376 DONE;
6377 }
6378}")
deb9225a 6379
8ffd9c51 6380(define_insn "mulsidi3_mq"
cd2b37d9 6381 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 6382 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 6383 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 6384 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 6385 "TARGET_POWER"
b19003d8 6386 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 6387 [(set_attr "type" "imul")
6388 (set_attr "length" "8")])
deb9225a 6389
f192bf8b 6390(define_insn "*mulsidi3_no_mq"
425c176f 6391 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 6392 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6393 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6394 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 6395 "*
6396{
6397 return (WORDS_BIG_ENDIAN)
6398 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6399 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6400}"
8ffd9c51
RK		 6401 [(set_attr "type" "imul")
6402 (set_attr "length" "8")])
deb9225a 6403
ebedb4dd
MM		 6404(define_split
6405 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6406 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6407 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6408 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6409 [(set (match_dup 3)
6410 (truncate:SI
6411 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6412 (sign_extend:DI (match_dup 2)))
6413 (const_int 32))))
6414 (set (match_dup 4)
6415 (mult:SI (match_dup 1)
6416 (match_dup 2)))]
6417 "
6418{
6419 int endian = (WORDS_BIG_ENDIAN == 0);
6420 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6421 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6422}")
6423
f192bf8b
DE		 6424(define_expand "umulsidi3"
6425 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6426 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6427 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6428 "TARGET_POWERPC && ! TARGET_POWERPC64"
6429 "
6430{
6431 if (TARGET_POWER)
6432 {
6433 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6434 DONE;
6435 }
6436}")
6437
6438(define_insn "umulsidi3_mq"
6439 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6440 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6441 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6442 (clobber (match_scratch:SI 3 "=q"))]
6443 "TARGET_POWERPC && TARGET_POWER"
6444 "*
6445{
6446 return (WORDS_BIG_ENDIAN)
6447 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6448 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6449}"
6450 [(set_attr "type" "imul")
6451 (set_attr "length" "8")])
6452
6453(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 6454 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6455 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6456 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6457 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 6458 "*
6459{
6460 return (WORDS_BIG_ENDIAN)
6461 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6462 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6463}"
6464 [(set_attr "type" "imul")
6465 (set_attr "length" "8")])
6466
ebedb4dd
MM		 6467(define_split
6468 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6469 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6470 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6471 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6472 [(set (match_dup 3)
6473 (truncate:SI
6474 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6475 (zero_extend:DI (match_dup 2)))
6476 (const_int 32))))
6477 (set (match_dup 4)
6478 (mult:SI (match_dup 1)
6479 (match_dup 2)))]
6480 "
6481{
6482 int endian = (WORDS_BIG_ENDIAN == 0);
6483 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6484 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6485}")
6486
8ffd9c51
RK		 6487(define_expand "smulsi3_highpart"
6488 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6489 (truncate:SI
6490 (lshiftrt:DI (mult:DI (sign_extend:DI
e42ac3de 6491 (match_operand:SI 1 "gpc_reg_operand" ""))
8ffd9c51 6492 (sign_extend:DI
e42ac3de 6493 (match_operand:SI 2 "gpc_reg_operand" "")))
8ffd9c51
RK		 6494 (const_int 32))))]
6495 ""
6496 "
6497{
6498 if (! TARGET_POWER && ! TARGET_POWERPC)
6499 {
39403d82
DE		 6500 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6501 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6502 emit_insn (gen_mulh_call ());
39403d82 6503 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 6504 DONE;
6505 }
6506 else if (TARGET_POWER)
6507 {
6508 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6509 DONE;
6510 }
6511}")
deb9225a 6512
8ffd9c51
RK		 6513(define_insn "smulsi3_highpart_mq"
6514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6515 (truncate:SI
fada905b
MM		 6516 (lshiftrt:DI (mult:DI (sign_extend:DI
6517 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6518 (sign_extend:DI
6519 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 6520 (const_int 32))))
6521 (clobber (match_scratch:SI 3 "=q"))]
6522 "TARGET_POWER"
6523 "mul %0,%1,%2"
6524 [(set_attr "type" "imul")])
deb9225a 6525
f192bf8b 6526(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 6527 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6528 (truncate:SI
fada905b
MM		 6529 (lshiftrt:DI (mult:DI (sign_extend:DI
6530 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6531 (sign_extend:DI
6532 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 6533 (const_int 32))))]
f192bf8b 6534 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 6535 "mulhw %0,%1,%2"
6536 [(set_attr "type" "imul")])
deb9225a 6537
f192bf8b
DE		 6538(define_expand "umulsi3_highpart"
6539 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6540 (truncate:SI
6541 (lshiftrt:DI (mult:DI (zero_extend:DI
6542 (match_operand:SI 1 "gpc_reg_operand" ""))
6543 (zero_extend:DI
6544 (match_operand:SI 2 "gpc_reg_operand" "")))
6545 (const_int 32))))]
6546 "TARGET_POWERPC"
6547 "
6548{
6549 if (TARGET_POWER)
6550 {
6551 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6552 DONE;
6553 }
6554}")
6555
6556(define_insn "umulsi3_highpart_mq"
6557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6558 (truncate:SI
6559 (lshiftrt:DI (mult:DI (zero_extend:DI
6560 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6561 (zero_extend:DI
6562 (match_operand:SI 2 "gpc_reg_operand" "r")))
6563 (const_int 32))))
6564 (clobber (match_scratch:SI 3 "=q"))]
6565 "TARGET_POWERPC && TARGET_POWER"
6566 "mulhwu %0,%1,%2"
6567 [(set_attr "type" "imul")])
6568
6569(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 6570 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6571 (truncate:SI
6572 (lshiftrt:DI (mult:DI (zero_extend:DI
6573 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6574 (zero_extend:DI
6575 (match_operand:SI 2 "gpc_reg_operand" "r")))
6576 (const_int 32))))]
f192bf8b 6577 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 6578 "mulhwu %0,%1,%2"
6579 [(set_attr "type" "imul")])
6580
6581;; If operands 0 and 2 are in the same register, we have a problem. But
6582;; operands 0 and 1 (the usual case) can be in the same register. That's
6583;; why we have the strange constraints below.
6584(define_insn "ashldi3_power"
6585 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6586 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6587 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6588 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6589 "TARGET_POWER"
6590 "@
6591 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6592 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6593 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6594 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6595 [(set_attr "length" "8")])
6596
6597(define_insn "lshrdi3_power"
47ad8c61 6598 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 6599 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6600 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6601 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6602 "TARGET_POWER"
6603 "@
47ad8c61 6604 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 6605 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6606 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6607 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6608 [(set_attr "length" "8")])
6609
6610;; Shift by a variable amount is too complex to be worth open-coding. We
6611;; just handle shifts by constants.
6612(define_insn "ashrdi3_power"
7093ddee 6613 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 6614 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6615 (match_operand:SI 2 "const_int_operand" "M,i")))
6616 (clobber (match_scratch:SI 3 "=X,q"))]
6617 "TARGET_POWER"
6618 "@
6619 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6620 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
44cd321e
PS		 6621 [(set_attr "type" "shift")
6622 (set_attr "length" "8")])
4aa74a4f
FS		 6623
6624(define_insn "ashrdi3_no_power"
6625 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6626 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6627 (match_operand:SI 2 "const_int_operand" "M,i")))]
97727e85 6628 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
4aa74a4f
FS		 6629 "@
6630 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6631 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
943c15ed
DE		 6632 [(set_attr "type" "two,three")
6633 (set_attr "length" "8,12")])
683bdff7
FJ		 6634
6635(define_insn "*ashrdisi3_noppc64"
6636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 6637 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
683bdff7
FJ		 6638 (const_int 32)) 4))]
6639 "TARGET_32BIT && !TARGET_POWERPC64"
6640 "*
6641{
6642 if (REGNO (operands[0]) == REGNO (operands[1]))
6643 return \"\";
6644 else
6645 return \"mr %0,%1\";
6646}"
6ae08853 6647 [(set_attr "length" "4")])
683bdff7 6648
266eb58a
DE		 6649\f
6650;; PowerPC64 DImode operations.
6651
ea112fc4 6652(define_insn_and_split "absdi2"
266eb58a 6653 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6654 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 6655 (clobber (match_scratch:DI 2 "=&r,&r"))]
6656 "TARGET_POWERPC64"
ea112fc4
DE		 6657 "#"
6658 "&& reload_completed"
a260abc9 6659 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6660 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 6661 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 6662 "")
6663
ea112fc4 6664(define_insn_and_split "*nabsdi2"
266eb58a 6665 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6666 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 6667 (clobber (match_scratch:DI 2 "=&r,&r"))]
6668 "TARGET_POWERPC64"
ea112fc4
DE		 6669 "#"
6670 "&& reload_completed"
a260abc9 6671 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6672 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 6673 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 6674 "")
6675
266eb58a 6676(define_insn "muldi3"
c9692532
DE		 6677 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6678 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6679 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
266eb58a 6680 "TARGET_POWERPC64"
c9692532
DE		 6681 "@
6682 mulld %0,%1,%2
6683 mulli %0,%1,%2"
6684 [(set (attr "type")
6685 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6686 (const_string "imul3")
6687 (match_operand:SI 2 "short_cint_operand" "")
6688 (const_string "imul2")]
6689 (const_string "lmul")))])
266eb58a 6690
9259f3b0
DE		 6691(define_insn "*muldi3_internal1"
6692 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6693 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6694 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6695 (const_int 0)))
6696 (clobber (match_scratch:DI 3 "=r,r"))]
6697 "TARGET_POWERPC64"
6698 "@
6699 mulld. %3,%1,%2
6700 #"
6701 [(set_attr "type" "lmul_compare")
6702 (set_attr "length" "4,8")])
6703
6704(define_split
6705 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6706 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6707 (match_operand:DI 2 "gpc_reg_operand" ""))
6708 (const_int 0)))
6709 (clobber (match_scratch:DI 3 ""))]
6710 "TARGET_POWERPC64 && reload_completed"
6711 [(set (match_dup 3)
6712 (mult:DI (match_dup 1) (match_dup 2)))
6713 (set (match_dup 0)
6714 (compare:CC (match_dup 3)
6715 (const_int 0)))]
6716 "")
6717
6718(define_insn "*muldi3_internal2"
6719 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6720 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6721 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6722 (const_int 0)))
6723 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6724 (mult:DI (match_dup 1) (match_dup 2)))]
6725 "TARGET_POWERPC64"
6726 "@
6727 mulld. %0,%1,%2
6728 #"
6729 [(set_attr "type" "lmul_compare")
6730 (set_attr "length" "4,8")])
6731
6732(define_split
c921bad8 6733 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9259f3b0
DE		 6734 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6735 (match_operand:DI 2 "gpc_reg_operand" ""))
6736 (const_int 0)))
6737 (set (match_operand:DI 0 "gpc_reg_operand" "")
6738 (mult:DI (match_dup 1) (match_dup 2)))]
6739 "TARGET_POWERPC64 && reload_completed"
6740 [(set (match_dup 0)
6741 (mult:DI (match_dup 1) (match_dup 2)))
6742 (set (match_dup 3)
6743 (compare:CC (match_dup 0)
6744 (const_int 0)))]
6745 "")
6746
266eb58a
DE		 6747(define_insn "smuldi3_highpart"
6748 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6749 (truncate:DI
6750 (lshiftrt:TI (mult:TI (sign_extend:TI
6751 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6752 (sign_extend:TI
6753 (match_operand:DI 2 "gpc_reg_operand" "r")))
6754 (const_int 64))))]
6755 "TARGET_POWERPC64"
6756 "mulhd %0,%1,%2"
3cb999d8 6757 [(set_attr "type" "lmul")])
266eb58a
DE		 6758
6759(define_insn "umuldi3_highpart"
6760 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6761 (truncate:DI
6762 (lshiftrt:TI (mult:TI (zero_extend:TI
6763 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6764 (zero_extend:TI
6765 (match_operand:DI 2 "gpc_reg_operand" "r")))
6766 (const_int 64))))]
6767 "TARGET_POWERPC64"
6768 "mulhdu %0,%1,%2"
3cb999d8 6769 [(set_attr "type" "lmul")])
266eb58a 6770
266eb58a 6771(define_insn "rotldi3"
44cd321e
PS		 6772 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6773 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6774 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 6775 "TARGET_POWERPC64"
44cd321e
PS		 6776 "@
6777 rldcl %0,%1,%2,0
6778 rldicl %0,%1,%H2,0"
6779 [(set_attr "type" "var_shift_rotate,integer")])
266eb58a 6780
a260abc9 6781(define_insn "*rotldi3_internal2"
44cd321e
PS		 6782 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6783 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6784 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6785 (const_int 0)))
44cd321e 6786 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6787 "TARGET_64BIT"
9ebbca7d 6788 "@
44cd321e
PS		 6789 rldcl. %3,%1,%2,0
6790 rldicl. %3,%1,%H2,0
6791 #
9ebbca7d 6792 #"
44cd321e
PS		 6793 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6794 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6795
6796(define_split
c921bad8 6797 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6798 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6799 (match_operand:DI 2 "reg_or_cint_operand" ""))
6800 (const_int 0)))
6801 (clobber (match_scratch:DI 3 ""))]
6802 "TARGET_POWERPC64 && reload_completed"
6803 [(set (match_dup 3)
6804 (rotate:DI (match_dup 1) (match_dup 2)))
6805 (set (match_dup 0)
6806 (compare:CC (match_dup 3)
6807 (const_int 0)))]
6808 "")
266eb58a 6809
a260abc9 6810(define_insn "*rotldi3_internal3"
44cd321e
PS		 6811 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6812 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6813 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6814 (const_int 0)))
44cd321e 6815 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 6816 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 6817 "TARGET_64BIT"
9ebbca7d 6818 "@
44cd321e
PS		 6819 rldcl. %0,%1,%2,0
6820 rldicl. %0,%1,%H2,0
6821 #
9ebbca7d 6822 #"
44cd321e
PS		 6823 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6824 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6825
6826(define_split
c921bad8 6827 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6828 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6829 (match_operand:DI 2 "reg_or_cint_operand" ""))
6830 (const_int 0)))
6831 (set (match_operand:DI 0 "gpc_reg_operand" "")
6832 (rotate:DI (match_dup 1) (match_dup 2)))]
6833 "TARGET_POWERPC64 && reload_completed"
6834 [(set (match_dup 0)
6835 (rotate:DI (match_dup 1) (match_dup 2)))
6836 (set (match_dup 3)
6837 (compare:CC (match_dup 0)
6838 (const_int 0)))]
6839 "")
266eb58a 6840
a260abc9 6841(define_insn "*rotldi3_internal4"
44cd321e
PS		 6842 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6843 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6844 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6845 (match_operand:DI 3 "mask64_operand" "n,n")))]
a260abc9 6846 "TARGET_POWERPC64"
44cd321e
PS		 6847 "@
6848 rldc%B3 %0,%1,%2,%S3
6849 rldic%B3 %0,%1,%H2,%S3"
6850 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6851
6852(define_insn "*rotldi3_internal5"
44cd321e 6853 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6854 (compare:CC (and:DI
44cd321e
PS		 6855 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6856 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6857 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6858 (const_int 0)))
44cd321e 6859 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
683bdff7 6860 "TARGET_64BIT"
9ebbca7d 6861 "@
44cd321e
PS		 6862 rldc%B3. %4,%1,%2,%S3
6863 rldic%B3. %4,%1,%H2,%S3
6864 #
9ebbca7d 6865 #"
44cd321e
PS		 6866 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6867 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6868
6869(define_split
c921bad8 6870 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6871 (compare:CC (and:DI
6872 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6873 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6874 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6875 (const_int 0)))
6876 (clobber (match_scratch:DI 4 ""))]
6877 "TARGET_POWERPC64 && reload_completed"
6878 [(set (match_dup 4)
6879 (and:DI (rotate:DI (match_dup 1)
6880 (match_dup 2))
6881 (match_dup 3)))
6882 (set (match_dup 0)
6883 (compare:CC (match_dup 4)
6884 (const_int 0)))]
6885 "")
a260abc9
DE		 6886
6887(define_insn "*rotldi3_internal6"
44cd321e 6888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6889 (compare:CC (and:DI
44cd321e
PS		 6890 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6891 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6892 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6893 (const_int 0)))
44cd321e 6894 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6895 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6896 "TARGET_64BIT"
9ebbca7d 6897 "@
44cd321e
PS		 6898 rldc%B3. %0,%1,%2,%S3
6899 rldic%B3. %0,%1,%H2,%S3
6900 #
9ebbca7d 6901 #"
44cd321e
PS		 6902 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6903 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6904
6905(define_split
c921bad8 6906 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6907 (compare:CC (and:DI
6908 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6909 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6910 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6911 (const_int 0)))
6912 (set (match_operand:DI 0 "gpc_reg_operand" "")
6913 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6914 "TARGET_POWERPC64 && reload_completed"
6915 [(set (match_dup 0)
6916 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6917 (set (match_dup 4)
6918 (compare:CC (match_dup 0)
6919 (const_int 0)))]
6920 "")
a260abc9
DE		 6921
6922(define_insn "*rotldi3_internal7"
44cd321e 6923 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6924 (zero_extend:DI
6925 (subreg:QI
44cd321e
PS		 6926 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6927 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6928 "TARGET_POWERPC64"
44cd321e
PS		 6929 "@
6930 rldcl %0,%1,%2,56
6931 rldicl %0,%1,%H2,56"
6932 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6933
6934(define_insn "*rotldi3_internal8"
44cd321e 6935 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6936 (compare:CC (zero_extend:DI
6937 (subreg:QI
44cd321e
PS		 6938 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6939 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6940 (const_int 0)))
44cd321e 6941 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6942 "TARGET_64BIT"
9ebbca7d 6943 "@
44cd321e
PS		 6944 rldcl. %3,%1,%2,56
6945 rldicl. %3,%1,%H2,56
6946 #
9ebbca7d 6947 #"
44cd321e
PS		 6948 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6949 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6950
6951(define_split
c921bad8 6952 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6953 (compare:CC (zero_extend:DI
6954 (subreg:QI
6955 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6956 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6957 (const_int 0)))
6958 (clobber (match_scratch:DI 3 ""))]
6959 "TARGET_POWERPC64 && reload_completed"
6960 [(set (match_dup 3)
6961 (zero_extend:DI (subreg:QI
6962 (rotate:DI (match_dup 1)
6963 (match_dup 2)) 0)))
6964 (set (match_dup 0)
6965 (compare:CC (match_dup 3)
6966 (const_int 0)))]
6967 "")
a260abc9
DE		 6968
6969(define_insn "*rotldi3_internal9"
44cd321e 6970 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6971 (compare:CC (zero_extend:DI
6972 (subreg:QI
44cd321e
PS		 6973 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6974 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6975 (const_int 0)))
44cd321e 6976 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6977 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6978 "TARGET_64BIT"
9ebbca7d 6979 "@
44cd321e
PS		 6980 rldcl. %0,%1,%2,56
6981 rldicl. %0,%1,%H2,56
6982 #
9ebbca7d 6983 #"
44cd321e
PS		 6984 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6985 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6986
6987(define_split
c921bad8 6988 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6989 (compare:CC (zero_extend:DI
6990 (subreg:QI
6991 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6992 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6993 (const_int 0)))
6994 (set (match_operand:DI 0 "gpc_reg_operand" "")
6995 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6996 "TARGET_POWERPC64 && reload_completed"
6997 [(set (match_dup 0)
6998 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6999 (set (match_dup 3)
7000 (compare:CC (match_dup 0)
7001 (const_int 0)))]
7002 "")
a260abc9
DE		 7003
7004(define_insn "*rotldi3_internal10"
44cd321e 7005 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 7006 (zero_extend:DI
7007 (subreg:HI
44cd321e
PS		 7008 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7009 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 7010 "TARGET_POWERPC64"
44cd321e
PS		 7011 "@
7012 rldcl %0,%1,%2,48
7013 rldicl %0,%1,%H2,48"
7014 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 7015
7016(define_insn "*rotldi3_internal11"
44cd321e 7017 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7018 (compare:CC (zero_extend:DI
7019 (subreg:HI
44cd321e
PS		 7020 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7021 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7022 (const_int 0)))
44cd321e 7023 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7024 "TARGET_64BIT"
9ebbca7d 7025 "@
44cd321e
PS		 7026 rldcl. %3,%1,%2,48
7027 rldicl. %3,%1,%H2,48
7028 #
9ebbca7d 7029 #"
44cd321e
PS		 7030 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7031 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7032
7033(define_split
c921bad8 7034 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7035 (compare:CC (zero_extend:DI
7036 (subreg:HI
7037 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7038 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7039 (const_int 0)))
7040 (clobber (match_scratch:DI 3 ""))]
7041 "TARGET_POWERPC64 && reload_completed"
7042 [(set (match_dup 3)
7043 (zero_extend:DI (subreg:HI
7044 (rotate:DI (match_dup 1)
7045 (match_dup 2)) 0)))
7046 (set (match_dup 0)
7047 (compare:CC (match_dup 3)
7048 (const_int 0)))]
7049 "")
a260abc9
DE		 7050
7051(define_insn "*rotldi3_internal12"
44cd321e 7052 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7053 (compare:CC (zero_extend:DI
7054 (subreg:HI
44cd321e
PS		 7055 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7056 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7057 (const_int 0)))
44cd321e 7058 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7059 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7060 "TARGET_64BIT"
9ebbca7d 7061 "@
44cd321e
PS		 7062 rldcl. %0,%1,%2,48
7063 rldicl. %0,%1,%H2,48
7064 #
9ebbca7d 7065 #"
44cd321e
PS		 7066 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7067 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7068
7069(define_split
c921bad8 7070 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7071 (compare:CC (zero_extend:DI
7072 (subreg:HI
7073 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7074 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7075 (const_int 0)))
7076 (set (match_operand:DI 0 "gpc_reg_operand" "")
7077 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7078 "TARGET_POWERPC64 && reload_completed"
7079 [(set (match_dup 0)
7080 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7081 (set (match_dup 3)
7082 (compare:CC (match_dup 0)
7083 (const_int 0)))]
7084 "")
a260abc9
DE		 7085
7086(define_insn "*rotldi3_internal13"
44cd321e 7087 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 7088 (zero_extend:DI
7089 (subreg:SI
44cd321e
PS		 7090 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7091 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 7092 "TARGET_POWERPC64"
44cd321e
PS		 7093 "@
7094 rldcl %0,%1,%2,32
7095 rldicl %0,%1,%H2,32"
7096 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 7097
7098(define_insn "*rotldi3_internal14"
44cd321e 7099 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7100 (compare:CC (zero_extend:DI
7101 (subreg:SI
44cd321e
PS		 7102 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7103 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7104 (const_int 0)))
44cd321e 7105 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7106 "TARGET_64BIT"
9ebbca7d 7107 "@
44cd321e
PS		 7108 rldcl. %3,%1,%2,32
7109 rldicl. %3,%1,%H2,32
7110 #
9ebbca7d 7111 #"
44cd321e
PS		 7112 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7113 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7114
7115(define_split
c921bad8 7116 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7117 (compare:CC (zero_extend:DI
7118 (subreg:SI
7119 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7120 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7121 (const_int 0)))
7122 (clobber (match_scratch:DI 3 ""))]
7123 "TARGET_POWERPC64 && reload_completed"
7124 [(set (match_dup 3)
7125 (zero_extend:DI (subreg:SI
7126 (rotate:DI (match_dup 1)
7127 (match_dup 2)) 0)))
7128 (set (match_dup 0)
7129 (compare:CC (match_dup 3)
7130 (const_int 0)))]
7131 "")
a260abc9
DE		 7132
7133(define_insn "*rotldi3_internal15"
44cd321e 7134 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7135 (compare:CC (zero_extend:DI
7136 (subreg:SI
44cd321e
PS		 7137 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7138 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7139 (const_int 0)))
44cd321e 7140 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7141 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7142 "TARGET_64BIT"
9ebbca7d 7143 "@
44cd321e
PS		 7144 rldcl. %0,%1,%2,32
7145 rldicl. %0,%1,%H2,32
7146 #
9ebbca7d 7147 #"
44cd321e
PS		 7148 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7149 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7150
7151(define_split
c921bad8 7152 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7153 (compare:CC (zero_extend:DI
7154 (subreg:SI
7155 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7156 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7157 (const_int 0)))
7158 (set (match_operand:DI 0 "gpc_reg_operand" "")
7159 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7160 "TARGET_POWERPC64 && reload_completed"
7161 [(set (match_dup 0)
7162 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7163 (set (match_dup 3)
7164 (compare:CC (match_dup 0)
7165 (const_int 0)))]
7166 "")
a260abc9 7167
266eb58a
DE		 7168(define_expand "ashldi3"
7169 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7170 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7171 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7172 "TARGET_POWERPC64 || TARGET_POWER"
7173 "
7174{
7175 if (TARGET_POWERPC64)
7176 ;
7177 else if (TARGET_POWER)
7178 {
7179 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7180 DONE;
7181 }
7182 else
7183 FAIL;
7184}")
7185
e2c953b6 7186(define_insn "*ashldi3_internal1"
44cd321e
PS		 7187 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7188 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7189 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7190 "TARGET_POWERPC64"
44cd321e
PS		 7191 "@
7192 sld %0,%1,%2
7193 sldi %0,%1,%H2"
7194 [(set_attr "type" "var_shift_rotate,shift")])
6ae08853 7195
e2c953b6 7196(define_insn "*ashldi3_internal2"
44cd321e
PS		 7197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7198 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7199 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7200 (const_int 0)))
44cd321e 7201 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7202 "TARGET_64BIT"
9ebbca7d 7203 "@
44cd321e
PS		 7204 sld. %3,%1,%2
7205 sldi. %3,%1,%H2
7206 #
9ebbca7d 7207 #"
44cd321e
PS		 7208 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7209 (set_attr "length" "4,4,8,8")])
6ae08853 7210
9ebbca7d
GK		 7211(define_split
7212 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7213 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7214 (match_operand:SI 2 "reg_or_cint_operand" ""))
7215 (const_int 0)))
7216 (clobber (match_scratch:DI 3 ""))]
7217 "TARGET_POWERPC64 && reload_completed"
7218 [(set (match_dup 3)
7219 (ashift:DI (match_dup 1) (match_dup 2)))
7220 (set (match_dup 0)
7221 (compare:CC (match_dup 3)
7222 (const_int 0)))]
7223 "")
7224
e2c953b6 7225(define_insn "*ashldi3_internal3"
44cd321e
PS		 7226 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7227 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7228 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7229 (const_int 0)))
44cd321e 7230 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7231 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 7232 "TARGET_64BIT"
9ebbca7d 7233 "@
44cd321e
PS		 7234 sld. %0,%1,%2
7235 sldi. %0,%1,%H2
7236 #
9ebbca7d 7237 #"
44cd321e
PS		 7238 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7239 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7240
7241(define_split
7242 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7243 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7244 (match_operand:SI 2 "reg_or_cint_operand" ""))
7245 (const_int 0)))
7246 (set (match_operand:DI 0 "gpc_reg_operand" "")
7247 (ashift:DI (match_dup 1) (match_dup 2)))]
7248 "TARGET_POWERPC64 && reload_completed"
7249 [(set (match_dup 0)
7250 (ashift:DI (match_dup 1) (match_dup 2)))
7251 (set (match_dup 3)
7252 (compare:CC (match_dup 0)
7253 (const_int 0)))]
7254 "")
266eb58a 7255
e2c953b6 7256(define_insn "*ashldi3_internal4"
3cb999d8
DE		 7257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7258 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7259 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 7260 (match_operand:DI 3 "const_int_operand" "n")))]
7261 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 7262 "rldic %0,%1,%H2,%W3")
3cb999d8 7263
e2c953b6 7264(define_insn "ashldi3_internal5"
9ebbca7d 7265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 7266 (compare:CC
9ebbca7d
GK		 7267 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7268 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7269 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7270 (const_int 0)))
9ebbca7d 7271 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7272 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7273 "@
e2c953b6 7274 rldic. %4,%1,%H2,%W3
9ebbca7d 7275 #"
9c6fdb46 7276 [(set_attr "type" "compare")
9ebbca7d
GK		 7277 (set_attr "length" "4,8")])
7278
7279(define_split
c921bad8 7280 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7281 (compare:CC
7282 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7283 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7284 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7285 (const_int 0)))
7286 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 7287 "TARGET_POWERPC64 && reload_completed
7288 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 7289 [(set (match_dup 4)
7290 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 7291 (match_dup 3)))
9ebbca7d
GK		 7292 (set (match_dup 0)
7293 (compare:CC (match_dup 4)
7294 (const_int 0)))]
7295 "")
3cb999d8 7296
e2c953b6 7297(define_insn "*ashldi3_internal6"
9ebbca7d 7298 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 7299 (compare:CC
9ebbca7d
GK		 7300 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7301 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7302 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7303 (const_int 0)))
9ebbca7d 7304 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 7305 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7306 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7307 "@
e2c953b6 7308 rldic. %0,%1,%H2,%W3
9ebbca7d 7309 #"
9c6fdb46 7310 [(set_attr "type" "compare")
9ebbca7d
GK		 7311 (set_attr "length" "4,8")])
7312
7313(define_split
c921bad8 7314 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7315 (compare:CC
7316 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7317 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7318 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7319 (const_int 0)))
7320 (set (match_operand:DI 0 "gpc_reg_operand" "")
7321 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 7322 "TARGET_POWERPC64 && reload_completed
7323 && includes_rldic_lshift_p (operands[2], operands[3])"
7324 [(set (match_dup 0)
7325 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7326 (match_dup 3)))
7327 (set (match_dup 4)
7328 (compare:CC (match_dup 0)
7329 (const_int 0)))]
7330 "")
7331
7332(define_insn "*ashldi3_internal7"
7333 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7334 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7335 (match_operand:SI 2 "const_int_operand" "i"))
1990cd79 7336 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 7337 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7338 "rldicr %0,%1,%H2,%S3")
7339
7340(define_insn "ashldi3_internal8"
7341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7342 (compare:CC
7343 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7344 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7345 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7346 (const_int 0)))
7347 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7348 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7349 "@
7350 rldicr. %4,%1,%H2,%S3
7351 #"
9c6fdb46 7352 [(set_attr "type" "compare")
c5059423
AM		 7353 (set_attr "length" "4,8")])
7354
7355(define_split
c921bad8 7356 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
c5059423
AM		 7357 (compare:CC
7358 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7359 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7360 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7361 (const_int 0)))
7362 (clobber (match_scratch:DI 4 ""))]
7363 "TARGET_POWERPC64 && reload_completed
7364 && includes_rldicr_lshift_p (operands[2], operands[3])"
7365 [(set (match_dup 4)
7366 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7367 (match_dup 3)))
7368 (set (match_dup 0)
7369 (compare:CC (match_dup 4)
7370 (const_int 0)))]
7371 "")
7372
7373(define_insn "*ashldi3_internal9"
7374 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7375 (compare:CC
7376 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7377 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7378 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7379 (const_int 0)))
7380 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7381 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7382 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7383 "@
7384 rldicr. %0,%1,%H2,%S3
7385 #"
9c6fdb46 7386 [(set_attr "type" "compare")
c5059423
AM		 7387 (set_attr "length" "4,8")])
7388
7389(define_split
c921bad8 7390 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
c5059423
AM		 7391 (compare:CC
7392 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7393 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7394 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7395 (const_int 0)))
7396 (set (match_operand:DI 0 "gpc_reg_operand" "")
7397 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7398 "TARGET_POWERPC64 && reload_completed
7399 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 7400 [(set (match_dup 0)
e2c953b6
DE		 7401 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7402 (match_dup 3)))
9ebbca7d
GK		 7403 (set (match_dup 4)
7404 (compare:CC (match_dup 0)
7405 (const_int 0)))]
7406 "")
7407
7408(define_expand "lshrdi3"
266eb58a
DE		 7409 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7410 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7411 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7412 "TARGET_POWERPC64 || TARGET_POWER"
7413 "
7414{
7415 if (TARGET_POWERPC64)
7416 ;
7417 else if (TARGET_POWER)
7418 {
7419 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7420 DONE;
7421 }
7422 else
7423 FAIL;
7424}")
7425
e2c953b6 7426(define_insn "*lshrdi3_internal1"
44cd321e
PS		 7427 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7428 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7429 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7430 "TARGET_POWERPC64"
44cd321e
PS		 7431 "@
7432 srd %0,%1,%2
7433 srdi %0,%1,%H2"
7434 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7435
e2c953b6 7436(define_insn "*lshrdi3_internal2"
44cd321e
PS		 7437 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7438 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7439 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
29ae5b89 7440 (const_int 0)))
44cd321e 7441 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7442 "TARGET_64BIT "
9ebbca7d 7443 "@
44cd321e
PS		 7444 srd. %3,%1,%2
7445 srdi. %3,%1,%H2
7446 #
9ebbca7d 7447 #"
44cd321e
PS		 7448 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7449 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7450
7451(define_split
c921bad8 7452 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7453 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7454 (match_operand:SI 2 "reg_or_cint_operand" ""))
7455 (const_int 0)))
7456 (clobber (match_scratch:DI 3 ""))]
7457 "TARGET_POWERPC64 && reload_completed"
7458 [(set (match_dup 3)
7459 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7460 (set (match_dup 0)
7461 (compare:CC (match_dup 3)
7462 (const_int 0)))]
7463 "")
266eb58a 7464
e2c953b6 7465(define_insn "*lshrdi3_internal3"
44cd321e
PS		 7466 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7467 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7468 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7469 (const_int 0)))
44cd321e 7470 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 7471 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7472 "TARGET_64BIT"
9ebbca7d 7473 "@
44cd321e
PS		 7474 srd. %0,%1,%2
7475 srdi. %0,%1,%H2
7476 #
9ebbca7d 7477 #"
44cd321e
PS		 7478 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7479 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7480
7481(define_split
c921bad8 7482 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7483 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7484 (match_operand:SI 2 "reg_or_cint_operand" ""))
7485 (const_int 0)))
7486 (set (match_operand:DI 0 "gpc_reg_operand" "")
7487 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7488 "TARGET_POWERPC64 && reload_completed"
7489 [(set (match_dup 0)
7490 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7491 (set (match_dup 3)
7492 (compare:CC (match_dup 0)
7493 (const_int 0)))]
7494 "")
266eb58a
DE		 7495
7496(define_expand "ashrdi3"
7497 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7498 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7499 (match_operand:SI 2 "reg_or_cint_operand" "")))]
97727e85 7500 "WORDS_BIG_ENDIAN"
266eb58a
DE		 7501 "
7502{
7503 if (TARGET_POWERPC64)
7504 ;
7505 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7506 {
7507 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7508 DONE;
7509 }
97727e85
AH		 7510 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7511 && WORDS_BIG_ENDIAN)
4aa74a4f
FS		 7512 {
7513 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7514 DONE;
7515 }
266eb58a
DE		 7516 else
7517 FAIL;
7518}")
7519
e2c953b6 7520(define_insn "*ashrdi3_internal1"
44cd321e
PS		 7521 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7522 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7523 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7524 "TARGET_POWERPC64"
44cd321e
PS		 7525 "@
7526 srad %0,%1,%2
7527 sradi %0,%1,%H2"
7528 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7529
e2c953b6 7530(define_insn "*ashrdi3_internal2"
44cd321e
PS		 7531 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7532 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7533 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7534 (const_int 0)))
44cd321e 7535 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7536 "TARGET_64BIT"
9ebbca7d 7537 "@
44cd321e
PS		 7538 srad. %3,%1,%2
7539 sradi. %3,%1,%H2
7540 #
9ebbca7d 7541 #"
44cd321e
PS		 7542 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7543 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7544
7545(define_split
7546 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7547 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7548 (match_operand:SI 2 "reg_or_cint_operand" ""))
7549 (const_int 0)))
7550 (clobber (match_scratch:DI 3 ""))]
7551 "TARGET_POWERPC64 && reload_completed"
7552 [(set (match_dup 3)
7553 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7554 (set (match_dup 0)
7555 (compare:CC (match_dup 3)
7556 (const_int 0)))]
7557 "")
266eb58a 7558
e2c953b6 7559(define_insn "*ashrdi3_internal3"
44cd321e
PS		 7560 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7561 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7562 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7563 (const_int 0)))
44cd321e 7564 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7565 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7566 "TARGET_64BIT"
9ebbca7d 7567 "@
44cd321e
PS		 7568 srad. %0,%1,%2
7569 sradi. %0,%1,%H2
7570 #
9ebbca7d 7571 #"
44cd321e
PS		 7572 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7573 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7574
7575(define_split
7576 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7577 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7578 (match_operand:SI 2 "reg_or_cint_operand" ""))
7579 (const_int 0)))
7580 (set (match_operand:DI 0 "gpc_reg_operand" "")
7581 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7582 "TARGET_POWERPC64 && reload_completed"
7583 [(set (match_dup 0)
7584 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7585 (set (match_dup 3)
7586 (compare:CC (match_dup 0)
7587 (const_int 0)))]
7588 "")
815cdc52 7589
c921bad8
AP		 7590(define_expand "anddi3"
7591 [(parallel
7592 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7593 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7594 (match_operand:DI 2 "and64_2_operand" "")))
7595 (clobber (match_scratch:CC 3 ""))])]
7596 "TARGET_POWERPC64"
7597 "")
7598
7599(define_insn "anddi3_mc"
e1e2e653
NS		 7600 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7601 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7602 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7603 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
c921bad8 7604 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
266eb58a
DE		 7605 "@
7606 and %0,%1,%2
29ae5b89 7607 rldic%B2 %0,%1,0,%S2
e1e2e653 7608 rlwinm %0,%1,0,%m2,%M2
29ae5b89 7609 andi. %0,%1,%b2
0ba1b2ff
AM		 7610 andis. %0,%1,%u2
7611 #"
e1e2e653
NS		 7612 [(set_attr "type" "*,*,*,compare,compare,*")
7613 (set_attr "length" "4,4,4,4,4,8")])
0ba1b2ff 7614
c921bad8
AP		 7615(define_insn "anddi3_nomc"
7616 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7617 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7618 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7619 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7620 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7621 "@
7622 and %0,%1,%2
7623 rldic%B2 %0,%1,0,%S2
7624 rlwinm %0,%1,0,%m2,%M2
7625 #"
7626 [(set_attr "length" "4,4,4,8")])
7627
0ba1b2ff
AM		 7628(define_split
7629 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7630 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7631 (match_operand:DI 2 "mask64_2_operand" "")))
7632 (clobber (match_scratch:CC 3 ""))]
7633 "TARGET_POWERPC64
7634 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7635 && !mask_operand (operands[2], DImode)
7636 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7637 [(set (match_dup 0)
7638 (and:DI (rotate:DI (match_dup 1)
7639 (match_dup 4))
7640 (match_dup 5)))
7641 (set (match_dup 0)
7642 (and:DI (rotate:DI (match_dup 0)
7643 (match_dup 6))
7644 (match_dup 7)))]
0ba1b2ff
AM		 7645{
7646 build_mask64_2_operands (operands[2], &operands[4]);
e1e2e653 7647})
266eb58a 7648
c921bad8 7649(define_insn "*anddi3_internal2_mc"
1990cd79
AM		 7650 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7651 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7652 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7653 (const_int 0)))
1990cd79
AM		 7654 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7655 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
c921bad8 7656 "TARGET_64BIT && rs6000_gen_cell_microcode"
266eb58a
DE		 7657 "@
7658 and. %3,%1,%2
6c873122 7659 rldic%B2. %3,%1,0,%S2
1990cd79 7660 rlwinm. %3,%1,0,%m2,%M2
6ffc8580
MM		 7661 andi. %3,%1,%b2
7662 andis. %3,%1,%u2
9ebbca7d
GK		 7663 #
7664 #
7665 #
0ba1b2ff
AM		 7666 #
7667 #
1990cd79 7668 #
9ebbca7d 7669 #"
44cd321e 7670 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7671 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d 7672
0ba1b2ff
AM		 7673(define_split
7674 [(set (match_operand:CC 0 "cc_reg_operand" "")
7675 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7676 (match_operand:DI 2 "mask64_2_operand" ""))
7677 (const_int 0)))
7678 (clobber (match_scratch:DI 3 ""))
7679 (clobber (match_scratch:CC 4 ""))]
1990cd79 7680 "TARGET_64BIT && reload_completed
0ba1b2ff 7681 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7682 && !mask_operand (operands[2], DImode)
7683 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7684 [(set (match_dup 3)
7685 (and:DI (rotate:DI (match_dup 1)
7686 (match_dup 5))
7687 (match_dup 6)))
7688 (parallel [(set (match_dup 0)
7689 (compare:CC (and:DI (rotate:DI (match_dup 3)
7690 (match_dup 7))
7691 (match_dup 8))
7692 (const_int 0)))
7693 (clobber (match_dup 3))])]
7694 "
7695{
7696 build_mask64_2_operands (operands[2], &operands[5]);
7697}")
7698
c921bad8 7699(define_insn "*anddi3_internal3_mc"
1990cd79
AM		 7700 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7701 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7702 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7703 (const_int 0)))
1990cd79 7704 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7705 (and:DI (match_dup 1) (match_dup 2)))
1990cd79 7706 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
c921bad8 7707 "TARGET_64BIT && rs6000_gen_cell_microcode"
266eb58a
DE		 7708 "@
7709 and. %0,%1,%2
6c873122 7710 rldic%B2. %0,%1,0,%S2
1990cd79 7711 rlwinm. %0,%1,0,%m2,%M2
6ffc8580
MM		 7712 andi. %0,%1,%b2
7713 andis. %0,%1,%u2
9ebbca7d
GK		 7714 #
7715 #
7716 #
0ba1b2ff
AM		 7717 #
7718 #
1990cd79 7719 #
9ebbca7d 7720 #"
44cd321e 7721 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7722 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d
GK		 7723
7724(define_split
c921bad8 7725 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d 7726 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
1990cd79 7727 (match_operand:DI 2 "and64_2_operand" ""))
9ebbca7d
GK		 7728 (const_int 0)))
7729 (set (match_operand:DI 0 "gpc_reg_operand" "")
7730 (and:DI (match_dup 1) (match_dup 2)))
7731 (clobber (match_scratch:CC 4 ""))]
1990cd79 7732 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 7733 [(parallel [(set (match_dup 0)
7734 (and:DI (match_dup 1) (match_dup 2)))
7735 (clobber (match_dup 4))])
7736 (set (match_dup 3)
7737 (compare:CC (match_dup 0)
7738 (const_int 0)))]
7739 "")
266eb58a 7740
0ba1b2ff
AM		 7741(define_split
7742 [(set (match_operand:CC 3 "cc_reg_operand" "")
7743 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7744 (match_operand:DI 2 "mask64_2_operand" ""))
7745 (const_int 0)))
7746 (set (match_operand:DI 0 "gpc_reg_operand" "")
7747 (and:DI (match_dup 1) (match_dup 2)))
7748 (clobber (match_scratch:CC 4 ""))]
1990cd79 7749 "TARGET_64BIT && reload_completed
0ba1b2ff 7750 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7751 && !mask_operand (operands[2], DImode)
7752 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7753 [(set (match_dup 0)
7754 (and:DI (rotate:DI (match_dup 1)
7755 (match_dup 5))
7756 (match_dup 6)))
7757 (parallel [(set (match_dup 3)
7758 (compare:CC (and:DI (rotate:DI (match_dup 0)
7759 (match_dup 7))
7760 (match_dup 8))
7761 (const_int 0)))
7762 (set (match_dup 0)
7763 (and:DI (rotate:DI (match_dup 0)
7764 (match_dup 7))
7765 (match_dup 8)))])]
7766 "
7767{
7768 build_mask64_2_operands (operands[2], &operands[5]);
7769}")
7770
a260abc9 7771(define_expand "iordi3"
266eb58a 7772 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7773 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7774 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7775 "TARGET_POWERPC64"
266eb58a
DE		 7776 "
7777{
dfbdccdb 7778 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7779 {
dfbdccdb 7780 HOST_WIDE_INT value;
b3a13419
ILT		 7781 rtx tmp = ((!can_create_pseudo_p ()
7782 || rtx_equal_p (operands[0], operands[1]))
a260abc9 7783 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7784
dfbdccdb
GK		 7785 if (GET_CODE (operands[2]) == CONST_INT)
7786 {
7787 value = INTVAL (operands[2]);
7788 emit_insn (gen_iordi3 (tmp, operands[1],
7789 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7790 }
e2c953b6 7791 else
dfbdccdb
GK		 7792 {
7793 value = CONST_DOUBLE_LOW (operands[2]);
7794 emit_insn (gen_iordi3 (tmp, operands[1],
7795 immed_double_const (value
7796 & (~ (HOST_WIDE_INT) 0xffff),
7797 0, DImode)));
7798 }
e2c953b6 7799
9ebbca7d
GK		 7800 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7801 DONE;
7802 }
266eb58a
DE		 7803}")
7804
a260abc9
DE		 7805(define_expand "xordi3"
7806 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7807 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7808 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7809 "TARGET_POWERPC64"
7810 "
7811{
dfbdccdb 7812 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7813 {
dfbdccdb 7814 HOST_WIDE_INT value;
b3a13419
ILT		 7815 rtx tmp = ((!can_create_pseudo_p ()
7816 || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7817 ? operands[0] : gen_reg_rtx (DImode));
7818
dfbdccdb
GK		 7819 if (GET_CODE (operands[2]) == CONST_INT)
7820 {
7821 value = INTVAL (operands[2]);
7822 emit_insn (gen_xordi3 (tmp, operands[1],
7823 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7824 }
e2c953b6 7825 else
dfbdccdb
GK		 7826 {
7827 value = CONST_DOUBLE_LOW (operands[2]);
7828 emit_insn (gen_xordi3 (tmp, operands[1],
7829 immed_double_const (value
7830 & (~ (HOST_WIDE_INT) 0xffff),
7831 0, DImode)));
7832 }
e2c953b6 7833
9ebbca7d
GK		 7834 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7835 DONE;
7836 }
a260abc9
DE		 7837}")
7838
dfbdccdb 7839(define_insn "*booldi3_internal1"
266eb58a 7840 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7841 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7842 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7843 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7844 "TARGET_POWERPC64"
1fd4e8c1 7845 "@
dfbdccdb
GK		 7846 %q3 %0,%1,%2
7847 %q3i %0,%1,%b2
7848 %q3is %0,%1,%u2")
1fd4e8c1 7849
dfbdccdb 7850(define_insn "*booldi3_internal2"
9ebbca7d 7851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7852 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7853 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7854 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7855 (const_int 0)))
9ebbca7d 7856 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7857 "TARGET_64BIT"
9ebbca7d 7858 "@
dfbdccdb 7859 %q4. %3,%1,%2
9ebbca7d
GK		 7860 #"
7861 [(set_attr "type" "compare")
7862 (set_attr "length" "4,8")])
7863
7864(define_split
c921bad8 7865 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 7866 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7867 [(match_operand:DI 1 "gpc_reg_operand" "")
7868 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7869 (const_int 0)))
9ebbca7d
GK		 7870 (clobber (match_scratch:DI 3 ""))]
7871 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7872 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7873 (set (match_dup 0)
7874 (compare:CC (match_dup 3)
7875 (const_int 0)))]
7876 "")
1fd4e8c1 7877
dfbdccdb 7878(define_insn "*booldi3_internal3"
9ebbca7d 7879 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
d93e052c 7880 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7881 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7882 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7883 (const_int 0)))
9ebbca7d 7884 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7885 (match_dup 4))]
683bdff7 7886 "TARGET_64BIT"
9ebbca7d 7887 "@
dfbdccdb 7888 %q4. %0,%1,%2
9ebbca7d
GK		 7889 #"
7890 [(set_attr "type" "compare")
7891 (set_attr "length" "4,8")])
7892
7893(define_split
c921bad8 7894 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 7895 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7896 [(match_operand:DI 1 "gpc_reg_operand" "")
7897 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7898 (const_int 0)))
75540af0 7899 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7900 (match_dup 4))]
9ebbca7d 7901 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7902 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7903 (set (match_dup 3)
7904 (compare:CC (match_dup 0)
7905 (const_int 0)))]
7906 "")
1fd4e8c1 7907
6ae08853 7908;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7909;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7910
7911(define_split
7912 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7913 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7914 [(match_operand:DI 1 "gpc_reg_operand" "")
7915 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7916 "TARGET_POWERPC64"
dfbdccdb
GK		 7917 [(set (match_dup 0) (match_dup 4))
7918 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7919"
7920{
dfbdccdb 7921 rtx i3,i4;
6ae08853 7922
9ebbca7d
GK		 7923 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7924 {
7925 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7926 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7927 0, DImode);
dfbdccdb 7928 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7929 }
7930 else
7931 {
dfbdccdb 7932 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7933 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7934 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7935 }
1c563bed 7936 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7937 operands[1], i3);
1c563bed 7938 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7939 operands[0], i4);
1fd4e8c1
RK		 7940}")
7941
dfbdccdb 7942(define_insn "*boolcdi3_internal1"
9ebbca7d 7943 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7944 (match_operator:DI 3 "boolean_operator"
7945 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7946 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7947 "TARGET_POWERPC64"
1d328b19 7948 "%q3 %0,%2,%1")
a473029f 7949
dfbdccdb 7950(define_insn "*boolcdi3_internal2"
9ebbca7d 7951 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7952 (compare:CC (match_operator:DI 4 "boolean_operator"
7953 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7954 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7955 (const_int 0)))
9ebbca7d 7956 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7957 "TARGET_64BIT"
9ebbca7d 7958 "@
1d328b19 7959 %q4. %3,%2,%1
9ebbca7d
GK		 7960 #"
7961 [(set_attr "type" "compare")
7962 (set_attr "length" "4,8")])
7963
7964(define_split
c921bad8 7965 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 7966 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7967 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7968 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7969 (const_int 0)))
9ebbca7d
GK		 7970 (clobber (match_scratch:DI 3 ""))]
7971 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7972 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7973 (set (match_dup 0)
7974 (compare:CC (match_dup 3)
7975 (const_int 0)))]
7976 "")
a473029f 7977
dfbdccdb 7978(define_insn "*boolcdi3_internal3"
9ebbca7d 7979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7980 (compare:CC (match_operator:DI 4 "boolean_operator"
7981 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7982 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7983 (const_int 0)))
9ebbca7d 7984 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7985 (match_dup 4))]
683bdff7 7986 "TARGET_64BIT"
9ebbca7d 7987 "@
1d328b19 7988 %q4. %0,%2,%1
9ebbca7d
GK		 7989 #"
7990 [(set_attr "type" "compare")
7991 (set_attr "length" "4,8")])
7992
7993(define_split
c921bad8 7994 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 7995 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7996 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7997 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7998 (const_int 0)))
75540af0 7999 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 8000 (match_dup 4))]
9ebbca7d 8001 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 8002 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 8003 (set (match_dup 3)
8004 (compare:CC (match_dup 0)
8005 (const_int 0)))]
8006 "")
266eb58a 8007
dfbdccdb 8008(define_insn "*boolccdi3_internal1"
a473029f 8009 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 8010 (match_operator:DI 3 "boolean_operator"
8011 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 8012 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 8013 "TARGET_POWERPC64"
dfbdccdb 8014 "%q3 %0,%1,%2")
a473029f 8015
dfbdccdb 8016(define_insn "*boolccdi3_internal2"
9ebbca7d 8017 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 8018 (compare:CC (match_operator:DI 4 "boolean_operator"
8019 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8020 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8021 (const_int 0)))
9ebbca7d 8022 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 8023 "TARGET_64BIT"
9ebbca7d 8024 "@
dfbdccdb 8025 %q4. %3,%1,%2
9ebbca7d
GK		 8026 #"
8027 [(set_attr "type" "compare")
8028 (set_attr "length" "4,8")])
8029
8030(define_split
c921bad8 8031 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 8032 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 8033 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8034 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 8035 (const_int 0)))
9ebbca7d
GK		 8036 (clobber (match_scratch:DI 3 ""))]
8037 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 8038 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 8039 (set (match_dup 0)
8040 (compare:CC (match_dup 3)
8041 (const_int 0)))]
8042 "")
266eb58a 8043
dfbdccdb 8044(define_insn "*boolccdi3_internal3"
9ebbca7d 8045 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 8046 (compare:CC (match_operator:DI 4 "boolean_operator"
8047 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8048 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8049 (const_int 0)))
9ebbca7d 8050 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 8051 (match_dup 4))]
683bdff7 8052 "TARGET_64BIT"
9ebbca7d 8053 "@
dfbdccdb 8054 %q4. %0,%1,%2
9ebbca7d
GK		 8055 #"
8056 [(set_attr "type" "compare")
8057 (set_attr "length" "4,8")])
8058
8059(define_split
c921bad8 8060 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 8061 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 8062 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8063 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 8064 (const_int 0)))
75540af0 8065 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 8066 (match_dup 4))]
9ebbca7d 8067 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 8068 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 8069 (set (match_dup 3)
8070 (compare:CC (match_dup 0)
8071 (const_int 0)))]
8072 "")
dfbdccdb 8073\f
1fd4e8c1 8074;; Now define ways of moving data around.
4697a36c 8075
766a866c
MM		 8076;; Set up a register with a value from the GOT table
8077
8078(define_expand "movsi_got"
52d3af72 8079 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8080 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 8081 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 8082 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 8083 "
8084{
38c1f2d7
MM		 8085 if (GET_CODE (operands[1]) == CONST)
8086 {
8087 rtx offset = const0_rtx;
8088 HOST_WIDE_INT value;
8089
8090 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8091 value = INTVAL (offset);
8092 if (value != 0)
8093 {
b3a13419
ILT		 8094 rtx tmp = (!can_create_pseudo_p ()
8095 ? operands[0]
8096 : gen_reg_rtx (Pmode));
38c1f2d7
MM		 8097 emit_insn (gen_movsi_got (tmp, operands[1]));
8098 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8099 DONE;
8100 }
8101 }
8102
c4c40373 8103 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 8104}")
8105
84f414bc 8106(define_insn "*movsi_got_internal"
52d3af72 8107 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 8108 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8109 (match_operand:SI 2 "gpc_reg_operand" "b")]
8110 UNSPEC_MOVSI_GOT))]
f607bc57 8111 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 8112 "{l|lwz} %0,%a1@got(%2)"
8113 [(set_attr "type" "load")])
8114
b22b9b3e
JL		 8115;; Used by sched, shorten_branches and final when the GOT pseudo reg
8116;; didn't get allocated to a hard register.
6ae08853 8117(define_split
75540af0 8118 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8119 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8120 (match_operand:SI 2 "memory_operand" "")]
8121 UNSPEC_MOVSI_GOT))]
f607bc57 8122 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 8123 && flag_pic == 1
8124 && (reload_in_progress || reload_completed)"
8125 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 8126 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8127 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 8128 "")
8129
1fd4e8c1
RK		 8130;; For SI, we special-case integers that can't be loaded in one insn. We
8131;; do the load 16-bits at a time. We could do this by loading from memory,
8132;; and this is even supposed to be faster, but it is simpler not to get
8133;; integers in the TOC.
ee890fe2
SS		 8134(define_insn "movsi_low"
8135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 8136 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 8137 (match_operand 2 "" ""))))]
8138 "TARGET_MACHO && ! TARGET_64BIT"
8139 "{l|lwz} %0,lo16(%2)(%1)"
8140 [(set_attr "type" "load")
8141 (set_attr "length" "4")])
8142
acad7ed3 8143(define_insn "*movsi_internal1"
165a5bad 8144 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
a004eb82 8145 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
2c5cac98 8146 "!TARGET_SINGLE_FPU &&
e0f56f41 8147 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
1fd4e8c1 8148 "@
deb9225a 8149 mr %0,%1
b9442c72 8150 {cal|la} %0,%a1
ca7f5001
RK		 8151 {l%U1%X1|lwz%U1%X1} %0,%1
8152 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 8153 {lil|li} %0,%1
802a0058 8154 {liu|lis} %0,%v1
beaec479 8155 #
aee86b38 8156 {cal|la} %0,%a1
1fd4e8c1 8157 mf%1 %0
5c23c401 8158 mt%0 %1
e76e75bb 8159 mt%0 %1
a004eb82 8160 mt%0 %1
e34eaae5 8161 {cror 0,0,0|nop}"
02ca7595 8162 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 8163 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 8164
2c5cac98
ME		 8165(define_insn "*movsi_internal1_single"
8166 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8167 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8168 "TARGET_SINGLE_FPU &&
e0f56f41 8169 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
2c5cac98
ME		 8170 "@
8171 mr %0,%1
8172 {cal|la} %0,%a1
8173 {l%U1%X1|lwz%U1%X1} %0,%1
8174 {st%U0%X0|stw%U0%X0} %1,%0
8175 {lil|li} %0,%1
8176 {liu|lis} %0,%v1
8177 #
8178 {cal|la} %0,%a1
8179 mf%1 %0
8180 mt%0 %1
8181 mt%0 %1
8182 mt%0 %1
8183 {cror 0,0,0|nop}
8184 stfs%U0%X0 %1, %0
8185 lfs%U1%X1 %0, %1"
8186 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8187 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8188
77fa0940
RK		 8189;; Split a load of a large constant into the appropriate two-insn
8190;; sequence.
8191
8192(define_split
8193 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8194 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 8195 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 8196 && (INTVAL (operands[1]) & 0xffff) != 0"
8197 [(set (match_dup 0)
8198 (match_dup 2))
8199 (set (match_dup 0)
8200 (ior:SI (match_dup 0)
8201 (match_dup 3)))]
8202 "
af8cb5c5
DE		 8203{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8204
8205 if (tem == operands[0])
8206 DONE;
8207 else
8208 FAIL;
77fa0940
RK		 8209}")
8210
4ae234b0 8211(define_insn "*mov<mode>_internal2"
bb84cb12 8212 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
4ae234b0 8213 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 8214 (const_int 0)))
4ae234b0
GK		 8215 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8216 ""
9ebbca7d 8217 "@
4ae234b0 8218 {cmpi|cmp<wd>i} %2,%0,0
9ebbca7d
GK		 8219 mr. %0,%1
8220 #"
bb84cb12
DE		 8221 [(set_attr "type" "cmp,compare,cmp")
8222 (set_attr "length" "4,4,8")])
8223
9ebbca7d 8224(define_split
c921bad8 8225 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
4ae234b0 8226 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9ebbca7d 8227 (const_int 0)))
4ae234b0
GK		 8228 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8229 "reload_completed"
9ebbca7d
GK		 8230 [(set (match_dup 0) (match_dup 1))
8231 (set (match_dup 2)
8232 (compare:CC (match_dup 0)
8233 (const_int 0)))]
8234 "")
bb84cb12 8235\f
e34eaae5 8236(define_insn "*movhi_internal"
fb81d7ce
RK		 8237 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8238 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8239 "gpc_reg_operand (operands[0], HImode)
8240 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 8241 "@
deb9225a 8242 mr %0,%1
1fd4e8c1
RK		 8243 lhz%U1%X1 %0,%1
8244 sth%U0%X0 %1,%0
19d5775a 8245 {lil|li} %0,%w1
1fd4e8c1 8246 mf%1 %0
e76e75bb 8247 mt%0 %1
fb81d7ce 8248 mt%0 %1
e34eaae5 8249 {cror 0,0,0|nop}"
02ca7595 8250 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1 8251
4ae234b0
GK		 8252(define_expand "mov<mode>"
8253 [(set (match_operand:INT 0 "general_operand" "")
8254 (match_operand:INT 1 "any_operand" ""))]
1fd4e8c1 8255 ""
4ae234b0 8256 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
1fd4e8c1 8257
e34eaae5 8258(define_insn "*movqi_internal"
fb81d7ce
RK		 8259 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8260 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8261 "gpc_reg_operand (operands[0], QImode)
8262 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 8263 "@
deb9225a 8264 mr %0,%1
1fd4e8c1
RK		 8265 lbz%U1%X1 %0,%1
8266 stb%U0%X0 %1,%0
19d5775a 8267 {lil|li} %0,%1
1fd4e8c1 8268 mf%1 %0
e76e75bb 8269 mt%0 %1
fb81d7ce 8270 mt%0 %1
e34eaae5 8271 {cror 0,0,0|nop}"
02ca7595 8272 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 8273\f
8274;; Here is how to move condition codes around. When we store CC data in
8275;; an integer register or memory, we store just the high-order 4 bits.
8276;; This lets us not shift in the most common case of CR0.
8277(define_expand "movcc"
8278 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8279 (match_operand:CC 1 "nonimmediate_operand" ""))]
8280 ""
8281 "")
8282
a65c591c 8283(define_insn "*movcc_internal1"
4eb585a4
DE		 8284 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8285 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
1fd4e8c1
RK		 8286 "register_operand (operands[0], CCmode)
8287 || register_operand (operands[1], CCmode)"
8288 "@
8289 mcrf %0,%1
8290 mtcrf 128,%1
ca7f5001 8291 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
4eb585a4 8292 crxor %0,%0,%0
2c4a9cff
DE		 8293 mfcr %0%Q1
8294 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 8295 mr %0,%1
4eb585a4 8296 {lil|li} %0,%1
b54cf83a 8297 mf%1 %0
b991a865
GK		 8298 mt%0 %1
8299 mt%0 %1
ca7f5001
RK		 8300 {l%U1%X1|lwz%U1%X1} %0,%1
8301 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff 8302 [(set (attr "type")
4eb585a4 8303 (cond [(eq_attr "alternative" "0,3")
2c4a9cff
DE		 8304 (const_string "cr_logical")
8305 (eq_attr "alternative" "1,2")
8306 (const_string "mtcr")
4eb585a4 8307 (eq_attr "alternative" "6,7,9")
2c4a9cff 8308 (const_string "integer")
2c4a9cff 8309 (eq_attr "alternative" "8")
4eb585a4
DE		 8310 (const_string "mfjmpr")
8311 (eq_attr "alternative" "10")
2c4a9cff 8312 (const_string "mtjmpr")
4eb585a4 8313 (eq_attr "alternative" "11")
2c4a9cff 8314 (const_string "load")
4eb585a4 8315 (eq_attr "alternative" "12")
2c4a9cff
DE		 8316 (const_string "store")
8317 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8318 (const_string "mfcrf")
8319 ]
8320 (const_string "mfcr")))
4eb585a4 8321 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
1fd4e8c1 8322\f
e52e05ca
MM		 8323;; For floating-point, we normally deal with the floating-point registers
8324;; unless -msoft-float is used. The sole exception is that parameter passing
8325;; can produce floating-point values in fixed-point registers. Unless the
8326;; value is a simple constant or already in memory, we deal with this by
8327;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 8328(define_expand "movsf"
8329 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8330 (match_operand:SF 1 "any_operand" ""))]
8331 ""
fb4d4348 8332 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 8333
1fd4e8c1 8334(define_split
cd2b37d9 8335 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 8336 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 8337 "reload_completed
5ae4759c
MM		 8338 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8339 || (GET_CODE (operands[0]) == SUBREG
8340 && GET_CODE (SUBREG_REG (operands[0])) == REG
8341 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 8342 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 8343 "
8344{
8345 long l;
8346 REAL_VALUE_TYPE rv;
8347
8348 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8349 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 8350
f99f88e0
DE		 8351 if (! TARGET_POWERPC64)
8352 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8353 else
8354 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 8355
2496c7bd 8356 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 8357}")
8358
c4c40373 8359(define_insn "*movsf_hardfloat"
fb3249ef 8360 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
ae6669e7 8361 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
d14a6d05 8362 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6 8363 || gpc_reg_operand (operands[1], SFmode))
696e45ba 8364 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
1fd4e8c1 8365 "@
f99f88e0
DE		 8366 mr %0,%1
8367 {l%U1%X1|lwz%U1%X1} %0,%1
8368 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 8369 fmr %0,%1
8370 lfs%U1%X1 %0,%1
c4c40373 8371 stfs%U0%X0 %1,%0
b991a865
GK		 8372 mt%0 %1
8373 mt%0 %1
8374 mf%1 %0
e0740893 8375 {cror 0,0,0|nop}
c4c40373
MM		 8376 #
8377 #"
9c6fdb46 8378 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
ae6669e7 8379 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 8380
c4c40373 8381(define_insn "*movsf_softfloat"
dd0fbae2
MK		 8382 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8383 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 8384 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8385 || gpc_reg_operand (operands[1], SFmode))
8386 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 8387 "@
8388 mr %0,%1
b991a865
GK		 8389 mt%0 %1
8390 mt%0 %1
8391 mf%1 %0
d14a6d05
MM		 8392 {l%U1%X1|lwz%U1%X1} %0,%1
8393 {st%U0%X0|stw%U0%X0} %1,%0
8394 {lil|li} %0,%1
802a0058 8395 {liu|lis} %0,%v1
aee86b38 8396 {cal|la} %0,%a1
c4c40373 8397 #
dd0fbae2
MK		 8398 #
8399 {cror 0,0,0|nop}"
9c6fdb46 8400 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
dd0fbae2 8401 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 8402
1fd4e8c1
RK		 8403\f
8404(define_expand "movdf"
8405 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8406 (match_operand:DF 1 "any_operand" ""))]
8407 ""
fb4d4348 8408 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 8409
8410(define_split
cd2b37d9 8411 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 8412 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 8413 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8414 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8415 || (GET_CODE (operands[0]) == SUBREG
8416 && GET_CODE (SUBREG_REG (operands[0])) == REG
8417 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8418 [(set (match_dup 2) (match_dup 4))
8419 (set (match_dup 3) (match_dup 1))]
8420 "
8421{
5ae4759c 8422 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 8423 HOST_WIDE_INT value = INTVAL (operands[1]);
8424
5ae4759c
MM		 8425 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8426 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 8427#if HOST_BITS_PER_WIDE_INT == 32
8428 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8429#else
8430 operands[4] = GEN_INT (value >> 32);
a65c591c 8431 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 8432#endif
c4c40373
MM		 8433}")
8434
c4c40373
MM		 8435(define_split
8436 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8437 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8438 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8439 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8440 || (GET_CODE (operands[0]) == SUBREG
8441 && GET_CODE (SUBREG_REG (operands[0])) == REG
8442 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8443 [(set (match_dup 2) (match_dup 4))
8444 (set (match_dup 3) (match_dup 5))]
8445 "
8446{
5ae4759c 8447 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 8448 long l[2];
8449 REAL_VALUE_TYPE rv;
8450
8451 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8452 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8453
5ae4759c
MM		 8454 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8455 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 8456 operands[4] = gen_int_mode (l[endian], SImode);
8457 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 8458}")
8459
efc08378
DE		 8460(define_split
8461 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8308679f 8462 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8463 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8464 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8465 || (GET_CODE (operands[0]) == SUBREG
8466 && GET_CODE (SUBREG_REG (operands[0])) == REG
8467 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 8468 [(set (match_dup 2) (match_dup 3))]
5ae4759c 8469 "
a260abc9
DE		 8470{
8471 int endian = (WORDS_BIG_ENDIAN == 0);
8472 long l[2];
8473 REAL_VALUE_TYPE rv;
4977bab6 8474#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 8475 HOST_WIDE_INT val;
4977bab6 8476#endif
a260abc9
DE		 8477
8478 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8479 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8480
8481 operands[2] = gen_lowpart (DImode, operands[0]);
8482 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 8483#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8484 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8485 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 8486
f5264b52 8487 operands[3] = gen_int_mode (val, DImode);
5b029315 8488#else
a260abc9 8489 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 8490#endif
a260abc9 8491}")
efc08378 8492
4eae5fe1 8493;; Don't have reload use general registers to load a constant. First,
1427100a 8494;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 8495;; a non-offsettable memref, but also it is less efficient than loading
8496;; the constant into an FP register, since it will probably be used there.
8497;; The "??" is a kludge until we can figure out a more reasonable way
8498;; of handling these non-offsettable values.
c4c40373 8499(define_insn "*movdf_hardfloat32"
914a7297
DE		 8500 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8501 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
696e45ba 8502 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
52d3af72
DE		 8503 && (gpc_reg_operand (operands[0], DFmode)
8504 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 8505 "*
8506{
8507 switch (which_alternative)
8508 {
a260abc9 8509 default:
37409796 8510 gcc_unreachable ();
e7113111
RK		 8511 case 0:
8512 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 8513 the first register operand 0 is the same as the second register
8514 of operand 1, we must copy in the opposite order. */
e7113111 8515 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8516 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 8517 else
deb9225a 8518 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 8519 case 1:
d04b6e6e
EB		 8520 if (rs6000_offsettable_memref_p (operands[1])
8521 || (GET_CODE (operands[1]) == MEM
8522 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8523 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
6fb5fa3c
DB		 8524 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8525 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
000034eb
DE		 8526 {
8527 /* If the low-address word is used in the address, we must load
8528 it last. Otherwise, load it first. Note that we cannot have
8529 auto-increment in that case since the address register is
8530 known to be dead. */
8531 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8532 operands[1], 0))
8533 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8534 else
6fb5fa3c 8535 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
000034eb 8536 }
e7113111 8537 else
000034eb
DE		 8538 {
8539 rtx addreg;
8540
000034eb
DE		 8541 addreg = find_addr_reg (XEXP (operands[1], 0));
8542 if (refers_to_regno_p (REGNO (operands[0]),
8543 REGNO (operands[0]) + 1,
8544 operands[1], 0))
8545 {
8546 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8547 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb 8548 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2284bd2b 8549 return \"{l%X1|lwz%X1} %0,%1\";
000034eb
DE		 8550 }
8551 else
8552 {
2284bd2b 8553 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
000034eb 8554 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8555 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb
DE		 8556 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8557 return \"\";
8558 }
8559 }
e7113111 8560 case 2:
d04b6e6e
EB		 8561 if (rs6000_offsettable_memref_p (operands[0])
8562 || (GET_CODE (operands[0]) == MEM
8563 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8564 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
6fb5fa3c
DB		 8565 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8566 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8567 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
000034eb
DE		 8568 else
8569 {
8570 rtx addreg;
8571
000034eb 8572 addreg = find_addr_reg (XEXP (operands[0], 0));
2284bd2b 8573 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
000034eb 8574 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8575 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
000034eb
DE		 8576 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8577 return \"\";
8578 }
e7113111 8579 case 3:
914a7297 8580 return \"fmr %0,%1\";
e7113111 8581 case 4:
914a7297 8582 return \"lfd%U1%X1 %0,%1\";
e7113111 8583 case 5:
914a7297 8584 return \"stfd%U0%X0 %1,%0\";
e7113111 8585 case 6:
c4c40373 8586 case 7:
c4c40373 8587 case 8:
914a7297 8588 return \"#\";
e7113111
RK		 8589 }
8590}"
943c15ed 8591 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
914a7297 8592 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 8593
c4c40373 8594(define_insn "*movdf_softfloat32"
1427100a
DE		 8595 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8596 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
696e45ba 8597 "! TARGET_POWERPC64
82ad047f 8598 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
696e45ba 8599 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
52d3af72
DE		 8600 && (gpc_reg_operand (operands[0], DFmode)
8601 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8602 "*
8603{
8604 switch (which_alternative)
8605 {
a260abc9 8606 default:
37409796 8607 gcc_unreachable ();
dc4f83ca
MM		 8608 case 0:
8609 /* We normally copy the low-numbered register first. However, if
8610 the first register operand 0 is the same as the second register of
8611 operand 1, we must copy in the opposite order. */
8612 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8613 return \"mr %L0,%L1\;mr %0,%1\";
8614 else
8615 return \"mr %0,%1\;mr %L0,%L1\";
8616 case 1:
3cb999d8
DE		 8617 /* If the low-address word is used in the address, we must load
8618 it last. Otherwise, load it first. Note that we cannot have
8619 auto-increment in that case since the address register is
8620 known to be dead. */
dc4f83ca 8621 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8622 operands[1], 0))
dc4f83ca
MM		 8623 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8624 else
6fb5fa3c 8625 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
dc4f83ca 8626 case 2:
6fb5fa3c 8627 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
dc4f83ca 8628 case 3:
c4c40373
MM		 8629 case 4:
8630 case 5:
dc4f83ca
MM		 8631 return \"#\";
8632 }
8633}"
943c15ed 8634 [(set_attr "type" "two,load,store,*,*,*")
c4c40373 8635 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8636
44cd321e
PS		 8637; ld/std require word-aligned displacements -> 'Y' constraint.
8638; List Y->r and r->Y before r->r for reload.
8639(define_insn "*movdf_hardfloat64_mfpgpr"
8640 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8641 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
696e45ba
ME		 8642 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8643 && TARGET_DOUBLE_FLOAT
44cd321e
PS		 8644 && (gpc_reg_operand (operands[0], DFmode)
8645 || gpc_reg_operand (operands[1], DFmode))"
8646 "@
8647 std%U0%X0 %1,%0
8648 ld%U1%X1 %0,%1
8649 mr %0,%1
8650 fmr %0,%1
8651 lfd%U1%X1 %0,%1
8652 stfd%U0%X0 %1,%0
8653 mt%0 %1
8654 mf%1 %0
8655 {cror 0,0,0|nop}
8656 #
8657 #
8658 #
8659 mftgpr %0,%1
8660 mffgpr %0,%1"
8661 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8662 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8663
d2288d5d
HP		 8664; ld/std require word-aligned displacements -> 'Y' constraint.
8665; List Y->r and r->Y before r->r for reload.
c4c40373 8666(define_insn "*movdf_hardfloat64"
fb3249ef 8667 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
ae6669e7 8668 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
696e45ba
ME		 8669 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8670 && TARGET_DOUBLE_FLOAT
52d3af72
DE		 8671 && (gpc_reg_operand (operands[0], DFmode)
8672 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8673 "@
96bb8ed3 8674 std%U0%X0 %1,%0
3364872d
FJ		 8675 ld%U1%X1 %0,%1
8676 mr %0,%1
3d5570cb 8677 fmr %0,%1
f63184ac 8678 lfd%U1%X1 %0,%1
914a7297
DE		 8679 stfd%U0%X0 %1,%0
8680 mt%0 %1
8681 mf%1 %0
e0740893 8682 {cror 0,0,0|nop}
914a7297
DE		 8683 #
8684 #
8685 #"
9c6fdb46 8686 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
ae6669e7 8687 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8688
c4c40373 8689(define_insn "*movdf_softfloat64"
d2288d5d
HP		 8690 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8691 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
a3170dc6 8692 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8693 && (gpc_reg_operand (operands[0], DFmode)
8694 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca 8695 "@
d2288d5d
HP		 8696 ld%U1%X1 %0,%1
8697 std%U0%X0 %1,%0
dc4f83ca 8698 mr %0,%1
914a7297
DE		 8699 mt%0 %1
8700 mf%1 %0
c4c40373
MM		 8701 #
8702 #
e2d0915c 8703 #
e0740893 8704 {cror 0,0,0|nop}"
9c6fdb46 8705 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
e2d0915c 8706 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 8707\f
06f4e019
DE		 8708(define_expand "movtf"
8709 [(set (match_operand:TF 0 "general_operand" "")
8710 (match_operand:TF 1 "any_operand" ""))]
8521c414 8711 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8712 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8713
a9baceb1
GK		 8714; It's important to list the o->f and f->o moves before f->f because
8715; otherwise reload, given m->f, will try to pick f->f and reload it,
409f61cd 8716; which doesn't make progress. Likewise r->Y must be before r->r.
a9baceb1 8717(define_insn_and_split "*movtf_internal"
409f61cd
AM		 8718 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8719 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
602ea4d3 8720 "!TARGET_IEEEQUAD
39e63627 8721 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8722 && (gpc_reg_operand (operands[0], TFmode)
8723 || gpc_reg_operand (operands[1], TFmode))"
a9baceb1 8724 "#"
ecb62ae7 8725 "&& reload_completed"
a9baceb1
GK		 8726 [(pc)]
8727{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
112ccb83 8728 [(set_attr "length" "8,8,8,20,20,16")])
06f4e019 8729
8521c414 8730(define_insn_and_split "*movtf_softfloat"
17caeff2 8731 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8521c414
JM		 8732 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8733 "!TARGET_IEEEQUAD
8734 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8735 && (gpc_reg_operand (operands[0], TFmode)
8736 || gpc_reg_operand (operands[1], TFmode))"
8737 "#"
8738 "&& reload_completed"
8739 [(pc)]
8740{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8741 [(set_attr "length" "20,20,16")])
8742
ecb62ae7 8743(define_expand "extenddftf2"
17caeff2
JM		 8744 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8745 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8746 "!TARGET_IEEEQUAD
8747 && TARGET_HARD_FLOAT
8748 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8749 && TARGET_LONG_DOUBLE_128"
8750{
8751 if (TARGET_E500_DOUBLE)
8752 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8753 else
8754 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8755 DONE;
8756})
8757
8758(define_expand "extenddftf2_fprs"
ecb62ae7
GK		 8759 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8760 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8761 (use (match_dup 2))])]
602ea4d3 8762 "!TARGET_IEEEQUAD
696e45ba
ME		 8763 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8764 && TARGET_LONG_DOUBLE_128"
06f4e019 8765{
ecb62ae7 8766 operands[2] = CONST0_RTX (DFmode);
aa9cf005
DE		 8767 /* Generate GOT reference early for SVR4 PIC. */
8768 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8769 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
ecb62ae7 8770})
06f4e019 8771
ecb62ae7
GK		 8772(define_insn_and_split "*extenddftf2_internal"
8773 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8774 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
97c54d9a 8775 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
602ea4d3 8776 "!TARGET_IEEEQUAD
696e45ba
ME		 8777 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8778 && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8779 "#"
8780 "&& reload_completed"
8781 [(pc)]
06f4e019 8782{
ecb62ae7
GK		 8783 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8784 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8785 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8786 operands[1]);
8787 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8788 operands[2]);
8789 DONE;
6ae08853 8790})
ecb62ae7
GK		 8791
8792(define_expand "extendsftf2"
8793 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8794 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
602ea4d3 8795 "!TARGET_IEEEQUAD
17caeff2
JM		 8796 && TARGET_HARD_FLOAT
8797 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8798 && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8799{
8800 rtx tmp = gen_reg_rtx (DFmode);
8801 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8802 emit_insn (gen_extenddftf2 (operands[0], tmp));
8803 DONE;
8804})
06f4e019 8805
8cb320b8 8806(define_expand "trunctfdf2"
589b3fda
DE		 8807 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8808 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8809 "!TARGET_IEEEQUAD
17caeff2
JM		 8810 && TARGET_HARD_FLOAT
8811 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8812 && TARGET_LONG_DOUBLE_128"
589b3fda 8813 "")
8cb320b8
DE		 8814
8815(define_insn_and_split "trunctfdf2_internal1"
8816 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8817 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
602ea4d3 8818 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8cb320b8
DE		 8819 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8820 "@
8821 #
8822 fmr %0,%1"
8823 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8824 [(const_int 0)]
8825{
8826 emit_note (NOTE_INSN_DELETED);
8827 DONE;
8828}
8829 [(set_attr "type" "fp")])
8830
8831(define_insn "trunctfdf2_internal2"
8832 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8833 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8834 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
696e45ba
ME		 8835 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8836 && TARGET_LONG_DOUBLE_128"
06f4e019 8837 "fadd %0,%1,%L1"
0bb7b92e
ME		 8838 [(set_attr "type" "fp")
8839 (set_attr "fp_type" "fp_addsub_d")])
06f4e019 8840
17caeff2
JM		 8841(define_expand "trunctfsf2"
8842 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8843 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8844 "!TARGET_IEEEQUAD
8845 && TARGET_HARD_FLOAT
8846 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8847 && TARGET_LONG_DOUBLE_128"
8848{
8849 if (TARGET_E500_DOUBLE)
8850 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8851 else
8852 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8853 DONE;
8854})
8855
8856(define_insn_and_split "trunctfsf2_fprs"
06f4e019 8857 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 8858 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8859 (clobber (match_scratch:DF 2 "=f"))]
602ea4d3 8860 "!TARGET_IEEEQUAD
696e45ba
ME		 8861 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8862 && TARGET_LONG_DOUBLE_128"
06f4e019 8863 "#"
ea112fc4 8864 "&& reload_completed"
06f4e019
DE		 8865 [(set (match_dup 2)
8866 (float_truncate:DF (match_dup 1)))
8867 (set (match_dup 0)
8868 (float_truncate:SF (match_dup 2)))]
ea112fc4 8869 "")
06f4e019 8870
0c90aa3c 8871(define_expand "floatsitf2"
d29b7f64
DE		 8872 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8873 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
602ea4d3 8874 "!TARGET_IEEEQUAD
17caeff2
JM		 8875 && TARGET_HARD_FLOAT
8876 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8877 && TARGET_LONG_DOUBLE_128"
0c90aa3c
GK		 8878{
8879 rtx tmp = gen_reg_rtx (DFmode);
8880 expand_float (tmp, operands[1], false);
8881 emit_insn (gen_extenddftf2 (operands[0], tmp));
8882 DONE;
8883})
06f4e019 8884
ecb62ae7
GK		 8885; fadd, but rounding towards zero.
8886; This is probably not the optimal code sequence.
8887(define_insn "fix_trunc_helper"
8888 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8889 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8890 UNSPEC_FIX_TRUNC_TF))
8891 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
696e45ba 8892 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
ecb62ae7
GK		 8893 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8894 [(set_attr "type" "fp")
8895 (set_attr "length" "20")])
8896
0c90aa3c 8897(define_expand "fix_trunctfsi2"
17caeff2
JM		 8898 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8899 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8900 "!TARGET_IEEEQUAD
8901 && (TARGET_POWER2 || TARGET_POWERPC)
8902 && TARGET_HARD_FLOAT
8903 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8904 && TARGET_LONG_DOUBLE_128"
8905{
8906 if (TARGET_E500_DOUBLE)
8907 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8908 else
8909 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8910 DONE;
8911})
8912
8913(define_expand "fix_trunctfsi2_fprs"
ecb62ae7
GK		 8914 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8915 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8916 (clobber (match_dup 2))
8917 (clobber (match_dup 3))
8918 (clobber (match_dup 4))
8919 (clobber (match_dup 5))])]
602ea4d3 8920 "!TARGET_IEEEQUAD
ecb62ae7
GK		 8921 && (TARGET_POWER2 || TARGET_POWERPC)
8922 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8923{
8924 operands[2] = gen_reg_rtx (DFmode);
8925 operands[3] = gen_reg_rtx (DFmode);
8926 operands[4] = gen_reg_rtx (DImode);
8927 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8928})
8929
8930(define_insn_and_split "*fix_trunctfsi2_internal"
61c07d3c 8931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
ecb62ae7
GK		 8932 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8933 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8934 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8935 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
b0d6c7d8 8936 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
602ea4d3 8937 "!TARGET_IEEEQUAD
39e63627 8938 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 8939 "#"
b3a13419 8940 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
ecb62ae7 8941 [(pc)]
0c90aa3c 8942{
ecb62ae7
GK		 8943 rtx lowword;
8944 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8945
230215f5
GK		 8946 gcc_assert (MEM_P (operands[5]));
8947 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
ecb62ae7
GK		 8948
8949 emit_insn (gen_fctiwz (operands[4], operands[2]));
8950 emit_move_insn (operands[5], operands[4]);
230215f5 8951 emit_move_insn (operands[0], lowword);
0c90aa3c
GK		 8952 DONE;
8953})
06f4e019 8954
17caeff2
JM		 8955(define_expand "negtf2"
8956 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8957 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8958 "!TARGET_IEEEQUAD
8959 && TARGET_HARD_FLOAT
8960 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8961 && TARGET_LONG_DOUBLE_128"
8962 "")
8963
8964(define_insn "negtf2_internal"
06f4e019
DE		 8965 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8966 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8967 "!TARGET_IEEEQUAD
39e63627 8968 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8969 "*
8970{
8971 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8972 return \"fneg %L0,%L1\;fneg %0,%1\";
8973 else
8974 return \"fneg %0,%1\;fneg %L0,%L1\";
8975}"
8976 [(set_attr "type" "fp")
8977 (set_attr "length" "8")])
8978
1a402dc1 8979(define_expand "abstf2"
17caeff2
JM		 8980 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8981 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8982 "!TARGET_IEEEQUAD
17caeff2
JM		 8983 && TARGET_HARD_FLOAT
8984 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8985 && TARGET_LONG_DOUBLE_128"
1a402dc1 8986 "
06f4e019 8987{
1a402dc1 8988 rtx label = gen_label_rtx ();
17caeff2
JM		 8989 if (TARGET_E500_DOUBLE)
8990 {
1cdc0d8f 8991 if (flag_finite_math_only && !flag_trapping_math)
17caeff2
JM		 8992 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8993 else
8994 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8995 }
8996 else
8997 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
1a402dc1
AM		 8998 emit_label (label);
8999 DONE;
9000}")
06f4e019 9001
1a402dc1 9002(define_expand "abstf2_internal"
e42ac3de
RS		 9003 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9004 (match_operand:TF 1 "gpc_reg_operand" ""))
1a402dc1
AM		 9005 (set (match_dup 3) (match_dup 5))
9006 (set (match_dup 5) (abs:DF (match_dup 5)))
9007 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9008 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9009 (label_ref (match_operand 2 "" ""))
9010 (pc)))
9011 (set (match_dup 6) (neg:DF (match_dup 6)))]
602ea4d3 9012 "!TARGET_IEEEQUAD
696e45ba
ME		 9013 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9014 && TARGET_LONG_DOUBLE_128"
1a402dc1 9015 "
06f4e019 9016{
1a402dc1
AM		 9017 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9018 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9019 operands[3] = gen_reg_rtx (DFmode);
9020 operands[4] = gen_reg_rtx (CCFPmode);
9021 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9022 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9023}")
06f4e019 9024\f
1fd4e8c1
RK		 9025;; Next come the multi-word integer load and store and the load and store
9026;; multiple insns.
1fd4e8c1 9027
112ccb83
GK		 9028; List r->r after r->"o<>", otherwise reload will try to reload a
9029; non-offsettable address by using r->r which won't make progress.
acad7ed3 9030(define_insn "*movdi_internal32"
17caeff2 9031 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
112ccb83 9032 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
a260abc9 9033 "! TARGET_POWERPC64
4e74d8ec
MM		 9034 && (gpc_reg_operand (operands[0], DImode)
9035 || gpc_reg_operand (operands[1], DImode))"
112ccb83
GK		 9036 "@
9037 #
9038 #
9039 #
9040 fmr %0,%1
9041 lfd%U1%X1 %0,%1
9042 stfd%U0%X0 %1,%0
9043 #"
9044 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
4e74d8ec
MM		 9045
9046(define_split
9047 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9048 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 9049 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 9050 [(set (match_dup 2) (match_dup 4))
9051 (set (match_dup 3) (match_dup 1))]
9052 "
9053{
5f59ecb7 9054 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 9055 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9056 DImode);
9057 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9058 DImode);
75d39459 9059#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 9060 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 9061#else
5f59ecb7 9062 operands[4] = GEN_INT (value >> 32);
a65c591c 9063 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 9064#endif
4e74d8ec
MM		 9065}")
9066
3a1f863f 9067(define_split
17caeff2 9068 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
3a1f863f 9069 (match_operand:DI 1 "input_operand" ""))]
6ae08853 9070 "reload_completed && !TARGET_POWERPC64
3a1f863f 9071 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 9072 [(pc)]
9073{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
3a1f863f 9074
44cd321e
PS		 9075(define_insn "*movdi_mfpgpr"
9076 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
9077 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
9078 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9079 && (gpc_reg_operand (operands[0], DImode)
9080 || gpc_reg_operand (operands[1], DImode))"
9081 "@
9082 mr %0,%1
9083 ld%U1%X1 %0,%1
9084 std%U0%X0 %1,%0
9085 li %0,%1
9086 lis %0,%v1
9087 #
9088 {cal|la} %0,%a1
9089 fmr %0,%1
9090 lfd%U1%X1 %0,%1
9091 stfd%U0%X0 %1,%0
9092 mf%1 %0
9093 mt%0 %1
9094 {cror 0,0,0|nop}
9095 mftgpr %0,%1
9096 mffgpr %0,%1"
9097 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9098 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9099
acad7ed3 9100(define_insn "*movdi_internal64"
343f6bbf 9101 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9615f239 9102 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
44cd321e 9103 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
4e74d8ec
MM		 9104 && (gpc_reg_operand (operands[0], DImode)
9105 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 9106 "@
3d5570cb
RK		 9107 mr %0,%1
9108 ld%U1%X1 %0,%1
96bb8ed3 9109 std%U0%X0 %1,%0
3d5570cb 9110 li %0,%1
802a0058 9111 lis %0,%v1
e6ca2c17 9112 #
aee86b38 9113 {cal|la} %0,%a1
3d5570cb
RK		 9114 fmr %0,%1
9115 lfd%U1%X1 %0,%1
9116 stfd%U0%X0 %1,%0
9117 mf%1 %0
08075ead 9118 mt%0 %1
e34eaae5 9119 {cror 0,0,0|nop}"
02ca7595 9120 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 9121 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9122
5f59ecb7 9123;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 9124(define_insn ""
9125 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9126 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 9127 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9128 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 9129 && num_insns_constant (operands[1], DImode) == 1"
9130 "*
9131{
9132 return ((unsigned HOST_WIDE_INT)
9133 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9134 ? \"li %0,%1\" : \"lis %0,%v1\";
9135}")
9136
a260abc9
DE		 9137;; Generate all one-bits and clear left or right.
9138;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9139(define_split
9140 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1990cd79 9141 (match_operand:DI 1 "mask64_operand" ""))]
a260abc9
DE		 9142 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9143 [(set (match_dup 0) (const_int -1))
e6ca2c17 9144 (set (match_dup 0)
a260abc9
DE		 9145 (and:DI (rotate:DI (match_dup 0)
9146 (const_int 0))
9147 (match_dup 1)))]
9148 "")
9149
9150;; Split a load of a large constant into the appropriate five-instruction
9151;; sequence. Handle anything in a constant number of insns.
9152;; When non-easy constants can go in the TOC, this should use
9153;; easy_fp_constant predicate.
9154(define_split
9155 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9156 (match_operand:DI 1 "const_int_operand" ""))]
9157 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9158 [(set (match_dup 0) (match_dup 2))
9159 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 9160 "
2bfcf297
DB		 9161{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9162
9163 if (tem == operands[0])
9164 DONE;
e8d791dd 9165 else
2bfcf297 9166 FAIL;
5f59ecb7 9167}")
e6ca2c17 9168
5f59ecb7
DE		 9169(define_split
9170 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9171 (match_operand:DI 1 "const_double_operand" ""))]
9172 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9173 [(set (match_dup 0) (match_dup 2))
9174 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 9175 "
2bfcf297
DB		 9176{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9177
9178 if (tem == operands[0])
9179 DONE;
9180 else
9181 FAIL;
e6ca2c17 9182}")
acad7ed3 9183\f
1fd4e8c1
RK		 9184;; TImode is similar, except that we usually want to compute the address into
9185;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 9186;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 9187
9188;; We say that MQ is clobbered in the last alternative because the first
9189;; alternative would never get used otherwise since it would need a reload
9190;; while the 2nd alternative would not. We put memory cases first so they
9191;; are preferred. Otherwise, we'd try to reload the output instead of
9192;; giving the SCRATCH mq.
3a1f863f 9193
a260abc9 9194(define_insn "*movti_power"
7f514158
AM		 9195 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9196 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9197 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
6ae08853 9198 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 9199 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 9200 "*
9201{
9202 switch (which_alternative)
9203 {
dc4f83ca 9204 default:
37409796 9205 gcc_unreachable ();
dc4f83ca 9206
1fd4e8c1 9207 case 0:
3a1f863f
DE		 9208 if (TARGET_STRING)
9209 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 9210 case 1:
1fd4e8c1 9211 case 2:
3a1f863f 9212 return \"#\";
1fd4e8c1
RK		 9213 case 3:
9214 /* If the address is not used in the output, we can use lsi. Otherwise,
9215 fall through to generating four loads. */
e876481c
DE		 9216 if (TARGET_STRING
9217 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 9218 return \"{lsi|lswi} %0,%P1,16\";
82e41834 9219 /* ... fall through ... */
1fd4e8c1 9220 case 4:
7f514158 9221 case 5:
3a1f863f 9222 return \"#\";
1fd4e8c1
RK		 9223 }
9224}"
7f514158 9225 [(set_attr "type" "store,store,*,load,load,*")])
51b8fc2c 9226
a260abc9 9227(define_insn "*movti_string"
7f514158
AM		 9228 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9229 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
3a1f863f 9230 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 9231 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9232 "*
9233{
9234 switch (which_alternative)
9235 {
9236 default:
37409796 9237 gcc_unreachable ();
dc4f83ca 9238 case 0:
3a1f863f
DE		 9239 if (TARGET_STRING)
9240 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 9241 case 1:
cd1d3445 9242 case 2:
3a1f863f 9243 return \"#\";
cd1d3445
DE		 9244 case 3:
9245 /* If the address is not used in the output, we can use lsi. Otherwise,
9246 fall through to generating four loads. */
6ae08853 9247 if (TARGET_STRING
3a1f863f 9248 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 9249 return \"{lsi|lswi} %0,%P1,16\";
9250 /* ... fall through ... */
9251 case 4:
7f514158 9252 case 5:
3a1f863f 9253 return \"#\";
dc4f83ca
MM		 9254 }
9255}"
c921bad8
AP		 9256 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9257 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9258 (const_string "always")
9259 (const_string "conditional")))])
dc4f83ca 9260
a260abc9 9261(define_insn "*movti_ppc64"
112ccb83
GK		 9262 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9263 (match_operand:TI 1 "input_operand" "r,r,m"))]
51b8fc2c
RK		 9264 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9265 || gpc_reg_operand (operands[1], TImode))"
112ccb83 9266 "#"
0be77bf2 9267 [(set_attr "type" "*,store,load")])
3a1f863f 9268
7f514158
AM		 9269(define_split
9270 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9271 (match_operand:TI 1 "const_double_operand" ""))]
9272 "TARGET_POWERPC64"
9273 [(set (match_dup 2) (match_dup 4))
9274 (set (match_dup 3) (match_dup 5))]
9275 "
9276{
9277 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9278 TImode);
9279 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9280 TImode);
9281 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9282 {
9283 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9284 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9285 }
9286 else if (GET_CODE (operands[1]) == CONST_INT)
9287 {
9288 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9289 operands[5] = operands[1];
9290 }
9291 else
9292 FAIL;
9293}")
9294
3a1f863f
DE		 9295(define_split
9296 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9297 (match_operand:TI 1 "input_operand" ""))]
a9baceb1 9298 "reload_completed
3a1f863f 9299 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 9300 [(pc)]
9301{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
1fd4e8c1
RK		 9302\f
9303(define_expand "load_multiple"
2f622005
RK		 9304 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9305 (match_operand:SI 1 "" ""))
9306 (use (match_operand:SI 2 "" ""))])]
09a625f7 9307 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9308 "
9309{
9310 int regno;
9311 int count;
792760b9 9312 rtx op1;
1fd4e8c1
RK		 9313 int i;
9314
9315 /* Support only loading a constant number of fixed-point registers from
9316 memory and only bother with this if more than two; the machine
9317 doesn't support more than eight. */
9318 if (GET_CODE (operands[2]) != CONST_INT
9319 || INTVAL (operands[2]) <= 2
9320 || INTVAL (operands[2]) > 8
9321 || GET_CODE (operands[1]) != MEM
9322 || GET_CODE (operands[0]) != REG
9323 || REGNO (operands[0]) >= 32)
9324 FAIL;
9325
9326 count = INTVAL (operands[2]);
9327 regno = REGNO (operands[0]);
9328
39403d82 9329 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 9330 op1 = replace_equiv_address (operands[1],
9331 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 9332
9333 for (i = 0; i < count; i++)
9334 XVECEXP (operands[3], 0, i)
39403d82 9335 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 9336 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 9337}")
9338
9caa3eb2 9339(define_insn "*ldmsi8"
1fd4e8c1 9340 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 9341 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9342 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9343 (set (match_operand:SI 3 "gpc_reg_operand" "")
9344 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9345 (set (match_operand:SI 4 "gpc_reg_operand" "")
9346 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9347 (set (match_operand:SI 5 "gpc_reg_operand" "")
9348 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9349 (set (match_operand:SI 6 "gpc_reg_operand" "")
9350 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9351 (set (match_operand:SI 7 "gpc_reg_operand" "")
9352 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9353 (set (match_operand:SI 8 "gpc_reg_operand" "")
9354 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9355 (set (match_operand:SI 9 "gpc_reg_operand" "")
9356 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9357 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 9358 "*
9caa3eb2 9359{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9360 [(set_attr "type" "load_ux")
9caa3eb2 9361 (set_attr "length" "32")])
1fd4e8c1 9362
9caa3eb2
DE		 9363(define_insn "*ldmsi7"
9364 [(match_parallel 0 "load_multiple_operation"
9365 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9366 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9367 (set (match_operand:SI 3 "gpc_reg_operand" "")
9368 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9369 (set (match_operand:SI 4 "gpc_reg_operand" "")
9370 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9371 (set (match_operand:SI 5 "gpc_reg_operand" "")
9372 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9373 (set (match_operand:SI 6 "gpc_reg_operand" "")
9374 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9375 (set (match_operand:SI 7 "gpc_reg_operand" "")
9376 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9377 (set (match_operand:SI 8 "gpc_reg_operand" "")
9378 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9379 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9380 "*
9381{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9382 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9383 (set_attr "length" "32")])
9384
9385(define_insn "*ldmsi6"
9386 [(match_parallel 0 "load_multiple_operation"
9387 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9388 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9389 (set (match_operand:SI 3 "gpc_reg_operand" "")
9390 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9391 (set (match_operand:SI 4 "gpc_reg_operand" "")
9392 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9393 (set (match_operand:SI 5 "gpc_reg_operand" "")
9394 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9395 (set (match_operand:SI 6 "gpc_reg_operand" "")
9396 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9397 (set (match_operand:SI 7 "gpc_reg_operand" "")
9398 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9399 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9400 "*
9401{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9402 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9403 (set_attr "length" "32")])
9404
9405(define_insn "*ldmsi5"
9406 [(match_parallel 0 "load_multiple_operation"
9407 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9408 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9409 (set (match_operand:SI 3 "gpc_reg_operand" "")
9410 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9411 (set (match_operand:SI 4 "gpc_reg_operand" "")
9412 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9413 (set (match_operand:SI 5 "gpc_reg_operand" "")
9414 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9415 (set (match_operand:SI 6 "gpc_reg_operand" "")
9416 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9417 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9418 "*
9419{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9420 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9421 (set_attr "length" "32")])
9422
9423(define_insn "*ldmsi4"
9424 [(match_parallel 0 "load_multiple_operation"
9425 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9426 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9427 (set (match_operand:SI 3 "gpc_reg_operand" "")
9428 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9429 (set (match_operand:SI 4 "gpc_reg_operand" "")
9430 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9431 (set (match_operand:SI 5 "gpc_reg_operand" "")
9432 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9433 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9434 "*
9435{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9436 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9437 (set_attr "length" "32")])
9438
9439(define_insn "*ldmsi3"
9440 [(match_parallel 0 "load_multiple_operation"
9441 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9442 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9443 (set (match_operand:SI 3 "gpc_reg_operand" "")
9444 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9445 (set (match_operand:SI 4 "gpc_reg_operand" "")
9446 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9447 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9448 "*
9449{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9450 [(set_attr "type" "load_ux")
e82ee4cc 9451 (set_attr "length" "32")])
b19003d8 9452
1fd4e8c1 9453(define_expand "store_multiple"
2f622005
RK		 9454 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9455 (match_operand:SI 1 "" ""))
9456 (clobber (scratch:SI))
9457 (use (match_operand:SI 2 "" ""))])]
09a625f7 9458 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9459 "
9460{
9461 int regno;
9462 int count;
9463 rtx to;
792760b9 9464 rtx op0;
1fd4e8c1
RK		 9465 int i;
9466
9467 /* Support only storing a constant number of fixed-point registers to
9468 memory and only bother with this if more than two; the machine
9469 doesn't support more than eight. */
9470 if (GET_CODE (operands[2]) != CONST_INT
9471 || INTVAL (operands[2]) <= 2
9472 || INTVAL (operands[2]) > 8
9473 || GET_CODE (operands[0]) != MEM
9474 || GET_CODE (operands[1]) != REG
9475 || REGNO (operands[1]) >= 32)
9476 FAIL;
9477
9478 count = INTVAL (operands[2]);
9479 regno = REGNO (operands[1]);
9480
39403d82 9481 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 9482 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 9483 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 9484
9485 XVECEXP (operands[3], 0, 0)
7ef788f0 9486 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 9487 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 9488 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 9489
9490 for (i = 1; i < count; i++)
9491 XVECEXP (operands[3], 0, i + 1)
39403d82 9492 = gen_rtx_SET (VOIDmode,
7ef788f0 9493 adjust_address_nv (op0, SImode, i * 4),
c5c76735 9494 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 9495}")
9496
e46e3130 9497(define_insn "*stmsi8"
d14a6d05 9498 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 9499 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9500 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9501 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9502 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9503 (match_operand:SI 4 "gpc_reg_operand" "r"))
9504 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9505 (match_operand:SI 5 "gpc_reg_operand" "r"))
9506 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9507 (match_operand:SI 6 "gpc_reg_operand" "r"))
9508 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9509 (match_operand:SI 7 "gpc_reg_operand" "r"))
9510 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9511 (match_operand:SI 8 "gpc_reg_operand" "r"))
9512 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9513 (match_operand:SI 9 "gpc_reg_operand" "r"))
9514 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9515 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9516 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9517 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9518 [(set_attr "type" "store_ux")
9519 (set_attr "cell_micro" "always")])
e46e3130
DJ		 9520
9521(define_insn "*stmsi7"
9522 [(match_parallel 0 "store_multiple_operation"
9523 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9524 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9525 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9526 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9527 (match_operand:SI 4 "gpc_reg_operand" "r"))
9528 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9529 (match_operand:SI 5 "gpc_reg_operand" "r"))
9530 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9531 (match_operand:SI 6 "gpc_reg_operand" "r"))
9532 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9533 (match_operand:SI 7 "gpc_reg_operand" "r"))
9534 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9535 (match_operand:SI 8 "gpc_reg_operand" "r"))
9536 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9537 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9538 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9539 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9540 [(set_attr "type" "store_ux")
9541 (set_attr "cell_micro" "always")])
e46e3130
DJ		 9542
9543(define_insn "*stmsi6"
9544 [(match_parallel 0 "store_multiple_operation"
9545 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9546 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9547 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9548 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9549 (match_operand:SI 4 "gpc_reg_operand" "r"))
9550 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9551 (match_operand:SI 5 "gpc_reg_operand" "r"))
9552 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9553 (match_operand:SI 6 "gpc_reg_operand" "r"))
9554 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9555 (match_operand:SI 7 "gpc_reg_operand" "r"))
9556 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9557 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9558 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9559 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9560 [(set_attr "type" "store_ux")
9561 (set_attr "cell_micro" "always")])
e46e3130
DJ		 9562
9563(define_insn "*stmsi5"
9564 [(match_parallel 0 "store_multiple_operation"
9565 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9566 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9567 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9568 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9569 (match_operand:SI 4 "gpc_reg_operand" "r"))
9570 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9571 (match_operand:SI 5 "gpc_reg_operand" "r"))
9572 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9573 (match_operand:SI 6 "gpc_reg_operand" "r"))
9574 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9575 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9576 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9577 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9578 [(set_attr "type" "store_ux")
9579 (set_attr "cell_micro" "always")])
e46e3130
DJ		 9580
9581(define_insn "*stmsi4"
9582 [(match_parallel 0 "store_multiple_operation"
9583 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9584 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9585 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9586 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9587 (match_operand:SI 4 "gpc_reg_operand" "r"))
9588 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9589 (match_operand:SI 5 "gpc_reg_operand" "r"))
9590 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9591 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9592 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82 9593 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9594 [(set_attr "type" "store_ux")
9595 (set_attr "cell_micro" "always")])
7e69e155 9596
e46e3130
DJ		 9597(define_insn "*stmsi3"
9598 [(match_parallel 0 "store_multiple_operation"
9599 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9600 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9601 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9602 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9603 (match_operand:SI 4 "gpc_reg_operand" "r"))
9604 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9605 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9606 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9607 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9608 [(set_attr "type" "store_ux")
9609 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9610
9611(define_insn "*stmsi8_power"
9612 [(match_parallel 0 "store_multiple_operation"
9613 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9614 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9615 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9616 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9617 (match_operand:SI 4 "gpc_reg_operand" "r"))
9618 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9619 (match_operand:SI 5 "gpc_reg_operand" "r"))
9620 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9621 (match_operand:SI 6 "gpc_reg_operand" "r"))
9622 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9623 (match_operand:SI 7 "gpc_reg_operand" "r"))
9624 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9625 (match_operand:SI 8 "gpc_reg_operand" "r"))
9626 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9627 (match_operand:SI 9 "gpc_reg_operand" "r"))
9628 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9629 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9630 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9631 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9632 [(set_attr "type" "store_ux")
9633 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9634
9635(define_insn "*stmsi7_power"
9636 [(match_parallel 0 "store_multiple_operation"
9637 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9638 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9639 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9640 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9641 (match_operand:SI 4 "gpc_reg_operand" "r"))
9642 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9643 (match_operand:SI 5 "gpc_reg_operand" "r"))
9644 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9645 (match_operand:SI 6 "gpc_reg_operand" "r"))
9646 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9647 (match_operand:SI 7 "gpc_reg_operand" "r"))
9648 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9649 (match_operand:SI 8 "gpc_reg_operand" "r"))
9650 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9651 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9652 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9653 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9654 [(set_attr "type" "store_ux")
9655 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9656
9657(define_insn "*stmsi6_power"
9658 [(match_parallel 0 "store_multiple_operation"
9659 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9660 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9661 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9662 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9663 (match_operand:SI 4 "gpc_reg_operand" "r"))
9664 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9665 (match_operand:SI 5 "gpc_reg_operand" "r"))
9666 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9667 (match_operand:SI 6 "gpc_reg_operand" "r"))
9668 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9669 (match_operand:SI 7 "gpc_reg_operand" "r"))
9670 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9671 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9672 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9673 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9674 [(set_attr "type" "store_ux")
9675 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9676
9677(define_insn "*stmsi5_power"
9678 [(match_parallel 0 "store_multiple_operation"
9679 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9680 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9681 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9682 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9683 (match_operand:SI 4 "gpc_reg_operand" "r"))
9684 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9685 (match_operand:SI 5 "gpc_reg_operand" "r"))
9686 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9687 (match_operand:SI 6 "gpc_reg_operand" "r"))
9688 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9689 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9690 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9691 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9692 [(set_attr "type" "store_ux")
9693 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9694
9695(define_insn "*stmsi4_power"
9696 [(match_parallel 0 "store_multiple_operation"
9697 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9698 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9699 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9700 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9701 (match_operand:SI 4 "gpc_reg_operand" "r"))
9702 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9703 (match_operand:SI 5 "gpc_reg_operand" "r"))
9704 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9705 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9706 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9707 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9708 [(set_attr "type" "store_ux")
9709 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9710
9711(define_insn "*stmsi3_power"
9712 [(match_parallel 0 "store_multiple_operation"
9713 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9714 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9715 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9716 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9717 (match_operand:SI 4 "gpc_reg_operand" "r"))
9718 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9719 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9720 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9721 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9722 [(set_attr "type" "store_ux")
9723 (set_attr "cell_micro" "always")])
7e69e155 9724\f
57e84f18 9725(define_expand "setmemsi"
fba73eb1 9726 [(parallel [(set (match_operand:BLK 0 "" "")
98843c92 9727 (match_operand 2 "const_int_operand" ""))
fba73eb1 9728 (use (match_operand:SI 1 "" ""))
57e84f18 9729 (use (match_operand:SI 3 "" ""))])]
fba73eb1
DE		 9730 ""
9731 "
9732{
57e84f18 9733 /* If value to set is not zero, use the library routine. */
a05be2e0 9734 if (operands[2] != const0_rtx)
57e84f18
AS		 9735 FAIL;
9736
fba73eb1
DE		 9737 if (expand_block_clear (operands))
9738 DONE;
9739 else
9740 FAIL;
9741}")
9742
7e69e155
MM		 9743;; String/block move insn.
9744;; Argument 0 is the destination
9745;; Argument 1 is the source
9746;; Argument 2 is the length
9747;; Argument 3 is the alignment
9748
70128ad9 9749(define_expand "movmemsi"
b6c9286a
MM		 9750 [(parallel [(set (match_operand:BLK 0 "" "")
9751 (match_operand:BLK 1 "" ""))
9752 (use (match_operand:SI 2 "" ""))
9753 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9754 ""
9755 "
9756{
9757 if (expand_block_move (operands))
9758 DONE;
9759 else
9760 FAIL;
9761}")
9762
9763;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9764;; register allocator doesn't have a clue about allocating 8 word registers.
9765;; rD/rS = r5 is preferred, efficient form.
70128ad9 9766(define_expand "movmemsi_8reg"
b6c9286a
MM		 9767 [(parallel [(set (match_operand 0 "" "")
9768 (match_operand 1 "" ""))
9769 (use (match_operand 2 "" ""))
9770 (use (match_operand 3 "" ""))
7e69e155
MM		 9771 (clobber (reg:SI 5))
9772 (clobber (reg:SI 6))
9773 (clobber (reg:SI 7))
9774 (clobber (reg:SI 8))
9775 (clobber (reg:SI 9))
9776 (clobber (reg:SI 10))
9777 (clobber (reg:SI 11))
9778 (clobber (reg:SI 12))
3c67b673 9779 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9780 "TARGET_STRING"
9781 "")
9782
9783(define_insn ""
52d3af72
DE		 9784 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9785 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9786 (use (match_operand:SI 2 "immediate_operand" "i"))
9787 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9788 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
7e69e155
MM		 9789 (clobber (reg:SI 6))
9790 (clobber (reg:SI 7))
9791 (clobber (reg:SI 8))
9792 (clobber (reg:SI 9))
9793 (clobber (reg:SI 10))
9794 (clobber (reg:SI 11))
9795 (clobber (reg:SI 12))
3c67b673 9796 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9797 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9798 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9799 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9800 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9801 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9802 && REGNO (operands[4]) == 5"
9803 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9804 [(set_attr "type" "store_ux")
c921bad8 9805 (set_attr "cell_micro" "always")
b7ff3d82 9806 (set_attr "length" "8")])
7e69e155
MM		 9807
9808(define_insn ""
4ae234b0
GK		 9809 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9810 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9811 (use (match_operand:SI 2 "immediate_operand" "i"))
9812 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9813 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
7e69e155
MM		 9814 (clobber (reg:SI 6))
9815 (clobber (reg:SI 7))
9816 (clobber (reg:SI 8))
9817 (clobber (reg:SI 9))
9818 (clobber (reg:SI 10))
9819 (clobber (reg:SI 11))
9820 (clobber (reg:SI 12))
edd54d25 9821 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9822 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9823 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9824 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9825 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9826 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9827 && REGNO (operands[4]) == 5"
9828 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9829 [(set_attr "type" "store_ux")
c921bad8 9830 (set_attr "cell_micro" "always")
b7ff3d82 9831 (set_attr "length" "8")])
7e69e155
MM		 9832
9833;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9834;; register allocator doesn't have a clue about allocating 6 word registers.
9835;; rD/rS = r5 is preferred, efficient form.
70128ad9 9836(define_expand "movmemsi_6reg"
b6c9286a
MM		 9837 [(parallel [(set (match_operand 0 "" "")
9838 (match_operand 1 "" ""))
9839 (use (match_operand 2 "" ""))
9840 (use (match_operand 3 "" ""))
f9562f27
DE		 9841 (clobber (reg:SI 5))
9842 (clobber (reg:SI 6))
7e69e155
MM		 9843 (clobber (reg:SI 7))
9844 (clobber (reg:SI 8))
9845 (clobber (reg:SI 9))
9846 (clobber (reg:SI 10))
3c67b673 9847 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9848 "TARGET_STRING"
9849 "")
9850
9851(define_insn ""
52d3af72
DE		 9852 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9853 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9854 (use (match_operand:SI 2 "immediate_operand" "i"))
9855 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9856 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 9857 (clobber (reg:SI 6))
9858 (clobber (reg:SI 7))
7e69e155
MM		 9859 (clobber (reg:SI 8))
9860 (clobber (reg:SI 9))
9861 (clobber (reg:SI 10))
3c67b673 9862 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9863 "TARGET_STRING && TARGET_POWER
9864 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9865 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9866 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9867 && REGNO (operands[4]) == 5"
3c67b673 9868 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9869 [(set_attr "type" "store_ux")
c921bad8 9870 (set_attr "cell_micro" "always")
b7ff3d82 9871 (set_attr "length" "8")])
7e69e155
MM		 9872
9873(define_insn ""
4ae234b0
GK		 9874 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9875 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9876 (use (match_operand:SI 2 "immediate_operand" "i"))
9877 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9878 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 9879 (clobber (reg:SI 6))
9880 (clobber (reg:SI 7))
7e69e155
MM		 9881 (clobber (reg:SI 8))
9882 (clobber (reg:SI 9))
9883 (clobber (reg:SI 10))
edd54d25 9884 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9885 "TARGET_STRING && ! TARGET_POWER
7e69e155 9886 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9887 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9888 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9889 && REGNO (operands[4]) == 5"
3c67b673 9890 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9891 [(set_attr "type" "store_ux")
c921bad8 9892 (set_attr "cell_micro" "always")
b7ff3d82 9893 (set_attr "length" "8")])
7e69e155 9894
f9562f27
DE		 9895;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9896;; problems with TImode.
9897;; rD/rS = r5 is preferred, efficient form.
70128ad9 9898(define_expand "movmemsi_4reg"
b6c9286a
MM		 9899 [(parallel [(set (match_operand 0 "" "")
9900 (match_operand 1 "" ""))
9901 (use (match_operand 2 "" ""))
9902 (use (match_operand 3 "" ""))
f9562f27
DE		 9903 (clobber (reg:SI 5))
9904 (clobber (reg:SI 6))
9905 (clobber (reg:SI 7))
9906 (clobber (reg:SI 8))
3c67b673 9907 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9908 "TARGET_STRING"
9909 "")
9910
9911(define_insn ""
52d3af72
DE		 9912 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9913 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9914 (use (match_operand:SI 2 "immediate_operand" "i"))
9915 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9916 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 9917 (clobber (reg:SI 6))
9918 (clobber (reg:SI 7))
9919 (clobber (reg:SI 8))
3c67b673 9920 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9921 "TARGET_STRING && TARGET_POWER
9922 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9923 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9924 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9925 && REGNO (operands[4]) == 5"
3c67b673 9926 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9927 [(set_attr "type" "store_ux")
c921bad8 9928 (set_attr "cell_micro" "always")
b7ff3d82 9929 (set_attr "length" "8")])
7e69e155
MM		 9930
9931(define_insn ""
4ae234b0
GK		 9932 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9933 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9934 (use (match_operand:SI 2 "immediate_operand" "i"))
9935 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9936 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 9937 (clobber (reg:SI 6))
9938 (clobber (reg:SI 7))
9939 (clobber (reg:SI 8))
edd54d25 9940 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9941 "TARGET_STRING && ! TARGET_POWER
7e69e155 9942 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9943 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9944 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9945 && REGNO (operands[4]) == 5"
3c67b673 9946 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9947 [(set_attr "type" "store_ux")
c921bad8 9948 (set_attr "cell_micro" "always")
b7ff3d82 9949 (set_attr "length" "8")])
7e69e155
MM		 9950
9951;; Move up to 8 bytes at a time.
70128ad9 9952(define_expand "movmemsi_2reg"
b6c9286a
MM		 9953 [(parallel [(set (match_operand 0 "" "")
9954 (match_operand 1 "" ""))
9955 (use (match_operand 2 "" ""))
9956 (use (match_operand 3 "" ""))
3c67b673
RK		 9957 (clobber (match_scratch:DI 4 ""))
9958 (clobber (match_scratch:SI 5 ""))])]
f9562f27 9959 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 9960 "")
9961
9962(define_insn ""
52d3af72
DE		 9963 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9964 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9965 (use (match_operand:SI 2 "immediate_operand" "i"))
9966 (use (match_operand:SI 3 "immediate_operand" "i"))
9967 (clobber (match_scratch:DI 4 "=&r"))
9968 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 9969 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 9970 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9971 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9972 [(set_attr "type" "store_ux")
c921bad8 9973 (set_attr "cell_micro" "always")
b7ff3d82 9974 (set_attr "length" "8")])
7e69e155
MM		 9975
9976(define_insn ""
52d3af72
DE		 9977 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9978 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9979 (use (match_operand:SI 2 "immediate_operand" "i"))
9980 (use (match_operand:SI 3 "immediate_operand" "i"))
9981 (clobber (match_scratch:DI 4 "=&r"))
edd54d25 9982 (clobber (match_scratch:SI 5 "=X"))]
f9562f27 9983 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 9984 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 9985 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9986 [(set_attr "type" "store_ux")
c921bad8 9987 (set_attr "cell_micro" "always")
b7ff3d82 9988 (set_attr "length" "8")])
7e69e155
MM		 9989
9990;; Move up to 4 bytes at a time.
70128ad9 9991(define_expand "movmemsi_1reg"
b6c9286a
MM		 9992 [(parallel [(set (match_operand 0 "" "")
9993 (match_operand 1 "" ""))
9994 (use (match_operand 2 "" ""))
9995 (use (match_operand 3 "" ""))
3c67b673
RK		 9996 (clobber (match_scratch:SI 4 ""))
9997 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 9998 "TARGET_STRING"
9999 "")
10000
10001(define_insn ""
52d3af72
DE		 10002 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10003 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 10004 (use (match_operand:SI 2 "immediate_operand" "i"))
10005 (use (match_operand:SI 3 "immediate_operand" "i"))
10006 (clobber (match_scratch:SI 4 "=&r"))
10007 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 10008 "TARGET_STRING && TARGET_POWER
10009 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 10010 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 10011 [(set_attr "type" "store_ux")
c921bad8 10012 (set_attr "cell_micro" "always")
b7ff3d82 10013 (set_attr "length" "8")])
7e69e155
MM		 10014
10015(define_insn ""
4ae234b0
GK		 10016 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10017 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 10018 (use (match_operand:SI 2 "immediate_operand" "i"))
10019 (use (match_operand:SI 3 "immediate_operand" "i"))
10020 (clobber (match_scratch:SI 4 "=&r"))
edd54d25 10021 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 10022 "TARGET_STRING && ! TARGET_POWER
7e69e155 10023 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7 10024 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 10025 [(set_attr "type" "store_ux")
c921bad8 10026 (set_attr "cell_micro" "always")
09a625f7 10027 (set_attr "length" "8")])
1fd4e8c1 10028\f
7e69e155 10029;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 10030;; get by using pre-decrement or pre-increment, but the hardware can also
10031;; do cases where the increment is not the size of the object.
10032;;
10033;; In all these cases, we use operands 0 and 1 for the register being
10034;; incremented because those are the operands that local-alloc will
10035;; tie and these are the pair most likely to be tieable (and the ones
10036;; that will benefit the most).
10037
38c1f2d7 10038(define_insn "*movdi_update1"
51b8fc2c 10039 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 10040 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 10041 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 10042 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10043 (plus:DI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10044 "TARGET_POWERPC64 && TARGET_UPDATE
10045 && (!avoiding_indexed_address_p (DImode)
10046 || !gpc_reg_operand (operands[2], DImode))"
51b8fc2c
RK		 10047 "@
10048 ldux %3,%0,%2
10049 ldu %3,%2(%0)"
b54cf83a 10050 [(set_attr "type" "load_ux,load_u")])
287f13ff 10051
2e6c9641
FJ		 10052(define_insn "movdi_<mode>_update"
10053 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10054 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c 10055 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
2e6c9641
FJ		 10056 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10057 (plus:P (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10058 "TARGET_POWERPC64 && TARGET_UPDATE
10059 && (!avoiding_indexed_address_p (Pmode)
10060 || !gpc_reg_operand (operands[2], Pmode)
10061 || (REG_P (operands[0])
10062 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
51b8fc2c
RK		 10063 "@
10064 stdux %3,%0,%2
b7ff3d82 10065 stdu %3,%2(%0)"
b54cf83a 10066 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 10067
d4bacef0
BE		 10068;; This pattern is only conditional on TARGET_POWERPC64, as it is
10069;; needed for stack allocation, even if the user passes -mno-update.
10070(define_insn "movdi_<mode>_update_stack"
10071 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10072 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10073 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10074 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10075 (plus:P (match_dup 1) (match_dup 2)))]
10076 "TARGET_POWERPC64"
10077 "@
10078 stdux %3,%0,%2
10079 stdu %3,%2(%0)"
10080 [(set_attr "type" "store_ux,store_u")])
10081
38c1f2d7 10082(define_insn "*movsi_update1"
cd2b37d9
RK		 10083 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10084 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10085 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10086 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10087 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10088 "TARGET_UPDATE
10089 && (!avoiding_indexed_address_p (SImode)
10090 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10091 "@
ca7f5001
RK		 10092 {lux|lwzux} %3,%0,%2
10093 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 10094 [(set_attr "type" "load_ux,load_u")])
10095
10096(define_insn "*movsi_update2"
10097 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10098 (sign_extend:DI
10099 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10100 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10101 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10102 (plus:DI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10103 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10104 && !avoiding_indexed_address_p (DImode)"
b54cf83a
DE		 10105 "lwaux %3,%0,%2"
10106 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 10107
4697a36c 10108(define_insn "movsi_update"
cd2b37d9 10109 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10110 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10111 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10112 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10113 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10114 "TARGET_UPDATE
10115 && (!avoiding_indexed_address_p (SImode)
10116 || !gpc_reg_operand (operands[2], SImode)
10117 || (REG_P (operands[0])
10118 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
1fd4e8c1 10119 "@
ca7f5001 10120 {stux|stwux} %3,%0,%2
b7ff3d82 10121 {stu|stwu} %3,%2(%0)"
b54cf83a 10122 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10123
d4bacef0
BE		 10124;; This is an unconditional pattern; needed for stack allocation, even
10125;; if the user passes -mno-update.
10126(define_insn "movsi_update_stack"
10127 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10128 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10129 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10130 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10131 (plus:SI (match_dup 1) (match_dup 2)))]
10132 ""
10133 "@
10134 {stux|stwux} %3,%0,%2
10135 {stu|stwu} %3,%2(%0)"
10136 [(set_attr "type" "store_ux,store_u")])
10137
b54cf83a 10138(define_insn "*movhi_update1"
cd2b37d9
RK		 10139 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10140 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10141 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10142 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10143 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10144 "TARGET_UPDATE
10145 && (!avoiding_indexed_address_p (SImode)
10146 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10147 "@
5f243543
RK		 10148 lhzux %3,%0,%2
10149 lhzu %3,%2(%0)"
b54cf83a 10150 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10151
38c1f2d7 10152(define_insn "*movhi_update2"
cd2b37d9 10153 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10154 (zero_extend:SI
cd2b37d9 10155 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10156 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10157 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10158 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10159 "TARGET_UPDATE
10160 && (!avoiding_indexed_address_p (SImode)
10161 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10162 "@
5f243543
RK		 10163 lhzux %3,%0,%2
10164 lhzu %3,%2(%0)"
b54cf83a 10165 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10166
38c1f2d7 10167(define_insn "*movhi_update3"
cd2b37d9 10168 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10169 (sign_extend:SI
cd2b37d9 10170 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10171 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10172 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10173 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10174 "TARGET_UPDATE && rs6000_gen_cell_microcode
10175 && (!avoiding_indexed_address_p (SImode)
10176 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10177 "@
5f243543
RK		 10178 lhaux %3,%0,%2
10179 lhau %3,%2(%0)"
b54cf83a 10180 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 10181
38c1f2d7 10182(define_insn "*movhi_update4"
cd2b37d9 10183 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10184 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10185 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10186 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10187 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10188 "TARGET_UPDATE
10189 && (!avoiding_indexed_address_p (SImode)
10190 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10191 "@
5f243543 10192 sthux %3,%0,%2
b7ff3d82 10193 sthu %3,%2(%0)"
b54cf83a 10194 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10195
38c1f2d7 10196(define_insn "*movqi_update1"
cd2b37d9
RK		 10197 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10198 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10199 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10200 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10201 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10202 "TARGET_UPDATE
10203 && (!avoiding_indexed_address_p (SImode)
10204 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10205 "@
5f243543
RK		 10206 lbzux %3,%0,%2
10207 lbzu %3,%2(%0)"
b54cf83a 10208 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10209
38c1f2d7 10210(define_insn "*movqi_update2"
cd2b37d9 10211 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10212 (zero_extend:SI
cd2b37d9 10213 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10214 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10215 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10216 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10217 "TARGET_UPDATE
10218 && (!avoiding_indexed_address_p (SImode)
10219 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10220 "@
5f243543
RK		 10221 lbzux %3,%0,%2
10222 lbzu %3,%2(%0)"
b54cf83a 10223 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10224
38c1f2d7 10225(define_insn "*movqi_update3"
cd2b37d9 10226 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10227 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10228 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10229 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10230 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10231 "TARGET_UPDATE
10232 && (!avoiding_indexed_address_p (SImode)
10233 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10234 "@
5f243543 10235 stbux %3,%0,%2
b7ff3d82 10236 stbu %3,%2(%0)"
b54cf83a 10237 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10238
38c1f2d7 10239(define_insn "*movsf_update1"
cd2b37d9 10240 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 10241 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10242 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10243 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10244 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10245 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10246 && (!avoiding_indexed_address_p (SImode)
10247 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10248 "@
5f243543
RK		 10249 lfsux %3,%0,%2
10250 lfsu %3,%2(%0)"
b54cf83a 10251 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10252
38c1f2d7 10253(define_insn "*movsf_update2"
cd2b37d9 10254 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10255 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10256 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10257 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10258 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10259 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10260 && (!avoiding_indexed_address_p (SImode)
10261 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10262 "@
85fff2f3 10263 stfsux %3,%0,%2
b7ff3d82 10264 stfsu %3,%2(%0)"
b54cf83a 10265 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 10266
38c1f2d7
MM		 10267(define_insn "*movsf_update3"
10268 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10269 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10270 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10271 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10272 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10273 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10274 && (!avoiding_indexed_address_p (SImode)
10275 || !gpc_reg_operand (operands[2], SImode))"
38c1f2d7
MM		 10276 "@
10277 {lux|lwzux} %3,%0,%2
10278 {lu|lwzu} %3,%2(%0)"
b54cf83a 10279 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 10280
10281(define_insn "*movsf_update4"
10282 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10283 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10284 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10285 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10286 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10287 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10288 && (!avoiding_indexed_address_p (SImode)
10289 || !gpc_reg_operand (operands[2], SImode))"
38c1f2d7
MM		 10290 "@
10291 {stux|stwux} %3,%0,%2
10292 {stu|stwu} %3,%2(%0)"
b54cf83a 10293 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 10294
10295(define_insn "*movdf_update1"
cd2b37d9
RK		 10296 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10297 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10298 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10299 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10300 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10301 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10302 && (!avoiding_indexed_address_p (SImode)
10303 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10304 "@
5f243543
RK		 10305 lfdux %3,%0,%2
10306 lfdu %3,%2(%0)"
b54cf83a 10307 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10308
38c1f2d7 10309(define_insn "*movdf_update2"
cd2b37d9 10310 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10311 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10312 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10313 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10314 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10315 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10316 && (!avoiding_indexed_address_p (SImode)
10317 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10318 "@
5f243543 10319 stfdux %3,%0,%2
b7ff3d82 10320 stfdu %3,%2(%0)"
b54cf83a 10321 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 10322
10323;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10324
90f81f99 10325(define_insn "*lfq_power2"
bb8df8a6
EC		 10326 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10327 (match_operand:V2DF 1 "memory_operand" ""))]
90f81f99
AP		 10328 "TARGET_POWER2
10329 && TARGET_HARD_FLOAT && TARGET_FPRS"
bb8df8a6 10330 "lfq%U1%X1 %0,%1")
90f81f99
AP		 10331
10332(define_peephole2
10333 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4c70a4f3 10334 (match_operand:DF 1 "memory_operand" ""))
90f81f99 10335 (set (match_operand:DF 2 "gpc_reg_operand" "")
4c70a4f3
RK		 10336 (match_operand:DF 3 "memory_operand" ""))]
10337 "TARGET_POWER2
696e45ba 10338 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4c70a4f3 10339 && registers_ok_for_quad_peep (operands[0], operands[2])
90f81f99
AP		 10340 && mems_ok_for_quad_peep (operands[1], operands[3])"
10341 [(set (match_dup 0)
bb8df8a6
EC		 10342 (match_dup 1))]
10343 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10344 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
4c70a4f3 10345
90f81f99 10346(define_insn "*stfq_power2"
bb8df8a6
EC		 10347 [(set (match_operand:V2DF 0 "memory_operand" "")
10348 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
90f81f99
AP		 10349 "TARGET_POWER2
10350 && TARGET_HARD_FLOAT && TARGET_FPRS"
10351 "stfq%U0%X0 %1,%0")
10352
10353
10354(define_peephole2
4c70a4f3 10355 [(set (match_operand:DF 0 "memory_operand" "")
90f81f99 10356 (match_operand:DF 1 "gpc_reg_operand" ""))
4c70a4f3 10357 (set (match_operand:DF 2 "memory_operand" "")
90f81f99 10358 (match_operand:DF 3 "gpc_reg_operand" ""))]
4c70a4f3 10359 "TARGET_POWER2
696e45ba 10360 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4c70a4f3 10361 && registers_ok_for_quad_peep (operands[1], operands[3])
90f81f99
AP		 10362 && mems_ok_for_quad_peep (operands[0], operands[2])"
10363 [(set (match_dup 0)
10364 (match_dup 1))]
bb8df8a6
EC		 10365 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10366 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
2f4d9502 10367
036aadfc 10368;; After inserting conditional returns we can sometimes have
2f4d9502
NS		 10369;; unnecessary register moves. Unfortunately we cannot have a
10370;; modeless peephole here, because some single SImode sets have early
10371;; clobber outputs. Although those sets expand to multi-ppc-insn
10372;; sequences, using get_attr_length here will smash the operands
10373;; array. Neither is there an early_cobbler_p predicate.
036aadfc 10374;; Disallow subregs for E500 so we don't munge frob_di_df_2.
2f4d9502
NS		 10375(define_peephole2
10376 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10377 (match_operand:DF 1 "any_operand" ""))
10378 (set (match_operand:DF 2 "gpc_reg_operand" "")
10379 (match_dup 0))]
036aadfc
AM		 10380 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10381 && peep2_reg_dead_p (2, operands[0])"
2f4d9502
NS		 10382 [(set (match_dup 2) (match_dup 1))])
10383
10384(define_peephole2
10385 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10386 (match_operand:SF 1 "any_operand" ""))
10387 (set (match_operand:SF 2 "gpc_reg_operand" "")
10388 (match_dup 0))]
10389 "peep2_reg_dead_p (2, operands[0])"
10390 [(set (match_dup 2) (match_dup 1))])
10391
1fd4e8c1 10392\f
c4501e62
JJ		 10393;; TLS support.
10394
02135bc1
SB		 10395;; Mode attributes for different ABIs.
10396(define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10397(define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10398(define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10399(define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10400
9752c4ad 10401(define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
02135bc1
SB		 10402 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10403 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10404 (match_operand 4 "" "g")))
10405 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10406 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10407 UNSPEC_TLSGD)
10408 (clobber (reg:SI LR_REGNO))]
10409 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10410 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
9752c4ad
AM		 10411 "&& TARGET_TLS_MARKERS"
10412 [(set (match_dup 0)
10413 (unspec:TLSmode [(match_dup 1)
10414 (match_dup 2)]
10415 UNSPEC_TLSGD))
10416 (parallel [(set (match_dup 0)
10417 (call (mem:TLSmode (match_dup 3))
10418 (match_dup 4)))
10419 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10420 (clobber (reg:SI LR_REGNO))])]
10421 ""
02135bc1
SB		 10422 [(set_attr "type" "two")
10423 (set_attr "length" "12")])
10424
9752c4ad 10425(define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
02135bc1
SB		 10426 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10427 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10428 (match_operand 4 "" "g")))
10429 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10430 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10431 UNSPEC_TLSGD)
10432 (clobber (reg:SI LR_REGNO))]
10433 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10434{
10435 if (flag_pic)
10436 {
10437 if (TARGET_SECURE_PLT && flag_pic == 2)
10438 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10439 else
10440 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10441 }
10442 else
10443 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10444}
9752c4ad
AM		 10445 "&& TARGET_TLS_MARKERS"
10446 [(set (match_dup 0)
10447 (unspec:TLSmode [(match_dup 1)
10448 (match_dup 2)]
10449 UNSPEC_TLSGD))
10450 (parallel [(set (match_dup 0)
10451 (call (mem:TLSmode (match_dup 3))
10452 (match_dup 4)))
10453 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10454 (clobber (reg:SI LR_REGNO))])]
10455 ""
02135bc1
SB		 10456 [(set_attr "type" "two")
10457 (set_attr "length" "8")])
c4501e62 10458
9752c4ad
AM		 10459(define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
10460 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10461 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10462 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10463 UNSPEC_TLSGD))]
10464 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10465 "addi %0,%1,%2@got@tlsgd"
10466 [(set_attr "length" "4")])
10467
10468(define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10469 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10470 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10471 (match_operand 2 "" "g")))
10472 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10473 UNSPEC_TLSGD)
10474 (clobber (reg:SI LR_REGNO))]
10475 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10476 "bl %z1(%3@tlsgd)\;%."
10477 [(set_attr "type" "branch")
10478 (set_attr "length" "8")])
10479
10480(define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10481 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10482 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10483 (match_operand 2 "" "g")))
10484 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10485 UNSPEC_TLSGD)
10486 (clobber (reg:SI LR_REGNO))]
10487 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10488{
10489 if (flag_pic)
10490 {
10491 if (TARGET_SECURE_PLT && flag_pic == 2)
10492 return "bl %z1+32768(%3@tlsgd)@plt";
10493 return "bl %z1(%3@tlsgd)@plt";
10494 }
10495 return "bl %z1(%3@tlsgd)";
10496}
10497 [(set_attr "type" "branch")
10498 (set_attr "length" "4")])
10499
10500(define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
02135bc1
SB		 10501 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10502 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10503 (match_operand 3 "" "g")))
10504 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10505 UNSPEC_TLSLD)
10506 (clobber (reg:SI LR_REGNO))]
10507 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10508 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
9752c4ad
AM		 10509 "&& TARGET_TLS_MARKERS"
10510 [(set (match_dup 0)
10511 (unspec:TLSmode [(match_dup 1)]
10512 UNSPEC_TLSLD))
10513 (parallel [(set (match_dup 0)
10514 (call (mem:TLSmode (match_dup 2))
10515 (match_dup 3)))
10516 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10517 (clobber (reg:SI LR_REGNO))])]
10518 ""
02135bc1 10519 [(set_attr "length" "12")])
c4501e62 10520
9752c4ad 10521(define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
02135bc1
SB		 10522 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10523 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10524 (match_operand 3 "" "g")))
10525 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10526 UNSPEC_TLSLD)
10527 (clobber (reg:SI LR_REGNO))]
10528 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10529{
10530 if (flag_pic)
10531 {
10532 if (TARGET_SECURE_PLT && flag_pic == 2)
10533 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10534 else
10535 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10536 }
10537 else
10538 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10539}
9752c4ad
AM		 10540 "&& TARGET_TLS_MARKERS"
10541 [(set (match_dup 0)
10542 (unspec:TLSmode [(match_dup 1)]
10543 UNSPEC_TLSLD))
10544 (parallel [(set (match_dup 0)
10545 (call (mem:TLSmode (match_dup 2))
10546 (match_dup 3)))
10547 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10548 (clobber (reg:SI LR_REGNO))])]
10549 ""
02135bc1 10550 [(set_attr "length" "8")])
c4501e62 10551
9752c4ad
AM		 10552(define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
10553 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10554 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10555 UNSPEC_TLSLD))]
10556 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10557 "addi %0,%1,%&@got@tlsld"
10558 [(set_attr "length" "4")])
10559
10560(define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10561 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10562 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10563 (match_operand 2 "" "g")))
10564 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10565 (clobber (reg:SI LR_REGNO))]
10566 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10567 "bl %z1(%&@tlsld)\;%."
10568 [(set_attr "type" "branch")
10569 (set_attr "length" "8")])
10570
10571(define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10572 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10573 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10574 (match_operand 2 "" "g")))
10575 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10576 (clobber (reg:SI LR_REGNO))]
10577 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10578{
10579 if (flag_pic)
10580 {
10581 if (TARGET_SECURE_PLT && flag_pic == 2)
10582 return "bl %z1+32768(%&@tlsld)@plt";
10583 return "bl %z1(%&@tlsld)@plt";
10584 }
10585 return "bl %z1(%&@tlsld)";
10586}
10587 [(set_attr "type" "branch")
10588 (set_attr "length" "4")])
10589
02135bc1
SB		 10590(define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10591 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10592 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10593 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10594 UNSPEC_TLSDTPREL))]
10595 "HAVE_AS_TLS"
10596 "addi %0,%1,%2@dtprel")
c4501e62 10597
02135bc1
SB		 10598(define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10599 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10600 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10601 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10602 UNSPEC_TLSDTPRELHA))]
10603 "HAVE_AS_TLS"
10604 "addis %0,%1,%2@dtprel@ha")
c4501e62 10605
02135bc1
SB		 10606(define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10607 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10608 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10609 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10610 UNSPEC_TLSDTPRELLO))]
10611 "HAVE_AS_TLS"
c4501e62
JJ		 10612 "addi %0,%1,%2@dtprel@l")
10613
02135bc1
SB		 10614(define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10615 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10616 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10617 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10618 UNSPEC_TLSGOTDTPREL))]
10619 "HAVE_AS_TLS"
10620 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10621
10622(define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10623 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10624 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10625 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10626 UNSPEC_TLSTPREL))]
10627 "HAVE_AS_TLS"
c4501e62
JJ		 10628 "addi %0,%1,%2@tprel")
10629
02135bc1
SB		 10630(define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10631 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10632 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10633 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10634 UNSPEC_TLSTPRELHA))]
10635 "HAVE_AS_TLS"
c4501e62
JJ		 10636 "addis %0,%1,%2@tprel@ha")
10637
02135bc1
SB		 10638(define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10639 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10640 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10641 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10642 UNSPEC_TLSTPRELLO))]
10643 "HAVE_AS_TLS"
c4501e62
JJ		 10644 "addi %0,%1,%2@tprel@l")
10645
c1207243 10646;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 10647;; optimization. The linker may edit the instructions emitted by a
10648;; tls_got_tprel/tls_tls pair to addis,addi.
02135bc1
SB		 10649(define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10650 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10651 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10652 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10653 UNSPEC_TLSGOTTPREL))]
10654 "HAVE_AS_TLS"
10655 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10656
10657(define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10658 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10659 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10660 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10661 UNSPEC_TLSTLS))]
10662 "HAVE_AS_TLS"
c4501e62
JJ		 10663 "add %0,%1,%2@tls")
10664
c4501e62 10665\f
1fd4e8c1
RK		 10666;; Next come insns related to the calling sequence.
10667;;
10668;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 10669;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 10670
10671(define_expand "allocate_stack"
e42ac3de 10672 [(set (match_operand 0 "gpc_reg_operand" "")
a260abc9
DE		 10673 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10674 (set (reg 1)
10675 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 10676 ""
10677 "
4697a36c 10678{ rtx chain = gen_reg_rtx (Pmode);
39403d82 10679 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 10680 rtx neg_op0;
d4bacef0 10681 rtx insn, par, set, mem;
1fd4e8c1
RK		 10682
10683 emit_move_insn (chain, stack_bot);
4697a36c 10684
a157febd 10685 /* Check stack bounds if necessary. */
e3b5732b 10686 if (crtl->limit_stack)
a157febd
GK		 10687 {
10688 rtx available;
6ae08853 10689 available = expand_binop (Pmode, sub_optab,
a157febd
GK		 10690 stack_pointer_rtx, stack_limit_rtx,
10691 NULL_RTX, 1, OPTAB_WIDEN);
10692 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10693 }
10694
e9a25f70
JL		 10695 if (GET_CODE (operands[1]) != CONST_INT
10696 || INTVAL (operands[1]) < -32767
10697 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 10698 {
10699 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 10700 if (TARGET_32BIT)
e9a25f70 10701 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 10702 else
e9a25f70 10703 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 10704 }
10705 else
e9a25f70 10706 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 10707
a2a237b5
BE		 10708 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10709 : gen_movdi_di_update_stack))
16044a80
PH		 10710 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10711 chain));
d4bacef0
BE		 10712 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10713 it now and set the alias set/attributes. The above gen_*_update
10714 calls will generate a PARALLEL with the MEM set being the first
10715 operation. */
10716 par = PATTERN (insn);
10717 gcc_assert (GET_CODE (par) == PARALLEL);
10718 set = XVECEXP (par, 0, 0);
10719 gcc_assert (GET_CODE (set) == SET);
10720 mem = SET_DEST (set);
10721 gcc_assert (MEM_P (mem));
10722 MEM_NOTRAP_P (mem) = 1;
10723 set_mem_alias_set (mem, get_frame_alias_set ());
e9a25f70
JL		 10724
10725 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 10726 DONE;
10727}")
59257ff7
RK		 10728
10729;; These patterns say how to save and restore the stack pointer. We need not
10730;; save the stack pointer at function level since we are careful to
10731;; preserve the backchain. At block level, we have to restore the backchain
10732;; when we restore the stack pointer.
10733;;
10734;; For nonlocal gotos, we must save both the stack pointer and its
10735;; backchain and restore both. Note that in the nonlocal case, the
10736;; save area is a memory location.
10737
10738(define_expand "save_stack_function"
ff381587
MM		 10739 [(match_operand 0 "any_operand" "")
10740 (match_operand 1 "any_operand" "")]
59257ff7 10741 ""
ff381587 10742 "DONE;")
59257ff7
RK		 10743
10744(define_expand "restore_stack_function"
ff381587
MM		 10745 [(match_operand 0 "any_operand" "")
10746 (match_operand 1 "any_operand" "")]
59257ff7 10747 ""
ff381587 10748 "DONE;")
59257ff7 10749
2eef28ec
AM		 10750;; Adjust stack pointer (op0) to a new value (op1).
10751;; First copy old stack backchain to new location, and ensure that the
10752;; scheduler won't reorder the sp assignment before the backchain write.
59257ff7 10753(define_expand "restore_stack_block"
2eef28ec
AM		 10754 [(set (match_dup 2) (match_dup 3))
10755 (set (match_dup 4) (match_dup 2))
10756 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10757 (set (match_operand 0 "register_operand" "")
10758 (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10759 ""
10760 "
dfdfa60f 10761{
583da60a 10762 operands[1] = force_reg (Pmode, operands[1]);
dfdfa60f 10763 operands[2] = gen_reg_rtx (Pmode);
2eef28ec
AM		 10764 operands[3] = gen_frame_mem (Pmode, operands[0]);
10765 operands[4] = gen_frame_mem (Pmode, operands[1]);
10766 operands[5] = gen_frame_mem (BLKmode, operands[0]);
dfdfa60f 10767}")
59257ff7
RK		 10768
10769(define_expand "save_stack_nonlocal"
2eef28ec
AM		 10770 [(set (match_dup 3) (match_dup 4))
10771 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10772 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10773 ""
10774 "
10775{
11b25716 10776 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10777
10778 /* Copy the backchain to the first word, sp to the second. */
2eef28ec
AM		 10779 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10780 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10781 operands[3] = gen_reg_rtx (Pmode);
10782 operands[4] = gen_frame_mem (Pmode, operands[1]);
59257ff7 10783}")
7e69e155 10784
59257ff7 10785(define_expand "restore_stack_nonlocal"
2eef28ec
AM		 10786 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10787 (set (match_dup 3) (match_dup 4))
10788 (set (match_dup 5) (match_dup 2))
10789 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10790 (set (match_operand 0 "register_operand" "") (match_dup 3))]
59257ff7
RK		 10791 ""
10792 "
10793{
11b25716 10794 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10795
10796 /* Restore the backchain from the first word, sp from the second. */
2eef28ec
AM		 10797 operands[2] = gen_reg_rtx (Pmode);
10798 operands[3] = gen_reg_rtx (Pmode);
10799 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10800 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10801 operands[5] = gen_frame_mem (Pmode, operands[3]);
10802 operands[6] = gen_frame_mem (BLKmode, operands[0]);
59257ff7 10803}")
9ebbca7d
GK		 10804\f
10805;; TOC register handling.
b6c9286a 10806
9ebbca7d 10807;; Code to initialize the TOC register...
f0f6a223 10808
9ebbca7d 10809(define_insn "load_toc_aix_si"
e72247f4 10810 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 10811 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10812 (use (reg:SI 2))])]
2bfcf297 10813 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 10814 "*
10815{
9ebbca7d
GK		 10816 char buf[30];
10817 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 10818 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10819 operands[2] = gen_rtx_REG (Pmode, 2);
10820 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 10821}"
10822 [(set_attr "type" "load")])
9ebbca7d
GK		 10823
10824(define_insn "load_toc_aix_di"
e72247f4 10825 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 10826 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10827 (use (reg:DI 2))])]
2bfcf297 10828 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 10829 "*
10830{
10831 char buf[30];
f585a356
DE		 10832#ifdef TARGET_RELOCATABLE
10833 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10834 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10835#else
9ebbca7d 10836 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 10837#endif
2bfcf297
DB		 10838 if (TARGET_ELF)
10839 strcat (buf, \"@toc\");
a8a05998 10840 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10841 operands[2] = gen_rtx_REG (Pmode, 2);
10842 return \"ld %0,%1(%2)\";
10843}"
10844 [(set_attr "type" "load")])
10845
10846(define_insn "load_toc_v4_pic_si"
1de43f85 10847 [(set (reg:SI LR_REGNO)
615158e2 10848 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 10849 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 10850 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10851 [(set_attr "type" "branch")
10852 (set_attr "length" "4")])
10853
9ebbca7d 10854(define_insn "load_toc_v4_PIC_1"
1de43f85 10855 [(set (reg:SI LR_REGNO)
e65a3857
DE		 10856 (match_operand:SI 0 "immediate_operand" "s"))
10857 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
7f970b70
AM		 10858 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10859 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
e65a3857 10860 "bcl 20,31,%0\\n%0:"
9ebbca7d
GK		 10861 [(set_attr "type" "branch")
10862 (set_attr "length" "4")])
10863
10864(define_insn "load_toc_v4_PIC_1b"
1de43f85 10865 [(set (reg:SI LR_REGNO)
e65a3857 10866 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
c4501e62 10867 UNSPEC_TOCPTR))]
20b71b17 10868 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
e65a3857 10869 "bcl 20,31,$+8\\n\\t.long %0-$"
9ebbca7d
GK		 10870 [(set_attr "type" "branch")
10871 (set_attr "length" "8")])
10872
10873(define_insn "load_toc_v4_PIC_2"
f585a356 10874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 10875 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 10876 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10877 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 10878 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 10879 "{l|lwz} %0,%2-%3(%1)"
10880 [(set_attr "type" "load")])
10881
7f970b70
AM		 10882(define_insn "load_toc_v4_PIC_3b"
10883 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10884 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10885 (high:SI
10886 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10887 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10888 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10889 "{cau|addis} %0,%1,%2-%3@ha")
10890
10891(define_insn "load_toc_v4_PIC_3c"
10892 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10893 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10894 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10895 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10896 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10897 "{cal|addi} %0,%1,%2-%3@l")
f51eee6a 10898
9ebbca7d
GK		 10899;; If the TOC is shared over a translation unit, as happens with all
10900;; the kinds of PIC that we support, we need to restore the TOC
10901;; pointer only when jumping over units of translation.
f51eee6a 10902;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 10903
10904(define_expand "builtin_setjmp_receiver"
10905 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 10906 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 10907 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10908 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 10909 "
10910{
84d7dd4a 10911#if TARGET_MACHO
f51eee6a
GK		 10912 if (DEFAULT_ABI == ABI_DARWIN)
10913 {
08a6a74b 10914 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
f51eee6a
GK		 10915 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10916 rtx tmplabrtx;
10917 char tmplab[20];
10918
08a6a74b 10919 crtl->uses_pic_offset_table = 1;
f51eee6a
GK		 10920 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10921 CODE_LABEL_NUMBER (operands[0]));
485bad26 10922 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a 10923
316fbf19 10924 emit_insn (gen_load_macho_picbase (tmplabrtx));
1de43f85 10925 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
b8a55285 10926 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
f51eee6a
GK		 10927 }
10928 else
84d7dd4a 10929#endif
f51eee6a 10930 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 10931 DONE;
10932}")
7f970b70
AM		 10933
10934;; Elf specific ways of loading addresses for non-PIC code.
10935;; The output of this could be r0, but we make a very strong
10936;; preference for a base register because it will usually
10937;; be needed there.
10938(define_insn "elf_high"
10939 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10940 (high:SI (match_operand 1 "" "")))]
10941 "TARGET_ELF && ! TARGET_64BIT"
10942 "{liu|lis} %0,%1@ha")
10943
10944(define_insn "elf_low"
10945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10946 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10947 (match_operand 2 "" "")))]
10948 "TARGET_ELF && ! TARGET_64BIT"
10949 "@
10950 {cal|la} %0,%2@l(%1)
10951 {ai|addic} %0,%1,%K2")
9ebbca7d
GK		 10952\f
10953;; A function pointer under AIX is a pointer to a data area whose first word
10954;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 10955;; pointer to its TOC, and whose third word contains a value to place in the
10956;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 10957;; "trampoline" need not have any executable code.
b6c9286a 10958
cccf3bdc
DE		 10959(define_expand "call_indirect_aix32"
10960 [(set (match_dup 2)
10961 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10962 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10963 (reg:SI 2))
cccf3bdc
DE		 10964 (set (reg:SI 11)
10965 (mem:SI (plus:SI (match_dup 0)
10966 (const_int 8))))
10967 (parallel [(call (mem:SI (match_dup 2))
10968 (match_operand 1 "" ""))
a893ac80 10969 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
cccf3bdc 10970 (use (reg:SI 11))
a893ac80 10971 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10972 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10973 "TARGET_32BIT"
10974 "
10975{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 10976
cccf3bdc
DE		 10977(define_expand "call_indirect_aix64"
10978 [(set (match_dup 2)
10979 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10980 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10981 (reg:DI 2))
cccf3bdc
DE		 10982 (set (reg:DI 11)
10983 (mem:DI (plus:DI (match_dup 0)
10984 (const_int 16))))
10985 (parallel [(call (mem:SI (match_dup 2))
10986 (match_operand 1 "" ""))
a893ac80 10987 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
cccf3bdc 10988 (use (reg:DI 11))
a893ac80 10989 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10990 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10991 "TARGET_64BIT"
10992 "
10993{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 10994
cccf3bdc
DE		 10995(define_expand "call_value_indirect_aix32"
10996 [(set (match_dup 3)
10997 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10998 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10999 (reg:SI 2))
cccf3bdc
DE		 11000 (set (reg:SI 11)
11001 (mem:SI (plus:SI (match_dup 1)
11002 (const_int 8))))
11003 (parallel [(set (match_operand 0 "" "")
11004 (call (mem:SI (match_dup 3))
11005 (match_operand 2 "" "")))
a893ac80 11006 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
cccf3bdc 11007 (use (reg:SI 11))
a893ac80 11008 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11009 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 11010 "TARGET_32BIT"
11011 "
11012{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 11013
cccf3bdc
DE		 11014(define_expand "call_value_indirect_aix64"
11015 [(set (match_dup 3)
11016 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11017 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11018 (reg:DI 2))
cccf3bdc
DE		 11019 (set (reg:DI 11)
11020 (mem:DI (plus:DI (match_dup 1)
11021 (const_int 16))))
11022 (parallel [(set (match_operand 0 "" "")
11023 (call (mem:SI (match_dup 3))
11024 (match_operand 2 "" "")))
a893ac80 11025 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
cccf3bdc 11026 (use (reg:DI 11))
a893ac80 11027 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11028 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 11029 "TARGET_64BIT"
11030 "
11031{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 11032
b6c9286a 11033;; Now the definitions for the call and call_value insns
1fd4e8c1 11034(define_expand "call"
a260abc9 11035 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 11036 (match_operand 1 "" ""))
4697a36c 11037 (use (match_operand 2 "" ""))
1de43f85 11038 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 11039 ""
11040 "
11041{
ee890fe2 11042#if TARGET_MACHO
ab82a49f 11043 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 11044 operands[0] = machopic_indirect_call_target (operands[0]);
11045#endif
11046
37409796
NS		 11047 gcc_assert (GET_CODE (operands[0]) == MEM);
11048 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
1fd4e8c1
RK		 11049
11050 operands[0] = XEXP (operands[0], 0);
7509c759 11051
6a4cee5f 11052 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 11053 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
efdba735 11054 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
1fd4e8c1 11055 {
6a4cee5f
MM		 11056 if (INTVAL (operands[2]) & CALL_LONG)
11057 operands[0] = rs6000_longcall_ref (operands[0]);
11058
37409796
NS		 11059 switch (DEFAULT_ABI)
11060 {
11061 case ABI_V4:
11062 case ABI_DARWIN:
11063 operands[0] = force_reg (Pmode, operands[0]);
11064 break;
1fd4e8c1 11065
37409796 11066 case ABI_AIX:
cccf3bdc
DE		 11067 /* AIX function pointers are really pointers to a three word
11068 area. */
11069 emit_call_insn (TARGET_32BIT
11070 ? gen_call_indirect_aix32 (force_reg (SImode,
11071 operands[0]),
11072 operands[1])
11073 : gen_call_indirect_aix64 (force_reg (DImode,
11074 operands[0]),
11075 operands[1]));
11076 DONE;
37409796
NS		 11077
11078 default:
11079 gcc_unreachable ();
b6c9286a 11080 }
1fd4e8c1
RK		 11081 }
11082}")
11083
11084(define_expand "call_value"
11085 [(parallel [(set (match_operand 0 "" "")
a260abc9 11086 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 11087 (match_operand 2 "" "")))
4697a36c 11088 (use (match_operand 3 "" ""))
1de43f85 11089 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 11090 ""
11091 "
11092{
ee890fe2 11093#if TARGET_MACHO
ab82a49f 11094 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 11095 operands[1] = machopic_indirect_call_target (operands[1]);
11096#endif
11097
37409796
NS		 11098 gcc_assert (GET_CODE (operands[1]) == MEM);
11099 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
1fd4e8c1
RK		 11100
11101 operands[1] = XEXP (operands[1], 0);
7509c759 11102
6a4cee5f 11103 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 11104 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
efdba735 11105 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
1fd4e8c1 11106 {
6756293c 11107 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 11108 operands[1] = rs6000_longcall_ref (operands[1]);
11109
37409796
NS		 11110 switch (DEFAULT_ABI)
11111 {
11112 case ABI_V4:
11113 case ABI_DARWIN:
11114 operands[1] = force_reg (Pmode, operands[1]);
11115 break;
1fd4e8c1 11116
37409796 11117 case ABI_AIX:
cccf3bdc
DE		 11118 /* AIX function pointers are really pointers to a three word
11119 area. */
11120 emit_call_insn (TARGET_32BIT
11121 ? gen_call_value_indirect_aix32 (operands[0],
11122 force_reg (SImode,
11123 operands[1]),
11124 operands[2])
11125 : gen_call_value_indirect_aix64 (operands[0],
11126 force_reg (DImode,
11127 operands[1]),
11128 operands[2]));
11129 DONE;
37409796
NS		 11130
11131 default:
11132 gcc_unreachable ();
b6c9286a 11133 }
1fd4e8c1
RK		 11134 }
11135}")
11136
04780ee7 11137;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 11138;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 11139;; either the function was not prototyped, or it was prototyped as a
11140;; variable argument function. It is > 0 if FP registers were passed
11141;; and < 0 if they were not.
04780ee7 11142
a260abc9 11143(define_insn "*call_local32"
4697a36c
MM		 11144 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11145 (match_operand 1 "" "g,g"))
11146 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11147 (clobber (reg:SI LR_REGNO))]
5a19791c 11148 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 11149 "*
11150{
6a4cee5f
MM		 11151 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11152 output_asm_insn (\"crxor 6,6,6\", operands);
11153
11154 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11155 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 11156
a226df46 11157 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 11158}"
b7ff3d82
DE		 11159 [(set_attr "type" "branch")
11160 (set_attr "length" "4,8")])
04780ee7 11161
a260abc9
DE		 11162(define_insn "*call_local64"
11163 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11164 (match_operand 1 "" "g,g"))
11165 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11166 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 11167 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11168 "*
11169{
11170 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11171 output_asm_insn (\"crxor 6,6,6\", operands);
11172
11173 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11174 output_asm_insn (\"creqv 6,6,6\", operands);
11175
11176 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11177}"
11178 [(set_attr "type" "branch")
11179 (set_attr "length" "4,8")])
11180
cccf3bdc 11181(define_insn "*call_value_local32"
d18dba68 11182 [(set (match_operand 0 "" "")
a260abc9
DE		 11183 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11184 (match_operand 2 "" "g,g")))
11185 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11186 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 11187 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11188 "*
11189{
11190 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11191 output_asm_insn (\"crxor 6,6,6\", operands);
11192
11193 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11194 output_asm_insn (\"creqv 6,6,6\", operands);
11195
11196 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11197}"
11198 [(set_attr "type" "branch")
11199 (set_attr "length" "4,8")])
11200
11201
cccf3bdc 11202(define_insn "*call_value_local64"
d18dba68 11203 [(set (match_operand 0 "" "")
a260abc9
DE		 11204 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11205 (match_operand 2 "" "g,g")))
11206 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11207 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 11208 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11209 "*
11210{
11211 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11212 output_asm_insn (\"crxor 6,6,6\", operands);
11213
11214 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11215 output_asm_insn (\"creqv 6,6,6\", operands);
11216
11217 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11218}"
11219 [(set_attr "type" "branch")
11220 (set_attr "length" "4,8")])
11221
04780ee7 11222;; Call to function which may be in another module. Restore the TOC
911f679c 11223;; pointer (r2) after the call unless this is System V.
a0ab749a 11224;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 11225;; either the function was not prototyped, or it was prototyped as a
11226;; variable argument function. It is > 0 if FP registers were passed
11227;; and < 0 if they were not.
04780ee7 11228
a893ac80
AP		 11229(define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11230 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11231 (match_operand 1 "" "g,g"))
11232 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11233 (use (reg:SI 11))
11234 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11235 (clobber (reg:SI LR_REGNO))]
11236 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11237 "#"
11238 "&& reload_completed"
11239 [(set (reg:SI 2)
11240 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11241 (parallel [(call (mem:SI (match_dup 0))
11242 (match_dup 1))
11243 (use (reg:SI 2))
11244 (use (reg:SI 11))
11245 (set (reg:SI 2)
11246 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11247 (clobber (reg:SI LR_REGNO))])]
11248 ""
11249 [(set_attr "type" "jmpreg")
11250 (set_attr "length" "12")])
11251
cccf3bdc 11252(define_insn "*call_indirect_nonlocal_aix32"
70ae0191
DE		 11253 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11254 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 11255 (use (reg:SI 2))
11256 (use (reg:SI 11))
11257 (set (reg:SI 2)
11258 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11259 (clobber (reg:SI LR_REGNO))]
a893ac80 11260 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
cccf3bdc
DE		 11261 "b%T0l\;{l|lwz} 2,20(1)"
11262 [(set_attr "type" "jmpreg")
11263 (set_attr "length" "8")])
11264
a260abc9 11265(define_insn "*call_nonlocal_aix32"
cc4d5fec 11266 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11267 (match_operand 1 "" "g"))
11268 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11269 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11270 "TARGET_32BIT
11271 && DEFAULT_ABI == ABI_AIX
5a19791c 11272 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 11273 "bl %z0\;%."
b7ff3d82 11274 [(set_attr "type" "branch")
cccf3bdc 11275 (set_attr "length" "8")])
a893ac80
AP		 11276
11277(define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11278 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11279 (match_operand 1 "" "g,g"))
11280 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11281 (const_int 8))))
11282 (use (reg:DI 11))
11283 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11284 (clobber (reg:SI LR_REGNO))]
11285 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11286 "#"
11287 "&& reload_completed"
11288 [(set (reg:DI 2)
11289 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11290 (parallel [(call (mem:SI (match_dup 0))
11291 (match_dup 1))
11292 (use (reg:DI 2))
11293 (use (reg:DI 11))
11294 (set (reg:DI 2)
11295 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11296 (clobber (reg:SI LR_REGNO))])]
11297 ""
11298 [(set_attr "type" "jmpreg")
11299 (set_attr "length" "12")])
cccf3bdc
DE		 11300
11301(define_insn "*call_indirect_nonlocal_aix64"
70ae0191
DE		 11302 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11303 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 11304 (use (reg:DI 2))
11305 (use (reg:DI 11))
11306 (set (reg:DI 2)
11307 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11308 (clobber (reg:SI LR_REGNO))]
a893ac80 11309 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
cccf3bdc
DE		 11310 "b%T0l\;ld 2,40(1)"
11311 [(set_attr "type" "jmpreg")
11312 (set_attr "length" "8")])
59313e4e 11313
a260abc9 11314(define_insn "*call_nonlocal_aix64"
cc4d5fec 11315 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11316 (match_operand 1 "" "g"))
11317 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11318 (clobber (reg:SI LR_REGNO))]
6ae08853 11319 "TARGET_64BIT
9ebbca7d 11320 && DEFAULT_ABI == ABI_AIX
a260abc9 11321 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 11322 "bl %z0\;%."
a260abc9 11323 [(set_attr "type" "branch")
cccf3bdc 11324 (set_attr "length" "8")])
7509c759 11325
a893ac80
AP		 11326(define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11327 [(set (match_operand 0 "" "")
11328 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11329 (match_operand 2 "" "g,g")))
11330 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11331 (const_int 4))))
11332 (use (reg:SI 11))
11333 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11334 (clobber (reg:SI LR_REGNO))]
11335 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11336 "#"
11337 "&& reload_completed"
11338 [(set (reg:SI 2)
11339 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11340 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11341 (match_dup 2)))
11342 (use (reg:SI 2))
11343 (use (reg:SI 11))
11344 (set (reg:SI 2)
11345 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11346 (clobber (reg:SI LR_REGNO))])]
11347 ""
11348 [(set_attr "type" "jmpreg")
11349 (set_attr "length" "12")])
11350
cccf3bdc 11351(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 11352 [(set (match_operand 0 "" "")
70ae0191
DE		 11353 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11354 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11355 (use (reg:SI 2))
11356 (use (reg:SI 11))
11357 (set (reg:SI 2)
11358 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11359 (clobber (reg:SI LR_REGNO))]
a893ac80 11360 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
cccf3bdc
DE		 11361 "b%T1l\;{l|lwz} 2,20(1)"
11362 [(set_attr "type" "jmpreg")
11363 (set_attr "length" "8")])
1fd4e8c1 11364
cccf3bdc 11365(define_insn "*call_value_nonlocal_aix32"
d18dba68 11366 [(set (match_operand 0 "" "")
cc4d5fec 11367 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11368 (match_operand 2 "" "g")))
11369 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11370 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11371 "TARGET_32BIT
11372 && DEFAULT_ABI == ABI_AIX
a260abc9 11373 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 11374 "bl %z1\;%."
b7ff3d82 11375 [(set_attr "type" "branch")
cccf3bdc 11376 (set_attr "length" "8")])
04780ee7 11377
a893ac80
AP		 11378(define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11379 [(set (match_operand 0 "" "")
11380 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11381 (match_operand 2 "" "g,g")))
11382 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
11383 (const_int 8))))
11384 (use (reg:DI 11))
11385 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11386 (clobber (reg:SI LR_REGNO))]
11387 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11388 "#"
11389 "&& reload_completed"
11390 [(set (reg:DI 2)
11391 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
11392 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11393 (match_dup 2)))
11394 (use (reg:DI 2))
11395 (use (reg:DI 11))
11396 (set (reg:DI 2)
11397 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11398 (clobber (reg:SI LR_REGNO))])]
11399 ""
11400 [(set_attr "type" "jmpreg")
11401 (set_attr "length" "12")])
11402
cccf3bdc 11403(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 11404 [(set (match_operand 0 "" "")
70ae0191
DE		 11405 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11406 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11407 (use (reg:DI 2))
11408 (use (reg:DI 11))
11409 (set (reg:DI 2)
11410 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11411 (clobber (reg:SI LR_REGNO))]
a893ac80 11412 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
cccf3bdc
DE		 11413 "b%T1l\;ld 2,40(1)"
11414 [(set_attr "type" "jmpreg")
11415 (set_attr "length" "8")])
11416
11417(define_insn "*call_value_nonlocal_aix64"
d18dba68 11418 [(set (match_operand 0 "" "")
cc4d5fec 11419 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11420 (match_operand 2 "" "g")))
11421 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11422 (clobber (reg:SI LR_REGNO))]
6ae08853 11423 "TARGET_64BIT
9ebbca7d 11424 && DEFAULT_ABI == ABI_AIX
5a19791c 11425 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 11426 "bl %z1\;%."
11427 [(set_attr "type" "branch")
11428 (set_attr "length" "8")])
11429
11430;; A function pointer under System V is just a normal pointer
11431;; operands[0] is the function pointer
11432;; operands[1] is the stack size to clean up
11433;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11434;; which indicates how to set cr1
11435
9613eaff
SH		 11436(define_insn "*call_indirect_nonlocal_sysv<mode>"
11437 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11438 (match_operand 1 "" "g,g,g,g"))
11439 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
1de43f85 11440 (clobber (reg:SI LR_REGNO))]
50d440bc 11441 "DEFAULT_ABI == ABI_V4
f607bc57 11442 || DEFAULT_ABI == ABI_DARWIN"
911f679c 11443{
cccf3bdc 11444 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11445 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 11446
cccf3bdc 11447 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11448 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11449
a5c76ee6
ZW		 11450 return "b%T0l";
11451}
6d0a8091
DJ		 11452 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11453 (set_attr "length" "4,4,8,8")])
cccf3bdc 11454
1d3155fc 11455(define_insn_and_split "*call_nonlocal_sysv<mode>"
9613eaff 11456 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11457 (match_operand 1 "" "g,g"))
11458 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11459 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11460 "(DEFAULT_ABI == ABI_DARWIN
11461 || (DEFAULT_ABI == ABI_V4
11462 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11463{
11464 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11465 output_asm_insn ("crxor 6,6,6", operands);
11466
11467 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11468 output_asm_insn ("creqv 6,6,6", operands);
11469
c989f2f7 11470#if TARGET_MACHO
efdba735
SH		 11471 return output_call(insn, operands, 0, 2);
11472#else
7f970b70
AM		 11473 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11474 {
1d3155fc
AM		 11475 gcc_assert (!TARGET_SECURE_PLT);
11476 return "bl %z0@plt";
7f970b70
AM		 11477 }
11478 else
11479 return "bl %z0";
6ae08853 11480#endif
1d3155fc
AM		 11481}
11482 "DEFAULT_ABI == ABI_V4
11483 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11484 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11485 [(parallel [(call (mem:SI (match_dup 0))
11486 (match_dup 1))
11487 (use (match_dup 2))
11488 (use (match_dup 3))
11489 (clobber (reg:SI LR_REGNO))])]
11490{
11491 operands[3] = pic_offset_table_rtx;
11492}
11493 [(set_attr "type" "branch,branch")
11494 (set_attr "length" "4,8")])
11495
11496(define_insn "*call_nonlocal_sysv_secure<mode>"
11497 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11498 (match_operand 1 "" "g,g"))
11499 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11500 (use (match_operand:SI 3 "register_operand" "r,r"))
11501 (clobber (reg:SI LR_REGNO))]
11502 "(DEFAULT_ABI == ABI_V4
11503 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11504 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11505{
11506 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11507 output_asm_insn ("crxor 6,6,6", operands);
11508
11509 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11510 output_asm_insn ("creqv 6,6,6", operands);
11511
11512 if (flag_pic == 2)
11513 /* The magic 32768 offset here and in the other sysv call insns
11514 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11515 See sysv4.h:toc_section. */
11516 return "bl %z0+32768@plt";
11517 else
11518 return "bl %z0@plt";
a5c76ee6
ZW		 11519}
11520 [(set_attr "type" "branch,branch")
11521 (set_attr "length" "4,8")])
11522
9613eaff 11523(define_insn "*call_value_indirect_nonlocal_sysv<mode>"
d18dba68 11524 [(set (match_operand 0 "" "")
9613eaff 11525 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11526 (match_operand 2 "" "g,g,g,g")))
11527 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
1de43f85 11528 (clobber (reg:SI LR_REGNO))]
50d440bc 11529 "DEFAULT_ABI == ABI_V4
f607bc57 11530 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 11531{
6a4cee5f 11532 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11533 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 11534
11535 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11536 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11537
a5c76ee6
ZW		 11538 return "b%T1l";
11539}
6d0a8091
DJ		 11540 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11541 (set_attr "length" "4,4,8,8")])
a5c76ee6 11542
1d3155fc 11543(define_insn_and_split "*call_value_nonlocal_sysv<mode>"
a5c76ee6 11544 [(set (match_operand 0 "" "")
9613eaff 11545 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11546 (match_operand 2 "" "g,g")))
11547 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11548 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11549 "(DEFAULT_ABI == ABI_DARWIN
11550 || (DEFAULT_ABI == ABI_V4
11551 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11552{
11553 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11554 output_asm_insn ("crxor 6,6,6", operands);
11555
11556 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11557 output_asm_insn ("creqv 6,6,6", operands);
11558
c989f2f7 11559#if TARGET_MACHO
efdba735
SH		 11560 return output_call(insn, operands, 1, 3);
11561#else
7f970b70
AM		 11562 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11563 {
1d3155fc
AM		 11564 gcc_assert (!TARGET_SECURE_PLT);
11565 return "bl %z1@plt";
7f970b70
AM		 11566 }
11567 else
11568 return "bl %z1";
6ae08853 11569#endif
1d3155fc
AM		 11570}
11571 "DEFAULT_ABI == ABI_V4
11572 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11573 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11574 [(parallel [(set (match_dup 0)
11575 (call (mem:SI (match_dup 1))
11576 (match_dup 2)))
11577 (use (match_dup 3))
11578 (use (match_dup 4))
11579 (clobber (reg:SI LR_REGNO))])]
11580{
11581 operands[4] = pic_offset_table_rtx;
11582}
11583 [(set_attr "type" "branch,branch")
11584 (set_attr "length" "4,8")])
11585
11586(define_insn "*call_value_nonlocal_sysv_secure<mode>"
11587 [(set (match_operand 0 "" "")
11588 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11589 (match_operand 2 "" "g,g")))
11590 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11591 (use (match_operand:SI 4 "register_operand" "r,r"))
11592 (clobber (reg:SI LR_REGNO))]
11593 "(DEFAULT_ABI == ABI_V4
11594 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11595 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11596{
11597 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11598 output_asm_insn ("crxor 6,6,6", operands);
11599
11600 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11601 output_asm_insn ("creqv 6,6,6", operands);
11602
11603 if (flag_pic == 2)
11604 return "bl %z1+32768@plt";
11605 else
11606 return "bl %z1@plt";
a5c76ee6
ZW		 11607}
11608 [(set_attr "type" "branch,branch")
11609 (set_attr "length" "4,8")])
e6f948e3
RK		 11610
11611;; Call subroutine returning any type.
e6f948e3
RK		 11612(define_expand "untyped_call"
11613 [(parallel [(call (match_operand 0 "" "")
11614 (const_int 0))
11615 (match_operand 1 "" "")
11616 (match_operand 2 "" "")])]
11617 ""
11618 "
11619{
11620 int i;
11621
7d70b8b2 11622 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 11623
11624 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11625 {
11626 rtx set = XVECEXP (operands[2], 0, i);
11627 emit_move_insn (SET_DEST (set), SET_SRC (set));
11628 }
11629
11630 /* The optimizer does not know that the call sets the function value
11631 registers we stored in the result block. We avoid problems by
11632 claiming that all hard registers are used and clobbered at this
11633 point. */
11634 emit_insn (gen_blockage ());
11635
11636 DONE;
11637}")
11638
5e1bf043
DJ		 11639;; sibling call patterns
11640(define_expand "sibcall"
11641 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11642 (match_operand 1 "" ""))
11643 (use (match_operand 2 "" ""))
1de43f85 11644 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11645 (return)])]
11646 ""
11647 "
11648{
11649#if TARGET_MACHO
ab82a49f 11650 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11651 operands[0] = machopic_indirect_call_target (operands[0]);
11652#endif
11653
37409796
NS		 11654 gcc_assert (GET_CODE (operands[0]) == MEM);
11655 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5e1bf043
DJ		 11656
11657 operands[0] = XEXP (operands[0], 0);
5e1bf043
DJ		 11658}")
11659
11660;; this and similar patterns must be marked as using LR, otherwise
11661;; dataflow will try to delete the store into it. This is true
11662;; even when the actual reg to jump to is in CTR, when LR was
11663;; saved and restored around the PIC-setting BCL.
11664(define_insn "*sibcall_local32"
11665 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11666 (match_operand 1 "" "g,g"))
11667 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11668 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11669 (return)]
11670 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11671 "*
11672{
11673 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11674 output_asm_insn (\"crxor 6,6,6\", operands);
11675
11676 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11677 output_asm_insn (\"creqv 6,6,6\", operands);
11678
11679 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11680}"
11681 [(set_attr "type" "branch")
11682 (set_attr "length" "4,8")])
11683
11684(define_insn "*sibcall_local64"
11685 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11686 (match_operand 1 "" "g,g"))
11687 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11688 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11689 (return)]
11690 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11691 "*
11692{
11693 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11694 output_asm_insn (\"crxor 6,6,6\", operands);
11695
11696 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11697 output_asm_insn (\"creqv 6,6,6\", operands);
11698
11699 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11700}"
11701 [(set_attr "type" "branch")
11702 (set_attr "length" "4,8")])
11703
11704(define_insn "*sibcall_value_local32"
11705 [(set (match_operand 0 "" "")
11706 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11707 (match_operand 2 "" "g,g")))
11708 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11709 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11710 (return)]
11711 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11712 "*
11713{
11714 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11715 output_asm_insn (\"crxor 6,6,6\", operands);
11716
11717 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11718 output_asm_insn (\"creqv 6,6,6\", operands);
11719
11720 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11721}"
11722 [(set_attr "type" "branch")
11723 (set_attr "length" "4,8")])
11724
11725
11726(define_insn "*sibcall_value_local64"
11727 [(set (match_operand 0 "" "")
11728 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11729 (match_operand 2 "" "g,g")))
11730 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11731 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11732 (return)]
11733 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11734 "*
11735{
11736 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11737 output_asm_insn (\"crxor 6,6,6\", operands);
11738
11739 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11740 output_asm_insn (\"creqv 6,6,6\", operands);
11741
11742 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11743}"
11744 [(set_attr "type" "branch")
11745 (set_attr "length" "4,8")])
11746
11747(define_insn "*sibcall_nonlocal_aix32"
11748 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11749 (match_operand 1 "" "g"))
11750 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11751 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11752 (return)]
11753 "TARGET_32BIT
11754 && DEFAULT_ABI == ABI_AIX
11755 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11756 "b %z0"
11757 [(set_attr "type" "branch")
11758 (set_attr "length" "4")])
11759
11760(define_insn "*sibcall_nonlocal_aix64"
11761 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11762 (match_operand 1 "" "g"))
11763 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11764 (use (reg:SI LR_REGNO))
5e1bf043 11765 (return)]
6ae08853 11766 "TARGET_64BIT
5e1bf043
DJ		 11767 && DEFAULT_ABI == ABI_AIX
11768 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11769 "b %z0"
11770 [(set_attr "type" "branch")
11771 (set_attr "length" "4")])
11772
11773(define_insn "*sibcall_value_nonlocal_aix32"
11774 [(set (match_operand 0 "" "")
11775 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11776 (match_operand 2 "" "g")))
11777 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11778 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11779 (return)]
11780 "TARGET_32BIT
11781 && DEFAULT_ABI == ABI_AIX
11782 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11783 "b %z1"
11784 [(set_attr "type" "branch")
11785 (set_attr "length" "4")])
11786
11787(define_insn "*sibcall_value_nonlocal_aix64"
11788 [(set (match_operand 0 "" "")
11789 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11790 (match_operand 2 "" "g")))
11791 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11792 (use (reg:SI LR_REGNO))
5e1bf043 11793 (return)]
6ae08853 11794 "TARGET_64BIT
5e1bf043
DJ		 11795 && DEFAULT_ABI == ABI_AIX
11796 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11797 "b %z1"
11798 [(set_attr "type" "branch")
11799 (set_attr "length" "4")])
11800
9613eaff
SH		 11801(define_insn "*sibcall_nonlocal_sysv<mode>"
11802 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11803 (match_operand 1 "" ""))
11804 (use (match_operand 2 "immediate_operand" "O,n"))
1de43f85 11805 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11806 (return)]
11807 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11808 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11809 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11810 "*
11811{
11812 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11813 output_asm_insn (\"crxor 6,6,6\", operands);
11814
11815 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11816 output_asm_insn (\"creqv 6,6,6\", operands);
11817
7f970b70
AM		 11818 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11819 {
1d3155fc
AM		 11820 gcc_assert (!TARGET_SECURE_PLT);
11821 return \"b %z0@plt\";
7f970b70
AM		 11822 }
11823 else
11824 return \"b %z0\";
5e1bf043
DJ		 11825}"
11826 [(set_attr "type" "branch,branch")
11827 (set_attr "length" "4,8")])
11828
11829(define_expand "sibcall_value"
11830 [(parallel [(set (match_operand 0 "register_operand" "")
11831 (call (mem:SI (match_operand 1 "address_operand" ""))
11832 (match_operand 2 "" "")))
11833 (use (match_operand 3 "" ""))
1de43f85 11834 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11835 (return)])]
11836 ""
11837 "
11838{
11839#if TARGET_MACHO
ab82a49f 11840 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11841 operands[1] = machopic_indirect_call_target (operands[1]);
11842#endif
11843
37409796
NS		 11844 gcc_assert (GET_CODE (operands[1]) == MEM);
11845 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5e1bf043
DJ		 11846
11847 operands[1] = XEXP (operands[1], 0);
5e1bf043
DJ		 11848}")
11849
9613eaff 11850(define_insn "*sibcall_value_nonlocal_sysv<mode>"
5e1bf043 11851 [(set (match_operand 0 "" "")
9613eaff 11852 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11853 (match_operand 2 "" "")))
11854 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11855 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11856 (return)]
11857 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11858 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11859 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11860 "*
11861{
11862 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11863 output_asm_insn (\"crxor 6,6,6\", operands);
11864
11865 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11866 output_asm_insn (\"creqv 6,6,6\", operands);
11867
7f970b70
AM		 11868 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11869 {
1d3155fc
AM		 11870 gcc_assert (!TARGET_SECURE_PLT);
11871 return \"b %z1@plt\";
7f970b70
AM		 11872 }
11873 else
11874 return \"b %z1\";
5e1bf043
DJ		 11875}"
11876 [(set_attr "type" "branch,branch")
11877 (set_attr "length" "4,8")])
11878
11879(define_expand "sibcall_epilogue"
11880 [(use (const_int 0))]
11881 "TARGET_SCHED_PROLOG"
11882 "
11883{
11884 rs6000_emit_epilogue (TRUE);
11885 DONE;
11886}")
11887
e6f948e3
RK		 11888;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11889;; all of memory. This blocks insns from being moved across this point.
11890
11891(define_insn "blockage"
615158e2 11892 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 11893 ""
11894 "")
1fd4e8c1
RK		 11895\f
11896;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 11897;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 11898;;
11899;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
f90b7a5a
PB		 11900;; insns, and branches.
11901
11902(define_expand "cbranch<mode>4"
11903 [(use (match_operator 0 "rs6000_cbranch_operator"
11904 [(match_operand:GPR 1 "gpc_reg_operand" "")
11905 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11906 (use (match_operand 3 ""))]
1fd4e8c1
RK		 11907 ""
11908 "
11909{
f90b7a5a 11910 /* Take care of the possibility that operands[2] might be negative but
1fd4e8c1 11911 this might be a logical operation. That insn doesn't exist. */
f90b7a5a
PB		 11912 if (GET_CODE (operands[2]) == CONST_INT
11913 && INTVAL (operands[2]) < 0)
11914 {
11915 operands[2] = force_reg (<MODE>mode, operands[2]);
11916 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11917 GET_MODE (operands[0]),
11918 operands[1], operands[2]);
11919 }
1fd4e8c1 11920
f90b7a5a 11921 rs6000_emit_cbranch (<MODE>mode, operands);
d6f99ca4
DE		 11922 DONE;
11923}")
11924
f90b7a5a
PB		 11925(define_expand "cbranch<mode>4"
11926 [(use (match_operator 0 "rs6000_cbranch_operator"
11927 [(match_operand:FP 1 "gpc_reg_operand" "")
11928 (match_operand:FP 2 "gpc_reg_operand" "")]))
11929 (use (match_operand 3 ""))]
1fd4e8c1
RK		 11930 ""
11931 "
6ae08853 11932{
f90b7a5a 11933 rs6000_emit_cbranch (<MODE>mode, operands);
39a10a29 11934 DONE;
1fd4e8c1
RK		 11935}")
11936
f90b7a5a
PB		 11937(define_expand "cstore<mode>4"
11938 [(use (match_operator 1 "rs6000_cbranch_operator"
11939 [(match_operand:GPR 2 "gpc_reg_operand" "")
11940 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11941 (clobber (match_operand:SI 0 "register_operand"))]
1fd4e8c1
RK		 11942 ""
11943 "
5638268e 11944{
f90b7a5a
PB		 11945 /* Take care of the possibility that operands[3] might be negative but
11946 this might be a logical operation. That insn doesn't exist. */
11947 if (GET_CODE (operands[3]) == CONST_INT
11948 && INTVAL (operands[3]) < 0)
11949 {
11950 operands[3] = force_reg (<MODE>mode, operands[3]);
11951 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11952 GET_MODE (operands[1]),
11953 operands[2], operands[3]);
11954 }
1fd4e8c1 11955
f90b7a5a
PB		 11956 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11957 For SEQ, likewise, except that comparisons with zero should be done
11958 with an scc insns. However, due to the order that combine see the
11959 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11960 the cases we don't want to handle or are best handled by portable
11961 code. */
11962 if (GET_CODE (operands[1]) == NE)
1fd4e8c1 11963 FAIL;
f90b7a5a
PB		 11964 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11965 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11966 && operands[3] == const0_rtx)
5638268e 11967 FAIL;
f90b7a5a 11968 rs6000_emit_sCOND (<MODE>mode, operands);
5638268e
DE		 11969 DONE;
11970}")
1fd4e8c1 11971
f90b7a5a
PB		 11972(define_expand "cstore<mode>4"
11973 [(use (match_operator 1 "rs6000_cbranch_operator"
11974 [(match_operand:FP 2 "gpc_reg_operand" "")
11975 (match_operand:FP 3 "gpc_reg_operand" "")]))
11976 (clobber (match_operand:SI 0 "register_operand"))]
1fd4e8c1
RK		 11977 ""
11978 "
5638268e 11979{
f90b7a5a 11980 rs6000_emit_sCOND (<MODE>mode, operands);
39a10a29 11981 DONE;
1fd4e8c1
RK		 11982}")
11983
b7053a3f 11984
3aebbe5f
JJ		 11985(define_expand "stack_protect_set"
11986 [(match_operand 0 "memory_operand" "")
11987 (match_operand 1 "memory_operand" "")]
11988 ""
11989{
77008252
JJ		 11990#ifdef TARGET_THREAD_SSP_OFFSET
11991 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11992 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11993 operands[1] = gen_rtx_MEM (Pmode, addr);
11994#endif
3aebbe5f
JJ		 11995 if (TARGET_64BIT)
11996 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11997 else
11998 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11999 DONE;
12000})
12001
12002(define_insn "stack_protect_setsi"
12003 [(set (match_operand:SI 0 "memory_operand" "=m")
12004 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12005 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12006 "TARGET_32BIT"
12007 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12008 [(set_attr "type" "three")
12009 (set_attr "length" "12")])
12010
12011(define_insn "stack_protect_setdi"
12012 [(set (match_operand:DI 0 "memory_operand" "=m")
12013 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12014 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12015 "TARGET_64BIT"
12016 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12017 [(set_attr "type" "three")
12018 (set_attr "length" "12")])
12019
12020(define_expand "stack_protect_test"
12021 [(match_operand 0 "memory_operand" "")
12022 (match_operand 1 "memory_operand" "")
12023 (match_operand 2 "" "")]
12024 ""
12025{
f90b7a5a 12026 rtx test, op0, op1;
77008252
JJ		 12027#ifdef TARGET_THREAD_SSP_OFFSET
12028 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12029 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12030 operands[1] = gen_rtx_MEM (Pmode, addr);
12031#endif
f90b7a5a
PB		 12032 op0 = operands[0];
12033 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12034 test = gen_rtx_EQ (VOIDmode, op0, op1);
12035 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
3aebbe5f
JJ		 12036 DONE;
12037})
12038
12039(define_insn "stack_protect_testsi"
12040 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12041 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12042 (match_operand:SI 2 "memory_operand" "m,m")]
12043 UNSPEC_SP_TEST))
41f12ed0
JJ		 12044 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12045 (clobber (match_scratch:SI 3 "=&r,&r"))]
3aebbe5f
JJ		 12046 "TARGET_32BIT"
12047 "@
12048 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12049 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12050 [(set_attr "length" "16,20")])
12051
12052(define_insn "stack_protect_testdi"
12053 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12054 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12055 (match_operand:DI 2 "memory_operand" "m,m")]
12056 UNSPEC_SP_TEST))
41f12ed0
JJ		 12057 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12058 (clobber (match_scratch:DI 3 "=&r,&r"))]
3aebbe5f
JJ		 12059 "TARGET_64BIT"
12060 "@
12061 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12062 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12063 [(set_attr "length" "16,20")])
12064
1fd4e8c1
RK		 12065\f
12066;; Here are the actual compare insns.
4ae234b0 12067(define_insn "*cmp<mode>_internal1"
1fd4e8c1 12068 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
4ae234b0
GK		 12069 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12070 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
1fd4e8c1 12071 ""
4ae234b0 12072 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
b54cf83a 12073 [(set_attr "type" "cmp")])
266eb58a 12074
f357808b 12075;; If we are comparing a register for equality with a large constant,
28d0e143
PB		 12076;; we can do this with an XOR followed by a compare. But this is profitable
12077;; only if the large constant is only used for the comparison (and in this
12078;; case we already have a register to reuse as scratch).
130869aa
PB		 12079;;
12080;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12081;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
f357808b 12082
28d0e143 12083(define_peephole2
130869aa 12084 [(set (match_operand:SI 0 "register_operand")
410c459d 12085 (match_operand:SI 1 "logical_const_operand" ""))
130869aa 12086 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
28d0e143 12087 [(match_dup 0)
410c459d 12088 (match_operand:SI 2 "logical_const_operand" "")]))
28d0e143 12089 (set (match_operand:CC 4 "cc_reg_operand" "")
130869aa 12090 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
28d0e143
PB		 12091 (match_dup 0)))
12092 (set (pc)
12093 (if_then_else (match_operator 6 "equality_operator"
12094 [(match_dup 4) (const_int 0)])
12095 (match_operand 7 "" "")
12096 (match_operand 8 "" "")))]
130869aa
PB		 12097 "peep2_reg_dead_p (3, operands[0])
12098 && peep2_reg_dead_p (4, operands[4])"
12099 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
28d0e143
PB		 12100 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12101 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12102
12103{
12104 /* Get the constant we are comparing against, and see what it looks like
12105 when sign-extended from 16 to 32 bits. Then see what constant we could
12106 XOR with SEXTC to get the sign-extended value. */
12107 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
130869aa 12108 SImode,
28d0e143
PB		 12109 operands[1], operands[2]);
12110 HOST_WIDE_INT c = INTVAL (cnst);
a65c591c 12111 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 12112 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 12113
28d0e143
PB		 12114 operands[9] = GEN_INT (xorv);
12115 operands[10] = GEN_INT (sextc);
12116})
f357808b 12117
acad7ed3 12118(define_insn "*cmpsi_internal2"
1fd4e8c1 12119 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 12120 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 12121 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 12122 ""
e2c953b6 12123 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 12124 [(set_attr "type" "cmp")])
1fd4e8c1 12125
acad7ed3 12126(define_insn "*cmpdi_internal2"
266eb58a
DE		 12127 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12128 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 12129 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 12130 ""
e2c953b6 12131 "cmpld%I2 %0,%1,%b2"
b54cf83a 12132 [(set_attr "type" "cmp")])
266eb58a 12133
1fd4e8c1
RK		 12134;; The following two insns don't exist as single insns, but if we provide
12135;; them, we can swap an add and compare, which will enable us to overlap more
12136;; of the required delay between a compare and branch. We generate code for
12137;; them by splitting.
12138
12139(define_insn ""
12140 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 12141 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12142 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 12143 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12144 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12145 ""
baf97f86
RK		 12146 "#"
12147 [(set_attr "length" "8")])
7e69e155 12148
1fd4e8c1
RK		 12149(define_insn ""
12150 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 12151 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12152 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 12153 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12154 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12155 ""
baf97f86
RK		 12156 "#"
12157 [(set_attr "length" "8")])
7e69e155 12158
1fd4e8c1
RK		 12159(define_split
12160 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 12161 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 12162 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 12163 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 12164 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12165 ""
12166 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12167 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12168
12169(define_split
12170 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 12171 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 12172 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 12173 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 12174 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12175 ""
12176 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12177 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12178
acad7ed3 12179(define_insn "*cmpsf_internal1"
1fd4e8c1 12180 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 12181 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12182 (match_operand:SF 2 "gpc_reg_operand" "f")))]
696e45ba 12183 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
1fd4e8c1
RK		 12184 "fcmpu %0,%1,%2"
12185 [(set_attr "type" "fpcompare")])
12186
acad7ed3 12187(define_insn "*cmpdf_internal1"
1fd4e8c1 12188 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 12189 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
12190 (match_operand:DF 2 "gpc_reg_operand" "f")))]
696e45ba 12191 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
1fd4e8c1
RK		 12192 "fcmpu %0,%1,%2"
12193 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 12194
12195;; Only need to compare second words if first words equal
12196(define_insn "*cmptf_internal1"
12197 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12198 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
12199 (match_operand:TF 2 "gpc_reg_operand" "f")))]
602ea4d3 12200 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
696e45ba 12201 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
ecb62ae7 12202 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 12203 [(set_attr "type" "fpcompare")
12204 (set_attr "length" "12")])
de17c25f
DE		 12205
12206(define_insn_and_split "*cmptf_internal2"
12207 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12208 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
12209 (match_operand:TF 2 "gpc_reg_operand" "f")))
12210 (clobber (match_scratch:DF 3 "=f"))
12211 (clobber (match_scratch:DF 4 "=f"))
12212 (clobber (match_scratch:DF 5 "=f"))
12213 (clobber (match_scratch:DF 6 "=f"))
12214 (clobber (match_scratch:DF 7 "=f"))
12215 (clobber (match_scratch:DF 8 "=f"))
12216 (clobber (match_scratch:DF 9 "=f"))
12217 (clobber (match_scratch:DF 10 "=f"))]
602ea4d3 12218 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
696e45ba 12219 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
de17c25f
DE		 12220 "#"
12221 "&& reload_completed"
12222 [(set (match_dup 3) (match_dup 13))
12223 (set (match_dup 4) (match_dup 14))
12224 (set (match_dup 9) (abs:DF (match_dup 5)))
12225 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12226 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12227 (label_ref (match_dup 11))
12228 (pc)))
12229 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12230 (set (pc) (label_ref (match_dup 12)))
12231 (match_dup 11)
12232 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12233 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12234 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12235 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12236 (match_dup 12)]
12237{
12238 REAL_VALUE_TYPE rv;
12239 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12240 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12241
12242 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12243 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12244 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12245 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12246 operands[11] = gen_label_rtx ();
12247 operands[12] = gen_label_rtx ();
12248 real_inf (&rv);
12249 operands[13] = force_const_mem (DFmode,
12250 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12251 operands[14] = force_const_mem (DFmode,
12252 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12253 DFmode));
12254 if (TARGET_TOC)
12255 {
12256 operands[13] = gen_const_mem (DFmode,
12257 create_TOC_reference (XEXP (operands[13], 0)));
12258 operands[14] = gen_const_mem (DFmode,
12259 create_TOC_reference (XEXP (operands[14], 0)));
12260 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12261 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12262 }
12263})
1fd4e8c1
RK		 12264\f
12265;; Now we have the scc insns. We can do some combinations because of the
12266;; way the machine works.
12267;;
12268;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 12269;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12270;; cases the insns below which don't use an intermediate CR field will
12271;; be used instead.
1fd4e8c1 12272(define_insn ""
cd2b37d9 12273 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12274 (match_operator:SI 1 "scc_comparison_operator"
12275 [(match_operand 2 "cc_reg_operand" "y")
12276 (const_int 0)]))]
12277 ""
2c4a9cff
DE		 12278 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12279 [(set (attr "type")
12280 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12281 (const_string "mfcrf")
12282 ]
12283 (const_string "mfcr")))
c1618c0c 12284 (set_attr "length" "8")])
1fd4e8c1 12285
423c1189 12286;; Same as above, but get the GT bit.
64022b5d 12287(define_insn "move_from_CR_gt_bit"
423c1189 12288 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
64022b5d 12289 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
c187a21f 12290 "TARGET_HARD_FLOAT && !TARGET_FPRS"
64022b5d 12291 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
423c1189 12292 [(set_attr "type" "mfcr")
c1618c0c 12293 (set_attr "length" "8")])
423c1189 12294
a3170dc6
AH		 12295;; Same as above, but get the OV/ORDERED bit.
12296(define_insn "move_from_CR_ov_bit"
12297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 12298 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 12299 "TARGET_ISEL"
b7053a3f 12300 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a 12301 [(set_attr "type" "mfcr")
c1618c0c 12302 (set_attr "length" "8")])
a3170dc6 12303
1fd4e8c1 12304(define_insn ""
9ebbca7d
GK		 12305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12306 (match_operator:DI 1 "scc_comparison_operator"
12307 [(match_operand 2 "cc_reg_operand" "y")
12308 (const_int 0)]))]
12309 "TARGET_POWERPC64"
2c4a9cff
DE		 12310 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12311 [(set (attr "type")
12312 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12313 (const_string "mfcrf")
12314 ]
12315 (const_string "mfcr")))
c1618c0c 12316 (set_attr "length" "8")])
9ebbca7d
GK		 12317
12318(define_insn ""
12319 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12320 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12321 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 12322 (const_int 0)])
12323 (const_int 0)))
9ebbca7d 12324 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 12325 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12326 "TARGET_32BIT"
9ebbca7d 12327 "@
2c4a9cff 12328 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 12329 #"
b19003d8 12330 [(set_attr "type" "delayed_compare")
c1618c0c 12331 (set_attr "length" "8,16")])
9ebbca7d
GK		 12332
12333(define_split
12334 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12335 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12336 [(match_operand 2 "cc_reg_operand" "")
12337 (const_int 0)])
12338 (const_int 0)))
12339 (set (match_operand:SI 3 "gpc_reg_operand" "")
12340 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12341 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12342 [(set (match_dup 3)
12343 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12344 (set (match_dup 0)
12345 (compare:CC (match_dup 3)
12346 (const_int 0)))]
12347 "")
1fd4e8c1
RK		 12348
12349(define_insn ""
cd2b37d9 12350 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12351 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12352 [(match_operand 2 "cc_reg_operand" "y")
12353 (const_int 0)])
12354 (match_operand:SI 3 "const_int_operand" "n")))]
12355 ""
12356 "*
12357{
12358 int is_bit = ccr_bit (operands[1], 1);
12359 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12360 int count;
12361
12362 if (is_bit >= put_bit)
12363 count = is_bit - put_bit;
12364 else
12365 count = 32 - (put_bit - is_bit);
12366
89e9f3a8
MM		 12367 operands[4] = GEN_INT (count);
12368 operands[5] = GEN_INT (put_bit);
1fd4e8c1 12369
2c4a9cff 12370 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 12371}"
2c4a9cff
DE		 12372 [(set (attr "type")
12373 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12374 (const_string "mfcrf")
12375 ]
12376 (const_string "mfcr")))
c1618c0c 12377 (set_attr "length" "8")])
1fd4e8c1
RK		 12378
12379(define_insn ""
9ebbca7d 12380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12381 (compare:CC
12382 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12383 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 12384 (const_int 0)])
9ebbca7d 12385 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 12386 (const_int 0)))
9ebbca7d 12387 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12388 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12389 (match_dup 3)))]
ce71f754 12390 ""
1fd4e8c1
RK		 12391 "*
12392{
12393 int is_bit = ccr_bit (operands[1], 1);
12394 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12395 int count;
12396
9ebbca7d
GK		 12397 /* Force split for non-cc0 compare. */
12398 if (which_alternative == 1)
12399 return \"#\";
12400
1fd4e8c1
RK		 12401 if (is_bit >= put_bit)
12402 count = is_bit - put_bit;
12403 else
12404 count = 32 - (put_bit - is_bit);
12405
89e9f3a8
MM		 12406 operands[5] = GEN_INT (count);
12407 operands[6] = GEN_INT (put_bit);
1fd4e8c1 12408
2c4a9cff 12409 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 12410}"
b19003d8 12411 [(set_attr "type" "delayed_compare")
c1618c0c 12412 (set_attr "length" "8,16")])
9ebbca7d
GK		 12413
12414(define_split
c921bad8 12415 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 12416 (compare:CC
12417 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12418 [(match_operand 2 "cc_reg_operand" "")
12419 (const_int 0)])
12420 (match_operand:SI 3 "const_int_operand" ""))
12421 (const_int 0)))
12422 (set (match_operand:SI 4 "gpc_reg_operand" "")
12423 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12424 (match_dup 3)))]
ce71f754 12425 "reload_completed"
9ebbca7d
GK		 12426 [(set (match_dup 4)
12427 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12428 (match_dup 3)))
12429 (set (match_dup 0)
12430 (compare:CC (match_dup 4)
12431 (const_int 0)))]
12432 "")
1fd4e8c1 12433
c5defebb
RK		 12434;; There is a 3 cycle delay between consecutive mfcr instructions
12435;; so it is useful to combine 2 scc instructions to use only one mfcr.
12436
12437(define_peephole
cd2b37d9 12438 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 12439 (match_operator:SI 1 "scc_comparison_operator"
12440 [(match_operand 2 "cc_reg_operand" "y")
12441 (const_int 0)]))
cd2b37d9 12442 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 12443 (match_operator:SI 4 "scc_comparison_operator"
12444 [(match_operand 5 "cc_reg_operand" "y")
12445 (const_int 0)]))]
309323c2 12446 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12447 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12448 [(set_attr "type" "mfcr")
c1618c0c 12449 (set_attr "length" "12")])
c5defebb 12450
9ebbca7d
GK		 12451(define_peephole
12452 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12453 (match_operator:DI 1 "scc_comparison_operator"
12454 [(match_operand 2 "cc_reg_operand" "y")
12455 (const_int 0)]))
12456 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12457 (match_operator:DI 4 "scc_comparison_operator"
12458 [(match_operand 5 "cc_reg_operand" "y")
12459 (const_int 0)]))]
309323c2 12460 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12461 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12462 [(set_attr "type" "mfcr")
c1618c0c 12463 (set_attr "length" "12")])
9ebbca7d 12464
1fd4e8c1
RK		 12465;; There are some scc insns that can be done directly, without a compare.
12466;; These are faster because they don't involve the communications between
12467;; the FXU and branch units. In fact, we will be replacing all of the
12468;; integer scc insns here or in the portable methods in emit_store_flag.
12469;;
12470;; Also support (neg (scc ..)) since that construct is used to replace
12471;; branches, (plus (scc ..) ..) since that construct is common and
12472;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12473;; cases where it is no more expensive than (neg (scc ..)).
12474
12475;; Have reload force a constant into a register for the simple insns that
12476;; otherwise won't accept constants. We do this because it is faster than
12477;; the cmp/mfcr sequence we would otherwise generate.
12478
e9441276
DE		 12479(define_mode_attr scc_eq_op2 [(SI "rKLI")
12480 (DI "rKJI")])
a260abc9 12481
e9441276
DE		 12482(define_insn_and_split "*eq<mode>"
12483 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12484 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
d0515b39 12485 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
27f0fe7f 12486 "!TARGET_POWER"
e9441276 12487 "#"
27f0fe7f 12488 "!TARGET_POWER"
d0515b39
DE		 12489 [(set (match_dup 0)
12490 (clz:GPR (match_dup 3)))
70ae0191 12491 (set (match_dup 0)
d0515b39 12492 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
70ae0191 12493 {
e9441276
DE		 12494 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12495 {
d0515b39
DE		 12496 /* Use output operand as intermediate. */
12497 operands[3] = operands[0];
12498
e9441276 12499 if (logical_operand (operands[2], <MODE>mode))
d0515b39 12500 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12501 gen_rtx_XOR (<MODE>mode,
12502 operands[1], operands[2])));
12503 else
d0515b39 12504 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12505 gen_rtx_PLUS (<MODE>mode, operands[1],
12506 negate_rtx (<MODE>mode,
12507 operands[2]))));
12508 }
12509 else
d0515b39 12510 operands[3] = operands[1];
9ebbca7d 12511
d0515b39 12512 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
e9441276 12513 })
a260abc9 12514
e9441276 12515(define_insn_and_split "*eq<mode>_compare"
d0515b39 12516 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
70ae0191 12517 (compare:CC
1fa5c709
DE		 12518 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12519 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
70ae0191 12520 (const_int 0)))
1fa5c709 12521 (set (match_operand:P 0 "gpc_reg_operand" "=r")
d0515b39 12522 (eq:P (match_dup 1) (match_dup 2)))]
27f0fe7f 12523 "!TARGET_POWER && optimize_size"
e9441276 12524 "#"
27f0fe7f 12525 "!TARGET_POWER && optimize_size"
d0515b39 12526 [(set (match_dup 0)
1fa5c709 12527 (clz:P (match_dup 4)))
d0515b39
DE		 12528 (parallel [(set (match_dup 3)
12529 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
70ae0191
DE		 12530 (const_int 0)))
12531 (set (match_dup 0)
d0515b39 12532 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
70ae0191 12533 {
e9441276
DE		 12534 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12535 {
d0515b39
DE		 12536 /* Use output operand as intermediate. */
12537 operands[4] = operands[0];
12538
e9441276
DE		 12539 if (logical_operand (operands[2], <MODE>mode))
12540 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12541 gen_rtx_XOR (<MODE>mode,
12542 operands[1], operands[2])));
12543 else
12544 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12545 gen_rtx_PLUS (<MODE>mode, operands[1],
12546 negate_rtx (<MODE>mode,
12547 operands[2]))));
12548 }
12549 else
12550 operands[4] = operands[1];
12551
d0515b39 12552 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
70ae0191
DE		 12553 })
12554
05f68097
DE		 12555(define_insn "*eqsi_power"
12556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12557 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12558 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12559 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12560 "TARGET_POWER"
12561 "@
12562 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12563 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12564 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12565 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12566 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12567 [(set_attr "type" "three,two,three,three,three")
12568 (set_attr "length" "12,8,12,12,12")])
12569
b19003d8
RK		 12570;; We have insns of the form shown by the first define_insn below. If
12571;; there is something inside the comparison operation, we must split it.
12572(define_split
12573 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12574 (plus:SI (match_operator 1 "comparison_operator"
12575 [(match_operand:SI 2 "" "")
12576 (match_operand:SI 3
12577 "reg_or_cint_operand" "")])
12578 (match_operand:SI 4 "gpc_reg_operand" "")))
12579 (clobber (match_operand:SI 5 "register_operand" ""))]
12580 "! gpc_reg_operand (operands[2], SImode)"
12581 [(set (match_dup 5) (match_dup 2))
12582 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12583 (match_dup 4)))])
1fd4e8c1 12584
297abd0d 12585(define_insn "*plus_eqsi"
5276df18 12586 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 12587 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
56fc483e 12588 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
5276df18 12589 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
59d6560b 12590 "TARGET_32BIT"
1fd4e8c1 12591 "@
5276df18
DE		 12592 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12593 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12594 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12595 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12596 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
943c15ed
DE		 12597 [(set_attr "type" "three,two,three,three,three")
12598 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1 12599
297abd0d 12600(define_insn "*compare_plus_eqsi"
9ebbca7d 12601 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12602 (compare:CC
1fd4e8c1 12603 (plus:SI
9ebbca7d 12604 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12605 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12606 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12607 (const_int 0)))
9ebbca7d 12608 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
297abd0d 12609 "TARGET_32BIT && optimize_size"
1fd4e8c1 12610 "@
ca7f5001 12611 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 12612 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 12613 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12614 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12615 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12616 #
12617 #
12618 #
12619 #
12620 #"
b19003d8 12621 [(set_attr "type" "compare")
9ebbca7d
GK		 12622 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12623
12624(define_split
12625 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12626 (compare:CC
12627 (plus:SI
12628 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12629 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12630 (match_operand:SI 3 "gpc_reg_operand" ""))
12631 (const_int 0)))
12632 (clobber (match_scratch:SI 4 ""))]
297abd0d 12633 "TARGET_32BIT && optimize_size && reload_completed"
9ebbca7d
GK		 12634 [(set (match_dup 4)
12635 (plus:SI (eq:SI (match_dup 1)
12636 (match_dup 2))
12637 (match_dup 3)))
12638 (set (match_dup 0)
12639 (compare:CC (match_dup 4)
12640 (const_int 0)))]
12641 "")
1fd4e8c1 12642
297abd0d 12643(define_insn "*plus_eqsi_compare"
0387639b 12644 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12645 (compare:CC
1fd4e8c1 12646 (plus:SI
9ebbca7d 12647 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12648 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12649 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12650 (const_int 0)))
0387639b
DE		 12651 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12652 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12653 "TARGET_32BIT && optimize_size"
1fd4e8c1 12654 "@
0387639b
DE		 12655 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12656 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12657 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12658 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12659 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12660 #
12661 #
12662 #
12663 #
12664 #"
12665 [(set_attr "type" "compare")
12666 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12667
12668(define_split
0387639b 12669 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12670 (compare:CC
12671 (plus:SI
12672 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12673 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12674 (match_operand:SI 3 "gpc_reg_operand" ""))
12675 (const_int 0)))
12676 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 12677 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12678 "TARGET_32BIT && optimize_size && reload_completed"
0387639b 12679 [(set (match_dup 0)
9ebbca7d 12680 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 12681 (set (match_dup 4)
9ebbca7d
GK		 12682 (compare:CC (match_dup 0)
12683 (const_int 0)))]
12684 "")
12685
d0515b39
DE		 12686(define_insn "*neg_eq0<mode>"
12687 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12688 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12689 (const_int 0))))]
59d6560b 12690 ""
d0515b39
DE		 12691 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12692 [(set_attr "type" "two")
12693 (set_attr "length" "8")])
12694
12695(define_insn_and_split "*neg_eq<mode>"
12696 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12697 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12698 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
59d6560b 12699 ""
d0515b39 12700 "#"
59d6560b 12701 ""
d0515b39
DE		 12702 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12703 {
12704 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12705 {
12706 /* Use output operand as intermediate. */
12707 operands[3] = operands[0];
12708
12709 if (logical_operand (operands[2], <MODE>mode))
12710 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12711 gen_rtx_XOR (<MODE>mode,
12712 operands[1], operands[2])));
12713 else
12714 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12715 gen_rtx_PLUS (<MODE>mode, operands[1],
12716 negate_rtx (<MODE>mode,
12717 operands[2]))));
12718 }
12719 else
12720 operands[3] = operands[1];
12721 })
1fd4e8c1 12722
ea9be077
MM		 12723;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12724;; since it nabs/sr is just as fast.
ce45ef46 12725(define_insn "*ne0si"
b4e95693 12726 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 12727 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12728 (const_int 31)))
12729 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 12730 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077 12731 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
943c15ed
DE		 12732 [(set_attr "type" "two")
12733 (set_attr "length" "8")])
ea9be077 12734
ce45ef46 12735(define_insn "*ne0di"
a260abc9
DE		 12736 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12737 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12738 (const_int 63)))
12739 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 12740 "TARGET_64BIT"
a260abc9 12741 "addic %2,%1,-1\;subfe %0,%2,%1"
943c15ed
DE		 12742 [(set_attr "type" "two")
12743 (set_attr "length" "8")])
a260abc9 12744
1fd4e8c1 12745;; This is what (plus (ne X (const_int 0)) Y) looks like.
297abd0d 12746(define_insn "*plus_ne0si"
cd2b37d9 12747 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 12748 (plus:SI (lshiftrt:SI
cd2b37d9 12749 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 12750 (const_int 31))
cd2b37d9 12751 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 12752 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 12753 "TARGET_32BIT"
ca7f5001 12754 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
943c15ed
DE		 12755 [(set_attr "type" "two")
12756 (set_attr "length" "8")])
1fd4e8c1 12757
297abd0d 12758(define_insn "*plus_ne0di"
a260abc9
DE		 12759 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12760 (plus:DI (lshiftrt:DI
12761 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12762 (const_int 63))
12763 (match_operand:DI 2 "gpc_reg_operand" "r")))
12764 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 12765 "TARGET_64BIT"
a260abc9 12766 "addic %3,%1,-1\;addze %0,%2"
943c15ed
DE		 12767 [(set_attr "type" "two")
12768 (set_attr "length" "8")])
a260abc9 12769
297abd0d 12770(define_insn "*compare_plus_ne0si"
9ebbca7d 12771 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12772 (compare:CC
12773 (plus:SI (lshiftrt:SI
9ebbca7d 12774 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12775 (const_int 31))
9ebbca7d 12776 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12777 (const_int 0)))
889b90a1
GK		 12778 (clobber (match_scratch:SI 3 "=&r,&r"))
12779 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 12780 "TARGET_32BIT"
9ebbca7d
GK		 12781 "@
12782 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12783 #"
b19003d8 12784 [(set_attr "type" "compare")
9ebbca7d
GK		 12785 (set_attr "length" "8,12")])
12786
12787(define_split
12788 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12789 (compare:CC
12790 (plus:SI (lshiftrt:SI
12791 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12792 (const_int 31))
12793 (match_operand:SI 2 "gpc_reg_operand" ""))
12794 (const_int 0)))
889b90a1
GK		 12795 (clobber (match_scratch:SI 3 ""))
12796 (clobber (match_scratch:SI 4 ""))]
683bdff7 12797 "TARGET_32BIT && reload_completed"
889b90a1 12798 [(parallel [(set (match_dup 3)
ce71f754
AM		 12799 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12800 (const_int 31))
12801 (match_dup 2)))
889b90a1 12802 (clobber (match_dup 4))])
9ebbca7d
GK		 12803 (set (match_dup 0)
12804 (compare:CC (match_dup 3)
12805 (const_int 0)))]
12806 "")
1fd4e8c1 12807
297abd0d 12808(define_insn "*compare_plus_ne0di"
9ebbca7d 12809 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12810 (compare:CC
12811 (plus:DI (lshiftrt:DI
9ebbca7d 12812 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12813 (const_int 63))
9ebbca7d 12814 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12815 (const_int 0)))
9ebbca7d 12816 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12817 "TARGET_64BIT"
9ebbca7d
GK		 12818 "@
12819 addic %3,%1,-1\;addze. %3,%2
12820 #"
a260abc9 12821 [(set_attr "type" "compare")
9ebbca7d
GK		 12822 (set_attr "length" "8,12")])
12823
12824(define_split
c921bad8 12825 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 12826 (compare:CC
12827 (plus:DI (lshiftrt:DI
12828 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12829 (const_int 63))
12830 (match_operand:DI 2 "gpc_reg_operand" ""))
12831 (const_int 0)))
12832 (clobber (match_scratch:DI 3 ""))]
683bdff7 12833 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12834 [(set (match_dup 3)
12835 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12836 (const_int 63))
12837 (match_dup 2)))
12838 (set (match_dup 0)
12839 (compare:CC (match_dup 3)
12840 (const_int 0)))]
12841 "")
a260abc9 12842
297abd0d 12843(define_insn "*plus_ne0si_compare"
9ebbca7d 12844 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12845 (compare:CC
12846 (plus:SI (lshiftrt:SI
9ebbca7d 12847 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12848 (const_int 31))
9ebbca7d 12849 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12850 (const_int 0)))
9ebbca7d 12851 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12852 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12853 (match_dup 2)))
9ebbca7d 12854 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 12855 "TARGET_32BIT"
9ebbca7d
GK		 12856 "@
12857 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12858 #"
b19003d8 12859 [(set_attr "type" "compare")
9ebbca7d
GK		 12860 (set_attr "length" "8,12")])
12861
12862(define_split
12863 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12864 (compare:CC
12865 (plus:SI (lshiftrt:SI
12866 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12867 (const_int 31))
12868 (match_operand:SI 2 "gpc_reg_operand" ""))
12869 (const_int 0)))
12870 (set (match_operand:SI 0 "gpc_reg_operand" "")
12871 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12872 (match_dup 2)))
12873 (clobber (match_scratch:SI 3 ""))]
683bdff7 12874 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12875 [(parallel [(set (match_dup 0)
12876 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12877 (match_dup 2)))
12878 (clobber (match_dup 3))])
12879 (set (match_dup 4)
12880 (compare:CC (match_dup 0)
12881 (const_int 0)))]
12882 "")
1fd4e8c1 12883
297abd0d 12884(define_insn "*plus_ne0di_compare"
9ebbca7d 12885 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12886 (compare:CC
12887 (plus:DI (lshiftrt:DI
9ebbca7d 12888 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12889 (const_int 63))
9ebbca7d 12890 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12891 (const_int 0)))
9ebbca7d 12892 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 12893 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12894 (match_dup 2)))
9ebbca7d 12895 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12896 "TARGET_64BIT"
9ebbca7d
GK		 12897 "@
12898 addic %3,%1,-1\;addze. %0,%2
12899 #"
a260abc9 12900 [(set_attr "type" "compare")
9ebbca7d
GK		 12901 (set_attr "length" "8,12")])
12902
12903(define_split
c921bad8 12904 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 12905 (compare:CC
12906 (plus:DI (lshiftrt:DI
12907 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12908 (const_int 63))
12909 (match_operand:DI 2 "gpc_reg_operand" ""))
12910 (const_int 0)))
12911 (set (match_operand:DI 0 "gpc_reg_operand" "")
12912 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12913 (match_dup 2)))
12914 (clobber (match_scratch:DI 3 ""))]
683bdff7 12915 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12916 [(parallel [(set (match_dup 0)
12917 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12918 (match_dup 2)))
12919 (clobber (match_dup 3))])
12920 (set (match_dup 4)
12921 (compare:CC (match_dup 0)
12922 (const_int 0)))]
12923 "")
a260abc9 12924
1fd4e8c1 12925(define_insn ""
cd2b37d9
RK		 12926 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12927 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 12928 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12929 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 12930 "TARGET_POWER"
1fd4e8c1 12931 "@
ca7f5001 12932 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 12933 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12934 [(set_attr "length" "12")])
1fd4e8c1
RK		 12935
12936(define_insn ""
9ebbca7d 12937 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12938 (compare:CC
9ebbca7d
GK		 12939 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12940 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 12941 (const_int 0)))
9ebbca7d 12942 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12943 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12944 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 12945 "TARGET_POWER"
1fd4e8c1 12946 "@
ca7f5001 12947 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 12948 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12949 #
12950 #"
12951 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12952 (set_attr "length" "12,12,16,16")])
12953
12954(define_split
12955 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12956 (compare:CC
12957 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12958 (match_operand:SI 2 "reg_or_short_operand" ""))
12959 (const_int 0)))
12960 (set (match_operand:SI 0 "gpc_reg_operand" "")
12961 (le:SI (match_dup 1) (match_dup 2)))
12962 (clobber (match_scratch:SI 3 ""))]
12963 "TARGET_POWER && reload_completed"
12964 [(parallel [(set (match_dup 0)
12965 (le:SI (match_dup 1) (match_dup 2)))
12966 (clobber (match_dup 3))])
12967 (set (match_dup 4)
12968 (compare:CC (match_dup 0)
12969 (const_int 0)))]
12970 "")
1fd4e8c1
RK		 12971
12972(define_insn ""
097657c3 12973 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12974 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12975 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 12976 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 12977 "TARGET_POWER"
1fd4e8c1 12978 "@
097657c3
AM		 12979 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12980 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 12981 [(set_attr "length" "12")])
1fd4e8c1
RK		 12982
12983(define_insn ""
9ebbca7d 12984 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12985 (compare:CC
9ebbca7d
GK		 12986 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12987 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12988 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12989 (const_int 0)))
9ebbca7d 12990 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 12991 "TARGET_POWER"
1fd4e8c1 12992 "@
ca7f5001 12993 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12994 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12995 #
12996 #"
b19003d8 12997 [(set_attr "type" "compare")
9ebbca7d
GK		 12998 (set_attr "length" "12,12,16,16")])
12999
13000(define_split
13001 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13002 (compare:CC
13003 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13004 (match_operand:SI 2 "reg_or_short_operand" ""))
13005 (match_operand:SI 3 "gpc_reg_operand" ""))
13006 (const_int 0)))
13007 (clobber (match_scratch:SI 4 ""))]
13008 "TARGET_POWER && reload_completed"
13009 [(set (match_dup 4)
13010 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 13011 (match_dup 3)))
9ebbca7d
GK		 13012 (set (match_dup 0)
13013 (compare:CC (match_dup 4)
13014 (const_int 0)))]
13015 "")
1fd4e8c1
RK		 13016
13017(define_insn ""
097657c3 13018 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13019 (compare:CC
9ebbca7d
GK		 13020 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13021 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13022 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13023 (const_int 0)))
097657c3
AM		 13024 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13025 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13026 "TARGET_POWER"
1fd4e8c1 13027 "@
097657c3
AM		 13028 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13029 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 13030 #
13031 #"
b19003d8 13032 [(set_attr "type" "compare")
9ebbca7d
GK		 13033 (set_attr "length" "12,12,16,16")])
13034
13035(define_split
097657c3 13036 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13037 (compare:CC
13038 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13039 (match_operand:SI 2 "reg_or_short_operand" ""))
13040 (match_operand:SI 3 "gpc_reg_operand" ""))
13041 (const_int 0)))
13042 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13043 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13044 "TARGET_POWER && reload_completed"
097657c3 13045 [(set (match_dup 0)
9ebbca7d 13046 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13047 (set (match_dup 4)
9ebbca7d
GK		 13048 (compare:CC (match_dup 0)
13049 (const_int 0)))]
13050 "")
1fd4e8c1
RK		 13051
13052(define_insn ""
cd2b37d9
RK		 13053 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13054 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13055 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 13056 "TARGET_POWER"
1fd4e8c1 13057 "@
ca7f5001
RK		 13058 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13059 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13060 [(set_attr "length" "12")])
1fd4e8c1 13061
a2dba291
DE		 13062(define_insn "*leu<mode>"
13063 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13064 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13065 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13066 ""
ca7f5001 13067 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 13068 [(set_attr "type" "three")
13069 (set_attr "length" "12")])
1fd4e8c1 13070
a2dba291 13071(define_insn "*leu<mode>_compare"
9ebbca7d 13072 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13073 (compare:CC
a2dba291
DE		 13074 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13075 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13076 (const_int 0)))
a2dba291
DE		 13077 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13078 (leu:P (match_dup 1) (match_dup 2)))]
13079 ""
9ebbca7d
GK		 13080 "@
13081 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13082 #"
b19003d8 13083 [(set_attr "type" "compare")
9ebbca7d
GK		 13084 (set_attr "length" "12,16")])
13085
13086(define_split
13087 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13088 (compare:CC
a2dba291
DE		 13089 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13090 (match_operand:P 2 "reg_or_short_operand" ""))
9ebbca7d 13091 (const_int 0)))
a2dba291
DE		 13092 (set (match_operand:P 0 "gpc_reg_operand" "")
13093 (leu:P (match_dup 1) (match_dup 2)))]
13094 "reload_completed"
9ebbca7d 13095 [(set (match_dup 0)
a2dba291 13096 (leu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 13097 (set (match_dup 3)
13098 (compare:CC (match_dup 0)
13099 (const_int 0)))]
13100 "")
1fd4e8c1 13101
a2dba291
DE		 13102(define_insn "*plus_leu<mode>"
13103 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13104 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13105 (match_operand:P 2 "reg_or_short_operand" "rI"))
13106 (match_operand:P 3 "gpc_reg_operand" "r")))]
13107 ""
80103f96 13108 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
943c15ed
DE		 13109 [(set_attr "type" "two")
13110 (set_attr "length" "8")])
1fd4e8c1
RK		 13111
13112(define_insn ""
9ebbca7d 13113 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13114 (compare:CC
9ebbca7d
GK		 13115 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13116 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13117 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13118 (const_int 0)))
9ebbca7d 13119 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 13120 "TARGET_32BIT"
9ebbca7d
GK		 13121 "@
13122 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13123 #"
b19003d8 13124 [(set_attr "type" "compare")
9ebbca7d
GK		 13125 (set_attr "length" "8,12")])
13126
13127(define_split
13128 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13129 (compare:CC
13130 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13131 (match_operand:SI 2 "reg_or_short_operand" ""))
13132 (match_operand:SI 3 "gpc_reg_operand" ""))
13133 (const_int 0)))
13134 (clobber (match_scratch:SI 4 ""))]
683bdff7 13135 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13136 [(set (match_dup 4)
13137 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13138 (match_dup 3)))
13139 (set (match_dup 0)
13140 (compare:CC (match_dup 4)
13141 (const_int 0)))]
13142 "")
1fd4e8c1
RK		 13143
13144(define_insn ""
097657c3 13145 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13146 (compare:CC
9ebbca7d
GK		 13147 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13148 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13149 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13150 (const_int 0)))
097657c3
AM		 13151 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13152 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13153 "TARGET_32BIT"
9ebbca7d 13154 "@
097657c3 13155 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 13156 #"
b19003d8 13157 [(set_attr "type" "compare")
9ebbca7d
GK		 13158 (set_attr "length" "8,12")])
13159
13160(define_split
097657c3 13161 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13162 (compare:CC
13163 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13164 (match_operand:SI 2 "reg_or_short_operand" ""))
13165 (match_operand:SI 3 "gpc_reg_operand" ""))
13166 (const_int 0)))
13167 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13168 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13169 "TARGET_32BIT && reload_completed"
097657c3 13170 [(set (match_dup 0)
9ebbca7d 13171 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13172 (set (match_dup 4)
9ebbca7d
GK		 13173 (compare:CC (match_dup 0)
13174 (const_int 0)))]
13175 "")
1fd4e8c1 13176
a2dba291
DE		 13177(define_insn "*neg_leu<mode>"
13178 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13179 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13180 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13181 ""
ca7f5001 13182 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
943c15ed
DE		 13183 [(set_attr "type" "three")
13184 (set_attr "length" "12")])
1fd4e8c1 13185
a2dba291
DE		 13186(define_insn "*and_neg_leu<mode>"
13187 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13188 (and:P (neg:P
13189 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13190 (match_operand:P 2 "reg_or_short_operand" "rI")))
13191 (match_operand:P 3 "gpc_reg_operand" "r")))]
13192 ""
097657c3 13193 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 13194 [(set_attr "type" "three")
13195 (set_attr "length" "12")])
1fd4e8c1
RK		 13196
13197(define_insn ""
9ebbca7d 13198 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 13199 (compare:CC
13200 (and:SI (neg:SI
9ebbca7d
GK		 13201 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13202 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13203 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13204 (const_int 0)))
9ebbca7d 13205 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 13206 "TARGET_32BIT"
9ebbca7d
GK		 13207 "@
13208 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13209 #"
13210 [(set_attr "type" "compare")
13211 (set_attr "length" "12,16")])
13212
13213(define_split
13214 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13215 (compare:CC
13216 (and:SI (neg:SI
13217 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13218 (match_operand:SI 2 "reg_or_short_operand" "")))
13219 (match_operand:SI 3 "gpc_reg_operand" ""))
13220 (const_int 0)))
13221 (clobber (match_scratch:SI 4 ""))]
683bdff7 13222 "TARGET_32BIT && reload_completed"
9ebbca7d 13223 [(set (match_dup 4)
097657c3
AM		 13224 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13225 (match_dup 3)))
9ebbca7d
GK		 13226 (set (match_dup 0)
13227 (compare:CC (match_dup 4)
13228 (const_int 0)))]
13229 "")
1fd4e8c1
RK		 13230
13231(define_insn ""
097657c3 13232 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 13233 (compare:CC
13234 (and:SI (neg:SI
9ebbca7d
GK		 13235 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13236 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13237 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13238 (const_int 0)))
097657c3
AM		 13239 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13240 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13241 "TARGET_32BIT"
9ebbca7d 13242 "@
097657c3 13243 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 13244 #"
b19003d8 13245 [(set_attr "type" "compare")
9ebbca7d
GK		 13246 (set_attr "length" "12,16")])
13247
13248(define_split
097657c3 13249 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13250 (compare:CC
13251 (and:SI (neg:SI
13252 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13253 (match_operand:SI 2 "reg_or_short_operand" "")))
13254 (match_operand:SI 3 "gpc_reg_operand" ""))
13255 (const_int 0)))
13256 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13257 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13258 "TARGET_32BIT && reload_completed"
097657c3
AM		 13259 [(set (match_dup 0)
13260 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13261 (match_dup 3)))
13262 (set (match_dup 4)
9ebbca7d
GK		 13263 (compare:CC (match_dup 0)
13264 (const_int 0)))]
13265 "")
1fd4e8c1
RK		 13266
13267(define_insn ""
cd2b37d9
RK		 13268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13269 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13270 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 13271 "TARGET_POWER"
7f340546 13272 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13273 [(set_attr "length" "12")])
1fd4e8c1
RK		 13274
13275(define_insn ""
9ebbca7d 13276 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13277 (compare:CC
9ebbca7d
GK		 13278 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13279 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13280 (const_int 0)))
9ebbca7d 13281 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13282 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13283 "TARGET_POWER"
9ebbca7d
GK		 13284 "@
13285 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13286 #"
29ae5b89 13287 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13288 (set_attr "length" "12,16")])
13289
13290(define_split
13291 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13292 (compare:CC
13293 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13294 (match_operand:SI 2 "reg_or_short_operand" ""))
13295 (const_int 0)))
13296 (set (match_operand:SI 0 "gpc_reg_operand" "")
13297 (lt:SI (match_dup 1) (match_dup 2)))]
13298 "TARGET_POWER && reload_completed"
13299 [(set (match_dup 0)
13300 (lt:SI (match_dup 1) (match_dup 2)))
13301 (set (match_dup 3)
13302 (compare:CC (match_dup 0)
13303 (const_int 0)))]
13304 "")
1fd4e8c1
RK		 13305
13306(define_insn ""
097657c3 13307 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13308 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13309 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13310 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13311 "TARGET_POWER"
097657c3 13312 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13313 [(set_attr "length" "12")])
1fd4e8c1
RK		 13314
13315(define_insn ""
9ebbca7d 13316 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13317 (compare:CC
9ebbca7d
GK		 13318 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13319 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13320 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13321 (const_int 0)))
9ebbca7d 13322 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13323 "TARGET_POWER"
9ebbca7d
GK		 13324 "@
13325 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13326 #"
b19003d8 13327 [(set_attr "type" "compare")
9ebbca7d
GK		 13328 (set_attr "length" "12,16")])
13329
13330(define_split
13331 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13332 (compare:CC
13333 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13334 (match_operand:SI 2 "reg_or_short_operand" ""))
13335 (match_operand:SI 3 "gpc_reg_operand" ""))
13336 (const_int 0)))
13337 (clobber (match_scratch:SI 4 ""))]
13338 "TARGET_POWER && reload_completed"
13339 [(set (match_dup 4)
13340 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 13341 (match_dup 3)))
9ebbca7d
GK		 13342 (set (match_dup 0)
13343 (compare:CC (match_dup 4)
13344 (const_int 0)))]
13345 "")
1fd4e8c1
RK		 13346
13347(define_insn ""
097657c3 13348 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13349 (compare:CC
9ebbca7d
GK		 13350 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13351 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13352 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13353 (const_int 0)))
097657c3
AM		 13354 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13355 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13356 "TARGET_POWER"
9ebbca7d 13357 "@
097657c3 13358 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13359 #"
b19003d8 13360 [(set_attr "type" "compare")
9ebbca7d
GK		 13361 (set_attr "length" "12,16")])
13362
13363(define_split
097657c3 13364 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13365 (compare:CC
13366 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13367 (match_operand:SI 2 "reg_or_short_operand" ""))
13368 (match_operand:SI 3 "gpc_reg_operand" ""))
13369 (const_int 0)))
13370 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13371 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13372 "TARGET_POWER && reload_completed"
097657c3 13373 [(set (match_dup 0)
9ebbca7d 13374 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13375 (set (match_dup 4)
9ebbca7d
GK		 13376 (compare:CC (match_dup 0)
13377 (const_int 0)))]
13378 "")
1fd4e8c1
RK		 13379
13380(define_insn ""
cd2b37d9
RK		 13381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13382 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13383 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13384 "TARGET_POWER"
13385 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13386 [(set_attr "length" "12")])
1fd4e8c1 13387
ce45ef46
DE		 13388(define_insn_and_split "*ltu<mode>"
13389 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13390 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13391 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13392 ""
c0600ecd 13393 "#"
ce45ef46
DE		 13394 ""
13395 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13396 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13397 "")
1fd4e8c1 13398
1e24ce83 13399(define_insn_and_split "*ltu<mode>_compare"
9ebbca7d 13400 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13401 (compare:CC
a2dba291
DE		 13402 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13403 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13404 (const_int 0)))
a2dba291
DE		 13405 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13406 (ltu:P (match_dup 1) (match_dup 2)))]
13407 ""
1e24ce83
DE		 13408 "#"
13409 ""
13410 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13411 (parallel [(set (match_dup 3)
13412 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13413 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13414 "")
1fd4e8c1 13415
a2dba291
DE		 13416(define_insn_and_split "*plus_ltu<mode>"
13417 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13418 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13419 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
1e24ce83 13420 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
a2dba291 13421 ""
c0600ecd 13422 "#"
04fa46cf 13423 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13424 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13425 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13426 "")
1fd4e8c1 13427
1e24ce83 13428(define_insn_and_split "*plus_ltu<mode>_compare"
097657c3 13429 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13430 (compare:CC
1e24ce83
DE		 13431 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13432 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13433 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13434 (const_int 0)))
1e24ce83
DE		 13435 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13436 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13437 ""
13438 "#"
13439 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13440 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13441 (parallel [(set (match_dup 4)
13442 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13443 (const_int 0)))
13444 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13445 "")
1fd4e8c1 13446
ce45ef46
DE		 13447(define_insn "*neg_ltu<mode>"
13448 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13449 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13450 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13451 ""
c0600ecd
DE		 13452 "@
13453 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13454 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
943c15ed 13455 [(set_attr "type" "two")
c0600ecd 13456 (set_attr "length" "8")])
1fd4e8c1
RK		 13457
13458(define_insn ""
cd2b37d9
RK		 13459 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13460 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 13461 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13462 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 13463 "TARGET_POWER"
13464 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 13465 [(set_attr "length" "12")])
1fd4e8c1 13466
9ebbca7d
GK		 13467(define_insn ""
13468 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13469 (compare:CC
9ebbca7d
GK		 13470 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13471 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13472 (const_int 0)))
9ebbca7d 13473 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13474 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 13475 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 13476 "TARGET_POWER"
9ebbca7d
GK		 13477 "@
13478 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13479 #"
13480 [(set_attr "type" "compare")
13481 (set_attr "length" "12,16")])
13482
13483(define_split
13484 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13485 (compare:CC
13486 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13487 (match_operand:SI 2 "reg_or_short_operand" ""))
13488 (const_int 0)))
13489 (set (match_operand:SI 0 "gpc_reg_operand" "")
13490 (ge:SI (match_dup 1) (match_dup 2)))
13491 (clobber (match_scratch:SI 3 ""))]
13492 "TARGET_POWER && reload_completed"
13493 [(parallel [(set (match_dup 0)
097657c3
AM		 13494 (ge:SI (match_dup 1) (match_dup 2)))
13495 (clobber (match_dup 3))])
9ebbca7d
GK		 13496 (set (match_dup 4)
13497 (compare:CC (match_dup 0)
13498 (const_int 0)))]
13499 "")
13500
1fd4e8c1 13501(define_insn ""
097657c3 13502 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13503 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13504 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13505 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13506 "TARGET_POWER"
097657c3 13507 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 13508 [(set_attr "length" "12")])
1fd4e8c1
RK		 13509
13510(define_insn ""
9ebbca7d 13511 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13512 (compare:CC
9ebbca7d
GK		 13513 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13514 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13515 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13516 (const_int 0)))
9ebbca7d 13517 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13518 "TARGET_POWER"
9ebbca7d
GK		 13519 "@
13520 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13521 #"
b19003d8 13522 [(set_attr "type" "compare")
9ebbca7d
GK		 13523 (set_attr "length" "12,16")])
13524
13525(define_split
13526 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13527 (compare:CC
13528 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13529 (match_operand:SI 2 "reg_or_short_operand" ""))
13530 (match_operand:SI 3 "gpc_reg_operand" ""))
13531 (const_int 0)))
13532 (clobber (match_scratch:SI 4 ""))]
13533 "TARGET_POWER && reload_completed"
13534 [(set (match_dup 4)
13535 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 13536 (match_dup 3)))
9ebbca7d
GK		 13537 (set (match_dup 0)
13538 (compare:CC (match_dup 4)
13539 (const_int 0)))]
13540 "")
1fd4e8c1
RK		 13541
13542(define_insn ""
097657c3 13543 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13544 (compare:CC
9ebbca7d
GK		 13545 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13546 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13547 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13548 (const_int 0)))
097657c3
AM		 13549 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13550 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13551 "TARGET_POWER"
9ebbca7d 13552 "@
097657c3 13553 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 13554 #"
b19003d8 13555 [(set_attr "type" "compare")
9ebbca7d
GK		 13556 (set_attr "length" "12,16")])
13557
13558(define_split
097657c3 13559 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13560 (compare:CC
13561 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13562 (match_operand:SI 2 "reg_or_short_operand" ""))
13563 (match_operand:SI 3 "gpc_reg_operand" ""))
13564 (const_int 0)))
13565 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13566 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13567 "TARGET_POWER && reload_completed"
097657c3 13568 [(set (match_dup 0)
9ebbca7d 13569 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13570 (set (match_dup 4)
9ebbca7d
GK		 13571 (compare:CC (match_dup 0)
13572 (const_int 0)))]
13573 "")
1fd4e8c1
RK		 13574
13575(define_insn ""
cd2b37d9
RK		 13576 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13577 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13578 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13579 "TARGET_POWER"
13580 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 13581 [(set_attr "length" "12")])
1fd4e8c1 13582
a2dba291
DE		 13583(define_insn "*geu<mode>"
13584 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13585 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13586 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13587 ""
1fd4e8c1 13588 "@
ca7f5001
RK		 13589 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13590 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 13591 [(set_attr "type" "three")
13592 (set_attr "length" "12")])
1fd4e8c1 13593
a2dba291 13594(define_insn "*geu<mode>_compare"
9ebbca7d 13595 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13596 (compare:CC
a2dba291
DE		 13597 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13598 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13599 (const_int 0)))
a2dba291
DE		 13600 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13601 (geu:P (match_dup 1) (match_dup 2)))]
13602 ""
1fd4e8c1 13603 "@
ca7f5001 13604 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 13605 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13606 #
13607 #"
b19003d8 13608 [(set_attr "type" "compare")
9ebbca7d
GK		 13609 (set_attr "length" "12,12,16,16")])
13610
13611(define_split
c921bad8 13612 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d 13613 (compare:CC
a2dba291
DE		 13614 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13615 (match_operand:P 2 "reg_or_neg_short_operand" ""))
9ebbca7d 13616 (const_int 0)))
a2dba291
DE		 13617 (set (match_operand:P 0 "gpc_reg_operand" "")
13618 (geu:P (match_dup 1) (match_dup 2)))]
13619 "reload_completed"
9ebbca7d 13620 [(set (match_dup 0)
a2dba291 13621 (geu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 13622 (set (match_dup 3)
13623 (compare:CC (match_dup 0)
13624 (const_int 0)))]
13625 "")
f9562f27 13626
a2dba291
DE		 13627(define_insn "*plus_geu<mode>"
13628 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13629 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13630 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13631 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13632 ""
1fd4e8c1 13633 "@
80103f96
FS		 13634 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13635 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
943c15ed
DE		 13636 [(set_attr "type" "two")
13637 (set_attr "length" "8")])
1fd4e8c1
RK		 13638
13639(define_insn ""
9ebbca7d 13640 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13641 (compare:CC
9ebbca7d
GK		 13642 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13643 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13644 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13645 (const_int 0)))
9ebbca7d 13646 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13647 "TARGET_32BIT"
1fd4e8c1 13648 "@
ca7f5001 13649 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13650 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13651 #
13652 #"
b19003d8 13653 [(set_attr "type" "compare")
9ebbca7d
GK		 13654 (set_attr "length" "8,8,12,12")])
13655
13656(define_split
13657 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13658 (compare:CC
13659 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13660 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13661 (match_operand:SI 3 "gpc_reg_operand" ""))
13662 (const_int 0)))
13663 (clobber (match_scratch:SI 4 ""))]
683bdff7 13664 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13665 [(set (match_dup 4)
13666 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13667 (match_dup 3)))
13668 (set (match_dup 0)
13669 (compare:CC (match_dup 4)
13670 (const_int 0)))]
13671 "")
1fd4e8c1
RK		 13672
13673(define_insn ""
097657c3 13674 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13675 (compare:CC
9ebbca7d
GK		 13676 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13677 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13678 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13679 (const_int 0)))
097657c3
AM		 13680 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13681 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13682 "TARGET_32BIT"
1fd4e8c1 13683 "@
097657c3
AM		 13684 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13685 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 13686 #
13687 #"
b19003d8 13688 [(set_attr "type" "compare")
9ebbca7d
GK		 13689 (set_attr "length" "8,8,12,12")])
13690
13691(define_split
097657c3 13692 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13693 (compare:CC
13694 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13695 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13696 (match_operand:SI 3 "gpc_reg_operand" ""))
13697 (const_int 0)))
13698 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13699 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13700 "TARGET_32BIT && reload_completed"
097657c3 13701 [(set (match_dup 0)
9ebbca7d 13702 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13703 (set (match_dup 4)
9ebbca7d
GK		 13704 (compare:CC (match_dup 0)
13705 (const_int 0)))]
13706 "")
1fd4e8c1 13707
a2dba291
DE		 13708(define_insn "*neg_geu<mode>"
13709 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13710 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13711 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13712 ""
1fd4e8c1 13713 "@
ca7f5001 13714 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 13715 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
943c15ed
DE		 13716 [(set_attr "type" "three")
13717 (set_attr "length" "12")])
1fd4e8c1 13718
a2dba291
DE		 13719(define_insn "*and_neg_geu<mode>"
13720 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13721 (and:P (neg:P
13722 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13723 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13724 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13725 ""
1fd4e8c1 13726 "@
097657c3
AM		 13727 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13728 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 13729 [(set_attr "type" "three")
13730 (set_attr "length" "12")])
1fd4e8c1
RK		 13731
13732(define_insn ""
9ebbca7d 13733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13734 (compare:CC
13735 (and:SI (neg:SI
9ebbca7d
GK		 13736 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13737 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13738 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13739 (const_int 0)))
9ebbca7d 13740 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13741 "TARGET_32BIT"
1fd4e8c1 13742 "@
ca7f5001 13743 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 13744 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13745 #
13746 #"
b19003d8 13747 [(set_attr "type" "compare")
9ebbca7d
GK		 13748 (set_attr "length" "12,12,16,16")])
13749
13750(define_split
13751 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13752 (compare:CC
13753 (and:SI (neg:SI
13754 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13755 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13756 (match_operand:SI 3 "gpc_reg_operand" ""))
13757 (const_int 0)))
13758 (clobber (match_scratch:SI 4 ""))]
683bdff7 13759 "TARGET_32BIT && reload_completed"
9ebbca7d 13760 [(set (match_dup 4)
097657c3
AM		 13761 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13762 (match_dup 3)))
9ebbca7d
GK		 13763 (set (match_dup 0)
13764 (compare:CC (match_dup 4)
13765 (const_int 0)))]
13766 "")
1fd4e8c1
RK		 13767
13768(define_insn ""
097657c3 13769 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13770 (compare:CC
13771 (and:SI (neg:SI
9ebbca7d
GK		 13772 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13773 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13774 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13775 (const_int 0)))
097657c3
AM		 13776 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13777 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13778 "TARGET_32BIT"
1fd4e8c1 13779 "@
097657c3
AM		 13780 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13781 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 13782 #
13783 #"
b19003d8 13784 [(set_attr "type" "compare")
9ebbca7d
GK		 13785 (set_attr "length" "12,12,16,16")])
13786
13787(define_split
097657c3 13788 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13789 (compare:CC
13790 (and:SI (neg:SI
13791 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13792 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13793 (match_operand:SI 3 "gpc_reg_operand" ""))
13794 (const_int 0)))
13795 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13796 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13797 "TARGET_32BIT && reload_completed"
097657c3 13798 [(set (match_dup 0)
9ebbca7d 13799 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 13800 (set (match_dup 4)
9ebbca7d
GK		 13801 (compare:CC (match_dup 0)
13802 (const_int 0)))]
13803 "")
1fd4e8c1 13804
1fd4e8c1 13805(define_insn ""
cd2b37d9
RK		 13806 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13807 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13808 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 13809 "TARGET_POWER"
13810 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13811 [(set_attr "length" "12")])
1fd4e8c1
RK		 13812
13813(define_insn ""
9ebbca7d 13814 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13815 (compare:CC
9ebbca7d
GK		 13816 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13817 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 13818 (const_int 0)))
9ebbca7d 13819 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13820 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13821 "TARGET_POWER"
9ebbca7d
GK		 13822 "@
13823 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13824 #"
29ae5b89 13825 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13826 (set_attr "length" "12,16")])
13827
13828(define_split
13829 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13830 (compare:CC
13831 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13832 (match_operand:SI 2 "reg_or_short_operand" ""))
13833 (const_int 0)))
13834 (set (match_operand:SI 0 "gpc_reg_operand" "")
13835 (gt:SI (match_dup 1) (match_dup 2)))]
13836 "TARGET_POWER && reload_completed"
13837 [(set (match_dup 0)
13838 (gt:SI (match_dup 1) (match_dup 2)))
13839 (set (match_dup 3)
13840 (compare:CC (match_dup 0)
13841 (const_int 0)))]
13842 "")
1fd4e8c1 13843
d0515b39 13844(define_insn "*plus_gt0<mode>"
a2dba291
DE		 13845 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13846 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13847 (const_int 0))
13848 (match_operand:P 2 "gpc_reg_operand" "r")))]
13849 ""
80103f96 13850 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
943c15ed
DE		 13851 [(set_attr "type" "three")
13852 (set_attr "length" "12")])
1fd4e8c1
RK		 13853
13854(define_insn ""
9ebbca7d 13855 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13856 (compare:CC
9ebbca7d 13857 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13858 (const_int 0))
9ebbca7d 13859 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 13860 (const_int 0)))
9ebbca7d 13861 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 13862 "TARGET_32BIT"
9ebbca7d
GK		 13863 "@
13864 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13865 #"
b19003d8 13866 [(set_attr "type" "compare")
9ebbca7d
GK		 13867 (set_attr "length" "12,16")])
13868
13869(define_split
13870 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13871 (compare:CC
13872 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13873 (const_int 0))
13874 (match_operand:SI 2 "gpc_reg_operand" ""))
13875 (const_int 0)))
13876 (clobber (match_scratch:SI 3 ""))]
683bdff7 13877 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13878 [(set (match_dup 3)
13879 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13880 (match_dup 2)))
13881 (set (match_dup 0)
13882 (compare:CC (match_dup 3)
13883 (const_int 0)))]
13884 "")
1fd4e8c1 13885
f9562f27 13886(define_insn ""
9ebbca7d 13887 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 13888 (compare:CC
9ebbca7d 13889 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13890 (const_int 0))
9ebbca7d 13891 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13892 (const_int 0)))
9ebbca7d 13893 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 13894 "TARGET_64BIT"
9ebbca7d
GK		 13895 "@
13896 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13897 #"
f9562f27 13898 [(set_attr "type" "compare")
9ebbca7d
GK		 13899 (set_attr "length" "12,16")])
13900
13901(define_split
c921bad8 13902 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 13903 (compare:CC
13904 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13905 (const_int 0))
13906 (match_operand:DI 2 "gpc_reg_operand" ""))
13907 (const_int 0)))
13908 (clobber (match_scratch:DI 3 ""))]
683bdff7 13909 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13910 [(set (match_dup 3)
13911 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 13912 (match_dup 2)))
9ebbca7d
GK		 13913 (set (match_dup 0)
13914 (compare:CC (match_dup 3)
13915 (const_int 0)))]
13916 "")
f9562f27 13917
1fd4e8c1 13918(define_insn ""
097657c3 13919 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 13920 (compare:CC
13921 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13922 (const_int 0))
13923 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13924 (const_int 0)))
097657c3
AM		 13925 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13926 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13927 "TARGET_32BIT"
9ebbca7d 13928 "@
097657c3 13929 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 13930 #"
13931 [(set_attr "type" "compare")
13932 (set_attr "length" "12,16")])
13933
13934(define_split
097657c3 13935 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 13936 (compare:CC
9ebbca7d 13937 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 13938 (const_int 0))
9ebbca7d 13939 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 13940 (const_int 0)))
9ebbca7d 13941 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13942 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13943 "TARGET_32BIT && reload_completed"
097657c3 13944 [(set (match_dup 0)
9ebbca7d 13945 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13946 (set (match_dup 3)
9ebbca7d
GK		 13947 (compare:CC (match_dup 0)
13948 (const_int 0)))]
13949 "")
1fd4e8c1 13950
f9562f27 13951(define_insn ""
097657c3 13952 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13953 (compare:CC
9ebbca7d 13954 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13955 (const_int 0))
9ebbca7d 13956 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13957 (const_int 0)))
097657c3
AM		 13958 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13959 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13960 "TARGET_64BIT"
9ebbca7d 13961 "@
097657c3 13962 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 13963 #"
f9562f27 13964 [(set_attr "type" "compare")
9ebbca7d
GK		 13965 (set_attr "length" "12,16")])
13966
13967(define_split
c921bad8 13968 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 13969 (compare:CC
13970 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13971 (const_int 0))
13972 (match_operand:DI 2 "gpc_reg_operand" ""))
13973 (const_int 0)))
13974 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13975 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13976 "TARGET_64BIT && reload_completed"
097657c3 13977 [(set (match_dup 0)
9ebbca7d 13978 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13979 (set (match_dup 3)
9ebbca7d
GK		 13980 (compare:CC (match_dup 0)
13981 (const_int 0)))]
13982 "")
f9562f27 13983
1fd4e8c1 13984(define_insn ""
097657c3 13985 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13986 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13987 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 13988 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13989 "TARGET_POWER"
097657c3 13990 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13991 [(set_attr "length" "12")])
1fd4e8c1
RK		 13992
13993(define_insn ""
9ebbca7d 13994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13995 (compare:CC
9ebbca7d
GK		 13996 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13997 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13998 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13999 (const_int 0)))
9ebbca7d 14000 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 14001 "TARGET_POWER"
9ebbca7d
GK		 14002 "@
14003 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14004 #"
b19003d8 14005 [(set_attr "type" "compare")
9ebbca7d
GK		 14006 (set_attr "length" "12,16")])
14007
14008(define_split
14009 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14010 (compare:CC
14011 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14012 (match_operand:SI 2 "reg_or_short_operand" ""))
14013 (match_operand:SI 3 "gpc_reg_operand" ""))
14014 (const_int 0)))
14015 (clobber (match_scratch:SI 4 ""))]
14016 "TARGET_POWER && reload_completed"
14017 [(set (match_dup 4)
097657c3 14018 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 14019 (set (match_dup 0)
14020 (compare:CC (match_dup 4)
14021 (const_int 0)))]
14022 "")
1fd4e8c1
RK		 14023
14024(define_insn ""
097657c3 14025 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 14026 (compare:CC
9ebbca7d
GK		 14027 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14028 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14029 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 14030 (const_int 0)))
097657c3
AM		 14031 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14032 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 14033 "TARGET_POWER"
9ebbca7d 14034 "@
097657c3 14035 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 14036 #"
b19003d8 14037 [(set_attr "type" "compare")
9ebbca7d
GK		 14038 (set_attr "length" "12,16")])
14039
14040(define_split
097657c3 14041 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 14042 (compare:CC
14043 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14044 (match_operand:SI 2 "reg_or_short_operand" ""))
14045 (match_operand:SI 3 "gpc_reg_operand" ""))
14046 (const_int 0)))
14047 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 14048 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 14049 "TARGET_POWER && reload_completed"
097657c3 14050 [(set (match_dup 0)
9ebbca7d 14051 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 14052 (set (match_dup 4)
9ebbca7d
GK		 14053 (compare:CC (match_dup 0)
14054 (const_int 0)))]
14055 "")
1fd4e8c1 14056
1fd4e8c1 14057(define_insn ""
cd2b37d9
RK		 14058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14059 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 14060 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 14061 "TARGET_POWER"
14062 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 14063 [(set_attr "length" "12")])
1fd4e8c1 14064
ce45ef46
DE		 14065(define_insn_and_split "*gtu<mode>"
14066 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14067 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14068 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14069 ""
c0600ecd 14070 "#"
ce45ef46
DE		 14071 ""
14072 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14073 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 14074 "")
f9562f27 14075
1e24ce83 14076(define_insn_and_split "*gtu<mode>_compare"
9ebbca7d 14077 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 14078 (compare:CC
a2dba291
DE		 14079 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14080 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 14081 (const_int 0)))
a2dba291
DE		 14082 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14083 (gtu:P (match_dup 1) (match_dup 2)))]
14084 ""
1e24ce83
DE		 14085 "#"
14086 ""
14087 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14088 (parallel [(set (match_dup 3)
14089 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14090 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 14091 "")
f9562f27 14092
1e24ce83 14093(define_insn_and_split "*plus_gtu<mode>"
a2dba291
DE		 14094 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14095 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14096 (match_operand:P 2 "reg_or_short_operand" "rI"))
14097 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14098 ""
c0600ecd 14099 "#"
04fa46cf 14100 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 14101 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14102 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 14103 "")
f9562f27 14104
1e24ce83 14105(define_insn_and_split "*plus_gtu<mode>_compare"
097657c3 14106 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 14107 (compare:CC
1e24ce83
DE		 14108 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14109 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14110 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 14111 (const_int 0)))
1e24ce83
DE		 14112 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14113 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14114 ""
14115 "#"
14116 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14117 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14118 (parallel [(set (match_dup 4)
14119 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14120 (const_int 0)))
14121 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 14122 "")
f9562f27 14123
ce45ef46
DE		 14124(define_insn "*neg_gtu<mode>"
14125 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14126 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14127 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14128 ""
ca7f5001 14129 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
943c15ed 14130 [(set_attr "type" "two")
c0600ecd 14131 (set_attr "length" "8")])
f9562f27 14132
1fd4e8c1
RK		 14133\f
14134;; Define both directions of branch and return. If we need a reload
14135;; register, we'd rather use CR0 since it is much easier to copy a
14136;; register CC value to there.
14137
14138(define_insn ""
14139 [(set (pc)
14140 (if_then_else (match_operator 1 "branch_comparison_operator"
14141 [(match_operand 2
b54cf83a 14142 "cc_reg_operand" "y")
1fd4e8c1
RK		 14143 (const_int 0)])
14144 (label_ref (match_operand 0 "" ""))
14145 (pc)))]
14146 ""
b19003d8
RK		 14147 "*
14148{
12a4e8c5 14149 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 14150}"
14151 [(set_attr "type" "branch")])
14152
1fd4e8c1
RK		 14153(define_insn ""
14154 [(set (pc)
14155 (if_then_else (match_operator 0 "branch_comparison_operator"
14156 [(match_operand 1
b54cf83a 14157 "cc_reg_operand" "y")
1fd4e8c1
RK		 14158 (const_int 0)])
14159 (return)
14160 (pc)))]
14161 "direct_return ()"
12a4e8c5
GK		 14162 "*
14163{
14164 return output_cbranch (operands[0], NULL, 0, insn);
14165}"
9c6fdb46 14166 [(set_attr "type" "jmpreg")
39a10a29 14167 (set_attr "length" "4")])
1fd4e8c1
RK		 14168
14169(define_insn ""
14170 [(set (pc)
14171 (if_then_else (match_operator 1 "branch_comparison_operator"
14172 [(match_operand 2
b54cf83a 14173 "cc_reg_operand" "y")
1fd4e8c1
RK		 14174 (const_int 0)])
14175 (pc)
14176 (label_ref (match_operand 0 "" ""))))]
14177 ""
b19003d8
RK		 14178 "*
14179{
12a4e8c5 14180 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 14181}"
14182 [(set_attr "type" "branch")])
1fd4e8c1
RK		 14183
14184(define_insn ""
14185 [(set (pc)
14186 (if_then_else (match_operator 0 "branch_comparison_operator"
14187 [(match_operand 1
b54cf83a 14188 "cc_reg_operand" "y")
1fd4e8c1
RK		 14189 (const_int 0)])
14190 (pc)
14191 (return)))]
14192 "direct_return ()"
12a4e8c5
GK		 14193 "*
14194{
14195 return output_cbranch (operands[0], NULL, 1, insn);
14196}"
9c6fdb46 14197 [(set_attr "type" "jmpreg")
39a10a29
GK		 14198 (set_attr "length" "4")])
14199
14200;; Logic on condition register values.
14201
14202; This pattern matches things like
14203; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14204; (eq:SI (reg:CCFP 68) (const_int 0)))
14205; (const_int 1)))
14206; which are generated by the branch logic.
b54cf83a 14207; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29 14208
423c1189 14209(define_insn "*cceq_ior_compare"
b54cf83a 14210 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 14211 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 14212 [(match_operator:SI 2
39a10a29
GK		 14213 "branch_positive_comparison_operator"
14214 [(match_operand 3
b54cf83a 14215 "cc_reg_operand" "y,y")
39a10a29 14216 (const_int 0)])
b54cf83a 14217 (match_operator:SI 4
39a10a29
GK		 14218 "branch_positive_comparison_operator"
14219 [(match_operand 5
b54cf83a 14220 "cc_reg_operand" "0,y")
39a10a29
GK		 14221 (const_int 0)])])
14222 (const_int 1)))]
24fab1d3 14223 ""
39a10a29 14224 "cr%q1 %E0,%j2,%j4"
b54cf83a 14225 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 14226
14227; Why is the constant -1 here, but 1 in the previous pattern?
14228; Because ~1 has all but the low bit set.
14229(define_insn ""
b54cf83a 14230 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 14231 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 14232 [(not:SI (match_operator:SI 2
39a10a29
GK		 14233 "branch_positive_comparison_operator"
14234 [(match_operand 3
b54cf83a 14235 "cc_reg_operand" "y,y")
39a10a29
GK		 14236 (const_int 0)]))
14237 (match_operator:SI 4
14238 "branch_positive_comparison_operator"
14239 [(match_operand 5
b54cf83a 14240 "cc_reg_operand" "0,y")
39a10a29
GK		 14241 (const_int 0)])])
14242 (const_int -1)))]
14243 ""
14244 "cr%q1 %E0,%j2,%j4"
b54cf83a 14245 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29 14246
423c1189 14247(define_insn "*cceq_rev_compare"
b54cf83a 14248 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 14249 (compare:CCEQ (match_operator:SI 1
39a10a29 14250 "branch_positive_comparison_operator"
6c873122 14251 [(match_operand 2
b54cf83a 14252 "cc_reg_operand" "0,y")
39a10a29
GK		 14253 (const_int 0)])
14254 (const_int 0)))]
423c1189 14255 ""
251b3667 14256 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 14257 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 14258
14259;; If we are comparing the result of two comparisons, this can be done
14260;; using creqv or crxor.
14261
14262(define_insn_and_split ""
14263 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14264 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14265 [(match_operand 2 "cc_reg_operand" "y")
14266 (const_int 0)])
14267 (match_operator 3 "branch_comparison_operator"
14268 [(match_operand 4 "cc_reg_operand" "y")
14269 (const_int 0)])))]
14270 ""
14271 "#"
14272 ""
14273 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14274 (match_dup 5)))]
14275 "
14276{
14277 int positive_1, positive_2;
14278
364849ee
DE		 14279 positive_1 = branch_positive_comparison_operator (operands[1],
14280 GET_MODE (operands[1]));
14281 positive_2 = branch_positive_comparison_operator (operands[3],
14282 GET_MODE (operands[3]));
39a10a29
GK		 14283
14284 if (! positive_1)
1c563bed 14285 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
0f4c242b
KH		 14286 GET_CODE (operands[1])),
14287 SImode,
14288 operands[2], const0_rtx);
39a10a29 14289 else if (GET_MODE (operands[1]) != SImode)
0f4c242b
KH		 14290 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14291 operands[2], const0_rtx);
39a10a29
GK		 14292
14293 if (! positive_2)
1c563bed 14294 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
0f4c242b
KH		 14295 GET_CODE (operands[3])),
14296 SImode,
14297 operands[4], const0_rtx);
39a10a29 14298 else if (GET_MODE (operands[3]) != SImode)
0f4c242b
KH		 14299 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14300 operands[4], const0_rtx);
39a10a29
GK		 14301
14302 if (positive_1 == positive_2)
251b3667
DE		 14303 {
14304 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14305 operands[5] = constm1_rtx;
14306 }
14307 else
14308 {
14309 operands[5] = const1_rtx;
14310 }
39a10a29 14311}")
1fd4e8c1
RK		 14312
14313;; Unconditional branch and return.
14314
14315(define_insn "jump"
14316 [(set (pc)
14317 (label_ref (match_operand 0 "" "")))]
14318 ""
b7ff3d82
DE		 14319 "b %l0"
14320 [(set_attr "type" "branch")])
1fd4e8c1
RK		 14321
14322(define_insn "return"
14323 [(return)]
14324 "direct_return ()"
324e52cc
TG		 14325 "{br|blr}"
14326 [(set_attr "type" "jmpreg")])
1fd4e8c1 14327
0ad91047 14328(define_expand "indirect_jump"
4ae234b0 14329 [(set (pc) (match_operand 0 "register_operand" ""))])
0ad91047 14330
4ae234b0
GK		 14331(define_insn "*indirect_jump<mode>"
14332 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14333 ""
b92b324d
DE		 14334 "@
14335 bctr
14336 {br|blr}"
324e52cc 14337 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14338
14339;; Table jump for switch statements:
14340(define_expand "tablejump"
e6ca2c17
DE		 14341 [(use (match_operand 0 "" ""))
14342 (use (label_ref (match_operand 1 "" "")))]
14343 ""
14344 "
14345{
14346 if (TARGET_32BIT)
14347 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14348 else
14349 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14350 DONE;
14351}")
14352
14353(define_expand "tablejumpsi"
1fd4e8c1
RK		 14354 [(set (match_dup 3)
14355 (plus:SI (match_operand:SI 0 "" "")
14356 (match_dup 2)))
14357 (parallel [(set (pc) (match_dup 3))
14358 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14359 "TARGET_32BIT"
1fd4e8c1
RK		 14360 "
14361{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 14362 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 14363 operands[3] = gen_reg_rtx (SImode);
14364}")
14365
e6ca2c17 14366(define_expand "tablejumpdi"
6ae08853 14367 [(set (match_dup 4)
e42ac3de 14368 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
9ebbca7d
GK		 14369 (set (match_dup 3)
14370 (plus:DI (match_dup 4)
e6ca2c17
DE		 14371 (match_dup 2)))
14372 (parallel [(set (pc) (match_dup 3))
14373 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14374 "TARGET_64BIT"
e6ca2c17 14375 "
9ebbca7d 14376{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 14377 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 14378 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 14379}")
14380
ce45ef46 14381(define_insn "*tablejump<mode>_internal1"
1fd4e8c1 14382 [(set (pc)
4ae234b0 14383 (match_operand:P 0 "register_operand" "c,*l"))
1fd4e8c1 14384 (use (label_ref (match_operand 1 "" "")))]
4ae234b0 14385 ""
c859cda6
DJ		 14386 "@
14387 bctr
14388 {br|blr}"
a6845123 14389 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14390
14391(define_insn "nop"
14392 [(const_int 0)]
14393 ""
ca7f5001 14394 "{cror 0,0,0|nop}")
1fd4e8c1 14395\f
7e69e155 14396;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 14397;; so loop.c knows what to generate.
14398
5527bf14
RH		 14399(define_expand "doloop_end"
14400 [(use (match_operand 0 "" "")) ; loop pseudo
14401 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14402 (use (match_operand 2 "" "")) ; max iterations
14403 (use (match_operand 3 "" "")) ; loop level
14404 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 14405 ""
14406 "
14407{
5527bf14
RH		 14408 /* Only use this on innermost loops. */
14409 if (INTVAL (operands[3]) > 1)
14410 FAIL;
683bdff7 14411 if (TARGET_64BIT)
5527bf14
RH		 14412 {
14413 if (GET_MODE (operands[0]) != DImode)
14414 FAIL;
14415 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14416 }
0ad91047 14417 else
5527bf14
RH		 14418 {
14419 if (GET_MODE (operands[0]) != SImode)
14420 FAIL;
14421 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14422 }
0ad91047
DE		 14423 DONE;
14424}")
14425
4ae234b0 14426(define_expand "ctr<mode>"
3cb999d8 14427 [(parallel [(set (pc)
4ae234b0 14428 (if_then_else (ne (match_operand:P 0 "register_operand" "")
3cb999d8
DE		 14429 (const_int 1))
14430 (label_ref (match_operand 1 "" ""))
14431 (pc)))
b6c9286a 14432 (set (match_dup 0)
4ae234b0 14433 (plus:P (match_dup 0)
b6c9286a 14434 (const_int -1)))
5f81043f 14435 (clobber (match_scratch:CC 2 ""))
4ae234b0
GK		 14436 (clobber (match_scratch:P 3 ""))])]
14437 ""
61c07d3c 14438 "")
c225ba7b 14439
1fd4e8c1
RK		 14440;; We need to be able to do this for any operand, including MEM, or we
14441;; will cause reload to blow up since we don't allow output reloads on
7e69e155 14442;; JUMP_INSNs.
0ad91047 14443;; For the length attribute to be calculated correctly, the
5f81043f
RK		 14444;; label MUST be operand 0.
14445
4ae234b0 14446(define_insn "*ctr<mode>_internal1"
0ad91047 14447 [(set (pc)
4ae234b0 14448 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14449 (const_int 1))
14450 (label_ref (match_operand 0 "" ""))
14451 (pc)))
4ae234b0
GK		 14452 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14453 (plus:P (match_dup 1)
0ad91047 14454 (const_int -1)))
43b68ce5 14455 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14456 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14457 ""
0ad91047
DE		 14458 "*
14459{
14460 if (which_alternative != 0)
14461 return \"#\";
856a6884 14462 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14463 return \"{bdn|bdnz} %l0\";
14464 else
f607bc57 14465 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14466}"
14467 [(set_attr "type" "branch")
5a195cb5 14468 (set_attr "length" "*,12,16,16")])
0ad91047 14469
4ae234b0 14470(define_insn "*ctr<mode>_internal2"
0ad91047 14471 [(set (pc)
4ae234b0 14472 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14473 (const_int 1))
14474 (pc)
14475 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14476 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14477 (plus:P (match_dup 1)
0ad91047 14478 (const_int -1)))
43b68ce5 14479 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14480 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14481 ""
5f81043f
RK		 14482 "*
14483{
14484 if (which_alternative != 0)
14485 return \"#\";
856a6884 14486 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14487 return \"bdz %l0\";
14488 else
f607bc57 14489 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14490}"
14491 [(set_attr "type" "branch")
5a195cb5 14492 (set_attr "length" "*,12,16,16")])
5f81043f 14493
0ad91047
DE		 14494;; Similar but use EQ
14495
4ae234b0 14496(define_insn "*ctr<mode>_internal5"
5f81043f 14497 [(set (pc)
4ae234b0 14498 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14499 (const_int 1))
a6845123 14500 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14501 (pc)))
4ae234b0
GK		 14502 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14503 (plus:P (match_dup 1)
0ad91047 14504 (const_int -1)))
43b68ce5 14505 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14506 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14507 ""
0ad91047
DE		 14508 "*
14509{
14510 if (which_alternative != 0)
14511 return \"#\";
856a6884 14512 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14513 return \"bdz %l0\";
14514 else
f607bc57 14515 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14516}"
14517 [(set_attr "type" "branch")
5a195cb5 14518 (set_attr "length" "*,12,16,16")])
0ad91047 14519
4ae234b0 14520(define_insn "*ctr<mode>_internal6"
0ad91047 14521 [(set (pc)
4ae234b0 14522 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14523 (const_int 1))
14524 (pc)
14525 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14526 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14527 (plus:P (match_dup 1)
0ad91047 14528 (const_int -1)))
43b68ce5 14529 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14530 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14531 ""
5f81043f
RK		 14532 "*
14533{
14534 if (which_alternative != 0)
14535 return \"#\";
856a6884 14536 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14537 return \"{bdn|bdnz} %l0\";
14538 else
f607bc57 14539 return \"bdz $+8\;b %l0\";
5f81043f
RK		 14540}"
14541 [(set_attr "type" "branch")
5a195cb5 14542 (set_attr "length" "*,12,16,16")])
5f81043f 14543
0ad91047
DE		 14544;; Now the splitters if we could not allocate the CTR register
14545
1fd4e8c1
RK		 14546(define_split
14547 [(set (pc)
14548 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14549 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14550 (const_int 1)])
61c07d3c
DE		 14551 (match_operand 5 "" "")
14552 (match_operand 6 "" "")))
4ae234b0
GK		 14553 (set (match_operand:P 0 "gpc_reg_operand" "")
14554 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14555 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14556 (clobber (match_scratch:P 4 ""))]
14557 "reload_completed"
0ad91047 14558 [(parallel [(set (match_dup 3)
4ae234b0 14559 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14560 (const_int -1))
14561 (const_int 0)))
14562 (set (match_dup 0)
4ae234b0 14563 (plus:P (match_dup 1)
0ad91047 14564 (const_int -1)))])
61c07d3c
DE		 14565 (set (pc) (if_then_else (match_dup 7)
14566 (match_dup 5)
14567 (match_dup 6)))]
0ad91047 14568 "
0f4c242b
KH		 14569{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14570 operands[3], const0_rtx); }")
0ad91047
DE		 14571
14572(define_split
14573 [(set (pc)
14574 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14575 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14576 (const_int 1)])
61c07d3c
DE		 14577 (match_operand 5 "" "")
14578 (match_operand 6 "" "")))
4ae234b0
GK		 14579 (set (match_operand:P 0 "nonimmediate_operand" "")
14580 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14581 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14582 (clobber (match_scratch:P 4 ""))]
14583 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
0ad91047 14584 [(parallel [(set (match_dup 3)
4ae234b0 14585 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14586 (const_int -1))
14587 (const_int 0)))
14588 (set (match_dup 4)
4ae234b0 14589 (plus:P (match_dup 1)
0ad91047
DE		 14590 (const_int -1)))])
14591 (set (match_dup 0)
14592 (match_dup 4))
61c07d3c
DE		 14593 (set (pc) (if_then_else (match_dup 7)
14594 (match_dup 5)
14595 (match_dup 6)))]
0ad91047 14596 "
0f4c242b
KH		 14597{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14598 operands[3], const0_rtx); }")
e0cd0770
JC		 14599\f
14600(define_insn "trap"
14601 [(trap_if (const_int 1) (const_int 0))]
14602 ""
44cd321e
PS		 14603 "{t 31,0,0|trap}"
14604 [(set_attr "type" "trap")])
e0cd0770 14605
f90b7a5a
PB		 14606(define_expand "ctrap<mode>4"
14607 [(trap_if (match_operator 0 "ordered_comparison_operator"
14608 [(match_operand:GPR 1 "register_operand")
14609 (match_operand:GPR 2 "reg_or_short_operand")])
14610 (match_operand 3 "zero_constant" ""))]
e0cd0770 14611 ""
f90b7a5a 14612 "")
e0cd0770
JC		 14613
14614(define_insn ""
f90b7a5a 14615 [(trap_if (match_operator 0 "ordered_comparison_operator"
4ae234b0
GK		 14616 [(match_operand:GPR 1 "register_operand" "r")
14617 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
e0cd0770
JC		 14618 (const_int 0))]
14619 ""
44cd321e
PS		 14620 "{t|t<wd>}%V0%I2 %1,%2"
14621 [(set_attr "type" "trap")])
9ebbca7d
GK		 14622\f
14623;; Insns related to generating the function prologue and epilogue.
14624
14625(define_expand "prologue"
14626 [(use (const_int 0))]
14627 "TARGET_SCHED_PROLOG"
14628 "
14629{
14630 rs6000_emit_prologue ();
14631 DONE;
14632}")
14633
2c4a9cff
DE		 14634(define_insn "*movesi_from_cr_one"
14635 [(match_parallel 0 "mfcr_operation"
14636 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14637 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14638 (match_operand 3 "immediate_operand" "n")]
14639 UNSPEC_MOVESI_FROM_CR))])]
14640 "TARGET_MFCRF"
14641 "*
14642{
14643 int mask = 0;
14644 int i;
14645 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14646 {
14647 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14648 operands[4] = GEN_INT (mask);
14649 output_asm_insn (\"mfcr %1,%4\", operands);
14650 }
14651 return \"\";
14652}"
14653 [(set_attr "type" "mfcrf")])
14654
9ebbca7d
GK		 14655(define_insn "movesi_from_cr"
14656 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1de43f85
DE		 14657 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14658 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14659 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14660 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
615158e2 14661 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 14662 ""
309323c2 14663 "mfcr %0"
b54cf83a 14664 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14665
14666(define_insn "*stmw"
e033a023
DE		 14667 [(match_parallel 0 "stmw_operation"
14668 [(set (match_operand:SI 1 "memory_operand" "=m")
14669 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14670 "TARGET_MULTIPLE"
9c6fdb46
DE		 14671 "{stm|stmw} %2,%1"
14672 [(set_attr "type" "store_ux")])
6ae08853 14673
f78c3290
NF		 14674(define_insn "*save_gpregs_<mode>"
14675 [(match_parallel 0 "any_parallel_operand"
14676 [(clobber (reg:P 65))
14677 (use (match_operand:P 1 "symbol_ref_operand" "s"))
e1ece9f1
NF		 14678 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14679 (set (match_operand:P 3 "memory_operand" "=m")
14680 (match_operand:P 4 "gpc_reg_operand" "r"))])]
f78c3290
NF		 14681 ""
14682 "bl %z1"
14683 [(set_attr "type" "branch")
14684 (set_attr "length" "4")])
14685
4ae234b0 14686(define_insn "*save_fpregs_<mode>"
85d346f1 14687 [(match_parallel 0 "any_parallel_operand"
e65a3857 14688 [(clobber (reg:P 65))
f78c3290 14689 (use (match_operand:P 1 "symbol_ref_operand" "s"))
e1ece9f1
NF		 14690 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14691 (set (match_operand:DF 3 "memory_operand" "=m")
14692 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
4ae234b0 14693 ""
e65a3857 14694 "bl %z1"
e033a023
DE		 14695 [(set_attr "type" "branch")
14696 (set_attr "length" "4")])
9ebbca7d
GK		 14697
14698; These are to explain that changes to the stack pointer should
14699; not be moved over stores to stack memory.
14700(define_insn "stack_tie"
14701 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 14702 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 14703 ""
14704 ""
14705 [(set_attr "length" "0")])
14706
14707
14708(define_expand "epilogue"
14709 [(use (const_int 0))]
14710 "TARGET_SCHED_PROLOG"
14711 "
14712{
14713 rs6000_emit_epilogue (FALSE);
14714 DONE;
14715}")
14716
14717; On some processors, doing the mtcrf one CC register at a time is
14718; faster (like on the 604e). On others, doing them all at once is
14719; faster; for instance, on the 601 and 750.
14720
14721(define_expand "movsi_to_cr_one"
e42ac3de
RS		 14722 [(set (match_operand:CC 0 "cc_reg_operand" "")
14723 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
615158e2 14724 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 14725 ""
14726 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14727
14728(define_insn "*movsi_to_cr"
35aba846
DE		 14729 [(match_parallel 0 "mtcrf_operation"
14730 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14731 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14732 (match_operand 3 "immediate_operand" "n")]
615158e2 14733 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 14734 ""
e35b9579
GK		 14735 "*
14736{
14737 int mask = 0;
14738 int i;
14739 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14740 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14741 operands[4] = GEN_INT (mask);
14742 return \"mtcrf %4,%2\";
309323c2 14743}"
b54cf83a 14744 [(set_attr "type" "mtcr")])
9ebbca7d 14745
b54cf83a 14746(define_insn "*mtcrfsi"
309323c2
DE		 14747 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14748 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 14749 (match_operand 2 "immediate_operand" "n")]
14750 UNSPEC_MOVESI_TO_CR))]
6ae08853 14751 "GET_CODE (operands[0]) == REG
309323c2
DE		 14752 && CR_REGNO_P (REGNO (operands[0]))
14753 && GET_CODE (operands[2]) == CONST_INT
14754 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14755 "mtcrf %R0,%1"
b54cf83a 14756 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14757
14758; The load-multiple instructions have similar properties.
14759; Note that "load_multiple" is a name known to the machine-independent
9c6fdb46 14760; code that actually corresponds to the PowerPC load-string.
9ebbca7d
GK		 14761
14762(define_insn "*lmw"
35aba846
DE		 14763 [(match_parallel 0 "lmw_operation"
14764 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14765 (match_operand:SI 2 "memory_operand" "m"))])]
14766 "TARGET_MULTIPLE"
9c6fdb46 14767 "{lm|lmw} %1,%2"
c921bad8
AP		 14768 [(set_attr "type" "load_ux")
14769 (set_attr "cell_micro" "always")])
6ae08853 14770
4ae234b0 14771(define_insn "*return_internal_<mode>"
e35b9579 14772 [(return)
4ae234b0
GK		 14773 (use (match_operand:P 0 "register_operand" "lc"))]
14774 ""
cccf3bdc 14775 "b%T0"
9ebbca7d
GK		 14776 [(set_attr "type" "jmpreg")])
14777
14778; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
85d346f1 14779; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
9ebbca7d 14780
f78c3290
NF		 14781(define_insn "*restore_gpregs_<mode>"
14782 [(match_parallel 0 "any_parallel_operand"
14783 [(clobber (match_operand:P 1 "register_operand" "=l"))
14784 (use (match_operand:P 2 "symbol_ref_operand" "s"))
e1ece9f1
NF		 14785 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14786 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14787 (match_operand:P 5 "memory_operand" "m"))])]
f78c3290
NF		 14788 ""
14789 "bl %z2"
14790 [(set_attr "type" "branch")
14791 (set_attr "length" "4")])
14792
14793(define_insn "*return_and_restore_gpregs_<mode>"
14794 [(match_parallel 0 "any_parallel_operand"
14795 [(return)
14796 (clobber (match_operand:P 1 "register_operand" "=l"))
14797 (use (match_operand:P 2 "symbol_ref_operand" "s"))
e1ece9f1
NF		 14798 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14799 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14800 (match_operand:P 5 "memory_operand" "m"))])]
f78c3290
NF		 14801 ""
14802 "b %z2"
14803 [(set_attr "type" "branch")
14804 (set_attr "length" "4")])
14805
4ae234b0 14806(define_insn "*return_and_restore_fpregs_<mode>"
85d346f1 14807 [(match_parallel 0 "any_parallel_operand"
e35b9579 14808 [(return)
f78c3290
NF		 14809 (clobber (match_operand:P 1 "register_operand" "=l"))
14810 (use (match_operand:P 2 "symbol_ref_operand" "s"))
e1ece9f1
NF		 14811 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14812 (set (match_operand:DF 4 "gpc_reg_operand" "=f")
14813 (match_operand:DF 5 "memory_operand" "m"))])]
4ae234b0 14814 ""
f78c3290
NF		 14815 "b %z2"
14816 [(set_attr "type" "branch")
14817 (set_attr "length" "4")])
9ebbca7d 14818
83720594
RH		 14819; This is used in compiling the unwind routines.
14820(define_expand "eh_return"
34dc173c 14821 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 14822 ""
14823 "
14824{
83720594 14825 if (TARGET_32BIT)
34dc173c 14826 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 14827 else
34dc173c 14828 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 14829 DONE;
14830}")
14831
83720594 14832; We can't expand this before we know where the link register is stored.
4ae234b0
GK		 14833(define_insn "eh_set_lr_<mode>"
14834 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
615158e2 14835 UNSPECV_EH_RR)
4ae234b0
GK		 14836 (clobber (match_scratch:P 1 "=&b"))]
14837 ""
83720594 14838 "#")
9ebbca7d
GK		 14839
14840(define_split
615158e2 14841 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 14842 (clobber (match_scratch 1 ""))]
14843 "reload_completed"
14844 [(const_int 0)]
9ebbca7d
GK		 14845 "
14846{
d1d0c603 14847 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 14848 DONE;
14849}")
0ac081f6 14850
01a2ccd0 14851(define_insn "prefetch"
3256a76e 14852 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
6041bf2f
DE		 14853 (match_operand:SI 1 "const_int_operand" "n")
14854 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14855 "TARGET_POWERPC"
6041bf2f
DE		 14856 "*
14857{
01a2ccd0
DE		 14858 if (GET_CODE (operands[0]) == REG)
14859 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14860 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14861}"
14862 [(set_attr "type" "load")])
915167f5 14863\f
a3170dc6 14864
f565b0a1 14865(include "sync.md")
10ed84db 14866(include "altivec.md")
a3170dc6 14867(include "spe.md")
7393f7f8 14868(include "dfp.md")
96038623 14869(include "paired.md")
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