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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
9ebbca7d | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
792760b9 | 3 | ;; 1999, 2000, 2001 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
5 | |
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d GK |
24 | |
25 | ;; `unspec' values used in rs6000.md: | |
26 | ;; Number Use | |
27 | ;; 0 frsp for POWER machines | |
28 | ;; 0/v blockage | |
29 | ;; 5 used to tie the stack contents and the stack pointer | |
30 | ;; 6 address of a word pointing to the TOC | |
31 | ;; 7 address of the TOC (more-or-less) | |
32 | ;; 8 movsi_got | |
33 | ;; 9/v eh_reg_restore | |
34 | ;; 10 fctiwz | |
35 | ;; 19 movesi_from_cr | |
36 | ;; 20 movesi_to_cr | |
1fd4e8c1 RK |
37 | \f |
38 | ;; Define an insn type attribute. This is used in function unit delay | |
39 | ;; computations. | |
39a10a29 | 40 | (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" |
1fd4e8c1 RK |
41 | (const_string "integer")) |
42 | ||
b19003d8 | 43 | ;; Length (in bytes). |
6cbadf36 GK |
44 | ; '(pc)' in the following doesn't include the instruction itself; it is |
45 | ; calculated as if the instruction had zero size. | |
b19003d8 RK |
46 | (define_attr "length" "" |
47 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 48 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 49 | (const_int -32768)) |
6cbadf36 GK |
50 | (lt (minus (match_dup 0) (pc)) |
51 | (const_int 32764))) | |
39a10a29 GK |
52 | (const_int 4) |
53 | (const_int 8)) | |
b19003d8 RK |
54 | (const_int 4))) |
55 | ||
cfb557c4 RK |
56 | ;; Processor type -- this attribute must exactly match the processor_type |
57 | ;; enumeration in rs6000.h. | |
58 | ||
ed947a96 | 59 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450" |
cfb557c4 RK |
60 | (const (symbol_ref "rs6000_cpu_attr"))) |
61 | ||
62 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
63 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
64 | ||
b7ff3d82 | 65 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 66 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
67 | (define_function_unit "lsu" 1 0 |
68 | (and (eq_attr "type" "load") | |
ed947a96 | 69 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400")) |
b6c9286a | 70 | 2 1) |
cfb557c4 | 71 | |
ed947a96 DJ |
72 | (define_function_unit "lsu" 1 0 |
73 | (and (eq_attr "type" "load") | |
74 | (eq_attr "cpu" "ppc7450")) | |
75 | 3 1) | |
76 | ||
cfb557c4 | 77 | (define_function_unit "lsu" 1 0 |
b7ff3d82 | 78 | (and (eq_attr "type" "store,fpstore") |
ed947a96 | 79 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 80 | 1 1) |
b6c9286a | 81 | |
ed947a96 DJ |
82 | (define_function_unit "lsu" 1 0 |
83 | (and (eq_attr "type" "store,fpstore") | |
84 | (eq_attr "cpu" "ppc750,ppc7400")) | |
85 | 2 1) | |
86 | ||
87 | (define_function_unit "lsu" 1 0 | |
88 | (and (eq_attr "type" "store") | |
89 | (eq_attr "cpu" "ppc7450")) | |
90 | 3 1) | |
91 | ||
92 | (define_function_unit "lsu" 1 0 | |
93 | (and (eq_attr "type" "fpstore") | |
94 | (eq_attr "cpu" "ppc7450")) | |
95 | 3 3) | |
96 | ||
b6c9286a MM |
97 | (define_function_unit "lsu" 1 0 |
98 | (and (eq_attr "type" "fpload") | |
ed947a96 | 99 | (eq_attr "cpu" "mpccore,ppc603,ppc750,ppc7400")) |
b6c9286a | 100 | 2 1) |
cfb557c4 | 101 | |
ed947a96 DJ |
102 | (define_function_unit "lsu" 1 0 |
103 | (and (eq_attr "type" "fpload") | |
104 | (eq_attr "cpu" "ppc7450")) | |
105 | 4 1) | |
106 | ||
b7ff3d82 DE |
107 | (define_function_unit "lsu" 1 0 |
108 | (and (eq_attr "type" "fpload") | |
3cb999d8 | 109 | (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 DE |
110 | 3 1) |
111 | ||
cfb557c4 RK |
112 | (define_function_unit "iu" 1 0 |
113 | (and (eq_attr "type" "load") | |
b7ff3d82 | 114 | (eq_attr "cpu" "rios1,ppc403,ppc601")) |
b6c9286a | 115 | 2 1) |
cfb557c4 RK |
116 | |
117 | (define_function_unit "iu" 1 0 | |
b7ff3d82 DE |
118 | (and (eq_attr "type" "store,fpstore") |
119 | (eq_attr "cpu" "rios1,ppc403,ppc601")) | |
120 | 1 1) | |
121 | ||
122 | (define_function_unit "fpu" 1 0 | |
123 | (and (eq_attr "type" "fpstore") | |
3624a679 | 124 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 125 | 0 1) |
cfb557c4 | 126 | |
49a0b204 | 127 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 128 | (and (eq_attr "type" "fpload") |
b6c9286a | 129 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
130 | 2 1) |
131 | ||
132 | (define_function_unit "iu" 1 0 | |
133 | (and (eq_attr "type" "fpload") | |
134 | (eq_attr "cpu" "ppc601")) | |
135 | 3 1) | |
136 | ||
137 | (define_function_unit "iu2" 2 0 | |
138 | (and (eq_attr "type" "load,fpload") | |
139 | (eq_attr "cpu" "rios2")) | |
140 | 2 1) | |
141 | ||
142 | (define_function_unit "iu2" 2 0 | |
143 | (and (eq_attr "type" "store,fpstore") | |
144 | (eq_attr "cpu" "rios2")) | |
145 | 1 1) | |
146 | ||
3cb999d8 | 147 | ; Integer Unit (RIOS1, PPC601, PPC603, RS64a) |
b7ff3d82 DE |
148 | (define_function_unit "iu" 1 0 |
149 | (and (eq_attr "type" "integer") | |
3cb999d8 | 150 | (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603")) |
b7ff3d82 | 151 | 1 1) |
49a0b204 | 152 | |
39a10a29 GK |
153 | (define_function_unit "iu" 1 0 |
154 | (and (eq_attr "type" "cr_logical") | |
5638268e | 155 | (eq_attr "cpu" "mpccore,ppc403,ppc601")) |
39a10a29 GK |
156 | 1 1) |
157 | ||
da0ae67f MM |
158 | (define_function_unit "iu" 1 0 |
159 | (and (eq_attr "type" "imul") | |
160 | (eq_attr "cpu" "ppc403")) | |
161 | 4 4) | |
162 | ||
cfb557c4 RK |
163 | (define_function_unit "iu" 1 0 |
164 | (and (eq_attr "type" "imul") | |
b7ff3d82 | 165 | (eq_attr "cpu" "rios1,ppc601,ppc603")) |
51b8fc2c | 166 | 5 5) |
cfb557c4 | 167 | |
3cb999d8 DE |
168 | (define_function_unit "iu" 1 0 |
169 | (and (eq_attr "type" "imul") | |
170 | (eq_attr "cpu" "rs64a")) | |
171 | 20 14) | |
172 | ||
173 | (define_function_unit "iu" 1 0 | |
174 | (and (eq_attr "type" "lmul") | |
175 | (eq_attr "cpu" "rs64a")) | |
176 | 34 34) | |
177 | ||
cfb557c4 RK |
178 | (define_function_unit "iu" 1 0 |
179 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 180 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 181 | 19 19) |
cfb557c4 | 182 | |
3cb999d8 DE |
183 | (define_function_unit "iu" 1 0 |
184 | (and (eq_attr "type" "idiv") | |
185 | (eq_attr "cpu" "rs64a")) | |
186 | 66 66) | |
187 | ||
188 | (define_function_unit "iu" 1 0 | |
189 | (and (eq_attr "type" "ldiv") | |
190 | (eq_attr "cpu" "rs64a")) | |
191 | 66 66) | |
192 | ||
cfb557c4 RK |
193 | (define_function_unit "iu" 1 0 |
194 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
195 | (eq_attr "cpu" "ppc403")) |
196 | 33 33) | |
51b8fc2c | 197 | |
da0ae67f MM |
198 | (define_function_unit "iu" 1 0 |
199 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
200 | (eq_attr "cpu" "ppc601")) |
201 | 36 36) | |
da0ae67f | 202 | |
51b8fc2c RK |
203 | (define_function_unit "iu" 1 0 |
204 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 205 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
206 | 37 36) |
207 | ||
208 | ; RIOS2 has two integer units: a primary one which can perform all | |
209 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
210 | ; and can perform "simple" integer operations. |
211 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
212 | ; for the complex insns. | |
51b8fc2c RK |
213 | (define_function_unit "iu2" 2 0 |
214 | (and (eq_attr "type" "integer") | |
215 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 216 | 1 1) |
b6c9286a MM |
217 | |
218 | (define_function_unit "iu2" 2 0 | |
219 | (and (eq_attr "type" "imul") | |
220 | (eq_attr "cpu" "rios2")) | |
221 | 2 2) | |
222 | ||
223 | (define_function_unit "iu2" 2 0 | |
224 | (and (eq_attr "type" "idiv") | |
225 | (eq_attr "cpu" "rios2")) | |
226 | 13 13) | |
51b8fc2c RK |
227 | |
228 | (define_function_unit "imuldiv" 1 0 | |
229 | (and (eq_attr "type" "imul") | |
230 | (eq_attr "cpu" "rios2")) | |
b6c9286a MM |
231 | 2 2) |
232 | ||
51b8fc2c RK |
233 | (define_function_unit "imuldiv" 1 0 |
234 | (and (eq_attr "type" "idiv") | |
235 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 236 | 13 13) |
51b8fc2c | 237 | |
cf27b467 MM |
238 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
239 | ; Divide latency varies greatly from 2-11, use 6 as average | |
240 | (define_function_unit "imuldiv" 1 0 | |
241 | (and (eq_attr "type" "imul") | |
242 | (eq_attr "cpu" "mpccore")) | |
243 | 2 1) | |
244 | ||
245 | (define_function_unit "imuldiv" 1 0 | |
246 | (and (eq_attr "type" "idiv") | |
247 | (eq_attr "cpu" "mpccore")) | |
248 | 6 6) | |
249 | ||
cac8ce95 | 250 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
251 | ; and one unit for divide/multiply operations (and move |
252 | ; from/to spr). | |
253 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 254 | (and (eq_attr "type" "integer") |
3cb999d8 | 255 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 256 | 1 1) |
51b8fc2c RK |
257 | |
258 | (define_function_unit "imuldiv" 1 0 | |
259 | (and (eq_attr "type" "imul") | |
3cb999d8 | 260 | (eq_attr "cpu" "ppc604")) |
b7ff3d82 | 261 | 4 2) |
51b8fc2c | 262 | |
3cb999d8 DE |
263 | (define_function_unit "imuldiv" 1 0 |
264 | (and (eq_attr "type" "imul") | |
265 | (eq_attr "cpu" "ppc620,ppc630")) | |
266 | 5 3) | |
267 | ||
268 | (define_function_unit "imuldiv" 1 0 | |
269 | (and (eq_attr "type" "lmul") | |
270 | (eq_attr "cpu" "ppc620,ppc630")) | |
271 | 5 3) | |
272 | ||
cac8ce95 DE |
273 | (define_function_unit "imuldiv" 1 0 |
274 | (and (eq_attr "type" "imul") | |
275 | (eq_attr "cpu" "ppc604e")) | |
276 | 2 1) | |
277 | ||
51b8fc2c RK |
278 | (define_function_unit "imuldiv" 1 0 |
279 | (and (eq_attr "type" "idiv") | |
3cb999d8 | 280 | (eq_attr "cpu" "ppc604,ppc604e")) |
b7ff3d82 | 281 | 20 19) |
cfb557c4 | 282 | |
3cb999d8 DE |
283 | (define_function_unit "imuldiv" 1 0 |
284 | (and (eq_attr "type" "idiv") | |
285 | (eq_attr "cpu" "ppc620")) | |
286 | 37 36) | |
287 | ||
288 | (define_function_unit "imuldiv" 1 0 | |
289 | (and (eq_attr "type" "idiv") | |
290 | (eq_attr "cpu" "ppc630")) | |
291 | 21 20) | |
292 | ||
293 | (define_function_unit "imuldiv" 1 0 | |
294 | (and (eq_attr "type" "ldiv") | |
295 | (eq_attr "cpu" "ppc620,ppc630")) | |
296 | 37 36) | |
297 | ||
ed947a96 DJ |
298 | ; PPC7450 has 3 integer units (for most integer insns) and one mul/div |
299 | ; unit, which also does CR-logical insns and move to/from SPR. | |
300 | ||
301 | (define_function_unit "iu3" 3 0 | |
302 | (and (eq_attr "type" "integer") | |
303 | (eq_attr "cpu" "ppc7450")) | |
304 | 1 1) | |
305 | ||
306 | (define_function_unit "imuldiv" 1 0 | |
307 | (and (eq_attr "type" "imul") | |
308 | (eq_attr "cpu" "ppc7450")) | |
309 | 4 4) | |
310 | ||
311 | (define_function_unit "imuldiv" 1 0 | |
312 | (and (eq_attr "type" "idiv") | |
313 | (eq_attr "cpu" "ppc7450")) | |
314 | 23 23) | |
315 | ||
316 | (define_function_unit "imuldiv" 1 0 | |
317 | (and (eq_attr "type" "cr_logical") | |
318 | (eq_attr "cpu" "ppc7450")) | |
319 | 1 1) | |
320 | ||
bef84347 VM |
321 | ; PPC750 has two integer units: a primary one which can perform all |
322 | ; operations and a secondary one which is fed in lock step with the first | |
323 | ; and can perform "simple" integer operations. | |
324 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
325 | ; for the complex insns. | |
326 | (define_function_unit "iu2" 2 0 | |
327 | (and (eq_attr "type" "integer") | |
ed947a96 | 328 | (eq_attr "cpu" "ppc750,ppc7400")) |
bef84347 VM |
329 | 1 1) |
330 | ||
331 | (define_function_unit "iu2" 2 0 | |
332 | (and (eq_attr "type" "imul") | |
ed947a96 DJ |
333 | (eq_attr "cpu" "ppc750,ppc7400")) |
334 | 4 4) | |
335 | ||
336 | (define_function_unit "iu2" 2 0 | |
337 | (and (eq_attr "type" "idiv") | |
338 | (eq_attr "cpu" "ppc750,ppc7400")) | |
339 | 19 19) | |
bef84347 VM |
340 | |
341 | (define_function_unit "imuldiv" 1 0 | |
342 | (and (eq_attr "type" "imul") | |
ed947a96 DJ |
343 | (eq_attr "cpu" "ppc750,ppc7400")) |
344 | 4 4) | |
bef84347 VM |
345 | |
346 | (define_function_unit "imuldiv" 1 0 | |
347 | (and (eq_attr "type" "idiv") | |
ed947a96 | 348 | (eq_attr "cpu" "ppc750,ppc7400")) |
bef84347 VM |
349 | 19 19) |
350 | ||
39a10a29 GK |
351 | ; CR-logical operations are execute-serialized, that is they don't |
352 | ; start (and block the function unit) until all preceding operations | |
353 | ; have finished. They don't block dispatch of other insns, though. | |
354 | ; I've imitated this by giving them longer latency. | |
355 | (define_function_unit "sru" 1 0 | |
356 | (and (eq_attr "type" "cr_logical") | |
ed947a96 | 357 | (eq_attr "cpu" "ppc603,ppc750,ppc7400")) |
39a10a29 GK |
358 | 3 2) |
359 | ||
b6c9286a | 360 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 361 | ; execute on the branch unit. |
b6c9286a MM |
362 | (define_function_unit "iu" 1 0 |
363 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
364 | (eq_attr "cpu" "rios1")) |
365 | 4 1) | |
366 | ||
367 | (define_function_unit "iu" 1 0 | |
368 | (and (eq_attr "type" "delayed_compare") | |
369 | (eq_attr "cpu" "rios1")) | |
370 | 5 1) | |
371 | ||
372 | (define_function_unit "iu" 1 0 | |
373 | (and (eq_attr "type" "compare,delayed_compare") | |
ed947a96 | 374 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 375 | 3 1) |
b6c9286a | 376 | |
ed947a96 DJ |
377 | ; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare |
378 | ; and a following branch, to reduce mispredicts | |
379 | (define_function_unit "iu" 1 0 | |
380 | (and (eq_attr "type" "compare,delayed_compare") | |
381 | (eq_attr "cpu" "ppc750,ppc7400")) | |
382 | 1 1) | |
383 | ||
384 | (define_function_unit "iu3" 3 0 | |
385 | (and (eq_attr "type" "compare,delayed_compare") | |
386 | (eq_attr "cpu" "ppc7450")) | |
387 | 1 1) | |
388 | ||
b6c9286a | 389 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 390 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 391 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 392 | 3 1) |
b6c9286a | 393 | |
b6c9286a | 394 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 395 | (and (eq_attr "type" "compare,delayed_compare") |
ed947a96 | 396 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400")) |
b6c9286a | 397 | 1 1) |
cfb557c4 | 398 | |
b6c9286a MM |
399 | ; fp compare uses fp unit |
400 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 401 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 402 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 403 | 9 1) |
cfb557c4 | 404 | |
b6c9286a MM |
405 | ; rios1 and rios2 have different fpcompare delays |
406 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 407 | (and (eq_attr "type" "fpcompare") |
3cb999d8 | 408 | (eq_attr "cpu" "rios2,ppc630")) |
b6c9286a MM |
409 | 5 1) |
410 | ||
411 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
412 | ; the integer unit | |
413 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 414 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
415 | (define_function_unit "iu" 1 0 |
416 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 417 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
418 | 0 2) |
419 | ||
420 | ; fp compare uses fp unit | |
421 | (define_function_unit "fpu" 1 0 | |
422 | (and (eq_attr "type" "fpcompare") | |
ed947a96 | 423 | (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b6c9286a | 424 | 5 1) |
cfb557c4 | 425 | |
ed947a96 DJ |
426 | (define_function_unit "fpu" 1 0 |
427 | (and (eq_attr "type" "fpcompare") | |
428 | (eq_attr "cpu" "ppc750,ppc7400,ppc7450")) | |
429 | 3 1) | |
430 | ||
cf27b467 MM |
431 | (define_function_unit "fpu" 1 0 |
432 | (and (eq_attr "type" "fpcompare") | |
433 | (eq_attr "cpu" "mpccore")) | |
434 | 1 1) | |
435 | ||
cfb557c4 | 436 | (define_function_unit "bpu" 1 0 |
324e52cc | 437 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 438 | (eq_attr "cpu" "rios1,rios2,rs64a")) |
b7ff3d82 | 439 | 5 1) |
cfb557c4 RK |
440 | |
441 | (define_function_unit "bpu" 1 0 | |
324e52cc | 442 | (and (eq_attr "type" "mtjmpr") |
ed947a96 | 443 | (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450")) |
b7ff3d82 | 444 | 4 1) |
cfb557c4 | 445 | |
39a10a29 GK |
446 | (define_function_unit "bpu" 1 0 |
447 | (and (eq_attr "type" "cr_logical") | |
5638268e | 448 | (eq_attr "cpu" "rios1,rios2,ppc604")) |
39a10a29 GK |
449 | 4 1) |
450 | ||
451 | (define_function_unit "cru" 1 0 | |
452 | (and (eq_attr "type" "cr_logical") | |
5638268e DE |
453 | (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a")) |
454 | 1 1) | |
39a10a29 | 455 | |
b6c9286a MM |
456 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
457 | (define_function_unit "bpu" 1 0 | |
458 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 459 | 1 1) |
b6c9286a MM |
460 | |
461 | (define_function_unit "bpu" 1 0 | |
462 | (eq_attr "type" "branch") | |
b7ff3d82 | 463 | 1 1) |
b6c9286a | 464 | |
cf27b467 | 465 | ; Floating Point Unit |
cfb557c4 | 466 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 467 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 468 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 469 | 2 1) |
cfb557c4 | 470 | |
cf27b467 MM |
471 | (define_function_unit "fpu" 1 0 |
472 | (and (eq_attr "type" "fp") | |
3cb999d8 DE |
473 | (eq_attr "cpu" "rs64a,mpccore")) |
474 | 4 2) | |
cf27b467 | 475 | |
cfb557c4 RK |
476 | (define_function_unit "fpu" 1 0 |
477 | (and (eq_attr "type" "fp") | |
51b8fc2c | 478 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 479 | 4 1) |
cfb557c4 | 480 | |
51b8fc2c RK |
481 | (define_function_unit "fpu" 1 0 |
482 | (and (eq_attr "type" "fp") | |
ed947a96 | 483 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750,ppc7400")) |
b6c9286a | 484 | 3 1) |
51b8fc2c | 485 | |
ed947a96 DJ |
486 | (define_function_unit "fpu" 1 0 |
487 | (and (eq_attr "type" "fp,dmul") | |
488 | (eq_attr "cpu" "ppc7450")) | |
489 | 5 1) | |
490 | ||
3cb999d8 DE |
491 | (define_function_unit "fpu" 1 0 |
492 | (and (eq_attr "type" "dmul") | |
493 | (eq_attr "cpu" "rs64a")) | |
494 | 7 2) | |
495 | ||
cf27b467 MM |
496 | (define_function_unit "fpu" 1 0 |
497 | (and (eq_attr "type" "dmul") | |
498 | (eq_attr "cpu" "mpccore")) | |
499 | 5 5) | |
500 | ||
cfb557c4 RK |
501 | (define_function_unit "fpu" 1 0 |
502 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 503 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 504 | 5 2) |
cfb557c4 | 505 | |
b6c9286a | 506 | ; is this true? |
cfb557c4 RK |
507 | (define_function_unit "fpu" 1 0 |
508 | (and (eq_attr "type" "dmul") | |
bef84347 | 509 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 510 | 4 2) |
cfb557c4 RK |
511 | |
512 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 513 | (and (eq_attr "type" "dmul") |
ed947a96 | 514 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc7400")) |
b6c9286a | 515 | 3 1) |
51b8fc2c RK |
516 | |
517 | (define_function_unit "fpu" 1 0 | |
518 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 519 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 520 | 19 19) |
cfb557c4 | 521 | |
3cb999d8 DE |
522 | (define_function_unit "fpu" 1 0 |
523 | (and (eq_attr "type" "sdiv") | |
524 | (eq_attr "cpu" "rs64a")) | |
525 | 31 31) | |
526 | ||
cfb557c4 RK |
527 | (define_function_unit "fpu" 1 0 |
528 | (and (eq_attr "type" "sdiv") | |
ed947a96 | 529 | (eq_attr "cpu" "ppc601,ppc750,ppc7400")) |
51b8fc2c RK |
530 | 17 17) |
531 | ||
ed947a96 DJ |
532 | (define_function_unit "fpu" 1 0 |
533 | (and (eq_attr "type" "sdiv") | |
534 | (eq_attr "cpu" "ppc7450")) | |
535 | 21 21) | |
536 | ||
cf27b467 MM |
537 | (define_function_unit "fpu" 1 0 |
538 | (and (eq_attr "type" "sdiv") | |
539 | (eq_attr "cpu" "mpccore")) | |
540 | 10 10) | |
541 | ||
51b8fc2c RK |
542 | (define_function_unit "fpu" 1 0 |
543 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 544 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 545 | 18 18) |
cfb557c4 | 546 | |
cf27b467 MM |
547 | (define_function_unit "fpu" 1 0 |
548 | (and (eq_attr "type" "ddiv") | |
549 | (eq_attr "cpu" "mpccore")) | |
550 | 17 17) | |
551 | ||
cfb557c4 RK |
552 | (define_function_unit "fpu" 1 0 |
553 | (and (eq_attr "type" "ddiv") | |
ed947a96 | 554 | (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620,ppc7400")) |
51b8fc2c | 555 | 31 31) |
cfb557c4 | 556 | |
ed947a96 DJ |
557 | (define_function_unit "fpu" 1 0 |
558 | (and (eq_attr "type" "ddiv") | |
559 | (eq_attr "cpu" "ppc7450")) | |
560 | 35 35) | |
561 | ||
cfb557c4 RK |
562 | (define_function_unit "fpu" 1 0 |
563 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 564 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 565 | 33 33) |
cfb557c4 RK |
566 | |
567 | (define_function_unit "fpu" 1 0 | |
568 | (and (eq_attr "type" "ssqrt") | |
a473029f | 569 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 570 | 31 31) |
cfb557c4 RK |
571 | |
572 | (define_function_unit "fpu" 1 0 | |
573 | (and (eq_attr "type" "dsqrt") | |
a473029f | 574 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 575 | 31 31) |
b73d04f2 | 576 | |
51b8fc2c | 577 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 RK |
578 | (define_function_unit "fpu2" 2 0 |
579 | (and (eq_attr "type" "fp") | |
4652f1d4 | 580 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 581 | 2 1) |
cfb557c4 | 582 | |
3cb999d8 DE |
583 | (define_function_unit "fpu2" 2 0 |
584 | (and (eq_attr "type" "fp") | |
585 | (eq_attr "cpu" "ppc630")) | |
586 | 3 1) | |
587 | ||
cfb557c4 RK |
588 | (define_function_unit "fpu2" 2 0 |
589 | (and (eq_attr "type" "dmul") | |
590 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 591 | 2 1) |
cfb557c4 | 592 | |
3cb999d8 DE |
593 | (define_function_unit "fpu2" 2 0 |
594 | (and (eq_attr "type" "dmul") | |
595 | (eq_attr "cpu" "ppc630")) | |
596 | 3 1) | |
597 | ||
cfb557c4 | 598 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 599 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 600 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 601 | 17 17) |
ca7f5001 | 602 | |
3cb999d8 DE |
603 | (define_function_unit "fpu2" 2 0 |
604 | (and (eq_attr "type" "sdiv") | |
605 | (eq_attr "cpu" "ppc630")) | |
606 | 17 17) | |
607 | ||
608 | (define_function_unit "fpu2" 2 0 | |
609 | (and (eq_attr "type" "ddiv") | |
610 | (eq_attr "cpu" "ppc630")) | |
611 | 21 21) | |
612 | ||
ca7f5001 | 613 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 614 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 615 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 616 | 26 26) |
b6c9286a | 617 | |
3cb999d8 DE |
618 | (define_function_unit "fpu2" 2 0 |
619 | (and (eq_attr "type" "ssqrt") | |
620 | (eq_attr "cpu" "ppc630")) | |
621 | 18 18) | |
622 | ||
623 | (define_function_unit "fpu2" 2 0 | |
624 | (and (eq_attr "type" "dsqrt") | |
625 | (eq_attr "cpu" "ppc630")) | |
626 | 26 26) | |
627 | ||
1fd4e8c1 RK |
628 | \f |
629 | ;; Start with fixed-point load and store insns. Here we put only the more | |
630 | ;; complex forms. Basic data transfer is done later. | |
631 | ||
51b8fc2c RK |
632 | (define_expand "zero_extendqidi2" |
633 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
634 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
635 | "TARGET_POWERPC64" | |
636 | "") | |
637 | ||
638 | (define_insn "" | |
639 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
640 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
641 | "TARGET_POWERPC64" | |
642 | "@ | |
643 | lbz%U1%X1 %0,%1 | |
4371f8af | 644 | rldicl %0,%1,0,56" |
51b8fc2c RK |
645 | [(set_attr "type" "load,*")]) |
646 | ||
647 | (define_insn "" | |
9ebbca7d GK |
648 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
649 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 650 | (const_int 0))) |
9ebbca7d | 651 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 652 | "TARGET_POWERPC64" |
9ebbca7d GK |
653 | "@ |
654 | rldicl. %2,%1,0,56 | |
655 | #" | |
656 | [(set_attr "type" "compare") | |
657 | (set_attr "length" "4,8")]) | |
658 | ||
659 | (define_split | |
660 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
661 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
662 | (const_int 0))) | |
663 | (clobber (match_scratch:DI 2 ""))] | |
664 | "TARGET_POWERPC64 && reload_completed" | |
665 | [(set (match_dup 2) | |
666 | (zero_extend:DI (match_dup 1))) | |
667 | (set (match_dup 0) | |
668 | (compare:CC (match_dup 2) | |
669 | (const_int 0)))] | |
670 | "") | |
51b8fc2c RK |
671 | |
672 | (define_insn "" | |
9ebbca7d GK |
673 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
674 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 675 | (const_int 0))) |
9ebbca7d | 676 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 677 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 678 | "TARGET_POWERPC64" |
9ebbca7d GK |
679 | "@ |
680 | rldicl. %0,%1,0,56 | |
681 | #" | |
682 | [(set_attr "type" "compare") | |
683 | (set_attr "length" "4,8")]) | |
684 | ||
685 | (define_split | |
686 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
687 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
688 | (const_int 0))) | |
689 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
690 | (zero_extend:DI (match_dup 1)))] | |
691 | "TARGET_POWERPC64 && reload_completed" | |
692 | [(set (match_dup 0) | |
693 | (zero_extend:DI (match_dup 1))) | |
694 | (set (match_dup 2) | |
695 | (compare:CC (match_dup 0) | |
696 | (const_int 0)))] | |
697 | "") | |
51b8fc2c | 698 | |
2bee0449 RK |
699 | (define_insn "extendqidi2" |
700 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
701 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 702 | "TARGET_POWERPC64" |
2bee0449 | 703 | "extsb %0,%1") |
51b8fc2c RK |
704 | |
705 | (define_insn "" | |
9ebbca7d GK |
706 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
707 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 708 | (const_int 0))) |
9ebbca7d | 709 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 710 | "TARGET_POWERPC64" |
9ebbca7d GK |
711 | "@ |
712 | extsb. %2,%1 | |
713 | #" | |
714 | [(set_attr "type" "compare") | |
715 | (set_attr "length" "4,8")]) | |
716 | ||
717 | (define_split | |
718 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
719 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
720 | (const_int 0))) | |
721 | (clobber (match_scratch:DI 2 ""))] | |
722 | "TARGET_POWERPC64 && reload_completed" | |
723 | [(set (match_dup 2) | |
724 | (sign_extend:DI (match_dup 1))) | |
725 | (set (match_dup 0) | |
726 | (compare:CC (match_dup 2) | |
727 | (const_int 0)))] | |
728 | "") | |
51b8fc2c RK |
729 | |
730 | (define_insn "" | |
9ebbca7d GK |
731 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
732 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 733 | (const_int 0))) |
9ebbca7d | 734 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
735 | (sign_extend:DI (match_dup 1)))] |
736 | "TARGET_POWERPC64" | |
9ebbca7d GK |
737 | "@ |
738 | extsb. %0,%1 | |
739 | #" | |
740 | [(set_attr "type" "compare") | |
741 | (set_attr "length" "4,8")]) | |
742 | ||
743 | (define_split | |
744 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
745 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
746 | (const_int 0))) | |
747 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
748 | (sign_extend:DI (match_dup 1)))] | |
749 | "TARGET_POWERPC64 && reload_completed" | |
750 | [(set (match_dup 0) | |
751 | (sign_extend:DI (match_dup 1))) | |
752 | (set (match_dup 2) | |
753 | (compare:CC (match_dup 0) | |
754 | (const_int 0)))] | |
755 | "") | |
51b8fc2c RK |
756 | |
757 | (define_expand "zero_extendhidi2" | |
758 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
759 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
760 | "TARGET_POWERPC64" | |
761 | "") | |
762 | ||
763 | (define_insn "" | |
764 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
765 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
766 | "TARGET_POWERPC64" | |
767 | "@ | |
768 | lhz%U1%X1 %0,%1 | |
4371f8af | 769 | rldicl %0,%1,0,48" |
51b8fc2c RK |
770 | [(set_attr "type" "load,*")]) |
771 | ||
772 | (define_insn "" | |
9ebbca7d GK |
773 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
774 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 775 | (const_int 0))) |
9ebbca7d | 776 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 777 | "TARGET_POWERPC64" |
9ebbca7d GK |
778 | "@ |
779 | rldicl. %2,%1,0,48 | |
780 | #" | |
781 | [(set_attr "type" "compare") | |
782 | (set_attr "length" "4,8")]) | |
783 | ||
784 | (define_split | |
785 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
786 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
787 | (const_int 0))) | |
788 | (clobber (match_scratch:DI 2 ""))] | |
789 | "TARGET_POWERPC64 && reload_completed" | |
790 | [(set (match_dup 2) | |
791 | (zero_extend:DI (match_dup 1))) | |
792 | (set (match_dup 0) | |
793 | (compare:CC (match_dup 2) | |
794 | (const_int 0)))] | |
795 | "") | |
51b8fc2c RK |
796 | |
797 | (define_insn "" | |
9ebbca7d GK |
798 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
799 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 800 | (const_int 0))) |
9ebbca7d | 801 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
802 | (zero_extend:DI (match_dup 1)))] |
803 | "TARGET_POWERPC64" | |
9ebbca7d GK |
804 | "@ |
805 | rldicl. %0,%1,0,48 | |
806 | #" | |
807 | [(set_attr "type" "compare") | |
808 | (set_attr "length" "4,8")]) | |
809 | ||
810 | (define_split | |
811 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
812 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
813 | (const_int 0))) | |
814 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
815 | (zero_extend:DI (match_dup 1)))] | |
816 | "TARGET_POWERPC64 && reload_completed" | |
817 | [(set (match_dup 0) | |
818 | (zero_extend:DI (match_dup 1))) | |
819 | (set (match_dup 2) | |
820 | (compare:CC (match_dup 0) | |
821 | (const_int 0)))] | |
822 | "") | |
51b8fc2c RK |
823 | |
824 | (define_expand "extendhidi2" | |
825 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
826 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
827 | "TARGET_POWERPC64" | |
828 | "") | |
829 | ||
830 | (define_insn "" | |
831 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
832 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
833 | "TARGET_POWERPC64" | |
834 | "@ | |
835 | lha%U1%X1 %0,%1 | |
836 | extsh %0,%1" | |
837 | [(set_attr "type" "load,*")]) | |
838 | ||
839 | (define_insn "" | |
9ebbca7d GK |
840 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
841 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 842 | (const_int 0))) |
9ebbca7d | 843 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 844 | "TARGET_POWERPC64" |
9ebbca7d GK |
845 | "@ |
846 | extsh. %2,%1 | |
847 | #" | |
848 | [(set_attr "type" "compare") | |
849 | (set_attr "length" "4,8")]) | |
850 | ||
851 | (define_split | |
852 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
853 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
854 | (const_int 0))) | |
855 | (clobber (match_scratch:DI 2 ""))] | |
856 | "TARGET_POWERPC64 && reload_completed" | |
857 | [(set (match_dup 2) | |
858 | (sign_extend:DI (match_dup 1))) | |
859 | (set (match_dup 0) | |
860 | (compare:CC (match_dup 2) | |
861 | (const_int 0)))] | |
862 | "") | |
51b8fc2c RK |
863 | |
864 | (define_insn "" | |
9ebbca7d GK |
865 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
866 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 867 | (const_int 0))) |
9ebbca7d | 868 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
869 | (sign_extend:DI (match_dup 1)))] |
870 | "TARGET_POWERPC64" | |
9ebbca7d GK |
871 | "@ |
872 | extsh. %0,%1 | |
873 | #" | |
874 | [(set_attr "type" "compare") | |
875 | (set_attr "length" "4,8")]) | |
876 | ||
877 | (define_split | |
878 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
879 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
880 | (const_int 0))) | |
881 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
882 | (sign_extend:DI (match_dup 1)))] | |
883 | "TARGET_POWERPC64 && reload_completed" | |
884 | [(set (match_dup 0) | |
885 | (sign_extend:DI (match_dup 1))) | |
886 | (set (match_dup 2) | |
887 | (compare:CC (match_dup 0) | |
888 | (const_int 0)))] | |
889 | "") | |
51b8fc2c RK |
890 | |
891 | (define_expand "zero_extendsidi2" | |
892 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
893 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
894 | "TARGET_POWERPC64" | |
895 | "") | |
896 | ||
897 | (define_insn "" | |
898 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
899 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
900 | "TARGET_POWERPC64" | |
901 | "@ | |
902 | lwz%U1%X1 %0,%1 | |
903 | rldicl %0,%1,0,32" | |
904 | [(set_attr "type" "load,*")]) | |
905 | ||
906 | (define_insn "" | |
9ebbca7d GK |
907 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
908 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 909 | (const_int 0))) |
9ebbca7d | 910 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 911 | "TARGET_POWERPC64" |
9ebbca7d GK |
912 | "@ |
913 | rldicl. %2,%1,0,32 | |
914 | #" | |
915 | [(set_attr "type" "compare") | |
916 | (set_attr "length" "4,8")]) | |
917 | ||
918 | (define_split | |
919 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
920 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
921 | (const_int 0))) | |
922 | (clobber (match_scratch:DI 2 ""))] | |
923 | "TARGET_POWERPC64 && reload_completed" | |
924 | [(set (match_dup 2) | |
925 | (zero_extend:DI (match_dup 1))) | |
926 | (set (match_dup 0) | |
927 | (compare:CC (match_dup 2) | |
928 | (const_int 0)))] | |
929 | "") | |
51b8fc2c RK |
930 | |
931 | (define_insn "" | |
9ebbca7d GK |
932 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
933 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 934 | (const_int 0))) |
9ebbca7d | 935 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
936 | (zero_extend:DI (match_dup 1)))] |
937 | "TARGET_POWERPC64" | |
9ebbca7d GK |
938 | "@ |
939 | rldicl. %0,%1,0,32 | |
940 | #" | |
941 | [(set_attr "type" "compare") | |
942 | (set_attr "length" "4,8")]) | |
943 | ||
944 | (define_split | |
945 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
946 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
947 | (const_int 0))) | |
948 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
949 | (zero_extend:DI (match_dup 1)))] | |
950 | "TARGET_POWERPC64 && reload_completed" | |
951 | [(set (match_dup 0) | |
952 | (zero_extend:DI (match_dup 1))) | |
953 | (set (match_dup 2) | |
954 | (compare:CC (match_dup 0) | |
955 | (const_int 0)))] | |
956 | "") | |
51b8fc2c RK |
957 | |
958 | (define_expand "extendsidi2" | |
959 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
960 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
961 | "TARGET_POWERPC64" | |
962 | "") | |
963 | ||
964 | (define_insn "" | |
965 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 966 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
967 | "TARGET_POWERPC64" |
968 | "@ | |
969 | lwa%U1%X1 %0,%1 | |
970 | extsw %0,%1" | |
971 | [(set_attr "type" "load,*")]) | |
972 | ||
973 | (define_insn "" | |
9ebbca7d GK |
974 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
975 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 976 | (const_int 0))) |
9ebbca7d | 977 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 978 | "TARGET_POWERPC64" |
9ebbca7d GK |
979 | "@ |
980 | extsw. %2,%1 | |
981 | #" | |
982 | [(set_attr "type" "compare") | |
983 | (set_attr "length" "4,8")]) | |
984 | ||
985 | (define_split | |
986 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
987 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
988 | (const_int 0))) | |
989 | (clobber (match_scratch:DI 2 ""))] | |
990 | "TARGET_POWERPC64 && reload_completed" | |
991 | [(set (match_dup 2) | |
992 | (sign_extend:DI (match_dup 1))) | |
993 | (set (match_dup 0) | |
994 | (compare:CC (match_dup 2) | |
995 | (const_int 0)))] | |
996 | "") | |
51b8fc2c RK |
997 | |
998 | (define_insn "" | |
9ebbca7d GK |
999 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1000 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1001 | (const_int 0))) |
9ebbca7d | 1002 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1003 | (sign_extend:DI (match_dup 1)))] |
1004 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1005 | "@ |
1006 | extsw. %0,%1 | |
1007 | #" | |
1008 | [(set_attr "type" "compare") | |
1009 | (set_attr "length" "4,8")]) | |
1010 | ||
1011 | (define_split | |
1012 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1013 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1014 | (const_int 0))) | |
1015 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1016 | (sign_extend:DI (match_dup 1)))] | |
1017 | "TARGET_POWERPC64 && reload_completed" | |
1018 | [(set (match_dup 0) | |
1019 | (sign_extend:DI (match_dup 1))) | |
1020 | (set (match_dup 2) | |
1021 | (compare:CC (match_dup 0) | |
1022 | (const_int 0)))] | |
1023 | "") | |
51b8fc2c | 1024 | |
1fd4e8c1 | 1025 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
1026 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1027 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1028 | "" |
1029 | "") | |
1030 | ||
1031 | (define_insn "" | |
cd2b37d9 | 1032 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1033 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1034 | "" | |
1035 | "@ | |
1036 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1037 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
1038 | [(set_attr "type" "load,*")]) |
1039 | ||
1040 | (define_insn "" | |
9ebbca7d GK |
1041 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1042 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1043 | (const_int 0))) |
9ebbca7d | 1044 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1045 | "" |
9ebbca7d GK |
1046 | "@ |
1047 | {andil.|andi.} %2,%1,0xff | |
1048 | #" | |
1049 | [(set_attr "type" "compare") | |
1050 | (set_attr "length" "4,8")]) | |
1051 | ||
1052 | (define_split | |
1053 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1054 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1055 | (const_int 0))) | |
1056 | (clobber (match_scratch:SI 2 ""))] | |
1057 | "reload_completed" | |
1058 | [(set (match_dup 2) | |
1059 | (zero_extend:SI (match_dup 1))) | |
1060 | (set (match_dup 0) | |
1061 | (compare:CC (match_dup 2) | |
1062 | (const_int 0)))] | |
1063 | "") | |
1fd4e8c1 RK |
1064 | |
1065 | (define_insn "" | |
9ebbca7d GK |
1066 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1067 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1068 | (const_int 0))) |
9ebbca7d | 1069 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1070 | (zero_extend:SI (match_dup 1)))] |
1071 | "" | |
9ebbca7d GK |
1072 | "@ |
1073 | {andil.|andi.} %0,%1,0xff | |
1074 | #" | |
1075 | [(set_attr "type" "compare") | |
1076 | (set_attr "length" "4,8")]) | |
1077 | ||
1078 | (define_split | |
1079 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1080 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1081 | (const_int 0))) | |
1082 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1083 | (zero_extend:SI (match_dup 1)))] | |
1084 | "reload_completed" | |
1085 | [(set (match_dup 0) | |
1086 | (zero_extend:SI (match_dup 1))) | |
1087 | (set (match_dup 2) | |
1088 | (compare:CC (match_dup 0) | |
1089 | (const_int 0)))] | |
1090 | "") | |
1fd4e8c1 | 1091 | |
51b8fc2c RK |
1092 | (define_expand "extendqisi2" |
1093 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1094 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1095 | "" | |
1096 | " | |
1097 | { | |
1098 | if (TARGET_POWERPC) | |
1099 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
1100 | else if (TARGET_POWER) | |
1101 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
1102 | else | |
1103 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
1104 | DONE; | |
1105 | }") | |
1106 | ||
1107 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
1108 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1109 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 1110 | "TARGET_POWERPC" |
2bee0449 | 1111 | "extsb %0,%1") |
51b8fc2c RK |
1112 | |
1113 | (define_insn "" | |
9ebbca7d GK |
1114 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1115 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1116 | (const_int 0))) |
9ebbca7d | 1117 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 1118 | "TARGET_POWERPC" |
9ebbca7d GK |
1119 | "@ |
1120 | extsb. %2,%1 | |
1121 | #" | |
1122 | [(set_attr "type" "compare") | |
1123 | (set_attr "length" "4,8")]) | |
1124 | ||
1125 | (define_split | |
1126 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1127 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1128 | (const_int 0))) | |
1129 | (clobber (match_scratch:SI 2 ""))] | |
1130 | "TARGET_POWERPC && reload_completed" | |
1131 | [(set (match_dup 2) | |
1132 | (sign_extend:SI (match_dup 1))) | |
1133 | (set (match_dup 0) | |
1134 | (compare:CC (match_dup 2) | |
1135 | (const_int 0)))] | |
1136 | "") | |
51b8fc2c RK |
1137 | |
1138 | (define_insn "" | |
9ebbca7d GK |
1139 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1140 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1141 | (const_int 0))) |
9ebbca7d | 1142 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1143 | (sign_extend:SI (match_dup 1)))] |
1144 | "TARGET_POWERPC" | |
9ebbca7d GK |
1145 | "@ |
1146 | extsb. %0,%1 | |
1147 | #" | |
1148 | [(set_attr "type" "compare") | |
1149 | (set_attr "length" "4,8")]) | |
1150 | ||
1151 | (define_split | |
1152 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1153 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1154 | (const_int 0))) | |
1155 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1156 | (sign_extend:SI (match_dup 1)))] | |
1157 | "TARGET_POWERPC && reload_completed" | |
1158 | [(set (match_dup 0) | |
1159 | (sign_extend:SI (match_dup 1))) | |
1160 | (set (match_dup 2) | |
1161 | (compare:CC (match_dup 0) | |
1162 | (const_int 0)))] | |
1163 | "") | |
51b8fc2c RK |
1164 | |
1165 | (define_expand "extendqisi2_power" | |
1166 | [(parallel [(set (match_dup 2) | |
1167 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1168 | (const_int 24))) | |
1169 | (clobber (scratch:SI))]) | |
1170 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1171 | (ashiftrt:SI (match_dup 2) | |
1172 | (const_int 24))) | |
1173 | (clobber (scratch:SI))])] | |
1174 | "TARGET_POWER" | |
1175 | " | |
1176 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1177 | operands[2] = gen_reg_rtx (SImode); }") | |
1178 | ||
1179 | (define_expand "extendqisi2_no_power" | |
1180 | [(set (match_dup 2) | |
1181 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1182 | (const_int 24))) | |
1183 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1184 | (ashiftrt:SI (match_dup 2) | |
1185 | (const_int 24)))] | |
1186 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1187 | " | |
1188 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1189 | operands[2] = gen_reg_rtx (SImode); }") | |
1190 | ||
1fd4e8c1 | 1191 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
1192 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
1193 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1194 | "" |
1195 | "") | |
1196 | ||
1197 | (define_insn "" | |
cd2b37d9 | 1198 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1199 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1200 | "" | |
1201 | "@ | |
1202 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1203 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
1204 | [(set_attr "type" "load,*")]) |
1205 | ||
1206 | (define_insn "" | |
9ebbca7d GK |
1207 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1208 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1209 | (const_int 0))) |
9ebbca7d | 1210 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 1211 | "" |
9ebbca7d GK |
1212 | "@ |
1213 | {andil.|andi.} %2,%1,0xff | |
1214 | #" | |
1215 | [(set_attr "type" "compare") | |
1216 | (set_attr "length" "4,8")]) | |
1217 | ||
1218 | (define_split | |
1219 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1220 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1221 | (const_int 0))) | |
1222 | (clobber (match_scratch:HI 2 ""))] | |
1223 | "reload_completed" | |
1224 | [(set (match_dup 2) | |
1225 | (zero_extend:HI (match_dup 1))) | |
1226 | (set (match_dup 0) | |
1227 | (compare:CC (match_dup 2) | |
1228 | (const_int 0)))] | |
1229 | "") | |
1fd4e8c1 | 1230 | |
51b8fc2c | 1231 | (define_insn "" |
9ebbca7d GK |
1232 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1233 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1234 | (const_int 0))) |
9ebbca7d | 1235 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
1236 | (zero_extend:HI (match_dup 1)))] |
1237 | "" | |
9ebbca7d GK |
1238 | "@ |
1239 | {andil.|andi.} %0,%1,0xff | |
1240 | #" | |
1241 | [(set_attr "type" "compare") | |
1242 | (set_attr "length" "4,8")]) | |
1243 | ||
1244 | (define_split | |
1245 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1246 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1247 | (const_int 0))) | |
1248 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1249 | (zero_extend:HI (match_dup 1)))] | |
1250 | "reload_completed" | |
1251 | [(set (match_dup 0) | |
1252 | (zero_extend:HI (match_dup 1))) | |
1253 | (set (match_dup 2) | |
1254 | (compare:CC (match_dup 0) | |
1255 | (const_int 0)))] | |
1256 | "") | |
815cdc52 MM |
1257 | |
1258 | (define_expand "extendqihi2" | |
1259 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
1260 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1261 | "" | |
1262 | " | |
1263 | { | |
1264 | if (TARGET_POWERPC) | |
1265 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
1266 | else if (TARGET_POWER) | |
1267 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
1268 | else | |
1269 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
1270 | DONE; | |
1271 | }") | |
1272 | ||
1273 | (define_insn "extendqihi2_ppc" | |
1274 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
1275 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
1276 | "TARGET_POWERPC" | |
1277 | "extsb %0,%1") | |
1278 | ||
1279 | (define_insn "" | |
9ebbca7d GK |
1280 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1281 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1282 | (const_int 0))) |
9ebbca7d | 1283 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 1284 | "TARGET_POWERPC" |
9ebbca7d GK |
1285 | "@ |
1286 | extsb. %2,%1 | |
1287 | #" | |
1288 | [(set_attr "type" "compare") | |
1289 | (set_attr "length" "4,8")]) | |
1290 | ||
1291 | (define_split | |
1292 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1293 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1294 | (const_int 0))) | |
1295 | (clobber (match_scratch:HI 2 ""))] | |
1296 | "TARGET_POWERPC && reload_completed" | |
1297 | [(set (match_dup 2) | |
1298 | (sign_extend:HI (match_dup 1))) | |
1299 | (set (match_dup 0) | |
1300 | (compare:CC (match_dup 2) | |
1301 | (const_int 0)))] | |
1302 | "") | |
815cdc52 MM |
1303 | |
1304 | (define_insn "" | |
9ebbca7d GK |
1305 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1306 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1307 | (const_int 0))) |
9ebbca7d | 1308 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1309 | (sign_extend:HI (match_dup 1)))] |
1310 | "TARGET_POWERPC" | |
9ebbca7d GK |
1311 | "@ |
1312 | extsb. %0,%1 | |
1313 | #" | |
1314 | [(set_attr "type" "compare") | |
1315 | (set_attr "length" "4,8")]) | |
1316 | ||
1317 | (define_split | |
1318 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1319 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1320 | (const_int 0))) | |
1321 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1322 | (sign_extend:HI (match_dup 1)))] | |
1323 | "TARGET_POWERPC && reload_completed" | |
1324 | [(set (match_dup 0) | |
1325 | (sign_extend:HI (match_dup 1))) | |
1326 | (set (match_dup 2) | |
1327 | (compare:CC (match_dup 0) | |
1328 | (const_int 0)))] | |
1329 | "") | |
51b8fc2c RK |
1330 | |
1331 | (define_expand "extendqihi2_power" | |
1332 | [(parallel [(set (match_dup 2) | |
1333 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1334 | (const_int 24))) | |
1335 | (clobber (scratch:SI))]) | |
1336 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
1337 | (ashiftrt:SI (match_dup 2) | |
1338 | (const_int 24))) | |
1339 | (clobber (scratch:SI))])] | |
1340 | "TARGET_POWER" | |
1341 | " | |
1342 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1343 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1344 | operands[2] = gen_reg_rtx (SImode); }") | |
1345 | ||
1346 | (define_expand "extendqihi2_no_power" | |
1347 | [(set (match_dup 2) | |
1348 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1349 | (const_int 24))) | |
1350 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1351 | (ashiftrt:SI (match_dup 2) | |
1352 | (const_int 24)))] | |
1353 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1354 | " | |
1355 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1356 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1357 | operands[2] = gen_reg_rtx (SImode); }") | |
1358 | ||
1fd4e8c1 | 1359 | (define_expand "zero_extendhisi2" |
5f243543 | 1360 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 1361 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
1362 | "" |
1363 | "") | |
1364 | ||
1365 | (define_insn "" | |
cd2b37d9 | 1366 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1367 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1368 | "" | |
1369 | "@ | |
1370 | lhz%U1%X1 %0,%1 | |
005a35b9 | 1371 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
1372 | [(set_attr "type" "load,*")]) |
1373 | ||
1374 | (define_insn "" | |
9ebbca7d GK |
1375 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1376 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1377 | (const_int 0))) |
9ebbca7d | 1378 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1379 | "" |
9ebbca7d GK |
1380 | "@ |
1381 | {andil.|andi.} %2,%1,0xffff | |
1382 | #" | |
1383 | [(set_attr "type" "compare") | |
1384 | (set_attr "length" "4,8")]) | |
1385 | ||
1386 | (define_split | |
1387 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1388 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1389 | (const_int 0))) | |
1390 | (clobber (match_scratch:SI 2 ""))] | |
1391 | "reload_completed" | |
1392 | [(set (match_dup 2) | |
1393 | (zero_extend:SI (match_dup 1))) | |
1394 | (set (match_dup 0) | |
1395 | (compare:CC (match_dup 2) | |
1396 | (const_int 0)))] | |
1397 | "") | |
1fd4e8c1 RK |
1398 | |
1399 | (define_insn "" | |
9ebbca7d GK |
1400 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1401 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1402 | (const_int 0))) |
9ebbca7d | 1403 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1404 | (zero_extend:SI (match_dup 1)))] |
1405 | "" | |
9ebbca7d GK |
1406 | "@ |
1407 | {andil.|andi.} %0,%1,0xffff | |
1408 | #" | |
1409 | [(set_attr "type" "compare") | |
1410 | (set_attr "length" "4,8")]) | |
1411 | ||
1412 | (define_split | |
1413 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1414 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1415 | (const_int 0))) | |
1416 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1417 | (zero_extend:SI (match_dup 1)))] | |
1418 | "reload_completed" | |
1419 | [(set (match_dup 0) | |
1420 | (zero_extend:SI (match_dup 1))) | |
1421 | (set (match_dup 2) | |
1422 | (compare:CC (match_dup 0) | |
1423 | (const_int 0)))] | |
1424 | "") | |
1fd4e8c1 RK |
1425 | |
1426 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
1427 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1428 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1429 | "" |
1430 | "") | |
1431 | ||
1432 | (define_insn "" | |
cd2b37d9 | 1433 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1434 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1435 | "" | |
1436 | "@ | |
1437 | lha%U1%X1 %0,%1 | |
ca7f5001 | 1438 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
1439 | [(set_attr "type" "load,*")]) |
1440 | ||
1441 | (define_insn "" | |
9ebbca7d GK |
1442 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1443 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1444 | (const_int 0))) |
9ebbca7d | 1445 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1446 | "" |
9ebbca7d GK |
1447 | "@ |
1448 | {exts.|extsh.} %2,%1 | |
1449 | #" | |
1450 | [(set_attr "type" "compare") | |
1451 | (set_attr "length" "4,8")]) | |
1452 | ||
1453 | (define_split | |
1454 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1455 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1456 | (const_int 0))) | |
1457 | (clobber (match_scratch:SI 2 ""))] | |
1458 | "reload_completed" | |
1459 | [(set (match_dup 2) | |
1460 | (sign_extend:SI (match_dup 1))) | |
1461 | (set (match_dup 0) | |
1462 | (compare:CC (match_dup 2) | |
1463 | (const_int 0)))] | |
1464 | "") | |
1fd4e8c1 RK |
1465 | |
1466 | (define_insn "" | |
9ebbca7d GK |
1467 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1468 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1469 | (const_int 0))) |
9ebbca7d | 1470 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1471 | (sign_extend:SI (match_dup 1)))] |
1472 | "" | |
9ebbca7d GK |
1473 | "@ |
1474 | {exts.|extsh.} %0,%1 | |
1475 | #" | |
1476 | [(set_attr "type" "compare") | |
1477 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1478 | \f |
9ebbca7d GK |
1479 | (define_split |
1480 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1481 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1482 | (const_int 0))) | |
1483 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1484 | (sign_extend:SI (match_dup 1)))] | |
1485 | "reload_completed" | |
1486 | [(set (match_dup 0) | |
1487 | (sign_extend:SI (match_dup 1))) | |
1488 | (set (match_dup 2) | |
1489 | (compare:CC (match_dup 0) | |
1490 | (const_int 0)))] | |
1491 | "") | |
1492 | ||
1fd4e8c1 | 1493 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
1494 | |
1495 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
1496 | ;; allowing register zero as source. | |
7cd5235b MM |
1497 | (define_expand "addsi3" |
1498 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1499 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 1500 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
1501 | "" |
1502 | " | |
1503 | { | |
677a9668 DE |
1504 | if (GET_CODE (operands[2]) == CONST_INT |
1505 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 1506 | { |
677a9668 | 1507 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
1508 | ? operands[0] : gen_reg_rtx (SImode)); |
1509 | ||
2bfcf297 DB |
1510 | HOST_WIDE_INT val = INTVAL (operands[2]); |
1511 | HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); | |
1512 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); | |
7cd5235b | 1513 | |
9ebbca7d GK |
1514 | /* The ordering here is important for the prolog expander. |
1515 | When space is allocated from the stack, adding 'low' first may | |
1516 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 1517 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
1518 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
1519 | DONE; | |
1520 | } | |
1521 | }") | |
1522 | ||
1523 | (define_insn "*addsi3_internal1" | |
1524 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1525 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1526 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1527 | "" |
1528 | "@ | |
deb9225a RK |
1529 | {cax|add} %0,%1,%2 |
1530 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1531 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1532 | {cau|addis} %0,%1,%v2" |
1533 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1534 | |
ee890fe2 SS |
1535 | (define_insn "addsi3_high" |
1536 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1537 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1538 | (high:SI (match_operand 2 "" ""))))] | |
1539 | "TARGET_MACHO && !TARGET_64BIT" | |
1540 | "{cau|addis} %0,%1,ha16(%2)" | |
1541 | [(set_attr "length" "4")]) | |
1542 | ||
7cd5235b | 1543 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1544 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1545 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1546 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1547 | (const_int 0))) |
cb8cc086 | 1548 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1549 | "! TARGET_POWERPC64" |
deb9225a RK |
1550 | "@ |
1551 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1552 | {ai.|addic.} %3,%1,%2 |
1553 | # | |
1554 | #" | |
1555 | [(set_attr "type" "compare") | |
1556 | (set_attr "length" "4,4,8,8")]) | |
1557 | ||
1558 | (define_split | |
1559 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1560 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1561 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1562 | (const_int 0))) | |
1563 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1564 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1565 | [(set (match_dup 3) |
1566 | (plus:SI (match_dup 1) | |
1567 | (match_dup 2))) | |
1568 | (set (match_dup 0) | |
1569 | (compare:CC (match_dup 3) | |
1570 | (const_int 0)))] | |
1571 | "") | |
7e69e155 | 1572 | |
7cd5235b | 1573 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1574 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1575 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1576 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1577 | (const_int 0))) |
cb8cc086 MM |
1578 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1579 | (plus:SI (match_dup 1) | |
1580 | (match_dup 2)))] | |
0ad91047 | 1581 | "! TARGET_POWERPC64" |
deb9225a RK |
1582 | "@ |
1583 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1584 | {ai.|addic.} %0,%1,%2 |
1585 | # | |
1586 | #" | |
1587 | [(set_attr "type" "compare") | |
1588 | (set_attr "length" "4,4,8,8")]) | |
1589 | ||
1590 | (define_split | |
1591 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1592 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1593 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1594 | (const_int 0))) | |
1595 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1596 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1597 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1598 | [(set (match_dup 0) |
1599 | (plus:SI (match_dup 1) | |
1600 | (match_dup 2))) | |
1601 | (set (match_dup 3) | |
1602 | (compare:CC (match_dup 0) | |
1603 | (const_int 0)))] | |
1604 | "") | |
7e69e155 | 1605 | |
f357808b RK |
1606 | ;; Split an add that we can't do in one insn into two insns, each of which |
1607 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1608 | ;; add should be last in case the result gets used in an address. | |
1609 | ||
1610 | (define_split | |
cd2b37d9 RK |
1611 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1612 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1613 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1614 | "" |
f357808b RK |
1615 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1616 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1617 | " | |
1fd4e8c1 | 1618 | { |
2bfcf297 DB |
1619 | HOST_WIDE_INT val = INTVAL (operands[2]); |
1620 | HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); | |
1621 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); | |
1fd4e8c1 | 1622 | |
2bfcf297 | 1623 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1624 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1625 | }") |
1626 | ||
8de2a197 | 1627 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1628 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1629 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1630 | "" |
ca7f5001 RK |
1631 | "nor %0,%1,%1") |
1632 | ||
1633 | (define_insn "" | |
52d3af72 DE |
1634 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1635 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1636 | (const_int 0))) |
52d3af72 | 1637 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1638 | "! TARGET_POWERPC64" |
52d3af72 DE |
1639 | "@ |
1640 | nor. %2,%1,%1 | |
1641 | #" | |
1642 | [(set_attr "type" "compare") | |
1643 | (set_attr "length" "4,8")]) | |
1644 | ||
1645 | (define_split | |
1646 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1647 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1648 | (const_int 0))) | |
1649 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1650 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1651 | [(set (match_dup 2) |
1652 | (not:SI (match_dup 1))) | |
1653 | (set (match_dup 0) | |
1654 | (compare:CC (match_dup 2) | |
1655 | (const_int 0)))] | |
1656 | "") | |
ca7f5001 RK |
1657 | |
1658 | (define_insn "" | |
52d3af72 DE |
1659 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1660 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1661 | (const_int 0))) |
52d3af72 | 1662 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1663 | (not:SI (match_dup 1)))] |
0ad91047 | 1664 | "! TARGET_POWERPC64" |
52d3af72 DE |
1665 | "@ |
1666 | nor. %0,%1,%1 | |
1667 | #" | |
1668 | [(set_attr "type" "compare") | |
1669 | (set_attr "length" "4,8")]) | |
1670 | ||
1671 | (define_split | |
1672 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1673 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1674 | (const_int 0))) | |
1cb18e3c | 1675 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1676 | (not:SI (match_dup 1)))] |
0ad91047 | 1677 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1678 | [(set (match_dup 0) |
1679 | (not:SI (match_dup 1))) | |
1680 | (set (match_dup 2) | |
1681 | (compare:CC (match_dup 0) | |
1682 | (const_int 0)))] | |
1683 | "") | |
1fd4e8c1 RK |
1684 | |
1685 | (define_insn "" | |
3d91674b RK |
1686 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1687 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1688 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1689 | "! TARGET_POWERPC" |
ca7f5001 | 1690 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1691 | |
deb9225a RK |
1692 | (define_insn "" |
1693 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1694 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1695 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1696 | "TARGET_POWERPC" | |
1697 | "@ | |
1698 | subf %0,%2,%1 | |
1699 | subfic %0,%2,%1") | |
1700 | ||
1fd4e8c1 | 1701 | (define_insn "" |
cb8cc086 MM |
1702 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1703 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1704 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1705 | (const_int 0))) |
cb8cc086 | 1706 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1707 | "! TARGET_POWERPC" |
cb8cc086 MM |
1708 | "@ |
1709 | {sf.|subfc.} %3,%2,%1 | |
1710 | #" | |
1711 | [(set_attr "type" "compare") | |
1712 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1713 | |
deb9225a | 1714 | (define_insn "" |
cb8cc086 MM |
1715 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1716 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1717 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1718 | (const_int 0))) |
cb8cc086 | 1719 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1720 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1721 | "@ |
1722 | subf. %3,%2,%1 | |
1723 | #" | |
1724 | [(set_attr "type" "compare") | |
1725 | (set_attr "length" "4,8")]) | |
1726 | ||
1727 | (define_split | |
1728 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1729 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1730 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1731 | (const_int 0))) | |
1732 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1733 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1734 | [(set (match_dup 3) |
1735 | (minus:SI (match_dup 1) | |
1736 | (match_dup 2))) | |
1737 | (set (match_dup 0) | |
1738 | (compare:CC (match_dup 3) | |
1739 | (const_int 0)))] | |
1740 | "") | |
deb9225a | 1741 | |
1fd4e8c1 | 1742 | (define_insn "" |
cb8cc086 MM |
1743 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1744 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1745 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1746 | (const_int 0))) |
cb8cc086 | 1747 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1748 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1749 | "! TARGET_POWERPC" |
cb8cc086 MM |
1750 | "@ |
1751 | {sf.|subfc.} %0,%2,%1 | |
1752 | #" | |
1753 | [(set_attr "type" "compare") | |
1754 | (set_attr "length" "4,8")]) | |
815cdc52 | 1755 | |
29ae5b89 | 1756 | (define_insn "" |
cb8cc086 MM |
1757 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1758 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1759 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1760 | (const_int 0))) |
cb8cc086 MM |
1761 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1762 | (minus:SI (match_dup 1) | |
1763 | (match_dup 2)))] | |
0ad91047 | 1764 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1765 | "@ |
1766 | subf. %0,%2,%1 | |
1767 | #" | |
cb8cc086 MM |
1768 | [(set_attr "type" "compare") |
1769 | (set_attr "length" "4,8")]) | |
1770 | ||
1771 | (define_split | |
1772 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1773 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1774 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1775 | (const_int 0))) | |
1776 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1777 | (minus:SI (match_dup 1) | |
1778 | (match_dup 2)))] | |
0ad91047 | 1779 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1780 | [(set (match_dup 0) |
1781 | (minus:SI (match_dup 1) | |
1782 | (match_dup 2))) | |
1783 | (set (match_dup 3) | |
1784 | (compare:CC (match_dup 0) | |
1785 | (const_int 0)))] | |
1786 | "") | |
deb9225a | 1787 | |
1fd4e8c1 | 1788 | (define_expand "subsi3" |
cd2b37d9 | 1789 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1790 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1791 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1792 | "" |
a0044fb1 RK |
1793 | " |
1794 | { | |
1795 | if (GET_CODE (operands[2]) == CONST_INT) | |
1796 | { | |
1797 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1798 | negate_rtx (SImode, operands[2]))); | |
1799 | DONE; | |
1800 | } | |
1801 | }") | |
1fd4e8c1 RK |
1802 | |
1803 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1804 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1805 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1806 | ;; combine. | |
1fd4e8c1 RK |
1807 | |
1808 | (define_expand "sminsi3" | |
1809 | [(set (match_dup 3) | |
cd2b37d9 | 1810 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1811 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1812 | (const_int 0) | |
1813 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1814 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1815 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1816 | "TARGET_POWER" |
1fd4e8c1 RK |
1817 | " |
1818 | { operands[3] = gen_reg_rtx (SImode); }") | |
1819 | ||
95ac8e67 RK |
1820 | (define_split |
1821 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1822 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1823 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1824 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1825 | "TARGET_POWER" |
95ac8e67 RK |
1826 | [(set (match_dup 3) |
1827 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1828 | (const_int 0) | |
1829 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1830 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1831 | "") | |
1832 | ||
1fd4e8c1 RK |
1833 | (define_expand "smaxsi3" |
1834 | [(set (match_dup 3) | |
cd2b37d9 | 1835 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1836 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1837 | (const_int 0) | |
1838 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1839 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1840 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1841 | "TARGET_POWER" |
1fd4e8c1 RK |
1842 | " |
1843 | { operands[3] = gen_reg_rtx (SImode); }") | |
1844 | ||
95ac8e67 RK |
1845 | (define_split |
1846 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1847 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1848 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1849 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1850 | "TARGET_POWER" |
95ac8e67 RK |
1851 | [(set (match_dup 3) |
1852 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1853 | (const_int 0) | |
1854 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1855 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1856 | "") | |
1857 | ||
1fd4e8c1 | 1858 | (define_expand "uminsi3" |
cd2b37d9 | 1859 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1860 | (match_dup 5))) |
cd2b37d9 | 1861 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1862 | (match_dup 5))) |
1fd4e8c1 RK |
1863 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1864 | (const_int 0) | |
1865 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1866 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1867 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1868 | "TARGET_POWER" |
1fd4e8c1 | 1869 | " |
bb68ff55 MM |
1870 | { |
1871 | operands[3] = gen_reg_rtx (SImode); | |
1872 | operands[4] = gen_reg_rtx (SImode); | |
1873 | operands[5] = GEN_INT (-2147483647 - 1); | |
1874 | }") | |
1fd4e8c1 RK |
1875 | |
1876 | (define_expand "umaxsi3" | |
cd2b37d9 | 1877 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1878 | (match_dup 5))) |
cd2b37d9 | 1879 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1880 | (match_dup 5))) |
1fd4e8c1 RK |
1881 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1882 | (const_int 0) | |
1883 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1884 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1885 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1886 | "TARGET_POWER" |
1fd4e8c1 | 1887 | " |
bb68ff55 MM |
1888 | { |
1889 | operands[3] = gen_reg_rtx (SImode); | |
1890 | operands[4] = gen_reg_rtx (SImode); | |
1891 | operands[5] = GEN_INT (-2147483647 - 1); | |
1892 | }") | |
1fd4e8c1 RK |
1893 | |
1894 | (define_insn "" | |
cd2b37d9 RK |
1895 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1896 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1897 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1898 | (const_int 0) |
1899 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1900 | "TARGET_POWER" |
1fd4e8c1 RK |
1901 | "doz%I2 %0,%1,%2") |
1902 | ||
1903 | (define_insn "" | |
9ebbca7d | 1904 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1905 | (compare:CC |
9ebbca7d GK |
1906 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1907 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1908 | (const_int 0) |
1909 | (minus:SI (match_dup 2) (match_dup 1))) | |
1910 | (const_int 0))) | |
9ebbca7d | 1911 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1912 | "TARGET_POWER" |
9ebbca7d GK |
1913 | "@ |
1914 | doz%I2. %3,%1,%2 | |
1915 | #" | |
1916 | [(set_attr "type" "delayed_compare") | |
1917 | (set_attr "length" "4,8")]) | |
1918 | ||
1919 | (define_split | |
1920 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1921 | (compare:CC | |
1922 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1923 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1924 | (const_int 0) | |
1925 | (minus:SI (match_dup 2) (match_dup 1))) | |
1926 | (const_int 0))) | |
1927 | (clobber (match_scratch:SI 3 ""))] | |
1928 | "TARGET_POWER && reload_completed" | |
1929 | [(set (match_dup 3) | |
1930 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1931 | (const_int 0) | |
1932 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1933 | (set (match_dup 0) | |
1934 | (compare:CC (match_dup 3) | |
1935 | (const_int 0)))] | |
1936 | "") | |
1fd4e8c1 RK |
1937 | |
1938 | (define_insn "" | |
9ebbca7d | 1939 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1940 | (compare:CC |
9ebbca7d GK |
1941 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1942 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1943 | (const_int 0) |
1944 | (minus:SI (match_dup 2) (match_dup 1))) | |
1945 | (const_int 0))) | |
9ebbca7d | 1946 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1947 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1948 | (const_int 0) | |
1949 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1950 | "TARGET_POWER" |
9ebbca7d GK |
1951 | "@ |
1952 | doz%I2. %0,%1,%2 | |
1953 | #" | |
1954 | [(set_attr "type" "delayed_compare") | |
1955 | (set_attr "length" "4,8")]) | |
1956 | ||
1957 | (define_split | |
1958 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1959 | (compare:CC | |
1960 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1961 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1962 | (const_int 0) | |
1963 | (minus:SI (match_dup 2) (match_dup 1))) | |
1964 | (const_int 0))) | |
1965 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1966 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1967 | (const_int 0) | |
1968 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1969 | "TARGET_POWER && reload_completed" | |
1970 | [(set (match_dup 0) | |
1971 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1972 | (const_int 0) | |
1973 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1974 | (set (match_dup 3) | |
1975 | (compare:CC (match_dup 0) | |
1976 | (const_int 0)))] | |
1977 | "") | |
1fd4e8c1 RK |
1978 | |
1979 | ;; We don't need abs with condition code because such comparisons should | |
1980 | ;; never be done. | |
ea9be077 MM |
1981 | (define_expand "abssi2" |
1982 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1983 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1984 | "" | |
1985 | " | |
1986 | { | |
0ad91047 | 1987 | if (! TARGET_POWER) |
ea9be077 MM |
1988 | { |
1989 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1990 | DONE; | |
1991 | } | |
1992 | }") | |
1993 | ||
1994 | (define_insn "abssi2_power" | |
cd2b37d9 RK |
1995 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1996 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1997 | "TARGET_POWER" |
1fd4e8c1 RK |
1998 | "abs %0,%1") |
1999 | ||
ea9be077 MM |
2000 | (define_insn "abssi2_nopower" |
2001 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
2002 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
2003 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 2004 | "! TARGET_POWER" |
3595d104 MM |
2005 | "* |
2006 | { | |
2007 | return (TARGET_POWERPC) | |
2008 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" | |
2009 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; | |
2010 | }" | |
ea9be077 MM |
2011 | [(set_attr "length" "12")]) |
2012 | ||
2013 | (define_split | |
1cb18e3c DE |
2014 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2015 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2016 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 2017 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
2018 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
2019 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 2020 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
2021 | "") |
2022 | ||
463b558b | 2023 | (define_insn "*nabs_power" |
cd2b37d9 RK |
2024 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2025 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 2026 | "TARGET_POWER" |
1fd4e8c1 RK |
2027 | "nabs %0,%1") |
2028 | ||
463b558b | 2029 | (define_insn "*nabs_no_power" |
ea9be077 MM |
2030 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
2031 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
2032 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 2033 | "! TARGET_POWER" |
3595d104 MM |
2034 | "* |
2035 | { | |
2036 | return (TARGET_POWERPC) | |
2037 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" | |
2038 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; | |
2039 | }" | |
ea9be077 MM |
2040 | [(set_attr "length" "12")]) |
2041 | ||
2042 | (define_split | |
75540af0 JH |
2043 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2044 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))) | |
2045 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 2046 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
2047 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
2048 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 2049 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
2050 | "") |
2051 | ||
1fd4e8c1 | 2052 | (define_insn "negsi2" |
cd2b37d9 RK |
2053 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2054 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
2055 | "" |
2056 | "neg %0,%1") | |
2057 | ||
2058 | (define_insn "" | |
9ebbca7d GK |
2059 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2060 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2061 | (const_int 0))) |
9ebbca7d | 2062 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 2063 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2064 | "@ |
2065 | neg. %2,%1 | |
2066 | #" | |
2067 | [(set_attr "type" "compare") | |
2068 | (set_attr "length" "4,8")]) | |
2069 | ||
2070 | (define_split | |
2071 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2072 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2073 | (const_int 0))) | |
2074 | (clobber (match_scratch:SI 2 ""))] | |
2075 | "! TARGET_POWERPC64 && reload_completed" | |
2076 | [(set (match_dup 2) | |
2077 | (neg:SI (match_dup 1))) | |
2078 | (set (match_dup 0) | |
2079 | (compare:CC (match_dup 2) | |
2080 | (const_int 0)))] | |
2081 | "") | |
1fd4e8c1 RK |
2082 | |
2083 | (define_insn "" | |
9ebbca7d GK |
2084 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
2085 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2086 | (const_int 0))) |
9ebbca7d | 2087 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 2088 | (neg:SI (match_dup 1)))] |
0ad91047 | 2089 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2090 | "@ |
2091 | neg. %0,%1 | |
2092 | #" | |
2093 | [(set_attr "type" "compare") | |
2094 | (set_attr "length" "4,8")]) | |
2095 | ||
2096 | (define_split | |
2097 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
2098 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2099 | (const_int 0))) | |
2100 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2101 | (neg:SI (match_dup 1)))] | |
2102 | "! TARGET_POWERPC64 && reload_completed" | |
2103 | [(set (match_dup 0) | |
2104 | (neg:SI (match_dup 1))) | |
2105 | (set (match_dup 2) | |
2106 | (compare:CC (match_dup 0) | |
2107 | (const_int 0)))] | |
2108 | "") | |
1fd4e8c1 RK |
2109 | |
2110 | (define_insn "ffssi2" | |
242e8072 RK |
2111 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
2112 | (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 2113 | "" |
7f340546 | 2114 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 2115 | [(set_attr "length" "16")]) |
1fd4e8c1 | 2116 | |
ca7f5001 RK |
2117 | (define_expand "mulsi3" |
2118 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2119 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2120 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
2121 | "" | |
2122 | " | |
2123 | { | |
2124 | if (TARGET_POWER) | |
68b40e7e | 2125 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 2126 | else |
68b40e7e | 2127 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2128 | DONE; |
2129 | }") | |
2130 | ||
68b40e7e | 2131 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
2132 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2133 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
2134 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
2135 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
2136 | "TARGET_POWER" |
2137 | "@ | |
2138 | {muls|mullw} %0,%1,%2 | |
2139 | {muli|mulli} %0,%1,%2" | |
2140 | [(set_attr "type" "imul")]) | |
2141 | ||
68b40e7e | 2142 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
2143 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2144 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2145 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 2146 | "! TARGET_POWER" |
1fd4e8c1 | 2147 | "@ |
d904e9ed RK |
2148 | {muls|mullw} %0,%1,%2 |
2149 | {muli|mulli} %0,%1,%2" | |
cfb557c4 | 2150 | [(set_attr "type" "imul")]) |
1fd4e8c1 RK |
2151 | |
2152 | (define_insn "" | |
9ebbca7d GK |
2153 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2154 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2155 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2156 | (const_int 0))) |
9ebbca7d GK |
2157 | (clobber (match_scratch:SI 3 "=r,r")) |
2158 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 2159 | "TARGET_POWER" |
9ebbca7d GK |
2160 | "@ |
2161 | {muls.|mullw.} %3,%1,%2 | |
2162 | #" | |
2163 | [(set_attr "type" "delayed_compare") | |
2164 | (set_attr "length" "4,8")]) | |
2165 | ||
2166 | (define_split | |
2167 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2168 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2169 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2170 | (const_int 0))) | |
2171 | (clobber (match_scratch:SI 3 "")) | |
2172 | (clobber (match_scratch:SI 4 ""))] | |
2173 | "TARGET_POWER && reload_completed" | |
2174 | [(parallel [(set (match_dup 3) | |
2175 | (mult:SI (match_dup 1) (match_dup 2))) | |
2176 | (clobber (match_dup 4))]) | |
2177 | (set (match_dup 0) | |
2178 | (compare:CC (match_dup 3) | |
2179 | (const_int 0)))] | |
2180 | "") | |
ca7f5001 RK |
2181 | |
2182 | (define_insn "" | |
9ebbca7d GK |
2183 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2184 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2185 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2186 | (const_int 0))) |
9ebbca7d | 2187 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 2188 | "! TARGET_POWER" |
9ebbca7d GK |
2189 | "@ |
2190 | {muls.|mullw.} %3,%1,%2 | |
2191 | #" | |
2192 | [(set_attr "type" "delayed_compare") | |
2193 | (set_attr "length" "4,8")]) | |
2194 | ||
2195 | (define_split | |
2196 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2197 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2198 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2199 | (const_int 0))) | |
2200 | (clobber (match_scratch:SI 3 ""))] | |
2201 | "! TARGET_POWER && reload_completed" | |
2202 | [(set (match_dup 3) | |
2203 | (mult:SI (match_dup 1) (match_dup 2))) | |
2204 | (set (match_dup 0) | |
2205 | (compare:CC (match_dup 3) | |
2206 | (const_int 0)))] | |
2207 | "") | |
1fd4e8c1 RK |
2208 | |
2209 | (define_insn "" | |
9ebbca7d GK |
2210 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2211 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2212 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2213 | (const_int 0))) |
9ebbca7d | 2214 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2215 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 2216 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 2217 | "TARGET_POWER" |
9ebbca7d GK |
2218 | "@ |
2219 | {muls.|mullw.} %0,%1,%2 | |
2220 | #" | |
2221 | [(set_attr "type" "delayed_compare") | |
2222 | (set_attr "length" "4,8")]) | |
2223 | ||
2224 | (define_split | |
2225 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2226 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2227 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2228 | (const_int 0))) | |
2229 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2230 | (mult:SI (match_dup 1) (match_dup 2))) | |
2231 | (clobber (match_scratch:SI 4 ""))] | |
2232 | "TARGET_POWER && reload_completed" | |
2233 | [(parallel [(set (match_dup 0) | |
2234 | (mult:SI (match_dup 1) (match_dup 2))) | |
2235 | (clobber (match_dup 4))]) | |
2236 | (set (match_dup 3) | |
2237 | (compare:CC (match_dup 0) | |
2238 | (const_int 0)))] | |
2239 | "") | |
ca7f5001 RK |
2240 | |
2241 | (define_insn "" | |
9ebbca7d GK |
2242 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2243 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2244 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2245 | (const_int 0))) |
9ebbca7d | 2246 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 2247 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 2248 | "! TARGET_POWER" |
9ebbca7d GK |
2249 | "@ |
2250 | {muls.|mullw.} %0,%1,%2 | |
2251 | #" | |
2252 | [(set_attr "type" "delayed_compare") | |
2253 | (set_attr "length" "4,8")]) | |
2254 | ||
2255 | (define_split | |
2256 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2257 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2258 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2259 | (const_int 0))) | |
2260 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2261 | (mult:SI (match_dup 1) (match_dup 2)))] | |
2262 | "! TARGET_POWER && reload_completed" | |
2263 | [(set (match_dup 0) | |
2264 | (mult:SI (match_dup 1) (match_dup 2))) | |
2265 | (set (match_dup 3) | |
2266 | (compare:CC (match_dup 0) | |
2267 | (const_int 0)))] | |
2268 | "") | |
1fd4e8c1 RK |
2269 | |
2270 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
2271 | ;; 0 and remainder to operand 3. | |
2272 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
2273 | ||
8ffd9c51 RK |
2274 | (define_expand "divmodsi4" |
2275 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2276 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2277 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2278 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
2279 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
2280 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2281 | " | |
2282 | { | |
2283 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2284 | { | |
39403d82 DE |
2285 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2286 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2287 | emit_insn (gen_divss_call ()); |
39403d82 DE |
2288 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2289 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
2290 | DONE; |
2291 | } | |
2292 | }") | |
deb9225a | 2293 | |
fada905b | 2294 | (define_insn "" |
cd2b37d9 RK |
2295 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2296 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2297 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2298 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 2299 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 2300 | "TARGET_POWER" |
cfb557c4 RK |
2301 | "divs %0,%1,%2" |
2302 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 2303 | |
8ffd9c51 RK |
2304 | (define_expand "udivsi3" |
2305 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2306 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2307 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
2308 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2309 | " | |
2310 | { | |
2311 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2312 | { | |
39403d82 DE |
2313 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2314 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2315 | emit_insn (gen_quous_call ()); |
39403d82 | 2316 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2317 | DONE; |
2318 | } | |
f192bf8b DE |
2319 | else if (TARGET_POWER) |
2320 | { | |
2321 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
2322 | DONE; | |
2323 | } | |
8ffd9c51 | 2324 | }") |
deb9225a | 2325 | |
f192bf8b DE |
2326 | (define_insn "udivsi3_mq" |
2327 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2328 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2329 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2330 | (clobber (match_scratch:SI 3 "=q"))] | |
2331 | "TARGET_POWERPC && TARGET_POWER" | |
2332 | "divwu %0,%1,%2" | |
2333 | [(set_attr "type" "idiv")]) | |
2334 | ||
2335 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
2336 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2337 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2338 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 2339 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 2340 | "divwu %0,%1,%2" |
ca7f5001 RK |
2341 | [(set_attr "type" "idiv")]) |
2342 | ||
1fd4e8c1 | 2343 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 2344 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
2345 | ;; used; for PowerPC, force operands into register and do a normal divide; |
2346 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 2347 | (define_expand "divsi3" |
cd2b37d9 RK |
2348 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2349 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
2350 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
2351 | "" | |
2352 | " | |
2353 | { | |
ca7f5001 | 2354 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 2355 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
2356 | && exact_log2 (INTVAL (operands[2])) >= 0) |
2357 | ; | |
b6c9286a | 2358 | else if (TARGET_POWERPC) |
f192bf8b DE |
2359 | { |
2360 | operands[2] = force_reg (SImode, operands[2]); | |
2361 | if (TARGET_POWER) | |
2362 | { | |
2363 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
2364 | DONE; | |
2365 | } | |
2366 | } | |
b6c9286a | 2367 | else if (TARGET_POWER) |
1fd4e8c1 | 2368 | FAIL; |
405c5495 | 2369 | else |
8ffd9c51 | 2370 | { |
39403d82 DE |
2371 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2372 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2373 | emit_insn (gen_quoss_call ()); |
39403d82 | 2374 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2375 | DONE; |
2376 | } | |
1fd4e8c1 RK |
2377 | }") |
2378 | ||
f192bf8b DE |
2379 | (define_insn "divsi3_mq" |
2380 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2381 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2382 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2383 | (clobber (match_scratch:SI 3 "=q"))] | |
2384 | "TARGET_POWERPC && TARGET_POWER" | |
2385 | "divw %0,%1,%2" | |
2386 | [(set_attr "type" "idiv")]) | |
2387 | ||
2388 | (define_insn "*divsi3_no_mq" | |
2389 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2390 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2391 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
2392 | "TARGET_POWERPC && ! TARGET_POWER" | |
2393 | "divw %0,%1,%2" | |
2394 | [(set_attr "type" "idiv")]) | |
2395 | ||
1fd4e8c1 | 2396 | (define_expand "modsi3" |
85644414 RK |
2397 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
2398 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 2399 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 2400 | "" |
1fd4e8c1 RK |
2401 | " |
2402 | { | |
481c7efa | 2403 | int i; |
39b52ba2 RK |
2404 | rtx temp1; |
2405 | rtx temp2; | |
2406 | ||
2bfcf297 DB |
2407 | if (GET_CODE (operands[2]) != CONST_INT |
2408 | || INTVAL (operands[2]) < 0 | |
2409 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
39b52ba2 RK |
2410 | FAIL; |
2411 | ||
2412 | temp1 = gen_reg_rtx (SImode); | |
2413 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 2414 | |
85644414 | 2415 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 2416 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
2417 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
2418 | DONE; | |
1fd4e8c1 RK |
2419 | }") |
2420 | ||
2421 | (define_insn "" | |
cd2b37d9 RK |
2422 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2423 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
2424 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
2425 | "" | |
ca7f5001 | 2426 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 2427 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
2428 | |
2429 | (define_insn "" | |
9ebbca7d GK |
2430 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2431 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2432 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2433 | (const_int 0))) |
9ebbca7d | 2434 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 2435 | "" |
9ebbca7d GK |
2436 | "@ |
2437 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
2438 | #" | |
b19003d8 | 2439 | [(set_attr "type" "compare") |
9ebbca7d GK |
2440 | (set_attr "length" "8,12")]) |
2441 | ||
2442 | (define_split | |
2443 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2444 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2445 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2446 | (const_int 0))) |
2447 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 2448 | "reload_completed" |
9ebbca7d GK |
2449 | [(set (match_dup 3) |
2450 | (div:SI (match_dup 1) (match_dup 2))) | |
2451 | (set (match_dup 0) | |
2452 | (compare:CC (match_dup 3) | |
2453 | (const_int 0)))] | |
2454 | "") | |
1fd4e8c1 RK |
2455 | |
2456 | (define_insn "" | |
9ebbca7d GK |
2457 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2458 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2459 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2460 | (const_int 0))) |
9ebbca7d | 2461 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2462 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2463 | "" |
9ebbca7d GK |
2464 | "@ |
2465 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2466 | #" | |
b19003d8 | 2467 | [(set_attr "type" "compare") |
9ebbca7d GK |
2468 | (set_attr "length" "8,12")]) |
2469 | ||
2470 | (define_split | |
2471 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2472 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2473 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2474 | (const_int 0))) |
2475 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2476 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2477 | "reload_completed" |
9ebbca7d GK |
2478 | [(set (match_dup 0) |
2479 | (div:SI (match_dup 1) (match_dup 2))) | |
2480 | (set (match_dup 3) | |
2481 | (compare:CC (match_dup 0) | |
2482 | (const_int 0)))] | |
2483 | "") | |
1fd4e8c1 RK |
2484 | |
2485 | (define_insn "" | |
cd2b37d9 | 2486 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2487 | (udiv:SI |
996a5f59 | 2488 | (plus:DI (ashift:DI |
cd2b37d9 | 2489 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2490 | (const_int 32)) |
23a900dc | 2491 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2492 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2493 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2494 | (umod:SI |
996a5f59 | 2495 | (plus:DI (ashift:DI |
1fd4e8c1 | 2496 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2497 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2498 | (match_dup 3)))] |
ca7f5001 | 2499 | "TARGET_POWER" |
cfb557c4 RK |
2500 | "div %0,%1,%3" |
2501 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2502 | |
2503 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2504 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2505 | ;; have to worry about the branches. So make a few subroutines here. | |
2506 | ;; | |
2507 | ;; First comes the normal case. | |
2508 | (define_expand "udivmodsi4_normal" | |
2509 | [(set (match_dup 4) (const_int 0)) | |
2510 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2511 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2512 | (const_int 32)) |
2513 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2514 | (match_operand:SI 2 "" ""))) | |
2515 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2516 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2517 | (const_int 32)) |
2518 | (zero_extend:DI (match_dup 1))) | |
2519 | (match_dup 2)))])] | |
ca7f5001 | 2520 | "TARGET_POWER" |
1fd4e8c1 RK |
2521 | " |
2522 | { operands[4] = gen_reg_rtx (SImode); }") | |
2523 | ||
2524 | ;; This handles the branches. | |
2525 | (define_expand "udivmodsi4_tests" | |
2526 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2527 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2528 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2529 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2530 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2531 | (set (match_dup 0) (const_int 1)) | |
2532 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2533 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2534 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2535 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2536 | "TARGET_POWER" |
1fd4e8c1 RK |
2537 | " |
2538 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2539 | operands[6] = gen_reg_rtx (CCmode); | |
2540 | }") | |
2541 | ||
2542 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2543 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2544 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2545 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2546 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2547 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2548 | "" |
1fd4e8c1 RK |
2549 | " |
2550 | { | |
2551 | rtx label = 0; | |
2552 | ||
8ffd9c51 | 2553 | if (! TARGET_POWER) |
c4d38ccb MM |
2554 | { |
2555 | if (! TARGET_POWERPC) | |
2556 | { | |
39403d82 DE |
2557 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2558 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2559 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2560 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2561 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2562 | DONE; |
2563 | } | |
2564 | else | |
2565 | FAIL; | |
2566 | } | |
0081a354 | 2567 | |
1fd4e8c1 RK |
2568 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2569 | { | |
2570 | operands[2] = force_reg (SImode, operands[2]); | |
2571 | label = gen_label_rtx (); | |
2572 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2573 | operands[3], label)); | |
2574 | } | |
2575 | else | |
2576 | operands[2] = force_reg (SImode, operands[2]); | |
2577 | ||
2578 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2579 | operands[3])); | |
2580 | if (label) | |
2581 | emit_label (label); | |
2582 | ||
2583 | DONE; | |
2584 | }") | |
0081a354 | 2585 | |
fada905b MM |
2586 | ;; AIX architecture-independent common-mode multiply (DImode), |
2587 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2588 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2589 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2590 | ;; assumed unused if generating common-mode, so ignore. | |
2591 | (define_insn "mulh_call" | |
2592 | [(set (reg:SI 3) | |
2593 | (truncate:SI | |
2594 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2595 | (sign_extend:DI (reg:SI 4))) | |
2596 | (const_int 32)))) | |
cf27b467 | 2597 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2598 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2599 | "bla __mulh" |
2600 | [(set_attr "type" "imul")]) | |
fada905b MM |
2601 | |
2602 | (define_insn "mull_call" | |
2603 | [(set (reg:DI 3) | |
2604 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2605 | (sign_extend:DI (reg:SI 4)))) | |
2606 | (clobber (match_scratch:SI 0 "=l")) | |
2607 | (clobber (reg:SI 0))] | |
2608 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2609 | "bla __mull" |
2610 | [(set_attr "type" "imul")]) | |
fada905b MM |
2611 | |
2612 | (define_insn "divss_call" | |
2613 | [(set (reg:SI 3) | |
2614 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2615 | (set (reg:SI 4) | |
2616 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2617 | (clobber (match_scratch:SI 0 "=l")) | |
2618 | (clobber (reg:SI 0))] | |
2619 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2620 | "bla __divss" |
2621 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2622 | |
2623 | (define_insn "divus_call" | |
8ffd9c51 RK |
2624 | [(set (reg:SI 3) |
2625 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2626 | (set (reg:SI 4) | |
2627 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2628 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2629 | (clobber (reg:SI 0)) |
2630 | (clobber (match_scratch:CC 1 "=x")) | |
2631 | (clobber (reg:CC 69))] | |
2632 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2633 | "bla __divus" |
2634 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2635 | |
2636 | (define_insn "quoss_call" | |
2637 | [(set (reg:SI 3) | |
2638 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2639 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2640 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2641 | "bla __quoss" |
2642 | [(set_attr "type" "idiv")]) | |
0081a354 | 2643 | |
fada905b MM |
2644 | (define_insn "quous_call" |
2645 | [(set (reg:SI 3) | |
2646 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2647 | (clobber (match_scratch:SI 0 "=l")) | |
2648 | (clobber (reg:SI 0)) | |
2649 | (clobber (match_scratch:CC 1 "=x")) | |
2650 | (clobber (reg:CC 69))] | |
2651 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2652 | "bla __quous" |
2653 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2654 | \f |
bb21487f | 2655 | ;; Logical instructions |
dfbdccdb GK |
2656 | ;; The logical instructions are mostly combined by using match_operator, |
2657 | ;; but the plain AND insns are somewhat different because there is no | |
2658 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2659 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2660 | ||
29ae5b89 JL |
2661 | (define_insn "andsi3" |
2662 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2663 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2664 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2665 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2666 | "" |
2667 | "@ | |
2668 | and %0,%1,%2 | |
ca7f5001 RK |
2669 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2670 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2671 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2672 | |
2673 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
2674 | ;; the test again -- this avoids a mcrf which on the higher end | |
2675 | ;; machines causes an execution serialization | |
1fd4e8c1 | 2676 | |
7cd5235b | 2677 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2678 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2679 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2680 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2681 | (const_int 0))) |
52d3af72 DE |
2682 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2683 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2684 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2685 | "@ |
2686 | and. %3,%1,%2 | |
ca7f5001 RK |
2687 | {andil.|andi.} %3,%1,%b2 |
2688 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2689 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2690 | # | |
2691 | # | |
2692 | # | |
2693 | #" | |
2694 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2695 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2696 | |
52d3af72 DE |
2697 | (define_split |
2698 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2699 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2700 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2701 | (const_int 0))) |
52d3af72 DE |
2702 | (clobber (match_scratch:SI 3 "")) |
2703 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2704 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2705 | [(parallel [(set (match_dup 3) |
2706 | (and:SI (match_dup 1) | |
2707 | (match_dup 2))) | |
2708 | (clobber (match_dup 4))]) | |
2709 | (set (match_dup 0) | |
2710 | (compare:CC (match_dup 3) | |
2711 | (const_int 0)))] | |
2712 | "") | |
2713 | ||
2714 | (define_insn "*andsi3_internal3" | |
2715 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2716 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2717 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2718 | (const_int 0))) |
2719 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2720 | (and:SI (match_dup 1) | |
2721 | (match_dup 2))) | |
2722 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2723 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2724 | "@ |
2725 | and. %0,%1,%2 | |
ca7f5001 RK |
2726 | {andil.|andi.} %0,%1,%b2 |
2727 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2728 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2729 | # | |
2730 | # | |
2731 | # | |
2732 | #" | |
2733 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2734 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2735 | ||
2736 | (define_split | |
2737 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2738 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2739 | (match_operand:SI 2 "and_operand" "")) | |
2740 | (const_int 0))) | |
2741 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2742 | (and:SI (match_dup 1) | |
2743 | (match_dup 2))) | |
2744 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2745 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2746 | [(parallel [(set (match_dup 0) |
2747 | (and:SI (match_dup 1) | |
2748 | (match_dup 2))) | |
2749 | (clobber (match_dup 4))]) | |
2750 | (set (match_dup 3) | |
2751 | (compare:CC (match_dup 0) | |
2752 | (const_int 0)))] | |
2753 | "") | |
1fd4e8c1 | 2754 | |
7cd5235b | 2755 | (define_expand "iorsi3" |
cd2b37d9 | 2756 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2757 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2758 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2759 | "" |
f357808b RK |
2760 | " |
2761 | { | |
7cd5235b | 2762 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2763 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2764 | { |
2765 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2766 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2767 | ? operands[0] : gen_reg_rtx (SImode)); |
2768 | ||
a260abc9 DE |
2769 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2770 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2771 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2772 | DONE; |
2773 | } | |
f357808b RK |
2774 | }") |
2775 | ||
7cd5235b | 2776 | (define_expand "xorsi3" |
cd2b37d9 | 2777 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2778 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2779 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2780 | "" |
7cd5235b | 2781 | " |
1fd4e8c1 | 2782 | { |
7cd5235b | 2783 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2784 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2785 | { |
2786 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2787 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2788 | ? operands[0] : gen_reg_rtx (SImode)); |
2789 | ||
a260abc9 DE |
2790 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2791 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2792 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2793 | DONE; |
2794 | } | |
1fd4e8c1 RK |
2795 | }") |
2796 | ||
dfbdccdb | 2797 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2798 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2799 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2800 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2801 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2802 | "" |
2803 | "@ | |
dfbdccdb GK |
2804 | %q3 %0,%1,%2 |
2805 | {%q3il|%q3i} %0,%1,%b2 | |
2806 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2807 | |
dfbdccdb | 2808 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2809 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2810 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2811 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2812 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2813 | (const_int 0))) | |
52d3af72 | 2814 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2815 | "! TARGET_POWERPC64" |
52d3af72 | 2816 | "@ |
dfbdccdb | 2817 | %q4. %3,%1,%2 |
52d3af72 DE |
2818 | #" |
2819 | [(set_attr "type" "compare") | |
2820 | (set_attr "length" "4,8")]) | |
2821 | ||
2822 | (define_split | |
2823 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2824 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2825 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2826 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2827 | (const_int 0))) |
52d3af72 | 2828 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2829 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2830 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2831 | (set (match_dup 0) |
2832 | (compare:CC (match_dup 3) | |
2833 | (const_int 0)))] | |
2834 | "") | |
815cdc52 | 2835 | |
dfbdccdb | 2836 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2837 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2838 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2839 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2840 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2841 | (const_int 0))) | |
52d3af72 | 2842 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2843 | (match_dup 4))] |
0ad91047 | 2844 | "! TARGET_POWERPC64" |
52d3af72 | 2845 | "@ |
dfbdccdb | 2846 | %q4. %0,%1,%2 |
52d3af72 DE |
2847 | #" |
2848 | [(set_attr "type" "compare") | |
2849 | (set_attr "length" "4,8")]) | |
2850 | ||
2851 | (define_split | |
75540af0 | 2852 | [(set (match_operand:CC 3 "cc_reg_operand" "") |
dfbdccdb | 2853 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2854 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2855 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2856 | (const_int 0))) |
75540af0 | 2857 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2858 | (match_dup 4))] |
0ad91047 | 2859 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2860 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2861 | (set (match_dup 3) |
2862 | (compare:CC (match_dup 0) | |
2863 | (const_int 0)))] | |
2864 | "") | |
1fd4e8c1 | 2865 | |
dfbdccdb GK |
2866 | ;; Split an logical operation that we can't do in one insn into two insns, |
2867 | ;; each of which does one 16-bit part. This is used by combine. | |
a260abc9 DE |
2868 | |
2869 | (define_split | |
2870 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2871 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2872 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2873 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2874 | "" |
dfbdccdb GK |
2875 | [(set (match_dup 0) (match_dup 4)) |
2876 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2877 | " |
2878 | { | |
dfbdccdb GK |
2879 | rtx i; |
2880 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2881 | operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2882 | operands[1], i); | |
2883 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2884 | operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2885 | operands[0], i); | |
a260abc9 DE |
2886 | }") |
2887 | ||
dfbdccdb | 2888 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2889 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2890 | (match_operator:SI 3 "boolean_operator" |
2891 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2892 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2893 | "" |
dfbdccdb | 2894 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2895 | |
dfbdccdb | 2896 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2897 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2898 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2899 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2900 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2901 | (const_int 0))) | |
52d3af72 | 2902 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2903 | "! TARGET_POWERPC64" |
52d3af72 | 2904 | "@ |
dfbdccdb | 2905 | %q4. %3,%2,%1 |
52d3af72 DE |
2906 | #" |
2907 | [(set_attr "type" "compare") | |
2908 | (set_attr "length" "4,8")]) | |
2909 | ||
2910 | (define_split | |
2911 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2912 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2913 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2914 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2915 | (const_int 0))) |
52d3af72 | 2916 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2917 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2918 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2919 | (set (match_dup 0) |
2920 | (compare:CC (match_dup 3) | |
2921 | (const_int 0)))] | |
2922 | "") | |
1fd4e8c1 | 2923 | |
dfbdccdb | 2924 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2925 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2926 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2927 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2928 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2929 | (const_int 0))) | |
52d3af72 | 2930 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2931 | (match_dup 4))] |
0ad91047 | 2932 | "! TARGET_POWERPC64" |
52d3af72 | 2933 | "@ |
dfbdccdb | 2934 | %q4. %0,%2,%1 |
52d3af72 DE |
2935 | #" |
2936 | [(set_attr "type" "compare") | |
2937 | (set_attr "length" "4,8")]) | |
2938 | ||
2939 | (define_split | |
75540af0 | 2940 | [(set (match_operand:CC 3 "cc_reg_operand" "") |
dfbdccdb | 2941 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2942 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2943 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2944 | (const_int 0))) |
75540af0 | 2945 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2946 | (match_dup 4))] |
0ad91047 | 2947 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2948 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2949 | (set (match_dup 3) |
2950 | (compare:CC (match_dup 0) | |
2951 | (const_int 0)))] | |
2952 | "") | |
2953 | ||
dfbdccdb | 2954 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2955 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2956 | (match_operator:SI 3 "boolean_operator" |
2957 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2958 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2959 | "" |
dfbdccdb | 2960 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2961 | |
dfbdccdb | 2962 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2963 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2964 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2965 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2966 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2967 | (const_int 0))) | |
52d3af72 | 2968 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2969 | "! TARGET_POWERPC64" |
52d3af72 | 2970 | "@ |
dfbdccdb | 2971 | %q4. %3,%1,%2 |
52d3af72 DE |
2972 | #" |
2973 | [(set_attr "type" "compare") | |
2974 | (set_attr "length" "4,8")]) | |
2975 | ||
2976 | (define_split | |
2977 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2978 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2979 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2980 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2981 | (const_int 0))) |
52d3af72 | 2982 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2983 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2984 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2985 | (set (match_dup 0) |
2986 | (compare:CC (match_dup 3) | |
2987 | (const_int 0)))] | |
2988 | "") | |
1fd4e8c1 | 2989 | |
dfbdccdb | 2990 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2991 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2992 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2993 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2994 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2995 | (const_int 0))) | |
52d3af72 | 2996 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2997 | (match_dup 4))] |
0ad91047 | 2998 | "! TARGET_POWERPC64" |
52d3af72 | 2999 | "@ |
dfbdccdb | 3000 | %q4. %0,%1,%2 |
52d3af72 DE |
3001 | #" |
3002 | [(set_attr "type" "compare") | |
3003 | (set_attr "length" "4,8")]) | |
3004 | ||
3005 | (define_split | |
75540af0 | 3006 | [(set (match_operand:CC 3 "cc_reg_operand" "") |
dfbdccdb | 3007 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3008 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3009 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 3010 | (const_int 0))) |
75540af0 | 3011 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 3012 | (match_dup 4))] |
0ad91047 | 3013 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3014 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
3015 | (set (match_dup 3) |
3016 | (compare:CC (match_dup 0) | |
3017 | (const_int 0)))] | |
3018 | "") | |
1fd4e8c1 RK |
3019 | |
3020 | ;; maskir insn. We need four forms because things might be in arbitrary | |
3021 | ;; orders. Don't define forms that only set CR fields because these | |
3022 | ;; would modify an input register. | |
3023 | ||
7cd5235b | 3024 | (define_insn "*maskir_internal1" |
cd2b37d9 | 3025 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
3026 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
3027 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
3028 | (and:SI (match_dup 2) | |
cd2b37d9 | 3029 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 3030 | "TARGET_POWER" |
01def764 | 3031 | "maskir %0,%3,%2") |
1fd4e8c1 | 3032 | |
7cd5235b | 3033 | (define_insn "*maskir_internal2" |
242e8072 | 3034 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
3035 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
3036 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 3037 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 3038 | (match_dup 2))))] |
ca7f5001 | 3039 | "TARGET_POWER" |
01def764 | 3040 | "maskir %0,%3,%2") |
1fd4e8c1 | 3041 | |
7cd5235b | 3042 | (define_insn "*maskir_internal3" |
cd2b37d9 | 3043 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 3044 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 3045 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
3046 | (and:SI (not:SI (match_dup 2)) |
3047 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 3048 | "TARGET_POWER" |
01def764 | 3049 | "maskir %0,%3,%2") |
1fd4e8c1 | 3050 | |
7cd5235b | 3051 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
3052 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3053 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
3054 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
3055 | (and:SI (not:SI (match_dup 2)) | |
3056 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 3057 | "TARGET_POWER" |
01def764 | 3058 | "maskir %0,%3,%2") |
1fd4e8c1 | 3059 | |
7cd5235b | 3060 | (define_insn "*maskir_internal5" |
9ebbca7d | 3061 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3062 | (compare:CC |
9ebbca7d GK |
3063 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3064 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 3065 | (and:SI (match_dup 2) |
9ebbca7d | 3066 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 3067 | (const_int 0))) |
9ebbca7d | 3068 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3069 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3070 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 3071 | "TARGET_POWER" |
9ebbca7d GK |
3072 | "@ |
3073 | maskir. %0,%3,%2 | |
3074 | #" | |
3075 | [(set_attr "type" "compare") | |
3076 | (set_attr "length" "4,8")]) | |
3077 | ||
3078 | (define_split | |
3079 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3080 | (compare:CC | |
3081 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3082 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3083 | (and:SI (match_dup 2) | |
3084 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
3085 | (const_int 0))) | |
3086 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3087 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3088 | (and:SI (match_dup 2) (match_dup 3))))] | |
3089 | "TARGET_POWER && reload_completed" | |
3090 | [(set (match_dup 0) | |
3091 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3092 | (and:SI (match_dup 2) (match_dup 3)))) | |
3093 | (set (match_dup 4) | |
3094 | (compare:CC (match_dup 0) | |
3095 | (const_int 0)))] | |
3096 | "") | |
1fd4e8c1 | 3097 | |
7cd5235b | 3098 | (define_insn "*maskir_internal6" |
9ebbca7d | 3099 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3100 | (compare:CC |
9ebbca7d GK |
3101 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3102 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
3103 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 3104 | (match_dup 2))) |
1fd4e8c1 | 3105 | (const_int 0))) |
9ebbca7d | 3106 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3107 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3108 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 3109 | "TARGET_POWER" |
9ebbca7d GK |
3110 | "@ |
3111 | maskir. %0,%3,%2 | |
3112 | #" | |
3113 | [(set_attr "type" "compare") | |
3114 | (set_attr "length" "4,8")]) | |
3115 | ||
3116 | (define_split | |
3117 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3118 | (compare:CC | |
3119 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3120 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3121 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3122 | (match_dup 2))) | |
3123 | (const_int 0))) | |
3124 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3125 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3126 | (and:SI (match_dup 3) (match_dup 2))))] | |
3127 | "TARGET_POWER && reload_completed" | |
3128 | [(set (match_dup 0) | |
3129 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3130 | (and:SI (match_dup 3) (match_dup 2)))) | |
3131 | (set (match_dup 4) | |
3132 | (compare:CC (match_dup 0) | |
3133 | (const_int 0)))] | |
3134 | "") | |
1fd4e8c1 | 3135 | |
7cd5235b | 3136 | (define_insn "*maskir_internal7" |
9ebbca7d | 3137 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 3138 | (compare:CC |
9ebbca7d GK |
3139 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
3140 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 3141 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3142 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 3143 | (const_int 0))) |
9ebbca7d | 3144 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
3145 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
3146 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3147 | "TARGET_POWER" | |
9ebbca7d GK |
3148 | "@ |
3149 | maskir. %0,%3,%2 | |
3150 | #" | |
3151 | [(set_attr "type" "compare") | |
3152 | (set_attr "length" "4,8")]) | |
3153 | ||
3154 | (define_split | |
3155 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3156 | (compare:CC | |
3157 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
3158 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
3159 | (and:SI (not:SI (match_dup 2)) | |
3160 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3161 | (const_int 0))) | |
3162 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3163 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3164 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3165 | "TARGET_POWER && reload_completed" | |
3166 | [(set (match_dup 0) | |
3167 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3168 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3169 | (set (match_dup 4) | |
3170 | (compare:CC (match_dup 0) | |
3171 | (const_int 0)))] | |
3172 | "") | |
1fd4e8c1 | 3173 | |
7cd5235b | 3174 | (define_insn "*maskir_internal8" |
9ebbca7d | 3175 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3176 | (compare:CC |
9ebbca7d GK |
3177 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
3178 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 3179 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3180 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 3181 | (const_int 0))) |
9ebbca7d | 3182 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3183 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
3184 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 3185 | "TARGET_POWER" |
9ebbca7d GK |
3186 | "@ |
3187 | maskir. %0,%3,%2 | |
3188 | #" | |
3189 | [(set_attr "type" "compare") | |
3190 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 3191 | \f |
9ebbca7d GK |
3192 | (define_split |
3193 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3194 | (compare:CC | |
3195 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3196 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3197 | (and:SI (not:SI (match_dup 2)) | |
3198 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3199 | (const_int 0))) | |
3200 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3201 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3202 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3203 | "TARGET_POWER && reload_completed" | |
3204 | [(set (match_dup 0) | |
3205 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3206 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3207 | (set (match_dup 4) | |
3208 | (compare:CC (match_dup 0) | |
3209 | (const_int 0)))] | |
3210 | "") | |
3211 | ||
1fd4e8c1 RK |
3212 | ;; Rotate and shift insns, in all their variants. These support shifts, |
3213 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 3214 | (define_expand "insv" |
0ad91047 DE |
3215 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
3216 | (match_operand:SI 1 "const_int_operand" "") | |
3217 | (match_operand:SI 2 "const_int_operand" "")) | |
3218 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
3219 | "" |
3220 | " | |
3221 | { | |
3222 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3223 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3224 | compiler if the address of the structure is taken later. */ | |
3225 | if (GET_CODE (operands[0]) == SUBREG | |
3226 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3227 | FAIL; | |
a78e33fc DE |
3228 | |
3229 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
3230 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
3231 | else | |
3232 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
3233 | DONE; | |
034c1be0 MM |
3234 | }") |
3235 | ||
a78e33fc | 3236 | (define_insn "insvsi" |
cd2b37d9 | 3237 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
3238 | (match_operand:SI 1 "const_int_operand" "i") |
3239 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 3240 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
3241 | "" |
3242 | "* | |
3243 | { | |
3244 | int start = INTVAL (operands[2]) & 31; | |
3245 | int size = INTVAL (operands[1]) & 31; | |
3246 | ||
89e9f3a8 MM |
3247 | operands[4] = GEN_INT (32 - start - size); |
3248 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3249 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
3250 | }") |
3251 | ||
a78e33fc | 3252 | (define_insn "*insvsi_internal1" |
d56d506a RK |
3253 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3254 | (match_operand:SI 1 "const_int_operand" "i") | |
3255 | (match_operand:SI 2 "const_int_operand" "i")) | |
3256 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3257 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3258 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3259 | "* |
3260 | { | |
3261 | int shift = INTVAL (operands[4]) & 31; | |
3262 | int start = INTVAL (operands[2]) & 31; | |
3263 | int size = INTVAL (operands[1]) & 31; | |
3264 | ||
89e9f3a8 MM |
3265 | operands[4] = GEN_INT (shift - start - size); |
3266 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3267 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3268 | }") |
3269 | ||
a78e33fc | 3270 | (define_insn "*insvsi_internal2" |
d56d506a RK |
3271 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3272 | (match_operand:SI 1 "const_int_operand" "i") | |
3273 | (match_operand:SI 2 "const_int_operand" "i")) | |
3274 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3275 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3276 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3277 | "* |
3278 | { | |
3279 | int shift = INTVAL (operands[4]) & 31; | |
3280 | int start = INTVAL (operands[2]) & 31; | |
3281 | int size = INTVAL (operands[1]) & 31; | |
3282 | ||
89e9f3a8 MM |
3283 | operands[4] = GEN_INT (32 - shift - start - size); |
3284 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3285 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3286 | }") |
3287 | ||
a78e33fc | 3288 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3289 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3290 | (match_operand:SI 1 "const_int_operand" "i") | |
3291 | (match_operand:SI 2 "const_int_operand" "i")) | |
3292 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3293 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3294 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3295 | "* |
3296 | { | |
3297 | int shift = INTVAL (operands[4]) & 31; | |
3298 | int start = INTVAL (operands[2]) & 31; | |
3299 | int size = INTVAL (operands[1]) & 31; | |
3300 | ||
89e9f3a8 MM |
3301 | operands[4] = GEN_INT (32 - shift - start - size); |
3302 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3303 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3304 | }") |
3305 | ||
a78e33fc | 3306 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3307 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3308 | (match_operand:SI 1 "const_int_operand" "i") | |
3309 | (match_operand:SI 2 "const_int_operand" "i")) | |
3310 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3311 | (match_operand:SI 4 "const_int_operand" "i") | |
3312 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3313 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3314 | "* | |
3315 | { | |
3316 | int extract_start = INTVAL (operands[5]) & 31; | |
3317 | int extract_size = INTVAL (operands[4]) & 31; | |
3318 | int insert_start = INTVAL (operands[2]) & 31; | |
3319 | int insert_size = INTVAL (operands[1]) & 31; | |
3320 | ||
3321 | /* Align extract field with insert field */ | |
3a598fbe | 3322 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3323 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3324 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
3325 | }") |
3326 | ||
a78e33fc | 3327 | (define_insn "insvdi" |
685f3906 | 3328 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3329 | (match_operand:SI 1 "const_int_operand" "i") |
3330 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3331 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3332 | "TARGET_POWERPC64" | |
3333 | "* | |
3334 | { | |
3335 | int start = INTVAL (operands[2]) & 63; | |
3336 | int size = INTVAL (operands[1]) & 63; | |
3337 | ||
a78e33fc DE |
3338 | operands[1] = GEN_INT (64 - start - size); |
3339 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3340 | }") |
3341 | ||
034c1be0 | 3342 | (define_expand "extzv" |
0ad91047 DE |
3343 | [(set (match_operand 0 "gpc_reg_operand" "") |
3344 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3345 | (match_operand:SI 2 "const_int_operand" "") | |
3346 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3347 | "" |
3348 | " | |
3349 | { | |
3350 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3351 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3352 | compiler if the address of the structure is taken later. */ | |
3353 | if (GET_CODE (operands[0]) == SUBREG | |
3354 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3355 | FAIL; | |
a78e33fc DE |
3356 | |
3357 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3358 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3359 | else | |
3360 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3361 | DONE; | |
034c1be0 MM |
3362 | }") |
3363 | ||
a78e33fc | 3364 | (define_insn "extzvsi" |
cd2b37d9 RK |
3365 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3366 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3367 | (match_operand:SI 2 "const_int_operand" "i") |
3368 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3369 | "" | |
3370 | "* | |
3371 | { | |
3372 | int start = INTVAL (operands[3]) & 31; | |
3373 | int size = INTVAL (operands[2]) & 31; | |
3374 | ||
3375 | if (start + size >= 32) | |
3376 | operands[3] = const0_rtx; | |
3377 | else | |
89e9f3a8 | 3378 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3379 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3380 | }") |
3381 | ||
a78e33fc | 3382 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3383 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3384 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3385 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3386 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3387 | (const_int 0))) |
9ebbca7d | 3388 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3389 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3390 | "* |
3391 | { | |
3392 | int start = INTVAL (operands[3]) & 31; | |
3393 | int size = INTVAL (operands[2]) & 31; | |
3394 | ||
9ebbca7d GK |
3395 | /* Force split for non-cc0 compare. */ |
3396 | if (which_alternative == 1) | |
3397 | return \"#\"; | |
3398 | ||
a7a975e1 RK |
3399 | /* If the bitfield being tested fits in the upper or lower half of a |
3400 | word, it is possible to use andiu. or andil. to test it. This is | |
3401 | useful because the condition register set-use delay is smaller for | |
3402 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3403 | position is 0 because the LT and GT bits may be set wrong. */ | |
3404 | ||
3405 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3406 | { |
3a598fbe | 3407 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3408 | - (1 << (16 - (start & 15) - size)))); |
3409 | if (start < 16) | |
ca7f5001 | 3410 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3411 | else |
ca7f5001 | 3412 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3413 | } |
7e69e155 | 3414 | |
1fd4e8c1 RK |
3415 | if (start + size >= 32) |
3416 | operands[3] = const0_rtx; | |
3417 | else | |
89e9f3a8 | 3418 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3419 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3420 | }" |
9ebbca7d GK |
3421 | [(set_attr "type" "compare") |
3422 | (set_attr "length" "4,8")]) | |
3423 | ||
3424 | (define_split | |
3425 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3426 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3427 | (match_operand:SI 2 "const_int_operand" "") | |
3428 | (match_operand:SI 3 "const_int_operand" "")) | |
3429 | (const_int 0))) | |
3430 | (clobber (match_scratch:SI 4 ""))] | |
3431 | "! TARGET_POWERPC64 && reload_completed" | |
3432 | [(set (match_dup 4) | |
3433 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3434 | (match_dup 3))) | |
3435 | (set (match_dup 0) | |
3436 | (compare:CC (match_dup 4) | |
3437 | (const_int 0)))] | |
3438 | "") | |
1fd4e8c1 | 3439 | |
a78e33fc | 3440 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3441 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3442 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3443 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3444 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3445 | (const_int 0))) |
9ebbca7d | 3446 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3447 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
0ad91047 | 3448 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3449 | "* |
3450 | { | |
3451 | int start = INTVAL (operands[3]) & 31; | |
3452 | int size = INTVAL (operands[2]) & 31; | |
3453 | ||
9ebbca7d GK |
3454 | /* Force split for non-cc0 compare. */ |
3455 | if (which_alternative == 1) | |
3456 | return \"#\"; | |
3457 | ||
a7a975e1 | 3458 | if (start >= 16 && start + size == 32) |
df031c43 | 3459 | { |
89e9f3a8 | 3460 | operands[3] = GEN_INT ((1 << (32 - start)) - 1); |
ca7f5001 | 3461 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 | 3462 | } |
7e69e155 | 3463 | |
1fd4e8c1 RK |
3464 | if (start + size >= 32) |
3465 | operands[3] = const0_rtx; | |
3466 | else | |
89e9f3a8 | 3467 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3468 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3469 | }" |
9ebbca7d GK |
3470 | [(set_attr "type" "delayed_compare") |
3471 | (set_attr "length" "4,8")]) | |
3472 | ||
3473 | (define_split | |
3474 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3475 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3476 | (match_operand:SI 2 "const_int_operand" "") | |
3477 | (match_operand:SI 3 "const_int_operand" "")) | |
3478 | (const_int 0))) | |
3479 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3480 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
3481 | "! TARGET_POWERPC64 && reload_completed" | |
3482 | [(set (match_dup 0) | |
3483 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3484 | (set (match_dup 4) | |
3485 | (compare:CC (match_dup 0) | |
3486 | (const_int 0)))] | |
3487 | "") | |
1fd4e8c1 | 3488 | |
a78e33fc | 3489 | (define_insn "extzvdi" |
685f3906 DE |
3490 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3491 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3492 | (match_operand:SI 2 "const_int_operand" "i") |
3493 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3494 | "TARGET_POWERPC64" |
3495 | "* | |
3496 | { | |
3497 | int start = INTVAL (operands[3]) & 63; | |
3498 | int size = INTVAL (operands[2]) & 63; | |
3499 | ||
3500 | if (start + size >= 64) | |
3501 | operands[3] = const0_rtx; | |
3502 | else | |
89e9f3a8 MM |
3503 | operands[3] = GEN_INT (start + size); |
3504 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3505 | return \"rldicl %0,%1,%3,%2\"; |
3506 | }") | |
3507 | ||
a78e33fc | 3508 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3509 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3510 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3511 | (match_operand:SI 2 "const_int_operand" "i") |
3512 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3513 | (const_int 0))) |
29ae5b89 | 3514 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
3515 | "TARGET_POWERPC64" |
3516 | "* | |
3517 | { | |
3518 | int start = INTVAL (operands[3]) & 63; | |
3519 | int size = INTVAL (operands[2]) & 63; | |
3520 | ||
3521 | if (start + size >= 64) | |
3522 | operands[3] = const0_rtx; | |
3523 | else | |
89e9f3a8 MM |
3524 | operands[3] = GEN_INT (start + size); |
3525 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3526 | return \"rldicl. %4,%1,%3,%2\"; |
3527 | }") | |
3528 | ||
a78e33fc | 3529 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3530 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3531 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3532 | (match_operand:SI 2 "const_int_operand" "i") |
3533 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3534 | (const_int 0))) |
29ae5b89 | 3535 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
3536 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
3537 | "TARGET_POWERPC64" | |
3538 | "* | |
3539 | { | |
3540 | int start = INTVAL (operands[3]) & 63; | |
3541 | int size = INTVAL (operands[2]) & 63; | |
3542 | ||
3543 | if (start + size >= 64) | |
3544 | operands[3] = const0_rtx; | |
3545 | else | |
89e9f3a8 MM |
3546 | operands[3] = GEN_INT (start + size); |
3547 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3548 | return \"rldicl. %0,%1,%3,%2\"; |
3549 | }") | |
3550 | ||
1fd4e8c1 | 3551 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3552 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3553 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3554 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3555 | "" | |
ca7f5001 | 3556 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3557 | |
a260abc9 | 3558 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3559 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3560 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3561 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3562 | (const_int 0))) |
9ebbca7d | 3563 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3564 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3565 | "@ |
3566 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3567 | #" | |
3568 | [(set_attr "type" "delayed_compare") | |
3569 | (set_attr "length" "4,8")]) | |
3570 | ||
3571 | (define_split | |
3572 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3573 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3574 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3575 | (const_int 0))) | |
3576 | (clobber (match_scratch:SI 3 ""))] | |
3577 | "! TARGET_POWERPC64 && reload_completed" | |
3578 | [(set (match_dup 3) | |
3579 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3580 | (set (match_dup 0) | |
3581 | (compare:CC (match_dup 3) | |
3582 | (const_int 0)))] | |
3583 | "") | |
1fd4e8c1 | 3584 | |
a260abc9 | 3585 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3586 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3587 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3588 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3589 | (const_int 0))) |
9ebbca7d | 3590 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3591 | (rotate:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3592 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3593 | "@ |
3594 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3595 | #" | |
3596 | [(set_attr "type" "delayed_compare") | |
3597 | (set_attr "length" "4,8")]) | |
3598 | ||
3599 | (define_split | |
3600 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3601 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3602 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3603 | (const_int 0))) | |
3604 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3605 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
3606 | "! TARGET_POWERPC64 && reload_completed" | |
3607 | [(set (match_dup 0) | |
3608 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3609 | (set (match_dup 3) | |
3610 | (compare:CC (match_dup 0) | |
3611 | (const_int 0)))] | |
3612 | "") | |
1fd4e8c1 | 3613 | |
a260abc9 | 3614 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3615 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3616 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3617 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
9615f239 | 3618 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3619 | "" |
ca7f5001 | 3620 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3621 | |
a260abc9 | 3622 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3623 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3624 | (compare:CC (and:SI |
9ebbca7d GK |
3625 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3626 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3627 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3628 | (const_int 0))) |
9ebbca7d | 3629 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3630 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3631 | "@ |
3632 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3633 | #" | |
3634 | [(set_attr "type" "delayed_compare") | |
3635 | (set_attr "length" "4,8")]) | |
3636 | ||
3637 | (define_split | |
3638 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3639 | (compare:CC (and:SI | |
3640 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3641 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3642 | (match_operand:SI 3 "mask_operand" "")) | |
3643 | (const_int 0))) | |
3644 | (clobber (match_scratch:SI 4 ""))] | |
3645 | "! TARGET_POWERPC64 && reload_completed" | |
3646 | [(set (match_dup 4) | |
3647 | (and:SI (rotate:SI (match_dup 1) | |
3648 | (match_dup 2)) | |
3649 | (match_dup 3))) | |
3650 | (set (match_dup 0) | |
3651 | (compare:CC (match_dup 4) | |
3652 | (const_int 0)))] | |
3653 | "") | |
1fd4e8c1 | 3654 | |
a260abc9 | 3655 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3656 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3657 | (compare:CC (and:SI |
9ebbca7d GK |
3658 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3659 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3660 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3661 | (const_int 0))) |
9ebbca7d | 3662 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3663 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3664 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3665 | "@ |
3666 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3667 | #" | |
3668 | [(set_attr "type" "delayed_compare") | |
3669 | (set_attr "length" "4,8")]) | |
3670 | ||
3671 | (define_split | |
3672 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3673 | (compare:CC (and:SI | |
3674 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3675 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3676 | (match_operand:SI 3 "mask_operand" "")) | |
3677 | (const_int 0))) | |
3678 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3679 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
3680 | "! TARGET_POWERPC64 && reload_completed" | |
3681 | [(set (match_dup 0) | |
3682 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3683 | (set (match_dup 4) | |
3684 | (compare:CC (match_dup 0) | |
3685 | (const_int 0)))] | |
3686 | "") | |
1fd4e8c1 | 3687 | |
a260abc9 | 3688 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3689 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3690 | (zero_extend:SI |
3691 | (subreg:QI | |
cd2b37d9 | 3692 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3693 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3694 | "" | |
ca7f5001 | 3695 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3696 | |
a260abc9 | 3697 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3698 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3699 | (compare:CC (zero_extend:SI |
3700 | (subreg:QI | |
9ebbca7d GK |
3701 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3702 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3703 | (const_int 0))) |
9ebbca7d | 3704 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3705 | "" |
9ebbca7d GK |
3706 | "@ |
3707 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3708 | #" | |
3709 | [(set_attr "type" "delayed_compare") | |
3710 | (set_attr "length" "4,8")]) | |
3711 | ||
3712 | (define_split | |
3713 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3714 | (compare:CC (zero_extend:SI | |
3715 | (subreg:QI | |
3716 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3717 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3718 | (const_int 0))) | |
3719 | (clobber (match_scratch:SI 3 ""))] | |
3720 | "reload_completed" | |
3721 | [(set (match_dup 3) | |
3722 | (zero_extend:SI (subreg:QI | |
3723 | (rotate:SI (match_dup 1) | |
3724 | (match_dup 2)) 0))) | |
3725 | (set (match_dup 0) | |
3726 | (compare:CC (match_dup 3) | |
3727 | (const_int 0)))] | |
3728 | "") | |
1fd4e8c1 | 3729 | |
a260abc9 | 3730 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3731 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3732 | (compare:CC (zero_extend:SI |
3733 | (subreg:QI | |
9ebbca7d GK |
3734 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3735 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3736 | (const_int 0))) |
9ebbca7d | 3737 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3738 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3739 | "" | |
9ebbca7d GK |
3740 | "@ |
3741 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3742 | #" | |
3743 | [(set_attr "type" "delayed_compare") | |
3744 | (set_attr "length" "4,8")]) | |
3745 | ||
3746 | (define_split | |
3747 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3748 | (compare:CC (zero_extend:SI | |
3749 | (subreg:QI | |
3750 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3751 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3752 | (const_int 0))) | |
3753 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3754 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3755 | "reload_completed" | |
3756 | [(set (match_dup 0) | |
3757 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3758 | (set (match_dup 3) | |
3759 | (compare:CC (match_dup 0) | |
3760 | (const_int 0)))] | |
3761 | "") | |
1fd4e8c1 | 3762 | |
a260abc9 | 3763 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3764 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3765 | (zero_extend:SI |
3766 | (subreg:HI | |
cd2b37d9 | 3767 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3768 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3769 | "" | |
ca7f5001 | 3770 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3771 | |
a260abc9 | 3772 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3773 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3774 | (compare:CC (zero_extend:SI |
3775 | (subreg:HI | |
9ebbca7d GK |
3776 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3777 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3778 | (const_int 0))) |
9ebbca7d | 3779 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3780 | "" |
9ebbca7d GK |
3781 | "@ |
3782 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3783 | #" | |
3784 | [(set_attr "type" "delayed_compare") | |
3785 | (set_attr "length" "4,8")]) | |
3786 | ||
3787 | (define_split | |
3788 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3789 | (compare:CC (zero_extend:SI | |
3790 | (subreg:HI | |
3791 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3792 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3793 | (const_int 0))) | |
3794 | (clobber (match_scratch:SI 3 ""))] | |
3795 | "reload_completed" | |
3796 | [(set (match_dup 3) | |
3797 | (zero_extend:SI (subreg:HI | |
3798 | (rotate:SI (match_dup 1) | |
3799 | (match_dup 2)) 0))) | |
3800 | (set (match_dup 0) | |
3801 | (compare:CC (match_dup 3) | |
3802 | (const_int 0)))] | |
3803 | "") | |
1fd4e8c1 | 3804 | |
a260abc9 | 3805 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3806 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3807 | (compare:CC (zero_extend:SI |
3808 | (subreg:HI | |
9ebbca7d GK |
3809 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3810 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3811 | (const_int 0))) |
9ebbca7d | 3812 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3813 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3814 | "" | |
9ebbca7d GK |
3815 | "@ |
3816 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3817 | #" | |
3818 | [(set_attr "type" "delayed_compare") | |
3819 | (set_attr "length" "4,8")]) | |
3820 | ||
3821 | (define_split | |
3822 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3823 | (compare:CC (zero_extend:SI | |
3824 | (subreg:HI | |
3825 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3826 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3827 | (const_int 0))) | |
3828 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3829 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3830 | "reload_completed" | |
3831 | [(set (match_dup 0) | |
3832 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3833 | (set (match_dup 3) | |
3834 | (compare:CC (match_dup 0) | |
3835 | (const_int 0)))] | |
3836 | "") | |
1fd4e8c1 RK |
3837 | |
3838 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3839 | ;; SHIFT_COUNT_TRUNCATED. | |
3840 | ||
ca7f5001 RK |
3841 | (define_expand "ashlsi3" |
3842 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3843 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3844 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3845 | "" | |
3846 | " | |
3847 | { | |
3848 | if (TARGET_POWER) | |
3849 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3850 | else | |
25c341fa | 3851 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3852 | DONE; |
3853 | }") | |
3854 | ||
3855 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3856 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3857 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3858 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3859 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3860 | "TARGET_POWER" |
1fd4e8c1 RK |
3861 | "@ |
3862 | sle %0,%1,%2 | |
9ebbca7d | 3863 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3864 | |
25c341fa | 3865 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3866 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3867 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3868 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3869 | "! TARGET_POWER" |
9ebbca7d | 3870 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3871 | |
3872 | (define_insn "" | |
9ebbca7d GK |
3873 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3874 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3875 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3876 | (const_int 0))) |
9ebbca7d GK |
3877 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3878 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3879 | "TARGET_POWER" |
1fd4e8c1 RK |
3880 | "@ |
3881 | sle. %3,%1,%2 | |
9ebbca7d GK |
3882 | {sli.|slwi.} %3,%1,%h2 |
3883 | # | |
3884 | #" | |
3885 | [(set_attr "type" "delayed_compare") | |
3886 | (set_attr "length" "4,4,8,8")]) | |
3887 | ||
3888 | (define_split | |
3889 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3890 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3891 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3892 | (const_int 0))) | |
3893 | (clobber (match_scratch:SI 3 "")) | |
3894 | (clobber (match_scratch:SI 4 ""))] | |
3895 | "TARGET_POWER && reload_completed" | |
3896 | [(parallel [(set (match_dup 3) | |
3897 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3898 | (clobber (match_dup 4))]) | |
3899 | (set (match_dup 0) | |
3900 | (compare:CC (match_dup 3) | |
3901 | (const_int 0)))] | |
3902 | "") | |
25c341fa | 3903 | |
ca7f5001 | 3904 | (define_insn "" |
9ebbca7d GK |
3905 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3906 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3907 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3908 | (const_int 0))) |
9ebbca7d | 3909 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3910 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3911 | "@ |
3912 | {sl|slw}%I2. %3,%1,%h2 | |
3913 | #" | |
3914 | [(set_attr "type" "delayed_compare") | |
3915 | (set_attr "length" "4,8")]) | |
3916 | ||
3917 | (define_split | |
3918 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3919 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3920 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3921 | (const_int 0))) | |
3922 | (clobber (match_scratch:SI 3 ""))] | |
3923 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3924 | [(set (match_dup 3) | |
3925 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3926 | (set (match_dup 0) | |
3927 | (compare:CC (match_dup 3) | |
3928 | (const_int 0)))] | |
3929 | "") | |
1fd4e8c1 RK |
3930 | |
3931 | (define_insn "" | |
9ebbca7d GK |
3932 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3933 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3934 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3935 | (const_int 0))) |
9ebbca7d | 3936 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3937 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3938 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3939 | "TARGET_POWER" |
1fd4e8c1 RK |
3940 | "@ |
3941 | sle. %0,%1,%2 | |
9ebbca7d GK |
3942 | {sli.|slwi.} %0,%1,%h2 |
3943 | # | |
3944 | #" | |
3945 | [(set_attr "type" "delayed_compare") | |
3946 | (set_attr "length" "4,4,8,8")]) | |
3947 | ||
3948 | (define_split | |
3949 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3950 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3951 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3952 | (const_int 0))) | |
3953 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3954 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3955 | (clobber (match_scratch:SI 4 ""))] | |
3956 | "TARGET_POWER && reload_completed" | |
3957 | [(parallel [(set (match_dup 0) | |
3958 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3959 | (clobber (match_dup 4))]) | |
3960 | (set (match_dup 3) | |
3961 | (compare:CC (match_dup 0) | |
3962 | (const_int 0)))] | |
3963 | "") | |
25c341fa | 3964 | |
ca7f5001 | 3965 | (define_insn "" |
9ebbca7d GK |
3966 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3967 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3968 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3969 | (const_int 0))) |
9ebbca7d | 3970 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3971 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3972 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3973 | "@ |
3974 | {sl|slw}%I2. %0,%1,%h2 | |
3975 | #" | |
3976 | [(set_attr "type" "delayed_compare") | |
3977 | (set_attr "length" "4,8")]) | |
3978 | ||
3979 | (define_split | |
3980 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3981 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3982 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3983 | (const_int 0))) | |
3984 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3985 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
3986 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3987 | [(set (match_dup 0) | |
3988 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3989 | (set (match_dup 3) | |
3990 | (compare:CC (match_dup 0) | |
3991 | (const_int 0)))] | |
3992 | "") | |
1fd4e8c1 RK |
3993 | |
3994 | (define_insn "" | |
cd2b37d9 RK |
3995 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3996 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3997 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 3998 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3999 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 4000 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
4001 | |
4002 | (define_insn "" | |
9ebbca7d | 4003 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4004 | (compare:CC |
9ebbca7d GK |
4005 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4006 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4007 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4008 | (const_int 0))) |
9ebbca7d | 4009 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4010 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4011 | "@ |
4012 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
4013 | #" | |
4014 | [(set_attr "type" "delayed_compare") | |
4015 | (set_attr "length" "4,8")]) | |
4016 | ||
4017 | (define_split | |
4018 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4019 | (compare:CC | |
4020 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4021 | (match_operand:SI 2 "const_int_operand" "")) | |
4022 | (match_operand:SI 3 "mask_operand" "")) | |
4023 | (const_int 0))) | |
4024 | (clobber (match_scratch:SI 4 ""))] | |
4025 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
4026 | [(set (match_dup 4) | |
4027 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
4028 | (match_dup 3))) | |
4029 | (set (match_dup 0) | |
4030 | (compare:CC (match_dup 4) | |
4031 | (const_int 0)))] | |
4032 | "") | |
1fd4e8c1 RK |
4033 | |
4034 | (define_insn "" | |
9ebbca7d | 4035 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4036 | (compare:CC |
9ebbca7d GK |
4037 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4038 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4039 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4040 | (const_int 0))) |
9ebbca7d | 4041 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4042 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4043 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4044 | "@ |
4045 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
4046 | #" | |
4047 | [(set_attr "type" "delayed_compare") | |
4048 | (set_attr "length" "4,8")]) | |
4049 | ||
4050 | (define_split | |
4051 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4052 | (compare:CC | |
4053 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4054 | (match_operand:SI 2 "const_int_operand" "")) | |
4055 | (match_operand:SI 3 "mask_operand" "")) | |
4056 | (const_int 0))) | |
4057 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4058 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4059 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
4060 | [(set (match_dup 0) | |
4061 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4062 | (set (match_dup 4) | |
4063 | (compare:CC (match_dup 0) | |
4064 | (const_int 0)))] | |
4065 | "") | |
1fd4e8c1 | 4066 | |
ca7f5001 | 4067 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 4068 | ;; "sli x,x,0". |
ca7f5001 RK |
4069 | (define_expand "lshrsi3" |
4070 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
4071 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
4072 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
4073 | "" | |
4074 | " | |
4075 | { | |
4076 | if (TARGET_POWER) | |
4077 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
4078 | else | |
25c341fa | 4079 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4080 | DONE; |
4081 | }") | |
4082 | ||
4083 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
4084 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
4085 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
4086 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
4087 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 4088 | "TARGET_POWER" |
1fd4e8c1 RK |
4089 | "@ |
4090 | sre %0,%1,%2 | |
bdf423cb | 4091 | mr %0,%1 |
ca7f5001 RK |
4092 | {s%A2i|s%A2wi} %0,%1,%h2") |
4093 | ||
25c341fa | 4094 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
4095 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4096 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4097 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 4098 | "! TARGET_POWER" |
bdf423cb MM |
4099 | "@ |
4100 | mr %0,%1 | |
4101 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
4102 | |
4103 | (define_insn "" | |
9ebbca7d GK |
4104 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
4105 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4106 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4107 | (const_int 0))) |
9ebbca7d GK |
4108 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
4109 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 4110 | "TARGET_POWER" |
1fd4e8c1 | 4111 | "@ |
29ae5b89 JL |
4112 | sre. %3,%1,%2 |
4113 | mr. %1,%1 | |
9ebbca7d GK |
4114 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
4115 | # | |
4116 | # | |
4117 | #" | |
4118 | [(set_attr "type" "delayed_compare") | |
4119 | (set_attr "length" "4,4,4,8,8,8")]) | |
4120 | ||
4121 | (define_split | |
4122 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4123 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4124 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4125 | (const_int 0))) | |
4126 | (clobber (match_scratch:SI 3 "")) | |
4127 | (clobber (match_scratch:SI 4 ""))] | |
4128 | "TARGET_POWER && reload_completed" | |
4129 | [(parallel [(set (match_dup 3) | |
4130 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4131 | (clobber (match_dup 4))]) | |
4132 | (set (match_dup 0) | |
4133 | (compare:CC (match_dup 3) | |
4134 | (const_int 0)))] | |
4135 | "") | |
ca7f5001 RK |
4136 | |
4137 | (define_insn "" | |
9ebbca7d GK |
4138 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4139 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4140 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 4141 | (const_int 0))) |
9ebbca7d | 4142 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
0ad91047 | 4143 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
4144 | "@ |
4145 | mr. %1,%1 | |
9ebbca7d GK |
4146 | {sr|srw}%I2. %3,%1,%h2 |
4147 | # | |
4148 | #" | |
4149 | [(set_attr "type" "delayed_compare") | |
4150 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 4151 | |
9ebbca7d GK |
4152 | (define_split |
4153 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4154 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4155 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4156 | (const_int 0))) | |
4157 | (clobber (match_scratch:SI 3 ""))] | |
4158 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4159 | [(set (match_dup 3) | |
4160 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4161 | (set (match_dup 0) | |
4162 | (compare:CC (match_dup 3) | |
4163 | (const_int 0)))] | |
4164 | "") | |
4165 | ||
4166 | (define_insn "" | |
4167 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
4168 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4169 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4170 | (const_int 0))) |
9ebbca7d | 4171 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 4172 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4173 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 4174 | "TARGET_POWER" |
1fd4e8c1 | 4175 | "@ |
29ae5b89 JL |
4176 | sre. %0,%1,%2 |
4177 | mr. %0,%1 | |
9ebbca7d GK |
4178 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
4179 | # | |
4180 | # | |
4181 | #" | |
4182 | [(set_attr "type" "delayed_compare") | |
4183 | (set_attr "length" "4,4,4,8,8,8")]) | |
4184 | ||
4185 | (define_split | |
4186 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4187 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4188 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4189 | (const_int 0))) | |
4190 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4191 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4192 | (clobber (match_scratch:SI 4 ""))] | |
4193 | "TARGET_POWER && reload_completed" | |
4194 | [(parallel [(set (match_dup 0) | |
4195 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4196 | (clobber (match_dup 4))]) | |
4197 | (set (match_dup 3) | |
4198 | (compare:CC (match_dup 0) | |
4199 | (const_int 0)))] | |
4200 | "") | |
ca7f5001 RK |
4201 | |
4202 | (define_insn "" | |
9ebbca7d GK |
4203 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4204 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4205 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4206 | (const_int 0))) |
9ebbca7d | 4207 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4208 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4209 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
4210 | "@ |
4211 | mr. %0,%1 | |
9ebbca7d GK |
4212 | {sr|srw}%I2. %0,%1,%h2 |
4213 | # | |
4214 | #" | |
4215 | [(set_attr "type" "delayed_compare") | |
4216 | (set_attr "length" "4,4,8,8")]) | |
4217 | ||
4218 | (define_split | |
4219 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4220 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4221 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4222 | (const_int 0))) | |
4223 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4224 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4225 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4226 | [(set (match_dup 0) | |
4227 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4228 | (set (match_dup 3) | |
4229 | (compare:CC (match_dup 0) | |
4230 | (const_int 0)))] | |
4231 | "") | |
1fd4e8c1 RK |
4232 | |
4233 | (define_insn "" | |
cd2b37d9 RK |
4234 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4235 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4236 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 4237 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 4238 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4239 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4240 | |
4241 | (define_insn "" | |
9ebbca7d | 4242 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4243 | (compare:CC |
9ebbca7d GK |
4244 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4245 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4246 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4247 | (const_int 0))) |
9ebbca7d | 4248 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4249 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4250 | "@ |
4251 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4252 | #" | |
4253 | [(set_attr "type" "delayed_compare") | |
4254 | (set_attr "length" "4,8")]) | |
4255 | ||
4256 | (define_split | |
4257 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4258 | (compare:CC | |
4259 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4260 | (match_operand:SI 2 "const_int_operand" "")) | |
4261 | (match_operand:SI 3 "mask_operand" "")) | |
4262 | (const_int 0))) | |
4263 | (clobber (match_scratch:SI 4 ""))] | |
4264 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4265 | [(set (match_dup 4) | |
4266 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4267 | (match_dup 3))) | |
4268 | (set (match_dup 0) | |
4269 | (compare:CC (match_dup 4) | |
4270 | (const_int 0)))] | |
4271 | "") | |
1fd4e8c1 RK |
4272 | |
4273 | (define_insn "" | |
9ebbca7d | 4274 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4275 | (compare:CC |
9ebbca7d GK |
4276 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4277 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4278 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4279 | (const_int 0))) |
9ebbca7d | 4280 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4281 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4282 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4283 | "@ |
4284 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4285 | #" | |
4286 | [(set_attr "type" "delayed_compare") | |
4287 | (set_attr "length" "4,8")]) | |
4288 | ||
4289 | (define_split | |
4290 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4291 | (compare:CC | |
4292 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4293 | (match_operand:SI 2 "const_int_operand" "")) | |
4294 | (match_operand:SI 3 "mask_operand" "")) | |
4295 | (const_int 0))) | |
4296 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4297 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4298 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4299 | [(set (match_dup 0) | |
4300 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4301 | (set (match_dup 4) | |
4302 | (compare:CC (match_dup 0) | |
4303 | (const_int 0)))] | |
4304 | "") | |
1fd4e8c1 RK |
4305 | |
4306 | (define_insn "" | |
cd2b37d9 | 4307 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4308 | (zero_extend:SI |
4309 | (subreg:QI | |
cd2b37d9 | 4310 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4311 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4312 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4313 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4314 | |
4315 | (define_insn "" | |
9ebbca7d | 4316 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4317 | (compare:CC |
4318 | (zero_extend:SI | |
4319 | (subreg:QI | |
9ebbca7d GK |
4320 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4321 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4322 | (const_int 0))) |
9ebbca7d | 4323 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4324 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4325 | "@ |
4326 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4327 | #" | |
4328 | [(set_attr "type" "delayed_compare") | |
4329 | (set_attr "length" "4,8")]) | |
4330 | ||
4331 | (define_split | |
4332 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4333 | (compare:CC | |
4334 | (zero_extend:SI | |
4335 | (subreg:QI | |
4336 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4337 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4338 | (const_int 0))) | |
4339 | (clobber (match_scratch:SI 3 ""))] | |
4340 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4341 | [(set (match_dup 3) | |
4342 | (zero_extend:SI (subreg:QI | |
4343 | (lshiftrt:SI (match_dup 1) | |
4344 | (match_dup 2)) 0))) | |
4345 | (set (match_dup 0) | |
4346 | (compare:CC (match_dup 3) | |
4347 | (const_int 0)))] | |
4348 | "") | |
1fd4e8c1 RK |
4349 | |
4350 | (define_insn "" | |
9ebbca7d | 4351 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4352 | (compare:CC |
4353 | (zero_extend:SI | |
4354 | (subreg:QI | |
9ebbca7d GK |
4355 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4356 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4357 | (const_int 0))) |
9ebbca7d | 4358 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4359 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4360 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4361 | "@ |
4362 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4363 | #" | |
4364 | [(set_attr "type" "delayed_compare") | |
4365 | (set_attr "length" "4,8")]) | |
4366 | ||
4367 | (define_split | |
4368 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4369 | (compare:CC | |
4370 | (zero_extend:SI | |
4371 | (subreg:QI | |
4372 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4373 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4374 | (const_int 0))) | |
4375 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4376 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4377 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4378 | [(set (match_dup 0) | |
4379 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4380 | (set (match_dup 3) | |
4381 | (compare:CC (match_dup 0) | |
4382 | (const_int 0)))] | |
4383 | "") | |
1fd4e8c1 RK |
4384 | |
4385 | (define_insn "" | |
cd2b37d9 | 4386 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4387 | (zero_extend:SI |
4388 | (subreg:HI | |
cd2b37d9 | 4389 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4390 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4391 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4392 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4393 | |
4394 | (define_insn "" | |
9ebbca7d | 4395 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4396 | (compare:CC |
4397 | (zero_extend:SI | |
4398 | (subreg:HI | |
9ebbca7d GK |
4399 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4400 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4401 | (const_int 0))) |
9ebbca7d | 4402 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4403 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4404 | "@ |
4405 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4406 | #" | |
4407 | [(set_attr "type" "delayed_compare") | |
4408 | (set_attr "length" "4,8")]) | |
4409 | ||
4410 | (define_split | |
4411 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4412 | (compare:CC | |
4413 | (zero_extend:SI | |
4414 | (subreg:HI | |
4415 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4416 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4417 | (const_int 0))) | |
4418 | (clobber (match_scratch:SI 3 ""))] | |
4419 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4420 | [(set (match_dup 3) | |
4421 | (zero_extend:SI (subreg:HI | |
4422 | (lshiftrt:SI (match_dup 1) | |
4423 | (match_dup 2)) 0))) | |
4424 | (set (match_dup 0) | |
4425 | (compare:CC (match_dup 3) | |
4426 | (const_int 0)))] | |
4427 | "") | |
1fd4e8c1 RK |
4428 | |
4429 | (define_insn "" | |
9ebbca7d | 4430 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4431 | (compare:CC |
4432 | (zero_extend:SI | |
4433 | (subreg:HI | |
9ebbca7d GK |
4434 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4435 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4436 | (const_int 0))) |
9ebbca7d | 4437 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4438 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4439 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4440 | "@ |
4441 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4442 | #" | |
4443 | [(set_attr "type" "delayed_compare") | |
4444 | (set_attr "length" "4,8")]) | |
4445 | ||
4446 | (define_split | |
4447 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4448 | (compare:CC | |
4449 | (zero_extend:SI | |
4450 | (subreg:HI | |
4451 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4452 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4453 | (const_int 0))) | |
4454 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4455 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4456 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4457 | [(set (match_dup 0) | |
4458 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4459 | (set (match_dup 3) | |
4460 | (compare:CC (match_dup 0) | |
4461 | (const_int 0)))] | |
4462 | "") | |
1fd4e8c1 RK |
4463 | |
4464 | (define_insn "" | |
cd2b37d9 | 4465 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4466 | (const_int 1) |
cd2b37d9 RK |
4467 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4468 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4469 | (const_int 31)))] |
ca7f5001 | 4470 | "TARGET_POWER" |
1fd4e8c1 RK |
4471 | "rrib %0,%1,%2") |
4472 | ||
4473 | (define_insn "" | |
cd2b37d9 | 4474 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4475 | (const_int 1) |
cd2b37d9 RK |
4476 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4477 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4478 | (const_int 31)))] |
ca7f5001 | 4479 | "TARGET_POWER" |
1fd4e8c1 RK |
4480 | "rrib %0,%1,%2") |
4481 | ||
4482 | (define_insn "" | |
cd2b37d9 | 4483 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4484 | (const_int 1) |
cd2b37d9 RK |
4485 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4486 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4487 | (const_int 1) |
4488 | (const_int 0)))] | |
ca7f5001 | 4489 | "TARGET_POWER" |
1fd4e8c1 RK |
4490 | "rrib %0,%1,%2") |
4491 | ||
ca7f5001 RK |
4492 | (define_expand "ashrsi3" |
4493 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4494 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4495 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4496 | "" | |
4497 | " | |
4498 | { | |
4499 | if (TARGET_POWER) | |
4500 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4501 | else | |
25c341fa | 4502 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4503 | DONE; |
4504 | }") | |
4505 | ||
4506 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4507 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4508 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4509 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4510 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4511 | "TARGET_POWER" |
1fd4e8c1 RK |
4512 | "@ |
4513 | srea %0,%1,%2 | |
ca7f5001 RK |
4514 | {srai|srawi} %0,%1,%h2") |
4515 | ||
25c341fa | 4516 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4517 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4518 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4519 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4520 | "! TARGET_POWER" |
d904e9ed | 4521 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4522 | |
4523 | (define_insn "" | |
9ebbca7d GK |
4524 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4525 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4526 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4527 | (const_int 0))) |
9ebbca7d GK |
4528 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4529 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4530 | "TARGET_POWER" |
1fd4e8c1 RK |
4531 | "@ |
4532 | srea. %3,%1,%2 | |
9ebbca7d GK |
4533 | {srai.|srawi.} %3,%1,%h2 |
4534 | # | |
4535 | #" | |
4536 | [(set_attr "type" "delayed_compare") | |
4537 | (set_attr "length" "4,4,8,8")]) | |
4538 | ||
4539 | (define_split | |
4540 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4541 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4542 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4543 | (const_int 0))) | |
4544 | (clobber (match_scratch:SI 3 "")) | |
4545 | (clobber (match_scratch:SI 4 ""))] | |
4546 | "TARGET_POWER && reload_completed" | |
4547 | [(parallel [(set (match_dup 3) | |
4548 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4549 | (clobber (match_dup 4))]) | |
4550 | (set (match_dup 0) | |
4551 | (compare:CC (match_dup 3) | |
4552 | (const_int 0)))] | |
4553 | "") | |
ca7f5001 RK |
4554 | |
4555 | (define_insn "" | |
9ebbca7d GK |
4556 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4557 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4558 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4559 | (const_int 0))) |
9ebbca7d | 4560 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4561 | "! TARGET_POWER" |
9ebbca7d GK |
4562 | "@ |
4563 | {sra|sraw}%I2. %3,%1,%h2 | |
4564 | #" | |
4565 | [(set_attr "type" "delayed_compare") | |
4566 | (set_attr "length" "4,8")]) | |
4567 | ||
4568 | (define_split | |
4569 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4570 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4571 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4572 | (const_int 0))) | |
4573 | (clobber (match_scratch:SI 3 ""))] | |
4574 | "! TARGET_POWER && reload_completed" | |
4575 | [(set (match_dup 3) | |
4576 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4577 | (set (match_dup 0) | |
4578 | (compare:CC (match_dup 3) | |
4579 | (const_int 0)))] | |
4580 | "") | |
1fd4e8c1 RK |
4581 | |
4582 | (define_insn "" | |
9ebbca7d GK |
4583 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4584 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4585 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4586 | (const_int 0))) |
9ebbca7d | 4587 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4588 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4589 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4590 | "TARGET_POWER" |
1fd4e8c1 RK |
4591 | "@ |
4592 | srea. %0,%1,%2 | |
9ebbca7d GK |
4593 | {srai.|srawi.} %0,%1,%h2 |
4594 | # | |
4595 | #" | |
4596 | [(set_attr "type" "delayed_compare") | |
4597 | (set_attr "length" "4,4,8,8")]) | |
4598 | ||
4599 | (define_split | |
4600 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4601 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4602 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4603 | (const_int 0))) | |
4604 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4605 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4606 | (clobber (match_scratch:SI 4 ""))] | |
4607 | "TARGET_POWER && reload_completed" | |
4608 | [(parallel [(set (match_dup 0) | |
4609 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4610 | (clobber (match_dup 4))]) | |
4611 | (set (match_dup 3) | |
4612 | (compare:CC (match_dup 0) | |
4613 | (const_int 0)))] | |
4614 | "") | |
1fd4e8c1 | 4615 | |
ca7f5001 | 4616 | (define_insn "" |
9ebbca7d GK |
4617 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4618 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4619 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4620 | (const_int 0))) |
9ebbca7d | 4621 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4622 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4623 | "! TARGET_POWER" |
9ebbca7d GK |
4624 | "@ |
4625 | {sra|sraw}%I2. %0,%1,%h2 | |
4626 | #" | |
4627 | [(set_attr "type" "delayed_compare") | |
4628 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4629 | \f |
9ebbca7d GK |
4630 | (define_split |
4631 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4632 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4633 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4634 | (const_int 0))) | |
4635 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4636 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4637 | "! TARGET_POWER && reload_completed" | |
4638 | [(set (match_dup 0) | |
4639 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4640 | (set (match_dup 3) | |
4641 | (compare:CC (match_dup 0) | |
4642 | (const_int 0)))] | |
4643 | "") | |
4644 | ||
1fd4e8c1 RK |
4645 | ;; Floating-point insns, excluding normal data motion. |
4646 | ;; | |
ca7f5001 RK |
4647 | ;; PowerPC has a full set of single-precision floating point instructions. |
4648 | ;; | |
4649 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4650 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4651 | ;; The only conversions we will do will be when storing to memory. In that | |
4652 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4653 | ;; |
4654 | ;; Note that when we store into a single-precision memory location, we need to | |
4655 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4656 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4657 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4658 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4659 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4660 | ||
e8112008 | 4661 | (define_insn "extendsfdf2" |
cd2b37d9 | 4662 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 4663 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 4664 | "TARGET_HARD_FLOAT" |
e8112008 | 4665 | "* |
5c30aff8 | 4666 | { |
e8112008 RK |
4667 | if (REGNO (operands[0]) == REGNO (operands[1])) |
4668 | return \"\"; | |
4669 | else | |
4670 | return \"fmr %0,%1\"; | |
4671 | }" | |
4672 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4673 | |
4674 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
4675 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4676 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4677 | "TARGET_HARD_FLOAT" |
dcac138d | 4678 | "frsp %0,%1" |
1fd4e8c1 RK |
4679 | [(set_attr "type" "fp")]) |
4680 | ||
455350f4 RK |
4681 | (define_insn "aux_truncdfsf2" |
4682 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4683 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
4684 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" | |
4685 | "frsp %0,%1" | |
4686 | [(set_attr "type" "fp")]) | |
4687 | ||
1fd4e8c1 | 4688 | (define_insn "negsf2" |
cd2b37d9 RK |
4689 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4690 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4691 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4692 | "fneg %0,%1" |
4693 | [(set_attr "type" "fp")]) | |
4694 | ||
4695 | (define_insn "abssf2" | |
cd2b37d9 RK |
4696 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4697 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4698 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4699 | "fabs %0,%1" |
4700 | [(set_attr "type" "fp")]) | |
4701 | ||
4702 | (define_insn "" | |
cd2b37d9 RK |
4703 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4704 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4705 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4706 | "fnabs %0,%1" |
4707 | [(set_attr "type" "fp")]) | |
4708 | ||
ca7f5001 RK |
4709 | (define_expand "addsf3" |
4710 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4711 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4712 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4713 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4714 | "") |
4715 | ||
4716 | (define_insn "" | |
cd2b37d9 RK |
4717 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4718 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4719 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4720 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4721 | "fadds %0,%1,%2" |
ca7f5001 RK |
4722 | [(set_attr "type" "fp")]) |
4723 | ||
4724 | (define_insn "" | |
4725 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4726 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4727 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4728 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4729 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4730 | [(set_attr "type" "fp")]) |
4731 | ||
4732 | (define_expand "subsf3" | |
4733 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4734 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4735 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4736 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4737 | "") |
4738 | ||
4739 | (define_insn "" | |
4740 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4741 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4742 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4743 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4744 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4745 | [(set_attr "type" "fp")]) |
4746 | ||
ca7f5001 | 4747 | (define_insn "" |
cd2b37d9 RK |
4748 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4749 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4750 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4751 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4752 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4753 | [(set_attr "type" "fp")]) |
4754 | ||
4755 | (define_expand "mulsf3" | |
4756 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4757 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4758 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4759 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4760 | "") |
4761 | ||
4762 | (define_insn "" | |
4763 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4764 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4765 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4766 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4767 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4768 | [(set_attr "type" "fp")]) |
4769 | ||
ca7f5001 | 4770 | (define_insn "" |
cd2b37d9 RK |
4771 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4772 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4773 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4774 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4775 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4776 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4777 | |
ca7f5001 RK |
4778 | (define_expand "divsf3" |
4779 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4780 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4781 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4782 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4783 | "") |
4784 | ||
4785 | (define_insn "" | |
cd2b37d9 RK |
4786 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4787 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4788 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4789 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4790 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4791 | [(set_attr "type" "sdiv")]) |
4792 | ||
4793 | (define_insn "" | |
4794 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4795 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4796 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4797 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4798 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4799 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4800 | |
4801 | (define_insn "" | |
cd2b37d9 RK |
4802 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4803 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4804 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4805 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4806 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4807 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4808 | [(set_attr "type" "fp")]) |
4809 | ||
4810 | (define_insn "" | |
4811 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4812 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4813 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4814 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4815 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4816 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4817 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4818 | |
4819 | (define_insn "" | |
cd2b37d9 RK |
4820 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4821 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4822 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4823 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4824 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4825 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4826 | [(set_attr "type" "fp")]) |
4827 | ||
4828 | (define_insn "" | |
4829 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4830 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4831 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4832 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4833 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4834 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4835 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4836 | |
4837 | (define_insn "" | |
cd2b37d9 RK |
4838 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4839 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4840 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4841 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4842 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4843 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4844 | [(set_attr "type" "fp")]) |
4845 | ||
4846 | (define_insn "" | |
4847 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4848 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4849 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4850 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4851 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4852 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4853 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4854 | |
4855 | (define_insn "" | |
cd2b37d9 RK |
4856 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4857 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4858 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4859 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4860 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4861 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4862 | [(set_attr "type" "fp")]) |
4863 | ||
4864 | (define_insn "" | |
4865 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4866 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4867 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4868 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4869 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4870 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4871 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4872 | |
ca7f5001 RK |
4873 | (define_expand "sqrtsf2" |
4874 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4875 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 4876 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4877 | "") |
4878 | ||
4879 | (define_insn "" | |
4880 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4881 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4882 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4883 | "fsqrts %0,%1" |
4884 | [(set_attr "type" "ssqrt")]) | |
4885 | ||
4886 | (define_insn "" | |
4887 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4888 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4889 | "TARGET_POWER2 && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4890 | "fsqrt %0,%1" |
4891 | [(set_attr "type" "dsqrt")]) | |
4892 | ||
94d7001a RK |
4893 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4894 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4895 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4896 | ;; combine. |
4897 | (define_expand "maxsf3" | |
8e871c05 | 4898 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4899 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4900 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4901 | (match_dup 1) |
4902 | (match_dup 2)))] | |
50a0b056 GK |
4903 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
4904 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") | |
2f607b94 | 4905 | |
8e871c05 | 4906 | (define_expand "minsf3" |
50a0b056 GK |
4907 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4908 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4909 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4910 | (match_dup 2) | |
4911 | (match_dup 1)))] | |
d14a6d05 | 4912 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 | 4913 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4914 | |
8e871c05 RK |
4915 | (define_split |
4916 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4917 | (match_operator:SF 3 "min_max_operator" |
4918 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4919 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
d14a6d05 | 4920 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 GK |
4921 | [(const_int 0)] |
4922 | " | |
4923 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
4924 | operands[1], operands[2]); | |
4925 | DONE; | |
4926 | }") | |
2f607b94 | 4927 | |
94d7001a | 4928 | (define_expand "movsfcc" |
0ad91047 | 4929 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4930 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4931 | (match_operand:SF 2 "gpc_reg_operand" "") |
4932 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 4933 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4934 | " |
4935 | { | |
50a0b056 GK |
4936 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4937 | DONE; | |
94d7001a | 4938 | else |
50a0b056 | 4939 | FAIL; |
94d7001a | 4940 | }") |
d56d506a | 4941 | |
50a0b056 | 4942 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4943 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4944 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4945 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4946 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4947 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4948 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4949 | "fsel %0,%1,%2,%3" |
4950 | [(set_attr "type" "fp")]) | |
2f607b94 | 4951 | |
50a0b056 | 4952 | (define_insn "*fseldfsf4" |
94d7001a RK |
4953 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4954 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4955 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4956 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4957 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4958 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4959 | "fsel %0,%1,%2,%3" |
4960 | [(set_attr "type" "fp")]) | |
d56d506a | 4961 | |
1fd4e8c1 | 4962 | (define_insn "negdf2" |
cd2b37d9 RK |
4963 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4964 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4965 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4966 | "fneg %0,%1" |
4967 | [(set_attr "type" "fp")]) | |
4968 | ||
4969 | (define_insn "absdf2" | |
cd2b37d9 RK |
4970 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4971 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4972 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4973 | "fabs %0,%1" |
4974 | [(set_attr "type" "fp")]) | |
4975 | ||
4976 | (define_insn "" | |
cd2b37d9 RK |
4977 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4978 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4979 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4980 | "fnabs %0,%1" |
4981 | [(set_attr "type" "fp")]) | |
4982 | ||
4983 | (define_insn "adddf3" | |
cd2b37d9 RK |
4984 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4985 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4986 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4987 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4988 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4989 | [(set_attr "type" "fp")]) |
4990 | ||
4991 | (define_insn "subdf3" | |
cd2b37d9 RK |
4992 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4993 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4994 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4995 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4996 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4997 | [(set_attr "type" "fp")]) |
4998 | ||
4999 | (define_insn "muldf3" | |
cd2b37d9 RK |
5000 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5001 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5002 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5003 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5004 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 5005 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5006 | |
5007 | (define_insn "divdf3" | |
cd2b37d9 RK |
5008 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5009 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5010 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5011 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5012 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 5013 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
5014 | |
5015 | (define_insn "" | |
cd2b37d9 RK |
5016 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5017 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5018 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5019 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 5020 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5021 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 5022 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5023 | |
5024 | (define_insn "" | |
cd2b37d9 RK |
5025 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5026 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5027 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5028 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 5029 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5030 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 5031 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5032 | |
5033 | (define_insn "" | |
cd2b37d9 RK |
5034 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5035 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5036 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5037 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 5038 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5039 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 5040 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5041 | |
5042 | (define_insn "" | |
cd2b37d9 RK |
5043 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5044 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5045 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5046 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 5047 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5048 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5049 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5050 | |
5051 | (define_insn "sqrtdf2" | |
5052 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5053 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5054 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5055 | "fsqrt %0,%1" |
5056 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5057 | |
50a0b056 GK |
5058 | ;; The conditional move instructions allow us to perform max and min |
5059 | ;; operations even when | |
b77dfefc | 5060 | |
8e871c05 | 5061 | (define_expand "maxdf3" |
8e871c05 | 5062 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5063 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
5064 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5065 | (match_dup 1) |
5066 | (match_dup 2)))] | |
50a0b056 GK |
5067 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
5068 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") | |
b77dfefc | 5069 | |
8e871c05 | 5070 | (define_expand "mindf3" |
50a0b056 GK |
5071 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5072 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
5073 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
5074 | (match_dup 2) | |
5075 | (match_dup 1)))] | |
d14a6d05 | 5076 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 | 5077 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5078 | |
8e871c05 RK |
5079 | (define_split |
5080 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5081 | (match_operator:DF 3 "min_max_operator" |
5082 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5083 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
d14a6d05 | 5084 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 GK |
5085 | [(const_int 0)] |
5086 | " | |
5087 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
5088 | operands[1], operands[2]); | |
5089 | DONE; | |
5090 | }") | |
b77dfefc | 5091 | |
94d7001a | 5092 | (define_expand "movdfcc" |
0ad91047 | 5093 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5094 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5095 | (match_operand:DF 2 "gpc_reg_operand" "") |
5096 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 5097 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5098 | " |
5099 | { | |
50a0b056 GK |
5100 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5101 | DONE; | |
94d7001a | 5102 | else |
50a0b056 | 5103 | FAIL; |
94d7001a | 5104 | }") |
d56d506a | 5105 | |
50a0b056 | 5106 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5107 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5108 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5109 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5110 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5111 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5112 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5113 | "fsel %0,%1,%2,%3" |
5114 | [(set_attr "type" "fp")]) | |
d56d506a | 5115 | |
50a0b056 | 5116 | (define_insn "*fselsfdf4" |
94d7001a RK |
5117 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5118 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5119 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5120 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5121 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5122 | "TARGET_PPC_GFXOPT" | |
5123 | "fsel %0,%1,%2,%3" | |
5124 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5125 | \f |
5126 | ;; Conversions to and from floating-point. | |
802a0058 | 5127 | |
9ebbca7d GK |
5128 | ; For each of these conversions, there is a define_expand, a define_insn |
5129 | ; with a '#' template, and a define_split (with C code). The idea is | |
5130 | ; to allow constant folding with the template of the define_insn, | |
5131 | ; then to have the insns split later (between sched1 and final). | |
5132 | ||
1fd4e8c1 | 5133 | (define_expand "floatsidf2" |
802a0058 MM |
5134 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5135 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5136 | (use (match_dup 2)) | |
5137 | (use (match_dup 3)) | |
208c89ce | 5138 | (clobber (match_dup 4)) |
a7df97e6 | 5139 | (clobber (match_dup 5)) |
9ebbca7d | 5140 | (clobber (match_dup 6))])] |
31bfaa0b | 5141 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5142 | " |
5143 | { | |
802a0058 MM |
5144 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5145 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); | |
9ebbca7d GK |
5146 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5147 | operands[5] = gen_reg_rtx (DFmode); | |
5148 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5149 | }") |
5150 | ||
802a0058 MM |
5151 | (define_insn "*floatsidf2_internal" |
5152 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5153 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5154 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5155 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5156 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5157 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f")) | |
5158 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))] | |
31bfaa0b | 5159 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5160 | "#" |
a7df97e6 | 5161 | [(set_attr "length" "24")]) |
802a0058 MM |
5162 | |
5163 | (define_split | |
dbe3df29 | 5164 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5165 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5166 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5167 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5168 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5169 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5170 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
31bfaa0b | 5171 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5172 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5173 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5174 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5175 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5176 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5177 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5178 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5179 | " |
5180 | { | |
9ebbca7d GK |
5181 | rtx lowword, highword; |
5182 | if (GET_CODE (operands[4]) != MEM) | |
5183 | abort(); | |
5184 | highword = XEXP (operands[4], 0); | |
5185 | lowword = plus_constant (highword, 4); | |
5186 | if (! WORDS_BIG_ENDIAN) | |
5187 | { | |
5188 | rtx tmp; | |
5189 | tmp = highword; highword = lowword; lowword = tmp; | |
5190 | } | |
5191 | ||
5192 | emit_insn (gen_xorsi3 (operands[6], operands[1], | |
5193 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); | |
5194 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5195 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5196 | emit_move_insn (operands[5], operands[4]); | |
5197 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5198 | DONE; | |
208c89ce | 5199 | }") |
802a0058 MM |
5200 | |
5201 | (define_expand "floatunssidf2" | |
5202 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5203 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5204 | (use (match_dup 2)) | |
5205 | (use (match_dup 3)) | |
a7df97e6 | 5206 | (clobber (match_dup 4)) |
9ebbca7d | 5207 | (clobber (match_dup 5))])] |
31bfaa0b | 5208 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5209 | " |
5210 | { | |
802a0058 MM |
5211 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5212 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); | |
9ebbca7d GK |
5213 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5214 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5215 | }") |
5216 | ||
802a0058 MM |
5217 | (define_insn "*floatunssidf2_internal" |
5218 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5219 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5220 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5221 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5222 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5223 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))] | |
31bfaa0b | 5224 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5225 | "#" |
a7df97e6 | 5226 | [(set_attr "length" "20")]) |
802a0058 MM |
5227 | |
5228 | (define_split | |
5229 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5230 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5231 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5232 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5233 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5234 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
31bfaa0b | 5235 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5236 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5237 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5238 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5239 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5240 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5241 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5242 | " | |
802a0058 | 5243 | { |
9ebbca7d GK |
5244 | rtx lowword, highword; |
5245 | if (GET_CODE (operands[4]) != MEM) | |
5246 | abort(); | |
5247 | highword = XEXP (operands[4], 0); | |
5248 | lowword = plus_constant (highword, 4); | |
5249 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5250 | { |
9ebbca7d GK |
5251 | rtx tmp; |
5252 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5253 | } |
802a0058 | 5254 | |
9ebbca7d GK |
5255 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5256 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5257 | emit_move_insn (operands[5], operands[4]); | |
5258 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5259 | DONE; | |
5260 | }") | |
1fd4e8c1 | 5261 | |
1fd4e8c1 | 5262 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5263 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5264 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5265 | (clobber (match_dup 2)) | |
9ebbca7d | 5266 | (clobber (match_dup 3))])] |
9cb8fcaf | 5267 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5268 | " |
5269 | { | |
802a0058 | 5270 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5271 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5272 | }") |
5273 | ||
802a0058 MM |
5274 | (define_insn "*fix_truncdfsi2_internal" |
5275 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5276 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5277 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) | |
9ebbca7d | 5278 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
9cb8fcaf | 5279 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
802a0058 | 5280 | "#" |
9ebbca7d | 5281 | [(set_attr "length" "16")]) |
802a0058 MM |
5282 | |
5283 | (define_split | |
5284 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5285 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5286 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5287 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
9cb8fcaf | 5288 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
9ebbca7d | 5289 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5290 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5291 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5292 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5293 | " | |
802a0058 | 5294 | { |
9ebbca7d GK |
5295 | rtx lowword; |
5296 | if (GET_CODE (operands[3]) != MEM) | |
5297 | abort(); | |
5298 | lowword = XEXP (operands[3], 0); | |
5299 | if (WORDS_BIG_ENDIAN) | |
5300 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5301 | |
9ebbca7d GK |
5302 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5303 | emit_move_insn (operands[3], operands[2]); | |
5304 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5305 | DONE; | |
5306 | }") | |
802a0058 | 5307 | |
9ebbca7d GK |
5308 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10)) |
5309 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) | |
5310 | ; because the first makes it clear that operand 0 is not live | |
5311 | ; before the instruction. | |
5312 | (define_insn "fctiwz" | |
5313 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5314 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] | |
a260abc9 DE |
5315 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
5316 | "{fcirz|fctiwz} %0,%1" | |
5317 | [(set_attr "type" "fp")]) | |
5318 | ||
a473029f RK |
5319 | (define_insn "floatdidf2" |
5320 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5321 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5322 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5323 | "fcfid %0,%1" |
5324 | [(set_attr "type" "fp")]) | |
5325 | ||
5326 | (define_insn "fix_truncdfdi2" | |
5327 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5328 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5329 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5330 | "fctidz %0,%1" |
5331 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5332 | \f |
5333 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5334 | ;; of instructions. The & constraints are to prevent the register |
5335 | ;; allocator from allocating registers that overlap with the inputs | |
5336 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5337 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5338 | |
266eb58a | 5339 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5340 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5341 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5342 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5343 | "! TARGET_POWERPC64" |
0f645302 MM |
5344 | "* |
5345 | { | |
5346 | if (WORDS_BIG_ENDIAN) | |
5347 | return (GET_CODE (operands[2])) != CONST_INT | |
5348 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5349 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5350 | else | |
5351 | return (GET_CODE (operands[2])) != CONST_INT | |
5352 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5353 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5354 | }" | |
b19003d8 | 5355 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5356 | |
266eb58a | 5357 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5358 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5359 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5360 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5361 | "! TARGET_POWERPC64" |
5502823b RK |
5362 | "* |
5363 | { | |
0f645302 MM |
5364 | if (WORDS_BIG_ENDIAN) |
5365 | return (GET_CODE (operands[1]) != CONST_INT) | |
5366 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5367 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5368 | else | |
5369 | return (GET_CODE (operands[1]) != CONST_INT) | |
5370 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5371 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5372 | }" |
ca7f5001 RK |
5373 | [(set_attr "length" "8")]) |
5374 | ||
266eb58a | 5375 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5376 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5377 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5378 | "! TARGET_POWERPC64" |
5502823b RK |
5379 | "* |
5380 | { | |
5381 | return (WORDS_BIG_ENDIAN) | |
5382 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5383 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5384 | }" | |
ca7f5001 RK |
5385 | [(set_attr "length" "8")]) |
5386 | ||
8ffd9c51 RK |
5387 | (define_expand "mulsidi3" |
5388 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5389 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5390 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5391 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5392 | " |
5393 | { | |
5394 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5395 | { | |
39403d82 DE |
5396 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5397 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5398 | emit_insn (gen_mull_call ()); |
cf27b467 | 5399 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5400 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5401 | else |
5402 | { | |
5403 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5404 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5405 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5406 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5407 | } |
8ffd9c51 RK |
5408 | DONE; |
5409 | } | |
5410 | else if (TARGET_POWER) | |
5411 | { | |
5412 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5413 | DONE; | |
5414 | } | |
5415 | }") | |
deb9225a | 5416 | |
8ffd9c51 | 5417 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5418 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5419 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5420 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5421 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5422 | "TARGET_POWER" |
b19003d8 | 5423 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5424 | [(set_attr "type" "imul") |
5425 | (set_attr "length" "8")]) | |
deb9225a | 5426 | |
f192bf8b | 5427 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5428 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5429 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5430 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5431 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5432 | "* |
5433 | { | |
5434 | return (WORDS_BIG_ENDIAN) | |
5435 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5436 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5437 | }" | |
8ffd9c51 RK |
5438 | [(set_attr "type" "imul") |
5439 | (set_attr "length" "8")]) | |
deb9225a | 5440 | |
ebedb4dd MM |
5441 | (define_split |
5442 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5443 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5444 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5445 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5446 | [(set (match_dup 3) |
5447 | (truncate:SI | |
5448 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5449 | (sign_extend:DI (match_dup 2))) | |
5450 | (const_int 32)))) | |
5451 | (set (match_dup 4) | |
5452 | (mult:SI (match_dup 1) | |
5453 | (match_dup 2)))] | |
5454 | " | |
5455 | { | |
5456 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5457 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5458 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5459 | }") | |
5460 | ||
f192bf8b DE |
5461 | (define_expand "umulsidi3" |
5462 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5463 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5464 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5465 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5466 | " | |
5467 | { | |
5468 | if (TARGET_POWER) | |
5469 | { | |
5470 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5471 | DONE; | |
5472 | } | |
5473 | }") | |
5474 | ||
5475 | (define_insn "umulsidi3_mq" | |
5476 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5477 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5478 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5479 | (clobber (match_scratch:SI 3 "=q"))] | |
5480 | "TARGET_POWERPC && TARGET_POWER" | |
5481 | "* | |
5482 | { | |
5483 | return (WORDS_BIG_ENDIAN) | |
5484 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5485 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5486 | }" | |
5487 | [(set_attr "type" "imul") | |
5488 | (set_attr "length" "8")]) | |
5489 | ||
5490 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5491 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5492 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5493 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5494 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5495 | "* |
5496 | { | |
5497 | return (WORDS_BIG_ENDIAN) | |
5498 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5499 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5500 | }" | |
5501 | [(set_attr "type" "imul") | |
5502 | (set_attr "length" "8")]) | |
5503 | ||
ebedb4dd MM |
5504 | (define_split |
5505 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5506 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5507 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5508 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5509 | [(set (match_dup 3) |
5510 | (truncate:SI | |
5511 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5512 | (zero_extend:DI (match_dup 2))) | |
5513 | (const_int 32)))) | |
5514 | (set (match_dup 4) | |
5515 | (mult:SI (match_dup 1) | |
5516 | (match_dup 2)))] | |
5517 | " | |
5518 | { | |
5519 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5520 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5521 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5522 | }") | |
5523 | ||
8ffd9c51 RK |
5524 | (define_expand "smulsi3_highpart" |
5525 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5526 | (truncate:SI | |
5527 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5528 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5529 | (sign_extend:DI | |
5530 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5531 | (const_int 32))))] | |
5532 | "" | |
5533 | " | |
5534 | { | |
5535 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5536 | { | |
39403d82 DE |
5537 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5538 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5539 | emit_insn (gen_mulh_call ()); |
39403d82 | 5540 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5541 | DONE; |
5542 | } | |
5543 | else if (TARGET_POWER) | |
5544 | { | |
5545 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5546 | DONE; | |
5547 | } | |
5548 | }") | |
deb9225a | 5549 | |
8ffd9c51 RK |
5550 | (define_insn "smulsi3_highpart_mq" |
5551 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5552 | (truncate:SI | |
fada905b MM |
5553 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5554 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5555 | (sign_extend:DI | |
5556 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5557 | (const_int 32)))) |
5558 | (clobber (match_scratch:SI 3 "=q"))] | |
5559 | "TARGET_POWER" | |
5560 | "mul %0,%1,%2" | |
5561 | [(set_attr "type" "imul")]) | |
deb9225a | 5562 | |
f192bf8b | 5563 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5564 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5565 | (truncate:SI | |
fada905b MM |
5566 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5567 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5568 | (sign_extend:DI | |
5569 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5570 | (const_int 32))))] |
f192bf8b | 5571 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5572 | "mulhw %0,%1,%2" |
5573 | [(set_attr "type" "imul")]) | |
deb9225a | 5574 | |
f192bf8b DE |
5575 | (define_expand "umulsi3_highpart" |
5576 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5577 | (truncate:SI | |
5578 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5579 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5580 | (zero_extend:DI | |
5581 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5582 | (const_int 32))))] | |
5583 | "TARGET_POWERPC" | |
5584 | " | |
5585 | { | |
5586 | if (TARGET_POWER) | |
5587 | { | |
5588 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5589 | DONE; | |
5590 | } | |
5591 | }") | |
5592 | ||
5593 | (define_insn "umulsi3_highpart_mq" | |
5594 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5595 | (truncate:SI | |
5596 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5597 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5598 | (zero_extend:DI | |
5599 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5600 | (const_int 32)))) | |
5601 | (clobber (match_scratch:SI 3 "=q"))] | |
5602 | "TARGET_POWERPC && TARGET_POWER" | |
5603 | "mulhwu %0,%1,%2" | |
5604 | [(set_attr "type" "imul")]) | |
5605 | ||
5606 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5607 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5608 | (truncate:SI | |
5609 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5610 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5611 | (zero_extend:DI | |
5612 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5613 | (const_int 32))))] | |
f192bf8b | 5614 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5615 | "mulhwu %0,%1,%2" |
5616 | [(set_attr "type" "imul")]) | |
5617 | ||
5618 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5619 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5620 | ;; why we have the strange constraints below. | |
5621 | (define_insn "ashldi3_power" | |
5622 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5623 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5624 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5625 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5626 | "TARGET_POWER" | |
5627 | "@ | |
5628 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5629 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5630 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5631 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5632 | [(set_attr "length" "8")]) | |
5633 | ||
5634 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5635 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5636 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5637 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5638 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5639 | "TARGET_POWER" | |
5640 | "@ | |
47ad8c61 | 5641 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5642 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5643 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5644 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5645 | [(set_attr "length" "8")]) | |
5646 | ||
5647 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5648 | ;; just handle shifts by constants. | |
5649 | (define_insn "ashrdi3_power" | |
7093ddee | 5650 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5651 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5652 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5653 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5654 | "TARGET_POWER" | |
5655 | "@ | |
5656 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5657 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5658 | [(set_attr "length" "8")]) | |
5659 | \f | |
5660 | ;; PowerPC64 DImode operations. | |
5661 | ||
5662 | (define_expand "adddi3" | |
5663 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5664 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 5665 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
5666 | "" |
5667 | " | |
5668 | { | |
a260abc9 DE |
5669 | if (! TARGET_POWERPC64) |
5670 | { | |
5671 | if (non_short_cint_operand (operands[2], DImode)) | |
5672 | FAIL; | |
5673 | } | |
5674 | else | |
5675 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5676 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5677 | { |
677a9668 | 5678 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5679 | ? operands[0] : gen_reg_rtx (DImode)); |
5680 | ||
2bfcf297 DB |
5681 | HOST_WIDE_INT val = INTVAL (operands[2]); |
5682 | HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); | |
5683 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); | |
a260abc9 | 5684 | |
2bfcf297 DB |
5685 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
5686 | FAIL; | |
a260abc9 | 5687 | |
2bfcf297 DB |
5688 | /* The ordering here is important for the prolog expander. |
5689 | When space is allocated from the stack, adding 'low' first may | |
5690 | produce a temporary deallocation (which would be bad). */ | |
5691 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
5692 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
5693 | DONE; | |
5694 | } | |
266eb58a DE |
5695 | }") |
5696 | ||
5697 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5698 | ;; allowing register zero as source. | |
5699 | ||
a260abc9 | 5700 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5701 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5702 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5703 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5704 | "TARGET_POWERPC64" |
5705 | "@ | |
5706 | add %0,%1,%2 | |
5707 | addi %0,%1,%2 | |
5708 | addic %0,%1,%2 | |
802a0058 | 5709 | addis %0,%1,%v2") |
266eb58a | 5710 | |
a260abc9 | 5711 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5712 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5713 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5714 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5715 | (const_int 0))) |
9ebbca7d | 5716 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
266eb58a DE |
5717 | "TARGET_POWERPC64" |
5718 | "@ | |
5719 | add. %3,%1,%2 | |
9ebbca7d GK |
5720 | addic. %3,%1,%2 |
5721 | # | |
5722 | #" | |
5723 | [(set_attr "type" "compare") | |
5724 | (set_attr "length" "4,4,8,8")]) | |
5725 | ||
5726 | (define_split | |
5727 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5728 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5729 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5730 | (const_int 0))) | |
5731 | (clobber (match_scratch:DI 3 ""))] | |
5732 | "TARGET_POWERPC64 && reload_completed" | |
5733 | [(set (match_dup 3) | |
5734 | (plus:DI (match_dup 1) (match_dup 2))) | |
5735 | (set (match_dup 0) | |
5736 | (compare:CC (match_dup 3) | |
5737 | (const_int 0)))] | |
5738 | "") | |
266eb58a | 5739 | |
a260abc9 | 5740 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5741 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5742 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5743 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5744 | (const_int 0))) |
9ebbca7d | 5745 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a DE |
5746 | (plus:DI (match_dup 1) (match_dup 2)))] |
5747 | "TARGET_POWERPC64" | |
5748 | "@ | |
5749 | add. %0,%1,%2 | |
9ebbca7d GK |
5750 | addic. %0,%1,%2 |
5751 | # | |
5752 | #" | |
5753 | [(set_attr "type" "compare") | |
5754 | (set_attr "length" "4,4,8,8")]) | |
5755 | ||
5756 | (define_split | |
5757 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5758 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5759 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5760 | (const_int 0))) | |
5761 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5762 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5763 | "TARGET_POWERPC64 && reload_completed" | |
5764 | [(set (match_dup 0) | |
5765 | (plus:DI (match_dup 1) (match_dup 2))) | |
5766 | (set (match_dup 3) | |
5767 | (compare:CC (match_dup 0) | |
5768 | (const_int 0)))] | |
5769 | "") | |
266eb58a DE |
5770 | |
5771 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5772 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5773 | ;; add should be last in case the result gets used in an address. | |
5774 | ||
5775 | (define_split | |
5776 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5777 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5778 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5779 | "TARGET_POWERPC64" | |
5780 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5781 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5782 | " | |
5783 | { | |
2bfcf297 DB |
5784 | HOST_WIDE_INT val = INTVAL (operands[2]); |
5785 | HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); | |
5786 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); | |
266eb58a | 5787 | |
2bfcf297 DB |
5788 | operands[4] = GEN_INT (low); |
5789 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
5790 | operands[3] = GEN_INT (rest); | |
5791 | else if (! no_new_pseudos) | |
38886f37 | 5792 | { |
2bfcf297 DB |
5793 | operands[3] = gen_reg_rtx (DImode); |
5794 | emit_move_insn (operands[3], operands[2]); | |
5795 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
5796 | DONE; | |
38886f37 | 5797 | } |
2bfcf297 DB |
5798 | else |
5799 | FAIL; | |
266eb58a DE |
5800 | }") |
5801 | ||
5802 | (define_insn "one_cmpldi2" | |
5803 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5804 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5805 | "TARGET_POWERPC64" | |
5806 | "nor %0,%1,%1") | |
5807 | ||
5808 | (define_insn "" | |
9ebbca7d GK |
5809 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5810 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5811 | (const_int 0))) |
9ebbca7d | 5812 | (clobber (match_scratch:DI 2 "=r,r"))] |
266eb58a | 5813 | "TARGET_POWERPC64" |
9ebbca7d GK |
5814 | "@ |
5815 | nor. %2,%1,%1 | |
5816 | #" | |
5817 | [(set_attr "type" "compare") | |
5818 | (set_attr "length" "4,8")]) | |
5819 | ||
5820 | (define_split | |
5821 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5822 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5823 | (const_int 0))) | |
5824 | (clobber (match_scratch:DI 2 ""))] | |
5825 | "TARGET_POWERPC64 && reload_completed" | |
5826 | [(set (match_dup 2) | |
5827 | (not:DI (match_dup 1))) | |
5828 | (set (match_dup 0) | |
5829 | (compare:CC (match_dup 2) | |
5830 | (const_int 0)))] | |
5831 | "") | |
266eb58a DE |
5832 | |
5833 | (define_insn "" | |
9ebbca7d GK |
5834 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5835 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5836 | (const_int 0))) |
9ebbca7d | 5837 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5838 | (not:DI (match_dup 1)))] |
5839 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5840 | "@ |
5841 | nor. %0,%1,%1 | |
5842 | #" | |
5843 | [(set_attr "type" "compare") | |
5844 | (set_attr "length" "4,8")]) | |
5845 | ||
5846 | (define_split | |
5847 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5848 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5849 | (const_int 0))) | |
5850 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5851 | (not:DI (match_dup 1)))] | |
5852 | "TARGET_POWERPC64 && reload_completed" | |
5853 | [(set (match_dup 0) | |
5854 | (not:DI (match_dup 1))) | |
5855 | (set (match_dup 2) | |
5856 | (compare:CC (match_dup 0) | |
5857 | (const_int 0)))] | |
5858 | "") | |
266eb58a DE |
5859 | |
5860 | (define_insn "" | |
5861 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5862 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5863 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5864 | "TARGET_POWERPC64" | |
5865 | "@ | |
5866 | subf %0,%2,%1 | |
5867 | subfic %0,%2,%1") | |
5868 | ||
5869 | (define_insn "" | |
9ebbca7d GK |
5870 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5871 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5872 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5873 | (const_int 0))) |
9ebbca7d | 5874 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 5875 | "TARGET_POWERPC64" |
9ebbca7d GK |
5876 | "@ |
5877 | subf. %3,%2,%1 | |
5878 | #" | |
5879 | [(set_attr "type" "compare") | |
5880 | (set_attr "length" "4,8")]) | |
5881 | ||
5882 | (define_split | |
5883 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5884 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5885 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5886 | (const_int 0))) | |
5887 | (clobber (match_scratch:DI 3 ""))] | |
5888 | "TARGET_POWERPC64 && reload_completed" | |
5889 | [(set (match_dup 3) | |
5890 | (minus:DI (match_dup 1) (match_dup 2))) | |
5891 | (set (match_dup 0) | |
5892 | (compare:CC (match_dup 3) | |
5893 | (const_int 0)))] | |
5894 | "") | |
266eb58a DE |
5895 | |
5896 | (define_insn "" | |
9ebbca7d GK |
5897 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5898 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5899 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5900 | (const_int 0))) |
9ebbca7d | 5901 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5902 | (minus:DI (match_dup 1) (match_dup 2)))] |
5903 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5904 | "@ |
5905 | subf. %0,%2,%1 | |
5906 | #" | |
5907 | [(set_attr "type" "compare") | |
5908 | (set_attr "length" "4,8")]) | |
5909 | ||
5910 | (define_split | |
5911 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5912 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5913 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5914 | (const_int 0))) | |
5915 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5916 | (minus:DI (match_dup 1) (match_dup 2)))] | |
5917 | "TARGET_POWERPC64 && reload_completed" | |
5918 | [(set (match_dup 0) | |
5919 | (minus:DI (match_dup 1) (match_dup 2))) | |
5920 | (set (match_dup 3) | |
5921 | (compare:CC (match_dup 0) | |
5922 | (const_int 0)))] | |
5923 | "") | |
266eb58a DE |
5924 | |
5925 | (define_expand "subdi3" | |
5926 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5927 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 5928 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
5929 | "" |
5930 | " | |
5931 | { | |
5932 | if (GET_CODE (operands[2]) == CONST_INT) | |
5933 | { | |
5934 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
5935 | negate_rtx (DImode, operands[2]))); | |
5936 | DONE; | |
5937 | } | |
5938 | }") | |
5939 | ||
5940 | (define_insn "absdi2" | |
5941 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
5942 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
5943 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5944 | "TARGET_POWERPC64" | |
a260abc9 | 5945 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" |
266eb58a DE |
5946 | [(set_attr "length" "12")]) |
5947 | ||
5948 | (define_split | |
75540af0 JH |
5949 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
5950 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
5951 | (clobber (match_scratch:DI 2 ""))] | |
266eb58a | 5952 | "TARGET_POWERPC64 && reload_completed" |
a260abc9 | 5953 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5954 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 5955 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
5956 | "") |
5957 | ||
19ba8161 | 5958 | (define_insn "*nabsdi2" |
266eb58a DE |
5959 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5960 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
5961 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5962 | "TARGET_POWERPC64" | |
a260abc9 | 5963 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" |
266eb58a DE |
5964 | [(set_attr "length" "12")]) |
5965 | ||
5966 | (define_split | |
75540af0 JH |
5967 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
5968 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))) | |
5969 | (clobber (match_scratch:DI 2 ""))] | |
266eb58a | 5970 | "TARGET_POWERPC64 && reload_completed" |
a260abc9 | 5971 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5972 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 5973 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
5974 | "") |
5975 | ||
5976 | (define_expand "negdi2" | |
5977 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5978 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
5979 | "" | |
5980 | "") | |
5981 | ||
5982 | (define_insn "" | |
5983 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5984 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5985 | "TARGET_POWERPC64" | |
5986 | "neg %0,%1") | |
5987 | ||
5988 | (define_insn "" | |
9ebbca7d GK |
5989 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5990 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5991 | (const_int 0))) |
9ebbca7d | 5992 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 5993 | "TARGET_POWERPC64" |
9ebbca7d GK |
5994 | "@ |
5995 | neg. %2,%1 | |
5996 | #" | |
5997 | [(set_attr "type" "compare") | |
5998 | (set_attr "length" "4,8")]) | |
5999 | ||
6000 | (define_split | |
6001 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6002 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6003 | (const_int 0))) | |
6004 | (clobber (match_scratch:DI 2 ""))] | |
6005 | "TARGET_POWERPC64 && reload_completed" | |
6006 | [(set (match_dup 2) | |
6007 | (neg:DI (match_dup 1))) | |
6008 | (set (match_dup 0) | |
6009 | (compare:CC (match_dup 2) | |
6010 | (const_int 0)))] | |
6011 | "") | |
815cdc52 | 6012 | |
29ae5b89 | 6013 | (define_insn "" |
9ebbca7d GK |
6014 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6015 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6016 | (const_int 0))) |
9ebbca7d | 6017 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6018 | (neg:DI (match_dup 1)))] |
29ae5b89 | 6019 | "TARGET_POWERPC64" |
9ebbca7d GK |
6020 | "@ |
6021 | neg. %0,%1 | |
6022 | #" | |
6023 | [(set_attr "type" "compare") | |
6024 | (set_attr "length" "4,8")]) | |
6025 | ||
6026 | (define_split | |
6027 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6028 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6029 | (const_int 0))) | |
6030 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6031 | (neg:DI (match_dup 1)))] | |
6032 | "TARGET_POWERPC64 && reload_completed" | |
6033 | [(set (match_dup 0) | |
6034 | (neg:DI (match_dup 1))) | |
6035 | (set (match_dup 2) | |
6036 | (compare:CC (match_dup 0) | |
6037 | (const_int 0)))] | |
6038 | "") | |
266eb58a DE |
6039 | |
6040 | (define_insn "ffsdi2" | |
6041 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
6042 | (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6043 | "TARGET_POWERPC64" | |
6044 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
6045 | [(set_attr "length" "16")]) | |
6046 | ||
6047 | (define_insn "muldi3" | |
6048 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6049 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6050 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6051 | "TARGET_POWERPC64" | |
6052 | "mulld %0,%1,%2" | |
3cb999d8 | 6053 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6054 | |
6055 | (define_insn "smuldi3_highpart" | |
6056 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6057 | (truncate:DI | |
6058 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6059 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6060 | (sign_extend:TI | |
6061 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6062 | (const_int 64))))] | |
6063 | "TARGET_POWERPC64" | |
6064 | "mulhd %0,%1,%2" | |
3cb999d8 | 6065 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6066 | |
6067 | (define_insn "umuldi3_highpart" | |
6068 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6069 | (truncate:DI | |
6070 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6071 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6072 | (zero_extend:TI | |
6073 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6074 | (const_int 64))))] | |
6075 | "TARGET_POWERPC64" | |
6076 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6077 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6078 | |
6079 | (define_expand "divdi3" | |
6080 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6081 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6082 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6083 | "TARGET_POWERPC64" | |
6084 | " | |
6085 | { | |
6086 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6087 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6088 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6089 | ; | |
6090 | else | |
6091 | operands[2] = force_reg (DImode, operands[2]); | |
6092 | }") | |
6093 | ||
6094 | (define_expand "moddi3" | |
6095 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6096 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6097 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6098 | "TARGET_POWERPC64" | |
6099 | " | |
6100 | { | |
2bfcf297 | 6101 | int i; |
266eb58a DE |
6102 | rtx temp1; |
6103 | rtx temp2; | |
6104 | ||
2bfcf297 DB |
6105 | if (GET_CODE (operands[2]) != CONST_INT |
6106 | || INTVAL (operands[2]) <= 0 | |
6107 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6108 | FAIL; |
6109 | ||
6110 | temp1 = gen_reg_rtx (DImode); | |
6111 | temp2 = gen_reg_rtx (DImode); | |
6112 | ||
6113 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6114 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6115 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6116 | DONE; | |
6117 | }") | |
6118 | ||
6119 | (define_insn "" | |
6120 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6121 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6122 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6123 | "TARGET_POWERPC64" | |
266eb58a DE |
6124 | "sradi %0,%1,%p2\;addze %0,%0" |
6125 | [(set_attr "length" "8")]) | |
6126 | ||
6127 | (define_insn "" | |
9ebbca7d GK |
6128 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6129 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6130 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6131 | (const_int 0))) |
9ebbca7d | 6132 | (clobber (match_scratch:DI 3 "=r,r"))] |
2bfcf297 | 6133 | "TARGET_POWERPC64" |
9ebbca7d GK |
6134 | "@ |
6135 | sradi %3,%1,%p2\;addze. %3,%3 | |
6136 | #" | |
266eb58a | 6137 | [(set_attr "type" "compare") |
9ebbca7d GK |
6138 | (set_attr "length" "8,12")]) |
6139 | ||
6140 | (define_split | |
6141 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6142 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6143 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6144 | (const_int 0))) |
6145 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6146 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6147 | [(set (match_dup 3) |
6148 | (div:DI (match_dup 1) (match_dup 2))) | |
6149 | (set (match_dup 0) | |
6150 | (compare:CC (match_dup 3) | |
6151 | (const_int 0)))] | |
6152 | "") | |
266eb58a DE |
6153 | |
6154 | (define_insn "" | |
9ebbca7d GK |
6155 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6156 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6157 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6158 | (const_int 0))) |
9ebbca7d | 6159 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6160 | (div:DI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 6161 | "TARGET_POWERPC64" |
9ebbca7d GK |
6162 | "@ |
6163 | sradi %0,%1,%p2\;addze. %0,%0 | |
6164 | #" | |
266eb58a | 6165 | [(set_attr "type" "compare") |
9ebbca7d | 6166 | (set_attr "length" "8,12")]) |
266eb58a | 6167 | |
9ebbca7d GK |
6168 | (define_split |
6169 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6170 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6171 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6172 | (const_int 0))) |
6173 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6174 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6175 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6176 | [(set (match_dup 0) |
6177 | (div:DI (match_dup 1) (match_dup 2))) | |
6178 | (set (match_dup 3) | |
6179 | (compare:CC (match_dup 0) | |
6180 | (const_int 0)))] | |
6181 | "") | |
6182 | ||
6183 | (define_insn "" | |
6184 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6185 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6186 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6187 | "TARGET_POWERPC64" |
6188 | "divd %0,%1,%2" | |
3cb999d8 | 6189 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6190 | |
6191 | (define_insn "udivdi3" | |
6192 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6193 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6194 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6195 | "TARGET_POWERPC64" | |
6196 | "divdu %0,%1,%2" | |
3cb999d8 | 6197 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6198 | |
6199 | (define_insn "rotldi3" | |
6200 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6201 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6202 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6203 | "TARGET_POWERPC64" | |
a66078ee | 6204 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6205 | |
a260abc9 | 6206 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6207 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6208 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6209 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6210 | (const_int 0))) |
9ebbca7d | 6211 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6212 | "TARGET_POWERPC64" |
9ebbca7d GK |
6213 | "@ |
6214 | rld%I2cl. %3,%1,%H2,0 | |
6215 | #" | |
6216 | [(set_attr "type" "delayed_compare") | |
6217 | (set_attr "length" "4,8")]) | |
6218 | ||
6219 | (define_split | |
6220 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6221 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6222 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6223 | (const_int 0))) | |
6224 | (clobber (match_scratch:DI 3 ""))] | |
6225 | "TARGET_POWERPC64 && reload_completed" | |
6226 | [(set (match_dup 3) | |
6227 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6228 | (set (match_dup 0) | |
6229 | (compare:CC (match_dup 3) | |
6230 | (const_int 0)))] | |
6231 | "") | |
266eb58a | 6232 | |
a260abc9 | 6233 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6234 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6235 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6236 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6237 | (const_int 0))) |
9ebbca7d | 6238 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6239 | (rotate:DI (match_dup 1) (match_dup 2)))] |
6240 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6241 | "@ |
6242 | rld%I2cl. %0,%1,%H2,0 | |
6243 | #" | |
6244 | [(set_attr "type" "delayed_compare") | |
6245 | (set_attr "length" "4,8")]) | |
6246 | ||
6247 | (define_split | |
6248 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6249 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6250 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6251 | (const_int 0))) | |
6252 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6253 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6254 | "TARGET_POWERPC64 && reload_completed" | |
6255 | [(set (match_dup 0) | |
6256 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6257 | (set (match_dup 3) | |
6258 | (compare:CC (match_dup 0) | |
6259 | (const_int 0)))] | |
6260 | "") | |
266eb58a | 6261 | |
a260abc9 DE |
6262 | (define_insn "*rotldi3_internal4" |
6263 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6264 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6265 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
6266 | (match_operand:DI 3 "mask64_operand" "S")))] | |
6267 | "TARGET_POWERPC64" | |
6268 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6269 | ||
6270 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6271 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6272 | (compare:CC (and:DI |
9ebbca7d GK |
6273 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6274 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6275 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6276 | (const_int 0))) |
9ebbca7d | 6277 | (clobber (match_scratch:DI 4 "=r,r"))] |
a260abc9 | 6278 | "TARGET_POWERPC64" |
9ebbca7d GK |
6279 | "@ |
6280 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6281 | #" | |
6282 | [(set_attr "type" "delayed_compare") | |
6283 | (set_attr "length" "4,8")]) | |
6284 | ||
6285 | (define_split | |
6286 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6287 | (compare:CC (and:DI | |
6288 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6289 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6290 | (match_operand:DI 3 "mask64_operand" "")) | |
6291 | (const_int 0))) | |
6292 | (clobber (match_scratch:DI 4 ""))] | |
6293 | "TARGET_POWERPC64 && reload_completed" | |
6294 | [(set (match_dup 4) | |
6295 | (and:DI (rotate:DI (match_dup 1) | |
6296 | (match_dup 2)) | |
6297 | (match_dup 3))) | |
6298 | (set (match_dup 0) | |
6299 | (compare:CC (match_dup 4) | |
6300 | (const_int 0)))] | |
6301 | "") | |
a260abc9 DE |
6302 | |
6303 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6304 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6305 | (compare:CC (and:DI |
9ebbca7d GK |
6306 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6307 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6308 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6309 | (const_int 0))) |
9ebbca7d | 6310 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6311 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
6312 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6313 | "@ |
6314 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6315 | #" | |
6316 | [(set_attr "type" "delayed_compare") | |
6317 | (set_attr "length" "4,8")]) | |
6318 | ||
6319 | (define_split | |
6320 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6321 | (compare:CC (and:DI | |
6322 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6323 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6324 | (match_operand:DI 3 "mask64_operand" "")) | |
6325 | (const_int 0))) | |
6326 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6327 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6328 | "TARGET_POWERPC64 && reload_completed" | |
6329 | [(set (match_dup 0) | |
6330 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6331 | (set (match_dup 4) | |
6332 | (compare:CC (match_dup 0) | |
6333 | (const_int 0)))] | |
6334 | "") | |
a260abc9 DE |
6335 | |
6336 | (define_insn "*rotldi3_internal7" | |
6337 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6338 | (zero_extend:DI | |
6339 | (subreg:QI | |
6340 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6341 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6342 | "TARGET_POWERPC64" | |
6343 | "rld%I2cl %0,%1,%H2,56") | |
6344 | ||
6345 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6346 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6347 | (compare:CC (zero_extend:DI |
6348 | (subreg:QI | |
9ebbca7d GK |
6349 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6350 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6351 | (const_int 0))) |
9ebbca7d | 6352 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6353 | "TARGET_POWERPC64" |
9ebbca7d GK |
6354 | "@ |
6355 | rld%I2cl. %3,%1,%H2,56 | |
6356 | #" | |
6357 | [(set_attr "type" "delayed_compare") | |
6358 | (set_attr "length" "4,8")]) | |
6359 | ||
6360 | (define_split | |
6361 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6362 | (compare:CC (zero_extend:DI | |
6363 | (subreg:QI | |
6364 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6365 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6366 | (const_int 0))) | |
6367 | (clobber (match_scratch:DI 3 ""))] | |
6368 | "TARGET_POWERPC64 && reload_completed" | |
6369 | [(set (match_dup 3) | |
6370 | (zero_extend:DI (subreg:QI | |
6371 | (rotate:DI (match_dup 1) | |
6372 | (match_dup 2)) 0))) | |
6373 | (set (match_dup 0) | |
6374 | (compare:CC (match_dup 3) | |
6375 | (const_int 0)))] | |
6376 | "") | |
a260abc9 DE |
6377 | |
6378 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6379 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6380 | (compare:CC (zero_extend:DI |
6381 | (subreg:QI | |
9ebbca7d GK |
6382 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6383 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6384 | (const_int 0))) |
9ebbca7d | 6385 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6386 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6387 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6388 | "@ |
6389 | rld%I2cl. %0,%1,%H2,56 | |
6390 | #" | |
6391 | [(set_attr "type" "delayed_compare") | |
6392 | (set_attr "length" "4,8")]) | |
6393 | ||
6394 | (define_split | |
6395 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6396 | (compare:CC (zero_extend:DI | |
6397 | (subreg:QI | |
6398 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6399 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6400 | (const_int 0))) | |
6401 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6402 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6403 | "TARGET_POWERPC64 && reload_completed" | |
6404 | [(set (match_dup 0) | |
6405 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6406 | (set (match_dup 3) | |
6407 | (compare:CC (match_dup 0) | |
6408 | (const_int 0)))] | |
6409 | "") | |
a260abc9 DE |
6410 | |
6411 | (define_insn "*rotldi3_internal10" | |
6412 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6413 | (zero_extend:DI | |
6414 | (subreg:HI | |
6415 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6416 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6417 | "TARGET_POWERPC64" | |
6418 | "rld%I2cl %0,%1,%H2,48") | |
6419 | ||
6420 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6421 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6422 | (compare:CC (zero_extend:DI |
6423 | (subreg:HI | |
9ebbca7d GK |
6424 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6425 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6426 | (const_int 0))) |
9ebbca7d | 6427 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6428 | "TARGET_POWERPC64" |
9ebbca7d GK |
6429 | "@ |
6430 | rld%I2cl. %3,%1,%H2,48 | |
6431 | #" | |
6432 | [(set_attr "type" "delayed_compare") | |
6433 | (set_attr "length" "4,8")]) | |
6434 | ||
6435 | (define_split | |
6436 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6437 | (compare:CC (zero_extend:DI | |
6438 | (subreg:HI | |
6439 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6440 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6441 | (const_int 0))) | |
6442 | (clobber (match_scratch:DI 3 ""))] | |
6443 | "TARGET_POWERPC64 && reload_completed" | |
6444 | [(set (match_dup 3) | |
6445 | (zero_extend:DI (subreg:HI | |
6446 | (rotate:DI (match_dup 1) | |
6447 | (match_dup 2)) 0))) | |
6448 | (set (match_dup 0) | |
6449 | (compare:CC (match_dup 3) | |
6450 | (const_int 0)))] | |
6451 | "") | |
a260abc9 DE |
6452 | |
6453 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6454 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6455 | (compare:CC (zero_extend:DI |
6456 | (subreg:HI | |
9ebbca7d GK |
6457 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6458 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6459 | (const_int 0))) |
9ebbca7d | 6460 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6461 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6462 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6463 | "@ |
6464 | rld%I2cl. %0,%1,%H2,48 | |
6465 | #" | |
6466 | [(set_attr "type" "delayed_compare") | |
6467 | (set_attr "length" "4,8")]) | |
6468 | ||
6469 | (define_split | |
6470 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6471 | (compare:CC (zero_extend:DI | |
6472 | (subreg:HI | |
6473 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6474 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6475 | (const_int 0))) | |
6476 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6477 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6478 | "TARGET_POWERPC64 && reload_completed" | |
6479 | [(set (match_dup 0) | |
6480 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6481 | (set (match_dup 3) | |
6482 | (compare:CC (match_dup 0) | |
6483 | (const_int 0)))] | |
6484 | "") | |
a260abc9 DE |
6485 | |
6486 | (define_insn "*rotldi3_internal13" | |
6487 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6488 | (zero_extend:DI | |
6489 | (subreg:SI | |
6490 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6491 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6492 | "TARGET_POWERPC64" | |
6493 | "rld%I2cl %0,%1,%H2,32") | |
6494 | ||
6495 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6496 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6497 | (compare:CC (zero_extend:DI |
6498 | (subreg:SI | |
9ebbca7d GK |
6499 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6500 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6501 | (const_int 0))) |
9ebbca7d | 6502 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6503 | "TARGET_POWERPC64" |
9ebbca7d GK |
6504 | "@ |
6505 | rld%I2cl. %3,%1,%H2,32 | |
6506 | #" | |
6507 | [(set_attr "type" "delayed_compare") | |
6508 | (set_attr "length" "4,8")]) | |
6509 | ||
6510 | (define_split | |
6511 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6512 | (compare:CC (zero_extend:DI | |
6513 | (subreg:SI | |
6514 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6515 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6516 | (const_int 0))) | |
6517 | (clobber (match_scratch:DI 3 ""))] | |
6518 | "TARGET_POWERPC64 && reload_completed" | |
6519 | [(set (match_dup 3) | |
6520 | (zero_extend:DI (subreg:SI | |
6521 | (rotate:DI (match_dup 1) | |
6522 | (match_dup 2)) 0))) | |
6523 | (set (match_dup 0) | |
6524 | (compare:CC (match_dup 3) | |
6525 | (const_int 0)))] | |
6526 | "") | |
a260abc9 DE |
6527 | |
6528 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6529 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6530 | (compare:CC (zero_extend:DI |
6531 | (subreg:SI | |
9ebbca7d GK |
6532 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6533 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6534 | (const_int 0))) |
9ebbca7d | 6535 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6536 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6537 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6538 | "@ |
6539 | rld%I2cl. %0,%1,%H2,32 | |
6540 | #" | |
6541 | [(set_attr "type" "delayed_compare") | |
6542 | (set_attr "length" "4,8")]) | |
6543 | ||
6544 | (define_split | |
6545 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6546 | (compare:CC (zero_extend:DI | |
6547 | (subreg:SI | |
6548 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6549 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6550 | (const_int 0))) | |
6551 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6552 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6553 | "TARGET_POWERPC64 && reload_completed" | |
6554 | [(set (match_dup 0) | |
6555 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6556 | (set (match_dup 3) | |
6557 | (compare:CC (match_dup 0) | |
6558 | (const_int 0)))] | |
6559 | "") | |
a260abc9 | 6560 | |
266eb58a DE |
6561 | (define_expand "ashldi3" |
6562 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6563 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6564 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6565 | "TARGET_POWERPC64 || TARGET_POWER" | |
6566 | " | |
6567 | { | |
6568 | if (TARGET_POWERPC64) | |
6569 | ; | |
6570 | else if (TARGET_POWER) | |
6571 | { | |
6572 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6573 | DONE; | |
6574 | } | |
6575 | else | |
6576 | FAIL; | |
6577 | }") | |
6578 | ||
e2c953b6 | 6579 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6580 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6581 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6582 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6583 | "TARGET_POWERPC64" | |
a66078ee | 6584 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
6585 | [(set_attr "length" "8")]) |
6586 | ||
e2c953b6 | 6587 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6588 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6589 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6590 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6591 | (const_int 0))) |
9ebbca7d | 6592 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6593 | "TARGET_POWERPC64" |
9ebbca7d GK |
6594 | "@ |
6595 | sld%I2. %3,%1,%H2 | |
6596 | #" | |
6597 | [(set_attr "type" "delayed_compare") | |
6598 | (set_attr "length" "4,8")]) | |
29ae5b89 | 6599 | |
9ebbca7d GK |
6600 | (define_split |
6601 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6602 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6603 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6604 | (const_int 0))) | |
6605 | (clobber (match_scratch:DI 3 ""))] | |
6606 | "TARGET_POWERPC64 && reload_completed" | |
6607 | [(set (match_dup 3) | |
6608 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6609 | (set (match_dup 0) | |
6610 | (compare:CC (match_dup 3) | |
6611 | (const_int 0)))] | |
6612 | "") | |
6613 | ||
e2c953b6 | 6614 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6615 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6616 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6617 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6618 | (const_int 0))) |
9ebbca7d | 6619 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6620 | (ashift:DI (match_dup 1) (match_dup 2)))] |
6621 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6622 | "@ |
6623 | sld%I2. %0,%1,%H2 | |
6624 | #" | |
6625 | [(set_attr "type" "delayed_compare") | |
6626 | (set_attr "length" "4,8")]) | |
6627 | ||
6628 | (define_split | |
6629 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6630 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6631 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6632 | (const_int 0))) | |
6633 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6634 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6635 | "TARGET_POWERPC64 && reload_completed" | |
6636 | [(set (match_dup 0) | |
6637 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6638 | (set (match_dup 3) | |
6639 | (compare:CC (match_dup 0) | |
6640 | (const_int 0)))] | |
6641 | "") | |
266eb58a | 6642 | |
e2c953b6 | 6643 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6644 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6645 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6646 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6647 | (match_operand:DI 3 "const_int_operand" "n")))] |
6648 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6649 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6650 | |
e2c953b6 | 6651 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6652 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6653 | (compare:CC |
9ebbca7d GK |
6654 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6655 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6656 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6657 | (const_int 0))) |
9ebbca7d | 6658 | (clobber (match_scratch:DI 4 "=r,r"))] |
c5059423 | 6659 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6660 | "@ |
e2c953b6 | 6661 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6662 | #" |
6663 | [(set_attr "type" "delayed_compare") | |
6664 | (set_attr "length" "4,8")]) | |
6665 | ||
6666 | (define_split | |
6667 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6668 | (compare:CC | |
6669 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6670 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6671 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6672 | (const_int 0))) |
6673 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6674 | "TARGET_POWERPC64 && reload_completed |
6675 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6676 | [(set (match_dup 4) |
6677 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6678 | (match_dup 3))) |
9ebbca7d GK |
6679 | (set (match_dup 0) |
6680 | (compare:CC (match_dup 4) | |
6681 | (const_int 0)))] | |
6682 | "") | |
3cb999d8 | 6683 | |
e2c953b6 | 6684 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6685 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6686 | (compare:CC |
9ebbca7d GK |
6687 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6688 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6689 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6690 | (const_int 0))) |
9ebbca7d | 6691 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6692 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
c5059423 | 6693 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6694 | "@ |
e2c953b6 | 6695 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6696 | #" |
6697 | [(set_attr "type" "delayed_compare") | |
6698 | (set_attr "length" "4,8")]) | |
6699 | ||
6700 | (define_split | |
6701 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6702 | (compare:CC | |
6703 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6704 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6705 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6706 | (const_int 0))) |
6707 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6708 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6709 | "TARGET_POWERPC64 && reload_completed |
6710 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6711 | [(set (match_dup 0) | |
6712 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6713 | (match_dup 3))) | |
6714 | (set (match_dup 4) | |
6715 | (compare:CC (match_dup 0) | |
6716 | (const_int 0)))] | |
6717 | "") | |
6718 | ||
6719 | (define_insn "*ashldi3_internal7" | |
6720 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6721 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6722 | (match_operand:SI 2 "const_int_operand" "i")) | |
6723 | (match_operand:DI 3 "mask64_operand" "S")))] | |
6724 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6725 | "rldicr %0,%1,%H2,%S3") | |
6726 | ||
6727 | (define_insn "ashldi3_internal8" | |
6728 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6729 | (compare:CC | |
6730 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6731 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
6732 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
6733 | (const_int 0))) | |
6734 | (clobber (match_scratch:DI 4 "=r,r"))] | |
6735 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6736 | "@ | |
6737 | rldicr. %4,%1,%H2,%S3 | |
6738 | #" | |
6739 | [(set_attr "type" "delayed_compare") | |
6740 | (set_attr "length" "4,8")]) | |
6741 | ||
6742 | (define_split | |
6743 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6744 | (compare:CC | |
6745 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6746 | (match_operand:SI 2 "const_int_operand" "")) | |
6747 | (match_operand:DI 3 "mask64_operand" "")) | |
6748 | (const_int 0))) | |
6749 | (clobber (match_scratch:DI 4 ""))] | |
6750 | "TARGET_POWERPC64 && reload_completed | |
6751 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6752 | [(set (match_dup 4) | |
6753 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6754 | (match_dup 3))) | |
6755 | (set (match_dup 0) | |
6756 | (compare:CC (match_dup 4) | |
6757 | (const_int 0)))] | |
6758 | "") | |
6759 | ||
6760 | (define_insn "*ashldi3_internal9" | |
6761 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6762 | (compare:CC | |
6763 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6764 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
6765 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
6766 | (const_int 0))) | |
6767 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6768 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6769 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6770 | "@ | |
6771 | rldicr. %0,%1,%H2,%S3 | |
6772 | #" | |
6773 | [(set_attr "type" "delayed_compare") | |
6774 | (set_attr "length" "4,8")]) | |
6775 | ||
6776 | (define_split | |
6777 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6778 | (compare:CC | |
6779 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6780 | (match_operand:SI 2 "const_int_operand" "")) | |
6781 | (match_operand:DI 3 "mask64_operand" "")) | |
6782 | (const_int 0))) | |
6783 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6784 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6785 | "TARGET_POWERPC64 && reload_completed | |
6786 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6787 | [(set (match_dup 0) |
e2c953b6 DE |
6788 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6789 | (match_dup 3))) | |
9ebbca7d GK |
6790 | (set (match_dup 4) |
6791 | (compare:CC (match_dup 0) | |
6792 | (const_int 0)))] | |
6793 | "") | |
6794 | ||
6795 | (define_expand "lshrdi3" | |
266eb58a DE |
6796 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6797 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6798 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6799 | "TARGET_POWERPC64 || TARGET_POWER" | |
6800 | " | |
6801 | { | |
6802 | if (TARGET_POWERPC64) | |
6803 | ; | |
6804 | else if (TARGET_POWER) | |
6805 | { | |
6806 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6807 | DONE; | |
6808 | } | |
6809 | else | |
6810 | FAIL; | |
6811 | }") | |
6812 | ||
e2c953b6 | 6813 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6814 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6815 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6816 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6817 | "TARGET_POWERPC64" | |
a66078ee | 6818 | "srd%I2 %0,%1,%H2") |
266eb58a | 6819 | |
e2c953b6 | 6820 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6821 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6822 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6823 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6824 | (const_int 0))) |
9ebbca7d | 6825 | (clobber (match_scratch:DI 3 "=r,r"))] |
29ae5b89 | 6826 | "TARGET_POWERPC64" |
9ebbca7d GK |
6827 | "@ |
6828 | srd%I2. %3,%1,%H2 | |
6829 | #" | |
6830 | [(set_attr "type" "delayed_compare") | |
6831 | (set_attr "length" "4,8")]) | |
6832 | ||
6833 | (define_split | |
6834 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6835 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6836 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6837 | (const_int 0))) | |
6838 | (clobber (match_scratch:DI 3 ""))] | |
6839 | "TARGET_POWERPC64 && reload_completed" | |
6840 | [(set (match_dup 3) | |
6841 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6842 | (set (match_dup 0) | |
6843 | (compare:CC (match_dup 3) | |
6844 | (const_int 0)))] | |
6845 | "") | |
266eb58a | 6846 | |
e2c953b6 | 6847 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6848 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6849 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6850 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6851 | (const_int 0))) |
9ebbca7d | 6852 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 JL |
6853 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
6854 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6855 | "@ |
6856 | srd%I2. %0,%1,%H2 | |
6857 | #" | |
6858 | [(set_attr "type" "delayed_compare") | |
6859 | (set_attr "length" "4,8")]) | |
6860 | ||
6861 | (define_split | |
6862 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6863 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6864 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6865 | (const_int 0))) | |
6866 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6867 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6868 | "TARGET_POWERPC64 && reload_completed" | |
6869 | [(set (match_dup 0) | |
6870 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6871 | (set (match_dup 3) | |
6872 | (compare:CC (match_dup 0) | |
6873 | (const_int 0)))] | |
6874 | "") | |
266eb58a DE |
6875 | |
6876 | (define_expand "ashrdi3" | |
6877 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6878 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6879 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6880 | "TARGET_POWERPC64 || TARGET_POWER" | |
6881 | " | |
6882 | { | |
6883 | if (TARGET_POWERPC64) | |
6884 | ; | |
6885 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6886 | { | |
6887 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6888 | DONE; | |
6889 | } | |
6890 | else | |
6891 | FAIL; | |
6892 | }") | |
6893 | ||
e2c953b6 | 6894 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
6895 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6896 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6897 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6898 | "TARGET_POWERPC64" | |
375490e0 | 6899 | "srad%I2 %0,%1,%H2") |
266eb58a | 6900 | |
e2c953b6 | 6901 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
6902 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6903 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6904 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6905 | (const_int 0))) |
9ebbca7d | 6906 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6907 | "TARGET_POWERPC64" |
9ebbca7d GK |
6908 | "@ |
6909 | srad%I2. %3,%1,%H2 | |
6910 | #" | |
6911 | [(set_attr "type" "delayed_compare") | |
6912 | (set_attr "length" "4,8")]) | |
6913 | ||
6914 | (define_split | |
6915 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6916 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6917 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6918 | (const_int 0))) | |
6919 | (clobber (match_scratch:DI 3 ""))] | |
6920 | "TARGET_POWERPC64 && reload_completed" | |
6921 | [(set (match_dup 3) | |
6922 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6923 | (set (match_dup 0) | |
6924 | (compare:CC (match_dup 3) | |
6925 | (const_int 0)))] | |
6926 | "") | |
266eb58a | 6927 | |
e2c953b6 | 6928 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
6929 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6930 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6931 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6932 | (const_int 0))) |
9ebbca7d | 6933 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6934 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6935 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6936 | "@ |
6937 | srad%I2. %0,%1,%H2 | |
6938 | #" | |
6939 | [(set_attr "type" "delayed_compare") | |
6940 | (set_attr "length" "4,8")]) | |
6941 | ||
6942 | (define_split | |
6943 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6944 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6945 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6946 | (const_int 0))) | |
6947 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6948 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
6949 | "TARGET_POWERPC64 && reload_completed" | |
6950 | [(set (match_dup 0) | |
6951 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6952 | (set (match_dup 3) | |
6953 | (compare:CC (match_dup 0) | |
6954 | (const_int 0)))] | |
6955 | "") | |
815cdc52 | 6956 | |
29ae5b89 JL |
6957 | (define_insn "anddi3" |
6958 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") | |
6959 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
6960 | (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) | |
6961 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
6ffc8580 | 6962 | "TARGET_POWERPC64" |
266eb58a DE |
6963 | "@ |
6964 | and %0,%1,%2 | |
29ae5b89 JL |
6965 | rldic%B2 %0,%1,0,%S2 |
6966 | andi. %0,%1,%b2 | |
6967 | andis. %0,%1,%u2") | |
266eb58a | 6968 | |
a260abc9 | 6969 | (define_insn "*anddi3_internal2" |
6c873122 | 6970 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") |
9ebbca7d | 6971 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,") |
6c873122 | 6972 | (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) |
266eb58a | 6973 | (const_int 0))) |
9ebbca7d | 6974 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r")) |
6c873122 | 6975 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] |
6ffc8580 | 6976 | "TARGET_POWERPC64" |
266eb58a DE |
6977 | "@ |
6978 | and. %3,%1,%2 | |
6c873122 | 6979 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
6980 | andi. %3,%1,%b2 |
6981 | andis. %3,%1,%u2 | |
9ebbca7d GK |
6982 | # |
6983 | # | |
6984 | # | |
6985 | #" | |
6c873122 | 6986 | [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") |
9ebbca7d GK |
6987 | (set_attr "length" "4,4,4,4,8,8,8,8")]) |
6988 | ||
6989 | (define_split | |
6990 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6991 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6992 | (match_operand:DI 2 "and64_operand" "")) | |
6993 | (const_int 0))) | |
6994 | (clobber (match_scratch:DI 3 "")) | |
6995 | (clobber (match_scratch:CC 4 ""))] | |
6996 | "TARGET_POWERPC64 && reload_completed" | |
6997 | [(parallel [(set (match_dup 3) | |
6998 | (and:DI (match_dup 1) | |
6999 | (match_dup 2))) | |
7000 | (clobber (match_dup 4))]) | |
7001 | (set (match_dup 0) | |
7002 | (compare:CC (match_dup 3) | |
7003 | (const_int 0)))] | |
7004 | "") | |
266eb58a | 7005 | |
a260abc9 | 7006 | (define_insn "*anddi3_internal3" |
6c873122 | 7007 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") |
9ebbca7d | 7008 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") |
6c873122 | 7009 | (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) |
266eb58a | 7010 | (const_int 0))) |
9ebbca7d GK |
7011 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") |
7012 | (and:DI (match_dup 1) (match_dup 2))) | |
6c873122 | 7013 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] |
6ffc8580 | 7014 | "TARGET_POWERPC64" |
266eb58a DE |
7015 | "@ |
7016 | and. %0,%1,%2 | |
6c873122 | 7017 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7018 | andi. %0,%1,%b2 |
7019 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7020 | # |
7021 | # | |
7022 | # | |
7023 | #" | |
6c873122 | 7024 | [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") |
9ebbca7d GK |
7025 | (set_attr "length" "4,4,4,4,8,8,8,8")]) |
7026 | ||
7027 | (define_split | |
7028 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7029 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7030 | (match_operand:DI 2 "and64_operand" "")) | |
7031 | (const_int 0))) | |
7032 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7033 | (and:DI (match_dup 1) (match_dup 2))) | |
7034 | (clobber (match_scratch:CC 4 ""))] | |
7035 | "TARGET_POWERPC64 && reload_completed" | |
7036 | [(parallel [(set (match_dup 0) | |
7037 | (and:DI (match_dup 1) (match_dup 2))) | |
7038 | (clobber (match_dup 4))]) | |
7039 | (set (match_dup 3) | |
7040 | (compare:CC (match_dup 0) | |
7041 | (const_int 0)))] | |
7042 | "") | |
266eb58a | 7043 | |
a260abc9 | 7044 | (define_expand "iordi3" |
266eb58a | 7045 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7046 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7047 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7048 | "TARGET_POWERPC64" |
266eb58a DE |
7049 | " |
7050 | { | |
dfbdccdb | 7051 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7052 | { |
dfbdccdb | 7053 | HOST_WIDE_INT value; |
677a9668 | 7054 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7055 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7056 | |
dfbdccdb GK |
7057 | if (GET_CODE (operands[2]) == CONST_INT) |
7058 | { | |
7059 | value = INTVAL (operands[2]); | |
7060 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7061 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7062 | } | |
e2c953b6 | 7063 | else |
dfbdccdb GK |
7064 | { |
7065 | value = CONST_DOUBLE_LOW (operands[2]); | |
7066 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7067 | immed_double_const (value | |
7068 | & (~ (HOST_WIDE_INT) 0xffff), | |
7069 | 0, DImode))); | |
7070 | } | |
e2c953b6 | 7071 | |
9ebbca7d GK |
7072 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7073 | DONE; | |
7074 | } | |
266eb58a DE |
7075 | }") |
7076 | ||
a260abc9 DE |
7077 | (define_expand "xordi3" |
7078 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7079 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7080 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7081 | "TARGET_POWERPC64" |
7082 | " | |
7083 | { | |
dfbdccdb | 7084 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7085 | { |
dfbdccdb | 7086 | HOST_WIDE_INT value; |
677a9668 | 7087 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7088 | ? operands[0] : gen_reg_rtx (DImode)); |
7089 | ||
dfbdccdb GK |
7090 | if (GET_CODE (operands[2]) == CONST_INT) |
7091 | { | |
7092 | value = INTVAL (operands[2]); | |
7093 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7094 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7095 | } | |
e2c953b6 | 7096 | else |
dfbdccdb GK |
7097 | { |
7098 | value = CONST_DOUBLE_LOW (operands[2]); | |
7099 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7100 | immed_double_const (value | |
7101 | & (~ (HOST_WIDE_INT) 0xffff), | |
7102 | 0, DImode))); | |
7103 | } | |
e2c953b6 | 7104 | |
9ebbca7d GK |
7105 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7106 | DONE; | |
7107 | } | |
a260abc9 DE |
7108 | }") |
7109 | ||
dfbdccdb | 7110 | (define_insn "*booldi3_internal1" |
266eb58a | 7111 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7112 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7113 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7114 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7115 | "TARGET_POWERPC64" |
1fd4e8c1 | 7116 | "@ |
dfbdccdb GK |
7117 | %q3 %0,%1,%2 |
7118 | %q3i %0,%1,%b2 | |
7119 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7120 | |
dfbdccdb | 7121 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7122 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7123 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7124 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7125 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7126 | (const_int 0))) | |
9ebbca7d | 7127 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7128 | "TARGET_POWERPC64" |
9ebbca7d | 7129 | "@ |
dfbdccdb | 7130 | %q4. %3,%1,%2 |
9ebbca7d GK |
7131 | #" |
7132 | [(set_attr "type" "compare") | |
7133 | (set_attr "length" "4,8")]) | |
7134 | ||
7135 | (define_split | |
7136 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7137 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7138 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7139 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7140 | (const_int 0))) |
9ebbca7d GK |
7141 | (clobber (match_scratch:DI 3 ""))] |
7142 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7143 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7144 | (set (match_dup 0) |
7145 | (compare:CC (match_dup 3) | |
7146 | (const_int 0)))] | |
7147 | "") | |
1fd4e8c1 | 7148 | |
dfbdccdb | 7149 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7150 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7151 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7152 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7153 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7154 | (const_int 0))) | |
9ebbca7d | 7155 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7156 | (match_dup 4))] |
266eb58a | 7157 | "TARGET_POWERPC64" |
9ebbca7d | 7158 | "@ |
dfbdccdb | 7159 | %q4. %0,%1,%2 |
9ebbca7d GK |
7160 | #" |
7161 | [(set_attr "type" "compare") | |
7162 | (set_attr "length" "4,8")]) | |
7163 | ||
7164 | (define_split | |
75540af0 | 7165 | [(set (match_operand:CC 3 "cc_reg_operand" "") |
dfbdccdb | 7166 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7167 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7168 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7169 | (const_int 0))) |
75540af0 | 7170 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7171 | (match_dup 4))] |
9ebbca7d | 7172 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7173 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7174 | (set (match_dup 3) |
7175 | (compare:CC (match_dup 0) | |
7176 | (const_int 0)))] | |
7177 | "") | |
1fd4e8c1 | 7178 | |
dfbdccdb GK |
7179 | ;; Split an logical operation that we can't do in one insn into two insns, |
7180 | ;; each of which does one 16-bit part. This is used by combine. | |
266eb58a DE |
7181 | |
7182 | (define_split | |
7183 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7184 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7185 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7186 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7187 | "TARGET_POWERPC64" |
dfbdccdb GK |
7188 | [(set (match_dup 0) (match_dup 4)) |
7189 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7190 | " |
7191 | { | |
dfbdccdb GK |
7192 | rtx i3,i4; |
7193 | ||
9ebbca7d GK |
7194 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7195 | { | |
7196 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7197 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7198 | 0, DImode); |
dfbdccdb | 7199 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7200 | } |
7201 | else | |
7202 | { | |
dfbdccdb | 7203 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7204 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7205 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7206 | } |
dfbdccdb GK |
7207 | operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, |
7208 | operands[1], i3); | |
7209 | operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, | |
7210 | operands[0], i4); | |
1fd4e8c1 RK |
7211 | }") |
7212 | ||
dfbdccdb | 7213 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7214 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7215 | (match_operator:DI 3 "boolean_operator" |
7216 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7217 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7218 | "TARGET_POWERPC64" |
1d328b19 | 7219 | "%q3 %0,%2,%1") |
a473029f | 7220 | |
dfbdccdb | 7221 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7222 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7223 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7224 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7225 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7226 | (const_int 0))) | |
9ebbca7d | 7227 | (clobber (match_scratch:DI 3 "=r,r"))] |
a473029f | 7228 | "TARGET_POWERPC64" |
9ebbca7d | 7229 | "@ |
1d328b19 | 7230 | %q4. %3,%2,%1 |
9ebbca7d GK |
7231 | #" |
7232 | [(set_attr "type" "compare") | |
7233 | (set_attr "length" "4,8")]) | |
7234 | ||
7235 | (define_split | |
7236 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7237 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7238 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7239 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7240 | (const_int 0))) |
9ebbca7d GK |
7241 | (clobber (match_scratch:DI 3 ""))] |
7242 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7243 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7244 | (set (match_dup 0) |
7245 | (compare:CC (match_dup 3) | |
7246 | (const_int 0)))] | |
7247 | "") | |
a473029f | 7248 | |
dfbdccdb | 7249 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7250 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7251 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7252 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7253 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7254 | (const_int 0))) | |
9ebbca7d | 7255 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7256 | (match_dup 4))] |
a473029f | 7257 | "TARGET_POWERPC64" |
9ebbca7d | 7258 | "@ |
1d328b19 | 7259 | %q4. %0,%2,%1 |
9ebbca7d GK |
7260 | #" |
7261 | [(set_attr "type" "compare") | |
7262 | (set_attr "length" "4,8")]) | |
7263 | ||
7264 | (define_split | |
75540af0 | 7265 | [(set (match_operand:CC 3 "cc_reg_operand" "") |
dfbdccdb | 7266 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7267 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7268 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7269 | (const_int 0))) |
75540af0 | 7270 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7271 | (match_dup 4))] |
9ebbca7d | 7272 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7273 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7274 | (set (match_dup 3) |
7275 | (compare:CC (match_dup 0) | |
7276 | (const_int 0)))] | |
7277 | "") | |
266eb58a | 7278 | |
dfbdccdb | 7279 | (define_insn "*boolccdi3_internal1" |
a473029f | 7280 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7281 | (match_operator:DI 3 "boolean_operator" |
7282 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7283 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7284 | "TARGET_POWERPC64" |
dfbdccdb | 7285 | "%q3 %0,%1,%2") |
a473029f | 7286 | |
dfbdccdb | 7287 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7288 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7289 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7290 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7291 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7292 | (const_int 0))) | |
9ebbca7d | 7293 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7294 | "TARGET_POWERPC64" |
9ebbca7d | 7295 | "@ |
dfbdccdb | 7296 | %q4. %3,%1,%2 |
9ebbca7d GK |
7297 | #" |
7298 | [(set_attr "type" "compare") | |
7299 | (set_attr "length" "4,8")]) | |
7300 | ||
7301 | (define_split | |
7302 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7303 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7304 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7305 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7306 | (const_int 0))) |
9ebbca7d GK |
7307 | (clobber (match_scratch:DI 3 ""))] |
7308 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7309 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7310 | (set (match_dup 0) |
7311 | (compare:CC (match_dup 3) | |
7312 | (const_int 0)))] | |
7313 | "") | |
266eb58a | 7314 | |
dfbdccdb | 7315 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7316 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7317 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7318 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7319 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7320 | (const_int 0))) | |
9ebbca7d | 7321 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7322 | (match_dup 4))] |
29ae5b89 | 7323 | "TARGET_POWERPC64" |
9ebbca7d | 7324 | "@ |
dfbdccdb | 7325 | %q4. %0,%1,%2 |
9ebbca7d GK |
7326 | #" |
7327 | [(set_attr "type" "compare") | |
7328 | (set_attr "length" "4,8")]) | |
7329 | ||
7330 | (define_split | |
75540af0 | 7331 | [(set (match_operand:CC 3 "cc_reg_operand" "") |
dfbdccdb | 7332 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7333 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7334 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7335 | (const_int 0))) |
75540af0 | 7336 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7337 | (match_dup 4))] |
9ebbca7d | 7338 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7339 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7340 | (set (match_dup 3) |
7341 | (compare:CC (match_dup 0) | |
7342 | (const_int 0)))] | |
7343 | "") | |
dfbdccdb | 7344 | \f |
1fd4e8c1 | 7345 | ;; Now define ways of moving data around. |
4697a36c MM |
7346 | |
7347 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7348 | ;; The output of this could be r0, but we make a very strong |
7349 | ;; preference for a base register because it will usually | |
7350 | ;; be needed there. | |
4697a36c | 7351 | (define_insn "elf_high" |
9ebbca7d | 7352 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7353 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7354 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7355 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7356 | |
7357 | (define_insn "elf_low" | |
9ebbca7d GK |
7358 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7359 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7360 | (match_operand 2 "" "")))] |
0ad91047 | 7361 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7362 | "@ |
7363 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7364 | {ai|addic} %0,%1,%K2") |
4697a36c | 7365 | |
ee890fe2 SS |
7366 | ;; Mach-O PIC trickery. |
7367 | (define_insn "macho_high" | |
7368 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
7369 | (high:SI (match_operand 1 "" "")))] | |
7370 | "TARGET_MACHO && ! TARGET_64BIT" | |
7371 | "{liu|lis} %0,ha16(%1)") | |
7372 | ||
7373 | (define_insn "macho_low" | |
7374 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
7375 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
7376 | (match_operand 2 "" "")))] | |
7377 | "TARGET_MACHO && ! TARGET_64BIT" | |
7378 | "@ | |
7379 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
7380 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
7381 | ||
766a866c MM |
7382 | ;; Set up a register with a value from the GOT table |
7383 | ||
7384 | (define_expand "movsi_got" | |
52d3af72 | 7385 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d GK |
7386 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
7387 | (match_dup 2)] 8))] | |
58307bcd | 7388 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
7389 | " |
7390 | { | |
38c1f2d7 MM |
7391 | if (GET_CODE (operands[1]) == CONST) |
7392 | { | |
7393 | rtx offset = const0_rtx; | |
7394 | HOST_WIDE_INT value; | |
7395 | ||
7396 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7397 | value = INTVAL (offset); | |
7398 | if (value != 0) | |
7399 | { | |
677a9668 | 7400 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7401 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7402 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7403 | DONE; | |
7404 | } | |
7405 | } | |
7406 | ||
c4c40373 | 7407 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7408 | }") |
7409 | ||
84f414bc | 7410 | (define_insn "*movsi_got_internal" |
52d3af72 | 7411 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7412 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7413 | (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] | |
c81bebd7 | 7414 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
7415 | "{l|lwz} %0,%a1@got(%2)" |
7416 | [(set_attr "type" "load")]) | |
7417 | ||
b22b9b3e JL |
7418 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7419 | ;; didn't get allocated to a hard register. | |
7420 | (define_split | |
75540af0 | 7421 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7422 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
75540af0 | 7423 | (match_operand:SI 2 "memory_operand" "")] 8))] |
b22b9b3e JL |
7424 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
7425 | && flag_pic == 1 | |
7426 | && (reload_in_progress || reload_completed)" | |
7427 | [(set (match_dup 0) (match_dup 2)) | |
9ebbca7d | 7428 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))] |
b22b9b3e JL |
7429 | "") |
7430 | ||
1fd4e8c1 RK |
7431 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7432 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7433 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7434 | ;; integers in the TOC. | |
7435 | (define_expand "movsi" | |
7436 | [(set (match_operand:SI 0 "general_operand" "") | |
7437 | (match_operand:SI 1 "any_operand" ""))] | |
7438 | "" | |
fb4d4348 | 7439 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7440 | |
ee890fe2 SS |
7441 | (define_insn "movsi_low" |
7442 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
7443 | (mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "b") | |
7444 | (match_operand 2 "" ""))))] | |
7445 | "TARGET_MACHO && ! TARGET_64BIT" | |
7446 | "{l|lwz} %0,lo16(%2)(%1)" | |
7447 | [(set_attr "type" "load") | |
7448 | (set_attr "length" "4")]) | |
7449 | ||
acad7ed3 | 7450 | (define_insn "*movsi_internal1" |
a260abc9 | 7451 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h") |
9615f239 | 7452 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))] |
19d5775a RK |
7453 | "gpc_reg_operand (operands[0], SImode) |
7454 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7455 | "@ |
deb9225a | 7456 | mr %0,%1 |
b9442c72 | 7457 | {cal|la} %0,%a1 |
ca7f5001 RK |
7458 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7459 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7460 | {lil|li} %0,%1 |
802a0058 | 7461 | {liu|lis} %0,%v1 |
beaec479 | 7462 | # |
aee86b38 | 7463 | {cal|la} %0,%a1 |
1fd4e8c1 | 7464 | mf%1 %0 |
5c23c401 | 7465 | mt%0 %1 |
e76e75bb RK |
7466 | mt%0 %1 |
7467 | cror 0,0,0" | |
a260abc9 DE |
7468 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*") |
7469 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")]) | |
1fd4e8c1 | 7470 | |
77fa0940 RK |
7471 | ;; Split a load of a large constant into the appropriate two-insn |
7472 | ;; sequence. | |
7473 | ||
7474 | (define_split | |
7475 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7476 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7477 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7478 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7479 | [(set (match_dup 0) | |
7480 | (match_dup 2)) | |
7481 | (set (match_dup 0) | |
7482 | (ior:SI (match_dup 0) | |
7483 | (match_dup 3)))] | |
7484 | " | |
7485 | { | |
5f59ecb7 | 7486 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 7487 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
77fa0940 RK |
7488 | }") |
7489 | ||
acad7ed3 | 7490 | (define_insn "*movsi_internal2" |
9ebbca7d GK |
7491 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
7492 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 7493 | (const_int 0))) |
9ebbca7d | 7494 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
0ad91047 | 7495 | "! TARGET_POWERPC64" |
9ebbca7d GK |
7496 | "@ |
7497 | mr. %0,%1 | |
7498 | #" | |
7499 | [(set_attr "type" "compare") | |
7500 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 7501 | \f |
9ebbca7d GK |
7502 | (define_split |
7503 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7504 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7505 | (const_int 0))) | |
7506 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
7507 | "! TARGET_POWERPC64 && reload_completed" | |
7508 | [(set (match_dup 0) (match_dup 1)) | |
7509 | (set (match_dup 2) | |
7510 | (compare:CC (match_dup 0) | |
7511 | (const_int 0)))] | |
7512 | "") | |
7513 | ||
1fd4e8c1 RK |
7514 | (define_expand "movhi" |
7515 | [(set (match_operand:HI 0 "general_operand" "") | |
7516 | (match_operand:HI 1 "any_operand" ""))] | |
7517 | "" | |
fb4d4348 | 7518 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 RK |
7519 | |
7520 | (define_insn "" | |
fb81d7ce RK |
7521 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7522 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7523 | "gpc_reg_operand (operands[0], HImode) |
7524 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7525 | "@ |
deb9225a | 7526 | mr %0,%1 |
1fd4e8c1 RK |
7527 | lhz%U1%X1 %0,%1 |
7528 | sth%U0%X0 %1,%0 | |
19d5775a | 7529 | {lil|li} %0,%w1 |
1fd4e8c1 | 7530 | mf%1 %0 |
e76e75bb | 7531 | mt%0 %1 |
fb81d7ce | 7532 | mt%0 %1 |
e76e75bb | 7533 | cror 0,0,0" |
b7ff3d82 | 7534 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7535 | |
7536 | (define_expand "movqi" | |
7537 | [(set (match_operand:QI 0 "general_operand" "") | |
7538 | (match_operand:QI 1 "any_operand" ""))] | |
7539 | "" | |
fb4d4348 | 7540 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 RK |
7541 | |
7542 | (define_insn "" | |
fb81d7ce RK |
7543 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7544 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7545 | "gpc_reg_operand (operands[0], QImode) |
7546 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7547 | "@ |
deb9225a | 7548 | mr %0,%1 |
1fd4e8c1 RK |
7549 | lbz%U1%X1 %0,%1 |
7550 | stb%U0%X0 %1,%0 | |
19d5775a | 7551 | {lil|li} %0,%1 |
1fd4e8c1 | 7552 | mf%1 %0 |
e76e75bb | 7553 | mt%0 %1 |
fb81d7ce | 7554 | mt%0 %1 |
e76e75bb | 7555 | cror 0,0,0" |
b7ff3d82 | 7556 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7557 | \f |
7558 | ;; Here is how to move condition codes around. When we store CC data in | |
7559 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7560 | ;; This lets us not shift in the most common case of CR0. | |
7561 | (define_expand "movcc" | |
7562 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7563 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7564 | "" | |
7565 | "") | |
7566 | ||
7567 | (define_insn "" | |
7568 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") | |
7569 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
7570 | "register_operand (operands[0], CCmode) | |
7571 | || register_operand (operands[1], CCmode)" | |
7572 | "@ | |
7573 | mcrf %0,%1 | |
7574 | mtcrf 128,%1 | |
ca7f5001 | 7575 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 7576 | mfcr %0 |
ca7f5001 | 7577 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 7578 | mr %0,%1 |
ca7f5001 RK |
7579 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7580 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b7ff3d82 | 7581 | [(set_attr "type" "*,*,*,compare,*,*,load,store") |
b19003d8 | 7582 | (set_attr "length" "*,*,12,*,8,*,*,*")]) |
1fd4e8c1 | 7583 | \f |
e52e05ca MM |
7584 | ;; For floating-point, we normally deal with the floating-point registers |
7585 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7586 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7587 | ;; value is a simple constant or already in memory, we deal with this by | |
7588 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7589 | (define_expand "movsf" |
7590 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7591 | (match_operand:SF 1 "any_operand" ""))] | |
7592 | "" | |
fb4d4348 | 7593 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7594 | |
1fd4e8c1 | 7595 | (define_split |
cd2b37d9 | 7596 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7597 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7598 | "reload_completed |
5ae4759c MM |
7599 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7600 | || (GET_CODE (operands[0]) == SUBREG | |
7601 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7602 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7603 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7604 | " |
7605 | { | |
7606 | long l; | |
7607 | REAL_VALUE_TYPE rv; | |
7608 | ||
7609 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7610 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7611 | |
f99f88e0 DE |
7612 | if (! TARGET_POWERPC64) |
7613 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7614 | else | |
7615 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7616 | |
38886f37 | 7617 | operands[3] = GEN_INT (trunc_int_for_mode (l, SImode)); |
a260abc9 DE |
7618 | }") |
7619 | ||
c4c40373 | 7620 | (define_insn "*movsf_hardfloat" |
f99f88e0 DE |
7621 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") |
7622 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] | |
d14a6d05 MM |
7623 | "(gpc_reg_operand (operands[0], SFmode) |
7624 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" | |
1fd4e8c1 | 7625 | "@ |
f99f88e0 DE |
7626 | mr %0,%1 |
7627 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7628 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7629 | fmr %0,%1 |
7630 | lfs%U1%X1 %0,%1 | |
c4c40373 MM |
7631 | stfs%U0%X0 %1,%0 |
7632 | # | |
7633 | #" | |
f99f88e0 DE |
7634 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") |
7635 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7636 | |
c4c40373 MM |
7637 | (define_insn "*movsf_softfloat" |
7638 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") | |
9615f239 | 7639 | (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))] |
d14a6d05 MM |
7640 | "(gpc_reg_operand (operands[0], SFmode) |
7641 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" | |
7642 | "@ | |
7643 | mr %0,%1 | |
7644 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7645 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7646 | {lil|li} %0,%1 | |
802a0058 | 7647 | {liu|lis} %0,%v1 |
aee86b38 | 7648 | {cal|la} %0,%a1 |
c4c40373 MM |
7649 | # |
7650 | #" | |
7651 | [(set_attr "type" "*,load,store,*,*,*,*,*") | |
7652 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7653 | |
1fd4e8c1 RK |
7654 | \f |
7655 | (define_expand "movdf" | |
7656 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7657 | (match_operand:DF 1 "any_operand" ""))] | |
7658 | "" | |
fb4d4348 | 7659 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7660 | |
7661 | (define_split | |
cd2b37d9 | 7662 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7663 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7664 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7665 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7666 | || (GET_CODE (operands[0]) == SUBREG | |
7667 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7668 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7669 | [(set (match_dup 2) (match_dup 4)) |
7670 | (set (match_dup 3) (match_dup 1))] | |
7671 | " | |
7672 | { | |
5ae4759c | 7673 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7674 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7675 | ||
5ae4759c MM |
7676 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7677 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7678 | #if HOST_BITS_PER_WIDE_INT == 32 |
7679 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7680 | #else | |
7681 | operands[4] = GEN_INT (value >> 32); | |
7682 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
7683 | #endif | |
c4c40373 MM |
7684 | }") |
7685 | ||
c4c40373 MM |
7686 | (define_split |
7687 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7688 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7689 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7690 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7691 | || (GET_CODE (operands[0]) == SUBREG | |
7692 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7693 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7694 | [(set (match_dup 2) (match_dup 4)) |
7695 | (set (match_dup 3) (match_dup 5))] | |
7696 | " | |
7697 | { | |
5ae4759c | 7698 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7699 | long l[2]; |
7700 | REAL_VALUE_TYPE rv; | |
7701 | ||
7702 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7703 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7704 | ||
5ae4759c MM |
7705 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7706 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
38886f37 AO |
7707 | operands[4] = GEN_INT (trunc_int_for_mode (l[endian], SImode)); |
7708 | operands[5] = GEN_INT (trunc_int_for_mode (l[1 - endian], SImode)); | |
c4c40373 MM |
7709 | }") |
7710 | ||
efc08378 DE |
7711 | (define_split |
7712 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7713 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7714 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7715 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7716 | || (GET_CODE (operands[0]) == SUBREG | |
7717 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7718 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7719 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7720 | " |
a260abc9 DE |
7721 | { |
7722 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7723 | long l[2]; | |
7724 | REAL_VALUE_TYPE rv; | |
7725 | ||
7726 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7727 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7728 | ||
7729 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7730 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
7731 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); | |
7732 | }") | |
efc08378 | 7733 | |
4eae5fe1 | 7734 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7735 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7736 | ;; a non-offsettable memref, but also it is less efficient than loading |
7737 | ;; the constant into an FP register, since it will probably be used there. | |
7738 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7739 | ;; of handling these non-offsettable values. | |
c4c40373 | 7740 | (define_insn "*movdf_hardfloat32" |
000034eb DE |
7741 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
7742 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 7743 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
7744 | && (gpc_reg_operand (operands[0], DFmode) |
7745 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7746 | "* |
7747 | { | |
7748 | switch (which_alternative) | |
7749 | { | |
a260abc9 | 7750 | default: |
a6c2a102 | 7751 | abort (); |
e7113111 RK |
7752 | case 0: |
7753 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
7754 | the first register operand 0 is the same as the second register |
7755 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 7756 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 7757 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 7758 | else |
deb9225a | 7759 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 7760 | case 1: |
2b97222d DE |
7761 | if (offsettable_memref_p (operands[1]) |
7762 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
7763 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
7764 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
7765 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
7766 | { |
7767 | /* If the low-address word is used in the address, we must load | |
7768 | it last. Otherwise, load it first. Note that we cannot have | |
7769 | auto-increment in that case since the address register is | |
7770 | known to be dead. */ | |
7771 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7772 | operands[1], 0)) | |
7773 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
7774 | else | |
7775 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7776 | } | |
e7113111 | 7777 | else |
000034eb DE |
7778 | { |
7779 | rtx addreg; | |
7780 | ||
000034eb DE |
7781 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
7782 | if (refers_to_regno_p (REGNO (operands[0]), | |
7783 | REGNO (operands[0]) + 1, | |
7784 | operands[1], 0)) | |
7785 | { | |
7786 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 7787 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 7788 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 7789 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
7790 | } |
7791 | else | |
7792 | { | |
2b97222d | 7793 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 7794 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7795 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
7796 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7797 | return \"\"; | |
7798 | } | |
7799 | } | |
e7113111 | 7800 | case 2: |
2b97222d DE |
7801 | if (offsettable_memref_p (operands[0]) |
7802 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
7803 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
7804 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
7805 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
7806 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
7807 | else | |
7808 | { | |
7809 | rtx addreg; | |
7810 | ||
000034eb | 7811 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 7812 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 7813 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7814 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
7815 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7816 | return \"\"; | |
7817 | } | |
e7113111 | 7818 | case 3: |
e7113111 | 7819 | case 4: |
e7113111 | 7820 | case 5: |
c4c40373 | 7821 | return \"#\"; |
e7113111 | 7822 | case 6: |
c4c40373 MM |
7823 | return \"fmr %0,%1\"; |
7824 | case 7: | |
7825 | return \"lfd%U1%X1 %0,%1\"; | |
7826 | case 8: | |
e7113111 RK |
7827 | return \"stfd%U0%X0 %1,%0\"; |
7828 | } | |
7829 | }" | |
c4c40373 | 7830 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
2f76d42c | 7831 | (set_attr "length" "8,16,16,8,12,16,*,*,*")]) |
51b8fc2c | 7832 | |
c4c40373 | 7833 | (define_insn "*movdf_softfloat32" |
1427100a DE |
7834 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7835 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 7836 | "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
7837 | && (gpc_reg_operand (operands[0], DFmode) |
7838 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7839 | "* |
7840 | { | |
7841 | switch (which_alternative) | |
7842 | { | |
a260abc9 | 7843 | default: |
a6c2a102 | 7844 | abort (); |
dc4f83ca MM |
7845 | case 0: |
7846 | /* We normally copy the low-numbered register first. However, if | |
7847 | the first register operand 0 is the same as the second register of | |
7848 | operand 1, we must copy in the opposite order. */ | |
7849 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
7850 | return \"mr %L0,%L1\;mr %0,%1\"; | |
7851 | else | |
7852 | return \"mr %0,%1\;mr %L0,%L1\"; | |
7853 | case 1: | |
3cb999d8 DE |
7854 | /* If the low-address word is used in the address, we must load |
7855 | it last. Otherwise, load it first. Note that we cannot have | |
7856 | auto-increment in that case since the address register is | |
7857 | known to be dead. */ | |
dc4f83ca | 7858 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 7859 | operands[1], 0)) |
dc4f83ca MM |
7860 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
7861 | else | |
7862 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7863 | case 2: | |
7864 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
7865 | case 3: | |
c4c40373 MM |
7866 | case 4: |
7867 | case 5: | |
dc4f83ca MM |
7868 | return \"#\"; |
7869 | } | |
7870 | }" | |
c4c40373 MM |
7871 | [(set_attr "type" "*,load,store,*,*,*") |
7872 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 7873 | |
c4c40373 | 7874 | (define_insn "*movdf_hardfloat64" |
1427100a DE |
7875 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
7876 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 7877 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
7878 | && (gpc_reg_operand (operands[0], DFmode) |
7879 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 7880 | "@ |
3d5570cb RK |
7881 | mr %0,%1 |
7882 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 7883 | std%U0%X0 %1,%0 |
3d5570cb | 7884 | # |
c4c40373 MM |
7885 | # |
7886 | # | |
3d5570cb | 7887 | fmr %0,%1 |
f63184ac | 7888 | lfd%U1%X1 %0,%1 |
3d5570cb | 7889 | stfd%U0%X0 %1,%0" |
c4c40373 MM |
7890 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
7891 | (set_attr "length" "4,4,4,8,12,16,4,4,4")]) | |
dc4f83ca | 7892 | |
c4c40373 | 7893 | (define_insn "*movdf_softfloat64" |
1427100a DE |
7894 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7895 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 7896 | "TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
7897 | && (gpc_reg_operand (operands[0], DFmode) |
7898 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7899 | "@ |
7900 | mr %0,%1 | |
7901 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 7902 | std%U0%X0 %1,%0 |
c4c40373 MM |
7903 | # |
7904 | # | |
dc4f83ca | 7905 | #" |
c4c40373 MM |
7906 | [(set_attr "type" "*,load,store,*,*,*") |
7907 | (set_attr "length" "*,*,*,8,12,16")]) | |
1fd4e8c1 RK |
7908 | \f |
7909 | ;; Next come the multi-word integer load and store and the load and store | |
7910 | ;; multiple insns. | |
7911 | (define_expand "movdi" | |
7912 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 7913 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 7914 | "" |
fb4d4348 | 7915 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 7916 | |
acad7ed3 | 7917 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
7918 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
7919 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 7920 | "! TARGET_POWERPC64 |
4e74d8ec MM |
7921 | && (gpc_reg_operand (operands[0], DImode) |
7922 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
7923 | "* |
7924 | { | |
7925 | switch (which_alternative) | |
7926 | { | |
a260abc9 | 7927 | default: |
a6c2a102 | 7928 | abort (); |
1fd4e8c1 RK |
7929 | case 0: |
7930 | /* We normally copy the low-numbered register first. However, if | |
7931 | the first register operand 0 is the same as the second register of | |
7932 | operand 1, we must copy in the opposite order. */ | |
7933 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 7934 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 7935 | else |
deb9225a | 7936 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
7937 | case 1: |
7938 | /* If the low-address word is used in the address, we must load it | |
7939 | last. Otherwise, load it first. Note that we cannot have | |
7940 | auto-increment in that case since the address register is known to be | |
7941 | dead. */ | |
7942 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 7943 | operands[1], 0)) |
ca7f5001 | 7944 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 7945 | else |
ca7f5001 | 7946 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 7947 | case 2: |
ca7f5001 | 7948 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
7949 | case 3: |
7950 | return \"fmr %0,%1\"; | |
7951 | case 4: | |
7952 | return \"lfd%U1%X1 %0,%1\"; | |
7953 | case 5: | |
7954 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
7955 | case 6: |
7956 | case 7: | |
7957 | case 8: | |
7958 | case 9: | |
7959 | case 10: | |
7960 | return \"#\"; | |
1fd4e8c1 RK |
7961 | } |
7962 | }" | |
4e74d8ec MM |
7963 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
7964 | (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) | |
7965 | ||
7966 | (define_split | |
7967 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7968 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 7969 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
7970 | [(set (match_dup 2) (match_dup 4)) |
7971 | (set (match_dup 3) (match_dup 1))] | |
7972 | " | |
7973 | { | |
5f59ecb7 | 7974 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
7975 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
7976 | DImode); | |
7977 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
7978 | DImode); | |
75d39459 | 7979 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 7980 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 7981 | #else |
5f59ecb7 DE |
7982 | operands[4] = GEN_INT (value >> 32); |
7983 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
75d39459 | 7984 | #endif |
4e74d8ec MM |
7985 | }") |
7986 | ||
4e74d8ec MM |
7987 | (define_split |
7988 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7989 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 7990 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
7991 | [(set (match_dup 2) (match_dup 4)) |
7992 | (set (match_dup 3) (match_dup 5))] | |
7993 | " | |
7994 | { | |
bdaa0181 GK |
7995 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
7996 | DImode); | |
7997 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
7998 | DImode); | |
f6968f59 MM |
7999 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
8000 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
8001 | }") |
8002 | ||
acad7ed3 | 8003 | (define_insn "*movdi_internal64" |
e6ca2c17 | 8004 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") |
9615f239 | 8005 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8006 | "TARGET_POWERPC64 |
4e74d8ec MM |
8007 | && (gpc_reg_operand (operands[0], DImode) |
8008 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8009 | "@ |
3d5570cb RK |
8010 | mr %0,%1 |
8011 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8012 | std%U0%X0 %1,%0 |
3d5570cb | 8013 | li %0,%1 |
802a0058 | 8014 | lis %0,%v1 |
e6ca2c17 | 8015 | # |
aee86b38 | 8016 | {cal|la} %0,%a1 |
3d5570cb RK |
8017 | fmr %0,%1 |
8018 | lfd%U1%X1 %0,%1 | |
8019 | stfd%U0%X0 %1,%0 | |
8020 | mf%1 %0 | |
08075ead DE |
8021 | mt%0 %1 |
8022 | cror 0,0,0" | |
b7ff3d82 | 8023 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
8024 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8025 | ||
5f59ecb7 | 8026 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8027 | (define_insn "" |
8028 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8029 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8030 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8031 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8032 | && num_insns_constant (operands[1], DImode) == 1" |
8033 | "* | |
8034 | { | |
8035 | return ((unsigned HOST_WIDE_INT) | |
8036 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8037 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8038 | }") | |
8039 | ||
a260abc9 DE |
8040 | ;; Generate all one-bits and clear left or right. |
8041 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8042 | (define_split | |
8043 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8044 | (match_operand:DI 1 "mask64_operand" ""))] | |
8045 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8046 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8047 | (set (match_dup 0) |
a260abc9 DE |
8048 | (and:DI (rotate:DI (match_dup 0) |
8049 | (const_int 0)) | |
8050 | (match_dup 1)))] | |
8051 | "") | |
8052 | ||
8053 | ;; Split a load of a large constant into the appropriate five-instruction | |
8054 | ;; sequence. Handle anything in a constant number of insns. | |
8055 | ;; When non-easy constants can go in the TOC, this should use | |
8056 | ;; easy_fp_constant predicate. | |
8057 | (define_split | |
8058 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8059 | (match_operand:DI 1 "const_int_operand" ""))] |
8060 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8061 | [(set (match_dup 0) (match_dup 2)) | |
8062 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8063 | " |
2bfcf297 DB |
8064 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8065 | ||
8066 | if (tem == operands[0]) | |
8067 | DONE; | |
e8d791dd | 8068 | else |
2bfcf297 | 8069 | FAIL; |
5f59ecb7 | 8070 | }") |
e6ca2c17 | 8071 | |
5f59ecb7 DE |
8072 | (define_split |
8073 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8074 | (match_operand:DI 1 "const_double_operand" ""))] |
8075 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8076 | [(set (match_dup 0) (match_dup 2)) | |
8077 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8078 | " |
2bfcf297 DB |
8079 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8080 | ||
8081 | if (tem == operands[0]) | |
8082 | DONE; | |
8083 | else | |
8084 | FAIL; | |
e6ca2c17 | 8085 | }") |
08075ead | 8086 | |
2bfcf297 | 8087 | ;; Split a load of a large constant into the appropriate five-instruction |
acad7ed3 | 8088 | (define_insn "*movdi_internal2" |
9ebbca7d GK |
8089 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
8090 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
08075ead | 8091 | (const_int 0))) |
9ebbca7d | 8092 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
08075ead | 8093 | "TARGET_POWERPC64" |
9ebbca7d GK |
8094 | "@ |
8095 | mr. %0,%1 | |
8096 | #" | |
8097 | [(set_attr "type" "compare") | |
8098 | (set_attr "length" "4,8")]) | |
acad7ed3 | 8099 | |
9ebbca7d GK |
8100 | (define_split |
8101 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8102 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8103 | (const_int 0))) | |
8104 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8105 | "TARGET_POWERPC64 && reload_completed" | |
8106 | [(set (match_dup 0) (match_dup 1)) | |
8107 | (set (match_dup 2) | |
8108 | (compare:CC (match_dup 0) | |
8109 | (const_int 0)))] | |
8110 | "") | |
acad7ed3 | 8111 | \f |
1fd4e8c1 RK |
8112 | ;; TImode is similar, except that we usually want to compute the address into |
8113 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8114 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8115 | (define_expand "movti" |
8116 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8117 | (match_operand:TI 1 "general_operand" "")) | |
8118 | (clobber (scratch:SI))])] | |
7e69e155 | 8119 | "TARGET_STRING || TARGET_POWERPC64" |
fb4d4348 | 8120 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8121 | |
8122 | ;; We say that MQ is clobbered in the last alternative because the first | |
8123 | ;; alternative would never get used otherwise since it would need a reload | |
8124 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8125 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8126 | ;; giving the SCRATCH mq. | |
a260abc9 | 8127 | (define_insn "*movti_power" |
e1469d0d | 8128 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8129 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8130 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 8131 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8132 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8133 | "* |
8134 | { | |
8135 | switch (which_alternative) | |
8136 | { | |
dc4f83ca MM |
8137 | default: |
8138 | abort (); | |
8139 | ||
1fd4e8c1 | 8140 | case 0: |
ca7f5001 | 8141 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
8142 | |
8143 | case 1: | |
ca7f5001 | 8144 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
8145 | |
8146 | case 2: | |
8147 | /* Normally copy registers with lowest numbered register copied first. | |
8148 | But copy in the other order if the first register of the output | |
8149 | is the second, third, or fourth register in the input. */ | |
8150 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8151 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 8152 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8153 | else |
deb9225a | 8154 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
8155 | case 3: |
8156 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8157 | fall through to generating four loads. */ | |
8158 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8159 | return \"{lsi|lswi} %0,%P1,16\"; |
1fd4e8c1 RK |
8160 | /* ... fall through ... */ |
8161 | case 4: | |
8162 | /* If the address register is the same as the register for the lowest- | |
8163 | addressed word, load it last. Similarly for the next two words. | |
8164 | Otherwise load lowest address to highest. */ | |
8165 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8166 | operands[1], 0)) | |
ca7f5001 | 8167 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
8168 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
8169 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 8170 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
8171 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
8172 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 8173 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 8174 | else |
ca7f5001 | 8175 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
8176 | } |
8177 | }" | |
b7ff3d82 | 8178 | [(set_attr "type" "store,store,*,load,load") |
b19003d8 | 8179 | (set_attr "length" "*,16,16,*,16")]) |
51b8fc2c | 8180 | |
a260abc9 | 8181 | (define_insn "*movti_string" |
dc4f83ca MM |
8182 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") |
8183 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) | |
8184 | (clobber (match_scratch:SI 2 "=X,X,X"))] | |
0ad91047 | 8185 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8186 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8187 | "* | |
8188 | { | |
8189 | switch (which_alternative) | |
8190 | { | |
8191 | default: | |
8192 | abort (); | |
8193 | ||
8194 | case 0: | |
8195 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; | |
8196 | ||
8197 | case 1: | |
8198 | /* Normally copy registers with lowest numbered register copied first. | |
8199 | But copy in the other order if the first register of the output | |
8200 | is the second, third, or fourth register in the input. */ | |
8201 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8202 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
8203 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
8204 | else | |
8205 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
8206 | case 2: | |
8207 | /* If the address register is the same as the register for the lowest- | |
8208 | addressed word, load it last. Similarly for the next two words. | |
8209 | Otherwise load lowest address to highest. */ | |
8210 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8211 | operands[1], 0)) | |
8212 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
8213 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
8214 | REGNO (operands[0]) + 2, operands[1], 0)) | |
8215 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
8216 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
8217 | REGNO (operands[0]) + 3, operands[1], 0)) | |
8218 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
8219 | else | |
8220 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
8221 | } | |
8222 | }" | |
b7ff3d82 | 8223 | [(set_attr "type" "store,*,load") |
dc4f83ca MM |
8224 | (set_attr "length" "16,16,16")]) |
8225 | ||
a260abc9 | 8226 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
8227 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
8228 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
8229 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
8230 | || gpc_reg_operand (operands[1], TImode))" | |
8231 | "* | |
8232 | { | |
8233 | switch (which_alternative) | |
8234 | { | |
a260abc9 | 8235 | default: |
a6c2a102 | 8236 | abort (); |
51b8fc2c RK |
8237 | case 0: |
8238 | /* We normally copy the low-numbered register first. However, if | |
8239 | the first register operand 0 is the same as the second register of | |
8240 | operand 1, we must copy in the opposite order. */ | |
8241 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8242 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8243 | else | |
8244 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8245 | case 1: | |
8246 | /* If the low-address word is used in the address, we must load it | |
8247 | last. Otherwise, load it first. Note that we cannot have | |
8248 | auto-increment in that case since the address register is known to be | |
8249 | dead. */ | |
8250 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8251 | operands[1], 0)) |
51b8fc2c RK |
8252 | return \"ld %L0,%L1\;ld %0,%1\"; |
8253 | else | |
8254 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
8255 | case 2: | |
8256 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
8257 | } | |
8258 | }" | |
b7ff3d82 | 8259 | [(set_attr "type" "*,load,store") |
51b8fc2c | 8260 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
8261 | \f |
8262 | (define_expand "load_multiple" | |
2f622005 RK |
8263 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8264 | (match_operand:SI 1 "" "")) | |
8265 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 8266 | "TARGET_STRING" |
1fd4e8c1 RK |
8267 | " |
8268 | { | |
8269 | int regno; | |
8270 | int count; | |
792760b9 | 8271 | rtx op1; |
1fd4e8c1 RK |
8272 | int i; |
8273 | ||
8274 | /* Support only loading a constant number of fixed-point registers from | |
8275 | memory and only bother with this if more than two; the machine | |
8276 | doesn't support more than eight. */ | |
8277 | if (GET_CODE (operands[2]) != CONST_INT | |
8278 | || INTVAL (operands[2]) <= 2 | |
8279 | || INTVAL (operands[2]) > 8 | |
8280 | || GET_CODE (operands[1]) != MEM | |
8281 | || GET_CODE (operands[0]) != REG | |
8282 | || REGNO (operands[0]) >= 32) | |
8283 | FAIL; | |
8284 | ||
8285 | count = INTVAL (operands[2]); | |
8286 | regno = REGNO (operands[0]); | |
8287 | ||
39403d82 | 8288 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8289 | op1 = replace_equiv_address (operands[1], |
8290 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8291 | |
8292 | for (i = 0; i < count; i++) | |
8293 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8294 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
792760b9 | 8295 | adjust_address (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8296 | }") |
8297 | ||
8298 | (define_insn "" | |
8299 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 8300 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
52d3af72 | 8301 | (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] |
7e69e155 | 8302 | "TARGET_STRING" |
1fd4e8c1 RK |
8303 | "* |
8304 | { | |
8305 | /* We have to handle the case where the pseudo used to contain the address | |
e82ee4cc RK |
8306 | is assigned to one of the output registers. */ |
8307 | int i, j; | |
8308 | int words = XVECLEN (operands[0], 0); | |
8309 | rtx xop[10]; | |
8310 | ||
8311 | if (XVECLEN (operands[0], 0) == 1) | |
8312 | return \"{l|lwz} %1,0(%2)\"; | |
1fd4e8c1 | 8313 | |
e82ee4cc | 8314 | for (i = 0; i < words; i++) |
1fd4e8c1 RK |
8315 | if (refers_to_regno_p (REGNO (operands[1]) + i, |
8316 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
8317 | { | |
e82ee4cc RK |
8318 | if (i == words-1) |
8319 | { | |
8320 | xop[0] = operands[1]; | |
8321 | xop[1] = operands[2]; | |
8322 | xop[2] = GEN_INT (4 * (words-1)); | |
d89ddcfd | 8323 | output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); |
e82ee4cc RK |
8324 | return \"\"; |
8325 | } | |
8326 | else if (i == 0) | |
8327 | { | |
8328 | xop[0] = operands[1]; | |
39403d82 | 8329 | xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
e82ee4cc RK |
8330 | xop[2] = GEN_INT (4 * (words-1)); |
8331 | output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); | |
8332 | return \"\"; | |
8333 | } | |
8334 | else | |
8335 | { | |
8336 | for (j = 0; j < words; j++) | |
8337 | if (j != i) | |
8338 | { | |
39403d82 | 8339 | xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); |
e82ee4cc RK |
8340 | xop[1] = operands[2]; |
8341 | xop[2] = GEN_INT (j * 4); | |
8342 | output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); | |
8343 | } | |
8344 | xop[0] = operands[2]; | |
8345 | xop[1] = GEN_INT (i * 4); | |
8346 | output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); | |
8347 | return \"\"; | |
8348 | } | |
1fd4e8c1 RK |
8349 | } |
8350 | ||
e82ee4cc | 8351 | return \"{lsi|lswi} %1,%2,%N0\"; |
1fd4e8c1 | 8352 | }" |
b19003d8 | 8353 | [(set_attr "type" "load") |
e82ee4cc | 8354 | (set_attr "length" "32")]) |
b19003d8 | 8355 | |
b7ff3d82 | 8356 | \f |
1fd4e8c1 | 8357 | (define_expand "store_multiple" |
2f622005 RK |
8358 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8359 | (match_operand:SI 1 "" "")) | |
8360 | (clobber (scratch:SI)) | |
8361 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 8362 | "TARGET_STRING" |
1fd4e8c1 RK |
8363 | " |
8364 | { | |
8365 | int regno; | |
8366 | int count; | |
8367 | rtx to; | |
792760b9 | 8368 | rtx op0; |
1fd4e8c1 RK |
8369 | int i; |
8370 | ||
8371 | /* Support only storing a constant number of fixed-point registers to | |
8372 | memory and only bother with this if more than two; the machine | |
8373 | doesn't support more than eight. */ | |
8374 | if (GET_CODE (operands[2]) != CONST_INT | |
8375 | || INTVAL (operands[2]) <= 2 | |
8376 | || INTVAL (operands[2]) > 8 | |
8377 | || GET_CODE (operands[0]) != MEM | |
8378 | || GET_CODE (operands[1]) != REG | |
8379 | || REGNO (operands[1]) >= 32) | |
8380 | FAIL; | |
8381 | ||
8382 | count = INTVAL (operands[2]); | |
8383 | regno = REGNO (operands[1]); | |
8384 | ||
39403d82 | 8385 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8386 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8387 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8388 | |
8389 | XVECEXP (operands[3], 0, 0) | |
68350f4f | 8390 | = gen_rtx_SET (VOIDmode, adjust_address (op0, SImode, 0), operands[1]); |
39403d82 | 8391 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8392 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8393 | |
8394 | for (i = 1; i < count; i++) | |
8395 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8396 | = gen_rtx_SET (VOIDmode, |
792760b9 | 8397 | adjust_address (op0, SImode, i * 4), |
c5c76735 | 8398 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8399 | }") |
8400 | ||
8401 | (define_insn "" | |
8402 | [(match_parallel 0 "store_multiple_operation" | |
8403 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8404 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8405 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8406 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8407 | "{stsi|stswi} %2,%P1,%O0" |
8408 | [(set_attr "type" "store")]) | |
d14a6d05 MM |
8409 | |
8410 | (define_insn "" | |
8411 | [(match_parallel 0 "store_multiple_operation" | |
52d3af72 | 8412 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
d14a6d05 MM |
8413 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
8414 | (clobber (match_scratch:SI 3 "X"))])] | |
0ad91047 | 8415 | "TARGET_STRING && ! TARGET_POWER" |
b7ff3d82 DE |
8416 | "{stsi|stswi} %2,%1,%O0" |
8417 | [(set_attr "type" "store")]) | |
7e69e155 MM |
8418 | |
8419 | \f | |
8420 | ;; String/block move insn. | |
8421 | ;; Argument 0 is the destination | |
8422 | ;; Argument 1 is the source | |
8423 | ;; Argument 2 is the length | |
8424 | ;; Argument 3 is the alignment | |
8425 | ||
8426 | (define_expand "movstrsi" | |
b6c9286a MM |
8427 | [(parallel [(set (match_operand:BLK 0 "" "") |
8428 | (match_operand:BLK 1 "" "")) | |
8429 | (use (match_operand:SI 2 "" "")) | |
8430 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
8431 | "" |
8432 | " | |
8433 | { | |
8434 | if (expand_block_move (operands)) | |
8435 | DONE; | |
8436 | else | |
8437 | FAIL; | |
8438 | }") | |
8439 | ||
8440 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8441 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
8442 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8443 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
8444 | [(parallel [(set (match_operand 0 "" "") |
8445 | (match_operand 1 "" "")) | |
8446 | (use (match_operand 2 "" "")) | |
8447 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
8448 | (clobber (reg:SI 5)) |
8449 | (clobber (reg:SI 6)) | |
8450 | (clobber (reg:SI 7)) | |
8451 | (clobber (reg:SI 8)) | |
8452 | (clobber (reg:SI 9)) | |
8453 | (clobber (reg:SI 10)) | |
8454 | (clobber (reg:SI 11)) | |
8455 | (clobber (reg:SI 12)) | |
3c67b673 | 8456 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8457 | "TARGET_STRING" |
8458 | "") | |
8459 | ||
8460 | (define_insn "" | |
52d3af72 DE |
8461 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8462 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8463 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8464 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8465 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8466 | (clobber (reg:SI 6)) |
8467 | (clobber (reg:SI 7)) | |
8468 | (clobber (reg:SI 8)) | |
8469 | (clobber (reg:SI 9)) | |
8470 | (clobber (reg:SI 10)) | |
8471 | (clobber (reg:SI 11)) | |
8472 | (clobber (reg:SI 12)) | |
3c67b673 | 8473 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 8474 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
8475 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8476 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8477 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8478 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8479 | && REGNO (operands[4]) == 5" |
8480 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8481 | [(set_attr "type" "load") |
8482 | (set_attr "length" "8")]) | |
7e69e155 MM |
8483 | |
8484 | (define_insn "" | |
52d3af72 DE |
8485 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8486 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8487 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8488 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8489 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8490 | (clobber (reg:SI 6)) |
8491 | (clobber (reg:SI 7)) | |
8492 | (clobber (reg:SI 8)) | |
8493 | (clobber (reg:SI 9)) | |
8494 | (clobber (reg:SI 10)) | |
8495 | (clobber (reg:SI 11)) | |
8496 | (clobber (reg:SI 12)) | |
3c67b673 | 8497 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8498 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
8499 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8500 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8501 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8502 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8503 | && REGNO (operands[4]) == 5" |
8504 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8505 | [(set_attr "type" "load") |
8506 | (set_attr "length" "8")]) | |
7e69e155 MM |
8507 | |
8508 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8509 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
8510 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8511 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
8512 | [(parallel [(set (match_operand 0 "" "") |
8513 | (match_operand 1 "" "")) | |
8514 | (use (match_operand 2 "" "")) | |
8515 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8516 | (clobber (reg:SI 5)) |
8517 | (clobber (reg:SI 6)) | |
7e69e155 MM |
8518 | (clobber (reg:SI 7)) |
8519 | (clobber (reg:SI 8)) | |
8520 | (clobber (reg:SI 9)) | |
8521 | (clobber (reg:SI 10)) | |
3c67b673 | 8522 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8523 | "TARGET_STRING" |
8524 | "") | |
8525 | ||
8526 | (define_insn "" | |
52d3af72 DE |
8527 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8528 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8529 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8530 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8531 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8532 | (clobber (reg:SI 6)) |
8533 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8534 | (clobber (reg:SI 8)) |
8535 | (clobber (reg:SI 9)) | |
8536 | (clobber (reg:SI 10)) | |
3c67b673 | 8537 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8538 | "TARGET_STRING && TARGET_POWER |
8539 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
8540 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8541 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8542 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8543 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8544 | [(set_attr "type" "load") |
8545 | (set_attr "length" "8")]) | |
7e69e155 MM |
8546 | |
8547 | (define_insn "" | |
52d3af72 DE |
8548 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8549 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8550 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8551 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8552 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8553 | (clobber (reg:SI 6)) |
8554 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8555 | (clobber (reg:SI 8)) |
8556 | (clobber (reg:SI 9)) | |
8557 | (clobber (reg:SI 10)) | |
3c67b673 | 8558 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8559 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8560 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
8561 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8562 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8563 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8564 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8565 | [(set_attr "type" "load") |
8566 | (set_attr "length" "8")]) | |
7e69e155 | 8567 | |
f9562f27 DE |
8568 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
8569 | ;; problems with TImode. | |
8570 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8571 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
8572 | [(parallel [(set (match_operand 0 "" "") |
8573 | (match_operand 1 "" "")) | |
8574 | (use (match_operand 2 "" "")) | |
8575 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8576 | (clobber (reg:SI 5)) |
8577 | (clobber (reg:SI 6)) | |
8578 | (clobber (reg:SI 7)) | |
8579 | (clobber (reg:SI 8)) | |
3c67b673 | 8580 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8581 | "TARGET_STRING" |
8582 | "") | |
8583 | ||
8584 | (define_insn "" | |
52d3af72 DE |
8585 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8586 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8587 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8588 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8589 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8590 | (clobber (reg:SI 6)) |
8591 | (clobber (reg:SI 7)) | |
8592 | (clobber (reg:SI 8)) | |
3c67b673 | 8593 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8594 | "TARGET_STRING && TARGET_POWER |
8595 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
8596 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8597 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8598 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8599 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8600 | [(set_attr "type" "load") |
8601 | (set_attr "length" "8")]) | |
7e69e155 MM |
8602 | |
8603 | (define_insn "" | |
52d3af72 DE |
8604 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8605 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8606 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8607 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8608 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8609 | (clobber (reg:SI 6)) |
8610 | (clobber (reg:SI 7)) | |
8611 | (clobber (reg:SI 8)) | |
3c67b673 | 8612 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8613 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8614 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
8615 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8616 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8617 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8618 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8619 | [(set_attr "type" "load") |
8620 | (set_attr "length" "8")]) | |
7e69e155 MM |
8621 | |
8622 | ;; Move up to 8 bytes at a time. | |
8623 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
8624 | [(parallel [(set (match_operand 0 "" "") |
8625 | (match_operand 1 "" "")) | |
8626 | (use (match_operand 2 "" "")) | |
8627 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8628 | (clobber (match_scratch:DI 4 "")) |
8629 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 8630 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
8631 | "") |
8632 | ||
8633 | (define_insn "" | |
52d3af72 DE |
8634 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8635 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8636 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8637 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8638 | (clobber (match_scratch:DI 4 "=&r")) | |
8639 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 8640 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
8641 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
8642 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8643 | [(set_attr "type" "load") |
8644 | (set_attr "length" "8")]) | |
7e69e155 MM |
8645 | |
8646 | (define_insn "" | |
52d3af72 DE |
8647 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8648 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8649 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8650 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8651 | (clobber (match_scratch:DI 4 "=&r")) | |
8652 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 8653 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 8654 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 8655 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8656 | [(set_attr "type" "load") |
8657 | (set_attr "length" "8")]) | |
7e69e155 MM |
8658 | |
8659 | ;; Move up to 4 bytes at a time. | |
8660 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
8661 | [(parallel [(set (match_operand 0 "" "") |
8662 | (match_operand 1 "" "")) | |
8663 | (use (match_operand 2 "" "")) | |
8664 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8665 | (clobber (match_scratch:SI 4 "")) |
8666 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
8667 | "TARGET_STRING" |
8668 | "") | |
8669 | ||
8670 | (define_insn "" | |
52d3af72 DE |
8671 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8672 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8673 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8674 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8675 | (clobber (match_scratch:SI 4 "=&r")) | |
8676 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
8677 | "TARGET_STRING && TARGET_POWER |
8678 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 8679 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8680 | [(set_attr "type" "load") |
8681 | (set_attr "length" "8")]) | |
7e69e155 MM |
8682 | |
8683 | (define_insn "" | |
52d3af72 DE |
8684 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8685 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8686 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8687 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8688 | (clobber (match_scratch:SI 4 "=&r")) | |
8689 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 8690 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8691 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
3c67b673 | 8692 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8693 | [(set_attr "type" "load") |
8694 | (set_attr "length" "8")]) | |
7e69e155 | 8695 | |
1fd4e8c1 | 8696 | \f |
7e69e155 | 8697 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
8698 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
8699 | ;; do cases where the increment is not the size of the object. | |
8700 | ;; | |
8701 | ;; In all these cases, we use operands 0 and 1 for the register being | |
8702 | ;; incremented because those are the operands that local-alloc will | |
8703 | ;; tie and these are the pair most likely to be tieable (and the ones | |
8704 | ;; that will benefit the most). | |
8705 | ||
38c1f2d7 | 8706 | (define_insn "*movdi_update1" |
51b8fc2c | 8707 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 8708 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
51b8fc2c RK |
8709 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))) |
8710 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
8711 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8712 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8713 | "@ |
8714 | ldux %3,%0,%2 | |
8715 | ldu %3,%2(%0)" | |
8716 | [(set_attr "type" "load")]) | |
8717 | ||
38c1f2d7 | 8718 | (define_insn "*movdi_update2" |
287f13ff RK |
8719 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
8720 | (sign_extend:DI | |
8721 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
8722 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
8723 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
8724 | (plus:DI (match_dup 1) (match_dup 2)))] | |
8725 | "TARGET_POWERPC64" | |
8726 | "lwaux %3,%0,%2" | |
8727 | [(set_attr "type" "load")]) | |
8728 | ||
4697a36c | 8729 | (define_insn "movdi_update" |
51b8fc2c RK |
8730 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
8731 | (match_operand:DI 2 "reg_or_short_operand" "r,I"))) | |
8732 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) | |
8733 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
8734 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8735 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8736 | "@ |
8737 | stdux %3,%0,%2 | |
b7ff3d82 DE |
8738 | stdu %3,%2(%0)" |
8739 | [(set_attr "type" "store")]) | |
51b8fc2c | 8740 | |
38c1f2d7 | 8741 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
8742 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
8743 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8744 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8745 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
8746 | (plus:SI (match_dup 1) (match_dup 2)))] |
8747 | "" | |
8748 | "@ | |
ca7f5001 RK |
8749 | {lux|lwzux} %3,%0,%2 |
8750 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 8751 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8752 | |
4697a36c | 8753 | (define_insn "movsi_update" |
cd2b37d9 | 8754 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8755 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8756 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
8757 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8758 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8759 | "TARGET_UPDATE" |
1fd4e8c1 | 8760 | "@ |
ca7f5001 | 8761 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
8762 | {stu|stwu} %3,%2(%0)" |
8763 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8764 | |
38c1f2d7 | 8765 | (define_insn "*movhi_update" |
cd2b37d9 RK |
8766 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
8767 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8768 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8769 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8770 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8771 | "TARGET_UPDATE" |
1fd4e8c1 | 8772 | "@ |
5f243543 RK |
8773 | lhzux %3,%0,%2 |
8774 | lhzu %3,%2(%0)" | |
cfb557c4 | 8775 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8776 | |
38c1f2d7 | 8777 | (define_insn "*movhi_update2" |
cd2b37d9 | 8778 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8779 | (zero_extend:SI |
cd2b37d9 | 8780 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8781 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8782 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8783 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8784 | "TARGET_UPDATE" |
1fd4e8c1 | 8785 | "@ |
5f243543 RK |
8786 | lhzux %3,%0,%2 |
8787 | lhzu %3,%2(%0)" | |
cfb557c4 | 8788 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8789 | |
38c1f2d7 | 8790 | (define_insn "*movhi_update3" |
cd2b37d9 | 8791 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8792 | (sign_extend:SI |
cd2b37d9 | 8793 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8794 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8795 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8796 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8797 | "TARGET_UPDATE" |
1fd4e8c1 | 8798 | "@ |
5f243543 RK |
8799 | lhaux %3,%0,%2 |
8800 | lhau %3,%2(%0)" | |
cfb557c4 | 8801 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8802 | |
38c1f2d7 | 8803 | (define_insn "*movhi_update4" |
cd2b37d9 | 8804 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8805 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8806 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
8807 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8808 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8809 | "TARGET_UPDATE" |
1fd4e8c1 | 8810 | "@ |
5f243543 | 8811 | sthux %3,%0,%2 |
b7ff3d82 DE |
8812 | sthu %3,%2(%0)" |
8813 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8814 | |
38c1f2d7 | 8815 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
8816 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
8817 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8818 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8819 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8820 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8821 | "TARGET_UPDATE" |
1fd4e8c1 | 8822 | "@ |
5f243543 RK |
8823 | lbzux %3,%0,%2 |
8824 | lbzu %3,%2(%0)" | |
cfb557c4 | 8825 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8826 | |
38c1f2d7 | 8827 | (define_insn "*movqi_update2" |
cd2b37d9 | 8828 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8829 | (zero_extend:SI |
cd2b37d9 | 8830 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8831 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8832 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8833 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8834 | "TARGET_UPDATE" |
1fd4e8c1 | 8835 | "@ |
5f243543 RK |
8836 | lbzux %3,%0,%2 |
8837 | lbzu %3,%2(%0)" | |
cfb557c4 | 8838 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8839 | |
38c1f2d7 | 8840 | (define_insn "*movqi_update3" |
cd2b37d9 | 8841 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8842 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8843 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
8844 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8845 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8846 | "TARGET_UPDATE" |
1fd4e8c1 | 8847 | "@ |
5f243543 | 8848 | stbux %3,%0,%2 |
b7ff3d82 DE |
8849 | stbu %3,%2(%0)" |
8850 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8851 | |
38c1f2d7 | 8852 | (define_insn "*movsf_update1" |
cd2b37d9 | 8853 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 8854 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8855 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8856 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8857 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8858 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8859 | "@ |
5f243543 RK |
8860 | lfsux %3,%0,%2 |
8861 | lfsu %3,%2(%0)" | |
cfb557c4 | 8862 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 8863 | |
38c1f2d7 | 8864 | (define_insn "*movsf_update2" |
cd2b37d9 | 8865 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8866 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8867 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
8868 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8869 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8870 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8871 | "@ |
85fff2f3 | 8872 | stfsux %3,%0,%2 |
b7ff3d82 DE |
8873 | stfsu %3,%2(%0)" |
8874 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 8875 | |
38c1f2d7 MM |
8876 | (define_insn "*movsf_update3" |
8877 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
8878 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
8879 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
8880 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
8881 | (plus:SI (match_dup 1) (match_dup 2)))] | |
8882 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
8883 | "@ | |
8884 | {lux|lwzux} %3,%0,%2 | |
8885 | {lu|lwzu} %3,%2(%0)" | |
8886 | [(set_attr "type" "load")]) | |
8887 | ||
8888 | (define_insn "*movsf_update4" | |
8889 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
8890 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
8891 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
8892 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
8893 | (plus:SI (match_dup 1) (match_dup 2)))] | |
8894 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
8895 | "@ | |
8896 | {stux|stwux} %3,%0,%2 | |
8897 | {stu|stwu} %3,%2(%0)" | |
8898 | [(set_attr "type" "store")]) | |
8899 | ||
8900 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
8901 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
8902 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8903 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8904 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8905 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8906 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8907 | "@ |
5f243543 RK |
8908 | lfdux %3,%0,%2 |
8909 | lfdu %3,%2(%0)" | |
cfb557c4 | 8910 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 8911 | |
38c1f2d7 | 8912 | (define_insn "*movdf_update2" |
cd2b37d9 | 8913 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8914 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8915 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
8916 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8917 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8918 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8919 | "@ |
5f243543 | 8920 | stfdux %3,%0,%2 |
b7ff3d82 DE |
8921 | stfdu %3,%2(%0)" |
8922 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
8923 | |
8924 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
8925 | ||
8926 | (define_peephole | |
8927 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8928 | (match_operand:DF 1 "memory_operand" "")) | |
8929 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
8930 | (match_operand:DF 3 "memory_operand" ""))] | |
8931 | "TARGET_POWER2 | |
d14a6d05 | 8932 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
8933 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
8934 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
8935 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
8936 | "lfq%U1%X1 %0,%1") | |
8937 | ||
8938 | (define_peephole | |
8939 | [(set (match_operand:DF 0 "memory_operand" "") | |
8940 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
8941 | (set (match_operand:DF 2 "memory_operand" "") | |
8942 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
8943 | "TARGET_POWER2 | |
d14a6d05 | 8944 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
8945 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
8946 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
8947 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
8948 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
8949 | \f |
8950 | ;; Next come insns related to the calling sequence. | |
8951 | ;; | |
8952 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 8953 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
8954 | |
8955 | (define_expand "allocate_stack" | |
52d3af72 | 8956 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
8957 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
8958 | (set (reg 1) | |
8959 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
8960 | "" |
8961 | " | |
4697a36c | 8962 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 8963 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 8964 | rtx neg_op0; |
1fd4e8c1 RK |
8965 | |
8966 | emit_move_insn (chain, stack_bot); | |
4697a36c | 8967 | |
a157febd GK |
8968 | /* Check stack bounds if necessary. */ |
8969 | if (current_function_limit_stack) | |
8970 | { | |
8971 | rtx available; | |
8972 | available = expand_binop (Pmode, sub_optab, | |
8973 | stack_pointer_rtx, stack_limit_rtx, | |
8974 | NULL_RTX, 1, OPTAB_WIDEN); | |
8975 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
8976 | } | |
8977 | ||
e9a25f70 JL |
8978 | if (GET_CODE (operands[1]) != CONST_INT |
8979 | || INTVAL (operands[1]) < -32767 | |
8980 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
8981 | { |
8982 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 8983 | if (TARGET_32BIT) |
e9a25f70 | 8984 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 8985 | else |
e9a25f70 | 8986 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
8987 | } |
8988 | else | |
e9a25f70 | 8989 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 8990 | |
38c1f2d7 MM |
8991 | if (TARGET_UPDATE) |
8992 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
8993 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 8994 | |
38c1f2d7 MM |
8995 | else |
8996 | { | |
8997 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
8998 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 8999 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9000 | } |
e9a25f70 JL |
9001 | |
9002 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9003 | DONE; |
9004 | }") | |
59257ff7 RK |
9005 | |
9006 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9007 | ;; save the stack pointer at function level since we are careful to | |
9008 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9009 | ;; when we restore the stack pointer. | |
9010 | ;; | |
9011 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9012 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9013 | ;; save area is a memory location. | |
9014 | ||
9015 | (define_expand "save_stack_function" | |
ff381587 MM |
9016 | [(match_operand 0 "any_operand" "") |
9017 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9018 | "" |
ff381587 | 9019 | "DONE;") |
59257ff7 RK |
9020 | |
9021 | (define_expand "restore_stack_function" | |
ff381587 MM |
9022 | [(match_operand 0 "any_operand" "") |
9023 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9024 | "" |
ff381587 | 9025 | "DONE;") |
59257ff7 RK |
9026 | |
9027 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9028 | [(use (match_operand 0 "register_operand" "")) |
9029 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9030 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9031 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9032 | "" |
9033 | " | |
dfdfa60f DE |
9034 | { |
9035 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9036 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9037 | }") |
59257ff7 RK |
9038 | |
9039 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9040 | [(match_operand 0 "memory_operand" "") |
9041 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9042 | "" |
9043 | " | |
9044 | { | |
a260abc9 | 9045 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9046 | |
9047 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9048 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
9049 | emit_move_insn (operand_subword (operands[0], 0, 0, |
9050 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
9051 | temp); |
9052 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
9053 | operands[1]); | |
59257ff7 RK |
9054 | DONE; |
9055 | }") | |
7e69e155 | 9056 | |
59257ff7 | 9057 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9058 | [(match_operand 0 "register_operand" "") |
9059 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9060 | "" |
9061 | " | |
9062 | { | |
a260abc9 | 9063 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9064 | |
9065 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
9066 | emit_move_insn (temp, |
9067 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
9068 | emit_move_insn (operands[0], | |
c5c76735 JL |
9069 | operand_subword (operands[1], 1, 0, |
9070 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 9071 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9072 | DONE; |
9073 | }") | |
9ebbca7d GK |
9074 | \f |
9075 | ;; TOC register handling. | |
b6c9286a | 9076 | |
9ebbca7d | 9077 | ;; Code to initialize the TOC register... |
f0f6a223 | 9078 | |
9ebbca7d | 9079 | (define_insn "load_toc_aix_si" |
46aaf10d DE |
9080 | [(parallel [(set (match_operand:SI 0 "register_operand" "=r") |
9081 | (unspec:SI [(const_int 0)] 7)) | |
9082 | (use (reg:SI 2))])] | |
2bfcf297 | 9083 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
9084 | "* |
9085 | { | |
9ebbca7d GK |
9086 | char buf[30]; |
9087 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9088 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9089 | operands[2] = gen_rtx_REG (Pmode, 2); |
9090 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9091 | }" |
9092 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9093 | |
9094 | (define_insn "load_toc_aix_di" | |
46aaf10d DE |
9095 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
9096 | (unspec:DI [(const_int 0)] 7)) | |
9097 | (use (reg:DI 2))])] | |
2bfcf297 | 9098 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
9099 | "* |
9100 | { | |
9101 | char buf[30]; | |
9102 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
2bfcf297 DB |
9103 | if (TARGET_ELF) |
9104 | strcat (buf, \"@toc\"); | |
a8a05998 | 9105 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9106 | operands[2] = gen_rtx_REG (Pmode, 2); |
9107 | return \"ld %0,%1(%2)\"; | |
9108 | }" | |
9109 | [(set_attr "type" "load")]) | |
9110 | ||
9111 | (define_insn "load_toc_v4_pic_si" | |
9112 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9113 | (unspec:SI [(const_int 0)] 7))] | |
9114 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1 | |
9115 | && TARGET_32BIT" | |
9116 | "bl _GLOBAL_OFFSET_TABLE_@local-4" | |
9117 | [(set_attr "type" "branch") | |
9118 | (set_attr "length" "4")]) | |
9119 | ||
9ebbca7d GK |
9120 | (define_insn "load_toc_v4_PIC_1" |
9121 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9122 | (match_operand:SI 1 "immediate_operand" "s")) | |
9123 | (unspec [(match_dup 1)] 7)] | |
9124 | "TARGET_ELF && flag_pic == 2" | |
9125 | "bl %1\\n%1:" | |
9126 | [(set_attr "type" "branch") | |
9127 | (set_attr "length" "4")]) | |
9128 | ||
9129 | (define_insn "load_toc_v4_PIC_1b" | |
9130 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9131 | (match_operand:SI 1 "immediate_operand" "s")) | |
9132 | (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] | |
9133 | "TARGET_ELF && flag_pic == 2" | |
9134 | "bl %1\\n\\t.long %2-%1+4\\n%1:" | |
9135 | [(set_attr "type" "branch") | |
9136 | (set_attr "length" "8")]) | |
9137 | ||
9138 | (define_insn "load_toc_v4_PIC_2" | |
9139 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9140 | (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") | |
9141 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") | |
9142 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
9143 | "TARGET_ELF && flag_pic == 2" | |
9144 | "{l|lwz} %0,%2-%3(%1)" | |
9145 | [(set_attr "type" "load")]) | |
9146 | ||
ee890fe2 SS |
9147 | (define_insn "load_macho_picbase" |
9148 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9149 | (unspec:SI [(const_int 0)] 15))] | |
9150 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" | |
9151 | "* | |
9152 | { | |
9153 | #if TARGET_MACHO | |
9154 | char *picbase = machopic_function_base_name (); | |
9155 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); | |
9156 | #endif | |
9157 | return \"bcl 20,31,%1\\n%1:\"; | |
9158 | }" | |
9159 | [(set_attr "type" "branch") | |
9160 | (set_attr "length" "4")]) | |
9161 | ||
9ebbca7d GK |
9162 | ;; If the TOC is shared over a translation unit, as happens with all |
9163 | ;; the kinds of PIC that we support, we need to restore the TOC | |
9164 | ;; pointer only when jumping over units of translation. | |
9165 | ||
9166 | (define_expand "builtin_setjmp_receiver" | |
9167 | [(use (label_ref (match_operand 0 "" "")))] | |
9168 | "((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1) | |
9169 | || (TARGET_TOC && TARGET_MINIMAL_TOC)" | |
9170 | " | |
9171 | { | |
9172 | rs6000_emit_load_toc_table (FALSE); | |
9173 | DONE; | |
9174 | }") | |
9175 | \f | |
9176 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
9177 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
9178 | ;; pointer to its TOC, and whose third word contains a value to place in the |
9179 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 9180 | ;; "trampoline" need not have any executable code. |
b6c9286a | 9181 | |
cccf3bdc DE |
9182 | (define_expand "call_indirect_aix32" |
9183 | [(set (match_dup 2) | |
9184 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
9185 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9186 | (reg:SI 2)) | |
9187 | (set (reg:SI 2) | |
9188 | (mem:SI (plus:SI (match_dup 0) | |
9189 | (const_int 4)))) | |
9190 | (set (reg:SI 11) | |
9191 | (mem:SI (plus:SI (match_dup 0) | |
9192 | (const_int 8)))) | |
9193 | (parallel [(call (mem:SI (match_dup 2)) | |
9194 | (match_operand 1 "" "")) | |
9195 | (use (reg:SI 2)) | |
9196 | (use (reg:SI 11)) | |
9197 | (set (reg:SI 2) | |
9198 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9199 | (clobber (scratch:SI))])] | |
9200 | "TARGET_32BIT" | |
9201 | " | |
9202 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9203 | |
cccf3bdc DE |
9204 | (define_expand "call_indirect_aix64" |
9205 | [(set (match_dup 2) | |
9206 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
9207 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9208 | (reg:DI 2)) | |
9209 | (set (reg:DI 2) | |
9210 | (mem:DI (plus:DI (match_dup 0) | |
9211 | (const_int 8)))) | |
9212 | (set (reg:DI 11) | |
9213 | (mem:DI (plus:DI (match_dup 0) | |
9214 | (const_int 16)))) | |
9215 | (parallel [(call (mem:SI (match_dup 2)) | |
9216 | (match_operand 1 "" "")) | |
9217 | (use (reg:DI 2)) | |
9218 | (use (reg:DI 11)) | |
9219 | (set (reg:DI 2) | |
9220 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9221 | (clobber (scratch:SI))])] | |
9222 | "TARGET_64BIT" | |
9223 | " | |
9224 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 9225 | |
cccf3bdc DE |
9226 | (define_expand "call_value_indirect_aix32" |
9227 | [(set (match_dup 3) | |
9228 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
9229 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9230 | (reg:SI 2)) | |
9231 | (set (reg:SI 2) | |
9232 | (mem:SI (plus:SI (match_dup 1) | |
9233 | (const_int 4)))) | |
9234 | (set (reg:SI 11) | |
9235 | (mem:SI (plus:SI (match_dup 1) | |
9236 | (const_int 8)))) | |
9237 | (parallel [(set (match_operand 0 "" "") | |
9238 | (call (mem:SI (match_dup 3)) | |
9239 | (match_operand 2 "" ""))) | |
9240 | (use (reg:SI 2)) | |
9241 | (use (reg:SI 11)) | |
9242 | (set (reg:SI 2) | |
9243 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9244 | (clobber (scratch:SI))])] | |
9245 | "TARGET_32BIT" | |
9246 | " | |
9247 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9248 | |
cccf3bdc DE |
9249 | (define_expand "call_value_indirect_aix64" |
9250 | [(set (match_dup 3) | |
9251 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
9252 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9253 | (reg:DI 2)) | |
9254 | (set (reg:DI 2) | |
9255 | (mem:DI (plus:DI (match_dup 1) | |
9256 | (const_int 8)))) | |
9257 | (set (reg:DI 11) | |
9258 | (mem:DI (plus:DI (match_dup 1) | |
9259 | (const_int 16)))) | |
9260 | (parallel [(set (match_operand 0 "" "") | |
9261 | (call (mem:SI (match_dup 3)) | |
9262 | (match_operand 2 "" ""))) | |
9263 | (use (reg:DI 2)) | |
9264 | (use (reg:DI 11)) | |
9265 | (set (reg:DI 2) | |
9266 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9267 | (clobber (scratch:SI))])] | |
9268 | "TARGET_64BIT" | |
9269 | " | |
9270 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 9271 | |
b6c9286a | 9272 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 9273 | (define_expand "call" |
a260abc9 | 9274 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 9275 | (match_operand 1 "" "")) |
4697a36c | 9276 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
9277 | (clobber (scratch:SI))])] |
9278 | "" | |
9279 | " | |
9280 | { | |
ee890fe2 SS |
9281 | #if TARGET_MACHO |
9282 | if (flag_pic) | |
9283 | operands[0] = machopic_indirect_call_target (operands[0]); | |
9284 | #endif | |
9285 | ||
1fd4e8c1 RK |
9286 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
9287 | abort (); | |
9288 | ||
9289 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 9290 | |
6a4cee5f MM |
9291 | if (GET_CODE (operands[0]) != SYMBOL_REF |
9292 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9293 | { |
6a4cee5f MM |
9294 | if (INTVAL (operands[2]) & CALL_LONG) |
9295 | operands[0] = rs6000_longcall_ref (operands[0]); | |
9296 | ||
cccf3bdc DE |
9297 | if (DEFAULT_ABI == ABI_V4 |
9298 | || DEFAULT_ABI == ABI_AIX_NODESC | |
ee890fe2 | 9299 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc DE |
9300 | || DEFAULT_ABI == ABI_SOLARIS) |
9301 | operands[0] = force_reg (Pmode, operands[0]); | |
1fd4e8c1 | 9302 | |
cccf3bdc DE |
9303 | else if (DEFAULT_ABI == ABI_AIX) |
9304 | { | |
9305 | /* AIX function pointers are really pointers to a three word | |
9306 | area. */ | |
9307 | emit_call_insn (TARGET_32BIT | |
9308 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
9309 | operands[0]), | |
9310 | operands[1]) | |
9311 | : gen_call_indirect_aix64 (force_reg (DImode, | |
9312 | operands[0]), | |
9313 | operands[1])); | |
9314 | DONE; | |
b6c9286a | 9315 | } |
cccf3bdc DE |
9316 | else |
9317 | abort (); | |
1fd4e8c1 RK |
9318 | } |
9319 | }") | |
9320 | ||
9321 | (define_expand "call_value" | |
9322 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 9323 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 9324 | (match_operand 2 "" ""))) |
4697a36c | 9325 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
9326 | (clobber (scratch:SI))])] |
9327 | "" | |
9328 | " | |
9329 | { | |
ee890fe2 SS |
9330 | #if TARGET_MACHO |
9331 | if (flag_pic) | |
9332 | operands[1] = machopic_indirect_call_target (operands[1]); | |
9333 | #endif | |
9334 | ||
1fd4e8c1 RK |
9335 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
9336 | abort (); | |
9337 | ||
9338 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 9339 | |
6a4cee5f MM |
9340 | if (GET_CODE (operands[1]) != SYMBOL_REF |
9341 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9342 | { |
6756293c | 9343 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
9344 | operands[1] = rs6000_longcall_ref (operands[1]); |
9345 | ||
cccf3bdc DE |
9346 | if (DEFAULT_ABI == ABI_V4 |
9347 | || DEFAULT_ABI == ABI_AIX_NODESC | |
ee890fe2 | 9348 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc DE |
9349 | || DEFAULT_ABI == ABI_SOLARIS) |
9350 | operands[0] = force_reg (Pmode, operands[0]); | |
1fd4e8c1 | 9351 | |
cccf3bdc DE |
9352 | else if (DEFAULT_ABI == ABI_AIX) |
9353 | { | |
9354 | /* AIX function pointers are really pointers to a three word | |
9355 | area. */ | |
9356 | emit_call_insn (TARGET_32BIT | |
9357 | ? gen_call_value_indirect_aix32 (operands[0], | |
9358 | force_reg (SImode, | |
9359 | operands[1]), | |
9360 | operands[2]) | |
9361 | : gen_call_value_indirect_aix64 (operands[0], | |
9362 | force_reg (DImode, | |
9363 | operands[1]), | |
9364 | operands[2])); | |
9365 | DONE; | |
b6c9286a | 9366 | } |
cccf3bdc DE |
9367 | else |
9368 | abort (); | |
1fd4e8c1 RK |
9369 | } |
9370 | }") | |
9371 | ||
04780ee7 | 9372 | ;; Call to function in current module. No TOC pointer reload needed. |
4697a36c MM |
9373 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9374 | ;; either the function was not prototyped, or it was prototyped as a | |
9375 | ;; variable argument function. It is > 0 if FP registers were passed | |
9376 | ;; and < 0 if they were not. | |
04780ee7 | 9377 | |
a260abc9 | 9378 | (define_insn "*call_local32" |
4697a36c MM |
9379 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
9380 | (match_operand 1 "" "g,g")) | |
9381 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9382 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 9383 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
9384 | "* |
9385 | { | |
6a4cee5f MM |
9386 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9387 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9388 | ||
9389 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9390 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 9391 | |
a226df46 | 9392 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 9393 | }" |
b7ff3d82 DE |
9394 | [(set_attr "type" "branch") |
9395 | (set_attr "length" "4,8")]) | |
04780ee7 | 9396 | |
a260abc9 DE |
9397 | (define_insn "*call_local64" |
9398 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
9399 | (match_operand 1 "" "g,g")) | |
9400 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9401 | (clobber (match_scratch:SI 3 "=l,l"))] | |
9402 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
9403 | "* | |
9404 | { | |
9405 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
9406 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9407 | ||
9408 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9409 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9410 | ||
9411 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
9412 | }" | |
9413 | [(set_attr "type" "branch") | |
9414 | (set_attr "length" "4,8")]) | |
9415 | ||
cccf3bdc | 9416 | (define_insn "*call_value_local32" |
a260abc9 DE |
9417 | [(set (match_operand 0 "" "=fg,fg") |
9418 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
9419 | (match_operand 2 "" "g,g"))) | |
9420 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9421 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9422 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
9423 | "* | |
9424 | { | |
9425 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9426 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9427 | ||
9428 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9429 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9430 | ||
9431 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9432 | }" | |
9433 | [(set_attr "type" "branch") | |
9434 | (set_attr "length" "4,8")]) | |
9435 | ||
9436 | ||
cccf3bdc | 9437 | (define_insn "*call_value_local64" |
a260abc9 DE |
9438 | [(set (match_operand 0 "" "=fg,fg") |
9439 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
9440 | (match_operand 2 "" "g,g"))) | |
9441 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9442 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9443 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
9444 | "* | |
9445 | { | |
9446 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9447 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9448 | ||
9449 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9450 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9451 | ||
9452 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9453 | }" | |
9454 | [(set_attr "type" "branch") | |
9455 | (set_attr "length" "4,8")]) | |
9456 | ||
04780ee7 | 9457 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 9458 | ;; pointer (r2) after the call unless this is System V. |
4697a36c MM |
9459 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9460 | ;; either the function was not prototyped, or it was prototyped as a | |
9461 | ;; variable argument function. It is > 0 if FP registers were passed | |
9462 | ;; and < 0 if they were not. | |
04780ee7 | 9463 | |
cccf3bdc DE |
9464 | (define_insn "*call_indirect_nonlocal_aix32" |
9465 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
9466 | (match_operand 1 "" "g")) | |
9467 | (use (reg:SI 2)) | |
9468 | (use (reg:SI 11)) | |
9469 | (set (reg:SI 2) | |
9470 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 9471 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
9472 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
9473 | "b%T0l\;{l|lwz} 2,20(1)" | |
9474 | [(set_attr "type" "jmpreg") | |
9475 | (set_attr "length" "8")]) | |
9476 | ||
a260abc9 | 9477 | (define_insn "*call_nonlocal_aix32" |
cccf3bdc DE |
9478 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s")) |
9479 | (match_operand 1 "" "g")) | |
9480 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9481 | (clobber (match_scratch:SI 3 "=l"))] | |
9482 | "TARGET_32BIT | |
9483 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 9484 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9485 | "bl %z0\;%." |
b7ff3d82 | 9486 | [(set_attr "type" "branch") |
cccf3bdc DE |
9487 | (set_attr "length" "8")]) |
9488 | ||
9489 | (define_insn "*call_indirect_nonlocal_aix64" | |
9490 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
9491 | (match_operand 1 "" "g")) | |
9492 | (use (reg:DI 2)) | |
9493 | (use (reg:DI 11)) | |
9494 | (set (reg:DI 2) | |
9495 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 9496 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
9497 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
9498 | "b%T0l\;ld 2,40(1)" | |
9499 | [(set_attr "type" "jmpreg") | |
9500 | (set_attr "length" "8")]) | |
59313e4e | 9501 | |
a260abc9 | 9502 | (define_insn "*call_nonlocal_aix64" |
cccf3bdc DE |
9503 | [(call (mem:SI (match_operand:DI 0 "call_operand" "s")) |
9504 | (match_operand 1 "" "g")) | |
9505 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9506 | (clobber (match_scratch:SI 3 "=l"))] | |
9ebbca7d GK |
9507 | "TARGET_64BIT |
9508 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 9509 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9510 | "bl %z0\;%." |
a260abc9 | 9511 | [(set_attr "type" "branch") |
cccf3bdc | 9512 | (set_attr "length" "8")]) |
7509c759 | 9513 | |
cccf3bdc DE |
9514 | (define_insn "*call_value_indirect_nonlocal_aix32" |
9515 | [(set (match_operand 0 "" "=fg") | |
9516 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) | |
9517 | (match_operand 2 "" "g"))) | |
9518 | (use (reg:SI 2)) | |
9519 | (use (reg:SI 11)) | |
9520 | (set (reg:SI 2) | |
9521 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9522 | (clobber (match_scratch:SI 3 "=l"))] | |
9523 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
9524 | "b%T1l\;{l|lwz} 2,20(1)" | |
9525 | [(set_attr "type" "jmpreg") | |
9526 | (set_attr "length" "8")]) | |
1fd4e8c1 | 9527 | |
cccf3bdc DE |
9528 | (define_insn "*call_value_nonlocal_aix32" |
9529 | [(set (match_operand 0 "" "=fg") | |
9530 | (call (mem:SI (match_operand:SI 1 "call_operand" "s")) | |
9531 | (match_operand 2 "" "g"))) | |
9532 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
9533 | (clobber (match_scratch:SI 4 "=l"))] | |
9534 | "TARGET_32BIT | |
9535 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 9536 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 9537 | "bl %z1\;%." |
b7ff3d82 | 9538 | [(set_attr "type" "branch") |
cccf3bdc | 9539 | (set_attr "length" "8")]) |
04780ee7 | 9540 | |
cccf3bdc DE |
9541 | (define_insn "*call_value_indirect_nonlocal_aix64" |
9542 | [(set (match_operand 0 "" "=fg") | |
9543 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) | |
9544 | (match_operand 2 "" "g"))) | |
9545 | (use (reg:DI 2)) | |
9546 | (use (reg:DI 11)) | |
9547 | (set (reg:DI 2) | |
9548 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9549 | (clobber (match_scratch:SI 3 "=l"))] | |
9550 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
9551 | "b%T1l\;ld 2,40(1)" | |
9552 | [(set_attr "type" "jmpreg") | |
9553 | (set_attr "length" "8")]) | |
9554 | ||
9555 | (define_insn "*call_value_nonlocal_aix64" | |
9556 | [(set (match_operand 0 "" "=fg") | |
9557 | (call (mem:SI (match_operand:DI 1 "call_operand" "s")) | |
9558 | (match_operand 2 "" "g"))) | |
9559 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
9560 | (clobber (match_scratch:SI 4 "=l"))] | |
9ebbca7d GK |
9561 | "TARGET_64BIT |
9562 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 9563 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
9564 | "bl %z1\;%." |
9565 | [(set_attr "type" "branch") | |
9566 | (set_attr "length" "8")]) | |
9567 | ||
9568 | ;; A function pointer under System V is just a normal pointer | |
9569 | ;; operands[0] is the function pointer | |
9570 | ;; operands[1] is the stack size to clean up | |
9571 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
9572 | ;; which indicates how to set cr1 | |
9573 | ||
9574 | (define_insn "*call_nonlocal_sysv" | |
9575 | [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s")) | |
9576 | (match_operand 1 "" "g,g,g,g")) | |
9577 | (use (match_operand:SI 2 "immediate_operand" "O,n,O,n")) | |
9578 | (clobber (match_scratch:SI 3 "=l,l,l,l"))] | |
9579 | "DEFAULT_ABI == ABI_AIX_NODESC | |
9580 | || DEFAULT_ABI == ABI_V4 | |
ee890fe2 | 9581 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc | 9582 | || DEFAULT_ABI == ABI_SOLARIS" |
911f679c MM |
9583 | "* |
9584 | { | |
cccf3bdc | 9585 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
6a4cee5f MM |
9586 | output_asm_insn (\"crxor 6,6,6\", operands); |
9587 | ||
cccf3bdc | 9588 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
6a4cee5f | 9589 | output_asm_insn (\"creqv 6,6,6\", operands); |
7509c759 | 9590 | |
cccf3bdc DE |
9591 | switch (which_alternative) |
9592 | { | |
9593 | default: | |
9594 | abort (); | |
9595 | case 0: | |
9596 | case 1: | |
9597 | return \"b%T0l\"; | |
9598 | case 2: | |
9599 | case 3: | |
9600 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; | |
9601 | } | |
b6c9286a | 9602 | }" |
cccf3bdc DE |
9603 | [(set_attr "type" "jmpreg,jmpreg,branch,branch") |
9604 | (set_attr "length" "4,8,4,8")]) | |
9605 | ||
9606 | (define_insn "*call_value_nonlocal_sysv" | |
9607 | [(set (match_operand 0 "" "=fg,fg,fg,fg") | |
9608 | (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s")) | |
9609 | (match_operand 2 "" "g,g,g,g"))) | |
9610 | (use (match_operand:SI 3 "immediate_operand" "O,n,O,n")) | |
9611 | (clobber (match_scratch:SI 4 "=l,l,l,l"))] | |
9612 | "DEFAULT_ABI == ABI_AIX_NODESC | |
9613 | || DEFAULT_ABI == ABI_V4 | |
ee890fe2 | 9614 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc | 9615 | || DEFAULT_ABI == ABI_SOLARIS" |
b6c9286a MM |
9616 | "* |
9617 | { | |
6a4cee5f MM |
9618 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
9619 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9620 | ||
9621 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9622 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 9623 | |
cccf3bdc DE |
9624 | switch (which_alternative) |
9625 | { | |
9626 | default: | |
9627 | abort (); | |
9628 | case 0: | |
9629 | case 1: | |
9630 | return \"b%T1l\"; | |
9631 | case 2: | |
9632 | case 3: | |
9633 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; | |
9634 | } | |
911f679c | 9635 | }" |
cccf3bdc DE |
9636 | [(set_attr "type" "jmpreg,jmpreg,branch,branch") |
9637 | (set_attr "length" "4,8,4,8")]) | |
e6f948e3 RK |
9638 | |
9639 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
9640 | (define_expand "untyped_call" |
9641 | [(parallel [(call (match_operand 0 "" "") | |
9642 | (const_int 0)) | |
9643 | (match_operand 1 "" "") | |
9644 | (match_operand 2 "" "")])] | |
9645 | "" | |
9646 | " | |
9647 | { | |
9648 | int i; | |
9649 | ||
7d70b8b2 | 9650 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
9651 | |
9652 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9653 | { | |
9654 | rtx set = XVECEXP (operands[2], 0, i); | |
9655 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9656 | } | |
9657 | ||
9658 | /* The optimizer does not know that the call sets the function value | |
9659 | registers we stored in the result block. We avoid problems by | |
9660 | claiming that all hard registers are used and clobbered at this | |
9661 | point. */ | |
9662 | emit_insn (gen_blockage ()); | |
9663 | ||
9664 | DONE; | |
9665 | }") | |
9666 | ||
9667 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9668 | ;; all of memory. This blocks insns from being moved across this point. | |
9669 | ||
9670 | (define_insn "blockage" | |
9671 | [(unspec_volatile [(const_int 0)] 0)] | |
9672 | "" | |
9673 | "") | |
1fd4e8c1 RK |
9674 | \f |
9675 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 9676 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
9677 | ;; |
9678 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
9679 | ;; insns, and branches. We store the operands of compares until we see | |
9680 | ;; how it is used. | |
9681 | (define_expand "cmpsi" | |
9682 | [(set (cc0) | |
cd2b37d9 | 9683 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
9684 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
9685 | "" | |
9686 | " | |
9687 | { | |
9688 | /* Take care of the possibility that operands[1] might be negative but | |
9689 | this might be a logical operation. That insn doesn't exist. */ | |
9690 | if (GET_CODE (operands[1]) == CONST_INT | |
9691 | && INTVAL (operands[1]) < 0) | |
9692 | operands[1] = force_reg (SImode, operands[1]); | |
9693 | ||
9694 | rs6000_compare_op0 = operands[0]; | |
9695 | rs6000_compare_op1 = operands[1]; | |
9696 | rs6000_compare_fp_p = 0; | |
9697 | DONE; | |
9698 | }") | |
9699 | ||
266eb58a DE |
9700 | (define_expand "cmpdi" |
9701 | [(set (cc0) | |
9702 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
9703 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
9704 | "TARGET_POWERPC64" | |
9705 | " | |
9706 | { | |
9707 | /* Take care of the possibility that operands[1] might be negative but | |
9708 | this might be a logical operation. That insn doesn't exist. */ | |
9709 | if (GET_CODE (operands[1]) == CONST_INT | |
9710 | && INTVAL (operands[1]) < 0) | |
9711 | operands[1] = force_reg (DImode, operands[1]); | |
9712 | ||
9713 | rs6000_compare_op0 = operands[0]; | |
9714 | rs6000_compare_op1 = operands[1]; | |
9715 | rs6000_compare_fp_p = 0; | |
9716 | DONE; | |
9717 | }") | |
9718 | ||
1fd4e8c1 | 9719 | (define_expand "cmpsf" |
cd2b37d9 RK |
9720 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
9721 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 9722 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9723 | " |
9724 | { | |
9725 | rs6000_compare_op0 = operands[0]; | |
9726 | rs6000_compare_op1 = operands[1]; | |
9727 | rs6000_compare_fp_p = 1; | |
9728 | DONE; | |
9729 | }") | |
9730 | ||
9731 | (define_expand "cmpdf" | |
cd2b37d9 RK |
9732 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
9733 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 9734 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9735 | " |
9736 | { | |
9737 | rs6000_compare_op0 = operands[0]; | |
9738 | rs6000_compare_op1 = operands[1]; | |
9739 | rs6000_compare_fp_p = 1; | |
9740 | DONE; | |
9741 | }") | |
9742 | ||
9743 | (define_expand "beq" | |
39a10a29 | 9744 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9745 | "" |
39a10a29 | 9746 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
9747 | |
9748 | (define_expand "bne" | |
39a10a29 | 9749 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9750 | "" |
39a10a29 | 9751 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 9752 | |
39a10a29 GK |
9753 | (define_expand "bge" |
9754 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9755 | "" |
39a10a29 | 9756 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
9757 | |
9758 | (define_expand "bgt" | |
39a10a29 | 9759 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9760 | "" |
39a10a29 | 9761 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
9762 | |
9763 | (define_expand "ble" | |
39a10a29 | 9764 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9765 | "" |
39a10a29 | 9766 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 9767 | |
39a10a29 GK |
9768 | (define_expand "blt" |
9769 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9770 | "" |
39a10a29 | 9771 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 9772 | |
39a10a29 GK |
9773 | (define_expand "bgeu" |
9774 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9775 | "" |
39a10a29 | 9776 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 9777 | |
39a10a29 GK |
9778 | (define_expand "bgtu" |
9779 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9780 | "" |
39a10a29 | 9781 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 9782 | |
39a10a29 GK |
9783 | (define_expand "bleu" |
9784 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9785 | "" |
39a10a29 | 9786 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 9787 | |
39a10a29 GK |
9788 | (define_expand "bltu" |
9789 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9790 | "" |
39a10a29 | 9791 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 9792 | |
1c882ea4 | 9793 | (define_expand "bunordered" |
39a10a29 | 9794 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9795 | "" |
39a10a29 | 9796 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
9797 | |
9798 | (define_expand "bordered" | |
39a10a29 | 9799 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9800 | "" |
39a10a29 | 9801 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
9802 | |
9803 | (define_expand "buneq" | |
39a10a29 | 9804 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9805 | "" |
39a10a29 | 9806 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
9807 | |
9808 | (define_expand "bunge" | |
39a10a29 | 9809 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9810 | "" |
39a10a29 | 9811 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
9812 | |
9813 | (define_expand "bungt" | |
39a10a29 | 9814 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9815 | "" |
39a10a29 | 9816 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
9817 | |
9818 | (define_expand "bunle" | |
39a10a29 | 9819 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9820 | "" |
39a10a29 | 9821 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
9822 | |
9823 | (define_expand "bunlt" | |
39a10a29 | 9824 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9825 | "" |
39a10a29 | 9826 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
9827 | |
9828 | (define_expand "bltgt" | |
39a10a29 | 9829 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9830 | "" |
39a10a29 | 9831 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 9832 | |
1fd4e8c1 RK |
9833 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
9834 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
9835 | ;; with an scc insns. However, due to the order that combine see the | |
9836 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
9837 | ;; the cases we don't want to handle. | |
9838 | (define_expand "seq" | |
39a10a29 | 9839 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9840 | "" |
39a10a29 | 9841 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
9842 | |
9843 | (define_expand "sne" | |
39a10a29 | 9844 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9845 | "" |
9846 | " | |
39a10a29 GK |
9847 | { |
9848 | if (! rs6000_compare_fp_p) | |
1fd4e8c1 RK |
9849 | FAIL; |
9850 | ||
39a10a29 GK |
9851 | rs6000_emit_sCOND (NE, operands[0]); |
9852 | DONE; | |
1fd4e8c1 RK |
9853 | }") |
9854 | ||
9855 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
9856 | (define_expand "sgt" | |
39a10a29 | 9857 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9858 | "" |
9859 | " | |
5638268e DE |
9860 | { |
9861 | if (! rs6000_compare_fp_p | |
9862 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
9863 | FAIL; |
9864 | ||
39a10a29 GK |
9865 | rs6000_emit_sCOND (GT, operands[0]); |
9866 | DONE; | |
1fd4e8c1 RK |
9867 | }") |
9868 | ||
9869 | ;; A < 0 is best done in the portable way for A an integer. | |
9870 | (define_expand "slt" | |
39a10a29 | 9871 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9872 | "" |
9873 | " | |
5638268e DE |
9874 | { |
9875 | if (! rs6000_compare_fp_p | |
9876 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
9877 | FAIL; |
9878 | ||
39a10a29 GK |
9879 | rs6000_emit_sCOND (LT, operands[0]); |
9880 | DONE; | |
1fd4e8c1 RK |
9881 | }") |
9882 | ||
5638268e | 9883 | ;; A >= 0 is best done the portable way for A an integer. |
1fd4e8c1 | 9884 | (define_expand "sge" |
39a10a29 | 9885 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9886 | "" |
5638268e DE |
9887 | " |
9888 | { | |
9889 | if (! rs6000_compare_fp_p | |
9890 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
9891 | FAIL; | |
9892 | ||
9893 | rs6000_emit_sCOND (GE, operands[0]); | |
9894 | DONE; | |
9895 | }") | |
1fd4e8c1 RK |
9896 | |
9897 | ;; A <= 0 is best done the portable way for A an integer. | |
9898 | (define_expand "sle" | |
39a10a29 | 9899 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9900 | "" |
9901 | " | |
5638268e DE |
9902 | { |
9903 | if (! rs6000_compare_fp_p | |
9904 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
9905 | FAIL; |
9906 | ||
39a10a29 GK |
9907 | rs6000_emit_sCOND (LE, operands[0]); |
9908 | DONE; | |
1fd4e8c1 RK |
9909 | }") |
9910 | ||
9911 | (define_expand "sgtu" | |
39a10a29 | 9912 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9913 | "" |
39a10a29 | 9914 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9915 | |
9916 | (define_expand "sltu" | |
39a10a29 | 9917 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9918 | "" |
39a10a29 | 9919 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9920 | |
9921 | (define_expand "sgeu" | |
39a10a29 | 9922 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9923 | "" |
39a10a29 | 9924 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9925 | |
9926 | (define_expand "sleu" | |
39a10a29 | 9927 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9928 | "" |
39a10a29 | 9929 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9930 | \f |
9931 | ;; Here are the actual compare insns. | |
acad7ed3 | 9932 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 9933 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 9934 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
9935 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
9936 | "" | |
7f340546 | 9937 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
9938 | [(set_attr "type" "compare")]) |
9939 | ||
acad7ed3 | 9940 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
9941 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
9942 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
9943 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
9944 | "TARGET_POWERPC64" | |
9945 | "cmpd%I2 %0,%1,%2" | |
9946 | [(set_attr "type" "compare")]) | |
9947 | ||
f357808b RK |
9948 | ;; If we are comparing a register for equality with a large constant, |
9949 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
9950 | ;; register for the result of the XOR. | |
9951 | ||
9952 | (define_split | |
9953 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 9954 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 9955 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 9956 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
9957 | "find_single_use (operands[0], insn, 0) |
9958 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
9959 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
9960 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
9961 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
9962 | " | |
9963 | { | |
9964 | /* Get the constant we are comparing against, C, and see what it looks like | |
9965 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
9966 | with C to get the sign-extended value. */ | |
9967 | ||
5f59ecb7 DE |
9968 | HOST_WIDE_INT c = INTVAL (operands[2]); |
9969 | HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000); | |
9970 | HOST_WIDE_INT xorv = c ^ sextc; | |
f357808b | 9971 | |
89e9f3a8 MM |
9972 | operands[4] = GEN_INT (xorv); |
9973 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
9974 | }") |
9975 | ||
acad7ed3 | 9976 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 9977 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 9978 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 9979 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 9980 | "" |
e2c953b6 | 9981 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
1fd4e8c1 RK |
9982 | [(set_attr "type" "compare")]) |
9983 | ||
acad7ed3 | 9984 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
9985 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
9986 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 9987 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 9988 | "" |
e2c953b6 | 9989 | "cmpld%I2 %0,%1,%b2" |
266eb58a DE |
9990 | [(set_attr "type" "compare")]) |
9991 | ||
1fd4e8c1 RK |
9992 | ;; The following two insns don't exist as single insns, but if we provide |
9993 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
9994 | ;; of the required delay between a compare and branch. We generate code for | |
9995 | ;; them by splitting. | |
9996 | ||
9997 | (define_insn "" | |
9998 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 9999 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10000 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 10001 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10002 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10003 | "" | |
baf97f86 RK |
10004 | "#" |
10005 | [(set_attr "length" "8")]) | |
7e69e155 | 10006 | |
1fd4e8c1 RK |
10007 | (define_insn "" |
10008 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10009 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10010 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 10011 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10012 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10013 | "" | |
baf97f86 RK |
10014 | "#" |
10015 | [(set_attr "length" "8")]) | |
7e69e155 | 10016 | |
1fd4e8c1 RK |
10017 | (define_split |
10018 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 10019 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10020 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 10021 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10022 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10023 | "" | |
10024 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
10025 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10026 | ||
10027 | (define_split | |
10028 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 10029 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10030 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 10031 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10032 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10033 | "" | |
10034 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
10035 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10036 | ||
acad7ed3 | 10037 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 10038 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10039 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
10040 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10041 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10042 | "fcmpu %0,%1,%2" |
10043 | [(set_attr "type" "fpcompare")]) | |
10044 | ||
acad7ed3 | 10045 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 10046 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10047 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
10048 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10049 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10050 | "fcmpu %0,%1,%2" |
10051 | [(set_attr "type" "fpcompare")]) | |
10052 | \f | |
10053 | ;; Now we have the scc insns. We can do some combinations because of the | |
10054 | ;; way the machine works. | |
10055 | ;; | |
10056 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
10057 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
10058 | ;; cases the insns below which don't use an intermediate CR field will | |
10059 | ;; be used instead. | |
1fd4e8c1 | 10060 | (define_insn "" |
cd2b37d9 | 10061 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10062 | (match_operator:SI 1 "scc_comparison_operator" |
10063 | [(match_operand 2 "cc_reg_operand" "y") | |
10064 | (const_int 0)]))] | |
10065 | "" | |
ca7f5001 | 10066 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b19003d8 | 10067 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10068 | |
10069 | (define_insn "" | |
9ebbca7d GK |
10070 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
10071 | (match_operator:DI 1 "scc_comparison_operator" | |
10072 | [(match_operand 2 "cc_reg_operand" "y") | |
10073 | (const_int 0)]))] | |
10074 | "TARGET_POWERPC64" | |
10075 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" | |
10076 | [(set_attr "length" "12")]) | |
10077 | ||
10078 | (define_insn "" | |
10079 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 10080 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 10081 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
10082 | (const_int 0)]) |
10083 | (const_int 0))) | |
9ebbca7d | 10084 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10085 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 10086 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10087 | "@ |
10088 | %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 | |
10089 | #" | |
b19003d8 | 10090 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10091 | (set_attr "length" "12,16")]) |
10092 | ||
10093 | (define_split | |
10094 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10095 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
10096 | [(match_operand 2 "cc_reg_operand" "") | |
10097 | (const_int 0)]) | |
10098 | (const_int 0))) | |
10099 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
10100 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
10101 | "! TARGET_POWERPC64 && reload_completed" | |
10102 | [(set (match_dup 3) | |
10103 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
10104 | (set (match_dup 0) | |
10105 | (compare:CC (match_dup 3) | |
10106 | (const_int 0)))] | |
10107 | "") | |
1fd4e8c1 RK |
10108 | |
10109 | (define_insn "" | |
cd2b37d9 | 10110 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10111 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
10112 | [(match_operand 2 "cc_reg_operand" "y") | |
10113 | (const_int 0)]) | |
10114 | (match_operand:SI 3 "const_int_operand" "n")))] | |
10115 | "" | |
10116 | "* | |
10117 | { | |
10118 | int is_bit = ccr_bit (operands[1], 1); | |
10119 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
10120 | int count; | |
10121 | ||
10122 | if (is_bit >= put_bit) | |
10123 | count = is_bit - put_bit; | |
10124 | else | |
10125 | count = 32 - (put_bit - is_bit); | |
10126 | ||
89e9f3a8 MM |
10127 | operands[4] = GEN_INT (count); |
10128 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 10129 | |
ca7f5001 | 10130 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 RK |
10131 | }" |
10132 | [(set_attr "length" "12")]) | |
1fd4e8c1 RK |
10133 | |
10134 | (define_insn "" | |
9ebbca7d | 10135 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10136 | (compare:CC |
10137 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 10138 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 10139 | (const_int 0)]) |
9ebbca7d | 10140 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 10141 | (const_int 0))) |
9ebbca7d | 10142 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
10143 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
10144 | (match_dup 3)))] | |
9ebbca7d | 10145 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
10146 | "* |
10147 | { | |
10148 | int is_bit = ccr_bit (operands[1], 1); | |
10149 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
10150 | int count; | |
10151 | ||
9ebbca7d GK |
10152 | /* Force split for non-cc0 compare. */ |
10153 | if (which_alternative == 1) | |
10154 | return \"#\"; | |
10155 | ||
1fd4e8c1 RK |
10156 | if (is_bit >= put_bit) |
10157 | count = is_bit - put_bit; | |
10158 | else | |
10159 | count = 32 - (put_bit - is_bit); | |
10160 | ||
89e9f3a8 MM |
10161 | operands[5] = GEN_INT (count); |
10162 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 10163 | |
ca7f5001 | 10164 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 10165 | }" |
b19003d8 | 10166 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10167 | (set_attr "length" "12,16")]) |
10168 | ||
10169 | (define_split | |
10170 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10171 | (compare:CC | |
10172 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
10173 | [(match_operand 2 "cc_reg_operand" "") | |
10174 | (const_int 0)]) | |
10175 | (match_operand:SI 3 "const_int_operand" "")) | |
10176 | (const_int 0))) | |
10177 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
10178 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10179 | (match_dup 3)))] | |
10180 | "! TARGET_POWERPC64 && reload_completed" | |
10181 | [(set (match_dup 4) | |
10182 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10183 | (match_dup 3))) | |
10184 | (set (match_dup 0) | |
10185 | (compare:CC (match_dup 4) | |
10186 | (const_int 0)))] | |
10187 | "") | |
1fd4e8c1 | 10188 | |
c5defebb RK |
10189 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
10190 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
10191 | ||
10192 | (define_peephole | |
cd2b37d9 | 10193 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
10194 | (match_operator:SI 1 "scc_comparison_operator" |
10195 | [(match_operand 2 "cc_reg_operand" "y") | |
10196 | (const_int 0)])) | |
cd2b37d9 | 10197 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
10198 | (match_operator:SI 4 "scc_comparison_operator" |
10199 | [(match_operand 5 "cc_reg_operand" "y") | |
10200 | (const_int 0)]))] | |
10201 | "REGNO (operands[2]) != REGNO (operands[5])" | |
ca7f5001 | 10202 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b19003d8 | 10203 | [(set_attr "length" "20")]) |
c5defebb | 10204 | |
9ebbca7d GK |
10205 | (define_peephole |
10206 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10207 | (match_operator:DI 1 "scc_comparison_operator" | |
10208 | [(match_operand 2 "cc_reg_operand" "y") | |
10209 | (const_int 0)])) | |
10210 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
10211 | (match_operator:DI 4 "scc_comparison_operator" | |
10212 | [(match_operand 5 "cc_reg_operand" "y") | |
10213 | (const_int 0)]))] | |
10214 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" | |
10215 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
10216 | [(set_attr "length" "20")]) | |
10217 | ||
1fd4e8c1 RK |
10218 | ;; There are some scc insns that can be done directly, without a compare. |
10219 | ;; These are faster because they don't involve the communications between | |
10220 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
10221 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
10222 | ;; | |
10223 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
10224 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
10225 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
10226 | ;; cases where it is no more expensive than (neg (scc ..)). | |
10227 | ||
10228 | ;; Have reload force a constant into a register for the simple insns that | |
10229 | ;; otherwise won't accept constants. We do this because it is faster than | |
10230 | ;; the cmp/mfcr sequence we would otherwise generate. | |
10231 | ||
10232 | (define_insn "" | |
cd2b37d9 RK |
10233 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
10234 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 10235 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 10236 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
f9562f27 | 10237 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10238 | "@ |
ca7f5001 | 10239 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 10240 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
10241 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
10242 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
10243 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 10244 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 10245 | |
a260abc9 DE |
10246 | (define_insn "" |
10247 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
10248 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
10249 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
10250 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
10251 | "TARGET_POWERPC64" | |
10252 | "@ | |
10253 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10254 | subfic %3,%1,0\;adde %0,%3,%1 | |
10255 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10256 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10257 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
10258 | [(set_attr "length" "12,8,12,12,12")]) | |
10259 | ||
1fd4e8c1 | 10260 | (define_insn "" |
9ebbca7d | 10261 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10262 | (compare:CC |
9ebbca7d GK |
10263 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10264 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 10265 | (const_int 0))) |
9ebbca7d | 10266 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 10267 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10268 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
f9562f27 | 10269 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10270 | "@ |
ca7f5001 RK |
10271 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
10272 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
10273 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
10274 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
10275 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
10276 | # | |
10277 | # | |
10278 | # | |
10279 | # | |
10280 | #" | |
b19003d8 | 10281 | [(set_attr "type" "compare") |
9ebbca7d GK |
10282 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10283 | ||
10284 | (define_split | |
10285 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10286 | (compare:CC | |
10287 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10288 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10289 | (const_int 0))) | |
10290 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10291 | (eq:SI (match_dup 1) (match_dup 2))) | |
10292 | (clobber (match_scratch:SI 3 ""))] | |
10293 | "! TARGET_POWERPC64 && reload_completed" | |
10294 | [(parallel [(set (match_dup 0) | |
10295 | (eq:SI (match_dup 1) (match_dup 2))) | |
10296 | (clobber (match_dup 3))]) | |
10297 | (set (match_dup 4) | |
10298 | (compare:CC (match_dup 0) | |
10299 | (const_int 0)))] | |
10300 | "") | |
b19003d8 | 10301 | |
a260abc9 | 10302 | (define_insn "" |
9ebbca7d | 10303 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 10304 | (compare:CC |
9ebbca7d GK |
10305 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10306 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 10307 | (const_int 0))) |
9ebbca7d | 10308 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 10309 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10310 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
a260abc9 DE |
10311 | "TARGET_POWERPC64" |
10312 | "@ | |
10313 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
10314 | subfic %3,%1,0\;adde. %0,%3,%1 | |
10315 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
10316 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
10317 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
10318 | # | |
10319 | # | |
10320 | # | |
10321 | # | |
10322 | #" | |
a260abc9 | 10323 | [(set_attr "type" "compare") |
9ebbca7d GK |
10324 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10325 | ||
10326 | (define_split | |
10327 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10328 | (compare:CC | |
10329 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
10330 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
10331 | (const_int 0))) | |
10332 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10333 | (eq:DI (match_dup 1) (match_dup 2))) | |
10334 | (clobber (match_scratch:DI 3 ""))] | |
10335 | "TARGET_POWERPC64 && reload_completed" | |
10336 | [(parallel [(set (match_dup 0) | |
10337 | (eq:DI (match_dup 1) (match_dup 2))) | |
10338 | (clobber (match_dup 3))]) | |
10339 | (set (match_dup 4) | |
10340 | (compare:CC (match_dup 0) | |
10341 | (const_int 0)))] | |
10342 | "") | |
a260abc9 | 10343 | |
b19003d8 RK |
10344 | ;; We have insns of the form shown by the first define_insn below. If |
10345 | ;; there is something inside the comparison operation, we must split it. | |
10346 | (define_split | |
10347 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
10348 | (plus:SI (match_operator 1 "comparison_operator" | |
10349 | [(match_operand:SI 2 "" "") | |
10350 | (match_operand:SI 3 | |
10351 | "reg_or_cint_operand" "")]) | |
10352 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
10353 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
10354 | "! gpc_reg_operand (operands[2], SImode)" | |
10355 | [(set (match_dup 5) (match_dup 2)) | |
10356 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
10357 | (match_dup 4)))]) | |
1fd4e8c1 RK |
10358 | |
10359 | (define_insn "" | |
cd2b37d9 RK |
10360 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
10361 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 10362 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
cd2b37d9 | 10363 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) |
1fd4e8c1 | 10364 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
f9562f27 | 10365 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10366 | "@ |
ca7f5001 RK |
10367 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
10368 | {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 | |
10369 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
10370 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
d9d934ef | 10371 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" |
b19003d8 | 10372 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
10373 | |
10374 | (define_insn "" | |
9ebbca7d | 10375 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10376 | (compare:CC |
1fd4e8c1 | 10377 | (plus:SI |
9ebbca7d GK |
10378 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10379 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
10380 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 10381 | (const_int 0))) |
9ebbca7d | 10382 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 10383 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10384 | "@ |
ca7f5001 | 10385 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 10386 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
10387 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
10388 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
10389 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
10390 | # | |
10391 | # | |
10392 | # | |
10393 | # | |
10394 | #" | |
b19003d8 | 10395 | [(set_attr "type" "compare") |
9ebbca7d GK |
10396 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10397 | ||
10398 | (define_split | |
10399 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10400 | (compare:CC | |
10401 | (plus:SI | |
10402 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10403 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10404 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10405 | (const_int 0))) | |
10406 | (clobber (match_scratch:SI 4 ""))] | |
10407 | "! TARGET_POWERPC64 && reload_completed" | |
10408 | [(set (match_dup 4) | |
10409 | (plus:SI (eq:SI (match_dup 1) | |
10410 | (match_dup 2)) | |
10411 | (match_dup 3))) | |
10412 | (set (match_dup 0) | |
10413 | (compare:CC (match_dup 4) | |
10414 | (const_int 0)))] | |
10415 | "") | |
1fd4e8c1 RK |
10416 | |
10417 | (define_insn "" | |
9ebbca7d | 10418 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10419 | (compare:CC |
1fd4e8c1 | 10420 | (plus:SI |
9ebbca7d GK |
10421 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10422 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
10423 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 10424 | (const_int 0))) |
9ebbca7d | 10425 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 10426 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10427 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 10428 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10429 | "@ |
ca7f5001 | 10430 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
19378cf8 | 10431 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 |
ca7f5001 RK |
10432 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
10433 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
10434 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
10435 | # | |
10436 | # | |
10437 | # | |
10438 | # | |
10439 | #" | |
10440 | [(set_attr "type" "compare") | |
10441 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
10442 | ||
10443 | (define_split | |
10444 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10445 | (compare:CC | |
10446 | (plus:SI | |
10447 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10448 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10449 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10450 | (const_int 0))) | |
10451 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10452 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10453 | (clobber (match_scratch:SI 4 ""))] | |
10454 | "! TARGET_POWERPC64 && reload_completed" | |
10455 | [(parallel [(set (match_dup 0) | |
10456 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10457 | (clobber (match_dup 4))]) | |
10458 | (set (match_dup 5) | |
10459 | (compare:CC (match_dup 0) | |
10460 | (const_int 0)))] | |
10461 | "") | |
10462 | ||
1fd4e8c1 | 10463 | (define_insn "" |
cd2b37d9 | 10464 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 10465 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 10466 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
f9562f27 | 10467 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10468 | "@ |
ca7f5001 RK |
10469 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
10470 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
10471 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
10472 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
10473 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 10474 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 10475 | |
ea9be077 MM |
10476 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
10477 | ;; since it nabs/sr is just as fast. | |
463b558b | 10478 | (define_insn "*ne0" |
b4e95693 | 10479 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
10480 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
10481 | (const_int 31))) | |
10482 | (clobber (match_scratch:SI 2 "=&r"))] | |
9ebbca7d | 10483 | "! TARGET_POWER && ! TARGET_POWERPC64" |
ea9be077 MM |
10484 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
10485 | [(set_attr "length" "8")]) | |
10486 | ||
a260abc9 DE |
10487 | (define_insn "" |
10488 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10489 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
10490 | (const_int 63))) | |
10491 | (clobber (match_scratch:DI 2 "=&r"))] | |
10492 | "TARGET_POWERPC64" | |
10493 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
10494 | [(set_attr "length" "8")]) | |
10495 | ||
1fd4e8c1 RK |
10496 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
10497 | (define_insn "" | |
cd2b37d9 | 10498 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10499 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 10500 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10501 | (const_int 31)) |
cd2b37d9 | 10502 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10503 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 10504 | "! TARGET_POWERPC64" |
ca7f5001 | 10505 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 10506 | [(set_attr "length" "8")]) |
1fd4e8c1 | 10507 | |
a260abc9 DE |
10508 | (define_insn "" |
10509 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10510 | (plus:DI (lshiftrt:DI | |
10511 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
10512 | (const_int 63)) | |
10513 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
10514 | (clobber (match_scratch:DI 3 "=&r"))] | |
10515 | "TARGET_POWERPC64" | |
10516 | "addic %3,%1,-1\;addze %0,%2" | |
10517 | [(set_attr "length" "8")]) | |
10518 | ||
1fd4e8c1 | 10519 | (define_insn "" |
9ebbca7d | 10520 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10521 | (compare:CC |
10522 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 10523 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10524 | (const_int 31)) |
9ebbca7d | 10525 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 10526 | (const_int 0))) |
9ebbca7d | 10527 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 10528 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10529 | "@ |
10530 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
10531 | #" | |
b19003d8 | 10532 | [(set_attr "type" "compare") |
9ebbca7d GK |
10533 | (set_attr "length" "8,12")]) |
10534 | ||
10535 | (define_split | |
10536 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10537 | (compare:CC | |
10538 | (plus:SI (lshiftrt:SI | |
10539 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10540 | (const_int 31)) | |
10541 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
10542 | (const_int 0))) | |
10543 | (clobber (match_scratch:SI 3 ""))] | |
10544 | "! TARGET_POWERPC64 && reload_completed" | |
10545 | [(set (match_dup 3) | |
10546 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) | |
10547 | (const_int 31)) | |
10548 | (match_dup 2))) | |
10549 | (set (match_dup 0) | |
10550 | (compare:CC (match_dup 3) | |
10551 | (const_int 0)))] | |
10552 | "") | |
1fd4e8c1 | 10553 | |
a260abc9 | 10554 | (define_insn "" |
9ebbca7d | 10555 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
10556 | (compare:CC |
10557 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 10558 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 10559 | (const_int 63)) |
9ebbca7d | 10560 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 10561 | (const_int 0))) |
9ebbca7d | 10562 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 10563 | "TARGET_POWERPC64" |
9ebbca7d GK |
10564 | "@ |
10565 | addic %3,%1,-1\;addze. %3,%2 | |
10566 | #" | |
a260abc9 | 10567 | [(set_attr "type" "compare") |
9ebbca7d GK |
10568 | (set_attr "length" "8,12")]) |
10569 | ||
10570 | (define_split | |
10571 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10572 | (compare:CC | |
10573 | (plus:DI (lshiftrt:DI | |
10574 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10575 | (const_int 63)) | |
10576 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
10577 | (const_int 0))) | |
10578 | (clobber (match_scratch:DI 3 ""))] | |
10579 | "TARGET_POWERPC64 && reload_completed" | |
10580 | [(set (match_dup 3) | |
10581 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
10582 | (const_int 63)) | |
10583 | (match_dup 2))) | |
10584 | (set (match_dup 0) | |
10585 | (compare:CC (match_dup 3) | |
10586 | (const_int 0)))] | |
10587 | "") | |
a260abc9 | 10588 | |
1fd4e8c1 | 10589 | (define_insn "" |
9ebbca7d | 10590 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10591 | (compare:CC |
10592 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 10593 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10594 | (const_int 31)) |
9ebbca7d | 10595 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 10596 | (const_int 0))) |
9ebbca7d | 10597 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
10598 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
10599 | (match_dup 2))) | |
9ebbca7d | 10600 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 10601 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10602 | "@ |
10603 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
10604 | #" | |
b19003d8 | 10605 | [(set_attr "type" "compare") |
9ebbca7d GK |
10606 | (set_attr "length" "8,12")]) |
10607 | ||
10608 | (define_split | |
10609 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10610 | (compare:CC | |
10611 | (plus:SI (lshiftrt:SI | |
10612 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10613 | (const_int 31)) | |
10614 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
10615 | (const_int 0))) | |
10616 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10617 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
10618 | (match_dup 2))) | |
10619 | (clobber (match_scratch:SI 3 ""))] | |
10620 | "! TARGET_POWERPC64 && reload_completed" | |
10621 | [(parallel [(set (match_dup 0) | |
10622 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
10623 | (match_dup 2))) | |
10624 | (clobber (match_dup 3))]) | |
10625 | (set (match_dup 4) | |
10626 | (compare:CC (match_dup 0) | |
10627 | (const_int 0)))] | |
10628 | "") | |
1fd4e8c1 | 10629 | |
a260abc9 | 10630 | (define_insn "" |
9ebbca7d | 10631 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
10632 | (compare:CC |
10633 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 10634 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 10635 | (const_int 63)) |
9ebbca7d | 10636 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 10637 | (const_int 0))) |
9ebbca7d | 10638 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
10639 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
10640 | (match_dup 2))) | |
9ebbca7d | 10641 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 10642 | "TARGET_POWERPC64" |
9ebbca7d GK |
10643 | "@ |
10644 | addic %3,%1,-1\;addze. %0,%2 | |
10645 | #" | |
a260abc9 | 10646 | [(set_attr "type" "compare") |
9ebbca7d GK |
10647 | (set_attr "length" "8,12")]) |
10648 | ||
10649 | (define_split | |
10650 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10651 | (compare:CC | |
10652 | (plus:DI (lshiftrt:DI | |
10653 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10654 | (const_int 63)) | |
10655 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
10656 | (const_int 0))) | |
10657 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10658 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
10659 | (match_dup 2))) | |
10660 | (clobber (match_scratch:DI 3 ""))] | |
10661 | "TARGET_POWERPC64 && reload_completed" | |
10662 | [(parallel [(set (match_dup 0) | |
10663 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
10664 | (match_dup 2))) | |
10665 | (clobber (match_dup 3))]) | |
10666 | (set (match_dup 4) | |
10667 | (compare:CC (match_dup 0) | |
10668 | (const_int 0)))] | |
10669 | "") | |
a260abc9 | 10670 | |
1fd4e8c1 | 10671 | (define_insn "" |
cd2b37d9 RK |
10672 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10673 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
10674 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
10675 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 10676 | "TARGET_POWER" |
1fd4e8c1 | 10677 | "@ |
ca7f5001 | 10678 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 10679 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 10680 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10681 | |
10682 | (define_insn "" | |
9ebbca7d | 10683 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10684 | (compare:CC |
9ebbca7d GK |
10685 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10686 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 10687 | (const_int 0))) |
9ebbca7d | 10688 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 10689 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10690 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 10691 | "TARGET_POWER" |
1fd4e8c1 | 10692 | "@ |
ca7f5001 | 10693 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
10694 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
10695 | # | |
10696 | #" | |
10697 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
10698 | (set_attr "length" "12,12,16,16")]) | |
10699 | ||
10700 | (define_split | |
10701 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10702 | (compare:CC | |
10703 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10704 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10705 | (const_int 0))) | |
10706 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10707 | (le:SI (match_dup 1) (match_dup 2))) | |
10708 | (clobber (match_scratch:SI 3 ""))] | |
10709 | "TARGET_POWER && reload_completed" | |
10710 | [(parallel [(set (match_dup 0) | |
10711 | (le:SI (match_dup 1) (match_dup 2))) | |
10712 | (clobber (match_dup 3))]) | |
10713 | (set (match_dup 4) | |
10714 | (compare:CC (match_dup 0) | |
10715 | (const_int 0)))] | |
10716 | "") | |
1fd4e8c1 RK |
10717 | |
10718 | (define_insn "" | |
cd2b37d9 RK |
10719 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10720 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 10721 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 10722 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10723 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 10724 | "TARGET_POWER" |
1fd4e8c1 | 10725 | "@ |
ca7f5001 RK |
10726 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
10727 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" | |
b19003d8 | 10728 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10729 | |
10730 | (define_insn "" | |
9ebbca7d | 10731 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10732 | (compare:CC |
9ebbca7d GK |
10733 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10734 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
10735 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 10736 | (const_int 0))) |
9ebbca7d | 10737 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 10738 | "TARGET_POWER" |
1fd4e8c1 | 10739 | "@ |
ca7f5001 | 10740 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
10741 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
10742 | # | |
10743 | #" | |
b19003d8 | 10744 | [(set_attr "type" "compare") |
9ebbca7d GK |
10745 | (set_attr "length" "12,12,16,16")]) |
10746 | ||
10747 | (define_split | |
10748 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10749 | (compare:CC | |
10750 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10751 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10752 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10753 | (const_int 0))) | |
10754 | (clobber (match_scratch:SI 4 ""))] | |
10755 | "TARGET_POWER && reload_completed" | |
10756 | [(set (match_dup 4) | |
10757 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
10758 | (match_dup 3))) | |
10759 | (set (match_dup 0) | |
10760 | (compare:CC (match_dup 4) | |
10761 | (const_int 0)))] | |
10762 | "") | |
1fd4e8c1 RK |
10763 | |
10764 | (define_insn "" | |
9ebbca7d | 10765 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10766 | (compare:CC |
9ebbca7d GK |
10767 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10768 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
10769 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 10770 | (const_int 0))) |
9ebbca7d | 10771 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 10772 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10773 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 10774 | "TARGET_POWER" |
1fd4e8c1 | 10775 | "@ |
ca7f5001 | 10776 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
10777 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3 |
10778 | # | |
10779 | #" | |
b19003d8 | 10780 | [(set_attr "type" "compare") |
9ebbca7d GK |
10781 | (set_attr "length" "12,12,16,16")]) |
10782 | ||
10783 | (define_split | |
10784 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10785 | (compare:CC | |
10786 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10787 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10788 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10789 | (const_int 0))) | |
10790 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10791 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10792 | (clobber (match_scratch:SI 4 ""))] | |
10793 | "TARGET_POWER && reload_completed" | |
10794 | [(parallel [(set (match_dup 0) | |
10795 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10796 | (clobber (match_dup 4))]) | |
10797 | (set (match_dup 5) | |
10798 | (compare:CC (match_dup 0) | |
10799 | (const_int 0)))] | |
10800 | "") | |
1fd4e8c1 RK |
10801 | |
10802 | (define_insn "" | |
cd2b37d9 RK |
10803 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10804 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 10805 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 10806 | "TARGET_POWER" |
1fd4e8c1 | 10807 | "@ |
ca7f5001 RK |
10808 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
10809 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 10810 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10811 | |
10812 | (define_insn "" | |
cd2b37d9 RK |
10813 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10814 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10815 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 10816 | "! TARGET_POWERPC64" |
ca7f5001 | 10817 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 10818 | [(set_attr "length" "12")]) |
1fd4e8c1 | 10819 | |
f9562f27 DE |
10820 | (define_insn "" |
10821 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10822 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
10823 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
10824 | "TARGET_POWERPC64" | |
10825 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" | |
10826 | [(set_attr "length" "12")]) | |
10827 | ||
10828 | (define_insn "" | |
9ebbca7d | 10829 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 10830 | (compare:CC |
9ebbca7d GK |
10831 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
10832 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 10833 | (const_int 0))) |
9ebbca7d | 10834 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
10835 | (leu:DI (match_dup 1) (match_dup 2)))] |
10836 | "TARGET_POWERPC64" | |
9ebbca7d GK |
10837 | "@ |
10838 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
10839 | #" | |
f9562f27 | 10840 | [(set_attr "type" "compare") |
9ebbca7d GK |
10841 | (set_attr "length" "12,16")]) |
10842 | ||
10843 | (define_split | |
10844 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
10845 | (compare:CC | |
10846 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
10847 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
10848 | (const_int 0))) | |
10849 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10850 | (leu:DI (match_dup 1) (match_dup 2)))] | |
10851 | "TARGET_POWERPC64 && reload_completed" | |
10852 | [(set (match_dup 0) | |
10853 | (leu:DI (match_dup 1) (match_dup 2))) | |
10854 | (set (match_dup 3) | |
10855 | (compare:CC (match_dup 0) | |
10856 | (const_int 0)))] | |
10857 | "") | |
f9562f27 | 10858 | |
1fd4e8c1 | 10859 | (define_insn "" |
9ebbca7d | 10860 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10861 | (compare:CC |
9ebbca7d GK |
10862 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10863 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 10864 | (const_int 0))) |
9ebbca7d | 10865 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10866 | (leu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 10867 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10868 | "@ |
10869 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
10870 | #" | |
b19003d8 | 10871 | [(set_attr "type" "compare") |
9ebbca7d GK |
10872 | (set_attr "length" "12,16")]) |
10873 | ||
10874 | (define_split | |
10875 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
10876 | (compare:CC | |
10877 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10878 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10879 | (const_int 0))) | |
10880 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10881 | (leu:SI (match_dup 1) (match_dup 2)))] | |
10882 | "! TARGET_POWERPC64 && reload_completed" | |
10883 | [(set (match_dup 0) | |
10884 | (leu:SI (match_dup 1) (match_dup 2))) | |
10885 | (set (match_dup 3) | |
10886 | (compare:CC (match_dup 0) | |
10887 | (const_int 0)))] | |
10888 | "") | |
1fd4e8c1 | 10889 | |
f9562f27 | 10890 | (define_insn "" |
9ebbca7d | 10891 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 10892 | (compare:CC |
9ebbca7d GK |
10893 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
10894 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 10895 | (const_int 0))) |
9ebbca7d | 10896 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
10897 | (leu:DI (match_dup 1) (match_dup 2)))] |
10898 | "TARGET_POWERPC64" | |
9ebbca7d GK |
10899 | "@ |
10900 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
10901 | #" | |
f9562f27 | 10902 | [(set_attr "type" "compare") |
9ebbca7d | 10903 | (set_attr "length" "12,16")]) |
f9562f27 | 10904 | |
1fd4e8c1 | 10905 | (define_insn "" |
cd2b37d9 RK |
10906 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10907 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10908 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 10909 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10910 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 10911 | "! TARGET_POWERPC64" |
ca7f5001 | 10912 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 10913 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
10914 | |
10915 | (define_insn "" | |
9ebbca7d | 10916 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10917 | (compare:CC |
9ebbca7d GK |
10918 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10919 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
10920 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10921 | (const_int 0))) |
9ebbca7d | 10922 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 10923 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10924 | "@ |
10925 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
10926 | #" | |
b19003d8 | 10927 | [(set_attr "type" "compare") |
9ebbca7d GK |
10928 | (set_attr "length" "8,12")]) |
10929 | ||
10930 | (define_split | |
10931 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10932 | (compare:CC | |
10933 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10934 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10935 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10936 | (const_int 0))) | |
10937 | (clobber (match_scratch:SI 4 ""))] | |
10938 | "! TARGET_POWERPC64 && reload_completed" | |
10939 | [(set (match_dup 4) | |
10940 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
10941 | (match_dup 3))) | |
10942 | (set (match_dup 0) | |
10943 | (compare:CC (match_dup 4) | |
10944 | (const_int 0)))] | |
10945 | "") | |
1fd4e8c1 RK |
10946 | |
10947 | (define_insn "" | |
9ebbca7d | 10948 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10949 | (compare:CC |
9ebbca7d GK |
10950 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10951 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
10952 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10953 | (const_int 0))) |
9ebbca7d | 10954 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10955 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10956 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 10957 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10958 | "@ |
10959 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3 | |
10960 | #" | |
b19003d8 | 10961 | [(set_attr "type" "compare") |
9ebbca7d GK |
10962 | (set_attr "length" "8,12")]) |
10963 | ||
10964 | (define_split | |
10965 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10966 | (compare:CC | |
10967 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10968 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10969 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10970 | (const_int 0))) | |
10971 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10972 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10973 | (clobber (match_scratch:SI 4 ""))] | |
10974 | "! TARGET_POWERPC64 && reload_completed" | |
10975 | [(parallel [(set (match_dup 0) | |
10976 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10977 | (clobber (match_dup 4))]) | |
10978 | (set (match_dup 5) | |
10979 | (compare:CC (match_dup 0) | |
10980 | (const_int 0)))] | |
10981 | "") | |
1fd4e8c1 RK |
10982 | |
10983 | (define_insn "" | |
cd2b37d9 RK |
10984 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10985 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10986 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 10987 | "! TARGET_POWERPC64" |
ca7f5001 | 10988 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 10989 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10990 | |
10991 | (define_insn "" | |
cd2b37d9 | 10992 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10993 | (and:SI (neg:SI |
cd2b37d9 | 10994 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10995 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 10996 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10997 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 10998 | "! TARGET_POWERPC64" |
ca7f5001 | 10999 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" |
b19003d8 | 11000 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11001 | |
11002 | (define_insn "" | |
9ebbca7d | 11003 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11004 | (compare:CC |
11005 | (and:SI (neg:SI | |
9ebbca7d GK |
11006 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11007 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11008 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11009 | (const_int 0))) |
9ebbca7d | 11010 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11011 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11012 | "@ |
11013 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
11014 | #" | |
11015 | [(set_attr "type" "compare") | |
11016 | (set_attr "length" "12,16")]) | |
11017 | ||
11018 | (define_split | |
11019 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11020 | (compare:CC | |
11021 | (and:SI (neg:SI | |
11022 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11023 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11024 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11025 | (const_int 0))) | |
11026 | (clobber (match_scratch:SI 4 ""))] | |
11027 | "! TARGET_POWERPC64 && reload_completed" | |
11028 | [(set (match_dup 4) | |
11029 | (and:SI (neg:SI (leu:SI (match_dup 1) | |
11030 | (match_dup 2))) | |
11031 | (match_dup 3))) | |
11032 | (set (match_dup 0) | |
11033 | (compare:CC (match_dup 4) | |
11034 | (const_int 0)))] | |
11035 | "") | |
1fd4e8c1 RK |
11036 | |
11037 | (define_insn "" | |
9ebbca7d | 11038 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11039 | (compare:CC |
11040 | (and:SI (neg:SI | |
9ebbca7d GK |
11041 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11042 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11043 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11044 | (const_int 0))) |
9ebbca7d | 11045 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11046 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 11047 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11048 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11049 | "@ |
11050 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 | |
11051 | #" | |
b19003d8 | 11052 | [(set_attr "type" "compare") |
9ebbca7d GK |
11053 | (set_attr "length" "12,16")]) |
11054 | ||
11055 | (define_split | |
11056 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11057 | (compare:CC | |
11058 | (and:SI (neg:SI | |
11059 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11060 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11061 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11062 | (const_int 0))) | |
11063 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11064 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11065 | (clobber (match_scratch:SI 4 ""))] | |
11066 | "! TARGET_POWERPC64 && reload_completed" | |
11067 | [(parallel [(set (match_dup 0) | |
11068 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11069 | (clobber (match_dup 4))]) | |
11070 | (set (match_dup 5) | |
11071 | (compare:CC (match_dup 0) | |
11072 | (const_int 0)))] | |
11073 | "") | |
1fd4e8c1 RK |
11074 | |
11075 | (define_insn "" | |
cd2b37d9 RK |
11076 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11077 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11078 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 11079 | "TARGET_POWER" |
7f340546 | 11080 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11081 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11082 | |
11083 | (define_insn "" | |
9ebbca7d | 11084 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11085 | (compare:CC |
9ebbca7d GK |
11086 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11087 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11088 | (const_int 0))) |
9ebbca7d | 11089 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11090 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11091 | "TARGET_POWER" |
9ebbca7d GK |
11092 | "@ |
11093 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11094 | #" | |
29ae5b89 | 11095 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11096 | (set_attr "length" "12,16")]) |
11097 | ||
11098 | (define_split | |
11099 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11100 | (compare:CC | |
11101 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11102 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11103 | (const_int 0))) | |
11104 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11105 | (lt:SI (match_dup 1) (match_dup 2)))] | |
11106 | "TARGET_POWER && reload_completed" | |
11107 | [(set (match_dup 0) | |
11108 | (lt:SI (match_dup 1) (match_dup 2))) | |
11109 | (set (match_dup 3) | |
11110 | (compare:CC (match_dup 0) | |
11111 | (const_int 0)))] | |
11112 | "") | |
1fd4e8c1 RK |
11113 | |
11114 | (define_insn "" | |
cd2b37d9 RK |
11115 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11116 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11117 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11118 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11119 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11120 | "TARGET_POWER" |
11121 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 11122 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11123 | |
11124 | (define_insn "" | |
9ebbca7d | 11125 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11126 | (compare:CC |
9ebbca7d GK |
11127 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11128 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11129 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11130 | (const_int 0))) |
9ebbca7d | 11131 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11132 | "TARGET_POWER" |
9ebbca7d GK |
11133 | "@ |
11134 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
11135 | #" | |
b19003d8 | 11136 | [(set_attr "type" "compare") |
9ebbca7d GK |
11137 | (set_attr "length" "12,16")]) |
11138 | ||
11139 | (define_split | |
11140 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11141 | (compare:CC | |
11142 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11143 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11144 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11145 | (const_int 0))) | |
11146 | (clobber (match_scratch:SI 4 ""))] | |
11147 | "TARGET_POWER && reload_completed" | |
11148 | [(set (match_dup 4) | |
11149 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
11150 | (match_dup 3))) | |
11151 | (set (match_dup 0) | |
11152 | (compare:CC (match_dup 4) | |
11153 | (const_int 0)))] | |
11154 | "") | |
1fd4e8c1 RK |
11155 | |
11156 | (define_insn "" | |
9ebbca7d | 11157 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11158 | (compare:CC |
9ebbca7d GK |
11159 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11160 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11161 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11162 | (const_int 0))) |
9ebbca7d | 11163 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11164 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11165 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11166 | "TARGET_POWER" |
9ebbca7d GK |
11167 | "@ |
11168 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
11169 | #" | |
b19003d8 | 11170 | [(set_attr "type" "compare") |
9ebbca7d GK |
11171 | (set_attr "length" "12,16")]) |
11172 | ||
11173 | (define_split | |
11174 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11175 | (compare:CC | |
11176 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11177 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11178 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11179 | (const_int 0))) | |
11180 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11181 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11182 | (clobber (match_scratch:SI 4 ""))] | |
11183 | "TARGET_POWER && reload_completed" | |
11184 | [(parallel [(set (match_dup 0) | |
11185 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11186 | (clobber (match_dup 4))]) | |
11187 | (set (match_dup 5) | |
11188 | (compare:CC (match_dup 0) | |
11189 | (const_int 0)))] | |
11190 | "") | |
1fd4e8c1 RK |
11191 | |
11192 | (define_insn "" | |
cd2b37d9 RK |
11193 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11194 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11195 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11196 | "TARGET_POWER" |
11197 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11198 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11199 | |
11200 | (define_insn "" | |
cd2b37d9 RK |
11201 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11202 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11203 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11204 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11205 | "@ |
ca7f5001 RK |
11206 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
11207 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 11208 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11209 | |
11210 | (define_insn "" | |
9ebbca7d | 11211 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11212 | (compare:CC |
9ebbca7d GK |
11213 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11214 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 11215 | (const_int 0))) |
9ebbca7d | 11216 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11217 | (ltu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11218 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11219 | "@ |
ca7f5001 | 11220 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
11221 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
11222 | # | |
11223 | #" | |
b19003d8 | 11224 | [(set_attr "type" "compare") |
9ebbca7d GK |
11225 | (set_attr "length" "12,12,16,16")]) |
11226 | ||
11227 | (define_split | |
11228 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11229 | (compare:CC | |
11230 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11231 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11232 | (const_int 0))) | |
11233 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11234 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
11235 | "! TARGET_POWERPC64 && reload_completed" | |
11236 | [(set (match_dup 0) | |
11237 | (ltu:SI (match_dup 1) (match_dup 2))) | |
11238 | (set (match_dup 3) | |
11239 | (compare:CC (match_dup 0) | |
11240 | (const_int 0)))] | |
11241 | "") | |
1fd4e8c1 RK |
11242 | |
11243 | (define_insn "" | |
19378cf8 MM |
11244 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11245 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
11246 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
11247 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI"))) | |
11248 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 11249 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11250 | "@ |
ca7f5001 | 11251 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 |
04be6346 | 11252 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
b19003d8 | 11253 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11254 | |
11255 | (define_insn "" | |
9ebbca7d | 11256 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11257 | (compare:CC |
9ebbca7d GK |
11258 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11259 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11260 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11261 | (const_int 0))) |
9ebbca7d | 11262 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11263 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11264 | "@ |
ca7f5001 | 11265 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
11266 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
11267 | # | |
11268 | #" | |
b19003d8 | 11269 | [(set_attr "type" "compare") |
9ebbca7d GK |
11270 | (set_attr "length" "12,12,16,16")]) |
11271 | ||
11272 | (define_split | |
11273 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11274 | (compare:CC | |
11275 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11276 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11277 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11278 | (const_int 0))) | |
11279 | (clobber (match_scratch:SI 4 ""))] | |
11280 | "! TARGET_POWERPC64 && reload_completed" | |
11281 | [(set (match_dup 4) | |
11282 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
11283 | (match_dup 3))) | |
11284 | (set (match_dup 0) | |
11285 | (compare:CC (match_dup 4) | |
11286 | (const_int 0)))] | |
11287 | "") | |
1fd4e8c1 RK |
11288 | |
11289 | (define_insn "" | |
9ebbca7d | 11290 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11291 | (compare:CC |
9ebbca7d GK |
11292 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11293 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11294 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11295 | (const_int 0))) |
9ebbca7d | 11296 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11297 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11298 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11299 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11300 | "@ |
ca7f5001 | 11301 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
9ebbca7d GK |
11302 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
11303 | # | |
11304 | #" | |
b19003d8 | 11305 | [(set_attr "type" "compare") |
9ebbca7d GK |
11306 | (set_attr "length" "12,12,16,16")]) |
11307 | ||
11308 | (define_split | |
11309 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11310 | (compare:CC | |
11311 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11312 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11313 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11314 | (const_int 0))) | |
11315 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11316 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11317 | (clobber (match_scratch:SI 4 ""))] | |
11318 | "! TARGET_POWERPC64 && reload_completed" | |
11319 | [(parallel [(set (match_dup 0) | |
11320 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11321 | (clobber (match_dup 4))]) | |
11322 | (set (match_dup 5) | |
11323 | (compare:CC (match_dup 0) | |
11324 | (const_int 0)))] | |
11325 | "") | |
1fd4e8c1 RK |
11326 | |
11327 | (define_insn "" | |
cd2b37d9 RK |
11328 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11329 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11330 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
f9562f27 | 11331 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11332 | "@ |
ca7f5001 RK |
11333 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
11334 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11335 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11336 | |
11337 | (define_insn "" | |
cd2b37d9 RK |
11338 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11339 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
11340 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
11341 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
11342 | "TARGET_POWER" |
11343 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 11344 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11345 | |
9ebbca7d GK |
11346 | (define_insn "" |
11347 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11348 | (compare:CC |
9ebbca7d GK |
11349 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11350 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11351 | (const_int 0))) |
9ebbca7d | 11352 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11353 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11354 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 11355 | "TARGET_POWER" |
9ebbca7d GK |
11356 | "@ |
11357 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
11358 | #" | |
11359 | [(set_attr "type" "compare") | |
11360 | (set_attr "length" "12,16")]) | |
11361 | ||
11362 | (define_split | |
11363 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11364 | (compare:CC | |
11365 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11366 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11367 | (const_int 0))) | |
11368 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11369 | (ge:SI (match_dup 1) (match_dup 2))) | |
11370 | (clobber (match_scratch:SI 3 ""))] | |
11371 | "TARGET_POWER && reload_completed" | |
11372 | [(parallel [(set (match_dup 0) | |
11373 | (ge:SI (match_dup 1) (match_dup 2))) | |
11374 | (clobber (match_dup 3))]) | |
11375 | (set (match_dup 4) | |
11376 | (compare:CC (match_dup 0) | |
11377 | (const_int 0)))] | |
11378 | "") | |
11379 | ||
1fd4e8c1 | 11380 | (define_insn "" |
cd2b37d9 RK |
11381 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11382 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11383 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11384 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11385 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11386 | "TARGET_POWER" |
11387 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" | |
b19003d8 | 11388 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11389 | |
11390 | (define_insn "" | |
9ebbca7d | 11391 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11392 | (compare:CC |
9ebbca7d GK |
11393 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11394 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11395 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11396 | (const_int 0))) |
9ebbca7d | 11397 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11398 | "TARGET_POWER" |
9ebbca7d GK |
11399 | "@ |
11400 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
11401 | #" | |
b19003d8 | 11402 | [(set_attr "type" "compare") |
9ebbca7d GK |
11403 | (set_attr "length" "12,16")]) |
11404 | ||
11405 | (define_split | |
11406 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11407 | (compare:CC | |
11408 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11409 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11410 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11411 | (const_int 0))) | |
11412 | (clobber (match_scratch:SI 4 ""))] | |
11413 | "TARGET_POWER && reload_completed" | |
11414 | [(set (match_dup 4) | |
11415 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
11416 | (match_dup 3))) | |
11417 | (set (match_dup 0) | |
11418 | (compare:CC (match_dup 4) | |
11419 | (const_int 0)))] | |
11420 | "") | |
1fd4e8c1 RK |
11421 | |
11422 | (define_insn "" | |
9ebbca7d | 11423 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11424 | (compare:CC |
9ebbca7d GK |
11425 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11426 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11427 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11428 | (const_int 0))) |
9ebbca7d | 11429 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11430 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11431 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11432 | "TARGET_POWER" |
9ebbca7d GK |
11433 | "@ |
11434 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
11435 | #" | |
b19003d8 | 11436 | [(set_attr "type" "compare") |
9ebbca7d GK |
11437 | (set_attr "length" "12,16")]) |
11438 | ||
11439 | (define_split | |
11440 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11441 | (compare:CC | |
11442 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11443 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11444 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11445 | (const_int 0))) | |
11446 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11447 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11448 | (clobber (match_scratch:SI 4 ""))] | |
11449 | "TARGET_POWER && reload_completed" | |
11450 | [(parallel [(set (match_dup 0) | |
11451 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11452 | (clobber (match_dup 4))]) | |
11453 | (set (match_dup 5) | |
11454 | (compare:CC (match_dup 0) | |
11455 | (const_int 0)))] | |
11456 | "") | |
1fd4e8c1 RK |
11457 | |
11458 | (define_insn "" | |
cd2b37d9 RK |
11459 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11460 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11461 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11462 | "TARGET_POWER" |
11463 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11464 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11465 | |
1fd4e8c1 | 11466 | (define_insn "" |
cd2b37d9 RK |
11467 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11468 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11469 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11470 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11471 | "@ |
ca7f5001 RK |
11472 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
11473 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 11474 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11475 | |
f9562f27 DE |
11476 | (define_insn "" |
11477 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
11478 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
11479 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
11480 | "TARGET_POWERPC64" | |
11481 | "@ | |
11482 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
11483 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
11484 | [(set_attr "length" "12")]) | |
11485 | ||
1fd4e8c1 | 11486 | (define_insn "" |
9ebbca7d | 11487 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11488 | (compare:CC |
9ebbca7d GK |
11489 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11490 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 11491 | (const_int 0))) |
9ebbca7d | 11492 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11493 | (geu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11494 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11495 | "@ |
ca7f5001 | 11496 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
11497 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
11498 | # | |
11499 | #" | |
b19003d8 | 11500 | [(set_attr "type" "compare") |
9ebbca7d GK |
11501 | (set_attr "length" "12,12,16,16")]) |
11502 | ||
11503 | (define_split | |
11504 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11505 | (compare:CC | |
11506 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11507 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11508 | (const_int 0))) | |
11509 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11510 | (geu:SI (match_dup 1) (match_dup 2)))] | |
11511 | "! TARGET_POWERPC64 && reload_completed" | |
11512 | [(set (match_dup 0) | |
11513 | (geu:SI (match_dup 1) (match_dup 2))) | |
11514 | (set (match_dup 3) | |
11515 | (compare:CC (match_dup 0) | |
11516 | (const_int 0)))] | |
11517 | "") | |
1fd4e8c1 | 11518 | |
f9562f27 | 11519 | (define_insn "" |
9ebbca7d | 11520 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 11521 | (compare:CC |
9ebbca7d GK |
11522 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
11523 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 11524 | (const_int 0))) |
9ebbca7d | 11525 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 DE |
11526 | (geu:DI (match_dup 1) (match_dup 2)))] |
11527 | "TARGET_POWERPC64" | |
11528 | "@ | |
11529 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
11530 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
11531 | # | |
11532 | #" | |
f9562f27 | 11533 | [(set_attr "type" "compare") |
9ebbca7d GK |
11534 | (set_attr "length" "12,12,16,16")]) |
11535 | ||
11536 | (define_split | |
11537 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11538 | (compare:CC | |
11539 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11540 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
11541 | (const_int 0))) | |
11542 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11543 | (geu:DI (match_dup 1) (match_dup 2)))] | |
11544 | "TARGET_POWERPC64 && reload_completed" | |
11545 | [(set (match_dup 0) | |
11546 | (geu:DI (match_dup 1) (match_dup 2))) | |
11547 | (set (match_dup 3) | |
11548 | (compare:CC (match_dup 0) | |
11549 | (const_int 0)))] | |
11550 | "") | |
f9562f27 | 11551 | |
1fd4e8c1 | 11552 | (define_insn "" |
cd2b37d9 RK |
11553 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11554 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11555 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 11556 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11557 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11558 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11559 | "@ |
ca7f5001 RK |
11560 | {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 |
11561 | {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 11562 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11563 | |
11564 | (define_insn "" | |
9ebbca7d | 11565 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11566 | (compare:CC |
9ebbca7d GK |
11567 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11568 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11569 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11570 | (const_int 0))) |
9ebbca7d | 11571 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11572 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11573 | "@ |
ca7f5001 | 11574 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11575 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
11576 | # | |
11577 | #" | |
b19003d8 | 11578 | [(set_attr "type" "compare") |
9ebbca7d GK |
11579 | (set_attr "length" "8,8,12,12")]) |
11580 | ||
11581 | (define_split | |
11582 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11583 | (compare:CC | |
11584 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11585 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11586 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11587 | (const_int 0))) | |
11588 | (clobber (match_scratch:SI 4 ""))] | |
11589 | "! TARGET_POWERPC64 && reload_completed" | |
11590 | [(set (match_dup 4) | |
11591 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
11592 | (match_dup 3))) | |
11593 | (set (match_dup 0) | |
11594 | (compare:CC (match_dup 4) | |
11595 | (const_int 0)))] | |
11596 | "") | |
1fd4e8c1 RK |
11597 | |
11598 | (define_insn "" | |
9ebbca7d | 11599 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11600 | (compare:CC |
9ebbca7d GK |
11601 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11602 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11603 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11604 | (const_int 0))) |
9ebbca7d | 11605 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11606 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11607 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11608 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11609 | "@ |
ca7f5001 | 11610 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
11611 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3 |
11612 | # | |
11613 | #" | |
b19003d8 | 11614 | [(set_attr "type" "compare") |
9ebbca7d GK |
11615 | (set_attr "length" "8,8,12,12")]) |
11616 | ||
11617 | (define_split | |
11618 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11619 | (compare:CC | |
11620 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11621 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11622 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11623 | (const_int 0))) | |
11624 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11625 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11626 | (clobber (match_scratch:SI 4 ""))] | |
11627 | "! TARGET_POWERPC64 && reload_completed" | |
11628 | [(parallel [(set (match_dup 0) | |
11629 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11630 | (clobber (match_dup 4))]) | |
11631 | (set (match_dup 5) | |
11632 | (compare:CC (match_dup 0) | |
11633 | (const_int 0)))] | |
11634 | "") | |
1fd4e8c1 RK |
11635 | |
11636 | (define_insn "" | |
cd2b37d9 RK |
11637 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11638 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11639 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
f9562f27 | 11640 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11641 | "@ |
ca7f5001 | 11642 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 11643 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 11644 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11645 | |
11646 | (define_insn "" | |
cd2b37d9 | 11647 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11648 | (and:SI (neg:SI |
cd2b37d9 | 11649 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11650 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 11651 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11652 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11653 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11654 | "@ |
ca7f5001 RK |
11655 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 |
11656 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" | |
b19003d8 | 11657 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11658 | |
11659 | (define_insn "" | |
9ebbca7d | 11660 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
11661 | (compare:CC |
11662 | (and:SI (neg:SI | |
9ebbca7d GK |
11663 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11664 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
11665 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11666 | (const_int 0))) |
9ebbca7d | 11667 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11668 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11669 | "@ |
ca7f5001 | 11670 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
11671 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
11672 | # | |
11673 | #" | |
b19003d8 | 11674 | [(set_attr "type" "compare") |
9ebbca7d GK |
11675 | (set_attr "length" "12,12,16,16")]) |
11676 | ||
11677 | (define_split | |
11678 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11679 | (compare:CC | |
11680 | (and:SI (neg:SI | |
11681 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11682 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
11683 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11684 | (const_int 0))) | |
11685 | (clobber (match_scratch:SI 4 ""))] | |
11686 | "! TARGET_POWERPC64 && reload_completed" | |
11687 | [(set (match_dup 4) | |
11688 | (and:SI (neg:SI (geu:SI (match_dup 1) | |
11689 | (match_dup 2))) | |
11690 | (match_dup 3))) | |
11691 | (set (match_dup 0) | |
11692 | (compare:CC (match_dup 4) | |
11693 | (const_int 0)))] | |
11694 | "") | |
1fd4e8c1 RK |
11695 | |
11696 | (define_insn "" | |
9ebbca7d | 11697 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
11698 | (compare:CC |
11699 | (and:SI (neg:SI | |
9ebbca7d GK |
11700 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11701 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
11702 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11703 | (const_int 0))) |
9ebbca7d | 11704 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11705 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 11706 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11707 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11708 | "@ |
ca7f5001 | 11709 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
9ebbca7d GK |
11710 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
11711 | # | |
11712 | #" | |
b19003d8 | 11713 | [(set_attr "type" "compare") |
9ebbca7d GK |
11714 | (set_attr "length" "12,12,16,16")]) |
11715 | ||
11716 | (define_split | |
11717 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11718 | (compare:CC | |
11719 | (and:SI (neg:SI | |
11720 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11721 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
11722 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11723 | (const_int 0))) | |
11724 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11725 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11726 | (clobber (match_scratch:SI 4 ""))] | |
11727 | "! TARGET_POWERPC64 && reload_completed" | |
11728 | [(parallel [(set (match_dup 0) | |
11729 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11730 | (clobber (match_dup 4))]) | |
11731 | (set (match_dup 5) | |
11732 | (compare:CC (match_dup 0) | |
11733 | (const_int 0)))] | |
11734 | "") | |
1fd4e8c1 RK |
11735 | |
11736 | (define_insn "" | |
cd2b37d9 RK |
11737 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11738 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11739 | (const_int 0)))] |
f9562f27 | 11740 | "! TARGET_POWERPC64" |
ca7f5001 | 11741 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11742 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11743 | |
f9562f27 DE |
11744 | (define_insn "" |
11745 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11746 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11747 | (const_int 0)))] | |
11748 | "TARGET_POWERPC64" | |
11749 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" | |
11750 | [(set_attr "length" "12")]) | |
11751 | ||
1fd4e8c1 | 11752 | (define_insn "" |
9ebbca7d | 11753 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11754 | (compare:CC |
9ebbca7d | 11755 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
11756 | (const_int 0)) |
11757 | (const_int 0))) | |
9ebbca7d | 11758 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11759 | (gt:SI (match_dup 1) (const_int 0)))] |
f9562f27 | 11760 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11761 | "@ |
11762 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
11763 | #" | |
29ae5b89 | 11764 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11765 | (set_attr "length" "12,16")]) |
11766 | ||
11767 | (define_split | |
11768 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
11769 | (compare:CC | |
11770 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11771 | (const_int 0)) | |
11772 | (const_int 0))) | |
11773 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11774 | (gt:SI (match_dup 1) (const_int 0)))] | |
11775 | "! TARGET_POWERPC64 && reload_completed" | |
11776 | [(set (match_dup 0) | |
11777 | (gt:SI (match_dup 1) (const_int 0))) | |
11778 | (set (match_dup 2) | |
11779 | (compare:CC (match_dup 0) | |
11780 | (const_int 0)))] | |
11781 | "") | |
1fd4e8c1 | 11782 | |
f9562f27 | 11783 | (define_insn "" |
9ebbca7d | 11784 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 11785 | (compare:CC |
9ebbca7d | 11786 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
11787 | (const_int 0)) |
11788 | (const_int 0))) | |
9ebbca7d | 11789 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11790 | (gt:DI (match_dup 1) (const_int 0)))] |
11791 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11792 | "@ |
11793 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
11794 | #" | |
f9562f27 | 11795 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11796 | (set_attr "length" "12,16")]) |
11797 | ||
11798 | (define_split | |
11799 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
11800 | (compare:CC | |
11801 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11802 | (const_int 0)) | |
11803 | (const_int 0))) | |
11804 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11805 | (gt:DI (match_dup 1) (const_int 0)))] | |
11806 | "TARGET_POWERPC64 && reload_completed" | |
11807 | [(set (match_dup 0) | |
11808 | (gt:DI (match_dup 1) (const_int 0))) | |
11809 | (set (match_dup 2) | |
11810 | (compare:CC (match_dup 0) | |
11811 | (const_int 0)))] | |
11812 | "") | |
f9562f27 | 11813 | |
1fd4e8c1 | 11814 | (define_insn "" |
cd2b37d9 RK |
11815 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11816 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11817 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
11818 | "TARGET_POWER" |
11819 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 11820 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11821 | |
11822 | (define_insn "" | |
9ebbca7d | 11823 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11824 | (compare:CC |
9ebbca7d GK |
11825 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11826 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 11827 | (const_int 0))) |
9ebbca7d | 11828 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11829 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11830 | "TARGET_POWER" |
9ebbca7d GK |
11831 | "@ |
11832 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11833 | #" | |
29ae5b89 | 11834 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11835 | (set_attr "length" "12,16")]) |
11836 | ||
11837 | (define_split | |
11838 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11839 | (compare:CC | |
11840 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11841 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11842 | (const_int 0))) | |
11843 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11844 | (gt:SI (match_dup 1) (match_dup 2)))] | |
11845 | "TARGET_POWER && reload_completed" | |
11846 | [(set (match_dup 0) | |
11847 | (gt:SI (match_dup 1) (match_dup 2))) | |
11848 | (set (match_dup 3) | |
11849 | (compare:CC (match_dup 0) | |
11850 | (const_int 0)))] | |
11851 | "") | |
1fd4e8c1 RK |
11852 | |
11853 | (define_insn "" | |
cd2b37d9 RK |
11854 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11855 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11856 | (const_int 0)) |
cd2b37d9 | 11857 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11858 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 11859 | "! TARGET_POWERPC64" |
ca7f5001 | 11860 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" |
b19003d8 | 11861 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11862 | |
f9562f27 DE |
11863 | (define_insn "" |
11864 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11865 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11866 | (const_int 0)) | |
11867 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11868 | (clobber (match_scratch:DI 3 "=&r"))] | |
11869 | "TARGET_POWERPC64" | |
11870 | "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2" | |
11871 | [(set_attr "length" "12")]) | |
11872 | ||
1fd4e8c1 | 11873 | (define_insn "" |
9ebbca7d | 11874 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11875 | (compare:CC |
9ebbca7d | 11876 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11877 | (const_int 0)) |
9ebbca7d | 11878 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11879 | (const_int 0))) |
9ebbca7d | 11880 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 11881 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11882 | "@ |
11883 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
11884 | #" | |
b19003d8 | 11885 | [(set_attr "type" "compare") |
9ebbca7d GK |
11886 | (set_attr "length" "12,16")]) |
11887 | ||
11888 | (define_split | |
11889 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11890 | (compare:CC | |
11891 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11892 | (const_int 0)) | |
11893 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11894 | (const_int 0))) | |
11895 | (clobber (match_scratch:SI 3 ""))] | |
11896 | "! TARGET_POWERPC64 && reload_completed" | |
11897 | [(set (match_dup 3) | |
11898 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
11899 | (match_dup 2))) | |
11900 | (set (match_dup 0) | |
11901 | (compare:CC (match_dup 3) | |
11902 | (const_int 0)))] | |
11903 | "") | |
1fd4e8c1 | 11904 | |
f9562f27 | 11905 | (define_insn "" |
9ebbca7d | 11906 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 11907 | (compare:CC |
9ebbca7d | 11908 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 11909 | (const_int 0)) |
9ebbca7d | 11910 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 11911 | (const_int 0))) |
9ebbca7d | 11912 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 11913 | "TARGET_POWERPC64" |
9ebbca7d GK |
11914 | "@ |
11915 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
11916 | #" | |
f9562f27 | 11917 | [(set_attr "type" "compare") |
9ebbca7d GK |
11918 | (set_attr "length" "12,16")]) |
11919 | ||
11920 | (define_split | |
11921 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11922 | (compare:CC | |
11923 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11924 | (const_int 0)) | |
11925 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11926 | (const_int 0))) | |
11927 | (clobber (match_scratch:DI 3 ""))] | |
11928 | "TARGET_POWERPC64 && reload_completed" | |
11929 | [(set (match_dup 3) | |
11930 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
11931 | (match_dup 2))) | |
11932 | (set (match_dup 0) | |
11933 | (compare:CC (match_dup 3) | |
11934 | (const_int 0)))] | |
11935 | "") | |
f9562f27 | 11936 | |
1fd4e8c1 | 11937 | (define_insn "" |
9ebbca7d GK |
11938 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
11939 | (compare:CC | |
11940 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
11941 | (const_int 0)) | |
11942 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
11943 | (const_int 0))) | |
11944 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
11945 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11946 | (clobber (match_scratch:SI 3 "=&r,&r"))] | |
11947 | "! TARGET_POWERPC64" | |
11948 | "@ | |
11949 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2 | |
11950 | #" | |
11951 | [(set_attr "type" "compare") | |
11952 | (set_attr "length" "12,16")]) | |
11953 | ||
11954 | (define_split | |
11955 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
1fd4e8c1 | 11956 | (compare:CC |
9ebbca7d | 11957 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11958 | (const_int 0)) |
9ebbca7d | 11959 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 11960 | (const_int 0))) |
9ebbca7d | 11961 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 11962 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d GK |
11963 | (clobber (match_scratch:SI 3 ""))] |
11964 | "! TARGET_POWERPC64 && reload_completed" | |
11965 | [(parallel [(set (match_dup 0) | |
11966 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11967 | (clobber (match_dup 3))]) | |
11968 | (set (match_dup 4) | |
11969 | (compare:CC (match_dup 0) | |
11970 | (const_int 0)))] | |
11971 | "") | |
1fd4e8c1 | 11972 | |
f9562f27 | 11973 | (define_insn "" |
9ebbca7d | 11974 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
f9562f27 | 11975 | (compare:CC |
9ebbca7d | 11976 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 11977 | (const_int 0)) |
9ebbca7d | 11978 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 11979 | (const_int 0))) |
9ebbca7d | 11980 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 11981 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d | 11982 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 11983 | "TARGET_POWERPC64" |
9ebbca7d GK |
11984 | "@ |
11985 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2 | |
11986 | #" | |
f9562f27 | 11987 | [(set_attr "type" "compare") |
9ebbca7d GK |
11988 | (set_attr "length" "12,16")]) |
11989 | ||
11990 | (define_split | |
11991 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11992 | (compare:CC | |
11993 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11994 | (const_int 0)) | |
11995 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11996 | (const_int 0))) | |
11997 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11998 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11999 | (clobber (match_scratch:DI 3 ""))] | |
12000 | "TARGET_POWERPC64 && reload_completed" | |
12001 | [(parallel [(set (match_dup 0) | |
12002 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
12003 | (clobber (match_dup 3))]) | |
12004 | (set (match_dup 4) | |
12005 | (compare:CC (match_dup 0) | |
12006 | (const_int 0)))] | |
12007 | "") | |
f9562f27 | 12008 | |
1fd4e8c1 | 12009 | (define_insn "" |
cd2b37d9 RK |
12010 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12011 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12012 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 12013 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 12014 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
12015 | "TARGET_POWER" |
12016 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 12017 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12018 | |
12019 | (define_insn "" | |
9ebbca7d | 12020 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12021 | (compare:CC |
9ebbca7d GK |
12022 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12023 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12024 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12025 | (const_int 0))) |
9ebbca7d | 12026 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12027 | "TARGET_POWER" |
9ebbca7d GK |
12028 | "@ |
12029 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12030 | #" | |
b19003d8 | 12031 | [(set_attr "type" "compare") |
9ebbca7d GK |
12032 | (set_attr "length" "12,16")]) |
12033 | ||
12034 | (define_split | |
12035 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12036 | (compare:CC | |
12037 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12038 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12039 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12040 | (const_int 0))) | |
12041 | (clobber (match_scratch:SI 4 ""))] | |
12042 | "TARGET_POWER && reload_completed" | |
12043 | [(set (match_dup 4) | |
12044 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) | |
12045 | (match_dup 3))) | |
12046 | (set (match_dup 0) | |
12047 | (compare:CC (match_dup 4) | |
12048 | (const_int 0)))] | |
12049 | "") | |
1fd4e8c1 RK |
12050 | |
12051 | (define_insn "" | |
9ebbca7d | 12052 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12053 | (compare:CC |
9ebbca7d GK |
12054 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12055 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12056 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12057 | (const_int 0))) |
9ebbca7d | 12058 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12059 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12060 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12061 | "TARGET_POWER" |
9ebbca7d GK |
12062 | "@ |
12063 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
12064 | #" | |
b19003d8 | 12065 | [(set_attr "type" "compare") |
9ebbca7d GK |
12066 | (set_attr "length" "12,16")]) |
12067 | ||
12068 | (define_split | |
12069 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12070 | (compare:CC | |
12071 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12072 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12073 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12074 | (const_int 0))) | |
12075 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12076 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12077 | (clobber (match_scratch:SI 4 ""))] | |
12078 | "TARGET_POWER && reload_completed" | |
12079 | [(parallel [(set (match_dup 0) | |
12080 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12081 | (clobber (match_dup 4))]) | |
12082 | (set (match_dup 5) | |
12083 | (compare:CC (match_dup 0) | |
12084 | (const_int 0)))] | |
12085 | "") | |
1fd4e8c1 RK |
12086 | |
12087 | (define_insn "" | |
cd2b37d9 RK |
12088 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12089 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12090 | (const_int 0))))] |
f9562f27 | 12091 | "! TARGET_POWERPC64" |
ca7f5001 | 12092 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 12093 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12094 | |
f9562f27 DE |
12095 | (define_insn "" |
12096 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12097 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12098 | (const_int 0))))] | |
12099 | "TARGET_POWERPC64" | |
12100 | "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63" | |
12101 | [(set_attr "length" "12")]) | |
12102 | ||
1fd4e8c1 | 12103 | (define_insn "" |
cd2b37d9 RK |
12104 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12105 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12106 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
12107 | "TARGET_POWER" |
12108 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12109 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12110 | |
12111 | (define_insn "" | |
cd2b37d9 RK |
12112 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12113 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12114 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 12115 | "! TARGET_POWERPC64" |
ca7f5001 | 12116 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 12117 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12118 | |
f9562f27 DE |
12119 | (define_insn "" |
12120 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12121 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12122 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
12123 | "TARGET_POWERPC64" | |
12124 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" | |
12125 | [(set_attr "length" "12")]) | |
12126 | ||
1fd4e8c1 | 12127 | (define_insn "" |
9ebbca7d | 12128 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12129 | (compare:CC |
9ebbca7d GK |
12130 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12131 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12132 | (const_int 0))) |
9ebbca7d | 12133 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12134 | (gtu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12135 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12136 | "@ |
12137 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
12138 | #" | |
b19003d8 | 12139 | [(set_attr "type" "compare") |
9ebbca7d GK |
12140 | (set_attr "length" "12,16")]) |
12141 | ||
12142 | (define_split | |
12143 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12144 | (compare:CC | |
12145 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12146 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12147 | (const_int 0))) | |
12148 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12149 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
12150 | "! TARGET_POWERPC64 && reload_completed" | |
12151 | [(set (match_dup 0) | |
12152 | (gtu:SI (match_dup 1) (match_dup 2))) | |
12153 | (set (match_dup 3) | |
12154 | (compare:CC (match_dup 0) | |
12155 | (const_int 0)))] | |
12156 | "") | |
1fd4e8c1 | 12157 | |
f9562f27 | 12158 | (define_insn "" |
9ebbca7d | 12159 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12160 | (compare:CC |
9ebbca7d GK |
12161 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12162 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12163 | (const_int 0))) |
9ebbca7d | 12164 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12165 | (gtu:DI (match_dup 1) (match_dup 2)))] |
12166 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12167 | "@ |
12168 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
12169 | #" | |
f9562f27 | 12170 | [(set_attr "type" "compare") |
9ebbca7d GK |
12171 | (set_attr "length" "12,16")]) |
12172 | ||
12173 | (define_split | |
12174 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12175 | (compare:CC | |
12176 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12177 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12178 | (const_int 0))) | |
12179 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12180 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
12181 | "TARGET_POWERPC64 && reload_completed" | |
12182 | [(set (match_dup 0) | |
12183 | (gtu:DI (match_dup 1) (match_dup 2))) | |
12184 | (set (match_dup 3) | |
12185 | (compare:CC (match_dup 0) | |
12186 | (const_int 0)))] | |
12187 | "") | |
f9562f27 | 12188 | |
1fd4e8c1 | 12189 | (define_insn "" |
19378cf8 MM |
12190 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12191 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12192 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
12193 | (match_operand:SI 3 "reg_or_short_operand" "r,rI"))) | |
12194 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 12195 | "! TARGET_POWERPC64" |
00751805 | 12196 | "@ |
ca7f5001 | 12197 | {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 |
ca7f5001 | 12198 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
19378cf8 | 12199 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 12200 | |
f9562f27 DE |
12201 | (define_insn "" |
12202 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12203 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12204 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
12205 | (match_operand:DI 3 "reg_or_short_operand" "r,rI"))) | |
12206 | (clobber (match_scratch:DI 4 "=&r,&r"))] | |
12207 | "TARGET_POWERPC64" | |
12208 | "@ | |
12209 | addic %4,%1,%k2\;addze %0,%3 | |
12210 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3" | |
12211 | [(set_attr "length" "8,12")]) | |
12212 | ||
1fd4e8c1 | 12213 | (define_insn "" |
9ebbca7d | 12214 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12215 | (compare:CC |
9ebbca7d GK |
12216 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12217 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
12218 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12219 | (const_int 0))) |
9ebbca7d | 12220 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12221 | "! TARGET_POWERPC64" |
00751805 | 12222 | "@ |
19378cf8 | 12223 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12224 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12225 | # | |
12226 | #" | |
b19003d8 | 12227 | [(set_attr "type" "compare") |
9ebbca7d GK |
12228 | (set_attr "length" "8,12,12,16")]) |
12229 | ||
12230 | (define_split | |
12231 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12232 | (compare:CC | |
12233 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12234 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12235 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12236 | (const_int 0))) | |
12237 | (clobber (match_scratch:SI 4 ""))] | |
12238 | "! TARGET_POWERPC64 && reload_completed" | |
12239 | [(set (match_dup 4) | |
12240 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
12241 | (match_dup 3))) | |
12242 | (set (match_dup 0) | |
12243 | (compare:CC (match_dup 4) | |
12244 | (const_int 0)))] | |
12245 | "") | |
1fd4e8c1 | 12246 | |
f9562f27 | 12247 | (define_insn "" |
9ebbca7d | 12248 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12249 | (compare:CC |
9ebbca7d GK |
12250 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12251 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
12252 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12253 | (const_int 0))) |
9ebbca7d | 12254 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
12255 | "TARGET_POWERPC64" |
12256 | "@ | |
12257 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
12258 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
12259 | # | |
12260 | #" | |
f9562f27 | 12261 | [(set_attr "type" "compare") |
9ebbca7d GK |
12262 | (set_attr "length" "8,12,12,16")]) |
12263 | ||
12264 | (define_split | |
12265 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12266 | (compare:CC | |
12267 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12268 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12269 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
12270 | (const_int 0))) | |
12271 | (clobber (match_scratch:DI 4 ""))] | |
12272 | "TARGET_POWERPC64 && reload_completed" | |
12273 | [(set (match_dup 4) | |
12274 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
12275 | (match_dup 3))) | |
12276 | (set (match_dup 0) | |
12277 | (compare:CC (match_dup 4) | |
12278 | (const_int 0)))] | |
12279 | "") | |
f9562f27 | 12280 | |
1fd4e8c1 | 12281 | (define_insn "" |
9ebbca7d | 12282 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12283 | (compare:CC |
9ebbca7d GK |
12284 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12285 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
12286 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12287 | (const_int 0))) |
9ebbca7d | 12288 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12289 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12290 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12291 | "! TARGET_POWERPC64" |
00751805 | 12292 | "@ |
ca7f5001 | 12293 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
12294 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
12295 | # | |
12296 | #" | |
b19003d8 | 12297 | [(set_attr "type" "compare") |
9ebbca7d GK |
12298 | (set_attr "length" "8,12,12,16")]) |
12299 | ||
12300 | (define_split | |
12301 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12302 | (compare:CC | |
12303 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12304 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12305 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12306 | (const_int 0))) | |
12307 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12308 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12309 | (clobber (match_scratch:SI 4 ""))] | |
12310 | "! TARGET_POWERPC64 && reload_completed" | |
12311 | [(parallel [(set (match_dup 0) | |
12312 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12313 | (clobber (match_dup 4))]) | |
12314 | (set (match_dup 5) | |
12315 | (compare:CC (match_dup 0) | |
12316 | (const_int 0)))] | |
12317 | "") | |
1fd4e8c1 | 12318 | |
f9562f27 | 12319 | (define_insn "" |
9ebbca7d | 12320 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12321 | (compare:CC |
9ebbca7d GK |
12322 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12323 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
12324 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12325 | (const_int 0))) |
9ebbca7d | 12326 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12327 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12328 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
12329 | "TARGET_POWERPC64" |
12330 | "@ | |
12331 | addic %4,%1,%k2\;addze. %0,%3 | |
9ebbca7d GK |
12332 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3 |
12333 | # | |
12334 | #" | |
f9562f27 | 12335 | [(set_attr "type" "compare") |
9ebbca7d GK |
12336 | (set_attr "length" "8,12,12,16")]) |
12337 | ||
12338 | (define_split | |
12339 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12340 | (compare:CC | |
12341 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12342 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12343 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
12344 | (const_int 0))) | |
12345 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12346 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12347 | (clobber (match_scratch:DI 4 ""))] | |
12348 | "TARGET_POWERPC64 && reload_completed" | |
12349 | [(parallel [(set (match_dup 0) | |
12350 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12351 | (clobber (match_dup 4))]) | |
12352 | (set (match_dup 5) | |
12353 | (compare:CC (match_dup 0) | |
12354 | (const_int 0)))] | |
12355 | "") | |
f9562f27 | 12356 | |
1fd4e8c1 | 12357 | (define_insn "" |
cd2b37d9 RK |
12358 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12359 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12360 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 12361 | "! TARGET_POWERPC64" |
ca7f5001 | 12362 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12363 | [(set_attr "length" "8")]) |
f9562f27 DE |
12364 | |
12365 | (define_insn "" | |
12366 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12367 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12368 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
12369 | "TARGET_POWERPC64" | |
12370 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" | |
12371 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
12372 | \f |
12373 | ;; Define both directions of branch and return. If we need a reload | |
12374 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
12375 | ;; register CC value to there. | |
12376 | ||
12377 | (define_insn "" | |
12378 | [(set (pc) | |
12379 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12380 | [(match_operand 2 | |
12381 | "cc_reg_operand" "x,?y") | |
12382 | (const_int 0)]) | |
12383 | (label_ref (match_operand 0 "" "")) | |
12384 | (pc)))] | |
12385 | "" | |
b19003d8 RK |
12386 | "* |
12387 | { | |
12a4e8c5 | 12388 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
12389 | }" |
12390 | [(set_attr "type" "branch")]) | |
12391 | ||
1fd4e8c1 RK |
12392 | (define_insn "" |
12393 | [(set (pc) | |
12394 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12395 | [(match_operand 1 | |
12396 | "cc_reg_operand" "x,?y") | |
12397 | (const_int 0)]) | |
12398 | (return) | |
12399 | (pc)))] | |
12400 | "direct_return ()" | |
12a4e8c5 GK |
12401 | "* |
12402 | { | |
12403 | return output_cbranch (operands[0], NULL, 0, insn); | |
12404 | }" | |
b7ff3d82 | 12405 | [(set_attr "type" "branch") |
39a10a29 | 12406 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
12407 | |
12408 | (define_insn "" | |
12409 | [(set (pc) | |
12410 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12411 | [(match_operand 2 | |
12412 | "cc_reg_operand" "x,?y") | |
12413 | (const_int 0)]) | |
12414 | (pc) | |
12415 | (label_ref (match_operand 0 "" ""))))] | |
12416 | "" | |
b19003d8 RK |
12417 | "* |
12418 | { | |
12a4e8c5 | 12419 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
12420 | }" |
12421 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12422 | |
12423 | (define_insn "" | |
12424 | [(set (pc) | |
12425 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12426 | [(match_operand 1 | |
12427 | "cc_reg_operand" "x,?y") | |
12428 | (const_int 0)]) | |
12429 | (pc) | |
12430 | (return)))] | |
12431 | "direct_return ()" | |
12a4e8c5 GK |
12432 | "* |
12433 | { | |
12434 | return output_cbranch (operands[0], NULL, 1, insn); | |
12435 | }" | |
b7ff3d82 | 12436 | [(set_attr "type" "branch") |
39a10a29 GK |
12437 | (set_attr "length" "4")]) |
12438 | ||
12439 | ;; Logic on condition register values. | |
12440 | ||
12441 | ; This pattern matches things like | |
12442 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
12443 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
12444 | ; (const_int 1))) | |
12445 | ; which are generated by the branch logic. | |
12446 | ||
12447 | (define_insn "" | |
12448 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12449 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" | |
12450 | [(match_operator:SI 2 | |
12451 | "branch_positive_comparison_operator" | |
12452 | [(match_operand 3 | |
12453 | "cc_reg_operand" "y") | |
12454 | (const_int 0)]) | |
12455 | (match_operator:SI 4 | |
12456 | "branch_positive_comparison_operator" | |
12457 | [(match_operand 5 | |
12458 | "cc_reg_operand" "y") | |
12459 | (const_int 0)])]) | |
12460 | (const_int 1)))] | |
12461 | "" | |
12462 | "cr%q1 %E0,%j2,%j4" | |
12463 | [(set_attr "type" "cr_logical")]) | |
12464 | ||
12465 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
12466 | ; Because ~1 has all but the low bit set. | |
12467 | (define_insn "" | |
12468 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12469 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" | |
12470 | [(not:SI (match_operator:SI 2 | |
12471 | "branch_positive_comparison_operator" | |
12472 | [(match_operand 3 | |
12473 | "cc_reg_operand" "y") | |
12474 | (const_int 0)])) | |
12475 | (match_operator:SI 4 | |
12476 | "branch_positive_comparison_operator" | |
12477 | [(match_operand 5 | |
12478 | "cc_reg_operand" "y") | |
12479 | (const_int 0)])]) | |
12480 | (const_int -1)))] | |
12481 | "" | |
12482 | "cr%q1 %E0,%j2,%j4" | |
12483 | [(set_attr "type" "cr_logical")]) | |
12484 | ||
12485 | (define_insn "" | |
12486 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
6c873122 | 12487 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 12488 | "branch_positive_comparison_operator" |
6c873122 | 12489 | [(match_operand 2 |
39a10a29 GK |
12490 | "cc_reg_operand" "y") |
12491 | (const_int 0)]) | |
12492 | (const_int 0)))] | |
12493 | "" | |
251b3667 | 12494 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
39a10a29 GK |
12495 | [(set_attr "type" "cr_logical")]) |
12496 | ||
12497 | ;; If we are comparing the result of two comparisons, this can be done | |
12498 | ;; using creqv or crxor. | |
12499 | ||
12500 | (define_insn_and_split "" | |
12501 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12502 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
12503 | [(match_operand 2 "cc_reg_operand" "y") | |
12504 | (const_int 0)]) | |
12505 | (match_operator 3 "branch_comparison_operator" | |
12506 | [(match_operand 4 "cc_reg_operand" "y") | |
12507 | (const_int 0)])))] | |
12508 | "" | |
12509 | "#" | |
12510 | "" | |
12511 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
12512 | (match_dup 5)))] | |
12513 | " | |
12514 | { | |
12515 | int positive_1, positive_2; | |
12516 | ||
12517 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
12518 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
12519 | ||
12520 | if (! positive_1) | |
2d4368e6 | 12521 | operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]), |
39a10a29 | 12522 | GET_CODE (operands[1])), |
2d4368e6 DE |
12523 | SImode, |
12524 | operands[2], const0_rtx); | |
39a10a29 | 12525 | else if (GET_MODE (operands[1]) != SImode) |
2d4368e6 DE |
12526 | operands[1] = gen_rtx (GET_CODE (operands[1]), |
12527 | SImode, | |
12528 | operands[2], const0_rtx); | |
39a10a29 GK |
12529 | |
12530 | if (! positive_2) | |
2d4368e6 | 12531 | operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]), |
39a10a29 | 12532 | GET_CODE (operands[3])), |
2d4368e6 DE |
12533 | SImode, |
12534 | operands[4], const0_rtx); | |
39a10a29 | 12535 | else if (GET_MODE (operands[3]) != SImode) |
2d4368e6 DE |
12536 | operands[3] = gen_rtx (GET_CODE (operands[3]), |
12537 | SImode, | |
12538 | operands[4], const0_rtx); | |
39a10a29 GK |
12539 | |
12540 | if (positive_1 == positive_2) | |
251b3667 DE |
12541 | { |
12542 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
12543 | operands[5] = constm1_rtx; | |
12544 | } | |
12545 | else | |
12546 | { | |
12547 | operands[5] = const1_rtx; | |
12548 | } | |
39a10a29 | 12549 | }") |
1fd4e8c1 RK |
12550 | |
12551 | ;; Unconditional branch and return. | |
12552 | ||
12553 | (define_insn "jump" | |
12554 | [(set (pc) | |
12555 | (label_ref (match_operand 0 "" "")))] | |
12556 | "" | |
b7ff3d82 DE |
12557 | "b %l0" |
12558 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12559 | |
12560 | (define_insn "return" | |
12561 | [(return)] | |
12562 | "direct_return ()" | |
324e52cc TG |
12563 | "{br|blr}" |
12564 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 12565 | |
0ad91047 DE |
12566 | (define_expand "indirect_jump" |
12567 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 12568 | "" |
0ad91047 DE |
12569 | " |
12570 | { | |
12571 | if (TARGET_32BIT) | |
12572 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
12573 | else | |
12574 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
12575 | DONE; | |
12576 | }") | |
12577 | ||
12578 | (define_insn "indirect_jumpsi" | |
cccf3bdc | 12579 | [(set (pc) (match_operand:SI 0 "register_operand" "cl"))] |
0ad91047 | 12580 | "TARGET_32BIT" |
cccf3bdc | 12581 | "b%T0" |
324e52cc | 12582 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 12583 | |
0ad91047 | 12584 | (define_insn "indirect_jumpdi" |
cccf3bdc | 12585 | [(set (pc) (match_operand:DI 0 "register_operand" "cl"))] |
0ad91047 | 12586 | "TARGET_64BIT" |
cccf3bdc | 12587 | "b%T0" |
266eb58a DE |
12588 | [(set_attr "type" "jmpreg")]) |
12589 | ||
1fd4e8c1 RK |
12590 | ;; Table jump for switch statements: |
12591 | (define_expand "tablejump" | |
e6ca2c17 DE |
12592 | [(use (match_operand 0 "" "")) |
12593 | (use (label_ref (match_operand 1 "" "")))] | |
12594 | "" | |
12595 | " | |
12596 | { | |
12597 | if (TARGET_32BIT) | |
12598 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
12599 | else | |
12600 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
12601 | DONE; | |
12602 | }") | |
12603 | ||
12604 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
12605 | [(set (match_dup 3) |
12606 | (plus:SI (match_operand:SI 0 "" "") | |
12607 | (match_dup 2))) | |
12608 | (parallel [(set (pc) (match_dup 3)) | |
12609 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 12610 | "TARGET_32BIT" |
1fd4e8c1 RK |
12611 | " |
12612 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 12613 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
12614 | operands[3] = gen_reg_rtx (SImode); |
12615 | }") | |
12616 | ||
e6ca2c17 | 12617 | (define_expand "tablejumpdi" |
9ebbca7d GK |
12618 | [(set (match_dup 4) |
12619 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) | |
12620 | (set (match_dup 3) | |
12621 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
12622 | (match_dup 2))) |
12623 | (parallel [(set (pc) (match_dup 3)) | |
12624 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 12625 | "TARGET_64BIT" |
e6ca2c17 | 12626 | " |
9ebbca7d | 12627 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 12628 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 12629 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
12630 | }") |
12631 | ||
1fd4e8c1 RK |
12632 | (define_insn "" |
12633 | [(set (pc) | |
cccf3bdc | 12634 | (match_operand:SI 0 "register_operand" "cl")) |
1fd4e8c1 | 12635 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 12636 | "TARGET_32BIT" |
cccf3bdc | 12637 | "b%T0" |
a6845123 | 12638 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 12639 | |
266eb58a DE |
12640 | (define_insn "" |
12641 | [(set (pc) | |
cccf3bdc | 12642 | (match_operand:DI 0 "register_operand" "cl")) |
266eb58a | 12643 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 12644 | "TARGET_64BIT" |
cccf3bdc | 12645 | "b%T0" |
266eb58a DE |
12646 | [(set_attr "type" "jmpreg")]) |
12647 | ||
1fd4e8c1 RK |
12648 | (define_insn "nop" |
12649 | [(const_int 0)] | |
12650 | "" | |
ca7f5001 | 12651 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 12652 | \f |
7e69e155 | 12653 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
12654 | ;; so loop.c knows what to generate. |
12655 | ||
5527bf14 RH |
12656 | (define_expand "doloop_end" |
12657 | [(use (match_operand 0 "" "")) ; loop pseudo | |
12658 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
12659 | (use (match_operand 2 "" "")) ; max iterations | |
12660 | (use (match_operand 3 "" "")) ; loop level | |
12661 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
12662 | "" |
12663 | " | |
12664 | { | |
5527bf14 RH |
12665 | /* Only use this on innermost loops. */ |
12666 | if (INTVAL (operands[3]) > 1) | |
12667 | FAIL; | |
0ad91047 | 12668 | if (TARGET_POWERPC64) |
5527bf14 RH |
12669 | { |
12670 | if (GET_MODE (operands[0]) != DImode) | |
12671 | FAIL; | |
12672 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
12673 | } | |
0ad91047 | 12674 | else |
5527bf14 RH |
12675 | { |
12676 | if (GET_MODE (operands[0]) != SImode) | |
12677 | FAIL; | |
12678 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
12679 | } | |
0ad91047 DE |
12680 | DONE; |
12681 | }") | |
12682 | ||
12683 | (define_expand "ctrsi" | |
3cb999d8 DE |
12684 | [(parallel [(set (pc) |
12685 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
12686 | (const_int 1)) | |
12687 | (label_ref (match_operand 1 "" "")) | |
12688 | (pc))) | |
b6c9286a MM |
12689 | (set (match_dup 0) |
12690 | (plus:SI (match_dup 0) | |
12691 | (const_int -1))) | |
5f81043f RK |
12692 | (clobber (match_scratch:CC 2 "")) |
12693 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
12694 | "! TARGET_POWERPC64" |
12695 | "") | |
12696 | ||
12697 | (define_expand "ctrdi" | |
3cb999d8 DE |
12698 | [(parallel [(set (pc) |
12699 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
12700 | (const_int 1)) | |
12701 | (label_ref (match_operand 1 "" "")) | |
12702 | (pc))) | |
0ad91047 DE |
12703 | (set (match_dup 0) |
12704 | (plus:DI (match_dup 0) | |
12705 | (const_int -1))) | |
12706 | (clobber (match_scratch:CC 2 "")) | |
12707 | (clobber (match_scratch:DI 3 ""))])] | |
12708 | "TARGET_POWERPC64" | |
c225ba7b RK |
12709 | "") |
12710 | ||
1fd4e8c1 RK |
12711 | ;; We need to be able to do this for any operand, including MEM, or we |
12712 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 12713 | ;; JUMP_INSNs. |
0ad91047 | 12714 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
12715 | ;; label MUST be operand 0. |
12716 | ||
0ad91047 | 12717 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 12718 | [(set (pc) |
5f81043f | 12719 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 12720 | (const_int 1)) |
a6845123 | 12721 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12722 | (pc))) |
5f81043f RK |
12723 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12724 | (plus:SI (match_dup 1) | |
12725 | (const_int -1))) | |
1fd4e8c1 RK |
12726 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
12727 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12728 | "! TARGET_POWERPC64" |
b19003d8 RK |
12729 | "* |
12730 | { | |
af87a13e | 12731 | if (which_alternative != 0) |
b19003d8 | 12732 | return \"#\"; |
856a6884 | 12733 | else if (get_attr_length (insn) == 4) |
a6845123 | 12734 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 12735 | else |
c81bebd7 | 12736 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 12737 | }" |
baf97f86 RK |
12738 | [(set_attr "type" "branch") |
12739 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 12740 | |
0ad91047 | 12741 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
12742 | [(set (pc) |
12743 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
12744 | (const_int 1)) | |
12745 | (pc) | |
12746 | (label_ref (match_operand 0 "" "")))) | |
12747 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
12748 | (plus:SI (match_dup 1) | |
12749 | (const_int -1))) | |
12750 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12751 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
12752 | "! TARGET_POWERPC64" |
12753 | "* | |
12754 | { | |
12755 | if (which_alternative != 0) | |
12756 | return \"#\"; | |
856a6884 | 12757 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12758 | return \"bdz %l0\"; |
12759 | else | |
12760 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
12761 | }" | |
12762 | [(set_attr "type" "branch") | |
12763 | (set_attr "length" "*,12,16")]) | |
12764 | ||
12765 | (define_insn "*ctrdi_internal1" | |
12766 | [(set (pc) | |
12767 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12768 | (const_int 1)) | |
12769 | (label_ref (match_operand 0 "" "")) | |
12770 | (pc))) | |
12771 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12772 | (plus:DI (match_dup 1) | |
12773 | (const_int -1))) | |
12774 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12775 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12776 | "TARGET_POWERPC64" | |
12777 | "* | |
12778 | { | |
12779 | if (which_alternative != 0) | |
12780 | return \"#\"; | |
856a6884 | 12781 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12782 | return \"{bdn|bdnz} %l0\"; |
12783 | else | |
12784 | return \"bdz %$+8\;b %l0\"; | |
12785 | }" | |
12786 | [(set_attr "type" "branch") | |
12787 | (set_attr "length" "*,12,16")]) | |
12788 | ||
12789 | (define_insn "*ctrdi_internal2" | |
12790 | [(set (pc) | |
12791 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12792 | (const_int 1)) | |
12793 | (pc) | |
12794 | (label_ref (match_operand 0 "" "")))) | |
12795 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12796 | (plus:DI (match_dup 1) | |
12797 | (const_int -1))) | |
12798 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12799 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12800 | "TARGET_POWERPC64" | |
5f81043f RK |
12801 | "* |
12802 | { | |
12803 | if (which_alternative != 0) | |
12804 | return \"#\"; | |
856a6884 | 12805 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
12806 | return \"bdz %l0\"; |
12807 | else | |
c81bebd7 | 12808 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
12809 | }" |
12810 | [(set_attr "type" "branch") | |
12811 | (set_attr "length" "*,12,16")]) | |
12812 | ||
c225ba7b | 12813 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
12814 | |
12815 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 12816 | [(set (pc) |
5f81043f | 12817 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 12818 | (const_int 0)) |
a6845123 | 12819 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12820 | (pc))) |
5f81043f RK |
12821 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12822 | (plus:SI (match_dup 1) | |
12823 | (const_int -1))) | |
1fd4e8c1 RK |
12824 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
12825 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12826 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
12827 | "* |
12828 | { | |
af87a13e | 12829 | if (which_alternative != 0) |
b19003d8 | 12830 | return \"#\"; |
856a6884 | 12831 | else if (get_attr_length (insn) == 4) |
a6845123 | 12832 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 12833 | else |
c81bebd7 | 12834 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 12835 | }" |
baf97f86 RK |
12836 | [(set_attr "type" "branch") |
12837 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 12838 | |
0ad91047 | 12839 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 12840 | [(set (pc) |
5f81043f RK |
12841 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
12842 | (const_int 0)) | |
12843 | (pc) | |
12844 | (label_ref (match_operand 0 "" "")))) | |
12845 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
12846 | (plus:SI (match_dup 1) | |
12847 | (const_int -1))) | |
12848 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
12849 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12850 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
12851 | "* |
12852 | { | |
12853 | if (which_alternative != 0) | |
12854 | return \"#\"; | |
856a6884 | 12855 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
12856 | return \"bdz %l0\"; |
12857 | else | |
c81bebd7 | 12858 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
12859 | }" |
12860 | [(set_attr "type" "branch") | |
12861 | (set_attr "length" "*,12,16")]) | |
12862 | ||
0ad91047 DE |
12863 | (define_insn "*ctrdi_internal3" |
12864 | [(set (pc) | |
12865 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12866 | (const_int 0)) | |
12867 | (label_ref (match_operand 0 "" "")) | |
12868 | (pc))) | |
12869 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12870 | (plus:DI (match_dup 1) | |
12871 | (const_int -1))) | |
12872 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
12873 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12874 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
12875 | "* | |
12876 | { | |
12877 | if (which_alternative != 0) | |
12878 | return \"#\"; | |
856a6884 | 12879 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12880 | return \"{bdn|bdnz} %l0\"; |
12881 | else | |
12882 | return \"bdz %$+8\;b %l0\"; | |
12883 | }" | |
12884 | [(set_attr "type" "branch") | |
12885 | (set_attr "length" "*,12,16")]) | |
12886 | ||
12887 | (define_insn "*ctrdi_internal4" | |
12888 | [(set (pc) | |
12889 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12890 | (const_int 0)) | |
12891 | (pc) | |
12892 | (label_ref (match_operand 0 "" "")))) | |
12893 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12894 | (plus:DI (match_dup 1) | |
12895 | (const_int -1))) | |
12896 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
12897 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12898 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
12899 | "* | |
12900 | { | |
12901 | if (which_alternative != 0) | |
12902 | return \"#\"; | |
856a6884 | 12903 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12904 | return \"bdz %l0\"; |
12905 | else | |
12906 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
12907 | }" | |
12908 | [(set_attr "type" "branch") | |
12909 | (set_attr "length" "*,12,16")]) | |
12910 | ||
12911 | ;; Similar but use EQ | |
12912 | ||
12913 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
12914 | [(set (pc) |
12915 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 12916 | (const_int 1)) |
a6845123 | 12917 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12918 | (pc))) |
5f81043f RK |
12919 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12920 | (plus:SI (match_dup 1) | |
12921 | (const_int -1))) | |
1fd4e8c1 RK |
12922 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
12923 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12924 | "! TARGET_POWERPC64" |
b19003d8 RK |
12925 | "* |
12926 | { | |
af87a13e | 12927 | if (which_alternative != 0) |
b19003d8 | 12928 | return \"#\"; |
856a6884 | 12929 | else if (get_attr_length (insn) == 4) |
a6845123 | 12930 | return \"bdz %l0\"; |
b19003d8 | 12931 | else |
c81bebd7 | 12932 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
b19003d8 | 12933 | }" |
baf97f86 RK |
12934 | [(set_attr "type" "branch") |
12935 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 12936 | |
0ad91047 | 12937 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
12938 | [(set (pc) |
12939 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
12940 | (const_int 1)) | |
12941 | (pc) | |
12942 | (label_ref (match_operand 0 "" "")))) | |
12943 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
12944 | (plus:SI (match_dup 1) | |
12945 | (const_int -1))) | |
12946 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12947 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
12948 | "! TARGET_POWERPC64" |
12949 | "* | |
12950 | { | |
12951 | if (which_alternative != 0) | |
12952 | return \"#\"; | |
856a6884 | 12953 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12954 | return \"{bdn|bdnz} %l0\"; |
12955 | else | |
12956 | return \"bdz %$+8\;b %l0\"; | |
12957 | }" | |
12958 | [(set_attr "type" "branch") | |
12959 | (set_attr "length" "*,12,16")]) | |
12960 | ||
12961 | (define_insn "*ctrdi_internal5" | |
12962 | [(set (pc) | |
12963 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12964 | (const_int 1)) | |
12965 | (label_ref (match_operand 0 "" "")) | |
12966 | (pc))) | |
12967 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12968 | (plus:DI (match_dup 1) | |
12969 | (const_int -1))) | |
12970 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12971 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12972 | "TARGET_POWERPC64" | |
12973 | "* | |
12974 | { | |
12975 | if (which_alternative != 0) | |
12976 | return \"#\"; | |
856a6884 | 12977 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12978 | return \"bdz %l0\"; |
12979 | else | |
12980 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
12981 | }" | |
12982 | [(set_attr "type" "branch") | |
12983 | (set_attr "length" "*,12,16")]) | |
12984 | ||
12985 | (define_insn "*ctrdi_internal6" | |
12986 | [(set (pc) | |
12987 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12988 | (const_int 1)) | |
12989 | (pc) | |
12990 | (label_ref (match_operand 0 "" "")))) | |
12991 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12992 | (plus:DI (match_dup 1) | |
12993 | (const_int -1))) | |
12994 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12995 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12996 | "TARGET_POWERPC64" | |
5f81043f RK |
12997 | "* |
12998 | { | |
12999 | if (which_alternative != 0) | |
13000 | return \"#\"; | |
856a6884 | 13001 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13002 | return \"{bdn|bdnz} %l0\"; |
13003 | else | |
c81bebd7 | 13004 | return \"bdz %$+8\;b %l0\"; |
5f81043f RK |
13005 | }" |
13006 | [(set_attr "type" "branch") | |
13007 | (set_attr "length" "*,12,16")]) | |
13008 | ||
0ad91047 DE |
13009 | ;; Now the splitters if we could not allocate the CTR register |
13010 | ||
1fd4e8c1 RK |
13011 | (define_split |
13012 | [(set (pc) | |
13013 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13014 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13015 | (const_int 1)]) |
13016 | (match_operand 5 "" "") | |
13017 | (match_operand 6 "" ""))) | |
cd2b37d9 | 13018 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
13019 | (plus:SI (match_dup 1) |
13020 | (const_int -1))) | |
1fd4e8c1 RK |
13021 | (clobber (match_scratch:CC 3 "")) |
13022 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 13023 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 13024 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13025 | (compare:CC (plus:SI (match_dup 1) |
13026 | (const_int -1)) | |
1fd4e8c1 | 13027 | (const_int 0))) |
5f81043f RK |
13028 | (set (match_dup 0) |
13029 | (plus:SI (match_dup 1) | |
13030 | (const_int -1)))]) | |
13031 | (set (pc) (if_then_else (match_dup 7) | |
13032 | (match_dup 5) | |
13033 | (match_dup 6)))] | |
1fd4e8c1 RK |
13034 | " |
13035 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13036 | const0_rtx); }") | |
13037 | ||
13038 | (define_split | |
13039 | [(set (pc) | |
13040 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13041 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13042 | (const_int 1)]) |
13043 | (match_operand 5 "" "") | |
13044 | (match_operand 6 "" ""))) | |
9ebbca7d | 13045 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
13046 | (plus:SI (match_dup 1) (const_int -1))) |
13047 | (clobber (match_scratch:CC 3 "")) | |
13048 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
13049 | "! TARGET_POWERPC64 && reload_completed |
13050 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 13051 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13052 | (compare:CC (plus:SI (match_dup 1) |
13053 | (const_int -1)) | |
1fd4e8c1 | 13054 | (const_int 0))) |
5f81043f RK |
13055 | (set (match_dup 4) |
13056 | (plus:SI (match_dup 1) | |
13057 | (const_int -1)))]) | |
13058 | (set (match_dup 0) | |
13059 | (match_dup 4)) | |
13060 | (set (pc) (if_then_else (match_dup 7) | |
13061 | (match_dup 5) | |
13062 | (match_dup 6)))] | |
1fd4e8c1 RK |
13063 | " |
13064 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13065 | const0_rtx); }") | |
0ad91047 DE |
13066 | (define_split |
13067 | [(set (pc) | |
13068 | (if_then_else (match_operator 2 "comparison_operator" | |
13069 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13070 | (const_int 1)]) | |
13071 | (match_operand 5 "" "") | |
13072 | (match_operand 6 "" ""))) | |
13073 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13074 | (plus:DI (match_dup 1) | |
13075 | (const_int -1))) | |
13076 | (clobber (match_scratch:CC 3 "")) | |
13077 | (clobber (match_scratch:DI 4 ""))] | |
13078 | "TARGET_POWERPC64 && reload_completed" | |
13079 | [(parallel [(set (match_dup 3) | |
13080 | (compare:CC (plus:DI (match_dup 1) | |
13081 | (const_int -1)) | |
13082 | (const_int 0))) | |
13083 | (set (match_dup 0) | |
13084 | (plus:DI (match_dup 1) | |
13085 | (const_int -1)))]) | |
13086 | (set (pc) (if_then_else (match_dup 7) | |
13087 | (match_dup 5) | |
13088 | (match_dup 6)))] | |
13089 | " | |
13090 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13091 | const0_rtx); }") | |
13092 | ||
13093 | (define_split | |
13094 | [(set (pc) | |
13095 | (if_then_else (match_operator 2 "comparison_operator" | |
13096 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13097 | (const_int 1)]) | |
13098 | (match_operand 5 "" "") | |
13099 | (match_operand 6 "" ""))) | |
9ebbca7d | 13100 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
13101 | (plus:DI (match_dup 1) (const_int -1))) |
13102 | (clobber (match_scratch:CC 3 "")) | |
13103 | (clobber (match_scratch:DI 4 ""))] | |
13104 | "TARGET_POWERPC64 && reload_completed | |
13105 | && ! gpc_reg_operand (operands[0], DImode)" | |
13106 | [(parallel [(set (match_dup 3) | |
13107 | (compare:CC (plus:DI (match_dup 1) | |
13108 | (const_int -1)) | |
13109 | (const_int 0))) | |
13110 | (set (match_dup 4) | |
13111 | (plus:DI (match_dup 1) | |
13112 | (const_int -1)))]) | |
13113 | (set (match_dup 0) | |
13114 | (match_dup 4)) | |
13115 | (set (pc) (if_then_else (match_dup 7) | |
13116 | (match_dup 5) | |
13117 | (match_dup 6)))] | |
13118 | " | |
13119 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13120 | const0_rtx); }") | |
e0cd0770 JC |
13121 | \f |
13122 | (define_insn "trap" | |
13123 | [(trap_if (const_int 1) (const_int 0))] | |
13124 | "" | |
13125 | "{t 31,0,0|trap}") | |
13126 | ||
13127 | (define_expand "conditional_trap" | |
13128 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13129 | [(match_dup 2) (match_dup 3)]) | |
13130 | (match_operand 1 "const_int_operand" ""))] | |
13131 | "" | |
13132 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
13133 | operands[2] = rs6000_compare_op0; | |
13134 | operands[3] = rs6000_compare_op1;") | |
13135 | ||
13136 | (define_insn "" | |
13137 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13138 | [(match_operand:SI 1 "register_operand" "r") | |
13139 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
13140 | (const_int 0))] | |
13141 | "" | |
a157febd GK |
13142 | "{t|tw}%V0%I2 %1,%2") |
13143 | ||
13144 | (define_insn "" | |
13145 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13146 | [(match_operand:DI 1 "register_operand" "r") | |
13147 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
13148 | (const_int 0))] | |
13149 | "TARGET_POWERPC64" | |
13150 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
13151 | \f |
13152 | ;; Insns related to generating the function prologue and epilogue. | |
13153 | ||
13154 | (define_expand "prologue" | |
13155 | [(use (const_int 0))] | |
13156 | "TARGET_SCHED_PROLOG" | |
13157 | " | |
13158 | { | |
13159 | rs6000_emit_prologue (); | |
13160 | DONE; | |
13161 | }") | |
13162 | ||
13163 | (define_insn "movesi_from_cr" | |
13164 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
13165 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) | |
13166 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))] | |
13167 | "" | |
13168 | "mfcr %0") | |
13169 | ||
13170 | (define_insn "*stmw" | |
13171 | [(match_parallel 0 "stmw_operation" | |
13172 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
13173 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
13174 | "TARGET_MULTIPLE" | |
13175 | "{stm|stmw} %2,%1") | |
13176 | ||
13177 | (define_insn "*save_fpregs_si" | |
13178 | [(match_parallel 0 "any_operand" | |
13179 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
13180 | (use (match_operand:SI 2 "call_operand" "s")) | |
13181 | (set (match_operand:DF 3 "memory_operand" "=m") | |
13182 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
13183 | "TARGET_32BIT" | |
13184 | "bl %z2") | |
13185 | ||
13186 | (define_insn "*save_fpregs_di" | |
13187 | [(match_parallel 0 "any_operand" | |
13188 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
13189 | (use (match_operand:DI 2 "call_operand" "s")) | |
13190 | (set (match_operand:DF 3 "memory_operand" "=m") | |
13191 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
13192 | "TARGET_64BIT" | |
13193 | "bl %z2") | |
13194 | ||
13195 | ; These are to explain that changes to the stack pointer should | |
13196 | ; not be moved over stores to stack memory. | |
13197 | (define_insn "stack_tie" | |
13198 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
13199 | (unspec:BLK [(match_dup 0)] 5))] | |
13200 | "" | |
13201 | "" | |
13202 | [(set_attr "length" "0")]) | |
13203 | ||
13204 | ||
13205 | (define_expand "epilogue" | |
13206 | [(use (const_int 0))] | |
13207 | "TARGET_SCHED_PROLOG" | |
13208 | " | |
13209 | { | |
13210 | rs6000_emit_epilogue (FALSE); | |
13211 | DONE; | |
13212 | }") | |
13213 | ||
13214 | ; On some processors, doing the mtcrf one CC register at a time is | |
13215 | ; faster (like on the 604e). On others, doing them all at once is | |
13216 | ; faster; for instance, on the 601 and 750. | |
13217 | ||
13218 | (define_expand "movsi_to_cr_one" | |
13219 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
13220 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
13221 | (match_dup 2)] 20))] | |
13222 | "" | |
13223 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
13224 | ||
13225 | (define_insn "*movsi_to_cr" | |
13226 | [(match_parallel 0 "mtcrf_operation" | |
e35b9579 GK |
13227 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") |
13228 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
13229 | (match_operand 3 "immediate_operand" "n")] | |
9ebbca7d GK |
13230 | 20))])] |
13231 | "" | |
e35b9579 GK |
13232 | "* |
13233 | { | |
13234 | int mask = 0; | |
13235 | int i; | |
13236 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
13237 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
13238 | operands[4] = GEN_INT (mask); | |
13239 | return \"mtcrf %4,%2\"; | |
13240 | }") | |
9ebbca7d GK |
13241 | |
13242 | (define_insn "" | |
13243 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
13244 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
13245 | (match_operand 2 "immediate_operand" "n")] 20))] | |
13246 | "GET_CODE (operands[0]) == REG | |
13247 | && CR_REGNO_P (REGNO (operands[0])) | |
13248 | && GET_CODE (operands[2]) == CONST_INT | |
13249 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
13250 | "mtcrf %R0,%1") | |
13251 | ||
13252 | ; The load-multiple instructions have similar properties. | |
13253 | ; Note that "load_multiple" is a name known to the machine-independent | |
13254 | ; code that actually corresponds to the powerpc load-string. | |
13255 | ||
13256 | (define_insn "*lmw" | |
13257 | [(match_parallel 0 "lmw_operation" | |
13258 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
13259 | (match_operand:SI 2 "memory_operand" "m"))])] | |
13260 | "TARGET_MULTIPLE" | |
13261 | "{lm|lmw} %1,%2") | |
13262 | ||
13263 | (define_insn "*return_internal_si" | |
e35b9579 GK |
13264 | [(return) |
13265 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 13266 | "TARGET_32BIT" |
cccf3bdc | 13267 | "b%T0" |
9ebbca7d GK |
13268 | [(set_attr "type" "jmpreg")]) |
13269 | ||
13270 | (define_insn "*return_internal_di" | |
e35b9579 GK |
13271 | [(return) |
13272 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 13273 | "TARGET_64BIT" |
cccf3bdc | 13274 | "b%T0" |
9ebbca7d GK |
13275 | [(set_attr "type" "jmpreg")]) |
13276 | ||
13277 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
13278 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
13279 | ||
13280 | (define_insn "*return_and_restore_fpregs_si" | |
13281 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
13282 | [(return) |
13283 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
13284 | (use (match_operand:SI 2 "call_operand" "s")) |
13285 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
13286 | (match_operand:DF 4 "memory_operand" "m"))])] | |
13287 | "TARGET_32BIT" | |
13288 | "b %z2") | |
13289 | ||
13290 | (define_insn "*return_and_restore_fpregs_di" | |
13291 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
13292 | [(return) |
13293 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
13294 | (use (match_operand:DI 2 "call_operand" "s")) |
13295 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
13296 | (match_operand:DF 4 "memory_operand" "m"))])] | |
13297 | "TARGET_64BIT" | |
13298 | "b %z2") | |
13299 | ||
83720594 RH |
13300 | ; This is used in compiling the unwind routines. |
13301 | (define_expand "eh_return" | |
13302 | [(use (match_operand 0 "general_operand" "")) | |
13303 | (use (match_operand 1 "general_operand" ""))] | |
9ebbca7d GK |
13304 | "" |
13305 | " | |
13306 | { | |
3553b09d | 13307 | #if TARGET_AIX |
83720594 | 13308 | rs6000_emit_eh_toc_restore (operands[0]); |
3553b09d | 13309 | #endif |
83720594 RH |
13310 | if (TARGET_32BIT) |
13311 | emit_insn (gen_eh_set_lr_si (operands[1])); | |
9ebbca7d | 13312 | else |
83720594 RH |
13313 | emit_insn (gen_eh_set_lr_di (operands[1])); |
13314 | emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]); | |
9ebbca7d GK |
13315 | DONE; |
13316 | }") | |
13317 | ||
83720594 RH |
13318 | ; We can't expand this before we know where the link register is stored. |
13319 | (define_insn "eh_set_lr_si" | |
13320 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9) | |
13321 | (clobber (match_scratch:SI 1 "=&r"))] | |
13322 | "TARGET_32BIT" | |
13323 | "#") | |
13324 | ||
13325 | (define_insn "eh_set_lr_di" | |
13326 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9) | |
13327 | (clobber (match_scratch:DI 1 "=&r"))] | |
13328 | "TARGET_64BIT" | |
13329 | "#") | |
9ebbca7d GK |
13330 | |
13331 | (define_split | |
83720594 RH |
13332 | [(unspec_volatile [(match_operand 0 "register_operand" "")] 9) |
13333 | (clobber (match_scratch 1 ""))] | |
13334 | "reload_completed" | |
13335 | [(const_int 0)] | |
9ebbca7d GK |
13336 | " |
13337 | { | |
83720594 | 13338 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d | 13339 | |
83720594 RH |
13340 | if (info->lr_save_p) |
13341 | { | |
13342 | rtx frame_rtx = stack_pointer_rtx; | |
13343 | int sp_offset = 0; | |
13344 | rtx tmp; | |
9ebbca7d | 13345 | |
83720594 RH |
13346 | if (frame_pointer_needed |
13347 | || current_function_calls_alloca | |
13348 | || info->total_size > 32767) | |
13349 | { | |
13350 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
13351 | frame_rtx = operands[1]; | |
13352 | } | |
13353 | else if (info->push_p) | |
13354 | sp_offset = info->total_size; | |
9ebbca7d | 13355 | |
83720594 RH |
13356 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); |
13357 | tmp = gen_rtx_MEM (Pmode, tmp); | |
13358 | emit_move_insn (tmp, operands[0]); | |
13359 | } | |
13360 | else | |
13361 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
13362 | DONE; | |
13363 | }") |