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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
409f61cd | 3 | ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 | 5 | |
5de601cf | 6 | ;; This file is part of GCC. |
1fd4e8c1 | 7 | |
5de601cf NC |
8 | ;; GCC is free software; you can redistribute it and/or modify it |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
1fd4e8c1 | 12 | |
5de601cf NC |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
1fd4e8c1 RK |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
5de601cf NC |
19 | ;; along with GCC; see the file COPYING. If not, write to the |
20 | ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | ;; MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d | 24 | |
615158e2 JJ |
25 | ;; |
26 | ;; UNSPEC usage | |
27 | ;; | |
28 | ||
29 | (define_constants | |
30 | [(UNSPEC_FRSP 0) ; frsp for POWER machines | |
31 | (UNSPEC_TIE 5) ; tie stack contents and stack pointer | |
32 | (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC | |
33 | (UNSPEC_TOC 7) ; address of the TOC (more-or-less) | |
34 | (UNSPEC_MOVSI_GOT 8) | |
35 | (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit | |
36 | (UNSPEC_FCTIWZ 10) | |
37 | (UNSPEC_LD_MPIC 15) ; load_macho_picbase | |
38 | (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic | |
39 | (UNSPEC_TLSGD 17) | |
40 | (UNSPEC_TLSLD 18) | |
41 | (UNSPEC_MOVESI_FROM_CR 19) | |
42 | (UNSPEC_MOVESI_TO_CR 20) | |
43 | (UNSPEC_TLSDTPREL 21) | |
44 | (UNSPEC_TLSDTPRELHA 22) | |
45 | (UNSPEC_TLSDTPRELLO 23) | |
46 | (UNSPEC_TLSGOTDTPREL 24) | |
47 | (UNSPEC_TLSTPREL 25) | |
48 | (UNSPEC_TLSTPRELHA 26) | |
49 | (UNSPEC_TLSTPRELLO 27) | |
50 | (UNSPEC_TLSGOTTPREL 28) | |
51 | (UNSPEC_TLSTLS 29) | |
ecb62ae7 | 52 | (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero |
6b1fedc3 | 53 | (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit |
615158e2 JJ |
54 | ]) |
55 | ||
56 | ;; | |
57 | ;; UNSPEC_VOLATILE usage | |
58 | ;; | |
59 | ||
60 | (define_constants | |
61 | [(UNSPECV_BLOCK 0) | |
62 | (UNSPECV_EH_RR 9) ; eh_reg_restore | |
63 | ]) | |
1fd4e8c1 RK |
64 | \f |
65 | ;; Define an insn type attribute. This is used in function unit delay | |
66 | ;; computations. | |
943c15ed | 67 | (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" |
1fd4e8c1 RK |
68 | (const_string "integer")) |
69 | ||
b19003d8 | 70 | ;; Length (in bytes). |
6ae08853 | 71 | ; '(pc)' in the following doesn't include the instruction itself; it is |
6cbadf36 | 72 | ; calculated as if the instruction had zero size. |
b19003d8 RK |
73 | (define_attr "length" "" |
74 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 75 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 76 | (const_int -32768)) |
6cbadf36 GK |
77 | (lt (minus (match_dup 0) (pc)) |
78 | (const_int 32764))) | |
39a10a29 GK |
79 | (const_int 4) |
80 | (const_int 8)) | |
b19003d8 RK |
81 | (const_int 4))) |
82 | ||
cfb557c4 RK |
83 | ;; Processor type -- this attribute must exactly match the processor_type |
84 | ;; enumeration in rs6000.h. | |
85 | ||
ec507f2d | 86 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" |
cfb557c4 RK |
87 | (const (symbol_ref "rs6000_cpu_attr"))) |
88 | ||
b54cf83a DE |
89 | (automata_option "ndfa") |
90 | ||
91 | (include "rios1.md") | |
92 | (include "rios2.md") | |
93 | (include "rs64.md") | |
94 | (include "mpc.md") | |
95 | (include "40x.md") | |
02ca7595 | 96 | (include "440.md") |
b54cf83a DE |
97 | (include "603.md") |
98 | (include "6xx.md") | |
99 | (include "7xx.md") | |
100 | (include "7450.md") | |
5e8006fa | 101 | (include "8540.md") |
b54cf83a | 102 | (include "power4.md") |
ec507f2d | 103 | (include "power5.md") |
ac9e2cff | 104 | (include "darwin.md") |
309323c2 | 105 | |
1fd4e8c1 | 106 | \f |
2e6c9641 FJ |
107 | ;; This mode macro allows :P to be used for patterns that operate on |
108 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
109 | (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) | |
110 | ||
1fd4e8c1 RK |
111 | ;; Start with fixed-point load and store insns. Here we put only the more |
112 | ;; complex forms. Basic data transfer is done later. | |
113 | ||
51b8fc2c RK |
114 | (define_expand "zero_extendqidi2" |
115 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
116 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
117 | "TARGET_POWERPC64" | |
118 | "") | |
119 | ||
120 | (define_insn "" | |
121 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
122 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
123 | "TARGET_POWERPC64" | |
124 | "@ | |
125 | lbz%U1%X1 %0,%1 | |
4371f8af | 126 | rldicl %0,%1,0,56" |
51b8fc2c RK |
127 | [(set_attr "type" "load,*")]) |
128 | ||
129 | (define_insn "" | |
9ebbca7d GK |
130 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
131 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 132 | (const_int 0))) |
9ebbca7d | 133 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 134 | "TARGET_64BIT" |
9ebbca7d GK |
135 | "@ |
136 | rldicl. %2,%1,0,56 | |
137 | #" | |
138 | [(set_attr "type" "compare") | |
139 | (set_attr "length" "4,8")]) | |
140 | ||
141 | (define_split | |
142 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
143 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
144 | (const_int 0))) | |
145 | (clobber (match_scratch:DI 2 ""))] | |
146 | "TARGET_POWERPC64 && reload_completed" | |
147 | [(set (match_dup 2) | |
148 | (zero_extend:DI (match_dup 1))) | |
149 | (set (match_dup 0) | |
150 | (compare:CC (match_dup 2) | |
151 | (const_int 0)))] | |
152 | "") | |
51b8fc2c RK |
153 | |
154 | (define_insn "" | |
9ebbca7d GK |
155 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
156 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 157 | (const_int 0))) |
9ebbca7d | 158 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 159 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 160 | "TARGET_64BIT" |
9ebbca7d GK |
161 | "@ |
162 | rldicl. %0,%1,0,56 | |
163 | #" | |
164 | [(set_attr "type" "compare") | |
165 | (set_attr "length" "4,8")]) | |
166 | ||
167 | (define_split | |
168 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
169 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
170 | (const_int 0))) | |
171 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
172 | (zero_extend:DI (match_dup 1)))] | |
173 | "TARGET_POWERPC64 && reload_completed" | |
174 | [(set (match_dup 0) | |
175 | (zero_extend:DI (match_dup 1))) | |
176 | (set (match_dup 2) | |
177 | (compare:CC (match_dup 0) | |
178 | (const_int 0)))] | |
179 | "") | |
51b8fc2c | 180 | |
2bee0449 RK |
181 | (define_insn "extendqidi2" |
182 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
183 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 184 | "TARGET_POWERPC64" |
2bee0449 | 185 | "extsb %0,%1") |
51b8fc2c RK |
186 | |
187 | (define_insn "" | |
9ebbca7d GK |
188 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
189 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 190 | (const_int 0))) |
9ebbca7d | 191 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 192 | "TARGET_64BIT" |
9ebbca7d GK |
193 | "@ |
194 | extsb. %2,%1 | |
195 | #" | |
196 | [(set_attr "type" "compare") | |
197 | (set_attr "length" "4,8")]) | |
198 | ||
199 | (define_split | |
200 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
201 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
202 | (const_int 0))) | |
203 | (clobber (match_scratch:DI 2 ""))] | |
204 | "TARGET_POWERPC64 && reload_completed" | |
205 | [(set (match_dup 2) | |
206 | (sign_extend:DI (match_dup 1))) | |
207 | (set (match_dup 0) | |
208 | (compare:CC (match_dup 2) | |
209 | (const_int 0)))] | |
210 | "") | |
51b8fc2c RK |
211 | |
212 | (define_insn "" | |
9ebbca7d GK |
213 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
214 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 215 | (const_int 0))) |
9ebbca7d | 216 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 217 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 218 | "TARGET_64BIT" |
9ebbca7d GK |
219 | "@ |
220 | extsb. %0,%1 | |
221 | #" | |
222 | [(set_attr "type" "compare") | |
223 | (set_attr "length" "4,8")]) | |
224 | ||
225 | (define_split | |
226 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
227 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
228 | (const_int 0))) | |
229 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
230 | (sign_extend:DI (match_dup 1)))] | |
231 | "TARGET_POWERPC64 && reload_completed" | |
232 | [(set (match_dup 0) | |
233 | (sign_extend:DI (match_dup 1))) | |
234 | (set (match_dup 2) | |
235 | (compare:CC (match_dup 0) | |
236 | (const_int 0)))] | |
237 | "") | |
51b8fc2c RK |
238 | |
239 | (define_expand "zero_extendhidi2" | |
240 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
241 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
242 | "TARGET_POWERPC64" | |
243 | "") | |
244 | ||
245 | (define_insn "" | |
246 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
247 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
248 | "TARGET_POWERPC64" | |
249 | "@ | |
250 | lhz%U1%X1 %0,%1 | |
4371f8af | 251 | rldicl %0,%1,0,48" |
51b8fc2c RK |
252 | [(set_attr "type" "load,*")]) |
253 | ||
254 | (define_insn "" | |
9ebbca7d GK |
255 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
256 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 257 | (const_int 0))) |
9ebbca7d | 258 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 259 | "TARGET_64BIT" |
9ebbca7d GK |
260 | "@ |
261 | rldicl. %2,%1,0,48 | |
262 | #" | |
263 | [(set_attr "type" "compare") | |
264 | (set_attr "length" "4,8")]) | |
265 | ||
266 | (define_split | |
267 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
268 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
269 | (const_int 0))) | |
270 | (clobber (match_scratch:DI 2 ""))] | |
271 | "TARGET_POWERPC64 && reload_completed" | |
272 | [(set (match_dup 2) | |
273 | (zero_extend:DI (match_dup 1))) | |
274 | (set (match_dup 0) | |
275 | (compare:CC (match_dup 2) | |
276 | (const_int 0)))] | |
277 | "") | |
51b8fc2c RK |
278 | |
279 | (define_insn "" | |
9ebbca7d GK |
280 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
281 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 282 | (const_int 0))) |
9ebbca7d | 283 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 284 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 285 | "TARGET_64BIT" |
9ebbca7d GK |
286 | "@ |
287 | rldicl. %0,%1,0,48 | |
288 | #" | |
289 | [(set_attr "type" "compare") | |
290 | (set_attr "length" "4,8")]) | |
291 | ||
292 | (define_split | |
293 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
294 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
295 | (const_int 0))) | |
296 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
297 | (zero_extend:DI (match_dup 1)))] | |
298 | "TARGET_POWERPC64 && reload_completed" | |
299 | [(set (match_dup 0) | |
300 | (zero_extend:DI (match_dup 1))) | |
301 | (set (match_dup 2) | |
302 | (compare:CC (match_dup 0) | |
303 | (const_int 0)))] | |
304 | "") | |
51b8fc2c RK |
305 | |
306 | (define_expand "extendhidi2" | |
307 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
308 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
309 | "TARGET_POWERPC64" | |
310 | "") | |
311 | ||
312 | (define_insn "" | |
313 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
314 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
315 | "TARGET_POWERPC64" | |
316 | "@ | |
317 | lha%U1%X1 %0,%1 | |
318 | extsh %0,%1" | |
b54cf83a | 319 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
320 | |
321 | (define_insn "" | |
9ebbca7d GK |
322 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
323 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 324 | (const_int 0))) |
9ebbca7d | 325 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 326 | "TARGET_64BIT" |
9ebbca7d GK |
327 | "@ |
328 | extsh. %2,%1 | |
329 | #" | |
330 | [(set_attr "type" "compare") | |
331 | (set_attr "length" "4,8")]) | |
332 | ||
333 | (define_split | |
334 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
335 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
336 | (const_int 0))) | |
337 | (clobber (match_scratch:DI 2 ""))] | |
338 | "TARGET_POWERPC64 && reload_completed" | |
339 | [(set (match_dup 2) | |
340 | (sign_extend:DI (match_dup 1))) | |
341 | (set (match_dup 0) | |
342 | (compare:CC (match_dup 2) | |
343 | (const_int 0)))] | |
344 | "") | |
51b8fc2c RK |
345 | |
346 | (define_insn "" | |
9ebbca7d GK |
347 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
348 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 349 | (const_int 0))) |
9ebbca7d | 350 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 351 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 352 | "TARGET_64BIT" |
9ebbca7d GK |
353 | "@ |
354 | extsh. %0,%1 | |
355 | #" | |
356 | [(set_attr "type" "compare") | |
357 | (set_attr "length" "4,8")]) | |
358 | ||
359 | (define_split | |
360 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
361 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
362 | (const_int 0))) | |
363 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
364 | (sign_extend:DI (match_dup 1)))] | |
365 | "TARGET_POWERPC64 && reload_completed" | |
366 | [(set (match_dup 0) | |
367 | (sign_extend:DI (match_dup 1))) | |
368 | (set (match_dup 2) | |
369 | (compare:CC (match_dup 0) | |
370 | (const_int 0)))] | |
371 | "") | |
51b8fc2c RK |
372 | |
373 | (define_expand "zero_extendsidi2" | |
374 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
375 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
376 | "TARGET_POWERPC64" | |
377 | "") | |
378 | ||
379 | (define_insn "" | |
380 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
381 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
382 | "TARGET_POWERPC64" | |
383 | "@ | |
384 | lwz%U1%X1 %0,%1 | |
385 | rldicl %0,%1,0,32" | |
386 | [(set_attr "type" "load,*")]) | |
387 | ||
388 | (define_insn "" | |
9ebbca7d GK |
389 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
390 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 391 | (const_int 0))) |
9ebbca7d | 392 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 393 | "TARGET_64BIT" |
9ebbca7d GK |
394 | "@ |
395 | rldicl. %2,%1,0,32 | |
396 | #" | |
397 | [(set_attr "type" "compare") | |
398 | (set_attr "length" "4,8")]) | |
399 | ||
400 | (define_split | |
401 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
402 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
403 | (const_int 0))) | |
404 | (clobber (match_scratch:DI 2 ""))] | |
405 | "TARGET_POWERPC64 && reload_completed" | |
406 | [(set (match_dup 2) | |
407 | (zero_extend:DI (match_dup 1))) | |
408 | (set (match_dup 0) | |
409 | (compare:CC (match_dup 2) | |
410 | (const_int 0)))] | |
411 | "") | |
51b8fc2c RK |
412 | |
413 | (define_insn "" | |
9ebbca7d GK |
414 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
415 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 416 | (const_int 0))) |
9ebbca7d | 417 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 418 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 419 | "TARGET_64BIT" |
9ebbca7d GK |
420 | "@ |
421 | rldicl. %0,%1,0,32 | |
422 | #" | |
423 | [(set_attr "type" "compare") | |
424 | (set_attr "length" "4,8")]) | |
425 | ||
426 | (define_split | |
427 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
428 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
429 | (const_int 0))) | |
430 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
431 | (zero_extend:DI (match_dup 1)))] | |
432 | "TARGET_POWERPC64 && reload_completed" | |
433 | [(set (match_dup 0) | |
434 | (zero_extend:DI (match_dup 1))) | |
435 | (set (match_dup 2) | |
436 | (compare:CC (match_dup 0) | |
437 | (const_int 0)))] | |
438 | "") | |
51b8fc2c RK |
439 | |
440 | (define_expand "extendsidi2" | |
441 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
442 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
443 | "TARGET_POWERPC64" | |
444 | "") | |
445 | ||
446 | (define_insn "" | |
447 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 448 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
449 | "TARGET_POWERPC64" |
450 | "@ | |
451 | lwa%U1%X1 %0,%1 | |
452 | extsw %0,%1" | |
b54cf83a | 453 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
454 | |
455 | (define_insn "" | |
9ebbca7d GK |
456 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
457 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 458 | (const_int 0))) |
9ebbca7d | 459 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 460 | "TARGET_64BIT" |
9ebbca7d GK |
461 | "@ |
462 | extsw. %2,%1 | |
463 | #" | |
464 | [(set_attr "type" "compare") | |
465 | (set_attr "length" "4,8")]) | |
466 | ||
467 | (define_split | |
468 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
469 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
470 | (const_int 0))) | |
471 | (clobber (match_scratch:DI 2 ""))] | |
472 | "TARGET_POWERPC64 && reload_completed" | |
473 | [(set (match_dup 2) | |
474 | (sign_extend:DI (match_dup 1))) | |
475 | (set (match_dup 0) | |
476 | (compare:CC (match_dup 2) | |
477 | (const_int 0)))] | |
478 | "") | |
51b8fc2c RK |
479 | |
480 | (define_insn "" | |
9ebbca7d GK |
481 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
482 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 483 | (const_int 0))) |
9ebbca7d | 484 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 485 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 486 | "TARGET_64BIT" |
9ebbca7d GK |
487 | "@ |
488 | extsw. %0,%1 | |
489 | #" | |
490 | [(set_attr "type" "compare") | |
491 | (set_attr "length" "4,8")]) | |
492 | ||
493 | (define_split | |
494 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
495 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
496 | (const_int 0))) | |
497 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
498 | (sign_extend:DI (match_dup 1)))] | |
499 | "TARGET_POWERPC64 && reload_completed" | |
500 | [(set (match_dup 0) | |
501 | (sign_extend:DI (match_dup 1))) | |
502 | (set (match_dup 2) | |
503 | (compare:CC (match_dup 0) | |
504 | (const_int 0)))] | |
505 | "") | |
51b8fc2c | 506 | |
1fd4e8c1 | 507 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
508 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
509 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
510 | "" |
511 | "") | |
512 | ||
513 | (define_insn "" | |
cd2b37d9 | 514 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
515 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
516 | "" | |
517 | "@ | |
518 | lbz%U1%X1 %0,%1 | |
005a35b9 | 519 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
520 | [(set_attr "type" "load,*")]) |
521 | ||
522 | (define_insn "" | |
9ebbca7d GK |
523 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
524 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 525 | (const_int 0))) |
9ebbca7d | 526 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 527 | "" |
9ebbca7d GK |
528 | "@ |
529 | {andil.|andi.} %2,%1,0xff | |
530 | #" | |
531 | [(set_attr "type" "compare") | |
532 | (set_attr "length" "4,8")]) | |
533 | ||
534 | (define_split | |
535 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
536 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
537 | (const_int 0))) | |
538 | (clobber (match_scratch:SI 2 ""))] | |
539 | "reload_completed" | |
540 | [(set (match_dup 2) | |
541 | (zero_extend:SI (match_dup 1))) | |
542 | (set (match_dup 0) | |
543 | (compare:CC (match_dup 2) | |
544 | (const_int 0)))] | |
545 | "") | |
1fd4e8c1 RK |
546 | |
547 | (define_insn "" | |
9ebbca7d GK |
548 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
549 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 550 | (const_int 0))) |
9ebbca7d | 551 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
552 | (zero_extend:SI (match_dup 1)))] |
553 | "" | |
9ebbca7d GK |
554 | "@ |
555 | {andil.|andi.} %0,%1,0xff | |
556 | #" | |
557 | [(set_attr "type" "compare") | |
558 | (set_attr "length" "4,8")]) | |
559 | ||
560 | (define_split | |
561 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
562 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
563 | (const_int 0))) | |
564 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
565 | (zero_extend:SI (match_dup 1)))] | |
566 | "reload_completed" | |
567 | [(set (match_dup 0) | |
568 | (zero_extend:SI (match_dup 1))) | |
569 | (set (match_dup 2) | |
570 | (compare:CC (match_dup 0) | |
571 | (const_int 0)))] | |
572 | "") | |
1fd4e8c1 | 573 | |
51b8fc2c RK |
574 | (define_expand "extendqisi2" |
575 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
576 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
577 | "" | |
578 | " | |
579 | { | |
580 | if (TARGET_POWERPC) | |
581 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
582 | else if (TARGET_POWER) | |
583 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
584 | else | |
585 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
586 | DONE; | |
587 | }") | |
588 | ||
589 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
590 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
591 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 592 | "TARGET_POWERPC" |
2bee0449 | 593 | "extsb %0,%1") |
51b8fc2c RK |
594 | |
595 | (define_insn "" | |
9ebbca7d GK |
596 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
597 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 598 | (const_int 0))) |
9ebbca7d | 599 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 600 | "TARGET_POWERPC" |
9ebbca7d GK |
601 | "@ |
602 | extsb. %2,%1 | |
603 | #" | |
604 | [(set_attr "type" "compare") | |
605 | (set_attr "length" "4,8")]) | |
606 | ||
607 | (define_split | |
608 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
609 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
610 | (const_int 0))) | |
611 | (clobber (match_scratch:SI 2 ""))] | |
612 | "TARGET_POWERPC && reload_completed" | |
613 | [(set (match_dup 2) | |
614 | (sign_extend:SI (match_dup 1))) | |
615 | (set (match_dup 0) | |
616 | (compare:CC (match_dup 2) | |
617 | (const_int 0)))] | |
618 | "") | |
51b8fc2c RK |
619 | |
620 | (define_insn "" | |
9ebbca7d GK |
621 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
622 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 623 | (const_int 0))) |
9ebbca7d | 624 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
625 | (sign_extend:SI (match_dup 1)))] |
626 | "TARGET_POWERPC" | |
9ebbca7d GK |
627 | "@ |
628 | extsb. %0,%1 | |
629 | #" | |
630 | [(set_attr "type" "compare") | |
631 | (set_attr "length" "4,8")]) | |
632 | ||
633 | (define_split | |
634 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
635 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
636 | (const_int 0))) | |
637 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
638 | (sign_extend:SI (match_dup 1)))] | |
639 | "TARGET_POWERPC && reload_completed" | |
640 | [(set (match_dup 0) | |
641 | (sign_extend:SI (match_dup 1))) | |
642 | (set (match_dup 2) | |
643 | (compare:CC (match_dup 0) | |
644 | (const_int 0)))] | |
645 | "") | |
51b8fc2c RK |
646 | |
647 | (define_expand "extendqisi2_power" | |
648 | [(parallel [(set (match_dup 2) | |
649 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
650 | (const_int 24))) | |
651 | (clobber (scratch:SI))]) | |
652 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
653 | (ashiftrt:SI (match_dup 2) | |
654 | (const_int 24))) | |
655 | (clobber (scratch:SI))])] | |
656 | "TARGET_POWER" | |
657 | " | |
658 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
659 | operands[2] = gen_reg_rtx (SImode); }") | |
660 | ||
661 | (define_expand "extendqisi2_no_power" | |
662 | [(set (match_dup 2) | |
663 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
664 | (const_int 24))) | |
665 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
666 | (ashiftrt:SI (match_dup 2) | |
667 | (const_int 24)))] | |
668 | "! TARGET_POWER && ! TARGET_POWERPC" | |
669 | " | |
670 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
671 | operands[2] = gen_reg_rtx (SImode); }") | |
672 | ||
1fd4e8c1 | 673 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
674 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
675 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
676 | "" |
677 | "") | |
678 | ||
679 | (define_insn "" | |
cd2b37d9 | 680 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
681 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
682 | "" | |
683 | "@ | |
684 | lbz%U1%X1 %0,%1 | |
005a35b9 | 685 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
686 | [(set_attr "type" "load,*")]) |
687 | ||
688 | (define_insn "" | |
9ebbca7d GK |
689 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
690 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 691 | (const_int 0))) |
9ebbca7d | 692 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 693 | "" |
9ebbca7d GK |
694 | "@ |
695 | {andil.|andi.} %2,%1,0xff | |
696 | #" | |
697 | [(set_attr "type" "compare") | |
698 | (set_attr "length" "4,8")]) | |
699 | ||
700 | (define_split | |
701 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
702 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
703 | (const_int 0))) | |
704 | (clobber (match_scratch:HI 2 ""))] | |
705 | "reload_completed" | |
706 | [(set (match_dup 2) | |
707 | (zero_extend:HI (match_dup 1))) | |
708 | (set (match_dup 0) | |
709 | (compare:CC (match_dup 2) | |
710 | (const_int 0)))] | |
711 | "") | |
1fd4e8c1 | 712 | |
51b8fc2c | 713 | (define_insn "" |
9ebbca7d GK |
714 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
715 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 716 | (const_int 0))) |
9ebbca7d | 717 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
718 | (zero_extend:HI (match_dup 1)))] |
719 | "" | |
9ebbca7d GK |
720 | "@ |
721 | {andil.|andi.} %0,%1,0xff | |
722 | #" | |
723 | [(set_attr "type" "compare") | |
724 | (set_attr "length" "4,8")]) | |
725 | ||
726 | (define_split | |
727 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
728 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
729 | (const_int 0))) | |
730 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
731 | (zero_extend:HI (match_dup 1)))] | |
732 | "reload_completed" | |
733 | [(set (match_dup 0) | |
734 | (zero_extend:HI (match_dup 1))) | |
735 | (set (match_dup 2) | |
736 | (compare:CC (match_dup 0) | |
737 | (const_int 0)))] | |
738 | "") | |
815cdc52 MM |
739 | |
740 | (define_expand "extendqihi2" | |
741 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
742 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
743 | "" | |
744 | " | |
745 | { | |
746 | if (TARGET_POWERPC) | |
747 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
748 | else if (TARGET_POWER) | |
749 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
750 | else | |
751 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
752 | DONE; | |
753 | }") | |
754 | ||
755 | (define_insn "extendqihi2_ppc" | |
756 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
757 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
758 | "TARGET_POWERPC" | |
759 | "extsb %0,%1") | |
760 | ||
761 | (define_insn "" | |
9ebbca7d GK |
762 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
763 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 764 | (const_int 0))) |
9ebbca7d | 765 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 766 | "TARGET_POWERPC" |
9ebbca7d GK |
767 | "@ |
768 | extsb. %2,%1 | |
769 | #" | |
770 | [(set_attr "type" "compare") | |
771 | (set_attr "length" "4,8")]) | |
772 | ||
773 | (define_split | |
774 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
775 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
776 | (const_int 0))) | |
777 | (clobber (match_scratch:HI 2 ""))] | |
778 | "TARGET_POWERPC && reload_completed" | |
779 | [(set (match_dup 2) | |
780 | (sign_extend:HI (match_dup 1))) | |
781 | (set (match_dup 0) | |
782 | (compare:CC (match_dup 2) | |
783 | (const_int 0)))] | |
784 | "") | |
815cdc52 MM |
785 | |
786 | (define_insn "" | |
9ebbca7d GK |
787 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
788 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 789 | (const_int 0))) |
9ebbca7d | 790 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
791 | (sign_extend:HI (match_dup 1)))] |
792 | "TARGET_POWERPC" | |
9ebbca7d GK |
793 | "@ |
794 | extsb. %0,%1 | |
795 | #" | |
796 | [(set_attr "type" "compare") | |
797 | (set_attr "length" "4,8")]) | |
798 | ||
799 | (define_split | |
800 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
801 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
802 | (const_int 0))) | |
803 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
804 | (sign_extend:HI (match_dup 1)))] | |
805 | "TARGET_POWERPC && reload_completed" | |
806 | [(set (match_dup 0) | |
807 | (sign_extend:HI (match_dup 1))) | |
808 | (set (match_dup 2) | |
809 | (compare:CC (match_dup 0) | |
810 | (const_int 0)))] | |
811 | "") | |
51b8fc2c RK |
812 | |
813 | (define_expand "extendqihi2_power" | |
814 | [(parallel [(set (match_dup 2) | |
815 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
816 | (const_int 24))) | |
817 | (clobber (scratch:SI))]) | |
818 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
819 | (ashiftrt:SI (match_dup 2) | |
820 | (const_int 24))) | |
821 | (clobber (scratch:SI))])] | |
822 | "TARGET_POWER" | |
823 | " | |
824 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
825 | operands[1] = gen_lowpart (SImode, operands[1]); | |
826 | operands[2] = gen_reg_rtx (SImode); }") | |
827 | ||
828 | (define_expand "extendqihi2_no_power" | |
829 | [(set (match_dup 2) | |
830 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
831 | (const_int 24))) | |
832 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
833 | (ashiftrt:SI (match_dup 2) | |
834 | (const_int 24)))] | |
835 | "! TARGET_POWER && ! TARGET_POWERPC" | |
836 | " | |
837 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
838 | operands[1] = gen_lowpart (SImode, operands[1]); | |
839 | operands[2] = gen_reg_rtx (SImode); }") | |
840 | ||
1fd4e8c1 | 841 | (define_expand "zero_extendhisi2" |
5f243543 | 842 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 843 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
844 | "" |
845 | "") | |
846 | ||
847 | (define_insn "" | |
cd2b37d9 | 848 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
849 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
850 | "" | |
851 | "@ | |
852 | lhz%U1%X1 %0,%1 | |
005a35b9 | 853 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
854 | [(set_attr "type" "load,*")]) |
855 | ||
856 | (define_insn "" | |
9ebbca7d GK |
857 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
858 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 859 | (const_int 0))) |
9ebbca7d | 860 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 861 | "" |
9ebbca7d GK |
862 | "@ |
863 | {andil.|andi.} %2,%1,0xffff | |
864 | #" | |
865 | [(set_attr "type" "compare") | |
866 | (set_attr "length" "4,8")]) | |
867 | ||
868 | (define_split | |
869 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
870 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
871 | (const_int 0))) | |
872 | (clobber (match_scratch:SI 2 ""))] | |
873 | "reload_completed" | |
874 | [(set (match_dup 2) | |
875 | (zero_extend:SI (match_dup 1))) | |
876 | (set (match_dup 0) | |
877 | (compare:CC (match_dup 2) | |
878 | (const_int 0)))] | |
879 | "") | |
1fd4e8c1 RK |
880 | |
881 | (define_insn "" | |
9ebbca7d GK |
882 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
883 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 884 | (const_int 0))) |
9ebbca7d | 885 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
886 | (zero_extend:SI (match_dup 1)))] |
887 | "" | |
9ebbca7d GK |
888 | "@ |
889 | {andil.|andi.} %0,%1,0xffff | |
890 | #" | |
891 | [(set_attr "type" "compare") | |
892 | (set_attr "length" "4,8")]) | |
893 | ||
894 | (define_split | |
895 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
896 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
897 | (const_int 0))) | |
898 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
899 | (zero_extend:SI (match_dup 1)))] | |
900 | "reload_completed" | |
901 | [(set (match_dup 0) | |
902 | (zero_extend:SI (match_dup 1))) | |
903 | (set (match_dup 2) | |
904 | (compare:CC (match_dup 0) | |
905 | (const_int 0)))] | |
906 | "") | |
1fd4e8c1 RK |
907 | |
908 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
909 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
910 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
911 | "" |
912 | "") | |
913 | ||
914 | (define_insn "" | |
cd2b37d9 | 915 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
916 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
917 | "" | |
918 | "@ | |
919 | lha%U1%X1 %0,%1 | |
ca7f5001 | 920 | {exts|extsh} %0,%1" |
b54cf83a | 921 | [(set_attr "type" "load_ext,*")]) |
1fd4e8c1 RK |
922 | |
923 | (define_insn "" | |
9ebbca7d GK |
924 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
925 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 926 | (const_int 0))) |
9ebbca7d | 927 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 928 | "" |
9ebbca7d GK |
929 | "@ |
930 | {exts.|extsh.} %2,%1 | |
931 | #" | |
932 | [(set_attr "type" "compare") | |
933 | (set_attr "length" "4,8")]) | |
934 | ||
935 | (define_split | |
936 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
937 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
938 | (const_int 0))) | |
939 | (clobber (match_scratch:SI 2 ""))] | |
940 | "reload_completed" | |
941 | [(set (match_dup 2) | |
942 | (sign_extend:SI (match_dup 1))) | |
943 | (set (match_dup 0) | |
944 | (compare:CC (match_dup 2) | |
945 | (const_int 0)))] | |
946 | "") | |
1fd4e8c1 RK |
947 | |
948 | (define_insn "" | |
9ebbca7d GK |
949 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
950 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 951 | (const_int 0))) |
9ebbca7d | 952 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
953 | (sign_extend:SI (match_dup 1)))] |
954 | "" | |
9ebbca7d GK |
955 | "@ |
956 | {exts.|extsh.} %0,%1 | |
957 | #" | |
958 | [(set_attr "type" "compare") | |
959 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 960 | \f |
9ebbca7d GK |
961 | (define_split |
962 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
963 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
964 | (const_int 0))) | |
965 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
966 | (sign_extend:SI (match_dup 1)))] | |
967 | "reload_completed" | |
968 | [(set (match_dup 0) | |
969 | (sign_extend:SI (match_dup 1))) | |
970 | (set (match_dup 2) | |
971 | (compare:CC (match_dup 0) | |
972 | (const_int 0)))] | |
973 | "") | |
974 | ||
1fd4e8c1 | 975 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
976 | |
977 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
978 | ;; allowing register zero as source. | |
7cd5235b MM |
979 | (define_expand "addsi3" |
980 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
981 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 982 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
983 | "" |
984 | " | |
985 | { | |
677a9668 DE |
986 | if (GET_CODE (operands[2]) == CONST_INT |
987 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 988 | { |
677a9668 | 989 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
990 | ? operands[0] : gen_reg_rtx (SImode)); |
991 | ||
2bfcf297 | 992 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 993 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 994 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
7cd5235b | 995 | |
9ebbca7d GK |
996 | /* The ordering here is important for the prolog expander. |
997 | When space is allocated from the stack, adding 'low' first may | |
998 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 999 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
1000 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
1001 | DONE; | |
1002 | } | |
1003 | }") | |
1004 | ||
1005 | (define_insn "*addsi3_internal1" | |
1006 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1007 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1008 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1009 | "" |
1010 | "@ | |
deb9225a RK |
1011 | {cax|add} %0,%1,%2 |
1012 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1013 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1014 | {cau|addis} %0,%1,%v2" |
1015 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1016 | |
ee890fe2 SS |
1017 | (define_insn "addsi3_high" |
1018 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1019 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1020 | (high:SI (match_operand 2 "" ""))))] | |
1021 | "TARGET_MACHO && !TARGET_64BIT" | |
1022 | "{cau|addis} %0,%1,ha16(%2)" | |
1023 | [(set_attr "length" "4")]) | |
1024 | ||
7cd5235b | 1025 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1026 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1027 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1028 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1029 | (const_int 0))) |
cb8cc086 | 1030 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
4b8a63d6 | 1031 | "TARGET_32BIT" |
deb9225a RK |
1032 | "@ |
1033 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1034 | {ai.|addic.} %3,%1,%2 |
1035 | # | |
1036 | #" | |
a62bfff2 | 1037 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1038 | (set_attr "length" "4,4,8,8")]) |
1039 | ||
1040 | (define_split | |
1041 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1042 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1043 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1044 | (const_int 0))) | |
1045 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 1046 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1047 | [(set (match_dup 3) |
1048 | (plus:SI (match_dup 1) | |
1049 | (match_dup 2))) | |
1050 | (set (match_dup 0) | |
1051 | (compare:CC (match_dup 3) | |
1052 | (const_int 0)))] | |
1053 | "") | |
7e69e155 | 1054 | |
7cd5235b | 1055 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1056 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1057 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1058 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1059 | (const_int 0))) |
cb8cc086 MM |
1060 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1061 | (plus:SI (match_dup 1) | |
1062 | (match_dup 2)))] | |
4b8a63d6 | 1063 | "TARGET_32BIT" |
deb9225a RK |
1064 | "@ |
1065 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1066 | {ai.|addic.} %0,%1,%2 |
1067 | # | |
1068 | #" | |
a62bfff2 | 1069 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1070 | (set_attr "length" "4,4,8,8")]) |
1071 | ||
1072 | (define_split | |
1073 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1074 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1075 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1076 | (const_int 0))) | |
1077 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1078 | (plus:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 1079 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1080 | [(set (match_dup 0) |
1081 | (plus:SI (match_dup 1) | |
1082 | (match_dup 2))) | |
1083 | (set (match_dup 3) | |
1084 | (compare:CC (match_dup 0) | |
1085 | (const_int 0)))] | |
1086 | "") | |
7e69e155 | 1087 | |
f357808b RK |
1088 | ;; Split an add that we can't do in one insn into two insns, each of which |
1089 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1090 | ;; add should be last in case the result gets used in an address. | |
1091 | ||
1092 | (define_split | |
cd2b37d9 RK |
1093 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1094 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1095 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1096 | "" |
f357808b RK |
1097 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1098 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1099 | " | |
1fd4e8c1 | 1100 | { |
2bfcf297 | 1101 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1102 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1103 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
1fd4e8c1 | 1104 | |
2bfcf297 | 1105 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1106 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1107 | }") |
1108 | ||
8de2a197 | 1109 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1110 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1111 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1112 | "" |
ca7f5001 RK |
1113 | "nor %0,%1,%1") |
1114 | ||
1115 | (define_insn "" | |
52d3af72 DE |
1116 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1117 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1118 | (const_int 0))) |
52d3af72 | 1119 | (clobber (match_scratch:SI 2 "=r,r"))] |
4b8a63d6 | 1120 | "TARGET_32BIT" |
52d3af72 DE |
1121 | "@ |
1122 | nor. %2,%1,%1 | |
1123 | #" | |
1124 | [(set_attr "type" "compare") | |
1125 | (set_attr "length" "4,8")]) | |
1126 | ||
1127 | (define_split | |
1128 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1129 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1130 | (const_int 0))) | |
1131 | (clobber (match_scratch:SI 2 ""))] | |
4b8a63d6 | 1132 | "TARGET_32BIT && reload_completed" |
52d3af72 DE |
1133 | [(set (match_dup 2) |
1134 | (not:SI (match_dup 1))) | |
1135 | (set (match_dup 0) | |
1136 | (compare:CC (match_dup 2) | |
1137 | (const_int 0)))] | |
1138 | "") | |
ca7f5001 RK |
1139 | |
1140 | (define_insn "" | |
52d3af72 DE |
1141 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1142 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1143 | (const_int 0))) |
52d3af72 | 1144 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1145 | (not:SI (match_dup 1)))] |
4b8a63d6 | 1146 | "TARGET_32BIT" |
52d3af72 DE |
1147 | "@ |
1148 | nor. %0,%1,%1 | |
1149 | #" | |
1150 | [(set_attr "type" "compare") | |
1151 | (set_attr "length" "4,8")]) | |
1152 | ||
1153 | (define_split | |
1154 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1155 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1156 | (const_int 0))) | |
1cb18e3c | 1157 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1158 | (not:SI (match_dup 1)))] |
4b8a63d6 | 1159 | "TARGET_32BIT && reload_completed" |
52d3af72 DE |
1160 | [(set (match_dup 0) |
1161 | (not:SI (match_dup 1))) | |
1162 | (set (match_dup 2) | |
1163 | (compare:CC (match_dup 0) | |
1164 | (const_int 0)))] | |
1165 | "") | |
1fd4e8c1 RK |
1166 | |
1167 | (define_insn "" | |
3d91674b RK |
1168 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1169 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1170 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1171 | "! TARGET_POWERPC" |
ca7f5001 | 1172 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1173 | |
deb9225a RK |
1174 | (define_insn "" |
1175 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1176 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1177 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1178 | "TARGET_POWERPC" | |
1179 | "@ | |
1180 | subf %0,%2,%1 | |
1181 | subfic %0,%2,%1") | |
1182 | ||
1fd4e8c1 | 1183 | (define_insn "" |
cb8cc086 MM |
1184 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1185 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1186 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1187 | (const_int 0))) |
cb8cc086 | 1188 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1189 | "! TARGET_POWERPC" |
cb8cc086 MM |
1190 | "@ |
1191 | {sf.|subfc.} %3,%2,%1 | |
1192 | #" | |
1193 | [(set_attr "type" "compare") | |
1194 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1195 | |
deb9225a | 1196 | (define_insn "" |
cb8cc086 MM |
1197 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1198 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1199 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1200 | (const_int 0))) |
cb8cc086 | 1201 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 1202 | "TARGET_POWERPC && TARGET_32BIT" |
cb8cc086 MM |
1203 | "@ |
1204 | subf. %3,%2,%1 | |
1205 | #" | |
a62bfff2 | 1206 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1207 | (set_attr "length" "4,8")]) |
1208 | ||
1209 | (define_split | |
1210 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1211 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1212 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1213 | (const_int 0))) | |
1214 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 1215 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1216 | [(set (match_dup 3) |
1217 | (minus:SI (match_dup 1) | |
1218 | (match_dup 2))) | |
1219 | (set (match_dup 0) | |
1220 | (compare:CC (match_dup 3) | |
1221 | (const_int 0)))] | |
1222 | "") | |
deb9225a | 1223 | |
1fd4e8c1 | 1224 | (define_insn "" |
cb8cc086 MM |
1225 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1226 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1227 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1228 | (const_int 0))) |
cb8cc086 | 1229 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1230 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1231 | "! TARGET_POWERPC" |
cb8cc086 MM |
1232 | "@ |
1233 | {sf.|subfc.} %0,%2,%1 | |
1234 | #" | |
1235 | [(set_attr "type" "compare") | |
1236 | (set_attr "length" "4,8")]) | |
815cdc52 | 1237 | |
29ae5b89 | 1238 | (define_insn "" |
cb8cc086 MM |
1239 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1240 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1241 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1242 | (const_int 0))) |
cb8cc086 MM |
1243 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1244 | (minus:SI (match_dup 1) | |
1245 | (match_dup 2)))] | |
4b8a63d6 | 1246 | "TARGET_POWERPC && TARGET_32BIT" |
90612787 DE |
1247 | "@ |
1248 | subf. %0,%2,%1 | |
1249 | #" | |
a62bfff2 | 1250 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1251 | (set_attr "length" "4,8")]) |
1252 | ||
1253 | (define_split | |
1254 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1255 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1256 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1257 | (const_int 0))) | |
1258 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1259 | (minus:SI (match_dup 1) | |
1260 | (match_dup 2)))] | |
4b8a63d6 | 1261 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1262 | [(set (match_dup 0) |
1263 | (minus:SI (match_dup 1) | |
1264 | (match_dup 2))) | |
1265 | (set (match_dup 3) | |
1266 | (compare:CC (match_dup 0) | |
1267 | (const_int 0)))] | |
1268 | "") | |
deb9225a | 1269 | |
1fd4e8c1 | 1270 | (define_expand "subsi3" |
cd2b37d9 | 1271 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1272 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1273 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1274 | "" |
a0044fb1 RK |
1275 | " |
1276 | { | |
1277 | if (GET_CODE (operands[2]) == CONST_INT) | |
1278 | { | |
1279 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1280 | negate_rtx (SImode, operands[2]))); | |
1281 | DONE; | |
1282 | } | |
1283 | }") | |
1fd4e8c1 RK |
1284 | |
1285 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1286 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1287 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1288 | ;; combine. | |
1fd4e8c1 RK |
1289 | |
1290 | (define_expand "sminsi3" | |
1291 | [(set (match_dup 3) | |
cd2b37d9 | 1292 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1293 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1294 | (const_int 0) | |
1295 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1296 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1297 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1298 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1299 | " |
a3170dc6 AH |
1300 | { |
1301 | if (TARGET_ISEL) | |
1302 | { | |
1303 | operands[2] = force_reg (SImode, operands[2]); | |
1304 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
1305 | DONE; | |
1306 | } | |
1307 | ||
1308 | operands[3] = gen_reg_rtx (SImode); | |
1309 | }") | |
1fd4e8c1 | 1310 | |
95ac8e67 RK |
1311 | (define_split |
1312 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1313 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1314 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1315 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1316 | "TARGET_POWER" |
95ac8e67 RK |
1317 | [(set (match_dup 3) |
1318 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1319 | (const_int 0) | |
1320 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1321 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1322 | "") | |
1323 | ||
1fd4e8c1 RK |
1324 | (define_expand "smaxsi3" |
1325 | [(set (match_dup 3) | |
cd2b37d9 | 1326 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1327 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1328 | (const_int 0) | |
1329 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1330 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1331 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1332 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1333 | " |
a3170dc6 AH |
1334 | { |
1335 | if (TARGET_ISEL) | |
1336 | { | |
1337 | operands[2] = force_reg (SImode, operands[2]); | |
1338 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
1339 | DONE; | |
1340 | } | |
1341 | operands[3] = gen_reg_rtx (SImode); | |
1342 | }") | |
1fd4e8c1 | 1343 | |
95ac8e67 RK |
1344 | (define_split |
1345 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1346 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1347 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1348 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1349 | "TARGET_POWER" |
95ac8e67 RK |
1350 | [(set (match_dup 3) |
1351 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1352 | (const_int 0) | |
1353 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1354 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1355 | "") | |
1356 | ||
1fd4e8c1 | 1357 | (define_expand "uminsi3" |
cd2b37d9 | 1358 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1359 | (match_dup 5))) |
cd2b37d9 | 1360 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1361 | (match_dup 5))) |
1fd4e8c1 RK |
1362 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1363 | (const_int 0) | |
1364 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1365 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1366 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1367 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1368 | " |
bb68ff55 | 1369 | { |
a3170dc6 AH |
1370 | if (TARGET_ISEL) |
1371 | { | |
1372 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
1373 | DONE; | |
1374 | } | |
bb68ff55 MM |
1375 | operands[3] = gen_reg_rtx (SImode); |
1376 | operands[4] = gen_reg_rtx (SImode); | |
1377 | operands[5] = GEN_INT (-2147483647 - 1); | |
1378 | }") | |
1fd4e8c1 RK |
1379 | |
1380 | (define_expand "umaxsi3" | |
cd2b37d9 | 1381 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1382 | (match_dup 5))) |
cd2b37d9 | 1383 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1384 | (match_dup 5))) |
1fd4e8c1 RK |
1385 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1386 | (const_int 0) | |
1387 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1388 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1389 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1390 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1391 | " |
bb68ff55 | 1392 | { |
a3170dc6 AH |
1393 | if (TARGET_ISEL) |
1394 | { | |
1395 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
1396 | DONE; | |
1397 | } | |
bb68ff55 MM |
1398 | operands[3] = gen_reg_rtx (SImode); |
1399 | operands[4] = gen_reg_rtx (SImode); | |
1400 | operands[5] = GEN_INT (-2147483647 - 1); | |
1401 | }") | |
1fd4e8c1 RK |
1402 | |
1403 | (define_insn "" | |
cd2b37d9 RK |
1404 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1405 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1406 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1407 | (const_int 0) |
1408 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1409 | "TARGET_POWER" |
1fd4e8c1 RK |
1410 | "doz%I2 %0,%1,%2") |
1411 | ||
1412 | (define_insn "" | |
9ebbca7d | 1413 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1414 | (compare:CC |
9ebbca7d GK |
1415 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1416 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1417 | (const_int 0) |
1418 | (minus:SI (match_dup 2) (match_dup 1))) | |
1419 | (const_int 0))) | |
9ebbca7d | 1420 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1421 | "TARGET_POWER" |
9ebbca7d GK |
1422 | "@ |
1423 | doz%I2. %3,%1,%2 | |
1424 | #" | |
1425 | [(set_attr "type" "delayed_compare") | |
1426 | (set_attr "length" "4,8")]) | |
1427 | ||
1428 | (define_split | |
1429 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1430 | (compare:CC | |
1431 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1432 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1433 | (const_int 0) | |
1434 | (minus:SI (match_dup 2) (match_dup 1))) | |
1435 | (const_int 0))) | |
1436 | (clobber (match_scratch:SI 3 ""))] | |
1437 | "TARGET_POWER && reload_completed" | |
1438 | [(set (match_dup 3) | |
1439 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1440 | (const_int 0) | |
1441 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1442 | (set (match_dup 0) | |
1443 | (compare:CC (match_dup 3) | |
1444 | (const_int 0)))] | |
1445 | "") | |
1fd4e8c1 RK |
1446 | |
1447 | (define_insn "" | |
9ebbca7d | 1448 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1449 | (compare:CC |
9ebbca7d GK |
1450 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1451 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1452 | (const_int 0) |
1453 | (minus:SI (match_dup 2) (match_dup 1))) | |
1454 | (const_int 0))) | |
9ebbca7d | 1455 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1456 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1457 | (const_int 0) | |
1458 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1459 | "TARGET_POWER" |
9ebbca7d GK |
1460 | "@ |
1461 | doz%I2. %0,%1,%2 | |
1462 | #" | |
1463 | [(set_attr "type" "delayed_compare") | |
1464 | (set_attr "length" "4,8")]) | |
1465 | ||
1466 | (define_split | |
1467 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1468 | (compare:CC | |
1469 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1470 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1471 | (const_int 0) | |
1472 | (minus:SI (match_dup 2) (match_dup 1))) | |
1473 | (const_int 0))) | |
1474 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1475 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1476 | (const_int 0) | |
1477 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1478 | "TARGET_POWER && reload_completed" | |
1479 | [(set (match_dup 0) | |
1480 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1481 | (const_int 0) | |
1482 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1483 | (set (match_dup 3) | |
1484 | (compare:CC (match_dup 0) | |
1485 | (const_int 0)))] | |
1486 | "") | |
1fd4e8c1 RK |
1487 | |
1488 | ;; We don't need abs with condition code because such comparisons should | |
1489 | ;; never be done. | |
ea9be077 MM |
1490 | (define_expand "abssi2" |
1491 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1492 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1493 | "" | |
1494 | " | |
1495 | { | |
a3170dc6 AH |
1496 | if (TARGET_ISEL) |
1497 | { | |
1498 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
1499 | DONE; | |
1500 | } | |
1501 | else if (! TARGET_POWER) | |
ea9be077 MM |
1502 | { |
1503 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1504 | DONE; | |
1505 | } | |
1506 | }") | |
1507 | ||
ea112fc4 | 1508 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
1509 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1510 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1511 | "TARGET_POWER" |
1fd4e8c1 RK |
1512 | "abs %0,%1") |
1513 | ||
a3170dc6 AH |
1514 | (define_insn_and_split "abssi2_isel" |
1515 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1516 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8c48b6f5 | 1517 | (clobber (match_scratch:SI 2 "=&b")) |
a3170dc6 AH |
1518 | (clobber (match_scratch:CC 3 "=y"))] |
1519 | "TARGET_ISEL" | |
1520 | "#" | |
1521 | "&& reload_completed" | |
1522 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
1523 | (set (match_dup 3) | |
1524 | (compare:CC (match_dup 1) | |
1525 | (const_int 0))) | |
1526 | (set (match_dup 0) | |
1527 | (if_then_else:SI (ge (match_dup 3) | |
1528 | (const_int 0)) | |
1529 | (match_dup 1) | |
1530 | (match_dup 2)))] | |
1531 | "") | |
1532 | ||
ea112fc4 | 1533 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 1534 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1535 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 1536 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 1537 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
1538 | "#" |
1539 | "&& reload_completed" | |
ea9be077 MM |
1540 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1541 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1542 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1543 | "") |
1544 | ||
463b558b | 1545 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1546 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1547 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1548 | "TARGET_POWER" |
1fd4e8c1 RK |
1549 | "nabs %0,%1") |
1550 | ||
ea112fc4 | 1551 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 1552 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1553 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 1554 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 1555 | "! TARGET_POWER" |
ea112fc4 DE |
1556 | "#" |
1557 | "&& reload_completed" | |
ea9be077 MM |
1558 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1559 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1560 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1561 | "") |
1562 | ||
1fd4e8c1 | 1563 | (define_insn "negsi2" |
cd2b37d9 RK |
1564 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1565 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1566 | "" |
1567 | "neg %0,%1") | |
1568 | ||
1569 | (define_insn "" | |
9ebbca7d GK |
1570 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1571 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1572 | (const_int 0))) |
9ebbca7d | 1573 | (clobber (match_scratch:SI 2 "=r,r"))] |
4b8a63d6 | 1574 | "TARGET_32BIT" |
9ebbca7d GK |
1575 | "@ |
1576 | neg. %2,%1 | |
1577 | #" | |
a62bfff2 | 1578 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1579 | (set_attr "length" "4,8")]) |
1580 | ||
1581 | (define_split | |
1582 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1583 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1584 | (const_int 0))) | |
1585 | (clobber (match_scratch:SI 2 ""))] | |
4b8a63d6 | 1586 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
1587 | [(set (match_dup 2) |
1588 | (neg:SI (match_dup 1))) | |
1589 | (set (match_dup 0) | |
1590 | (compare:CC (match_dup 2) | |
1591 | (const_int 0)))] | |
1592 | "") | |
1fd4e8c1 RK |
1593 | |
1594 | (define_insn "" | |
9ebbca7d GK |
1595 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1596 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1597 | (const_int 0))) |
9ebbca7d | 1598 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1599 | (neg:SI (match_dup 1)))] |
4b8a63d6 | 1600 | "TARGET_32BIT" |
9ebbca7d GK |
1601 | "@ |
1602 | neg. %0,%1 | |
1603 | #" | |
a62bfff2 | 1604 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1605 | (set_attr "length" "4,8")]) |
1606 | ||
1607 | (define_split | |
1608 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1609 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1610 | (const_int 0))) | |
1611 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1612 | (neg:SI (match_dup 1)))] | |
4b8a63d6 | 1613 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
1614 | [(set (match_dup 0) |
1615 | (neg:SI (match_dup 1))) | |
1616 | (set (match_dup 2) | |
1617 | (compare:CC (match_dup 0) | |
1618 | (const_int 0)))] | |
1619 | "") | |
1fd4e8c1 | 1620 | |
1b1edcfa DE |
1621 | (define_insn "clzsi2" |
1622 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1623 | (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1624 | "" | |
1625 | "{cntlz|cntlzw} %0,%1") | |
1626 | ||
1627 | (define_expand "ctzsi2" | |
4977bab6 | 1628 | [(set (match_dup 2) |
1b1edcfa | 1629 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 1630 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) |
1b1edcfa DE |
1631 | (match_dup 2))) |
1632 | (clobber (scratch:CC))]) | |
d865b122 | 1633 | (set (match_dup 4) (clz:SI (match_dup 3))) |
4977bab6 | 1634 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 1635 | (minus:SI (const_int 31) (match_dup 4)))] |
1fd4e8c1 | 1636 | "" |
4977bab6 ZW |
1637 | { |
1638 | operands[2] = gen_reg_rtx (SImode); | |
1639 | operands[3] = gen_reg_rtx (SImode); | |
1640 | operands[4] = gen_reg_rtx (SImode); | |
1641 | }) | |
6ae08853 | 1642 | |
1b1edcfa DE |
1643 | (define_expand "ffssi2" |
1644 | [(set (match_dup 2) | |
1645 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
1646 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) | |
1647 | (match_dup 2))) | |
1648 | (clobber (scratch:CC))]) | |
1649 | (set (match_dup 4) (clz:SI (match_dup 3))) | |
1650 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1651 | (minus:SI (const_int 32) (match_dup 4)))] | |
4977bab6 | 1652 | "" |
1b1edcfa DE |
1653 | { |
1654 | operands[2] = gen_reg_rtx (SImode); | |
1655 | operands[3] = gen_reg_rtx (SImode); | |
1656 | operands[4] = gen_reg_rtx (SImode); | |
1657 | }) | |
6ae08853 | 1658 | |
ca7f5001 RK |
1659 | (define_expand "mulsi3" |
1660 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1661 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1662 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1663 | "" | |
1664 | " | |
1665 | { | |
1666 | if (TARGET_POWER) | |
68b40e7e | 1667 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1668 | else |
68b40e7e | 1669 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1670 | DONE; |
1671 | }") | |
1672 | ||
68b40e7e | 1673 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1674 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1675 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1676 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1677 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1678 | "TARGET_POWER" |
1679 | "@ | |
1680 | {muls|mullw} %0,%1,%2 | |
1681 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1682 | [(set (attr "type") |
c859cda6 DJ |
1683 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1684 | (const_string "imul3") | |
6ae08853 | 1685 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1686 | (const_string "imul2")] |
1687 | (const_string "imul")))]) | |
ca7f5001 | 1688 | |
68b40e7e | 1689 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1690 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1691 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1692 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1693 | "! TARGET_POWER" |
1fd4e8c1 | 1694 | "@ |
d904e9ed RK |
1695 | {muls|mullw} %0,%1,%2 |
1696 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1697 | [(set (attr "type") |
c859cda6 DJ |
1698 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1699 | (const_string "imul3") | |
6ae08853 | 1700 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1701 | (const_string "imul2")] |
1702 | (const_string "imul")))]) | |
1fd4e8c1 | 1703 | |
9259f3b0 | 1704 | (define_insn "*mulsi3_mq_internal1" |
9ebbca7d GK |
1705 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1706 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1707 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1708 | (const_int 0))) |
9ebbca7d GK |
1709 | (clobber (match_scratch:SI 3 "=r,r")) |
1710 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 1711 | "TARGET_POWER" |
9ebbca7d GK |
1712 | "@ |
1713 | {muls.|mullw.} %3,%1,%2 | |
1714 | #" | |
9259f3b0 | 1715 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1716 | (set_attr "length" "4,8")]) |
1717 | ||
1718 | (define_split | |
1719 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1720 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1721 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1722 | (const_int 0))) | |
1723 | (clobber (match_scratch:SI 3 "")) | |
1724 | (clobber (match_scratch:SI 4 ""))] | |
1725 | "TARGET_POWER && reload_completed" | |
1726 | [(parallel [(set (match_dup 3) | |
1727 | (mult:SI (match_dup 1) (match_dup 2))) | |
1728 | (clobber (match_dup 4))]) | |
1729 | (set (match_dup 0) | |
1730 | (compare:CC (match_dup 3) | |
1731 | (const_int 0)))] | |
1732 | "") | |
ca7f5001 | 1733 | |
9259f3b0 | 1734 | (define_insn "*mulsi3_no_mq_internal1" |
9ebbca7d GK |
1735 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1736 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1737 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1738 | (const_int 0))) |
9ebbca7d | 1739 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 1740 | "! TARGET_POWER" |
9ebbca7d GK |
1741 | "@ |
1742 | {muls.|mullw.} %3,%1,%2 | |
1743 | #" | |
9259f3b0 | 1744 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1745 | (set_attr "length" "4,8")]) |
1746 | ||
1747 | (define_split | |
1748 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1749 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1750 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1751 | (const_int 0))) | |
1752 | (clobber (match_scratch:SI 3 ""))] | |
1753 | "! TARGET_POWER && reload_completed" | |
1754 | [(set (match_dup 3) | |
1755 | (mult:SI (match_dup 1) (match_dup 2))) | |
1756 | (set (match_dup 0) | |
1757 | (compare:CC (match_dup 3) | |
1758 | (const_int 0)))] | |
1759 | "") | |
1fd4e8c1 | 1760 | |
9259f3b0 | 1761 | (define_insn "*mulsi3_mq_internal2" |
9ebbca7d GK |
1762 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1763 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1764 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1765 | (const_int 0))) |
9ebbca7d | 1766 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 1767 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 1768 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 1769 | "TARGET_POWER" |
9ebbca7d GK |
1770 | "@ |
1771 | {muls.|mullw.} %0,%1,%2 | |
1772 | #" | |
9259f3b0 | 1773 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1774 | (set_attr "length" "4,8")]) |
1775 | ||
1776 | (define_split | |
1777 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1778 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1779 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1780 | (const_int 0))) | |
1781 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1782 | (mult:SI (match_dup 1) (match_dup 2))) | |
1783 | (clobber (match_scratch:SI 4 ""))] | |
1784 | "TARGET_POWER && reload_completed" | |
1785 | [(parallel [(set (match_dup 0) | |
1786 | (mult:SI (match_dup 1) (match_dup 2))) | |
1787 | (clobber (match_dup 4))]) | |
1788 | (set (match_dup 3) | |
1789 | (compare:CC (match_dup 0) | |
1790 | (const_int 0)))] | |
1791 | "") | |
ca7f5001 | 1792 | |
9259f3b0 | 1793 | (define_insn "*mulsi3_no_mq_internal2" |
9ebbca7d GK |
1794 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1795 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1796 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1797 | (const_int 0))) |
9ebbca7d | 1798 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 1799 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1800 | "! TARGET_POWER" |
9ebbca7d GK |
1801 | "@ |
1802 | {muls.|mullw.} %0,%1,%2 | |
1803 | #" | |
9259f3b0 | 1804 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1805 | (set_attr "length" "4,8")]) |
1806 | ||
1807 | (define_split | |
1808 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1809 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1810 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1811 | (const_int 0))) | |
1812 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1813 | (mult:SI (match_dup 1) (match_dup 2)))] | |
1814 | "! TARGET_POWER && reload_completed" | |
1815 | [(set (match_dup 0) | |
1816 | (mult:SI (match_dup 1) (match_dup 2))) | |
1817 | (set (match_dup 3) | |
1818 | (compare:CC (match_dup 0) | |
1819 | (const_int 0)))] | |
1820 | "") | |
1fd4e8c1 RK |
1821 | |
1822 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1823 | ;; 0 and remainder to operand 3. | |
1824 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1825 | ||
8ffd9c51 RK |
1826 | (define_expand "divmodsi4" |
1827 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1828 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1829 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 1830 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
1831 | (mod:SI (match_dup 1) (match_dup 2)))])] |
1832 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1833 | " | |
1834 | { | |
1835 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1836 | { | |
39403d82 DE |
1837 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1838 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1839 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1840 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1841 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1842 | DONE; |
1843 | } | |
1844 | }") | |
deb9225a | 1845 | |
bb157ff4 | 1846 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
1847 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1848 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1849 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 1850 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 1851 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1852 | "TARGET_POWER" |
cfb557c4 RK |
1853 | "divs %0,%1,%2" |
1854 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1855 | |
8ffd9c51 RK |
1856 | (define_expand "udivsi3" |
1857 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1858 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1859 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1860 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1861 | " | |
1862 | { | |
1863 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1864 | { | |
39403d82 DE |
1865 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1866 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1867 | emit_insn (gen_quous_call ()); |
39403d82 | 1868 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1869 | DONE; |
1870 | } | |
f192bf8b DE |
1871 | else if (TARGET_POWER) |
1872 | { | |
1873 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1874 | DONE; | |
1875 | } | |
8ffd9c51 | 1876 | }") |
deb9225a | 1877 | |
f192bf8b DE |
1878 | (define_insn "udivsi3_mq" |
1879 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1880 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1881 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1882 | (clobber (match_scratch:SI 3 "=q"))] | |
1883 | "TARGET_POWERPC && TARGET_POWER" | |
1884 | "divwu %0,%1,%2" | |
1885 | [(set_attr "type" "idiv")]) | |
1886 | ||
1887 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1888 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1889 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1890 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1891 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1892 | "divwu %0,%1,%2" |
ca7f5001 RK |
1893 | [(set_attr "type" "idiv")]) |
1894 | ||
1fd4e8c1 | 1895 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1896 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1897 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1898 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1899 | (define_expand "divsi3" |
cd2b37d9 RK |
1900 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1901 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1902 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1903 | "" | |
1904 | " | |
1905 | { | |
ca7f5001 | 1906 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 1907 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
1908 | && exact_log2 (INTVAL (operands[2])) >= 0) |
1909 | ; | |
b6c9286a | 1910 | else if (TARGET_POWERPC) |
f192bf8b DE |
1911 | { |
1912 | operands[2] = force_reg (SImode, operands[2]); | |
1913 | if (TARGET_POWER) | |
1914 | { | |
1915 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1916 | DONE; | |
1917 | } | |
1918 | } | |
b6c9286a | 1919 | else if (TARGET_POWER) |
1fd4e8c1 | 1920 | FAIL; |
405c5495 | 1921 | else |
8ffd9c51 | 1922 | { |
39403d82 DE |
1923 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1924 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1925 | emit_insn (gen_quoss_call ()); |
39403d82 | 1926 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1927 | DONE; |
1928 | } | |
1fd4e8c1 RK |
1929 | }") |
1930 | ||
f192bf8b DE |
1931 | (define_insn "divsi3_mq" |
1932 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1933 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1934 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1935 | (clobber (match_scratch:SI 3 "=q"))] | |
1936 | "TARGET_POWERPC && TARGET_POWER" | |
1937 | "divw %0,%1,%2" | |
1938 | [(set_attr "type" "idiv")]) | |
1939 | ||
1940 | (define_insn "*divsi3_no_mq" | |
1941 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1942 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1943 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1944 | "TARGET_POWERPC && ! TARGET_POWER" | |
1945 | "divw %0,%1,%2" | |
1946 | [(set_attr "type" "idiv")]) | |
1947 | ||
1fd4e8c1 | 1948 | (define_expand "modsi3" |
85644414 RK |
1949 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1950 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1951 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1952 | "" |
1fd4e8c1 RK |
1953 | " |
1954 | { | |
481c7efa | 1955 | int i; |
39b52ba2 RK |
1956 | rtx temp1; |
1957 | rtx temp2; | |
1958 | ||
2bfcf297 | 1959 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 1960 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 1961 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
1962 | FAIL; |
1963 | ||
1964 | temp1 = gen_reg_rtx (SImode); | |
1965 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1966 | |
85644414 | 1967 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1968 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1969 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1970 | DONE; | |
1fd4e8c1 RK |
1971 | }") |
1972 | ||
1973 | (define_insn "" | |
cd2b37d9 RK |
1974 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1975 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
1976 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
1977 | "" | |
ca7f5001 | 1978 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
943c15ed DE |
1979 | [(set_attr "type" "two") |
1980 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
1981 | |
1982 | (define_insn "" | |
9ebbca7d GK |
1983 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1984 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 1985 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 1986 | (const_int 0))) |
9ebbca7d | 1987 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 1988 | "" |
9ebbca7d GK |
1989 | "@ |
1990 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
1991 | #" | |
b19003d8 | 1992 | [(set_attr "type" "compare") |
9ebbca7d GK |
1993 | (set_attr "length" "8,12")]) |
1994 | ||
1995 | (define_split | |
1996 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1997 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 1998 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
1999 | (const_int 0))) |
2000 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 2001 | "reload_completed" |
9ebbca7d GK |
2002 | [(set (match_dup 3) |
2003 | (div:SI (match_dup 1) (match_dup 2))) | |
2004 | (set (match_dup 0) | |
2005 | (compare:CC (match_dup 3) | |
2006 | (const_int 0)))] | |
2007 | "") | |
1fd4e8c1 RK |
2008 | |
2009 | (define_insn "" | |
9ebbca7d GK |
2010 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2011 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2012 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2013 | (const_int 0))) |
9ebbca7d | 2014 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2015 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2016 | "" |
9ebbca7d GK |
2017 | "@ |
2018 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2019 | #" | |
b19003d8 | 2020 | [(set_attr "type" "compare") |
9ebbca7d GK |
2021 | (set_attr "length" "8,12")]) |
2022 | ||
2023 | (define_split | |
2024 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2025 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2026 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2027 | (const_int 0))) |
2028 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2029 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2030 | "reload_completed" |
9ebbca7d GK |
2031 | [(set (match_dup 0) |
2032 | (div:SI (match_dup 1) (match_dup 2))) | |
2033 | (set (match_dup 3) | |
2034 | (compare:CC (match_dup 0) | |
2035 | (const_int 0)))] | |
2036 | "") | |
1fd4e8c1 RK |
2037 | |
2038 | (define_insn "" | |
cd2b37d9 | 2039 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2040 | (udiv:SI |
996a5f59 | 2041 | (plus:DI (ashift:DI |
cd2b37d9 | 2042 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2043 | (const_int 32)) |
23a900dc | 2044 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2045 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2046 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2047 | (umod:SI |
996a5f59 | 2048 | (plus:DI (ashift:DI |
1fd4e8c1 | 2049 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2050 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2051 | (match_dup 3)))] |
ca7f5001 | 2052 | "TARGET_POWER" |
cfb557c4 RK |
2053 | "div %0,%1,%3" |
2054 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2055 | |
2056 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2057 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2058 | ;; have to worry about the branches. So make a few subroutines here. | |
2059 | ;; | |
2060 | ;; First comes the normal case. | |
2061 | (define_expand "udivmodsi4_normal" | |
2062 | [(set (match_dup 4) (const_int 0)) | |
2063 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2064 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2065 | (const_int 32)) |
2066 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2067 | (match_operand:SI 2 "" ""))) | |
2068 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2069 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2070 | (const_int 32)) |
2071 | (zero_extend:DI (match_dup 1))) | |
2072 | (match_dup 2)))])] | |
ca7f5001 | 2073 | "TARGET_POWER" |
1fd4e8c1 RK |
2074 | " |
2075 | { operands[4] = gen_reg_rtx (SImode); }") | |
2076 | ||
2077 | ;; This handles the branches. | |
2078 | (define_expand "udivmodsi4_tests" | |
2079 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2080 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2081 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2082 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2083 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2084 | (set (match_dup 0) (const_int 1)) | |
2085 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2086 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2087 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2088 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2089 | "TARGET_POWER" |
1fd4e8c1 RK |
2090 | " |
2091 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2092 | operands[6] = gen_reg_rtx (CCmode); | |
2093 | }") | |
2094 | ||
2095 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2096 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2097 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2098 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2099 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2100 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2101 | "" |
1fd4e8c1 RK |
2102 | " |
2103 | { | |
2104 | rtx label = 0; | |
2105 | ||
8ffd9c51 | 2106 | if (! TARGET_POWER) |
c4d38ccb MM |
2107 | { |
2108 | if (! TARGET_POWERPC) | |
2109 | { | |
39403d82 DE |
2110 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2111 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2112 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2113 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2114 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2115 | DONE; |
2116 | } | |
2117 | else | |
2118 | FAIL; | |
2119 | } | |
0081a354 | 2120 | |
1fd4e8c1 RK |
2121 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2122 | { | |
2123 | operands[2] = force_reg (SImode, operands[2]); | |
2124 | label = gen_label_rtx (); | |
2125 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2126 | operands[3], label)); | |
2127 | } | |
2128 | else | |
2129 | operands[2] = force_reg (SImode, operands[2]); | |
2130 | ||
2131 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2132 | operands[3])); | |
2133 | if (label) | |
2134 | emit_label (label); | |
2135 | ||
2136 | DONE; | |
2137 | }") | |
0081a354 | 2138 | |
fada905b MM |
2139 | ;; AIX architecture-independent common-mode multiply (DImode), |
2140 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2141 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2142 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2143 | ;; assumed unused if generating common-mode, so ignore. | |
2144 | (define_insn "mulh_call" | |
2145 | [(set (reg:SI 3) | |
2146 | (truncate:SI | |
2147 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2148 | (sign_extend:DI (reg:SI 4))) | |
2149 | (const_int 32)))) | |
cf27b467 | 2150 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2151 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2152 | "bla __mulh" |
2153 | [(set_attr "type" "imul")]) | |
fada905b MM |
2154 | |
2155 | (define_insn "mull_call" | |
2156 | [(set (reg:DI 3) | |
2157 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2158 | (sign_extend:DI (reg:SI 4)))) | |
2159 | (clobber (match_scratch:SI 0 "=l")) | |
2160 | (clobber (reg:SI 0))] | |
2161 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2162 | "bla __mull" |
2163 | [(set_attr "type" "imul")]) | |
fada905b MM |
2164 | |
2165 | (define_insn "divss_call" | |
2166 | [(set (reg:SI 3) | |
2167 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2168 | (set (reg:SI 4) | |
2169 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2170 | (clobber (match_scratch:SI 0 "=l")) | |
2171 | (clobber (reg:SI 0))] | |
2172 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2173 | "bla __divss" |
2174 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2175 | |
2176 | (define_insn "divus_call" | |
8ffd9c51 RK |
2177 | [(set (reg:SI 3) |
2178 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2179 | (set (reg:SI 4) | |
2180 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2181 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2182 | (clobber (reg:SI 0)) |
2183 | (clobber (match_scratch:CC 1 "=x")) | |
2184 | (clobber (reg:CC 69))] | |
2185 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2186 | "bla __divus" |
2187 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2188 | |
2189 | (define_insn "quoss_call" | |
2190 | [(set (reg:SI 3) | |
2191 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2192 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2193 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2194 | "bla __quoss" |
2195 | [(set_attr "type" "idiv")]) | |
0081a354 | 2196 | |
fada905b MM |
2197 | (define_insn "quous_call" |
2198 | [(set (reg:SI 3) | |
2199 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2200 | (clobber (match_scratch:SI 0 "=l")) | |
2201 | (clobber (reg:SI 0)) | |
2202 | (clobber (match_scratch:CC 1 "=x")) | |
2203 | (clobber (reg:CC 69))] | |
2204 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2205 | "bla __quous" |
2206 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2207 | \f |
bb21487f | 2208 | ;; Logical instructions |
dfbdccdb GK |
2209 | ;; The logical instructions are mostly combined by using match_operator, |
2210 | ;; but the plain AND insns are somewhat different because there is no | |
2211 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2212 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2213 | ||
29ae5b89 JL |
2214 | (define_insn "andsi3" |
2215 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2216 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2217 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2218 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2219 | "" |
2220 | "@ | |
2221 | and %0,%1,%2 | |
ca7f5001 RK |
2222 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2223 | {andil.|andi.} %0,%1,%b2 | |
520308bc DE |
2224 | {andiu.|andis.} %0,%1,%u2" |
2225 | [(set_attr "type" "*,*,compare,compare")]) | |
52d3af72 DE |
2226 | |
2227 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2228 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2229 | ;; machines causes an execution serialization |
1fd4e8c1 | 2230 | |
7cd5235b | 2231 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2232 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2233 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2234 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2235 | (const_int 0))) |
52d3af72 DE |
2236 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2237 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2238 | "TARGET_32BIT" |
1fd4e8c1 RK |
2239 | "@ |
2240 | and. %3,%1,%2 | |
ca7f5001 RK |
2241 | {andil.|andi.} %3,%1,%b2 |
2242 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2243 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2244 | # | |
2245 | # | |
2246 | # | |
2247 | #" | |
2248 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2249 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2250 | |
0ba1b2ff AM |
2251 | (define_insn "*andsi3_internal3" |
2252 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2253 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2254 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2255 | (const_int 0))) | |
2256 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2257 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2258 | "TARGET_64BIT" |
0ba1b2ff AM |
2259 | "@ |
2260 | # | |
2261 | {andil.|andi.} %3,%1,%b2 | |
2262 | {andiu.|andis.} %3,%1,%u2 | |
2263 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2264 | # | |
2265 | # | |
2266 | # | |
2267 | #" | |
2268 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2269 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2270 | ||
52d3af72 DE |
2271 | (define_split |
2272 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2273 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2274 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2275 | (const_int 0))) |
52d3af72 DE |
2276 | (clobber (match_scratch:SI 3 "")) |
2277 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2278 | "reload_completed" |
52d3af72 DE |
2279 | [(parallel [(set (match_dup 3) |
2280 | (and:SI (match_dup 1) | |
2281 | (match_dup 2))) | |
2282 | (clobber (match_dup 4))]) | |
2283 | (set (match_dup 0) | |
2284 | (compare:CC (match_dup 3) | |
2285 | (const_int 0)))] | |
2286 | "") | |
2287 | ||
0ba1b2ff AM |
2288 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2289 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2290 | ||
2291 | (define_split | |
2292 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2293 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2294 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2295 | (const_int 0))) | |
2296 | (clobber (match_scratch:SI 3 "")) | |
2297 | (clobber (match_scratch:CC 4 ""))] | |
2298 | "TARGET_POWERPC64 && reload_completed" | |
2299 | [(parallel [(set (match_dup 3) | |
2300 | (and:SI (match_dup 1) | |
2301 | (match_dup 2))) | |
2302 | (clobber (match_dup 4))]) | |
2303 | (set (match_dup 0) | |
2304 | (compare:CC (match_dup 3) | |
2305 | (const_int 0)))] | |
2306 | "") | |
2307 | ||
2308 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2309 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2310 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2311 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2312 | (const_int 0))) |
2313 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2314 | (and:SI (match_dup 1) | |
2315 | (match_dup 2))) | |
2316 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2317 | "TARGET_32BIT" |
1fd4e8c1 RK |
2318 | "@ |
2319 | and. %0,%1,%2 | |
ca7f5001 RK |
2320 | {andil.|andi.} %0,%1,%b2 |
2321 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2322 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2323 | # | |
2324 | # | |
2325 | # | |
2326 | #" | |
2327 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2328 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2329 | ||
0ba1b2ff AM |
2330 | (define_insn "*andsi3_internal5" |
2331 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2332 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2333 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2334 | (const_int 0))) | |
2335 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2336 | (and:SI (match_dup 1) | |
2337 | (match_dup 2))) | |
2338 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2339 | "TARGET_64BIT" |
0ba1b2ff AM |
2340 | "@ |
2341 | # | |
2342 | {andil.|andi.} %0,%1,%b2 | |
2343 | {andiu.|andis.} %0,%1,%u2 | |
2344 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
2345 | # | |
2346 | # | |
2347 | # | |
2348 | #" | |
2349 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2350 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2351 | ||
52d3af72 DE |
2352 | (define_split |
2353 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2354 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2355 | (match_operand:SI 2 "and_operand" "")) | |
2356 | (const_int 0))) | |
2357 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2358 | (and:SI (match_dup 1) | |
2359 | (match_dup 2))) | |
2360 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2361 | "reload_completed" |
52d3af72 DE |
2362 | [(parallel [(set (match_dup 0) |
2363 | (and:SI (match_dup 1) | |
2364 | (match_dup 2))) | |
2365 | (clobber (match_dup 4))]) | |
2366 | (set (match_dup 3) | |
2367 | (compare:CC (match_dup 0) | |
2368 | (const_int 0)))] | |
2369 | "") | |
1fd4e8c1 | 2370 | |
0ba1b2ff AM |
2371 | (define_split |
2372 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
2373 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2374 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2375 | (const_int 0))) | |
2376 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2377 | (and:SI (match_dup 1) | |
2378 | (match_dup 2))) | |
2379 | (clobber (match_scratch:CC 4 ""))] | |
2380 | "TARGET_POWERPC64 && reload_completed" | |
2381 | [(parallel [(set (match_dup 0) | |
2382 | (and:SI (match_dup 1) | |
2383 | (match_dup 2))) | |
2384 | (clobber (match_dup 4))]) | |
2385 | (set (match_dup 3) | |
2386 | (compare:CC (match_dup 0) | |
2387 | (const_int 0)))] | |
2388 | "") | |
2389 | ||
2390 | ;; Handle the PowerPC64 rlwinm corner case | |
2391 | ||
2392 | (define_insn_and_split "*andsi3_internal6" | |
2393 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2394 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2395 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
2396 | "TARGET_POWERPC64" | |
2397 | "#" | |
2398 | "TARGET_POWERPC64" | |
2399 | [(set (match_dup 0) | |
2400 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
2401 | (match_dup 4))) | |
2402 | (set (match_dup 0) | |
2403 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
2404 | " | |
2405 | { | |
2406 | int mb = extract_MB (operands[2]); | |
2407 | int me = extract_ME (operands[2]); | |
2408 | operands[3] = GEN_INT (me + 1); | |
2409 | operands[5] = GEN_INT (32 - (me + 1)); | |
2410 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2411 | }" | |
2412 | [(set_attr "length" "8")]) | |
2413 | ||
7cd5235b | 2414 | (define_expand "iorsi3" |
cd2b37d9 | 2415 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2416 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2417 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2418 | "" |
f357808b RK |
2419 | " |
2420 | { | |
7cd5235b | 2421 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2422 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2423 | { |
2424 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2425 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2426 | ? operands[0] : gen_reg_rtx (SImode)); |
2427 | ||
a260abc9 DE |
2428 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2429 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2430 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2431 | DONE; |
2432 | } | |
f357808b RK |
2433 | }") |
2434 | ||
7cd5235b | 2435 | (define_expand "xorsi3" |
cd2b37d9 | 2436 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2437 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2438 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2439 | "" |
7cd5235b | 2440 | " |
1fd4e8c1 | 2441 | { |
7cd5235b | 2442 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2443 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2444 | { |
2445 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2446 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2447 | ? operands[0] : gen_reg_rtx (SImode)); |
2448 | ||
a260abc9 DE |
2449 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2450 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2451 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2452 | DONE; |
2453 | } | |
1fd4e8c1 RK |
2454 | }") |
2455 | ||
dfbdccdb | 2456 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2457 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2458 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2459 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2460 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2461 | "" |
2462 | "@ | |
dfbdccdb GK |
2463 | %q3 %0,%1,%2 |
2464 | {%q3il|%q3i} %0,%1,%b2 | |
2465 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2466 | |
dfbdccdb | 2467 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2468 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2469 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2470 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2471 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2472 | (const_int 0))) | |
52d3af72 | 2473 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2474 | "TARGET_32BIT" |
52d3af72 | 2475 | "@ |
dfbdccdb | 2476 | %q4. %3,%1,%2 |
52d3af72 DE |
2477 | #" |
2478 | [(set_attr "type" "compare") | |
2479 | (set_attr "length" "4,8")]) | |
2480 | ||
2481 | (define_split | |
2482 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2483 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2484 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2485 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2486 | (const_int 0))) |
52d3af72 | 2487 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2488 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2489 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2490 | (set (match_dup 0) |
2491 | (compare:CC (match_dup 3) | |
2492 | (const_int 0)))] | |
2493 | "") | |
815cdc52 | 2494 | |
dfbdccdb | 2495 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2496 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2497 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2498 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2499 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2500 | (const_int 0))) | |
52d3af72 | 2501 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2502 | (match_dup 4))] |
4b8a63d6 | 2503 | "TARGET_32BIT" |
52d3af72 | 2504 | "@ |
dfbdccdb | 2505 | %q4. %0,%1,%2 |
52d3af72 DE |
2506 | #" |
2507 | [(set_attr "type" "compare") | |
2508 | (set_attr "length" "4,8")]) | |
2509 | ||
2510 | (define_split | |
e72247f4 | 2511 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2512 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2513 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2514 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2515 | (const_int 0))) |
75540af0 | 2516 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2517 | (match_dup 4))] |
4b8a63d6 | 2518 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2519 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2520 | (set (match_dup 3) |
2521 | (compare:CC (match_dup 0) | |
2522 | (const_int 0)))] | |
2523 | "") | |
1fd4e8c1 | 2524 | |
6ae08853 | 2525 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 2526 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
2527 | |
2528 | (define_split | |
2529 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2530 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2531 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2532 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2533 | "" |
dfbdccdb GK |
2534 | [(set (match_dup 0) (match_dup 4)) |
2535 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2536 | " |
2537 | { | |
dfbdccdb GK |
2538 | rtx i; |
2539 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
1c563bed | 2540 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2541 | operands[1], i); |
dfbdccdb | 2542 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1c563bed | 2543 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2544 | operands[0], i); |
a260abc9 DE |
2545 | }") |
2546 | ||
dfbdccdb | 2547 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2548 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2549 | (match_operator:SI 3 "boolean_operator" |
2550 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2551 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2552 | "" |
dfbdccdb | 2553 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2554 | |
dfbdccdb | 2555 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2556 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2557 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2558 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2559 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2560 | (const_int 0))) | |
52d3af72 | 2561 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2562 | "TARGET_32BIT" |
52d3af72 | 2563 | "@ |
dfbdccdb | 2564 | %q4. %3,%2,%1 |
52d3af72 DE |
2565 | #" |
2566 | [(set_attr "type" "compare") | |
2567 | (set_attr "length" "4,8")]) | |
2568 | ||
2569 | (define_split | |
2570 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2571 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2572 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2573 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2574 | (const_int 0))) |
52d3af72 | 2575 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2576 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2577 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2578 | (set (match_dup 0) |
2579 | (compare:CC (match_dup 3) | |
2580 | (const_int 0)))] | |
2581 | "") | |
1fd4e8c1 | 2582 | |
dfbdccdb | 2583 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2584 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2585 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2586 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2587 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2588 | (const_int 0))) | |
52d3af72 | 2589 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2590 | (match_dup 4))] |
4b8a63d6 | 2591 | "TARGET_32BIT" |
52d3af72 | 2592 | "@ |
dfbdccdb | 2593 | %q4. %0,%2,%1 |
52d3af72 DE |
2594 | #" |
2595 | [(set_attr "type" "compare") | |
2596 | (set_attr "length" "4,8")]) | |
2597 | ||
2598 | (define_split | |
e72247f4 | 2599 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2600 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2601 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2602 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2603 | (const_int 0))) |
75540af0 | 2604 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2605 | (match_dup 4))] |
4b8a63d6 | 2606 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2607 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2608 | (set (match_dup 3) |
2609 | (compare:CC (match_dup 0) | |
2610 | (const_int 0)))] | |
2611 | "") | |
2612 | ||
dfbdccdb | 2613 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2614 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2615 | (match_operator:SI 3 "boolean_operator" |
2616 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2617 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2618 | "" |
dfbdccdb | 2619 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2620 | |
dfbdccdb | 2621 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2622 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2623 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2624 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2625 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2626 | (const_int 0))) | |
52d3af72 | 2627 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2628 | "TARGET_32BIT" |
52d3af72 | 2629 | "@ |
dfbdccdb | 2630 | %q4. %3,%1,%2 |
52d3af72 DE |
2631 | #" |
2632 | [(set_attr "type" "compare") | |
2633 | (set_attr "length" "4,8")]) | |
2634 | ||
2635 | (define_split | |
2636 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2637 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2638 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2639 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2640 | (const_int 0))) |
52d3af72 | 2641 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2642 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2643 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2644 | (set (match_dup 0) |
2645 | (compare:CC (match_dup 3) | |
2646 | (const_int 0)))] | |
2647 | "") | |
1fd4e8c1 | 2648 | |
dfbdccdb | 2649 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2650 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2651 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2652 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2653 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2654 | (const_int 0))) | |
52d3af72 | 2655 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2656 | (match_dup 4))] |
4b8a63d6 | 2657 | "TARGET_32BIT" |
52d3af72 | 2658 | "@ |
dfbdccdb | 2659 | %q4. %0,%1,%2 |
52d3af72 DE |
2660 | #" |
2661 | [(set_attr "type" "compare") | |
2662 | (set_attr "length" "4,8")]) | |
2663 | ||
2664 | (define_split | |
e72247f4 | 2665 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2666 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2667 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2668 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2669 | (const_int 0))) |
75540af0 | 2670 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2671 | (match_dup 4))] |
4b8a63d6 | 2672 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2673 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2674 | (set (match_dup 3) |
2675 | (compare:CC (match_dup 0) | |
2676 | (const_int 0)))] | |
2677 | "") | |
1fd4e8c1 RK |
2678 | |
2679 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2680 | ;; orders. Don't define forms that only set CR fields because these | |
2681 | ;; would modify an input register. | |
2682 | ||
7cd5235b | 2683 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2684 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2685 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2686 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2687 | (and:SI (match_dup 2) | |
cd2b37d9 | 2688 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2689 | "TARGET_POWER" |
01def764 | 2690 | "maskir %0,%3,%2") |
1fd4e8c1 | 2691 | |
7cd5235b | 2692 | (define_insn "*maskir_internal2" |
242e8072 | 2693 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2694 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2695 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2696 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2697 | (match_dup 2))))] |
ca7f5001 | 2698 | "TARGET_POWER" |
01def764 | 2699 | "maskir %0,%3,%2") |
1fd4e8c1 | 2700 | |
7cd5235b | 2701 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2702 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2703 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2704 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2705 | (and:SI (not:SI (match_dup 2)) |
2706 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2707 | "TARGET_POWER" |
01def764 | 2708 | "maskir %0,%3,%2") |
1fd4e8c1 | 2709 | |
7cd5235b | 2710 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2711 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2712 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2713 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2714 | (and:SI (not:SI (match_dup 2)) | |
2715 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2716 | "TARGET_POWER" |
01def764 | 2717 | "maskir %0,%3,%2") |
1fd4e8c1 | 2718 | |
7cd5235b | 2719 | (define_insn "*maskir_internal5" |
9ebbca7d | 2720 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2721 | (compare:CC |
9ebbca7d GK |
2722 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2723 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2724 | (and:SI (match_dup 2) |
9ebbca7d | 2725 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2726 | (const_int 0))) |
9ebbca7d | 2727 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2728 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2729 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2730 | "TARGET_POWER" |
9ebbca7d GK |
2731 | "@ |
2732 | maskir. %0,%3,%2 | |
2733 | #" | |
2734 | [(set_attr "type" "compare") | |
2735 | (set_attr "length" "4,8")]) | |
2736 | ||
2737 | (define_split | |
2738 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2739 | (compare:CC | |
2740 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2741 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2742 | (and:SI (match_dup 2) | |
2743 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2744 | (const_int 0))) | |
2745 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2746 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2747 | (and:SI (match_dup 2) (match_dup 3))))] | |
2748 | "TARGET_POWER && reload_completed" | |
2749 | [(set (match_dup 0) | |
2750 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2751 | (and:SI (match_dup 2) (match_dup 3)))) | |
2752 | (set (match_dup 4) | |
2753 | (compare:CC (match_dup 0) | |
2754 | (const_int 0)))] | |
2755 | "") | |
1fd4e8c1 | 2756 | |
7cd5235b | 2757 | (define_insn "*maskir_internal6" |
9ebbca7d | 2758 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2759 | (compare:CC |
9ebbca7d GK |
2760 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2761 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2762 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2763 | (match_dup 2))) |
1fd4e8c1 | 2764 | (const_int 0))) |
9ebbca7d | 2765 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2766 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2767 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2768 | "TARGET_POWER" |
9ebbca7d GK |
2769 | "@ |
2770 | maskir. %0,%3,%2 | |
2771 | #" | |
2772 | [(set_attr "type" "compare") | |
2773 | (set_attr "length" "4,8")]) | |
2774 | ||
2775 | (define_split | |
2776 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2777 | (compare:CC | |
2778 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2779 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2780 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2781 | (match_dup 2))) | |
2782 | (const_int 0))) | |
2783 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2784 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2785 | (and:SI (match_dup 3) (match_dup 2))))] | |
2786 | "TARGET_POWER && reload_completed" | |
2787 | [(set (match_dup 0) | |
2788 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2789 | (and:SI (match_dup 3) (match_dup 2)))) | |
2790 | (set (match_dup 4) | |
2791 | (compare:CC (match_dup 0) | |
2792 | (const_int 0)))] | |
2793 | "") | |
1fd4e8c1 | 2794 | |
7cd5235b | 2795 | (define_insn "*maskir_internal7" |
9ebbca7d | 2796 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 2797 | (compare:CC |
9ebbca7d GK |
2798 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
2799 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2800 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2801 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 2802 | (const_int 0))) |
9ebbca7d | 2803 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
2804 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2805 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2806 | "TARGET_POWER" | |
9ebbca7d GK |
2807 | "@ |
2808 | maskir. %0,%3,%2 | |
2809 | #" | |
2810 | [(set_attr "type" "compare") | |
2811 | (set_attr "length" "4,8")]) | |
2812 | ||
2813 | (define_split | |
2814 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2815 | (compare:CC | |
2816 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
2817 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
2818 | (and:SI (not:SI (match_dup 2)) | |
2819 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2820 | (const_int 0))) | |
2821 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2822 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2823 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2824 | "TARGET_POWER && reload_completed" | |
2825 | [(set (match_dup 0) | |
2826 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2827 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2828 | (set (match_dup 4) | |
2829 | (compare:CC (match_dup 0) | |
2830 | (const_int 0)))] | |
2831 | "") | |
1fd4e8c1 | 2832 | |
7cd5235b | 2833 | (define_insn "*maskir_internal8" |
9ebbca7d | 2834 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2835 | (compare:CC |
9ebbca7d GK |
2836 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
2837 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 2838 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2839 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 2840 | (const_int 0))) |
9ebbca7d | 2841 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2842 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2843 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2844 | "TARGET_POWER" |
9ebbca7d GK |
2845 | "@ |
2846 | maskir. %0,%3,%2 | |
2847 | #" | |
2848 | [(set_attr "type" "compare") | |
2849 | (set_attr "length" "4,8")]) | |
fcce224d | 2850 | |
9ebbca7d GK |
2851 | (define_split |
2852 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2853 | (compare:CC | |
2854 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2855 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2856 | (and:SI (not:SI (match_dup 2)) | |
2857 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2858 | (const_int 0))) | |
2859 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2860 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2861 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2862 | "TARGET_POWER && reload_completed" | |
2863 | [(set (match_dup 0) | |
2864 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2865 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2866 | (set (match_dup 4) | |
2867 | (compare:CC (match_dup 0) | |
2868 | (const_int 0)))] | |
2869 | "") | |
fcce224d | 2870 | \f |
1fd4e8c1 RK |
2871 | ;; Rotate and shift insns, in all their variants. These support shifts, |
2872 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2873 | (define_expand "insv" |
0ad91047 DE |
2874 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2875 | (match_operand:SI 1 "const_int_operand" "") | |
2876 | (match_operand:SI 2 "const_int_operand" "")) | |
2877 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2878 | "" |
2879 | " | |
2880 | { | |
2881 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2882 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2883 | compiler if the address of the structure is taken later. */ | |
2884 | if (GET_CODE (operands[0]) == SUBREG | |
2885 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2886 | FAIL; | |
a78e33fc DE |
2887 | |
2888 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2889 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2890 | else | |
2891 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2892 | DONE; | |
034c1be0 MM |
2893 | }") |
2894 | ||
a78e33fc | 2895 | (define_insn "insvsi" |
cd2b37d9 | 2896 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2897 | (match_operand:SI 1 "const_int_operand" "i") |
2898 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2899 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2900 | "" |
2901 | "* | |
2902 | { | |
2903 | int start = INTVAL (operands[2]) & 31; | |
2904 | int size = INTVAL (operands[1]) & 31; | |
2905 | ||
89e9f3a8 MM |
2906 | operands[4] = GEN_INT (32 - start - size); |
2907 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2908 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2909 | }" |
2910 | [(set_attr "type" "insert_word")]) | |
1fd4e8c1 | 2911 | |
a78e33fc | 2912 | (define_insn "*insvsi_internal1" |
d56d506a RK |
2913 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2914 | (match_operand:SI 1 "const_int_operand" "i") | |
2915 | (match_operand:SI 2 "const_int_operand" "i")) | |
2916 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2917 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2918 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2919 | "* |
2920 | { | |
2921 | int shift = INTVAL (operands[4]) & 31; | |
2922 | int start = INTVAL (operands[2]) & 31; | |
2923 | int size = INTVAL (operands[1]) & 31; | |
2924 | ||
89e9f3a8 MM |
2925 | operands[4] = GEN_INT (shift - start - size); |
2926 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2927 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2928 | }" |
2929 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2930 | |
a78e33fc | 2931 | (define_insn "*insvsi_internal2" |
d56d506a RK |
2932 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2933 | (match_operand:SI 1 "const_int_operand" "i") | |
2934 | (match_operand:SI 2 "const_int_operand" "i")) | |
2935 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2936 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2937 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2938 | "* |
2939 | { | |
2940 | int shift = INTVAL (operands[4]) & 31; | |
2941 | int start = INTVAL (operands[2]) & 31; | |
2942 | int size = INTVAL (operands[1]) & 31; | |
2943 | ||
89e9f3a8 MM |
2944 | operands[4] = GEN_INT (32 - shift - start - size); |
2945 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2946 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2947 | }" |
2948 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2949 | |
a78e33fc | 2950 | (define_insn "*insvsi_internal3" |
d56d506a RK |
2951 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2952 | (match_operand:SI 1 "const_int_operand" "i") | |
2953 | (match_operand:SI 2 "const_int_operand" "i")) | |
2954 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2955 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 2956 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2957 | "* |
2958 | { | |
2959 | int shift = INTVAL (operands[4]) & 31; | |
2960 | int start = INTVAL (operands[2]) & 31; | |
2961 | int size = INTVAL (operands[1]) & 31; | |
2962 | ||
89e9f3a8 MM |
2963 | operands[4] = GEN_INT (32 - shift - start - size); |
2964 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2965 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2966 | }" |
2967 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2968 | |
a78e33fc | 2969 | (define_insn "*insvsi_internal4" |
d56d506a RK |
2970 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2971 | (match_operand:SI 1 "const_int_operand" "i") | |
2972 | (match_operand:SI 2 "const_int_operand" "i")) | |
2973 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2974 | (match_operand:SI 4 "const_int_operand" "i") | |
2975 | (match_operand:SI 5 "const_int_operand" "i")))] | |
2976 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
2977 | "* | |
2978 | { | |
2979 | int extract_start = INTVAL (operands[5]) & 31; | |
2980 | int extract_size = INTVAL (operands[4]) & 31; | |
2981 | int insert_start = INTVAL (operands[2]) & 31; | |
2982 | int insert_size = INTVAL (operands[1]) & 31; | |
2983 | ||
2984 | /* Align extract field with insert field */ | |
3a598fbe | 2985 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 2986 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 2987 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
8e8238f1 DE |
2988 | }" |
2989 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2990 | |
f241bf89 EC |
2991 | ;; combine patterns for rlwimi |
2992 | (define_insn "*insvsi_internal5" | |
2993 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2994 | (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
2995 | (match_operand:SI 1 "mask_operand" "i")) | |
2996 | (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2997 | (match_operand:SI 2 "const_int_operand" "i")) | |
2998 | (match_operand:SI 5 "mask_operand" "i"))))] | |
2999 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3000 | "* | |
3001 | { | |
3002 | int me = extract_ME(operands[5]); | |
3003 | int mb = extract_MB(operands[5]); | |
3004 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3005 | operands[2] = GEN_INT(mb); | |
3006 | operands[1] = GEN_INT(me); | |
3007 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3008 | }" | |
3009 | [(set_attr "type" "insert_word")]) | |
3010 | ||
3011 | (define_insn "*insvsi_internal6" | |
3012 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3013 | (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3014 | (match_operand:SI 2 "const_int_operand" "i")) | |
3015 | (match_operand:SI 5 "mask_operand" "i")) | |
3016 | (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
3017 | (match_operand:SI 1 "mask_operand" "i"))))] | |
3018 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3019 | "* | |
3020 | { | |
3021 | int me = extract_ME(operands[5]); | |
3022 | int mb = extract_MB(operands[5]); | |
3023 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3024 | operands[2] = GEN_INT(mb); | |
3025 | operands[1] = GEN_INT(me); | |
3026 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3027 | }" | |
3028 | [(set_attr "type" "insert_word")]) | |
3029 | ||
a78e33fc | 3030 | (define_insn "insvdi" |
685f3906 | 3031 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3032 | (match_operand:SI 1 "const_int_operand" "i") |
3033 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3034 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3035 | "TARGET_POWERPC64" | |
3036 | "* | |
3037 | { | |
3038 | int start = INTVAL (operands[2]) & 63; | |
3039 | int size = INTVAL (operands[1]) & 63; | |
3040 | ||
a78e33fc DE |
3041 | operands[1] = GEN_INT (64 - start - size); |
3042 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3043 | }") |
3044 | ||
11ac38b2 DE |
3045 | (define_insn "*insvdi_internal2" |
3046 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3047 | (match_operand:SI 1 "const_int_operand" "i") | |
3048 | (match_operand:SI 2 "const_int_operand" "i")) | |
3049 | (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3050 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3051 | "TARGET_POWERPC64 | |
3052 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3053 | "* | |
3054 | { | |
3055 | int shift = INTVAL (operands[4]) & 63; | |
3056 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3057 | int size = INTVAL (operands[1]) & 63; | |
3058 | ||
3059 | operands[4] = GEN_INT (64 - shift - start - size); | |
3060 | operands[2] = GEN_INT (start); | |
3061 | operands[1] = GEN_INT (start + size - 1); | |
3062 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3063 | }") | |
3064 | ||
3065 | (define_insn "*insvdi_internal3" | |
3066 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3067 | (match_operand:SI 1 "const_int_operand" "i") | |
3068 | (match_operand:SI 2 "const_int_operand" "i")) | |
3069 | (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3070 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3071 | "TARGET_POWERPC64 | |
3072 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3073 | "* | |
3074 | { | |
3075 | int shift = INTVAL (operands[4]) & 63; | |
3076 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3077 | int size = INTVAL (operands[1]) & 63; | |
3078 | ||
3079 | operands[4] = GEN_INT (64 - shift - start - size); | |
3080 | operands[2] = GEN_INT (start); | |
3081 | operands[1] = GEN_INT (start + size - 1); | |
3082 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3083 | }") | |
3084 | ||
034c1be0 | 3085 | (define_expand "extzv" |
0ad91047 DE |
3086 | [(set (match_operand 0 "gpc_reg_operand" "") |
3087 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3088 | (match_operand:SI 2 "const_int_operand" "") | |
3089 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3090 | "" |
3091 | " | |
3092 | { | |
3093 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3094 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3095 | compiler if the address of the structure is taken later. */ | |
3096 | if (GET_CODE (operands[0]) == SUBREG | |
3097 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3098 | FAIL; | |
a78e33fc DE |
3099 | |
3100 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3101 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3102 | else | |
3103 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3104 | DONE; | |
034c1be0 MM |
3105 | }") |
3106 | ||
a78e33fc | 3107 | (define_insn "extzvsi" |
cd2b37d9 RK |
3108 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3109 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3110 | (match_operand:SI 2 "const_int_operand" "i") |
3111 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3112 | "" | |
3113 | "* | |
3114 | { | |
3115 | int start = INTVAL (operands[3]) & 31; | |
3116 | int size = INTVAL (operands[2]) & 31; | |
3117 | ||
3118 | if (start + size >= 32) | |
3119 | operands[3] = const0_rtx; | |
3120 | else | |
89e9f3a8 | 3121 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3122 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3123 | }") |
3124 | ||
a78e33fc | 3125 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3126 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3127 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3128 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3129 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3130 | (const_int 0))) |
9ebbca7d | 3131 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3132 | "" |
1fd4e8c1 RK |
3133 | "* |
3134 | { | |
3135 | int start = INTVAL (operands[3]) & 31; | |
3136 | int size = INTVAL (operands[2]) & 31; | |
3137 | ||
9ebbca7d GK |
3138 | /* Force split for non-cc0 compare. */ |
3139 | if (which_alternative == 1) | |
3140 | return \"#\"; | |
3141 | ||
43a88a8c | 3142 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3143 | word, it is possible to use andiu. or andil. to test it. This is |
3144 | useful because the condition register set-use delay is smaller for | |
3145 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3146 | position is 0 because the LT and GT bits may be set wrong. */ | |
3147 | ||
3148 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3149 | { |
3a598fbe | 3150 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3151 | - (1 << (16 - (start & 15) - size)))); |
3152 | if (start < 16) | |
ca7f5001 | 3153 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3154 | else |
ca7f5001 | 3155 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3156 | } |
7e69e155 | 3157 | |
1fd4e8c1 RK |
3158 | if (start + size >= 32) |
3159 | operands[3] = const0_rtx; | |
3160 | else | |
89e9f3a8 | 3161 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3162 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3163 | }" |
9ebbca7d GK |
3164 | [(set_attr "type" "compare") |
3165 | (set_attr "length" "4,8")]) | |
3166 | ||
3167 | (define_split | |
3168 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3169 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3170 | (match_operand:SI 2 "const_int_operand" "") | |
3171 | (match_operand:SI 3 "const_int_operand" "")) | |
3172 | (const_int 0))) | |
3173 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3174 | "reload_completed" |
9ebbca7d GK |
3175 | [(set (match_dup 4) |
3176 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3177 | (match_dup 3))) | |
3178 | (set (match_dup 0) | |
3179 | (compare:CC (match_dup 4) | |
3180 | (const_int 0)))] | |
3181 | "") | |
1fd4e8c1 | 3182 | |
a78e33fc | 3183 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3184 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3185 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3186 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3187 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3188 | (const_int 0))) |
9ebbca7d | 3189 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3190 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3191 | "" |
1fd4e8c1 RK |
3192 | "* |
3193 | { | |
3194 | int start = INTVAL (operands[3]) & 31; | |
3195 | int size = INTVAL (operands[2]) & 31; | |
3196 | ||
9ebbca7d GK |
3197 | /* Force split for non-cc0 compare. */ |
3198 | if (which_alternative == 1) | |
3199 | return \"#\"; | |
3200 | ||
bc401279 | 3201 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3202 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3203 | if (start >= 16 && start + size == 32) |
df031c43 | 3204 | { |
bc401279 AM |
3205 | operands[3] = GEN_INT ((1 << size) - 1); |
3206 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3207 | } |
7e69e155 | 3208 | |
1fd4e8c1 RK |
3209 | if (start + size >= 32) |
3210 | operands[3] = const0_rtx; | |
3211 | else | |
89e9f3a8 | 3212 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3213 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3214 | }" |
ce71f754 | 3215 | [(set_attr "type" "compare") |
9ebbca7d GK |
3216 | (set_attr "length" "4,8")]) |
3217 | ||
3218 | (define_split | |
3219 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3220 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3221 | (match_operand:SI 2 "const_int_operand" "") | |
3222 | (match_operand:SI 3 "const_int_operand" "")) | |
3223 | (const_int 0))) | |
3224 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3225 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3226 | "reload_completed" |
9ebbca7d GK |
3227 | [(set (match_dup 0) |
3228 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3229 | (set (match_dup 4) | |
3230 | (compare:CC (match_dup 0) | |
3231 | (const_int 0)))] | |
3232 | "") | |
1fd4e8c1 | 3233 | |
a78e33fc | 3234 | (define_insn "extzvdi" |
685f3906 DE |
3235 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3236 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3237 | (match_operand:SI 2 "const_int_operand" "i") |
3238 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3239 | "TARGET_POWERPC64" |
3240 | "* | |
3241 | { | |
3242 | int start = INTVAL (operands[3]) & 63; | |
3243 | int size = INTVAL (operands[2]) & 63; | |
3244 | ||
3245 | if (start + size >= 64) | |
3246 | operands[3] = const0_rtx; | |
3247 | else | |
89e9f3a8 MM |
3248 | operands[3] = GEN_INT (start + size); |
3249 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3250 | return \"rldicl %0,%1,%3,%2\"; |
3251 | }") | |
3252 | ||
a78e33fc | 3253 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3254 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3255 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3256 | (match_operand:SI 2 "const_int_operand" "i") |
3257 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3258 | (const_int 0))) |
29ae5b89 | 3259 | (clobber (match_scratch:DI 4 "=r"))] |
683bdff7 | 3260 | "TARGET_64BIT" |
685f3906 DE |
3261 | "* |
3262 | { | |
3263 | int start = INTVAL (operands[3]) & 63; | |
3264 | int size = INTVAL (operands[2]) & 63; | |
3265 | ||
3266 | if (start + size >= 64) | |
3267 | operands[3] = const0_rtx; | |
3268 | else | |
89e9f3a8 MM |
3269 | operands[3] = GEN_INT (start + size); |
3270 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3271 | return \"rldicl. %4,%1,%3,%2\"; |
9a3c428b DE |
3272 | }" |
3273 | [(set_attr "type" "compare")]) | |
685f3906 | 3274 | |
a78e33fc | 3275 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3276 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3277 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3278 | (match_operand:SI 2 "const_int_operand" "i") |
3279 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3280 | (const_int 0))) |
29ae5b89 | 3281 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 | 3282 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
683bdff7 | 3283 | "TARGET_64BIT" |
685f3906 DE |
3284 | "* |
3285 | { | |
3286 | int start = INTVAL (operands[3]) & 63; | |
3287 | int size = INTVAL (operands[2]) & 63; | |
3288 | ||
3289 | if (start + size >= 64) | |
3290 | operands[3] = const0_rtx; | |
3291 | else | |
89e9f3a8 MM |
3292 | operands[3] = GEN_INT (start + size); |
3293 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3294 | return \"rldicl. %0,%1,%3,%2\"; |
9a3c428b DE |
3295 | }" |
3296 | [(set_attr "type" "compare")]) | |
685f3906 | 3297 | |
1fd4e8c1 | 3298 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3299 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3300 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3301 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3302 | "" | |
ca7f5001 | 3303 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3304 | |
a260abc9 | 3305 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3306 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3307 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3308 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3309 | (const_int 0))) |
9ebbca7d | 3310 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 3311 | "" |
9ebbca7d GK |
3312 | "@ |
3313 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3314 | #" | |
3315 | [(set_attr "type" "delayed_compare") | |
3316 | (set_attr "length" "4,8")]) | |
3317 | ||
3318 | (define_split | |
3319 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3320 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3321 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3322 | (const_int 0))) | |
3323 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 3324 | "reload_completed" |
9ebbca7d GK |
3325 | [(set (match_dup 3) |
3326 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3327 | (set (match_dup 0) | |
3328 | (compare:CC (match_dup 3) | |
3329 | (const_int 0)))] | |
3330 | "") | |
1fd4e8c1 | 3331 | |
a260abc9 | 3332 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3333 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3334 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3335 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3336 | (const_int 0))) |
9ebbca7d | 3337 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3338 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 3339 | "" |
9ebbca7d GK |
3340 | "@ |
3341 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3342 | #" | |
3343 | [(set_attr "type" "delayed_compare") | |
3344 | (set_attr "length" "4,8")]) | |
3345 | ||
3346 | (define_split | |
3347 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3348 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3349 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3350 | (const_int 0))) | |
3351 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3352 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 3353 | "reload_completed" |
9ebbca7d GK |
3354 | [(set (match_dup 0) |
3355 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3356 | (set (match_dup 3) | |
3357 | (compare:CC (match_dup 0) | |
3358 | (const_int 0)))] | |
3359 | "") | |
1fd4e8c1 | 3360 | |
a260abc9 | 3361 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3362 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3363 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3364 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 3365 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3366 | "" |
ca7f5001 | 3367 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3368 | |
a260abc9 | 3369 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3370 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3371 | (compare:CC (and:SI |
9ebbca7d GK |
3372 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3373 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3374 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3375 | (const_int 0))) |
9ebbca7d | 3376 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3377 | "" |
9ebbca7d GK |
3378 | "@ |
3379 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3380 | #" | |
3381 | [(set_attr "type" "delayed_compare") | |
3382 | (set_attr "length" "4,8")]) | |
3383 | ||
3384 | (define_split | |
3385 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3386 | (compare:CC (and:SI | |
3387 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3388 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3389 | (match_operand:SI 3 "mask_operand" "")) | |
3390 | (const_int 0))) | |
3391 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3392 | "reload_completed" |
9ebbca7d GK |
3393 | [(set (match_dup 4) |
3394 | (and:SI (rotate:SI (match_dup 1) | |
3395 | (match_dup 2)) | |
3396 | (match_dup 3))) | |
3397 | (set (match_dup 0) | |
3398 | (compare:CC (match_dup 4) | |
3399 | (const_int 0)))] | |
3400 | "") | |
1fd4e8c1 | 3401 | |
a260abc9 | 3402 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3403 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3404 | (compare:CC (and:SI |
9ebbca7d GK |
3405 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3406 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3407 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3408 | (const_int 0))) |
9ebbca7d | 3409 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3410 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3411 | "" |
9ebbca7d GK |
3412 | "@ |
3413 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3414 | #" | |
3415 | [(set_attr "type" "delayed_compare") | |
3416 | (set_attr "length" "4,8")]) | |
3417 | ||
3418 | (define_split | |
3419 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3420 | (compare:CC (and:SI | |
3421 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3422 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3423 | (match_operand:SI 3 "mask_operand" "")) | |
3424 | (const_int 0))) | |
3425 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3426 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3427 | "reload_completed" |
9ebbca7d GK |
3428 | [(set (match_dup 0) |
3429 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3430 | (set (match_dup 4) | |
3431 | (compare:CC (match_dup 0) | |
3432 | (const_int 0)))] | |
3433 | "") | |
1fd4e8c1 | 3434 | |
a260abc9 | 3435 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3436 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3437 | (zero_extend:SI |
3438 | (subreg:QI | |
cd2b37d9 | 3439 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3440 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3441 | "" | |
ca7f5001 | 3442 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3443 | |
a260abc9 | 3444 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3445 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3446 | (compare:CC (zero_extend:SI |
3447 | (subreg:QI | |
9ebbca7d GK |
3448 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3449 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3450 | (const_int 0))) |
9ebbca7d | 3451 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3452 | "" |
9ebbca7d GK |
3453 | "@ |
3454 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3455 | #" | |
3456 | [(set_attr "type" "delayed_compare") | |
3457 | (set_attr "length" "4,8")]) | |
3458 | ||
3459 | (define_split | |
3460 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3461 | (compare:CC (zero_extend:SI | |
3462 | (subreg:QI | |
3463 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3464 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3465 | (const_int 0))) | |
3466 | (clobber (match_scratch:SI 3 ""))] | |
3467 | "reload_completed" | |
3468 | [(set (match_dup 3) | |
3469 | (zero_extend:SI (subreg:QI | |
3470 | (rotate:SI (match_dup 1) | |
3471 | (match_dup 2)) 0))) | |
3472 | (set (match_dup 0) | |
3473 | (compare:CC (match_dup 3) | |
3474 | (const_int 0)))] | |
3475 | "") | |
1fd4e8c1 | 3476 | |
a260abc9 | 3477 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3478 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3479 | (compare:CC (zero_extend:SI |
3480 | (subreg:QI | |
9ebbca7d GK |
3481 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3482 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3483 | (const_int 0))) |
9ebbca7d | 3484 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3485 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3486 | "" | |
9ebbca7d GK |
3487 | "@ |
3488 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3489 | #" | |
3490 | [(set_attr "type" "delayed_compare") | |
3491 | (set_attr "length" "4,8")]) | |
3492 | ||
3493 | (define_split | |
3494 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3495 | (compare:CC (zero_extend:SI | |
3496 | (subreg:QI | |
3497 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3498 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3499 | (const_int 0))) | |
3500 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3501 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3502 | "reload_completed" | |
3503 | [(set (match_dup 0) | |
3504 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3505 | (set (match_dup 3) | |
3506 | (compare:CC (match_dup 0) | |
3507 | (const_int 0)))] | |
3508 | "") | |
1fd4e8c1 | 3509 | |
a260abc9 | 3510 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3511 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3512 | (zero_extend:SI |
3513 | (subreg:HI | |
cd2b37d9 | 3514 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3515 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3516 | "" | |
ca7f5001 | 3517 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3518 | |
a260abc9 | 3519 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3520 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3521 | (compare:CC (zero_extend:SI |
3522 | (subreg:HI | |
9ebbca7d GK |
3523 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3524 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3525 | (const_int 0))) |
9ebbca7d | 3526 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3527 | "" |
9ebbca7d GK |
3528 | "@ |
3529 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3530 | #" | |
3531 | [(set_attr "type" "delayed_compare") | |
3532 | (set_attr "length" "4,8")]) | |
3533 | ||
3534 | (define_split | |
3535 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3536 | (compare:CC (zero_extend:SI | |
3537 | (subreg:HI | |
3538 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3539 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3540 | (const_int 0))) | |
3541 | (clobber (match_scratch:SI 3 ""))] | |
3542 | "reload_completed" | |
3543 | [(set (match_dup 3) | |
3544 | (zero_extend:SI (subreg:HI | |
3545 | (rotate:SI (match_dup 1) | |
3546 | (match_dup 2)) 0))) | |
3547 | (set (match_dup 0) | |
3548 | (compare:CC (match_dup 3) | |
3549 | (const_int 0)))] | |
3550 | "") | |
1fd4e8c1 | 3551 | |
a260abc9 | 3552 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3553 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3554 | (compare:CC (zero_extend:SI |
3555 | (subreg:HI | |
9ebbca7d GK |
3556 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3557 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3558 | (const_int 0))) |
9ebbca7d | 3559 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3560 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3561 | "" | |
9ebbca7d GK |
3562 | "@ |
3563 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3564 | #" | |
3565 | [(set_attr "type" "delayed_compare") | |
3566 | (set_attr "length" "4,8")]) | |
3567 | ||
3568 | (define_split | |
3569 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3570 | (compare:CC (zero_extend:SI | |
3571 | (subreg:HI | |
3572 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3573 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3574 | (const_int 0))) | |
3575 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3576 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3577 | "reload_completed" | |
3578 | [(set (match_dup 0) | |
3579 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3580 | (set (match_dup 3) | |
3581 | (compare:CC (match_dup 0) | |
3582 | (const_int 0)))] | |
3583 | "") | |
1fd4e8c1 RK |
3584 | |
3585 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3586 | ;; SHIFT_COUNT_TRUNCATED. | |
3587 | ||
ca7f5001 RK |
3588 | (define_expand "ashlsi3" |
3589 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3590 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3591 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3592 | "" | |
3593 | " | |
3594 | { | |
3595 | if (TARGET_POWER) | |
3596 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3597 | else | |
25c341fa | 3598 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3599 | DONE; |
3600 | }") | |
3601 | ||
3602 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3603 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3604 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3605 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3606 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3607 | "TARGET_POWER" |
1fd4e8c1 RK |
3608 | "@ |
3609 | sle %0,%1,%2 | |
9ebbca7d | 3610 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3611 | |
25c341fa | 3612 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3613 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3614 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3615 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3616 | "! TARGET_POWER" |
9ebbca7d | 3617 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3618 | |
3619 | (define_insn "" | |
9ebbca7d GK |
3620 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3621 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3622 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3623 | (const_int 0))) |
9ebbca7d GK |
3624 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3625 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3626 | "TARGET_POWER" |
1fd4e8c1 RK |
3627 | "@ |
3628 | sle. %3,%1,%2 | |
9ebbca7d GK |
3629 | {sli.|slwi.} %3,%1,%h2 |
3630 | # | |
3631 | #" | |
3632 | [(set_attr "type" "delayed_compare") | |
3633 | (set_attr "length" "4,4,8,8")]) | |
3634 | ||
3635 | (define_split | |
3636 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3637 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3638 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3639 | (const_int 0))) | |
3640 | (clobber (match_scratch:SI 3 "")) | |
3641 | (clobber (match_scratch:SI 4 ""))] | |
3642 | "TARGET_POWER && reload_completed" | |
3643 | [(parallel [(set (match_dup 3) | |
3644 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3645 | (clobber (match_dup 4))]) | |
3646 | (set (match_dup 0) | |
3647 | (compare:CC (match_dup 3) | |
3648 | (const_int 0)))] | |
3649 | "") | |
25c341fa | 3650 | |
ca7f5001 | 3651 | (define_insn "" |
9ebbca7d GK |
3652 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3653 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3654 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3655 | (const_int 0))) |
9ebbca7d | 3656 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 3657 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3658 | "@ |
3659 | {sl|slw}%I2. %3,%1,%h2 | |
3660 | #" | |
3661 | [(set_attr "type" "delayed_compare") | |
3662 | (set_attr "length" "4,8")]) | |
3663 | ||
3664 | (define_split | |
3665 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3666 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3667 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3668 | (const_int 0))) | |
3669 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3670 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3671 | [(set (match_dup 3) |
3672 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3673 | (set (match_dup 0) | |
3674 | (compare:CC (match_dup 3) | |
3675 | (const_int 0)))] | |
3676 | "") | |
1fd4e8c1 RK |
3677 | |
3678 | (define_insn "" | |
9ebbca7d GK |
3679 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3680 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3681 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3682 | (const_int 0))) |
9ebbca7d | 3683 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3684 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3685 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3686 | "TARGET_POWER" |
1fd4e8c1 RK |
3687 | "@ |
3688 | sle. %0,%1,%2 | |
9ebbca7d GK |
3689 | {sli.|slwi.} %0,%1,%h2 |
3690 | # | |
3691 | #" | |
3692 | [(set_attr "type" "delayed_compare") | |
3693 | (set_attr "length" "4,4,8,8")]) | |
3694 | ||
3695 | (define_split | |
3696 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3697 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3698 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3699 | (const_int 0))) | |
3700 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3701 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3702 | (clobber (match_scratch:SI 4 ""))] | |
3703 | "TARGET_POWER && reload_completed" | |
3704 | [(parallel [(set (match_dup 0) | |
3705 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3706 | (clobber (match_dup 4))]) | |
3707 | (set (match_dup 3) | |
3708 | (compare:CC (match_dup 0) | |
3709 | (const_int 0)))] | |
3710 | "") | |
25c341fa | 3711 | |
ca7f5001 | 3712 | (define_insn "" |
9ebbca7d GK |
3713 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3714 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3715 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3716 | (const_int 0))) |
9ebbca7d | 3717 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3718 | (ashift:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3719 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3720 | "@ |
3721 | {sl|slw}%I2. %0,%1,%h2 | |
3722 | #" | |
3723 | [(set_attr "type" "delayed_compare") | |
3724 | (set_attr "length" "4,8")]) | |
3725 | ||
3726 | (define_split | |
3727 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3728 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3729 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3730 | (const_int 0))) | |
3731 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3732 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3733 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3734 | [(set (match_dup 0) |
3735 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3736 | (set (match_dup 3) | |
3737 | (compare:CC (match_dup 0) | |
3738 | (const_int 0)))] | |
3739 | "") | |
1fd4e8c1 RK |
3740 | |
3741 | (define_insn "" | |
cd2b37d9 RK |
3742 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3743 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3744 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3745 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3746 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3747 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3748 | |
3749 | (define_insn "" | |
9ebbca7d | 3750 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3751 | (compare:CC |
9ebbca7d GK |
3752 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3753 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3754 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3755 | (const_int 0))) |
9ebbca7d | 3756 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3757 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3758 | "@ |
3759 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3760 | #" | |
3761 | [(set_attr "type" "delayed_compare") | |
3762 | (set_attr "length" "4,8")]) | |
3763 | ||
3764 | (define_split | |
3765 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3766 | (compare:CC | |
3767 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3768 | (match_operand:SI 2 "const_int_operand" "")) | |
3769 | (match_operand:SI 3 "mask_operand" "")) | |
3770 | (const_int 0))) | |
3771 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3772 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3773 | [(set (match_dup 4) |
3774 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3775 | (match_dup 3))) | |
3776 | (set (match_dup 0) | |
3777 | (compare:CC (match_dup 4) | |
3778 | (const_int 0)))] | |
3779 | "") | |
1fd4e8c1 RK |
3780 | |
3781 | (define_insn "" | |
9ebbca7d | 3782 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3783 | (compare:CC |
9ebbca7d GK |
3784 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3785 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3786 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3787 | (const_int 0))) |
9ebbca7d | 3788 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3789 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3790 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3791 | "@ |
3792 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3793 | #" | |
3794 | [(set_attr "type" "delayed_compare") | |
3795 | (set_attr "length" "4,8")]) | |
3796 | ||
3797 | (define_split | |
3798 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3799 | (compare:CC | |
3800 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3801 | (match_operand:SI 2 "const_int_operand" "")) | |
3802 | (match_operand:SI 3 "mask_operand" "")) | |
3803 | (const_int 0))) | |
3804 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3805 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3806 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3807 | [(set (match_dup 0) |
3808 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3809 | (set (match_dup 4) | |
3810 | (compare:CC (match_dup 0) | |
3811 | (const_int 0)))] | |
3812 | "") | |
1fd4e8c1 | 3813 | |
ca7f5001 | 3814 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3815 | ;; "sli x,x,0". |
ca7f5001 RK |
3816 | (define_expand "lshrsi3" |
3817 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3818 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3819 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3820 | "" | |
3821 | " | |
3822 | { | |
3823 | if (TARGET_POWER) | |
3824 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3825 | else | |
25c341fa | 3826 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3827 | DONE; |
3828 | }") | |
3829 | ||
3830 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3831 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3832 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3833 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3834 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3835 | "TARGET_POWER" |
1fd4e8c1 RK |
3836 | "@ |
3837 | sre %0,%1,%2 | |
bdf423cb | 3838 | mr %0,%1 |
ca7f5001 RK |
3839 | {s%A2i|s%A2wi} %0,%1,%h2") |
3840 | ||
25c341fa | 3841 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3842 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3843 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3844 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3845 | "! TARGET_POWER" |
bdf423cb MM |
3846 | "@ |
3847 | mr %0,%1 | |
3848 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3849 | |
3850 | (define_insn "" | |
9ebbca7d GK |
3851 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3852 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3853 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3854 | (const_int 0))) |
9ebbca7d GK |
3855 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3856 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3857 | "TARGET_POWER" |
1fd4e8c1 | 3858 | "@ |
29ae5b89 JL |
3859 | sre. %3,%1,%2 |
3860 | mr. %1,%1 | |
9ebbca7d GK |
3861 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
3862 | # | |
3863 | # | |
3864 | #" | |
3865 | [(set_attr "type" "delayed_compare") | |
3866 | (set_attr "length" "4,4,4,8,8,8")]) | |
3867 | ||
3868 | (define_split | |
3869 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3870 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3871 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3872 | (const_int 0))) | |
3873 | (clobber (match_scratch:SI 3 "")) | |
3874 | (clobber (match_scratch:SI 4 ""))] | |
3875 | "TARGET_POWER && reload_completed" | |
3876 | [(parallel [(set (match_dup 3) | |
3877 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3878 | (clobber (match_dup 4))]) | |
3879 | (set (match_dup 0) | |
3880 | (compare:CC (match_dup 3) | |
3881 | (const_int 0)))] | |
3882 | "") | |
ca7f5001 RK |
3883 | |
3884 | (define_insn "" | |
9ebbca7d GK |
3885 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3886 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3887 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 3888 | (const_int 0))) |
9ebbca7d | 3889 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
4b8a63d6 | 3890 | "! TARGET_POWER && TARGET_32BIT" |
bdf423cb MM |
3891 | "@ |
3892 | mr. %1,%1 | |
9ebbca7d GK |
3893 | {sr|srw}%I2. %3,%1,%h2 |
3894 | # | |
3895 | #" | |
3896 | [(set_attr "type" "delayed_compare") | |
3897 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 3898 | |
9ebbca7d GK |
3899 | (define_split |
3900 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3901 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3902 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3903 | (const_int 0))) | |
3904 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3905 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3906 | [(set (match_dup 3) |
3907 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3908 | (set (match_dup 0) | |
3909 | (compare:CC (match_dup 3) | |
3910 | (const_int 0)))] | |
3911 | "") | |
3912 | ||
3913 | (define_insn "" | |
3914 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
3915 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3916 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3917 | (const_int 0))) |
9ebbca7d | 3918 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 3919 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3920 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 3921 | "TARGET_POWER" |
1fd4e8c1 | 3922 | "@ |
29ae5b89 JL |
3923 | sre. %0,%1,%2 |
3924 | mr. %0,%1 | |
9ebbca7d GK |
3925 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
3926 | # | |
3927 | # | |
3928 | #" | |
3929 | [(set_attr "type" "delayed_compare") | |
3930 | (set_attr "length" "4,4,4,8,8,8")]) | |
3931 | ||
3932 | (define_split | |
3933 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3934 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3935 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3936 | (const_int 0))) | |
3937 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3938 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3939 | (clobber (match_scratch:SI 4 ""))] | |
3940 | "TARGET_POWER && reload_completed" | |
3941 | [(parallel [(set (match_dup 0) | |
3942 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3943 | (clobber (match_dup 4))]) | |
3944 | (set (match_dup 3) | |
3945 | (compare:CC (match_dup 0) | |
3946 | (const_int 0)))] | |
3947 | "") | |
ca7f5001 RK |
3948 | |
3949 | (define_insn "" | |
9ebbca7d GK |
3950 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3951 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3952 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 3953 | (const_int 0))) |
9ebbca7d | 3954 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 3955 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3956 | "! TARGET_POWER && TARGET_32BIT" |
29ae5b89 JL |
3957 | "@ |
3958 | mr. %0,%1 | |
9ebbca7d GK |
3959 | {sr|srw}%I2. %0,%1,%h2 |
3960 | # | |
3961 | #" | |
3962 | [(set_attr "type" "delayed_compare") | |
3963 | (set_attr "length" "4,4,8,8")]) | |
3964 | ||
3965 | (define_split | |
3966 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3967 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3968 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3969 | (const_int 0))) | |
3970 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3971 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3972 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3973 | [(set (match_dup 0) |
3974 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3975 | (set (match_dup 3) | |
3976 | (compare:CC (match_dup 0) | |
3977 | (const_int 0)))] | |
3978 | "") | |
1fd4e8c1 RK |
3979 | |
3980 | (define_insn "" | |
cd2b37d9 RK |
3981 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3982 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3983 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3984 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3985 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 3986 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
3987 | |
3988 | (define_insn "" | |
9ebbca7d | 3989 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3990 | (compare:CC |
9ebbca7d GK |
3991 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3992 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3993 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3994 | (const_int 0))) |
9ebbca7d | 3995 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3996 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3997 | "@ |
3998 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
3999 | #" | |
4000 | [(set_attr "type" "delayed_compare") | |
4001 | (set_attr "length" "4,8")]) | |
4002 | ||
4003 | (define_split | |
4004 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4005 | (compare:CC | |
4006 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4007 | (match_operand:SI 2 "const_int_operand" "")) | |
4008 | (match_operand:SI 3 "mask_operand" "")) | |
4009 | (const_int 0))) | |
4010 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 4011 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4012 | [(set (match_dup 4) |
4013 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4014 | (match_dup 3))) | |
4015 | (set (match_dup 0) | |
4016 | (compare:CC (match_dup 4) | |
4017 | (const_int 0)))] | |
4018 | "") | |
1fd4e8c1 RK |
4019 | |
4020 | (define_insn "" | |
9ebbca7d | 4021 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4022 | (compare:CC |
9ebbca7d GK |
4023 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4024 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4025 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4026 | (const_int 0))) |
9ebbca7d | 4027 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4028 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 4029 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4030 | "@ |
4031 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4032 | #" | |
4033 | [(set_attr "type" "delayed_compare") | |
4034 | (set_attr "length" "4,8")]) | |
4035 | ||
4036 | (define_split | |
4037 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4038 | (compare:CC | |
4039 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4040 | (match_operand:SI 2 "const_int_operand" "")) | |
4041 | (match_operand:SI 3 "mask_operand" "")) | |
4042 | (const_int 0))) | |
4043 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4044 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4045 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4046 | [(set (match_dup 0) |
4047 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4048 | (set (match_dup 4) | |
4049 | (compare:CC (match_dup 0) | |
4050 | (const_int 0)))] | |
4051 | "") | |
1fd4e8c1 RK |
4052 | |
4053 | (define_insn "" | |
cd2b37d9 | 4054 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4055 | (zero_extend:SI |
4056 | (subreg:QI | |
cd2b37d9 | 4057 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4058 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4059 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4060 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4061 | |
4062 | (define_insn "" | |
9ebbca7d | 4063 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4064 | (compare:CC |
4065 | (zero_extend:SI | |
4066 | (subreg:QI | |
9ebbca7d GK |
4067 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4068 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4069 | (const_int 0))) |
9ebbca7d | 4070 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4071 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4072 | "@ |
4073 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4074 | #" | |
4075 | [(set_attr "type" "delayed_compare") | |
4076 | (set_attr "length" "4,8")]) | |
4077 | ||
4078 | (define_split | |
4079 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4080 | (compare:CC | |
4081 | (zero_extend:SI | |
4082 | (subreg:QI | |
4083 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4084 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4085 | (const_int 0))) | |
4086 | (clobber (match_scratch:SI 3 ""))] | |
4087 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4088 | [(set (match_dup 3) | |
4089 | (zero_extend:SI (subreg:QI | |
4090 | (lshiftrt:SI (match_dup 1) | |
4091 | (match_dup 2)) 0))) | |
4092 | (set (match_dup 0) | |
4093 | (compare:CC (match_dup 3) | |
4094 | (const_int 0)))] | |
4095 | "") | |
1fd4e8c1 RK |
4096 | |
4097 | (define_insn "" | |
9ebbca7d | 4098 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4099 | (compare:CC |
4100 | (zero_extend:SI | |
4101 | (subreg:QI | |
9ebbca7d GK |
4102 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4103 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4104 | (const_int 0))) |
9ebbca7d | 4105 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4106 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4107 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4108 | "@ |
4109 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4110 | #" | |
4111 | [(set_attr "type" "delayed_compare") | |
4112 | (set_attr "length" "4,8")]) | |
4113 | ||
4114 | (define_split | |
4115 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4116 | (compare:CC | |
4117 | (zero_extend:SI | |
4118 | (subreg:QI | |
4119 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4120 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4121 | (const_int 0))) | |
4122 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4123 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4124 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4125 | [(set (match_dup 0) | |
4126 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4127 | (set (match_dup 3) | |
4128 | (compare:CC (match_dup 0) | |
4129 | (const_int 0)))] | |
4130 | "") | |
1fd4e8c1 RK |
4131 | |
4132 | (define_insn "" | |
cd2b37d9 | 4133 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4134 | (zero_extend:SI |
4135 | (subreg:HI | |
cd2b37d9 | 4136 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4137 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4138 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4139 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4140 | |
4141 | (define_insn "" | |
9ebbca7d | 4142 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4143 | (compare:CC |
4144 | (zero_extend:SI | |
4145 | (subreg:HI | |
9ebbca7d GK |
4146 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4147 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4148 | (const_int 0))) |
9ebbca7d | 4149 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4150 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4151 | "@ |
4152 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4153 | #" | |
4154 | [(set_attr "type" "delayed_compare") | |
4155 | (set_attr "length" "4,8")]) | |
4156 | ||
4157 | (define_split | |
4158 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4159 | (compare:CC | |
4160 | (zero_extend:SI | |
4161 | (subreg:HI | |
4162 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4163 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4164 | (const_int 0))) | |
4165 | (clobber (match_scratch:SI 3 ""))] | |
4166 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4167 | [(set (match_dup 3) | |
4168 | (zero_extend:SI (subreg:HI | |
4169 | (lshiftrt:SI (match_dup 1) | |
4170 | (match_dup 2)) 0))) | |
4171 | (set (match_dup 0) | |
4172 | (compare:CC (match_dup 3) | |
4173 | (const_int 0)))] | |
4174 | "") | |
1fd4e8c1 RK |
4175 | |
4176 | (define_insn "" | |
9ebbca7d | 4177 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4178 | (compare:CC |
4179 | (zero_extend:SI | |
4180 | (subreg:HI | |
9ebbca7d GK |
4181 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4182 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4183 | (const_int 0))) |
9ebbca7d | 4184 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4185 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4186 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4187 | "@ |
4188 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4189 | #" | |
4190 | [(set_attr "type" "delayed_compare") | |
4191 | (set_attr "length" "4,8")]) | |
4192 | ||
4193 | (define_split | |
4194 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4195 | (compare:CC | |
4196 | (zero_extend:SI | |
4197 | (subreg:HI | |
4198 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4199 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4200 | (const_int 0))) | |
4201 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4202 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4203 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4204 | [(set (match_dup 0) | |
4205 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4206 | (set (match_dup 3) | |
4207 | (compare:CC (match_dup 0) | |
4208 | (const_int 0)))] | |
4209 | "") | |
1fd4e8c1 RK |
4210 | |
4211 | (define_insn "" | |
cd2b37d9 | 4212 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4213 | (const_int 1) |
cd2b37d9 RK |
4214 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4215 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4216 | (const_int 31)))] |
ca7f5001 | 4217 | "TARGET_POWER" |
1fd4e8c1 RK |
4218 | "rrib %0,%1,%2") |
4219 | ||
4220 | (define_insn "" | |
cd2b37d9 | 4221 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4222 | (const_int 1) |
cd2b37d9 RK |
4223 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4224 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4225 | (const_int 31)))] |
ca7f5001 | 4226 | "TARGET_POWER" |
1fd4e8c1 RK |
4227 | "rrib %0,%1,%2") |
4228 | ||
4229 | (define_insn "" | |
cd2b37d9 | 4230 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4231 | (const_int 1) |
cd2b37d9 RK |
4232 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4233 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4234 | (const_int 1) |
4235 | (const_int 0)))] | |
ca7f5001 | 4236 | "TARGET_POWER" |
1fd4e8c1 RK |
4237 | "rrib %0,%1,%2") |
4238 | ||
ca7f5001 RK |
4239 | (define_expand "ashrsi3" |
4240 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4241 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4242 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4243 | "" | |
4244 | " | |
4245 | { | |
4246 | if (TARGET_POWER) | |
4247 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4248 | else | |
25c341fa | 4249 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4250 | DONE; |
4251 | }") | |
4252 | ||
4253 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4254 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4255 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4256 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4257 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4258 | "TARGET_POWER" |
1fd4e8c1 RK |
4259 | "@ |
4260 | srea %0,%1,%2 | |
ca7f5001 RK |
4261 | {srai|srawi} %0,%1,%h2") |
4262 | ||
25c341fa | 4263 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4264 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4265 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4266 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4267 | "! TARGET_POWER" |
d904e9ed | 4268 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4269 | |
4270 | (define_insn "" | |
9ebbca7d GK |
4271 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4272 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4273 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4274 | (const_int 0))) |
9ebbca7d GK |
4275 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4276 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4277 | "TARGET_POWER" |
1fd4e8c1 RK |
4278 | "@ |
4279 | srea. %3,%1,%2 | |
9ebbca7d GK |
4280 | {srai.|srawi.} %3,%1,%h2 |
4281 | # | |
4282 | #" | |
4283 | [(set_attr "type" "delayed_compare") | |
4284 | (set_attr "length" "4,4,8,8")]) | |
4285 | ||
4286 | (define_split | |
4287 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4288 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4289 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4290 | (const_int 0))) | |
4291 | (clobber (match_scratch:SI 3 "")) | |
4292 | (clobber (match_scratch:SI 4 ""))] | |
4293 | "TARGET_POWER && reload_completed" | |
4294 | [(parallel [(set (match_dup 3) | |
4295 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4296 | (clobber (match_dup 4))]) | |
4297 | (set (match_dup 0) | |
4298 | (compare:CC (match_dup 3) | |
4299 | (const_int 0)))] | |
4300 | "") | |
ca7f5001 RK |
4301 | |
4302 | (define_insn "" | |
9ebbca7d GK |
4303 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4304 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4305 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4306 | (const_int 0))) |
9ebbca7d | 4307 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4308 | "! TARGET_POWER" |
9ebbca7d GK |
4309 | "@ |
4310 | {sra|sraw}%I2. %3,%1,%h2 | |
4311 | #" | |
4312 | [(set_attr "type" "delayed_compare") | |
4313 | (set_attr "length" "4,8")]) | |
4314 | ||
4315 | (define_split | |
4316 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4317 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4318 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4319 | (const_int 0))) | |
4320 | (clobber (match_scratch:SI 3 ""))] | |
4321 | "! TARGET_POWER && reload_completed" | |
4322 | [(set (match_dup 3) | |
4323 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4324 | (set (match_dup 0) | |
4325 | (compare:CC (match_dup 3) | |
4326 | (const_int 0)))] | |
4327 | "") | |
1fd4e8c1 RK |
4328 | |
4329 | (define_insn "" | |
9ebbca7d GK |
4330 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4331 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4332 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4333 | (const_int 0))) |
9ebbca7d | 4334 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4335 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4336 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4337 | "TARGET_POWER" |
1fd4e8c1 RK |
4338 | "@ |
4339 | srea. %0,%1,%2 | |
9ebbca7d GK |
4340 | {srai.|srawi.} %0,%1,%h2 |
4341 | # | |
4342 | #" | |
4343 | [(set_attr "type" "delayed_compare") | |
4344 | (set_attr "length" "4,4,8,8")]) | |
4345 | ||
4346 | (define_split | |
4347 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4348 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4349 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4350 | (const_int 0))) | |
4351 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4352 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4353 | (clobber (match_scratch:SI 4 ""))] | |
4354 | "TARGET_POWER && reload_completed" | |
4355 | [(parallel [(set (match_dup 0) | |
4356 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4357 | (clobber (match_dup 4))]) | |
4358 | (set (match_dup 3) | |
4359 | (compare:CC (match_dup 0) | |
4360 | (const_int 0)))] | |
4361 | "") | |
1fd4e8c1 | 4362 | |
ca7f5001 | 4363 | (define_insn "" |
9ebbca7d GK |
4364 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4365 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4366 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4367 | (const_int 0))) |
9ebbca7d | 4368 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4369 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4370 | "! TARGET_POWER" |
9ebbca7d GK |
4371 | "@ |
4372 | {sra|sraw}%I2. %0,%1,%h2 | |
4373 | #" | |
4374 | [(set_attr "type" "delayed_compare") | |
4375 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4376 | \f |
9ebbca7d GK |
4377 | (define_split |
4378 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4379 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4380 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4381 | (const_int 0))) | |
4382 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4383 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4384 | "! TARGET_POWER && reload_completed" | |
4385 | [(set (match_dup 0) | |
4386 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4387 | (set (match_dup 3) | |
4388 | (compare:CC (match_dup 0) | |
4389 | (const_int 0)))] | |
4390 | "") | |
4391 | ||
1fd4e8c1 RK |
4392 | ;; Floating-point insns, excluding normal data motion. |
4393 | ;; | |
ca7f5001 RK |
4394 | ;; PowerPC has a full set of single-precision floating point instructions. |
4395 | ;; | |
4396 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4397 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4398 | ;; The only conversions we will do will be when storing to memory. In that | |
4399 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4400 | ;; |
4401 | ;; Note that when we store into a single-precision memory location, we need to | |
4402 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4403 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4404 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4405 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4406 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4407 | ||
99176a91 AH |
4408 | (define_expand "extendsfdf2" |
4409 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4410 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4411 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4412 | "") | |
4413 | ||
4414 | (define_insn_and_split "*extendsfdf2_fpr" | |
11ac38b2 DE |
4415 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") |
4416 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))] | |
a3170dc6 | 4417 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
11ac38b2 DE |
4418 | "@ |
4419 | # | |
4420 | fmr %0,%1" | |
4421 | "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" | |
4422 | [(const_int 0)] | |
5c30aff8 | 4423 | { |
11ac38b2 DE |
4424 | emit_note (NOTE_INSN_DELETED); |
4425 | DONE; | |
4426 | } | |
e8112008 | 4427 | [(set_attr "type" "fp")]) |
1fd4e8c1 | 4428 | |
7a2f7870 AH |
4429 | (define_expand "truncdfsf2" |
4430 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4431 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4432 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4433 | "") | |
4434 | ||
99176a91 | 4435 | (define_insn "*truncdfsf2_fpr" |
cd2b37d9 RK |
4436 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4437 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4438 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 4439 | "frsp %0,%1" |
1fd4e8c1 RK |
4440 | [(set_attr "type" "fp")]) |
4441 | ||
455350f4 RK |
4442 | (define_insn "aux_truncdfsf2" |
4443 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
615158e2 | 4444 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] |
a3170dc6 | 4445 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
4446 | "frsp %0,%1" |
4447 | [(set_attr "type" "fp")]) | |
4448 | ||
a3170dc6 AH |
4449 | (define_expand "negsf2" |
4450 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4451 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4452 | "TARGET_HARD_FLOAT" | |
4453 | "") | |
4454 | ||
4455 | (define_insn "*negsf2" | |
cd2b37d9 RK |
4456 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4457 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4458 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4459 | "fneg %0,%1" |
4460 | [(set_attr "type" "fp")]) | |
4461 | ||
a3170dc6 AH |
4462 | (define_expand "abssf2" |
4463 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4464 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4465 | "TARGET_HARD_FLOAT" | |
4466 | "") | |
4467 | ||
4468 | (define_insn "*abssf2" | |
cd2b37d9 RK |
4469 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4470 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4471 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4472 | "fabs %0,%1" |
4473 | [(set_attr "type" "fp")]) | |
4474 | ||
4475 | (define_insn "" | |
cd2b37d9 RK |
4476 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4477 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4478 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4479 | "fnabs %0,%1" |
4480 | [(set_attr "type" "fp")]) | |
4481 | ||
ca7f5001 RK |
4482 | (define_expand "addsf3" |
4483 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4484 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4485 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4486 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4487 | "") |
4488 | ||
4489 | (define_insn "" | |
cd2b37d9 RK |
4490 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4491 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4492 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4493 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4494 | "fadds %0,%1,%2" |
ca7f5001 RK |
4495 | [(set_attr "type" "fp")]) |
4496 | ||
4497 | (define_insn "" | |
4498 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4499 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4500 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4501 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4502 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4503 | [(set_attr "type" "fp")]) |
4504 | ||
4505 | (define_expand "subsf3" | |
4506 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4507 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4508 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4509 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4510 | "") |
4511 | ||
4512 | (define_insn "" | |
4513 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4514 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4515 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4516 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4517 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4518 | [(set_attr "type" "fp")]) |
4519 | ||
ca7f5001 | 4520 | (define_insn "" |
cd2b37d9 RK |
4521 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4522 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4523 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4524 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4525 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4526 | [(set_attr "type" "fp")]) |
4527 | ||
4528 | (define_expand "mulsf3" | |
4529 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4530 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4531 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4532 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4533 | "") |
4534 | ||
4535 | (define_insn "" | |
4536 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4537 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4538 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4539 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4540 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4541 | [(set_attr "type" "fp")]) |
4542 | ||
ca7f5001 | 4543 | (define_insn "" |
cd2b37d9 RK |
4544 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4545 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4546 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4547 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4548 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4549 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4550 | |
ca7f5001 RK |
4551 | (define_expand "divsf3" |
4552 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4553 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4554 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4555 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4556 | "") |
4557 | ||
4558 | (define_insn "" | |
cd2b37d9 RK |
4559 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4560 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4561 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4562 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4563 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4564 | [(set_attr "type" "sdiv")]) |
4565 | ||
4566 | (define_insn "" | |
4567 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4568 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4569 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4570 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4571 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4572 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4573 | |
4574 | (define_insn "" | |
cd2b37d9 RK |
4575 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4576 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4577 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4578 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4579 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4580 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4581 | [(set_attr "type" "fp")]) |
4582 | ||
4583 | (define_insn "" | |
4584 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4585 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4586 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4587 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4588 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4589 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4590 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4591 | |
4592 | (define_insn "" | |
cd2b37d9 RK |
4593 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4594 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4595 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4596 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4597 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4598 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4599 | [(set_attr "type" "fp")]) |
4600 | ||
4601 | (define_insn "" | |
4602 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4603 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4604 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4605 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4606 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4607 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4608 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4609 | |
4610 | (define_insn "" | |
cd2b37d9 RK |
4611 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4612 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4613 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4614 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4615 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4616 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4617 | "fnmadds %0,%1,%2,%3" | |
4618 | [(set_attr "type" "fp")]) | |
4619 | ||
4620 | (define_insn "" | |
4621 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4622 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4623 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4624 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4625 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4626 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4627 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4628 | [(set_attr "type" "fp")]) |
4629 | ||
4630 | (define_insn "" | |
4631 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4632 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4633 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4634 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4635 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4636 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4637 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4638 | |
16823694 GK |
4639 | (define_insn "" |
4640 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4641 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4642 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4643 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4644 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4645 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4646 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4647 | [(set_attr "type" "dmul")]) | |
4648 | ||
1fd4e8c1 | 4649 | (define_insn "" |
cd2b37d9 RK |
4650 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4651 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4652 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4653 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4654 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4655 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4656 | "fnmsubs %0,%1,%2,%3" | |
4657 | [(set_attr "type" "fp")]) | |
4658 | ||
4659 | (define_insn "" | |
4660 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4661 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4662 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4663 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4664 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4665 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4666 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4667 | [(set_attr "type" "fp")]) |
4668 | ||
4669 | (define_insn "" | |
4670 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4671 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4672 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4673 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4674 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4675 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4676 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4677 | |
16823694 GK |
4678 | (define_insn "" |
4679 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4680 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4681 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4682 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4683 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4684 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4685 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4686 | [(set_attr "type" "fp")]) | |
4687 | ||
ca7f5001 RK |
4688 | (define_expand "sqrtsf2" |
4689 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4690 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 4691 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4692 | "") |
4693 | ||
4694 | (define_insn "" | |
4695 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4696 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4697 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4698 | "fsqrts %0,%1" |
4699 | [(set_attr "type" "ssqrt")]) | |
4700 | ||
4701 | (define_insn "" | |
4702 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4703 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4704 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4705 | "fsqrt %0,%1" |
4706 | [(set_attr "type" "dsqrt")]) | |
4707 | ||
94d7001a RK |
4708 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4709 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4710 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4711 | ;; combine. |
4712 | (define_expand "maxsf3" | |
8e871c05 | 4713 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4714 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4715 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4716 | (match_dup 1) |
4717 | (match_dup 2)))] | |
89e73849 | 4718 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4719 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 4720 | |
8e871c05 | 4721 | (define_expand "minsf3" |
50a0b056 GK |
4722 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4723 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4724 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4725 | (match_dup 2) | |
4726 | (match_dup 1)))] | |
89e73849 | 4727 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4728 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4729 | |
8e871c05 RK |
4730 | (define_split |
4731 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4732 | (match_operator:SF 3 "min_max_operator" |
4733 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4734 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 4735 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
4736 | [(const_int 0)] |
4737 | " | |
6ae08853 | 4738 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
4739 | operands[1], operands[2]); |
4740 | DONE; | |
4741 | }") | |
2f607b94 | 4742 | |
a3170dc6 AH |
4743 | (define_expand "movsicc" |
4744 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4745 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
4746 | (match_operand:SI 2 "gpc_reg_operand" "") | |
4747 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
4748 | "TARGET_ISEL" | |
4749 | " | |
4750 | { | |
4751 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
4752 | DONE; | |
4753 | else | |
4754 | FAIL; | |
4755 | }") | |
4756 | ||
4757 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
4758 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
4759 | ;; because we may switch the operands and rB may end up being rA. | |
4760 | ;; | |
4761 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
4762 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
4763 | ;; change the mode underneath our feet and then gets confused trying | |
4764 | ;; to reload the value. | |
4765 | (define_insn "isel_signed" | |
4766 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4767 | (if_then_else:SI | |
4768 | (match_operator 1 "comparison_operator" | |
4769 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
4770 | (const_int 0)]) | |
4771 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4772 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4773 | "TARGET_ISEL" | |
4774 | "* | |
4775 | { return output_isel (operands); }" | |
4776 | [(set_attr "length" "4")]) | |
4777 | ||
4778 | (define_insn "isel_unsigned" | |
4779 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4780 | (if_then_else:SI | |
4781 | (match_operator 1 "comparison_operator" | |
4782 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
4783 | (const_int 0)]) | |
4784 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4785 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4786 | "TARGET_ISEL" | |
4787 | "* | |
4788 | { return output_isel (operands); }" | |
4789 | [(set_attr "length" "4")]) | |
4790 | ||
94d7001a | 4791 | (define_expand "movsfcc" |
0ad91047 | 4792 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4793 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4794 | (match_operand:SF 2 "gpc_reg_operand" "") |
4795 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4796 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4797 | " |
4798 | { | |
50a0b056 GK |
4799 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4800 | DONE; | |
94d7001a | 4801 | else |
50a0b056 | 4802 | FAIL; |
94d7001a | 4803 | }") |
d56d506a | 4804 | |
50a0b056 | 4805 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4806 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4807 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4808 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4809 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4810 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4811 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4812 | "fsel %0,%1,%2,%3" |
4813 | [(set_attr "type" "fp")]) | |
2f607b94 | 4814 | |
50a0b056 | 4815 | (define_insn "*fseldfsf4" |
94d7001a RK |
4816 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4817 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4818 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4819 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4820 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4821 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4822 | "fsel %0,%1,%2,%3" |
4823 | [(set_attr "type" "fp")]) | |
d56d506a | 4824 | |
7a2f7870 AH |
4825 | (define_expand "negdf2" |
4826 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4827 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4828 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4829 | "") | |
4830 | ||
99176a91 | 4831 | (define_insn "*negdf2_fpr" |
cd2b37d9 RK |
4832 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4833 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4834 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4835 | "fneg %0,%1" |
4836 | [(set_attr "type" "fp")]) | |
4837 | ||
7a2f7870 AH |
4838 | (define_expand "absdf2" |
4839 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4840 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4841 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4842 | "") | |
4843 | ||
99176a91 | 4844 | (define_insn "*absdf2_fpr" |
cd2b37d9 RK |
4845 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4846 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4847 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4848 | "fabs %0,%1" |
4849 | [(set_attr "type" "fp")]) | |
4850 | ||
99176a91 | 4851 | (define_insn "*nabsdf2_fpr" |
cd2b37d9 RK |
4852 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4853 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4854 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4855 | "fnabs %0,%1" |
4856 | [(set_attr "type" "fp")]) | |
4857 | ||
7a2f7870 AH |
4858 | (define_expand "adddf3" |
4859 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4860 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4861 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4862 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4863 | "") | |
4864 | ||
99176a91 | 4865 | (define_insn "*adddf3_fpr" |
cd2b37d9 RK |
4866 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4867 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4868 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4869 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4870 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4871 | [(set_attr "type" "fp")]) |
4872 | ||
7a2f7870 AH |
4873 | (define_expand "subdf3" |
4874 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4875 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4876 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4877 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4878 | "") | |
4879 | ||
99176a91 | 4880 | (define_insn "*subdf3_fpr" |
cd2b37d9 RK |
4881 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4882 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4883 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4884 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4885 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4886 | [(set_attr "type" "fp")]) |
4887 | ||
7a2f7870 AH |
4888 | (define_expand "muldf3" |
4889 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4890 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4891 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4892 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4893 | "") | |
4894 | ||
99176a91 | 4895 | (define_insn "*muldf3_fpr" |
cd2b37d9 RK |
4896 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4897 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4898 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4899 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4900 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4901 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4902 | |
7a2f7870 AH |
4903 | (define_expand "divdf3" |
4904 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4905 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4906 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4907 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4908 | "") | |
4909 | ||
99176a91 | 4910 | (define_insn "*divdf3_fpr" |
cd2b37d9 RK |
4911 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4912 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4913 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4914 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4915 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4916 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4917 | |
4918 | (define_insn "" | |
cd2b37d9 RK |
4919 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4920 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4921 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4922 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4923 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4924 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4925 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4926 | |
4927 | (define_insn "" | |
cd2b37d9 RK |
4928 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4929 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4930 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4931 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4932 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4933 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4934 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4935 | |
4936 | (define_insn "" | |
cd2b37d9 RK |
4937 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4938 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4939 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4940 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4941 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4942 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4943 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4944 | [(set_attr "type" "dmul")]) | |
4945 | ||
4946 | (define_insn "" | |
4947 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4948 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
4949 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4950 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4951 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4952 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 4953 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 4954 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4955 | |
4956 | (define_insn "" | |
cd2b37d9 RK |
4957 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4958 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4959 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4960 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4961 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4962 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4963 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4964 | [(set_attr "type" "dmul")]) | |
4965 | ||
4966 | (define_insn "" | |
4967 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4968 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
4969 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4970 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
6ae08853 | 4971 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
16823694 | 4972 | && ! HONOR_SIGNED_ZEROS (DFmode)" |
ca7f5001 | 4973 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 4974 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
4975 | |
4976 | (define_insn "sqrtdf2" | |
4977 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4978 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4979 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4980 | "fsqrt %0,%1" |
4981 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 4982 | |
50a0b056 | 4983 | ;; The conditional move instructions allow us to perform max and min |
6ae08853 | 4984 | ;; operations even when |
b77dfefc | 4985 | |
8e871c05 | 4986 | (define_expand "maxdf3" |
8e871c05 | 4987 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4988 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
4989 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4990 | (match_dup 1) |
4991 | (match_dup 2)))] | |
89e73849 | 4992 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4993 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 4994 | |
8e871c05 | 4995 | (define_expand "mindf3" |
50a0b056 GK |
4996 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4997 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
4998 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
4999 | (match_dup 2) | |
5000 | (match_dup 1)))] | |
89e73849 | 5001 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5002 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5003 | |
8e871c05 RK |
5004 | (define_split |
5005 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5006 | (match_operator:DF 3 "min_max_operator" |
5007 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5008 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 5009 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
5010 | [(const_int 0)] |
5011 | " | |
6ae08853 | 5012 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
5013 | operands[1], operands[2]); |
5014 | DONE; | |
5015 | }") | |
b77dfefc | 5016 | |
94d7001a | 5017 | (define_expand "movdfcc" |
0ad91047 | 5018 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5019 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5020 | (match_operand:DF 2 "gpc_reg_operand" "") |
5021 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 5022 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
5023 | " |
5024 | { | |
50a0b056 GK |
5025 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5026 | DONE; | |
94d7001a | 5027 | else |
50a0b056 | 5028 | FAIL; |
94d7001a | 5029 | }") |
d56d506a | 5030 | |
50a0b056 | 5031 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5032 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5033 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5034 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5035 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5036 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5037 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
5038 | "fsel %0,%1,%2,%3" |
5039 | [(set_attr "type" "fp")]) | |
d56d506a | 5040 | |
50a0b056 | 5041 | (define_insn "*fselsfdf4" |
94d7001a RK |
5042 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5043 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5044 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5045 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5046 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5047 | "TARGET_PPC_GFXOPT" | |
5048 | "fsel %0,%1,%2,%3" | |
5049 | [(set_attr "type" "fp")]) | |
1fd4e8c1 | 5050 | \f |
d095928f AH |
5051 | ;; Conversions to and from floating-point. |
5052 | ||
5053 | (define_expand "fixuns_truncsfsi2" | |
5054 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5055 | (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5056 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5057 | "") | |
5058 | ||
5059 | (define_expand "fix_truncsfsi2" | |
5060 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5061 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5062 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5063 | "") | |
5064 | ||
9ebbca7d GK |
5065 | ; For each of these conversions, there is a define_expand, a define_insn |
5066 | ; with a '#' template, and a define_split (with C code). The idea is | |
5067 | ; to allow constant folding with the template of the define_insn, | |
5068 | ; then to have the insns split later (between sched1 and final). | |
5069 | ||
1fd4e8c1 | 5070 | (define_expand "floatsidf2" |
802a0058 MM |
5071 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5072 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5073 | (use (match_dup 2)) | |
5074 | (use (match_dup 3)) | |
208c89ce | 5075 | (clobber (match_dup 4)) |
a7df97e6 | 5076 | (clobber (match_dup 5)) |
9ebbca7d | 5077 | (clobber (match_dup 6))])] |
a3170dc6 | 5078 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5079 | " |
5080 | { | |
99176a91 AH |
5081 | if (TARGET_E500_DOUBLE) |
5082 | { | |
5083 | emit_insn (gen_spe_floatsidf2 (operands[0], operands[1])); | |
5084 | DONE; | |
5085 | } | |
05d49501 AM |
5086 | if (TARGET_POWERPC64) |
5087 | { | |
5088 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5089 | rtx t1 = gen_reg_rtx (DImode); | |
5090 | rtx t2 = gen_reg_rtx (DImode); | |
5091 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
5092 | DONE; | |
5093 | } | |
5094 | ||
802a0058 | 5095 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5096 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5097 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5098 | operands[5] = gen_reg_rtx (DFmode); | |
5099 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5100 | }") |
5101 | ||
802a0058 MM |
5102 | (define_insn "*floatsidf2_internal" |
5103 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5104 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5105 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5106 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5107 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5108 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5109 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5110 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5111 | "#" |
a7df97e6 | 5112 | [(set_attr "length" "24")]) |
802a0058 MM |
5113 | |
5114 | (define_split | |
dbe3df29 | 5115 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5116 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5117 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5118 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5119 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5120 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5121 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
a3170dc6 | 5122 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5123 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5124 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5125 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5126 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5127 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5128 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5129 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5130 | " |
5131 | { | |
9ebbca7d GK |
5132 | rtx lowword, highword; |
5133 | if (GET_CODE (operands[4]) != MEM) | |
5134 | abort(); | |
5135 | highword = XEXP (operands[4], 0); | |
5136 | lowword = plus_constant (highword, 4); | |
5137 | if (! WORDS_BIG_ENDIAN) | |
5138 | { | |
5139 | rtx tmp; | |
5140 | tmp = highword; highword = lowword; lowword = tmp; | |
5141 | } | |
5142 | ||
6ae08853 | 5143 | emit_insn (gen_xorsi3 (operands[6], operands[1], |
9ebbca7d GK |
5144 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); |
5145 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5146 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5147 | emit_move_insn (operands[5], operands[4]); | |
5148 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5149 | DONE; | |
208c89ce | 5150 | }") |
802a0058 | 5151 | |
a3170dc6 AH |
5152 | (define_expand "floatunssisf2" |
5153 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5154 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5155 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5156 | "") | |
5157 | ||
802a0058 MM |
5158 | (define_expand "floatunssidf2" |
5159 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5160 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5161 | (use (match_dup 2)) | |
5162 | (use (match_dup 3)) | |
a7df97e6 | 5163 | (clobber (match_dup 4)) |
9ebbca7d | 5164 | (clobber (match_dup 5))])] |
99176a91 | 5165 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
1fd4e8c1 RK |
5166 | " |
5167 | { | |
99176a91 AH |
5168 | if (TARGET_E500_DOUBLE) |
5169 | { | |
5170 | emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1])); | |
5171 | DONE; | |
5172 | } | |
05d49501 AM |
5173 | if (TARGET_POWERPC64) |
5174 | { | |
5175 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5176 | rtx t1 = gen_reg_rtx (DImode); | |
5177 | rtx t2 = gen_reg_rtx (DImode); | |
5178 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5179 | t1, t2)); | |
5180 | DONE; | |
5181 | } | |
5182 | ||
802a0058 | 5183 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5184 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5185 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5186 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5187 | }") |
5188 | ||
802a0058 MM |
5189 | (define_insn "*floatunssidf2_internal" |
5190 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5191 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5192 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5193 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5194 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5195 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5196 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5197 | "#" |
a7df97e6 | 5198 | [(set_attr "length" "20")]) |
802a0058 MM |
5199 | |
5200 | (define_split | |
5201 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5202 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5203 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5204 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5205 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5206 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
a3170dc6 | 5207 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5208 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5209 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5210 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5211 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5212 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5213 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5214 | " | |
802a0058 | 5215 | { |
9ebbca7d GK |
5216 | rtx lowword, highword; |
5217 | if (GET_CODE (operands[4]) != MEM) | |
5218 | abort(); | |
5219 | highword = XEXP (operands[4], 0); | |
5220 | lowword = plus_constant (highword, 4); | |
5221 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5222 | { |
9ebbca7d GK |
5223 | rtx tmp; |
5224 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5225 | } |
802a0058 | 5226 | |
9ebbca7d GK |
5227 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5228 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5229 | emit_move_insn (operands[5], operands[4]); | |
5230 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5231 | DONE; | |
5232 | }") | |
1fd4e8c1 | 5233 | |
1fd4e8c1 | 5234 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5235 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5236 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5237 | (clobber (match_dup 2)) | |
9ebbca7d | 5238 | (clobber (match_dup 3))])] |
99176a91 AH |
5239 | "(TARGET_POWER2 || TARGET_POWERPC) |
5240 | && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
1fd4e8c1 RK |
5241 | " |
5242 | { | |
99176a91 AH |
5243 | if (TARGET_E500_DOUBLE) |
5244 | { | |
5245 | emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1])); | |
5246 | DONE; | |
5247 | } | |
802a0058 | 5248 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5249 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5250 | }") |
5251 | ||
802a0058 MM |
5252 | (define_insn "*fix_truncdfsi2_internal" |
5253 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5254 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5255 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5256 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5257 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5258 | "#" |
9ebbca7d | 5259 | [(set_attr "length" "16")]) |
802a0058 MM |
5260 | |
5261 | (define_split | |
5262 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5263 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5264 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5265 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
a3170dc6 | 5266 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d | 5267 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5268 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5269 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5270 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5271 | " | |
802a0058 | 5272 | { |
9ebbca7d GK |
5273 | rtx lowword; |
5274 | if (GET_CODE (operands[3]) != MEM) | |
5275 | abort(); | |
5276 | lowword = XEXP (operands[3], 0); | |
5277 | if (WORDS_BIG_ENDIAN) | |
5278 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5279 | |
9ebbca7d GK |
5280 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5281 | emit_move_insn (operands[3], operands[2]); | |
5282 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5283 | DONE; | |
5284 | }") | |
802a0058 | 5285 | |
615158e2 | 5286 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) |
9ebbca7d GK |
5287 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) |
5288 | ; because the first makes it clear that operand 0 is not live | |
5289 | ; before the instruction. | |
5290 | (define_insn "fctiwz" | |
61c07d3c | 5291 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
615158e2 JJ |
5292 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] |
5293 | UNSPEC_FCTIWZ))] | |
a3170dc6 | 5294 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5295 | "{fcirz|fctiwz} %0,%1" |
5296 | [(set_attr "type" "fp")]) | |
5297 | ||
a3170dc6 AH |
5298 | (define_expand "floatsisf2" |
5299 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5300 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5301 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5302 | "") | |
5303 | ||
a473029f RK |
5304 | (define_insn "floatdidf2" |
5305 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5306 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5307 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5308 | "fcfid %0,%1" |
5309 | [(set_attr "type" "fp")]) | |
5310 | ||
05d49501 AM |
5311 | (define_insn_and_split "floatsidf_ppc64" |
5312 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5313 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5314 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5315 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5316 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5317 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5318 | "#" |
ecb62ae7 | 5319 | "&& 1" |
05d49501 AM |
5320 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) |
5321 | (set (match_dup 2) (match_dup 3)) | |
5322 | (set (match_dup 4) (match_dup 2)) | |
5323 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5324 | "") | |
5325 | ||
5326 | (define_insn_and_split "floatunssidf_ppc64" | |
5327 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5328 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5329 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5330 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5331 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5332 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5333 | "#" |
ecb62ae7 | 5334 | "&& 1" |
05d49501 AM |
5335 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) |
5336 | (set (match_dup 2) (match_dup 3)) | |
5337 | (set (match_dup 4) (match_dup 2)) | |
5338 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5339 | "") | |
5340 | ||
a473029f | 5341 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5342 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5343 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5344 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5345 | "fctidz %0,%1" |
5346 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5347 | |
678b7733 AM |
5348 | (define_expand "floatdisf2" |
5349 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5350 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
994cf173 | 5351 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5352 | " |
5353 | { | |
994cf173 | 5354 | rtx val = operands[1]; |
678b7733 AM |
5355 | if (!flag_unsafe_math_optimizations) |
5356 | { | |
5357 | rtx label = gen_label_rtx (); | |
994cf173 AM |
5358 | val = gen_reg_rtx (DImode); |
5359 | emit_insn (gen_floatdisf2_internal2 (val, operands[1], label)); | |
678b7733 AM |
5360 | emit_label (label); |
5361 | } | |
994cf173 | 5362 | emit_insn (gen_floatdisf2_internal1 (operands[0], val)); |
678b7733 AM |
5363 | DONE; |
5364 | }") | |
5365 | ||
5366 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
5367 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
5368 | ;; from double rounding. | |
5369 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 5370 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 5371 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 5372 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 5373 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
5374 | "#" |
5375 | "&& reload_completed" | |
5376 | [(set (match_dup 2) | |
5377 | (float:DF (match_dup 1))) | |
5378 | (set (match_dup 0) | |
5379 | (float_truncate:SF (match_dup 2)))] | |
5380 | "") | |
678b7733 AM |
5381 | |
5382 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 5383 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
5384 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
5385 | ;; rounding position. | |
5386 | (define_expand "floatdisf2_internal2" | |
994cf173 AM |
5387 | [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") |
5388 | (const_int 53))) | |
5389 | (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1) | |
5390 | (const_int 2047))) | |
5391 | (clobber (scratch:CC))]) | |
5392 | (set (match_dup 3) (plus:DI (match_dup 3) | |
5393 | (const_int 1))) | |
5394 | (set (match_dup 0) (plus:DI (match_dup 0) | |
5395 | (const_int 2047))) | |
5396 | (set (match_dup 4) (compare:CCUNS (match_dup 3) | |
5397 | (const_int 3))) | |
5398 | (set (match_dup 0) (ior:DI (match_dup 0) | |
5399 | (match_dup 1))) | |
5400 | (parallel [(set (match_dup 0) (and:DI (match_dup 0) | |
5401 | (const_int -2048))) | |
5402 | (clobber (scratch:CC))]) | |
5403 | (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) | |
5404 | (label_ref (match_operand:DI 2 "" "")) | |
678b7733 | 5405 | (pc))) |
994cf173 AM |
5406 | (set (match_dup 0) (match_dup 1))] |
5407 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
678b7733 AM |
5408 | " |
5409 | { | |
678b7733 | 5410 | operands[3] = gen_reg_rtx (DImode); |
994cf173 | 5411 | operands[4] = gen_reg_rtx (CCUNSmode); |
678b7733 | 5412 | }") |
1fd4e8c1 RK |
5413 | \f |
5414 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5415 | ;; of instructions. The & constraints are to prevent the register |
5416 | ;; allocator from allocating registers that overlap with the inputs | |
5417 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5418 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5419 | |
266eb58a | 5420 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5421 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5422 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5423 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5424 | "! TARGET_POWERPC64" |
0f645302 MM |
5425 | "* |
5426 | { | |
5427 | if (WORDS_BIG_ENDIAN) | |
5428 | return (GET_CODE (operands[2])) != CONST_INT | |
5429 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5430 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5431 | else | |
5432 | return (GET_CODE (operands[2])) != CONST_INT | |
5433 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5434 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5435 | }" | |
943c15ed DE |
5436 | [(set_attr "type" "two") |
5437 | (set_attr "length" "8")]) | |
1fd4e8c1 | 5438 | |
266eb58a | 5439 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5440 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5441 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5442 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5443 | "! TARGET_POWERPC64" |
5502823b RK |
5444 | "* |
5445 | { | |
0f645302 MM |
5446 | if (WORDS_BIG_ENDIAN) |
5447 | return (GET_CODE (operands[1]) != CONST_INT) | |
5448 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5449 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5450 | else | |
5451 | return (GET_CODE (operands[1]) != CONST_INT) | |
5452 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5453 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5454 | }" |
943c15ed DE |
5455 | [(set_attr "type" "two") |
5456 | (set_attr "length" "8")]) | |
ca7f5001 | 5457 | |
266eb58a | 5458 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5459 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5460 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5461 | "! TARGET_POWERPC64" |
5502823b RK |
5462 | "* |
5463 | { | |
5464 | return (WORDS_BIG_ENDIAN) | |
5465 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5466 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5467 | }" | |
943c15ed DE |
5468 | [(set_attr "type" "two") |
5469 | (set_attr "length" "8")]) | |
ca7f5001 | 5470 | |
8ffd9c51 RK |
5471 | (define_expand "mulsidi3" |
5472 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5473 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5474 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5475 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5476 | " |
5477 | { | |
5478 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5479 | { | |
39403d82 DE |
5480 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5481 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5482 | emit_insn (gen_mull_call ()); |
cf27b467 | 5483 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5484 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5485 | else |
5486 | { | |
5487 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5488 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5489 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5490 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5491 | } |
8ffd9c51 RK |
5492 | DONE; |
5493 | } | |
5494 | else if (TARGET_POWER) | |
5495 | { | |
5496 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5497 | DONE; | |
5498 | } | |
5499 | }") | |
deb9225a | 5500 | |
8ffd9c51 | 5501 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5502 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5503 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5504 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5505 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5506 | "TARGET_POWER" |
b19003d8 | 5507 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5508 | [(set_attr "type" "imul") |
5509 | (set_attr "length" "8")]) | |
deb9225a | 5510 | |
f192bf8b | 5511 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5512 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5513 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5514 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5515 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5516 | "* |
5517 | { | |
5518 | return (WORDS_BIG_ENDIAN) | |
5519 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5520 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5521 | }" | |
8ffd9c51 RK |
5522 | [(set_attr "type" "imul") |
5523 | (set_attr "length" "8")]) | |
deb9225a | 5524 | |
ebedb4dd MM |
5525 | (define_split |
5526 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5527 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5528 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5529 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5530 | [(set (match_dup 3) |
5531 | (truncate:SI | |
5532 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5533 | (sign_extend:DI (match_dup 2))) | |
5534 | (const_int 32)))) | |
5535 | (set (match_dup 4) | |
5536 | (mult:SI (match_dup 1) | |
5537 | (match_dup 2)))] | |
5538 | " | |
5539 | { | |
5540 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5541 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5542 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5543 | }") | |
5544 | ||
f192bf8b DE |
5545 | (define_expand "umulsidi3" |
5546 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5547 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5548 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5549 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5550 | " | |
5551 | { | |
5552 | if (TARGET_POWER) | |
5553 | { | |
5554 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5555 | DONE; | |
5556 | } | |
5557 | }") | |
5558 | ||
5559 | (define_insn "umulsidi3_mq" | |
5560 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5561 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5562 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5563 | (clobber (match_scratch:SI 3 "=q"))] | |
5564 | "TARGET_POWERPC && TARGET_POWER" | |
5565 | "* | |
5566 | { | |
5567 | return (WORDS_BIG_ENDIAN) | |
5568 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5569 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5570 | }" | |
5571 | [(set_attr "type" "imul") | |
5572 | (set_attr "length" "8")]) | |
5573 | ||
5574 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5575 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5576 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5577 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5578 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5579 | "* |
5580 | { | |
5581 | return (WORDS_BIG_ENDIAN) | |
5582 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5583 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5584 | }" | |
5585 | [(set_attr "type" "imul") | |
5586 | (set_attr "length" "8")]) | |
5587 | ||
ebedb4dd MM |
5588 | (define_split |
5589 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5590 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5591 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5592 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5593 | [(set (match_dup 3) |
5594 | (truncate:SI | |
5595 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5596 | (zero_extend:DI (match_dup 2))) | |
5597 | (const_int 32)))) | |
5598 | (set (match_dup 4) | |
5599 | (mult:SI (match_dup 1) | |
5600 | (match_dup 2)))] | |
5601 | " | |
5602 | { | |
5603 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5604 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5605 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5606 | }") | |
5607 | ||
8ffd9c51 RK |
5608 | (define_expand "smulsi3_highpart" |
5609 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5610 | (truncate:SI | |
5611 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5612 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5613 | (sign_extend:DI | |
5614 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5615 | (const_int 32))))] | |
5616 | "" | |
5617 | " | |
5618 | { | |
5619 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5620 | { | |
39403d82 DE |
5621 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5622 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5623 | emit_insn (gen_mulh_call ()); |
39403d82 | 5624 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5625 | DONE; |
5626 | } | |
5627 | else if (TARGET_POWER) | |
5628 | { | |
5629 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5630 | DONE; | |
5631 | } | |
5632 | }") | |
deb9225a | 5633 | |
8ffd9c51 RK |
5634 | (define_insn "smulsi3_highpart_mq" |
5635 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5636 | (truncate:SI | |
fada905b MM |
5637 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5638 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5639 | (sign_extend:DI | |
5640 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5641 | (const_int 32)))) |
5642 | (clobber (match_scratch:SI 3 "=q"))] | |
5643 | "TARGET_POWER" | |
5644 | "mul %0,%1,%2" | |
5645 | [(set_attr "type" "imul")]) | |
deb9225a | 5646 | |
f192bf8b | 5647 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5648 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5649 | (truncate:SI | |
fada905b MM |
5650 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5651 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5652 | (sign_extend:DI | |
5653 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5654 | (const_int 32))))] |
f192bf8b | 5655 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5656 | "mulhw %0,%1,%2" |
5657 | [(set_attr "type" "imul")]) | |
deb9225a | 5658 | |
f192bf8b DE |
5659 | (define_expand "umulsi3_highpart" |
5660 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5661 | (truncate:SI | |
5662 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5663 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5664 | (zero_extend:DI | |
5665 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5666 | (const_int 32))))] | |
5667 | "TARGET_POWERPC" | |
5668 | " | |
5669 | { | |
5670 | if (TARGET_POWER) | |
5671 | { | |
5672 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5673 | DONE; | |
5674 | } | |
5675 | }") | |
5676 | ||
5677 | (define_insn "umulsi3_highpart_mq" | |
5678 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5679 | (truncate:SI | |
5680 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5681 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5682 | (zero_extend:DI | |
5683 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5684 | (const_int 32)))) | |
5685 | (clobber (match_scratch:SI 3 "=q"))] | |
5686 | "TARGET_POWERPC && TARGET_POWER" | |
5687 | "mulhwu %0,%1,%2" | |
5688 | [(set_attr "type" "imul")]) | |
5689 | ||
5690 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5691 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5692 | (truncate:SI | |
5693 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5694 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5695 | (zero_extend:DI | |
5696 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5697 | (const_int 32))))] | |
f192bf8b | 5698 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5699 | "mulhwu %0,%1,%2" |
5700 | [(set_attr "type" "imul")]) | |
5701 | ||
5702 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5703 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5704 | ;; why we have the strange constraints below. | |
5705 | (define_insn "ashldi3_power" | |
5706 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5707 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5708 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5709 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5710 | "TARGET_POWER" | |
5711 | "@ | |
5712 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5713 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5714 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5715 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5716 | [(set_attr "length" "8")]) | |
5717 | ||
5718 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5719 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5720 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5721 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5722 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5723 | "TARGET_POWER" | |
5724 | "@ | |
47ad8c61 | 5725 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5726 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5727 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5728 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5729 | [(set_attr "length" "8")]) | |
5730 | ||
5731 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5732 | ;; just handle shifts by constants. | |
5733 | (define_insn "ashrdi3_power" | |
7093ddee | 5734 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5735 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5736 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5737 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5738 | "TARGET_POWER" | |
5739 | "@ | |
5740 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5741 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5742 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
5743 | |
5744 | (define_insn "ashrdi3_no_power" | |
5745 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
5746 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5747 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
97727e85 | 5748 | "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN" |
4aa74a4f FS |
5749 | "@ |
5750 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5751 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
943c15ed DE |
5752 | [(set_attr "type" "two,three") |
5753 | (set_attr "length" "8,12")]) | |
683bdff7 FJ |
5754 | |
5755 | (define_insn "*ashrdisi3_noppc64" | |
5756 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 5757 | (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
683bdff7 FJ |
5758 | (const_int 32)) 4))] |
5759 | "TARGET_32BIT && !TARGET_POWERPC64" | |
5760 | "* | |
5761 | { | |
5762 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
5763 | return \"\"; | |
5764 | else | |
5765 | return \"mr %0,%1\"; | |
5766 | }" | |
6ae08853 | 5767 | [(set_attr "length" "4")]) |
683bdff7 | 5768 | |
266eb58a DE |
5769 | \f |
5770 | ;; PowerPC64 DImode operations. | |
5771 | ||
5772 | (define_expand "adddi3" | |
5773 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5774 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 5775 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
5776 | "" |
5777 | " | |
5778 | { | |
a260abc9 DE |
5779 | if (! TARGET_POWERPC64) |
5780 | { | |
5781 | if (non_short_cint_operand (operands[2], DImode)) | |
5782 | FAIL; | |
5783 | } | |
5784 | else | |
5785 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5786 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5787 | { |
677a9668 | 5788 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5789 | ? operands[0] : gen_reg_rtx (DImode)); |
5790 | ||
2bfcf297 | 5791 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5792 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5793 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
a260abc9 | 5794 | |
2bfcf297 DB |
5795 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
5796 | FAIL; | |
a260abc9 | 5797 | |
2bfcf297 DB |
5798 | /* The ordering here is important for the prolog expander. |
5799 | When space is allocated from the stack, adding 'low' first may | |
5800 | produce a temporary deallocation (which would be bad). */ | |
5801 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
5802 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
5803 | DONE; | |
5804 | } | |
266eb58a DE |
5805 | }") |
5806 | ||
5807 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5808 | ;; allowing register zero as source. | |
5809 | ||
a260abc9 | 5810 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5811 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5812 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5813 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5814 | "TARGET_POWERPC64" |
5815 | "@ | |
5816 | add %0,%1,%2 | |
5817 | addi %0,%1,%2 | |
5818 | addic %0,%1,%2 | |
802a0058 | 5819 | addis %0,%1,%v2") |
266eb58a | 5820 | |
a260abc9 | 5821 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5822 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5823 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5824 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5825 | (const_int 0))) |
9ebbca7d | 5826 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
683bdff7 | 5827 | "TARGET_64BIT" |
266eb58a DE |
5828 | "@ |
5829 | add. %3,%1,%2 | |
9ebbca7d GK |
5830 | addic. %3,%1,%2 |
5831 | # | |
5832 | #" | |
a62bfff2 | 5833 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5834 | (set_attr "length" "4,4,8,8")]) |
5835 | ||
5836 | (define_split | |
5837 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5838 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5839 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5840 | (const_int 0))) | |
5841 | (clobber (match_scratch:DI 3 ""))] | |
5842 | "TARGET_POWERPC64 && reload_completed" | |
5843 | [(set (match_dup 3) | |
5844 | (plus:DI (match_dup 1) (match_dup 2))) | |
5845 | (set (match_dup 0) | |
5846 | (compare:CC (match_dup 3) | |
5847 | (const_int 0)))] | |
5848 | "") | |
266eb58a | 5849 | |
a260abc9 | 5850 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5851 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5852 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5853 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5854 | (const_int 0))) |
9ebbca7d | 5855 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a | 5856 | (plus:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 5857 | "TARGET_64BIT" |
266eb58a DE |
5858 | "@ |
5859 | add. %0,%1,%2 | |
9ebbca7d GK |
5860 | addic. %0,%1,%2 |
5861 | # | |
5862 | #" | |
a62bfff2 | 5863 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5864 | (set_attr "length" "4,4,8,8")]) |
5865 | ||
5866 | (define_split | |
5867 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5868 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5869 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5870 | (const_int 0))) | |
5871 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5872 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5873 | "TARGET_POWERPC64 && reload_completed" | |
5874 | [(set (match_dup 0) | |
5875 | (plus:DI (match_dup 1) (match_dup 2))) | |
5876 | (set (match_dup 3) | |
5877 | (compare:CC (match_dup 0) | |
5878 | (const_int 0)))] | |
5879 | "") | |
266eb58a DE |
5880 | |
5881 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5882 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5883 | ;; add should be last in case the result gets used in an address. | |
5884 | ||
5885 | (define_split | |
5886 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5887 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5888 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5889 | "TARGET_POWERPC64" | |
5890 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5891 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5892 | " | |
5893 | { | |
2bfcf297 | 5894 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5895 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5896 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
266eb58a | 5897 | |
2bfcf297 DB |
5898 | operands[4] = GEN_INT (low); |
5899 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
5900 | operands[3] = GEN_INT (rest); | |
5901 | else if (! no_new_pseudos) | |
38886f37 | 5902 | { |
2bfcf297 DB |
5903 | operands[3] = gen_reg_rtx (DImode); |
5904 | emit_move_insn (operands[3], operands[2]); | |
5905 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
5906 | DONE; | |
38886f37 | 5907 | } |
2bfcf297 DB |
5908 | else |
5909 | FAIL; | |
266eb58a DE |
5910 | }") |
5911 | ||
5912 | (define_insn "one_cmpldi2" | |
5913 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5914 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5915 | "TARGET_POWERPC64" | |
5916 | "nor %0,%1,%1") | |
5917 | ||
5918 | (define_insn "" | |
9ebbca7d GK |
5919 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5920 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5921 | (const_int 0))) |
9ebbca7d | 5922 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 5923 | "TARGET_64BIT" |
9ebbca7d GK |
5924 | "@ |
5925 | nor. %2,%1,%1 | |
5926 | #" | |
5927 | [(set_attr "type" "compare") | |
5928 | (set_attr "length" "4,8")]) | |
5929 | ||
5930 | (define_split | |
5931 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5932 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5933 | (const_int 0))) | |
5934 | (clobber (match_scratch:DI 2 ""))] | |
5935 | "TARGET_POWERPC64 && reload_completed" | |
5936 | [(set (match_dup 2) | |
5937 | (not:DI (match_dup 1))) | |
5938 | (set (match_dup 0) | |
5939 | (compare:CC (match_dup 2) | |
5940 | (const_int 0)))] | |
5941 | "") | |
266eb58a DE |
5942 | |
5943 | (define_insn "" | |
9ebbca7d GK |
5944 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5945 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5946 | (const_int 0))) |
9ebbca7d | 5947 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 5948 | (not:DI (match_dup 1)))] |
683bdff7 | 5949 | "TARGET_64BIT" |
9ebbca7d GK |
5950 | "@ |
5951 | nor. %0,%1,%1 | |
5952 | #" | |
5953 | [(set_attr "type" "compare") | |
5954 | (set_attr "length" "4,8")]) | |
5955 | ||
5956 | (define_split | |
5957 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5958 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5959 | (const_int 0))) | |
5960 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5961 | (not:DI (match_dup 1)))] | |
5962 | "TARGET_POWERPC64 && reload_completed" | |
5963 | [(set (match_dup 0) | |
5964 | (not:DI (match_dup 1))) | |
5965 | (set (match_dup 2) | |
5966 | (compare:CC (match_dup 0) | |
5967 | (const_int 0)))] | |
5968 | "") | |
266eb58a DE |
5969 | |
5970 | (define_insn "" | |
5971 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5972 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5973 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5974 | "TARGET_POWERPC64" | |
5975 | "@ | |
5976 | subf %0,%2,%1 | |
5977 | subfic %0,%2,%1") | |
5978 | ||
5979 | (define_insn "" | |
9ebbca7d GK |
5980 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5981 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5982 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5983 | (const_int 0))) |
9ebbca7d | 5984 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 5985 | "TARGET_64BIT" |
9ebbca7d GK |
5986 | "@ |
5987 | subf. %3,%2,%1 | |
5988 | #" | |
a62bfff2 | 5989 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5990 | (set_attr "length" "4,8")]) |
5991 | ||
5992 | (define_split | |
5993 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5994 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5995 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5996 | (const_int 0))) | |
5997 | (clobber (match_scratch:DI 3 ""))] | |
5998 | "TARGET_POWERPC64 && reload_completed" | |
5999 | [(set (match_dup 3) | |
6000 | (minus:DI (match_dup 1) (match_dup 2))) | |
6001 | (set (match_dup 0) | |
6002 | (compare:CC (match_dup 3) | |
6003 | (const_int 0)))] | |
6004 | "") | |
266eb58a DE |
6005 | |
6006 | (define_insn "" | |
9ebbca7d GK |
6007 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6008 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6009 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6010 | (const_int 0))) |
9ebbca7d | 6011 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6012 | (minus:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6013 | "TARGET_64BIT" |
9ebbca7d GK |
6014 | "@ |
6015 | subf. %0,%2,%1 | |
6016 | #" | |
a62bfff2 | 6017 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6018 | (set_attr "length" "4,8")]) |
6019 | ||
6020 | (define_split | |
6021 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6022 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6023 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6024 | (const_int 0))) | |
6025 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6026 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6027 | "TARGET_POWERPC64 && reload_completed" | |
6028 | [(set (match_dup 0) | |
6029 | (minus:DI (match_dup 1) (match_dup 2))) | |
6030 | (set (match_dup 3) | |
6031 | (compare:CC (match_dup 0) | |
6032 | (const_int 0)))] | |
6033 | "") | |
266eb58a DE |
6034 | |
6035 | (define_expand "subdi3" | |
6036 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6037 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 6038 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
6039 | "" |
6040 | " | |
6041 | { | |
6042 | if (GET_CODE (operands[2]) == CONST_INT) | |
6043 | { | |
6044 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
6045 | negate_rtx (DImode, operands[2]))); | |
6046 | DONE; | |
6047 | } | |
6048 | }") | |
6049 | ||
ea112fc4 | 6050 | (define_insn_and_split "absdi2" |
266eb58a | 6051 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6052 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
6053 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6054 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6055 | "#" |
6056 | "&& reload_completed" | |
a260abc9 | 6057 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6058 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 6059 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
6060 | "") |
6061 | ||
ea112fc4 | 6062 | (define_insn_and_split "*nabsdi2" |
266eb58a | 6063 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6064 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
6065 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6066 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6067 | "#" |
6068 | "&& reload_completed" | |
a260abc9 | 6069 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6070 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 6071 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
6072 | "") |
6073 | ||
6074 | (define_expand "negdi2" | |
6075 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6076 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
6077 | "" | |
6078 | "") | |
6079 | ||
6080 | (define_insn "" | |
6081 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6082 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6083 | "TARGET_POWERPC64" | |
6084 | "neg %0,%1") | |
6085 | ||
6086 | (define_insn "" | |
9ebbca7d GK |
6087 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6088 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6089 | (const_int 0))) |
9ebbca7d | 6090 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 6091 | "TARGET_64BIT" |
9ebbca7d GK |
6092 | "@ |
6093 | neg. %2,%1 | |
6094 | #" | |
a62bfff2 | 6095 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6096 | (set_attr "length" "4,8")]) |
6097 | ||
6098 | (define_split | |
6099 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6100 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6101 | (const_int 0))) | |
6102 | (clobber (match_scratch:DI 2 ""))] | |
6103 | "TARGET_POWERPC64 && reload_completed" | |
6104 | [(set (match_dup 2) | |
6105 | (neg:DI (match_dup 1))) | |
6106 | (set (match_dup 0) | |
6107 | (compare:CC (match_dup 2) | |
6108 | (const_int 0)))] | |
6109 | "") | |
815cdc52 | 6110 | |
29ae5b89 | 6111 | (define_insn "" |
9ebbca7d GK |
6112 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6113 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6114 | (const_int 0))) |
9ebbca7d | 6115 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6116 | (neg:DI (match_dup 1)))] |
683bdff7 | 6117 | "TARGET_64BIT" |
9ebbca7d GK |
6118 | "@ |
6119 | neg. %0,%1 | |
6120 | #" | |
a62bfff2 | 6121 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6122 | (set_attr "length" "4,8")]) |
6123 | ||
6124 | (define_split | |
6125 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6126 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6127 | (const_int 0))) | |
6128 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6129 | (neg:DI (match_dup 1)))] | |
6130 | "TARGET_POWERPC64 && reload_completed" | |
6131 | [(set (match_dup 0) | |
6132 | (neg:DI (match_dup 1))) | |
6133 | (set (match_dup 2) | |
6134 | (compare:CC (match_dup 0) | |
6135 | (const_int 0)))] | |
6136 | "") | |
266eb58a | 6137 | |
1b1edcfa DE |
6138 | (define_insn "clzdi2" |
6139 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6140 | (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6141 | "TARGET_POWERPC64" | |
6142 | "cntlzd %0,%1") | |
6143 | ||
6144 | (define_expand "ctzdi2" | |
4977bab6 | 6145 | [(set (match_dup 2) |
1b1edcfa | 6146 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
6ae08853 AM |
6147 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
6148 | (match_dup 2))) | |
1b1edcfa | 6149 | (clobber (scratch:CC))]) |
d865b122 | 6150 | (set (match_dup 4) (clz:DI (match_dup 3))) |
4977bab6 | 6151 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 6152 | (minus:DI (const_int 63) (match_dup 4)))] |
266eb58a | 6153 | "TARGET_POWERPC64" |
4977bab6 | 6154 | { |
6ae08853 | 6155 | operands[2] = gen_reg_rtx (DImode); |
4977bab6 ZW |
6156 | operands[3] = gen_reg_rtx (DImode); |
6157 | operands[4] = gen_reg_rtx (DImode); | |
6158 | }) | |
6159 | ||
1b1edcfa DE |
6160 | (define_expand "ffsdi2" |
6161 | [(set (match_dup 2) | |
6162 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
6ae08853 AM |
6163 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
6164 | (match_dup 2))) | |
1b1edcfa DE |
6165 | (clobber (scratch:CC))]) |
6166 | (set (match_dup 4) (clz:DI (match_dup 3))) | |
6167 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6168 | (minus:DI (const_int 64) (match_dup 4)))] | |
4977bab6 | 6169 | "TARGET_POWERPC64" |
1b1edcfa | 6170 | { |
6ae08853 | 6171 | operands[2] = gen_reg_rtx (DImode); |
1b1edcfa DE |
6172 | operands[3] = gen_reg_rtx (DImode); |
6173 | operands[4] = gen_reg_rtx (DImode); | |
6174 | }) | |
266eb58a DE |
6175 | |
6176 | (define_insn "muldi3" | |
6177 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6178 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6179 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6180 | "TARGET_POWERPC64" | |
6181 | "mulld %0,%1,%2" | |
3cb999d8 | 6182 | [(set_attr "type" "lmul")]) |
266eb58a | 6183 | |
9259f3b0 DE |
6184 | (define_insn "*muldi3_internal1" |
6185 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6186 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6187 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6188 | (const_int 0))) | |
6189 | (clobber (match_scratch:DI 3 "=r,r"))] | |
6190 | "TARGET_POWERPC64" | |
6191 | "@ | |
6192 | mulld. %3,%1,%2 | |
6193 | #" | |
6194 | [(set_attr "type" "lmul_compare") | |
6195 | (set_attr "length" "4,8")]) | |
6196 | ||
6197 | (define_split | |
6198 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6199 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6200 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6201 | (const_int 0))) | |
6202 | (clobber (match_scratch:DI 3 ""))] | |
6203 | "TARGET_POWERPC64 && reload_completed" | |
6204 | [(set (match_dup 3) | |
6205 | (mult:DI (match_dup 1) (match_dup 2))) | |
6206 | (set (match_dup 0) | |
6207 | (compare:CC (match_dup 3) | |
6208 | (const_int 0)))] | |
6209 | "") | |
6210 | ||
6211 | (define_insn "*muldi3_internal2" | |
6212 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | |
6213 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6214 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6215 | (const_int 0))) | |
6216 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6217 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6218 | "TARGET_POWERPC64" | |
6219 | "@ | |
6220 | mulld. %0,%1,%2 | |
6221 | #" | |
6222 | [(set_attr "type" "lmul_compare") | |
6223 | (set_attr "length" "4,8")]) | |
6224 | ||
6225 | (define_split | |
6226 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6227 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6228 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6229 | (const_int 0))) | |
6230 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6231 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6232 | "TARGET_POWERPC64 && reload_completed" | |
6233 | [(set (match_dup 0) | |
6234 | (mult:DI (match_dup 1) (match_dup 2))) | |
6235 | (set (match_dup 3) | |
6236 | (compare:CC (match_dup 0) | |
6237 | (const_int 0)))] | |
6238 | "") | |
6239 | ||
266eb58a DE |
6240 | (define_insn "smuldi3_highpart" |
6241 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6242 | (truncate:DI | |
6243 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6244 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6245 | (sign_extend:TI | |
6246 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6247 | (const_int 64))))] | |
6248 | "TARGET_POWERPC64" | |
6249 | "mulhd %0,%1,%2" | |
3cb999d8 | 6250 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6251 | |
6252 | (define_insn "umuldi3_highpart" | |
6253 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6254 | (truncate:DI | |
6255 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6256 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6257 | (zero_extend:TI | |
6258 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6259 | (const_int 64))))] | |
6260 | "TARGET_POWERPC64" | |
6261 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6262 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6263 | |
6264 | (define_expand "divdi3" | |
6265 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6266 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6267 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6268 | "TARGET_POWERPC64" | |
6269 | " | |
6270 | { | |
6271 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6272 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6273 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6274 | ; | |
6275 | else | |
6276 | operands[2] = force_reg (DImode, operands[2]); | |
6277 | }") | |
6278 | ||
6279 | (define_expand "moddi3" | |
6280 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6281 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6282 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6283 | "TARGET_POWERPC64" | |
6284 | " | |
6285 | { | |
2bfcf297 | 6286 | int i; |
266eb58a DE |
6287 | rtx temp1; |
6288 | rtx temp2; | |
6289 | ||
2bfcf297 DB |
6290 | if (GET_CODE (operands[2]) != CONST_INT |
6291 | || INTVAL (operands[2]) <= 0 | |
6292 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6293 | FAIL; |
6294 | ||
6295 | temp1 = gen_reg_rtx (DImode); | |
6296 | temp2 = gen_reg_rtx (DImode); | |
6297 | ||
6298 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6299 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6300 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6301 | DONE; | |
6302 | }") | |
6303 | ||
6304 | (define_insn "" | |
6305 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6306 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6307 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6308 | "TARGET_POWERPC64" | |
266eb58a | 6309 | "sradi %0,%1,%p2\;addze %0,%0" |
943c15ed DE |
6310 | [(set_attr "type" "two") |
6311 | (set_attr "length" "8")]) | |
266eb58a DE |
6312 | |
6313 | (define_insn "" | |
9ebbca7d GK |
6314 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6315 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6316 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6317 | (const_int 0))) |
9ebbca7d | 6318 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6319 | "TARGET_64BIT" |
9ebbca7d GK |
6320 | "@ |
6321 | sradi %3,%1,%p2\;addze. %3,%3 | |
6322 | #" | |
266eb58a | 6323 | [(set_attr "type" "compare") |
9ebbca7d GK |
6324 | (set_attr "length" "8,12")]) |
6325 | ||
6326 | (define_split | |
6327 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6328 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6329 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6330 | (const_int 0))) |
6331 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6332 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6333 | [(set (match_dup 3) |
6334 | (div:DI (match_dup 1) (match_dup 2))) | |
6335 | (set (match_dup 0) | |
6336 | (compare:CC (match_dup 3) | |
6337 | (const_int 0)))] | |
6338 | "") | |
266eb58a DE |
6339 | |
6340 | (define_insn "" | |
9ebbca7d GK |
6341 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6342 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6343 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6344 | (const_int 0))) |
9ebbca7d | 6345 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6346 | (div:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6347 | "TARGET_64BIT" |
9ebbca7d GK |
6348 | "@ |
6349 | sradi %0,%1,%p2\;addze. %0,%0 | |
6350 | #" | |
266eb58a | 6351 | [(set_attr "type" "compare") |
9ebbca7d | 6352 | (set_attr "length" "8,12")]) |
266eb58a | 6353 | |
9ebbca7d GK |
6354 | (define_split |
6355 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6356 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6357 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6358 | (const_int 0))) |
6359 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6360 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6361 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6362 | [(set (match_dup 0) |
6363 | (div:DI (match_dup 1) (match_dup 2))) | |
6364 | (set (match_dup 3) | |
6365 | (compare:CC (match_dup 0) | |
6366 | (const_int 0)))] | |
6367 | "") | |
6368 | ||
6369 | (define_insn "" | |
6370 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6371 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6372 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6373 | "TARGET_POWERPC64" |
6374 | "divd %0,%1,%2" | |
3cb999d8 | 6375 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6376 | |
6377 | (define_insn "udivdi3" | |
6378 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6379 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6380 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6381 | "TARGET_POWERPC64" | |
6382 | "divdu %0,%1,%2" | |
3cb999d8 | 6383 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6384 | |
6385 | (define_insn "rotldi3" | |
6386 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6387 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6388 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6389 | "TARGET_POWERPC64" | |
a66078ee | 6390 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6391 | |
a260abc9 | 6392 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6393 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6394 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6395 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6396 | (const_int 0))) |
9ebbca7d | 6397 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6398 | "TARGET_64BIT" |
9ebbca7d GK |
6399 | "@ |
6400 | rld%I2cl. %3,%1,%H2,0 | |
6401 | #" | |
6402 | [(set_attr "type" "delayed_compare") | |
6403 | (set_attr "length" "4,8")]) | |
6404 | ||
6405 | (define_split | |
6406 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6407 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6408 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6409 | (const_int 0))) | |
6410 | (clobber (match_scratch:DI 3 ""))] | |
6411 | "TARGET_POWERPC64 && reload_completed" | |
6412 | [(set (match_dup 3) | |
6413 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6414 | (set (match_dup 0) | |
6415 | (compare:CC (match_dup 3) | |
6416 | (const_int 0)))] | |
6417 | "") | |
266eb58a | 6418 | |
a260abc9 | 6419 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6420 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6421 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6422 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6423 | (const_int 0))) |
9ebbca7d | 6424 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6425 | (rotate:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6426 | "TARGET_64BIT" |
9ebbca7d GK |
6427 | "@ |
6428 | rld%I2cl. %0,%1,%H2,0 | |
6429 | #" | |
6430 | [(set_attr "type" "delayed_compare") | |
6431 | (set_attr "length" "4,8")]) | |
6432 | ||
6433 | (define_split | |
6434 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6435 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6436 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6437 | (const_int 0))) | |
6438 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6439 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6440 | "TARGET_POWERPC64 && reload_completed" | |
6441 | [(set (match_dup 0) | |
6442 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6443 | (set (match_dup 3) | |
6444 | (compare:CC (match_dup 0) | |
6445 | (const_int 0)))] | |
6446 | "") | |
266eb58a | 6447 | |
a260abc9 DE |
6448 | (define_insn "*rotldi3_internal4" |
6449 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6450 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6451 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
ce71f754 | 6452 | (match_operand:DI 3 "mask64_operand" "n")))] |
a260abc9 DE |
6453 | "TARGET_POWERPC64" |
6454 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6455 | ||
6456 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6457 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6458 | (compare:CC (and:DI |
9ebbca7d GK |
6459 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6460 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6461 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6462 | (const_int 0))) |
9ebbca7d | 6463 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6464 | "TARGET_64BIT" |
9ebbca7d GK |
6465 | "@ |
6466 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6467 | #" | |
6468 | [(set_attr "type" "delayed_compare") | |
6469 | (set_attr "length" "4,8")]) | |
6470 | ||
6471 | (define_split | |
6472 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6473 | (compare:CC (and:DI | |
6474 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6475 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6476 | (match_operand:DI 3 "mask64_operand" "")) | |
6477 | (const_int 0))) | |
6478 | (clobber (match_scratch:DI 4 ""))] | |
6479 | "TARGET_POWERPC64 && reload_completed" | |
6480 | [(set (match_dup 4) | |
6481 | (and:DI (rotate:DI (match_dup 1) | |
6482 | (match_dup 2)) | |
6483 | (match_dup 3))) | |
6484 | (set (match_dup 0) | |
6485 | (compare:CC (match_dup 4) | |
6486 | (const_int 0)))] | |
6487 | "") | |
a260abc9 DE |
6488 | |
6489 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6490 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6491 | (compare:CC (and:DI |
9ebbca7d GK |
6492 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6493 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6494 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6495 | (const_int 0))) |
9ebbca7d | 6496 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6497 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6498 | "TARGET_64BIT" |
9ebbca7d GK |
6499 | "@ |
6500 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6501 | #" | |
6502 | [(set_attr "type" "delayed_compare") | |
6503 | (set_attr "length" "4,8")]) | |
6504 | ||
6505 | (define_split | |
6506 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6507 | (compare:CC (and:DI | |
6508 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6509 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6510 | (match_operand:DI 3 "mask64_operand" "")) | |
6511 | (const_int 0))) | |
6512 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6513 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6514 | "TARGET_POWERPC64 && reload_completed" | |
6515 | [(set (match_dup 0) | |
6516 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6517 | (set (match_dup 4) | |
6518 | (compare:CC (match_dup 0) | |
6519 | (const_int 0)))] | |
6520 | "") | |
a260abc9 DE |
6521 | |
6522 | (define_insn "*rotldi3_internal7" | |
6523 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6524 | (zero_extend:DI | |
6525 | (subreg:QI | |
6526 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6527 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6528 | "TARGET_POWERPC64" | |
6529 | "rld%I2cl %0,%1,%H2,56") | |
6530 | ||
6531 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6532 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6533 | (compare:CC (zero_extend:DI |
6534 | (subreg:QI | |
9ebbca7d GK |
6535 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6536 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6537 | (const_int 0))) |
9ebbca7d | 6538 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6539 | "TARGET_64BIT" |
9ebbca7d GK |
6540 | "@ |
6541 | rld%I2cl. %3,%1,%H2,56 | |
6542 | #" | |
6543 | [(set_attr "type" "delayed_compare") | |
6544 | (set_attr "length" "4,8")]) | |
6545 | ||
6546 | (define_split | |
6547 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6548 | (compare:CC (zero_extend:DI | |
6549 | (subreg:QI | |
6550 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6551 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6552 | (const_int 0))) | |
6553 | (clobber (match_scratch:DI 3 ""))] | |
6554 | "TARGET_POWERPC64 && reload_completed" | |
6555 | [(set (match_dup 3) | |
6556 | (zero_extend:DI (subreg:QI | |
6557 | (rotate:DI (match_dup 1) | |
6558 | (match_dup 2)) 0))) | |
6559 | (set (match_dup 0) | |
6560 | (compare:CC (match_dup 3) | |
6561 | (const_int 0)))] | |
6562 | "") | |
a260abc9 DE |
6563 | |
6564 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6565 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6566 | (compare:CC (zero_extend:DI |
6567 | (subreg:QI | |
9ebbca7d GK |
6568 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6569 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6570 | (const_int 0))) |
9ebbca7d | 6571 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6572 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6573 | "TARGET_64BIT" |
9ebbca7d GK |
6574 | "@ |
6575 | rld%I2cl. %0,%1,%H2,56 | |
6576 | #" | |
6577 | [(set_attr "type" "delayed_compare") | |
6578 | (set_attr "length" "4,8")]) | |
6579 | ||
6580 | (define_split | |
6581 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6582 | (compare:CC (zero_extend:DI | |
6583 | (subreg:QI | |
6584 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6585 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6586 | (const_int 0))) | |
6587 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6588 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6589 | "TARGET_POWERPC64 && reload_completed" | |
6590 | [(set (match_dup 0) | |
6591 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6592 | (set (match_dup 3) | |
6593 | (compare:CC (match_dup 0) | |
6594 | (const_int 0)))] | |
6595 | "") | |
a260abc9 DE |
6596 | |
6597 | (define_insn "*rotldi3_internal10" | |
6598 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6599 | (zero_extend:DI | |
6600 | (subreg:HI | |
6601 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6602 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6603 | "TARGET_POWERPC64" | |
6604 | "rld%I2cl %0,%1,%H2,48") | |
6605 | ||
6606 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6607 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6608 | (compare:CC (zero_extend:DI |
6609 | (subreg:HI | |
9ebbca7d GK |
6610 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6611 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6612 | (const_int 0))) |
9ebbca7d | 6613 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6614 | "TARGET_64BIT" |
9ebbca7d GK |
6615 | "@ |
6616 | rld%I2cl. %3,%1,%H2,48 | |
6617 | #" | |
6618 | [(set_attr "type" "delayed_compare") | |
6619 | (set_attr "length" "4,8")]) | |
6620 | ||
6621 | (define_split | |
6622 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6623 | (compare:CC (zero_extend:DI | |
6624 | (subreg:HI | |
6625 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6626 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6627 | (const_int 0))) | |
6628 | (clobber (match_scratch:DI 3 ""))] | |
6629 | "TARGET_POWERPC64 && reload_completed" | |
6630 | [(set (match_dup 3) | |
6631 | (zero_extend:DI (subreg:HI | |
6632 | (rotate:DI (match_dup 1) | |
6633 | (match_dup 2)) 0))) | |
6634 | (set (match_dup 0) | |
6635 | (compare:CC (match_dup 3) | |
6636 | (const_int 0)))] | |
6637 | "") | |
a260abc9 DE |
6638 | |
6639 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6640 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6641 | (compare:CC (zero_extend:DI |
6642 | (subreg:HI | |
9ebbca7d GK |
6643 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6644 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6645 | (const_int 0))) |
9ebbca7d | 6646 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6647 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6648 | "TARGET_64BIT" |
9ebbca7d GK |
6649 | "@ |
6650 | rld%I2cl. %0,%1,%H2,48 | |
6651 | #" | |
6652 | [(set_attr "type" "delayed_compare") | |
6653 | (set_attr "length" "4,8")]) | |
6654 | ||
6655 | (define_split | |
6656 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6657 | (compare:CC (zero_extend:DI | |
6658 | (subreg:HI | |
6659 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6660 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6661 | (const_int 0))) | |
6662 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6663 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6664 | "TARGET_POWERPC64 && reload_completed" | |
6665 | [(set (match_dup 0) | |
6666 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6667 | (set (match_dup 3) | |
6668 | (compare:CC (match_dup 0) | |
6669 | (const_int 0)))] | |
6670 | "") | |
a260abc9 DE |
6671 | |
6672 | (define_insn "*rotldi3_internal13" | |
6673 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6674 | (zero_extend:DI | |
6675 | (subreg:SI | |
6676 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6677 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6678 | "TARGET_POWERPC64" | |
6679 | "rld%I2cl %0,%1,%H2,32") | |
6680 | ||
6681 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6682 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6683 | (compare:CC (zero_extend:DI |
6684 | (subreg:SI | |
9ebbca7d GK |
6685 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6686 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6687 | (const_int 0))) |
9ebbca7d | 6688 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6689 | "TARGET_64BIT" |
9ebbca7d GK |
6690 | "@ |
6691 | rld%I2cl. %3,%1,%H2,32 | |
6692 | #" | |
6693 | [(set_attr "type" "delayed_compare") | |
6694 | (set_attr "length" "4,8")]) | |
6695 | ||
6696 | (define_split | |
6697 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6698 | (compare:CC (zero_extend:DI | |
6699 | (subreg:SI | |
6700 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6701 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6702 | (const_int 0))) | |
6703 | (clobber (match_scratch:DI 3 ""))] | |
6704 | "TARGET_POWERPC64 && reload_completed" | |
6705 | [(set (match_dup 3) | |
6706 | (zero_extend:DI (subreg:SI | |
6707 | (rotate:DI (match_dup 1) | |
6708 | (match_dup 2)) 0))) | |
6709 | (set (match_dup 0) | |
6710 | (compare:CC (match_dup 3) | |
6711 | (const_int 0)))] | |
6712 | "") | |
a260abc9 DE |
6713 | |
6714 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6715 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6716 | (compare:CC (zero_extend:DI |
6717 | (subreg:SI | |
9ebbca7d GK |
6718 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6719 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6720 | (const_int 0))) |
9ebbca7d | 6721 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6722 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6723 | "TARGET_64BIT" |
9ebbca7d GK |
6724 | "@ |
6725 | rld%I2cl. %0,%1,%H2,32 | |
6726 | #" | |
6727 | [(set_attr "type" "delayed_compare") | |
6728 | (set_attr "length" "4,8")]) | |
6729 | ||
6730 | (define_split | |
6731 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6732 | (compare:CC (zero_extend:DI | |
6733 | (subreg:SI | |
6734 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6735 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6736 | (const_int 0))) | |
6737 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6738 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6739 | "TARGET_POWERPC64 && reload_completed" | |
6740 | [(set (match_dup 0) | |
6741 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6742 | (set (match_dup 3) | |
6743 | (compare:CC (match_dup 0) | |
6744 | (const_int 0)))] | |
6745 | "") | |
a260abc9 | 6746 | |
266eb58a DE |
6747 | (define_expand "ashldi3" |
6748 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6749 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6750 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6751 | "TARGET_POWERPC64 || TARGET_POWER" | |
6752 | " | |
6753 | { | |
6754 | if (TARGET_POWERPC64) | |
6755 | ; | |
6756 | else if (TARGET_POWER) | |
6757 | { | |
6758 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6759 | DONE; | |
6760 | } | |
6761 | else | |
6762 | FAIL; | |
6763 | }") | |
6764 | ||
e2c953b6 | 6765 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6766 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6767 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6768 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6769 | "TARGET_POWERPC64" | |
943c15ed | 6770 | "sld%I2 %0,%1,%H2") |
6ae08853 | 6771 | |
e2c953b6 | 6772 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6773 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6774 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6775 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6776 | (const_int 0))) |
9ebbca7d | 6777 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6778 | "TARGET_64BIT" |
9ebbca7d GK |
6779 | "@ |
6780 | sld%I2. %3,%1,%H2 | |
6781 | #" | |
6782 | [(set_attr "type" "delayed_compare") | |
6783 | (set_attr "length" "4,8")]) | |
6ae08853 | 6784 | |
9ebbca7d GK |
6785 | (define_split |
6786 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6787 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6788 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6789 | (const_int 0))) | |
6790 | (clobber (match_scratch:DI 3 ""))] | |
6791 | "TARGET_POWERPC64 && reload_completed" | |
6792 | [(set (match_dup 3) | |
6793 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6794 | (set (match_dup 0) | |
6795 | (compare:CC (match_dup 3) | |
6796 | (const_int 0)))] | |
6797 | "") | |
6798 | ||
e2c953b6 | 6799 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6800 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6801 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6802 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6803 | (const_int 0))) |
9ebbca7d | 6804 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6805 | (ashift:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6806 | "TARGET_64BIT" |
9ebbca7d GK |
6807 | "@ |
6808 | sld%I2. %0,%1,%H2 | |
6809 | #" | |
6810 | [(set_attr "type" "delayed_compare") | |
6811 | (set_attr "length" "4,8")]) | |
6812 | ||
6813 | (define_split | |
6814 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6815 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6816 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6817 | (const_int 0))) | |
6818 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6819 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6820 | "TARGET_POWERPC64 && reload_completed" | |
6821 | [(set (match_dup 0) | |
6822 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6823 | (set (match_dup 3) | |
6824 | (compare:CC (match_dup 0) | |
6825 | (const_int 0)))] | |
6826 | "") | |
266eb58a | 6827 | |
e2c953b6 | 6828 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6829 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6830 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6831 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6832 | (match_operand:DI 3 "const_int_operand" "n")))] |
6833 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6834 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6835 | |
e2c953b6 | 6836 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6837 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6838 | (compare:CC |
9ebbca7d GK |
6839 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6840 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6841 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6842 | (const_int 0))) |
9ebbca7d | 6843 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6844 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6845 | "@ |
e2c953b6 | 6846 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6847 | #" |
6848 | [(set_attr "type" "delayed_compare") | |
6849 | (set_attr "length" "4,8")]) | |
6850 | ||
6851 | (define_split | |
6852 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6853 | (compare:CC | |
6854 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6855 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6856 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6857 | (const_int 0))) |
6858 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6859 | "TARGET_POWERPC64 && reload_completed |
6860 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6861 | [(set (match_dup 4) |
6862 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6863 | (match_dup 3))) |
9ebbca7d GK |
6864 | (set (match_dup 0) |
6865 | (compare:CC (match_dup 4) | |
6866 | (const_int 0)))] | |
6867 | "") | |
3cb999d8 | 6868 | |
e2c953b6 | 6869 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6870 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6871 | (compare:CC |
9ebbca7d GK |
6872 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6873 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6874 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6875 | (const_int 0))) |
9ebbca7d | 6876 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6877 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6878 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6879 | "@ |
e2c953b6 | 6880 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6881 | #" |
6882 | [(set_attr "type" "delayed_compare") | |
6883 | (set_attr "length" "4,8")]) | |
6884 | ||
6885 | (define_split | |
6886 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6887 | (compare:CC | |
6888 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6889 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6890 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6891 | (const_int 0))) |
6892 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6893 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6894 | "TARGET_POWERPC64 && reload_completed |
6895 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6896 | [(set (match_dup 0) | |
6897 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6898 | (match_dup 3))) | |
6899 | (set (match_dup 4) | |
6900 | (compare:CC (match_dup 0) | |
6901 | (const_int 0)))] | |
6902 | "") | |
6903 | ||
6904 | (define_insn "*ashldi3_internal7" | |
6905 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6906 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6907 | (match_operand:SI 2 "const_int_operand" "i")) | |
ce71f754 | 6908 | (match_operand:DI 3 "mask64_operand" "n")))] |
c5059423 AM |
6909 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
6910 | "rldicr %0,%1,%H2,%S3") | |
6911 | ||
6912 | (define_insn "ashldi3_internal8" | |
6913 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6914 | (compare:CC | |
6915 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6916 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6917 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6918 | (const_int 0))) |
6919 | (clobber (match_scratch:DI 4 "=r,r"))] | |
683bdff7 | 6920 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6921 | "@ |
6922 | rldicr. %4,%1,%H2,%S3 | |
6923 | #" | |
6924 | [(set_attr "type" "delayed_compare") | |
6925 | (set_attr "length" "4,8")]) | |
6926 | ||
6927 | (define_split | |
6928 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6929 | (compare:CC | |
6930 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6931 | (match_operand:SI 2 "const_int_operand" "")) | |
6932 | (match_operand:DI 3 "mask64_operand" "")) | |
6933 | (const_int 0))) | |
6934 | (clobber (match_scratch:DI 4 ""))] | |
6935 | "TARGET_POWERPC64 && reload_completed | |
6936 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6937 | [(set (match_dup 4) | |
6938 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6939 | (match_dup 3))) | |
6940 | (set (match_dup 0) | |
6941 | (compare:CC (match_dup 4) | |
6942 | (const_int 0)))] | |
6943 | "") | |
6944 | ||
6945 | (define_insn "*ashldi3_internal9" | |
6946 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6947 | (compare:CC | |
6948 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6949 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6950 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6951 | (const_int 0))) |
6952 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6953 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 6954 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6955 | "@ |
6956 | rldicr. %0,%1,%H2,%S3 | |
6957 | #" | |
6958 | [(set_attr "type" "delayed_compare") | |
6959 | (set_attr "length" "4,8")]) | |
6960 | ||
6961 | (define_split | |
6962 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6963 | (compare:CC | |
6964 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6965 | (match_operand:SI 2 "const_int_operand" "")) | |
6966 | (match_operand:DI 3 "mask64_operand" "")) | |
6967 | (const_int 0))) | |
6968 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6969 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6970 | "TARGET_POWERPC64 && reload_completed | |
6971 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6972 | [(set (match_dup 0) |
e2c953b6 DE |
6973 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6974 | (match_dup 3))) | |
9ebbca7d GK |
6975 | (set (match_dup 4) |
6976 | (compare:CC (match_dup 0) | |
6977 | (const_int 0)))] | |
6978 | "") | |
6979 | ||
6980 | (define_expand "lshrdi3" | |
266eb58a DE |
6981 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6982 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6983 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6984 | "TARGET_POWERPC64 || TARGET_POWER" | |
6985 | " | |
6986 | { | |
6987 | if (TARGET_POWERPC64) | |
6988 | ; | |
6989 | else if (TARGET_POWER) | |
6990 | { | |
6991 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6992 | DONE; | |
6993 | } | |
6994 | else | |
6995 | FAIL; | |
6996 | }") | |
6997 | ||
e2c953b6 | 6998 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6999 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7000 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7001 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7002 | "TARGET_POWERPC64" | |
a66078ee | 7003 | "srd%I2 %0,%1,%H2") |
266eb58a | 7004 | |
e2c953b6 | 7005 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
7006 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7007 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7008 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 7009 | (const_int 0))) |
9ebbca7d | 7010 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7011 | "TARGET_64BIT " |
9ebbca7d GK |
7012 | "@ |
7013 | srd%I2. %3,%1,%H2 | |
7014 | #" | |
7015 | [(set_attr "type" "delayed_compare") | |
7016 | (set_attr "length" "4,8")]) | |
7017 | ||
7018 | (define_split | |
7019 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7020 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7021 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7022 | (const_int 0))) | |
7023 | (clobber (match_scratch:DI 3 ""))] | |
7024 | "TARGET_POWERPC64 && reload_completed" | |
7025 | [(set (match_dup 3) | |
7026 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7027 | (set (match_dup 0) | |
7028 | (compare:CC (match_dup 3) | |
7029 | (const_int 0)))] | |
7030 | "") | |
266eb58a | 7031 | |
e2c953b6 | 7032 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
7033 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7034 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7035 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7036 | (const_int 0))) |
9ebbca7d | 7037 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 7038 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 7039 | "TARGET_64BIT" |
9ebbca7d GK |
7040 | "@ |
7041 | srd%I2. %0,%1,%H2 | |
7042 | #" | |
7043 | [(set_attr "type" "delayed_compare") | |
7044 | (set_attr "length" "4,8")]) | |
7045 | ||
7046 | (define_split | |
7047 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7048 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7049 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7050 | (const_int 0))) | |
7051 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7052 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
7053 | "TARGET_POWERPC64 && reload_completed" | |
7054 | [(set (match_dup 0) | |
7055 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7056 | (set (match_dup 3) | |
7057 | (compare:CC (match_dup 0) | |
7058 | (const_int 0)))] | |
7059 | "") | |
266eb58a DE |
7060 | |
7061 | (define_expand "ashrdi3" | |
7062 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7063 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7064 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
97727e85 | 7065 | "WORDS_BIG_ENDIAN" |
266eb58a DE |
7066 | " |
7067 | { | |
7068 | if (TARGET_POWERPC64) | |
7069 | ; | |
7070 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
7071 | { | |
7072 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
7073 | DONE; | |
7074 | } | |
97727e85 AH |
7075 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT |
7076 | && WORDS_BIG_ENDIAN) | |
4aa74a4f FS |
7077 | { |
7078 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
7079 | DONE; | |
7080 | } | |
266eb58a DE |
7081 | else |
7082 | FAIL; | |
7083 | }") | |
7084 | ||
e2c953b6 | 7085 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
7086 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7087 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7088 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7089 | "TARGET_POWERPC64" | |
375490e0 | 7090 | "srad%I2 %0,%1,%H2") |
266eb58a | 7091 | |
e2c953b6 | 7092 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
7093 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7094 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7095 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7096 | (const_int 0))) |
9ebbca7d | 7097 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7098 | "TARGET_64BIT" |
9ebbca7d GK |
7099 | "@ |
7100 | srad%I2. %3,%1,%H2 | |
7101 | #" | |
7102 | [(set_attr "type" "delayed_compare") | |
7103 | (set_attr "length" "4,8")]) | |
7104 | ||
7105 | (define_split | |
7106 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7107 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7108 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7109 | (const_int 0))) | |
7110 | (clobber (match_scratch:DI 3 ""))] | |
7111 | "TARGET_POWERPC64 && reload_completed" | |
7112 | [(set (match_dup 3) | |
7113 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7114 | (set (match_dup 0) | |
7115 | (compare:CC (match_dup 3) | |
7116 | (const_int 0)))] | |
7117 | "") | |
266eb58a | 7118 | |
e2c953b6 | 7119 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
7120 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7121 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7122 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7123 | (const_int 0))) |
9ebbca7d | 7124 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 7125 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 7126 | "TARGET_64BIT" |
9ebbca7d GK |
7127 | "@ |
7128 | srad%I2. %0,%1,%H2 | |
7129 | #" | |
7130 | [(set_attr "type" "delayed_compare") | |
7131 | (set_attr "length" "4,8")]) | |
7132 | ||
7133 | (define_split | |
7134 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7135 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7136 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7137 | (const_int 0))) | |
7138 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7139 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7140 | "TARGET_POWERPC64 && reload_completed" | |
7141 | [(set (match_dup 0) | |
7142 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7143 | (set (match_dup 3) | |
7144 | (compare:CC (match_dup 0) | |
7145 | (const_int 0)))] | |
7146 | "") | |
815cdc52 | 7147 | |
29ae5b89 | 7148 | (define_insn "anddi3" |
e1e2e653 NS |
7149 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
7150 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") | |
7151 | (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t"))) | |
7152 | (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))] | |
6ffc8580 | 7153 | "TARGET_POWERPC64" |
266eb58a DE |
7154 | "@ |
7155 | and %0,%1,%2 | |
29ae5b89 | 7156 | rldic%B2 %0,%1,0,%S2 |
e1e2e653 | 7157 | rlwinm %0,%1,0,%m2,%M2 |
29ae5b89 | 7158 | andi. %0,%1,%b2 |
0ba1b2ff AM |
7159 | andis. %0,%1,%u2 |
7160 | #" | |
e1e2e653 NS |
7161 | [(set_attr "type" "*,*,*,compare,compare,*") |
7162 | (set_attr "length" "4,4,4,4,4,8")]) | |
0ba1b2ff AM |
7163 | |
7164 | (define_split | |
7165 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7166 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7167 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
7168 | (clobber (match_scratch:CC 3 ""))] | |
7169 | "TARGET_POWERPC64 | |
7170 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7171 | && !mask64_operand (operands[2], DImode)" | |
7172 | [(set (match_dup 0) | |
7173 | (and:DI (rotate:DI (match_dup 1) | |
7174 | (match_dup 4)) | |
7175 | (match_dup 5))) | |
7176 | (set (match_dup 0) | |
7177 | (and:DI (rotate:DI (match_dup 0) | |
7178 | (match_dup 6)) | |
7179 | (match_dup 7)))] | |
0ba1b2ff AM |
7180 | { |
7181 | build_mask64_2_operands (operands[2], &operands[4]); | |
e1e2e653 | 7182 | }) |
266eb58a | 7183 | |
a260abc9 | 7184 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
7185 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7186 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7187 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7188 | (const_int 0))) |
0ba1b2ff AM |
7189 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
7190 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
683bdff7 | 7191 | "TARGET_64BIT" |
266eb58a DE |
7192 | "@ |
7193 | and. %3,%1,%2 | |
6c873122 | 7194 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
7195 | andi. %3,%1,%b2 |
7196 | andis. %3,%1,%u2 | |
9ebbca7d GK |
7197 | # |
7198 | # | |
7199 | # | |
0ba1b2ff AM |
7200 | # |
7201 | # | |
9ebbca7d | 7202 | #" |
0ba1b2ff AM |
7203 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7204 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7205 | |
7206 | (define_split | |
7207 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7208 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7209 | (match_operand:DI 2 "and64_operand" "")) | |
7210 | (const_int 0))) | |
7211 | (clobber (match_scratch:DI 3 "")) | |
7212 | (clobber (match_scratch:CC 4 ""))] | |
7213 | "TARGET_POWERPC64 && reload_completed" | |
7214 | [(parallel [(set (match_dup 3) | |
7215 | (and:DI (match_dup 1) | |
7216 | (match_dup 2))) | |
7217 | (clobber (match_dup 4))]) | |
7218 | (set (match_dup 0) | |
7219 | (compare:CC (match_dup 3) | |
7220 | (const_int 0)))] | |
7221 | "") | |
266eb58a | 7222 | |
0ba1b2ff AM |
7223 | (define_split |
7224 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
7225 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7226 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7227 | (const_int 0))) | |
7228 | (clobber (match_scratch:DI 3 "")) | |
7229 | (clobber (match_scratch:CC 4 ""))] | |
7230 | "TARGET_POWERPC64 && reload_completed | |
7231 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7232 | && !mask64_operand (operands[2], DImode)" | |
7233 | [(set (match_dup 3) | |
7234 | (and:DI (rotate:DI (match_dup 1) | |
7235 | (match_dup 5)) | |
7236 | (match_dup 6))) | |
7237 | (parallel [(set (match_dup 0) | |
7238 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
7239 | (match_dup 7)) | |
7240 | (match_dup 8)) | |
7241 | (const_int 0))) | |
7242 | (clobber (match_dup 3))])] | |
7243 | " | |
7244 | { | |
7245 | build_mask64_2_operands (operands[2], &operands[5]); | |
7246 | }") | |
7247 | ||
a260abc9 | 7248 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
7249 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7250 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7251 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7252 | (const_int 0))) |
0ba1b2ff | 7253 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 7254 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 7255 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
683bdff7 | 7256 | "TARGET_64BIT" |
266eb58a DE |
7257 | "@ |
7258 | and. %0,%1,%2 | |
6c873122 | 7259 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7260 | andi. %0,%1,%b2 |
7261 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7262 | # |
7263 | # | |
7264 | # | |
0ba1b2ff AM |
7265 | # |
7266 | # | |
9ebbca7d | 7267 | #" |
0ba1b2ff AM |
7268 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7269 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7270 | |
7271 | (define_split | |
7272 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7273 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7274 | (match_operand:DI 2 "and64_operand" "")) | |
7275 | (const_int 0))) | |
7276 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7277 | (and:DI (match_dup 1) (match_dup 2))) | |
7278 | (clobber (match_scratch:CC 4 ""))] | |
7279 | "TARGET_POWERPC64 && reload_completed" | |
7280 | [(parallel [(set (match_dup 0) | |
7281 | (and:DI (match_dup 1) (match_dup 2))) | |
7282 | (clobber (match_dup 4))]) | |
7283 | (set (match_dup 3) | |
7284 | (compare:CC (match_dup 0) | |
7285 | (const_int 0)))] | |
7286 | "") | |
266eb58a | 7287 | |
0ba1b2ff AM |
7288 | (define_split |
7289 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
7290 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7291 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7292 | (const_int 0))) | |
7293 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7294 | (and:DI (match_dup 1) (match_dup 2))) | |
7295 | (clobber (match_scratch:CC 4 ""))] | |
7296 | "TARGET_POWERPC64 && reload_completed | |
7297 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7298 | && !mask64_operand (operands[2], DImode)" | |
7299 | [(set (match_dup 0) | |
7300 | (and:DI (rotate:DI (match_dup 1) | |
7301 | (match_dup 5)) | |
7302 | (match_dup 6))) | |
7303 | (parallel [(set (match_dup 3) | |
7304 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
7305 | (match_dup 7)) | |
7306 | (match_dup 8)) | |
7307 | (const_int 0))) | |
7308 | (set (match_dup 0) | |
7309 | (and:DI (rotate:DI (match_dup 0) | |
7310 | (match_dup 7)) | |
7311 | (match_dup 8)))])] | |
7312 | " | |
7313 | { | |
7314 | build_mask64_2_operands (operands[2], &operands[5]); | |
7315 | }") | |
7316 | ||
a260abc9 | 7317 | (define_expand "iordi3" |
266eb58a | 7318 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7319 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7320 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7321 | "TARGET_POWERPC64" |
266eb58a DE |
7322 | " |
7323 | { | |
dfbdccdb | 7324 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7325 | { |
dfbdccdb | 7326 | HOST_WIDE_INT value; |
677a9668 | 7327 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7328 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7329 | |
dfbdccdb GK |
7330 | if (GET_CODE (operands[2]) == CONST_INT) |
7331 | { | |
7332 | value = INTVAL (operands[2]); | |
7333 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7334 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7335 | } | |
e2c953b6 | 7336 | else |
dfbdccdb GK |
7337 | { |
7338 | value = CONST_DOUBLE_LOW (operands[2]); | |
7339 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7340 | immed_double_const (value | |
7341 | & (~ (HOST_WIDE_INT) 0xffff), | |
7342 | 0, DImode))); | |
7343 | } | |
e2c953b6 | 7344 | |
9ebbca7d GK |
7345 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7346 | DONE; | |
7347 | } | |
266eb58a DE |
7348 | }") |
7349 | ||
a260abc9 DE |
7350 | (define_expand "xordi3" |
7351 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7352 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7353 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7354 | "TARGET_POWERPC64" |
7355 | " | |
7356 | { | |
dfbdccdb | 7357 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7358 | { |
dfbdccdb | 7359 | HOST_WIDE_INT value; |
677a9668 | 7360 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7361 | ? operands[0] : gen_reg_rtx (DImode)); |
7362 | ||
dfbdccdb GK |
7363 | if (GET_CODE (operands[2]) == CONST_INT) |
7364 | { | |
7365 | value = INTVAL (operands[2]); | |
7366 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7367 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7368 | } | |
e2c953b6 | 7369 | else |
dfbdccdb GK |
7370 | { |
7371 | value = CONST_DOUBLE_LOW (operands[2]); | |
7372 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7373 | immed_double_const (value | |
7374 | & (~ (HOST_WIDE_INT) 0xffff), | |
7375 | 0, DImode))); | |
7376 | } | |
e2c953b6 | 7377 | |
9ebbca7d GK |
7378 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7379 | DONE; | |
7380 | } | |
a260abc9 DE |
7381 | }") |
7382 | ||
dfbdccdb | 7383 | (define_insn "*booldi3_internal1" |
266eb58a | 7384 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7385 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7386 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7387 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7388 | "TARGET_POWERPC64" |
1fd4e8c1 | 7389 | "@ |
dfbdccdb GK |
7390 | %q3 %0,%1,%2 |
7391 | %q3i %0,%1,%b2 | |
7392 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7393 | |
dfbdccdb | 7394 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7395 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7396 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7397 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7398 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7399 | (const_int 0))) | |
9ebbca7d | 7400 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7401 | "TARGET_64BIT" |
9ebbca7d | 7402 | "@ |
dfbdccdb | 7403 | %q4. %3,%1,%2 |
9ebbca7d GK |
7404 | #" |
7405 | [(set_attr "type" "compare") | |
7406 | (set_attr "length" "4,8")]) | |
7407 | ||
7408 | (define_split | |
7409 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7410 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7411 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7412 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7413 | (const_int 0))) |
9ebbca7d GK |
7414 | (clobber (match_scratch:DI 3 ""))] |
7415 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7416 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7417 | (set (match_dup 0) |
7418 | (compare:CC (match_dup 3) | |
7419 | (const_int 0)))] | |
7420 | "") | |
1fd4e8c1 | 7421 | |
dfbdccdb | 7422 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7423 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7424 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7425 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7426 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7427 | (const_int 0))) | |
9ebbca7d | 7428 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7429 | (match_dup 4))] |
683bdff7 | 7430 | "TARGET_64BIT" |
9ebbca7d | 7431 | "@ |
dfbdccdb | 7432 | %q4. %0,%1,%2 |
9ebbca7d GK |
7433 | #" |
7434 | [(set_attr "type" "compare") | |
7435 | (set_attr "length" "4,8")]) | |
7436 | ||
7437 | (define_split | |
e72247f4 | 7438 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7439 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7440 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7441 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7442 | (const_int 0))) |
75540af0 | 7443 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7444 | (match_dup 4))] |
9ebbca7d | 7445 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7446 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7447 | (set (match_dup 3) |
7448 | (compare:CC (match_dup 0) | |
7449 | (const_int 0)))] | |
7450 | "") | |
1fd4e8c1 | 7451 | |
6ae08853 | 7452 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 7453 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
7454 | |
7455 | (define_split | |
7456 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7457 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7458 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7459 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7460 | "TARGET_POWERPC64" |
dfbdccdb GK |
7461 | [(set (match_dup 0) (match_dup 4)) |
7462 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7463 | " |
7464 | { | |
dfbdccdb | 7465 | rtx i3,i4; |
6ae08853 | 7466 | |
9ebbca7d GK |
7467 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7468 | { | |
7469 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7470 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7471 | 0, DImode); |
dfbdccdb | 7472 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7473 | } |
7474 | else | |
7475 | { | |
dfbdccdb | 7476 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7477 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7478 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7479 | } |
1c563bed | 7480 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7481 | operands[1], i3); |
1c563bed | 7482 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7483 | operands[0], i4); |
1fd4e8c1 RK |
7484 | }") |
7485 | ||
dfbdccdb | 7486 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7487 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7488 | (match_operator:DI 3 "boolean_operator" |
7489 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7490 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7491 | "TARGET_POWERPC64" |
1d328b19 | 7492 | "%q3 %0,%2,%1") |
a473029f | 7493 | |
dfbdccdb | 7494 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7495 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7496 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7497 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7498 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7499 | (const_int 0))) | |
9ebbca7d | 7500 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7501 | "TARGET_64BIT" |
9ebbca7d | 7502 | "@ |
1d328b19 | 7503 | %q4. %3,%2,%1 |
9ebbca7d GK |
7504 | #" |
7505 | [(set_attr "type" "compare") | |
7506 | (set_attr "length" "4,8")]) | |
7507 | ||
7508 | (define_split | |
7509 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7510 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7511 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7512 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7513 | (const_int 0))) |
9ebbca7d GK |
7514 | (clobber (match_scratch:DI 3 ""))] |
7515 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7516 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7517 | (set (match_dup 0) |
7518 | (compare:CC (match_dup 3) | |
7519 | (const_int 0)))] | |
7520 | "") | |
a473029f | 7521 | |
dfbdccdb | 7522 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7523 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7524 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7525 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7526 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7527 | (const_int 0))) | |
9ebbca7d | 7528 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7529 | (match_dup 4))] |
683bdff7 | 7530 | "TARGET_64BIT" |
9ebbca7d | 7531 | "@ |
1d328b19 | 7532 | %q4. %0,%2,%1 |
9ebbca7d GK |
7533 | #" |
7534 | [(set_attr "type" "compare") | |
7535 | (set_attr "length" "4,8")]) | |
7536 | ||
7537 | (define_split | |
e72247f4 | 7538 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7539 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7540 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7541 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7542 | (const_int 0))) |
75540af0 | 7543 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7544 | (match_dup 4))] |
9ebbca7d | 7545 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7546 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7547 | (set (match_dup 3) |
7548 | (compare:CC (match_dup 0) | |
7549 | (const_int 0)))] | |
7550 | "") | |
266eb58a | 7551 | |
dfbdccdb | 7552 | (define_insn "*boolccdi3_internal1" |
a473029f | 7553 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7554 | (match_operator:DI 3 "boolean_operator" |
7555 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7556 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7557 | "TARGET_POWERPC64" |
dfbdccdb | 7558 | "%q3 %0,%1,%2") |
a473029f | 7559 | |
dfbdccdb | 7560 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7561 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7562 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7563 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7564 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7565 | (const_int 0))) | |
9ebbca7d | 7566 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7567 | "TARGET_64BIT" |
9ebbca7d | 7568 | "@ |
dfbdccdb | 7569 | %q4. %3,%1,%2 |
9ebbca7d GK |
7570 | #" |
7571 | [(set_attr "type" "compare") | |
7572 | (set_attr "length" "4,8")]) | |
7573 | ||
7574 | (define_split | |
7575 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7576 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7577 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7578 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7579 | (const_int 0))) |
9ebbca7d GK |
7580 | (clobber (match_scratch:DI 3 ""))] |
7581 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7582 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7583 | (set (match_dup 0) |
7584 | (compare:CC (match_dup 3) | |
7585 | (const_int 0)))] | |
7586 | "") | |
266eb58a | 7587 | |
dfbdccdb | 7588 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7589 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7590 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7591 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7592 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7593 | (const_int 0))) | |
9ebbca7d | 7594 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7595 | (match_dup 4))] |
683bdff7 | 7596 | "TARGET_64BIT" |
9ebbca7d | 7597 | "@ |
dfbdccdb | 7598 | %q4. %0,%1,%2 |
9ebbca7d GK |
7599 | #" |
7600 | [(set_attr "type" "compare") | |
7601 | (set_attr "length" "4,8")]) | |
7602 | ||
7603 | (define_split | |
e72247f4 | 7604 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7605 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7606 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7607 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7608 | (const_int 0))) |
75540af0 | 7609 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7610 | (match_dup 4))] |
9ebbca7d | 7611 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7612 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7613 | (set (match_dup 3) |
7614 | (compare:CC (match_dup 0) | |
7615 | (const_int 0)))] | |
7616 | "") | |
dfbdccdb | 7617 | \f |
1fd4e8c1 | 7618 | ;; Now define ways of moving data around. |
4697a36c MM |
7619 | |
7620 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7621 | ;; The output of this could be r0, but we make a very strong |
7622 | ;; preference for a base register because it will usually | |
7623 | ;; be needed there. | |
4697a36c | 7624 | (define_insn "elf_high" |
9ebbca7d | 7625 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7626 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7627 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7628 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7629 | |
7630 | (define_insn "elf_low" | |
9ebbca7d GK |
7631 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7632 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7633 | (match_operand 2 "" "")))] |
0ad91047 | 7634 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7635 | "@ |
7636 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7637 | {ai|addic} %0,%1,%K2") |
4697a36c | 7638 | |
ee890fe2 | 7639 | |
766a866c MM |
7640 | ;; Set up a register with a value from the GOT table |
7641 | ||
7642 | (define_expand "movsi_got" | |
52d3af72 | 7643 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7644 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
615158e2 | 7645 | (match_dup 2)] UNSPEC_MOVSI_GOT))] |
f607bc57 | 7646 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7647 | " |
7648 | { | |
38c1f2d7 MM |
7649 | if (GET_CODE (operands[1]) == CONST) |
7650 | { | |
7651 | rtx offset = const0_rtx; | |
7652 | HOST_WIDE_INT value; | |
7653 | ||
7654 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7655 | value = INTVAL (offset); | |
7656 | if (value != 0) | |
7657 | { | |
677a9668 | 7658 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7659 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7660 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7661 | DONE; | |
7662 | } | |
7663 | } | |
7664 | ||
c4c40373 | 7665 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7666 | }") |
7667 | ||
84f414bc | 7668 | (define_insn "*movsi_got_internal" |
52d3af72 | 7669 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d | 7670 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7671 | (match_operand:SI 2 "gpc_reg_operand" "b")] |
7672 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7673 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7674 | "{l|lwz} %0,%a1@got(%2)" |
7675 | [(set_attr "type" "load")]) | |
7676 | ||
b22b9b3e JL |
7677 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7678 | ;; didn't get allocated to a hard register. | |
6ae08853 | 7679 | (define_split |
75540af0 | 7680 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7681 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7682 | (match_operand:SI 2 "memory_operand" "")] |
7683 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7684 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7685 | && flag_pic == 1 |
7686 | && (reload_in_progress || reload_completed)" | |
7687 | [(set (match_dup 0) (match_dup 2)) | |
615158e2 JJ |
7688 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] |
7689 | UNSPEC_MOVSI_GOT))] | |
b22b9b3e JL |
7690 | "") |
7691 | ||
1fd4e8c1 RK |
7692 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7693 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7694 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7695 | ;; integers in the TOC. | |
7696 | (define_expand "movsi" | |
7697 | [(set (match_operand:SI 0 "general_operand" "") | |
7698 | (match_operand:SI 1 "any_operand" ""))] | |
7699 | "" | |
fb4d4348 | 7700 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7701 | |
ee890fe2 SS |
7702 | (define_insn "movsi_low" |
7703 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7704 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7705 | (match_operand 2 "" ""))))] |
7706 | "TARGET_MACHO && ! TARGET_64BIT" | |
7707 | "{l|lwz} %0,lo16(%2)(%1)" | |
7708 | [(set_attr "type" "load") | |
7709 | (set_attr "length" "4")]) | |
7710 | ||
acad7ed3 | 7711 | (define_insn "*movsi_internal1" |
165a5bad | 7712 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
a004eb82 | 7713 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] |
19d5775a RK |
7714 | "gpc_reg_operand (operands[0], SImode) |
7715 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7716 | "@ |
deb9225a | 7717 | mr %0,%1 |
b9442c72 | 7718 | {cal|la} %0,%a1 |
ca7f5001 RK |
7719 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7720 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7721 | {lil|li} %0,%1 |
802a0058 | 7722 | {liu|lis} %0,%v1 |
beaec479 | 7723 | # |
aee86b38 | 7724 | {cal|la} %0,%a1 |
1fd4e8c1 | 7725 | mf%1 %0 |
5c23c401 | 7726 | mt%0 %1 |
e76e75bb | 7727 | mt%0 %1 |
a004eb82 | 7728 | mt%0 %1 |
e34eaae5 | 7729 | {cror 0,0,0|nop}" |
02ca7595 | 7730 | [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") |
a004eb82 | 7731 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7732 | |
77fa0940 RK |
7733 | ;; Split a load of a large constant into the appropriate two-insn |
7734 | ;; sequence. | |
7735 | ||
7736 | (define_split | |
7737 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7738 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7739 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7740 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7741 | [(set (match_dup 0) | |
7742 | (match_dup 2)) | |
7743 | (set (match_dup 0) | |
7744 | (ior:SI (match_dup 0) | |
7745 | (match_dup 3)))] | |
7746 | " | |
af8cb5c5 DE |
7747 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
7748 | ||
7749 | if (tem == operands[0]) | |
7750 | DONE; | |
7751 | else | |
7752 | FAIL; | |
77fa0940 RK |
7753 | }") |
7754 | ||
acad7ed3 | 7755 | (define_insn "*movsi_internal2" |
bb84cb12 DE |
7756 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
7757 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r") | |
1fd4e8c1 | 7758 | (const_int 0))) |
bb84cb12 | 7759 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
4b8a63d6 | 7760 | "TARGET_32BIT" |
9ebbca7d | 7761 | "@ |
bb84cb12 | 7762 | {cmpi|cmpwi} %2,%0,0 |
9ebbca7d GK |
7763 | mr. %0,%1 |
7764 | #" | |
bb84cb12 DE |
7765 | [(set_attr "type" "cmp,compare,cmp") |
7766 | (set_attr "length" "4,4,8")]) | |
7767 | ||
9ebbca7d GK |
7768 | (define_split |
7769 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7770 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7771 | (const_int 0))) | |
7772 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
4b8a63d6 | 7773 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
7774 | [(set (match_dup 0) (match_dup 1)) |
7775 | (set (match_dup 2) | |
7776 | (compare:CC (match_dup 0) | |
7777 | (const_int 0)))] | |
7778 | "") | |
bb84cb12 | 7779 | \f |
1fd4e8c1 RK |
7780 | (define_expand "movhi" |
7781 | [(set (match_operand:HI 0 "general_operand" "") | |
7782 | (match_operand:HI 1 "any_operand" ""))] | |
7783 | "" | |
fb4d4348 | 7784 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 | 7785 | |
e34eaae5 | 7786 | (define_insn "*movhi_internal" |
fb81d7ce RK |
7787 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7788 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7789 | "gpc_reg_operand (operands[0], HImode) |
7790 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7791 | "@ |
deb9225a | 7792 | mr %0,%1 |
1fd4e8c1 RK |
7793 | lhz%U1%X1 %0,%1 |
7794 | sth%U0%X0 %1,%0 | |
19d5775a | 7795 | {lil|li} %0,%w1 |
1fd4e8c1 | 7796 | mf%1 %0 |
e76e75bb | 7797 | mt%0 %1 |
fb81d7ce | 7798 | mt%0 %1 |
e34eaae5 | 7799 | {cror 0,0,0|nop}" |
02ca7595 | 7800 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7801 | |
7802 | (define_expand "movqi" | |
7803 | [(set (match_operand:QI 0 "general_operand" "") | |
7804 | (match_operand:QI 1 "any_operand" ""))] | |
7805 | "" | |
fb4d4348 | 7806 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 | 7807 | |
e34eaae5 | 7808 | (define_insn "*movqi_internal" |
fb81d7ce RK |
7809 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7810 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7811 | "gpc_reg_operand (operands[0], QImode) |
7812 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7813 | "@ |
deb9225a | 7814 | mr %0,%1 |
1fd4e8c1 RK |
7815 | lbz%U1%X1 %0,%1 |
7816 | stb%U0%X0 %1,%0 | |
19d5775a | 7817 | {lil|li} %0,%1 |
1fd4e8c1 | 7818 | mf%1 %0 |
e76e75bb | 7819 | mt%0 %1 |
fb81d7ce | 7820 | mt%0 %1 |
e34eaae5 | 7821 | {cror 0,0,0|nop}" |
02ca7595 | 7822 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7823 | \f |
7824 | ;; Here is how to move condition codes around. When we store CC data in | |
7825 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7826 | ;; This lets us not shift in the most common case of CR0. | |
7827 | (define_expand "movcc" | |
7828 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7829 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7830 | "" | |
7831 | "") | |
7832 | ||
a65c591c | 7833 | (define_insn "*movcc_internal1" |
b54cf83a DE |
7834 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") |
7835 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] | |
1fd4e8c1 RK |
7836 | "register_operand (operands[0], CCmode) |
7837 | || register_operand (operands[1], CCmode)" | |
7838 | "@ | |
7839 | mcrf %0,%1 | |
7840 | mtcrf 128,%1 | |
ca7f5001 | 7841 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
2c4a9cff DE |
7842 | mfcr %0%Q1 |
7843 | mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 | |
deb9225a | 7844 | mr %0,%1 |
b54cf83a | 7845 | mf%1 %0 |
b991a865 GK |
7846 | mt%0 %1 |
7847 | mt%0 %1 | |
ca7f5001 RK |
7848 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7849 | {st%U0%U1|stw%U0%U1} %1,%0" | |
2c4a9cff DE |
7850 | [(set (attr "type") |
7851 | (cond [(eq_attr "alternative" "0") | |
7852 | (const_string "cr_logical") | |
7853 | (eq_attr "alternative" "1,2") | |
7854 | (const_string "mtcr") | |
7855 | (eq_attr "alternative" "5,7") | |
7856 | (const_string "integer") | |
7857 | (eq_attr "alternative" "6") | |
7858 | (const_string "mfjmpr") | |
7859 | (eq_attr "alternative" "8") | |
7860 | (const_string "mtjmpr") | |
7861 | (eq_attr "alternative" "9") | |
7862 | (const_string "load") | |
7863 | (eq_attr "alternative" "10") | |
7864 | (const_string "store") | |
7865 | (ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
7866 | (const_string "mfcrf") | |
7867 | ] | |
7868 | (const_string "mfcr"))) | |
b991a865 | 7869 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7870 | \f |
e52e05ca MM |
7871 | ;; For floating-point, we normally deal with the floating-point registers |
7872 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7873 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7874 | ;; value is a simple constant or already in memory, we deal with this by | |
7875 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7876 | (define_expand "movsf" |
7877 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7878 | (match_operand:SF 1 "any_operand" ""))] | |
7879 | "" | |
fb4d4348 | 7880 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7881 | |
1fd4e8c1 | 7882 | (define_split |
cd2b37d9 | 7883 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7884 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7885 | "reload_completed |
5ae4759c MM |
7886 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7887 | || (GET_CODE (operands[0]) == SUBREG | |
7888 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7889 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7890 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7891 | " |
7892 | { | |
7893 | long l; | |
7894 | REAL_VALUE_TYPE rv; | |
7895 | ||
7896 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7897 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7898 | |
f99f88e0 DE |
7899 | if (! TARGET_POWERPC64) |
7900 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7901 | else | |
7902 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7903 | |
2496c7bd | 7904 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7905 | }") |
7906 | ||
c4c40373 | 7907 | (define_insn "*movsf_hardfloat" |
ae6669e7 DJ |
7908 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r") |
7909 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] | |
d14a6d05 | 7910 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7911 | || gpc_reg_operand (operands[1], SFmode)) |
7912 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 7913 | "@ |
f99f88e0 DE |
7914 | mr %0,%1 |
7915 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7916 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7917 | fmr %0,%1 |
7918 | lfs%U1%X1 %0,%1 | |
c4c40373 | 7919 | stfs%U0%X0 %1,%0 |
b991a865 GK |
7920 | mt%0 %1 |
7921 | mt%0 %1 | |
7922 | mf%1 %0 | |
e0740893 | 7923 | {cror 0,0,0|nop} |
c4c40373 MM |
7924 | # |
7925 | #" | |
ae6669e7 DJ |
7926 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*") |
7927 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7928 | |
c4c40373 | 7929 | (define_insn "*movsf_softfloat" |
dd0fbae2 MK |
7930 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") |
7931 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
d14a6d05 | 7932 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7933 | || gpc_reg_operand (operands[1], SFmode)) |
7934 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
7935 | "@ |
7936 | mr %0,%1 | |
b991a865 GK |
7937 | mt%0 %1 |
7938 | mt%0 %1 | |
7939 | mf%1 %0 | |
d14a6d05 MM |
7940 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7941 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7942 | {lil|li} %0,%1 | |
802a0058 | 7943 | {liu|lis} %0,%v1 |
aee86b38 | 7944 | {cal|la} %0,%a1 |
c4c40373 | 7945 | # |
dd0fbae2 MK |
7946 | # |
7947 | {cror 0,0,0|nop}" | |
7948 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") | |
7949 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
d14a6d05 | 7950 | |
1fd4e8c1 RK |
7951 | \f |
7952 | (define_expand "movdf" | |
7953 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7954 | (match_operand:DF 1 "any_operand" ""))] | |
7955 | "" | |
fb4d4348 | 7956 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7957 | |
7958 | (define_split | |
cd2b37d9 | 7959 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7960 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7961 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7962 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7963 | || (GET_CODE (operands[0]) == SUBREG | |
7964 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7965 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7966 | [(set (match_dup 2) (match_dup 4)) |
7967 | (set (match_dup 3) (match_dup 1))] | |
7968 | " | |
7969 | { | |
5ae4759c | 7970 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7971 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7972 | ||
5ae4759c MM |
7973 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7974 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7975 | #if HOST_BITS_PER_WIDE_INT == 32 |
7976 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7977 | #else | |
7978 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 7979 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 7980 | #endif |
c4c40373 MM |
7981 | }") |
7982 | ||
c4c40373 MM |
7983 | (define_split |
7984 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7985 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7986 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7987 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7988 | || (GET_CODE (operands[0]) == SUBREG | |
7989 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7990 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7991 | [(set (match_dup 2) (match_dup 4)) |
7992 | (set (match_dup 3) (match_dup 5))] | |
7993 | " | |
7994 | { | |
5ae4759c | 7995 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7996 | long l[2]; |
7997 | REAL_VALUE_TYPE rv; | |
7998 | ||
7999 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8000 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8001 | ||
5ae4759c MM |
8002 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
8003 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
8004 | operands[4] = gen_int_mode (l[endian], SImode); |
8005 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
8006 | }") |
8007 | ||
efc08378 DE |
8008 | (define_split |
8009 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 8010 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 8011 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8012 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8013 | || (GET_CODE (operands[0]) == SUBREG | |
8014 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8015 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 8016 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 8017 | " |
a260abc9 DE |
8018 | { |
8019 | int endian = (WORDS_BIG_ENDIAN == 0); | |
8020 | long l[2]; | |
8021 | REAL_VALUE_TYPE rv; | |
4977bab6 | 8022 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 8023 | HOST_WIDE_INT val; |
4977bab6 | 8024 | #endif |
a260abc9 DE |
8025 | |
8026 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8027 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8028 | ||
8029 | operands[2] = gen_lowpart (DImode, operands[0]); | |
8030 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 8031 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
8032 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
8033 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 8034 | |
f5264b52 | 8035 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 8036 | #else |
a260abc9 | 8037 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 8038 | #endif |
a260abc9 | 8039 | }") |
efc08378 | 8040 | |
4eae5fe1 | 8041 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 8042 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
8043 | ;; a non-offsettable memref, but also it is less efficient than loading |
8044 | ;; the constant into an FP register, since it will probably be used there. | |
8045 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
8046 | ;; of handling these non-offsettable values. | |
c4c40373 | 8047 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
8048 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
8049 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 8050 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8051 | && (gpc_reg_operand (operands[0], DFmode) |
8052 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
8053 | "* |
8054 | { | |
8055 | switch (which_alternative) | |
8056 | { | |
a260abc9 | 8057 | default: |
a6c2a102 | 8058 | abort (); |
e7113111 RK |
8059 | case 0: |
8060 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
8061 | the first register operand 0 is the same as the second register |
8062 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 8063 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 8064 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 8065 | else |
deb9225a | 8066 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 8067 | case 1: |
819e019c EC |
8068 | if (GET_CODE (operands[1]) == MEM |
8069 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0), | |
8070 | reload_completed || reload_in_progress) | |
8071 | || GET_CODE (XEXP (operands[1], 0)) == REG | |
8072 | || GET_CODE (XEXP (operands[1], 0)) == LO_SUM | |
69f51a21 | 8073 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC |
819e019c | 8074 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) |
000034eb DE |
8075 | { |
8076 | /* If the low-address word is used in the address, we must load | |
8077 | it last. Otherwise, load it first. Note that we cannot have | |
8078 | auto-increment in that case since the address register is | |
8079 | known to be dead. */ | |
8080 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8081 | operands[1], 0)) | |
8082 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
8083 | else | |
8084 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8085 | } | |
e7113111 | 8086 | else |
000034eb DE |
8087 | { |
8088 | rtx addreg; | |
8089 | ||
000034eb DE |
8090 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
8091 | if (refers_to_regno_p (REGNO (operands[0]), | |
8092 | REGNO (operands[0]) + 1, | |
8093 | operands[1], 0)) | |
8094 | { | |
8095 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 8096 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 8097 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 8098 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
8099 | } |
8100 | else | |
8101 | { | |
2b97222d | 8102 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 8103 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8104 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
8105 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8106 | return \"\"; | |
8107 | } | |
8108 | } | |
e7113111 | 8109 | case 2: |
819e019c EC |
8110 | if (GET_CODE (operands[0]) == MEM |
8111 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0), | |
8112 | reload_completed || reload_in_progress) | |
8113 | || GET_CODE (XEXP (operands[0], 0)) == REG | |
8114 | || GET_CODE (XEXP (operands[0], 0)) == LO_SUM | |
69f51a21 | 8115 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC |
819e019c | 8116 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)) |
000034eb DE |
8117 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8118 | else | |
8119 | { | |
8120 | rtx addreg; | |
8121 | ||
000034eb | 8122 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8123 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8124 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8125 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8126 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8127 | return \"\"; | |
8128 | } | |
e7113111 | 8129 | case 3: |
914a7297 | 8130 | return \"fmr %0,%1\"; |
e7113111 | 8131 | case 4: |
914a7297 | 8132 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 8133 | case 5: |
914a7297 | 8134 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 8135 | case 6: |
c4c40373 | 8136 | case 7: |
c4c40373 | 8137 | case 8: |
914a7297 | 8138 | return \"#\"; |
e7113111 RK |
8139 | } |
8140 | }" | |
943c15ed | 8141 | [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") |
914a7297 | 8142 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) |
51b8fc2c | 8143 | |
c4c40373 | 8144 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8145 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8146 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
7a2f7870 | 8147 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) |
52d3af72 DE |
8148 | && (gpc_reg_operand (operands[0], DFmode) |
8149 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8150 | "* |
8151 | { | |
8152 | switch (which_alternative) | |
8153 | { | |
a260abc9 | 8154 | default: |
a6c2a102 | 8155 | abort (); |
dc4f83ca MM |
8156 | case 0: |
8157 | /* We normally copy the low-numbered register first. However, if | |
8158 | the first register operand 0 is the same as the second register of | |
8159 | operand 1, we must copy in the opposite order. */ | |
8160 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8161 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8162 | else | |
8163 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8164 | case 1: | |
3cb999d8 DE |
8165 | /* If the low-address word is used in the address, we must load |
8166 | it last. Otherwise, load it first. Note that we cannot have | |
8167 | auto-increment in that case since the address register is | |
8168 | known to be dead. */ | |
dc4f83ca | 8169 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8170 | operands[1], 0)) |
dc4f83ca MM |
8171 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8172 | else | |
8173 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8174 | case 2: | |
8175 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8176 | case 3: | |
c4c40373 MM |
8177 | case 4: |
8178 | case 5: | |
dc4f83ca MM |
8179 | return \"#\"; |
8180 | } | |
8181 | }" | |
943c15ed | 8182 | [(set_attr "type" "two,load,store,*,*,*") |
c4c40373 | 8183 | (set_attr "length" "8,8,8,8,12,16")]) |
dc4f83ca | 8184 | |
d2288d5d HP |
8185 | ; ld/std require word-aligned displacements -> 'Y' constraint. |
8186 | ; List Y->r and r->Y before r->r for reload. | |
c4c40373 | 8187 | (define_insn "*movdf_hardfloat64" |
ae6669e7 DJ |
8188 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r") |
8189 | (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] | |
a3170dc6 | 8190 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8191 | && (gpc_reg_operand (operands[0], DFmode) |
8192 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8193 | "@ |
96bb8ed3 | 8194 | std%U0%X0 %1,%0 |
3364872d FJ |
8195 | ld%U1%X1 %0,%1 |
8196 | mr %0,%1 | |
3d5570cb | 8197 | fmr %0,%1 |
f63184ac | 8198 | lfd%U1%X1 %0,%1 |
914a7297 DE |
8199 | stfd%U0%X0 %1,%0 |
8200 | mt%0 %1 | |
8201 | mf%1 %0 | |
e0740893 | 8202 | {cror 0,0,0|nop} |
914a7297 DE |
8203 | # |
8204 | # | |
8205 | #" | |
ae6669e7 DJ |
8206 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*") |
8207 | (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 8208 | |
c4c40373 | 8209 | (define_insn "*movdf_softfloat64" |
d2288d5d HP |
8210 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") |
8211 | (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] | |
a3170dc6 | 8212 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8213 | && (gpc_reg_operand (operands[0], DFmode) |
8214 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca | 8215 | "@ |
d2288d5d HP |
8216 | ld%U1%X1 %0,%1 |
8217 | std%U0%X0 %1,%0 | |
dc4f83ca | 8218 | mr %0,%1 |
914a7297 DE |
8219 | mt%0 %1 |
8220 | mf%1 %0 | |
c4c40373 MM |
8221 | # |
8222 | # | |
e2d0915c | 8223 | # |
e0740893 | 8224 | {cror 0,0,0|nop}" |
d2288d5d | 8225 | [(set_attr "type" "load,store,*,*,*,*,*,*,*") |
e2d0915c | 8226 | (set_attr "length" "4,4,4,4,4,8,12,16,4")]) |
1fd4e8c1 | 8227 | \f |
06f4e019 DE |
8228 | (define_expand "movtf" |
8229 | [(set (match_operand:TF 0 "general_operand" "") | |
8230 | (match_operand:TF 1 "any_operand" ""))] | |
39e63627 GK |
8231 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8232 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8233 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
8234 | ||
a9baceb1 GK |
8235 | ; It's important to list the o->f and f->o moves before f->f because |
8236 | ; otherwise reload, given m->f, will try to pick f->f and reload it, | |
409f61cd | 8237 | ; which doesn't make progress. Likewise r->Y must be before r->r. |
a9baceb1 | 8238 | (define_insn_and_split "*movtf_internal" |
409f61cd AM |
8239 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r") |
8240 | (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))] | |
39e63627 GK |
8241 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8242 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
8243 | && (gpc_reg_operand (operands[0], TFmode) |
8244 | || gpc_reg_operand (operands[1], TFmode))" | |
a9baceb1 | 8245 | "#" |
ecb62ae7 | 8246 | "&& reload_completed" |
a9baceb1 GK |
8247 | [(pc)] |
8248 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } | |
112ccb83 | 8249 | [(set_attr "length" "8,8,8,20,20,16")]) |
06f4e019 | 8250 | |
ecb62ae7 GK |
8251 | (define_expand "extenddftf2" |
8252 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8253 | (float_extend:TF (match_operand:DF 1 "input_operand" ""))) | |
8254 | (use (match_dup 2))])] | |
39e63627 GK |
8255 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8256 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8257 | { |
ecb62ae7 GK |
8258 | operands[2] = CONST0_RTX (DFmode); |
8259 | }) | |
06f4e019 | 8260 | |
ecb62ae7 GK |
8261 | (define_insn_and_split "*extenddftf2_internal" |
8262 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") | |
8263 | (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) | |
8264 | (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))] | |
39e63627 GK |
8265 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8266 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8267 | "#" |
8268 | "&& reload_completed" | |
8269 | [(pc)] | |
06f4e019 | 8270 | { |
ecb62ae7 GK |
8271 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; |
8272 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
8273 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), | |
8274 | operands[1]); | |
8275 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), | |
8276 | operands[2]); | |
8277 | DONE; | |
6ae08853 | 8278 | }) |
ecb62ae7 GK |
8279 | |
8280 | (define_expand "extendsftf2" | |
8281 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8282 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
8283 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8284 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8285 | { | |
8286 | rtx tmp = gen_reg_rtx (DFmode); | |
8287 | emit_insn (gen_extendsfdf2 (tmp, operands[1])); | |
8288 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8289 | DONE; | |
8290 | }) | |
06f4e019 DE |
8291 | |
8292 | (define_insn "trunctfdf2" | |
8293 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8294 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8295 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8296 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8297 | "fadd %0,%1,%L1" |
8298 | [(set_attr "type" "fp") | |
ecb62ae7 | 8299 | (set_attr "length" "4")]) |
06f4e019 DE |
8300 | |
8301 | (define_insn_and_split "trunctfsf2" | |
8302 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
8303 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8304 | (clobber (match_scratch:DF 2 "=f"))] | |
39e63627 GK |
8305 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8306 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8307 | "#" |
ea112fc4 | 8308 | "&& reload_completed" |
06f4e019 DE |
8309 | [(set (match_dup 2) |
8310 | (float_truncate:DF (match_dup 1))) | |
8311 | (set (match_dup 0) | |
8312 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 8313 | "") |
06f4e019 | 8314 | |
0c90aa3c | 8315 | (define_expand "floatsitf2" |
ea112fc4 | 8316 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
0c90aa3c | 8317 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))] |
39e63627 GK |
8318 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8319 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
0c90aa3c GK |
8320 | { |
8321 | rtx tmp = gen_reg_rtx (DFmode); | |
8322 | expand_float (tmp, operands[1], false); | |
8323 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8324 | DONE; | |
8325 | }) | |
06f4e019 | 8326 | |
ecb62ae7 GK |
8327 | ; fadd, but rounding towards zero. |
8328 | ; This is probably not the optimal code sequence. | |
8329 | (define_insn "fix_trunc_helper" | |
8330 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8331 | (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] | |
8332 | UNSPEC_FIX_TRUNC_TF)) | |
8333 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] | |
8334 | "TARGET_HARD_FLOAT && TARGET_FPRS" | |
8335 | "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" | |
8336 | [(set_attr "type" "fp") | |
8337 | (set_attr "length" "20")]) | |
8338 | ||
0c90aa3c | 8339 | (define_expand "fix_trunctfsi2" |
ecb62ae7 GK |
8340 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
8341 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) | |
8342 | (clobber (match_dup 2)) | |
8343 | (clobber (match_dup 3)) | |
8344 | (clobber (match_dup 4)) | |
8345 | (clobber (match_dup 5))])] | |
8346 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8347 | && (TARGET_POWER2 || TARGET_POWERPC) | |
8348 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8349 | { | |
8350 | operands[2] = gen_reg_rtx (DFmode); | |
8351 | operands[3] = gen_reg_rtx (DFmode); | |
8352 | operands[4] = gen_reg_rtx (DImode); | |
8353 | operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
8354 | }) | |
8355 | ||
8356 | (define_insn_and_split "*fix_trunctfsi2_internal" | |
61c07d3c | 8357 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ecb62ae7 GK |
8358 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8359 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) | |
8360 | (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) | |
8361 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) | |
8362 | (clobber (match_operand:DI 5 "memory_operand" "=o"))] | |
39e63627 GK |
8363 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8364 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8365 | "#" |
8366 | "&& reload_completed" | |
8367 | [(pc)] | |
0c90aa3c | 8368 | { |
ecb62ae7 GK |
8369 | rtx lowword; |
8370 | emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); | |
8371 | ||
8372 | if (GET_CODE (operands[5]) != MEM) | |
8373 | abort(); | |
8374 | lowword = XEXP (operands[5], 0); | |
8375 | if (WORDS_BIG_ENDIAN) | |
8376 | lowword = plus_constant (lowword, 4); | |
8377 | ||
8378 | emit_insn (gen_fctiwz (operands[4], operands[2])); | |
8379 | emit_move_insn (operands[5], operands[4]); | |
8380 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
0c90aa3c GK |
8381 | DONE; |
8382 | }) | |
06f4e019 DE |
8383 | |
8384 | (define_insn "negtf2" | |
8385 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8386 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8387 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8388 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8389 | "* |
8390 | { | |
8391 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8392 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8393 | else | |
8394 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8395 | }" | |
8396 | [(set_attr "type" "fp") | |
8397 | (set_attr "length" "8")]) | |
8398 | ||
1a402dc1 | 8399 | (define_expand "abstf2" |
06f4e019 DE |
8400 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8401 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8402 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8403 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8404 | " |
06f4e019 | 8405 | { |
1a402dc1 AM |
8406 | rtx label = gen_label_rtx (); |
8407 | emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); | |
8408 | emit_label (label); | |
8409 | DONE; | |
8410 | }") | |
06f4e019 | 8411 | |
1a402dc1 | 8412 | (define_expand "abstf2_internal" |
06f4e019 | 8413 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
1a402dc1 AM |
8414 | (match_operand:TF 1 "gpc_reg_operand" "f")) |
8415 | (set (match_dup 3) (match_dup 5)) | |
8416 | (set (match_dup 5) (abs:DF (match_dup 5))) | |
8417 | (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) | |
8418 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
8419 | (label_ref (match_operand 2 "" "")) | |
8420 | (pc))) | |
8421 | (set (match_dup 6) (neg:DF (match_dup 6)))] | |
39e63627 GK |
8422 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8423 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8424 | " |
06f4e019 | 8425 | { |
1a402dc1 AM |
8426 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); |
8427 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
8428 | operands[3] = gen_reg_rtx (DFmode); | |
8429 | operands[4] = gen_reg_rtx (CCFPmode); | |
8430 | operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
8431 | operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
8432 | }") | |
06f4e019 | 8433 | \f |
1fd4e8c1 RK |
8434 | ;; Next come the multi-word integer load and store and the load and store |
8435 | ;; multiple insns. | |
8436 | (define_expand "movdi" | |
8437 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8438 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 8439 | "" |
fb4d4348 | 8440 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 8441 | |
112ccb83 GK |
8442 | ; List r->r after r->"o<>", otherwise reload will try to reload a |
8443 | ; non-offsettable address by using r->r which won't make progress. | |
acad7ed3 | 8444 | (define_insn "*movdi_internal32" |
343f6bbf | 8445 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r") |
112ccb83 | 8446 | (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] |
a260abc9 | 8447 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8448 | && (gpc_reg_operand (operands[0], DImode) |
8449 | || gpc_reg_operand (operands[1], DImode))" | |
112ccb83 GK |
8450 | "@ |
8451 | # | |
8452 | # | |
8453 | # | |
8454 | fmr %0,%1 | |
8455 | lfd%U1%X1 %0,%1 | |
8456 | stfd%U0%X0 %1,%0 | |
8457 | #" | |
8458 | [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")]) | |
4e74d8ec MM |
8459 | |
8460 | (define_split | |
8461 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8462 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8463 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8464 | [(set (match_dup 2) (match_dup 4)) |
8465 | (set (match_dup 3) (match_dup 1))] | |
8466 | " | |
8467 | { | |
5f59ecb7 | 8468 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8469 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8470 | DImode); | |
8471 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8472 | DImode); | |
75d39459 | 8473 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8474 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8475 | #else |
5f59ecb7 | 8476 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8477 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8478 | #endif |
4e74d8ec MM |
8479 | }") |
8480 | ||
3a1f863f DE |
8481 | (define_split |
8482 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8483 | (match_operand:DI 1 "input_operand" ""))] | |
6ae08853 | 8484 | "reload_completed && !TARGET_POWERPC64 |
3a1f863f | 8485 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8486 | [(pc)] |
8487 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
3a1f863f | 8488 | |
acad7ed3 | 8489 | (define_insn "*movdi_internal64" |
343f6bbf | 8490 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h") |
9615f239 | 8491 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8492 | "TARGET_POWERPC64 |
4e74d8ec MM |
8493 | && (gpc_reg_operand (operands[0], DImode) |
8494 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8495 | "@ |
3d5570cb RK |
8496 | mr %0,%1 |
8497 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8498 | std%U0%X0 %1,%0 |
3d5570cb | 8499 | li %0,%1 |
802a0058 | 8500 | lis %0,%v1 |
e6ca2c17 | 8501 | # |
aee86b38 | 8502 | {cal|la} %0,%a1 |
3d5570cb RK |
8503 | fmr %0,%1 |
8504 | lfd%U1%X1 %0,%1 | |
8505 | stfd%U0%X0 %1,%0 | |
8506 | mf%1 %0 | |
08075ead | 8507 | mt%0 %1 |
e34eaae5 | 8508 | {cror 0,0,0|nop}" |
02ca7595 | 8509 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") |
e6ca2c17 DE |
8510 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8511 | ||
5f59ecb7 | 8512 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8513 | (define_insn "" |
8514 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8515 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8516 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8517 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8518 | && num_insns_constant (operands[1], DImode) == 1" |
8519 | "* | |
8520 | { | |
8521 | return ((unsigned HOST_WIDE_INT) | |
8522 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8523 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8524 | }") | |
8525 | ||
a260abc9 DE |
8526 | ;; Generate all one-bits and clear left or right. |
8527 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8528 | (define_split | |
8529 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8530 | (match_operand:DI 1 "mask64_operand" ""))] | |
8531 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8532 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8533 | (set (match_dup 0) |
a260abc9 DE |
8534 | (and:DI (rotate:DI (match_dup 0) |
8535 | (const_int 0)) | |
8536 | (match_dup 1)))] | |
8537 | "") | |
8538 | ||
8539 | ;; Split a load of a large constant into the appropriate five-instruction | |
8540 | ;; sequence. Handle anything in a constant number of insns. | |
8541 | ;; When non-easy constants can go in the TOC, this should use | |
8542 | ;; easy_fp_constant predicate. | |
8543 | (define_split | |
8544 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8545 | (match_operand:DI 1 "const_int_operand" ""))] |
8546 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8547 | [(set (match_dup 0) (match_dup 2)) | |
8548 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8549 | " |
2bfcf297 DB |
8550 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8551 | ||
8552 | if (tem == operands[0]) | |
8553 | DONE; | |
e8d791dd | 8554 | else |
2bfcf297 | 8555 | FAIL; |
5f59ecb7 | 8556 | }") |
e6ca2c17 | 8557 | |
5f59ecb7 DE |
8558 | (define_split |
8559 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8560 | (match_operand:DI 1 "const_double_operand" ""))] |
8561 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8562 | [(set (match_dup 0) (match_dup 2)) | |
8563 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8564 | " |
2bfcf297 DB |
8565 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8566 | ||
8567 | if (tem == operands[0]) | |
8568 | DONE; | |
8569 | else | |
8570 | FAIL; | |
e6ca2c17 | 8571 | }") |
08075ead | 8572 | |
acad7ed3 | 8573 | (define_insn "*movdi_internal2" |
bb84cb12 DE |
8574 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
8575 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r") | |
08075ead | 8576 | (const_int 0))) |
bb84cb12 | 8577 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
683bdff7 | 8578 | "TARGET_64BIT" |
9ebbca7d | 8579 | "@ |
bb84cb12 | 8580 | cmpdi %2,%0,0 |
9ebbca7d GK |
8581 | mr. %0,%1 |
8582 | #" | |
bb84cb12 DE |
8583 | [(set_attr "type" "cmp,compare,cmp") |
8584 | (set_attr "length" "4,4,8")]) | |
acad7ed3 | 8585 | |
9ebbca7d GK |
8586 | (define_split |
8587 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8588 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8589 | (const_int 0))) | |
8590 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8591 | "TARGET_POWERPC64 && reload_completed" | |
8592 | [(set (match_dup 0) (match_dup 1)) | |
8593 | (set (match_dup 2) | |
8594 | (compare:CC (match_dup 0) | |
8595 | (const_int 0)))] | |
8596 | "") | |
acad7ed3 | 8597 | \f |
1fd4e8c1 RK |
8598 | ;; TImode is similar, except that we usually want to compute the address into |
8599 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8600 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8601 | (define_expand "movti" |
8602 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8603 | (match_operand:TI 1 "general_operand" "")) | |
8604 | (clobber (scratch:SI))])] | |
3a1f863f | 8605 | "" |
fb4d4348 | 8606 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8607 | |
8608 | ;; We say that MQ is clobbered in the last alternative because the first | |
8609 | ;; alternative would never get used otherwise since it would need a reload | |
8610 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8611 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8612 | ;; giving the SCRATCH mq. | |
3a1f863f | 8613 | |
a260abc9 | 8614 | (define_insn "*movti_power" |
7f514158 AM |
8615 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r") |
8616 | (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n")) | |
8617 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))] | |
6ae08853 | 8618 | "TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8619 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8620 | "* |
8621 | { | |
8622 | switch (which_alternative) | |
8623 | { | |
dc4f83ca MM |
8624 | default: |
8625 | abort (); | |
8626 | ||
1fd4e8c1 | 8627 | case 0: |
3a1f863f DE |
8628 | if (TARGET_STRING) |
8629 | return \"{stsi|stswi} %1,%P0,16\"; | |
1fd4e8c1 | 8630 | case 1: |
1fd4e8c1 | 8631 | case 2: |
3a1f863f | 8632 | return \"#\"; |
1fd4e8c1 RK |
8633 | case 3: |
8634 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8635 | fall through to generating four loads. */ | |
e876481c DE |
8636 | if (TARGET_STRING |
8637 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8638 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8639 | /* ... fall through ... */ |
1fd4e8c1 | 8640 | case 4: |
7f514158 | 8641 | case 5: |
3a1f863f | 8642 | return \"#\"; |
1fd4e8c1 RK |
8643 | } |
8644 | }" | |
7f514158 | 8645 | [(set_attr "type" "store,store,*,load,load,*")]) |
51b8fc2c | 8646 | |
a260abc9 | 8647 | (define_insn "*movti_string" |
7f514158 AM |
8648 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r") |
8649 | (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))] | |
3a1f863f | 8650 | "! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8651 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8652 | "* | |
8653 | { | |
8654 | switch (which_alternative) | |
8655 | { | |
8656 | default: | |
8657 | abort (); | |
dc4f83ca | 8658 | case 0: |
3a1f863f DE |
8659 | if (TARGET_STRING) |
8660 | return \"{stsi|stswi} %1,%P0,16\"; | |
dc4f83ca | 8661 | case 1: |
cd1d3445 | 8662 | case 2: |
3a1f863f | 8663 | return \"#\"; |
cd1d3445 DE |
8664 | case 3: |
8665 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8666 | fall through to generating four loads. */ | |
6ae08853 | 8667 | if (TARGET_STRING |
3a1f863f | 8668 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) |
cd1d3445 DE |
8669 | return \"{lsi|lswi} %0,%P1,16\"; |
8670 | /* ... fall through ... */ | |
8671 | case 4: | |
7f514158 | 8672 | case 5: |
3a1f863f | 8673 | return \"#\"; |
dc4f83ca MM |
8674 | } |
8675 | }" | |
7f514158 | 8676 | [(set_attr "type" "store,store,*,load,load,*")]) |
dc4f83ca | 8677 | |
a260abc9 | 8678 | (define_insn "*movti_ppc64" |
112ccb83 GK |
8679 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") |
8680 | (match_operand:TI 1 "input_operand" "r,r,m"))] | |
51b8fc2c RK |
8681 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) |
8682 | || gpc_reg_operand (operands[1], TImode))" | |
112ccb83 | 8683 | "#" |
3a1f863f DE |
8684 | [(set_attr "type" "*,load,store")]) |
8685 | ||
7f514158 AM |
8686 | (define_split |
8687 | [(set (match_operand:TI 0 "gpc_reg_operand" "") | |
8688 | (match_operand:TI 1 "const_double_operand" ""))] | |
8689 | "TARGET_POWERPC64" | |
8690 | [(set (match_dup 2) (match_dup 4)) | |
8691 | (set (match_dup 3) (match_dup 5))] | |
8692 | " | |
8693 | { | |
8694 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, | |
8695 | TImode); | |
8696 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8697 | TImode); | |
8698 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
8699 | { | |
8700 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8701 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8702 | } | |
8703 | else if (GET_CODE (operands[1]) == CONST_INT) | |
8704 | { | |
8705 | operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); | |
8706 | operands[5] = operands[1]; | |
8707 | } | |
8708 | else | |
8709 | FAIL; | |
8710 | }") | |
8711 | ||
3a1f863f DE |
8712 | (define_split |
8713 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
8714 | (match_operand:TI 1 "input_operand" ""))] | |
a9baceb1 | 8715 | "reload_completed |
3a1f863f | 8716 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8717 | [(pc)] |
8718 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
1fd4e8c1 RK |
8719 | \f |
8720 | (define_expand "load_multiple" | |
2f622005 RK |
8721 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8722 | (match_operand:SI 1 "" "")) | |
8723 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8724 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8725 | " |
8726 | { | |
8727 | int regno; | |
8728 | int count; | |
792760b9 | 8729 | rtx op1; |
1fd4e8c1 RK |
8730 | int i; |
8731 | ||
8732 | /* Support only loading a constant number of fixed-point registers from | |
8733 | memory and only bother with this if more than two; the machine | |
8734 | doesn't support more than eight. */ | |
8735 | if (GET_CODE (operands[2]) != CONST_INT | |
8736 | || INTVAL (operands[2]) <= 2 | |
8737 | || INTVAL (operands[2]) > 8 | |
8738 | || GET_CODE (operands[1]) != MEM | |
8739 | || GET_CODE (operands[0]) != REG | |
8740 | || REGNO (operands[0]) >= 32) | |
8741 | FAIL; | |
8742 | ||
8743 | count = INTVAL (operands[2]); | |
8744 | regno = REGNO (operands[0]); | |
8745 | ||
39403d82 | 8746 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8747 | op1 = replace_equiv_address (operands[1], |
8748 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8749 | |
8750 | for (i = 0; i < count; i++) | |
8751 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8752 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 8753 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8754 | }") |
8755 | ||
9caa3eb2 | 8756 | (define_insn "*ldmsi8" |
1fd4e8c1 | 8757 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
8758 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
8759 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8760 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8761 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8762 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8763 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8764 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8765 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8766 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8767 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8768 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8769 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8770 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8771 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
8772 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
8773 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
8774 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 8775 | "* |
9caa3eb2 DE |
8776 | { return rs6000_output_load_multiple (operands); }" |
8777 | [(set_attr "type" "load") | |
8778 | (set_attr "length" "32")]) | |
1fd4e8c1 | 8779 | |
9caa3eb2 DE |
8780 | (define_insn "*ldmsi7" |
8781 | [(match_parallel 0 "load_multiple_operation" | |
8782 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8783 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8784 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8785 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8786 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8787 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8788 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8789 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8790 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8791 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8792 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8793 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8794 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8795 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
8796 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
8797 | "* | |
8798 | { return rs6000_output_load_multiple (operands); }" | |
8799 | [(set_attr "type" "load") | |
8800 | (set_attr "length" "32")]) | |
8801 | ||
8802 | (define_insn "*ldmsi6" | |
8803 | [(match_parallel 0 "load_multiple_operation" | |
8804 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8805 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8806 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8807 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8808 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8809 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8810 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8811 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8812 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8813 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8814 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8815 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
8816 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
8817 | "* | |
8818 | { return rs6000_output_load_multiple (operands); }" | |
8819 | [(set_attr "type" "load") | |
8820 | (set_attr "length" "32")]) | |
8821 | ||
8822 | (define_insn "*ldmsi5" | |
8823 | [(match_parallel 0 "load_multiple_operation" | |
8824 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8825 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8826 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8827 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8828 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8829 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8830 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8831 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8832 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8833 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
8834 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
8835 | "* | |
8836 | { return rs6000_output_load_multiple (operands); }" | |
8837 | [(set_attr "type" "load") | |
8838 | (set_attr "length" "32")]) | |
8839 | ||
8840 | (define_insn "*ldmsi4" | |
8841 | [(match_parallel 0 "load_multiple_operation" | |
8842 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8843 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8844 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8845 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8846 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8847 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8848 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8849 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
8850 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
8851 | "* | |
8852 | { return rs6000_output_load_multiple (operands); }" | |
8853 | [(set_attr "type" "load") | |
8854 | (set_attr "length" "32")]) | |
8855 | ||
8856 | (define_insn "*ldmsi3" | |
8857 | [(match_parallel 0 "load_multiple_operation" | |
8858 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8859 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8860 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8861 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8862 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8863 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
8864 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
8865 | "* | |
8866 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 8867 | [(set_attr "type" "load") |
e82ee4cc | 8868 | (set_attr "length" "32")]) |
b19003d8 | 8869 | |
1fd4e8c1 | 8870 | (define_expand "store_multiple" |
2f622005 RK |
8871 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8872 | (match_operand:SI 1 "" "")) | |
8873 | (clobber (scratch:SI)) | |
8874 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8875 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8876 | " |
8877 | { | |
8878 | int regno; | |
8879 | int count; | |
8880 | rtx to; | |
792760b9 | 8881 | rtx op0; |
1fd4e8c1 RK |
8882 | int i; |
8883 | ||
8884 | /* Support only storing a constant number of fixed-point registers to | |
8885 | memory and only bother with this if more than two; the machine | |
8886 | doesn't support more than eight. */ | |
8887 | if (GET_CODE (operands[2]) != CONST_INT | |
8888 | || INTVAL (operands[2]) <= 2 | |
8889 | || INTVAL (operands[2]) > 8 | |
8890 | || GET_CODE (operands[0]) != MEM | |
8891 | || GET_CODE (operands[1]) != REG | |
8892 | || REGNO (operands[1]) >= 32) | |
8893 | FAIL; | |
8894 | ||
8895 | count = INTVAL (operands[2]); | |
8896 | regno = REGNO (operands[1]); | |
8897 | ||
39403d82 | 8898 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8899 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8900 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8901 | |
8902 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 8903 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 8904 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8905 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8906 | |
8907 | for (i = 1; i < count; i++) | |
8908 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8909 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 8910 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 8911 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8912 | }") |
8913 | ||
9caa3eb2 | 8914 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
8915 | [(match_parallel 0 "store_multiple_operation" |
8916 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8917 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8918 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8919 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8920 | "{stsi|stswi} %2,%P1,%O0" |
8921 | [(set_attr "type" "store")]) | |
d14a6d05 | 8922 | |
e46e3130 | 8923 | (define_insn "*stmsi8" |
d14a6d05 | 8924 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
8925 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
8926 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8927 | (clobber (match_scratch:SI 3 "X")) | |
8928 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8929 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8930 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8931 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8932 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8933 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8934 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8935 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8936 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8937 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8938 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8939 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
8940 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
8941 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
8942 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
8943 | "{stsi|stswi} %2,%1,%O0" | |
8944 | [(set_attr "type" "store")]) | |
8945 | ||
8946 | (define_insn "*stmsi7" | |
8947 | [(match_parallel 0 "store_multiple_operation" | |
8948 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8949 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8950 | (clobber (match_scratch:SI 3 "X")) | |
8951 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8952 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8953 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8954 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8955 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8956 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8957 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8958 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8959 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8960 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8961 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8962 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
8963 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
8964 | "{stsi|stswi} %2,%1,%O0" | |
8965 | [(set_attr "type" "store")]) | |
8966 | ||
8967 | (define_insn "*stmsi6" | |
8968 | [(match_parallel 0 "store_multiple_operation" | |
8969 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8970 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8971 | (clobber (match_scratch:SI 3 "X")) | |
8972 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8973 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8974 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8975 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8976 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8977 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8978 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8979 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8980 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8981 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
8982 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
8983 | "{stsi|stswi} %2,%1,%O0" | |
8984 | [(set_attr "type" "store")]) | |
8985 | ||
8986 | (define_insn "*stmsi5" | |
8987 | [(match_parallel 0 "store_multiple_operation" | |
8988 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8989 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8990 | (clobber (match_scratch:SI 3 "X")) | |
8991 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8992 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8993 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8994 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8995 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8996 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8997 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8998 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
8999 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
9000 | "{stsi|stswi} %2,%1,%O0" | |
9001 | [(set_attr "type" "store")]) | |
9002 | ||
9003 | (define_insn "*stmsi4" | |
9004 | [(match_parallel 0 "store_multiple_operation" | |
9005 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9006 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9007 | (clobber (match_scratch:SI 3 "X")) | |
9008 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9009 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9010 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9011 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9012 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9013 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
9014 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
9015 | "{stsi|stswi} %2,%1,%O0" |
9016 | [(set_attr "type" "store")]) | |
7e69e155 | 9017 | |
e46e3130 DJ |
9018 | (define_insn "*stmsi3" |
9019 | [(match_parallel 0 "store_multiple_operation" | |
9020 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9021 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9022 | (clobber (match_scratch:SI 3 "X")) | |
9023 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9024 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9025 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9026 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
9027 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
9028 | "{stsi|stswi} %2,%1,%O0" | |
9029 | [(set_attr "type" "store")]) | |
7e69e155 | 9030 | \f |
fba73eb1 DE |
9031 | (define_expand "clrmemsi" |
9032 | [(parallel [(set (match_operand:BLK 0 "" "") | |
9033 | (const_int 0)) | |
9034 | (use (match_operand:SI 1 "" "")) | |
9035 | (use (match_operand:SI 2 "" ""))])] | |
9036 | "" | |
9037 | " | |
9038 | { | |
9039 | if (expand_block_clear (operands)) | |
9040 | DONE; | |
9041 | else | |
9042 | FAIL; | |
9043 | }") | |
9044 | ||
7e69e155 MM |
9045 | ;; String/block move insn. |
9046 | ;; Argument 0 is the destination | |
9047 | ;; Argument 1 is the source | |
9048 | ;; Argument 2 is the length | |
9049 | ;; Argument 3 is the alignment | |
9050 | ||
70128ad9 | 9051 | (define_expand "movmemsi" |
b6c9286a MM |
9052 | [(parallel [(set (match_operand:BLK 0 "" "") |
9053 | (match_operand:BLK 1 "" "")) | |
9054 | (use (match_operand:SI 2 "" "")) | |
9055 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
9056 | "" |
9057 | " | |
9058 | { | |
9059 | if (expand_block_move (operands)) | |
9060 | DONE; | |
9061 | else | |
9062 | FAIL; | |
9063 | }") | |
9064 | ||
9065 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
9066 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
9067 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9068 | (define_expand "movmemsi_8reg" |
b6c9286a MM |
9069 | [(parallel [(set (match_operand 0 "" "") |
9070 | (match_operand 1 "" "")) | |
9071 | (use (match_operand 2 "" "")) | |
9072 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
9073 | (clobber (reg:SI 5)) |
9074 | (clobber (reg:SI 6)) | |
9075 | (clobber (reg:SI 7)) | |
9076 | (clobber (reg:SI 8)) | |
9077 | (clobber (reg:SI 9)) | |
9078 | (clobber (reg:SI 10)) | |
9079 | (clobber (reg:SI 11)) | |
9080 | (clobber (reg:SI 12)) | |
3c67b673 | 9081 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9082 | "TARGET_STRING" |
9083 | "") | |
9084 | ||
9085 | (define_insn "" | |
52d3af72 DE |
9086 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9087 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9088 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9089 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9090 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9091 | (clobber (reg:SI 6)) |
9092 | (clobber (reg:SI 7)) | |
9093 | (clobber (reg:SI 8)) | |
9094 | (clobber (reg:SI 9)) | |
9095 | (clobber (reg:SI 10)) | |
9096 | (clobber (reg:SI 11)) | |
9097 | (clobber (reg:SI 12)) | |
3c67b673 | 9098 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 9099 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
9100 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9101 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9102 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9103 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9104 | && REGNO (operands[4]) == 5" |
9105 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9106 | [(set_attr "type" "load") |
9107 | (set_attr "length" "8")]) | |
7e69e155 MM |
9108 | |
9109 | (define_insn "" | |
52d3af72 DE |
9110 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9111 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9112 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9113 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9114 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9115 | (clobber (reg:SI 6)) |
9116 | (clobber (reg:SI 7)) | |
9117 | (clobber (reg:SI 8)) | |
9118 | (clobber (reg:SI 9)) | |
9119 | (clobber (reg:SI 10)) | |
9120 | (clobber (reg:SI 11)) | |
9121 | (clobber (reg:SI 12)) | |
3c67b673 | 9122 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9123 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
9124 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9125 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9126 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9127 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9128 | && REGNO (operands[4]) == 5" |
9129 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9130 | [(set_attr "type" "load") |
9131 | (set_attr "length" "8")]) | |
7e69e155 | 9132 | |
09a625f7 TR |
9133 | (define_insn "" |
9134 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9135 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9136 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9137 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9138 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9139 | (clobber (reg:SI 6)) | |
9140 | (clobber (reg:SI 7)) | |
9141 | (clobber (reg:SI 8)) | |
9142 | (clobber (reg:SI 9)) | |
9143 | (clobber (reg:SI 10)) | |
9144 | (clobber (reg:SI 11)) | |
9145 | (clobber (reg:SI 12)) | |
9146 | (clobber (match_scratch:SI 5 "X"))] | |
9147 | "TARGET_STRING && TARGET_POWERPC64 | |
9148 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
9149 | || INTVAL (operands[2]) == 0) | |
9150 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
9151 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
9152 | && REGNO (operands[4]) == 5" | |
9153 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9154 | [(set_attr "type" "load") | |
9155 | (set_attr "length" "8")]) | |
9156 | ||
7e69e155 | 9157 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
9158 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
9159 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9160 | (define_expand "movmemsi_6reg" |
b6c9286a MM |
9161 | [(parallel [(set (match_operand 0 "" "") |
9162 | (match_operand 1 "" "")) | |
9163 | (use (match_operand 2 "" "")) | |
9164 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9165 | (clobber (reg:SI 5)) |
9166 | (clobber (reg:SI 6)) | |
7e69e155 MM |
9167 | (clobber (reg:SI 7)) |
9168 | (clobber (reg:SI 8)) | |
9169 | (clobber (reg:SI 9)) | |
9170 | (clobber (reg:SI 10)) | |
3c67b673 | 9171 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9172 | "TARGET_STRING" |
9173 | "") | |
9174 | ||
9175 | (define_insn "" | |
52d3af72 DE |
9176 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9177 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9178 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9179 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9180 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9181 | (clobber (reg:SI 6)) |
9182 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9183 | (clobber (reg:SI 8)) |
9184 | (clobber (reg:SI 9)) | |
9185 | (clobber (reg:SI 10)) | |
3c67b673 | 9186 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9187 | "TARGET_STRING && TARGET_POWER |
9188 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
9189 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9190 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9191 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9192 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9193 | [(set_attr "type" "load") |
9194 | (set_attr "length" "8")]) | |
7e69e155 MM |
9195 | |
9196 | (define_insn "" | |
52d3af72 DE |
9197 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9198 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9199 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9200 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9201 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9202 | (clobber (reg:SI 6)) |
9203 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9204 | (clobber (reg:SI 8)) |
9205 | (clobber (reg:SI 9)) | |
9206 | (clobber (reg:SI 10)) | |
3c67b673 | 9207 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9208 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9209 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
9210 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9211 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9212 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9213 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9214 | [(set_attr "type" "load") |
9215 | (set_attr "length" "8")]) | |
7e69e155 | 9216 | |
09a625f7 TR |
9217 | (define_insn "" |
9218 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9219 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9220 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9221 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9222 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9223 | (clobber (reg:SI 6)) | |
9224 | (clobber (reg:SI 7)) | |
9225 | (clobber (reg:SI 8)) | |
9226 | (clobber (reg:SI 9)) | |
9227 | (clobber (reg:SI 10)) | |
9228 | (clobber (match_scratch:SI 5 "X"))] | |
9229 | "TARGET_STRING && TARGET_POWERPC64 | |
9230 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
9231 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
9232 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9233 | && REGNO (operands[4]) == 5" | |
9234 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9235 | [(set_attr "type" "load") | |
9236 | (set_attr "length" "8")]) | |
9237 | ||
f9562f27 DE |
9238 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9239 | ;; problems with TImode. | |
9240 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9241 | (define_expand "movmemsi_4reg" |
b6c9286a MM |
9242 | [(parallel [(set (match_operand 0 "" "") |
9243 | (match_operand 1 "" "")) | |
9244 | (use (match_operand 2 "" "")) | |
9245 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9246 | (clobber (reg:SI 5)) |
9247 | (clobber (reg:SI 6)) | |
9248 | (clobber (reg:SI 7)) | |
9249 | (clobber (reg:SI 8)) | |
3c67b673 | 9250 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9251 | "TARGET_STRING" |
9252 | "") | |
9253 | ||
9254 | (define_insn "" | |
52d3af72 DE |
9255 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9256 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9257 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9258 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9259 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9260 | (clobber (reg:SI 6)) |
9261 | (clobber (reg:SI 7)) | |
9262 | (clobber (reg:SI 8)) | |
3c67b673 | 9263 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9264 | "TARGET_STRING && TARGET_POWER |
9265 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9266 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9267 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9268 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9269 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9270 | [(set_attr "type" "load") |
9271 | (set_attr "length" "8")]) | |
7e69e155 MM |
9272 | |
9273 | (define_insn "" | |
52d3af72 DE |
9274 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9275 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9276 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9277 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9278 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9279 | (clobber (reg:SI 6)) |
9280 | (clobber (reg:SI 7)) | |
9281 | (clobber (reg:SI 8)) | |
3c67b673 | 9282 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9283 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9284 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9285 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9286 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9287 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9288 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9289 | [(set_attr "type" "load") |
9290 | (set_attr "length" "8")]) | |
7e69e155 | 9291 | |
09a625f7 TR |
9292 | (define_insn "" |
9293 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9294 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9295 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9296 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9297 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9298 | (clobber (reg:SI 6)) | |
9299 | (clobber (reg:SI 7)) | |
9300 | (clobber (reg:SI 8)) | |
9301 | (clobber (match_scratch:SI 5 "X"))] | |
9302 | "TARGET_STRING && TARGET_POWERPC64 | |
9303 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
9304 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
9305 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9306 | && REGNO (operands[4]) == 5" | |
9307 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9308 | [(set_attr "type" "load") | |
9309 | (set_attr "length" "8")]) | |
9310 | ||
7e69e155 | 9311 | ;; Move up to 8 bytes at a time. |
70128ad9 | 9312 | (define_expand "movmemsi_2reg" |
b6c9286a MM |
9313 | [(parallel [(set (match_operand 0 "" "") |
9314 | (match_operand 1 "" "")) | |
9315 | (use (match_operand 2 "" "")) | |
9316 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9317 | (clobber (match_scratch:DI 4 "")) |
9318 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9319 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9320 | "") |
9321 | ||
9322 | (define_insn "" | |
52d3af72 DE |
9323 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9324 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9325 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9326 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9327 | (clobber (match_scratch:DI 4 "=&r")) | |
9328 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9329 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9330 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9331 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9332 | [(set_attr "type" "load") |
9333 | (set_attr "length" "8")]) | |
7e69e155 MM |
9334 | |
9335 | (define_insn "" | |
52d3af72 DE |
9336 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9337 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9338 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9339 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9340 | (clobber (match_scratch:DI 4 "=&r")) | |
9341 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9342 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9343 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9344 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9345 | [(set_attr "type" "load") |
9346 | (set_attr "length" "8")]) | |
7e69e155 MM |
9347 | |
9348 | ;; Move up to 4 bytes at a time. | |
70128ad9 | 9349 | (define_expand "movmemsi_1reg" |
b6c9286a MM |
9350 | [(parallel [(set (match_operand 0 "" "") |
9351 | (match_operand 1 "" "")) | |
9352 | (use (match_operand 2 "" "")) | |
9353 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9354 | (clobber (match_scratch:SI 4 "")) |
9355 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9356 | "TARGET_STRING" |
9357 | "") | |
9358 | ||
9359 | (define_insn "" | |
52d3af72 DE |
9360 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9361 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9362 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9363 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9364 | (clobber (match_scratch:SI 4 "=&r")) | |
9365 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9366 | "TARGET_STRING && TARGET_POWER |
9367 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9368 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9369 | [(set_attr "type" "load") |
9370 | (set_attr "length" "8")]) | |
7e69e155 MM |
9371 | |
9372 | (define_insn "" | |
52d3af72 DE |
9373 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9374 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9375 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9376 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9377 | (clobber (match_scratch:SI 4 "=&r")) | |
9378 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9379 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9380 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
9381 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
9382 | [(set_attr "type" "load") | |
9383 | (set_attr "length" "8")]) | |
9384 | ||
9385 | (define_insn "" | |
9386 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9387 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9388 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9389 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9390 | (clobber (match_scratch:SI 4 "=&r")) | |
9391 | (clobber (match_scratch:SI 5 "X"))] | |
9392 | "TARGET_STRING && TARGET_POWERPC64 | |
9393 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9394 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9395 | [(set_attr "type" "load") |
9396 | (set_attr "length" "8")]) | |
7e69e155 | 9397 | |
1fd4e8c1 | 9398 | \f |
7e69e155 | 9399 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9400 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9401 | ;; do cases where the increment is not the size of the object. | |
9402 | ;; | |
9403 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9404 | ;; incremented because those are the operands that local-alloc will | |
9405 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9406 | ;; that will benefit the most). | |
9407 | ||
38c1f2d7 | 9408 | (define_insn "*movdi_update1" |
51b8fc2c | 9409 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9410 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9411 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
9412 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
9413 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9414 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9415 | "@ |
9416 | ldux %3,%0,%2 | |
9417 | ldu %3,%2(%0)" | |
b54cf83a | 9418 | [(set_attr "type" "load_ux,load_u")]) |
287f13ff | 9419 | |
2e6c9641 FJ |
9420 | (define_insn "movdi_<mode>_update" |
9421 | [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") | |
9422 | (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) | |
51b8fc2c | 9423 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
2e6c9641 FJ |
9424 | (set (match_operand:P 0 "gpc_reg_operand" "=b,b") |
9425 | (plus:P (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9426 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9427 | "@ |
9428 | stdux %3,%0,%2 | |
b7ff3d82 | 9429 | stdu %3,%2(%0)" |
b54cf83a | 9430 | [(set_attr "type" "store_ux,store_u")]) |
51b8fc2c | 9431 | |
38c1f2d7 | 9432 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9433 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9434 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9435 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9436 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9437 | (plus:SI (match_dup 1) (match_dup 2)))] |
f7b3ab8a | 9438 | "TARGET_UPDATE" |
1fd4e8c1 | 9439 | "@ |
ca7f5001 RK |
9440 | {lux|lwzux} %3,%0,%2 |
9441 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a DE |
9442 | [(set_attr "type" "load_ux,load_u")]) |
9443 | ||
9444 | (define_insn "*movsi_update2" | |
9445 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
9446 | (sign_extend:DI | |
9447 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9448 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9449 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9450 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9451 | "TARGET_POWERPC64" | |
9452 | "lwaux %3,%0,%2" | |
9453 | [(set_attr "type" "load_ext_ux")]) | |
1fd4e8c1 | 9454 | |
4697a36c | 9455 | (define_insn "movsi_update" |
cd2b37d9 | 9456 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9457 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9458 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9459 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9460 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9461 | "TARGET_UPDATE" |
1fd4e8c1 | 9462 | "@ |
ca7f5001 | 9463 | {stux|stwux} %3,%0,%2 |
b7ff3d82 | 9464 | {stu|stwu} %3,%2(%0)" |
b54cf83a | 9465 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9466 | |
b54cf83a | 9467 | (define_insn "*movhi_update1" |
cd2b37d9 RK |
9468 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9469 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9470 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9471 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9472 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9473 | "TARGET_UPDATE" |
1fd4e8c1 | 9474 | "@ |
5f243543 RK |
9475 | lhzux %3,%0,%2 |
9476 | lhzu %3,%2(%0)" | |
b54cf83a | 9477 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9478 | |
38c1f2d7 | 9479 | (define_insn "*movhi_update2" |
cd2b37d9 | 9480 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9481 | (zero_extend:SI |
cd2b37d9 | 9482 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9483 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9484 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9485 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9486 | "TARGET_UPDATE" |
1fd4e8c1 | 9487 | "@ |
5f243543 RK |
9488 | lhzux %3,%0,%2 |
9489 | lhzu %3,%2(%0)" | |
b54cf83a | 9490 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9491 | |
38c1f2d7 | 9492 | (define_insn "*movhi_update3" |
cd2b37d9 | 9493 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9494 | (sign_extend:SI |
cd2b37d9 | 9495 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9496 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9497 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9498 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9499 | "TARGET_UPDATE" |
1fd4e8c1 | 9500 | "@ |
5f243543 RK |
9501 | lhaux %3,%0,%2 |
9502 | lhau %3,%2(%0)" | |
b54cf83a | 9503 | [(set_attr "type" "load_ext_ux,load_ext_u")]) |
1fd4e8c1 | 9504 | |
38c1f2d7 | 9505 | (define_insn "*movhi_update4" |
cd2b37d9 | 9506 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9507 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9508 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9509 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9510 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9511 | "TARGET_UPDATE" |
1fd4e8c1 | 9512 | "@ |
5f243543 | 9513 | sthux %3,%0,%2 |
b7ff3d82 | 9514 | sthu %3,%2(%0)" |
b54cf83a | 9515 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9516 | |
38c1f2d7 | 9517 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9518 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9519 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9520 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9521 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9522 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9523 | "TARGET_UPDATE" |
1fd4e8c1 | 9524 | "@ |
5f243543 RK |
9525 | lbzux %3,%0,%2 |
9526 | lbzu %3,%2(%0)" | |
b54cf83a | 9527 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9528 | |
38c1f2d7 | 9529 | (define_insn "*movqi_update2" |
cd2b37d9 | 9530 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9531 | (zero_extend:SI |
cd2b37d9 | 9532 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9533 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9534 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9535 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9536 | "TARGET_UPDATE" |
1fd4e8c1 | 9537 | "@ |
5f243543 RK |
9538 | lbzux %3,%0,%2 |
9539 | lbzu %3,%2(%0)" | |
b54cf83a | 9540 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9541 | |
38c1f2d7 | 9542 | (define_insn "*movqi_update3" |
cd2b37d9 | 9543 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9544 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9545 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9546 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9547 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9548 | "TARGET_UPDATE" |
1fd4e8c1 | 9549 | "@ |
5f243543 | 9550 | stbux %3,%0,%2 |
b7ff3d82 | 9551 | stbu %3,%2(%0)" |
b54cf83a | 9552 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9553 | |
38c1f2d7 | 9554 | (define_insn "*movsf_update1" |
cd2b37d9 | 9555 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9556 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9557 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9558 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9559 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9560 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9561 | "@ |
5f243543 RK |
9562 | lfsux %3,%0,%2 |
9563 | lfsu %3,%2(%0)" | |
b54cf83a | 9564 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9565 | |
38c1f2d7 | 9566 | (define_insn "*movsf_update2" |
cd2b37d9 | 9567 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9568 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9569 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9570 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9571 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9572 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9573 | "@ |
85fff2f3 | 9574 | stfsux %3,%0,%2 |
b7ff3d82 | 9575 | stfsu %3,%2(%0)" |
b54cf83a | 9576 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
1fd4e8c1 | 9577 | |
38c1f2d7 MM |
9578 | (define_insn "*movsf_update3" |
9579 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9580 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9581 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9582 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9583 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9584 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9585 | "@ |
9586 | {lux|lwzux} %3,%0,%2 | |
9587 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a | 9588 | [(set_attr "type" "load_ux,load_u")]) |
38c1f2d7 MM |
9589 | |
9590 | (define_insn "*movsf_update4" | |
9591 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9592 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9593 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9594 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9595 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9596 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9597 | "@ |
9598 | {stux|stwux} %3,%0,%2 | |
9599 | {stu|stwu} %3,%2(%0)" | |
b54cf83a | 9600 | [(set_attr "type" "store_ux,store_u")]) |
38c1f2d7 MM |
9601 | |
9602 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9603 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9604 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9605 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9606 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9607 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9608 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9609 | "@ |
5f243543 RK |
9610 | lfdux %3,%0,%2 |
9611 | lfdu %3,%2(%0)" | |
b54cf83a | 9612 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9613 | |
38c1f2d7 | 9614 | (define_insn "*movdf_update2" |
cd2b37d9 | 9615 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9616 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9617 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9618 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9619 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9620 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9621 | "@ |
5f243543 | 9622 | stfdux %3,%0,%2 |
b7ff3d82 | 9623 | stfdu %3,%2(%0)" |
b54cf83a | 9624 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
4c70a4f3 RK |
9625 | |
9626 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9627 | ||
90f81f99 AP |
9628 | (define_insn "*lfq_power2" |
9629 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
9630 | (match_operand:TF 1 "memory_operand" ""))] | |
9631 | "TARGET_POWER2 | |
9632 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9633 | "lfq%U1%X1 %0,%1") | |
9634 | ||
9635 | (define_peephole2 | |
9636 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4c70a4f3 | 9637 | (match_operand:DF 1 "memory_operand" "")) |
90f81f99 | 9638 | (set (match_operand:DF 2 "gpc_reg_operand" "") |
4c70a4f3 RK |
9639 | (match_operand:DF 3 "memory_operand" ""))] |
9640 | "TARGET_POWER2 | |
a3170dc6 | 9641 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9642 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
90f81f99 AP |
9643 | && mems_ok_for_quad_peep (operands[1], operands[3])" |
9644 | [(set (match_dup 0) | |
9645 | (match_dup 1))] | |
9646 | "operands[1] = widen_memory_access (operands[1], TFmode, 0); | |
9647 | operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));") | |
4c70a4f3 | 9648 | |
90f81f99 AP |
9649 | (define_insn "*stfq_power2" |
9650 | [(set (match_operand:TF 0 "memory_operand" "") | |
9651 | (match_operand:TF 1 "gpc_reg_operand" "f"))] | |
9652 | "TARGET_POWER2 | |
9653 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9654 | "stfq%U0%X0 %1,%0") | |
9655 | ||
9656 | ||
9657 | (define_peephole2 | |
4c70a4f3 | 9658 | [(set (match_operand:DF 0 "memory_operand" "") |
90f81f99 | 9659 | (match_operand:DF 1 "gpc_reg_operand" "")) |
4c70a4f3 | 9660 | (set (match_operand:DF 2 "memory_operand" "") |
90f81f99 | 9661 | (match_operand:DF 3 "gpc_reg_operand" ""))] |
4c70a4f3 | 9662 | "TARGET_POWER2 |
a3170dc6 | 9663 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9664 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
90f81f99 AP |
9665 | && mems_ok_for_quad_peep (operands[0], operands[2])" |
9666 | [(set (match_dup 0) | |
9667 | (match_dup 1))] | |
9668 | "operands[0] = widen_memory_access (operands[0], TFmode, 0); | |
9669 | operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));") | |
2f4d9502 NS |
9670 | |
9671 | ;; after inserting conditional returns we can sometimes have | |
9672 | ;; unnecessary register moves. Unfortunately we cannot have a | |
9673 | ;; modeless peephole here, because some single SImode sets have early | |
9674 | ;; clobber outputs. Although those sets expand to multi-ppc-insn | |
9675 | ;; sequences, using get_attr_length here will smash the operands | |
9676 | ;; array. Neither is there an early_cobbler_p predicate. | |
9677 | (define_peephole2 | |
9678 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
9679 | (match_operand:DF 1 "any_operand" "")) | |
9680 | (set (match_operand:DF 2 "gpc_reg_operand" "") | |
9681 | (match_dup 0))] | |
9682 | "peep2_reg_dead_p (2, operands[0])" | |
9683 | [(set (match_dup 2) (match_dup 1))]) | |
9684 | ||
9685 | (define_peephole2 | |
9686 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
9687 | (match_operand:SF 1 "any_operand" "")) | |
9688 | (set (match_operand:SF 2 "gpc_reg_operand" "") | |
9689 | (match_dup 0))] | |
9690 | "peep2_reg_dead_p (2, operands[0])" | |
9691 | [(set (match_dup 2) (match_dup 1))]) | |
9692 | ||
1fd4e8c1 | 9693 | \f |
c4501e62 JJ |
9694 | ;; TLS support. |
9695 | ||
9696 | ;; "b" output constraint here and on tls_ld to support tls linker optimization. | |
9697 | (define_insn "tls_gd_32" | |
b150f4f3 DE |
9698 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9699 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9700 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9701 | UNSPEC_TLSGD))] | |
9702 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9703 | "addi %0,%1,%2@got@tlsgd") | |
9704 | ||
9705 | (define_insn "tls_gd_64" | |
b150f4f3 DE |
9706 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9707 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9708 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9709 | UNSPEC_TLSGD))] | |
9710 | "HAVE_AS_TLS && TARGET_64BIT" | |
9711 | "addi %0,%1,%2@got@tlsgd") | |
9712 | ||
9713 | (define_insn "tls_ld_32" | |
b150f4f3 DE |
9714 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9715 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9716 | UNSPEC_TLSLD))] |
9717 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9718 | "addi %0,%1,%&@got@tlsld") | |
9719 | ||
9720 | (define_insn "tls_ld_64" | |
b150f4f3 DE |
9721 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9722 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9723 | UNSPEC_TLSLD))] |
9724 | "HAVE_AS_TLS && TARGET_64BIT" | |
9725 | "addi %0,%1,%&@got@tlsld") | |
9726 | ||
9727 | (define_insn "tls_dtprel_32" | |
b150f4f3 DE |
9728 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9729 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9730 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9731 | UNSPEC_TLSDTPREL))] | |
9732 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9733 | "addi %0,%1,%2@dtprel") | |
9734 | ||
9735 | (define_insn "tls_dtprel_64" | |
b150f4f3 DE |
9736 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9737 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9738 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9739 | UNSPEC_TLSDTPREL))] | |
9740 | "HAVE_AS_TLS && TARGET_64BIT" | |
9741 | "addi %0,%1,%2@dtprel") | |
9742 | ||
9743 | (define_insn "tls_dtprel_ha_32" | |
b150f4f3 DE |
9744 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9745 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9746 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9747 | UNSPEC_TLSDTPRELHA))] | |
9748 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9749 | "addis %0,%1,%2@dtprel@ha") | |
9750 | ||
9751 | (define_insn "tls_dtprel_ha_64" | |
b150f4f3 DE |
9752 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9753 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9754 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9755 | UNSPEC_TLSDTPRELHA))] | |
9756 | "HAVE_AS_TLS && TARGET_64BIT" | |
9757 | "addis %0,%1,%2@dtprel@ha") | |
9758 | ||
9759 | (define_insn "tls_dtprel_lo_32" | |
b150f4f3 DE |
9760 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9761 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9762 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9763 | UNSPEC_TLSDTPRELLO))] | |
9764 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9765 | "addi %0,%1,%2@dtprel@l") | |
9766 | ||
9767 | (define_insn "tls_dtprel_lo_64" | |
b150f4f3 DE |
9768 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9769 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9770 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9771 | UNSPEC_TLSDTPRELLO))] | |
9772 | "HAVE_AS_TLS && TARGET_64BIT" | |
9773 | "addi %0,%1,%2@dtprel@l") | |
9774 | ||
9775 | (define_insn "tls_got_dtprel_32" | |
b150f4f3 DE |
9776 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9777 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9778 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9779 | UNSPEC_TLSGOTDTPREL))] | |
9780 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9781 | "lwz %0,%2@got@dtprel(%1)") | |
9782 | ||
9783 | (define_insn "tls_got_dtprel_64" | |
b150f4f3 DE |
9784 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9785 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9786 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9787 | UNSPEC_TLSGOTDTPREL))] | |
9788 | "HAVE_AS_TLS && TARGET_64BIT" | |
9789 | "ld %0,%2@got@dtprel(%1)") | |
9790 | ||
9791 | (define_insn "tls_tprel_32" | |
b150f4f3 DE |
9792 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9793 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9794 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9795 | UNSPEC_TLSTPREL))] | |
9796 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9797 | "addi %0,%1,%2@tprel") | |
9798 | ||
9799 | (define_insn "tls_tprel_64" | |
b150f4f3 DE |
9800 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9801 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9802 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9803 | UNSPEC_TLSTPREL))] | |
9804 | "HAVE_AS_TLS && TARGET_64BIT" | |
9805 | "addi %0,%1,%2@tprel") | |
9806 | ||
9807 | (define_insn "tls_tprel_ha_32" | |
b150f4f3 DE |
9808 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9809 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9810 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9811 | UNSPEC_TLSTPRELHA))] | |
9812 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9813 | "addis %0,%1,%2@tprel@ha") | |
9814 | ||
9815 | (define_insn "tls_tprel_ha_64" | |
b150f4f3 DE |
9816 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9817 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9818 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9819 | UNSPEC_TLSTPRELHA))] | |
9820 | "HAVE_AS_TLS && TARGET_64BIT" | |
9821 | "addis %0,%1,%2@tprel@ha") | |
9822 | ||
9823 | (define_insn "tls_tprel_lo_32" | |
b150f4f3 DE |
9824 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9825 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9826 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9827 | UNSPEC_TLSTPRELLO))] | |
9828 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9829 | "addi %0,%1,%2@tprel@l") | |
9830 | ||
9831 | (define_insn "tls_tprel_lo_64" | |
b150f4f3 DE |
9832 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9833 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9834 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9835 | UNSPEC_TLSTPRELLO))] | |
9836 | "HAVE_AS_TLS && TARGET_64BIT" | |
9837 | "addi %0,%1,%2@tprel@l") | |
9838 | ||
c1207243 | 9839 | ;; "b" output constraint here and on tls_tls input to support linker tls |
c4501e62 JJ |
9840 | ;; optimization. The linker may edit the instructions emitted by a |
9841 | ;; tls_got_tprel/tls_tls pair to addis,addi. | |
9842 | (define_insn "tls_got_tprel_32" | |
b150f4f3 DE |
9843 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9844 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9845 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9846 | UNSPEC_TLSGOTTPREL))] | |
9847 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9848 | "lwz %0,%2@got@tprel(%1)") | |
9849 | ||
9850 | (define_insn "tls_got_tprel_64" | |
b150f4f3 DE |
9851 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9852 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9853 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9854 | UNSPEC_TLSGOTTPREL))] | |
9855 | "HAVE_AS_TLS && TARGET_64BIT" | |
9856 | "ld %0,%2@got@tprel(%1)") | |
9857 | ||
9858 | (define_insn "tls_tls_32" | |
b150f4f3 DE |
9859 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9860 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9861 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9862 | UNSPEC_TLSTLS))] | |
9863 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9864 | "add %0,%1,%2@tls") | |
9865 | ||
9866 | (define_insn "tls_tls_64" | |
b150f4f3 DE |
9867 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9868 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9869 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9870 | UNSPEC_TLSTLS))] | |
9871 | "HAVE_AS_TLS && TARGET_64BIT" | |
9872 | "add %0,%1,%2@tls") | |
9873 | \f | |
1fd4e8c1 RK |
9874 | ;; Next come insns related to the calling sequence. |
9875 | ;; | |
9876 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9877 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9878 | |
9879 | (define_expand "allocate_stack" | |
52d3af72 | 9880 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9881 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9882 | (set (reg 1) | |
9883 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9884 | "" |
9885 | " | |
4697a36c | 9886 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9887 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9888 | rtx neg_op0; |
1fd4e8c1 RK |
9889 | |
9890 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9891 | |
a157febd GK |
9892 | /* Check stack bounds if necessary. */ |
9893 | if (current_function_limit_stack) | |
9894 | { | |
9895 | rtx available; | |
6ae08853 | 9896 | available = expand_binop (Pmode, sub_optab, |
a157febd GK |
9897 | stack_pointer_rtx, stack_limit_rtx, |
9898 | NULL_RTX, 1, OPTAB_WIDEN); | |
9899 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9900 | } | |
9901 | ||
e9a25f70 JL |
9902 | if (GET_CODE (operands[1]) != CONST_INT |
9903 | || INTVAL (operands[1]) < -32767 | |
9904 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9905 | { |
9906 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9907 | if (TARGET_32BIT) |
e9a25f70 | 9908 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9909 | else |
e9a25f70 | 9910 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9911 | } |
9912 | else | |
e9a25f70 | 9913 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9914 | |
38c1f2d7 | 9915 | if (TARGET_UPDATE) |
2e6c9641 | 9916 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update)) |
38c1f2d7 | 9917 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); |
4697a36c | 9918 | |
38c1f2d7 MM |
9919 | else |
9920 | { | |
9921 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9922 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9923 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9924 | } |
e9a25f70 JL |
9925 | |
9926 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9927 | DONE; |
9928 | }") | |
59257ff7 RK |
9929 | |
9930 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9931 | ;; save the stack pointer at function level since we are careful to | |
9932 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9933 | ;; when we restore the stack pointer. | |
9934 | ;; | |
9935 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9936 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9937 | ;; save area is a memory location. | |
9938 | ||
9939 | (define_expand "save_stack_function" | |
ff381587 MM |
9940 | [(match_operand 0 "any_operand" "") |
9941 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9942 | "" |
ff381587 | 9943 | "DONE;") |
59257ff7 RK |
9944 | |
9945 | (define_expand "restore_stack_function" | |
ff381587 MM |
9946 | [(match_operand 0 "any_operand" "") |
9947 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9948 | "" |
ff381587 | 9949 | "DONE;") |
59257ff7 RK |
9950 | |
9951 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9952 | [(use (match_operand 0 "register_operand" "")) |
9953 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9954 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9955 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9956 | "" |
9957 | " | |
dfdfa60f DE |
9958 | { |
9959 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9960 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9961 | }") |
59257ff7 RK |
9962 | |
9963 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9964 | [(match_operand 0 "memory_operand" "") |
9965 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9966 | "" |
9967 | " | |
9968 | { | |
a260abc9 | 9969 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 9970 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9971 | |
9972 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9973 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
39e453d7 DE |
9974 | emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp); |
9975 | emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word), | |
a260abc9 | 9976 | operands[1]); |
59257ff7 RK |
9977 | DONE; |
9978 | }") | |
7e69e155 | 9979 | |
59257ff7 | 9980 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9981 | [(match_operand 0 "register_operand" "") |
9982 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9983 | "" |
9984 | " | |
9985 | { | |
a260abc9 | 9986 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 9987 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9988 | |
9989 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 | 9990 | emit_move_insn (temp, |
39e453d7 | 9991 | adjust_address_nv (operands[1], Pmode, 0)); |
a260abc9 | 9992 | emit_move_insn (operands[0], |
39e453d7 | 9993 | adjust_address_nv (operands[1], Pmode, units_per_word)); |
39403d82 | 9994 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9995 | DONE; |
9996 | }") | |
9ebbca7d GK |
9997 | \f |
9998 | ;; TOC register handling. | |
b6c9286a | 9999 | |
9ebbca7d | 10000 | ;; Code to initialize the TOC register... |
f0f6a223 | 10001 | |
9ebbca7d | 10002 | (define_insn "load_toc_aix_si" |
e72247f4 | 10003 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
615158e2 | 10004 | (unspec:SI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 10005 | (use (reg:SI 2))])] |
2bfcf297 | 10006 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
10007 | "* |
10008 | { | |
9ebbca7d GK |
10009 | char buf[30]; |
10010 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 10011 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10012 | operands[2] = gen_rtx_REG (Pmode, 2); |
10013 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
10014 | }" |
10015 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
10016 | |
10017 | (define_insn "load_toc_aix_di" | |
e72247f4 | 10018 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
615158e2 | 10019 | (unspec:DI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 10020 | (use (reg:DI 2))])] |
2bfcf297 | 10021 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
10022 | "* |
10023 | { | |
10024 | char buf[30]; | |
f585a356 DE |
10025 | #ifdef TARGET_RELOCATABLE |
10026 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
10027 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
10028 | #else | |
9ebbca7d | 10029 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 10030 | #endif |
2bfcf297 DB |
10031 | if (TARGET_ELF) |
10032 | strcat (buf, \"@toc\"); | |
a8a05998 | 10033 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10034 | operands[2] = gen_rtx_REG (Pmode, 2); |
10035 | return \"ld %0,%1(%2)\"; | |
10036 | }" | |
10037 | [(set_attr "type" "load")]) | |
10038 | ||
10039 | (define_insn "load_toc_v4_pic_si" | |
10040 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 | 10041 | (unspec:SI [(const_int 0)] UNSPEC_TOC))] |
f607bc57 | 10042 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
10043 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
10044 | [(set_attr "type" "branch") | |
10045 | (set_attr "length" "4")]) | |
10046 | ||
9ebbca7d GK |
10047 | (define_insn "load_toc_v4_PIC_1" |
10048 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10049 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 | 10050 | (use (unspec [(match_dup 1)] UNSPEC_TOC))] |
20b71b17 | 10051 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 10052 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
10053 | [(set_attr "type" "branch") |
10054 | (set_attr "length" "4")]) | |
10055 | ||
10056 | (define_insn "load_toc_v4_PIC_1b" | |
10057 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10058 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 JJ |
10059 | (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] |
10060 | UNSPEC_TOCPTR))] | |
20b71b17 | 10061 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
c4501e62 | 10062 | "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1" |
9ebbca7d GK |
10063 | [(set_attr "type" "branch") |
10064 | (set_attr "length" "8")]) | |
10065 | ||
10066 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 10067 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 10068 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
10069 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
10070 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 10071 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
10072 | "{l|lwz} %0,%2-%3(%1)" |
10073 | [(set_attr "type" "load")]) | |
10074 | ||
f51eee6a | 10075 | |
9ebbca7d GK |
10076 | ;; If the TOC is shared over a translation unit, as happens with all |
10077 | ;; the kinds of PIC that we support, we need to restore the TOC | |
10078 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 10079 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
10080 | |
10081 | (define_expand "builtin_setjmp_receiver" | |
10082 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 10083 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
10084 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
10085 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
10086 | " |
10087 | { | |
84d7dd4a | 10088 | #if TARGET_MACHO |
f51eee6a GK |
10089 | if (DEFAULT_ABI == ABI_DARWIN) |
10090 | { | |
d24652ee | 10091 | const char *picbase = machopic_function_base_name (); |
485bad26 | 10092 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); |
f51eee6a GK |
10093 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
10094 | rtx tmplabrtx; | |
10095 | char tmplab[20]; | |
10096 | ||
10097 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
10098 | CODE_LABEL_NUMBER (operands[0])); | |
485bad26 | 10099 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); |
f51eee6a | 10100 | |
b8a55285 AP |
10101 | emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); |
10102 | emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
f51eee6a GK |
10103 | } |
10104 | else | |
84d7dd4a | 10105 | #endif |
f51eee6a | 10106 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
10107 | DONE; |
10108 | }") | |
10109 | \f | |
10110 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
10111 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
10112 | ;; pointer to its TOC, and whose third word contains a value to place in the |
10113 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 10114 | ;; "trampoline" need not have any executable code. |
b6c9286a | 10115 | |
cccf3bdc DE |
10116 | (define_expand "call_indirect_aix32" |
10117 | [(set (match_dup 2) | |
10118 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
10119 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10120 | (reg:SI 2)) | |
10121 | (set (reg:SI 2) | |
10122 | (mem:SI (plus:SI (match_dup 0) | |
10123 | (const_int 4)))) | |
10124 | (set (reg:SI 11) | |
10125 | (mem:SI (plus:SI (match_dup 0) | |
10126 | (const_int 8)))) | |
10127 | (parallel [(call (mem:SI (match_dup 2)) | |
10128 | (match_operand 1 "" "")) | |
10129 | (use (reg:SI 2)) | |
10130 | (use (reg:SI 11)) | |
10131 | (set (reg:SI 2) | |
10132 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10133 | (clobber (scratch:SI))])] | |
10134 | "TARGET_32BIT" | |
10135 | " | |
10136 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10137 | |
cccf3bdc DE |
10138 | (define_expand "call_indirect_aix64" |
10139 | [(set (match_dup 2) | |
10140 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
10141 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10142 | (reg:DI 2)) | |
10143 | (set (reg:DI 2) | |
10144 | (mem:DI (plus:DI (match_dup 0) | |
10145 | (const_int 8)))) | |
10146 | (set (reg:DI 11) | |
10147 | (mem:DI (plus:DI (match_dup 0) | |
10148 | (const_int 16)))) | |
10149 | (parallel [(call (mem:SI (match_dup 2)) | |
10150 | (match_operand 1 "" "")) | |
10151 | (use (reg:DI 2)) | |
10152 | (use (reg:DI 11)) | |
10153 | (set (reg:DI 2) | |
10154 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10155 | (clobber (scratch:SI))])] | |
10156 | "TARGET_64BIT" | |
10157 | " | |
10158 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 10159 | |
cccf3bdc DE |
10160 | (define_expand "call_value_indirect_aix32" |
10161 | [(set (match_dup 3) | |
10162 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10163 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10164 | (reg:SI 2)) | |
10165 | (set (reg:SI 2) | |
10166 | (mem:SI (plus:SI (match_dup 1) | |
10167 | (const_int 4)))) | |
10168 | (set (reg:SI 11) | |
10169 | (mem:SI (plus:SI (match_dup 1) | |
10170 | (const_int 8)))) | |
10171 | (parallel [(set (match_operand 0 "" "") | |
10172 | (call (mem:SI (match_dup 3)) | |
10173 | (match_operand 2 "" ""))) | |
10174 | (use (reg:SI 2)) | |
10175 | (use (reg:SI 11)) | |
10176 | (set (reg:SI 2) | |
10177 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10178 | (clobber (scratch:SI))])] | |
10179 | "TARGET_32BIT" | |
10180 | " | |
10181 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10182 | |
cccf3bdc DE |
10183 | (define_expand "call_value_indirect_aix64" |
10184 | [(set (match_dup 3) | |
10185 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10186 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10187 | (reg:DI 2)) | |
10188 | (set (reg:DI 2) | |
10189 | (mem:DI (plus:DI (match_dup 1) | |
10190 | (const_int 8)))) | |
10191 | (set (reg:DI 11) | |
10192 | (mem:DI (plus:DI (match_dup 1) | |
10193 | (const_int 16)))) | |
10194 | (parallel [(set (match_operand 0 "" "") | |
10195 | (call (mem:SI (match_dup 3)) | |
10196 | (match_operand 2 "" ""))) | |
10197 | (use (reg:DI 2)) | |
10198 | (use (reg:DI 11)) | |
10199 | (set (reg:DI 2) | |
10200 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10201 | (clobber (scratch:SI))])] | |
10202 | "TARGET_64BIT" | |
10203 | " | |
10204 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 10205 | |
b6c9286a | 10206 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 10207 | (define_expand "call" |
a260abc9 | 10208 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 10209 | (match_operand 1 "" "")) |
4697a36c | 10210 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
10211 | (clobber (scratch:SI))])] |
10212 | "" | |
10213 | " | |
10214 | { | |
ee890fe2 | 10215 | #if TARGET_MACHO |
ab82a49f | 10216 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10217 | operands[0] = machopic_indirect_call_target (operands[0]); |
10218 | #endif | |
10219 | ||
1fd4e8c1 RK |
10220 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
10221 | abort (); | |
10222 | ||
10223 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 10224 | |
6a4cee5f | 10225 | if (GET_CODE (operands[0]) != SYMBOL_REF |
473f51b6 | 10226 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) |
efdba735 | 10227 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10228 | { |
6a4cee5f MM |
10229 | if (INTVAL (operands[2]) & CALL_LONG) |
10230 | operands[0] = rs6000_longcall_ref (operands[0]); | |
10231 | ||
cccf3bdc | 10232 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10233 | || DEFAULT_ABI == ABI_DARWIN) |
bbf294a5 | 10234 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10235 | |
cccf3bdc DE |
10236 | else if (DEFAULT_ABI == ABI_AIX) |
10237 | { | |
10238 | /* AIX function pointers are really pointers to a three word | |
10239 | area. */ | |
10240 | emit_call_insn (TARGET_32BIT | |
10241 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
10242 | operands[0]), | |
10243 | operands[1]) | |
10244 | : gen_call_indirect_aix64 (force_reg (DImode, | |
10245 | operands[0]), | |
10246 | operands[1])); | |
10247 | DONE; | |
b6c9286a | 10248 | } |
cccf3bdc DE |
10249 | else |
10250 | abort (); | |
1fd4e8c1 RK |
10251 | } |
10252 | }") | |
10253 | ||
10254 | (define_expand "call_value" | |
10255 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 10256 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 10257 | (match_operand 2 "" ""))) |
4697a36c | 10258 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
10259 | (clobber (scratch:SI))])] |
10260 | "" | |
10261 | " | |
10262 | { | |
ee890fe2 | 10263 | #if TARGET_MACHO |
ab82a49f | 10264 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10265 | operands[1] = machopic_indirect_call_target (operands[1]); |
10266 | #endif | |
10267 | ||
1fd4e8c1 RK |
10268 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
10269 | abort (); | |
10270 | ||
10271 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 10272 | |
6a4cee5f | 10273 | if (GET_CODE (operands[1]) != SYMBOL_REF |
473f51b6 | 10274 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) |
efdba735 | 10275 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10276 | { |
6756293c | 10277 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
10278 | operands[1] = rs6000_longcall_ref (operands[1]); |
10279 | ||
cccf3bdc | 10280 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10281 | || DEFAULT_ABI == ABI_DARWIN) |
bbf294a5 | 10282 | operands[1] = force_reg (Pmode, operands[1]); |
1fd4e8c1 | 10283 | |
cccf3bdc DE |
10284 | else if (DEFAULT_ABI == ABI_AIX) |
10285 | { | |
10286 | /* AIX function pointers are really pointers to a three word | |
10287 | area. */ | |
10288 | emit_call_insn (TARGET_32BIT | |
10289 | ? gen_call_value_indirect_aix32 (operands[0], | |
10290 | force_reg (SImode, | |
10291 | operands[1]), | |
10292 | operands[2]) | |
10293 | : gen_call_value_indirect_aix64 (operands[0], | |
10294 | force_reg (DImode, | |
10295 | operands[1]), | |
10296 | operands[2])); | |
10297 | DONE; | |
b6c9286a | 10298 | } |
cccf3bdc DE |
10299 | else |
10300 | abort (); | |
1fd4e8c1 RK |
10301 | } |
10302 | }") | |
10303 | ||
04780ee7 | 10304 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 10305 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10306 | ;; either the function was not prototyped, or it was prototyped as a |
10307 | ;; variable argument function. It is > 0 if FP registers were passed | |
10308 | ;; and < 0 if they were not. | |
04780ee7 | 10309 | |
a260abc9 | 10310 | (define_insn "*call_local32" |
4697a36c MM |
10311 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
10312 | (match_operand 1 "" "g,g")) | |
10313 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10314 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 10315 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
10316 | "* |
10317 | { | |
6a4cee5f MM |
10318 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
10319 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10320 | ||
10321 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10322 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 10323 | |
a226df46 | 10324 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 10325 | }" |
b7ff3d82 DE |
10326 | [(set_attr "type" "branch") |
10327 | (set_attr "length" "4,8")]) | |
04780ee7 | 10328 | |
a260abc9 DE |
10329 | (define_insn "*call_local64" |
10330 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10331 | (match_operand 1 "" "g,g")) | |
10332 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10333 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10334 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10335 | "* | |
10336 | { | |
10337 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10338 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10339 | ||
10340 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10341 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10342 | ||
10343 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
10344 | }" | |
10345 | [(set_attr "type" "branch") | |
10346 | (set_attr "length" "4,8")]) | |
10347 | ||
cccf3bdc | 10348 | (define_insn "*call_value_local32" |
d18dba68 | 10349 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10350 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
10351 | (match_operand 2 "" "g,g"))) | |
10352 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10353 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10354 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10355 | "* | |
10356 | { | |
10357 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10358 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10359 | ||
10360 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10361 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10362 | ||
10363 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10364 | }" | |
10365 | [(set_attr "type" "branch") | |
10366 | (set_attr "length" "4,8")]) | |
10367 | ||
10368 | ||
cccf3bdc | 10369 | (define_insn "*call_value_local64" |
d18dba68 | 10370 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10371 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
10372 | (match_operand 2 "" "g,g"))) | |
10373 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10374 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10375 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10376 | "* | |
10377 | { | |
10378 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10379 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10380 | ||
10381 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10382 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10383 | ||
10384 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10385 | }" | |
10386 | [(set_attr "type" "branch") | |
10387 | (set_attr "length" "4,8")]) | |
10388 | ||
04780ee7 | 10389 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 10390 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 10391 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10392 | ;; either the function was not prototyped, or it was prototyped as a |
10393 | ;; variable argument function. It is > 0 if FP registers were passed | |
10394 | ;; and < 0 if they were not. | |
04780ee7 | 10395 | |
cccf3bdc DE |
10396 | (define_insn "*call_indirect_nonlocal_aix32" |
10397 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
10398 | (match_operand 1 "" "g")) | |
10399 | (use (reg:SI 2)) | |
10400 | (use (reg:SI 11)) | |
10401 | (set (reg:SI 2) | |
10402 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 10403 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10404 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10405 | "b%T0l\;{l|lwz} 2,20(1)" | |
10406 | [(set_attr "type" "jmpreg") | |
10407 | (set_attr "length" "8")]) | |
10408 | ||
a260abc9 | 10409 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10410 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10411 | (match_operand 1 "" "g")) |
10412 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10413 | (clobber (match_scratch:SI 3 "=l"))] | |
10414 | "TARGET_32BIT | |
10415 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10416 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10417 | "bl %z0\;%." |
b7ff3d82 | 10418 | [(set_attr "type" "branch") |
cccf3bdc DE |
10419 | (set_attr "length" "8")]) |
10420 | ||
10421 | (define_insn "*call_indirect_nonlocal_aix64" | |
10422 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
10423 | (match_operand 1 "" "g")) | |
10424 | (use (reg:DI 2)) | |
10425 | (use (reg:DI 11)) | |
10426 | (set (reg:DI 2) | |
10427 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 10428 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10429 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10430 | "b%T0l\;ld 2,40(1)" | |
10431 | [(set_attr "type" "jmpreg") | |
10432 | (set_attr "length" "8")]) | |
59313e4e | 10433 | |
a260abc9 | 10434 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10435 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10436 | (match_operand 1 "" "g")) |
10437 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10438 | (clobber (match_scratch:SI 3 "=l"))] | |
6ae08853 | 10439 | "TARGET_64BIT |
9ebbca7d | 10440 | && DEFAULT_ABI == ABI_AIX |
a260abc9 | 10441 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10442 | "bl %z0\;%." |
a260abc9 | 10443 | [(set_attr "type" "branch") |
cccf3bdc | 10444 | (set_attr "length" "8")]) |
7509c759 | 10445 | |
cccf3bdc | 10446 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10447 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10448 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
10449 | (match_operand 2 "" "g"))) | |
10450 | (use (reg:SI 2)) | |
10451 | (use (reg:SI 11)) | |
10452 | (set (reg:SI 2) | |
10453 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10454 | (clobber (match_scratch:SI 3 "=l"))] | |
10455 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
10456 | "b%T1l\;{l|lwz} 2,20(1)" | |
10457 | [(set_attr "type" "jmpreg") | |
10458 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10459 | |
cccf3bdc | 10460 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10461 | [(set (match_operand 0 "" "") |
cc4d5fec | 10462 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10463 | (match_operand 2 "" "g"))) |
10464 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10465 | (clobber (match_scratch:SI 4 "=l"))] | |
10466 | "TARGET_32BIT | |
10467 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10468 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10469 | "bl %z1\;%." |
b7ff3d82 | 10470 | [(set_attr "type" "branch") |
cccf3bdc | 10471 | (set_attr "length" "8")]) |
04780ee7 | 10472 | |
cccf3bdc | 10473 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10474 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10475 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
10476 | (match_operand 2 "" "g"))) | |
10477 | (use (reg:DI 2)) | |
10478 | (use (reg:DI 11)) | |
10479 | (set (reg:DI 2) | |
10480 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10481 | (clobber (match_scratch:SI 3 "=l"))] | |
10482 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
10483 | "b%T1l\;ld 2,40(1)" | |
10484 | [(set_attr "type" "jmpreg") | |
10485 | (set_attr "length" "8")]) | |
10486 | ||
10487 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10488 | [(set (match_operand 0 "" "") |
cc4d5fec | 10489 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10490 | (match_operand 2 "" "g"))) |
10491 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10492 | (clobber (match_scratch:SI 4 "=l"))] | |
6ae08853 | 10493 | "TARGET_64BIT |
9ebbca7d | 10494 | && DEFAULT_ABI == ABI_AIX |
5a19791c | 10495 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10496 | "bl %z1\;%." |
10497 | [(set_attr "type" "branch") | |
10498 | (set_attr "length" "8")]) | |
10499 | ||
10500 | ;; A function pointer under System V is just a normal pointer | |
10501 | ;; operands[0] is the function pointer | |
10502 | ;; operands[1] is the stack size to clean up | |
10503 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10504 | ;; which indicates how to set cr1 | |
10505 | ||
a5c76ee6 ZW |
10506 | (define_insn "*call_indirect_nonlocal_sysv" |
10507 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) | |
10508 | (match_operand 1 "" "g,g")) | |
10509 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10510 | (clobber (match_scratch:SI 3 "=l,l"))] | |
50d440bc | 10511 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10512 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10513 | { |
cccf3bdc | 10514 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10515 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10516 | |
cccf3bdc | 10517 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10518 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10519 | |
a5c76ee6 ZW |
10520 | return "b%T0l"; |
10521 | } | |
10522 | [(set_attr "type" "jmpreg,jmpreg") | |
10523 | (set_attr "length" "4,8")]) | |
cccf3bdc | 10524 | |
a5c76ee6 ZW |
10525 | (define_insn "*call_nonlocal_sysv" |
10526 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10527 | (match_operand 1 "" "g,g")) | |
10528 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10529 | (clobber (match_scratch:SI 3 "=l,l"))] | |
efdba735 SH |
10530 | "(DEFAULT_ABI == ABI_DARWIN |
10531 | || (DEFAULT_ABI == ABI_V4 | |
10532 | && (INTVAL (operands[2]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10533 | { |
10534 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10535 | output_asm_insn ("crxor 6,6,6", operands); | |
10536 | ||
10537 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10538 | output_asm_insn ("creqv 6,6,6", operands); | |
10539 | ||
c989f2f7 | 10540 | #if TARGET_MACHO |
efdba735 SH |
10541 | return output_call(insn, operands, 0, 2); |
10542 | #else | |
a5c76ee6 | 10543 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; |
6ae08853 | 10544 | #endif |
a5c76ee6 ZW |
10545 | } |
10546 | [(set_attr "type" "branch,branch") | |
10547 | (set_attr "length" "4,8")]) | |
10548 | ||
10549 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10550 | [(set (match_operand 0 "" "") |
a5c76ee6 ZW |
10551 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) |
10552 | (match_operand 2 "" "g,g"))) | |
10553 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10554 | (clobber (match_scratch:SI 4 "=l,l"))] | |
50d440bc | 10555 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10556 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10557 | { |
6a4cee5f | 10558 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10559 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10560 | |
10561 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10562 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10563 | |
a5c76ee6 ZW |
10564 | return "b%T1l"; |
10565 | } | |
10566 | [(set_attr "type" "jmpreg,jmpreg") | |
10567 | (set_attr "length" "4,8")]) | |
10568 | ||
10569 | (define_insn "*call_value_nonlocal_sysv" | |
10570 | [(set (match_operand 0 "" "") | |
10571 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10572 | (match_operand 2 "" "g,g"))) | |
10573 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10574 | (clobber (match_scratch:SI 4 "=l,l"))] | |
efdba735 SH |
10575 | "(DEFAULT_ABI == ABI_DARWIN |
10576 | || (DEFAULT_ABI == ABI_V4 | |
10577 | && (INTVAL (operands[3]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10578 | { |
10579 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10580 | output_asm_insn ("crxor 6,6,6", operands); | |
10581 | ||
10582 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10583 | output_asm_insn ("creqv 6,6,6", operands); | |
10584 | ||
c989f2f7 | 10585 | #if TARGET_MACHO |
efdba735 SH |
10586 | return output_call(insn, operands, 1, 3); |
10587 | #else | |
a5c76ee6 | 10588 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; |
6ae08853 | 10589 | #endif |
a5c76ee6 ZW |
10590 | } |
10591 | [(set_attr "type" "branch,branch") | |
10592 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10593 | |
10594 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10595 | (define_expand "untyped_call" |
10596 | [(parallel [(call (match_operand 0 "" "") | |
10597 | (const_int 0)) | |
10598 | (match_operand 1 "" "") | |
10599 | (match_operand 2 "" "")])] | |
10600 | "" | |
10601 | " | |
10602 | { | |
10603 | int i; | |
10604 | ||
7d70b8b2 | 10605 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10606 | |
10607 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10608 | { | |
10609 | rtx set = XVECEXP (operands[2], 0, i); | |
10610 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10611 | } | |
10612 | ||
10613 | /* The optimizer does not know that the call sets the function value | |
10614 | registers we stored in the result block. We avoid problems by | |
10615 | claiming that all hard registers are used and clobbered at this | |
10616 | point. */ | |
10617 | emit_insn (gen_blockage ()); | |
10618 | ||
10619 | DONE; | |
10620 | }") | |
10621 | ||
5e1bf043 DJ |
10622 | ;; sibling call patterns |
10623 | (define_expand "sibcall" | |
10624 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
10625 | (match_operand 1 "" "")) | |
10626 | (use (match_operand 2 "" "")) | |
fe352c29 | 10627 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
10628 | (return)])] |
10629 | "" | |
10630 | " | |
10631 | { | |
10632 | #if TARGET_MACHO | |
ab82a49f | 10633 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10634 | operands[0] = machopic_indirect_call_target (operands[0]); |
10635 | #endif | |
10636 | ||
10637 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
10638 | abort (); | |
10639 | ||
10640 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 10641 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10642 | |
10643 | }") | |
10644 | ||
10645 | ;; this and similar patterns must be marked as using LR, otherwise | |
10646 | ;; dataflow will try to delete the store into it. This is true | |
10647 | ;; even when the actual reg to jump to is in CTR, when LR was | |
10648 | ;; saved and restored around the PIC-setting BCL. | |
10649 | (define_insn "*sibcall_local32" | |
10650 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
10651 | (match_operand 1 "" "g,g")) | |
10652 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10653 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10654 | (return)] |
10655 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
10656 | "* | |
10657 | { | |
10658 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10659 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10660 | ||
10661 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10662 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10663 | ||
10664 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10665 | }" | |
10666 | [(set_attr "type" "branch") | |
10667 | (set_attr "length" "4,8")]) | |
10668 | ||
10669 | (define_insn "*sibcall_local64" | |
10670 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10671 | (match_operand 1 "" "g,g")) | |
10672 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10673 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10674 | (return)] |
10675 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10676 | "* | |
10677 | { | |
10678 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10679 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10680 | ||
10681 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10682 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10683 | ||
10684 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10685 | }" | |
10686 | [(set_attr "type" "branch") | |
10687 | (set_attr "length" "4,8")]) | |
10688 | ||
10689 | (define_insn "*sibcall_value_local32" | |
10690 | [(set (match_operand 0 "" "") | |
10691 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
10692 | (match_operand 2 "" "g,g"))) | |
10693 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10694 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10695 | (return)] |
10696 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10697 | "* | |
10698 | { | |
10699 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10700 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10701 | ||
10702 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10703 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10704 | ||
10705 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10706 | }" | |
10707 | [(set_attr "type" "branch") | |
10708 | (set_attr "length" "4,8")]) | |
10709 | ||
10710 | ||
10711 | (define_insn "*sibcall_value_local64" | |
10712 | [(set (match_operand 0 "" "") | |
10713 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
10714 | (match_operand 2 "" "g,g"))) | |
10715 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10716 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10717 | (return)] |
10718 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10719 | "* | |
10720 | { | |
10721 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10722 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10723 | ||
10724 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10725 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10726 | ||
10727 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10728 | }" | |
10729 | [(set_attr "type" "branch") | |
10730 | (set_attr "length" "4,8")]) | |
10731 | ||
10732 | (define_insn "*sibcall_nonlocal_aix32" | |
10733 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
10734 | (match_operand 1 "" "g")) | |
10735 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10736 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10737 | (return)] |
10738 | "TARGET_32BIT | |
10739 | && DEFAULT_ABI == ABI_AIX | |
10740 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10741 | "b %z0" | |
10742 | [(set_attr "type" "branch") | |
10743 | (set_attr "length" "4")]) | |
10744 | ||
10745 | (define_insn "*sibcall_nonlocal_aix64" | |
10746 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
10747 | (match_operand 1 "" "g")) | |
10748 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10749 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 | 10750 | (return)] |
6ae08853 | 10751 | "TARGET_64BIT |
5e1bf043 DJ |
10752 | && DEFAULT_ABI == ABI_AIX |
10753 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10754 | "b %z0" | |
10755 | [(set_attr "type" "branch") | |
10756 | (set_attr "length" "4")]) | |
10757 | ||
10758 | (define_insn "*sibcall_value_nonlocal_aix32" | |
10759 | [(set (match_operand 0 "" "") | |
10760 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
10761 | (match_operand 2 "" "g"))) | |
10762 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10763 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10764 | (return)] |
10765 | "TARGET_32BIT | |
10766 | && DEFAULT_ABI == ABI_AIX | |
10767 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10768 | "b %z1" | |
10769 | [(set_attr "type" "branch") | |
10770 | (set_attr "length" "4")]) | |
10771 | ||
10772 | (define_insn "*sibcall_value_nonlocal_aix64" | |
10773 | [(set (match_operand 0 "" "") | |
10774 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
10775 | (match_operand 2 "" "g"))) | |
10776 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10777 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 | 10778 | (return)] |
6ae08853 | 10779 | "TARGET_64BIT |
5e1bf043 DJ |
10780 | && DEFAULT_ABI == ABI_AIX |
10781 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10782 | "b %z1" | |
10783 | [(set_attr "type" "branch") | |
10784 | (set_attr "length" "4")]) | |
10785 | ||
10786 | (define_insn "*sibcall_nonlocal_sysv" | |
10787 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10788 | (match_operand 1 "" "")) | |
10789 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 10790 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10791 | (return)] |
10792 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10793 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10794 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
10795 | "* | |
10796 | { | |
10797 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10798 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10799 | ||
10800 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10801 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10802 | ||
10803 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; | |
10804 | }" | |
10805 | [(set_attr "type" "branch,branch") | |
10806 | (set_attr "length" "4,8")]) | |
10807 | ||
10808 | (define_expand "sibcall_value" | |
10809 | [(parallel [(set (match_operand 0 "register_operand" "") | |
10810 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
10811 | (match_operand 2 "" ""))) | |
10812 | (use (match_operand 3 "" "")) | |
fe352c29 | 10813 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
10814 | (return)])] |
10815 | "" | |
10816 | " | |
10817 | { | |
10818 | #if TARGET_MACHO | |
ab82a49f | 10819 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10820 | operands[1] = machopic_indirect_call_target (operands[1]); |
10821 | #endif | |
10822 | ||
10823 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
10824 | abort (); | |
10825 | ||
10826 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 10827 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10828 | |
10829 | }") | |
10830 | ||
10831 | (define_insn "*sibcall_value_nonlocal_sysv" | |
10832 | [(set (match_operand 0 "" "") | |
10833 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10834 | (match_operand 2 "" ""))) | |
10835 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10836 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10837 | (return)] |
10838 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10839 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10840 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
10841 | "* | |
10842 | { | |
10843 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10844 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10845 | ||
10846 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10847 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10848 | ||
10849 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; | |
10850 | }" | |
10851 | [(set_attr "type" "branch,branch") | |
10852 | (set_attr "length" "4,8")]) | |
10853 | ||
10854 | (define_expand "sibcall_epilogue" | |
10855 | [(use (const_int 0))] | |
10856 | "TARGET_SCHED_PROLOG" | |
10857 | " | |
10858 | { | |
10859 | rs6000_emit_epilogue (TRUE); | |
10860 | DONE; | |
10861 | }") | |
10862 | ||
e6f948e3 RK |
10863 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
10864 | ;; all of memory. This blocks insns from being moved across this point. | |
10865 | ||
10866 | (define_insn "blockage" | |
615158e2 | 10867 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] |
e6f948e3 RK |
10868 | "" |
10869 | "") | |
1fd4e8c1 RK |
10870 | \f |
10871 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10872 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10873 | ;; |
10874 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10875 | ;; insns, and branches. We store the operands of compares until we see | |
10876 | ;; how it is used. | |
10877 | (define_expand "cmpsi" | |
10878 | [(set (cc0) | |
cd2b37d9 | 10879 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10880 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10881 | "" | |
10882 | " | |
10883 | { | |
10884 | /* Take care of the possibility that operands[1] might be negative but | |
10885 | this might be a logical operation. That insn doesn't exist. */ | |
10886 | if (GET_CODE (operands[1]) == CONST_INT | |
10887 | && INTVAL (operands[1]) < 0) | |
10888 | operands[1] = force_reg (SImode, operands[1]); | |
10889 | ||
10890 | rs6000_compare_op0 = operands[0]; | |
10891 | rs6000_compare_op1 = operands[1]; | |
10892 | rs6000_compare_fp_p = 0; | |
10893 | DONE; | |
10894 | }") | |
10895 | ||
266eb58a DE |
10896 | (define_expand "cmpdi" |
10897 | [(set (cc0) | |
10898 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10899 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10900 | "TARGET_POWERPC64" | |
10901 | " | |
10902 | { | |
10903 | /* Take care of the possibility that operands[1] might be negative but | |
10904 | this might be a logical operation. That insn doesn't exist. */ | |
10905 | if (GET_CODE (operands[1]) == CONST_INT | |
10906 | && INTVAL (operands[1]) < 0) | |
10907 | operands[1] = force_reg (DImode, operands[1]); | |
10908 | ||
10909 | rs6000_compare_op0 = operands[0]; | |
10910 | rs6000_compare_op1 = operands[1]; | |
10911 | rs6000_compare_fp_p = 0; | |
10912 | DONE; | |
10913 | }") | |
10914 | ||
1fd4e8c1 | 10915 | (define_expand "cmpsf" |
cd2b37d9 RK |
10916 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
10917 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10918 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10919 | " |
10920 | { | |
10921 | rs6000_compare_op0 = operands[0]; | |
10922 | rs6000_compare_op1 = operands[1]; | |
10923 | rs6000_compare_fp_p = 1; | |
10924 | DONE; | |
10925 | }") | |
10926 | ||
10927 | (define_expand "cmpdf" | |
cd2b37d9 RK |
10928 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
10929 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
7a2f7870 | 10930 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
1fd4e8c1 RK |
10931 | " |
10932 | { | |
10933 | rs6000_compare_op0 = operands[0]; | |
10934 | rs6000_compare_op1 = operands[1]; | |
10935 | rs6000_compare_fp_p = 1; | |
10936 | DONE; | |
10937 | }") | |
10938 | ||
d6f99ca4 | 10939 | (define_expand "cmptf" |
e7a4130e DE |
10940 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
10941 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
39e63627 GK |
10942 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
10943 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
d6f99ca4 DE |
10944 | " |
10945 | { | |
10946 | rs6000_compare_op0 = operands[0]; | |
10947 | rs6000_compare_op1 = operands[1]; | |
10948 | rs6000_compare_fp_p = 1; | |
10949 | DONE; | |
10950 | }") | |
10951 | ||
1fd4e8c1 | 10952 | (define_expand "beq" |
39a10a29 | 10953 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10954 | "" |
39a10a29 | 10955 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10956 | |
10957 | (define_expand "bne" | |
39a10a29 | 10958 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10959 | "" |
39a10a29 | 10960 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 10961 | |
39a10a29 GK |
10962 | (define_expand "bge" |
10963 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10964 | "" |
39a10a29 | 10965 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
10966 | |
10967 | (define_expand "bgt" | |
39a10a29 | 10968 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10969 | "" |
39a10a29 | 10970 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
10971 | |
10972 | (define_expand "ble" | |
39a10a29 | 10973 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10974 | "" |
39a10a29 | 10975 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 10976 | |
39a10a29 GK |
10977 | (define_expand "blt" |
10978 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10979 | "" |
39a10a29 | 10980 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 10981 | |
39a10a29 GK |
10982 | (define_expand "bgeu" |
10983 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10984 | "" |
39a10a29 | 10985 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 10986 | |
39a10a29 GK |
10987 | (define_expand "bgtu" |
10988 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10989 | "" |
39a10a29 | 10990 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10991 | |
39a10a29 GK |
10992 | (define_expand "bleu" |
10993 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10994 | "" |
39a10a29 | 10995 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 10996 | |
39a10a29 GK |
10997 | (define_expand "bltu" |
10998 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10999 | "" |
39a10a29 | 11000 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11001 | |
1c882ea4 | 11002 | (define_expand "bunordered" |
39a10a29 | 11003 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 11004 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 11005 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11006 | |
11007 | (define_expand "bordered" | |
39a10a29 | 11008 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 11009 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 11010 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11011 | |
11012 | (define_expand "buneq" | |
39a10a29 | 11013 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11014 | "" |
39a10a29 | 11015 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
11016 | |
11017 | (define_expand "bunge" | |
39a10a29 | 11018 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11019 | "" |
39a10a29 | 11020 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
11021 | |
11022 | (define_expand "bungt" | |
39a10a29 | 11023 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11024 | "" |
39a10a29 | 11025 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
11026 | |
11027 | (define_expand "bunle" | |
39a10a29 | 11028 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11029 | "" |
39a10a29 | 11030 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
11031 | |
11032 | (define_expand "bunlt" | |
39a10a29 | 11033 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11034 | "" |
39a10a29 | 11035 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
11036 | |
11037 | (define_expand "bltgt" | |
39a10a29 | 11038 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11039 | "" |
39a10a29 | 11040 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 11041 | |
1fd4e8c1 RK |
11042 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
11043 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
11044 | ;; with an scc insns. However, due to the order that combine see the | |
11045 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
11046 | ;; the cases we don't want to handle. | |
11047 | (define_expand "seq" | |
39a10a29 | 11048 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11049 | "" |
39a10a29 | 11050 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11051 | |
11052 | (define_expand "sne" | |
39a10a29 | 11053 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11054 | "" |
11055 | " | |
6ae08853 | 11056 | { |
39a10a29 | 11057 | if (! rs6000_compare_fp_p) |
1fd4e8c1 RK |
11058 | FAIL; |
11059 | ||
6ae08853 | 11060 | rs6000_emit_sCOND (NE, operands[0]); |
39a10a29 | 11061 | DONE; |
1fd4e8c1 RK |
11062 | }") |
11063 | ||
b7053a3f GK |
11064 | ;; A >= 0 is best done the portable way for A an integer. |
11065 | (define_expand "sge" | |
39a10a29 | 11066 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11067 | "" |
11068 | " | |
5638268e | 11069 | { |
e56d7409 | 11070 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
11071 | FAIL; |
11072 | ||
b7053a3f | 11073 | rs6000_emit_sCOND (GE, operands[0]); |
39a10a29 | 11074 | DONE; |
1fd4e8c1 RK |
11075 | }") |
11076 | ||
b7053a3f GK |
11077 | ;; A > 0 is best done using the portable sequence, so fail in that case. |
11078 | (define_expand "sgt" | |
39a10a29 | 11079 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11080 | "" |
11081 | " | |
5638268e | 11082 | { |
e56d7409 | 11083 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
11084 | FAIL; |
11085 | ||
6ae08853 | 11086 | rs6000_emit_sCOND (GT, operands[0]); |
39a10a29 | 11087 | DONE; |
1fd4e8c1 RK |
11088 | }") |
11089 | ||
b7053a3f GK |
11090 | ;; A <= 0 is best done the portable way for A an integer. |
11091 | (define_expand "sle" | |
39a10a29 | 11092 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11093 | "" |
5638268e DE |
11094 | " |
11095 | { | |
e56d7409 | 11096 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
5638268e DE |
11097 | FAIL; |
11098 | ||
6ae08853 | 11099 | rs6000_emit_sCOND (LE, operands[0]); |
5638268e DE |
11100 | DONE; |
11101 | }") | |
1fd4e8c1 | 11102 | |
b7053a3f GK |
11103 | ;; A < 0 is best done in the portable way for A an integer. |
11104 | (define_expand "slt" | |
39a10a29 | 11105 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11106 | "" |
11107 | " | |
5638268e | 11108 | { |
e56d7409 | 11109 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
11110 | FAIL; |
11111 | ||
6ae08853 | 11112 | rs6000_emit_sCOND (LT, operands[0]); |
39a10a29 | 11113 | DONE; |
1fd4e8c1 RK |
11114 | }") |
11115 | ||
b7053a3f GK |
11116 | (define_expand "sgeu" |
11117 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11118 | "" | |
11119 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") | |
11120 | ||
1fd4e8c1 | 11121 | (define_expand "sgtu" |
39a10a29 | 11122 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11123 | "" |
39a10a29 | 11124 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 11125 | |
b7053a3f GK |
11126 | (define_expand "sleu" |
11127 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11128 | "" | |
11129 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") | |
11130 | ||
1fd4e8c1 | 11131 | (define_expand "sltu" |
39a10a29 | 11132 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11133 | "" |
39a10a29 | 11134 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11135 | |
b7053a3f | 11136 | (define_expand "sunordered" |
39a10a29 | 11137 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
7836a61f | 11138 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
b7053a3f | 11139 | "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") |
1fd4e8c1 | 11140 | |
b7053a3f | 11141 | (define_expand "sordered" |
39a10a29 | 11142 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
7836a61f | 11143 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
b7053a3f GK |
11144 | "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") |
11145 | ||
11146 | (define_expand "suneq" | |
11147 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11148 | "" | |
11149 | "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") | |
11150 | ||
11151 | (define_expand "sunge" | |
11152 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11153 | "" | |
11154 | "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") | |
11155 | ||
11156 | (define_expand "sungt" | |
11157 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11158 | "" | |
11159 | "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") | |
11160 | ||
11161 | (define_expand "sunle" | |
11162 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11163 | "" | |
11164 | "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") | |
11165 | ||
11166 | (define_expand "sunlt" | |
11167 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11168 | "" | |
11169 | "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") | |
11170 | ||
11171 | (define_expand "sltgt" | |
11172 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11173 | "" | |
11174 | "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") | |
11175 | ||
1fd4e8c1 RK |
11176 | \f |
11177 | ;; Here are the actual compare insns. | |
acad7ed3 | 11178 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 11179 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11180 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
11181 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
11182 | "" | |
7f340546 | 11183 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
b54cf83a | 11184 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11185 | |
acad7ed3 | 11186 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
11187 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
11188 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
11189 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11190 | "TARGET_POWERPC64" | |
11191 | "cmpd%I2 %0,%1,%2" | |
b54cf83a | 11192 | [(set_attr "type" "cmp")]) |
266eb58a | 11193 | |
f357808b RK |
11194 | ;; If we are comparing a register for equality with a large constant, |
11195 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
11196 | ;; register for the result of the XOR. | |
11197 | ||
11198 | (define_split | |
11199 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 11200 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 11201 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 11202 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
11203 | "find_single_use (operands[0], insn, 0) |
11204 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
11205 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
11206 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
11207 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
11208 | " | |
11209 | { | |
11210 | /* Get the constant we are comparing against, C, and see what it looks like | |
11211 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
11212 | with C to get the sign-extended value. */ | |
11213 | ||
5f59ecb7 | 11214 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 11215 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 11216 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 11217 | |
89e9f3a8 MM |
11218 | operands[4] = GEN_INT (xorv); |
11219 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
11220 | }") |
11221 | ||
acad7ed3 | 11222 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 11223 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11224 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 11225 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 11226 | "" |
e2c953b6 | 11227 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
b54cf83a | 11228 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11229 | |
acad7ed3 | 11230 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
11231 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
11232 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 11233 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 11234 | "" |
e2c953b6 | 11235 | "cmpld%I2 %0,%1,%b2" |
b54cf83a | 11236 | [(set_attr "type" "cmp")]) |
266eb58a | 11237 | |
1fd4e8c1 RK |
11238 | ;; The following two insns don't exist as single insns, but if we provide |
11239 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
11240 | ;; of the required delay between a compare and branch. We generate code for | |
11241 | ;; them by splitting. | |
11242 | ||
11243 | (define_insn "" | |
11244 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11245 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11246 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 11247 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11248 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11249 | "" | |
baf97f86 RK |
11250 | "#" |
11251 | [(set_attr "length" "8")]) | |
7e69e155 | 11252 | |
1fd4e8c1 RK |
11253 | (define_insn "" |
11254 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11255 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11256 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 11257 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11258 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11259 | "" | |
baf97f86 RK |
11260 | "#" |
11261 | [(set_attr "length" "8")]) | |
7e69e155 | 11262 | |
1fd4e8c1 RK |
11263 | (define_split |
11264 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 11265 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11266 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 11267 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11268 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11269 | "" | |
11270 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
11271 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11272 | ||
11273 | (define_split | |
11274 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 11275 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11276 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 11277 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11278 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11279 | "" | |
11280 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
11281 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11282 | ||
acad7ed3 | 11283 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 11284 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11285 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
11286 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11287 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11288 | "fcmpu %0,%1,%2" |
11289 | [(set_attr "type" "fpcompare")]) | |
11290 | ||
acad7ed3 | 11291 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 11292 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11293 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
11294 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11295 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11296 | "fcmpu %0,%1,%2" |
11297 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
11298 | |
11299 | ;; Only need to compare second words if first words equal | |
11300 | (define_insn "*cmptf_internal1" | |
11301 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11302 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11303 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
39e63627 GK |
11304 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
11305 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 | 11306 | "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
11307 | [(set_attr "type" "fpcompare") |
11308 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11309 | \f |
11310 | ;; Now we have the scc insns. We can do some combinations because of the | |
11311 | ;; way the machine works. | |
11312 | ;; | |
11313 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
11314 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
11315 | ;; cases the insns below which don't use an intermediate CR field will | |
11316 | ;; be used instead. | |
1fd4e8c1 | 11317 | (define_insn "" |
cd2b37d9 | 11318 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11319 | (match_operator:SI 1 "scc_comparison_operator" |
11320 | [(match_operand 2 "cc_reg_operand" "y") | |
11321 | (const_int 0)]))] | |
11322 | "" | |
2c4a9cff DE |
11323 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11324 | [(set (attr "type") | |
11325 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11326 | (const_string "mfcrf") | |
11327 | ] | |
11328 | (const_string "mfcr"))) | |
c1618c0c | 11329 | (set_attr "length" "8")]) |
1fd4e8c1 | 11330 | |
423c1189 | 11331 | ;; Same as above, but get the GT bit. |
6b1fedc3 | 11332 | (define_insn "move_from_CR_eq_bit" |
423c1189 | 11333 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6b1fedc3 | 11334 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))] |
423c1189 AH |
11335 | "TARGET_E500" |
11336 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1" | |
11337 | [(set_attr "type" "mfcr") | |
c1618c0c | 11338 | (set_attr "length" "8")]) |
423c1189 | 11339 | |
a3170dc6 AH |
11340 | ;; Same as above, but get the OV/ORDERED bit. |
11341 | (define_insn "move_from_CR_ov_bit" | |
11342 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
615158e2 | 11343 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] |
a3170dc6 | 11344 | "TARGET_ISEL" |
b7053a3f | 11345 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" |
b54cf83a | 11346 | [(set_attr "type" "mfcr") |
c1618c0c | 11347 | (set_attr "length" "8")]) |
a3170dc6 | 11348 | |
1fd4e8c1 | 11349 | (define_insn "" |
9ebbca7d GK |
11350 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11351 | (match_operator:DI 1 "scc_comparison_operator" | |
11352 | [(match_operand 2 "cc_reg_operand" "y") | |
11353 | (const_int 0)]))] | |
11354 | "TARGET_POWERPC64" | |
2c4a9cff DE |
11355 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11356 | [(set (attr "type") | |
11357 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11358 | (const_string "mfcrf") | |
11359 | ] | |
11360 | (const_string "mfcr"))) | |
c1618c0c | 11361 | (set_attr "length" "8")]) |
9ebbca7d GK |
11362 | |
11363 | (define_insn "" | |
11364 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11365 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 11366 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
11367 | (const_int 0)]) |
11368 | (const_int 0))) | |
9ebbca7d | 11369 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11370 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
4b8a63d6 | 11371 | "TARGET_32BIT" |
9ebbca7d | 11372 | "@ |
2c4a9cff | 11373 | mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 |
9ebbca7d | 11374 | #" |
b19003d8 | 11375 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11376 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11377 | |
11378 | (define_split | |
11379 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11380 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11381 | [(match_operand 2 "cc_reg_operand" "") | |
11382 | (const_int 0)]) | |
11383 | (const_int 0))) | |
11384 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11385 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
4b8a63d6 | 11386 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11387 | [(set (match_dup 3) |
11388 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11389 | (set (match_dup 0) | |
11390 | (compare:CC (match_dup 3) | |
11391 | (const_int 0)))] | |
11392 | "") | |
1fd4e8c1 RK |
11393 | |
11394 | (define_insn "" | |
cd2b37d9 | 11395 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11396 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11397 | [(match_operand 2 "cc_reg_operand" "y") | |
11398 | (const_int 0)]) | |
11399 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11400 | "" | |
11401 | "* | |
11402 | { | |
11403 | int is_bit = ccr_bit (operands[1], 1); | |
11404 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11405 | int count; | |
11406 | ||
11407 | if (is_bit >= put_bit) | |
11408 | count = is_bit - put_bit; | |
11409 | else | |
11410 | count = 32 - (put_bit - is_bit); | |
11411 | ||
89e9f3a8 MM |
11412 | operands[4] = GEN_INT (count); |
11413 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11414 | |
2c4a9cff | 11415 | return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11416 | }" |
2c4a9cff DE |
11417 | [(set (attr "type") |
11418 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11419 | (const_string "mfcrf") | |
11420 | ] | |
11421 | (const_string "mfcr"))) | |
c1618c0c | 11422 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
11423 | |
11424 | (define_insn "" | |
9ebbca7d | 11425 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11426 | (compare:CC |
11427 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11428 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11429 | (const_int 0)]) |
9ebbca7d | 11430 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11431 | (const_int 0))) |
9ebbca7d | 11432 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11433 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11434 | (match_dup 3)))] | |
ce71f754 | 11435 | "" |
1fd4e8c1 RK |
11436 | "* |
11437 | { | |
11438 | int is_bit = ccr_bit (operands[1], 1); | |
11439 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11440 | int count; | |
11441 | ||
9ebbca7d GK |
11442 | /* Force split for non-cc0 compare. */ |
11443 | if (which_alternative == 1) | |
11444 | return \"#\"; | |
11445 | ||
1fd4e8c1 RK |
11446 | if (is_bit >= put_bit) |
11447 | count = is_bit - put_bit; | |
11448 | else | |
11449 | count = 32 - (put_bit - is_bit); | |
11450 | ||
89e9f3a8 MM |
11451 | operands[5] = GEN_INT (count); |
11452 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11453 | |
2c4a9cff | 11454 | return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11455 | }" |
b19003d8 | 11456 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11457 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11458 | |
11459 | (define_split | |
11460 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11461 | (compare:CC | |
11462 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11463 | [(match_operand 2 "cc_reg_operand" "") | |
11464 | (const_int 0)]) | |
11465 | (match_operand:SI 3 "const_int_operand" "")) | |
11466 | (const_int 0))) | |
11467 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11468 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11469 | (match_dup 3)))] | |
ce71f754 | 11470 | "reload_completed" |
9ebbca7d GK |
11471 | [(set (match_dup 4) |
11472 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11473 | (match_dup 3))) | |
11474 | (set (match_dup 0) | |
11475 | (compare:CC (match_dup 4) | |
11476 | (const_int 0)))] | |
11477 | "") | |
1fd4e8c1 | 11478 | |
c5defebb RK |
11479 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11480 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11481 | ||
11482 | (define_peephole | |
cd2b37d9 | 11483 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11484 | (match_operator:SI 1 "scc_comparison_operator" |
11485 | [(match_operand 2 "cc_reg_operand" "y") | |
11486 | (const_int 0)])) | |
cd2b37d9 | 11487 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11488 | (match_operator:SI 4 "scc_comparison_operator" |
11489 | [(match_operand 5 "cc_reg_operand" "y") | |
11490 | (const_int 0)]))] | |
309323c2 | 11491 | "REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11492 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11493 | [(set_attr "type" "mfcr") |
c1618c0c | 11494 | (set_attr "length" "12")]) |
c5defebb | 11495 | |
9ebbca7d GK |
11496 | (define_peephole |
11497 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11498 | (match_operator:DI 1 "scc_comparison_operator" | |
11499 | [(match_operand 2 "cc_reg_operand" "y") | |
11500 | (const_int 0)])) | |
11501 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11502 | (match_operator:DI 4 "scc_comparison_operator" | |
11503 | [(match_operand 5 "cc_reg_operand" "y") | |
11504 | (const_int 0)]))] | |
309323c2 | 11505 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11506 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11507 | [(set_attr "type" "mfcr") |
c1618c0c | 11508 | (set_attr "length" "12")]) |
9ebbca7d | 11509 | |
1fd4e8c1 RK |
11510 | ;; There are some scc insns that can be done directly, without a compare. |
11511 | ;; These are faster because they don't involve the communications between | |
11512 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11513 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11514 | ;; | |
11515 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11516 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11517 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11518 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11519 | ||
11520 | ;; Have reload force a constant into a register for the simple insns that | |
11521 | ;; otherwise won't accept constants. We do this because it is faster than | |
11522 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11523 | ||
11524 | (define_insn "" | |
cd2b37d9 RK |
11525 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11526 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11527 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11528 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
683bdff7 | 11529 | "TARGET_32BIT" |
1fd4e8c1 | 11530 | "@ |
ca7f5001 | 11531 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11532 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11533 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11534 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
11535 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
943c15ed DE |
11536 | [(set_attr "type" "three,two,three,three,three") |
11537 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 | 11538 | |
a260abc9 DE |
11539 | (define_insn "" |
11540 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
11541 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
11542 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
11543 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
683bdff7 | 11544 | "TARGET_64BIT" |
a260abc9 DE |
11545 | "@ |
11546 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11547 | subfic %3,%1,0\;adde %0,%3,%1 | |
11548 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11549 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11550 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
943c15ed DE |
11551 | [(set_attr "type" "three,two,three,three,three") |
11552 | (set_attr "length" "12,8,12,12,12")]) | |
a260abc9 | 11553 | |
1fd4e8c1 | 11554 | (define_insn "" |
9ebbca7d | 11555 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11556 | (compare:CC |
9ebbca7d GK |
11557 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11558 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 11559 | (const_int 0))) |
9ebbca7d | 11560 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11561 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11562 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11563 | "TARGET_32BIT" |
1fd4e8c1 | 11564 | "@ |
ca7f5001 RK |
11565 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11566 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
11567 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
11568 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
11569 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11570 | # | |
11571 | # | |
11572 | # | |
11573 | # | |
11574 | #" | |
b19003d8 | 11575 | [(set_attr "type" "compare") |
9ebbca7d GK |
11576 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11577 | ||
11578 | (define_split | |
11579 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11580 | (compare:CC | |
11581 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11582 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11583 | (const_int 0))) | |
11584 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11585 | (eq:SI (match_dup 1) (match_dup 2))) | |
11586 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11587 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11588 | [(parallel [(set (match_dup 0) |
11589 | (eq:SI (match_dup 1) (match_dup 2))) | |
11590 | (clobber (match_dup 3))]) | |
11591 | (set (match_dup 4) | |
11592 | (compare:CC (match_dup 0) | |
11593 | (const_int 0)))] | |
11594 | "") | |
b19003d8 | 11595 | |
a260abc9 | 11596 | (define_insn "" |
9ebbca7d | 11597 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 11598 | (compare:CC |
9ebbca7d GK |
11599 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11600 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 11601 | (const_int 0))) |
9ebbca7d | 11602 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 11603 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11604 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11605 | "TARGET_64BIT" |
a260abc9 DE |
11606 | "@ |
11607 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11608 | subfic %3,%1,0\;adde. %0,%3,%1 | |
11609 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11610 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
11611 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
11612 | # | |
11613 | # | |
11614 | # | |
11615 | # | |
11616 | #" | |
a260abc9 | 11617 | [(set_attr "type" "compare") |
9ebbca7d GK |
11618 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11619 | ||
11620 | (define_split | |
11621 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11622 | (compare:CC | |
11623 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11624 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
11625 | (const_int 0))) | |
11626 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11627 | (eq:DI (match_dup 1) (match_dup 2))) | |
11628 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11629 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11630 | [(parallel [(set (match_dup 0) |
11631 | (eq:DI (match_dup 1) (match_dup 2))) | |
11632 | (clobber (match_dup 3))]) | |
11633 | (set (match_dup 4) | |
11634 | (compare:CC (match_dup 0) | |
11635 | (const_int 0)))] | |
11636 | "") | |
a260abc9 | 11637 | |
b19003d8 RK |
11638 | ;; We have insns of the form shown by the first define_insn below. If |
11639 | ;; there is something inside the comparison operation, we must split it. | |
11640 | (define_split | |
11641 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11642 | (plus:SI (match_operator 1 "comparison_operator" | |
11643 | [(match_operand:SI 2 "" "") | |
11644 | (match_operand:SI 3 | |
11645 | "reg_or_cint_operand" "")]) | |
11646 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11647 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11648 | "! gpc_reg_operand (operands[2], SImode)" | |
11649 | [(set (match_dup 5) (match_dup 2)) | |
11650 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11651 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11652 | |
11653 | (define_insn "" | |
5276df18 | 11654 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11655 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11656 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 11657 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
683bdff7 | 11658 | "TARGET_32BIT" |
1fd4e8c1 | 11659 | "@ |
5276df18 DE |
11660 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11661 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11662 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11663 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11664 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
943c15ed DE |
11665 | [(set_attr "type" "three,two,three,three,three") |
11666 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 RK |
11667 | |
11668 | (define_insn "" | |
9ebbca7d | 11669 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11670 | (compare:CC |
1fd4e8c1 | 11671 | (plus:SI |
9ebbca7d GK |
11672 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11673 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11674 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11675 | (const_int 0))) |
9ebbca7d | 11676 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
683bdff7 | 11677 | "TARGET_32BIT" |
1fd4e8c1 | 11678 | "@ |
ca7f5001 | 11679 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11680 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11681 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11682 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11683 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11684 | # | |
11685 | # | |
11686 | # | |
11687 | # | |
11688 | #" | |
b19003d8 | 11689 | [(set_attr "type" "compare") |
9ebbca7d GK |
11690 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11691 | ||
11692 | (define_split | |
11693 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11694 | (compare:CC | |
11695 | (plus:SI | |
11696 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11697 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11698 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11699 | (const_int 0))) | |
11700 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11701 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11702 | [(set (match_dup 4) |
11703 | (plus:SI (eq:SI (match_dup 1) | |
11704 | (match_dup 2)) | |
11705 | (match_dup 3))) | |
11706 | (set (match_dup 0) | |
11707 | (compare:CC (match_dup 4) | |
11708 | (const_int 0)))] | |
11709 | "") | |
1fd4e8c1 RK |
11710 | |
11711 | (define_insn "" | |
0387639b | 11712 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11713 | (compare:CC |
1fd4e8c1 | 11714 | (plus:SI |
9ebbca7d GK |
11715 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11716 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11717 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11718 | (const_int 0))) |
0387639b DE |
11719 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11720 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 11721 | "TARGET_32BIT" |
1fd4e8c1 | 11722 | "@ |
0387639b DE |
11723 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11724 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11725 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11726 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11727 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11728 | # |
11729 | # | |
11730 | # | |
11731 | # | |
11732 | #" | |
11733 | [(set_attr "type" "compare") | |
11734 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11735 | ||
11736 | (define_split | |
0387639b | 11737 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11738 | (compare:CC |
11739 | (plus:SI | |
11740 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11741 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11742 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11743 | (const_int 0))) | |
11744 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11745 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 11746 | "TARGET_32BIT && reload_completed" |
0387639b | 11747 | [(set (match_dup 0) |
9ebbca7d | 11748 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11749 | (set (match_dup 4) |
9ebbca7d GK |
11750 | (compare:CC (match_dup 0) |
11751 | (const_int 0)))] | |
11752 | "") | |
11753 | ||
1fd4e8c1 | 11754 | (define_insn "" |
cd2b37d9 | 11755 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11756 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11757 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
683bdff7 | 11758 | "TARGET_32BIT" |
1fd4e8c1 | 11759 | "@ |
ca7f5001 RK |
11760 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11761 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11762 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11763 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11764 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
943c15ed DE |
11765 | [(set_attr "type" "three,two,three,three,three") |
11766 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 | 11767 | |
ea9be077 MM |
11768 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11769 | ;; since it nabs/sr is just as fast. | |
463b558b | 11770 | (define_insn "*ne0" |
b4e95693 | 11771 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11772 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11773 | (const_int 31))) | |
11774 | (clobber (match_scratch:SI 2 "=&r"))] | |
683bdff7 | 11775 | "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" |
ea9be077 | 11776 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
943c15ed DE |
11777 | [(set_attr "type" "two") |
11778 | (set_attr "length" "8")]) | |
ea9be077 | 11779 | |
a260abc9 DE |
11780 | (define_insn "" |
11781 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11782 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11783 | (const_int 63))) | |
11784 | (clobber (match_scratch:DI 2 "=&r"))] | |
683bdff7 | 11785 | "TARGET_64BIT" |
a260abc9 | 11786 | "addic %2,%1,-1\;subfe %0,%2,%1" |
943c15ed DE |
11787 | [(set_attr "type" "two") |
11788 | (set_attr "length" "8")]) | |
a260abc9 | 11789 | |
1fd4e8c1 RK |
11790 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11791 | (define_insn "" | |
cd2b37d9 | 11792 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11793 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11794 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11795 | (const_int 31)) |
cd2b37d9 | 11796 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11797 | (clobber (match_scratch:SI 3 "=&r"))] |
683bdff7 | 11798 | "TARGET_32BIT" |
ca7f5001 | 11799 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
943c15ed DE |
11800 | [(set_attr "type" "two") |
11801 | (set_attr "length" "8")]) | |
1fd4e8c1 | 11802 | |
a260abc9 DE |
11803 | (define_insn "" |
11804 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11805 | (plus:DI (lshiftrt:DI | |
11806 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11807 | (const_int 63)) | |
11808 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11809 | (clobber (match_scratch:DI 3 "=&r"))] | |
683bdff7 | 11810 | "TARGET_64BIT" |
a260abc9 | 11811 | "addic %3,%1,-1\;addze %0,%2" |
943c15ed DE |
11812 | [(set_attr "type" "two") |
11813 | (set_attr "length" "8")]) | |
a260abc9 | 11814 | |
1fd4e8c1 | 11815 | (define_insn "" |
9ebbca7d | 11816 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11817 | (compare:CC |
11818 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11819 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11820 | (const_int 31)) |
9ebbca7d | 11821 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11822 | (const_int 0))) |
889b90a1 GK |
11823 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11824 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
683bdff7 | 11825 | "TARGET_32BIT" |
9ebbca7d GK |
11826 | "@ |
11827 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11828 | #" | |
b19003d8 | 11829 | [(set_attr "type" "compare") |
9ebbca7d GK |
11830 | (set_attr "length" "8,12")]) |
11831 | ||
11832 | (define_split | |
11833 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11834 | (compare:CC | |
11835 | (plus:SI (lshiftrt:SI | |
11836 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11837 | (const_int 31)) | |
11838 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11839 | (const_int 0))) | |
889b90a1 GK |
11840 | (clobber (match_scratch:SI 3 "")) |
11841 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11842 | "TARGET_32BIT && reload_completed" |
889b90a1 | 11843 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
11844 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
11845 | (const_int 31)) | |
11846 | (match_dup 2))) | |
889b90a1 | 11847 | (clobber (match_dup 4))]) |
9ebbca7d GK |
11848 | (set (match_dup 0) |
11849 | (compare:CC (match_dup 3) | |
11850 | (const_int 0)))] | |
11851 | "") | |
1fd4e8c1 | 11852 | |
a260abc9 | 11853 | (define_insn "" |
9ebbca7d | 11854 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11855 | (compare:CC |
11856 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11857 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11858 | (const_int 63)) |
9ebbca7d | 11859 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11860 | (const_int 0))) |
9ebbca7d | 11861 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11862 | "TARGET_64BIT" |
9ebbca7d GK |
11863 | "@ |
11864 | addic %3,%1,-1\;addze. %3,%2 | |
11865 | #" | |
a260abc9 | 11866 | [(set_attr "type" "compare") |
9ebbca7d GK |
11867 | (set_attr "length" "8,12")]) |
11868 | ||
11869 | (define_split | |
11870 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11871 | (compare:CC | |
11872 | (plus:DI (lshiftrt:DI | |
11873 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11874 | (const_int 63)) | |
11875 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11876 | (const_int 0))) | |
11877 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11878 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11879 | [(set (match_dup 3) |
11880 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11881 | (const_int 63)) | |
11882 | (match_dup 2))) | |
11883 | (set (match_dup 0) | |
11884 | (compare:CC (match_dup 3) | |
11885 | (const_int 0)))] | |
11886 | "") | |
a260abc9 | 11887 | |
1fd4e8c1 | 11888 | (define_insn "" |
9ebbca7d | 11889 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11890 | (compare:CC |
11891 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11892 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11893 | (const_int 31)) |
9ebbca7d | 11894 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11895 | (const_int 0))) |
9ebbca7d | 11896 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11897 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11898 | (match_dup 2))) | |
9ebbca7d | 11899 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 11900 | "TARGET_32BIT" |
9ebbca7d GK |
11901 | "@ |
11902 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11903 | #" | |
b19003d8 | 11904 | [(set_attr "type" "compare") |
9ebbca7d GK |
11905 | (set_attr "length" "8,12")]) |
11906 | ||
11907 | (define_split | |
11908 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11909 | (compare:CC | |
11910 | (plus:SI (lshiftrt:SI | |
11911 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11912 | (const_int 31)) | |
11913 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11914 | (const_int 0))) | |
11915 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11916 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11917 | (match_dup 2))) | |
11918 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11919 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11920 | [(parallel [(set (match_dup 0) |
11921 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11922 | (match_dup 2))) | |
11923 | (clobber (match_dup 3))]) | |
11924 | (set (match_dup 4) | |
11925 | (compare:CC (match_dup 0) | |
11926 | (const_int 0)))] | |
11927 | "") | |
1fd4e8c1 | 11928 | |
a260abc9 | 11929 | (define_insn "" |
9ebbca7d | 11930 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11931 | (compare:CC |
11932 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11933 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11934 | (const_int 63)) |
9ebbca7d | 11935 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11936 | (const_int 0))) |
9ebbca7d | 11937 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11938 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11939 | (match_dup 2))) | |
9ebbca7d | 11940 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11941 | "TARGET_64BIT" |
9ebbca7d GK |
11942 | "@ |
11943 | addic %3,%1,-1\;addze. %0,%2 | |
11944 | #" | |
a260abc9 | 11945 | [(set_attr "type" "compare") |
9ebbca7d GK |
11946 | (set_attr "length" "8,12")]) |
11947 | ||
11948 | (define_split | |
11949 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11950 | (compare:CC | |
11951 | (plus:DI (lshiftrt:DI | |
11952 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11953 | (const_int 63)) | |
11954 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11955 | (const_int 0))) | |
11956 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11957 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11958 | (match_dup 2))) | |
11959 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11960 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11961 | [(parallel [(set (match_dup 0) |
11962 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11963 | (match_dup 2))) | |
11964 | (clobber (match_dup 3))]) | |
11965 | (set (match_dup 4) | |
11966 | (compare:CC (match_dup 0) | |
11967 | (const_int 0)))] | |
11968 | "") | |
a260abc9 | 11969 | |
1fd4e8c1 | 11970 | (define_insn "" |
cd2b37d9 RK |
11971 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11972 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11973 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11974 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11975 | "TARGET_POWER" |
1fd4e8c1 | 11976 | "@ |
ca7f5001 | 11977 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11978 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11979 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11980 | |
11981 | (define_insn "" | |
9ebbca7d | 11982 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11983 | (compare:CC |
9ebbca7d GK |
11984 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11985 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 11986 | (const_int 0))) |
9ebbca7d | 11987 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11988 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11989 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 11990 | "TARGET_POWER" |
1fd4e8c1 | 11991 | "@ |
ca7f5001 | 11992 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
11993 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
11994 | # | |
11995 | #" | |
11996 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
11997 | (set_attr "length" "12,12,16,16")]) | |
11998 | ||
11999 | (define_split | |
12000 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12001 | (compare:CC | |
12002 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12003 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12004 | (const_int 0))) | |
12005 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12006 | (le:SI (match_dup 1) (match_dup 2))) | |
12007 | (clobber (match_scratch:SI 3 ""))] | |
12008 | "TARGET_POWER && reload_completed" | |
12009 | [(parallel [(set (match_dup 0) | |
12010 | (le:SI (match_dup 1) (match_dup 2))) | |
12011 | (clobber (match_dup 3))]) | |
12012 | (set (match_dup 4) | |
12013 | (compare:CC (match_dup 0) | |
12014 | (const_int 0)))] | |
12015 | "") | |
1fd4e8c1 RK |
12016 | |
12017 | (define_insn "" | |
097657c3 | 12018 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12019 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12020 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 12021 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 12022 | "TARGET_POWER" |
1fd4e8c1 | 12023 | "@ |
097657c3 AM |
12024 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
12025 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 12026 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12027 | |
12028 | (define_insn "" | |
9ebbca7d | 12029 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12030 | (compare:CC |
9ebbca7d GK |
12031 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12032 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12033 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12034 | (const_int 0))) |
9ebbca7d | 12035 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 12036 | "TARGET_POWER" |
1fd4e8c1 | 12037 | "@ |
ca7f5001 | 12038 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12039 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
12040 | # | |
12041 | #" | |
b19003d8 | 12042 | [(set_attr "type" "compare") |
9ebbca7d GK |
12043 | (set_attr "length" "12,12,16,16")]) |
12044 | ||
12045 | (define_split | |
12046 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12047 | (compare:CC | |
12048 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12049 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12050 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12051 | (const_int 0))) | |
12052 | (clobber (match_scratch:SI 4 ""))] | |
12053 | "TARGET_POWER && reload_completed" | |
12054 | [(set (match_dup 4) | |
12055 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12056 | (match_dup 3))) |
9ebbca7d GK |
12057 | (set (match_dup 0) |
12058 | (compare:CC (match_dup 4) | |
12059 | (const_int 0)))] | |
12060 | "") | |
1fd4e8c1 RK |
12061 | |
12062 | (define_insn "" | |
097657c3 | 12063 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12064 | (compare:CC |
9ebbca7d GK |
12065 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12066 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12067 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12068 | (const_int 0))) |
097657c3 AM |
12069 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12070 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12071 | "TARGET_POWER" |
1fd4e8c1 | 12072 | "@ |
097657c3 AM |
12073 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
12074 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12075 | # |
12076 | #" | |
b19003d8 | 12077 | [(set_attr "type" "compare") |
9ebbca7d GK |
12078 | (set_attr "length" "12,12,16,16")]) |
12079 | ||
12080 | (define_split | |
097657c3 | 12081 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12082 | (compare:CC |
12083 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12084 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12085 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12086 | (const_int 0))) | |
12087 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12088 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12089 | "TARGET_POWER && reload_completed" |
097657c3 | 12090 | [(set (match_dup 0) |
9ebbca7d | 12091 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12092 | (set (match_dup 4) |
9ebbca7d GK |
12093 | (compare:CC (match_dup 0) |
12094 | (const_int 0)))] | |
12095 | "") | |
1fd4e8c1 RK |
12096 | |
12097 | (define_insn "" | |
cd2b37d9 RK |
12098 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12099 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12100 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 12101 | "TARGET_POWER" |
1fd4e8c1 | 12102 | "@ |
ca7f5001 RK |
12103 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
12104 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12105 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12106 | |
12107 | (define_insn "" | |
cd2b37d9 RK |
12108 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12109 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12110 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
4b8a63d6 | 12111 | "TARGET_32BIT" |
ca7f5001 | 12112 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
943c15ed DE |
12113 | [(set_attr "type" "three") |
12114 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12115 | |
f9562f27 DE |
12116 | (define_insn "" |
12117 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12118 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12119 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 12120 | "TARGET_64BIT" |
f9562f27 | 12121 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" |
943c15ed DE |
12122 | [(set_attr "type" "three") |
12123 | (set_attr "length" "12")]) | |
f9562f27 DE |
12124 | |
12125 | (define_insn "" | |
9ebbca7d | 12126 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12127 | (compare:CC |
9ebbca7d GK |
12128 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12129 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12130 | (const_int 0))) |
9ebbca7d | 12131 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 12132 | (leu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12133 | "TARGET_64BIT" |
9ebbca7d GK |
12134 | "@ |
12135 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
12136 | #" | |
f9562f27 | 12137 | [(set_attr "type" "compare") |
9ebbca7d GK |
12138 | (set_attr "length" "12,16")]) |
12139 | ||
12140 | (define_split | |
12141 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12142 | (compare:CC | |
12143 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12144 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12145 | (const_int 0))) | |
12146 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12147 | (leu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12148 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12149 | [(set (match_dup 0) |
12150 | (leu:DI (match_dup 1) (match_dup 2))) | |
12151 | (set (match_dup 3) | |
12152 | (compare:CC (match_dup 0) | |
12153 | (const_int 0)))] | |
12154 | "") | |
f9562f27 | 12155 | |
1fd4e8c1 | 12156 | (define_insn "" |
9ebbca7d | 12157 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12158 | (compare:CC |
9ebbca7d GK |
12159 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12160 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12161 | (const_int 0))) |
9ebbca7d | 12162 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12163 | (leu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12164 | "TARGET_32BIT" |
9ebbca7d GK |
12165 | "@ |
12166 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
12167 | #" | |
b19003d8 | 12168 | [(set_attr "type" "compare") |
9ebbca7d GK |
12169 | (set_attr "length" "12,16")]) |
12170 | ||
12171 | (define_split | |
12172 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12173 | (compare:CC | |
12174 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12175 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12176 | (const_int 0))) | |
12177 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12178 | (leu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12179 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12180 | [(set (match_dup 0) |
12181 | (leu:SI (match_dup 1) (match_dup 2))) | |
12182 | (set (match_dup 3) | |
12183 | (compare:CC (match_dup 0) | |
12184 | (const_int 0)))] | |
12185 | "") | |
1fd4e8c1 RK |
12186 | |
12187 | (define_insn "" | |
80103f96 | 12188 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12189 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12190 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 12191 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12192 | "TARGET_32BIT" |
80103f96 | 12193 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
943c15ed DE |
12194 | [(set_attr "type" "two") |
12195 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
12196 | |
12197 | (define_insn "" | |
9ebbca7d | 12198 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12199 | (compare:CC |
9ebbca7d GK |
12200 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12201 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12202 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12203 | (const_int 0))) |
9ebbca7d | 12204 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12205 | "TARGET_32BIT" |
9ebbca7d GK |
12206 | "@ |
12207 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
12208 | #" | |
b19003d8 | 12209 | [(set_attr "type" "compare") |
9ebbca7d GK |
12210 | (set_attr "length" "8,12")]) |
12211 | ||
12212 | (define_split | |
12213 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12214 | (compare:CC | |
12215 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12216 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12217 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12218 | (const_int 0))) | |
12219 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12220 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12221 | [(set (match_dup 4) |
12222 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
12223 | (match_dup 3))) | |
12224 | (set (match_dup 0) | |
12225 | (compare:CC (match_dup 4) | |
12226 | (const_int 0)))] | |
12227 | "") | |
1fd4e8c1 RK |
12228 | |
12229 | (define_insn "" | |
097657c3 | 12230 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12231 | (compare:CC |
9ebbca7d GK |
12232 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12233 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12234 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12235 | (const_int 0))) |
097657c3 AM |
12236 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12237 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12238 | "TARGET_32BIT" |
9ebbca7d | 12239 | "@ |
097657c3 | 12240 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 12241 | #" |
b19003d8 | 12242 | [(set_attr "type" "compare") |
9ebbca7d GK |
12243 | (set_attr "length" "8,12")]) |
12244 | ||
12245 | (define_split | |
097657c3 | 12246 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12247 | (compare:CC |
12248 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12249 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12250 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12251 | (const_int 0))) | |
12252 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12253 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12254 | "TARGET_32BIT && reload_completed" |
097657c3 | 12255 | [(set (match_dup 0) |
9ebbca7d | 12256 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12257 | (set (match_dup 4) |
9ebbca7d GK |
12258 | (compare:CC (match_dup 0) |
12259 | (const_int 0)))] | |
12260 | "") | |
1fd4e8c1 RK |
12261 | |
12262 | (define_insn "" | |
cd2b37d9 RK |
12263 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12264 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12265 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 12266 | "TARGET_32BIT" |
ca7f5001 | 12267 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
943c15ed DE |
12268 | [(set_attr "type" "three") |
12269 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12270 | |
12271 | (define_insn "" | |
097657c3 | 12272 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 12273 | (and:SI (neg:SI |
cd2b37d9 | 12274 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12275 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 12276 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12277 | "TARGET_32BIT" |
097657c3 | 12278 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
943c15ed DE |
12279 | [(set_attr "type" "three") |
12280 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12281 | |
12282 | (define_insn "" | |
9ebbca7d | 12283 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12284 | (compare:CC |
12285 | (and:SI (neg:SI | |
9ebbca7d GK |
12286 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12287 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12288 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12289 | (const_int 0))) |
9ebbca7d | 12290 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12291 | "TARGET_32BIT" |
9ebbca7d GK |
12292 | "@ |
12293 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
12294 | #" | |
12295 | [(set_attr "type" "compare") | |
12296 | (set_attr "length" "12,16")]) | |
12297 | ||
12298 | (define_split | |
12299 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12300 | (compare:CC | |
12301 | (and:SI (neg:SI | |
12302 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12303 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12304 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12305 | (const_int 0))) | |
12306 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12307 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12308 | [(set (match_dup 4) |
097657c3 AM |
12309 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
12310 | (match_dup 3))) | |
9ebbca7d GK |
12311 | (set (match_dup 0) |
12312 | (compare:CC (match_dup 4) | |
12313 | (const_int 0)))] | |
12314 | "") | |
1fd4e8c1 RK |
12315 | |
12316 | (define_insn "" | |
097657c3 | 12317 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12318 | (compare:CC |
12319 | (and:SI (neg:SI | |
9ebbca7d GK |
12320 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12321 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12322 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12323 | (const_int 0))) |
097657c3 AM |
12324 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12325 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12326 | "TARGET_32BIT" |
9ebbca7d | 12327 | "@ |
097657c3 | 12328 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 12329 | #" |
b19003d8 | 12330 | [(set_attr "type" "compare") |
9ebbca7d GK |
12331 | (set_attr "length" "12,16")]) |
12332 | ||
12333 | (define_split | |
097657c3 | 12334 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12335 | (compare:CC |
12336 | (and:SI (neg:SI | |
12337 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12338 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12339 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12340 | (const_int 0))) | |
12341 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12342 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 12343 | "TARGET_32BIT && reload_completed" |
097657c3 AM |
12344 | [(set (match_dup 0) |
12345 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
12346 | (match_dup 3))) | |
12347 | (set (match_dup 4) | |
9ebbca7d GK |
12348 | (compare:CC (match_dup 0) |
12349 | (const_int 0)))] | |
12350 | "") | |
1fd4e8c1 RK |
12351 | |
12352 | (define_insn "" | |
cd2b37d9 RK |
12353 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12354 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12355 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 12356 | "TARGET_POWER" |
7f340546 | 12357 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12358 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12359 | |
12360 | (define_insn "" | |
9ebbca7d | 12361 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12362 | (compare:CC |
9ebbca7d GK |
12363 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12364 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12365 | (const_int 0))) |
9ebbca7d | 12366 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12367 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12368 | "TARGET_POWER" |
9ebbca7d GK |
12369 | "@ |
12370 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12371 | #" | |
29ae5b89 | 12372 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12373 | (set_attr "length" "12,16")]) |
12374 | ||
12375 | (define_split | |
12376 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12377 | (compare:CC | |
12378 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12379 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12380 | (const_int 0))) | |
12381 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12382 | (lt:SI (match_dup 1) (match_dup 2)))] | |
12383 | "TARGET_POWER && reload_completed" | |
12384 | [(set (match_dup 0) | |
12385 | (lt:SI (match_dup 1) (match_dup 2))) | |
12386 | (set (match_dup 3) | |
12387 | (compare:CC (match_dup 0) | |
12388 | (const_int 0)))] | |
12389 | "") | |
1fd4e8c1 RK |
12390 | |
12391 | (define_insn "" | |
097657c3 | 12392 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12393 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12394 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12395 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12396 | "TARGET_POWER" |
097657c3 | 12397 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12398 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12399 | |
12400 | (define_insn "" | |
9ebbca7d | 12401 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12402 | (compare:CC |
9ebbca7d GK |
12403 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12404 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12405 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12406 | (const_int 0))) |
9ebbca7d | 12407 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12408 | "TARGET_POWER" |
9ebbca7d GK |
12409 | "@ |
12410 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12411 | #" | |
b19003d8 | 12412 | [(set_attr "type" "compare") |
9ebbca7d GK |
12413 | (set_attr "length" "12,16")]) |
12414 | ||
12415 | (define_split | |
12416 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12417 | (compare:CC | |
12418 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12419 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12420 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12421 | (const_int 0))) | |
12422 | (clobber (match_scratch:SI 4 ""))] | |
12423 | "TARGET_POWER && reload_completed" | |
12424 | [(set (match_dup 4) | |
12425 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12426 | (match_dup 3))) |
9ebbca7d GK |
12427 | (set (match_dup 0) |
12428 | (compare:CC (match_dup 4) | |
12429 | (const_int 0)))] | |
12430 | "") | |
1fd4e8c1 RK |
12431 | |
12432 | (define_insn "" | |
097657c3 | 12433 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12434 | (compare:CC |
9ebbca7d GK |
12435 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12436 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12437 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12438 | (const_int 0))) |
097657c3 AM |
12439 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12440 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12441 | "TARGET_POWER" |
9ebbca7d | 12442 | "@ |
097657c3 | 12443 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12444 | #" |
b19003d8 | 12445 | [(set_attr "type" "compare") |
9ebbca7d GK |
12446 | (set_attr "length" "12,16")]) |
12447 | ||
12448 | (define_split | |
097657c3 | 12449 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12450 | (compare:CC |
12451 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12452 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12453 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12454 | (const_int 0))) | |
12455 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12456 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12457 | "TARGET_POWER && reload_completed" |
097657c3 | 12458 | [(set (match_dup 0) |
9ebbca7d | 12459 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12460 | (set (match_dup 4) |
9ebbca7d GK |
12461 | (compare:CC (match_dup 0) |
12462 | (const_int 0)))] | |
12463 | "") | |
1fd4e8c1 RK |
12464 | |
12465 | (define_insn "" | |
cd2b37d9 RK |
12466 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12467 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12468 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12469 | "TARGET_POWER" |
12470 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12471 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12472 | |
c0600ecd | 12473 | (define_insn_and_split "" |
cd2b37d9 RK |
12474 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12475 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12476 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12477 | "TARGET_32BIT" |
c0600ecd DE |
12478 | "#" |
12479 | "TARGET_32BIT" | |
12480 | [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) | |
12481 | (set (match_dup 0) (neg:SI (match_dup 0)))] | |
12482 | "") | |
12483 | ||
12484 | (define_insn_and_split "" | |
12485 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12486 | (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12487 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
12488 | "TARGET_64BIT" | |
12489 | "#" | |
12490 | "TARGET_64BIT" | |
12491 | [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) | |
12492 | (set (match_dup 0) (neg:DI (match_dup 0)))] | |
12493 | "") | |
1fd4e8c1 RK |
12494 | |
12495 | (define_insn "" | |
9ebbca7d | 12496 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12497 | (compare:CC |
9ebbca7d GK |
12498 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12499 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12500 | (const_int 0))) |
9ebbca7d | 12501 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12502 | (ltu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12503 | "TARGET_32BIT" |
1fd4e8c1 | 12504 | "@ |
ca7f5001 | 12505 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12506 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12507 | # | |
12508 | #" | |
b19003d8 | 12509 | [(set_attr "type" "compare") |
9ebbca7d GK |
12510 | (set_attr "length" "12,12,16,16")]) |
12511 | ||
12512 | (define_split | |
12513 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12514 | (compare:CC | |
12515 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12516 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12517 | (const_int 0))) | |
12518 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12519 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12520 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12521 | [(set (match_dup 0) |
12522 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12523 | (set (match_dup 3) | |
12524 | (compare:CC (match_dup 0) | |
12525 | (const_int 0)))] | |
12526 | "") | |
1fd4e8c1 | 12527 | |
c0600ecd DE |
12528 | (define_insn_and_split "" |
12529 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
12530 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12531 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
12532 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] | |
683bdff7 | 12533 | "TARGET_32BIT" |
c0600ecd DE |
12534 | "#" |
12535 | "TARGET_32BIT" | |
12536 | [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) | |
12537 | (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] | |
12538 | "") | |
12539 | ||
12540 | (define_insn_and_split "" | |
12541 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12542 | (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12543 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")) | |
12544 | (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))] | |
12545 | "TARGET_64BIT" | |
12546 | "#" | |
12547 | "TARGET_64BIT" | |
12548 | [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) | |
12549 | (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] | |
12550 | "") | |
1fd4e8c1 RK |
12551 | |
12552 | (define_insn "" | |
9ebbca7d | 12553 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12554 | (compare:CC |
9ebbca7d GK |
12555 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12556 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12557 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12558 | (const_int 0))) |
9ebbca7d | 12559 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12560 | "TARGET_32BIT" |
1fd4e8c1 | 12561 | "@ |
c9dbf840 DE |
12562 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 |
12563 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 | |
9ebbca7d GK |
12564 | # |
12565 | #" | |
b19003d8 | 12566 | [(set_attr "type" "compare") |
9ebbca7d GK |
12567 | (set_attr "length" "12,12,16,16")]) |
12568 | ||
12569 | (define_split | |
12570 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12571 | (compare:CC | |
12572 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12573 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12574 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12575 | (const_int 0))) | |
12576 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12577 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12578 | [(set (match_dup 4) |
12579 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12580 | (match_dup 3))) |
9ebbca7d GK |
12581 | (set (match_dup 0) |
12582 | (compare:CC (match_dup 4) | |
12583 | (const_int 0)))] | |
12584 | "") | |
1fd4e8c1 RK |
12585 | |
12586 | (define_insn "" | |
097657c3 | 12587 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12588 | (compare:CC |
9ebbca7d GK |
12589 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12590 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12591 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12592 | (const_int 0))) |
097657c3 AM |
12593 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12594 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12595 | "TARGET_32BIT" |
1fd4e8c1 | 12596 | "@ |
c9dbf840 DE |
12597 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 |
12598 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 | |
9ebbca7d GK |
12599 | # |
12600 | #" | |
b19003d8 | 12601 | [(set_attr "type" "compare") |
9ebbca7d GK |
12602 | (set_attr "length" "12,12,16,16")]) |
12603 | ||
12604 | (define_split | |
097657c3 | 12605 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12606 | (compare:CC |
12607 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12608 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12609 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12610 | (const_int 0))) | |
12611 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12612 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12613 | "TARGET_32BIT && reload_completed" |
097657c3 | 12614 | [(set (match_dup 0) |
9ebbca7d | 12615 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12616 | (set (match_dup 4) |
9ebbca7d GK |
12617 | (compare:CC (match_dup 0) |
12618 | (const_int 0)))] | |
12619 | "") | |
1fd4e8c1 RK |
12620 | |
12621 | (define_insn "" | |
cd2b37d9 RK |
12622 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12623 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12624 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
683bdff7 | 12625 | "TARGET_32BIT" |
1fd4e8c1 | 12626 | "@ |
ca7f5001 RK |
12627 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12628 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
943c15ed | 12629 | [(set_attr "type" "two") |
c0600ecd DE |
12630 | (set_attr "length" "8")]) |
12631 | ||
12632 | (define_insn "" | |
12633 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12634 | (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12635 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))] | |
12636 | "TARGET_64BIT" | |
12637 | "@ | |
12638 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 | |
12639 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
943c15ed | 12640 | [(set_attr "type" "two") |
c0600ecd | 12641 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
12642 | |
12643 | (define_insn "" | |
cd2b37d9 RK |
12644 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12645 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12646 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12647 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12648 | "TARGET_POWER" |
12649 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12650 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12651 | |
9ebbca7d GK |
12652 | (define_insn "" |
12653 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12654 | (compare:CC |
9ebbca7d GK |
12655 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12656 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12657 | (const_int 0))) |
9ebbca7d | 12658 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12659 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12660 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12661 | "TARGET_POWER" |
9ebbca7d GK |
12662 | "@ |
12663 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12664 | #" | |
12665 | [(set_attr "type" "compare") | |
12666 | (set_attr "length" "12,16")]) | |
12667 | ||
12668 | (define_split | |
12669 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12670 | (compare:CC | |
12671 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12672 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12673 | (const_int 0))) | |
12674 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12675 | (ge:SI (match_dup 1) (match_dup 2))) | |
12676 | (clobber (match_scratch:SI 3 ""))] | |
12677 | "TARGET_POWER && reload_completed" | |
12678 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12679 | (ge:SI (match_dup 1) (match_dup 2))) |
12680 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12681 | (set (match_dup 4) |
12682 | (compare:CC (match_dup 0) | |
12683 | (const_int 0)))] | |
12684 | "") | |
12685 | ||
1fd4e8c1 | 12686 | (define_insn "" |
097657c3 | 12687 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12688 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12689 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12690 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12691 | "TARGET_POWER" |
097657c3 | 12692 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12693 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12694 | |
12695 | (define_insn "" | |
9ebbca7d | 12696 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12697 | (compare:CC |
9ebbca7d GK |
12698 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12699 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12700 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12701 | (const_int 0))) |
9ebbca7d | 12702 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12703 | "TARGET_POWER" |
9ebbca7d GK |
12704 | "@ |
12705 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12706 | #" | |
b19003d8 | 12707 | [(set_attr "type" "compare") |
9ebbca7d GK |
12708 | (set_attr "length" "12,16")]) |
12709 | ||
12710 | (define_split | |
12711 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12712 | (compare:CC | |
12713 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12714 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12715 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12716 | (const_int 0))) | |
12717 | (clobber (match_scratch:SI 4 ""))] | |
12718 | "TARGET_POWER && reload_completed" | |
12719 | [(set (match_dup 4) | |
12720 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12721 | (match_dup 3))) |
9ebbca7d GK |
12722 | (set (match_dup 0) |
12723 | (compare:CC (match_dup 4) | |
12724 | (const_int 0)))] | |
12725 | "") | |
1fd4e8c1 RK |
12726 | |
12727 | (define_insn "" | |
097657c3 | 12728 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12729 | (compare:CC |
9ebbca7d GK |
12730 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12731 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12732 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12733 | (const_int 0))) |
097657c3 AM |
12734 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12735 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12736 | "TARGET_POWER" |
9ebbca7d | 12737 | "@ |
097657c3 | 12738 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12739 | #" |
b19003d8 | 12740 | [(set_attr "type" "compare") |
9ebbca7d GK |
12741 | (set_attr "length" "12,16")]) |
12742 | ||
12743 | (define_split | |
097657c3 | 12744 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12745 | (compare:CC |
12746 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12747 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12748 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12749 | (const_int 0))) | |
12750 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12751 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12752 | "TARGET_POWER && reload_completed" |
097657c3 | 12753 | [(set (match_dup 0) |
9ebbca7d | 12754 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12755 | (set (match_dup 4) |
9ebbca7d GK |
12756 | (compare:CC (match_dup 0) |
12757 | (const_int 0)))] | |
12758 | "") | |
1fd4e8c1 RK |
12759 | |
12760 | (define_insn "" | |
cd2b37d9 RK |
12761 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12762 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12763 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12764 | "TARGET_POWER" |
12765 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12766 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12767 | |
1fd4e8c1 | 12768 | (define_insn "" |
cd2b37d9 RK |
12769 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12770 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12771 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12772 | "TARGET_32BIT" |
1fd4e8c1 | 12773 | "@ |
ca7f5001 RK |
12774 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12775 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
943c15ed DE |
12776 | [(set_attr "type" "three") |
12777 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12778 | |
f9562f27 DE |
12779 | (define_insn "" |
12780 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12781 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12782 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
683bdff7 | 12783 | "TARGET_64BIT" |
f9562f27 DE |
12784 | "@ |
12785 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12786 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
943c15ed DE |
12787 | [(set_attr "type" "three") |
12788 | (set_attr "length" "12")]) | |
f9562f27 | 12789 | |
1fd4e8c1 | 12790 | (define_insn "" |
9ebbca7d | 12791 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12792 | (compare:CC |
9ebbca7d GK |
12793 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12794 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12795 | (const_int 0))) |
9ebbca7d | 12796 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12797 | (geu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12798 | "TARGET_32BIT" |
1fd4e8c1 | 12799 | "@ |
ca7f5001 | 12800 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12801 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12802 | # | |
12803 | #" | |
b19003d8 | 12804 | [(set_attr "type" "compare") |
9ebbca7d GK |
12805 | (set_attr "length" "12,12,16,16")]) |
12806 | ||
12807 | (define_split | |
12808 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12809 | (compare:CC | |
12810 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12811 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12812 | (const_int 0))) | |
12813 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12814 | (geu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12815 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12816 | [(set (match_dup 0) |
12817 | (geu:SI (match_dup 1) (match_dup 2))) | |
12818 | (set (match_dup 3) | |
12819 | (compare:CC (match_dup 0) | |
12820 | (const_int 0)))] | |
12821 | "") | |
1fd4e8c1 | 12822 | |
f9562f27 | 12823 | (define_insn "" |
9ebbca7d | 12824 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12825 | (compare:CC |
9ebbca7d GK |
12826 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12827 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12828 | (const_int 0))) |
9ebbca7d | 12829 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12830 | (geu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12831 | "TARGET_64BIT" |
f9562f27 DE |
12832 | "@ |
12833 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12834 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12835 | # | |
12836 | #" | |
f9562f27 | 12837 | [(set_attr "type" "compare") |
9ebbca7d GK |
12838 | (set_attr "length" "12,12,16,16")]) |
12839 | ||
12840 | (define_split | |
12841 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12842 | (compare:CC | |
12843 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12844 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12845 | (const_int 0))) | |
12846 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12847 | (geu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12848 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12849 | [(set (match_dup 0) |
12850 | (geu:DI (match_dup 1) (match_dup 2))) | |
12851 | (set (match_dup 3) | |
12852 | (compare:CC (match_dup 0) | |
12853 | (const_int 0)))] | |
12854 | "") | |
f9562f27 | 12855 | |
1fd4e8c1 | 12856 | (define_insn "" |
80103f96 | 12857 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12858 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12859 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 12860 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12861 | "TARGET_32BIT" |
1fd4e8c1 | 12862 | "@ |
80103f96 FS |
12863 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
12864 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
943c15ed DE |
12865 | [(set_attr "type" "two") |
12866 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
12867 | |
12868 | (define_insn "" | |
9ebbca7d | 12869 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12870 | (compare:CC |
9ebbca7d GK |
12871 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12872 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12873 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12874 | (const_int 0))) |
9ebbca7d | 12875 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12876 | "TARGET_32BIT" |
1fd4e8c1 | 12877 | "@ |
ca7f5001 | 12878 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12879 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12880 | # | |
12881 | #" | |
b19003d8 | 12882 | [(set_attr "type" "compare") |
9ebbca7d GK |
12883 | (set_attr "length" "8,8,12,12")]) |
12884 | ||
12885 | (define_split | |
12886 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12887 | (compare:CC | |
12888 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12889 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12890 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12891 | (const_int 0))) | |
12892 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12893 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12894 | [(set (match_dup 4) |
12895 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12896 | (match_dup 3))) | |
12897 | (set (match_dup 0) | |
12898 | (compare:CC (match_dup 4) | |
12899 | (const_int 0)))] | |
12900 | "") | |
1fd4e8c1 RK |
12901 | |
12902 | (define_insn "" | |
097657c3 | 12903 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12904 | (compare:CC |
9ebbca7d GK |
12905 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12906 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12907 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12908 | (const_int 0))) |
097657c3 AM |
12909 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12910 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12911 | "TARGET_32BIT" |
1fd4e8c1 | 12912 | "@ |
097657c3 AM |
12913 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
12914 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12915 | # |
12916 | #" | |
b19003d8 | 12917 | [(set_attr "type" "compare") |
9ebbca7d GK |
12918 | (set_attr "length" "8,8,12,12")]) |
12919 | ||
12920 | (define_split | |
097657c3 | 12921 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12922 | (compare:CC |
12923 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12924 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12925 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12926 | (const_int 0))) | |
12927 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12928 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12929 | "TARGET_32BIT && reload_completed" |
097657c3 | 12930 | [(set (match_dup 0) |
9ebbca7d | 12931 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12932 | (set (match_dup 4) |
9ebbca7d GK |
12933 | (compare:CC (match_dup 0) |
12934 | (const_int 0)))] | |
12935 | "") | |
1fd4e8c1 RK |
12936 | |
12937 | (define_insn "" | |
cd2b37d9 RK |
12938 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12939 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12940 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
683bdff7 | 12941 | "TARGET_32BIT" |
1fd4e8c1 | 12942 | "@ |
ca7f5001 | 12943 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12944 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
943c15ed DE |
12945 | [(set_attr "type" "three") |
12946 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12947 | |
12948 | (define_insn "" | |
097657c3 | 12949 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 12950 | (and:SI (neg:SI |
cd2b37d9 | 12951 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12952 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 12953 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12954 | "TARGET_32BIT" |
1fd4e8c1 | 12955 | "@ |
097657c3 AM |
12956 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
12957 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
943c15ed DE |
12958 | [(set_attr "type" "three") |
12959 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12960 | |
12961 | (define_insn "" | |
9ebbca7d | 12962 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12963 | (compare:CC |
12964 | (and:SI (neg:SI | |
9ebbca7d GK |
12965 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12966 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12967 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12968 | (const_int 0))) |
9ebbca7d | 12969 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12970 | "TARGET_32BIT" |
1fd4e8c1 | 12971 | "@ |
ca7f5001 | 12972 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12973 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12974 | # | |
12975 | #" | |
b19003d8 | 12976 | [(set_attr "type" "compare") |
9ebbca7d GK |
12977 | (set_attr "length" "12,12,16,16")]) |
12978 | ||
12979 | (define_split | |
12980 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12981 | (compare:CC | |
12982 | (and:SI (neg:SI | |
12983 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12984 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12985 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12986 | (const_int 0))) | |
12987 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12988 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12989 | [(set (match_dup 4) |
097657c3 AM |
12990 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
12991 | (match_dup 3))) | |
9ebbca7d GK |
12992 | (set (match_dup 0) |
12993 | (compare:CC (match_dup 4) | |
12994 | (const_int 0)))] | |
12995 | "") | |
1fd4e8c1 RK |
12996 | |
12997 | (define_insn "" | |
097657c3 | 12998 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12999 | (compare:CC |
13000 | (and:SI (neg:SI | |
9ebbca7d GK |
13001 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13002 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
13003 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13004 | (const_int 0))) |
097657c3 AM |
13005 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13006 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 13007 | "TARGET_32BIT" |
1fd4e8c1 | 13008 | "@ |
097657c3 AM |
13009 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
13010 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
13011 | # |
13012 | #" | |
b19003d8 | 13013 | [(set_attr "type" "compare") |
9ebbca7d GK |
13014 | (set_attr "length" "12,12,16,16")]) |
13015 | ||
13016 | (define_split | |
097657c3 | 13017 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13018 | (compare:CC |
13019 | (and:SI (neg:SI | |
13020 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13021 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
13022 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13023 | (const_int 0))) | |
13024 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13025 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 13026 | "TARGET_32BIT && reload_completed" |
097657c3 | 13027 | [(set (match_dup 0) |
9ebbca7d | 13028 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 13029 | (set (match_dup 4) |
9ebbca7d GK |
13030 | (compare:CC (match_dup 0) |
13031 | (const_int 0)))] | |
13032 | "") | |
1fd4e8c1 RK |
13033 | |
13034 | (define_insn "" | |
cd2b37d9 RK |
13035 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13036 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13037 | (const_int 0)))] |
683bdff7 | 13038 | "TARGET_32BIT" |
ca7f5001 | 13039 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
943c15ed DE |
13040 | [(set_attr "type" "three") |
13041 | (set_attr "length" "12")]) | |
1fd4e8c1 | 13042 | |
f9562f27 DE |
13043 | (define_insn "" |
13044 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13045 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13046 | (const_int 0)))] | |
683bdff7 | 13047 | "TARGET_64BIT" |
f9562f27 | 13048 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" |
943c15ed DE |
13049 | [(set_attr "type" "three") |
13050 | (set_attr "length" "12")]) | |
f9562f27 | 13051 | |
1fd4e8c1 | 13052 | (define_insn "" |
9ebbca7d | 13053 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13054 | (compare:CC |
9ebbca7d | 13055 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
13056 | (const_int 0)) |
13057 | (const_int 0))) | |
9ebbca7d | 13058 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13059 | (gt:SI (match_dup 1) (const_int 0)))] |
683bdff7 | 13060 | "TARGET_32BIT" |
9ebbca7d GK |
13061 | "@ |
13062 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
13063 | #" | |
29ae5b89 | 13064 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13065 | (set_attr "length" "12,16")]) |
13066 | ||
13067 | (define_split | |
13068 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13069 | (compare:CC | |
13070 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13071 | (const_int 0)) | |
13072 | (const_int 0))) | |
13073 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13074 | (gt:SI (match_dup 1) (const_int 0)))] | |
683bdff7 | 13075 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13076 | [(set (match_dup 0) |
13077 | (gt:SI (match_dup 1) (const_int 0))) | |
13078 | (set (match_dup 2) | |
13079 | (compare:CC (match_dup 0) | |
13080 | (const_int 0)))] | |
13081 | "") | |
1fd4e8c1 | 13082 | |
f9562f27 | 13083 | (define_insn "" |
9ebbca7d | 13084 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 13085 | (compare:CC |
9ebbca7d | 13086 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
13087 | (const_int 0)) |
13088 | (const_int 0))) | |
9ebbca7d | 13089 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13090 | (gt:DI (match_dup 1) (const_int 0)))] |
683bdff7 | 13091 | "TARGET_64BIT" |
9ebbca7d GK |
13092 | "@ |
13093 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
13094 | #" | |
f9562f27 | 13095 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13096 | (set_attr "length" "12,16")]) |
13097 | ||
13098 | (define_split | |
13099 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13100 | (compare:CC | |
13101 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13102 | (const_int 0)) | |
13103 | (const_int 0))) | |
13104 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13105 | (gt:DI (match_dup 1) (const_int 0)))] | |
683bdff7 | 13106 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13107 | [(set (match_dup 0) |
13108 | (gt:DI (match_dup 1) (const_int 0))) | |
13109 | (set (match_dup 2) | |
13110 | (compare:CC (match_dup 0) | |
13111 | (const_int 0)))] | |
13112 | "") | |
f9562f27 | 13113 | |
1fd4e8c1 | 13114 | (define_insn "" |
cd2b37d9 RK |
13115 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13116 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13117 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
13118 | "TARGET_POWER" |
13119 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 13120 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13121 | |
13122 | (define_insn "" | |
9ebbca7d | 13123 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13124 | (compare:CC |
9ebbca7d GK |
13125 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13126 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 13127 | (const_int 0))) |
9ebbca7d | 13128 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13129 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 13130 | "TARGET_POWER" |
9ebbca7d GK |
13131 | "@ |
13132 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
13133 | #" | |
29ae5b89 | 13134 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13135 | (set_attr "length" "12,16")]) |
13136 | ||
13137 | (define_split | |
13138 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13139 | (compare:CC | |
13140 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13141 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13142 | (const_int 0))) | |
13143 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13144 | (gt:SI (match_dup 1) (match_dup 2)))] | |
13145 | "TARGET_POWER && reload_completed" | |
13146 | [(set (match_dup 0) | |
13147 | (gt:SI (match_dup 1) (match_dup 2))) | |
13148 | (set (match_dup 3) | |
13149 | (compare:CC (match_dup 0) | |
13150 | (const_int 0)))] | |
13151 | "") | |
1fd4e8c1 RK |
13152 | |
13153 | (define_insn "" | |
80103f96 | 13154 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13155 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13156 | (const_int 0)) |
80103f96 | 13157 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 13158 | "TARGET_32BIT" |
80103f96 | 13159 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
943c15ed DE |
13160 | [(set_attr "type" "three") |
13161 | (set_attr "length" "12")]) | |
1fd4e8c1 | 13162 | |
f9562f27 | 13163 | (define_insn "" |
097657c3 | 13164 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
13165 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13166 | (const_int 0)) | |
097657c3 | 13167 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 13168 | "TARGET_64BIT" |
097657c3 | 13169 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
943c15ed DE |
13170 | [(set_attr "type" "three") |
13171 | (set_attr "length" "12")]) | |
f9562f27 | 13172 | |
1fd4e8c1 | 13173 | (define_insn "" |
9ebbca7d | 13174 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13175 | (compare:CC |
9ebbca7d | 13176 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13177 | (const_int 0)) |
9ebbca7d | 13178 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 13179 | (const_int 0))) |
9ebbca7d | 13180 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 13181 | "TARGET_32BIT" |
9ebbca7d GK |
13182 | "@ |
13183 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
13184 | #" | |
b19003d8 | 13185 | [(set_attr "type" "compare") |
9ebbca7d GK |
13186 | (set_attr "length" "12,16")]) |
13187 | ||
13188 | (define_split | |
13189 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13190 | (compare:CC | |
13191 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13192 | (const_int 0)) | |
13193 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
13194 | (const_int 0))) | |
13195 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 13196 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13197 | [(set (match_dup 3) |
13198 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
13199 | (match_dup 2))) | |
13200 | (set (match_dup 0) | |
13201 | (compare:CC (match_dup 3) | |
13202 | (const_int 0)))] | |
13203 | "") | |
1fd4e8c1 | 13204 | |
f9562f27 | 13205 | (define_insn "" |
9ebbca7d | 13206 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 13207 | (compare:CC |
9ebbca7d | 13208 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13209 | (const_int 0)) |
9ebbca7d | 13210 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13211 | (const_int 0))) |
9ebbca7d | 13212 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 13213 | "TARGET_64BIT" |
9ebbca7d GK |
13214 | "@ |
13215 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
13216 | #" | |
f9562f27 | 13217 | [(set_attr "type" "compare") |
9ebbca7d GK |
13218 | (set_attr "length" "12,16")]) |
13219 | ||
13220 | (define_split | |
13221 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13222 | (compare:CC | |
13223 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13224 | (const_int 0)) | |
13225 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13226 | (const_int 0))) | |
13227 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 13228 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13229 | [(set (match_dup 3) |
13230 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 13231 | (match_dup 2))) |
9ebbca7d GK |
13232 | (set (match_dup 0) |
13233 | (compare:CC (match_dup 3) | |
13234 | (const_int 0)))] | |
13235 | "") | |
f9562f27 | 13236 | |
1fd4e8c1 | 13237 | (define_insn "" |
097657c3 | 13238 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
13239 | (compare:CC |
13240 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
13241 | (const_int 0)) | |
13242 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
13243 | (const_int 0))) | |
097657c3 AM |
13244 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13245 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13246 | "TARGET_32BIT" |
9ebbca7d | 13247 | "@ |
097657c3 | 13248 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
13249 | #" |
13250 | [(set_attr "type" "compare") | |
13251 | (set_attr "length" "12,16")]) | |
13252 | ||
13253 | (define_split | |
097657c3 | 13254 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 13255 | (compare:CC |
9ebbca7d | 13256 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 13257 | (const_int 0)) |
9ebbca7d | 13258 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 13259 | (const_int 0))) |
9ebbca7d | 13260 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 13261 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13262 | "TARGET_32BIT && reload_completed" |
097657c3 | 13263 | [(set (match_dup 0) |
9ebbca7d | 13264 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13265 | (set (match_dup 3) |
9ebbca7d GK |
13266 | (compare:CC (match_dup 0) |
13267 | (const_int 0)))] | |
13268 | "") | |
1fd4e8c1 | 13269 | |
f9562f27 | 13270 | (define_insn "" |
097657c3 | 13271 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13272 | (compare:CC |
9ebbca7d | 13273 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13274 | (const_int 0)) |
9ebbca7d | 13275 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13276 | (const_int 0))) |
097657c3 AM |
13277 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
13278 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13279 | "TARGET_64BIT" |
9ebbca7d | 13280 | "@ |
097657c3 | 13281 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 13282 | #" |
f9562f27 | 13283 | [(set_attr "type" "compare") |
9ebbca7d GK |
13284 | (set_attr "length" "12,16")]) |
13285 | ||
13286 | (define_split | |
097657c3 | 13287 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13288 | (compare:CC |
13289 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13290 | (const_int 0)) | |
13291 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13292 | (const_int 0))) | |
13293 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13294 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13295 | "TARGET_64BIT && reload_completed" |
097657c3 | 13296 | [(set (match_dup 0) |
9ebbca7d | 13297 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13298 | (set (match_dup 3) |
9ebbca7d GK |
13299 | (compare:CC (match_dup 0) |
13300 | (const_int 0)))] | |
13301 | "") | |
f9562f27 | 13302 | |
1fd4e8c1 | 13303 | (define_insn "" |
097657c3 | 13304 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13305 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13306 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 13307 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 13308 | "TARGET_POWER" |
097657c3 | 13309 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 13310 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13311 | |
13312 | (define_insn "" | |
9ebbca7d | 13313 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13314 | (compare:CC |
9ebbca7d GK |
13315 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13316 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13317 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13318 | (const_int 0))) |
9ebbca7d | 13319 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13320 | "TARGET_POWER" |
9ebbca7d GK |
13321 | "@ |
13322 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
13323 | #" | |
b19003d8 | 13324 | [(set_attr "type" "compare") |
9ebbca7d GK |
13325 | (set_attr "length" "12,16")]) |
13326 | ||
13327 | (define_split | |
13328 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13329 | (compare:CC | |
13330 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13331 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13332 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13333 | (const_int 0))) | |
13334 | (clobber (match_scratch:SI 4 ""))] | |
13335 | "TARGET_POWER && reload_completed" | |
13336 | [(set (match_dup 4) | |
097657c3 | 13337 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
13338 | (set (match_dup 0) |
13339 | (compare:CC (match_dup 4) | |
13340 | (const_int 0)))] | |
13341 | "") | |
1fd4e8c1 RK |
13342 | |
13343 | (define_insn "" | |
097657c3 | 13344 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13345 | (compare:CC |
9ebbca7d GK |
13346 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13347 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13348 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13349 | (const_int 0))) |
097657c3 AM |
13350 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13351 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 13352 | "TARGET_POWER" |
9ebbca7d | 13353 | "@ |
097657c3 | 13354 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 13355 | #" |
b19003d8 | 13356 | [(set_attr "type" "compare") |
9ebbca7d GK |
13357 | (set_attr "length" "12,16")]) |
13358 | ||
13359 | (define_split | |
097657c3 | 13360 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13361 | (compare:CC |
13362 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13363 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13364 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13365 | (const_int 0))) | |
13366 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13367 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13368 | "TARGET_POWER && reload_completed" |
097657c3 | 13369 | [(set (match_dup 0) |
9ebbca7d | 13370 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13371 | (set (match_dup 4) |
9ebbca7d GK |
13372 | (compare:CC (match_dup 0) |
13373 | (const_int 0)))] | |
13374 | "") | |
1fd4e8c1 RK |
13375 | |
13376 | (define_insn "" | |
cd2b37d9 RK |
13377 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13378 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13379 | (const_int 0))))] |
683bdff7 | 13380 | "TARGET_32BIT" |
ca7f5001 | 13381 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
943c15ed DE |
13382 | [(set_attr "type" "three") |
13383 | (set_attr "length" "12")]) | |
1fd4e8c1 | 13384 | |
f9562f27 DE |
13385 | (define_insn "" |
13386 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13387 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13388 | (const_int 0))))] | |
683bdff7 | 13389 | "TARGET_64BIT" |
8377288b | 13390 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
943c15ed DE |
13391 | [(set_attr "type" "three") |
13392 | (set_attr "length" "12")]) | |
f9562f27 | 13393 | |
1fd4e8c1 | 13394 | (define_insn "" |
cd2b37d9 RK |
13395 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13396 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13397 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
13398 | "TARGET_POWER" |
13399 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 13400 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13401 | |
c0600ecd | 13402 | (define_insn_and_split "" |
cd2b37d9 | 13403 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c0600ecd DE |
13404 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
13405 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13406 | "TARGET_32BIT" |
c0600ecd DE |
13407 | "#" |
13408 | "TARGET_32BIT" | |
13409 | [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) | |
13410 | (set (match_dup 0) (neg:SI (match_dup 0)))] | |
13411 | "") | |
1fd4e8c1 | 13412 | |
c0600ecd | 13413 | (define_insn_and_split "" |
f9562f27 | 13414 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
c0600ecd DE |
13415 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13416 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13417 | "TARGET_64BIT" |
c0600ecd DE |
13418 | "#" |
13419 | "TARGET_64BIT" | |
13420 | [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) | |
13421 | (set (match_dup 0) (neg:DI (match_dup 0)))] | |
13422 | "") | |
f9562f27 | 13423 | |
1fd4e8c1 | 13424 | (define_insn "" |
9ebbca7d | 13425 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13426 | (compare:CC |
9ebbca7d GK |
13427 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13428 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13429 | (const_int 0))) |
9ebbca7d | 13430 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13431 | (gtu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13432 | "TARGET_32BIT" |
9ebbca7d GK |
13433 | "@ |
13434 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13435 | #" | |
b19003d8 | 13436 | [(set_attr "type" "compare") |
9ebbca7d GK |
13437 | (set_attr "length" "12,16")]) |
13438 | ||
13439 | (define_split | |
13440 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13441 | (compare:CC | |
13442 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13443 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13444 | (const_int 0))) | |
13445 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13446 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13447 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13448 | [(set (match_dup 0) |
13449 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13450 | (set (match_dup 3) | |
13451 | (compare:CC (match_dup 0) | |
13452 | (const_int 0)))] | |
13453 | "") | |
1fd4e8c1 | 13454 | |
f9562f27 | 13455 | (define_insn "" |
9ebbca7d | 13456 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13457 | (compare:CC |
9ebbca7d GK |
13458 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13459 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13460 | (const_int 0))) |
9ebbca7d | 13461 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13462 | (gtu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13463 | "TARGET_64BIT" |
9ebbca7d GK |
13464 | "@ |
13465 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13466 | #" | |
f9562f27 | 13467 | [(set_attr "type" "compare") |
9ebbca7d GK |
13468 | (set_attr "length" "12,16")]) |
13469 | ||
13470 | (define_split | |
13471 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13472 | (compare:CC | |
13473 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13474 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13475 | (const_int 0))) | |
13476 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13477 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13478 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13479 | [(set (match_dup 0) |
13480 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13481 | (set (match_dup 3) | |
13482 | (compare:CC (match_dup 0) | |
13483 | (const_int 0)))] | |
13484 | "") | |
f9562f27 | 13485 | |
c0600ecd DE |
13486 | (define_insn_and_split "" |
13487 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
13488 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
13489 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
13490 | (match_operand:SI 3 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13491 | "TARGET_32BIT" |
c0600ecd DE |
13492 | "#" |
13493 | "TARGET_32BIT" | |
13494 | [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) | |
13495 | (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] | |
13496 | "") | |
1fd4e8c1 | 13497 | |
c0600ecd DE |
13498 | (define_insn_and_split "" |
13499 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13500 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13501 | (match_operand:DI 2 "reg_or_short_operand" "rI")) | |
13502 | (match_operand:DI 3 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13503 | "TARGET_64BIT" |
c0600ecd DE |
13504 | "#" |
13505 | "TARGET_64BIT" | |
13506 | [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) | |
13507 | (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] | |
13508 | "") | |
f9562f27 | 13509 | |
1fd4e8c1 | 13510 | (define_insn "" |
9ebbca7d | 13511 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13512 | (compare:CC |
9ebbca7d GK |
13513 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13514 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13515 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13516 | (const_int 0))) |
9ebbca7d | 13517 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13518 | "TARGET_32BIT" |
00751805 | 13519 | "@ |
19378cf8 | 13520 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
c9dbf840 | 13521 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 |
9ebbca7d GK |
13522 | # |
13523 | #" | |
b19003d8 | 13524 | [(set_attr "type" "compare") |
9ebbca7d GK |
13525 | (set_attr "length" "8,12,12,16")]) |
13526 | ||
13527 | (define_split | |
13528 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13529 | (compare:CC | |
13530 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13531 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13532 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13533 | (const_int 0))) | |
13534 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 13535 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13536 | [(set (match_dup 4) |
13537 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13538 | (match_dup 3))) |
9ebbca7d GK |
13539 | (set (match_dup 0) |
13540 | (compare:CC (match_dup 4) | |
13541 | (const_int 0)))] | |
13542 | "") | |
1fd4e8c1 | 13543 | |
f9562f27 | 13544 | (define_insn "" |
9ebbca7d | 13545 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13546 | (compare:CC |
9ebbca7d GK |
13547 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13548 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13549 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13550 | (const_int 0))) |
9ebbca7d | 13551 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13552 | "TARGET_64BIT" |
f9562f27 DE |
13553 | "@ |
13554 | addic %4,%1,%k2\;addze. %4,%3 | |
c9dbf840 | 13555 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3 |
9ebbca7d GK |
13556 | # |
13557 | #" | |
f9562f27 | 13558 | [(set_attr "type" "compare") |
9ebbca7d GK |
13559 | (set_attr "length" "8,12,12,16")]) |
13560 | ||
13561 | (define_split | |
13562 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13563 | (compare:CC | |
13564 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13565 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13566 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13567 | (const_int 0))) | |
13568 | (clobber (match_scratch:DI 4 ""))] | |
683bdff7 | 13569 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13570 | [(set (match_dup 4) |
13571 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13572 | (match_dup 3))) | |
13573 | (set (match_dup 0) | |
13574 | (compare:CC (match_dup 4) | |
13575 | (const_int 0)))] | |
13576 | "") | |
f9562f27 | 13577 | |
1fd4e8c1 | 13578 | (define_insn "" |
097657c3 | 13579 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13580 | (compare:CC |
9ebbca7d GK |
13581 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13582 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13583 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13584 | (const_int 0))) |
097657c3 AM |
13585 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13586 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13587 | "TARGET_32BIT" |
00751805 | 13588 | "@ |
097657c3 | 13589 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
c9dbf840 | 13590 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 |
9ebbca7d GK |
13591 | # |
13592 | #" | |
b19003d8 | 13593 | [(set_attr "type" "compare") |
9ebbca7d GK |
13594 | (set_attr "length" "8,12,12,16")]) |
13595 | ||
13596 | (define_split | |
097657c3 | 13597 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13598 | (compare:CC |
13599 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13600 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13601 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13602 | (const_int 0))) | |
13603 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13604 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13605 | "TARGET_32BIT && reload_completed" |
097657c3 | 13606 | [(set (match_dup 0) |
9ebbca7d | 13607 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13608 | (set (match_dup 4) |
9ebbca7d GK |
13609 | (compare:CC (match_dup 0) |
13610 | (const_int 0)))] | |
13611 | "") | |
1fd4e8c1 | 13612 | |
f9562f27 | 13613 | (define_insn "" |
097657c3 | 13614 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13615 | (compare:CC |
9ebbca7d GK |
13616 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13617 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13618 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13619 | (const_int 0))) |
097657c3 AM |
13620 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13621 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13622 | "TARGET_64BIT" |
f9562f27 | 13623 | "@ |
097657c3 | 13624 | addic %0,%1,%k2\;addze. %0,%3 |
c9dbf840 | 13625 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3 |
9ebbca7d GK |
13626 | # |
13627 | #" | |
f9562f27 | 13628 | [(set_attr "type" "compare") |
9ebbca7d GK |
13629 | (set_attr "length" "8,12,12,16")]) |
13630 | ||
13631 | (define_split | |
097657c3 | 13632 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13633 | (compare:CC |
13634 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13635 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13636 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13637 | (const_int 0))) | |
13638 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13639 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13640 | "TARGET_64BIT && reload_completed" |
097657c3 | 13641 | [(set (match_dup 0) |
9ebbca7d | 13642 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13643 | (set (match_dup 4) |
9ebbca7d GK |
13644 | (compare:CC (match_dup 0) |
13645 | (const_int 0)))] | |
13646 | "") | |
f9562f27 | 13647 | |
1fd4e8c1 | 13648 | (define_insn "" |
cd2b37d9 RK |
13649 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13650 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13651 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 13652 | "TARGET_32BIT" |
ca7f5001 | 13653 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
943c15ed | 13654 | [(set_attr "type" "two") |
c0600ecd | 13655 | (set_attr "length" "8")]) |
f9562f27 DE |
13656 | |
13657 | (define_insn "" | |
13658 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13659 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13660 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
683bdff7 | 13661 | "TARGET_64BIT" |
f9562f27 | 13662 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" |
943c15ed | 13663 | [(set_attr "type" "two") |
c0600ecd | 13664 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
13665 | \f |
13666 | ;; Define both directions of branch and return. If we need a reload | |
13667 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13668 | ;; register CC value to there. | |
13669 | ||
13670 | (define_insn "" | |
13671 | [(set (pc) | |
13672 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13673 | [(match_operand 2 | |
b54cf83a | 13674 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13675 | (const_int 0)]) |
13676 | (label_ref (match_operand 0 "" "")) | |
13677 | (pc)))] | |
13678 | "" | |
b19003d8 RK |
13679 | "* |
13680 | { | |
12a4e8c5 | 13681 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13682 | }" |
13683 | [(set_attr "type" "branch")]) | |
13684 | ||
1fd4e8c1 RK |
13685 | (define_insn "" |
13686 | [(set (pc) | |
13687 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13688 | [(match_operand 1 | |
b54cf83a | 13689 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13690 | (const_int 0)]) |
13691 | (return) | |
13692 | (pc)))] | |
13693 | "direct_return ()" | |
12a4e8c5 GK |
13694 | "* |
13695 | { | |
13696 | return output_cbranch (operands[0], NULL, 0, insn); | |
13697 | }" | |
b7ff3d82 | 13698 | [(set_attr "type" "branch") |
39a10a29 | 13699 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
13700 | |
13701 | (define_insn "" | |
13702 | [(set (pc) | |
13703 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13704 | [(match_operand 2 | |
b54cf83a | 13705 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13706 | (const_int 0)]) |
13707 | (pc) | |
13708 | (label_ref (match_operand 0 "" ""))))] | |
13709 | "" | |
b19003d8 RK |
13710 | "* |
13711 | { | |
12a4e8c5 | 13712 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13713 | }" |
13714 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13715 | |
13716 | (define_insn "" | |
13717 | [(set (pc) | |
13718 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13719 | [(match_operand 1 | |
b54cf83a | 13720 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13721 | (const_int 0)]) |
13722 | (pc) | |
13723 | (return)))] | |
13724 | "direct_return ()" | |
12a4e8c5 GK |
13725 | "* |
13726 | { | |
13727 | return output_cbranch (operands[0], NULL, 1, insn); | |
13728 | }" | |
b7ff3d82 | 13729 | [(set_attr "type" "branch") |
39a10a29 GK |
13730 | (set_attr "length" "4")]) |
13731 | ||
13732 | ;; Logic on condition register values. | |
13733 | ||
13734 | ; This pattern matches things like | |
13735 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
13736 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
13737 | ; (const_int 1))) | |
13738 | ; which are generated by the branch logic. | |
b54cf83a | 13739 | ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) |
39a10a29 | 13740 | |
423c1189 | 13741 | (define_insn "*cceq_ior_compare" |
b54cf83a | 13742 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13743 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" |
b54cf83a | 13744 | [(match_operator:SI 2 |
39a10a29 GK |
13745 | "branch_positive_comparison_operator" |
13746 | [(match_operand 3 | |
b54cf83a | 13747 | "cc_reg_operand" "y,y") |
39a10a29 | 13748 | (const_int 0)]) |
b54cf83a | 13749 | (match_operator:SI 4 |
39a10a29 GK |
13750 | "branch_positive_comparison_operator" |
13751 | [(match_operand 5 | |
b54cf83a | 13752 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13753 | (const_int 0)])]) |
13754 | (const_int 1)))] | |
24fab1d3 | 13755 | "" |
39a10a29 | 13756 | "cr%q1 %E0,%j2,%j4" |
b54cf83a | 13757 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13758 | |
13759 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
13760 | ; Because ~1 has all but the low bit set. | |
13761 | (define_insn "" | |
b54cf83a | 13762 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13763 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" |
b54cf83a | 13764 | [(not:SI (match_operator:SI 2 |
39a10a29 GK |
13765 | "branch_positive_comparison_operator" |
13766 | [(match_operand 3 | |
b54cf83a | 13767 | "cc_reg_operand" "y,y") |
39a10a29 GK |
13768 | (const_int 0)])) |
13769 | (match_operator:SI 4 | |
13770 | "branch_positive_comparison_operator" | |
13771 | [(match_operand 5 | |
b54cf83a | 13772 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13773 | (const_int 0)])]) |
13774 | (const_int -1)))] | |
13775 | "" | |
13776 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13777 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 | 13778 | |
423c1189 | 13779 | (define_insn "*cceq_rev_compare" |
b54cf83a | 13780 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
6c873122 | 13781 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 13782 | "branch_positive_comparison_operator" |
6c873122 | 13783 | [(match_operand 2 |
b54cf83a | 13784 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13785 | (const_int 0)]) |
13786 | (const_int 0)))] | |
423c1189 | 13787 | "" |
251b3667 | 13788 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
b54cf83a | 13789 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13790 | |
13791 | ;; If we are comparing the result of two comparisons, this can be done | |
13792 | ;; using creqv or crxor. | |
13793 | ||
13794 | (define_insn_and_split "" | |
13795 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13796 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
13797 | [(match_operand 2 "cc_reg_operand" "y") | |
13798 | (const_int 0)]) | |
13799 | (match_operator 3 "branch_comparison_operator" | |
13800 | [(match_operand 4 "cc_reg_operand" "y") | |
13801 | (const_int 0)])))] | |
13802 | "" | |
13803 | "#" | |
13804 | "" | |
13805 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13806 | (match_dup 5)))] | |
13807 | " | |
13808 | { | |
13809 | int positive_1, positive_2; | |
13810 | ||
13811 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
13812 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
13813 | ||
13814 | if (! positive_1) | |
1c563bed | 13815 | operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), |
0f4c242b KH |
13816 | GET_CODE (operands[1])), |
13817 | SImode, | |
13818 | operands[2], const0_rtx); | |
39a10a29 | 13819 | else if (GET_MODE (operands[1]) != SImode) |
0f4c242b KH |
13820 | operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, |
13821 | operands[2], const0_rtx); | |
39a10a29 GK |
13822 | |
13823 | if (! positive_2) | |
1c563bed | 13824 | operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), |
0f4c242b KH |
13825 | GET_CODE (operands[3])), |
13826 | SImode, | |
13827 | operands[4], const0_rtx); | |
39a10a29 | 13828 | else if (GET_MODE (operands[3]) != SImode) |
0f4c242b KH |
13829 | operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
13830 | operands[4], const0_rtx); | |
39a10a29 GK |
13831 | |
13832 | if (positive_1 == positive_2) | |
251b3667 DE |
13833 | { |
13834 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13835 | operands[5] = constm1_rtx; | |
13836 | } | |
13837 | else | |
13838 | { | |
13839 | operands[5] = const1_rtx; | |
13840 | } | |
39a10a29 | 13841 | }") |
1fd4e8c1 RK |
13842 | |
13843 | ;; Unconditional branch and return. | |
13844 | ||
13845 | (define_insn "jump" | |
13846 | [(set (pc) | |
13847 | (label_ref (match_operand 0 "" "")))] | |
13848 | "" | |
b7ff3d82 DE |
13849 | "b %l0" |
13850 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13851 | |
13852 | (define_insn "return" | |
13853 | [(return)] | |
13854 | "direct_return ()" | |
324e52cc TG |
13855 | "{br|blr}" |
13856 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13857 | |
0ad91047 DE |
13858 | (define_expand "indirect_jump" |
13859 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 13860 | "" |
0ad91047 DE |
13861 | " |
13862 | { | |
13863 | if (TARGET_32BIT) | |
13864 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
13865 | else | |
13866 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
13867 | DONE; | |
13868 | }") | |
13869 | ||
13870 | (define_insn "indirect_jumpsi" | |
b92b324d | 13871 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 13872 | "TARGET_32BIT" |
b92b324d DE |
13873 | "@ |
13874 | bctr | |
13875 | {br|blr}" | |
324e52cc | 13876 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13877 | |
0ad91047 | 13878 | (define_insn "indirect_jumpdi" |
b92b324d | 13879 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 13880 | "TARGET_64BIT" |
b92b324d DE |
13881 | "@ |
13882 | bctr | |
13883 | blr" | |
266eb58a DE |
13884 | [(set_attr "type" "jmpreg")]) |
13885 | ||
1fd4e8c1 RK |
13886 | ;; Table jump for switch statements: |
13887 | (define_expand "tablejump" | |
e6ca2c17 DE |
13888 | [(use (match_operand 0 "" "")) |
13889 | (use (label_ref (match_operand 1 "" "")))] | |
13890 | "" | |
13891 | " | |
13892 | { | |
13893 | if (TARGET_32BIT) | |
13894 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13895 | else | |
13896 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13897 | DONE; | |
13898 | }") | |
13899 | ||
13900 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13901 | [(set (match_dup 3) |
13902 | (plus:SI (match_operand:SI 0 "" "") | |
13903 | (match_dup 2))) | |
13904 | (parallel [(set (pc) (match_dup 3)) | |
13905 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13906 | "TARGET_32BIT" |
1fd4e8c1 RK |
13907 | " |
13908 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13909 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13910 | operands[3] = gen_reg_rtx (SImode); |
13911 | }") | |
13912 | ||
e6ca2c17 | 13913 | (define_expand "tablejumpdi" |
6ae08853 | 13914 | [(set (match_dup 4) |
9ebbca7d GK |
13915 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) |
13916 | (set (match_dup 3) | |
13917 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13918 | (match_dup 2))) |
13919 | (parallel [(set (pc) (match_dup 3)) | |
13920 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13921 | "TARGET_64BIT" |
e6ca2c17 | 13922 | " |
9ebbca7d | 13923 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13924 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13925 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13926 | }") |
13927 | ||
1fd4e8c1 RK |
13928 | (define_insn "" |
13929 | [(set (pc) | |
c859cda6 | 13930 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13931 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13932 | "TARGET_32BIT" |
c859cda6 DJ |
13933 | "@ |
13934 | bctr | |
13935 | {br|blr}" | |
a6845123 | 13936 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13937 | |
266eb58a DE |
13938 | (define_insn "" |
13939 | [(set (pc) | |
c859cda6 | 13940 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 13941 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13942 | "TARGET_64BIT" |
c859cda6 DJ |
13943 | "@ |
13944 | bctr | |
13945 | blr" | |
266eb58a DE |
13946 | [(set_attr "type" "jmpreg")]) |
13947 | ||
1fd4e8c1 RK |
13948 | (define_insn "nop" |
13949 | [(const_int 0)] | |
13950 | "" | |
ca7f5001 | 13951 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13952 | \f |
7e69e155 | 13953 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13954 | ;; so loop.c knows what to generate. |
13955 | ||
5527bf14 RH |
13956 | (define_expand "doloop_end" |
13957 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13958 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13959 | (use (match_operand 2 "" "")) ; max iterations | |
13960 | (use (match_operand 3 "" "")) ; loop level | |
13961 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13962 | "" |
13963 | " | |
13964 | { | |
5527bf14 RH |
13965 | /* Only use this on innermost loops. */ |
13966 | if (INTVAL (operands[3]) > 1) | |
13967 | FAIL; | |
683bdff7 | 13968 | if (TARGET_64BIT) |
5527bf14 RH |
13969 | { |
13970 | if (GET_MODE (operands[0]) != DImode) | |
13971 | FAIL; | |
13972 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13973 | } | |
0ad91047 | 13974 | else |
5527bf14 RH |
13975 | { |
13976 | if (GET_MODE (operands[0]) != SImode) | |
13977 | FAIL; | |
13978 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13979 | } | |
0ad91047 DE |
13980 | DONE; |
13981 | }") | |
13982 | ||
13983 | (define_expand "ctrsi" | |
3cb999d8 DE |
13984 | [(parallel [(set (pc) |
13985 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
13986 | (const_int 1)) | |
13987 | (label_ref (match_operand 1 "" "")) | |
13988 | (pc))) | |
b6c9286a MM |
13989 | (set (match_dup 0) |
13990 | (plus:SI (match_dup 0) | |
13991 | (const_int -1))) | |
5f81043f RK |
13992 | (clobber (match_scratch:CC 2 "")) |
13993 | (clobber (match_scratch:SI 3 ""))])] | |
683bdff7 | 13994 | "TARGET_32BIT" |
0ad91047 DE |
13995 | "") |
13996 | ||
13997 | (define_expand "ctrdi" | |
3cb999d8 DE |
13998 | [(parallel [(set (pc) |
13999 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
14000 | (const_int 1)) | |
14001 | (label_ref (match_operand 1 "" "")) | |
14002 | (pc))) | |
0ad91047 DE |
14003 | (set (match_dup 0) |
14004 | (plus:DI (match_dup 0) | |
14005 | (const_int -1))) | |
14006 | (clobber (match_scratch:CC 2 "")) | |
61c07d3c | 14007 | (clobber (match_scratch:DI 3 ""))])] |
683bdff7 | 14008 | "TARGET_64BIT" |
61c07d3c | 14009 | "") |
c225ba7b | 14010 | |
1fd4e8c1 RK |
14011 | ;; We need to be able to do this for any operand, including MEM, or we |
14012 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 14013 | ;; JUMP_INSNs. |
0ad91047 | 14014 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
14015 | ;; label MUST be operand 0. |
14016 | ||
0ad91047 | 14017 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 14018 | [(set (pc) |
43b68ce5 | 14019 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 14020 | (const_int 1)) |
a6845123 | 14021 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14022 | (pc))) |
b150f4f3 | 14023 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14024 | (plus:SI (match_dup 1) |
14025 | (const_int -1))) | |
43b68ce5 DE |
14026 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14027 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14028 | "TARGET_32BIT" |
b19003d8 RK |
14029 | "* |
14030 | { | |
af87a13e | 14031 | if (which_alternative != 0) |
b19003d8 | 14032 | return \"#\"; |
856a6884 | 14033 | else if (get_attr_length (insn) == 4) |
a6845123 | 14034 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 14035 | else |
f607bc57 | 14036 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 14037 | }" |
baf97f86 | 14038 | [(set_attr "type" "branch") |
5a195cb5 | 14039 | (set_attr "length" "*,12,16,16")]) |
7e69e155 | 14040 | |
0ad91047 | 14041 | (define_insn "*ctrsi_internal2" |
5f81043f | 14042 | [(set (pc) |
43b68ce5 | 14043 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
14044 | (const_int 1)) |
14045 | (pc) | |
14046 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14047 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14048 | (plus:SI (match_dup 1) |
14049 | (const_int -1))) | |
43b68ce5 DE |
14050 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14051 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14052 | "TARGET_32BIT" |
0ad91047 DE |
14053 | "* |
14054 | { | |
14055 | if (which_alternative != 0) | |
14056 | return \"#\"; | |
856a6884 | 14057 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14058 | return \"bdz %l0\"; |
14059 | else | |
f607bc57 | 14060 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14061 | }" |
14062 | [(set_attr "type" "branch") | |
5a195cb5 | 14063 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14064 | |
14065 | (define_insn "*ctrdi_internal1" | |
14066 | [(set (pc) | |
43b68ce5 | 14067 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14068 | (const_int 1)) |
14069 | (label_ref (match_operand 0 "" "")) | |
14070 | (pc))) | |
b150f4f3 | 14071 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14072 | (plus:DI (match_dup 1) |
14073 | (const_int -1))) | |
43b68ce5 DE |
14074 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14075 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14076 | "TARGET_64BIT" |
0ad91047 DE |
14077 | "* |
14078 | { | |
14079 | if (which_alternative != 0) | |
14080 | return \"#\"; | |
856a6884 | 14081 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14082 | return \"{bdn|bdnz} %l0\"; |
14083 | else | |
f607bc57 | 14084 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14085 | }" |
14086 | [(set_attr "type" "branch") | |
5a195cb5 | 14087 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14088 | |
14089 | (define_insn "*ctrdi_internal2" | |
14090 | [(set (pc) | |
43b68ce5 | 14091 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14092 | (const_int 1)) |
14093 | (pc) | |
14094 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14095 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14096 | (plus:DI (match_dup 1) |
14097 | (const_int -1))) | |
43b68ce5 DE |
14098 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14099 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14100 | "TARGET_64BIT" |
5f81043f RK |
14101 | "* |
14102 | { | |
14103 | if (which_alternative != 0) | |
14104 | return \"#\"; | |
856a6884 | 14105 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14106 | return \"bdz %l0\"; |
14107 | else | |
f607bc57 | 14108 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
14109 | }" |
14110 | [(set_attr "type" "branch") | |
5a195cb5 | 14111 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14112 | |
0ad91047 DE |
14113 | ;; Similar but use EQ |
14114 | ||
14115 | (define_insn "*ctrsi_internal5" | |
5f81043f | 14116 | [(set (pc) |
43b68ce5 | 14117 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 14118 | (const_int 1)) |
a6845123 | 14119 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14120 | (pc))) |
b150f4f3 | 14121 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14122 | (plus:SI (match_dup 1) |
14123 | (const_int -1))) | |
43b68ce5 DE |
14124 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14125 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14126 | "TARGET_32BIT" |
b19003d8 RK |
14127 | "* |
14128 | { | |
af87a13e | 14129 | if (which_alternative != 0) |
b19003d8 | 14130 | return \"#\"; |
856a6884 | 14131 | else if (get_attr_length (insn) == 4) |
a6845123 | 14132 | return \"bdz %l0\"; |
b19003d8 | 14133 | else |
f607bc57 | 14134 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 14135 | }" |
baf97f86 | 14136 | [(set_attr "type" "branch") |
5a195cb5 | 14137 | (set_attr "length" "*,12,16,16")]) |
1fd4e8c1 | 14138 | |
0ad91047 | 14139 | (define_insn "*ctrsi_internal6" |
5f81043f | 14140 | [(set (pc) |
43b68ce5 | 14141 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
14142 | (const_int 1)) |
14143 | (pc) | |
14144 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14145 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14146 | (plus:SI (match_dup 1) |
14147 | (const_int -1))) | |
43b68ce5 DE |
14148 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14149 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14150 | "TARGET_32BIT" |
0ad91047 DE |
14151 | "* |
14152 | { | |
14153 | if (which_alternative != 0) | |
14154 | return \"#\"; | |
856a6884 | 14155 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14156 | return \"{bdn|bdnz} %l0\"; |
14157 | else | |
f607bc57 | 14158 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14159 | }" |
14160 | [(set_attr "type" "branch") | |
5a195cb5 | 14161 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14162 | |
14163 | (define_insn "*ctrdi_internal5" | |
14164 | [(set (pc) | |
43b68ce5 | 14165 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14166 | (const_int 1)) |
14167 | (label_ref (match_operand 0 "" "")) | |
14168 | (pc))) | |
b150f4f3 | 14169 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14170 | (plus:DI (match_dup 1) |
14171 | (const_int -1))) | |
43b68ce5 DE |
14172 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14173 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14174 | "TARGET_64BIT" |
0ad91047 DE |
14175 | "* |
14176 | { | |
14177 | if (which_alternative != 0) | |
14178 | return \"#\"; | |
856a6884 | 14179 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14180 | return \"bdz %l0\"; |
14181 | else | |
f607bc57 | 14182 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14183 | }" |
14184 | [(set_attr "type" "branch") | |
5a195cb5 | 14185 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14186 | |
14187 | (define_insn "*ctrdi_internal6" | |
14188 | [(set (pc) | |
43b68ce5 | 14189 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14190 | (const_int 1)) |
14191 | (pc) | |
14192 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14193 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14194 | (plus:DI (match_dup 1) |
14195 | (const_int -1))) | |
43b68ce5 DE |
14196 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14197 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14198 | "TARGET_64BIT" |
5f81043f RK |
14199 | "* |
14200 | { | |
14201 | if (which_alternative != 0) | |
14202 | return \"#\"; | |
856a6884 | 14203 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14204 | return \"{bdn|bdnz} %l0\"; |
14205 | else | |
f607bc57 | 14206 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
14207 | }" |
14208 | [(set_attr "type" "branch") | |
5a195cb5 | 14209 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14210 | |
0ad91047 DE |
14211 | ;; Now the splitters if we could not allocate the CTR register |
14212 | ||
1fd4e8c1 RK |
14213 | (define_split |
14214 | [(set (pc) | |
14215 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14216 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14217 | (const_int 1)]) |
14218 | (match_operand 5 "" "") | |
14219 | (match_operand 6 "" ""))) | |
cd2b37d9 | 14220 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
14221 | (plus:SI (match_dup 1) |
14222 | (const_int -1))) | |
1fd4e8c1 RK |
14223 | (clobber (match_scratch:CC 3 "")) |
14224 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14225 | "TARGET_32BIT && reload_completed" |
1fd4e8c1 | 14226 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14227 | (compare:CC (plus:SI (match_dup 1) |
14228 | (const_int -1)) | |
1fd4e8c1 | 14229 | (const_int 0))) |
5f81043f RK |
14230 | (set (match_dup 0) |
14231 | (plus:SI (match_dup 1) | |
14232 | (const_int -1)))]) | |
14233 | (set (pc) (if_then_else (match_dup 7) | |
14234 | (match_dup 5) | |
14235 | (match_dup 6)))] | |
1fd4e8c1 | 14236 | " |
0f4c242b KH |
14237 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14238 | operands[3], const0_rtx); }") | |
1fd4e8c1 RK |
14239 | |
14240 | (define_split | |
14241 | [(set (pc) | |
14242 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14243 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14244 | (const_int 1)]) |
14245 | (match_operand 5 "" "") | |
14246 | (match_operand 6 "" ""))) | |
9ebbca7d | 14247 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
14248 | (plus:SI (match_dup 1) (const_int -1))) |
14249 | (clobber (match_scratch:CC 3 "")) | |
14250 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14251 | "TARGET_32BIT && reload_completed |
0ad91047 | 14252 | && ! gpc_reg_operand (operands[0], SImode)" |
1fd4e8c1 | 14253 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14254 | (compare:CC (plus:SI (match_dup 1) |
14255 | (const_int -1)) | |
1fd4e8c1 | 14256 | (const_int 0))) |
5f81043f RK |
14257 | (set (match_dup 4) |
14258 | (plus:SI (match_dup 1) | |
14259 | (const_int -1)))]) | |
14260 | (set (match_dup 0) | |
14261 | (match_dup 4)) | |
14262 | (set (pc) (if_then_else (match_dup 7) | |
14263 | (match_dup 5) | |
14264 | (match_dup 6)))] | |
1fd4e8c1 | 14265 | " |
0f4c242b KH |
14266 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14267 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14268 | (define_split |
14269 | [(set (pc) | |
14270 | (if_then_else (match_operator 2 "comparison_operator" | |
14271 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14272 | (const_int 1)]) | |
61c07d3c DE |
14273 | (match_operand 5 "" "") |
14274 | (match_operand 6 "" ""))) | |
0ad91047 DE |
14275 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
14276 | (plus:DI (match_dup 1) | |
14277 | (const_int -1))) | |
14278 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14279 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14280 | "TARGET_64BIT && reload_completed" |
0ad91047 DE |
14281 | [(parallel [(set (match_dup 3) |
14282 | (compare:CC (plus:DI (match_dup 1) | |
14283 | (const_int -1)) | |
14284 | (const_int 0))) | |
14285 | (set (match_dup 0) | |
14286 | (plus:DI (match_dup 1) | |
14287 | (const_int -1)))]) | |
61c07d3c DE |
14288 | (set (pc) (if_then_else (match_dup 7) |
14289 | (match_dup 5) | |
14290 | (match_dup 6)))] | |
0ad91047 | 14291 | " |
0f4c242b KH |
14292 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14293 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14294 | |
14295 | (define_split | |
14296 | [(set (pc) | |
14297 | (if_then_else (match_operator 2 "comparison_operator" | |
14298 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14299 | (const_int 1)]) | |
61c07d3c DE |
14300 | (match_operand 5 "" "") |
14301 | (match_operand 6 "" ""))) | |
9ebbca7d | 14302 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
14303 | (plus:DI (match_dup 1) (const_int -1))) |
14304 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14305 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14306 | "TARGET_64BIT && reload_completed |
0ad91047 DE |
14307 | && ! gpc_reg_operand (operands[0], DImode)" |
14308 | [(parallel [(set (match_dup 3) | |
14309 | (compare:CC (plus:DI (match_dup 1) | |
14310 | (const_int -1)) | |
14311 | (const_int 0))) | |
14312 | (set (match_dup 4) | |
14313 | (plus:DI (match_dup 1) | |
14314 | (const_int -1)))]) | |
14315 | (set (match_dup 0) | |
14316 | (match_dup 4)) | |
61c07d3c DE |
14317 | (set (pc) (if_then_else (match_dup 7) |
14318 | (match_dup 5) | |
14319 | (match_dup 6)))] | |
0ad91047 | 14320 | " |
0f4c242b KH |
14321 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14322 | operands[3], const0_rtx); }") | |
e0cd0770 JC |
14323 | \f |
14324 | (define_insn "trap" | |
14325 | [(trap_if (const_int 1) (const_int 0))] | |
14326 | "" | |
14327 | "{t 31,0,0|trap}") | |
14328 | ||
14329 | (define_expand "conditional_trap" | |
14330 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14331 | [(match_dup 2) (match_dup 3)]) | |
14332 | (match_operand 1 "const_int_operand" ""))] | |
14333 | "" | |
14334 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14335 | operands[2] = rs6000_compare_op0; | |
14336 | operands[3] = rs6000_compare_op1;") | |
14337 | ||
14338 | (define_insn "" | |
14339 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14340 | [(match_operand:SI 1 "register_operand" "r") | |
14341 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14342 | (const_int 0))] | |
14343 | "" | |
a157febd GK |
14344 | "{t|tw}%V0%I2 %1,%2") |
14345 | ||
14346 | (define_insn "" | |
14347 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14348 | [(match_operand:DI 1 "register_operand" "r") | |
14349 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14350 | (const_int 0))] | |
14351 | "TARGET_POWERPC64" | |
14352 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14353 | \f |
14354 | ;; Insns related to generating the function prologue and epilogue. | |
14355 | ||
14356 | (define_expand "prologue" | |
14357 | [(use (const_int 0))] | |
14358 | "TARGET_SCHED_PROLOG" | |
14359 | " | |
14360 | { | |
14361 | rs6000_emit_prologue (); | |
14362 | DONE; | |
14363 | }") | |
14364 | ||
2c4a9cff DE |
14365 | (define_insn "*movesi_from_cr_one" |
14366 | [(match_parallel 0 "mfcr_operation" | |
14367 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14368 | (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") | |
14369 | (match_operand 3 "immediate_operand" "n")] | |
14370 | UNSPEC_MOVESI_FROM_CR))])] | |
14371 | "TARGET_MFCRF" | |
14372 | "* | |
14373 | { | |
14374 | int mask = 0; | |
14375 | int i; | |
14376 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14377 | { | |
14378 | mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14379 | operands[4] = GEN_INT (mask); | |
14380 | output_asm_insn (\"mfcr %1,%4\", operands); | |
14381 | } | |
14382 | return \"\"; | |
14383 | }" | |
14384 | [(set_attr "type" "mfcrf")]) | |
14385 | ||
9ebbca7d GK |
14386 | (define_insn "movesi_from_cr" |
14387 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 14388 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) |
615158e2 JJ |
14389 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] |
14390 | UNSPEC_MOVESI_FROM_CR))] | |
9ebbca7d | 14391 | "" |
309323c2 | 14392 | "mfcr %0" |
b54cf83a | 14393 | [(set_attr "type" "mfcr")]) |
9ebbca7d GK |
14394 | |
14395 | (define_insn "*stmw" | |
e033a023 DE |
14396 | [(match_parallel 0 "stmw_operation" |
14397 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14398 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14399 | "TARGET_MULTIPLE" | |
14400 | "{stm|stmw} %2,%1") | |
6ae08853 | 14401 | |
9ebbca7d | 14402 | (define_insn "*save_fpregs_si" |
85d346f1 | 14403 | [(match_parallel 0 "any_parallel_operand" |
e033a023 DE |
14404 | [(clobber (match_operand:SI 1 "register_operand" "=l")) |
14405 | (use (match_operand:SI 2 "call_operand" "s")) | |
14406 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14407 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14408 | "TARGET_32BIT" | |
14409 | "bl %z2" | |
14410 | [(set_attr "type" "branch") | |
14411 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14412 | |
14413 | (define_insn "*save_fpregs_di" | |
85d346f1 | 14414 | [(match_parallel 0 "any_parallel_operand" |
e033a023 DE |
14415 | [(clobber (match_operand:DI 1 "register_operand" "=l")) |
14416 | (use (match_operand:DI 2 "call_operand" "s")) | |
14417 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14418 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14419 | "TARGET_64BIT" | |
14420 | "bl %z2" | |
14421 | [(set_attr "type" "branch") | |
14422 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14423 | |
14424 | ; These are to explain that changes to the stack pointer should | |
14425 | ; not be moved over stores to stack memory. | |
14426 | (define_insn "stack_tie" | |
14427 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
615158e2 | 14428 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] |
9ebbca7d GK |
14429 | "" |
14430 | "" | |
14431 | [(set_attr "length" "0")]) | |
14432 | ||
14433 | ||
14434 | (define_expand "epilogue" | |
14435 | [(use (const_int 0))] | |
14436 | "TARGET_SCHED_PROLOG" | |
14437 | " | |
14438 | { | |
14439 | rs6000_emit_epilogue (FALSE); | |
14440 | DONE; | |
14441 | }") | |
14442 | ||
14443 | ; On some processors, doing the mtcrf one CC register at a time is | |
14444 | ; faster (like on the 604e). On others, doing them all at once is | |
14445 | ; faster; for instance, on the 601 and 750. | |
14446 | ||
14447 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
14448 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14449 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 | 14450 | (match_dup 2)] UNSPEC_MOVESI_TO_CR))] |
35aba846 DE |
14451 | "" |
14452 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
14453 | |
14454 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
14455 | [(match_parallel 0 "mtcrf_operation" |
14456 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
14457 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
14458 | (match_operand 3 "immediate_operand" "n")] | |
615158e2 | 14459 | UNSPEC_MOVESI_TO_CR))])] |
9ebbca7d | 14460 | "" |
e35b9579 GK |
14461 | "* |
14462 | { | |
14463 | int mask = 0; | |
14464 | int i; | |
14465 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14466 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14467 | operands[4] = GEN_INT (mask); | |
14468 | return \"mtcrf %4,%2\"; | |
309323c2 | 14469 | }" |
b54cf83a | 14470 | [(set_attr "type" "mtcr")]) |
9ebbca7d | 14471 | |
b54cf83a | 14472 | (define_insn "*mtcrfsi" |
309323c2 DE |
14473 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14474 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 JJ |
14475 | (match_operand 2 "immediate_operand" "n")] |
14476 | UNSPEC_MOVESI_TO_CR))] | |
6ae08853 | 14477 | "GET_CODE (operands[0]) == REG |
309323c2 DE |
14478 | && CR_REGNO_P (REGNO (operands[0])) |
14479 | && GET_CODE (operands[2]) == CONST_INT | |
14480 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14481 | "mtcrf %R0,%1" | |
b54cf83a | 14482 | [(set_attr "type" "mtcr")]) |
9ebbca7d GK |
14483 | |
14484 | ; The load-multiple instructions have similar properties. | |
14485 | ; Note that "load_multiple" is a name known to the machine-independent | |
14486 | ; code that actually corresponds to the powerpc load-string. | |
14487 | ||
14488 | (define_insn "*lmw" | |
35aba846 DE |
14489 | [(match_parallel 0 "lmw_operation" |
14490 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14491 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14492 | "TARGET_MULTIPLE" | |
14493 | "{lm|lmw} %1,%2") | |
6ae08853 | 14494 | |
9ebbca7d | 14495 | (define_insn "*return_internal_si" |
e35b9579 GK |
14496 | [(return) |
14497 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 14498 | "TARGET_32BIT" |
cccf3bdc | 14499 | "b%T0" |
9ebbca7d GK |
14500 | [(set_attr "type" "jmpreg")]) |
14501 | ||
14502 | (define_insn "*return_internal_di" | |
e35b9579 GK |
14503 | [(return) |
14504 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 14505 | "TARGET_64BIT" |
cccf3bdc | 14506 | "b%T0" |
9ebbca7d GK |
14507 | [(set_attr "type" "jmpreg")]) |
14508 | ||
14509 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
85d346f1 | 14510 | ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible... |
9ebbca7d GK |
14511 | |
14512 | (define_insn "*return_and_restore_fpregs_si" | |
85d346f1 | 14513 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 GK |
14514 | [(return) |
14515 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
14516 | (use (match_operand:SI 2 "call_operand" "s")) |
14517 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14518 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14519 | "TARGET_32BIT" | |
14520 | "b %z2") | |
14521 | ||
14522 | (define_insn "*return_and_restore_fpregs_di" | |
85d346f1 | 14523 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 GK |
14524 | [(return) |
14525 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
14526 | (use (match_operand:DI 2 "call_operand" "s")) |
14527 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14528 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14529 | "TARGET_64BIT" | |
14530 | "b %z2") | |
14531 | ||
83720594 RH |
14532 | ; This is used in compiling the unwind routines. |
14533 | (define_expand "eh_return" | |
34dc173c | 14534 | [(use (match_operand 0 "general_operand" ""))] |
9ebbca7d GK |
14535 | "" |
14536 | " | |
14537 | { | |
83720594 | 14538 | if (TARGET_32BIT) |
34dc173c | 14539 | emit_insn (gen_eh_set_lr_si (operands[0])); |
9ebbca7d | 14540 | else |
34dc173c | 14541 | emit_insn (gen_eh_set_lr_di (operands[0])); |
9ebbca7d GK |
14542 | DONE; |
14543 | }") | |
14544 | ||
83720594 RH |
14545 | ; We can't expand this before we know where the link register is stored. |
14546 | (define_insn "eh_set_lr_si" | |
615158e2 JJ |
14547 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] |
14548 | UNSPECV_EH_RR) | |
466eb3e0 | 14549 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
14550 | "TARGET_32BIT" |
14551 | "#") | |
14552 | ||
14553 | (define_insn "eh_set_lr_di" | |
615158e2 JJ |
14554 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
14555 | UNSPECV_EH_RR) | |
466eb3e0 | 14556 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
14557 | "TARGET_64BIT" |
14558 | "#") | |
9ebbca7d GK |
14559 | |
14560 | (define_split | |
615158e2 | 14561 | [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) |
83720594 RH |
14562 | (clobber (match_scratch 1 ""))] |
14563 | "reload_completed" | |
14564 | [(const_int 0)] | |
9ebbca7d GK |
14565 | " |
14566 | { | |
d1d0c603 | 14567 | rs6000_emit_eh_reg_restore (operands[0], operands[1]); |
83720594 RH |
14568 | DONE; |
14569 | }") | |
0ac081f6 | 14570 | |
01a2ccd0 DE |
14571 | (define_insn "prefetch" |
14572 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
14573 | (match_operand:SI 1 "const_int_operand" "n") |
14574 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 14575 | "TARGET_POWERPC" |
6041bf2f DE |
14576 | "* |
14577 | { | |
01a2ccd0 DE |
14578 | if (GET_CODE (operands[0]) == REG) |
14579 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
14580 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
14581 | }" |
14582 | [(set_attr "type" "load")]) | |
a3170dc6 | 14583 | |
10ed84db | 14584 | (include "altivec.md") |
a3170dc6 | 14585 | (include "spe.md") |