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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
affad9a4 | 3 | ;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 | 5 | |
5de601cf | 6 | ;; This file is part of GCC. |
1fd4e8c1 | 7 | |
5de601cf NC |
8 | ;; GCC is free software; you can redistribute it and/or modify it |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
1fd4e8c1 | 12 | |
5de601cf NC |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
1fd4e8c1 RK |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
5de601cf NC |
19 | ;; along with GCC; see the file COPYING. If not, write to the |
20 | ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | ;; MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d | 24 | |
615158e2 JJ |
25 | ;; |
26 | ;; UNSPEC usage | |
27 | ;; | |
28 | ||
29 | (define_constants | |
30 | [(UNSPEC_FRSP 0) ; frsp for POWER machines | |
31 | (UNSPEC_TIE 5) ; tie stack contents and stack pointer | |
32 | (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC | |
33 | (UNSPEC_TOC 7) ; address of the TOC (more-or-less) | |
34 | (UNSPEC_MOVSI_GOT 8) | |
35 | (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit | |
36 | (UNSPEC_FCTIWZ 10) | |
37 | (UNSPEC_LD_MPIC 15) ; load_macho_picbase | |
38 | (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic | |
39 | (UNSPEC_TLSGD 17) | |
40 | (UNSPEC_TLSLD 18) | |
41 | (UNSPEC_MOVESI_FROM_CR 19) | |
42 | (UNSPEC_MOVESI_TO_CR 20) | |
43 | (UNSPEC_TLSDTPREL 21) | |
44 | (UNSPEC_TLSDTPRELHA 22) | |
45 | (UNSPEC_TLSDTPRELLO 23) | |
46 | (UNSPEC_TLSGOTDTPREL 24) | |
47 | (UNSPEC_TLSTPREL 25) | |
48 | (UNSPEC_TLSTPRELHA 26) | |
49 | (UNSPEC_TLSTPRELLO 27) | |
50 | (UNSPEC_TLSGOTTPREL 28) | |
51 | (UNSPEC_TLSTLS 29) | |
ecb62ae7 | 52 | (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero |
6b1fedc3 | 53 | (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit |
615158e2 JJ |
54 | ]) |
55 | ||
56 | ;; | |
57 | ;; UNSPEC_VOLATILE usage | |
58 | ;; | |
59 | ||
60 | (define_constants | |
61 | [(UNSPECV_BLOCK 0) | |
62 | (UNSPECV_EH_RR 9) ; eh_reg_restore | |
63 | ]) | |
1fd4e8c1 RK |
64 | \f |
65 | ;; Define an insn type attribute. This is used in function unit delay | |
66 | ;; computations. | |
2c4a9cff | 67 | (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" |
1fd4e8c1 RK |
68 | (const_string "integer")) |
69 | ||
b19003d8 | 70 | ;; Length (in bytes). |
6ae08853 | 71 | ; '(pc)' in the following doesn't include the instruction itself; it is |
6cbadf36 | 72 | ; calculated as if the instruction had zero size. |
b19003d8 RK |
73 | (define_attr "length" "" |
74 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 75 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 76 | (const_int -32768)) |
6cbadf36 GK |
77 | (lt (minus (match_dup 0) (pc)) |
78 | (const_int 32764))) | |
39a10a29 GK |
79 | (const_int 4) |
80 | (const_int 8)) | |
b19003d8 RK |
81 | (const_int 4))) |
82 | ||
cfb557c4 RK |
83 | ;; Processor type -- this attribute must exactly match the processor_type |
84 | ;; enumeration in rs6000.h. | |
85 | ||
ec507f2d | 86 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" |
cfb557c4 RK |
87 | (const (symbol_ref "rs6000_cpu_attr"))) |
88 | ||
b54cf83a DE |
89 | (automata_option "ndfa") |
90 | ||
91 | (include "rios1.md") | |
92 | (include "rios2.md") | |
93 | (include "rs64.md") | |
94 | (include "mpc.md") | |
95 | (include "40x.md") | |
02ca7595 | 96 | (include "440.md") |
b54cf83a DE |
97 | (include "603.md") |
98 | (include "6xx.md") | |
99 | (include "7xx.md") | |
100 | (include "7450.md") | |
5e8006fa | 101 | (include "8540.md") |
b54cf83a | 102 | (include "power4.md") |
ec507f2d | 103 | (include "power5.md") |
ac9e2cff | 104 | (include "darwin.md") |
309323c2 | 105 | |
1fd4e8c1 | 106 | \f |
2e6c9641 FJ |
107 | ;; This mode macro allows :P to be used for patterns that operate on |
108 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
109 | (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) | |
110 | ||
1fd4e8c1 RK |
111 | ;; Start with fixed-point load and store insns. Here we put only the more |
112 | ;; complex forms. Basic data transfer is done later. | |
113 | ||
51b8fc2c RK |
114 | (define_expand "zero_extendqidi2" |
115 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
116 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
117 | "TARGET_POWERPC64" | |
118 | "") | |
119 | ||
120 | (define_insn "" | |
121 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
122 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
123 | "TARGET_POWERPC64" | |
124 | "@ | |
125 | lbz%U1%X1 %0,%1 | |
4371f8af | 126 | rldicl %0,%1,0,56" |
51b8fc2c RK |
127 | [(set_attr "type" "load,*")]) |
128 | ||
129 | (define_insn "" | |
9ebbca7d GK |
130 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
131 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 132 | (const_int 0))) |
9ebbca7d | 133 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 134 | "TARGET_64BIT" |
9ebbca7d GK |
135 | "@ |
136 | rldicl. %2,%1,0,56 | |
137 | #" | |
138 | [(set_attr "type" "compare") | |
139 | (set_attr "length" "4,8")]) | |
140 | ||
141 | (define_split | |
142 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
143 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
144 | (const_int 0))) | |
145 | (clobber (match_scratch:DI 2 ""))] | |
146 | "TARGET_POWERPC64 && reload_completed" | |
147 | [(set (match_dup 2) | |
148 | (zero_extend:DI (match_dup 1))) | |
149 | (set (match_dup 0) | |
150 | (compare:CC (match_dup 2) | |
151 | (const_int 0)))] | |
152 | "") | |
51b8fc2c RK |
153 | |
154 | (define_insn "" | |
9ebbca7d GK |
155 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
156 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 157 | (const_int 0))) |
9ebbca7d | 158 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 159 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 160 | "TARGET_64BIT" |
9ebbca7d GK |
161 | "@ |
162 | rldicl. %0,%1,0,56 | |
163 | #" | |
164 | [(set_attr "type" "compare") | |
165 | (set_attr "length" "4,8")]) | |
166 | ||
167 | (define_split | |
168 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
169 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
170 | (const_int 0))) | |
171 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
172 | (zero_extend:DI (match_dup 1)))] | |
173 | "TARGET_POWERPC64 && reload_completed" | |
174 | [(set (match_dup 0) | |
175 | (zero_extend:DI (match_dup 1))) | |
176 | (set (match_dup 2) | |
177 | (compare:CC (match_dup 0) | |
178 | (const_int 0)))] | |
179 | "") | |
51b8fc2c | 180 | |
2bee0449 RK |
181 | (define_insn "extendqidi2" |
182 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
183 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 184 | "TARGET_POWERPC64" |
2bee0449 | 185 | "extsb %0,%1") |
51b8fc2c RK |
186 | |
187 | (define_insn "" | |
9ebbca7d GK |
188 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
189 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 190 | (const_int 0))) |
9ebbca7d | 191 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 192 | "TARGET_64BIT" |
9ebbca7d GK |
193 | "@ |
194 | extsb. %2,%1 | |
195 | #" | |
196 | [(set_attr "type" "compare") | |
197 | (set_attr "length" "4,8")]) | |
198 | ||
199 | (define_split | |
200 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
201 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
202 | (const_int 0))) | |
203 | (clobber (match_scratch:DI 2 ""))] | |
204 | "TARGET_POWERPC64 && reload_completed" | |
205 | [(set (match_dup 2) | |
206 | (sign_extend:DI (match_dup 1))) | |
207 | (set (match_dup 0) | |
208 | (compare:CC (match_dup 2) | |
209 | (const_int 0)))] | |
210 | "") | |
51b8fc2c RK |
211 | |
212 | (define_insn "" | |
9ebbca7d GK |
213 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
214 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 215 | (const_int 0))) |
9ebbca7d | 216 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 217 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 218 | "TARGET_64BIT" |
9ebbca7d GK |
219 | "@ |
220 | extsb. %0,%1 | |
221 | #" | |
222 | [(set_attr "type" "compare") | |
223 | (set_attr "length" "4,8")]) | |
224 | ||
225 | (define_split | |
226 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
227 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
228 | (const_int 0))) | |
229 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
230 | (sign_extend:DI (match_dup 1)))] | |
231 | "TARGET_POWERPC64 && reload_completed" | |
232 | [(set (match_dup 0) | |
233 | (sign_extend:DI (match_dup 1))) | |
234 | (set (match_dup 2) | |
235 | (compare:CC (match_dup 0) | |
236 | (const_int 0)))] | |
237 | "") | |
51b8fc2c RK |
238 | |
239 | (define_expand "zero_extendhidi2" | |
240 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
241 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
242 | "TARGET_POWERPC64" | |
243 | "") | |
244 | ||
245 | (define_insn "" | |
246 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
247 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
248 | "TARGET_POWERPC64" | |
249 | "@ | |
250 | lhz%U1%X1 %0,%1 | |
4371f8af | 251 | rldicl %0,%1,0,48" |
51b8fc2c RK |
252 | [(set_attr "type" "load,*")]) |
253 | ||
254 | (define_insn "" | |
9ebbca7d GK |
255 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
256 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 257 | (const_int 0))) |
9ebbca7d | 258 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 259 | "TARGET_64BIT" |
9ebbca7d GK |
260 | "@ |
261 | rldicl. %2,%1,0,48 | |
262 | #" | |
263 | [(set_attr "type" "compare") | |
264 | (set_attr "length" "4,8")]) | |
265 | ||
266 | (define_split | |
267 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
268 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
269 | (const_int 0))) | |
270 | (clobber (match_scratch:DI 2 ""))] | |
271 | "TARGET_POWERPC64 && reload_completed" | |
272 | [(set (match_dup 2) | |
273 | (zero_extend:DI (match_dup 1))) | |
274 | (set (match_dup 0) | |
275 | (compare:CC (match_dup 2) | |
276 | (const_int 0)))] | |
277 | "") | |
51b8fc2c RK |
278 | |
279 | (define_insn "" | |
9ebbca7d GK |
280 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
281 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 282 | (const_int 0))) |
9ebbca7d | 283 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 284 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 285 | "TARGET_64BIT" |
9ebbca7d GK |
286 | "@ |
287 | rldicl. %0,%1,0,48 | |
288 | #" | |
289 | [(set_attr "type" "compare") | |
290 | (set_attr "length" "4,8")]) | |
291 | ||
292 | (define_split | |
293 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
294 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
295 | (const_int 0))) | |
296 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
297 | (zero_extend:DI (match_dup 1)))] | |
298 | "TARGET_POWERPC64 && reload_completed" | |
299 | [(set (match_dup 0) | |
300 | (zero_extend:DI (match_dup 1))) | |
301 | (set (match_dup 2) | |
302 | (compare:CC (match_dup 0) | |
303 | (const_int 0)))] | |
304 | "") | |
51b8fc2c RK |
305 | |
306 | (define_expand "extendhidi2" | |
307 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
308 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
309 | "TARGET_POWERPC64" | |
310 | "") | |
311 | ||
312 | (define_insn "" | |
313 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
314 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
315 | "TARGET_POWERPC64" | |
316 | "@ | |
317 | lha%U1%X1 %0,%1 | |
318 | extsh %0,%1" | |
b54cf83a | 319 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
320 | |
321 | (define_insn "" | |
9ebbca7d GK |
322 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
323 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 324 | (const_int 0))) |
9ebbca7d | 325 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 326 | "TARGET_64BIT" |
9ebbca7d GK |
327 | "@ |
328 | extsh. %2,%1 | |
329 | #" | |
330 | [(set_attr "type" "compare") | |
331 | (set_attr "length" "4,8")]) | |
332 | ||
333 | (define_split | |
334 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
335 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
336 | (const_int 0))) | |
337 | (clobber (match_scratch:DI 2 ""))] | |
338 | "TARGET_POWERPC64 && reload_completed" | |
339 | [(set (match_dup 2) | |
340 | (sign_extend:DI (match_dup 1))) | |
341 | (set (match_dup 0) | |
342 | (compare:CC (match_dup 2) | |
343 | (const_int 0)))] | |
344 | "") | |
51b8fc2c RK |
345 | |
346 | (define_insn "" | |
9ebbca7d GK |
347 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
348 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 349 | (const_int 0))) |
9ebbca7d | 350 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 351 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 352 | "TARGET_64BIT" |
9ebbca7d GK |
353 | "@ |
354 | extsh. %0,%1 | |
355 | #" | |
356 | [(set_attr "type" "compare") | |
357 | (set_attr "length" "4,8")]) | |
358 | ||
359 | (define_split | |
360 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
361 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
362 | (const_int 0))) | |
363 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
364 | (sign_extend:DI (match_dup 1)))] | |
365 | "TARGET_POWERPC64 && reload_completed" | |
366 | [(set (match_dup 0) | |
367 | (sign_extend:DI (match_dup 1))) | |
368 | (set (match_dup 2) | |
369 | (compare:CC (match_dup 0) | |
370 | (const_int 0)))] | |
371 | "") | |
51b8fc2c RK |
372 | |
373 | (define_expand "zero_extendsidi2" | |
374 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
375 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
376 | "TARGET_POWERPC64" | |
377 | "") | |
378 | ||
379 | (define_insn "" | |
380 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
381 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
382 | "TARGET_POWERPC64" | |
383 | "@ | |
384 | lwz%U1%X1 %0,%1 | |
385 | rldicl %0,%1,0,32" | |
386 | [(set_attr "type" "load,*")]) | |
387 | ||
388 | (define_insn "" | |
9ebbca7d GK |
389 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
390 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 391 | (const_int 0))) |
9ebbca7d | 392 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 393 | "TARGET_64BIT" |
9ebbca7d GK |
394 | "@ |
395 | rldicl. %2,%1,0,32 | |
396 | #" | |
397 | [(set_attr "type" "compare") | |
398 | (set_attr "length" "4,8")]) | |
399 | ||
400 | (define_split | |
401 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
402 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
403 | (const_int 0))) | |
404 | (clobber (match_scratch:DI 2 ""))] | |
405 | "TARGET_POWERPC64 && reload_completed" | |
406 | [(set (match_dup 2) | |
407 | (zero_extend:DI (match_dup 1))) | |
408 | (set (match_dup 0) | |
409 | (compare:CC (match_dup 2) | |
410 | (const_int 0)))] | |
411 | "") | |
51b8fc2c RK |
412 | |
413 | (define_insn "" | |
9ebbca7d GK |
414 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
415 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 416 | (const_int 0))) |
9ebbca7d | 417 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 418 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 419 | "TARGET_64BIT" |
9ebbca7d GK |
420 | "@ |
421 | rldicl. %0,%1,0,32 | |
422 | #" | |
423 | [(set_attr "type" "compare") | |
424 | (set_attr "length" "4,8")]) | |
425 | ||
426 | (define_split | |
427 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
428 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
429 | (const_int 0))) | |
430 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
431 | (zero_extend:DI (match_dup 1)))] | |
432 | "TARGET_POWERPC64 && reload_completed" | |
433 | [(set (match_dup 0) | |
434 | (zero_extend:DI (match_dup 1))) | |
435 | (set (match_dup 2) | |
436 | (compare:CC (match_dup 0) | |
437 | (const_int 0)))] | |
438 | "") | |
51b8fc2c RK |
439 | |
440 | (define_expand "extendsidi2" | |
441 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
442 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
443 | "TARGET_POWERPC64" | |
444 | "") | |
445 | ||
446 | (define_insn "" | |
447 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 448 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
449 | "TARGET_POWERPC64" |
450 | "@ | |
451 | lwa%U1%X1 %0,%1 | |
452 | extsw %0,%1" | |
b54cf83a | 453 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
454 | |
455 | (define_insn "" | |
9ebbca7d GK |
456 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
457 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 458 | (const_int 0))) |
9ebbca7d | 459 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 460 | "TARGET_64BIT" |
9ebbca7d GK |
461 | "@ |
462 | extsw. %2,%1 | |
463 | #" | |
464 | [(set_attr "type" "compare") | |
465 | (set_attr "length" "4,8")]) | |
466 | ||
467 | (define_split | |
468 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
469 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
470 | (const_int 0))) | |
471 | (clobber (match_scratch:DI 2 ""))] | |
472 | "TARGET_POWERPC64 && reload_completed" | |
473 | [(set (match_dup 2) | |
474 | (sign_extend:DI (match_dup 1))) | |
475 | (set (match_dup 0) | |
476 | (compare:CC (match_dup 2) | |
477 | (const_int 0)))] | |
478 | "") | |
51b8fc2c RK |
479 | |
480 | (define_insn "" | |
9ebbca7d GK |
481 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
482 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 483 | (const_int 0))) |
9ebbca7d | 484 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 485 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 486 | "TARGET_64BIT" |
9ebbca7d GK |
487 | "@ |
488 | extsw. %0,%1 | |
489 | #" | |
490 | [(set_attr "type" "compare") | |
491 | (set_attr "length" "4,8")]) | |
492 | ||
493 | (define_split | |
494 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
495 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
496 | (const_int 0))) | |
497 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
498 | (sign_extend:DI (match_dup 1)))] | |
499 | "TARGET_POWERPC64 && reload_completed" | |
500 | [(set (match_dup 0) | |
501 | (sign_extend:DI (match_dup 1))) | |
502 | (set (match_dup 2) | |
503 | (compare:CC (match_dup 0) | |
504 | (const_int 0)))] | |
505 | "") | |
51b8fc2c | 506 | |
1fd4e8c1 | 507 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
508 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
509 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
510 | "" |
511 | "") | |
512 | ||
513 | (define_insn "" | |
cd2b37d9 | 514 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
515 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
516 | "" | |
517 | "@ | |
518 | lbz%U1%X1 %0,%1 | |
005a35b9 | 519 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
520 | [(set_attr "type" "load,*")]) |
521 | ||
522 | (define_insn "" | |
9ebbca7d GK |
523 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
524 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 525 | (const_int 0))) |
9ebbca7d | 526 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 527 | "" |
9ebbca7d GK |
528 | "@ |
529 | {andil.|andi.} %2,%1,0xff | |
530 | #" | |
531 | [(set_attr "type" "compare") | |
532 | (set_attr "length" "4,8")]) | |
533 | ||
534 | (define_split | |
535 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
536 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
537 | (const_int 0))) | |
538 | (clobber (match_scratch:SI 2 ""))] | |
539 | "reload_completed" | |
540 | [(set (match_dup 2) | |
541 | (zero_extend:SI (match_dup 1))) | |
542 | (set (match_dup 0) | |
543 | (compare:CC (match_dup 2) | |
544 | (const_int 0)))] | |
545 | "") | |
1fd4e8c1 RK |
546 | |
547 | (define_insn "" | |
9ebbca7d GK |
548 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
549 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 550 | (const_int 0))) |
9ebbca7d | 551 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
552 | (zero_extend:SI (match_dup 1)))] |
553 | "" | |
9ebbca7d GK |
554 | "@ |
555 | {andil.|andi.} %0,%1,0xff | |
556 | #" | |
557 | [(set_attr "type" "compare") | |
558 | (set_attr "length" "4,8")]) | |
559 | ||
560 | (define_split | |
561 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
562 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
563 | (const_int 0))) | |
564 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
565 | (zero_extend:SI (match_dup 1)))] | |
566 | "reload_completed" | |
567 | [(set (match_dup 0) | |
568 | (zero_extend:SI (match_dup 1))) | |
569 | (set (match_dup 2) | |
570 | (compare:CC (match_dup 0) | |
571 | (const_int 0)))] | |
572 | "") | |
1fd4e8c1 | 573 | |
51b8fc2c RK |
574 | (define_expand "extendqisi2" |
575 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
576 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
577 | "" | |
578 | " | |
579 | { | |
580 | if (TARGET_POWERPC) | |
581 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
582 | else if (TARGET_POWER) | |
583 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
584 | else | |
585 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
586 | DONE; | |
587 | }") | |
588 | ||
589 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
590 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
591 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 592 | "TARGET_POWERPC" |
2bee0449 | 593 | "extsb %0,%1") |
51b8fc2c RK |
594 | |
595 | (define_insn "" | |
9ebbca7d GK |
596 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
597 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 598 | (const_int 0))) |
9ebbca7d | 599 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 600 | "TARGET_POWERPC" |
9ebbca7d GK |
601 | "@ |
602 | extsb. %2,%1 | |
603 | #" | |
604 | [(set_attr "type" "compare") | |
605 | (set_attr "length" "4,8")]) | |
606 | ||
607 | (define_split | |
608 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
609 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
610 | (const_int 0))) | |
611 | (clobber (match_scratch:SI 2 ""))] | |
612 | "TARGET_POWERPC && reload_completed" | |
613 | [(set (match_dup 2) | |
614 | (sign_extend:SI (match_dup 1))) | |
615 | (set (match_dup 0) | |
616 | (compare:CC (match_dup 2) | |
617 | (const_int 0)))] | |
618 | "") | |
51b8fc2c RK |
619 | |
620 | (define_insn "" | |
9ebbca7d GK |
621 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
622 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 623 | (const_int 0))) |
9ebbca7d | 624 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
625 | (sign_extend:SI (match_dup 1)))] |
626 | "TARGET_POWERPC" | |
9ebbca7d GK |
627 | "@ |
628 | extsb. %0,%1 | |
629 | #" | |
630 | [(set_attr "type" "compare") | |
631 | (set_attr "length" "4,8")]) | |
632 | ||
633 | (define_split | |
634 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
635 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
636 | (const_int 0))) | |
637 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
638 | (sign_extend:SI (match_dup 1)))] | |
639 | "TARGET_POWERPC && reload_completed" | |
640 | [(set (match_dup 0) | |
641 | (sign_extend:SI (match_dup 1))) | |
642 | (set (match_dup 2) | |
643 | (compare:CC (match_dup 0) | |
644 | (const_int 0)))] | |
645 | "") | |
51b8fc2c RK |
646 | |
647 | (define_expand "extendqisi2_power" | |
648 | [(parallel [(set (match_dup 2) | |
649 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
650 | (const_int 24))) | |
651 | (clobber (scratch:SI))]) | |
652 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
653 | (ashiftrt:SI (match_dup 2) | |
654 | (const_int 24))) | |
655 | (clobber (scratch:SI))])] | |
656 | "TARGET_POWER" | |
657 | " | |
658 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
659 | operands[2] = gen_reg_rtx (SImode); }") | |
660 | ||
661 | (define_expand "extendqisi2_no_power" | |
662 | [(set (match_dup 2) | |
663 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
664 | (const_int 24))) | |
665 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
666 | (ashiftrt:SI (match_dup 2) | |
667 | (const_int 24)))] | |
668 | "! TARGET_POWER && ! TARGET_POWERPC" | |
669 | " | |
670 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
671 | operands[2] = gen_reg_rtx (SImode); }") | |
672 | ||
1fd4e8c1 | 673 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
674 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
675 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
676 | "" |
677 | "") | |
678 | ||
679 | (define_insn "" | |
cd2b37d9 | 680 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
681 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
682 | "" | |
683 | "@ | |
684 | lbz%U1%X1 %0,%1 | |
005a35b9 | 685 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
686 | [(set_attr "type" "load,*")]) |
687 | ||
688 | (define_insn "" | |
9ebbca7d GK |
689 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
690 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 691 | (const_int 0))) |
9ebbca7d | 692 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 693 | "" |
9ebbca7d GK |
694 | "@ |
695 | {andil.|andi.} %2,%1,0xff | |
696 | #" | |
697 | [(set_attr "type" "compare") | |
698 | (set_attr "length" "4,8")]) | |
699 | ||
700 | (define_split | |
701 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
702 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
703 | (const_int 0))) | |
704 | (clobber (match_scratch:HI 2 ""))] | |
705 | "reload_completed" | |
706 | [(set (match_dup 2) | |
707 | (zero_extend:HI (match_dup 1))) | |
708 | (set (match_dup 0) | |
709 | (compare:CC (match_dup 2) | |
710 | (const_int 0)))] | |
711 | "") | |
1fd4e8c1 | 712 | |
51b8fc2c | 713 | (define_insn "" |
9ebbca7d GK |
714 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
715 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 716 | (const_int 0))) |
9ebbca7d | 717 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
718 | (zero_extend:HI (match_dup 1)))] |
719 | "" | |
9ebbca7d GK |
720 | "@ |
721 | {andil.|andi.} %0,%1,0xff | |
722 | #" | |
723 | [(set_attr "type" "compare") | |
724 | (set_attr "length" "4,8")]) | |
725 | ||
726 | (define_split | |
727 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
728 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
729 | (const_int 0))) | |
730 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
731 | (zero_extend:HI (match_dup 1)))] | |
732 | "reload_completed" | |
733 | [(set (match_dup 0) | |
734 | (zero_extend:HI (match_dup 1))) | |
735 | (set (match_dup 2) | |
736 | (compare:CC (match_dup 0) | |
737 | (const_int 0)))] | |
738 | "") | |
815cdc52 MM |
739 | |
740 | (define_expand "extendqihi2" | |
741 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
742 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
743 | "" | |
744 | " | |
745 | { | |
746 | if (TARGET_POWERPC) | |
747 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
748 | else if (TARGET_POWER) | |
749 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
750 | else | |
751 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
752 | DONE; | |
753 | }") | |
754 | ||
755 | (define_insn "extendqihi2_ppc" | |
756 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
757 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
758 | "TARGET_POWERPC" | |
759 | "extsb %0,%1") | |
760 | ||
761 | (define_insn "" | |
9ebbca7d GK |
762 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
763 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 764 | (const_int 0))) |
9ebbca7d | 765 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 766 | "TARGET_POWERPC" |
9ebbca7d GK |
767 | "@ |
768 | extsb. %2,%1 | |
769 | #" | |
770 | [(set_attr "type" "compare") | |
771 | (set_attr "length" "4,8")]) | |
772 | ||
773 | (define_split | |
774 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
775 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
776 | (const_int 0))) | |
777 | (clobber (match_scratch:HI 2 ""))] | |
778 | "TARGET_POWERPC && reload_completed" | |
779 | [(set (match_dup 2) | |
780 | (sign_extend:HI (match_dup 1))) | |
781 | (set (match_dup 0) | |
782 | (compare:CC (match_dup 2) | |
783 | (const_int 0)))] | |
784 | "") | |
815cdc52 MM |
785 | |
786 | (define_insn "" | |
9ebbca7d GK |
787 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
788 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 789 | (const_int 0))) |
9ebbca7d | 790 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
791 | (sign_extend:HI (match_dup 1)))] |
792 | "TARGET_POWERPC" | |
9ebbca7d GK |
793 | "@ |
794 | extsb. %0,%1 | |
795 | #" | |
796 | [(set_attr "type" "compare") | |
797 | (set_attr "length" "4,8")]) | |
798 | ||
799 | (define_split | |
800 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
801 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
802 | (const_int 0))) | |
803 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
804 | (sign_extend:HI (match_dup 1)))] | |
805 | "TARGET_POWERPC && reload_completed" | |
806 | [(set (match_dup 0) | |
807 | (sign_extend:HI (match_dup 1))) | |
808 | (set (match_dup 2) | |
809 | (compare:CC (match_dup 0) | |
810 | (const_int 0)))] | |
811 | "") | |
51b8fc2c RK |
812 | |
813 | (define_expand "extendqihi2_power" | |
814 | [(parallel [(set (match_dup 2) | |
815 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
816 | (const_int 24))) | |
817 | (clobber (scratch:SI))]) | |
818 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
819 | (ashiftrt:SI (match_dup 2) | |
820 | (const_int 24))) | |
821 | (clobber (scratch:SI))])] | |
822 | "TARGET_POWER" | |
823 | " | |
824 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
825 | operands[1] = gen_lowpart (SImode, operands[1]); | |
826 | operands[2] = gen_reg_rtx (SImode); }") | |
827 | ||
828 | (define_expand "extendqihi2_no_power" | |
829 | [(set (match_dup 2) | |
830 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
831 | (const_int 24))) | |
832 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
833 | (ashiftrt:SI (match_dup 2) | |
834 | (const_int 24)))] | |
835 | "! TARGET_POWER && ! TARGET_POWERPC" | |
836 | " | |
837 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
838 | operands[1] = gen_lowpart (SImode, operands[1]); | |
839 | operands[2] = gen_reg_rtx (SImode); }") | |
840 | ||
1fd4e8c1 | 841 | (define_expand "zero_extendhisi2" |
5f243543 | 842 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 843 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
844 | "" |
845 | "") | |
846 | ||
847 | (define_insn "" | |
cd2b37d9 | 848 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
849 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
850 | "" | |
851 | "@ | |
852 | lhz%U1%X1 %0,%1 | |
005a35b9 | 853 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
854 | [(set_attr "type" "load,*")]) |
855 | ||
856 | (define_insn "" | |
9ebbca7d GK |
857 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
858 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 859 | (const_int 0))) |
9ebbca7d | 860 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 861 | "" |
9ebbca7d GK |
862 | "@ |
863 | {andil.|andi.} %2,%1,0xffff | |
864 | #" | |
865 | [(set_attr "type" "compare") | |
866 | (set_attr "length" "4,8")]) | |
867 | ||
868 | (define_split | |
869 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
870 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
871 | (const_int 0))) | |
872 | (clobber (match_scratch:SI 2 ""))] | |
873 | "reload_completed" | |
874 | [(set (match_dup 2) | |
875 | (zero_extend:SI (match_dup 1))) | |
876 | (set (match_dup 0) | |
877 | (compare:CC (match_dup 2) | |
878 | (const_int 0)))] | |
879 | "") | |
1fd4e8c1 RK |
880 | |
881 | (define_insn "" | |
9ebbca7d GK |
882 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
883 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 884 | (const_int 0))) |
9ebbca7d | 885 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
886 | (zero_extend:SI (match_dup 1)))] |
887 | "" | |
9ebbca7d GK |
888 | "@ |
889 | {andil.|andi.} %0,%1,0xffff | |
890 | #" | |
891 | [(set_attr "type" "compare") | |
892 | (set_attr "length" "4,8")]) | |
893 | ||
894 | (define_split | |
895 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
896 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
897 | (const_int 0))) | |
898 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
899 | (zero_extend:SI (match_dup 1)))] | |
900 | "reload_completed" | |
901 | [(set (match_dup 0) | |
902 | (zero_extend:SI (match_dup 1))) | |
903 | (set (match_dup 2) | |
904 | (compare:CC (match_dup 0) | |
905 | (const_int 0)))] | |
906 | "") | |
1fd4e8c1 RK |
907 | |
908 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
909 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
910 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
911 | "" |
912 | "") | |
913 | ||
914 | (define_insn "" | |
cd2b37d9 | 915 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
916 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
917 | "" | |
918 | "@ | |
919 | lha%U1%X1 %0,%1 | |
ca7f5001 | 920 | {exts|extsh} %0,%1" |
b54cf83a | 921 | [(set_attr "type" "load_ext,*")]) |
1fd4e8c1 RK |
922 | |
923 | (define_insn "" | |
9ebbca7d GK |
924 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
925 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 926 | (const_int 0))) |
9ebbca7d | 927 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 928 | "" |
9ebbca7d GK |
929 | "@ |
930 | {exts.|extsh.} %2,%1 | |
931 | #" | |
932 | [(set_attr "type" "compare") | |
933 | (set_attr "length" "4,8")]) | |
934 | ||
935 | (define_split | |
936 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
937 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
938 | (const_int 0))) | |
939 | (clobber (match_scratch:SI 2 ""))] | |
940 | "reload_completed" | |
941 | [(set (match_dup 2) | |
942 | (sign_extend:SI (match_dup 1))) | |
943 | (set (match_dup 0) | |
944 | (compare:CC (match_dup 2) | |
945 | (const_int 0)))] | |
946 | "") | |
1fd4e8c1 RK |
947 | |
948 | (define_insn "" | |
9ebbca7d GK |
949 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
950 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 951 | (const_int 0))) |
9ebbca7d | 952 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
953 | (sign_extend:SI (match_dup 1)))] |
954 | "" | |
9ebbca7d GK |
955 | "@ |
956 | {exts.|extsh.} %0,%1 | |
957 | #" | |
958 | [(set_attr "type" "compare") | |
959 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 960 | \f |
9ebbca7d GK |
961 | (define_split |
962 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
963 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
964 | (const_int 0))) | |
965 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
966 | (sign_extend:SI (match_dup 1)))] | |
967 | "reload_completed" | |
968 | [(set (match_dup 0) | |
969 | (sign_extend:SI (match_dup 1))) | |
970 | (set (match_dup 2) | |
971 | (compare:CC (match_dup 0) | |
972 | (const_int 0)))] | |
973 | "") | |
974 | ||
1fd4e8c1 | 975 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
976 | |
977 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
978 | ;; allowing register zero as source. | |
7cd5235b MM |
979 | (define_expand "addsi3" |
980 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
981 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 982 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
983 | "" |
984 | " | |
985 | { | |
677a9668 DE |
986 | if (GET_CODE (operands[2]) == CONST_INT |
987 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 988 | { |
677a9668 | 989 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
990 | ? operands[0] : gen_reg_rtx (SImode)); |
991 | ||
2bfcf297 | 992 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 993 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 994 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
7cd5235b | 995 | |
9ebbca7d GK |
996 | /* The ordering here is important for the prolog expander. |
997 | When space is allocated from the stack, adding 'low' first may | |
998 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 999 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
1000 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
1001 | DONE; | |
1002 | } | |
1003 | }") | |
1004 | ||
1005 | (define_insn "*addsi3_internal1" | |
1006 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1007 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1008 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1009 | "" |
1010 | "@ | |
deb9225a RK |
1011 | {cax|add} %0,%1,%2 |
1012 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1013 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1014 | {cau|addis} %0,%1,%v2" |
1015 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1016 | |
ee890fe2 SS |
1017 | (define_insn "addsi3_high" |
1018 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1019 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1020 | (high:SI (match_operand 2 "" ""))))] | |
1021 | "TARGET_MACHO && !TARGET_64BIT" | |
1022 | "{cau|addis} %0,%1,ha16(%2)" | |
1023 | [(set_attr "length" "4")]) | |
1024 | ||
7cd5235b | 1025 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1026 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1027 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1028 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1029 | (const_int 0))) |
cb8cc086 | 1030 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
4b8a63d6 | 1031 | "TARGET_32BIT" |
deb9225a RK |
1032 | "@ |
1033 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1034 | {ai.|addic.} %3,%1,%2 |
1035 | # | |
1036 | #" | |
a62bfff2 | 1037 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1038 | (set_attr "length" "4,4,8,8")]) |
1039 | ||
1040 | (define_split | |
1041 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1042 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1043 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1044 | (const_int 0))) | |
1045 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 1046 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1047 | [(set (match_dup 3) |
1048 | (plus:SI (match_dup 1) | |
1049 | (match_dup 2))) | |
1050 | (set (match_dup 0) | |
1051 | (compare:CC (match_dup 3) | |
1052 | (const_int 0)))] | |
1053 | "") | |
7e69e155 | 1054 | |
7cd5235b | 1055 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1056 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1057 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1058 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1059 | (const_int 0))) |
cb8cc086 MM |
1060 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1061 | (plus:SI (match_dup 1) | |
1062 | (match_dup 2)))] | |
4b8a63d6 | 1063 | "TARGET_32BIT" |
deb9225a RK |
1064 | "@ |
1065 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1066 | {ai.|addic.} %0,%1,%2 |
1067 | # | |
1068 | #" | |
a62bfff2 | 1069 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1070 | (set_attr "length" "4,4,8,8")]) |
1071 | ||
1072 | (define_split | |
1073 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1074 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1075 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1076 | (const_int 0))) | |
1077 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1078 | (plus:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 1079 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1080 | [(set (match_dup 0) |
1081 | (plus:SI (match_dup 1) | |
1082 | (match_dup 2))) | |
1083 | (set (match_dup 3) | |
1084 | (compare:CC (match_dup 0) | |
1085 | (const_int 0)))] | |
1086 | "") | |
7e69e155 | 1087 | |
f357808b RK |
1088 | ;; Split an add that we can't do in one insn into two insns, each of which |
1089 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1090 | ;; add should be last in case the result gets used in an address. | |
1091 | ||
1092 | (define_split | |
cd2b37d9 RK |
1093 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1094 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1095 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1096 | "" |
f357808b RK |
1097 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1098 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1099 | " | |
1fd4e8c1 | 1100 | { |
2bfcf297 | 1101 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1102 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1103 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
1fd4e8c1 | 1104 | |
2bfcf297 | 1105 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1106 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1107 | }") |
1108 | ||
8de2a197 | 1109 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1110 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1111 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1112 | "" |
ca7f5001 RK |
1113 | "nor %0,%1,%1") |
1114 | ||
1115 | (define_insn "" | |
52d3af72 DE |
1116 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1117 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1118 | (const_int 0))) |
52d3af72 | 1119 | (clobber (match_scratch:SI 2 "=r,r"))] |
4b8a63d6 | 1120 | "TARGET_32BIT" |
52d3af72 DE |
1121 | "@ |
1122 | nor. %2,%1,%1 | |
1123 | #" | |
1124 | [(set_attr "type" "compare") | |
1125 | (set_attr "length" "4,8")]) | |
1126 | ||
1127 | (define_split | |
1128 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1129 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1130 | (const_int 0))) | |
1131 | (clobber (match_scratch:SI 2 ""))] | |
4b8a63d6 | 1132 | "TARGET_32BIT && reload_completed" |
52d3af72 DE |
1133 | [(set (match_dup 2) |
1134 | (not:SI (match_dup 1))) | |
1135 | (set (match_dup 0) | |
1136 | (compare:CC (match_dup 2) | |
1137 | (const_int 0)))] | |
1138 | "") | |
ca7f5001 RK |
1139 | |
1140 | (define_insn "" | |
52d3af72 DE |
1141 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1142 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1143 | (const_int 0))) |
52d3af72 | 1144 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1145 | (not:SI (match_dup 1)))] |
4b8a63d6 | 1146 | "TARGET_32BIT" |
52d3af72 DE |
1147 | "@ |
1148 | nor. %0,%1,%1 | |
1149 | #" | |
1150 | [(set_attr "type" "compare") | |
1151 | (set_attr "length" "4,8")]) | |
1152 | ||
1153 | (define_split | |
1154 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1155 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1156 | (const_int 0))) | |
1cb18e3c | 1157 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1158 | (not:SI (match_dup 1)))] |
4b8a63d6 | 1159 | "TARGET_32BIT && reload_completed" |
52d3af72 DE |
1160 | [(set (match_dup 0) |
1161 | (not:SI (match_dup 1))) | |
1162 | (set (match_dup 2) | |
1163 | (compare:CC (match_dup 0) | |
1164 | (const_int 0)))] | |
1165 | "") | |
1fd4e8c1 RK |
1166 | |
1167 | (define_insn "" | |
3d91674b RK |
1168 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1169 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1170 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1171 | "! TARGET_POWERPC" |
ca7f5001 | 1172 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1173 | |
deb9225a RK |
1174 | (define_insn "" |
1175 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1176 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1177 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1178 | "TARGET_POWERPC" | |
1179 | "@ | |
1180 | subf %0,%2,%1 | |
1181 | subfic %0,%2,%1") | |
1182 | ||
1fd4e8c1 | 1183 | (define_insn "" |
cb8cc086 MM |
1184 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1185 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1186 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1187 | (const_int 0))) |
cb8cc086 | 1188 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1189 | "! TARGET_POWERPC" |
cb8cc086 MM |
1190 | "@ |
1191 | {sf.|subfc.} %3,%2,%1 | |
1192 | #" | |
1193 | [(set_attr "type" "compare") | |
1194 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1195 | |
deb9225a | 1196 | (define_insn "" |
cb8cc086 MM |
1197 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1198 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1199 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1200 | (const_int 0))) |
cb8cc086 | 1201 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 1202 | "TARGET_POWERPC && TARGET_32BIT" |
cb8cc086 MM |
1203 | "@ |
1204 | subf. %3,%2,%1 | |
1205 | #" | |
a62bfff2 | 1206 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1207 | (set_attr "length" "4,8")]) |
1208 | ||
1209 | (define_split | |
1210 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1211 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1212 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1213 | (const_int 0))) | |
1214 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 1215 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1216 | [(set (match_dup 3) |
1217 | (minus:SI (match_dup 1) | |
1218 | (match_dup 2))) | |
1219 | (set (match_dup 0) | |
1220 | (compare:CC (match_dup 3) | |
1221 | (const_int 0)))] | |
1222 | "") | |
deb9225a | 1223 | |
1fd4e8c1 | 1224 | (define_insn "" |
cb8cc086 MM |
1225 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1226 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1227 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1228 | (const_int 0))) |
cb8cc086 | 1229 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1230 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1231 | "! TARGET_POWERPC" |
cb8cc086 MM |
1232 | "@ |
1233 | {sf.|subfc.} %0,%2,%1 | |
1234 | #" | |
1235 | [(set_attr "type" "compare") | |
1236 | (set_attr "length" "4,8")]) | |
815cdc52 | 1237 | |
29ae5b89 | 1238 | (define_insn "" |
cb8cc086 MM |
1239 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1240 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1241 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1242 | (const_int 0))) |
cb8cc086 MM |
1243 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1244 | (minus:SI (match_dup 1) | |
1245 | (match_dup 2)))] | |
4b8a63d6 | 1246 | "TARGET_POWERPC && TARGET_32BIT" |
90612787 DE |
1247 | "@ |
1248 | subf. %0,%2,%1 | |
1249 | #" | |
a62bfff2 | 1250 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1251 | (set_attr "length" "4,8")]) |
1252 | ||
1253 | (define_split | |
1254 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1255 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1256 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1257 | (const_int 0))) | |
1258 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1259 | (minus:SI (match_dup 1) | |
1260 | (match_dup 2)))] | |
4b8a63d6 | 1261 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1262 | [(set (match_dup 0) |
1263 | (minus:SI (match_dup 1) | |
1264 | (match_dup 2))) | |
1265 | (set (match_dup 3) | |
1266 | (compare:CC (match_dup 0) | |
1267 | (const_int 0)))] | |
1268 | "") | |
deb9225a | 1269 | |
1fd4e8c1 | 1270 | (define_expand "subsi3" |
cd2b37d9 | 1271 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1272 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1273 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1274 | "" |
a0044fb1 RK |
1275 | " |
1276 | { | |
1277 | if (GET_CODE (operands[2]) == CONST_INT) | |
1278 | { | |
1279 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1280 | negate_rtx (SImode, operands[2]))); | |
1281 | DONE; | |
1282 | } | |
1283 | }") | |
1fd4e8c1 RK |
1284 | |
1285 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1286 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1287 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1288 | ;; combine. | |
1fd4e8c1 RK |
1289 | |
1290 | (define_expand "sminsi3" | |
1291 | [(set (match_dup 3) | |
cd2b37d9 | 1292 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1293 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1294 | (const_int 0) | |
1295 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1296 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1297 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1298 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1299 | " |
a3170dc6 AH |
1300 | { |
1301 | if (TARGET_ISEL) | |
1302 | { | |
1303 | operands[2] = force_reg (SImode, operands[2]); | |
1304 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
1305 | DONE; | |
1306 | } | |
1307 | ||
1308 | operands[3] = gen_reg_rtx (SImode); | |
1309 | }") | |
1fd4e8c1 | 1310 | |
95ac8e67 RK |
1311 | (define_split |
1312 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1313 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1314 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1315 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1316 | "TARGET_POWER" |
95ac8e67 RK |
1317 | [(set (match_dup 3) |
1318 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1319 | (const_int 0) | |
1320 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1321 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1322 | "") | |
1323 | ||
1fd4e8c1 RK |
1324 | (define_expand "smaxsi3" |
1325 | [(set (match_dup 3) | |
cd2b37d9 | 1326 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1327 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1328 | (const_int 0) | |
1329 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1330 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1331 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1332 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1333 | " |
a3170dc6 AH |
1334 | { |
1335 | if (TARGET_ISEL) | |
1336 | { | |
1337 | operands[2] = force_reg (SImode, operands[2]); | |
1338 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
1339 | DONE; | |
1340 | } | |
1341 | operands[3] = gen_reg_rtx (SImode); | |
1342 | }") | |
1fd4e8c1 | 1343 | |
95ac8e67 RK |
1344 | (define_split |
1345 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1346 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1347 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1348 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1349 | "TARGET_POWER" |
95ac8e67 RK |
1350 | [(set (match_dup 3) |
1351 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1352 | (const_int 0) | |
1353 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1354 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1355 | "") | |
1356 | ||
1fd4e8c1 | 1357 | (define_expand "uminsi3" |
cd2b37d9 | 1358 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1359 | (match_dup 5))) |
cd2b37d9 | 1360 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1361 | (match_dup 5))) |
1fd4e8c1 RK |
1362 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1363 | (const_int 0) | |
1364 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1365 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1366 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1367 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1368 | " |
bb68ff55 | 1369 | { |
a3170dc6 AH |
1370 | if (TARGET_ISEL) |
1371 | { | |
1372 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
1373 | DONE; | |
1374 | } | |
bb68ff55 MM |
1375 | operands[3] = gen_reg_rtx (SImode); |
1376 | operands[4] = gen_reg_rtx (SImode); | |
1377 | operands[5] = GEN_INT (-2147483647 - 1); | |
1378 | }") | |
1fd4e8c1 RK |
1379 | |
1380 | (define_expand "umaxsi3" | |
cd2b37d9 | 1381 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1382 | (match_dup 5))) |
cd2b37d9 | 1383 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1384 | (match_dup 5))) |
1fd4e8c1 RK |
1385 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1386 | (const_int 0) | |
1387 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1388 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1389 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1390 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1391 | " |
bb68ff55 | 1392 | { |
a3170dc6 AH |
1393 | if (TARGET_ISEL) |
1394 | { | |
1395 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
1396 | DONE; | |
1397 | } | |
bb68ff55 MM |
1398 | operands[3] = gen_reg_rtx (SImode); |
1399 | operands[4] = gen_reg_rtx (SImode); | |
1400 | operands[5] = GEN_INT (-2147483647 - 1); | |
1401 | }") | |
1fd4e8c1 RK |
1402 | |
1403 | (define_insn "" | |
cd2b37d9 RK |
1404 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1405 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1406 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1407 | (const_int 0) |
1408 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1409 | "TARGET_POWER" |
1fd4e8c1 RK |
1410 | "doz%I2 %0,%1,%2") |
1411 | ||
1412 | (define_insn "" | |
9ebbca7d | 1413 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1414 | (compare:CC |
9ebbca7d GK |
1415 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1416 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1417 | (const_int 0) |
1418 | (minus:SI (match_dup 2) (match_dup 1))) | |
1419 | (const_int 0))) | |
9ebbca7d | 1420 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1421 | "TARGET_POWER" |
9ebbca7d GK |
1422 | "@ |
1423 | doz%I2. %3,%1,%2 | |
1424 | #" | |
1425 | [(set_attr "type" "delayed_compare") | |
1426 | (set_attr "length" "4,8")]) | |
1427 | ||
1428 | (define_split | |
1429 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1430 | (compare:CC | |
1431 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1432 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1433 | (const_int 0) | |
1434 | (minus:SI (match_dup 2) (match_dup 1))) | |
1435 | (const_int 0))) | |
1436 | (clobber (match_scratch:SI 3 ""))] | |
1437 | "TARGET_POWER && reload_completed" | |
1438 | [(set (match_dup 3) | |
1439 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1440 | (const_int 0) | |
1441 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1442 | (set (match_dup 0) | |
1443 | (compare:CC (match_dup 3) | |
1444 | (const_int 0)))] | |
1445 | "") | |
1fd4e8c1 RK |
1446 | |
1447 | (define_insn "" | |
9ebbca7d | 1448 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1449 | (compare:CC |
9ebbca7d GK |
1450 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1451 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1452 | (const_int 0) |
1453 | (minus:SI (match_dup 2) (match_dup 1))) | |
1454 | (const_int 0))) | |
9ebbca7d | 1455 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1456 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1457 | (const_int 0) | |
1458 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1459 | "TARGET_POWER" |
9ebbca7d GK |
1460 | "@ |
1461 | doz%I2. %0,%1,%2 | |
1462 | #" | |
1463 | [(set_attr "type" "delayed_compare") | |
1464 | (set_attr "length" "4,8")]) | |
1465 | ||
1466 | (define_split | |
1467 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1468 | (compare:CC | |
1469 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1470 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1471 | (const_int 0) | |
1472 | (minus:SI (match_dup 2) (match_dup 1))) | |
1473 | (const_int 0))) | |
1474 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1475 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1476 | (const_int 0) | |
1477 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1478 | "TARGET_POWER && reload_completed" | |
1479 | [(set (match_dup 0) | |
1480 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1481 | (const_int 0) | |
1482 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1483 | (set (match_dup 3) | |
1484 | (compare:CC (match_dup 0) | |
1485 | (const_int 0)))] | |
1486 | "") | |
1fd4e8c1 RK |
1487 | |
1488 | ;; We don't need abs with condition code because such comparisons should | |
1489 | ;; never be done. | |
ea9be077 MM |
1490 | (define_expand "abssi2" |
1491 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1492 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1493 | "" | |
1494 | " | |
1495 | { | |
a3170dc6 AH |
1496 | if (TARGET_ISEL) |
1497 | { | |
1498 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
1499 | DONE; | |
1500 | } | |
1501 | else if (! TARGET_POWER) | |
ea9be077 MM |
1502 | { |
1503 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1504 | DONE; | |
1505 | } | |
1506 | }") | |
1507 | ||
ea112fc4 | 1508 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
1509 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1510 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1511 | "TARGET_POWER" |
1fd4e8c1 RK |
1512 | "abs %0,%1") |
1513 | ||
a3170dc6 AH |
1514 | (define_insn_and_split "abssi2_isel" |
1515 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1516 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8c48b6f5 | 1517 | (clobber (match_scratch:SI 2 "=&b")) |
a3170dc6 AH |
1518 | (clobber (match_scratch:CC 3 "=y"))] |
1519 | "TARGET_ISEL" | |
1520 | "#" | |
1521 | "&& reload_completed" | |
1522 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
1523 | (set (match_dup 3) | |
1524 | (compare:CC (match_dup 1) | |
1525 | (const_int 0))) | |
1526 | (set (match_dup 0) | |
1527 | (if_then_else:SI (ge (match_dup 3) | |
1528 | (const_int 0)) | |
1529 | (match_dup 1) | |
1530 | (match_dup 2)))] | |
1531 | "") | |
1532 | ||
ea112fc4 | 1533 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 1534 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1535 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 1536 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 1537 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
1538 | "#" |
1539 | "&& reload_completed" | |
ea9be077 MM |
1540 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1541 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1542 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1543 | "") |
1544 | ||
463b558b | 1545 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1546 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1547 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1548 | "TARGET_POWER" |
1fd4e8c1 RK |
1549 | "nabs %0,%1") |
1550 | ||
ea112fc4 | 1551 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 1552 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1553 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 1554 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 1555 | "! TARGET_POWER" |
ea112fc4 DE |
1556 | "#" |
1557 | "&& reload_completed" | |
ea9be077 MM |
1558 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1559 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1560 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1561 | "") |
1562 | ||
1fd4e8c1 | 1563 | (define_insn "negsi2" |
cd2b37d9 RK |
1564 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1565 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1566 | "" |
1567 | "neg %0,%1") | |
1568 | ||
1569 | (define_insn "" | |
9ebbca7d GK |
1570 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1571 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1572 | (const_int 0))) |
9ebbca7d | 1573 | (clobber (match_scratch:SI 2 "=r,r"))] |
4b8a63d6 | 1574 | "TARGET_32BIT" |
9ebbca7d GK |
1575 | "@ |
1576 | neg. %2,%1 | |
1577 | #" | |
a62bfff2 | 1578 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1579 | (set_attr "length" "4,8")]) |
1580 | ||
1581 | (define_split | |
1582 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1583 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1584 | (const_int 0))) | |
1585 | (clobber (match_scratch:SI 2 ""))] | |
4b8a63d6 | 1586 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
1587 | [(set (match_dup 2) |
1588 | (neg:SI (match_dup 1))) | |
1589 | (set (match_dup 0) | |
1590 | (compare:CC (match_dup 2) | |
1591 | (const_int 0)))] | |
1592 | "") | |
1fd4e8c1 RK |
1593 | |
1594 | (define_insn "" | |
9ebbca7d GK |
1595 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1596 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1597 | (const_int 0))) |
9ebbca7d | 1598 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1599 | (neg:SI (match_dup 1)))] |
4b8a63d6 | 1600 | "TARGET_32BIT" |
9ebbca7d GK |
1601 | "@ |
1602 | neg. %0,%1 | |
1603 | #" | |
a62bfff2 | 1604 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1605 | (set_attr "length" "4,8")]) |
1606 | ||
1607 | (define_split | |
1608 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1609 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1610 | (const_int 0))) | |
1611 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1612 | (neg:SI (match_dup 1)))] | |
4b8a63d6 | 1613 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
1614 | [(set (match_dup 0) |
1615 | (neg:SI (match_dup 1))) | |
1616 | (set (match_dup 2) | |
1617 | (compare:CC (match_dup 0) | |
1618 | (const_int 0)))] | |
1619 | "") | |
1fd4e8c1 | 1620 | |
1b1edcfa DE |
1621 | (define_insn "clzsi2" |
1622 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1623 | (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1624 | "" | |
1625 | "{cntlz|cntlzw} %0,%1") | |
1626 | ||
1627 | (define_expand "ctzsi2" | |
4977bab6 | 1628 | [(set (match_dup 2) |
1b1edcfa | 1629 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 1630 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) |
1b1edcfa DE |
1631 | (match_dup 2))) |
1632 | (clobber (scratch:CC))]) | |
d865b122 | 1633 | (set (match_dup 4) (clz:SI (match_dup 3))) |
4977bab6 | 1634 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 1635 | (minus:SI (const_int 31) (match_dup 4)))] |
1fd4e8c1 | 1636 | "" |
4977bab6 ZW |
1637 | { |
1638 | operands[2] = gen_reg_rtx (SImode); | |
1639 | operands[3] = gen_reg_rtx (SImode); | |
1640 | operands[4] = gen_reg_rtx (SImode); | |
1641 | }) | |
6ae08853 | 1642 | |
1b1edcfa DE |
1643 | (define_expand "ffssi2" |
1644 | [(set (match_dup 2) | |
1645 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
1646 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) | |
1647 | (match_dup 2))) | |
1648 | (clobber (scratch:CC))]) | |
1649 | (set (match_dup 4) (clz:SI (match_dup 3))) | |
1650 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1651 | (minus:SI (const_int 32) (match_dup 4)))] | |
4977bab6 | 1652 | "" |
1b1edcfa DE |
1653 | { |
1654 | operands[2] = gen_reg_rtx (SImode); | |
1655 | operands[3] = gen_reg_rtx (SImode); | |
1656 | operands[4] = gen_reg_rtx (SImode); | |
1657 | }) | |
6ae08853 | 1658 | |
ca7f5001 RK |
1659 | (define_expand "mulsi3" |
1660 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1661 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1662 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1663 | "" | |
1664 | " | |
1665 | { | |
1666 | if (TARGET_POWER) | |
68b40e7e | 1667 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1668 | else |
68b40e7e | 1669 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1670 | DONE; |
1671 | }") | |
1672 | ||
68b40e7e | 1673 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1674 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1675 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1676 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1677 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1678 | "TARGET_POWER" |
1679 | "@ | |
1680 | {muls|mullw} %0,%1,%2 | |
1681 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1682 | [(set (attr "type") |
c859cda6 DJ |
1683 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1684 | (const_string "imul3") | |
6ae08853 | 1685 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1686 | (const_string "imul2")] |
1687 | (const_string "imul")))]) | |
ca7f5001 | 1688 | |
68b40e7e | 1689 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1690 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1691 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1692 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1693 | "! TARGET_POWER" |
1fd4e8c1 | 1694 | "@ |
d904e9ed RK |
1695 | {muls|mullw} %0,%1,%2 |
1696 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1697 | [(set (attr "type") |
c859cda6 DJ |
1698 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1699 | (const_string "imul3") | |
6ae08853 | 1700 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1701 | (const_string "imul2")] |
1702 | (const_string "imul")))]) | |
1fd4e8c1 | 1703 | |
9259f3b0 | 1704 | (define_insn "*mulsi3_mq_internal1" |
9ebbca7d GK |
1705 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1706 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1707 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1708 | (const_int 0))) |
9ebbca7d GK |
1709 | (clobber (match_scratch:SI 3 "=r,r")) |
1710 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 1711 | "TARGET_POWER" |
9ebbca7d GK |
1712 | "@ |
1713 | {muls.|mullw.} %3,%1,%2 | |
1714 | #" | |
9259f3b0 | 1715 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1716 | (set_attr "length" "4,8")]) |
1717 | ||
1718 | (define_split | |
1719 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1720 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1721 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1722 | (const_int 0))) | |
1723 | (clobber (match_scratch:SI 3 "")) | |
1724 | (clobber (match_scratch:SI 4 ""))] | |
1725 | "TARGET_POWER && reload_completed" | |
1726 | [(parallel [(set (match_dup 3) | |
1727 | (mult:SI (match_dup 1) (match_dup 2))) | |
1728 | (clobber (match_dup 4))]) | |
1729 | (set (match_dup 0) | |
1730 | (compare:CC (match_dup 3) | |
1731 | (const_int 0)))] | |
1732 | "") | |
ca7f5001 | 1733 | |
9259f3b0 | 1734 | (define_insn "*mulsi3_no_mq_internal1" |
9ebbca7d GK |
1735 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1736 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1737 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1738 | (const_int 0))) |
9ebbca7d | 1739 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 1740 | "! TARGET_POWER" |
9ebbca7d GK |
1741 | "@ |
1742 | {muls.|mullw.} %3,%1,%2 | |
1743 | #" | |
9259f3b0 | 1744 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1745 | (set_attr "length" "4,8")]) |
1746 | ||
1747 | (define_split | |
1748 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1749 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1750 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1751 | (const_int 0))) | |
1752 | (clobber (match_scratch:SI 3 ""))] | |
1753 | "! TARGET_POWER && reload_completed" | |
1754 | [(set (match_dup 3) | |
1755 | (mult:SI (match_dup 1) (match_dup 2))) | |
1756 | (set (match_dup 0) | |
1757 | (compare:CC (match_dup 3) | |
1758 | (const_int 0)))] | |
1759 | "") | |
1fd4e8c1 | 1760 | |
9259f3b0 | 1761 | (define_insn "*mulsi3_mq_internal2" |
9ebbca7d GK |
1762 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1763 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1764 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1765 | (const_int 0))) |
9ebbca7d | 1766 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 1767 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 1768 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 1769 | "TARGET_POWER" |
9ebbca7d GK |
1770 | "@ |
1771 | {muls.|mullw.} %0,%1,%2 | |
1772 | #" | |
9259f3b0 | 1773 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1774 | (set_attr "length" "4,8")]) |
1775 | ||
1776 | (define_split | |
1777 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1778 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1779 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1780 | (const_int 0))) | |
1781 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1782 | (mult:SI (match_dup 1) (match_dup 2))) | |
1783 | (clobber (match_scratch:SI 4 ""))] | |
1784 | "TARGET_POWER && reload_completed" | |
1785 | [(parallel [(set (match_dup 0) | |
1786 | (mult:SI (match_dup 1) (match_dup 2))) | |
1787 | (clobber (match_dup 4))]) | |
1788 | (set (match_dup 3) | |
1789 | (compare:CC (match_dup 0) | |
1790 | (const_int 0)))] | |
1791 | "") | |
ca7f5001 | 1792 | |
9259f3b0 | 1793 | (define_insn "*mulsi3_no_mq_internal2" |
9ebbca7d GK |
1794 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1795 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1796 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1797 | (const_int 0))) |
9ebbca7d | 1798 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 1799 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1800 | "! TARGET_POWER" |
9ebbca7d GK |
1801 | "@ |
1802 | {muls.|mullw.} %0,%1,%2 | |
1803 | #" | |
9259f3b0 | 1804 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1805 | (set_attr "length" "4,8")]) |
1806 | ||
1807 | (define_split | |
1808 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1809 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1810 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1811 | (const_int 0))) | |
1812 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1813 | (mult:SI (match_dup 1) (match_dup 2)))] | |
1814 | "! TARGET_POWER && reload_completed" | |
1815 | [(set (match_dup 0) | |
1816 | (mult:SI (match_dup 1) (match_dup 2))) | |
1817 | (set (match_dup 3) | |
1818 | (compare:CC (match_dup 0) | |
1819 | (const_int 0)))] | |
1820 | "") | |
1fd4e8c1 RK |
1821 | |
1822 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1823 | ;; 0 and remainder to operand 3. | |
1824 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1825 | ||
8ffd9c51 RK |
1826 | (define_expand "divmodsi4" |
1827 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1828 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1829 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 1830 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
1831 | (mod:SI (match_dup 1) (match_dup 2)))])] |
1832 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1833 | " | |
1834 | { | |
1835 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1836 | { | |
39403d82 DE |
1837 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1838 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1839 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1840 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1841 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1842 | DONE; |
1843 | } | |
1844 | }") | |
deb9225a | 1845 | |
bb157ff4 | 1846 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
1847 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1848 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1849 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 1850 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 1851 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1852 | "TARGET_POWER" |
cfb557c4 RK |
1853 | "divs %0,%1,%2" |
1854 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1855 | |
8ffd9c51 RK |
1856 | (define_expand "udivsi3" |
1857 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1858 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1859 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1860 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1861 | " | |
1862 | { | |
1863 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1864 | { | |
39403d82 DE |
1865 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1866 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1867 | emit_insn (gen_quous_call ()); |
39403d82 | 1868 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1869 | DONE; |
1870 | } | |
f192bf8b DE |
1871 | else if (TARGET_POWER) |
1872 | { | |
1873 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1874 | DONE; | |
1875 | } | |
8ffd9c51 | 1876 | }") |
deb9225a | 1877 | |
f192bf8b DE |
1878 | (define_insn "udivsi3_mq" |
1879 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1880 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1881 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1882 | (clobber (match_scratch:SI 3 "=q"))] | |
1883 | "TARGET_POWERPC && TARGET_POWER" | |
1884 | "divwu %0,%1,%2" | |
1885 | [(set_attr "type" "idiv")]) | |
1886 | ||
1887 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1888 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1889 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1890 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1891 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1892 | "divwu %0,%1,%2" |
ca7f5001 RK |
1893 | [(set_attr "type" "idiv")]) |
1894 | ||
1fd4e8c1 | 1895 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1896 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1897 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1898 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1899 | (define_expand "divsi3" |
cd2b37d9 RK |
1900 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1901 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1902 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1903 | "" | |
1904 | " | |
1905 | { | |
ca7f5001 | 1906 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 1907 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
1908 | && exact_log2 (INTVAL (operands[2])) >= 0) |
1909 | ; | |
b6c9286a | 1910 | else if (TARGET_POWERPC) |
f192bf8b DE |
1911 | { |
1912 | operands[2] = force_reg (SImode, operands[2]); | |
1913 | if (TARGET_POWER) | |
1914 | { | |
1915 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1916 | DONE; | |
1917 | } | |
1918 | } | |
b6c9286a | 1919 | else if (TARGET_POWER) |
1fd4e8c1 | 1920 | FAIL; |
405c5495 | 1921 | else |
8ffd9c51 | 1922 | { |
39403d82 DE |
1923 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1924 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1925 | emit_insn (gen_quoss_call ()); |
39403d82 | 1926 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1927 | DONE; |
1928 | } | |
1fd4e8c1 RK |
1929 | }") |
1930 | ||
f192bf8b DE |
1931 | (define_insn "divsi3_mq" |
1932 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1933 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1934 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1935 | (clobber (match_scratch:SI 3 "=q"))] | |
1936 | "TARGET_POWERPC && TARGET_POWER" | |
1937 | "divw %0,%1,%2" | |
1938 | [(set_attr "type" "idiv")]) | |
1939 | ||
1940 | (define_insn "*divsi3_no_mq" | |
1941 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1942 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1943 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1944 | "TARGET_POWERPC && ! TARGET_POWER" | |
1945 | "divw %0,%1,%2" | |
1946 | [(set_attr "type" "idiv")]) | |
1947 | ||
1fd4e8c1 | 1948 | (define_expand "modsi3" |
85644414 RK |
1949 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1950 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1951 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1952 | "" |
1fd4e8c1 RK |
1953 | " |
1954 | { | |
481c7efa | 1955 | int i; |
39b52ba2 RK |
1956 | rtx temp1; |
1957 | rtx temp2; | |
1958 | ||
2bfcf297 | 1959 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 1960 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 1961 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
1962 | FAIL; |
1963 | ||
1964 | temp1 = gen_reg_rtx (SImode); | |
1965 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1966 | |
85644414 | 1967 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1968 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1969 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1970 | DONE; | |
1fd4e8c1 RK |
1971 | }") |
1972 | ||
1973 | (define_insn "" | |
cd2b37d9 RK |
1974 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1975 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
1976 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
1977 | "" | |
ca7f5001 | 1978 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 1979 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
1980 | |
1981 | (define_insn "" | |
9ebbca7d GK |
1982 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1983 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 1984 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 1985 | (const_int 0))) |
9ebbca7d | 1986 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 1987 | "" |
9ebbca7d GK |
1988 | "@ |
1989 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
1990 | #" | |
b19003d8 | 1991 | [(set_attr "type" "compare") |
9ebbca7d GK |
1992 | (set_attr "length" "8,12")]) |
1993 | ||
1994 | (define_split | |
1995 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1996 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 1997 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
1998 | (const_int 0))) |
1999 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 2000 | "reload_completed" |
9ebbca7d GK |
2001 | [(set (match_dup 3) |
2002 | (div:SI (match_dup 1) (match_dup 2))) | |
2003 | (set (match_dup 0) | |
2004 | (compare:CC (match_dup 3) | |
2005 | (const_int 0)))] | |
2006 | "") | |
1fd4e8c1 RK |
2007 | |
2008 | (define_insn "" | |
9ebbca7d GK |
2009 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2010 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2011 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2012 | (const_int 0))) |
9ebbca7d | 2013 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2014 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2015 | "" |
9ebbca7d GK |
2016 | "@ |
2017 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2018 | #" | |
b19003d8 | 2019 | [(set_attr "type" "compare") |
9ebbca7d GK |
2020 | (set_attr "length" "8,12")]) |
2021 | ||
2022 | (define_split | |
2023 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2024 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2025 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2026 | (const_int 0))) |
2027 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2028 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2029 | "reload_completed" |
9ebbca7d GK |
2030 | [(set (match_dup 0) |
2031 | (div:SI (match_dup 1) (match_dup 2))) | |
2032 | (set (match_dup 3) | |
2033 | (compare:CC (match_dup 0) | |
2034 | (const_int 0)))] | |
2035 | "") | |
1fd4e8c1 RK |
2036 | |
2037 | (define_insn "" | |
cd2b37d9 | 2038 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2039 | (udiv:SI |
996a5f59 | 2040 | (plus:DI (ashift:DI |
cd2b37d9 | 2041 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2042 | (const_int 32)) |
23a900dc | 2043 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2044 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2045 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2046 | (umod:SI |
996a5f59 | 2047 | (plus:DI (ashift:DI |
1fd4e8c1 | 2048 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2049 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2050 | (match_dup 3)))] |
ca7f5001 | 2051 | "TARGET_POWER" |
cfb557c4 RK |
2052 | "div %0,%1,%3" |
2053 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2054 | |
2055 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2056 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2057 | ;; have to worry about the branches. So make a few subroutines here. | |
2058 | ;; | |
2059 | ;; First comes the normal case. | |
2060 | (define_expand "udivmodsi4_normal" | |
2061 | [(set (match_dup 4) (const_int 0)) | |
2062 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2063 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2064 | (const_int 32)) |
2065 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2066 | (match_operand:SI 2 "" ""))) | |
2067 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2068 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2069 | (const_int 32)) |
2070 | (zero_extend:DI (match_dup 1))) | |
2071 | (match_dup 2)))])] | |
ca7f5001 | 2072 | "TARGET_POWER" |
1fd4e8c1 RK |
2073 | " |
2074 | { operands[4] = gen_reg_rtx (SImode); }") | |
2075 | ||
2076 | ;; This handles the branches. | |
2077 | (define_expand "udivmodsi4_tests" | |
2078 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2079 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2080 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2081 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2082 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2083 | (set (match_dup 0) (const_int 1)) | |
2084 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2085 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2086 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2087 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2088 | "TARGET_POWER" |
1fd4e8c1 RK |
2089 | " |
2090 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2091 | operands[6] = gen_reg_rtx (CCmode); | |
2092 | }") | |
2093 | ||
2094 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2095 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2096 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2097 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2098 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2099 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2100 | "" |
1fd4e8c1 RK |
2101 | " |
2102 | { | |
2103 | rtx label = 0; | |
2104 | ||
8ffd9c51 | 2105 | if (! TARGET_POWER) |
c4d38ccb MM |
2106 | { |
2107 | if (! TARGET_POWERPC) | |
2108 | { | |
39403d82 DE |
2109 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2110 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2111 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2112 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2113 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2114 | DONE; |
2115 | } | |
2116 | else | |
2117 | FAIL; | |
2118 | } | |
0081a354 | 2119 | |
1fd4e8c1 RK |
2120 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2121 | { | |
2122 | operands[2] = force_reg (SImode, operands[2]); | |
2123 | label = gen_label_rtx (); | |
2124 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2125 | operands[3], label)); | |
2126 | } | |
2127 | else | |
2128 | operands[2] = force_reg (SImode, operands[2]); | |
2129 | ||
2130 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2131 | operands[3])); | |
2132 | if (label) | |
2133 | emit_label (label); | |
2134 | ||
2135 | DONE; | |
2136 | }") | |
0081a354 | 2137 | |
fada905b MM |
2138 | ;; AIX architecture-independent common-mode multiply (DImode), |
2139 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2140 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2141 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2142 | ;; assumed unused if generating common-mode, so ignore. | |
2143 | (define_insn "mulh_call" | |
2144 | [(set (reg:SI 3) | |
2145 | (truncate:SI | |
2146 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2147 | (sign_extend:DI (reg:SI 4))) | |
2148 | (const_int 32)))) | |
cf27b467 | 2149 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2150 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2151 | "bla __mulh" |
2152 | [(set_attr "type" "imul")]) | |
fada905b MM |
2153 | |
2154 | (define_insn "mull_call" | |
2155 | [(set (reg:DI 3) | |
2156 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2157 | (sign_extend:DI (reg:SI 4)))) | |
2158 | (clobber (match_scratch:SI 0 "=l")) | |
2159 | (clobber (reg:SI 0))] | |
2160 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2161 | "bla __mull" |
2162 | [(set_attr "type" "imul")]) | |
fada905b MM |
2163 | |
2164 | (define_insn "divss_call" | |
2165 | [(set (reg:SI 3) | |
2166 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2167 | (set (reg:SI 4) | |
2168 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2169 | (clobber (match_scratch:SI 0 "=l")) | |
2170 | (clobber (reg:SI 0))] | |
2171 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2172 | "bla __divss" |
2173 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2174 | |
2175 | (define_insn "divus_call" | |
8ffd9c51 RK |
2176 | [(set (reg:SI 3) |
2177 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2178 | (set (reg:SI 4) | |
2179 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2180 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2181 | (clobber (reg:SI 0)) |
2182 | (clobber (match_scratch:CC 1 "=x")) | |
2183 | (clobber (reg:CC 69))] | |
2184 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2185 | "bla __divus" |
2186 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2187 | |
2188 | (define_insn "quoss_call" | |
2189 | [(set (reg:SI 3) | |
2190 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2191 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2192 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2193 | "bla __quoss" |
2194 | [(set_attr "type" "idiv")]) | |
0081a354 | 2195 | |
fada905b MM |
2196 | (define_insn "quous_call" |
2197 | [(set (reg:SI 3) | |
2198 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2199 | (clobber (match_scratch:SI 0 "=l")) | |
2200 | (clobber (reg:SI 0)) | |
2201 | (clobber (match_scratch:CC 1 "=x")) | |
2202 | (clobber (reg:CC 69))] | |
2203 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2204 | "bla __quous" |
2205 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2206 | \f |
bb21487f | 2207 | ;; Logical instructions |
dfbdccdb GK |
2208 | ;; The logical instructions are mostly combined by using match_operator, |
2209 | ;; but the plain AND insns are somewhat different because there is no | |
2210 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2211 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2212 | ||
29ae5b89 JL |
2213 | (define_insn "andsi3" |
2214 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2215 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2216 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2217 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2218 | "" |
2219 | "@ | |
2220 | and %0,%1,%2 | |
ca7f5001 RK |
2221 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2222 | {andil.|andi.} %0,%1,%b2 | |
520308bc DE |
2223 | {andiu.|andis.} %0,%1,%u2" |
2224 | [(set_attr "type" "*,*,compare,compare")]) | |
52d3af72 DE |
2225 | |
2226 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2227 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2228 | ;; machines causes an execution serialization |
1fd4e8c1 | 2229 | |
7cd5235b | 2230 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2231 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2232 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2233 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2234 | (const_int 0))) |
52d3af72 DE |
2235 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2236 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2237 | "TARGET_32BIT" |
1fd4e8c1 RK |
2238 | "@ |
2239 | and. %3,%1,%2 | |
ca7f5001 RK |
2240 | {andil.|andi.} %3,%1,%b2 |
2241 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2242 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2243 | # | |
2244 | # | |
2245 | # | |
2246 | #" | |
2247 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2248 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2249 | |
0ba1b2ff AM |
2250 | (define_insn "*andsi3_internal3" |
2251 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2252 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2253 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2254 | (const_int 0))) | |
2255 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2256 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2257 | "TARGET_64BIT" |
0ba1b2ff AM |
2258 | "@ |
2259 | # | |
2260 | {andil.|andi.} %3,%1,%b2 | |
2261 | {andiu.|andis.} %3,%1,%u2 | |
2262 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2263 | # | |
2264 | # | |
2265 | # | |
2266 | #" | |
2267 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2268 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2269 | ||
52d3af72 DE |
2270 | (define_split |
2271 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2272 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2273 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2274 | (const_int 0))) |
52d3af72 DE |
2275 | (clobber (match_scratch:SI 3 "")) |
2276 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2277 | "reload_completed" |
52d3af72 DE |
2278 | [(parallel [(set (match_dup 3) |
2279 | (and:SI (match_dup 1) | |
2280 | (match_dup 2))) | |
2281 | (clobber (match_dup 4))]) | |
2282 | (set (match_dup 0) | |
2283 | (compare:CC (match_dup 3) | |
2284 | (const_int 0)))] | |
2285 | "") | |
2286 | ||
0ba1b2ff AM |
2287 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2288 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2289 | ||
2290 | (define_split | |
2291 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2292 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2293 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2294 | (const_int 0))) | |
2295 | (clobber (match_scratch:SI 3 "")) | |
2296 | (clobber (match_scratch:CC 4 ""))] | |
2297 | "TARGET_POWERPC64 && reload_completed" | |
2298 | [(parallel [(set (match_dup 3) | |
2299 | (and:SI (match_dup 1) | |
2300 | (match_dup 2))) | |
2301 | (clobber (match_dup 4))]) | |
2302 | (set (match_dup 0) | |
2303 | (compare:CC (match_dup 3) | |
2304 | (const_int 0)))] | |
2305 | "") | |
2306 | ||
2307 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2308 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2309 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2310 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2311 | (const_int 0))) |
2312 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2313 | (and:SI (match_dup 1) | |
2314 | (match_dup 2))) | |
2315 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2316 | "TARGET_32BIT" |
1fd4e8c1 RK |
2317 | "@ |
2318 | and. %0,%1,%2 | |
ca7f5001 RK |
2319 | {andil.|andi.} %0,%1,%b2 |
2320 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2321 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2322 | # | |
2323 | # | |
2324 | # | |
2325 | #" | |
2326 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2327 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2328 | ||
0ba1b2ff AM |
2329 | (define_insn "*andsi3_internal5" |
2330 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2331 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2332 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2333 | (const_int 0))) | |
2334 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2335 | (and:SI (match_dup 1) | |
2336 | (match_dup 2))) | |
2337 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2338 | "TARGET_64BIT" |
0ba1b2ff AM |
2339 | "@ |
2340 | # | |
2341 | {andil.|andi.} %0,%1,%b2 | |
2342 | {andiu.|andis.} %0,%1,%u2 | |
2343 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
2344 | # | |
2345 | # | |
2346 | # | |
2347 | #" | |
2348 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2349 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2350 | ||
52d3af72 DE |
2351 | (define_split |
2352 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2353 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2354 | (match_operand:SI 2 "and_operand" "")) | |
2355 | (const_int 0))) | |
2356 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2357 | (and:SI (match_dup 1) | |
2358 | (match_dup 2))) | |
2359 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2360 | "reload_completed" |
52d3af72 DE |
2361 | [(parallel [(set (match_dup 0) |
2362 | (and:SI (match_dup 1) | |
2363 | (match_dup 2))) | |
2364 | (clobber (match_dup 4))]) | |
2365 | (set (match_dup 3) | |
2366 | (compare:CC (match_dup 0) | |
2367 | (const_int 0)))] | |
2368 | "") | |
1fd4e8c1 | 2369 | |
0ba1b2ff AM |
2370 | (define_split |
2371 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
2372 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2373 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2374 | (const_int 0))) | |
2375 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2376 | (and:SI (match_dup 1) | |
2377 | (match_dup 2))) | |
2378 | (clobber (match_scratch:CC 4 ""))] | |
2379 | "TARGET_POWERPC64 && reload_completed" | |
2380 | [(parallel [(set (match_dup 0) | |
2381 | (and:SI (match_dup 1) | |
2382 | (match_dup 2))) | |
2383 | (clobber (match_dup 4))]) | |
2384 | (set (match_dup 3) | |
2385 | (compare:CC (match_dup 0) | |
2386 | (const_int 0)))] | |
2387 | "") | |
2388 | ||
2389 | ;; Handle the PowerPC64 rlwinm corner case | |
2390 | ||
2391 | (define_insn_and_split "*andsi3_internal6" | |
2392 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2393 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2394 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
2395 | "TARGET_POWERPC64" | |
2396 | "#" | |
2397 | "TARGET_POWERPC64" | |
2398 | [(set (match_dup 0) | |
2399 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
2400 | (match_dup 4))) | |
2401 | (set (match_dup 0) | |
2402 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
2403 | " | |
2404 | { | |
2405 | int mb = extract_MB (operands[2]); | |
2406 | int me = extract_ME (operands[2]); | |
2407 | operands[3] = GEN_INT (me + 1); | |
2408 | operands[5] = GEN_INT (32 - (me + 1)); | |
2409 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2410 | }" | |
2411 | [(set_attr "length" "8")]) | |
2412 | ||
2413 | (define_insn_and_split "*andsi3_internal7" | |
2414 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") | |
2415 | (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r") | |
2416 | (match_operand:SI 1 "mask_operand_wrap" "i,i")) | |
2417 | (const_int 0))) | |
2418 | (clobber (match_scratch:SI 3 "=r,r"))] | |
2419 | "TARGET_POWERPC64" | |
2420 | "#" | |
2421 | "TARGET_POWERPC64" | |
2422 | [(parallel [(set (match_dup 2) | |
2423 | (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4)) | |
2424 | (match_dup 5)) | |
2425 | (const_int 0))) | |
2426 | (clobber (match_dup 3))])] | |
2427 | " | |
2428 | { | |
2429 | int mb = extract_MB (operands[1]); | |
2430 | int me = extract_ME (operands[1]); | |
2431 | operands[4] = GEN_INT (me + 1); | |
2432 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2433 | }" | |
2434 | [(set_attr "type" "delayed_compare,compare") | |
2435 | (set_attr "length" "4,8")]) | |
2436 | ||
2437 | (define_insn_and_split "*andsi3_internal8" | |
2438 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") | |
2439 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2440 | (match_operand:SI 2 "mask_operand_wrap" "i,i")) | |
2441 | (const_int 0))) | |
2442 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
2443 | (and:SI (match_dup 1) | |
2444 | (match_dup 2)))] | |
2445 | "TARGET_POWERPC64" | |
2446 | "#" | |
2447 | "TARGET_POWERPC64" | |
2448 | [(parallel [(set (match_dup 3) | |
2449 | (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
2450 | (match_dup 5)) | |
2451 | (const_int 0))) | |
2452 | (set (match_dup 0) | |
2453 | (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
2454 | (match_dup 5)))]) | |
2455 | (set (match_dup 0) | |
2456 | (rotate:SI (match_dup 0) (match_dup 6)))] | |
2457 | " | |
2458 | { | |
2459 | int mb = extract_MB (operands[2]); | |
2460 | int me = extract_ME (operands[2]); | |
2461 | operands[4] = GEN_INT (me + 1); | |
2462 | operands[6] = GEN_INT (32 - (me + 1)); | |
2463 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2464 | }" | |
2465 | [(set_attr "type" "delayed_compare,compare") | |
2466 | (set_attr "length" "8,12")]) | |
2467 | ||
7cd5235b | 2468 | (define_expand "iorsi3" |
cd2b37d9 | 2469 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2470 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2471 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2472 | "" |
f357808b RK |
2473 | " |
2474 | { | |
7cd5235b | 2475 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2476 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2477 | { |
2478 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2479 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2480 | ? operands[0] : gen_reg_rtx (SImode)); |
2481 | ||
a260abc9 DE |
2482 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2483 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2484 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2485 | DONE; |
2486 | } | |
f357808b RK |
2487 | }") |
2488 | ||
7cd5235b | 2489 | (define_expand "xorsi3" |
cd2b37d9 | 2490 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2491 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2492 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2493 | "" |
7cd5235b | 2494 | " |
1fd4e8c1 | 2495 | { |
7cd5235b | 2496 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2497 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2498 | { |
2499 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2500 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2501 | ? operands[0] : gen_reg_rtx (SImode)); |
2502 | ||
a260abc9 DE |
2503 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2504 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2505 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2506 | DONE; |
2507 | } | |
1fd4e8c1 RK |
2508 | }") |
2509 | ||
dfbdccdb | 2510 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2511 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2512 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2513 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2514 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2515 | "" |
2516 | "@ | |
dfbdccdb GK |
2517 | %q3 %0,%1,%2 |
2518 | {%q3il|%q3i} %0,%1,%b2 | |
2519 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2520 | |
dfbdccdb | 2521 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2522 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2523 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2524 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2525 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2526 | (const_int 0))) | |
52d3af72 | 2527 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2528 | "TARGET_32BIT" |
52d3af72 | 2529 | "@ |
dfbdccdb | 2530 | %q4. %3,%1,%2 |
52d3af72 DE |
2531 | #" |
2532 | [(set_attr "type" "compare") | |
2533 | (set_attr "length" "4,8")]) | |
2534 | ||
2535 | (define_split | |
2536 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2537 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2538 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2539 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2540 | (const_int 0))) |
52d3af72 | 2541 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2542 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2543 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2544 | (set (match_dup 0) |
2545 | (compare:CC (match_dup 3) | |
2546 | (const_int 0)))] | |
2547 | "") | |
815cdc52 | 2548 | |
dfbdccdb | 2549 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2550 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2551 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2552 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2553 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2554 | (const_int 0))) | |
52d3af72 | 2555 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2556 | (match_dup 4))] |
4b8a63d6 | 2557 | "TARGET_32BIT" |
52d3af72 | 2558 | "@ |
dfbdccdb | 2559 | %q4. %0,%1,%2 |
52d3af72 DE |
2560 | #" |
2561 | [(set_attr "type" "compare") | |
2562 | (set_attr "length" "4,8")]) | |
2563 | ||
2564 | (define_split | |
e72247f4 | 2565 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2566 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2567 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2568 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2569 | (const_int 0))) |
75540af0 | 2570 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2571 | (match_dup 4))] |
4b8a63d6 | 2572 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2573 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2574 | (set (match_dup 3) |
2575 | (compare:CC (match_dup 0) | |
2576 | (const_int 0)))] | |
2577 | "") | |
1fd4e8c1 | 2578 | |
6ae08853 | 2579 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 2580 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
2581 | |
2582 | (define_split | |
2583 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2584 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2585 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2586 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2587 | "" |
dfbdccdb GK |
2588 | [(set (match_dup 0) (match_dup 4)) |
2589 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2590 | " |
2591 | { | |
dfbdccdb GK |
2592 | rtx i; |
2593 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
1c563bed | 2594 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2595 | operands[1], i); |
dfbdccdb | 2596 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1c563bed | 2597 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2598 | operands[0], i); |
a260abc9 DE |
2599 | }") |
2600 | ||
dfbdccdb | 2601 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2602 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2603 | (match_operator:SI 3 "boolean_operator" |
2604 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2605 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2606 | "" |
dfbdccdb | 2607 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2608 | |
dfbdccdb | 2609 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2610 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2611 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2612 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2613 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2614 | (const_int 0))) | |
52d3af72 | 2615 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2616 | "TARGET_32BIT" |
52d3af72 | 2617 | "@ |
dfbdccdb | 2618 | %q4. %3,%2,%1 |
52d3af72 DE |
2619 | #" |
2620 | [(set_attr "type" "compare") | |
2621 | (set_attr "length" "4,8")]) | |
2622 | ||
2623 | (define_split | |
2624 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2625 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2626 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2627 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2628 | (const_int 0))) |
52d3af72 | 2629 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2630 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2631 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2632 | (set (match_dup 0) |
2633 | (compare:CC (match_dup 3) | |
2634 | (const_int 0)))] | |
2635 | "") | |
1fd4e8c1 | 2636 | |
dfbdccdb | 2637 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2638 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2639 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2640 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2641 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2642 | (const_int 0))) | |
52d3af72 | 2643 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2644 | (match_dup 4))] |
4b8a63d6 | 2645 | "TARGET_32BIT" |
52d3af72 | 2646 | "@ |
dfbdccdb | 2647 | %q4. %0,%2,%1 |
52d3af72 DE |
2648 | #" |
2649 | [(set_attr "type" "compare") | |
2650 | (set_attr "length" "4,8")]) | |
2651 | ||
2652 | (define_split | |
e72247f4 | 2653 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2654 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2655 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2656 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2657 | (const_int 0))) |
75540af0 | 2658 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2659 | (match_dup 4))] |
4b8a63d6 | 2660 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2661 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2662 | (set (match_dup 3) |
2663 | (compare:CC (match_dup 0) | |
2664 | (const_int 0)))] | |
2665 | "") | |
2666 | ||
dfbdccdb | 2667 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2668 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2669 | (match_operator:SI 3 "boolean_operator" |
2670 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2671 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2672 | "" |
dfbdccdb | 2673 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2674 | |
dfbdccdb | 2675 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2676 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2677 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2678 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2679 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2680 | (const_int 0))) | |
52d3af72 | 2681 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2682 | "TARGET_32BIT" |
52d3af72 | 2683 | "@ |
dfbdccdb | 2684 | %q4. %3,%1,%2 |
52d3af72 DE |
2685 | #" |
2686 | [(set_attr "type" "compare") | |
2687 | (set_attr "length" "4,8")]) | |
2688 | ||
2689 | (define_split | |
2690 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2691 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2692 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2693 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2694 | (const_int 0))) |
52d3af72 | 2695 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2696 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2697 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2698 | (set (match_dup 0) |
2699 | (compare:CC (match_dup 3) | |
2700 | (const_int 0)))] | |
2701 | "") | |
1fd4e8c1 | 2702 | |
dfbdccdb | 2703 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2704 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2705 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2706 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2707 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2708 | (const_int 0))) | |
52d3af72 | 2709 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2710 | (match_dup 4))] |
4b8a63d6 | 2711 | "TARGET_32BIT" |
52d3af72 | 2712 | "@ |
dfbdccdb | 2713 | %q4. %0,%1,%2 |
52d3af72 DE |
2714 | #" |
2715 | [(set_attr "type" "compare") | |
2716 | (set_attr "length" "4,8")]) | |
2717 | ||
2718 | (define_split | |
e72247f4 | 2719 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2720 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2721 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2722 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2723 | (const_int 0))) |
75540af0 | 2724 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2725 | (match_dup 4))] |
4b8a63d6 | 2726 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2727 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2728 | (set (match_dup 3) |
2729 | (compare:CC (match_dup 0) | |
2730 | (const_int 0)))] | |
2731 | "") | |
1fd4e8c1 RK |
2732 | |
2733 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2734 | ;; orders. Don't define forms that only set CR fields because these | |
2735 | ;; would modify an input register. | |
2736 | ||
7cd5235b | 2737 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2738 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2739 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2740 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2741 | (and:SI (match_dup 2) | |
cd2b37d9 | 2742 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2743 | "TARGET_POWER" |
01def764 | 2744 | "maskir %0,%3,%2") |
1fd4e8c1 | 2745 | |
7cd5235b | 2746 | (define_insn "*maskir_internal2" |
242e8072 | 2747 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2748 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2749 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2750 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2751 | (match_dup 2))))] |
ca7f5001 | 2752 | "TARGET_POWER" |
01def764 | 2753 | "maskir %0,%3,%2") |
1fd4e8c1 | 2754 | |
7cd5235b | 2755 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2756 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2757 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2758 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2759 | (and:SI (not:SI (match_dup 2)) |
2760 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2761 | "TARGET_POWER" |
01def764 | 2762 | "maskir %0,%3,%2") |
1fd4e8c1 | 2763 | |
7cd5235b | 2764 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2765 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2766 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2767 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2768 | (and:SI (not:SI (match_dup 2)) | |
2769 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2770 | "TARGET_POWER" |
01def764 | 2771 | "maskir %0,%3,%2") |
1fd4e8c1 | 2772 | |
7cd5235b | 2773 | (define_insn "*maskir_internal5" |
9ebbca7d | 2774 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2775 | (compare:CC |
9ebbca7d GK |
2776 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2777 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2778 | (and:SI (match_dup 2) |
9ebbca7d | 2779 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2780 | (const_int 0))) |
9ebbca7d | 2781 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2782 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2783 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2784 | "TARGET_POWER" |
9ebbca7d GK |
2785 | "@ |
2786 | maskir. %0,%3,%2 | |
2787 | #" | |
2788 | [(set_attr "type" "compare") | |
2789 | (set_attr "length" "4,8")]) | |
2790 | ||
2791 | (define_split | |
2792 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2793 | (compare:CC | |
2794 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2795 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2796 | (and:SI (match_dup 2) | |
2797 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2798 | (const_int 0))) | |
2799 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2800 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2801 | (and:SI (match_dup 2) (match_dup 3))))] | |
2802 | "TARGET_POWER && reload_completed" | |
2803 | [(set (match_dup 0) | |
2804 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2805 | (and:SI (match_dup 2) (match_dup 3)))) | |
2806 | (set (match_dup 4) | |
2807 | (compare:CC (match_dup 0) | |
2808 | (const_int 0)))] | |
2809 | "") | |
1fd4e8c1 | 2810 | |
7cd5235b | 2811 | (define_insn "*maskir_internal6" |
9ebbca7d | 2812 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2813 | (compare:CC |
9ebbca7d GK |
2814 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2815 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2816 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2817 | (match_dup 2))) |
1fd4e8c1 | 2818 | (const_int 0))) |
9ebbca7d | 2819 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2820 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2821 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2822 | "TARGET_POWER" |
9ebbca7d GK |
2823 | "@ |
2824 | maskir. %0,%3,%2 | |
2825 | #" | |
2826 | [(set_attr "type" "compare") | |
2827 | (set_attr "length" "4,8")]) | |
2828 | ||
2829 | (define_split | |
2830 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2831 | (compare:CC | |
2832 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2833 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2834 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2835 | (match_dup 2))) | |
2836 | (const_int 0))) | |
2837 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2838 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2839 | (and:SI (match_dup 3) (match_dup 2))))] | |
2840 | "TARGET_POWER && reload_completed" | |
2841 | [(set (match_dup 0) | |
2842 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2843 | (and:SI (match_dup 3) (match_dup 2)))) | |
2844 | (set (match_dup 4) | |
2845 | (compare:CC (match_dup 0) | |
2846 | (const_int 0)))] | |
2847 | "") | |
1fd4e8c1 | 2848 | |
7cd5235b | 2849 | (define_insn "*maskir_internal7" |
9ebbca7d | 2850 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 2851 | (compare:CC |
9ebbca7d GK |
2852 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
2853 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2854 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2855 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 2856 | (const_int 0))) |
9ebbca7d | 2857 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
2858 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2859 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2860 | "TARGET_POWER" | |
9ebbca7d GK |
2861 | "@ |
2862 | maskir. %0,%3,%2 | |
2863 | #" | |
2864 | [(set_attr "type" "compare") | |
2865 | (set_attr "length" "4,8")]) | |
2866 | ||
2867 | (define_split | |
2868 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2869 | (compare:CC | |
2870 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
2871 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
2872 | (and:SI (not:SI (match_dup 2)) | |
2873 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2874 | (const_int 0))) | |
2875 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2876 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2877 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2878 | "TARGET_POWER && reload_completed" | |
2879 | [(set (match_dup 0) | |
2880 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2881 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2882 | (set (match_dup 4) | |
2883 | (compare:CC (match_dup 0) | |
2884 | (const_int 0)))] | |
2885 | "") | |
1fd4e8c1 | 2886 | |
7cd5235b | 2887 | (define_insn "*maskir_internal8" |
9ebbca7d | 2888 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2889 | (compare:CC |
9ebbca7d GK |
2890 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
2891 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 2892 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2893 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 2894 | (const_int 0))) |
9ebbca7d | 2895 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2896 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2897 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2898 | "TARGET_POWER" |
9ebbca7d GK |
2899 | "@ |
2900 | maskir. %0,%3,%2 | |
2901 | #" | |
2902 | [(set_attr "type" "compare") | |
2903 | (set_attr "length" "4,8")]) | |
fcce224d | 2904 | |
9ebbca7d GK |
2905 | (define_split |
2906 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2907 | (compare:CC | |
2908 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2909 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2910 | (and:SI (not:SI (match_dup 2)) | |
2911 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2912 | (const_int 0))) | |
2913 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2914 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2915 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2916 | "TARGET_POWER && reload_completed" | |
2917 | [(set (match_dup 0) | |
2918 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2919 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2920 | (set (match_dup 4) | |
2921 | (compare:CC (match_dup 0) | |
2922 | (const_int 0)))] | |
2923 | "") | |
fcce224d | 2924 | \f |
1fd4e8c1 RK |
2925 | ;; Rotate and shift insns, in all their variants. These support shifts, |
2926 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2927 | (define_expand "insv" |
0ad91047 DE |
2928 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2929 | (match_operand:SI 1 "const_int_operand" "") | |
2930 | (match_operand:SI 2 "const_int_operand" "")) | |
2931 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2932 | "" |
2933 | " | |
2934 | { | |
2935 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2936 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2937 | compiler if the address of the structure is taken later. */ | |
2938 | if (GET_CODE (operands[0]) == SUBREG | |
2939 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2940 | FAIL; | |
a78e33fc DE |
2941 | |
2942 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2943 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2944 | else | |
2945 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2946 | DONE; | |
034c1be0 MM |
2947 | }") |
2948 | ||
a78e33fc | 2949 | (define_insn "insvsi" |
cd2b37d9 | 2950 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2951 | (match_operand:SI 1 "const_int_operand" "i") |
2952 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2953 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2954 | "" |
2955 | "* | |
2956 | { | |
2957 | int start = INTVAL (operands[2]) & 31; | |
2958 | int size = INTVAL (operands[1]) & 31; | |
2959 | ||
89e9f3a8 MM |
2960 | operands[4] = GEN_INT (32 - start - size); |
2961 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2962 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2963 | }" |
2964 | [(set_attr "type" "insert_word")]) | |
1fd4e8c1 | 2965 | |
a78e33fc | 2966 | (define_insn "*insvsi_internal1" |
d56d506a RK |
2967 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2968 | (match_operand:SI 1 "const_int_operand" "i") | |
2969 | (match_operand:SI 2 "const_int_operand" "i")) | |
2970 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2971 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2972 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2973 | "* |
2974 | { | |
2975 | int shift = INTVAL (operands[4]) & 31; | |
2976 | int start = INTVAL (operands[2]) & 31; | |
2977 | int size = INTVAL (operands[1]) & 31; | |
2978 | ||
89e9f3a8 MM |
2979 | operands[4] = GEN_INT (shift - start - size); |
2980 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2981 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2982 | }" |
2983 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2984 | |
a78e33fc | 2985 | (define_insn "*insvsi_internal2" |
d56d506a RK |
2986 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2987 | (match_operand:SI 1 "const_int_operand" "i") | |
2988 | (match_operand:SI 2 "const_int_operand" "i")) | |
2989 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2990 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2991 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2992 | "* |
2993 | { | |
2994 | int shift = INTVAL (operands[4]) & 31; | |
2995 | int start = INTVAL (operands[2]) & 31; | |
2996 | int size = INTVAL (operands[1]) & 31; | |
2997 | ||
89e9f3a8 MM |
2998 | operands[4] = GEN_INT (32 - shift - start - size); |
2999 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3000 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3001 | }" |
3002 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3003 | |
a78e33fc | 3004 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3005 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3006 | (match_operand:SI 1 "const_int_operand" "i") | |
3007 | (match_operand:SI 2 "const_int_operand" "i")) | |
3008 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3009 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3010 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3011 | "* |
3012 | { | |
3013 | int shift = INTVAL (operands[4]) & 31; | |
3014 | int start = INTVAL (operands[2]) & 31; | |
3015 | int size = INTVAL (operands[1]) & 31; | |
3016 | ||
89e9f3a8 MM |
3017 | operands[4] = GEN_INT (32 - shift - start - size); |
3018 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3019 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3020 | }" |
3021 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3022 | |
a78e33fc | 3023 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3024 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3025 | (match_operand:SI 1 "const_int_operand" "i") | |
3026 | (match_operand:SI 2 "const_int_operand" "i")) | |
3027 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3028 | (match_operand:SI 4 "const_int_operand" "i") | |
3029 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3030 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3031 | "* | |
3032 | { | |
3033 | int extract_start = INTVAL (operands[5]) & 31; | |
3034 | int extract_size = INTVAL (operands[4]) & 31; | |
3035 | int insert_start = INTVAL (operands[2]) & 31; | |
3036 | int insert_size = INTVAL (operands[1]) & 31; | |
3037 | ||
3038 | /* Align extract field with insert field */ | |
3a598fbe | 3039 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3040 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3041 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
8e8238f1 DE |
3042 | }" |
3043 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3044 | |
f241bf89 EC |
3045 | ;; combine patterns for rlwimi |
3046 | (define_insn "*insvsi_internal5" | |
3047 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3048 | (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
3049 | (match_operand:SI 1 "mask_operand" "i")) | |
3050 | (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3051 | (match_operand:SI 2 "const_int_operand" "i")) | |
3052 | (match_operand:SI 5 "mask_operand" "i"))))] | |
3053 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3054 | "* | |
3055 | { | |
3056 | int me = extract_ME(operands[5]); | |
3057 | int mb = extract_MB(operands[5]); | |
3058 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3059 | operands[2] = GEN_INT(mb); | |
3060 | operands[1] = GEN_INT(me); | |
3061 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3062 | }" | |
3063 | [(set_attr "type" "insert_word")]) | |
3064 | ||
3065 | (define_insn "*insvsi_internal6" | |
3066 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3067 | (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3068 | (match_operand:SI 2 "const_int_operand" "i")) | |
3069 | (match_operand:SI 5 "mask_operand" "i")) | |
3070 | (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
3071 | (match_operand:SI 1 "mask_operand" "i"))))] | |
3072 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3073 | "* | |
3074 | { | |
3075 | int me = extract_ME(operands[5]); | |
3076 | int mb = extract_MB(operands[5]); | |
3077 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3078 | operands[2] = GEN_INT(mb); | |
3079 | operands[1] = GEN_INT(me); | |
3080 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3081 | }" | |
3082 | [(set_attr "type" "insert_word")]) | |
3083 | ||
a78e33fc | 3084 | (define_insn "insvdi" |
685f3906 | 3085 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3086 | (match_operand:SI 1 "const_int_operand" "i") |
3087 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3088 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3089 | "TARGET_POWERPC64" | |
3090 | "* | |
3091 | { | |
3092 | int start = INTVAL (operands[2]) & 63; | |
3093 | int size = INTVAL (operands[1]) & 63; | |
3094 | ||
a78e33fc DE |
3095 | operands[1] = GEN_INT (64 - start - size); |
3096 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3097 | }") |
3098 | ||
11ac38b2 DE |
3099 | (define_insn "*insvdi_internal2" |
3100 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3101 | (match_operand:SI 1 "const_int_operand" "i") | |
3102 | (match_operand:SI 2 "const_int_operand" "i")) | |
3103 | (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3104 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3105 | "TARGET_POWERPC64 | |
3106 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3107 | "* | |
3108 | { | |
3109 | int shift = INTVAL (operands[4]) & 63; | |
3110 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3111 | int size = INTVAL (operands[1]) & 63; | |
3112 | ||
3113 | operands[4] = GEN_INT (64 - shift - start - size); | |
3114 | operands[2] = GEN_INT (start); | |
3115 | operands[1] = GEN_INT (start + size - 1); | |
3116 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3117 | }") | |
3118 | ||
3119 | (define_insn "*insvdi_internal3" | |
3120 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3121 | (match_operand:SI 1 "const_int_operand" "i") | |
3122 | (match_operand:SI 2 "const_int_operand" "i")) | |
3123 | (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3124 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3125 | "TARGET_POWERPC64 | |
3126 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3127 | "* | |
3128 | { | |
3129 | int shift = INTVAL (operands[4]) & 63; | |
3130 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3131 | int size = INTVAL (operands[1]) & 63; | |
3132 | ||
3133 | operands[4] = GEN_INT (64 - shift - start - size); | |
3134 | operands[2] = GEN_INT (start); | |
3135 | operands[1] = GEN_INT (start + size - 1); | |
3136 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3137 | }") | |
3138 | ||
034c1be0 | 3139 | (define_expand "extzv" |
0ad91047 DE |
3140 | [(set (match_operand 0 "gpc_reg_operand" "") |
3141 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3142 | (match_operand:SI 2 "const_int_operand" "") | |
3143 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3144 | "" |
3145 | " | |
3146 | { | |
3147 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3148 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3149 | compiler if the address of the structure is taken later. */ | |
3150 | if (GET_CODE (operands[0]) == SUBREG | |
3151 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3152 | FAIL; | |
a78e33fc DE |
3153 | |
3154 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3155 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3156 | else | |
3157 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3158 | DONE; | |
034c1be0 MM |
3159 | }") |
3160 | ||
a78e33fc | 3161 | (define_insn "extzvsi" |
cd2b37d9 RK |
3162 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3163 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3164 | (match_operand:SI 2 "const_int_operand" "i") |
3165 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3166 | "" | |
3167 | "* | |
3168 | { | |
3169 | int start = INTVAL (operands[3]) & 31; | |
3170 | int size = INTVAL (operands[2]) & 31; | |
3171 | ||
3172 | if (start + size >= 32) | |
3173 | operands[3] = const0_rtx; | |
3174 | else | |
89e9f3a8 | 3175 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3176 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3177 | }") |
3178 | ||
a78e33fc | 3179 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3180 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3181 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3182 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3183 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3184 | (const_int 0))) |
9ebbca7d | 3185 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3186 | "" |
1fd4e8c1 RK |
3187 | "* |
3188 | { | |
3189 | int start = INTVAL (operands[3]) & 31; | |
3190 | int size = INTVAL (operands[2]) & 31; | |
3191 | ||
9ebbca7d GK |
3192 | /* Force split for non-cc0 compare. */ |
3193 | if (which_alternative == 1) | |
3194 | return \"#\"; | |
3195 | ||
43a88a8c | 3196 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3197 | word, it is possible to use andiu. or andil. to test it. This is |
3198 | useful because the condition register set-use delay is smaller for | |
3199 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3200 | position is 0 because the LT and GT bits may be set wrong. */ | |
3201 | ||
3202 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3203 | { |
3a598fbe | 3204 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3205 | - (1 << (16 - (start & 15) - size)))); |
3206 | if (start < 16) | |
ca7f5001 | 3207 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3208 | else |
ca7f5001 | 3209 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3210 | } |
7e69e155 | 3211 | |
1fd4e8c1 RK |
3212 | if (start + size >= 32) |
3213 | operands[3] = const0_rtx; | |
3214 | else | |
89e9f3a8 | 3215 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3216 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3217 | }" |
9ebbca7d GK |
3218 | [(set_attr "type" "compare") |
3219 | (set_attr "length" "4,8")]) | |
3220 | ||
3221 | (define_split | |
3222 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3223 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3224 | (match_operand:SI 2 "const_int_operand" "") | |
3225 | (match_operand:SI 3 "const_int_operand" "")) | |
3226 | (const_int 0))) | |
3227 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3228 | "reload_completed" |
9ebbca7d GK |
3229 | [(set (match_dup 4) |
3230 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3231 | (match_dup 3))) | |
3232 | (set (match_dup 0) | |
3233 | (compare:CC (match_dup 4) | |
3234 | (const_int 0)))] | |
3235 | "") | |
1fd4e8c1 | 3236 | |
a78e33fc | 3237 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3238 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3239 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3240 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3241 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3242 | (const_int 0))) |
9ebbca7d | 3243 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3244 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3245 | "" |
1fd4e8c1 RK |
3246 | "* |
3247 | { | |
3248 | int start = INTVAL (operands[3]) & 31; | |
3249 | int size = INTVAL (operands[2]) & 31; | |
3250 | ||
9ebbca7d GK |
3251 | /* Force split for non-cc0 compare. */ |
3252 | if (which_alternative == 1) | |
3253 | return \"#\"; | |
3254 | ||
bc401279 | 3255 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3256 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3257 | if (start >= 16 && start + size == 32) |
df031c43 | 3258 | { |
bc401279 AM |
3259 | operands[3] = GEN_INT ((1 << size) - 1); |
3260 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3261 | } |
7e69e155 | 3262 | |
1fd4e8c1 RK |
3263 | if (start + size >= 32) |
3264 | operands[3] = const0_rtx; | |
3265 | else | |
89e9f3a8 | 3266 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3267 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3268 | }" |
ce71f754 | 3269 | [(set_attr "type" "compare") |
9ebbca7d GK |
3270 | (set_attr "length" "4,8")]) |
3271 | ||
3272 | (define_split | |
3273 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3274 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3275 | (match_operand:SI 2 "const_int_operand" "") | |
3276 | (match_operand:SI 3 "const_int_operand" "")) | |
3277 | (const_int 0))) | |
3278 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3279 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3280 | "reload_completed" |
9ebbca7d GK |
3281 | [(set (match_dup 0) |
3282 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3283 | (set (match_dup 4) | |
3284 | (compare:CC (match_dup 0) | |
3285 | (const_int 0)))] | |
3286 | "") | |
1fd4e8c1 | 3287 | |
a78e33fc | 3288 | (define_insn "extzvdi" |
685f3906 DE |
3289 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3290 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3291 | (match_operand:SI 2 "const_int_operand" "i") |
3292 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3293 | "TARGET_POWERPC64" |
3294 | "* | |
3295 | { | |
3296 | int start = INTVAL (operands[3]) & 63; | |
3297 | int size = INTVAL (operands[2]) & 63; | |
3298 | ||
3299 | if (start + size >= 64) | |
3300 | operands[3] = const0_rtx; | |
3301 | else | |
89e9f3a8 MM |
3302 | operands[3] = GEN_INT (start + size); |
3303 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3304 | return \"rldicl %0,%1,%3,%2\"; |
3305 | }") | |
3306 | ||
a78e33fc | 3307 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3308 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3309 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3310 | (match_operand:SI 2 "const_int_operand" "i") |
3311 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3312 | (const_int 0))) |
29ae5b89 | 3313 | (clobber (match_scratch:DI 4 "=r"))] |
683bdff7 | 3314 | "TARGET_64BIT" |
685f3906 DE |
3315 | "* |
3316 | { | |
3317 | int start = INTVAL (operands[3]) & 63; | |
3318 | int size = INTVAL (operands[2]) & 63; | |
3319 | ||
3320 | if (start + size >= 64) | |
3321 | operands[3] = const0_rtx; | |
3322 | else | |
89e9f3a8 MM |
3323 | operands[3] = GEN_INT (start + size); |
3324 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3325 | return \"rldicl. %4,%1,%3,%2\"; |
3326 | }") | |
3327 | ||
a78e33fc | 3328 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3329 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3330 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3331 | (match_operand:SI 2 "const_int_operand" "i") |
3332 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3333 | (const_int 0))) |
29ae5b89 | 3334 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 | 3335 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
683bdff7 | 3336 | "TARGET_64BIT" |
685f3906 DE |
3337 | "* |
3338 | { | |
3339 | int start = INTVAL (operands[3]) & 63; | |
3340 | int size = INTVAL (operands[2]) & 63; | |
3341 | ||
3342 | if (start + size >= 64) | |
3343 | operands[3] = const0_rtx; | |
3344 | else | |
89e9f3a8 MM |
3345 | operands[3] = GEN_INT (start + size); |
3346 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3347 | return \"rldicl. %0,%1,%3,%2\"; |
3348 | }") | |
3349 | ||
1fd4e8c1 | 3350 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3351 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3352 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3353 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3354 | "" | |
ca7f5001 | 3355 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3356 | |
a260abc9 | 3357 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3358 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3359 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3360 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3361 | (const_int 0))) |
9ebbca7d | 3362 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 3363 | "" |
9ebbca7d GK |
3364 | "@ |
3365 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3366 | #" | |
3367 | [(set_attr "type" "delayed_compare") | |
3368 | (set_attr "length" "4,8")]) | |
3369 | ||
3370 | (define_split | |
3371 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3372 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3373 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3374 | (const_int 0))) | |
3375 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 3376 | "reload_completed" |
9ebbca7d GK |
3377 | [(set (match_dup 3) |
3378 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3379 | (set (match_dup 0) | |
3380 | (compare:CC (match_dup 3) | |
3381 | (const_int 0)))] | |
3382 | "") | |
1fd4e8c1 | 3383 | |
a260abc9 | 3384 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3385 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3386 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3387 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3388 | (const_int 0))) |
9ebbca7d | 3389 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3390 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 3391 | "" |
9ebbca7d GK |
3392 | "@ |
3393 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3394 | #" | |
3395 | [(set_attr "type" "delayed_compare") | |
3396 | (set_attr "length" "4,8")]) | |
3397 | ||
3398 | (define_split | |
3399 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3400 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3401 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3402 | (const_int 0))) | |
3403 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3404 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 3405 | "reload_completed" |
9ebbca7d GK |
3406 | [(set (match_dup 0) |
3407 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3408 | (set (match_dup 3) | |
3409 | (compare:CC (match_dup 0) | |
3410 | (const_int 0)))] | |
3411 | "") | |
1fd4e8c1 | 3412 | |
a260abc9 | 3413 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3414 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3415 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3416 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 3417 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3418 | "" |
ca7f5001 | 3419 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3420 | |
a260abc9 | 3421 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3422 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3423 | (compare:CC (and:SI |
9ebbca7d GK |
3424 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3425 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3426 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3427 | (const_int 0))) |
9ebbca7d | 3428 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3429 | "" |
9ebbca7d GK |
3430 | "@ |
3431 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3432 | #" | |
3433 | [(set_attr "type" "delayed_compare") | |
3434 | (set_attr "length" "4,8")]) | |
3435 | ||
3436 | (define_split | |
3437 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3438 | (compare:CC (and:SI | |
3439 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3440 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3441 | (match_operand:SI 3 "mask_operand" "")) | |
3442 | (const_int 0))) | |
3443 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3444 | "reload_completed" |
9ebbca7d GK |
3445 | [(set (match_dup 4) |
3446 | (and:SI (rotate:SI (match_dup 1) | |
3447 | (match_dup 2)) | |
3448 | (match_dup 3))) | |
3449 | (set (match_dup 0) | |
3450 | (compare:CC (match_dup 4) | |
3451 | (const_int 0)))] | |
3452 | "") | |
1fd4e8c1 | 3453 | |
a260abc9 | 3454 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3455 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3456 | (compare:CC (and:SI |
9ebbca7d GK |
3457 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3458 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3459 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3460 | (const_int 0))) |
9ebbca7d | 3461 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3462 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3463 | "" |
9ebbca7d GK |
3464 | "@ |
3465 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3466 | #" | |
3467 | [(set_attr "type" "delayed_compare") | |
3468 | (set_attr "length" "4,8")]) | |
3469 | ||
3470 | (define_split | |
3471 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3472 | (compare:CC (and:SI | |
3473 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3474 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3475 | (match_operand:SI 3 "mask_operand" "")) | |
3476 | (const_int 0))) | |
3477 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3478 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3479 | "reload_completed" |
9ebbca7d GK |
3480 | [(set (match_dup 0) |
3481 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3482 | (set (match_dup 4) | |
3483 | (compare:CC (match_dup 0) | |
3484 | (const_int 0)))] | |
3485 | "") | |
1fd4e8c1 | 3486 | |
a260abc9 | 3487 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3488 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3489 | (zero_extend:SI |
3490 | (subreg:QI | |
cd2b37d9 | 3491 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3492 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3493 | "" | |
ca7f5001 | 3494 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3495 | |
a260abc9 | 3496 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3497 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3498 | (compare:CC (zero_extend:SI |
3499 | (subreg:QI | |
9ebbca7d GK |
3500 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3501 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3502 | (const_int 0))) |
9ebbca7d | 3503 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3504 | "" |
9ebbca7d GK |
3505 | "@ |
3506 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3507 | #" | |
3508 | [(set_attr "type" "delayed_compare") | |
3509 | (set_attr "length" "4,8")]) | |
3510 | ||
3511 | (define_split | |
3512 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3513 | (compare:CC (zero_extend:SI | |
3514 | (subreg:QI | |
3515 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3516 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3517 | (const_int 0))) | |
3518 | (clobber (match_scratch:SI 3 ""))] | |
3519 | "reload_completed" | |
3520 | [(set (match_dup 3) | |
3521 | (zero_extend:SI (subreg:QI | |
3522 | (rotate:SI (match_dup 1) | |
3523 | (match_dup 2)) 0))) | |
3524 | (set (match_dup 0) | |
3525 | (compare:CC (match_dup 3) | |
3526 | (const_int 0)))] | |
3527 | "") | |
1fd4e8c1 | 3528 | |
a260abc9 | 3529 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3530 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3531 | (compare:CC (zero_extend:SI |
3532 | (subreg:QI | |
9ebbca7d GK |
3533 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3534 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3535 | (const_int 0))) |
9ebbca7d | 3536 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3537 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3538 | "" | |
9ebbca7d GK |
3539 | "@ |
3540 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3541 | #" | |
3542 | [(set_attr "type" "delayed_compare") | |
3543 | (set_attr "length" "4,8")]) | |
3544 | ||
3545 | (define_split | |
3546 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3547 | (compare:CC (zero_extend:SI | |
3548 | (subreg:QI | |
3549 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3550 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3551 | (const_int 0))) | |
3552 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3553 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3554 | "reload_completed" | |
3555 | [(set (match_dup 0) | |
3556 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3557 | (set (match_dup 3) | |
3558 | (compare:CC (match_dup 0) | |
3559 | (const_int 0)))] | |
3560 | "") | |
1fd4e8c1 | 3561 | |
a260abc9 | 3562 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3563 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3564 | (zero_extend:SI |
3565 | (subreg:HI | |
cd2b37d9 | 3566 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3567 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3568 | "" | |
ca7f5001 | 3569 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3570 | |
a260abc9 | 3571 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3572 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3573 | (compare:CC (zero_extend:SI |
3574 | (subreg:HI | |
9ebbca7d GK |
3575 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3576 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3577 | (const_int 0))) |
9ebbca7d | 3578 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3579 | "" |
9ebbca7d GK |
3580 | "@ |
3581 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3582 | #" | |
3583 | [(set_attr "type" "delayed_compare") | |
3584 | (set_attr "length" "4,8")]) | |
3585 | ||
3586 | (define_split | |
3587 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3588 | (compare:CC (zero_extend:SI | |
3589 | (subreg:HI | |
3590 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3591 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3592 | (const_int 0))) | |
3593 | (clobber (match_scratch:SI 3 ""))] | |
3594 | "reload_completed" | |
3595 | [(set (match_dup 3) | |
3596 | (zero_extend:SI (subreg:HI | |
3597 | (rotate:SI (match_dup 1) | |
3598 | (match_dup 2)) 0))) | |
3599 | (set (match_dup 0) | |
3600 | (compare:CC (match_dup 3) | |
3601 | (const_int 0)))] | |
3602 | "") | |
1fd4e8c1 | 3603 | |
a260abc9 | 3604 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3605 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3606 | (compare:CC (zero_extend:SI |
3607 | (subreg:HI | |
9ebbca7d GK |
3608 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3609 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3610 | (const_int 0))) |
9ebbca7d | 3611 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3612 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3613 | "" | |
9ebbca7d GK |
3614 | "@ |
3615 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3616 | #" | |
3617 | [(set_attr "type" "delayed_compare") | |
3618 | (set_attr "length" "4,8")]) | |
3619 | ||
3620 | (define_split | |
3621 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3622 | (compare:CC (zero_extend:SI | |
3623 | (subreg:HI | |
3624 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3625 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3626 | (const_int 0))) | |
3627 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3628 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3629 | "reload_completed" | |
3630 | [(set (match_dup 0) | |
3631 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3632 | (set (match_dup 3) | |
3633 | (compare:CC (match_dup 0) | |
3634 | (const_int 0)))] | |
3635 | "") | |
1fd4e8c1 RK |
3636 | |
3637 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3638 | ;; SHIFT_COUNT_TRUNCATED. | |
3639 | ||
ca7f5001 RK |
3640 | (define_expand "ashlsi3" |
3641 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3642 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3643 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3644 | "" | |
3645 | " | |
3646 | { | |
3647 | if (TARGET_POWER) | |
3648 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3649 | else | |
25c341fa | 3650 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3651 | DONE; |
3652 | }") | |
3653 | ||
3654 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3655 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3656 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3657 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3658 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3659 | "TARGET_POWER" |
1fd4e8c1 RK |
3660 | "@ |
3661 | sle %0,%1,%2 | |
9ebbca7d | 3662 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3663 | |
25c341fa | 3664 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3665 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3666 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3667 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3668 | "! TARGET_POWER" |
9ebbca7d | 3669 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3670 | |
3671 | (define_insn "" | |
9ebbca7d GK |
3672 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3673 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3674 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3675 | (const_int 0))) |
9ebbca7d GK |
3676 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3677 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3678 | "TARGET_POWER" |
1fd4e8c1 RK |
3679 | "@ |
3680 | sle. %3,%1,%2 | |
9ebbca7d GK |
3681 | {sli.|slwi.} %3,%1,%h2 |
3682 | # | |
3683 | #" | |
3684 | [(set_attr "type" "delayed_compare") | |
3685 | (set_attr "length" "4,4,8,8")]) | |
3686 | ||
3687 | (define_split | |
3688 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3689 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3690 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3691 | (const_int 0))) | |
3692 | (clobber (match_scratch:SI 3 "")) | |
3693 | (clobber (match_scratch:SI 4 ""))] | |
3694 | "TARGET_POWER && reload_completed" | |
3695 | [(parallel [(set (match_dup 3) | |
3696 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3697 | (clobber (match_dup 4))]) | |
3698 | (set (match_dup 0) | |
3699 | (compare:CC (match_dup 3) | |
3700 | (const_int 0)))] | |
3701 | "") | |
25c341fa | 3702 | |
ca7f5001 | 3703 | (define_insn "" |
9ebbca7d GK |
3704 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3705 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3706 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3707 | (const_int 0))) |
9ebbca7d | 3708 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 3709 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3710 | "@ |
3711 | {sl|slw}%I2. %3,%1,%h2 | |
3712 | #" | |
3713 | [(set_attr "type" "delayed_compare") | |
3714 | (set_attr "length" "4,8")]) | |
3715 | ||
3716 | (define_split | |
3717 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3718 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3719 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3720 | (const_int 0))) | |
3721 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3722 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3723 | [(set (match_dup 3) |
3724 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3725 | (set (match_dup 0) | |
3726 | (compare:CC (match_dup 3) | |
3727 | (const_int 0)))] | |
3728 | "") | |
1fd4e8c1 RK |
3729 | |
3730 | (define_insn "" | |
9ebbca7d GK |
3731 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3732 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3733 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3734 | (const_int 0))) |
9ebbca7d | 3735 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3736 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3737 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3738 | "TARGET_POWER" |
1fd4e8c1 RK |
3739 | "@ |
3740 | sle. %0,%1,%2 | |
9ebbca7d GK |
3741 | {sli.|slwi.} %0,%1,%h2 |
3742 | # | |
3743 | #" | |
3744 | [(set_attr "type" "delayed_compare") | |
3745 | (set_attr "length" "4,4,8,8")]) | |
3746 | ||
3747 | (define_split | |
3748 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3749 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3750 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3751 | (const_int 0))) | |
3752 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3753 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3754 | (clobber (match_scratch:SI 4 ""))] | |
3755 | "TARGET_POWER && reload_completed" | |
3756 | [(parallel [(set (match_dup 0) | |
3757 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3758 | (clobber (match_dup 4))]) | |
3759 | (set (match_dup 3) | |
3760 | (compare:CC (match_dup 0) | |
3761 | (const_int 0)))] | |
3762 | "") | |
25c341fa | 3763 | |
ca7f5001 | 3764 | (define_insn "" |
9ebbca7d GK |
3765 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3766 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3767 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3768 | (const_int 0))) |
9ebbca7d | 3769 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3770 | (ashift:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3771 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3772 | "@ |
3773 | {sl|slw}%I2. %0,%1,%h2 | |
3774 | #" | |
3775 | [(set_attr "type" "delayed_compare") | |
3776 | (set_attr "length" "4,8")]) | |
3777 | ||
3778 | (define_split | |
3779 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3780 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3781 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3782 | (const_int 0))) | |
3783 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3784 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3785 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3786 | [(set (match_dup 0) |
3787 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3788 | (set (match_dup 3) | |
3789 | (compare:CC (match_dup 0) | |
3790 | (const_int 0)))] | |
3791 | "") | |
1fd4e8c1 RK |
3792 | |
3793 | (define_insn "" | |
cd2b37d9 RK |
3794 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3795 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3796 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3797 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3798 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3799 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3800 | |
3801 | (define_insn "" | |
9ebbca7d | 3802 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3803 | (compare:CC |
9ebbca7d GK |
3804 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3805 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3806 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3807 | (const_int 0))) |
9ebbca7d | 3808 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3809 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3810 | "@ |
3811 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3812 | #" | |
3813 | [(set_attr "type" "delayed_compare") | |
3814 | (set_attr "length" "4,8")]) | |
3815 | ||
3816 | (define_split | |
3817 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3818 | (compare:CC | |
3819 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3820 | (match_operand:SI 2 "const_int_operand" "")) | |
3821 | (match_operand:SI 3 "mask_operand" "")) | |
3822 | (const_int 0))) | |
3823 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3824 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3825 | [(set (match_dup 4) |
3826 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3827 | (match_dup 3))) | |
3828 | (set (match_dup 0) | |
3829 | (compare:CC (match_dup 4) | |
3830 | (const_int 0)))] | |
3831 | "") | |
1fd4e8c1 RK |
3832 | |
3833 | (define_insn "" | |
9ebbca7d | 3834 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3835 | (compare:CC |
9ebbca7d GK |
3836 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3837 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3838 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3839 | (const_int 0))) |
9ebbca7d | 3840 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3841 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3842 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3843 | "@ |
3844 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3845 | #" | |
3846 | [(set_attr "type" "delayed_compare") | |
3847 | (set_attr "length" "4,8")]) | |
3848 | ||
3849 | (define_split | |
3850 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3851 | (compare:CC | |
3852 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3853 | (match_operand:SI 2 "const_int_operand" "")) | |
3854 | (match_operand:SI 3 "mask_operand" "")) | |
3855 | (const_int 0))) | |
3856 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3857 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3858 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3859 | [(set (match_dup 0) |
3860 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3861 | (set (match_dup 4) | |
3862 | (compare:CC (match_dup 0) | |
3863 | (const_int 0)))] | |
3864 | "") | |
1fd4e8c1 | 3865 | |
ca7f5001 | 3866 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3867 | ;; "sli x,x,0". |
ca7f5001 RK |
3868 | (define_expand "lshrsi3" |
3869 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3870 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3871 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3872 | "" | |
3873 | " | |
3874 | { | |
3875 | if (TARGET_POWER) | |
3876 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3877 | else | |
25c341fa | 3878 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3879 | DONE; |
3880 | }") | |
3881 | ||
3882 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3883 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3884 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3885 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3886 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3887 | "TARGET_POWER" |
1fd4e8c1 RK |
3888 | "@ |
3889 | sre %0,%1,%2 | |
bdf423cb | 3890 | mr %0,%1 |
ca7f5001 RK |
3891 | {s%A2i|s%A2wi} %0,%1,%h2") |
3892 | ||
25c341fa | 3893 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3894 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3895 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3896 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3897 | "! TARGET_POWER" |
bdf423cb MM |
3898 | "@ |
3899 | mr %0,%1 | |
3900 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3901 | |
3902 | (define_insn "" | |
9ebbca7d GK |
3903 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3904 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3905 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3906 | (const_int 0))) |
9ebbca7d GK |
3907 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3908 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3909 | "TARGET_POWER" |
1fd4e8c1 | 3910 | "@ |
29ae5b89 JL |
3911 | sre. %3,%1,%2 |
3912 | mr. %1,%1 | |
9ebbca7d GK |
3913 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
3914 | # | |
3915 | # | |
3916 | #" | |
3917 | [(set_attr "type" "delayed_compare") | |
3918 | (set_attr "length" "4,4,4,8,8,8")]) | |
3919 | ||
3920 | (define_split | |
3921 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3922 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3923 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3924 | (const_int 0))) | |
3925 | (clobber (match_scratch:SI 3 "")) | |
3926 | (clobber (match_scratch:SI 4 ""))] | |
3927 | "TARGET_POWER && reload_completed" | |
3928 | [(parallel [(set (match_dup 3) | |
3929 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3930 | (clobber (match_dup 4))]) | |
3931 | (set (match_dup 0) | |
3932 | (compare:CC (match_dup 3) | |
3933 | (const_int 0)))] | |
3934 | "") | |
ca7f5001 RK |
3935 | |
3936 | (define_insn "" | |
9ebbca7d GK |
3937 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3938 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3939 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 3940 | (const_int 0))) |
9ebbca7d | 3941 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
4b8a63d6 | 3942 | "! TARGET_POWER && TARGET_32BIT" |
bdf423cb MM |
3943 | "@ |
3944 | mr. %1,%1 | |
9ebbca7d GK |
3945 | {sr|srw}%I2. %3,%1,%h2 |
3946 | # | |
3947 | #" | |
3948 | [(set_attr "type" "delayed_compare") | |
3949 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 3950 | |
9ebbca7d GK |
3951 | (define_split |
3952 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3953 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3954 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3955 | (const_int 0))) | |
3956 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3957 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3958 | [(set (match_dup 3) |
3959 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3960 | (set (match_dup 0) | |
3961 | (compare:CC (match_dup 3) | |
3962 | (const_int 0)))] | |
3963 | "") | |
3964 | ||
3965 | (define_insn "" | |
3966 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
3967 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3968 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3969 | (const_int 0))) |
9ebbca7d | 3970 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 3971 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3972 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 3973 | "TARGET_POWER" |
1fd4e8c1 | 3974 | "@ |
29ae5b89 JL |
3975 | sre. %0,%1,%2 |
3976 | mr. %0,%1 | |
9ebbca7d GK |
3977 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
3978 | # | |
3979 | # | |
3980 | #" | |
3981 | [(set_attr "type" "delayed_compare") | |
3982 | (set_attr "length" "4,4,4,8,8,8")]) | |
3983 | ||
3984 | (define_split | |
3985 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3986 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3987 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3988 | (const_int 0))) | |
3989 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3990 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3991 | (clobber (match_scratch:SI 4 ""))] | |
3992 | "TARGET_POWER && reload_completed" | |
3993 | [(parallel [(set (match_dup 0) | |
3994 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3995 | (clobber (match_dup 4))]) | |
3996 | (set (match_dup 3) | |
3997 | (compare:CC (match_dup 0) | |
3998 | (const_int 0)))] | |
3999 | "") | |
ca7f5001 RK |
4000 | |
4001 | (define_insn "" | |
9ebbca7d GK |
4002 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4003 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4004 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4005 | (const_int 0))) |
9ebbca7d | 4006 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4007 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 4008 | "! TARGET_POWER && TARGET_32BIT" |
29ae5b89 JL |
4009 | "@ |
4010 | mr. %0,%1 | |
9ebbca7d GK |
4011 | {sr|srw}%I2. %0,%1,%h2 |
4012 | # | |
4013 | #" | |
4014 | [(set_attr "type" "delayed_compare") | |
4015 | (set_attr "length" "4,4,8,8")]) | |
4016 | ||
4017 | (define_split | |
4018 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4019 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4020 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4021 | (const_int 0))) | |
4022 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4023 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 4024 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
4025 | [(set (match_dup 0) |
4026 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4027 | (set (match_dup 3) | |
4028 | (compare:CC (match_dup 0) | |
4029 | (const_int 0)))] | |
4030 | "") | |
1fd4e8c1 RK |
4031 | |
4032 | (define_insn "" | |
cd2b37d9 RK |
4033 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4034 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4035 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 4036 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 4037 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4038 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4039 | |
4040 | (define_insn "" | |
9ebbca7d | 4041 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4042 | (compare:CC |
9ebbca7d GK |
4043 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4044 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4045 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4046 | (const_int 0))) |
9ebbca7d | 4047 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 4048 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4049 | "@ |
4050 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4051 | #" | |
4052 | [(set_attr "type" "delayed_compare") | |
4053 | (set_attr "length" "4,8")]) | |
4054 | ||
4055 | (define_split | |
4056 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4057 | (compare:CC | |
4058 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4059 | (match_operand:SI 2 "const_int_operand" "")) | |
4060 | (match_operand:SI 3 "mask_operand" "")) | |
4061 | (const_int 0))) | |
4062 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 4063 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4064 | [(set (match_dup 4) |
4065 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4066 | (match_dup 3))) | |
4067 | (set (match_dup 0) | |
4068 | (compare:CC (match_dup 4) | |
4069 | (const_int 0)))] | |
4070 | "") | |
1fd4e8c1 RK |
4071 | |
4072 | (define_insn "" | |
9ebbca7d | 4073 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4074 | (compare:CC |
9ebbca7d GK |
4075 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4076 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4077 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4078 | (const_int 0))) |
9ebbca7d | 4079 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4080 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 4081 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4082 | "@ |
4083 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4084 | #" | |
4085 | [(set_attr "type" "delayed_compare") | |
4086 | (set_attr "length" "4,8")]) | |
4087 | ||
4088 | (define_split | |
4089 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4090 | (compare:CC | |
4091 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4092 | (match_operand:SI 2 "const_int_operand" "")) | |
4093 | (match_operand:SI 3 "mask_operand" "")) | |
4094 | (const_int 0))) | |
4095 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4096 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4097 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4098 | [(set (match_dup 0) |
4099 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4100 | (set (match_dup 4) | |
4101 | (compare:CC (match_dup 0) | |
4102 | (const_int 0)))] | |
4103 | "") | |
1fd4e8c1 RK |
4104 | |
4105 | (define_insn "" | |
cd2b37d9 | 4106 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4107 | (zero_extend:SI |
4108 | (subreg:QI | |
cd2b37d9 | 4109 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4110 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4111 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4112 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4113 | |
4114 | (define_insn "" | |
9ebbca7d | 4115 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4116 | (compare:CC |
4117 | (zero_extend:SI | |
4118 | (subreg:QI | |
9ebbca7d GK |
4119 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4120 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4121 | (const_int 0))) |
9ebbca7d | 4122 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4123 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4124 | "@ |
4125 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4126 | #" | |
4127 | [(set_attr "type" "delayed_compare") | |
4128 | (set_attr "length" "4,8")]) | |
4129 | ||
4130 | (define_split | |
4131 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4132 | (compare:CC | |
4133 | (zero_extend:SI | |
4134 | (subreg:QI | |
4135 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4136 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4137 | (const_int 0))) | |
4138 | (clobber (match_scratch:SI 3 ""))] | |
4139 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4140 | [(set (match_dup 3) | |
4141 | (zero_extend:SI (subreg:QI | |
4142 | (lshiftrt:SI (match_dup 1) | |
4143 | (match_dup 2)) 0))) | |
4144 | (set (match_dup 0) | |
4145 | (compare:CC (match_dup 3) | |
4146 | (const_int 0)))] | |
4147 | "") | |
1fd4e8c1 RK |
4148 | |
4149 | (define_insn "" | |
9ebbca7d | 4150 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4151 | (compare:CC |
4152 | (zero_extend:SI | |
4153 | (subreg:QI | |
9ebbca7d GK |
4154 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4155 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4156 | (const_int 0))) |
9ebbca7d | 4157 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4158 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4159 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4160 | "@ |
4161 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4162 | #" | |
4163 | [(set_attr "type" "delayed_compare") | |
4164 | (set_attr "length" "4,8")]) | |
4165 | ||
4166 | (define_split | |
4167 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4168 | (compare:CC | |
4169 | (zero_extend:SI | |
4170 | (subreg:QI | |
4171 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4172 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4173 | (const_int 0))) | |
4174 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4175 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4176 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4177 | [(set (match_dup 0) | |
4178 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4179 | (set (match_dup 3) | |
4180 | (compare:CC (match_dup 0) | |
4181 | (const_int 0)))] | |
4182 | "") | |
1fd4e8c1 RK |
4183 | |
4184 | (define_insn "" | |
cd2b37d9 | 4185 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4186 | (zero_extend:SI |
4187 | (subreg:HI | |
cd2b37d9 | 4188 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4189 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4190 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4191 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4192 | |
4193 | (define_insn "" | |
9ebbca7d | 4194 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4195 | (compare:CC |
4196 | (zero_extend:SI | |
4197 | (subreg:HI | |
9ebbca7d GK |
4198 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4199 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4200 | (const_int 0))) |
9ebbca7d | 4201 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4202 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4203 | "@ |
4204 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4205 | #" | |
4206 | [(set_attr "type" "delayed_compare") | |
4207 | (set_attr "length" "4,8")]) | |
4208 | ||
4209 | (define_split | |
4210 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4211 | (compare:CC | |
4212 | (zero_extend:SI | |
4213 | (subreg:HI | |
4214 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4215 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4216 | (const_int 0))) | |
4217 | (clobber (match_scratch:SI 3 ""))] | |
4218 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4219 | [(set (match_dup 3) | |
4220 | (zero_extend:SI (subreg:HI | |
4221 | (lshiftrt:SI (match_dup 1) | |
4222 | (match_dup 2)) 0))) | |
4223 | (set (match_dup 0) | |
4224 | (compare:CC (match_dup 3) | |
4225 | (const_int 0)))] | |
4226 | "") | |
1fd4e8c1 RK |
4227 | |
4228 | (define_insn "" | |
9ebbca7d | 4229 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4230 | (compare:CC |
4231 | (zero_extend:SI | |
4232 | (subreg:HI | |
9ebbca7d GK |
4233 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4234 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4235 | (const_int 0))) |
9ebbca7d | 4236 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4237 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4238 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4239 | "@ |
4240 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4241 | #" | |
4242 | [(set_attr "type" "delayed_compare") | |
4243 | (set_attr "length" "4,8")]) | |
4244 | ||
4245 | (define_split | |
4246 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4247 | (compare:CC | |
4248 | (zero_extend:SI | |
4249 | (subreg:HI | |
4250 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4251 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4252 | (const_int 0))) | |
4253 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4254 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4255 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4256 | [(set (match_dup 0) | |
4257 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4258 | (set (match_dup 3) | |
4259 | (compare:CC (match_dup 0) | |
4260 | (const_int 0)))] | |
4261 | "") | |
1fd4e8c1 RK |
4262 | |
4263 | (define_insn "" | |
cd2b37d9 | 4264 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4265 | (const_int 1) |
cd2b37d9 RK |
4266 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4267 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4268 | (const_int 31)))] |
ca7f5001 | 4269 | "TARGET_POWER" |
1fd4e8c1 RK |
4270 | "rrib %0,%1,%2") |
4271 | ||
4272 | (define_insn "" | |
cd2b37d9 | 4273 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4274 | (const_int 1) |
cd2b37d9 RK |
4275 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4276 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4277 | (const_int 31)))] |
ca7f5001 | 4278 | "TARGET_POWER" |
1fd4e8c1 RK |
4279 | "rrib %0,%1,%2") |
4280 | ||
4281 | (define_insn "" | |
cd2b37d9 | 4282 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4283 | (const_int 1) |
cd2b37d9 RK |
4284 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4285 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4286 | (const_int 1) |
4287 | (const_int 0)))] | |
ca7f5001 | 4288 | "TARGET_POWER" |
1fd4e8c1 RK |
4289 | "rrib %0,%1,%2") |
4290 | ||
ca7f5001 RK |
4291 | (define_expand "ashrsi3" |
4292 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4293 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4294 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4295 | "" | |
4296 | " | |
4297 | { | |
4298 | if (TARGET_POWER) | |
4299 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4300 | else | |
25c341fa | 4301 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4302 | DONE; |
4303 | }") | |
4304 | ||
4305 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4306 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4307 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4308 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4309 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4310 | "TARGET_POWER" |
1fd4e8c1 RK |
4311 | "@ |
4312 | srea %0,%1,%2 | |
ca7f5001 RK |
4313 | {srai|srawi} %0,%1,%h2") |
4314 | ||
25c341fa | 4315 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4316 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4317 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4318 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4319 | "! TARGET_POWER" |
d904e9ed | 4320 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4321 | |
4322 | (define_insn "" | |
9ebbca7d GK |
4323 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4324 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4325 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4326 | (const_int 0))) |
9ebbca7d GK |
4327 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4328 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4329 | "TARGET_POWER" |
1fd4e8c1 RK |
4330 | "@ |
4331 | srea. %3,%1,%2 | |
9ebbca7d GK |
4332 | {srai.|srawi.} %3,%1,%h2 |
4333 | # | |
4334 | #" | |
4335 | [(set_attr "type" "delayed_compare") | |
4336 | (set_attr "length" "4,4,8,8")]) | |
4337 | ||
4338 | (define_split | |
4339 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4340 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4341 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4342 | (const_int 0))) | |
4343 | (clobber (match_scratch:SI 3 "")) | |
4344 | (clobber (match_scratch:SI 4 ""))] | |
4345 | "TARGET_POWER && reload_completed" | |
4346 | [(parallel [(set (match_dup 3) | |
4347 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4348 | (clobber (match_dup 4))]) | |
4349 | (set (match_dup 0) | |
4350 | (compare:CC (match_dup 3) | |
4351 | (const_int 0)))] | |
4352 | "") | |
ca7f5001 RK |
4353 | |
4354 | (define_insn "" | |
9ebbca7d GK |
4355 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4356 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4357 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4358 | (const_int 0))) |
9ebbca7d | 4359 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4360 | "! TARGET_POWER" |
9ebbca7d GK |
4361 | "@ |
4362 | {sra|sraw}%I2. %3,%1,%h2 | |
4363 | #" | |
4364 | [(set_attr "type" "delayed_compare") | |
4365 | (set_attr "length" "4,8")]) | |
4366 | ||
4367 | (define_split | |
4368 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4369 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4370 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4371 | (const_int 0))) | |
4372 | (clobber (match_scratch:SI 3 ""))] | |
4373 | "! TARGET_POWER && reload_completed" | |
4374 | [(set (match_dup 3) | |
4375 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4376 | (set (match_dup 0) | |
4377 | (compare:CC (match_dup 3) | |
4378 | (const_int 0)))] | |
4379 | "") | |
1fd4e8c1 RK |
4380 | |
4381 | (define_insn "" | |
9ebbca7d GK |
4382 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4383 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4384 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4385 | (const_int 0))) |
9ebbca7d | 4386 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4387 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4388 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4389 | "TARGET_POWER" |
1fd4e8c1 RK |
4390 | "@ |
4391 | srea. %0,%1,%2 | |
9ebbca7d GK |
4392 | {srai.|srawi.} %0,%1,%h2 |
4393 | # | |
4394 | #" | |
4395 | [(set_attr "type" "delayed_compare") | |
4396 | (set_attr "length" "4,4,8,8")]) | |
4397 | ||
4398 | (define_split | |
4399 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4400 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4401 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4402 | (const_int 0))) | |
4403 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4404 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4405 | (clobber (match_scratch:SI 4 ""))] | |
4406 | "TARGET_POWER && reload_completed" | |
4407 | [(parallel [(set (match_dup 0) | |
4408 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4409 | (clobber (match_dup 4))]) | |
4410 | (set (match_dup 3) | |
4411 | (compare:CC (match_dup 0) | |
4412 | (const_int 0)))] | |
4413 | "") | |
1fd4e8c1 | 4414 | |
ca7f5001 | 4415 | (define_insn "" |
9ebbca7d GK |
4416 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4417 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4418 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4419 | (const_int 0))) |
9ebbca7d | 4420 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4421 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4422 | "! TARGET_POWER" |
9ebbca7d GK |
4423 | "@ |
4424 | {sra|sraw}%I2. %0,%1,%h2 | |
4425 | #" | |
4426 | [(set_attr "type" "delayed_compare") | |
4427 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4428 | \f |
9ebbca7d GK |
4429 | (define_split |
4430 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4431 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4432 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4433 | (const_int 0))) | |
4434 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4435 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4436 | "! TARGET_POWER && reload_completed" | |
4437 | [(set (match_dup 0) | |
4438 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4439 | (set (match_dup 3) | |
4440 | (compare:CC (match_dup 0) | |
4441 | (const_int 0)))] | |
4442 | "") | |
4443 | ||
1fd4e8c1 RK |
4444 | ;; Floating-point insns, excluding normal data motion. |
4445 | ;; | |
ca7f5001 RK |
4446 | ;; PowerPC has a full set of single-precision floating point instructions. |
4447 | ;; | |
4448 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4449 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4450 | ;; The only conversions we will do will be when storing to memory. In that | |
4451 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4452 | ;; |
4453 | ;; Note that when we store into a single-precision memory location, we need to | |
4454 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4455 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4456 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4457 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4458 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4459 | ||
11ac38b2 DE |
4460 | (define_insn_and_split "extendsfdf2" |
4461 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") | |
4462 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))] | |
a3170dc6 | 4463 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
11ac38b2 DE |
4464 | "@ |
4465 | # | |
4466 | fmr %0,%1" | |
4467 | "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" | |
4468 | [(const_int 0)] | |
5c30aff8 | 4469 | { |
11ac38b2 DE |
4470 | emit_note (NOTE_INSN_DELETED); |
4471 | DONE; | |
4472 | } | |
e8112008 | 4473 | [(set_attr "type" "fp")]) |
1fd4e8c1 RK |
4474 | |
4475 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
4476 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4477 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4478 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 4479 | "frsp %0,%1" |
1fd4e8c1 RK |
4480 | [(set_attr "type" "fp")]) |
4481 | ||
455350f4 RK |
4482 | (define_insn "aux_truncdfsf2" |
4483 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
615158e2 | 4484 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] |
a3170dc6 | 4485 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
4486 | "frsp %0,%1" |
4487 | [(set_attr "type" "fp")]) | |
4488 | ||
a3170dc6 AH |
4489 | (define_expand "negsf2" |
4490 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4491 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4492 | "TARGET_HARD_FLOAT" | |
4493 | "") | |
4494 | ||
4495 | (define_insn "*negsf2" | |
cd2b37d9 RK |
4496 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4497 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4498 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4499 | "fneg %0,%1" |
4500 | [(set_attr "type" "fp")]) | |
4501 | ||
a3170dc6 AH |
4502 | (define_expand "abssf2" |
4503 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4504 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4505 | "TARGET_HARD_FLOAT" | |
4506 | "") | |
4507 | ||
4508 | (define_insn "*abssf2" | |
cd2b37d9 RK |
4509 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4510 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4511 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4512 | "fabs %0,%1" |
4513 | [(set_attr "type" "fp")]) | |
4514 | ||
4515 | (define_insn "" | |
cd2b37d9 RK |
4516 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4517 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4518 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4519 | "fnabs %0,%1" |
4520 | [(set_attr "type" "fp")]) | |
4521 | ||
ca7f5001 RK |
4522 | (define_expand "addsf3" |
4523 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4524 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4525 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4526 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4527 | "") |
4528 | ||
4529 | (define_insn "" | |
cd2b37d9 RK |
4530 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4531 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4532 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4533 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4534 | "fadds %0,%1,%2" |
ca7f5001 RK |
4535 | [(set_attr "type" "fp")]) |
4536 | ||
4537 | (define_insn "" | |
4538 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4539 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4540 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4541 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4542 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4543 | [(set_attr "type" "fp")]) |
4544 | ||
4545 | (define_expand "subsf3" | |
4546 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4547 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4548 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4549 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4550 | "") |
4551 | ||
4552 | (define_insn "" | |
4553 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4554 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4555 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4556 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4557 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4558 | [(set_attr "type" "fp")]) |
4559 | ||
ca7f5001 | 4560 | (define_insn "" |
cd2b37d9 RK |
4561 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4562 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4563 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4564 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4565 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4566 | [(set_attr "type" "fp")]) |
4567 | ||
4568 | (define_expand "mulsf3" | |
4569 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4570 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4571 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4572 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4573 | "") |
4574 | ||
4575 | (define_insn "" | |
4576 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4577 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4578 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4579 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4580 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4581 | [(set_attr "type" "fp")]) |
4582 | ||
ca7f5001 | 4583 | (define_insn "" |
cd2b37d9 RK |
4584 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4585 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4586 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4587 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4588 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4589 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4590 | |
ca7f5001 RK |
4591 | (define_expand "divsf3" |
4592 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4593 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4594 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4595 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4596 | "") |
4597 | ||
4598 | (define_insn "" | |
cd2b37d9 RK |
4599 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4600 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4601 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4602 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4603 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4604 | [(set_attr "type" "sdiv")]) |
4605 | ||
4606 | (define_insn "" | |
4607 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4608 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4609 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4610 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4611 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4612 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4613 | |
4614 | (define_insn "" | |
cd2b37d9 RK |
4615 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4616 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4617 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4618 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4619 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4620 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4621 | [(set_attr "type" "fp")]) |
4622 | ||
4623 | (define_insn "" | |
4624 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4625 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4626 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4627 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4628 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4629 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4630 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4631 | |
4632 | (define_insn "" | |
cd2b37d9 RK |
4633 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4634 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4635 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4636 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4637 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4638 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4639 | [(set_attr "type" "fp")]) |
4640 | ||
4641 | (define_insn "" | |
4642 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4643 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4644 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4645 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4646 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4647 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4648 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4649 | |
4650 | (define_insn "" | |
cd2b37d9 RK |
4651 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4652 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4653 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4654 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4655 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4656 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4657 | "fnmadds %0,%1,%2,%3" | |
4658 | [(set_attr "type" "fp")]) | |
4659 | ||
4660 | (define_insn "" | |
4661 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4662 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4663 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4664 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4665 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4666 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4667 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4668 | [(set_attr "type" "fp")]) |
4669 | ||
4670 | (define_insn "" | |
4671 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4672 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4673 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4674 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4675 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4676 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4677 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4678 | |
16823694 GK |
4679 | (define_insn "" |
4680 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4681 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4682 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4683 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4684 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4685 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4686 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4687 | [(set_attr "type" "dmul")]) | |
4688 | ||
1fd4e8c1 | 4689 | (define_insn "" |
cd2b37d9 RK |
4690 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4691 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4692 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4693 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4694 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4695 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4696 | "fnmsubs %0,%1,%2,%3" | |
4697 | [(set_attr "type" "fp")]) | |
4698 | ||
4699 | (define_insn "" | |
4700 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4701 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4702 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4703 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4704 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4705 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4706 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4707 | [(set_attr "type" "fp")]) |
4708 | ||
4709 | (define_insn "" | |
4710 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4711 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4712 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4713 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4714 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4715 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4716 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4717 | |
16823694 GK |
4718 | (define_insn "" |
4719 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4720 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4721 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4722 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4723 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4724 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4725 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4726 | [(set_attr "type" "fp")]) | |
4727 | ||
ca7f5001 RK |
4728 | (define_expand "sqrtsf2" |
4729 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4730 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 4731 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4732 | "") |
4733 | ||
4734 | (define_insn "" | |
4735 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4736 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4737 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4738 | "fsqrts %0,%1" |
4739 | [(set_attr "type" "ssqrt")]) | |
4740 | ||
4741 | (define_insn "" | |
4742 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4743 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4744 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4745 | "fsqrt %0,%1" |
4746 | [(set_attr "type" "dsqrt")]) | |
4747 | ||
94d7001a RK |
4748 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4749 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4750 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4751 | ;; combine. |
4752 | (define_expand "maxsf3" | |
8e871c05 | 4753 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4754 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4755 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4756 | (match_dup 1) |
4757 | (match_dup 2)))] | |
a3170dc6 | 4758 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4759 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 4760 | |
8e871c05 | 4761 | (define_expand "minsf3" |
50a0b056 GK |
4762 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4763 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4764 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4765 | (match_dup 2) | |
4766 | (match_dup 1)))] | |
a3170dc6 | 4767 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4768 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4769 | |
8e871c05 RK |
4770 | (define_split |
4771 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4772 | (match_operator:SF 3 "min_max_operator" |
4773 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4774 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
a3170dc6 | 4775 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 GK |
4776 | [(const_int 0)] |
4777 | " | |
6ae08853 | 4778 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
4779 | operands[1], operands[2]); |
4780 | DONE; | |
4781 | }") | |
2f607b94 | 4782 | |
a3170dc6 AH |
4783 | (define_expand "movsicc" |
4784 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4785 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
4786 | (match_operand:SI 2 "gpc_reg_operand" "") | |
4787 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
4788 | "TARGET_ISEL" | |
4789 | " | |
4790 | { | |
4791 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
4792 | DONE; | |
4793 | else | |
4794 | FAIL; | |
4795 | }") | |
4796 | ||
4797 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
4798 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
4799 | ;; because we may switch the operands and rB may end up being rA. | |
4800 | ;; | |
4801 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
4802 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
4803 | ;; change the mode underneath our feet and then gets confused trying | |
4804 | ;; to reload the value. | |
4805 | (define_insn "isel_signed" | |
4806 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4807 | (if_then_else:SI | |
4808 | (match_operator 1 "comparison_operator" | |
4809 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
4810 | (const_int 0)]) | |
4811 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4812 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4813 | "TARGET_ISEL" | |
4814 | "* | |
4815 | { return output_isel (operands); }" | |
4816 | [(set_attr "length" "4")]) | |
4817 | ||
4818 | (define_insn "isel_unsigned" | |
4819 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4820 | (if_then_else:SI | |
4821 | (match_operator 1 "comparison_operator" | |
4822 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
4823 | (const_int 0)]) | |
4824 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4825 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4826 | "TARGET_ISEL" | |
4827 | "* | |
4828 | { return output_isel (operands); }" | |
4829 | [(set_attr "length" "4")]) | |
4830 | ||
94d7001a | 4831 | (define_expand "movsfcc" |
0ad91047 | 4832 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4833 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4834 | (match_operand:SF 2 "gpc_reg_operand" "") |
4835 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4836 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4837 | " |
4838 | { | |
50a0b056 GK |
4839 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4840 | DONE; | |
94d7001a | 4841 | else |
50a0b056 | 4842 | FAIL; |
94d7001a | 4843 | }") |
d56d506a | 4844 | |
50a0b056 | 4845 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4846 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4847 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4848 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4849 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4850 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4851 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4852 | "fsel %0,%1,%2,%3" |
4853 | [(set_attr "type" "fp")]) | |
2f607b94 | 4854 | |
50a0b056 | 4855 | (define_insn "*fseldfsf4" |
94d7001a RK |
4856 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4857 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4858 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4859 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4860 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4861 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4862 | "fsel %0,%1,%2,%3" |
4863 | [(set_attr "type" "fp")]) | |
d56d506a | 4864 | |
1fd4e8c1 | 4865 | (define_insn "negdf2" |
cd2b37d9 RK |
4866 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4867 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4868 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4869 | "fneg %0,%1" |
4870 | [(set_attr "type" "fp")]) | |
4871 | ||
4872 | (define_insn "absdf2" | |
cd2b37d9 RK |
4873 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4874 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4875 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4876 | "fabs %0,%1" |
4877 | [(set_attr "type" "fp")]) | |
4878 | ||
4879 | (define_insn "" | |
cd2b37d9 RK |
4880 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4881 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4882 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4883 | "fnabs %0,%1" |
4884 | [(set_attr "type" "fp")]) | |
4885 | ||
4886 | (define_insn "adddf3" | |
cd2b37d9 RK |
4887 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4888 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4889 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4890 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4891 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4892 | [(set_attr "type" "fp")]) |
4893 | ||
4894 | (define_insn "subdf3" | |
cd2b37d9 RK |
4895 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4896 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4897 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4898 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4899 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4900 | [(set_attr "type" "fp")]) |
4901 | ||
4902 | (define_insn "muldf3" | |
cd2b37d9 RK |
4903 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4904 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4905 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4906 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4907 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4908 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4909 | |
4910 | (define_insn "divdf3" | |
cd2b37d9 RK |
4911 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4912 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4913 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4914 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4915 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4916 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4917 | |
4918 | (define_insn "" | |
cd2b37d9 RK |
4919 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4920 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4921 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4922 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4923 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4924 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4925 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4926 | |
4927 | (define_insn "" | |
cd2b37d9 RK |
4928 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4929 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4930 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4931 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4932 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4933 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4934 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4935 | |
4936 | (define_insn "" | |
cd2b37d9 RK |
4937 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4938 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4939 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4940 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4941 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4942 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4943 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4944 | [(set_attr "type" "dmul")]) | |
4945 | ||
4946 | (define_insn "" | |
4947 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4948 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
4949 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4950 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4951 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4952 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 4953 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 4954 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4955 | |
4956 | (define_insn "" | |
cd2b37d9 RK |
4957 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4958 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4959 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4960 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4961 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4962 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4963 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4964 | [(set_attr "type" "dmul")]) | |
4965 | ||
4966 | (define_insn "" | |
4967 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4968 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
4969 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4970 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
6ae08853 | 4971 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
16823694 | 4972 | && ! HONOR_SIGNED_ZEROS (DFmode)" |
ca7f5001 | 4973 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 4974 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
4975 | |
4976 | (define_insn "sqrtdf2" | |
4977 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4978 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4979 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4980 | "fsqrt %0,%1" |
4981 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 4982 | |
50a0b056 | 4983 | ;; The conditional move instructions allow us to perform max and min |
6ae08853 | 4984 | ;; operations even when |
b77dfefc | 4985 | |
8e871c05 | 4986 | (define_expand "maxdf3" |
8e871c05 | 4987 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4988 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
4989 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4990 | (match_dup 1) |
4991 | (match_dup 2)))] | |
a3170dc6 | 4992 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4993 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 4994 | |
8e871c05 | 4995 | (define_expand "mindf3" |
50a0b056 GK |
4996 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4997 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
4998 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
4999 | (match_dup 2) | |
5000 | (match_dup 1)))] | |
a3170dc6 | 5001 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 5002 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5003 | |
8e871c05 RK |
5004 | (define_split |
5005 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5006 | (match_operator:DF 3 "min_max_operator" |
5007 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5008 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
a3170dc6 | 5009 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 GK |
5010 | [(const_int 0)] |
5011 | " | |
6ae08853 | 5012 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
5013 | operands[1], operands[2]); |
5014 | DONE; | |
5015 | }") | |
b77dfefc | 5016 | |
94d7001a | 5017 | (define_expand "movdfcc" |
0ad91047 | 5018 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5019 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5020 | (match_operand:DF 2 "gpc_reg_operand" "") |
5021 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 5022 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
5023 | " |
5024 | { | |
50a0b056 GK |
5025 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5026 | DONE; | |
94d7001a | 5027 | else |
50a0b056 | 5028 | FAIL; |
94d7001a | 5029 | }") |
d56d506a | 5030 | |
50a0b056 | 5031 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5032 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5033 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5034 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5035 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5036 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5037 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
5038 | "fsel %0,%1,%2,%3" |
5039 | [(set_attr "type" "fp")]) | |
d56d506a | 5040 | |
50a0b056 | 5041 | (define_insn "*fselsfdf4" |
94d7001a RK |
5042 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5043 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5044 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5045 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5046 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5047 | "TARGET_PPC_GFXOPT" | |
5048 | "fsel %0,%1,%2,%3" | |
5049 | [(set_attr "type" "fp")]) | |
1fd4e8c1 | 5050 | \f |
d095928f AH |
5051 | ;; Conversions to and from floating-point. |
5052 | ||
5053 | (define_expand "fixuns_truncsfsi2" | |
5054 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5055 | (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5056 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5057 | "") | |
5058 | ||
5059 | (define_expand "fix_truncsfsi2" | |
5060 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5061 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5062 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5063 | "") | |
5064 | ||
9ebbca7d GK |
5065 | ; For each of these conversions, there is a define_expand, a define_insn |
5066 | ; with a '#' template, and a define_split (with C code). The idea is | |
5067 | ; to allow constant folding with the template of the define_insn, | |
5068 | ; then to have the insns split later (between sched1 and final). | |
5069 | ||
1fd4e8c1 | 5070 | (define_expand "floatsidf2" |
802a0058 MM |
5071 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5072 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5073 | (use (match_dup 2)) | |
5074 | (use (match_dup 3)) | |
208c89ce | 5075 | (clobber (match_dup 4)) |
a7df97e6 | 5076 | (clobber (match_dup 5)) |
9ebbca7d | 5077 | (clobber (match_dup 6))])] |
a3170dc6 | 5078 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5079 | " |
5080 | { | |
05d49501 AM |
5081 | if (TARGET_POWERPC64) |
5082 | { | |
5083 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5084 | rtx t1 = gen_reg_rtx (DImode); | |
5085 | rtx t2 = gen_reg_rtx (DImode); | |
5086 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
5087 | DONE; | |
5088 | } | |
5089 | ||
802a0058 | 5090 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5091 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5092 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5093 | operands[5] = gen_reg_rtx (DFmode); | |
5094 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5095 | }") |
5096 | ||
802a0058 MM |
5097 | (define_insn "*floatsidf2_internal" |
5098 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5099 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5100 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5101 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5102 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5103 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5104 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5105 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5106 | "#" |
a7df97e6 | 5107 | [(set_attr "length" "24")]) |
802a0058 MM |
5108 | |
5109 | (define_split | |
dbe3df29 | 5110 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5111 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5112 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5113 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5114 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5115 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5116 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
a3170dc6 | 5117 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5118 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5119 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5120 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5121 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5122 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5123 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5124 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5125 | " |
5126 | { | |
9ebbca7d GK |
5127 | rtx lowword, highword; |
5128 | if (GET_CODE (operands[4]) != MEM) | |
5129 | abort(); | |
5130 | highword = XEXP (operands[4], 0); | |
5131 | lowword = plus_constant (highword, 4); | |
5132 | if (! WORDS_BIG_ENDIAN) | |
5133 | { | |
5134 | rtx tmp; | |
5135 | tmp = highword; highword = lowword; lowword = tmp; | |
5136 | } | |
5137 | ||
6ae08853 | 5138 | emit_insn (gen_xorsi3 (operands[6], operands[1], |
9ebbca7d GK |
5139 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); |
5140 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5141 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5142 | emit_move_insn (operands[5], operands[4]); | |
5143 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5144 | DONE; | |
208c89ce | 5145 | }") |
802a0058 | 5146 | |
a3170dc6 AH |
5147 | (define_expand "floatunssisf2" |
5148 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5149 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5150 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5151 | "") | |
5152 | ||
802a0058 MM |
5153 | (define_expand "floatunssidf2" |
5154 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5155 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5156 | (use (match_dup 2)) | |
5157 | (use (match_dup 3)) | |
a7df97e6 | 5158 | (clobber (match_dup 4)) |
9ebbca7d | 5159 | (clobber (match_dup 5))])] |
a3170dc6 | 5160 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5161 | " |
5162 | { | |
05d49501 AM |
5163 | if (TARGET_POWERPC64) |
5164 | { | |
5165 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5166 | rtx t1 = gen_reg_rtx (DImode); | |
5167 | rtx t2 = gen_reg_rtx (DImode); | |
5168 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5169 | t1, t2)); | |
5170 | DONE; | |
5171 | } | |
5172 | ||
802a0058 | 5173 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5174 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5175 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5176 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5177 | }") |
5178 | ||
802a0058 MM |
5179 | (define_insn "*floatunssidf2_internal" |
5180 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5181 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5182 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5183 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5184 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5185 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5186 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5187 | "#" |
a7df97e6 | 5188 | [(set_attr "length" "20")]) |
802a0058 MM |
5189 | |
5190 | (define_split | |
5191 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5192 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5193 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5194 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5195 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5196 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
a3170dc6 | 5197 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5198 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5199 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5200 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5201 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5202 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5203 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5204 | " | |
802a0058 | 5205 | { |
9ebbca7d GK |
5206 | rtx lowword, highword; |
5207 | if (GET_CODE (operands[4]) != MEM) | |
5208 | abort(); | |
5209 | highword = XEXP (operands[4], 0); | |
5210 | lowword = plus_constant (highword, 4); | |
5211 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5212 | { |
9ebbca7d GK |
5213 | rtx tmp; |
5214 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5215 | } |
802a0058 | 5216 | |
9ebbca7d GK |
5217 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5218 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5219 | emit_move_insn (operands[5], operands[4]); | |
5220 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5221 | DONE; | |
5222 | }") | |
1fd4e8c1 | 5223 | |
1fd4e8c1 | 5224 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5225 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5226 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5227 | (clobber (match_dup 2)) | |
9ebbca7d | 5228 | (clobber (match_dup 3))])] |
a3170dc6 | 5229 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5230 | " |
5231 | { | |
802a0058 | 5232 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5233 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5234 | }") |
5235 | ||
802a0058 MM |
5236 | (define_insn "*fix_truncdfsi2_internal" |
5237 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5238 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5239 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5240 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5241 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5242 | "#" |
9ebbca7d | 5243 | [(set_attr "length" "16")]) |
802a0058 MM |
5244 | |
5245 | (define_split | |
5246 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5247 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5248 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5249 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
a3170dc6 | 5250 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d | 5251 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5252 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5253 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5254 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5255 | " | |
802a0058 | 5256 | { |
9ebbca7d GK |
5257 | rtx lowword; |
5258 | if (GET_CODE (operands[3]) != MEM) | |
5259 | abort(); | |
5260 | lowword = XEXP (operands[3], 0); | |
5261 | if (WORDS_BIG_ENDIAN) | |
5262 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5263 | |
9ebbca7d GK |
5264 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5265 | emit_move_insn (operands[3], operands[2]); | |
5266 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5267 | DONE; | |
5268 | }") | |
802a0058 | 5269 | |
615158e2 | 5270 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) |
9ebbca7d GK |
5271 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) |
5272 | ; because the first makes it clear that operand 0 is not live | |
5273 | ; before the instruction. | |
5274 | (define_insn "fctiwz" | |
61c07d3c | 5275 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
615158e2 JJ |
5276 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] |
5277 | UNSPEC_FCTIWZ))] | |
a3170dc6 | 5278 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5279 | "{fcirz|fctiwz} %0,%1" |
5280 | [(set_attr "type" "fp")]) | |
5281 | ||
a3170dc6 AH |
5282 | (define_expand "floatsisf2" |
5283 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5284 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5285 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5286 | "") | |
5287 | ||
a473029f RK |
5288 | (define_insn "floatdidf2" |
5289 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5290 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5291 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5292 | "fcfid %0,%1" |
5293 | [(set_attr "type" "fp")]) | |
5294 | ||
05d49501 AM |
5295 | (define_insn_and_split "floatsidf_ppc64" |
5296 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5297 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5298 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5299 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5300 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5301 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5302 | "#" |
ecb62ae7 | 5303 | "&& 1" |
05d49501 AM |
5304 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) |
5305 | (set (match_dup 2) (match_dup 3)) | |
5306 | (set (match_dup 4) (match_dup 2)) | |
5307 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5308 | "") | |
5309 | ||
5310 | (define_insn_and_split "floatunssidf_ppc64" | |
5311 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5312 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5313 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5314 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5315 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5316 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5317 | "#" |
ecb62ae7 | 5318 | "&& 1" |
05d49501 AM |
5319 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) |
5320 | (set (match_dup 2) (match_dup 3)) | |
5321 | (set (match_dup 4) (match_dup 2)) | |
5322 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5323 | "") | |
5324 | ||
a473029f | 5325 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5326 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5327 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5328 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5329 | "fctidz %0,%1" |
5330 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5331 | |
678b7733 AM |
5332 | (define_expand "floatdisf2" |
5333 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5334 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
683bdff7 | 5335 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5336 | " |
5337 | { | |
5338 | if (!flag_unsafe_math_optimizations) | |
5339 | { | |
5340 | rtx label = gen_label_rtx (); | |
5341 | emit_insn (gen_floatdisf2_internal2 (operands[1], label)); | |
5342 | emit_label (label); | |
5343 | } | |
5344 | emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1])); | |
5345 | DONE; | |
5346 | }") | |
5347 | ||
5348 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
5349 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
5350 | ;; from double rounding. | |
5351 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 5352 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 5353 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 5354 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 5355 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
5356 | "#" |
5357 | "&& reload_completed" | |
5358 | [(set (match_dup 2) | |
5359 | (float:DF (match_dup 1))) | |
5360 | (set (match_dup 0) | |
5361 | (float_truncate:SF (match_dup 2)))] | |
5362 | "") | |
678b7733 AM |
5363 | |
5364 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 5365 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
5366 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
5367 | ;; rounding position. | |
5368 | (define_expand "floatdisf2_internal2" | |
42a6388c AM |
5369 | [(parallel [(set (match_dup 4) |
5370 | (compare:CC (and:DI (match_operand:DI 0 "" "") | |
5371 | (const_int 2047)) | |
5372 | (const_int 0))) | |
5373 | (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047))) | |
5374 | (clobber (match_scratch:CC 7 ""))]) | |
678b7733 AM |
5375 | (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53))) |
5376 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) | |
5377 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
5378 | (label_ref (match_operand:DI 1 "" "")) | |
5379 | (pc))) | |
5380 | (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2))) | |
5381 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
5382 | (label_ref (match_dup 1)) | |
5383 | (pc))) | |
5384 | (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2))) | |
5385 | (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))] | |
683bdff7 | 5386 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5387 | " |
5388 | { | |
5389 | operands[2] = gen_reg_rtx (DImode); | |
5390 | operands[3] = gen_reg_rtx (DImode); | |
5391 | operands[4] = gen_reg_rtx (CCmode); | |
5392 | operands[5] = gen_reg_rtx (CCUNSmode); | |
5393 | }") | |
1fd4e8c1 RK |
5394 | \f |
5395 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5396 | ;; of instructions. The & constraints are to prevent the register |
5397 | ;; allocator from allocating registers that overlap with the inputs | |
5398 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5399 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5400 | |
266eb58a | 5401 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5402 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5403 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5404 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5405 | "! TARGET_POWERPC64" |
0f645302 MM |
5406 | "* |
5407 | { | |
5408 | if (WORDS_BIG_ENDIAN) | |
5409 | return (GET_CODE (operands[2])) != CONST_INT | |
5410 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5411 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5412 | else | |
5413 | return (GET_CODE (operands[2])) != CONST_INT | |
5414 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5415 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5416 | }" | |
b19003d8 | 5417 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5418 | |
266eb58a | 5419 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5420 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5421 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5422 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5423 | "! TARGET_POWERPC64" |
5502823b RK |
5424 | "* |
5425 | { | |
0f645302 MM |
5426 | if (WORDS_BIG_ENDIAN) |
5427 | return (GET_CODE (operands[1]) != CONST_INT) | |
5428 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5429 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5430 | else | |
5431 | return (GET_CODE (operands[1]) != CONST_INT) | |
5432 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5433 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5434 | }" |
ca7f5001 RK |
5435 | [(set_attr "length" "8")]) |
5436 | ||
266eb58a | 5437 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5438 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5439 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5440 | "! TARGET_POWERPC64" |
5502823b RK |
5441 | "* |
5442 | { | |
5443 | return (WORDS_BIG_ENDIAN) | |
5444 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5445 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5446 | }" | |
ca7f5001 RK |
5447 | [(set_attr "length" "8")]) |
5448 | ||
8ffd9c51 RK |
5449 | (define_expand "mulsidi3" |
5450 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5451 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5452 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5453 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5454 | " |
5455 | { | |
5456 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5457 | { | |
39403d82 DE |
5458 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5459 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5460 | emit_insn (gen_mull_call ()); |
cf27b467 | 5461 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5462 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5463 | else |
5464 | { | |
5465 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5466 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5467 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5468 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5469 | } |
8ffd9c51 RK |
5470 | DONE; |
5471 | } | |
5472 | else if (TARGET_POWER) | |
5473 | { | |
5474 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5475 | DONE; | |
5476 | } | |
5477 | }") | |
deb9225a | 5478 | |
8ffd9c51 | 5479 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5480 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5481 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5482 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5483 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5484 | "TARGET_POWER" |
b19003d8 | 5485 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5486 | [(set_attr "type" "imul") |
5487 | (set_attr "length" "8")]) | |
deb9225a | 5488 | |
f192bf8b | 5489 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5490 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5491 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5492 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5493 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5494 | "* |
5495 | { | |
5496 | return (WORDS_BIG_ENDIAN) | |
5497 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5498 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5499 | }" | |
8ffd9c51 RK |
5500 | [(set_attr "type" "imul") |
5501 | (set_attr "length" "8")]) | |
deb9225a | 5502 | |
ebedb4dd MM |
5503 | (define_split |
5504 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5505 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5506 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5507 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5508 | [(set (match_dup 3) |
5509 | (truncate:SI | |
5510 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5511 | (sign_extend:DI (match_dup 2))) | |
5512 | (const_int 32)))) | |
5513 | (set (match_dup 4) | |
5514 | (mult:SI (match_dup 1) | |
5515 | (match_dup 2)))] | |
5516 | " | |
5517 | { | |
5518 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5519 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5520 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5521 | }") | |
5522 | ||
f192bf8b DE |
5523 | (define_expand "umulsidi3" |
5524 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5525 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5526 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5527 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5528 | " | |
5529 | { | |
5530 | if (TARGET_POWER) | |
5531 | { | |
5532 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5533 | DONE; | |
5534 | } | |
5535 | }") | |
5536 | ||
5537 | (define_insn "umulsidi3_mq" | |
5538 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5539 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5540 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5541 | (clobber (match_scratch:SI 3 "=q"))] | |
5542 | "TARGET_POWERPC && TARGET_POWER" | |
5543 | "* | |
5544 | { | |
5545 | return (WORDS_BIG_ENDIAN) | |
5546 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5547 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5548 | }" | |
5549 | [(set_attr "type" "imul") | |
5550 | (set_attr "length" "8")]) | |
5551 | ||
5552 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5553 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5554 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5555 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5556 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5557 | "* |
5558 | { | |
5559 | return (WORDS_BIG_ENDIAN) | |
5560 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5561 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5562 | }" | |
5563 | [(set_attr "type" "imul") | |
5564 | (set_attr "length" "8")]) | |
5565 | ||
ebedb4dd MM |
5566 | (define_split |
5567 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5568 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5569 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5570 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5571 | [(set (match_dup 3) |
5572 | (truncate:SI | |
5573 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5574 | (zero_extend:DI (match_dup 2))) | |
5575 | (const_int 32)))) | |
5576 | (set (match_dup 4) | |
5577 | (mult:SI (match_dup 1) | |
5578 | (match_dup 2)))] | |
5579 | " | |
5580 | { | |
5581 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5582 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5583 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5584 | }") | |
5585 | ||
8ffd9c51 RK |
5586 | (define_expand "smulsi3_highpart" |
5587 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5588 | (truncate:SI | |
5589 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5590 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5591 | (sign_extend:DI | |
5592 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5593 | (const_int 32))))] | |
5594 | "" | |
5595 | " | |
5596 | { | |
5597 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5598 | { | |
39403d82 DE |
5599 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5600 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5601 | emit_insn (gen_mulh_call ()); |
39403d82 | 5602 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5603 | DONE; |
5604 | } | |
5605 | else if (TARGET_POWER) | |
5606 | { | |
5607 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5608 | DONE; | |
5609 | } | |
5610 | }") | |
deb9225a | 5611 | |
8ffd9c51 RK |
5612 | (define_insn "smulsi3_highpart_mq" |
5613 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5614 | (truncate:SI | |
fada905b MM |
5615 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5616 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5617 | (sign_extend:DI | |
5618 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5619 | (const_int 32)))) |
5620 | (clobber (match_scratch:SI 3 "=q"))] | |
5621 | "TARGET_POWER" | |
5622 | "mul %0,%1,%2" | |
5623 | [(set_attr "type" "imul")]) | |
deb9225a | 5624 | |
f192bf8b | 5625 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5626 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5627 | (truncate:SI | |
fada905b MM |
5628 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5629 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5630 | (sign_extend:DI | |
5631 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5632 | (const_int 32))))] |
f192bf8b | 5633 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5634 | "mulhw %0,%1,%2" |
5635 | [(set_attr "type" "imul")]) | |
deb9225a | 5636 | |
f192bf8b DE |
5637 | (define_expand "umulsi3_highpart" |
5638 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5639 | (truncate:SI | |
5640 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5641 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5642 | (zero_extend:DI | |
5643 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5644 | (const_int 32))))] | |
5645 | "TARGET_POWERPC" | |
5646 | " | |
5647 | { | |
5648 | if (TARGET_POWER) | |
5649 | { | |
5650 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5651 | DONE; | |
5652 | } | |
5653 | }") | |
5654 | ||
5655 | (define_insn "umulsi3_highpart_mq" | |
5656 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5657 | (truncate:SI | |
5658 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5659 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5660 | (zero_extend:DI | |
5661 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5662 | (const_int 32)))) | |
5663 | (clobber (match_scratch:SI 3 "=q"))] | |
5664 | "TARGET_POWERPC && TARGET_POWER" | |
5665 | "mulhwu %0,%1,%2" | |
5666 | [(set_attr "type" "imul")]) | |
5667 | ||
5668 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5669 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5670 | (truncate:SI | |
5671 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5672 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5673 | (zero_extend:DI | |
5674 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5675 | (const_int 32))))] | |
f192bf8b | 5676 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5677 | "mulhwu %0,%1,%2" |
5678 | [(set_attr "type" "imul")]) | |
5679 | ||
5680 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5681 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5682 | ;; why we have the strange constraints below. | |
5683 | (define_insn "ashldi3_power" | |
5684 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5685 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5686 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5687 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5688 | "TARGET_POWER" | |
5689 | "@ | |
5690 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5691 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5692 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5693 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5694 | [(set_attr "length" "8")]) | |
5695 | ||
5696 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5697 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5698 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5699 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5700 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5701 | "TARGET_POWER" | |
5702 | "@ | |
47ad8c61 | 5703 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5704 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5705 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5706 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5707 | [(set_attr "length" "8")]) | |
5708 | ||
5709 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5710 | ;; just handle shifts by constants. | |
5711 | (define_insn "ashrdi3_power" | |
7093ddee | 5712 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5713 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5714 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5715 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5716 | "TARGET_POWER" | |
5717 | "@ | |
5718 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5719 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5720 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
5721 | |
5722 | (define_insn "ashrdi3_no_power" | |
5723 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
5724 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5725 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
97727e85 | 5726 | "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN" |
4aa74a4f FS |
5727 | "@ |
5728 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5729 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
5730 | [(set_attr "length" "8,12")]) | |
683bdff7 FJ |
5731 | |
5732 | (define_insn "*ashrdisi3_noppc64" | |
5733 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 5734 | (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
683bdff7 FJ |
5735 | (const_int 32)) 4))] |
5736 | "TARGET_32BIT && !TARGET_POWERPC64" | |
5737 | "* | |
5738 | { | |
5739 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
5740 | return \"\"; | |
5741 | else | |
5742 | return \"mr %0,%1\"; | |
5743 | }" | |
6ae08853 | 5744 | [(set_attr "length" "4")]) |
683bdff7 | 5745 | |
266eb58a DE |
5746 | \f |
5747 | ;; PowerPC64 DImode operations. | |
5748 | ||
5749 | (define_expand "adddi3" | |
5750 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5751 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 5752 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
5753 | "" |
5754 | " | |
5755 | { | |
a260abc9 DE |
5756 | if (! TARGET_POWERPC64) |
5757 | { | |
5758 | if (non_short_cint_operand (operands[2], DImode)) | |
5759 | FAIL; | |
5760 | } | |
5761 | else | |
5762 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5763 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5764 | { |
677a9668 | 5765 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5766 | ? operands[0] : gen_reg_rtx (DImode)); |
5767 | ||
2bfcf297 | 5768 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5769 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5770 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
a260abc9 | 5771 | |
2bfcf297 DB |
5772 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
5773 | FAIL; | |
a260abc9 | 5774 | |
2bfcf297 DB |
5775 | /* The ordering here is important for the prolog expander. |
5776 | When space is allocated from the stack, adding 'low' first may | |
5777 | produce a temporary deallocation (which would be bad). */ | |
5778 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
5779 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
5780 | DONE; | |
5781 | } | |
266eb58a DE |
5782 | }") |
5783 | ||
5784 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5785 | ;; allowing register zero as source. | |
5786 | ||
a260abc9 | 5787 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5788 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5789 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5790 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5791 | "TARGET_POWERPC64" |
5792 | "@ | |
5793 | add %0,%1,%2 | |
5794 | addi %0,%1,%2 | |
5795 | addic %0,%1,%2 | |
802a0058 | 5796 | addis %0,%1,%v2") |
266eb58a | 5797 | |
a260abc9 | 5798 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5799 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5800 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5801 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5802 | (const_int 0))) |
9ebbca7d | 5803 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
683bdff7 | 5804 | "TARGET_64BIT" |
266eb58a DE |
5805 | "@ |
5806 | add. %3,%1,%2 | |
9ebbca7d GK |
5807 | addic. %3,%1,%2 |
5808 | # | |
5809 | #" | |
a62bfff2 | 5810 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5811 | (set_attr "length" "4,4,8,8")]) |
5812 | ||
5813 | (define_split | |
5814 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5815 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5816 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5817 | (const_int 0))) | |
5818 | (clobber (match_scratch:DI 3 ""))] | |
5819 | "TARGET_POWERPC64 && reload_completed" | |
5820 | [(set (match_dup 3) | |
5821 | (plus:DI (match_dup 1) (match_dup 2))) | |
5822 | (set (match_dup 0) | |
5823 | (compare:CC (match_dup 3) | |
5824 | (const_int 0)))] | |
5825 | "") | |
266eb58a | 5826 | |
a260abc9 | 5827 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5828 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5829 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5830 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5831 | (const_int 0))) |
9ebbca7d | 5832 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a | 5833 | (plus:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 5834 | "TARGET_64BIT" |
266eb58a DE |
5835 | "@ |
5836 | add. %0,%1,%2 | |
9ebbca7d GK |
5837 | addic. %0,%1,%2 |
5838 | # | |
5839 | #" | |
a62bfff2 | 5840 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5841 | (set_attr "length" "4,4,8,8")]) |
5842 | ||
5843 | (define_split | |
5844 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5845 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5846 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5847 | (const_int 0))) | |
5848 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5849 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5850 | "TARGET_POWERPC64 && reload_completed" | |
5851 | [(set (match_dup 0) | |
5852 | (plus:DI (match_dup 1) (match_dup 2))) | |
5853 | (set (match_dup 3) | |
5854 | (compare:CC (match_dup 0) | |
5855 | (const_int 0)))] | |
5856 | "") | |
266eb58a DE |
5857 | |
5858 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5859 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5860 | ;; add should be last in case the result gets used in an address. | |
5861 | ||
5862 | (define_split | |
5863 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5864 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5865 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5866 | "TARGET_POWERPC64" | |
5867 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5868 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5869 | " | |
5870 | { | |
2bfcf297 | 5871 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5872 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5873 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
266eb58a | 5874 | |
2bfcf297 DB |
5875 | operands[4] = GEN_INT (low); |
5876 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
5877 | operands[3] = GEN_INT (rest); | |
5878 | else if (! no_new_pseudos) | |
38886f37 | 5879 | { |
2bfcf297 DB |
5880 | operands[3] = gen_reg_rtx (DImode); |
5881 | emit_move_insn (operands[3], operands[2]); | |
5882 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
5883 | DONE; | |
38886f37 | 5884 | } |
2bfcf297 DB |
5885 | else |
5886 | FAIL; | |
266eb58a DE |
5887 | }") |
5888 | ||
5889 | (define_insn "one_cmpldi2" | |
5890 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5891 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5892 | "TARGET_POWERPC64" | |
5893 | "nor %0,%1,%1") | |
5894 | ||
5895 | (define_insn "" | |
9ebbca7d GK |
5896 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5897 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5898 | (const_int 0))) |
9ebbca7d | 5899 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 5900 | "TARGET_64BIT" |
9ebbca7d GK |
5901 | "@ |
5902 | nor. %2,%1,%1 | |
5903 | #" | |
5904 | [(set_attr "type" "compare") | |
5905 | (set_attr "length" "4,8")]) | |
5906 | ||
5907 | (define_split | |
5908 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5909 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5910 | (const_int 0))) | |
5911 | (clobber (match_scratch:DI 2 ""))] | |
5912 | "TARGET_POWERPC64 && reload_completed" | |
5913 | [(set (match_dup 2) | |
5914 | (not:DI (match_dup 1))) | |
5915 | (set (match_dup 0) | |
5916 | (compare:CC (match_dup 2) | |
5917 | (const_int 0)))] | |
5918 | "") | |
266eb58a DE |
5919 | |
5920 | (define_insn "" | |
9ebbca7d GK |
5921 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5922 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5923 | (const_int 0))) |
9ebbca7d | 5924 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 5925 | (not:DI (match_dup 1)))] |
683bdff7 | 5926 | "TARGET_64BIT" |
9ebbca7d GK |
5927 | "@ |
5928 | nor. %0,%1,%1 | |
5929 | #" | |
5930 | [(set_attr "type" "compare") | |
5931 | (set_attr "length" "4,8")]) | |
5932 | ||
5933 | (define_split | |
5934 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5935 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5936 | (const_int 0))) | |
5937 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5938 | (not:DI (match_dup 1)))] | |
5939 | "TARGET_POWERPC64 && reload_completed" | |
5940 | [(set (match_dup 0) | |
5941 | (not:DI (match_dup 1))) | |
5942 | (set (match_dup 2) | |
5943 | (compare:CC (match_dup 0) | |
5944 | (const_int 0)))] | |
5945 | "") | |
266eb58a DE |
5946 | |
5947 | (define_insn "" | |
5948 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5949 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5950 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5951 | "TARGET_POWERPC64" | |
5952 | "@ | |
5953 | subf %0,%2,%1 | |
5954 | subfic %0,%2,%1") | |
5955 | ||
5956 | (define_insn "" | |
9ebbca7d GK |
5957 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5958 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5959 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5960 | (const_int 0))) |
9ebbca7d | 5961 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 5962 | "TARGET_64BIT" |
9ebbca7d GK |
5963 | "@ |
5964 | subf. %3,%2,%1 | |
5965 | #" | |
a62bfff2 | 5966 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5967 | (set_attr "length" "4,8")]) |
5968 | ||
5969 | (define_split | |
5970 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5971 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5972 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5973 | (const_int 0))) | |
5974 | (clobber (match_scratch:DI 3 ""))] | |
5975 | "TARGET_POWERPC64 && reload_completed" | |
5976 | [(set (match_dup 3) | |
5977 | (minus:DI (match_dup 1) (match_dup 2))) | |
5978 | (set (match_dup 0) | |
5979 | (compare:CC (match_dup 3) | |
5980 | (const_int 0)))] | |
5981 | "") | |
266eb58a DE |
5982 | |
5983 | (define_insn "" | |
9ebbca7d GK |
5984 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5985 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5986 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5987 | (const_int 0))) |
9ebbca7d | 5988 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 5989 | (minus:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 5990 | "TARGET_64BIT" |
9ebbca7d GK |
5991 | "@ |
5992 | subf. %0,%2,%1 | |
5993 | #" | |
a62bfff2 | 5994 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5995 | (set_attr "length" "4,8")]) |
5996 | ||
5997 | (define_split | |
5998 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5999 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6000 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6001 | (const_int 0))) | |
6002 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6003 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6004 | "TARGET_POWERPC64 && reload_completed" | |
6005 | [(set (match_dup 0) | |
6006 | (minus:DI (match_dup 1) (match_dup 2))) | |
6007 | (set (match_dup 3) | |
6008 | (compare:CC (match_dup 0) | |
6009 | (const_int 0)))] | |
6010 | "") | |
266eb58a DE |
6011 | |
6012 | (define_expand "subdi3" | |
6013 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6014 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 6015 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
6016 | "" |
6017 | " | |
6018 | { | |
6019 | if (GET_CODE (operands[2]) == CONST_INT) | |
6020 | { | |
6021 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
6022 | negate_rtx (DImode, operands[2]))); | |
6023 | DONE; | |
6024 | } | |
6025 | }") | |
6026 | ||
ea112fc4 | 6027 | (define_insn_and_split "absdi2" |
266eb58a | 6028 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6029 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
6030 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6031 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6032 | "#" |
6033 | "&& reload_completed" | |
a260abc9 | 6034 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6035 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 6036 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
6037 | "") |
6038 | ||
ea112fc4 | 6039 | (define_insn_and_split "*nabsdi2" |
266eb58a | 6040 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6041 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
6042 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6043 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6044 | "#" |
6045 | "&& reload_completed" | |
a260abc9 | 6046 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6047 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 6048 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
6049 | "") |
6050 | ||
6051 | (define_expand "negdi2" | |
6052 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6053 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
6054 | "" | |
6055 | "") | |
6056 | ||
6057 | (define_insn "" | |
6058 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6059 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6060 | "TARGET_POWERPC64" | |
6061 | "neg %0,%1") | |
6062 | ||
6063 | (define_insn "" | |
9ebbca7d GK |
6064 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6065 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6066 | (const_int 0))) |
9ebbca7d | 6067 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 6068 | "TARGET_64BIT" |
9ebbca7d GK |
6069 | "@ |
6070 | neg. %2,%1 | |
6071 | #" | |
a62bfff2 | 6072 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6073 | (set_attr "length" "4,8")]) |
6074 | ||
6075 | (define_split | |
6076 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6077 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6078 | (const_int 0))) | |
6079 | (clobber (match_scratch:DI 2 ""))] | |
6080 | "TARGET_POWERPC64 && reload_completed" | |
6081 | [(set (match_dup 2) | |
6082 | (neg:DI (match_dup 1))) | |
6083 | (set (match_dup 0) | |
6084 | (compare:CC (match_dup 2) | |
6085 | (const_int 0)))] | |
6086 | "") | |
815cdc52 | 6087 | |
29ae5b89 | 6088 | (define_insn "" |
9ebbca7d GK |
6089 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6090 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6091 | (const_int 0))) |
9ebbca7d | 6092 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6093 | (neg:DI (match_dup 1)))] |
683bdff7 | 6094 | "TARGET_64BIT" |
9ebbca7d GK |
6095 | "@ |
6096 | neg. %0,%1 | |
6097 | #" | |
a62bfff2 | 6098 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6099 | (set_attr "length" "4,8")]) |
6100 | ||
6101 | (define_split | |
6102 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6103 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6104 | (const_int 0))) | |
6105 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6106 | (neg:DI (match_dup 1)))] | |
6107 | "TARGET_POWERPC64 && reload_completed" | |
6108 | [(set (match_dup 0) | |
6109 | (neg:DI (match_dup 1))) | |
6110 | (set (match_dup 2) | |
6111 | (compare:CC (match_dup 0) | |
6112 | (const_int 0)))] | |
6113 | "") | |
266eb58a | 6114 | |
1b1edcfa DE |
6115 | (define_insn "clzdi2" |
6116 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6117 | (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6118 | "TARGET_POWERPC64" | |
6119 | "cntlzd %0,%1") | |
6120 | ||
6121 | (define_expand "ctzdi2" | |
4977bab6 | 6122 | [(set (match_dup 2) |
1b1edcfa | 6123 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
6ae08853 AM |
6124 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
6125 | (match_dup 2))) | |
1b1edcfa | 6126 | (clobber (scratch:CC))]) |
d865b122 | 6127 | (set (match_dup 4) (clz:DI (match_dup 3))) |
4977bab6 | 6128 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 6129 | (minus:DI (const_int 63) (match_dup 4)))] |
266eb58a | 6130 | "TARGET_POWERPC64" |
4977bab6 | 6131 | { |
6ae08853 | 6132 | operands[2] = gen_reg_rtx (DImode); |
4977bab6 ZW |
6133 | operands[3] = gen_reg_rtx (DImode); |
6134 | operands[4] = gen_reg_rtx (DImode); | |
6135 | }) | |
6136 | ||
1b1edcfa DE |
6137 | (define_expand "ffsdi2" |
6138 | [(set (match_dup 2) | |
6139 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
6ae08853 AM |
6140 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
6141 | (match_dup 2))) | |
1b1edcfa DE |
6142 | (clobber (scratch:CC))]) |
6143 | (set (match_dup 4) (clz:DI (match_dup 3))) | |
6144 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6145 | (minus:DI (const_int 64) (match_dup 4)))] | |
4977bab6 | 6146 | "TARGET_POWERPC64" |
1b1edcfa | 6147 | { |
6ae08853 | 6148 | operands[2] = gen_reg_rtx (DImode); |
1b1edcfa DE |
6149 | operands[3] = gen_reg_rtx (DImode); |
6150 | operands[4] = gen_reg_rtx (DImode); | |
6151 | }) | |
266eb58a DE |
6152 | |
6153 | (define_insn "muldi3" | |
6154 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6155 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6156 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6157 | "TARGET_POWERPC64" | |
6158 | "mulld %0,%1,%2" | |
3cb999d8 | 6159 | [(set_attr "type" "lmul")]) |
266eb58a | 6160 | |
9259f3b0 DE |
6161 | (define_insn "*muldi3_internal1" |
6162 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6163 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6164 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6165 | (const_int 0))) | |
6166 | (clobber (match_scratch:DI 3 "=r,r"))] | |
6167 | "TARGET_POWERPC64" | |
6168 | "@ | |
6169 | mulld. %3,%1,%2 | |
6170 | #" | |
6171 | [(set_attr "type" "lmul_compare") | |
6172 | (set_attr "length" "4,8")]) | |
6173 | ||
6174 | (define_split | |
6175 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6176 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6177 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6178 | (const_int 0))) | |
6179 | (clobber (match_scratch:DI 3 ""))] | |
6180 | "TARGET_POWERPC64 && reload_completed" | |
6181 | [(set (match_dup 3) | |
6182 | (mult:DI (match_dup 1) (match_dup 2))) | |
6183 | (set (match_dup 0) | |
6184 | (compare:CC (match_dup 3) | |
6185 | (const_int 0)))] | |
6186 | "") | |
6187 | ||
6188 | (define_insn "*muldi3_internal2" | |
6189 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | |
6190 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6191 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6192 | (const_int 0))) | |
6193 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6194 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6195 | "TARGET_POWERPC64" | |
6196 | "@ | |
6197 | mulld. %0,%1,%2 | |
6198 | #" | |
6199 | [(set_attr "type" "lmul_compare") | |
6200 | (set_attr "length" "4,8")]) | |
6201 | ||
6202 | (define_split | |
6203 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6204 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6205 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6206 | (const_int 0))) | |
6207 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6208 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6209 | "TARGET_POWERPC64 && reload_completed" | |
6210 | [(set (match_dup 0) | |
6211 | (mult:DI (match_dup 1) (match_dup 2))) | |
6212 | (set (match_dup 3) | |
6213 | (compare:CC (match_dup 0) | |
6214 | (const_int 0)))] | |
6215 | "") | |
6216 | ||
266eb58a DE |
6217 | (define_insn "smuldi3_highpart" |
6218 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6219 | (truncate:DI | |
6220 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6221 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6222 | (sign_extend:TI | |
6223 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6224 | (const_int 64))))] | |
6225 | "TARGET_POWERPC64" | |
6226 | "mulhd %0,%1,%2" | |
3cb999d8 | 6227 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6228 | |
6229 | (define_insn "umuldi3_highpart" | |
6230 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6231 | (truncate:DI | |
6232 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6233 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6234 | (zero_extend:TI | |
6235 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6236 | (const_int 64))))] | |
6237 | "TARGET_POWERPC64" | |
6238 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6239 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6240 | |
6241 | (define_expand "divdi3" | |
6242 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6243 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6244 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6245 | "TARGET_POWERPC64" | |
6246 | " | |
6247 | { | |
6248 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6249 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6250 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6251 | ; | |
6252 | else | |
6253 | operands[2] = force_reg (DImode, operands[2]); | |
6254 | }") | |
6255 | ||
6256 | (define_expand "moddi3" | |
6257 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6258 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6259 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6260 | "TARGET_POWERPC64" | |
6261 | " | |
6262 | { | |
2bfcf297 | 6263 | int i; |
266eb58a DE |
6264 | rtx temp1; |
6265 | rtx temp2; | |
6266 | ||
2bfcf297 DB |
6267 | if (GET_CODE (operands[2]) != CONST_INT |
6268 | || INTVAL (operands[2]) <= 0 | |
6269 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6270 | FAIL; |
6271 | ||
6272 | temp1 = gen_reg_rtx (DImode); | |
6273 | temp2 = gen_reg_rtx (DImode); | |
6274 | ||
6275 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6276 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6277 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6278 | DONE; | |
6279 | }") | |
6280 | ||
6281 | (define_insn "" | |
6282 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6283 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6284 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6285 | "TARGET_POWERPC64" | |
266eb58a DE |
6286 | "sradi %0,%1,%p2\;addze %0,%0" |
6287 | [(set_attr "length" "8")]) | |
6288 | ||
6289 | (define_insn "" | |
9ebbca7d GK |
6290 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6291 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6292 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6293 | (const_int 0))) |
9ebbca7d | 6294 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6295 | "TARGET_64BIT" |
9ebbca7d GK |
6296 | "@ |
6297 | sradi %3,%1,%p2\;addze. %3,%3 | |
6298 | #" | |
266eb58a | 6299 | [(set_attr "type" "compare") |
9ebbca7d GK |
6300 | (set_attr "length" "8,12")]) |
6301 | ||
6302 | (define_split | |
6303 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6304 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6305 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6306 | (const_int 0))) |
6307 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6308 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6309 | [(set (match_dup 3) |
6310 | (div:DI (match_dup 1) (match_dup 2))) | |
6311 | (set (match_dup 0) | |
6312 | (compare:CC (match_dup 3) | |
6313 | (const_int 0)))] | |
6314 | "") | |
266eb58a DE |
6315 | |
6316 | (define_insn "" | |
9ebbca7d GK |
6317 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6318 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6319 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6320 | (const_int 0))) |
9ebbca7d | 6321 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6322 | (div:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6323 | "TARGET_64BIT" |
9ebbca7d GK |
6324 | "@ |
6325 | sradi %0,%1,%p2\;addze. %0,%0 | |
6326 | #" | |
266eb58a | 6327 | [(set_attr "type" "compare") |
9ebbca7d | 6328 | (set_attr "length" "8,12")]) |
266eb58a | 6329 | |
9ebbca7d GK |
6330 | (define_split |
6331 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6332 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6333 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6334 | (const_int 0))) |
6335 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6336 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6337 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6338 | [(set (match_dup 0) |
6339 | (div:DI (match_dup 1) (match_dup 2))) | |
6340 | (set (match_dup 3) | |
6341 | (compare:CC (match_dup 0) | |
6342 | (const_int 0)))] | |
6343 | "") | |
6344 | ||
6345 | (define_insn "" | |
6346 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6347 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6348 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6349 | "TARGET_POWERPC64" |
6350 | "divd %0,%1,%2" | |
3cb999d8 | 6351 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6352 | |
6353 | (define_insn "udivdi3" | |
6354 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6355 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6356 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6357 | "TARGET_POWERPC64" | |
6358 | "divdu %0,%1,%2" | |
3cb999d8 | 6359 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6360 | |
6361 | (define_insn "rotldi3" | |
6362 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6363 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6364 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6365 | "TARGET_POWERPC64" | |
a66078ee | 6366 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6367 | |
a260abc9 | 6368 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6369 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6370 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6371 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6372 | (const_int 0))) |
9ebbca7d | 6373 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6374 | "TARGET_64BIT" |
9ebbca7d GK |
6375 | "@ |
6376 | rld%I2cl. %3,%1,%H2,0 | |
6377 | #" | |
6378 | [(set_attr "type" "delayed_compare") | |
6379 | (set_attr "length" "4,8")]) | |
6380 | ||
6381 | (define_split | |
6382 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6383 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6384 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6385 | (const_int 0))) | |
6386 | (clobber (match_scratch:DI 3 ""))] | |
6387 | "TARGET_POWERPC64 && reload_completed" | |
6388 | [(set (match_dup 3) | |
6389 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6390 | (set (match_dup 0) | |
6391 | (compare:CC (match_dup 3) | |
6392 | (const_int 0)))] | |
6393 | "") | |
266eb58a | 6394 | |
a260abc9 | 6395 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6396 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6397 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6398 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6399 | (const_int 0))) |
9ebbca7d | 6400 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6401 | (rotate:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6402 | "TARGET_64BIT" |
9ebbca7d GK |
6403 | "@ |
6404 | rld%I2cl. %0,%1,%H2,0 | |
6405 | #" | |
6406 | [(set_attr "type" "delayed_compare") | |
6407 | (set_attr "length" "4,8")]) | |
6408 | ||
6409 | (define_split | |
6410 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6411 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6412 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6413 | (const_int 0))) | |
6414 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6415 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6416 | "TARGET_POWERPC64 && reload_completed" | |
6417 | [(set (match_dup 0) | |
6418 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6419 | (set (match_dup 3) | |
6420 | (compare:CC (match_dup 0) | |
6421 | (const_int 0)))] | |
6422 | "") | |
266eb58a | 6423 | |
a260abc9 DE |
6424 | (define_insn "*rotldi3_internal4" |
6425 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6426 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6427 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
ce71f754 | 6428 | (match_operand:DI 3 "mask64_operand" "n")))] |
a260abc9 DE |
6429 | "TARGET_POWERPC64" |
6430 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6431 | ||
6432 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6433 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6434 | (compare:CC (and:DI |
9ebbca7d GK |
6435 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6436 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6437 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6438 | (const_int 0))) |
9ebbca7d | 6439 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6440 | "TARGET_64BIT" |
9ebbca7d GK |
6441 | "@ |
6442 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6443 | #" | |
6444 | [(set_attr "type" "delayed_compare") | |
6445 | (set_attr "length" "4,8")]) | |
6446 | ||
6447 | (define_split | |
6448 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6449 | (compare:CC (and:DI | |
6450 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6451 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6452 | (match_operand:DI 3 "mask64_operand" "")) | |
6453 | (const_int 0))) | |
6454 | (clobber (match_scratch:DI 4 ""))] | |
6455 | "TARGET_POWERPC64 && reload_completed" | |
6456 | [(set (match_dup 4) | |
6457 | (and:DI (rotate:DI (match_dup 1) | |
6458 | (match_dup 2)) | |
6459 | (match_dup 3))) | |
6460 | (set (match_dup 0) | |
6461 | (compare:CC (match_dup 4) | |
6462 | (const_int 0)))] | |
6463 | "") | |
a260abc9 DE |
6464 | |
6465 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6466 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6467 | (compare:CC (and:DI |
9ebbca7d GK |
6468 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6469 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6470 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6471 | (const_int 0))) |
9ebbca7d | 6472 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6473 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6474 | "TARGET_64BIT" |
9ebbca7d GK |
6475 | "@ |
6476 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6477 | #" | |
6478 | [(set_attr "type" "delayed_compare") | |
6479 | (set_attr "length" "4,8")]) | |
6480 | ||
6481 | (define_split | |
6482 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6483 | (compare:CC (and:DI | |
6484 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6485 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6486 | (match_operand:DI 3 "mask64_operand" "")) | |
6487 | (const_int 0))) | |
6488 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6489 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6490 | "TARGET_POWERPC64 && reload_completed" | |
6491 | [(set (match_dup 0) | |
6492 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6493 | (set (match_dup 4) | |
6494 | (compare:CC (match_dup 0) | |
6495 | (const_int 0)))] | |
6496 | "") | |
a260abc9 DE |
6497 | |
6498 | (define_insn "*rotldi3_internal7" | |
6499 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6500 | (zero_extend:DI | |
6501 | (subreg:QI | |
6502 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6503 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6504 | "TARGET_POWERPC64" | |
6505 | "rld%I2cl %0,%1,%H2,56") | |
6506 | ||
6507 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6508 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6509 | (compare:CC (zero_extend:DI |
6510 | (subreg:QI | |
9ebbca7d GK |
6511 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6512 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6513 | (const_int 0))) |
9ebbca7d | 6514 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6515 | "TARGET_64BIT" |
9ebbca7d GK |
6516 | "@ |
6517 | rld%I2cl. %3,%1,%H2,56 | |
6518 | #" | |
6519 | [(set_attr "type" "delayed_compare") | |
6520 | (set_attr "length" "4,8")]) | |
6521 | ||
6522 | (define_split | |
6523 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6524 | (compare:CC (zero_extend:DI | |
6525 | (subreg:QI | |
6526 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6527 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6528 | (const_int 0))) | |
6529 | (clobber (match_scratch:DI 3 ""))] | |
6530 | "TARGET_POWERPC64 && reload_completed" | |
6531 | [(set (match_dup 3) | |
6532 | (zero_extend:DI (subreg:QI | |
6533 | (rotate:DI (match_dup 1) | |
6534 | (match_dup 2)) 0))) | |
6535 | (set (match_dup 0) | |
6536 | (compare:CC (match_dup 3) | |
6537 | (const_int 0)))] | |
6538 | "") | |
a260abc9 DE |
6539 | |
6540 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6541 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6542 | (compare:CC (zero_extend:DI |
6543 | (subreg:QI | |
9ebbca7d GK |
6544 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6545 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6546 | (const_int 0))) |
9ebbca7d | 6547 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6548 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6549 | "TARGET_64BIT" |
9ebbca7d GK |
6550 | "@ |
6551 | rld%I2cl. %0,%1,%H2,56 | |
6552 | #" | |
6553 | [(set_attr "type" "delayed_compare") | |
6554 | (set_attr "length" "4,8")]) | |
6555 | ||
6556 | (define_split | |
6557 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6558 | (compare:CC (zero_extend:DI | |
6559 | (subreg:QI | |
6560 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6561 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6562 | (const_int 0))) | |
6563 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6564 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6565 | "TARGET_POWERPC64 && reload_completed" | |
6566 | [(set (match_dup 0) | |
6567 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6568 | (set (match_dup 3) | |
6569 | (compare:CC (match_dup 0) | |
6570 | (const_int 0)))] | |
6571 | "") | |
a260abc9 DE |
6572 | |
6573 | (define_insn "*rotldi3_internal10" | |
6574 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6575 | (zero_extend:DI | |
6576 | (subreg:HI | |
6577 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6578 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6579 | "TARGET_POWERPC64" | |
6580 | "rld%I2cl %0,%1,%H2,48") | |
6581 | ||
6582 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6583 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6584 | (compare:CC (zero_extend:DI |
6585 | (subreg:HI | |
9ebbca7d GK |
6586 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6587 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6588 | (const_int 0))) |
9ebbca7d | 6589 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6590 | "TARGET_64BIT" |
9ebbca7d GK |
6591 | "@ |
6592 | rld%I2cl. %3,%1,%H2,48 | |
6593 | #" | |
6594 | [(set_attr "type" "delayed_compare") | |
6595 | (set_attr "length" "4,8")]) | |
6596 | ||
6597 | (define_split | |
6598 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6599 | (compare:CC (zero_extend:DI | |
6600 | (subreg:HI | |
6601 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6602 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6603 | (const_int 0))) | |
6604 | (clobber (match_scratch:DI 3 ""))] | |
6605 | "TARGET_POWERPC64 && reload_completed" | |
6606 | [(set (match_dup 3) | |
6607 | (zero_extend:DI (subreg:HI | |
6608 | (rotate:DI (match_dup 1) | |
6609 | (match_dup 2)) 0))) | |
6610 | (set (match_dup 0) | |
6611 | (compare:CC (match_dup 3) | |
6612 | (const_int 0)))] | |
6613 | "") | |
a260abc9 DE |
6614 | |
6615 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6616 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6617 | (compare:CC (zero_extend:DI |
6618 | (subreg:HI | |
9ebbca7d GK |
6619 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6620 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6621 | (const_int 0))) |
9ebbca7d | 6622 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6623 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6624 | "TARGET_64BIT" |
9ebbca7d GK |
6625 | "@ |
6626 | rld%I2cl. %0,%1,%H2,48 | |
6627 | #" | |
6628 | [(set_attr "type" "delayed_compare") | |
6629 | (set_attr "length" "4,8")]) | |
6630 | ||
6631 | (define_split | |
6632 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6633 | (compare:CC (zero_extend:DI | |
6634 | (subreg:HI | |
6635 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6636 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6637 | (const_int 0))) | |
6638 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6639 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6640 | "TARGET_POWERPC64 && reload_completed" | |
6641 | [(set (match_dup 0) | |
6642 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6643 | (set (match_dup 3) | |
6644 | (compare:CC (match_dup 0) | |
6645 | (const_int 0)))] | |
6646 | "") | |
a260abc9 DE |
6647 | |
6648 | (define_insn "*rotldi3_internal13" | |
6649 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6650 | (zero_extend:DI | |
6651 | (subreg:SI | |
6652 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6653 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6654 | "TARGET_POWERPC64" | |
6655 | "rld%I2cl %0,%1,%H2,32") | |
6656 | ||
6657 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6658 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6659 | (compare:CC (zero_extend:DI |
6660 | (subreg:SI | |
9ebbca7d GK |
6661 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6662 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6663 | (const_int 0))) |
9ebbca7d | 6664 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6665 | "TARGET_64BIT" |
9ebbca7d GK |
6666 | "@ |
6667 | rld%I2cl. %3,%1,%H2,32 | |
6668 | #" | |
6669 | [(set_attr "type" "delayed_compare") | |
6670 | (set_attr "length" "4,8")]) | |
6671 | ||
6672 | (define_split | |
6673 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6674 | (compare:CC (zero_extend:DI | |
6675 | (subreg:SI | |
6676 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6677 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6678 | (const_int 0))) | |
6679 | (clobber (match_scratch:DI 3 ""))] | |
6680 | "TARGET_POWERPC64 && reload_completed" | |
6681 | [(set (match_dup 3) | |
6682 | (zero_extend:DI (subreg:SI | |
6683 | (rotate:DI (match_dup 1) | |
6684 | (match_dup 2)) 0))) | |
6685 | (set (match_dup 0) | |
6686 | (compare:CC (match_dup 3) | |
6687 | (const_int 0)))] | |
6688 | "") | |
a260abc9 DE |
6689 | |
6690 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6691 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6692 | (compare:CC (zero_extend:DI |
6693 | (subreg:SI | |
9ebbca7d GK |
6694 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6695 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6696 | (const_int 0))) |
9ebbca7d | 6697 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6698 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6699 | "TARGET_64BIT" |
9ebbca7d GK |
6700 | "@ |
6701 | rld%I2cl. %0,%1,%H2,32 | |
6702 | #" | |
6703 | [(set_attr "type" "delayed_compare") | |
6704 | (set_attr "length" "4,8")]) | |
6705 | ||
6706 | (define_split | |
6707 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6708 | (compare:CC (zero_extend:DI | |
6709 | (subreg:SI | |
6710 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6711 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6712 | (const_int 0))) | |
6713 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6714 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6715 | "TARGET_POWERPC64 && reload_completed" | |
6716 | [(set (match_dup 0) | |
6717 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6718 | (set (match_dup 3) | |
6719 | (compare:CC (match_dup 0) | |
6720 | (const_int 0)))] | |
6721 | "") | |
a260abc9 | 6722 | |
266eb58a DE |
6723 | (define_expand "ashldi3" |
6724 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6725 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6726 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6727 | "TARGET_POWERPC64 || TARGET_POWER" | |
6728 | " | |
6729 | { | |
6730 | if (TARGET_POWERPC64) | |
6731 | ; | |
6732 | else if (TARGET_POWER) | |
6733 | { | |
6734 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6735 | DONE; | |
6736 | } | |
6737 | else | |
6738 | FAIL; | |
6739 | }") | |
6740 | ||
e2c953b6 | 6741 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6742 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6743 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6744 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6745 | "TARGET_POWERPC64" | |
a66078ee | 6746 | "sld%I2 %0,%1,%H2" |
266eb58a | 6747 | [(set_attr "length" "8")]) |
6ae08853 | 6748 | |
e2c953b6 | 6749 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6750 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6751 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6752 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6753 | (const_int 0))) |
9ebbca7d | 6754 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6755 | "TARGET_64BIT" |
9ebbca7d GK |
6756 | "@ |
6757 | sld%I2. %3,%1,%H2 | |
6758 | #" | |
6759 | [(set_attr "type" "delayed_compare") | |
6760 | (set_attr "length" "4,8")]) | |
6ae08853 | 6761 | |
9ebbca7d GK |
6762 | (define_split |
6763 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6764 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6765 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6766 | (const_int 0))) | |
6767 | (clobber (match_scratch:DI 3 ""))] | |
6768 | "TARGET_POWERPC64 && reload_completed" | |
6769 | [(set (match_dup 3) | |
6770 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6771 | (set (match_dup 0) | |
6772 | (compare:CC (match_dup 3) | |
6773 | (const_int 0)))] | |
6774 | "") | |
6775 | ||
e2c953b6 | 6776 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6777 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6778 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6779 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6780 | (const_int 0))) |
9ebbca7d | 6781 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6782 | (ashift:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6783 | "TARGET_64BIT" |
9ebbca7d GK |
6784 | "@ |
6785 | sld%I2. %0,%1,%H2 | |
6786 | #" | |
6787 | [(set_attr "type" "delayed_compare") | |
6788 | (set_attr "length" "4,8")]) | |
6789 | ||
6790 | (define_split | |
6791 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6792 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6793 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6794 | (const_int 0))) | |
6795 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6796 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6797 | "TARGET_POWERPC64 && reload_completed" | |
6798 | [(set (match_dup 0) | |
6799 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6800 | (set (match_dup 3) | |
6801 | (compare:CC (match_dup 0) | |
6802 | (const_int 0)))] | |
6803 | "") | |
266eb58a | 6804 | |
e2c953b6 | 6805 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6806 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6807 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6808 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6809 | (match_operand:DI 3 "const_int_operand" "n")))] |
6810 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6811 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6812 | |
e2c953b6 | 6813 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6814 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6815 | (compare:CC |
9ebbca7d GK |
6816 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6817 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6818 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6819 | (const_int 0))) |
9ebbca7d | 6820 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6821 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6822 | "@ |
e2c953b6 | 6823 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6824 | #" |
6825 | [(set_attr "type" "delayed_compare") | |
6826 | (set_attr "length" "4,8")]) | |
6827 | ||
6828 | (define_split | |
6829 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6830 | (compare:CC | |
6831 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6832 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6833 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6834 | (const_int 0))) |
6835 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6836 | "TARGET_POWERPC64 && reload_completed |
6837 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6838 | [(set (match_dup 4) |
6839 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6840 | (match_dup 3))) |
9ebbca7d GK |
6841 | (set (match_dup 0) |
6842 | (compare:CC (match_dup 4) | |
6843 | (const_int 0)))] | |
6844 | "") | |
3cb999d8 | 6845 | |
e2c953b6 | 6846 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6847 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6848 | (compare:CC |
9ebbca7d GK |
6849 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6850 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6851 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6852 | (const_int 0))) |
9ebbca7d | 6853 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6854 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6855 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6856 | "@ |
e2c953b6 | 6857 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6858 | #" |
6859 | [(set_attr "type" "delayed_compare") | |
6860 | (set_attr "length" "4,8")]) | |
6861 | ||
6862 | (define_split | |
6863 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6864 | (compare:CC | |
6865 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6866 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6867 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6868 | (const_int 0))) |
6869 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6870 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6871 | "TARGET_POWERPC64 && reload_completed |
6872 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6873 | [(set (match_dup 0) | |
6874 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6875 | (match_dup 3))) | |
6876 | (set (match_dup 4) | |
6877 | (compare:CC (match_dup 0) | |
6878 | (const_int 0)))] | |
6879 | "") | |
6880 | ||
6881 | (define_insn "*ashldi3_internal7" | |
6882 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6883 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6884 | (match_operand:SI 2 "const_int_operand" "i")) | |
ce71f754 | 6885 | (match_operand:DI 3 "mask64_operand" "n")))] |
c5059423 AM |
6886 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
6887 | "rldicr %0,%1,%H2,%S3") | |
6888 | ||
6889 | (define_insn "ashldi3_internal8" | |
6890 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6891 | (compare:CC | |
6892 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6893 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6894 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6895 | (const_int 0))) |
6896 | (clobber (match_scratch:DI 4 "=r,r"))] | |
683bdff7 | 6897 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6898 | "@ |
6899 | rldicr. %4,%1,%H2,%S3 | |
6900 | #" | |
6901 | [(set_attr "type" "delayed_compare") | |
6902 | (set_attr "length" "4,8")]) | |
6903 | ||
6904 | (define_split | |
6905 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6906 | (compare:CC | |
6907 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6908 | (match_operand:SI 2 "const_int_operand" "")) | |
6909 | (match_operand:DI 3 "mask64_operand" "")) | |
6910 | (const_int 0))) | |
6911 | (clobber (match_scratch:DI 4 ""))] | |
6912 | "TARGET_POWERPC64 && reload_completed | |
6913 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6914 | [(set (match_dup 4) | |
6915 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6916 | (match_dup 3))) | |
6917 | (set (match_dup 0) | |
6918 | (compare:CC (match_dup 4) | |
6919 | (const_int 0)))] | |
6920 | "") | |
6921 | ||
6922 | (define_insn "*ashldi3_internal9" | |
6923 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6924 | (compare:CC | |
6925 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6926 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6927 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6928 | (const_int 0))) |
6929 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6930 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 6931 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6932 | "@ |
6933 | rldicr. %0,%1,%H2,%S3 | |
6934 | #" | |
6935 | [(set_attr "type" "delayed_compare") | |
6936 | (set_attr "length" "4,8")]) | |
6937 | ||
6938 | (define_split | |
6939 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6940 | (compare:CC | |
6941 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6942 | (match_operand:SI 2 "const_int_operand" "")) | |
6943 | (match_operand:DI 3 "mask64_operand" "")) | |
6944 | (const_int 0))) | |
6945 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6946 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6947 | "TARGET_POWERPC64 && reload_completed | |
6948 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6949 | [(set (match_dup 0) |
e2c953b6 DE |
6950 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6951 | (match_dup 3))) | |
9ebbca7d GK |
6952 | (set (match_dup 4) |
6953 | (compare:CC (match_dup 0) | |
6954 | (const_int 0)))] | |
6955 | "") | |
6956 | ||
6957 | (define_expand "lshrdi3" | |
266eb58a DE |
6958 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6959 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6960 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6961 | "TARGET_POWERPC64 || TARGET_POWER" | |
6962 | " | |
6963 | { | |
6964 | if (TARGET_POWERPC64) | |
6965 | ; | |
6966 | else if (TARGET_POWER) | |
6967 | { | |
6968 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6969 | DONE; | |
6970 | } | |
6971 | else | |
6972 | FAIL; | |
6973 | }") | |
6974 | ||
e2c953b6 | 6975 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6976 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6977 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6978 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6979 | "TARGET_POWERPC64" | |
a66078ee | 6980 | "srd%I2 %0,%1,%H2") |
266eb58a | 6981 | |
e2c953b6 | 6982 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6983 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6984 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6985 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6986 | (const_int 0))) |
9ebbca7d | 6987 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6988 | "TARGET_64BIT " |
9ebbca7d GK |
6989 | "@ |
6990 | srd%I2. %3,%1,%H2 | |
6991 | #" | |
6992 | [(set_attr "type" "delayed_compare") | |
6993 | (set_attr "length" "4,8")]) | |
6994 | ||
6995 | (define_split | |
6996 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6997 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6998 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6999 | (const_int 0))) | |
7000 | (clobber (match_scratch:DI 3 ""))] | |
7001 | "TARGET_POWERPC64 && reload_completed" | |
7002 | [(set (match_dup 3) | |
7003 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7004 | (set (match_dup 0) | |
7005 | (compare:CC (match_dup 3) | |
7006 | (const_int 0)))] | |
7007 | "") | |
266eb58a | 7008 | |
e2c953b6 | 7009 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
7010 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7011 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7012 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7013 | (const_int 0))) |
9ebbca7d | 7014 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 7015 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 7016 | "TARGET_64BIT" |
9ebbca7d GK |
7017 | "@ |
7018 | srd%I2. %0,%1,%H2 | |
7019 | #" | |
7020 | [(set_attr "type" "delayed_compare") | |
7021 | (set_attr "length" "4,8")]) | |
7022 | ||
7023 | (define_split | |
7024 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7025 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7026 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7027 | (const_int 0))) | |
7028 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7029 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
7030 | "TARGET_POWERPC64 && reload_completed" | |
7031 | [(set (match_dup 0) | |
7032 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7033 | (set (match_dup 3) | |
7034 | (compare:CC (match_dup 0) | |
7035 | (const_int 0)))] | |
7036 | "") | |
266eb58a DE |
7037 | |
7038 | (define_expand "ashrdi3" | |
7039 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7040 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7041 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
97727e85 | 7042 | "WORDS_BIG_ENDIAN" |
266eb58a DE |
7043 | " |
7044 | { | |
7045 | if (TARGET_POWERPC64) | |
7046 | ; | |
7047 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
7048 | { | |
7049 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
7050 | DONE; | |
7051 | } | |
97727e85 AH |
7052 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT |
7053 | && WORDS_BIG_ENDIAN) | |
4aa74a4f FS |
7054 | { |
7055 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
7056 | DONE; | |
7057 | } | |
266eb58a DE |
7058 | else |
7059 | FAIL; | |
7060 | }") | |
7061 | ||
e2c953b6 | 7062 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
7063 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7064 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7065 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7066 | "TARGET_POWERPC64" | |
375490e0 | 7067 | "srad%I2 %0,%1,%H2") |
266eb58a | 7068 | |
e2c953b6 | 7069 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
7070 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7071 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7072 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7073 | (const_int 0))) |
9ebbca7d | 7074 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7075 | "TARGET_64BIT" |
9ebbca7d GK |
7076 | "@ |
7077 | srad%I2. %3,%1,%H2 | |
7078 | #" | |
7079 | [(set_attr "type" "delayed_compare") | |
7080 | (set_attr "length" "4,8")]) | |
7081 | ||
7082 | (define_split | |
7083 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7084 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7085 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7086 | (const_int 0))) | |
7087 | (clobber (match_scratch:DI 3 ""))] | |
7088 | "TARGET_POWERPC64 && reload_completed" | |
7089 | [(set (match_dup 3) | |
7090 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7091 | (set (match_dup 0) | |
7092 | (compare:CC (match_dup 3) | |
7093 | (const_int 0)))] | |
7094 | "") | |
266eb58a | 7095 | |
e2c953b6 | 7096 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
7097 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7098 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7099 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7100 | (const_int 0))) |
9ebbca7d | 7101 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 7102 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 7103 | "TARGET_64BIT" |
9ebbca7d GK |
7104 | "@ |
7105 | srad%I2. %0,%1,%H2 | |
7106 | #" | |
7107 | [(set_attr "type" "delayed_compare") | |
7108 | (set_attr "length" "4,8")]) | |
7109 | ||
7110 | (define_split | |
7111 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7112 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7113 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7114 | (const_int 0))) | |
7115 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7116 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7117 | "TARGET_POWERPC64 && reload_completed" | |
7118 | [(set (match_dup 0) | |
7119 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7120 | (set (match_dup 3) | |
7121 | (compare:CC (match_dup 0) | |
7122 | (const_int 0)))] | |
7123 | "") | |
815cdc52 | 7124 | |
29ae5b89 | 7125 | (define_insn "anddi3" |
0ba1b2ff AM |
7126 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") |
7127 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
7128 | (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t"))) | |
7129 | (clobber (match_scratch:CC 3 "=X,X,x,x,X"))] | |
6ffc8580 | 7130 | "TARGET_POWERPC64" |
266eb58a DE |
7131 | "@ |
7132 | and %0,%1,%2 | |
29ae5b89 JL |
7133 | rldic%B2 %0,%1,0,%S2 |
7134 | andi. %0,%1,%b2 | |
0ba1b2ff AM |
7135 | andis. %0,%1,%u2 |
7136 | #" | |
520308bc DE |
7137 | [(set_attr "type" "*,*,compare,compare,*") |
7138 | (set_attr "length" "4,4,4,4,8")]) | |
0ba1b2ff AM |
7139 | |
7140 | (define_split | |
7141 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7142 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7143 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
7144 | (clobber (match_scratch:CC 3 ""))] | |
7145 | "TARGET_POWERPC64 | |
7146 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7147 | && !mask64_operand (operands[2], DImode)" | |
7148 | [(set (match_dup 0) | |
7149 | (and:DI (rotate:DI (match_dup 1) | |
7150 | (match_dup 4)) | |
7151 | (match_dup 5))) | |
7152 | (set (match_dup 0) | |
7153 | (and:DI (rotate:DI (match_dup 0) | |
7154 | (match_dup 6)) | |
7155 | (match_dup 7)))] | |
7156 | " | |
7157 | { | |
7158 | build_mask64_2_operands (operands[2], &operands[4]); | |
7159 | }") | |
266eb58a | 7160 | |
a260abc9 | 7161 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
7162 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7163 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7164 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7165 | (const_int 0))) |
0ba1b2ff AM |
7166 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
7167 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
683bdff7 | 7168 | "TARGET_64BIT" |
266eb58a DE |
7169 | "@ |
7170 | and. %3,%1,%2 | |
6c873122 | 7171 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
7172 | andi. %3,%1,%b2 |
7173 | andis. %3,%1,%u2 | |
9ebbca7d GK |
7174 | # |
7175 | # | |
7176 | # | |
0ba1b2ff AM |
7177 | # |
7178 | # | |
9ebbca7d | 7179 | #" |
0ba1b2ff AM |
7180 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7181 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7182 | |
7183 | (define_split | |
7184 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7185 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7186 | (match_operand:DI 2 "and64_operand" "")) | |
7187 | (const_int 0))) | |
7188 | (clobber (match_scratch:DI 3 "")) | |
7189 | (clobber (match_scratch:CC 4 ""))] | |
7190 | "TARGET_POWERPC64 && reload_completed" | |
7191 | [(parallel [(set (match_dup 3) | |
7192 | (and:DI (match_dup 1) | |
7193 | (match_dup 2))) | |
7194 | (clobber (match_dup 4))]) | |
7195 | (set (match_dup 0) | |
7196 | (compare:CC (match_dup 3) | |
7197 | (const_int 0)))] | |
7198 | "") | |
266eb58a | 7199 | |
0ba1b2ff AM |
7200 | (define_split |
7201 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
7202 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7203 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7204 | (const_int 0))) | |
7205 | (clobber (match_scratch:DI 3 "")) | |
7206 | (clobber (match_scratch:CC 4 ""))] | |
7207 | "TARGET_POWERPC64 && reload_completed | |
7208 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7209 | && !mask64_operand (operands[2], DImode)" | |
7210 | [(set (match_dup 3) | |
7211 | (and:DI (rotate:DI (match_dup 1) | |
7212 | (match_dup 5)) | |
7213 | (match_dup 6))) | |
7214 | (parallel [(set (match_dup 0) | |
7215 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
7216 | (match_dup 7)) | |
7217 | (match_dup 8)) | |
7218 | (const_int 0))) | |
7219 | (clobber (match_dup 3))])] | |
7220 | " | |
7221 | { | |
7222 | build_mask64_2_operands (operands[2], &operands[5]); | |
7223 | }") | |
7224 | ||
a260abc9 | 7225 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
7226 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7227 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7228 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7229 | (const_int 0))) |
0ba1b2ff | 7230 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 7231 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 7232 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
683bdff7 | 7233 | "TARGET_64BIT" |
266eb58a DE |
7234 | "@ |
7235 | and. %0,%1,%2 | |
6c873122 | 7236 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7237 | andi. %0,%1,%b2 |
7238 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7239 | # |
7240 | # | |
7241 | # | |
0ba1b2ff AM |
7242 | # |
7243 | # | |
9ebbca7d | 7244 | #" |
0ba1b2ff AM |
7245 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7246 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7247 | |
7248 | (define_split | |
7249 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7250 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7251 | (match_operand:DI 2 "and64_operand" "")) | |
7252 | (const_int 0))) | |
7253 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7254 | (and:DI (match_dup 1) (match_dup 2))) | |
7255 | (clobber (match_scratch:CC 4 ""))] | |
7256 | "TARGET_POWERPC64 && reload_completed" | |
7257 | [(parallel [(set (match_dup 0) | |
7258 | (and:DI (match_dup 1) (match_dup 2))) | |
7259 | (clobber (match_dup 4))]) | |
7260 | (set (match_dup 3) | |
7261 | (compare:CC (match_dup 0) | |
7262 | (const_int 0)))] | |
7263 | "") | |
266eb58a | 7264 | |
0ba1b2ff AM |
7265 | (define_split |
7266 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
7267 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7268 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7269 | (const_int 0))) | |
7270 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7271 | (and:DI (match_dup 1) (match_dup 2))) | |
7272 | (clobber (match_scratch:CC 4 ""))] | |
7273 | "TARGET_POWERPC64 && reload_completed | |
7274 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7275 | && !mask64_operand (operands[2], DImode)" | |
7276 | [(set (match_dup 0) | |
7277 | (and:DI (rotate:DI (match_dup 1) | |
7278 | (match_dup 5)) | |
7279 | (match_dup 6))) | |
7280 | (parallel [(set (match_dup 3) | |
7281 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
7282 | (match_dup 7)) | |
7283 | (match_dup 8)) | |
7284 | (const_int 0))) | |
7285 | (set (match_dup 0) | |
7286 | (and:DI (rotate:DI (match_dup 0) | |
7287 | (match_dup 7)) | |
7288 | (match_dup 8)))])] | |
7289 | " | |
7290 | { | |
7291 | build_mask64_2_operands (operands[2], &operands[5]); | |
7292 | }") | |
7293 | ||
a260abc9 | 7294 | (define_expand "iordi3" |
266eb58a | 7295 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7296 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7297 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7298 | "TARGET_POWERPC64" |
266eb58a DE |
7299 | " |
7300 | { | |
dfbdccdb | 7301 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7302 | { |
dfbdccdb | 7303 | HOST_WIDE_INT value; |
677a9668 | 7304 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7305 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7306 | |
dfbdccdb GK |
7307 | if (GET_CODE (operands[2]) == CONST_INT) |
7308 | { | |
7309 | value = INTVAL (operands[2]); | |
7310 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7311 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7312 | } | |
e2c953b6 | 7313 | else |
dfbdccdb GK |
7314 | { |
7315 | value = CONST_DOUBLE_LOW (operands[2]); | |
7316 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7317 | immed_double_const (value | |
7318 | & (~ (HOST_WIDE_INT) 0xffff), | |
7319 | 0, DImode))); | |
7320 | } | |
e2c953b6 | 7321 | |
9ebbca7d GK |
7322 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7323 | DONE; | |
7324 | } | |
266eb58a DE |
7325 | }") |
7326 | ||
a260abc9 DE |
7327 | (define_expand "xordi3" |
7328 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7329 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7330 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7331 | "TARGET_POWERPC64" |
7332 | " | |
7333 | { | |
dfbdccdb | 7334 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7335 | { |
dfbdccdb | 7336 | HOST_WIDE_INT value; |
677a9668 | 7337 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7338 | ? operands[0] : gen_reg_rtx (DImode)); |
7339 | ||
dfbdccdb GK |
7340 | if (GET_CODE (operands[2]) == CONST_INT) |
7341 | { | |
7342 | value = INTVAL (operands[2]); | |
7343 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7344 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7345 | } | |
e2c953b6 | 7346 | else |
dfbdccdb GK |
7347 | { |
7348 | value = CONST_DOUBLE_LOW (operands[2]); | |
7349 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7350 | immed_double_const (value | |
7351 | & (~ (HOST_WIDE_INT) 0xffff), | |
7352 | 0, DImode))); | |
7353 | } | |
e2c953b6 | 7354 | |
9ebbca7d GK |
7355 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7356 | DONE; | |
7357 | } | |
a260abc9 DE |
7358 | }") |
7359 | ||
dfbdccdb | 7360 | (define_insn "*booldi3_internal1" |
266eb58a | 7361 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7362 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7363 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7364 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7365 | "TARGET_POWERPC64" |
1fd4e8c1 | 7366 | "@ |
dfbdccdb GK |
7367 | %q3 %0,%1,%2 |
7368 | %q3i %0,%1,%b2 | |
7369 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7370 | |
dfbdccdb | 7371 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7372 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7373 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7374 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7375 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7376 | (const_int 0))) | |
9ebbca7d | 7377 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7378 | "TARGET_64BIT" |
9ebbca7d | 7379 | "@ |
dfbdccdb | 7380 | %q4. %3,%1,%2 |
9ebbca7d GK |
7381 | #" |
7382 | [(set_attr "type" "compare") | |
7383 | (set_attr "length" "4,8")]) | |
7384 | ||
7385 | (define_split | |
7386 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7387 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7388 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7389 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7390 | (const_int 0))) |
9ebbca7d GK |
7391 | (clobber (match_scratch:DI 3 ""))] |
7392 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7393 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7394 | (set (match_dup 0) |
7395 | (compare:CC (match_dup 3) | |
7396 | (const_int 0)))] | |
7397 | "") | |
1fd4e8c1 | 7398 | |
dfbdccdb | 7399 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7400 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7401 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7402 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7403 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7404 | (const_int 0))) | |
9ebbca7d | 7405 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7406 | (match_dup 4))] |
683bdff7 | 7407 | "TARGET_64BIT" |
9ebbca7d | 7408 | "@ |
dfbdccdb | 7409 | %q4. %0,%1,%2 |
9ebbca7d GK |
7410 | #" |
7411 | [(set_attr "type" "compare") | |
7412 | (set_attr "length" "4,8")]) | |
7413 | ||
7414 | (define_split | |
e72247f4 | 7415 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7416 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7417 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7418 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7419 | (const_int 0))) |
75540af0 | 7420 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7421 | (match_dup 4))] |
9ebbca7d | 7422 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7423 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7424 | (set (match_dup 3) |
7425 | (compare:CC (match_dup 0) | |
7426 | (const_int 0)))] | |
7427 | "") | |
1fd4e8c1 | 7428 | |
6ae08853 | 7429 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 7430 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
7431 | |
7432 | (define_split | |
7433 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7434 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7435 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7436 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7437 | "TARGET_POWERPC64" |
dfbdccdb GK |
7438 | [(set (match_dup 0) (match_dup 4)) |
7439 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7440 | " |
7441 | { | |
dfbdccdb | 7442 | rtx i3,i4; |
6ae08853 | 7443 | |
9ebbca7d GK |
7444 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7445 | { | |
7446 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7447 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7448 | 0, DImode); |
dfbdccdb | 7449 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7450 | } |
7451 | else | |
7452 | { | |
dfbdccdb | 7453 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7454 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7455 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7456 | } |
1c563bed | 7457 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7458 | operands[1], i3); |
1c563bed | 7459 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7460 | operands[0], i4); |
1fd4e8c1 RK |
7461 | }") |
7462 | ||
dfbdccdb | 7463 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7464 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7465 | (match_operator:DI 3 "boolean_operator" |
7466 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7467 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7468 | "TARGET_POWERPC64" |
1d328b19 | 7469 | "%q3 %0,%2,%1") |
a473029f | 7470 | |
dfbdccdb | 7471 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7472 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7473 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7474 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7475 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7476 | (const_int 0))) | |
9ebbca7d | 7477 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7478 | "TARGET_64BIT" |
9ebbca7d | 7479 | "@ |
1d328b19 | 7480 | %q4. %3,%2,%1 |
9ebbca7d GK |
7481 | #" |
7482 | [(set_attr "type" "compare") | |
7483 | (set_attr "length" "4,8")]) | |
7484 | ||
7485 | (define_split | |
7486 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7487 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7488 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7489 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7490 | (const_int 0))) |
9ebbca7d GK |
7491 | (clobber (match_scratch:DI 3 ""))] |
7492 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7493 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7494 | (set (match_dup 0) |
7495 | (compare:CC (match_dup 3) | |
7496 | (const_int 0)))] | |
7497 | "") | |
a473029f | 7498 | |
dfbdccdb | 7499 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7500 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7501 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7502 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7503 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7504 | (const_int 0))) | |
9ebbca7d | 7505 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7506 | (match_dup 4))] |
683bdff7 | 7507 | "TARGET_64BIT" |
9ebbca7d | 7508 | "@ |
1d328b19 | 7509 | %q4. %0,%2,%1 |
9ebbca7d GK |
7510 | #" |
7511 | [(set_attr "type" "compare") | |
7512 | (set_attr "length" "4,8")]) | |
7513 | ||
7514 | (define_split | |
e72247f4 | 7515 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7516 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7517 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7518 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7519 | (const_int 0))) |
75540af0 | 7520 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7521 | (match_dup 4))] |
9ebbca7d | 7522 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7523 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7524 | (set (match_dup 3) |
7525 | (compare:CC (match_dup 0) | |
7526 | (const_int 0)))] | |
7527 | "") | |
266eb58a | 7528 | |
dfbdccdb | 7529 | (define_insn "*boolccdi3_internal1" |
a473029f | 7530 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7531 | (match_operator:DI 3 "boolean_operator" |
7532 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7533 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7534 | "TARGET_POWERPC64" |
dfbdccdb | 7535 | "%q3 %0,%1,%2") |
a473029f | 7536 | |
dfbdccdb | 7537 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7538 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7539 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7540 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7541 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7542 | (const_int 0))) | |
9ebbca7d | 7543 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7544 | "TARGET_64BIT" |
9ebbca7d | 7545 | "@ |
dfbdccdb | 7546 | %q4. %3,%1,%2 |
9ebbca7d GK |
7547 | #" |
7548 | [(set_attr "type" "compare") | |
7549 | (set_attr "length" "4,8")]) | |
7550 | ||
7551 | (define_split | |
7552 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7553 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7554 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7555 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7556 | (const_int 0))) |
9ebbca7d GK |
7557 | (clobber (match_scratch:DI 3 ""))] |
7558 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7559 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7560 | (set (match_dup 0) |
7561 | (compare:CC (match_dup 3) | |
7562 | (const_int 0)))] | |
7563 | "") | |
266eb58a | 7564 | |
dfbdccdb | 7565 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7566 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7567 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7568 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7569 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7570 | (const_int 0))) | |
9ebbca7d | 7571 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7572 | (match_dup 4))] |
683bdff7 | 7573 | "TARGET_64BIT" |
9ebbca7d | 7574 | "@ |
dfbdccdb | 7575 | %q4. %0,%1,%2 |
9ebbca7d GK |
7576 | #" |
7577 | [(set_attr "type" "compare") | |
7578 | (set_attr "length" "4,8")]) | |
7579 | ||
7580 | (define_split | |
e72247f4 | 7581 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7582 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7583 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7584 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7585 | (const_int 0))) |
75540af0 | 7586 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7587 | (match_dup 4))] |
9ebbca7d | 7588 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7589 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7590 | (set (match_dup 3) |
7591 | (compare:CC (match_dup 0) | |
7592 | (const_int 0)))] | |
7593 | "") | |
dfbdccdb | 7594 | \f |
1fd4e8c1 | 7595 | ;; Now define ways of moving data around. |
4697a36c MM |
7596 | |
7597 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7598 | ;; The output of this could be r0, but we make a very strong |
7599 | ;; preference for a base register because it will usually | |
7600 | ;; be needed there. | |
4697a36c | 7601 | (define_insn "elf_high" |
9ebbca7d | 7602 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7603 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7604 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7605 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7606 | |
7607 | (define_insn "elf_low" | |
9ebbca7d GK |
7608 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7609 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7610 | (match_operand 2 "" "")))] |
0ad91047 | 7611 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7612 | "@ |
7613 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7614 | {ai|addic} %0,%1,%K2") |
4697a36c | 7615 | |
ee890fe2 SS |
7616 | ;; Mach-O PIC trickery. |
7617 | (define_insn "macho_high" | |
7618 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
7619 | (high:SI (match_operand 1 "" "")))] | |
7620 | "TARGET_MACHO && ! TARGET_64BIT" | |
7621 | "{liu|lis} %0,ha16(%1)") | |
7622 | ||
7623 | (define_insn "macho_low" | |
7624 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
7625 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
7626 | (match_operand 2 "" "")))] | |
7627 | "TARGET_MACHO && ! TARGET_64BIT" | |
7628 | "@ | |
7629 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
7630 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
7631 | ||
766a866c MM |
7632 | ;; Set up a register with a value from the GOT table |
7633 | ||
7634 | (define_expand "movsi_got" | |
52d3af72 | 7635 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7636 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
615158e2 | 7637 | (match_dup 2)] UNSPEC_MOVSI_GOT))] |
f607bc57 | 7638 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7639 | " |
7640 | { | |
38c1f2d7 MM |
7641 | if (GET_CODE (operands[1]) == CONST) |
7642 | { | |
7643 | rtx offset = const0_rtx; | |
7644 | HOST_WIDE_INT value; | |
7645 | ||
7646 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7647 | value = INTVAL (offset); | |
7648 | if (value != 0) | |
7649 | { | |
677a9668 | 7650 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7651 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7652 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7653 | DONE; | |
7654 | } | |
7655 | } | |
7656 | ||
c4c40373 | 7657 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7658 | }") |
7659 | ||
84f414bc | 7660 | (define_insn "*movsi_got_internal" |
52d3af72 | 7661 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d | 7662 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7663 | (match_operand:SI 2 "gpc_reg_operand" "b")] |
7664 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7665 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7666 | "{l|lwz} %0,%a1@got(%2)" |
7667 | [(set_attr "type" "load")]) | |
7668 | ||
b22b9b3e JL |
7669 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7670 | ;; didn't get allocated to a hard register. | |
6ae08853 | 7671 | (define_split |
75540af0 | 7672 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7673 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7674 | (match_operand:SI 2 "memory_operand" "")] |
7675 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7676 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7677 | && flag_pic == 1 |
7678 | && (reload_in_progress || reload_completed)" | |
7679 | [(set (match_dup 0) (match_dup 2)) | |
615158e2 JJ |
7680 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] |
7681 | UNSPEC_MOVSI_GOT))] | |
b22b9b3e JL |
7682 | "") |
7683 | ||
1fd4e8c1 RK |
7684 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7685 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7686 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7687 | ;; integers in the TOC. | |
7688 | (define_expand "movsi" | |
7689 | [(set (match_operand:SI 0 "general_operand" "") | |
7690 | (match_operand:SI 1 "any_operand" ""))] | |
7691 | "" | |
fb4d4348 | 7692 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7693 | |
ee890fe2 SS |
7694 | (define_insn "movsi_low" |
7695 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7696 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7697 | (match_operand 2 "" ""))))] |
7698 | "TARGET_MACHO && ! TARGET_64BIT" | |
7699 | "{l|lwz} %0,lo16(%2)(%1)" | |
7700 | [(set_attr "type" "load") | |
7701 | (set_attr "length" "4")]) | |
7702 | ||
c859cda6 | 7703 | (define_insn "movsi_low_st" |
f585a356 | 7704 | [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7705 | (match_operand 2 "" ""))) |
7706 | (match_operand:SI 0 "gpc_reg_operand" "r"))] | |
7707 | "TARGET_MACHO && ! TARGET_64BIT" | |
7708 | "{st|stw} %0,lo16(%2)(%1)" | |
7709 | [(set_attr "type" "store") | |
7710 | (set_attr "length" "4")]) | |
7711 | ||
7712 | (define_insn "movdf_low" | |
234e114c | 7713 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7714 | (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7715 | (match_operand 2 "" ""))))] |
a3170dc6 | 7716 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
234e114c DJ |
7717 | "* |
7718 | { | |
7719 | switch (which_alternative) | |
7720 | { | |
7721 | case 0: | |
7722 | return \"lfd %0,lo16(%2)(%1)\"; | |
7723 | case 1: | |
7724 | { | |
7725 | rtx operands2[4]; | |
7726 | operands2[0] = operands[0]; | |
7727 | operands2[1] = operands[1]; | |
7728 | operands2[2] = operands[2]; | |
683bdff7 | 7729 | if (TARGET_POWERPC64 && TARGET_32BIT) |
a3c9585f | 7730 | /* Note, old assemblers didn't support relocation here. */ |
683bdff7 | 7731 | return \"ld %0,lo16(%2)(%1)\"; |
ab82a49f | 7732 | else |
683bdff7 | 7733 | { |
6ae08853 | 7734 | operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
683bdff7 FJ |
7735 | output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); |
7736 | #if TARGET_MACHO | |
7737 | if (MACHO_DYNAMIC_NO_PIC_P) | |
7738 | output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands); | |
6ae08853 | 7739 | else |
683bdff7 FJ |
7740 | /* We cannot rely on ha16(low half)==ha16(high half), alas, |
7741 | although in practice it almost always is. */ | |
7742 | output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); | |
ab82a49f | 7743 | #endif |
683bdff7 FJ |
7744 | return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); |
7745 | } | |
234e114c DJ |
7746 | } |
7747 | default: | |
7748 | abort(); | |
7749 | } | |
7750 | }" | |
c859cda6 | 7751 | [(set_attr "type" "load") |
234e114c | 7752 | (set_attr "length" "4,12")]) |
c859cda6 DJ |
7753 | |
7754 | (define_insn "movdf_low_st" | |
f585a356 | 7755 | [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7756 | (match_operand 2 "" ""))) |
7757 | (match_operand:DF 0 "gpc_reg_operand" "f"))] | |
a3170dc6 | 7758 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
c859cda6 DJ |
7759 | "stfd %0,lo16(%2)(%1)" |
7760 | [(set_attr "type" "store") | |
7761 | (set_attr "length" "4")]) | |
7762 | ||
7763 | (define_insn "movsf_low" | |
fd3b43f2 | 7764 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7765 | (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7766 | (match_operand 2 "" ""))))] |
a3170dc6 | 7767 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
fd3b43f2 DJ |
7768 | "@ |
7769 | lfs %0,lo16(%2)(%1) | |
7770 | {l|lwz} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
7771 | [(set_attr "type" "load") |
7772 | (set_attr "length" "4")]) | |
7773 | ||
7774 | (define_insn "movsf_low_st" | |
f585a356 | 7775 | [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7776 | (match_operand 2 "" ""))) |
fd3b43f2 | 7777 | (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] |
a3170dc6 | 7778 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
fd3b43f2 DJ |
7779 | "@ |
7780 | stfs %0,lo16(%2)(%1) | |
7781 | {st|stw} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
7782 | [(set_attr "type" "store") |
7783 | (set_attr "length" "4")]) | |
7784 | ||
acad7ed3 | 7785 | (define_insn "*movsi_internal1" |
a004eb82 AH |
7786 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
7787 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] | |
19d5775a RK |
7788 | "gpc_reg_operand (operands[0], SImode) |
7789 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7790 | "@ |
deb9225a | 7791 | mr %0,%1 |
b9442c72 | 7792 | {cal|la} %0,%a1 |
ca7f5001 RK |
7793 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7794 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7795 | {lil|li} %0,%1 |
802a0058 | 7796 | {liu|lis} %0,%v1 |
beaec479 | 7797 | # |
aee86b38 | 7798 | {cal|la} %0,%a1 |
1fd4e8c1 | 7799 | mf%1 %0 |
5c23c401 | 7800 | mt%0 %1 |
e76e75bb | 7801 | mt%0 %1 |
a004eb82 | 7802 | mt%0 %1 |
e34eaae5 | 7803 | {cror 0,0,0|nop}" |
02ca7595 | 7804 | [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") |
a004eb82 | 7805 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7806 | |
77fa0940 RK |
7807 | ;; Split a load of a large constant into the appropriate two-insn |
7808 | ;; sequence. | |
7809 | ||
7810 | (define_split | |
7811 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7812 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7813 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7814 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7815 | [(set (match_dup 0) | |
7816 | (match_dup 2)) | |
7817 | (set (match_dup 0) | |
7818 | (ior:SI (match_dup 0) | |
7819 | (match_dup 3)))] | |
7820 | " | |
af8cb5c5 DE |
7821 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
7822 | ||
7823 | if (tem == operands[0]) | |
7824 | DONE; | |
7825 | else | |
7826 | FAIL; | |
77fa0940 RK |
7827 | }") |
7828 | ||
acad7ed3 | 7829 | (define_insn "*movsi_internal2" |
bb84cb12 DE |
7830 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
7831 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r") | |
1fd4e8c1 | 7832 | (const_int 0))) |
bb84cb12 | 7833 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
4b8a63d6 | 7834 | "TARGET_32BIT" |
9ebbca7d | 7835 | "@ |
bb84cb12 | 7836 | {cmpi|cmpwi} %2,%0,0 |
9ebbca7d GK |
7837 | mr. %0,%1 |
7838 | #" | |
bb84cb12 DE |
7839 | [(set_attr "type" "cmp,compare,cmp") |
7840 | (set_attr "length" "4,4,8")]) | |
7841 | ||
9ebbca7d GK |
7842 | (define_split |
7843 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7844 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7845 | (const_int 0))) | |
7846 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
4b8a63d6 | 7847 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
7848 | [(set (match_dup 0) (match_dup 1)) |
7849 | (set (match_dup 2) | |
7850 | (compare:CC (match_dup 0) | |
7851 | (const_int 0)))] | |
7852 | "") | |
bb84cb12 | 7853 | \f |
1fd4e8c1 RK |
7854 | (define_expand "movhi" |
7855 | [(set (match_operand:HI 0 "general_operand" "") | |
7856 | (match_operand:HI 1 "any_operand" ""))] | |
7857 | "" | |
fb4d4348 | 7858 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 | 7859 | |
e34eaae5 | 7860 | (define_insn "*movhi_internal" |
fb81d7ce RK |
7861 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7862 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7863 | "gpc_reg_operand (operands[0], HImode) |
7864 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7865 | "@ |
deb9225a | 7866 | mr %0,%1 |
1fd4e8c1 RK |
7867 | lhz%U1%X1 %0,%1 |
7868 | sth%U0%X0 %1,%0 | |
19d5775a | 7869 | {lil|li} %0,%w1 |
1fd4e8c1 | 7870 | mf%1 %0 |
e76e75bb | 7871 | mt%0 %1 |
fb81d7ce | 7872 | mt%0 %1 |
e34eaae5 | 7873 | {cror 0,0,0|nop}" |
02ca7595 | 7874 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7875 | |
7876 | (define_expand "movqi" | |
7877 | [(set (match_operand:QI 0 "general_operand" "") | |
7878 | (match_operand:QI 1 "any_operand" ""))] | |
7879 | "" | |
fb4d4348 | 7880 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 | 7881 | |
e34eaae5 | 7882 | (define_insn "*movqi_internal" |
fb81d7ce RK |
7883 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7884 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7885 | "gpc_reg_operand (operands[0], QImode) |
7886 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7887 | "@ |
deb9225a | 7888 | mr %0,%1 |
1fd4e8c1 RK |
7889 | lbz%U1%X1 %0,%1 |
7890 | stb%U0%X0 %1,%0 | |
19d5775a | 7891 | {lil|li} %0,%1 |
1fd4e8c1 | 7892 | mf%1 %0 |
e76e75bb | 7893 | mt%0 %1 |
fb81d7ce | 7894 | mt%0 %1 |
e34eaae5 | 7895 | {cror 0,0,0|nop}" |
02ca7595 | 7896 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7897 | \f |
7898 | ;; Here is how to move condition codes around. When we store CC data in | |
7899 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7900 | ;; This lets us not shift in the most common case of CR0. | |
7901 | (define_expand "movcc" | |
7902 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7903 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7904 | "" | |
7905 | "") | |
7906 | ||
a65c591c | 7907 | (define_insn "*movcc_internal1" |
b54cf83a DE |
7908 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") |
7909 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] | |
1fd4e8c1 RK |
7910 | "register_operand (operands[0], CCmode) |
7911 | || register_operand (operands[1], CCmode)" | |
7912 | "@ | |
7913 | mcrf %0,%1 | |
7914 | mtcrf 128,%1 | |
ca7f5001 | 7915 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
2c4a9cff DE |
7916 | mfcr %0%Q1 |
7917 | mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 | |
deb9225a | 7918 | mr %0,%1 |
b54cf83a | 7919 | mf%1 %0 |
b991a865 GK |
7920 | mt%0 %1 |
7921 | mt%0 %1 | |
ca7f5001 RK |
7922 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7923 | {st%U0%U1|stw%U0%U1} %1,%0" | |
2c4a9cff DE |
7924 | [(set (attr "type") |
7925 | (cond [(eq_attr "alternative" "0") | |
7926 | (const_string "cr_logical") | |
7927 | (eq_attr "alternative" "1,2") | |
7928 | (const_string "mtcr") | |
7929 | (eq_attr "alternative" "5,7") | |
7930 | (const_string "integer") | |
7931 | (eq_attr "alternative" "6") | |
7932 | (const_string "mfjmpr") | |
7933 | (eq_attr "alternative" "8") | |
7934 | (const_string "mtjmpr") | |
7935 | (eq_attr "alternative" "9") | |
7936 | (const_string "load") | |
7937 | (eq_attr "alternative" "10") | |
7938 | (const_string "store") | |
7939 | (ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
7940 | (const_string "mfcrf") | |
7941 | ] | |
7942 | (const_string "mfcr"))) | |
b991a865 | 7943 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7944 | \f |
e52e05ca MM |
7945 | ;; For floating-point, we normally deal with the floating-point registers |
7946 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7947 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7948 | ;; value is a simple constant or already in memory, we deal with this by | |
7949 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7950 | (define_expand "movsf" |
7951 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7952 | (match_operand:SF 1 "any_operand" ""))] | |
7953 | "" | |
fb4d4348 | 7954 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7955 | |
1fd4e8c1 | 7956 | (define_split |
cd2b37d9 | 7957 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7958 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7959 | "reload_completed |
5ae4759c MM |
7960 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7961 | || (GET_CODE (operands[0]) == SUBREG | |
7962 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7963 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7964 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7965 | " |
7966 | { | |
7967 | long l; | |
7968 | REAL_VALUE_TYPE rv; | |
7969 | ||
7970 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7971 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7972 | |
f99f88e0 DE |
7973 | if (! TARGET_POWERPC64) |
7974 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7975 | else | |
7976 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7977 | |
2496c7bd | 7978 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7979 | }") |
7980 | ||
c4c40373 | 7981 | (define_insn "*movsf_hardfloat" |
ae6669e7 DJ |
7982 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r") |
7983 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] | |
d14a6d05 | 7984 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7985 | || gpc_reg_operand (operands[1], SFmode)) |
7986 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 7987 | "@ |
f99f88e0 DE |
7988 | mr %0,%1 |
7989 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7990 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7991 | fmr %0,%1 |
7992 | lfs%U1%X1 %0,%1 | |
c4c40373 | 7993 | stfs%U0%X0 %1,%0 |
b991a865 GK |
7994 | mt%0 %1 |
7995 | mt%0 %1 | |
7996 | mf%1 %0 | |
e0740893 | 7997 | {cror 0,0,0|nop} |
c4c40373 MM |
7998 | # |
7999 | #" | |
ae6669e7 DJ |
8000 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*") |
8001 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 8002 | |
c4c40373 | 8003 | (define_insn "*movsf_softfloat" |
dd0fbae2 MK |
8004 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") |
8005 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
d14a6d05 | 8006 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
8007 | || gpc_reg_operand (operands[1], SFmode)) |
8008 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
8009 | "@ |
8010 | mr %0,%1 | |
b991a865 GK |
8011 | mt%0 %1 |
8012 | mt%0 %1 | |
8013 | mf%1 %0 | |
d14a6d05 MM |
8014 | {l%U1%X1|lwz%U1%X1} %0,%1 |
8015 | {st%U0%X0|stw%U0%X0} %1,%0 | |
8016 | {lil|li} %0,%1 | |
802a0058 | 8017 | {liu|lis} %0,%v1 |
aee86b38 | 8018 | {cal|la} %0,%a1 |
c4c40373 | 8019 | # |
dd0fbae2 MK |
8020 | # |
8021 | {cror 0,0,0|nop}" | |
8022 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") | |
8023 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
d14a6d05 | 8024 | |
1fd4e8c1 RK |
8025 | \f |
8026 | (define_expand "movdf" | |
8027 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
8028 | (match_operand:DF 1 "any_operand" ""))] | |
8029 | "" | |
fb4d4348 | 8030 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
8031 | |
8032 | (define_split | |
cd2b37d9 | 8033 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 8034 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 8035 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8036 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8037 | || (GET_CODE (operands[0]) == SUBREG | |
8038 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8039 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
8040 | [(set (match_dup 2) (match_dup 4)) |
8041 | (set (match_dup 3) (match_dup 1))] | |
8042 | " | |
8043 | { | |
5ae4759c | 8044 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
8045 | HOST_WIDE_INT value = INTVAL (operands[1]); |
8046 | ||
5ae4759c MM |
8047 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
8048 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
8049 | #if HOST_BITS_PER_WIDE_INT == 32 |
8050 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
8051 | #else | |
8052 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 8053 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 8054 | #endif |
c4c40373 MM |
8055 | }") |
8056 | ||
c4c40373 MM |
8057 | (define_split |
8058 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
8059 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 8060 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8061 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8062 | || (GET_CODE (operands[0]) == SUBREG | |
8063 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8064 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
8065 | [(set (match_dup 2) (match_dup 4)) |
8066 | (set (match_dup 3) (match_dup 5))] | |
8067 | " | |
8068 | { | |
5ae4759c | 8069 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
8070 | long l[2]; |
8071 | REAL_VALUE_TYPE rv; | |
8072 | ||
8073 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8074 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8075 | ||
5ae4759c MM |
8076 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
8077 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
8078 | operands[4] = gen_int_mode (l[endian], SImode); |
8079 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
8080 | }") |
8081 | ||
efc08378 DE |
8082 | (define_split |
8083 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 8084 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 8085 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8086 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8087 | || (GET_CODE (operands[0]) == SUBREG | |
8088 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8089 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 8090 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 8091 | " |
a260abc9 DE |
8092 | { |
8093 | int endian = (WORDS_BIG_ENDIAN == 0); | |
8094 | long l[2]; | |
8095 | REAL_VALUE_TYPE rv; | |
4977bab6 | 8096 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 8097 | HOST_WIDE_INT val; |
4977bab6 | 8098 | #endif |
a260abc9 DE |
8099 | |
8100 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8101 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8102 | ||
8103 | operands[2] = gen_lowpart (DImode, operands[0]); | |
8104 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 8105 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
8106 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
8107 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 8108 | |
f5264b52 | 8109 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 8110 | #else |
a260abc9 | 8111 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 8112 | #endif |
a260abc9 | 8113 | }") |
efc08378 | 8114 | |
4eae5fe1 | 8115 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 8116 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
8117 | ;; a non-offsettable memref, but also it is less efficient than loading |
8118 | ;; the constant into an FP register, since it will probably be used there. | |
8119 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
8120 | ;; of handling these non-offsettable values. | |
c4c40373 | 8121 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
8122 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
8123 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 8124 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8125 | && (gpc_reg_operand (operands[0], DFmode) |
8126 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
8127 | "* |
8128 | { | |
8129 | switch (which_alternative) | |
8130 | { | |
a260abc9 | 8131 | default: |
a6c2a102 | 8132 | abort (); |
e7113111 RK |
8133 | case 0: |
8134 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
8135 | the first register operand 0 is the same as the second register |
8136 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 8137 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 8138 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 8139 | else |
deb9225a | 8140 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 8141 | case 1: |
819e019c EC |
8142 | if (GET_CODE (operands[1]) == MEM |
8143 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0), | |
8144 | reload_completed || reload_in_progress) | |
8145 | || GET_CODE (XEXP (operands[1], 0)) == REG | |
8146 | || GET_CODE (XEXP (operands[1], 0)) == LO_SUM | |
69f51a21 | 8147 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC |
819e019c | 8148 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) |
000034eb DE |
8149 | { |
8150 | /* If the low-address word is used in the address, we must load | |
8151 | it last. Otherwise, load it first. Note that we cannot have | |
8152 | auto-increment in that case since the address register is | |
8153 | known to be dead. */ | |
8154 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8155 | operands[1], 0)) | |
8156 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
8157 | else | |
8158 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8159 | } | |
e7113111 | 8160 | else |
000034eb DE |
8161 | { |
8162 | rtx addreg; | |
8163 | ||
000034eb DE |
8164 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
8165 | if (refers_to_regno_p (REGNO (operands[0]), | |
8166 | REGNO (operands[0]) + 1, | |
8167 | operands[1], 0)) | |
8168 | { | |
8169 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 8170 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 8171 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 8172 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
8173 | } |
8174 | else | |
8175 | { | |
2b97222d | 8176 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 8177 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8178 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
8179 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8180 | return \"\"; | |
8181 | } | |
8182 | } | |
e7113111 | 8183 | case 2: |
819e019c EC |
8184 | if (GET_CODE (operands[0]) == MEM |
8185 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0), | |
8186 | reload_completed || reload_in_progress) | |
8187 | || GET_CODE (XEXP (operands[0], 0)) == REG | |
8188 | || GET_CODE (XEXP (operands[0], 0)) == LO_SUM | |
69f51a21 | 8189 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC |
819e019c | 8190 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)) |
000034eb DE |
8191 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8192 | else | |
8193 | { | |
8194 | rtx addreg; | |
8195 | ||
000034eb | 8196 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8197 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8198 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8199 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8200 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8201 | return \"\"; | |
8202 | } | |
e7113111 | 8203 | case 3: |
914a7297 | 8204 | return \"fmr %0,%1\"; |
e7113111 | 8205 | case 4: |
914a7297 | 8206 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 8207 | case 5: |
914a7297 | 8208 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 8209 | case 6: |
c4c40373 | 8210 | case 7: |
c4c40373 | 8211 | case 8: |
914a7297 | 8212 | return \"#\"; |
e7113111 RK |
8213 | } |
8214 | }" | |
914a7297 DE |
8215 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*") |
8216 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) | |
51b8fc2c | 8217 | |
c4c40373 | 8218 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8219 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8220 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
a3170dc6 | 8221 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8222 | && (gpc_reg_operand (operands[0], DFmode) |
8223 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8224 | "* |
8225 | { | |
8226 | switch (which_alternative) | |
8227 | { | |
a260abc9 | 8228 | default: |
a6c2a102 | 8229 | abort (); |
dc4f83ca MM |
8230 | case 0: |
8231 | /* We normally copy the low-numbered register first. However, if | |
8232 | the first register operand 0 is the same as the second register of | |
8233 | operand 1, we must copy in the opposite order. */ | |
8234 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8235 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8236 | else | |
8237 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8238 | case 1: | |
3cb999d8 DE |
8239 | /* If the low-address word is used in the address, we must load |
8240 | it last. Otherwise, load it first. Note that we cannot have | |
8241 | auto-increment in that case since the address register is | |
8242 | known to be dead. */ | |
dc4f83ca | 8243 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8244 | operands[1], 0)) |
dc4f83ca MM |
8245 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8246 | else | |
8247 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8248 | case 2: | |
8249 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8250 | case 3: | |
c4c40373 MM |
8251 | case 4: |
8252 | case 5: | |
dc4f83ca MM |
8253 | return \"#\"; |
8254 | } | |
8255 | }" | |
c4c40373 MM |
8256 | [(set_attr "type" "*,load,store,*,*,*") |
8257 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 8258 | |
d2288d5d HP |
8259 | ; ld/std require word-aligned displacements -> 'Y' constraint. |
8260 | ; List Y->r and r->Y before r->r for reload. | |
c4c40373 | 8261 | (define_insn "*movdf_hardfloat64" |
ae6669e7 DJ |
8262 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r") |
8263 | (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] | |
a3170dc6 | 8264 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8265 | && (gpc_reg_operand (operands[0], DFmode) |
8266 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8267 | "@ |
96bb8ed3 | 8268 | std%U0%X0 %1,%0 |
3364872d FJ |
8269 | ld%U1%X1 %0,%1 |
8270 | mr %0,%1 | |
3d5570cb | 8271 | fmr %0,%1 |
f63184ac | 8272 | lfd%U1%X1 %0,%1 |
914a7297 DE |
8273 | stfd%U0%X0 %1,%0 |
8274 | mt%0 %1 | |
8275 | mf%1 %0 | |
e0740893 | 8276 | {cror 0,0,0|nop} |
914a7297 DE |
8277 | # |
8278 | # | |
8279 | #" | |
ae6669e7 DJ |
8280 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*") |
8281 | (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 8282 | |
c4c40373 | 8283 | (define_insn "*movdf_softfloat64" |
d2288d5d HP |
8284 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") |
8285 | (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] | |
a3170dc6 | 8286 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8287 | && (gpc_reg_operand (operands[0], DFmode) |
8288 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca | 8289 | "@ |
d2288d5d HP |
8290 | ld%U1%X1 %0,%1 |
8291 | std%U0%X0 %1,%0 | |
dc4f83ca | 8292 | mr %0,%1 |
914a7297 DE |
8293 | mt%0 %1 |
8294 | mf%1 %0 | |
c4c40373 MM |
8295 | # |
8296 | # | |
e2d0915c | 8297 | # |
e0740893 | 8298 | {cror 0,0,0|nop}" |
d2288d5d | 8299 | [(set_attr "type" "load,store,*,*,*,*,*,*,*") |
e2d0915c | 8300 | (set_attr "length" "4,4,4,4,4,8,12,16,4")]) |
1fd4e8c1 | 8301 | \f |
06f4e019 DE |
8302 | (define_expand "movtf" |
8303 | [(set (match_operand:TF 0 "general_operand" "") | |
8304 | (match_operand:TF 1 "any_operand" ""))] | |
39e63627 GK |
8305 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8306 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8307 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
8308 | ||
a9baceb1 GK |
8309 | ; It's important to list the o->f and f->o moves before f->f because |
8310 | ; otherwise reload, given m->f, will try to pick f->f and reload it, | |
112ccb83 | 8311 | ; which doesn't make progress. Likewise r->o<> must be before r->r. |
a9baceb1 | 8312 | (define_insn_and_split "*movtf_internal" |
112ccb83 GK |
8313 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,o<>,r") |
8314 | (match_operand:TF 1 "input_operand" "f,o,f,mGHF,r,r"))] | |
39e63627 GK |
8315 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8316 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
8317 | && (gpc_reg_operand (operands[0], TFmode) |
8318 | || gpc_reg_operand (operands[1], TFmode))" | |
a9baceb1 | 8319 | "#" |
ecb62ae7 | 8320 | "&& reload_completed" |
a9baceb1 GK |
8321 | [(pc)] |
8322 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } | |
112ccb83 | 8323 | [(set_attr "length" "8,8,8,20,20,16")]) |
06f4e019 | 8324 | |
ecb62ae7 GK |
8325 | (define_expand "extenddftf2" |
8326 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8327 | (float_extend:TF (match_operand:DF 1 "input_operand" ""))) | |
8328 | (use (match_dup 2))])] | |
39e63627 GK |
8329 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8330 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8331 | { |
ecb62ae7 GK |
8332 | operands[2] = CONST0_RTX (DFmode); |
8333 | }) | |
06f4e019 | 8334 | |
ecb62ae7 GK |
8335 | (define_insn_and_split "*extenddftf2_internal" |
8336 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") | |
8337 | (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) | |
8338 | (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))] | |
39e63627 GK |
8339 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8340 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8341 | "#" |
8342 | "&& reload_completed" | |
8343 | [(pc)] | |
06f4e019 | 8344 | { |
ecb62ae7 GK |
8345 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; |
8346 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
8347 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), | |
8348 | operands[1]); | |
8349 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), | |
8350 | operands[2]); | |
8351 | DONE; | |
6ae08853 | 8352 | }) |
ecb62ae7 GK |
8353 | |
8354 | (define_expand "extendsftf2" | |
8355 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8356 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
8357 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8358 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8359 | { | |
8360 | rtx tmp = gen_reg_rtx (DFmode); | |
8361 | emit_insn (gen_extendsfdf2 (tmp, operands[1])); | |
8362 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8363 | DONE; | |
8364 | }) | |
06f4e019 DE |
8365 | |
8366 | (define_insn "trunctfdf2" | |
8367 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8368 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8369 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8370 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8371 | "fadd %0,%1,%L1" |
8372 | [(set_attr "type" "fp") | |
ecb62ae7 | 8373 | (set_attr "length" "4")]) |
06f4e019 DE |
8374 | |
8375 | (define_insn_and_split "trunctfsf2" | |
8376 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
8377 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8378 | (clobber (match_scratch:DF 2 "=f"))] | |
39e63627 GK |
8379 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8380 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8381 | "#" |
ea112fc4 | 8382 | "&& reload_completed" |
06f4e019 DE |
8383 | [(set (match_dup 2) |
8384 | (float_truncate:DF (match_dup 1))) | |
8385 | (set (match_dup 0) | |
8386 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 8387 | "") |
06f4e019 | 8388 | |
0c90aa3c | 8389 | (define_expand "floatsitf2" |
ea112fc4 | 8390 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
0c90aa3c | 8391 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))] |
39e63627 GK |
8392 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8393 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
0c90aa3c GK |
8394 | { |
8395 | rtx tmp = gen_reg_rtx (DFmode); | |
8396 | expand_float (tmp, operands[1], false); | |
8397 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8398 | DONE; | |
8399 | }) | |
06f4e019 | 8400 | |
ecb62ae7 GK |
8401 | ; fadd, but rounding towards zero. |
8402 | ; This is probably not the optimal code sequence. | |
8403 | (define_insn "fix_trunc_helper" | |
8404 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8405 | (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] | |
8406 | UNSPEC_FIX_TRUNC_TF)) | |
8407 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] | |
8408 | "TARGET_HARD_FLOAT && TARGET_FPRS" | |
8409 | "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" | |
8410 | [(set_attr "type" "fp") | |
8411 | (set_attr "length" "20")]) | |
8412 | ||
0c90aa3c | 8413 | (define_expand "fix_trunctfsi2" |
ecb62ae7 GK |
8414 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
8415 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) | |
8416 | (clobber (match_dup 2)) | |
8417 | (clobber (match_dup 3)) | |
8418 | (clobber (match_dup 4)) | |
8419 | (clobber (match_dup 5))])] | |
8420 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8421 | && (TARGET_POWER2 || TARGET_POWERPC) | |
8422 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8423 | { | |
8424 | operands[2] = gen_reg_rtx (DFmode); | |
8425 | operands[3] = gen_reg_rtx (DFmode); | |
8426 | operands[4] = gen_reg_rtx (DImode); | |
8427 | operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
8428 | }) | |
8429 | ||
8430 | (define_insn_and_split "*fix_trunctfsi2_internal" | |
61c07d3c | 8431 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ecb62ae7 GK |
8432 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8433 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) | |
8434 | (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) | |
8435 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) | |
8436 | (clobber (match_operand:DI 5 "memory_operand" "=o"))] | |
39e63627 GK |
8437 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8438 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8439 | "#" |
8440 | "&& reload_completed" | |
8441 | [(pc)] | |
0c90aa3c | 8442 | { |
ecb62ae7 GK |
8443 | rtx lowword; |
8444 | emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); | |
8445 | ||
8446 | if (GET_CODE (operands[5]) != MEM) | |
8447 | abort(); | |
8448 | lowword = XEXP (operands[5], 0); | |
8449 | if (WORDS_BIG_ENDIAN) | |
8450 | lowword = plus_constant (lowword, 4); | |
8451 | ||
8452 | emit_insn (gen_fctiwz (operands[4], operands[2])); | |
8453 | emit_move_insn (operands[5], operands[4]); | |
8454 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
0c90aa3c GK |
8455 | DONE; |
8456 | }) | |
06f4e019 DE |
8457 | |
8458 | (define_insn "negtf2" | |
8459 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8460 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8461 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8462 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8463 | "* |
8464 | { | |
8465 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8466 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8467 | else | |
8468 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8469 | }" | |
8470 | [(set_attr "type" "fp") | |
8471 | (set_attr "length" "8")]) | |
8472 | ||
1a402dc1 | 8473 | (define_expand "abstf2" |
06f4e019 DE |
8474 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8475 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8476 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8477 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8478 | " |
06f4e019 | 8479 | { |
1a402dc1 AM |
8480 | rtx label = gen_label_rtx (); |
8481 | emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); | |
8482 | emit_label (label); | |
8483 | DONE; | |
8484 | }") | |
06f4e019 | 8485 | |
1a402dc1 | 8486 | (define_expand "abstf2_internal" |
06f4e019 | 8487 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
1a402dc1 AM |
8488 | (match_operand:TF 1 "gpc_reg_operand" "f")) |
8489 | (set (match_dup 3) (match_dup 5)) | |
8490 | (set (match_dup 5) (abs:DF (match_dup 5))) | |
8491 | (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) | |
8492 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
8493 | (label_ref (match_operand 2 "" "")) | |
8494 | (pc))) | |
8495 | (set (match_dup 6) (neg:DF (match_dup 6)))] | |
39e63627 GK |
8496 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8497 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8498 | " |
06f4e019 | 8499 | { |
1a402dc1 AM |
8500 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); |
8501 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
8502 | operands[3] = gen_reg_rtx (DFmode); | |
8503 | operands[4] = gen_reg_rtx (CCFPmode); | |
8504 | operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
8505 | operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
8506 | }") | |
06f4e019 | 8507 | \f |
1fd4e8c1 RK |
8508 | ;; Next come the multi-word integer load and store and the load and store |
8509 | ;; multiple insns. | |
8510 | (define_expand "movdi" | |
8511 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8512 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 8513 | "" |
fb4d4348 | 8514 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 8515 | |
112ccb83 GK |
8516 | ; List r->r after r->"o<>", otherwise reload will try to reload a |
8517 | ; non-offsettable address by using r->r which won't make progress. | |
acad7ed3 | 8518 | (define_insn "*movdi_internal32" |
112ccb83 GK |
8519 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,f,f,m,r") |
8520 | (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] | |
a260abc9 | 8521 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8522 | && (gpc_reg_operand (operands[0], DImode) |
8523 | || gpc_reg_operand (operands[1], DImode))" | |
112ccb83 GK |
8524 | "@ |
8525 | # | |
8526 | # | |
8527 | # | |
8528 | fmr %0,%1 | |
8529 | lfd%U1%X1 %0,%1 | |
8530 | stfd%U0%X0 %1,%0 | |
8531 | #" | |
8532 | [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")]) | |
4e74d8ec MM |
8533 | |
8534 | (define_split | |
8535 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8536 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8537 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8538 | [(set (match_dup 2) (match_dup 4)) |
8539 | (set (match_dup 3) (match_dup 1))] | |
8540 | " | |
8541 | { | |
5f59ecb7 | 8542 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8543 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8544 | DImode); | |
8545 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8546 | DImode); | |
75d39459 | 8547 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8548 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8549 | #else |
5f59ecb7 | 8550 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8551 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8552 | #endif |
4e74d8ec MM |
8553 | }") |
8554 | ||
3a1f863f DE |
8555 | (define_split |
8556 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8557 | (match_operand:DI 1 "input_operand" ""))] | |
6ae08853 | 8558 | "reload_completed && !TARGET_POWERPC64 |
3a1f863f | 8559 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8560 | [(pc)] |
8561 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
3a1f863f | 8562 | |
6fc19dc9 AM |
8563 | (define_split |
8564 | [(set (match_operand:TI 0 "gpc_reg_operand" "") | |
8565 | (match_operand:TI 1 "const_double_operand" ""))] | |
8566 | "TARGET_POWERPC64" | |
8567 | [(set (match_dup 2) (match_dup 4)) | |
8568 | (set (match_dup 3) (match_dup 5))] | |
8569 | " | |
8570 | { | |
8571 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, | |
8572 | TImode); | |
8573 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8574 | TImode); | |
8575 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
8576 | { | |
8577 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8578 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8579 | } | |
8580 | else if (GET_CODE (operands[1]) == CONST_INT) | |
8581 | { | |
8582 | operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); | |
8583 | operands[5] = operands[1]; | |
8584 | } | |
8585 | else | |
8586 | FAIL; | |
8587 | }") | |
8588 | ||
acad7ed3 | 8589 | (define_insn "*movdi_internal64" |
fa0a2ae5 | 8590 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,??f,f,m,r,*h,*h") |
9615f239 | 8591 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8592 | "TARGET_POWERPC64 |
4e74d8ec MM |
8593 | && (gpc_reg_operand (operands[0], DImode) |
8594 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8595 | "@ |
3d5570cb RK |
8596 | mr %0,%1 |
8597 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8598 | std%U0%X0 %1,%0 |
3d5570cb | 8599 | li %0,%1 |
802a0058 | 8600 | lis %0,%v1 |
e6ca2c17 | 8601 | # |
aee86b38 | 8602 | {cal|la} %0,%a1 |
3d5570cb RK |
8603 | fmr %0,%1 |
8604 | lfd%U1%X1 %0,%1 | |
8605 | stfd%U0%X0 %1,%0 | |
8606 | mf%1 %0 | |
08075ead | 8607 | mt%0 %1 |
e34eaae5 | 8608 | {cror 0,0,0|nop}" |
02ca7595 | 8609 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") |
e6ca2c17 DE |
8610 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8611 | ||
5f59ecb7 | 8612 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8613 | (define_insn "" |
8614 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8615 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8616 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8617 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8618 | && num_insns_constant (operands[1], DImode) == 1" |
8619 | "* | |
8620 | { | |
8621 | return ((unsigned HOST_WIDE_INT) | |
8622 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8623 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8624 | }") | |
8625 | ||
a260abc9 DE |
8626 | ;; Generate all one-bits and clear left or right. |
8627 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8628 | (define_split | |
8629 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8630 | (match_operand:DI 1 "mask64_operand" ""))] | |
8631 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8632 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8633 | (set (match_dup 0) |
a260abc9 DE |
8634 | (and:DI (rotate:DI (match_dup 0) |
8635 | (const_int 0)) | |
8636 | (match_dup 1)))] | |
8637 | "") | |
8638 | ||
8639 | ;; Split a load of a large constant into the appropriate five-instruction | |
8640 | ;; sequence. Handle anything in a constant number of insns. | |
8641 | ;; When non-easy constants can go in the TOC, this should use | |
8642 | ;; easy_fp_constant predicate. | |
8643 | (define_split | |
8644 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8645 | (match_operand:DI 1 "const_int_operand" ""))] |
8646 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8647 | [(set (match_dup 0) (match_dup 2)) | |
8648 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8649 | " |
2bfcf297 DB |
8650 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8651 | ||
8652 | if (tem == operands[0]) | |
8653 | DONE; | |
e8d791dd | 8654 | else |
2bfcf297 | 8655 | FAIL; |
5f59ecb7 | 8656 | }") |
e6ca2c17 | 8657 | |
5f59ecb7 DE |
8658 | (define_split |
8659 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8660 | (match_operand:DI 1 "const_double_operand" ""))] |
8661 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8662 | [(set (match_dup 0) (match_dup 2)) | |
8663 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8664 | " |
2bfcf297 DB |
8665 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8666 | ||
8667 | if (tem == operands[0]) | |
8668 | DONE; | |
8669 | else | |
8670 | FAIL; | |
e6ca2c17 | 8671 | }") |
08075ead | 8672 | |
acad7ed3 | 8673 | (define_insn "*movdi_internal2" |
bb84cb12 DE |
8674 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
8675 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r") | |
08075ead | 8676 | (const_int 0))) |
bb84cb12 | 8677 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
683bdff7 | 8678 | "TARGET_64BIT" |
9ebbca7d | 8679 | "@ |
bb84cb12 | 8680 | cmpdi %2,%0,0 |
9ebbca7d GK |
8681 | mr. %0,%1 |
8682 | #" | |
bb84cb12 DE |
8683 | [(set_attr "type" "cmp,compare,cmp") |
8684 | (set_attr "length" "4,4,8")]) | |
acad7ed3 | 8685 | |
9ebbca7d GK |
8686 | (define_split |
8687 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8688 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8689 | (const_int 0))) | |
8690 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8691 | "TARGET_POWERPC64 && reload_completed" | |
8692 | [(set (match_dup 0) (match_dup 1)) | |
8693 | (set (match_dup 2) | |
8694 | (compare:CC (match_dup 0) | |
8695 | (const_int 0)))] | |
8696 | "") | |
acad7ed3 | 8697 | \f |
1fd4e8c1 RK |
8698 | ;; TImode is similar, except that we usually want to compute the address into |
8699 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8700 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8701 | (define_expand "movti" |
8702 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8703 | (match_operand:TI 1 "general_operand" "")) | |
8704 | (clobber (scratch:SI))])] | |
3a1f863f | 8705 | "" |
fb4d4348 | 8706 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8707 | |
8708 | ;; We say that MQ is clobbered in the last alternative because the first | |
8709 | ;; alternative would never get used otherwise since it would need a reload | |
8710 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8711 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8712 | ;; giving the SCRATCH mq. | |
3a1f863f | 8713 | |
a260abc9 | 8714 | (define_insn "*movti_power" |
e1469d0d | 8715 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8716 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8717 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
6ae08853 | 8718 | "TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8719 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8720 | "* |
8721 | { | |
8722 | switch (which_alternative) | |
8723 | { | |
dc4f83ca MM |
8724 | default: |
8725 | abort (); | |
8726 | ||
1fd4e8c1 | 8727 | case 0: |
3a1f863f DE |
8728 | if (TARGET_STRING) |
8729 | return \"{stsi|stswi} %1,%P0,16\"; | |
1fd4e8c1 | 8730 | case 1: |
1fd4e8c1 | 8731 | case 2: |
3a1f863f | 8732 | return \"#\"; |
1fd4e8c1 RK |
8733 | case 3: |
8734 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8735 | fall through to generating four loads. */ | |
e876481c DE |
8736 | if (TARGET_STRING |
8737 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8738 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8739 | /* ... fall through ... */ |
1fd4e8c1 | 8740 | case 4: |
3a1f863f | 8741 | return \"#\"; |
1fd4e8c1 RK |
8742 | } |
8743 | }" | |
3a1f863f | 8744 | [(set_attr "type" "store,store,*,load,load")]) |
51b8fc2c | 8745 | |
a260abc9 | 8746 | (define_insn "*movti_string" |
112ccb83 | 8747 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r") |
27dc0551 | 8748 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))] |
3a1f863f | 8749 | "! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8750 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8751 | "* | |
8752 | { | |
8753 | switch (which_alternative) | |
8754 | { | |
8755 | default: | |
8756 | abort (); | |
dc4f83ca | 8757 | case 0: |
3a1f863f DE |
8758 | if (TARGET_STRING) |
8759 | return \"{stsi|stswi} %1,%P0,16\"; | |
dc4f83ca | 8760 | case 1: |
cd1d3445 | 8761 | case 2: |
3a1f863f | 8762 | return \"#\"; |
cd1d3445 DE |
8763 | case 3: |
8764 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8765 | fall through to generating four loads. */ | |
6ae08853 | 8766 | if (TARGET_STRING |
3a1f863f | 8767 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) |
cd1d3445 DE |
8768 | return \"{lsi|lswi} %0,%P1,16\"; |
8769 | /* ... fall through ... */ | |
8770 | case 4: | |
3a1f863f | 8771 | return \"#\"; |
dc4f83ca MM |
8772 | } |
8773 | }" | |
3a1f863f | 8774 | [(set_attr "type" "store,store,*,load,load")]) |
dc4f83ca | 8775 | |
a260abc9 | 8776 | (define_insn "*movti_ppc64" |
112ccb83 GK |
8777 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") |
8778 | (match_operand:TI 1 "input_operand" "r,r,m"))] | |
51b8fc2c RK |
8779 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) |
8780 | || gpc_reg_operand (operands[1], TImode))" | |
112ccb83 | 8781 | "#" |
3a1f863f DE |
8782 | [(set_attr "type" "*,load,store")]) |
8783 | ||
8784 | (define_split | |
8785 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
8786 | (match_operand:TI 1 "input_operand" ""))] | |
a9baceb1 | 8787 | "reload_completed |
3a1f863f | 8788 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8789 | [(pc)] |
8790 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
1fd4e8c1 RK |
8791 | \f |
8792 | (define_expand "load_multiple" | |
2f622005 RK |
8793 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8794 | (match_operand:SI 1 "" "")) | |
8795 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8796 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8797 | " |
8798 | { | |
8799 | int regno; | |
8800 | int count; | |
792760b9 | 8801 | rtx op1; |
1fd4e8c1 RK |
8802 | int i; |
8803 | ||
8804 | /* Support only loading a constant number of fixed-point registers from | |
8805 | memory and only bother with this if more than two; the machine | |
8806 | doesn't support more than eight. */ | |
8807 | if (GET_CODE (operands[2]) != CONST_INT | |
8808 | || INTVAL (operands[2]) <= 2 | |
8809 | || INTVAL (operands[2]) > 8 | |
8810 | || GET_CODE (operands[1]) != MEM | |
8811 | || GET_CODE (operands[0]) != REG | |
8812 | || REGNO (operands[0]) >= 32) | |
8813 | FAIL; | |
8814 | ||
8815 | count = INTVAL (operands[2]); | |
8816 | regno = REGNO (operands[0]); | |
8817 | ||
39403d82 | 8818 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8819 | op1 = replace_equiv_address (operands[1], |
8820 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8821 | |
8822 | for (i = 0; i < count; i++) | |
8823 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8824 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 8825 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8826 | }") |
8827 | ||
9caa3eb2 | 8828 | (define_insn "*ldmsi8" |
1fd4e8c1 | 8829 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
8830 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
8831 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8832 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8833 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8834 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8835 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8836 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8837 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8838 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8839 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8840 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8841 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8842 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8843 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
8844 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
8845 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
8846 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 8847 | "* |
9caa3eb2 DE |
8848 | { return rs6000_output_load_multiple (operands); }" |
8849 | [(set_attr "type" "load") | |
8850 | (set_attr "length" "32")]) | |
1fd4e8c1 | 8851 | |
9caa3eb2 DE |
8852 | (define_insn "*ldmsi7" |
8853 | [(match_parallel 0 "load_multiple_operation" | |
8854 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8855 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8856 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8857 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8858 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8859 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8860 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8861 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8862 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8863 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8864 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8865 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8866 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8867 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
8868 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
8869 | "* | |
8870 | { return rs6000_output_load_multiple (operands); }" | |
8871 | [(set_attr "type" "load") | |
8872 | (set_attr "length" "32")]) | |
8873 | ||
8874 | (define_insn "*ldmsi6" | |
8875 | [(match_parallel 0 "load_multiple_operation" | |
8876 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8877 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8878 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8879 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8880 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8881 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8882 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8883 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8884 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8885 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8886 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8887 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
8888 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
8889 | "* | |
8890 | { return rs6000_output_load_multiple (operands); }" | |
8891 | [(set_attr "type" "load") | |
8892 | (set_attr "length" "32")]) | |
8893 | ||
8894 | (define_insn "*ldmsi5" | |
8895 | [(match_parallel 0 "load_multiple_operation" | |
8896 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8897 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8898 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8899 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8900 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8901 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8902 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8903 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8904 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8905 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
8906 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
8907 | "* | |
8908 | { return rs6000_output_load_multiple (operands); }" | |
8909 | [(set_attr "type" "load") | |
8910 | (set_attr "length" "32")]) | |
8911 | ||
8912 | (define_insn "*ldmsi4" | |
8913 | [(match_parallel 0 "load_multiple_operation" | |
8914 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8915 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8916 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8917 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8918 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8919 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8920 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8921 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
8922 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
8923 | "* | |
8924 | { return rs6000_output_load_multiple (operands); }" | |
8925 | [(set_attr "type" "load") | |
8926 | (set_attr "length" "32")]) | |
8927 | ||
8928 | (define_insn "*ldmsi3" | |
8929 | [(match_parallel 0 "load_multiple_operation" | |
8930 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8931 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8932 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8933 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8934 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8935 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
8936 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
8937 | "* | |
8938 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 8939 | [(set_attr "type" "load") |
e82ee4cc | 8940 | (set_attr "length" "32")]) |
b19003d8 | 8941 | |
1fd4e8c1 | 8942 | (define_expand "store_multiple" |
2f622005 RK |
8943 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8944 | (match_operand:SI 1 "" "")) | |
8945 | (clobber (scratch:SI)) | |
8946 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8947 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8948 | " |
8949 | { | |
8950 | int regno; | |
8951 | int count; | |
8952 | rtx to; | |
792760b9 | 8953 | rtx op0; |
1fd4e8c1 RK |
8954 | int i; |
8955 | ||
8956 | /* Support only storing a constant number of fixed-point registers to | |
8957 | memory and only bother with this if more than two; the machine | |
8958 | doesn't support more than eight. */ | |
8959 | if (GET_CODE (operands[2]) != CONST_INT | |
8960 | || INTVAL (operands[2]) <= 2 | |
8961 | || INTVAL (operands[2]) > 8 | |
8962 | || GET_CODE (operands[0]) != MEM | |
8963 | || GET_CODE (operands[1]) != REG | |
8964 | || REGNO (operands[1]) >= 32) | |
8965 | FAIL; | |
8966 | ||
8967 | count = INTVAL (operands[2]); | |
8968 | regno = REGNO (operands[1]); | |
8969 | ||
39403d82 | 8970 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8971 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8972 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8973 | |
8974 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 8975 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 8976 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8977 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8978 | |
8979 | for (i = 1; i < count; i++) | |
8980 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8981 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 8982 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 8983 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8984 | }") |
8985 | ||
9caa3eb2 | 8986 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
8987 | [(match_parallel 0 "store_multiple_operation" |
8988 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8989 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8990 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8991 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8992 | "{stsi|stswi} %2,%P1,%O0" |
8993 | [(set_attr "type" "store")]) | |
d14a6d05 | 8994 | |
e46e3130 | 8995 | (define_insn "*stmsi8" |
d14a6d05 | 8996 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
8997 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
8998 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8999 | (clobber (match_scratch:SI 3 "X")) | |
9000 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9001 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9002 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9003 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9004 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9005 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9006 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9007 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9008 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9009 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
9010 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
9011 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
9012 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
9013 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
9014 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
9015 | "{stsi|stswi} %2,%1,%O0" | |
9016 | [(set_attr "type" "store")]) | |
9017 | ||
9018 | (define_insn "*stmsi7" | |
9019 | [(match_parallel 0 "store_multiple_operation" | |
9020 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9021 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9022 | (clobber (match_scratch:SI 3 "X")) | |
9023 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9024 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9025 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9026 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9027 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9028 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9029 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9030 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9031 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9032 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
9033 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
9034 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
9035 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
9036 | "{stsi|stswi} %2,%1,%O0" | |
9037 | [(set_attr "type" "store")]) | |
9038 | ||
9039 | (define_insn "*stmsi6" | |
9040 | [(match_parallel 0 "store_multiple_operation" | |
9041 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9042 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9043 | (clobber (match_scratch:SI 3 "X")) | |
9044 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9045 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9046 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9047 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9048 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9049 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9050 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9051 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9052 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9053 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
9054 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
9055 | "{stsi|stswi} %2,%1,%O0" | |
9056 | [(set_attr "type" "store")]) | |
9057 | ||
9058 | (define_insn "*stmsi5" | |
9059 | [(match_parallel 0 "store_multiple_operation" | |
9060 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9061 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9062 | (clobber (match_scratch:SI 3 "X")) | |
9063 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9064 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9065 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9066 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9067 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9068 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9069 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9070 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
9071 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
9072 | "{stsi|stswi} %2,%1,%O0" | |
9073 | [(set_attr "type" "store")]) | |
9074 | ||
9075 | (define_insn "*stmsi4" | |
9076 | [(match_parallel 0 "store_multiple_operation" | |
9077 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9078 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9079 | (clobber (match_scratch:SI 3 "X")) | |
9080 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9081 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9082 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9083 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9084 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9085 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
9086 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
9087 | "{stsi|stswi} %2,%1,%O0" |
9088 | [(set_attr "type" "store")]) | |
7e69e155 | 9089 | |
e46e3130 DJ |
9090 | (define_insn "*stmsi3" |
9091 | [(match_parallel 0 "store_multiple_operation" | |
9092 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9093 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9094 | (clobber (match_scratch:SI 3 "X")) | |
9095 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9096 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9097 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9098 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
9099 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
9100 | "{stsi|stswi} %2,%1,%O0" | |
9101 | [(set_attr "type" "store")]) | |
7e69e155 | 9102 | \f |
fba73eb1 DE |
9103 | (define_expand "clrmemsi" |
9104 | [(parallel [(set (match_operand:BLK 0 "" "") | |
9105 | (const_int 0)) | |
9106 | (use (match_operand:SI 1 "" "")) | |
9107 | (use (match_operand:SI 2 "" ""))])] | |
9108 | "" | |
9109 | " | |
9110 | { | |
9111 | if (expand_block_clear (operands)) | |
9112 | DONE; | |
9113 | else | |
9114 | FAIL; | |
9115 | }") | |
9116 | ||
7e69e155 MM |
9117 | ;; String/block move insn. |
9118 | ;; Argument 0 is the destination | |
9119 | ;; Argument 1 is the source | |
9120 | ;; Argument 2 is the length | |
9121 | ;; Argument 3 is the alignment | |
9122 | ||
70128ad9 | 9123 | (define_expand "movmemsi" |
b6c9286a MM |
9124 | [(parallel [(set (match_operand:BLK 0 "" "") |
9125 | (match_operand:BLK 1 "" "")) | |
9126 | (use (match_operand:SI 2 "" "")) | |
9127 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
9128 | "" |
9129 | " | |
9130 | { | |
9131 | if (expand_block_move (operands)) | |
9132 | DONE; | |
9133 | else | |
9134 | FAIL; | |
9135 | }") | |
9136 | ||
9137 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
9138 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
9139 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9140 | (define_expand "movmemsi_8reg" |
b6c9286a MM |
9141 | [(parallel [(set (match_operand 0 "" "") |
9142 | (match_operand 1 "" "")) | |
9143 | (use (match_operand 2 "" "")) | |
9144 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
9145 | (clobber (reg:SI 5)) |
9146 | (clobber (reg:SI 6)) | |
9147 | (clobber (reg:SI 7)) | |
9148 | (clobber (reg:SI 8)) | |
9149 | (clobber (reg:SI 9)) | |
9150 | (clobber (reg:SI 10)) | |
9151 | (clobber (reg:SI 11)) | |
9152 | (clobber (reg:SI 12)) | |
3c67b673 | 9153 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9154 | "TARGET_STRING" |
9155 | "") | |
9156 | ||
9157 | (define_insn "" | |
52d3af72 DE |
9158 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9159 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9160 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9161 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9162 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9163 | (clobber (reg:SI 6)) |
9164 | (clobber (reg:SI 7)) | |
9165 | (clobber (reg:SI 8)) | |
9166 | (clobber (reg:SI 9)) | |
9167 | (clobber (reg:SI 10)) | |
9168 | (clobber (reg:SI 11)) | |
9169 | (clobber (reg:SI 12)) | |
3c67b673 | 9170 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 9171 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
9172 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9173 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9174 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9175 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9176 | && REGNO (operands[4]) == 5" |
9177 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9178 | [(set_attr "type" "load") |
9179 | (set_attr "length" "8")]) | |
7e69e155 MM |
9180 | |
9181 | (define_insn "" | |
52d3af72 DE |
9182 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9183 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9184 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9185 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9186 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9187 | (clobber (reg:SI 6)) |
9188 | (clobber (reg:SI 7)) | |
9189 | (clobber (reg:SI 8)) | |
9190 | (clobber (reg:SI 9)) | |
9191 | (clobber (reg:SI 10)) | |
9192 | (clobber (reg:SI 11)) | |
9193 | (clobber (reg:SI 12)) | |
3c67b673 | 9194 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9195 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
9196 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9197 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9198 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9199 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9200 | && REGNO (operands[4]) == 5" |
9201 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9202 | [(set_attr "type" "load") |
9203 | (set_attr "length" "8")]) | |
7e69e155 | 9204 | |
09a625f7 TR |
9205 | (define_insn "" |
9206 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9207 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9208 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9209 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9210 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9211 | (clobber (reg:SI 6)) | |
9212 | (clobber (reg:SI 7)) | |
9213 | (clobber (reg:SI 8)) | |
9214 | (clobber (reg:SI 9)) | |
9215 | (clobber (reg:SI 10)) | |
9216 | (clobber (reg:SI 11)) | |
9217 | (clobber (reg:SI 12)) | |
9218 | (clobber (match_scratch:SI 5 "X"))] | |
9219 | "TARGET_STRING && TARGET_POWERPC64 | |
9220 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
9221 | || INTVAL (operands[2]) == 0) | |
9222 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
9223 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
9224 | && REGNO (operands[4]) == 5" | |
9225 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9226 | [(set_attr "type" "load") | |
9227 | (set_attr "length" "8")]) | |
9228 | ||
7e69e155 | 9229 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
9230 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
9231 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9232 | (define_expand "movmemsi_6reg" |
b6c9286a MM |
9233 | [(parallel [(set (match_operand 0 "" "") |
9234 | (match_operand 1 "" "")) | |
9235 | (use (match_operand 2 "" "")) | |
9236 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9237 | (clobber (reg:SI 5)) |
9238 | (clobber (reg:SI 6)) | |
7e69e155 MM |
9239 | (clobber (reg:SI 7)) |
9240 | (clobber (reg:SI 8)) | |
9241 | (clobber (reg:SI 9)) | |
9242 | (clobber (reg:SI 10)) | |
3c67b673 | 9243 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9244 | "TARGET_STRING" |
9245 | "") | |
9246 | ||
9247 | (define_insn "" | |
52d3af72 DE |
9248 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9249 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9250 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9251 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9252 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9253 | (clobber (reg:SI 6)) |
9254 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9255 | (clobber (reg:SI 8)) |
9256 | (clobber (reg:SI 9)) | |
9257 | (clobber (reg:SI 10)) | |
3c67b673 | 9258 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9259 | "TARGET_STRING && TARGET_POWER |
9260 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
9261 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9262 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9263 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9264 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9265 | [(set_attr "type" "load") |
9266 | (set_attr "length" "8")]) | |
7e69e155 MM |
9267 | |
9268 | (define_insn "" | |
52d3af72 DE |
9269 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9270 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9271 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9272 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9273 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9274 | (clobber (reg:SI 6)) |
9275 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9276 | (clobber (reg:SI 8)) |
9277 | (clobber (reg:SI 9)) | |
9278 | (clobber (reg:SI 10)) | |
3c67b673 | 9279 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9280 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9281 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
9282 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9283 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9284 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9285 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9286 | [(set_attr "type" "load") |
9287 | (set_attr "length" "8")]) | |
7e69e155 | 9288 | |
09a625f7 TR |
9289 | (define_insn "" |
9290 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9291 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9292 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9293 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9294 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9295 | (clobber (reg:SI 6)) | |
9296 | (clobber (reg:SI 7)) | |
9297 | (clobber (reg:SI 8)) | |
9298 | (clobber (reg:SI 9)) | |
9299 | (clobber (reg:SI 10)) | |
9300 | (clobber (match_scratch:SI 5 "X"))] | |
9301 | "TARGET_STRING && TARGET_POWERPC64 | |
9302 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
9303 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
9304 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9305 | && REGNO (operands[4]) == 5" | |
9306 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9307 | [(set_attr "type" "load") | |
9308 | (set_attr "length" "8")]) | |
9309 | ||
f9562f27 DE |
9310 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9311 | ;; problems with TImode. | |
9312 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9313 | (define_expand "movmemsi_4reg" |
b6c9286a MM |
9314 | [(parallel [(set (match_operand 0 "" "") |
9315 | (match_operand 1 "" "")) | |
9316 | (use (match_operand 2 "" "")) | |
9317 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9318 | (clobber (reg:SI 5)) |
9319 | (clobber (reg:SI 6)) | |
9320 | (clobber (reg:SI 7)) | |
9321 | (clobber (reg:SI 8)) | |
3c67b673 | 9322 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9323 | "TARGET_STRING" |
9324 | "") | |
9325 | ||
9326 | (define_insn "" | |
52d3af72 DE |
9327 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9328 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9329 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9330 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9331 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9332 | (clobber (reg:SI 6)) |
9333 | (clobber (reg:SI 7)) | |
9334 | (clobber (reg:SI 8)) | |
3c67b673 | 9335 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9336 | "TARGET_STRING && TARGET_POWER |
9337 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9338 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9339 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9340 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9341 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9342 | [(set_attr "type" "load") |
9343 | (set_attr "length" "8")]) | |
7e69e155 MM |
9344 | |
9345 | (define_insn "" | |
52d3af72 DE |
9346 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9347 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9348 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9349 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9350 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9351 | (clobber (reg:SI 6)) |
9352 | (clobber (reg:SI 7)) | |
9353 | (clobber (reg:SI 8)) | |
3c67b673 | 9354 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9355 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9356 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9357 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9358 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9359 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9360 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9361 | [(set_attr "type" "load") |
9362 | (set_attr "length" "8")]) | |
7e69e155 | 9363 | |
09a625f7 TR |
9364 | (define_insn "" |
9365 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9366 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9367 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9368 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9369 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9370 | (clobber (reg:SI 6)) | |
9371 | (clobber (reg:SI 7)) | |
9372 | (clobber (reg:SI 8)) | |
9373 | (clobber (match_scratch:SI 5 "X"))] | |
9374 | "TARGET_STRING && TARGET_POWERPC64 | |
9375 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
9376 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
9377 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9378 | && REGNO (operands[4]) == 5" | |
9379 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9380 | [(set_attr "type" "load") | |
9381 | (set_attr "length" "8")]) | |
9382 | ||
7e69e155 | 9383 | ;; Move up to 8 bytes at a time. |
70128ad9 | 9384 | (define_expand "movmemsi_2reg" |
b6c9286a MM |
9385 | [(parallel [(set (match_operand 0 "" "") |
9386 | (match_operand 1 "" "")) | |
9387 | (use (match_operand 2 "" "")) | |
9388 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9389 | (clobber (match_scratch:DI 4 "")) |
9390 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9391 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9392 | "") |
9393 | ||
9394 | (define_insn "" | |
52d3af72 DE |
9395 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9396 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9397 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9398 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9399 | (clobber (match_scratch:DI 4 "=&r")) | |
9400 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9401 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9402 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9403 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9404 | [(set_attr "type" "load") |
9405 | (set_attr "length" "8")]) | |
7e69e155 MM |
9406 | |
9407 | (define_insn "" | |
52d3af72 DE |
9408 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9409 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9410 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9411 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9412 | (clobber (match_scratch:DI 4 "=&r")) | |
9413 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9414 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9415 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9416 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9417 | [(set_attr "type" "load") |
9418 | (set_attr "length" "8")]) | |
7e69e155 MM |
9419 | |
9420 | ;; Move up to 4 bytes at a time. | |
70128ad9 | 9421 | (define_expand "movmemsi_1reg" |
b6c9286a MM |
9422 | [(parallel [(set (match_operand 0 "" "") |
9423 | (match_operand 1 "" "")) | |
9424 | (use (match_operand 2 "" "")) | |
9425 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9426 | (clobber (match_scratch:SI 4 "")) |
9427 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9428 | "TARGET_STRING" |
9429 | "") | |
9430 | ||
9431 | (define_insn "" | |
52d3af72 DE |
9432 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9433 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9434 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9435 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9436 | (clobber (match_scratch:SI 4 "=&r")) | |
9437 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9438 | "TARGET_STRING && TARGET_POWER |
9439 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9440 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9441 | [(set_attr "type" "load") |
9442 | (set_attr "length" "8")]) | |
7e69e155 MM |
9443 | |
9444 | (define_insn "" | |
52d3af72 DE |
9445 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9446 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9447 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9448 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9449 | (clobber (match_scratch:SI 4 "=&r")) | |
9450 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9451 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9452 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
9453 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
9454 | [(set_attr "type" "load") | |
9455 | (set_attr "length" "8")]) | |
9456 | ||
9457 | (define_insn "" | |
9458 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9459 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9460 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9461 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9462 | (clobber (match_scratch:SI 4 "=&r")) | |
9463 | (clobber (match_scratch:SI 5 "X"))] | |
9464 | "TARGET_STRING && TARGET_POWERPC64 | |
9465 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9466 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9467 | [(set_attr "type" "load") |
9468 | (set_attr "length" "8")]) | |
7e69e155 | 9469 | |
1fd4e8c1 | 9470 | \f |
7e69e155 | 9471 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9472 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9473 | ;; do cases where the increment is not the size of the object. | |
9474 | ;; | |
9475 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9476 | ;; incremented because those are the operands that local-alloc will | |
9477 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9478 | ;; that will benefit the most). | |
9479 | ||
38c1f2d7 | 9480 | (define_insn "*movdi_update1" |
51b8fc2c | 9481 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9482 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9483 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
9484 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
9485 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9486 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9487 | "@ |
9488 | ldux %3,%0,%2 | |
9489 | ldu %3,%2(%0)" | |
b54cf83a | 9490 | [(set_attr "type" "load_ux,load_u")]) |
287f13ff | 9491 | |
2e6c9641 FJ |
9492 | (define_insn "movdi_<mode>_update" |
9493 | [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") | |
9494 | (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) | |
51b8fc2c | 9495 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
2e6c9641 FJ |
9496 | (set (match_operand:P 0 "gpc_reg_operand" "=b,b") |
9497 | (plus:P (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9498 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9499 | "@ |
9500 | stdux %3,%0,%2 | |
b7ff3d82 | 9501 | stdu %3,%2(%0)" |
b54cf83a | 9502 | [(set_attr "type" "store_ux,store_u")]) |
51b8fc2c | 9503 | |
38c1f2d7 | 9504 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9505 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9506 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9507 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9508 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9509 | (plus:SI (match_dup 1) (match_dup 2)))] |
f7b3ab8a | 9510 | "TARGET_UPDATE" |
1fd4e8c1 | 9511 | "@ |
ca7f5001 RK |
9512 | {lux|lwzux} %3,%0,%2 |
9513 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a DE |
9514 | [(set_attr "type" "load_ux,load_u")]) |
9515 | ||
9516 | (define_insn "*movsi_update2" | |
9517 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
9518 | (sign_extend:DI | |
9519 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9520 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9521 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9522 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9523 | "TARGET_POWERPC64" | |
9524 | "lwaux %3,%0,%2" | |
9525 | [(set_attr "type" "load_ext_ux")]) | |
1fd4e8c1 | 9526 | |
4697a36c | 9527 | (define_insn "movsi_update" |
cd2b37d9 | 9528 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9529 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9530 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9531 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9532 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9533 | "TARGET_UPDATE" |
1fd4e8c1 | 9534 | "@ |
ca7f5001 | 9535 | {stux|stwux} %3,%0,%2 |
b7ff3d82 | 9536 | {stu|stwu} %3,%2(%0)" |
b54cf83a | 9537 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9538 | |
b54cf83a | 9539 | (define_insn "*movhi_update1" |
cd2b37d9 RK |
9540 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9541 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9542 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9543 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9544 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9545 | "TARGET_UPDATE" |
1fd4e8c1 | 9546 | "@ |
5f243543 RK |
9547 | lhzux %3,%0,%2 |
9548 | lhzu %3,%2(%0)" | |
b54cf83a | 9549 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9550 | |
38c1f2d7 | 9551 | (define_insn "*movhi_update2" |
cd2b37d9 | 9552 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9553 | (zero_extend:SI |
cd2b37d9 | 9554 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9555 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9556 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9557 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9558 | "TARGET_UPDATE" |
1fd4e8c1 | 9559 | "@ |
5f243543 RK |
9560 | lhzux %3,%0,%2 |
9561 | lhzu %3,%2(%0)" | |
b54cf83a | 9562 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9563 | |
38c1f2d7 | 9564 | (define_insn "*movhi_update3" |
cd2b37d9 | 9565 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9566 | (sign_extend:SI |
cd2b37d9 | 9567 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9568 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9569 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9570 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9571 | "TARGET_UPDATE" |
1fd4e8c1 | 9572 | "@ |
5f243543 RK |
9573 | lhaux %3,%0,%2 |
9574 | lhau %3,%2(%0)" | |
b54cf83a | 9575 | [(set_attr "type" "load_ext_ux,load_ext_u")]) |
1fd4e8c1 | 9576 | |
38c1f2d7 | 9577 | (define_insn "*movhi_update4" |
cd2b37d9 | 9578 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9579 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9580 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9581 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9582 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9583 | "TARGET_UPDATE" |
1fd4e8c1 | 9584 | "@ |
5f243543 | 9585 | sthux %3,%0,%2 |
b7ff3d82 | 9586 | sthu %3,%2(%0)" |
b54cf83a | 9587 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9588 | |
38c1f2d7 | 9589 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9590 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9591 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9592 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9593 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9594 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9595 | "TARGET_UPDATE" |
1fd4e8c1 | 9596 | "@ |
5f243543 RK |
9597 | lbzux %3,%0,%2 |
9598 | lbzu %3,%2(%0)" | |
b54cf83a | 9599 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9600 | |
38c1f2d7 | 9601 | (define_insn "*movqi_update2" |
cd2b37d9 | 9602 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9603 | (zero_extend:SI |
cd2b37d9 | 9604 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9605 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9606 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9607 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9608 | "TARGET_UPDATE" |
1fd4e8c1 | 9609 | "@ |
5f243543 RK |
9610 | lbzux %3,%0,%2 |
9611 | lbzu %3,%2(%0)" | |
b54cf83a | 9612 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9613 | |
38c1f2d7 | 9614 | (define_insn "*movqi_update3" |
cd2b37d9 | 9615 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9616 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9617 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9618 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9619 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9620 | "TARGET_UPDATE" |
1fd4e8c1 | 9621 | "@ |
5f243543 | 9622 | stbux %3,%0,%2 |
b7ff3d82 | 9623 | stbu %3,%2(%0)" |
b54cf83a | 9624 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9625 | |
38c1f2d7 | 9626 | (define_insn "*movsf_update1" |
cd2b37d9 | 9627 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9628 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9629 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9630 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9631 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9632 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9633 | "@ |
5f243543 RK |
9634 | lfsux %3,%0,%2 |
9635 | lfsu %3,%2(%0)" | |
b54cf83a | 9636 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9637 | |
38c1f2d7 | 9638 | (define_insn "*movsf_update2" |
cd2b37d9 | 9639 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9640 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9641 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9642 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9643 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9644 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9645 | "@ |
85fff2f3 | 9646 | stfsux %3,%0,%2 |
b7ff3d82 | 9647 | stfsu %3,%2(%0)" |
b54cf83a | 9648 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
1fd4e8c1 | 9649 | |
38c1f2d7 MM |
9650 | (define_insn "*movsf_update3" |
9651 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9652 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9653 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9654 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9655 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9656 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9657 | "@ |
9658 | {lux|lwzux} %3,%0,%2 | |
9659 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a | 9660 | [(set_attr "type" "load_ux,load_u")]) |
38c1f2d7 MM |
9661 | |
9662 | (define_insn "*movsf_update4" | |
9663 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9664 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9665 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9666 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9667 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9668 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9669 | "@ |
9670 | {stux|stwux} %3,%0,%2 | |
9671 | {stu|stwu} %3,%2(%0)" | |
b54cf83a | 9672 | [(set_attr "type" "store_ux,store_u")]) |
38c1f2d7 MM |
9673 | |
9674 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9675 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9676 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9677 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9678 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9679 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9680 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9681 | "@ |
5f243543 RK |
9682 | lfdux %3,%0,%2 |
9683 | lfdu %3,%2(%0)" | |
b54cf83a | 9684 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9685 | |
38c1f2d7 | 9686 | (define_insn "*movdf_update2" |
cd2b37d9 | 9687 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9688 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9689 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9690 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9691 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9692 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9693 | "@ |
5f243543 | 9694 | stfdux %3,%0,%2 |
b7ff3d82 | 9695 | stfdu %3,%2(%0)" |
b54cf83a | 9696 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
4c70a4f3 RK |
9697 | |
9698 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9699 | ||
90f81f99 AP |
9700 | (define_insn "*lfq_power2" |
9701 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
9702 | (match_operand:TF 1 "memory_operand" ""))] | |
9703 | "TARGET_POWER2 | |
9704 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9705 | "lfq%U1%X1 %0,%1") | |
9706 | ||
9707 | (define_peephole2 | |
9708 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4c70a4f3 | 9709 | (match_operand:DF 1 "memory_operand" "")) |
90f81f99 | 9710 | (set (match_operand:DF 2 "gpc_reg_operand" "") |
4c70a4f3 RK |
9711 | (match_operand:DF 3 "memory_operand" ""))] |
9712 | "TARGET_POWER2 | |
a3170dc6 | 9713 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9714 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
90f81f99 AP |
9715 | && mems_ok_for_quad_peep (operands[1], operands[3])" |
9716 | [(set (match_dup 0) | |
9717 | (match_dup 1))] | |
9718 | "operands[1] = widen_memory_access (operands[1], TFmode, 0); | |
9719 | operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));") | |
4c70a4f3 | 9720 | |
90f81f99 AP |
9721 | (define_insn "*stfq_power2" |
9722 | [(set (match_operand:TF 0 "memory_operand" "") | |
9723 | (match_operand:TF 1 "gpc_reg_operand" "f"))] | |
9724 | "TARGET_POWER2 | |
9725 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9726 | "stfq%U0%X0 %1,%0") | |
9727 | ||
9728 | ||
9729 | (define_peephole2 | |
4c70a4f3 | 9730 | [(set (match_operand:DF 0 "memory_operand" "") |
90f81f99 | 9731 | (match_operand:DF 1 "gpc_reg_operand" "")) |
4c70a4f3 | 9732 | (set (match_operand:DF 2 "memory_operand" "") |
90f81f99 | 9733 | (match_operand:DF 3 "gpc_reg_operand" ""))] |
4c70a4f3 | 9734 | "TARGET_POWER2 |
a3170dc6 | 9735 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9736 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
90f81f99 AP |
9737 | && mems_ok_for_quad_peep (operands[0], operands[2])" |
9738 | [(set (match_dup 0) | |
9739 | (match_dup 1))] | |
9740 | "operands[0] = widen_memory_access (operands[0], TFmode, 0); | |
9741 | operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));") | |
1fd4e8c1 | 9742 | \f |
c4501e62 JJ |
9743 | ;; TLS support. |
9744 | ||
9745 | ;; "b" output constraint here and on tls_ld to support tls linker optimization. | |
9746 | (define_insn "tls_gd_32" | |
b150f4f3 DE |
9747 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9748 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9749 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9750 | UNSPEC_TLSGD))] | |
9751 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9752 | "addi %0,%1,%2@got@tlsgd") | |
9753 | ||
9754 | (define_insn "tls_gd_64" | |
b150f4f3 DE |
9755 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9756 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9757 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9758 | UNSPEC_TLSGD))] | |
9759 | "HAVE_AS_TLS && TARGET_64BIT" | |
9760 | "addi %0,%1,%2@got@tlsgd") | |
9761 | ||
9762 | (define_insn "tls_ld_32" | |
b150f4f3 DE |
9763 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9764 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9765 | UNSPEC_TLSLD))] |
9766 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9767 | "addi %0,%1,%&@got@tlsld") | |
9768 | ||
9769 | (define_insn "tls_ld_64" | |
b150f4f3 DE |
9770 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9771 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9772 | UNSPEC_TLSLD))] |
9773 | "HAVE_AS_TLS && TARGET_64BIT" | |
9774 | "addi %0,%1,%&@got@tlsld") | |
9775 | ||
9776 | (define_insn "tls_dtprel_32" | |
b150f4f3 DE |
9777 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9778 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9779 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9780 | UNSPEC_TLSDTPREL))] | |
9781 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9782 | "addi %0,%1,%2@dtprel") | |
9783 | ||
9784 | (define_insn "tls_dtprel_64" | |
b150f4f3 DE |
9785 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9786 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9787 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9788 | UNSPEC_TLSDTPREL))] | |
9789 | "HAVE_AS_TLS && TARGET_64BIT" | |
9790 | "addi %0,%1,%2@dtprel") | |
9791 | ||
9792 | (define_insn "tls_dtprel_ha_32" | |
b150f4f3 DE |
9793 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9794 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9795 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9796 | UNSPEC_TLSDTPRELHA))] | |
9797 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9798 | "addis %0,%1,%2@dtprel@ha") | |
9799 | ||
9800 | (define_insn "tls_dtprel_ha_64" | |
b150f4f3 DE |
9801 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9802 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9803 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9804 | UNSPEC_TLSDTPRELHA))] | |
9805 | "HAVE_AS_TLS && TARGET_64BIT" | |
9806 | "addis %0,%1,%2@dtprel@ha") | |
9807 | ||
9808 | (define_insn "tls_dtprel_lo_32" | |
b150f4f3 DE |
9809 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9810 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9811 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9812 | UNSPEC_TLSDTPRELLO))] | |
9813 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9814 | "addi %0,%1,%2@dtprel@l") | |
9815 | ||
9816 | (define_insn "tls_dtprel_lo_64" | |
b150f4f3 DE |
9817 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9818 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9819 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9820 | UNSPEC_TLSDTPRELLO))] | |
9821 | "HAVE_AS_TLS && TARGET_64BIT" | |
9822 | "addi %0,%1,%2@dtprel@l") | |
9823 | ||
9824 | (define_insn "tls_got_dtprel_32" | |
b150f4f3 DE |
9825 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9826 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9827 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9828 | UNSPEC_TLSGOTDTPREL))] | |
9829 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9830 | "lwz %0,%2@got@dtprel(%1)") | |
9831 | ||
9832 | (define_insn "tls_got_dtprel_64" | |
b150f4f3 DE |
9833 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9834 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9835 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9836 | UNSPEC_TLSGOTDTPREL))] | |
9837 | "HAVE_AS_TLS && TARGET_64BIT" | |
9838 | "ld %0,%2@got@dtprel(%1)") | |
9839 | ||
9840 | (define_insn "tls_tprel_32" | |
b150f4f3 DE |
9841 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9842 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9843 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9844 | UNSPEC_TLSTPREL))] | |
9845 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9846 | "addi %0,%1,%2@tprel") | |
9847 | ||
9848 | (define_insn "tls_tprel_64" | |
b150f4f3 DE |
9849 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9850 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9851 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9852 | UNSPEC_TLSTPREL))] | |
9853 | "HAVE_AS_TLS && TARGET_64BIT" | |
9854 | "addi %0,%1,%2@tprel") | |
9855 | ||
9856 | (define_insn "tls_tprel_ha_32" | |
b150f4f3 DE |
9857 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9858 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9859 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9860 | UNSPEC_TLSTPRELHA))] | |
9861 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9862 | "addis %0,%1,%2@tprel@ha") | |
9863 | ||
9864 | (define_insn "tls_tprel_ha_64" | |
b150f4f3 DE |
9865 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9866 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9867 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9868 | UNSPEC_TLSTPRELHA))] | |
9869 | "HAVE_AS_TLS && TARGET_64BIT" | |
9870 | "addis %0,%1,%2@tprel@ha") | |
9871 | ||
9872 | (define_insn "tls_tprel_lo_32" | |
b150f4f3 DE |
9873 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9874 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9875 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9876 | UNSPEC_TLSTPRELLO))] | |
9877 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9878 | "addi %0,%1,%2@tprel@l") | |
9879 | ||
9880 | (define_insn "tls_tprel_lo_64" | |
b150f4f3 DE |
9881 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9882 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9883 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9884 | UNSPEC_TLSTPRELLO))] | |
9885 | "HAVE_AS_TLS && TARGET_64BIT" | |
9886 | "addi %0,%1,%2@tprel@l") | |
9887 | ||
c1207243 | 9888 | ;; "b" output constraint here and on tls_tls input to support linker tls |
c4501e62 JJ |
9889 | ;; optimization. The linker may edit the instructions emitted by a |
9890 | ;; tls_got_tprel/tls_tls pair to addis,addi. | |
9891 | (define_insn "tls_got_tprel_32" | |
b150f4f3 DE |
9892 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9893 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9894 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9895 | UNSPEC_TLSGOTTPREL))] | |
9896 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9897 | "lwz %0,%2@got@tprel(%1)") | |
9898 | ||
9899 | (define_insn "tls_got_tprel_64" | |
b150f4f3 DE |
9900 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9901 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9902 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9903 | UNSPEC_TLSGOTTPREL))] | |
9904 | "HAVE_AS_TLS && TARGET_64BIT" | |
9905 | "ld %0,%2@got@tprel(%1)") | |
9906 | ||
9907 | (define_insn "tls_tls_32" | |
b150f4f3 DE |
9908 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9909 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9910 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9911 | UNSPEC_TLSTLS))] | |
9912 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9913 | "add %0,%1,%2@tls") | |
9914 | ||
9915 | (define_insn "tls_tls_64" | |
b150f4f3 DE |
9916 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9917 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9918 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9919 | UNSPEC_TLSTLS))] | |
9920 | "HAVE_AS_TLS && TARGET_64BIT" | |
9921 | "add %0,%1,%2@tls") | |
9922 | \f | |
1fd4e8c1 RK |
9923 | ;; Next come insns related to the calling sequence. |
9924 | ;; | |
9925 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9926 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9927 | |
9928 | (define_expand "allocate_stack" | |
52d3af72 | 9929 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9930 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9931 | (set (reg 1) | |
9932 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9933 | "" |
9934 | " | |
4697a36c | 9935 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9936 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9937 | rtx neg_op0; |
1fd4e8c1 RK |
9938 | |
9939 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9940 | |
a157febd GK |
9941 | /* Check stack bounds if necessary. */ |
9942 | if (current_function_limit_stack) | |
9943 | { | |
9944 | rtx available; | |
6ae08853 | 9945 | available = expand_binop (Pmode, sub_optab, |
a157febd GK |
9946 | stack_pointer_rtx, stack_limit_rtx, |
9947 | NULL_RTX, 1, OPTAB_WIDEN); | |
9948 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9949 | } | |
9950 | ||
e9a25f70 JL |
9951 | if (GET_CODE (operands[1]) != CONST_INT |
9952 | || INTVAL (operands[1]) < -32767 | |
9953 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9954 | { |
9955 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9956 | if (TARGET_32BIT) |
e9a25f70 | 9957 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9958 | else |
e9a25f70 | 9959 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9960 | } |
9961 | else | |
e9a25f70 | 9962 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9963 | |
38c1f2d7 | 9964 | if (TARGET_UPDATE) |
2e6c9641 | 9965 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update)) |
38c1f2d7 | 9966 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); |
4697a36c | 9967 | |
38c1f2d7 MM |
9968 | else |
9969 | { | |
9970 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9971 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9972 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9973 | } |
e9a25f70 JL |
9974 | |
9975 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9976 | DONE; |
9977 | }") | |
59257ff7 RK |
9978 | |
9979 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9980 | ;; save the stack pointer at function level since we are careful to | |
9981 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9982 | ;; when we restore the stack pointer. | |
9983 | ;; | |
9984 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9985 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9986 | ;; save area is a memory location. | |
9987 | ||
9988 | (define_expand "save_stack_function" | |
ff381587 MM |
9989 | [(match_operand 0 "any_operand" "") |
9990 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9991 | "" |
ff381587 | 9992 | "DONE;") |
59257ff7 RK |
9993 | |
9994 | (define_expand "restore_stack_function" | |
ff381587 MM |
9995 | [(match_operand 0 "any_operand" "") |
9996 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9997 | "" |
ff381587 | 9998 | "DONE;") |
59257ff7 RK |
9999 | |
10000 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
10001 | [(use (match_operand 0 "register_operand" "")) |
10002 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 10003 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 10004 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
10005 | "" |
10006 | " | |
dfdfa60f DE |
10007 | { |
10008 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 10009 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 10010 | }") |
59257ff7 RK |
10011 | |
10012 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
10013 | [(match_operand 0 "memory_operand" "") |
10014 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
10015 | "" |
10016 | " | |
10017 | { | |
a260abc9 | 10018 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 10019 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
10020 | |
10021 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 10022 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
39e453d7 DE |
10023 | emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp); |
10024 | emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word), | |
a260abc9 | 10025 | operands[1]); |
59257ff7 RK |
10026 | DONE; |
10027 | }") | |
7e69e155 | 10028 | |
59257ff7 | 10029 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
10030 | [(match_operand 0 "register_operand" "") |
10031 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
10032 | "" |
10033 | " | |
10034 | { | |
a260abc9 | 10035 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 10036 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
10037 | |
10038 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 | 10039 | emit_move_insn (temp, |
39e453d7 | 10040 | adjust_address_nv (operands[1], Pmode, 0)); |
a260abc9 | 10041 | emit_move_insn (operands[0], |
39e453d7 | 10042 | adjust_address_nv (operands[1], Pmode, units_per_word)); |
39403d82 | 10043 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
10044 | DONE; |
10045 | }") | |
9ebbca7d GK |
10046 | \f |
10047 | ;; TOC register handling. | |
b6c9286a | 10048 | |
9ebbca7d | 10049 | ;; Code to initialize the TOC register... |
f0f6a223 | 10050 | |
9ebbca7d | 10051 | (define_insn "load_toc_aix_si" |
e72247f4 | 10052 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
615158e2 | 10053 | (unspec:SI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 10054 | (use (reg:SI 2))])] |
2bfcf297 | 10055 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
10056 | "* |
10057 | { | |
9ebbca7d GK |
10058 | char buf[30]; |
10059 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 10060 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10061 | operands[2] = gen_rtx_REG (Pmode, 2); |
10062 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
10063 | }" |
10064 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
10065 | |
10066 | (define_insn "load_toc_aix_di" | |
e72247f4 | 10067 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
615158e2 | 10068 | (unspec:DI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 10069 | (use (reg:DI 2))])] |
2bfcf297 | 10070 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
10071 | "* |
10072 | { | |
10073 | char buf[30]; | |
f585a356 DE |
10074 | #ifdef TARGET_RELOCATABLE |
10075 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
10076 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
10077 | #else | |
9ebbca7d | 10078 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 10079 | #endif |
2bfcf297 DB |
10080 | if (TARGET_ELF) |
10081 | strcat (buf, \"@toc\"); | |
a8a05998 | 10082 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10083 | operands[2] = gen_rtx_REG (Pmode, 2); |
10084 | return \"ld %0,%1(%2)\"; | |
10085 | }" | |
10086 | [(set_attr "type" "load")]) | |
10087 | ||
10088 | (define_insn "load_toc_v4_pic_si" | |
10089 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 | 10090 | (unspec:SI [(const_int 0)] UNSPEC_TOC))] |
f607bc57 | 10091 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
10092 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
10093 | [(set_attr "type" "branch") | |
10094 | (set_attr "length" "4")]) | |
10095 | ||
9ebbca7d GK |
10096 | (define_insn "load_toc_v4_PIC_1" |
10097 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10098 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 | 10099 | (use (unspec [(match_dup 1)] UNSPEC_TOC))] |
20b71b17 | 10100 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 10101 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
10102 | [(set_attr "type" "branch") |
10103 | (set_attr "length" "4")]) | |
10104 | ||
10105 | (define_insn "load_toc_v4_PIC_1b" | |
10106 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10107 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 JJ |
10108 | (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] |
10109 | UNSPEC_TOCPTR))] | |
20b71b17 | 10110 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
c4501e62 | 10111 | "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1" |
9ebbca7d GK |
10112 | [(set_attr "type" "branch") |
10113 | (set_attr "length" "8")]) | |
10114 | ||
10115 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 10116 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 10117 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
10118 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
10119 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 10120 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
10121 | "{l|lwz} %0,%2-%3(%1)" |
10122 | [(set_attr "type" "load")]) | |
10123 | ||
ee890fe2 SS |
10124 | (define_insn "load_macho_picbase" |
10125 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 JJ |
10126 | (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] |
10127 | UNSPEC_LD_MPIC))] | |
ee890fe2 | 10128 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" |
f51eee6a | 10129 | "bcl 20,31,%1\\n%1:" |
ee890fe2 SS |
10130 | [(set_attr "type" "branch") |
10131 | (set_attr "length" "4")]) | |
10132 | ||
f51eee6a GK |
10133 | (define_insn "macho_correct_pic" |
10134 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
8291cc0e | 10135 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
f51eee6a GK |
10136 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "s") |
10137 | (match_operand:SI 3 "immediate_operand" "s")] | |
615158e2 | 10138 | UNSPEC_MPIC_CORRECT)))] |
f51eee6a | 10139 | "DEFAULT_ABI == ABI_DARWIN" |
8291cc0e | 10140 | "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)" |
f51eee6a GK |
10141 | [(set_attr "length" "8")]) |
10142 | ||
9ebbca7d GK |
10143 | ;; If the TOC is shared over a translation unit, as happens with all |
10144 | ;; the kinds of PIC that we support, we need to restore the TOC | |
10145 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 10146 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
10147 | |
10148 | (define_expand "builtin_setjmp_receiver" | |
10149 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 10150 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
10151 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
10152 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
10153 | " |
10154 | { | |
84d7dd4a | 10155 | #if TARGET_MACHO |
f51eee6a GK |
10156 | if (DEFAULT_ABI == ABI_DARWIN) |
10157 | { | |
d24652ee | 10158 | const char *picbase = machopic_function_base_name (); |
485bad26 | 10159 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); |
f51eee6a GK |
10160 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
10161 | rtx tmplabrtx; | |
10162 | char tmplab[20]; | |
10163 | ||
10164 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
10165 | CODE_LABEL_NUMBER (operands[0])); | |
485bad26 | 10166 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); |
f51eee6a | 10167 | |
ac9e2cff AP |
10168 | emit_insn (TARGET_64BIT |
10169 | ? gen_load_macho_picbase_di (picreg, tmplabrtx) | |
10170 | : gen_load_macho_picbase (picreg, tmplabrtx)); | |
10171 | emit_insn (TARGET_64BIT | |
10172 | ? gen_macho_correct_pic_di (picreg, picreg, picrtx, tmplabrtx) | |
10173 | : gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
f51eee6a GK |
10174 | } |
10175 | else | |
84d7dd4a | 10176 | #endif |
f51eee6a | 10177 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
10178 | DONE; |
10179 | }") | |
10180 | \f | |
10181 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
10182 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
10183 | ;; pointer to its TOC, and whose third word contains a value to place in the |
10184 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 10185 | ;; "trampoline" need not have any executable code. |
b6c9286a | 10186 | |
cccf3bdc DE |
10187 | (define_expand "call_indirect_aix32" |
10188 | [(set (match_dup 2) | |
10189 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
10190 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10191 | (reg:SI 2)) | |
10192 | (set (reg:SI 2) | |
10193 | (mem:SI (plus:SI (match_dup 0) | |
10194 | (const_int 4)))) | |
10195 | (set (reg:SI 11) | |
10196 | (mem:SI (plus:SI (match_dup 0) | |
10197 | (const_int 8)))) | |
10198 | (parallel [(call (mem:SI (match_dup 2)) | |
10199 | (match_operand 1 "" "")) | |
10200 | (use (reg:SI 2)) | |
10201 | (use (reg:SI 11)) | |
10202 | (set (reg:SI 2) | |
10203 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10204 | (clobber (scratch:SI))])] | |
10205 | "TARGET_32BIT" | |
10206 | " | |
10207 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10208 | |
cccf3bdc DE |
10209 | (define_expand "call_indirect_aix64" |
10210 | [(set (match_dup 2) | |
10211 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
10212 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10213 | (reg:DI 2)) | |
10214 | (set (reg:DI 2) | |
10215 | (mem:DI (plus:DI (match_dup 0) | |
10216 | (const_int 8)))) | |
10217 | (set (reg:DI 11) | |
10218 | (mem:DI (plus:DI (match_dup 0) | |
10219 | (const_int 16)))) | |
10220 | (parallel [(call (mem:SI (match_dup 2)) | |
10221 | (match_operand 1 "" "")) | |
10222 | (use (reg:DI 2)) | |
10223 | (use (reg:DI 11)) | |
10224 | (set (reg:DI 2) | |
10225 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10226 | (clobber (scratch:SI))])] | |
10227 | "TARGET_64BIT" | |
10228 | " | |
10229 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 10230 | |
cccf3bdc DE |
10231 | (define_expand "call_value_indirect_aix32" |
10232 | [(set (match_dup 3) | |
10233 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10234 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10235 | (reg:SI 2)) | |
10236 | (set (reg:SI 2) | |
10237 | (mem:SI (plus:SI (match_dup 1) | |
10238 | (const_int 4)))) | |
10239 | (set (reg:SI 11) | |
10240 | (mem:SI (plus:SI (match_dup 1) | |
10241 | (const_int 8)))) | |
10242 | (parallel [(set (match_operand 0 "" "") | |
10243 | (call (mem:SI (match_dup 3)) | |
10244 | (match_operand 2 "" ""))) | |
10245 | (use (reg:SI 2)) | |
10246 | (use (reg:SI 11)) | |
10247 | (set (reg:SI 2) | |
10248 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10249 | (clobber (scratch:SI))])] | |
10250 | "TARGET_32BIT" | |
10251 | " | |
10252 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10253 | |
cccf3bdc DE |
10254 | (define_expand "call_value_indirect_aix64" |
10255 | [(set (match_dup 3) | |
10256 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10257 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10258 | (reg:DI 2)) | |
10259 | (set (reg:DI 2) | |
10260 | (mem:DI (plus:DI (match_dup 1) | |
10261 | (const_int 8)))) | |
10262 | (set (reg:DI 11) | |
10263 | (mem:DI (plus:DI (match_dup 1) | |
10264 | (const_int 16)))) | |
10265 | (parallel [(set (match_operand 0 "" "") | |
10266 | (call (mem:SI (match_dup 3)) | |
10267 | (match_operand 2 "" ""))) | |
10268 | (use (reg:DI 2)) | |
10269 | (use (reg:DI 11)) | |
10270 | (set (reg:DI 2) | |
10271 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10272 | (clobber (scratch:SI))])] | |
10273 | "TARGET_64BIT" | |
10274 | " | |
10275 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 10276 | |
b6c9286a | 10277 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 10278 | (define_expand "call" |
a260abc9 | 10279 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 10280 | (match_operand 1 "" "")) |
4697a36c | 10281 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
10282 | (clobber (scratch:SI))])] |
10283 | "" | |
10284 | " | |
10285 | { | |
ee890fe2 | 10286 | #if TARGET_MACHO |
ab82a49f | 10287 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10288 | operands[0] = machopic_indirect_call_target (operands[0]); |
10289 | #endif | |
10290 | ||
1fd4e8c1 RK |
10291 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
10292 | abort (); | |
10293 | ||
10294 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 10295 | |
6a4cee5f | 10296 | if (GET_CODE (operands[0]) != SYMBOL_REF |
473f51b6 | 10297 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) |
efdba735 | 10298 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10299 | { |
6a4cee5f MM |
10300 | if (INTVAL (operands[2]) & CALL_LONG) |
10301 | operands[0] = rs6000_longcall_ref (operands[0]); | |
10302 | ||
cccf3bdc | 10303 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10304 | || DEFAULT_ABI == ABI_DARWIN) |
bbf294a5 | 10305 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10306 | |
cccf3bdc DE |
10307 | else if (DEFAULT_ABI == ABI_AIX) |
10308 | { | |
10309 | /* AIX function pointers are really pointers to a three word | |
10310 | area. */ | |
10311 | emit_call_insn (TARGET_32BIT | |
10312 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
10313 | operands[0]), | |
10314 | operands[1]) | |
10315 | : gen_call_indirect_aix64 (force_reg (DImode, | |
10316 | operands[0]), | |
10317 | operands[1])); | |
10318 | DONE; | |
b6c9286a | 10319 | } |
cccf3bdc DE |
10320 | else |
10321 | abort (); | |
1fd4e8c1 RK |
10322 | } |
10323 | }") | |
10324 | ||
10325 | (define_expand "call_value" | |
10326 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 10327 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 10328 | (match_operand 2 "" ""))) |
4697a36c | 10329 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
10330 | (clobber (scratch:SI))])] |
10331 | "" | |
10332 | " | |
10333 | { | |
ee890fe2 | 10334 | #if TARGET_MACHO |
ab82a49f | 10335 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10336 | operands[1] = machopic_indirect_call_target (operands[1]); |
10337 | #endif | |
10338 | ||
1fd4e8c1 RK |
10339 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
10340 | abort (); | |
10341 | ||
10342 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 10343 | |
6a4cee5f | 10344 | if (GET_CODE (operands[1]) != SYMBOL_REF |
473f51b6 | 10345 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) |
efdba735 | 10346 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10347 | { |
6756293c | 10348 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
10349 | operands[1] = rs6000_longcall_ref (operands[1]); |
10350 | ||
cccf3bdc | 10351 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10352 | || DEFAULT_ABI == ABI_DARWIN) |
bbf294a5 | 10353 | operands[1] = force_reg (Pmode, operands[1]); |
1fd4e8c1 | 10354 | |
cccf3bdc DE |
10355 | else if (DEFAULT_ABI == ABI_AIX) |
10356 | { | |
10357 | /* AIX function pointers are really pointers to a three word | |
10358 | area. */ | |
10359 | emit_call_insn (TARGET_32BIT | |
10360 | ? gen_call_value_indirect_aix32 (operands[0], | |
10361 | force_reg (SImode, | |
10362 | operands[1]), | |
10363 | operands[2]) | |
10364 | : gen_call_value_indirect_aix64 (operands[0], | |
10365 | force_reg (DImode, | |
10366 | operands[1]), | |
10367 | operands[2])); | |
10368 | DONE; | |
b6c9286a | 10369 | } |
cccf3bdc DE |
10370 | else |
10371 | abort (); | |
1fd4e8c1 RK |
10372 | } |
10373 | }") | |
10374 | ||
04780ee7 | 10375 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 10376 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10377 | ;; either the function was not prototyped, or it was prototyped as a |
10378 | ;; variable argument function. It is > 0 if FP registers were passed | |
10379 | ;; and < 0 if they were not. | |
04780ee7 | 10380 | |
a260abc9 | 10381 | (define_insn "*call_local32" |
4697a36c MM |
10382 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
10383 | (match_operand 1 "" "g,g")) | |
10384 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10385 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 10386 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
10387 | "* |
10388 | { | |
6a4cee5f MM |
10389 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
10390 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10391 | ||
10392 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10393 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 10394 | |
a226df46 | 10395 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 10396 | }" |
b7ff3d82 DE |
10397 | [(set_attr "type" "branch") |
10398 | (set_attr "length" "4,8")]) | |
04780ee7 | 10399 | |
a260abc9 DE |
10400 | (define_insn "*call_local64" |
10401 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10402 | (match_operand 1 "" "g,g")) | |
10403 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10404 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10405 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10406 | "* | |
10407 | { | |
10408 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10409 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10410 | ||
10411 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10412 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10413 | ||
10414 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
10415 | }" | |
10416 | [(set_attr "type" "branch") | |
10417 | (set_attr "length" "4,8")]) | |
10418 | ||
cccf3bdc | 10419 | (define_insn "*call_value_local32" |
d18dba68 | 10420 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10421 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
10422 | (match_operand 2 "" "g,g"))) | |
10423 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10424 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10425 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10426 | "* | |
10427 | { | |
10428 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10429 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10430 | ||
10431 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10432 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10433 | ||
10434 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10435 | }" | |
10436 | [(set_attr "type" "branch") | |
10437 | (set_attr "length" "4,8")]) | |
10438 | ||
10439 | ||
cccf3bdc | 10440 | (define_insn "*call_value_local64" |
d18dba68 | 10441 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10442 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
10443 | (match_operand 2 "" "g,g"))) | |
10444 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10445 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10446 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10447 | "* | |
10448 | { | |
10449 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10450 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10451 | ||
10452 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10453 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10454 | ||
10455 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10456 | }" | |
10457 | [(set_attr "type" "branch") | |
10458 | (set_attr "length" "4,8")]) | |
10459 | ||
04780ee7 | 10460 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 10461 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 10462 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10463 | ;; either the function was not prototyped, or it was prototyped as a |
10464 | ;; variable argument function. It is > 0 if FP registers were passed | |
10465 | ;; and < 0 if they were not. | |
04780ee7 | 10466 | |
cccf3bdc DE |
10467 | (define_insn "*call_indirect_nonlocal_aix32" |
10468 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
10469 | (match_operand 1 "" "g")) | |
10470 | (use (reg:SI 2)) | |
10471 | (use (reg:SI 11)) | |
10472 | (set (reg:SI 2) | |
10473 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 10474 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10475 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10476 | "b%T0l\;{l|lwz} 2,20(1)" | |
10477 | [(set_attr "type" "jmpreg") | |
10478 | (set_attr "length" "8")]) | |
10479 | ||
a260abc9 | 10480 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10481 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10482 | (match_operand 1 "" "g")) |
10483 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10484 | (clobber (match_scratch:SI 3 "=l"))] | |
10485 | "TARGET_32BIT | |
10486 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10487 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10488 | "bl %z0\;%." |
b7ff3d82 | 10489 | [(set_attr "type" "branch") |
cccf3bdc DE |
10490 | (set_attr "length" "8")]) |
10491 | ||
10492 | (define_insn "*call_indirect_nonlocal_aix64" | |
10493 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
10494 | (match_operand 1 "" "g")) | |
10495 | (use (reg:DI 2)) | |
10496 | (use (reg:DI 11)) | |
10497 | (set (reg:DI 2) | |
10498 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 10499 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10500 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10501 | "b%T0l\;ld 2,40(1)" | |
10502 | [(set_attr "type" "jmpreg") | |
10503 | (set_attr "length" "8")]) | |
59313e4e | 10504 | |
a260abc9 | 10505 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10506 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10507 | (match_operand 1 "" "g")) |
10508 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10509 | (clobber (match_scratch:SI 3 "=l"))] | |
6ae08853 | 10510 | "TARGET_64BIT |
9ebbca7d | 10511 | && DEFAULT_ABI == ABI_AIX |
a260abc9 | 10512 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10513 | "bl %z0\;%." |
a260abc9 | 10514 | [(set_attr "type" "branch") |
cccf3bdc | 10515 | (set_attr "length" "8")]) |
7509c759 | 10516 | |
cccf3bdc | 10517 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10518 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10519 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
10520 | (match_operand 2 "" "g"))) | |
10521 | (use (reg:SI 2)) | |
10522 | (use (reg:SI 11)) | |
10523 | (set (reg:SI 2) | |
10524 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10525 | (clobber (match_scratch:SI 3 "=l"))] | |
10526 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
10527 | "b%T1l\;{l|lwz} 2,20(1)" | |
10528 | [(set_attr "type" "jmpreg") | |
10529 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10530 | |
cccf3bdc | 10531 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10532 | [(set (match_operand 0 "" "") |
cc4d5fec | 10533 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10534 | (match_operand 2 "" "g"))) |
10535 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10536 | (clobber (match_scratch:SI 4 "=l"))] | |
10537 | "TARGET_32BIT | |
10538 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10539 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10540 | "bl %z1\;%." |
b7ff3d82 | 10541 | [(set_attr "type" "branch") |
cccf3bdc | 10542 | (set_attr "length" "8")]) |
04780ee7 | 10543 | |
cccf3bdc | 10544 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10545 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10546 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
10547 | (match_operand 2 "" "g"))) | |
10548 | (use (reg:DI 2)) | |
10549 | (use (reg:DI 11)) | |
10550 | (set (reg:DI 2) | |
10551 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10552 | (clobber (match_scratch:SI 3 "=l"))] | |
10553 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
10554 | "b%T1l\;ld 2,40(1)" | |
10555 | [(set_attr "type" "jmpreg") | |
10556 | (set_attr "length" "8")]) | |
10557 | ||
10558 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10559 | [(set (match_operand 0 "" "") |
cc4d5fec | 10560 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10561 | (match_operand 2 "" "g"))) |
10562 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10563 | (clobber (match_scratch:SI 4 "=l"))] | |
6ae08853 | 10564 | "TARGET_64BIT |
9ebbca7d | 10565 | && DEFAULT_ABI == ABI_AIX |
5a19791c | 10566 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10567 | "bl %z1\;%." |
10568 | [(set_attr "type" "branch") | |
10569 | (set_attr "length" "8")]) | |
10570 | ||
10571 | ;; A function pointer under System V is just a normal pointer | |
10572 | ;; operands[0] is the function pointer | |
10573 | ;; operands[1] is the stack size to clean up | |
10574 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10575 | ;; which indicates how to set cr1 | |
10576 | ||
a5c76ee6 ZW |
10577 | (define_insn "*call_indirect_nonlocal_sysv" |
10578 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) | |
10579 | (match_operand 1 "" "g,g")) | |
10580 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10581 | (clobber (match_scratch:SI 3 "=l,l"))] | |
50d440bc | 10582 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10583 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10584 | { |
cccf3bdc | 10585 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10586 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10587 | |
cccf3bdc | 10588 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10589 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10590 | |
a5c76ee6 ZW |
10591 | return "b%T0l"; |
10592 | } | |
10593 | [(set_attr "type" "jmpreg,jmpreg") | |
10594 | (set_attr "length" "4,8")]) | |
cccf3bdc | 10595 | |
a5c76ee6 ZW |
10596 | (define_insn "*call_nonlocal_sysv" |
10597 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10598 | (match_operand 1 "" "g,g")) | |
10599 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10600 | (clobber (match_scratch:SI 3 "=l,l"))] | |
efdba735 SH |
10601 | "(DEFAULT_ABI == ABI_DARWIN |
10602 | || (DEFAULT_ABI == ABI_V4 | |
10603 | && (INTVAL (operands[2]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10604 | { |
10605 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10606 | output_asm_insn ("crxor 6,6,6", operands); | |
10607 | ||
10608 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10609 | output_asm_insn ("creqv 6,6,6", operands); | |
10610 | ||
c989f2f7 | 10611 | #if TARGET_MACHO |
efdba735 SH |
10612 | return output_call(insn, operands, 0, 2); |
10613 | #else | |
a5c76ee6 | 10614 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; |
6ae08853 | 10615 | #endif |
a5c76ee6 ZW |
10616 | } |
10617 | [(set_attr "type" "branch,branch") | |
10618 | (set_attr "length" "4,8")]) | |
10619 | ||
10620 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10621 | [(set (match_operand 0 "" "") |
a5c76ee6 ZW |
10622 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) |
10623 | (match_operand 2 "" "g,g"))) | |
10624 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10625 | (clobber (match_scratch:SI 4 "=l,l"))] | |
50d440bc | 10626 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10627 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10628 | { |
6a4cee5f | 10629 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10630 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10631 | |
10632 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10633 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10634 | |
a5c76ee6 ZW |
10635 | return "b%T1l"; |
10636 | } | |
10637 | [(set_attr "type" "jmpreg,jmpreg") | |
10638 | (set_attr "length" "4,8")]) | |
10639 | ||
10640 | (define_insn "*call_value_nonlocal_sysv" | |
10641 | [(set (match_operand 0 "" "") | |
10642 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10643 | (match_operand 2 "" "g,g"))) | |
10644 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10645 | (clobber (match_scratch:SI 4 "=l,l"))] | |
efdba735 SH |
10646 | "(DEFAULT_ABI == ABI_DARWIN |
10647 | || (DEFAULT_ABI == ABI_V4 | |
10648 | && (INTVAL (operands[3]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10649 | { |
10650 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10651 | output_asm_insn ("crxor 6,6,6", operands); | |
10652 | ||
10653 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10654 | output_asm_insn ("creqv 6,6,6", operands); | |
10655 | ||
c989f2f7 | 10656 | #if TARGET_MACHO |
efdba735 SH |
10657 | return output_call(insn, operands, 1, 3); |
10658 | #else | |
a5c76ee6 | 10659 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; |
6ae08853 | 10660 | #endif |
a5c76ee6 ZW |
10661 | } |
10662 | [(set_attr "type" "branch,branch") | |
10663 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10664 | |
10665 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10666 | (define_expand "untyped_call" |
10667 | [(parallel [(call (match_operand 0 "" "") | |
10668 | (const_int 0)) | |
10669 | (match_operand 1 "" "") | |
10670 | (match_operand 2 "" "")])] | |
10671 | "" | |
10672 | " | |
10673 | { | |
10674 | int i; | |
10675 | ||
7d70b8b2 | 10676 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10677 | |
10678 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10679 | { | |
10680 | rtx set = XVECEXP (operands[2], 0, i); | |
10681 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10682 | } | |
10683 | ||
10684 | /* The optimizer does not know that the call sets the function value | |
10685 | registers we stored in the result block. We avoid problems by | |
10686 | claiming that all hard registers are used and clobbered at this | |
10687 | point. */ | |
10688 | emit_insn (gen_blockage ()); | |
10689 | ||
10690 | DONE; | |
10691 | }") | |
10692 | ||
5e1bf043 DJ |
10693 | ;; sibling call patterns |
10694 | (define_expand "sibcall" | |
10695 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
10696 | (match_operand 1 "" "")) | |
10697 | (use (match_operand 2 "" "")) | |
fe352c29 | 10698 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
10699 | (return)])] |
10700 | "" | |
10701 | " | |
10702 | { | |
10703 | #if TARGET_MACHO | |
ab82a49f | 10704 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10705 | operands[0] = machopic_indirect_call_target (operands[0]); |
10706 | #endif | |
10707 | ||
10708 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
10709 | abort (); | |
10710 | ||
10711 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 10712 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10713 | |
10714 | }") | |
10715 | ||
10716 | ;; this and similar patterns must be marked as using LR, otherwise | |
10717 | ;; dataflow will try to delete the store into it. This is true | |
10718 | ;; even when the actual reg to jump to is in CTR, when LR was | |
10719 | ;; saved and restored around the PIC-setting BCL. | |
10720 | (define_insn "*sibcall_local32" | |
10721 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
10722 | (match_operand 1 "" "g,g")) | |
10723 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10724 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10725 | (return)] |
10726 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
10727 | "* | |
10728 | { | |
10729 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10730 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10731 | ||
10732 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10733 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10734 | ||
10735 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10736 | }" | |
10737 | [(set_attr "type" "branch") | |
10738 | (set_attr "length" "4,8")]) | |
10739 | ||
10740 | (define_insn "*sibcall_local64" | |
10741 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10742 | (match_operand 1 "" "g,g")) | |
10743 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10744 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10745 | (return)] |
10746 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10747 | "* | |
10748 | { | |
10749 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10750 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10751 | ||
10752 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10753 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10754 | ||
10755 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10756 | }" | |
10757 | [(set_attr "type" "branch") | |
10758 | (set_attr "length" "4,8")]) | |
10759 | ||
10760 | (define_insn "*sibcall_value_local32" | |
10761 | [(set (match_operand 0 "" "") | |
10762 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
10763 | (match_operand 2 "" "g,g"))) | |
10764 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10765 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10766 | (return)] |
10767 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10768 | "* | |
10769 | { | |
10770 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10771 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10772 | ||
10773 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10774 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10775 | ||
10776 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10777 | }" | |
10778 | [(set_attr "type" "branch") | |
10779 | (set_attr "length" "4,8")]) | |
10780 | ||
10781 | ||
10782 | (define_insn "*sibcall_value_local64" | |
10783 | [(set (match_operand 0 "" "") | |
10784 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
10785 | (match_operand 2 "" "g,g"))) | |
10786 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10787 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10788 | (return)] |
10789 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10790 | "* | |
10791 | { | |
10792 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10793 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10794 | ||
10795 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10796 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10797 | ||
10798 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10799 | }" | |
10800 | [(set_attr "type" "branch") | |
10801 | (set_attr "length" "4,8")]) | |
10802 | ||
10803 | (define_insn "*sibcall_nonlocal_aix32" | |
10804 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
10805 | (match_operand 1 "" "g")) | |
10806 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10807 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10808 | (return)] |
10809 | "TARGET_32BIT | |
10810 | && DEFAULT_ABI == ABI_AIX | |
10811 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10812 | "b %z0" | |
10813 | [(set_attr "type" "branch") | |
10814 | (set_attr "length" "4")]) | |
10815 | ||
10816 | (define_insn "*sibcall_nonlocal_aix64" | |
10817 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
10818 | (match_operand 1 "" "g")) | |
10819 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10820 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 | 10821 | (return)] |
6ae08853 | 10822 | "TARGET_64BIT |
5e1bf043 DJ |
10823 | && DEFAULT_ABI == ABI_AIX |
10824 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10825 | "b %z0" | |
10826 | [(set_attr "type" "branch") | |
10827 | (set_attr "length" "4")]) | |
10828 | ||
10829 | (define_insn "*sibcall_value_nonlocal_aix32" | |
10830 | [(set (match_operand 0 "" "") | |
10831 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
10832 | (match_operand 2 "" "g"))) | |
10833 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10834 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10835 | (return)] |
10836 | "TARGET_32BIT | |
10837 | && DEFAULT_ABI == ABI_AIX | |
10838 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10839 | "b %z1" | |
10840 | [(set_attr "type" "branch") | |
10841 | (set_attr "length" "4")]) | |
10842 | ||
10843 | (define_insn "*sibcall_value_nonlocal_aix64" | |
10844 | [(set (match_operand 0 "" "") | |
10845 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
10846 | (match_operand 2 "" "g"))) | |
10847 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10848 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 | 10849 | (return)] |
6ae08853 | 10850 | "TARGET_64BIT |
5e1bf043 DJ |
10851 | && DEFAULT_ABI == ABI_AIX |
10852 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10853 | "b %z1" | |
10854 | [(set_attr "type" "branch") | |
10855 | (set_attr "length" "4")]) | |
10856 | ||
10857 | (define_insn "*sibcall_nonlocal_sysv" | |
10858 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10859 | (match_operand 1 "" "")) | |
10860 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 10861 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10862 | (return)] |
10863 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10864 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10865 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
10866 | "* | |
10867 | { | |
10868 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10869 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10870 | ||
10871 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10872 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10873 | ||
10874 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; | |
10875 | }" | |
10876 | [(set_attr "type" "branch,branch") | |
10877 | (set_attr "length" "4,8")]) | |
10878 | ||
10879 | (define_expand "sibcall_value" | |
10880 | [(parallel [(set (match_operand 0 "register_operand" "") | |
10881 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
10882 | (match_operand 2 "" ""))) | |
10883 | (use (match_operand 3 "" "")) | |
fe352c29 | 10884 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
10885 | (return)])] |
10886 | "" | |
10887 | " | |
10888 | { | |
10889 | #if TARGET_MACHO | |
ab82a49f | 10890 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10891 | operands[1] = machopic_indirect_call_target (operands[1]); |
10892 | #endif | |
10893 | ||
10894 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
10895 | abort (); | |
10896 | ||
10897 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 10898 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10899 | |
10900 | }") | |
10901 | ||
10902 | (define_insn "*sibcall_value_nonlocal_sysv" | |
10903 | [(set (match_operand 0 "" "") | |
10904 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10905 | (match_operand 2 "" ""))) | |
10906 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10907 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10908 | (return)] |
10909 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10910 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10911 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
10912 | "* | |
10913 | { | |
10914 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10915 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10916 | ||
10917 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10918 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10919 | ||
10920 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; | |
10921 | }" | |
10922 | [(set_attr "type" "branch,branch") | |
10923 | (set_attr "length" "4,8")]) | |
10924 | ||
10925 | (define_expand "sibcall_epilogue" | |
10926 | [(use (const_int 0))] | |
10927 | "TARGET_SCHED_PROLOG" | |
10928 | " | |
10929 | { | |
10930 | rs6000_emit_epilogue (TRUE); | |
10931 | DONE; | |
10932 | }") | |
10933 | ||
e6f948e3 RK |
10934 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
10935 | ;; all of memory. This blocks insns from being moved across this point. | |
10936 | ||
10937 | (define_insn "blockage" | |
615158e2 | 10938 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] |
e6f948e3 RK |
10939 | "" |
10940 | "") | |
1fd4e8c1 RK |
10941 | \f |
10942 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10943 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10944 | ;; |
10945 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10946 | ;; insns, and branches. We store the operands of compares until we see | |
10947 | ;; how it is used. | |
10948 | (define_expand "cmpsi" | |
10949 | [(set (cc0) | |
cd2b37d9 | 10950 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10951 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10952 | "" | |
10953 | " | |
10954 | { | |
10955 | /* Take care of the possibility that operands[1] might be negative but | |
10956 | this might be a logical operation. That insn doesn't exist. */ | |
10957 | if (GET_CODE (operands[1]) == CONST_INT | |
10958 | && INTVAL (operands[1]) < 0) | |
10959 | operands[1] = force_reg (SImode, operands[1]); | |
10960 | ||
10961 | rs6000_compare_op0 = operands[0]; | |
10962 | rs6000_compare_op1 = operands[1]; | |
10963 | rs6000_compare_fp_p = 0; | |
10964 | DONE; | |
10965 | }") | |
10966 | ||
266eb58a DE |
10967 | (define_expand "cmpdi" |
10968 | [(set (cc0) | |
10969 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10970 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10971 | "TARGET_POWERPC64" | |
10972 | " | |
10973 | { | |
10974 | /* Take care of the possibility that operands[1] might be negative but | |
10975 | this might be a logical operation. That insn doesn't exist. */ | |
10976 | if (GET_CODE (operands[1]) == CONST_INT | |
10977 | && INTVAL (operands[1]) < 0) | |
10978 | operands[1] = force_reg (DImode, operands[1]); | |
10979 | ||
10980 | rs6000_compare_op0 = operands[0]; | |
10981 | rs6000_compare_op1 = operands[1]; | |
10982 | rs6000_compare_fp_p = 0; | |
10983 | DONE; | |
10984 | }") | |
10985 | ||
1fd4e8c1 | 10986 | (define_expand "cmpsf" |
cd2b37d9 RK |
10987 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
10988 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10989 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10990 | " |
10991 | { | |
10992 | rs6000_compare_op0 = operands[0]; | |
10993 | rs6000_compare_op1 = operands[1]; | |
10994 | rs6000_compare_fp_p = 1; | |
10995 | DONE; | |
10996 | }") | |
10997 | ||
10998 | (define_expand "cmpdf" | |
cd2b37d9 RK |
10999 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
11000 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 11001 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11002 | " |
11003 | { | |
11004 | rs6000_compare_op0 = operands[0]; | |
11005 | rs6000_compare_op1 = operands[1]; | |
11006 | rs6000_compare_fp_p = 1; | |
11007 | DONE; | |
11008 | }") | |
11009 | ||
d6f99ca4 | 11010 | (define_expand "cmptf" |
e7a4130e DE |
11011 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
11012 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
39e63627 GK |
11013 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
11014 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
d6f99ca4 DE |
11015 | " |
11016 | { | |
11017 | rs6000_compare_op0 = operands[0]; | |
11018 | rs6000_compare_op1 = operands[1]; | |
11019 | rs6000_compare_fp_p = 1; | |
11020 | DONE; | |
11021 | }") | |
11022 | ||
1fd4e8c1 | 11023 | (define_expand "beq" |
39a10a29 | 11024 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11025 | "" |
39a10a29 | 11026 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11027 | |
11028 | (define_expand "bne" | |
39a10a29 | 11029 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11030 | "" |
39a10a29 | 11031 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 11032 | |
39a10a29 GK |
11033 | (define_expand "bge" |
11034 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11035 | "" |
39a10a29 | 11036 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
11037 | |
11038 | (define_expand "bgt" | |
39a10a29 | 11039 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11040 | "" |
39a10a29 | 11041 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
11042 | |
11043 | (define_expand "ble" | |
39a10a29 | 11044 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11045 | "" |
39a10a29 | 11046 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 11047 | |
39a10a29 GK |
11048 | (define_expand "blt" |
11049 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11050 | "" |
39a10a29 | 11051 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 11052 | |
39a10a29 GK |
11053 | (define_expand "bgeu" |
11054 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11055 | "" |
39a10a29 | 11056 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 11057 | |
39a10a29 GK |
11058 | (define_expand "bgtu" |
11059 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11060 | "" |
39a10a29 | 11061 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 11062 | |
39a10a29 GK |
11063 | (define_expand "bleu" |
11064 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11065 | "" |
39a10a29 | 11066 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 11067 | |
39a10a29 GK |
11068 | (define_expand "bltu" |
11069 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11070 | "" |
39a10a29 | 11071 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11072 | |
1c882ea4 | 11073 | (define_expand "bunordered" |
39a10a29 | 11074 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 11075 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 11076 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11077 | |
11078 | (define_expand "bordered" | |
39a10a29 | 11079 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 11080 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 11081 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11082 | |
11083 | (define_expand "buneq" | |
39a10a29 | 11084 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11085 | "" |
39a10a29 | 11086 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
11087 | |
11088 | (define_expand "bunge" | |
39a10a29 | 11089 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11090 | "" |
39a10a29 | 11091 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
11092 | |
11093 | (define_expand "bungt" | |
39a10a29 | 11094 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11095 | "" |
39a10a29 | 11096 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
11097 | |
11098 | (define_expand "bunle" | |
39a10a29 | 11099 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11100 | "" |
39a10a29 | 11101 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
11102 | |
11103 | (define_expand "bunlt" | |
39a10a29 | 11104 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11105 | "" |
39a10a29 | 11106 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
11107 | |
11108 | (define_expand "bltgt" | |
39a10a29 | 11109 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11110 | "" |
39a10a29 | 11111 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 11112 | |
1fd4e8c1 RK |
11113 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
11114 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
11115 | ;; with an scc insns. However, due to the order that combine see the | |
11116 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
11117 | ;; the cases we don't want to handle. | |
11118 | (define_expand "seq" | |
39a10a29 | 11119 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11120 | "" |
39a10a29 | 11121 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11122 | |
11123 | (define_expand "sne" | |
39a10a29 | 11124 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11125 | "" |
11126 | " | |
6ae08853 | 11127 | { |
39a10a29 | 11128 | if (! rs6000_compare_fp_p) |
1fd4e8c1 RK |
11129 | FAIL; |
11130 | ||
6ae08853 | 11131 | rs6000_emit_sCOND (NE, operands[0]); |
39a10a29 | 11132 | DONE; |
1fd4e8c1 RK |
11133 | }") |
11134 | ||
b7053a3f GK |
11135 | ;; A >= 0 is best done the portable way for A an integer. |
11136 | (define_expand "sge" | |
39a10a29 | 11137 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11138 | "" |
11139 | " | |
5638268e DE |
11140 | { |
11141 | if (! rs6000_compare_fp_p | |
11142 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
11143 | FAIL; |
11144 | ||
b7053a3f | 11145 | rs6000_emit_sCOND (GE, operands[0]); |
39a10a29 | 11146 | DONE; |
1fd4e8c1 RK |
11147 | }") |
11148 | ||
b7053a3f GK |
11149 | ;; A > 0 is best done using the portable sequence, so fail in that case. |
11150 | (define_expand "sgt" | |
39a10a29 | 11151 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11152 | "" |
11153 | " | |
5638268e | 11154 | { |
b7053a3f | 11155 | if (! rs6000_compare_fp_p |
5638268e | 11156 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) |
1fd4e8c1 RK |
11157 | FAIL; |
11158 | ||
6ae08853 | 11159 | rs6000_emit_sCOND (GT, operands[0]); |
39a10a29 | 11160 | DONE; |
1fd4e8c1 RK |
11161 | }") |
11162 | ||
b7053a3f GK |
11163 | ;; A <= 0 is best done the portable way for A an integer. |
11164 | (define_expand "sle" | |
39a10a29 | 11165 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11166 | "" |
5638268e DE |
11167 | " |
11168 | { | |
11169 | if (! rs6000_compare_fp_p | |
11170 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
11171 | FAIL; | |
11172 | ||
6ae08853 | 11173 | rs6000_emit_sCOND (LE, operands[0]); |
5638268e DE |
11174 | DONE; |
11175 | }") | |
1fd4e8c1 | 11176 | |
b7053a3f GK |
11177 | ;; A < 0 is best done in the portable way for A an integer. |
11178 | (define_expand "slt" | |
39a10a29 | 11179 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11180 | "" |
11181 | " | |
5638268e | 11182 | { |
6ae08853 | 11183 | if (! rs6000_compare_fp_p |
5638268e | 11184 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) |
1fd4e8c1 RK |
11185 | FAIL; |
11186 | ||
6ae08853 | 11187 | rs6000_emit_sCOND (LT, operands[0]); |
39a10a29 | 11188 | DONE; |
1fd4e8c1 RK |
11189 | }") |
11190 | ||
b7053a3f GK |
11191 | (define_expand "sgeu" |
11192 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11193 | "" | |
11194 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") | |
11195 | ||
1fd4e8c1 | 11196 | (define_expand "sgtu" |
39a10a29 | 11197 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11198 | "" |
39a10a29 | 11199 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 11200 | |
b7053a3f GK |
11201 | (define_expand "sleu" |
11202 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11203 | "" | |
11204 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") | |
11205 | ||
1fd4e8c1 | 11206 | (define_expand "sltu" |
39a10a29 | 11207 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11208 | "" |
39a10a29 | 11209 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11210 | |
b7053a3f | 11211 | (define_expand "sunordered" |
39a10a29 | 11212 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11213 | "" |
b7053a3f | 11214 | "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") |
1fd4e8c1 | 11215 | |
b7053a3f | 11216 | (define_expand "sordered" |
39a10a29 | 11217 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11218 | "" |
b7053a3f GK |
11219 | "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") |
11220 | ||
11221 | (define_expand "suneq" | |
11222 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11223 | "" | |
11224 | "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") | |
11225 | ||
11226 | (define_expand "sunge" | |
11227 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11228 | "" | |
11229 | "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") | |
11230 | ||
11231 | (define_expand "sungt" | |
11232 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11233 | "" | |
11234 | "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") | |
11235 | ||
11236 | (define_expand "sunle" | |
11237 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11238 | "" | |
11239 | "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") | |
11240 | ||
11241 | (define_expand "sunlt" | |
11242 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11243 | "" | |
11244 | "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") | |
11245 | ||
11246 | (define_expand "sltgt" | |
11247 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11248 | "" | |
11249 | "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") | |
11250 | ||
1fd4e8c1 RK |
11251 | \f |
11252 | ;; Here are the actual compare insns. | |
acad7ed3 | 11253 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 11254 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11255 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
11256 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
11257 | "" | |
7f340546 | 11258 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
b54cf83a | 11259 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11260 | |
acad7ed3 | 11261 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
11262 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
11263 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
11264 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11265 | "TARGET_POWERPC64" | |
11266 | "cmpd%I2 %0,%1,%2" | |
b54cf83a | 11267 | [(set_attr "type" "cmp")]) |
266eb58a | 11268 | |
f357808b RK |
11269 | ;; If we are comparing a register for equality with a large constant, |
11270 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
11271 | ;; register for the result of the XOR. | |
11272 | ||
11273 | (define_split | |
11274 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 11275 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 11276 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 11277 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
11278 | "find_single_use (operands[0], insn, 0) |
11279 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
11280 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
11281 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
11282 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
11283 | " | |
11284 | { | |
11285 | /* Get the constant we are comparing against, C, and see what it looks like | |
11286 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
11287 | with C to get the sign-extended value. */ | |
11288 | ||
5f59ecb7 | 11289 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 11290 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 11291 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 11292 | |
89e9f3a8 MM |
11293 | operands[4] = GEN_INT (xorv); |
11294 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
11295 | }") |
11296 | ||
acad7ed3 | 11297 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 11298 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11299 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 11300 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 11301 | "" |
e2c953b6 | 11302 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
b54cf83a | 11303 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11304 | |
acad7ed3 | 11305 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
11306 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
11307 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 11308 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 11309 | "" |
e2c953b6 | 11310 | "cmpld%I2 %0,%1,%b2" |
b54cf83a | 11311 | [(set_attr "type" "cmp")]) |
266eb58a | 11312 | |
1fd4e8c1 RK |
11313 | ;; The following two insns don't exist as single insns, but if we provide |
11314 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
11315 | ;; of the required delay between a compare and branch. We generate code for | |
11316 | ;; them by splitting. | |
11317 | ||
11318 | (define_insn "" | |
11319 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11320 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11321 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 11322 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11323 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11324 | "" | |
baf97f86 RK |
11325 | "#" |
11326 | [(set_attr "length" "8")]) | |
7e69e155 | 11327 | |
1fd4e8c1 RK |
11328 | (define_insn "" |
11329 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11330 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11331 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 11332 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11333 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11334 | "" | |
baf97f86 RK |
11335 | "#" |
11336 | [(set_attr "length" "8")]) | |
7e69e155 | 11337 | |
1fd4e8c1 RK |
11338 | (define_split |
11339 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 11340 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11341 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 11342 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11343 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11344 | "" | |
11345 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
11346 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11347 | ||
11348 | (define_split | |
11349 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 11350 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11351 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 11352 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11353 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11354 | "" | |
11355 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
11356 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11357 | ||
acad7ed3 | 11358 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 11359 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11360 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
11361 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11362 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11363 | "fcmpu %0,%1,%2" |
11364 | [(set_attr "type" "fpcompare")]) | |
11365 | ||
acad7ed3 | 11366 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 11367 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11368 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
11369 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11370 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11371 | "fcmpu %0,%1,%2" |
11372 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
11373 | |
11374 | ;; Only need to compare second words if first words equal | |
11375 | (define_insn "*cmptf_internal1" | |
11376 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11377 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11378 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
39e63627 GK |
11379 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
11380 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 | 11381 | "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
11382 | [(set_attr "type" "fpcompare") |
11383 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11384 | \f |
11385 | ;; Now we have the scc insns. We can do some combinations because of the | |
11386 | ;; way the machine works. | |
11387 | ;; | |
11388 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
11389 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
11390 | ;; cases the insns below which don't use an intermediate CR field will | |
11391 | ;; be used instead. | |
1fd4e8c1 | 11392 | (define_insn "" |
cd2b37d9 | 11393 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11394 | (match_operator:SI 1 "scc_comparison_operator" |
11395 | [(match_operand 2 "cc_reg_operand" "y") | |
11396 | (const_int 0)]))] | |
11397 | "" | |
2c4a9cff DE |
11398 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11399 | [(set (attr "type") | |
11400 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11401 | (const_string "mfcrf") | |
11402 | ] | |
11403 | (const_string "mfcr"))) | |
c1618c0c | 11404 | (set_attr "length" "8")]) |
1fd4e8c1 | 11405 | |
423c1189 | 11406 | ;; Same as above, but get the GT bit. |
6b1fedc3 | 11407 | (define_insn "move_from_CR_eq_bit" |
423c1189 | 11408 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6b1fedc3 | 11409 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))] |
423c1189 AH |
11410 | "TARGET_E500" |
11411 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1" | |
11412 | [(set_attr "type" "mfcr") | |
c1618c0c | 11413 | (set_attr "length" "8")]) |
423c1189 | 11414 | |
a3170dc6 AH |
11415 | ;; Same as above, but get the OV/ORDERED bit. |
11416 | (define_insn "move_from_CR_ov_bit" | |
11417 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
615158e2 | 11418 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] |
a3170dc6 | 11419 | "TARGET_ISEL" |
b7053a3f | 11420 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" |
b54cf83a | 11421 | [(set_attr "type" "mfcr") |
c1618c0c | 11422 | (set_attr "length" "8")]) |
a3170dc6 | 11423 | |
1fd4e8c1 | 11424 | (define_insn "" |
9ebbca7d GK |
11425 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11426 | (match_operator:DI 1 "scc_comparison_operator" | |
11427 | [(match_operand 2 "cc_reg_operand" "y") | |
11428 | (const_int 0)]))] | |
11429 | "TARGET_POWERPC64" | |
2c4a9cff DE |
11430 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11431 | [(set (attr "type") | |
11432 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11433 | (const_string "mfcrf") | |
11434 | ] | |
11435 | (const_string "mfcr"))) | |
c1618c0c | 11436 | (set_attr "length" "8")]) |
9ebbca7d GK |
11437 | |
11438 | (define_insn "" | |
11439 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11440 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 11441 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
11442 | (const_int 0)]) |
11443 | (const_int 0))) | |
9ebbca7d | 11444 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11445 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
4b8a63d6 | 11446 | "TARGET_32BIT" |
9ebbca7d | 11447 | "@ |
2c4a9cff | 11448 | mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 |
9ebbca7d | 11449 | #" |
b19003d8 | 11450 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11451 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11452 | |
11453 | (define_split | |
11454 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11455 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11456 | [(match_operand 2 "cc_reg_operand" "") | |
11457 | (const_int 0)]) | |
11458 | (const_int 0))) | |
11459 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11460 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
4b8a63d6 | 11461 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11462 | [(set (match_dup 3) |
11463 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11464 | (set (match_dup 0) | |
11465 | (compare:CC (match_dup 3) | |
11466 | (const_int 0)))] | |
11467 | "") | |
1fd4e8c1 RK |
11468 | |
11469 | (define_insn "" | |
cd2b37d9 | 11470 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11471 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11472 | [(match_operand 2 "cc_reg_operand" "y") | |
11473 | (const_int 0)]) | |
11474 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11475 | "" | |
11476 | "* | |
11477 | { | |
11478 | int is_bit = ccr_bit (operands[1], 1); | |
11479 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11480 | int count; | |
11481 | ||
11482 | if (is_bit >= put_bit) | |
11483 | count = is_bit - put_bit; | |
11484 | else | |
11485 | count = 32 - (put_bit - is_bit); | |
11486 | ||
89e9f3a8 MM |
11487 | operands[4] = GEN_INT (count); |
11488 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11489 | |
2c4a9cff | 11490 | return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11491 | }" |
2c4a9cff DE |
11492 | [(set (attr "type") |
11493 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11494 | (const_string "mfcrf") | |
11495 | ] | |
11496 | (const_string "mfcr"))) | |
c1618c0c | 11497 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
11498 | |
11499 | (define_insn "" | |
9ebbca7d | 11500 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11501 | (compare:CC |
11502 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11503 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11504 | (const_int 0)]) |
9ebbca7d | 11505 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11506 | (const_int 0))) |
9ebbca7d | 11507 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11508 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11509 | (match_dup 3)))] | |
ce71f754 | 11510 | "" |
1fd4e8c1 RK |
11511 | "* |
11512 | { | |
11513 | int is_bit = ccr_bit (operands[1], 1); | |
11514 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11515 | int count; | |
11516 | ||
9ebbca7d GK |
11517 | /* Force split for non-cc0 compare. */ |
11518 | if (which_alternative == 1) | |
11519 | return \"#\"; | |
11520 | ||
1fd4e8c1 RK |
11521 | if (is_bit >= put_bit) |
11522 | count = is_bit - put_bit; | |
11523 | else | |
11524 | count = 32 - (put_bit - is_bit); | |
11525 | ||
89e9f3a8 MM |
11526 | operands[5] = GEN_INT (count); |
11527 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11528 | |
2c4a9cff | 11529 | return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11530 | }" |
b19003d8 | 11531 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11532 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11533 | |
11534 | (define_split | |
11535 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11536 | (compare:CC | |
11537 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11538 | [(match_operand 2 "cc_reg_operand" "") | |
11539 | (const_int 0)]) | |
11540 | (match_operand:SI 3 "const_int_operand" "")) | |
11541 | (const_int 0))) | |
11542 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11543 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11544 | (match_dup 3)))] | |
ce71f754 | 11545 | "reload_completed" |
9ebbca7d GK |
11546 | [(set (match_dup 4) |
11547 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11548 | (match_dup 3))) | |
11549 | (set (match_dup 0) | |
11550 | (compare:CC (match_dup 4) | |
11551 | (const_int 0)))] | |
11552 | "") | |
1fd4e8c1 | 11553 | |
c5defebb RK |
11554 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11555 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11556 | ||
11557 | (define_peephole | |
cd2b37d9 | 11558 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11559 | (match_operator:SI 1 "scc_comparison_operator" |
11560 | [(match_operand 2 "cc_reg_operand" "y") | |
11561 | (const_int 0)])) | |
cd2b37d9 | 11562 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11563 | (match_operator:SI 4 "scc_comparison_operator" |
11564 | [(match_operand 5 "cc_reg_operand" "y") | |
11565 | (const_int 0)]))] | |
309323c2 | 11566 | "REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11567 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11568 | [(set_attr "type" "mfcr") |
c1618c0c | 11569 | (set_attr "length" "12")]) |
c5defebb | 11570 | |
9ebbca7d GK |
11571 | (define_peephole |
11572 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11573 | (match_operator:DI 1 "scc_comparison_operator" | |
11574 | [(match_operand 2 "cc_reg_operand" "y") | |
11575 | (const_int 0)])) | |
11576 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11577 | (match_operator:DI 4 "scc_comparison_operator" | |
11578 | [(match_operand 5 "cc_reg_operand" "y") | |
11579 | (const_int 0)]))] | |
309323c2 | 11580 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11581 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11582 | [(set_attr "type" "mfcr") |
c1618c0c | 11583 | (set_attr "length" "12")]) |
9ebbca7d | 11584 | |
1fd4e8c1 RK |
11585 | ;; There are some scc insns that can be done directly, without a compare. |
11586 | ;; These are faster because they don't involve the communications between | |
11587 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11588 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11589 | ;; | |
11590 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11591 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11592 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11593 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11594 | ||
11595 | ;; Have reload force a constant into a register for the simple insns that | |
11596 | ;; otherwise won't accept constants. We do this because it is faster than | |
11597 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11598 | ||
11599 | (define_insn "" | |
cd2b37d9 RK |
11600 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11601 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11602 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11603 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
683bdff7 | 11604 | "TARGET_32BIT" |
1fd4e8c1 | 11605 | "@ |
ca7f5001 | 11606 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11607 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11608 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11609 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
11610 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 11611 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11612 | |
a260abc9 DE |
11613 | (define_insn "" |
11614 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
11615 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
11616 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
11617 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
683bdff7 | 11618 | "TARGET_64BIT" |
a260abc9 DE |
11619 | "@ |
11620 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11621 | subfic %3,%1,0\;adde %0,%3,%1 | |
11622 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11623 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11624 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
11625 | [(set_attr "length" "12,8,12,12,12")]) | |
11626 | ||
1fd4e8c1 | 11627 | (define_insn "" |
9ebbca7d | 11628 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11629 | (compare:CC |
9ebbca7d GK |
11630 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11631 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 11632 | (const_int 0))) |
9ebbca7d | 11633 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11634 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11635 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11636 | "TARGET_32BIT" |
1fd4e8c1 | 11637 | "@ |
ca7f5001 RK |
11638 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11639 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
11640 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
11641 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
11642 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11643 | # | |
11644 | # | |
11645 | # | |
11646 | # | |
11647 | #" | |
b19003d8 | 11648 | [(set_attr "type" "compare") |
9ebbca7d GK |
11649 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11650 | ||
11651 | (define_split | |
11652 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11653 | (compare:CC | |
11654 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11655 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11656 | (const_int 0))) | |
11657 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11658 | (eq:SI (match_dup 1) (match_dup 2))) | |
11659 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11660 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11661 | [(parallel [(set (match_dup 0) |
11662 | (eq:SI (match_dup 1) (match_dup 2))) | |
11663 | (clobber (match_dup 3))]) | |
11664 | (set (match_dup 4) | |
11665 | (compare:CC (match_dup 0) | |
11666 | (const_int 0)))] | |
11667 | "") | |
b19003d8 | 11668 | |
a260abc9 | 11669 | (define_insn "" |
9ebbca7d | 11670 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 11671 | (compare:CC |
9ebbca7d GK |
11672 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11673 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 11674 | (const_int 0))) |
9ebbca7d | 11675 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 11676 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11677 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11678 | "TARGET_64BIT" |
a260abc9 DE |
11679 | "@ |
11680 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11681 | subfic %3,%1,0\;adde. %0,%3,%1 | |
11682 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11683 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
11684 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
11685 | # | |
11686 | # | |
11687 | # | |
11688 | # | |
11689 | #" | |
a260abc9 | 11690 | [(set_attr "type" "compare") |
9ebbca7d GK |
11691 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11692 | ||
11693 | (define_split | |
11694 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11695 | (compare:CC | |
11696 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11697 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
11698 | (const_int 0))) | |
11699 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11700 | (eq:DI (match_dup 1) (match_dup 2))) | |
11701 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11702 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11703 | [(parallel [(set (match_dup 0) |
11704 | (eq:DI (match_dup 1) (match_dup 2))) | |
11705 | (clobber (match_dup 3))]) | |
11706 | (set (match_dup 4) | |
11707 | (compare:CC (match_dup 0) | |
11708 | (const_int 0)))] | |
11709 | "") | |
a260abc9 | 11710 | |
b19003d8 RK |
11711 | ;; We have insns of the form shown by the first define_insn below. If |
11712 | ;; there is something inside the comparison operation, we must split it. | |
11713 | (define_split | |
11714 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11715 | (plus:SI (match_operator 1 "comparison_operator" | |
11716 | [(match_operand:SI 2 "" "") | |
11717 | (match_operand:SI 3 | |
11718 | "reg_or_cint_operand" "")]) | |
11719 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11720 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11721 | "! gpc_reg_operand (operands[2], SImode)" | |
11722 | [(set (match_dup 5) (match_dup 2)) | |
11723 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11724 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11725 | |
11726 | (define_insn "" | |
5276df18 | 11727 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11728 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11729 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 11730 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
683bdff7 | 11731 | "TARGET_32BIT" |
1fd4e8c1 | 11732 | "@ |
5276df18 DE |
11733 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11734 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11735 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11736 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11737 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
b19003d8 | 11738 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
11739 | |
11740 | (define_insn "" | |
9ebbca7d | 11741 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11742 | (compare:CC |
1fd4e8c1 | 11743 | (plus:SI |
9ebbca7d GK |
11744 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11745 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11746 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11747 | (const_int 0))) |
9ebbca7d | 11748 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
683bdff7 | 11749 | "TARGET_32BIT" |
1fd4e8c1 | 11750 | "@ |
ca7f5001 | 11751 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11752 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11753 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11754 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11755 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11756 | # | |
11757 | # | |
11758 | # | |
11759 | # | |
11760 | #" | |
b19003d8 | 11761 | [(set_attr "type" "compare") |
9ebbca7d GK |
11762 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11763 | ||
11764 | (define_split | |
11765 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11766 | (compare:CC | |
11767 | (plus:SI | |
11768 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11769 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11770 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11771 | (const_int 0))) | |
11772 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11773 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11774 | [(set (match_dup 4) |
11775 | (plus:SI (eq:SI (match_dup 1) | |
11776 | (match_dup 2)) | |
11777 | (match_dup 3))) | |
11778 | (set (match_dup 0) | |
11779 | (compare:CC (match_dup 4) | |
11780 | (const_int 0)))] | |
11781 | "") | |
1fd4e8c1 RK |
11782 | |
11783 | (define_insn "" | |
0387639b | 11784 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11785 | (compare:CC |
1fd4e8c1 | 11786 | (plus:SI |
9ebbca7d GK |
11787 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11788 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11789 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11790 | (const_int 0))) |
0387639b DE |
11791 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11792 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 11793 | "TARGET_32BIT" |
1fd4e8c1 | 11794 | "@ |
0387639b DE |
11795 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11796 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11797 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11798 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11799 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11800 | # |
11801 | # | |
11802 | # | |
11803 | # | |
11804 | #" | |
11805 | [(set_attr "type" "compare") | |
11806 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11807 | ||
11808 | (define_split | |
0387639b | 11809 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11810 | (compare:CC |
11811 | (plus:SI | |
11812 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11813 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11814 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11815 | (const_int 0))) | |
11816 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11817 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 11818 | "TARGET_32BIT && reload_completed" |
0387639b | 11819 | [(set (match_dup 0) |
9ebbca7d | 11820 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11821 | (set (match_dup 4) |
9ebbca7d GK |
11822 | (compare:CC (match_dup 0) |
11823 | (const_int 0)))] | |
11824 | "") | |
11825 | ||
1fd4e8c1 | 11826 | (define_insn "" |
cd2b37d9 | 11827 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11828 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11829 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
683bdff7 | 11830 | "TARGET_32BIT" |
1fd4e8c1 | 11831 | "@ |
ca7f5001 RK |
11832 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11833 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11834 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11835 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11836 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11837 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11838 | |
ea9be077 MM |
11839 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11840 | ;; since it nabs/sr is just as fast. | |
463b558b | 11841 | (define_insn "*ne0" |
b4e95693 | 11842 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11843 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11844 | (const_int 31))) | |
11845 | (clobber (match_scratch:SI 2 "=&r"))] | |
683bdff7 | 11846 | "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" |
ea9be077 MM |
11847 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
11848 | [(set_attr "length" "8")]) | |
11849 | ||
a260abc9 DE |
11850 | (define_insn "" |
11851 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11852 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11853 | (const_int 63))) | |
11854 | (clobber (match_scratch:DI 2 "=&r"))] | |
683bdff7 | 11855 | "TARGET_64BIT" |
a260abc9 DE |
11856 | "addic %2,%1,-1\;subfe %0,%2,%1" |
11857 | [(set_attr "length" "8")]) | |
11858 | ||
1fd4e8c1 RK |
11859 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11860 | (define_insn "" | |
cd2b37d9 | 11861 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11862 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11863 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11864 | (const_int 31)) |
cd2b37d9 | 11865 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11866 | (clobber (match_scratch:SI 3 "=&r"))] |
683bdff7 | 11867 | "TARGET_32BIT" |
ca7f5001 | 11868 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 11869 | [(set_attr "length" "8")]) |
1fd4e8c1 | 11870 | |
a260abc9 DE |
11871 | (define_insn "" |
11872 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11873 | (plus:DI (lshiftrt:DI | |
11874 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11875 | (const_int 63)) | |
11876 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11877 | (clobber (match_scratch:DI 3 "=&r"))] | |
683bdff7 | 11878 | "TARGET_64BIT" |
a260abc9 DE |
11879 | "addic %3,%1,-1\;addze %0,%2" |
11880 | [(set_attr "length" "8")]) | |
11881 | ||
1fd4e8c1 | 11882 | (define_insn "" |
9ebbca7d | 11883 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11884 | (compare:CC |
11885 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11886 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11887 | (const_int 31)) |
9ebbca7d | 11888 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11889 | (const_int 0))) |
889b90a1 GK |
11890 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11891 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
683bdff7 | 11892 | "TARGET_32BIT" |
9ebbca7d GK |
11893 | "@ |
11894 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11895 | #" | |
b19003d8 | 11896 | [(set_attr "type" "compare") |
9ebbca7d GK |
11897 | (set_attr "length" "8,12")]) |
11898 | ||
11899 | (define_split | |
11900 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11901 | (compare:CC | |
11902 | (plus:SI (lshiftrt:SI | |
11903 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11904 | (const_int 31)) | |
11905 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11906 | (const_int 0))) | |
889b90a1 GK |
11907 | (clobber (match_scratch:SI 3 "")) |
11908 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11909 | "TARGET_32BIT && reload_completed" |
889b90a1 | 11910 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
11911 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
11912 | (const_int 31)) | |
11913 | (match_dup 2))) | |
889b90a1 | 11914 | (clobber (match_dup 4))]) |
9ebbca7d GK |
11915 | (set (match_dup 0) |
11916 | (compare:CC (match_dup 3) | |
11917 | (const_int 0)))] | |
11918 | "") | |
1fd4e8c1 | 11919 | |
a260abc9 | 11920 | (define_insn "" |
9ebbca7d | 11921 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11922 | (compare:CC |
11923 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11924 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11925 | (const_int 63)) |
9ebbca7d | 11926 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11927 | (const_int 0))) |
9ebbca7d | 11928 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11929 | "TARGET_64BIT" |
9ebbca7d GK |
11930 | "@ |
11931 | addic %3,%1,-1\;addze. %3,%2 | |
11932 | #" | |
a260abc9 | 11933 | [(set_attr "type" "compare") |
9ebbca7d GK |
11934 | (set_attr "length" "8,12")]) |
11935 | ||
11936 | (define_split | |
11937 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11938 | (compare:CC | |
11939 | (plus:DI (lshiftrt:DI | |
11940 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11941 | (const_int 63)) | |
11942 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11943 | (const_int 0))) | |
11944 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11945 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11946 | [(set (match_dup 3) |
11947 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11948 | (const_int 63)) | |
11949 | (match_dup 2))) | |
11950 | (set (match_dup 0) | |
11951 | (compare:CC (match_dup 3) | |
11952 | (const_int 0)))] | |
11953 | "") | |
a260abc9 | 11954 | |
1fd4e8c1 | 11955 | (define_insn "" |
9ebbca7d | 11956 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11957 | (compare:CC |
11958 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11959 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11960 | (const_int 31)) |
9ebbca7d | 11961 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11962 | (const_int 0))) |
9ebbca7d | 11963 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11964 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11965 | (match_dup 2))) | |
9ebbca7d | 11966 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 11967 | "TARGET_32BIT" |
9ebbca7d GK |
11968 | "@ |
11969 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11970 | #" | |
b19003d8 | 11971 | [(set_attr "type" "compare") |
9ebbca7d GK |
11972 | (set_attr "length" "8,12")]) |
11973 | ||
11974 | (define_split | |
11975 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11976 | (compare:CC | |
11977 | (plus:SI (lshiftrt:SI | |
11978 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11979 | (const_int 31)) | |
11980 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11981 | (const_int 0))) | |
11982 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11983 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11984 | (match_dup 2))) | |
11985 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11986 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11987 | [(parallel [(set (match_dup 0) |
11988 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11989 | (match_dup 2))) | |
11990 | (clobber (match_dup 3))]) | |
11991 | (set (match_dup 4) | |
11992 | (compare:CC (match_dup 0) | |
11993 | (const_int 0)))] | |
11994 | "") | |
1fd4e8c1 | 11995 | |
a260abc9 | 11996 | (define_insn "" |
9ebbca7d | 11997 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11998 | (compare:CC |
11999 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 12000 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 12001 | (const_int 63)) |
9ebbca7d | 12002 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 12003 | (const_int 0))) |
9ebbca7d | 12004 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
12005 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
12006 | (match_dup 2))) | |
9ebbca7d | 12007 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 12008 | "TARGET_64BIT" |
9ebbca7d GK |
12009 | "@ |
12010 | addic %3,%1,-1\;addze. %0,%2 | |
12011 | #" | |
a260abc9 | 12012 | [(set_attr "type" "compare") |
9ebbca7d GK |
12013 | (set_attr "length" "8,12")]) |
12014 | ||
12015 | (define_split | |
12016 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12017 | (compare:CC | |
12018 | (plus:DI (lshiftrt:DI | |
12019 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
12020 | (const_int 63)) | |
12021 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12022 | (const_int 0))) | |
12023 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12024 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
12025 | (match_dup 2))) | |
12026 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 12027 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12028 | [(parallel [(set (match_dup 0) |
12029 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
12030 | (match_dup 2))) | |
12031 | (clobber (match_dup 3))]) | |
12032 | (set (match_dup 4) | |
12033 | (compare:CC (match_dup 0) | |
12034 | (const_int 0)))] | |
12035 | "") | |
a260abc9 | 12036 | |
1fd4e8c1 | 12037 | (define_insn "" |
cd2b37d9 RK |
12038 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12039 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
12040 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
12041 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 12042 | "TARGET_POWER" |
1fd4e8c1 | 12043 | "@ |
ca7f5001 | 12044 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 12045 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12046 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12047 | |
12048 | (define_insn "" | |
9ebbca7d | 12049 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12050 | (compare:CC |
9ebbca7d GK |
12051 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12052 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 12053 | (const_int 0))) |
9ebbca7d | 12054 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12055 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12056 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 12057 | "TARGET_POWER" |
1fd4e8c1 | 12058 | "@ |
ca7f5001 | 12059 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
12060 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
12061 | # | |
12062 | #" | |
12063 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
12064 | (set_attr "length" "12,12,16,16")]) | |
12065 | ||
12066 | (define_split | |
12067 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12068 | (compare:CC | |
12069 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12070 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12071 | (const_int 0))) | |
12072 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12073 | (le:SI (match_dup 1) (match_dup 2))) | |
12074 | (clobber (match_scratch:SI 3 ""))] | |
12075 | "TARGET_POWER && reload_completed" | |
12076 | [(parallel [(set (match_dup 0) | |
12077 | (le:SI (match_dup 1) (match_dup 2))) | |
12078 | (clobber (match_dup 3))]) | |
12079 | (set (match_dup 4) | |
12080 | (compare:CC (match_dup 0) | |
12081 | (const_int 0)))] | |
12082 | "") | |
1fd4e8c1 RK |
12083 | |
12084 | (define_insn "" | |
097657c3 | 12085 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12086 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12087 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 12088 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 12089 | "TARGET_POWER" |
1fd4e8c1 | 12090 | "@ |
097657c3 AM |
12091 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
12092 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 12093 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12094 | |
12095 | (define_insn "" | |
9ebbca7d | 12096 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12097 | (compare:CC |
9ebbca7d GK |
12098 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12099 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12100 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12101 | (const_int 0))) |
9ebbca7d | 12102 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 12103 | "TARGET_POWER" |
1fd4e8c1 | 12104 | "@ |
ca7f5001 | 12105 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12106 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
12107 | # | |
12108 | #" | |
b19003d8 | 12109 | [(set_attr "type" "compare") |
9ebbca7d GK |
12110 | (set_attr "length" "12,12,16,16")]) |
12111 | ||
12112 | (define_split | |
12113 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12114 | (compare:CC | |
12115 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12116 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12117 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12118 | (const_int 0))) | |
12119 | (clobber (match_scratch:SI 4 ""))] | |
12120 | "TARGET_POWER && reload_completed" | |
12121 | [(set (match_dup 4) | |
12122 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12123 | (match_dup 3))) |
9ebbca7d GK |
12124 | (set (match_dup 0) |
12125 | (compare:CC (match_dup 4) | |
12126 | (const_int 0)))] | |
12127 | "") | |
1fd4e8c1 RK |
12128 | |
12129 | (define_insn "" | |
097657c3 | 12130 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12131 | (compare:CC |
9ebbca7d GK |
12132 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12133 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12134 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12135 | (const_int 0))) |
097657c3 AM |
12136 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12137 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12138 | "TARGET_POWER" |
1fd4e8c1 | 12139 | "@ |
097657c3 AM |
12140 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
12141 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12142 | # |
12143 | #" | |
b19003d8 | 12144 | [(set_attr "type" "compare") |
9ebbca7d GK |
12145 | (set_attr "length" "12,12,16,16")]) |
12146 | ||
12147 | (define_split | |
097657c3 | 12148 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12149 | (compare:CC |
12150 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12151 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12152 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12153 | (const_int 0))) | |
12154 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12155 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12156 | "TARGET_POWER && reload_completed" |
097657c3 | 12157 | [(set (match_dup 0) |
9ebbca7d | 12158 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12159 | (set (match_dup 4) |
9ebbca7d GK |
12160 | (compare:CC (match_dup 0) |
12161 | (const_int 0)))] | |
12162 | "") | |
1fd4e8c1 RK |
12163 | |
12164 | (define_insn "" | |
cd2b37d9 RK |
12165 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12166 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12167 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 12168 | "TARGET_POWER" |
1fd4e8c1 | 12169 | "@ |
ca7f5001 RK |
12170 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
12171 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12172 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12173 | |
12174 | (define_insn "" | |
cd2b37d9 RK |
12175 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12176 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12177 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
4b8a63d6 | 12178 | "TARGET_32BIT" |
ca7f5001 | 12179 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 12180 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12181 | |
f9562f27 DE |
12182 | (define_insn "" |
12183 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12184 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12185 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 12186 | "TARGET_64BIT" |
f9562f27 DE |
12187 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" |
12188 | [(set_attr "length" "12")]) | |
12189 | ||
12190 | (define_insn "" | |
9ebbca7d | 12191 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12192 | (compare:CC |
9ebbca7d GK |
12193 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12194 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12195 | (const_int 0))) |
9ebbca7d | 12196 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 12197 | (leu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12198 | "TARGET_64BIT" |
9ebbca7d GK |
12199 | "@ |
12200 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
12201 | #" | |
f9562f27 | 12202 | [(set_attr "type" "compare") |
9ebbca7d GK |
12203 | (set_attr "length" "12,16")]) |
12204 | ||
12205 | (define_split | |
12206 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12207 | (compare:CC | |
12208 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12209 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12210 | (const_int 0))) | |
12211 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12212 | (leu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12213 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12214 | [(set (match_dup 0) |
12215 | (leu:DI (match_dup 1) (match_dup 2))) | |
12216 | (set (match_dup 3) | |
12217 | (compare:CC (match_dup 0) | |
12218 | (const_int 0)))] | |
12219 | "") | |
f9562f27 | 12220 | |
1fd4e8c1 | 12221 | (define_insn "" |
9ebbca7d | 12222 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12223 | (compare:CC |
9ebbca7d GK |
12224 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12225 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12226 | (const_int 0))) |
9ebbca7d | 12227 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12228 | (leu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12229 | "TARGET_32BIT" |
9ebbca7d GK |
12230 | "@ |
12231 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
12232 | #" | |
b19003d8 | 12233 | [(set_attr "type" "compare") |
9ebbca7d GK |
12234 | (set_attr "length" "12,16")]) |
12235 | ||
12236 | (define_split | |
12237 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12238 | (compare:CC | |
12239 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12240 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12241 | (const_int 0))) | |
12242 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12243 | (leu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12244 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12245 | [(set (match_dup 0) |
12246 | (leu:SI (match_dup 1) (match_dup 2))) | |
12247 | (set (match_dup 3) | |
12248 | (compare:CC (match_dup 0) | |
12249 | (const_int 0)))] | |
12250 | "") | |
1fd4e8c1 RK |
12251 | |
12252 | (define_insn "" | |
80103f96 | 12253 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12254 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12255 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 12256 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12257 | "TARGET_32BIT" |
80103f96 | 12258 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 12259 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12260 | |
12261 | (define_insn "" | |
9ebbca7d | 12262 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12263 | (compare:CC |
9ebbca7d GK |
12264 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12265 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12266 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12267 | (const_int 0))) |
9ebbca7d | 12268 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12269 | "TARGET_32BIT" |
9ebbca7d GK |
12270 | "@ |
12271 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
12272 | #" | |
b19003d8 | 12273 | [(set_attr "type" "compare") |
9ebbca7d GK |
12274 | (set_attr "length" "8,12")]) |
12275 | ||
12276 | (define_split | |
12277 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12278 | (compare:CC | |
12279 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12280 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12281 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12282 | (const_int 0))) | |
12283 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12284 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12285 | [(set (match_dup 4) |
12286 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
12287 | (match_dup 3))) | |
12288 | (set (match_dup 0) | |
12289 | (compare:CC (match_dup 4) | |
12290 | (const_int 0)))] | |
12291 | "") | |
1fd4e8c1 RK |
12292 | |
12293 | (define_insn "" | |
097657c3 | 12294 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12295 | (compare:CC |
9ebbca7d GK |
12296 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12297 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12298 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12299 | (const_int 0))) |
097657c3 AM |
12300 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12301 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12302 | "TARGET_32BIT" |
9ebbca7d | 12303 | "@ |
097657c3 | 12304 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 12305 | #" |
b19003d8 | 12306 | [(set_attr "type" "compare") |
9ebbca7d GK |
12307 | (set_attr "length" "8,12")]) |
12308 | ||
12309 | (define_split | |
097657c3 | 12310 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12311 | (compare:CC |
12312 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12313 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12314 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12315 | (const_int 0))) | |
12316 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12317 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12318 | "TARGET_32BIT && reload_completed" |
097657c3 | 12319 | [(set (match_dup 0) |
9ebbca7d | 12320 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12321 | (set (match_dup 4) |
9ebbca7d GK |
12322 | (compare:CC (match_dup 0) |
12323 | (const_int 0)))] | |
12324 | "") | |
1fd4e8c1 RK |
12325 | |
12326 | (define_insn "" | |
cd2b37d9 RK |
12327 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12328 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12329 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 12330 | "TARGET_32BIT" |
ca7f5001 | 12331 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 12332 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12333 | |
12334 | (define_insn "" | |
097657c3 | 12335 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 12336 | (and:SI (neg:SI |
cd2b37d9 | 12337 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12338 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 12339 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12340 | "TARGET_32BIT" |
097657c3 | 12341 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
b19003d8 | 12342 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12343 | |
12344 | (define_insn "" | |
9ebbca7d | 12345 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12346 | (compare:CC |
12347 | (and:SI (neg:SI | |
9ebbca7d GK |
12348 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12349 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12350 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12351 | (const_int 0))) |
9ebbca7d | 12352 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12353 | "TARGET_32BIT" |
9ebbca7d GK |
12354 | "@ |
12355 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
12356 | #" | |
12357 | [(set_attr "type" "compare") | |
12358 | (set_attr "length" "12,16")]) | |
12359 | ||
12360 | (define_split | |
12361 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12362 | (compare:CC | |
12363 | (and:SI (neg:SI | |
12364 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12365 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12366 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12367 | (const_int 0))) | |
12368 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12369 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12370 | [(set (match_dup 4) |
097657c3 AM |
12371 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
12372 | (match_dup 3))) | |
9ebbca7d GK |
12373 | (set (match_dup 0) |
12374 | (compare:CC (match_dup 4) | |
12375 | (const_int 0)))] | |
12376 | "") | |
1fd4e8c1 RK |
12377 | |
12378 | (define_insn "" | |
097657c3 | 12379 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12380 | (compare:CC |
12381 | (and:SI (neg:SI | |
9ebbca7d GK |
12382 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12383 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12384 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12385 | (const_int 0))) |
097657c3 AM |
12386 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12387 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12388 | "TARGET_32BIT" |
9ebbca7d | 12389 | "@ |
097657c3 | 12390 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 12391 | #" |
b19003d8 | 12392 | [(set_attr "type" "compare") |
9ebbca7d GK |
12393 | (set_attr "length" "12,16")]) |
12394 | ||
12395 | (define_split | |
097657c3 | 12396 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12397 | (compare:CC |
12398 | (and:SI (neg:SI | |
12399 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12400 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12401 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12402 | (const_int 0))) | |
12403 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12404 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 12405 | "TARGET_32BIT && reload_completed" |
097657c3 AM |
12406 | [(set (match_dup 0) |
12407 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
12408 | (match_dup 3))) | |
12409 | (set (match_dup 4) | |
9ebbca7d GK |
12410 | (compare:CC (match_dup 0) |
12411 | (const_int 0)))] | |
12412 | "") | |
1fd4e8c1 RK |
12413 | |
12414 | (define_insn "" | |
cd2b37d9 RK |
12415 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12416 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12417 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 12418 | "TARGET_POWER" |
7f340546 | 12419 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12420 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12421 | |
12422 | (define_insn "" | |
9ebbca7d | 12423 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12424 | (compare:CC |
9ebbca7d GK |
12425 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12426 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12427 | (const_int 0))) |
9ebbca7d | 12428 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12429 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12430 | "TARGET_POWER" |
9ebbca7d GK |
12431 | "@ |
12432 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12433 | #" | |
29ae5b89 | 12434 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12435 | (set_attr "length" "12,16")]) |
12436 | ||
12437 | (define_split | |
12438 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12439 | (compare:CC | |
12440 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12441 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12442 | (const_int 0))) | |
12443 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12444 | (lt:SI (match_dup 1) (match_dup 2)))] | |
12445 | "TARGET_POWER && reload_completed" | |
12446 | [(set (match_dup 0) | |
12447 | (lt:SI (match_dup 1) (match_dup 2))) | |
12448 | (set (match_dup 3) | |
12449 | (compare:CC (match_dup 0) | |
12450 | (const_int 0)))] | |
12451 | "") | |
1fd4e8c1 RK |
12452 | |
12453 | (define_insn "" | |
097657c3 | 12454 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12455 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12456 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12457 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12458 | "TARGET_POWER" |
097657c3 | 12459 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12460 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12461 | |
12462 | (define_insn "" | |
9ebbca7d | 12463 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12464 | (compare:CC |
9ebbca7d GK |
12465 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12466 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12467 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12468 | (const_int 0))) |
9ebbca7d | 12469 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12470 | "TARGET_POWER" |
9ebbca7d GK |
12471 | "@ |
12472 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12473 | #" | |
b19003d8 | 12474 | [(set_attr "type" "compare") |
9ebbca7d GK |
12475 | (set_attr "length" "12,16")]) |
12476 | ||
12477 | (define_split | |
12478 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12479 | (compare:CC | |
12480 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12481 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12482 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12483 | (const_int 0))) | |
12484 | (clobber (match_scratch:SI 4 ""))] | |
12485 | "TARGET_POWER && reload_completed" | |
12486 | [(set (match_dup 4) | |
12487 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12488 | (match_dup 3))) |
9ebbca7d GK |
12489 | (set (match_dup 0) |
12490 | (compare:CC (match_dup 4) | |
12491 | (const_int 0)))] | |
12492 | "") | |
1fd4e8c1 RK |
12493 | |
12494 | (define_insn "" | |
097657c3 | 12495 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12496 | (compare:CC |
9ebbca7d GK |
12497 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12498 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12499 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12500 | (const_int 0))) |
097657c3 AM |
12501 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12502 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12503 | "TARGET_POWER" |
9ebbca7d | 12504 | "@ |
097657c3 | 12505 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12506 | #" |
b19003d8 | 12507 | [(set_attr "type" "compare") |
9ebbca7d GK |
12508 | (set_attr "length" "12,16")]) |
12509 | ||
12510 | (define_split | |
097657c3 | 12511 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12512 | (compare:CC |
12513 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12514 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12515 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12516 | (const_int 0))) | |
12517 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12518 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12519 | "TARGET_POWER && reload_completed" |
097657c3 | 12520 | [(set (match_dup 0) |
9ebbca7d | 12521 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12522 | (set (match_dup 4) |
9ebbca7d GK |
12523 | (compare:CC (match_dup 0) |
12524 | (const_int 0)))] | |
12525 | "") | |
1fd4e8c1 RK |
12526 | |
12527 | (define_insn "" | |
cd2b37d9 RK |
12528 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12529 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12530 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12531 | "TARGET_POWER" |
12532 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12533 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12534 | |
12535 | (define_insn "" | |
cd2b37d9 RK |
12536 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12537 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12538 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12539 | "TARGET_32BIT" |
1fd4e8c1 | 12540 | "@ |
ca7f5001 RK |
12541 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
12542 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 12543 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12544 | |
12545 | (define_insn "" | |
9ebbca7d | 12546 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12547 | (compare:CC |
9ebbca7d GK |
12548 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12549 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12550 | (const_int 0))) |
9ebbca7d | 12551 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12552 | (ltu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12553 | "TARGET_32BIT" |
1fd4e8c1 | 12554 | "@ |
ca7f5001 | 12555 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12556 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12557 | # | |
12558 | #" | |
b19003d8 | 12559 | [(set_attr "type" "compare") |
9ebbca7d GK |
12560 | (set_attr "length" "12,12,16,16")]) |
12561 | ||
12562 | (define_split | |
12563 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12564 | (compare:CC | |
12565 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12566 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12567 | (const_int 0))) | |
12568 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12569 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12570 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12571 | [(set (match_dup 0) |
12572 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12573 | (set (match_dup 3) | |
12574 | (compare:CC (match_dup 0) | |
12575 | (const_int 0)))] | |
12576 | "") | |
1fd4e8c1 RK |
12577 | |
12578 | (define_insn "" | |
80103f96 | 12579 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
12580 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12581 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
80103f96 | 12582 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] |
683bdff7 | 12583 | "TARGET_32BIT" |
1fd4e8c1 | 12584 | "@ |
80103f96 FS |
12585 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3 |
12586 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
b19003d8 | 12587 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12588 | |
12589 | (define_insn "" | |
9ebbca7d | 12590 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12591 | (compare:CC |
9ebbca7d GK |
12592 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12593 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12594 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12595 | (const_int 0))) |
9ebbca7d | 12596 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12597 | "TARGET_32BIT" |
1fd4e8c1 | 12598 | "@ |
ca7f5001 | 12599 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
12600 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12601 | # | |
12602 | #" | |
b19003d8 | 12603 | [(set_attr "type" "compare") |
9ebbca7d GK |
12604 | (set_attr "length" "12,12,16,16")]) |
12605 | ||
12606 | (define_split | |
12607 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12608 | (compare:CC | |
12609 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12610 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12611 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12612 | (const_int 0))) | |
12613 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12614 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12615 | [(set (match_dup 4) |
12616 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12617 | (match_dup 3))) |
9ebbca7d GK |
12618 | (set (match_dup 0) |
12619 | (compare:CC (match_dup 4) | |
12620 | (const_int 0)))] | |
12621 | "") | |
1fd4e8c1 RK |
12622 | |
12623 | (define_insn "" | |
097657c3 | 12624 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12625 | (compare:CC |
9ebbca7d GK |
12626 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12627 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12628 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12629 | (const_int 0))) |
097657c3 AM |
12630 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12631 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12632 | "TARGET_32BIT" |
1fd4e8c1 | 12633 | "@ |
097657c3 AM |
12634 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 |
12635 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
12636 | # |
12637 | #" | |
b19003d8 | 12638 | [(set_attr "type" "compare") |
9ebbca7d GK |
12639 | (set_attr "length" "12,12,16,16")]) |
12640 | ||
12641 | (define_split | |
097657c3 | 12642 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12643 | (compare:CC |
12644 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12645 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12646 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12647 | (const_int 0))) | |
12648 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12649 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12650 | "TARGET_32BIT && reload_completed" |
097657c3 | 12651 | [(set (match_dup 0) |
9ebbca7d | 12652 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12653 | (set (match_dup 4) |
9ebbca7d GK |
12654 | (compare:CC (match_dup 0) |
12655 | (const_int 0)))] | |
12656 | "") | |
1fd4e8c1 RK |
12657 | |
12658 | (define_insn "" | |
cd2b37d9 RK |
12659 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12660 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12661 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
683bdff7 | 12662 | "TARGET_32BIT" |
1fd4e8c1 | 12663 | "@ |
ca7f5001 RK |
12664 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12665 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12666 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12667 | |
12668 | (define_insn "" | |
cd2b37d9 RK |
12669 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12670 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12671 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12672 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12673 | "TARGET_POWER" |
12674 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12675 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12676 | |
9ebbca7d GK |
12677 | (define_insn "" |
12678 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12679 | (compare:CC |
9ebbca7d GK |
12680 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12681 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12682 | (const_int 0))) |
9ebbca7d | 12683 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12684 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12685 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12686 | "TARGET_POWER" |
9ebbca7d GK |
12687 | "@ |
12688 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12689 | #" | |
12690 | [(set_attr "type" "compare") | |
12691 | (set_attr "length" "12,16")]) | |
12692 | ||
12693 | (define_split | |
12694 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12695 | (compare:CC | |
12696 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12697 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12698 | (const_int 0))) | |
12699 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12700 | (ge:SI (match_dup 1) (match_dup 2))) | |
12701 | (clobber (match_scratch:SI 3 ""))] | |
12702 | "TARGET_POWER && reload_completed" | |
12703 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12704 | (ge:SI (match_dup 1) (match_dup 2))) |
12705 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12706 | (set (match_dup 4) |
12707 | (compare:CC (match_dup 0) | |
12708 | (const_int 0)))] | |
12709 | "") | |
12710 | ||
1fd4e8c1 | 12711 | (define_insn "" |
097657c3 | 12712 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12713 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12714 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12715 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12716 | "TARGET_POWER" |
097657c3 | 12717 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12718 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12719 | |
12720 | (define_insn "" | |
9ebbca7d | 12721 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12722 | (compare:CC |
9ebbca7d GK |
12723 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12724 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12725 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12726 | (const_int 0))) |
9ebbca7d | 12727 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12728 | "TARGET_POWER" |
9ebbca7d GK |
12729 | "@ |
12730 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12731 | #" | |
b19003d8 | 12732 | [(set_attr "type" "compare") |
9ebbca7d GK |
12733 | (set_attr "length" "12,16")]) |
12734 | ||
12735 | (define_split | |
12736 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12737 | (compare:CC | |
12738 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12739 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12740 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12741 | (const_int 0))) | |
12742 | (clobber (match_scratch:SI 4 ""))] | |
12743 | "TARGET_POWER && reload_completed" | |
12744 | [(set (match_dup 4) | |
12745 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12746 | (match_dup 3))) |
9ebbca7d GK |
12747 | (set (match_dup 0) |
12748 | (compare:CC (match_dup 4) | |
12749 | (const_int 0)))] | |
12750 | "") | |
1fd4e8c1 RK |
12751 | |
12752 | (define_insn "" | |
097657c3 | 12753 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12754 | (compare:CC |
9ebbca7d GK |
12755 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12756 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12757 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12758 | (const_int 0))) |
097657c3 AM |
12759 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12760 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12761 | "TARGET_POWER" |
9ebbca7d | 12762 | "@ |
097657c3 | 12763 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12764 | #" |
b19003d8 | 12765 | [(set_attr "type" "compare") |
9ebbca7d GK |
12766 | (set_attr "length" "12,16")]) |
12767 | ||
12768 | (define_split | |
097657c3 | 12769 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12770 | (compare:CC |
12771 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12772 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12773 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12774 | (const_int 0))) | |
12775 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12776 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12777 | "TARGET_POWER && reload_completed" |
097657c3 | 12778 | [(set (match_dup 0) |
9ebbca7d | 12779 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12780 | (set (match_dup 4) |
9ebbca7d GK |
12781 | (compare:CC (match_dup 0) |
12782 | (const_int 0)))] | |
12783 | "") | |
1fd4e8c1 RK |
12784 | |
12785 | (define_insn "" | |
cd2b37d9 RK |
12786 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12787 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12788 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12789 | "TARGET_POWER" |
12790 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12791 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12792 | |
1fd4e8c1 | 12793 | (define_insn "" |
cd2b37d9 RK |
12794 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12795 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12796 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12797 | "TARGET_32BIT" |
1fd4e8c1 | 12798 | "@ |
ca7f5001 RK |
12799 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12800 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 12801 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12802 | |
f9562f27 DE |
12803 | (define_insn "" |
12804 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12805 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12806 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
683bdff7 | 12807 | "TARGET_64BIT" |
f9562f27 DE |
12808 | "@ |
12809 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12810 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
12811 | [(set_attr "length" "12")]) | |
12812 | ||
1fd4e8c1 | 12813 | (define_insn "" |
9ebbca7d | 12814 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12815 | (compare:CC |
9ebbca7d GK |
12816 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12817 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12818 | (const_int 0))) |
9ebbca7d | 12819 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12820 | (geu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12821 | "TARGET_32BIT" |
1fd4e8c1 | 12822 | "@ |
ca7f5001 | 12823 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12824 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12825 | # | |
12826 | #" | |
b19003d8 | 12827 | [(set_attr "type" "compare") |
9ebbca7d GK |
12828 | (set_attr "length" "12,12,16,16")]) |
12829 | ||
12830 | (define_split | |
12831 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12832 | (compare:CC | |
12833 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12834 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12835 | (const_int 0))) | |
12836 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12837 | (geu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12838 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12839 | [(set (match_dup 0) |
12840 | (geu:SI (match_dup 1) (match_dup 2))) | |
12841 | (set (match_dup 3) | |
12842 | (compare:CC (match_dup 0) | |
12843 | (const_int 0)))] | |
12844 | "") | |
1fd4e8c1 | 12845 | |
f9562f27 | 12846 | (define_insn "" |
9ebbca7d | 12847 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12848 | (compare:CC |
9ebbca7d GK |
12849 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12850 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12851 | (const_int 0))) |
9ebbca7d | 12852 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12853 | (geu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12854 | "TARGET_64BIT" |
f9562f27 DE |
12855 | "@ |
12856 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12857 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12858 | # | |
12859 | #" | |
f9562f27 | 12860 | [(set_attr "type" "compare") |
9ebbca7d GK |
12861 | (set_attr "length" "12,12,16,16")]) |
12862 | ||
12863 | (define_split | |
12864 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12865 | (compare:CC | |
12866 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12867 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12868 | (const_int 0))) | |
12869 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12870 | (geu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12871 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12872 | [(set (match_dup 0) |
12873 | (geu:DI (match_dup 1) (match_dup 2))) | |
12874 | (set (match_dup 3) | |
12875 | (compare:CC (match_dup 0) | |
12876 | (const_int 0)))] | |
12877 | "") | |
f9562f27 | 12878 | |
1fd4e8c1 | 12879 | (define_insn "" |
80103f96 | 12880 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12881 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12882 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 12883 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12884 | "TARGET_32BIT" |
1fd4e8c1 | 12885 | "@ |
80103f96 FS |
12886 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
12887 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 12888 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12889 | |
12890 | (define_insn "" | |
9ebbca7d | 12891 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12892 | (compare:CC |
9ebbca7d GK |
12893 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12894 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12895 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12896 | (const_int 0))) |
9ebbca7d | 12897 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12898 | "TARGET_32BIT" |
1fd4e8c1 | 12899 | "@ |
ca7f5001 | 12900 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12901 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12902 | # | |
12903 | #" | |
b19003d8 | 12904 | [(set_attr "type" "compare") |
9ebbca7d GK |
12905 | (set_attr "length" "8,8,12,12")]) |
12906 | ||
12907 | (define_split | |
12908 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12909 | (compare:CC | |
12910 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12911 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12912 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12913 | (const_int 0))) | |
12914 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12915 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12916 | [(set (match_dup 4) |
12917 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12918 | (match_dup 3))) | |
12919 | (set (match_dup 0) | |
12920 | (compare:CC (match_dup 4) | |
12921 | (const_int 0)))] | |
12922 | "") | |
1fd4e8c1 RK |
12923 | |
12924 | (define_insn "" | |
097657c3 | 12925 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12926 | (compare:CC |
9ebbca7d GK |
12927 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12928 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12929 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12930 | (const_int 0))) |
097657c3 AM |
12931 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12932 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12933 | "TARGET_32BIT" |
1fd4e8c1 | 12934 | "@ |
097657c3 AM |
12935 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
12936 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12937 | # |
12938 | #" | |
b19003d8 | 12939 | [(set_attr "type" "compare") |
9ebbca7d GK |
12940 | (set_attr "length" "8,8,12,12")]) |
12941 | ||
12942 | (define_split | |
097657c3 | 12943 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12944 | (compare:CC |
12945 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12946 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12947 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12948 | (const_int 0))) | |
12949 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12950 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12951 | "TARGET_32BIT && reload_completed" |
097657c3 | 12952 | [(set (match_dup 0) |
9ebbca7d | 12953 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12954 | (set (match_dup 4) |
9ebbca7d GK |
12955 | (compare:CC (match_dup 0) |
12956 | (const_int 0)))] | |
12957 | "") | |
1fd4e8c1 RK |
12958 | |
12959 | (define_insn "" | |
cd2b37d9 RK |
12960 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12961 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12962 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
683bdff7 | 12963 | "TARGET_32BIT" |
1fd4e8c1 | 12964 | "@ |
ca7f5001 | 12965 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12966 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12967 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12968 | |
12969 | (define_insn "" | |
097657c3 | 12970 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 12971 | (and:SI (neg:SI |
cd2b37d9 | 12972 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12973 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 12974 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12975 | "TARGET_32BIT" |
1fd4e8c1 | 12976 | "@ |
097657c3 AM |
12977 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
12978 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
b19003d8 | 12979 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12980 | |
12981 | (define_insn "" | |
9ebbca7d | 12982 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12983 | (compare:CC |
12984 | (and:SI (neg:SI | |
9ebbca7d GK |
12985 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12986 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12987 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12988 | (const_int 0))) |
9ebbca7d | 12989 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12990 | "TARGET_32BIT" |
1fd4e8c1 | 12991 | "@ |
ca7f5001 | 12992 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12993 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12994 | # | |
12995 | #" | |
b19003d8 | 12996 | [(set_attr "type" "compare") |
9ebbca7d GK |
12997 | (set_attr "length" "12,12,16,16")]) |
12998 | ||
12999 | (define_split | |
13000 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13001 | (compare:CC | |
13002 | (and:SI (neg:SI | |
13003 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13004 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
13005 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13006 | (const_int 0))) | |
13007 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 13008 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 13009 | [(set (match_dup 4) |
097657c3 AM |
13010 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
13011 | (match_dup 3))) | |
9ebbca7d GK |
13012 | (set (match_dup 0) |
13013 | (compare:CC (match_dup 4) | |
13014 | (const_int 0)))] | |
13015 | "") | |
1fd4e8c1 RK |
13016 | |
13017 | (define_insn "" | |
097657c3 | 13018 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
13019 | (compare:CC |
13020 | (and:SI (neg:SI | |
9ebbca7d GK |
13021 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13022 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
13023 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13024 | (const_int 0))) |
097657c3 AM |
13025 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13026 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 13027 | "TARGET_32BIT" |
1fd4e8c1 | 13028 | "@ |
097657c3 AM |
13029 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
13030 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
13031 | # |
13032 | #" | |
b19003d8 | 13033 | [(set_attr "type" "compare") |
9ebbca7d GK |
13034 | (set_attr "length" "12,12,16,16")]) |
13035 | ||
13036 | (define_split | |
097657c3 | 13037 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13038 | (compare:CC |
13039 | (and:SI (neg:SI | |
13040 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13041 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
13042 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13043 | (const_int 0))) | |
13044 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13045 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 13046 | "TARGET_32BIT && reload_completed" |
097657c3 | 13047 | [(set (match_dup 0) |
9ebbca7d | 13048 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 13049 | (set (match_dup 4) |
9ebbca7d GK |
13050 | (compare:CC (match_dup 0) |
13051 | (const_int 0)))] | |
13052 | "") | |
1fd4e8c1 RK |
13053 | |
13054 | (define_insn "" | |
cd2b37d9 RK |
13055 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13056 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13057 | (const_int 0)))] |
683bdff7 | 13058 | "TARGET_32BIT" |
ca7f5001 | 13059 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 13060 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13061 | |
f9562f27 DE |
13062 | (define_insn "" |
13063 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13064 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13065 | (const_int 0)))] | |
683bdff7 | 13066 | "TARGET_64BIT" |
f9562f27 DE |
13067 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" |
13068 | [(set_attr "length" "12")]) | |
13069 | ||
1fd4e8c1 | 13070 | (define_insn "" |
9ebbca7d | 13071 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13072 | (compare:CC |
9ebbca7d | 13073 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
13074 | (const_int 0)) |
13075 | (const_int 0))) | |
9ebbca7d | 13076 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13077 | (gt:SI (match_dup 1) (const_int 0)))] |
683bdff7 | 13078 | "TARGET_32BIT" |
9ebbca7d GK |
13079 | "@ |
13080 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
13081 | #" | |
29ae5b89 | 13082 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13083 | (set_attr "length" "12,16")]) |
13084 | ||
13085 | (define_split | |
13086 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13087 | (compare:CC | |
13088 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13089 | (const_int 0)) | |
13090 | (const_int 0))) | |
13091 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13092 | (gt:SI (match_dup 1) (const_int 0)))] | |
683bdff7 | 13093 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13094 | [(set (match_dup 0) |
13095 | (gt:SI (match_dup 1) (const_int 0))) | |
13096 | (set (match_dup 2) | |
13097 | (compare:CC (match_dup 0) | |
13098 | (const_int 0)))] | |
13099 | "") | |
1fd4e8c1 | 13100 | |
f9562f27 | 13101 | (define_insn "" |
9ebbca7d | 13102 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 13103 | (compare:CC |
9ebbca7d | 13104 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
13105 | (const_int 0)) |
13106 | (const_int 0))) | |
9ebbca7d | 13107 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13108 | (gt:DI (match_dup 1) (const_int 0)))] |
683bdff7 | 13109 | "TARGET_64BIT" |
9ebbca7d GK |
13110 | "@ |
13111 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
13112 | #" | |
f9562f27 | 13113 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13114 | (set_attr "length" "12,16")]) |
13115 | ||
13116 | (define_split | |
13117 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13118 | (compare:CC | |
13119 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13120 | (const_int 0)) | |
13121 | (const_int 0))) | |
13122 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13123 | (gt:DI (match_dup 1) (const_int 0)))] | |
683bdff7 | 13124 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13125 | [(set (match_dup 0) |
13126 | (gt:DI (match_dup 1) (const_int 0))) | |
13127 | (set (match_dup 2) | |
13128 | (compare:CC (match_dup 0) | |
13129 | (const_int 0)))] | |
13130 | "") | |
f9562f27 | 13131 | |
1fd4e8c1 | 13132 | (define_insn "" |
cd2b37d9 RK |
13133 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13134 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13135 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
13136 | "TARGET_POWER" |
13137 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 13138 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13139 | |
13140 | (define_insn "" | |
9ebbca7d | 13141 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13142 | (compare:CC |
9ebbca7d GK |
13143 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13144 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 13145 | (const_int 0))) |
9ebbca7d | 13146 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13147 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 13148 | "TARGET_POWER" |
9ebbca7d GK |
13149 | "@ |
13150 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
13151 | #" | |
29ae5b89 | 13152 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13153 | (set_attr "length" "12,16")]) |
13154 | ||
13155 | (define_split | |
13156 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13157 | (compare:CC | |
13158 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13159 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13160 | (const_int 0))) | |
13161 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13162 | (gt:SI (match_dup 1) (match_dup 2)))] | |
13163 | "TARGET_POWER && reload_completed" | |
13164 | [(set (match_dup 0) | |
13165 | (gt:SI (match_dup 1) (match_dup 2))) | |
13166 | (set (match_dup 3) | |
13167 | (compare:CC (match_dup 0) | |
13168 | (const_int 0)))] | |
13169 | "") | |
1fd4e8c1 RK |
13170 | |
13171 | (define_insn "" | |
80103f96 | 13172 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13173 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13174 | (const_int 0)) |
80103f96 | 13175 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 13176 | "TARGET_32BIT" |
80103f96 | 13177 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
b19003d8 | 13178 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13179 | |
f9562f27 | 13180 | (define_insn "" |
097657c3 | 13181 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
13182 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13183 | (const_int 0)) | |
097657c3 | 13184 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 13185 | "TARGET_64BIT" |
097657c3 | 13186 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
f9562f27 DE |
13187 | [(set_attr "length" "12")]) |
13188 | ||
1fd4e8c1 | 13189 | (define_insn "" |
9ebbca7d | 13190 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13191 | (compare:CC |
9ebbca7d | 13192 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13193 | (const_int 0)) |
9ebbca7d | 13194 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 13195 | (const_int 0))) |
9ebbca7d | 13196 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 13197 | "TARGET_32BIT" |
9ebbca7d GK |
13198 | "@ |
13199 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
13200 | #" | |
b19003d8 | 13201 | [(set_attr "type" "compare") |
9ebbca7d GK |
13202 | (set_attr "length" "12,16")]) |
13203 | ||
13204 | (define_split | |
13205 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13206 | (compare:CC | |
13207 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13208 | (const_int 0)) | |
13209 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
13210 | (const_int 0))) | |
13211 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 13212 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13213 | [(set (match_dup 3) |
13214 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
13215 | (match_dup 2))) | |
13216 | (set (match_dup 0) | |
13217 | (compare:CC (match_dup 3) | |
13218 | (const_int 0)))] | |
13219 | "") | |
1fd4e8c1 | 13220 | |
f9562f27 | 13221 | (define_insn "" |
9ebbca7d | 13222 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 13223 | (compare:CC |
9ebbca7d | 13224 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13225 | (const_int 0)) |
9ebbca7d | 13226 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13227 | (const_int 0))) |
9ebbca7d | 13228 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 13229 | "TARGET_64BIT" |
9ebbca7d GK |
13230 | "@ |
13231 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
13232 | #" | |
f9562f27 | 13233 | [(set_attr "type" "compare") |
9ebbca7d GK |
13234 | (set_attr "length" "12,16")]) |
13235 | ||
13236 | (define_split | |
13237 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13238 | (compare:CC | |
13239 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13240 | (const_int 0)) | |
13241 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13242 | (const_int 0))) | |
13243 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 13244 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13245 | [(set (match_dup 3) |
13246 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 13247 | (match_dup 2))) |
9ebbca7d GK |
13248 | (set (match_dup 0) |
13249 | (compare:CC (match_dup 3) | |
13250 | (const_int 0)))] | |
13251 | "") | |
f9562f27 | 13252 | |
1fd4e8c1 | 13253 | (define_insn "" |
097657c3 | 13254 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
13255 | (compare:CC |
13256 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
13257 | (const_int 0)) | |
13258 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
13259 | (const_int 0))) | |
097657c3 AM |
13260 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13261 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13262 | "TARGET_32BIT" |
9ebbca7d | 13263 | "@ |
097657c3 | 13264 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
13265 | #" |
13266 | [(set_attr "type" "compare") | |
13267 | (set_attr "length" "12,16")]) | |
13268 | ||
13269 | (define_split | |
097657c3 | 13270 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 13271 | (compare:CC |
9ebbca7d | 13272 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 13273 | (const_int 0)) |
9ebbca7d | 13274 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 13275 | (const_int 0))) |
9ebbca7d | 13276 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 13277 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13278 | "TARGET_32BIT && reload_completed" |
097657c3 | 13279 | [(set (match_dup 0) |
9ebbca7d | 13280 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13281 | (set (match_dup 3) |
9ebbca7d GK |
13282 | (compare:CC (match_dup 0) |
13283 | (const_int 0)))] | |
13284 | "") | |
1fd4e8c1 | 13285 | |
f9562f27 | 13286 | (define_insn "" |
097657c3 | 13287 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13288 | (compare:CC |
9ebbca7d | 13289 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13290 | (const_int 0)) |
9ebbca7d | 13291 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13292 | (const_int 0))) |
097657c3 AM |
13293 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
13294 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13295 | "TARGET_64BIT" |
9ebbca7d | 13296 | "@ |
097657c3 | 13297 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 13298 | #" |
f9562f27 | 13299 | [(set_attr "type" "compare") |
9ebbca7d GK |
13300 | (set_attr "length" "12,16")]) |
13301 | ||
13302 | (define_split | |
097657c3 | 13303 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13304 | (compare:CC |
13305 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13306 | (const_int 0)) | |
13307 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13308 | (const_int 0))) | |
13309 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13310 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13311 | "TARGET_64BIT && reload_completed" |
097657c3 | 13312 | [(set (match_dup 0) |
9ebbca7d | 13313 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13314 | (set (match_dup 3) |
9ebbca7d GK |
13315 | (compare:CC (match_dup 0) |
13316 | (const_int 0)))] | |
13317 | "") | |
f9562f27 | 13318 | |
1fd4e8c1 | 13319 | (define_insn "" |
097657c3 | 13320 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13321 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13322 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 13323 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 13324 | "TARGET_POWER" |
097657c3 | 13325 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 13326 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13327 | |
13328 | (define_insn "" | |
9ebbca7d | 13329 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13330 | (compare:CC |
9ebbca7d GK |
13331 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13332 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13333 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13334 | (const_int 0))) |
9ebbca7d | 13335 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13336 | "TARGET_POWER" |
9ebbca7d GK |
13337 | "@ |
13338 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
13339 | #" | |
b19003d8 | 13340 | [(set_attr "type" "compare") |
9ebbca7d GK |
13341 | (set_attr "length" "12,16")]) |
13342 | ||
13343 | (define_split | |
13344 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13345 | (compare:CC | |
13346 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13347 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13348 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13349 | (const_int 0))) | |
13350 | (clobber (match_scratch:SI 4 ""))] | |
13351 | "TARGET_POWER && reload_completed" | |
13352 | [(set (match_dup 4) | |
097657c3 | 13353 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
13354 | (set (match_dup 0) |
13355 | (compare:CC (match_dup 4) | |
13356 | (const_int 0)))] | |
13357 | "") | |
1fd4e8c1 RK |
13358 | |
13359 | (define_insn "" | |
097657c3 | 13360 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13361 | (compare:CC |
9ebbca7d GK |
13362 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13363 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13364 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13365 | (const_int 0))) |
097657c3 AM |
13366 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13367 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 13368 | "TARGET_POWER" |
9ebbca7d | 13369 | "@ |
097657c3 | 13370 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 13371 | #" |
b19003d8 | 13372 | [(set_attr "type" "compare") |
9ebbca7d GK |
13373 | (set_attr "length" "12,16")]) |
13374 | ||
13375 | (define_split | |
097657c3 | 13376 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13377 | (compare:CC |
13378 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13379 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13380 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13381 | (const_int 0))) | |
13382 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13383 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13384 | "TARGET_POWER && reload_completed" |
097657c3 | 13385 | [(set (match_dup 0) |
9ebbca7d | 13386 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13387 | (set (match_dup 4) |
9ebbca7d GK |
13388 | (compare:CC (match_dup 0) |
13389 | (const_int 0)))] | |
13390 | "") | |
1fd4e8c1 RK |
13391 | |
13392 | (define_insn "" | |
cd2b37d9 RK |
13393 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13394 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13395 | (const_int 0))))] |
683bdff7 | 13396 | "TARGET_32BIT" |
ca7f5001 | 13397 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 13398 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13399 | |
f9562f27 DE |
13400 | (define_insn "" |
13401 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13402 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13403 | (const_int 0))))] | |
683bdff7 | 13404 | "TARGET_64BIT" |
8377288b | 13405 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
f9562f27 DE |
13406 | [(set_attr "length" "12")]) |
13407 | ||
1fd4e8c1 | 13408 | (define_insn "" |
cd2b37d9 RK |
13409 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13410 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13411 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
13412 | "TARGET_POWER" |
13413 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 13414 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13415 | |
13416 | (define_insn "" | |
cd2b37d9 RK |
13417 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13418 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13419 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
683bdff7 | 13420 | "TARGET_32BIT" |
ca7f5001 | 13421 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 13422 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13423 | |
f9562f27 DE |
13424 | (define_insn "" |
13425 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13426 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13427 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13428 | "TARGET_64BIT" |
f9562f27 DE |
13429 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" |
13430 | [(set_attr "length" "12")]) | |
13431 | ||
1fd4e8c1 | 13432 | (define_insn "" |
9ebbca7d | 13433 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13434 | (compare:CC |
9ebbca7d GK |
13435 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13436 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13437 | (const_int 0))) |
9ebbca7d | 13438 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13439 | (gtu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13440 | "TARGET_32BIT" |
9ebbca7d GK |
13441 | "@ |
13442 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13443 | #" | |
b19003d8 | 13444 | [(set_attr "type" "compare") |
9ebbca7d GK |
13445 | (set_attr "length" "12,16")]) |
13446 | ||
13447 | (define_split | |
13448 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13449 | (compare:CC | |
13450 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13451 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13452 | (const_int 0))) | |
13453 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13454 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13455 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13456 | [(set (match_dup 0) |
13457 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13458 | (set (match_dup 3) | |
13459 | (compare:CC (match_dup 0) | |
13460 | (const_int 0)))] | |
13461 | "") | |
1fd4e8c1 | 13462 | |
f9562f27 | 13463 | (define_insn "" |
9ebbca7d | 13464 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13465 | (compare:CC |
9ebbca7d GK |
13466 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13467 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13468 | (const_int 0))) |
9ebbca7d | 13469 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13470 | (gtu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13471 | "TARGET_64BIT" |
9ebbca7d GK |
13472 | "@ |
13473 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13474 | #" | |
f9562f27 | 13475 | [(set_attr "type" "compare") |
9ebbca7d GK |
13476 | (set_attr "length" "12,16")]) |
13477 | ||
13478 | (define_split | |
13479 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13480 | (compare:CC | |
13481 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13482 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13483 | (const_int 0))) | |
13484 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13485 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13486 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13487 | [(set (match_dup 0) |
13488 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13489 | (set (match_dup 3) | |
13490 | (compare:CC (match_dup 0) | |
13491 | (const_int 0)))] | |
13492 | "") | |
f9562f27 | 13493 | |
1fd4e8c1 | 13494 | (define_insn "" |
80103f96 | 13495 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
13496 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13497 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
80103f96 | 13498 | (match_operand:SI 3 "reg_or_short_operand" "r,rI")))] |
683bdff7 | 13499 | "TARGET_32BIT" |
00751805 | 13500 | "@ |
80103f96 FS |
13501 | {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3 |
13502 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
19378cf8 | 13503 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 13504 | |
f9562f27 | 13505 | (define_insn "" |
097657c3 | 13506 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
f9562f27 DE |
13507 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13508 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
097657c3 | 13509 | (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] |
683bdff7 | 13510 | "TARGET_64BIT" |
f9562f27 | 13511 | "@ |
097657c3 AM |
13512 | addic %0,%1,%k2\;addze %0,%3 |
13513 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" | |
f9562f27 DE |
13514 | [(set_attr "length" "8,12")]) |
13515 | ||
1fd4e8c1 | 13516 | (define_insn "" |
9ebbca7d | 13517 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13518 | (compare:CC |
9ebbca7d GK |
13519 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13520 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13521 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13522 | (const_int 0))) |
9ebbca7d | 13523 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13524 | "TARGET_32BIT" |
00751805 | 13525 | "@ |
19378cf8 | 13526 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
13527 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
13528 | # | |
13529 | #" | |
b19003d8 | 13530 | [(set_attr "type" "compare") |
9ebbca7d GK |
13531 | (set_attr "length" "8,12,12,16")]) |
13532 | ||
13533 | (define_split | |
13534 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13535 | (compare:CC | |
13536 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13537 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13538 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13539 | (const_int 0))) | |
13540 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 13541 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13542 | [(set (match_dup 4) |
13543 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13544 | (match_dup 3))) |
9ebbca7d GK |
13545 | (set (match_dup 0) |
13546 | (compare:CC (match_dup 4) | |
13547 | (const_int 0)))] | |
13548 | "") | |
1fd4e8c1 | 13549 | |
f9562f27 | 13550 | (define_insn "" |
9ebbca7d | 13551 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13552 | (compare:CC |
9ebbca7d GK |
13553 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13554 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13555 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13556 | (const_int 0))) |
9ebbca7d | 13557 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13558 | "TARGET_64BIT" |
f9562f27 DE |
13559 | "@ |
13560 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
13561 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
13562 | # | |
13563 | #" | |
f9562f27 | 13564 | [(set_attr "type" "compare") |
9ebbca7d GK |
13565 | (set_attr "length" "8,12,12,16")]) |
13566 | ||
13567 | (define_split | |
13568 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13569 | (compare:CC | |
13570 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13571 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13572 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13573 | (const_int 0))) | |
13574 | (clobber (match_scratch:DI 4 ""))] | |
683bdff7 | 13575 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13576 | [(set (match_dup 4) |
13577 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13578 | (match_dup 3))) | |
13579 | (set (match_dup 0) | |
13580 | (compare:CC (match_dup 4) | |
13581 | (const_int 0)))] | |
13582 | "") | |
f9562f27 | 13583 | |
1fd4e8c1 | 13584 | (define_insn "" |
097657c3 | 13585 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13586 | (compare:CC |
9ebbca7d GK |
13587 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13588 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13589 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13590 | (const_int 0))) |
097657c3 AM |
13591 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13592 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13593 | "TARGET_32BIT" |
00751805 | 13594 | "@ |
097657c3 AM |
13595 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
13596 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
13597 | # |
13598 | #" | |
b19003d8 | 13599 | [(set_attr "type" "compare") |
9ebbca7d GK |
13600 | (set_attr "length" "8,12,12,16")]) |
13601 | ||
13602 | (define_split | |
097657c3 | 13603 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13604 | (compare:CC |
13605 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13606 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13607 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13608 | (const_int 0))) | |
13609 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13610 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13611 | "TARGET_32BIT && reload_completed" |
097657c3 | 13612 | [(set (match_dup 0) |
9ebbca7d | 13613 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13614 | (set (match_dup 4) |
9ebbca7d GK |
13615 | (compare:CC (match_dup 0) |
13616 | (const_int 0)))] | |
13617 | "") | |
1fd4e8c1 | 13618 | |
f9562f27 | 13619 | (define_insn "" |
097657c3 | 13620 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13621 | (compare:CC |
9ebbca7d GK |
13622 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13623 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13624 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13625 | (const_int 0))) |
097657c3 AM |
13626 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13627 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13628 | "TARGET_64BIT" |
f9562f27 | 13629 | "@ |
097657c3 AM |
13630 | addic %0,%1,%k2\;addze. %0,%3 |
13631 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 | |
9ebbca7d GK |
13632 | # |
13633 | #" | |
f9562f27 | 13634 | [(set_attr "type" "compare") |
9ebbca7d GK |
13635 | (set_attr "length" "8,12,12,16")]) |
13636 | ||
13637 | (define_split | |
097657c3 | 13638 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13639 | (compare:CC |
13640 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13641 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13642 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13643 | (const_int 0))) | |
13644 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13645 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13646 | "TARGET_64BIT && reload_completed" |
097657c3 | 13647 | [(set (match_dup 0) |
9ebbca7d | 13648 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13649 | (set (match_dup 4) |
9ebbca7d GK |
13650 | (compare:CC (match_dup 0) |
13651 | (const_int 0)))] | |
13652 | "") | |
f9562f27 | 13653 | |
1fd4e8c1 | 13654 | (define_insn "" |
cd2b37d9 RK |
13655 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13656 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13657 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 13658 | "TARGET_32BIT" |
ca7f5001 | 13659 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 13660 | [(set_attr "length" "8")]) |
f9562f27 DE |
13661 | |
13662 | (define_insn "" | |
13663 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13664 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13665 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
683bdff7 | 13666 | "TARGET_64BIT" |
f9562f27 DE |
13667 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" |
13668 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
13669 | \f |
13670 | ;; Define both directions of branch and return. If we need a reload | |
13671 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13672 | ;; register CC value to there. | |
13673 | ||
13674 | (define_insn "" | |
13675 | [(set (pc) | |
13676 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13677 | [(match_operand 2 | |
b54cf83a | 13678 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13679 | (const_int 0)]) |
13680 | (label_ref (match_operand 0 "" "")) | |
13681 | (pc)))] | |
13682 | "" | |
b19003d8 RK |
13683 | "* |
13684 | { | |
12a4e8c5 | 13685 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13686 | }" |
13687 | [(set_attr "type" "branch")]) | |
13688 | ||
1fd4e8c1 RK |
13689 | (define_insn "" |
13690 | [(set (pc) | |
13691 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13692 | [(match_operand 1 | |
b54cf83a | 13693 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13694 | (const_int 0)]) |
13695 | (return) | |
13696 | (pc)))] | |
13697 | "direct_return ()" | |
12a4e8c5 GK |
13698 | "* |
13699 | { | |
13700 | return output_cbranch (operands[0], NULL, 0, insn); | |
13701 | }" | |
b7ff3d82 | 13702 | [(set_attr "type" "branch") |
39a10a29 | 13703 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
13704 | |
13705 | (define_insn "" | |
13706 | [(set (pc) | |
13707 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13708 | [(match_operand 2 | |
b54cf83a | 13709 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13710 | (const_int 0)]) |
13711 | (pc) | |
13712 | (label_ref (match_operand 0 "" ""))))] | |
13713 | "" | |
b19003d8 RK |
13714 | "* |
13715 | { | |
12a4e8c5 | 13716 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13717 | }" |
13718 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13719 | |
13720 | (define_insn "" | |
13721 | [(set (pc) | |
13722 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13723 | [(match_operand 1 | |
b54cf83a | 13724 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13725 | (const_int 0)]) |
13726 | (pc) | |
13727 | (return)))] | |
13728 | "direct_return ()" | |
12a4e8c5 GK |
13729 | "* |
13730 | { | |
13731 | return output_cbranch (operands[0], NULL, 1, insn); | |
13732 | }" | |
b7ff3d82 | 13733 | [(set_attr "type" "branch") |
39a10a29 GK |
13734 | (set_attr "length" "4")]) |
13735 | ||
13736 | ;; Logic on condition register values. | |
13737 | ||
13738 | ; This pattern matches things like | |
13739 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
13740 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
13741 | ; (const_int 1))) | |
13742 | ; which are generated by the branch logic. | |
b54cf83a | 13743 | ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) |
39a10a29 | 13744 | |
423c1189 | 13745 | (define_insn "*cceq_ior_compare" |
b54cf83a | 13746 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13747 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" |
b54cf83a | 13748 | [(match_operator:SI 2 |
39a10a29 GK |
13749 | "branch_positive_comparison_operator" |
13750 | [(match_operand 3 | |
b54cf83a | 13751 | "cc_reg_operand" "y,y") |
39a10a29 | 13752 | (const_int 0)]) |
b54cf83a | 13753 | (match_operator:SI 4 |
39a10a29 GK |
13754 | "branch_positive_comparison_operator" |
13755 | [(match_operand 5 | |
b54cf83a | 13756 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13757 | (const_int 0)])]) |
13758 | (const_int 1)))] | |
24fab1d3 | 13759 | "" |
39a10a29 | 13760 | "cr%q1 %E0,%j2,%j4" |
b54cf83a | 13761 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13762 | |
13763 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
13764 | ; Because ~1 has all but the low bit set. | |
13765 | (define_insn "" | |
b54cf83a | 13766 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13767 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" |
b54cf83a | 13768 | [(not:SI (match_operator:SI 2 |
39a10a29 GK |
13769 | "branch_positive_comparison_operator" |
13770 | [(match_operand 3 | |
b54cf83a | 13771 | "cc_reg_operand" "y,y") |
39a10a29 GK |
13772 | (const_int 0)])) |
13773 | (match_operator:SI 4 | |
13774 | "branch_positive_comparison_operator" | |
13775 | [(match_operand 5 | |
b54cf83a | 13776 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13777 | (const_int 0)])]) |
13778 | (const_int -1)))] | |
13779 | "" | |
13780 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13781 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 | 13782 | |
423c1189 | 13783 | (define_insn "*cceq_rev_compare" |
b54cf83a | 13784 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
6c873122 | 13785 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 13786 | "branch_positive_comparison_operator" |
6c873122 | 13787 | [(match_operand 2 |
b54cf83a | 13788 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13789 | (const_int 0)]) |
13790 | (const_int 0)))] | |
423c1189 | 13791 | "" |
251b3667 | 13792 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
b54cf83a | 13793 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13794 | |
13795 | ;; If we are comparing the result of two comparisons, this can be done | |
13796 | ;; using creqv or crxor. | |
13797 | ||
13798 | (define_insn_and_split "" | |
13799 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13800 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
13801 | [(match_operand 2 "cc_reg_operand" "y") | |
13802 | (const_int 0)]) | |
13803 | (match_operator 3 "branch_comparison_operator" | |
13804 | [(match_operand 4 "cc_reg_operand" "y") | |
13805 | (const_int 0)])))] | |
13806 | "" | |
13807 | "#" | |
13808 | "" | |
13809 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13810 | (match_dup 5)))] | |
13811 | " | |
13812 | { | |
13813 | int positive_1, positive_2; | |
13814 | ||
13815 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
13816 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
13817 | ||
13818 | if (! positive_1) | |
1c563bed | 13819 | operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), |
0f4c242b KH |
13820 | GET_CODE (operands[1])), |
13821 | SImode, | |
13822 | operands[2], const0_rtx); | |
39a10a29 | 13823 | else if (GET_MODE (operands[1]) != SImode) |
0f4c242b KH |
13824 | operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, |
13825 | operands[2], const0_rtx); | |
39a10a29 GK |
13826 | |
13827 | if (! positive_2) | |
1c563bed | 13828 | operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), |
0f4c242b KH |
13829 | GET_CODE (operands[3])), |
13830 | SImode, | |
13831 | operands[4], const0_rtx); | |
39a10a29 | 13832 | else if (GET_MODE (operands[3]) != SImode) |
0f4c242b KH |
13833 | operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
13834 | operands[4], const0_rtx); | |
39a10a29 GK |
13835 | |
13836 | if (positive_1 == positive_2) | |
251b3667 DE |
13837 | { |
13838 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13839 | operands[5] = constm1_rtx; | |
13840 | } | |
13841 | else | |
13842 | { | |
13843 | operands[5] = const1_rtx; | |
13844 | } | |
39a10a29 | 13845 | }") |
1fd4e8c1 RK |
13846 | |
13847 | ;; Unconditional branch and return. | |
13848 | ||
13849 | (define_insn "jump" | |
13850 | [(set (pc) | |
13851 | (label_ref (match_operand 0 "" "")))] | |
13852 | "" | |
b7ff3d82 DE |
13853 | "b %l0" |
13854 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13855 | |
13856 | (define_insn "return" | |
13857 | [(return)] | |
13858 | "direct_return ()" | |
324e52cc TG |
13859 | "{br|blr}" |
13860 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13861 | |
0ad91047 DE |
13862 | (define_expand "indirect_jump" |
13863 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 13864 | "" |
0ad91047 DE |
13865 | " |
13866 | { | |
13867 | if (TARGET_32BIT) | |
13868 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
13869 | else | |
13870 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
13871 | DONE; | |
13872 | }") | |
13873 | ||
13874 | (define_insn "indirect_jumpsi" | |
b92b324d | 13875 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 13876 | "TARGET_32BIT" |
b92b324d DE |
13877 | "@ |
13878 | bctr | |
13879 | {br|blr}" | |
324e52cc | 13880 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13881 | |
0ad91047 | 13882 | (define_insn "indirect_jumpdi" |
b92b324d | 13883 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 13884 | "TARGET_64BIT" |
b92b324d DE |
13885 | "@ |
13886 | bctr | |
13887 | blr" | |
266eb58a DE |
13888 | [(set_attr "type" "jmpreg")]) |
13889 | ||
1fd4e8c1 RK |
13890 | ;; Table jump for switch statements: |
13891 | (define_expand "tablejump" | |
e6ca2c17 DE |
13892 | [(use (match_operand 0 "" "")) |
13893 | (use (label_ref (match_operand 1 "" "")))] | |
13894 | "" | |
13895 | " | |
13896 | { | |
13897 | if (TARGET_32BIT) | |
13898 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13899 | else | |
13900 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13901 | DONE; | |
13902 | }") | |
13903 | ||
13904 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13905 | [(set (match_dup 3) |
13906 | (plus:SI (match_operand:SI 0 "" "") | |
13907 | (match_dup 2))) | |
13908 | (parallel [(set (pc) (match_dup 3)) | |
13909 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13910 | "TARGET_32BIT" |
1fd4e8c1 RK |
13911 | " |
13912 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13913 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13914 | operands[3] = gen_reg_rtx (SImode); |
13915 | }") | |
13916 | ||
e6ca2c17 | 13917 | (define_expand "tablejumpdi" |
6ae08853 | 13918 | [(set (match_dup 4) |
9ebbca7d GK |
13919 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) |
13920 | (set (match_dup 3) | |
13921 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13922 | (match_dup 2))) |
13923 | (parallel [(set (pc) (match_dup 3)) | |
13924 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13925 | "TARGET_64BIT" |
e6ca2c17 | 13926 | " |
9ebbca7d | 13927 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13928 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13929 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13930 | }") |
13931 | ||
1fd4e8c1 RK |
13932 | (define_insn "" |
13933 | [(set (pc) | |
c859cda6 | 13934 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13935 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13936 | "TARGET_32BIT" |
c859cda6 DJ |
13937 | "@ |
13938 | bctr | |
13939 | {br|blr}" | |
a6845123 | 13940 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13941 | |
266eb58a DE |
13942 | (define_insn "" |
13943 | [(set (pc) | |
c859cda6 | 13944 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 13945 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13946 | "TARGET_64BIT" |
c859cda6 DJ |
13947 | "@ |
13948 | bctr | |
13949 | blr" | |
266eb58a DE |
13950 | [(set_attr "type" "jmpreg")]) |
13951 | ||
1fd4e8c1 RK |
13952 | (define_insn "nop" |
13953 | [(const_int 0)] | |
13954 | "" | |
ca7f5001 | 13955 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13956 | \f |
7e69e155 | 13957 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13958 | ;; so loop.c knows what to generate. |
13959 | ||
5527bf14 RH |
13960 | (define_expand "doloop_end" |
13961 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13962 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13963 | (use (match_operand 2 "" "")) ; max iterations | |
13964 | (use (match_operand 3 "" "")) ; loop level | |
13965 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13966 | "" |
13967 | " | |
13968 | { | |
5527bf14 RH |
13969 | /* Only use this on innermost loops. */ |
13970 | if (INTVAL (operands[3]) > 1) | |
13971 | FAIL; | |
683bdff7 | 13972 | if (TARGET_64BIT) |
5527bf14 RH |
13973 | { |
13974 | if (GET_MODE (operands[0]) != DImode) | |
13975 | FAIL; | |
13976 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13977 | } | |
0ad91047 | 13978 | else |
5527bf14 RH |
13979 | { |
13980 | if (GET_MODE (operands[0]) != SImode) | |
13981 | FAIL; | |
13982 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13983 | } | |
0ad91047 DE |
13984 | DONE; |
13985 | }") | |
13986 | ||
13987 | (define_expand "ctrsi" | |
3cb999d8 DE |
13988 | [(parallel [(set (pc) |
13989 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
13990 | (const_int 1)) | |
13991 | (label_ref (match_operand 1 "" "")) | |
13992 | (pc))) | |
b6c9286a MM |
13993 | (set (match_dup 0) |
13994 | (plus:SI (match_dup 0) | |
13995 | (const_int -1))) | |
5f81043f RK |
13996 | (clobber (match_scratch:CC 2 "")) |
13997 | (clobber (match_scratch:SI 3 ""))])] | |
683bdff7 | 13998 | "TARGET_32BIT" |
0ad91047 DE |
13999 | "") |
14000 | ||
14001 | (define_expand "ctrdi" | |
3cb999d8 DE |
14002 | [(parallel [(set (pc) |
14003 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
14004 | (const_int 1)) | |
14005 | (label_ref (match_operand 1 "" "")) | |
14006 | (pc))) | |
0ad91047 DE |
14007 | (set (match_dup 0) |
14008 | (plus:DI (match_dup 0) | |
14009 | (const_int -1))) | |
14010 | (clobber (match_scratch:CC 2 "")) | |
61c07d3c | 14011 | (clobber (match_scratch:DI 3 ""))])] |
683bdff7 | 14012 | "TARGET_64BIT" |
61c07d3c | 14013 | "") |
c225ba7b | 14014 | |
1fd4e8c1 RK |
14015 | ;; We need to be able to do this for any operand, including MEM, or we |
14016 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 14017 | ;; JUMP_INSNs. |
0ad91047 | 14018 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
14019 | ;; label MUST be operand 0. |
14020 | ||
0ad91047 | 14021 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 14022 | [(set (pc) |
43b68ce5 | 14023 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 14024 | (const_int 1)) |
a6845123 | 14025 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14026 | (pc))) |
b150f4f3 | 14027 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14028 | (plus:SI (match_dup 1) |
14029 | (const_int -1))) | |
43b68ce5 DE |
14030 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14031 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14032 | "TARGET_32BIT" |
b19003d8 RK |
14033 | "* |
14034 | { | |
af87a13e | 14035 | if (which_alternative != 0) |
b19003d8 | 14036 | return \"#\"; |
856a6884 | 14037 | else if (get_attr_length (insn) == 4) |
a6845123 | 14038 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 14039 | else |
f607bc57 | 14040 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 14041 | }" |
baf97f86 | 14042 | [(set_attr "type" "branch") |
5a195cb5 | 14043 | (set_attr "length" "*,12,16,16")]) |
7e69e155 | 14044 | |
0ad91047 | 14045 | (define_insn "*ctrsi_internal2" |
5f81043f | 14046 | [(set (pc) |
43b68ce5 | 14047 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
14048 | (const_int 1)) |
14049 | (pc) | |
14050 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14051 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14052 | (plus:SI (match_dup 1) |
14053 | (const_int -1))) | |
43b68ce5 DE |
14054 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14055 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14056 | "TARGET_32BIT" |
0ad91047 DE |
14057 | "* |
14058 | { | |
14059 | if (which_alternative != 0) | |
14060 | return \"#\"; | |
856a6884 | 14061 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14062 | return \"bdz %l0\"; |
14063 | else | |
f607bc57 | 14064 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14065 | }" |
14066 | [(set_attr "type" "branch") | |
5a195cb5 | 14067 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14068 | |
14069 | (define_insn "*ctrdi_internal1" | |
14070 | [(set (pc) | |
43b68ce5 | 14071 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14072 | (const_int 1)) |
14073 | (label_ref (match_operand 0 "" "")) | |
14074 | (pc))) | |
b150f4f3 | 14075 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14076 | (plus:DI (match_dup 1) |
14077 | (const_int -1))) | |
43b68ce5 DE |
14078 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14079 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14080 | "TARGET_64BIT" |
0ad91047 DE |
14081 | "* |
14082 | { | |
14083 | if (which_alternative != 0) | |
14084 | return \"#\"; | |
856a6884 | 14085 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14086 | return \"{bdn|bdnz} %l0\"; |
14087 | else | |
f607bc57 | 14088 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14089 | }" |
14090 | [(set_attr "type" "branch") | |
5a195cb5 | 14091 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14092 | |
14093 | (define_insn "*ctrdi_internal2" | |
14094 | [(set (pc) | |
43b68ce5 | 14095 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14096 | (const_int 1)) |
14097 | (pc) | |
14098 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14099 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14100 | (plus:DI (match_dup 1) |
14101 | (const_int -1))) | |
43b68ce5 DE |
14102 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14103 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14104 | "TARGET_64BIT" |
5f81043f RK |
14105 | "* |
14106 | { | |
14107 | if (which_alternative != 0) | |
14108 | return \"#\"; | |
856a6884 | 14109 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14110 | return \"bdz %l0\"; |
14111 | else | |
f607bc57 | 14112 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
14113 | }" |
14114 | [(set_attr "type" "branch") | |
5a195cb5 | 14115 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14116 | |
0ad91047 DE |
14117 | ;; Similar but use EQ |
14118 | ||
14119 | (define_insn "*ctrsi_internal5" | |
5f81043f | 14120 | [(set (pc) |
43b68ce5 | 14121 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 14122 | (const_int 1)) |
a6845123 | 14123 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14124 | (pc))) |
b150f4f3 | 14125 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14126 | (plus:SI (match_dup 1) |
14127 | (const_int -1))) | |
43b68ce5 DE |
14128 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14129 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14130 | "TARGET_32BIT" |
b19003d8 RK |
14131 | "* |
14132 | { | |
af87a13e | 14133 | if (which_alternative != 0) |
b19003d8 | 14134 | return \"#\"; |
856a6884 | 14135 | else if (get_attr_length (insn) == 4) |
a6845123 | 14136 | return \"bdz %l0\"; |
b19003d8 | 14137 | else |
f607bc57 | 14138 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 14139 | }" |
baf97f86 | 14140 | [(set_attr "type" "branch") |
5a195cb5 | 14141 | (set_attr "length" "*,12,16,16")]) |
1fd4e8c1 | 14142 | |
0ad91047 | 14143 | (define_insn "*ctrsi_internal6" |
5f81043f | 14144 | [(set (pc) |
43b68ce5 | 14145 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
14146 | (const_int 1)) |
14147 | (pc) | |
14148 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14149 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14150 | (plus:SI (match_dup 1) |
14151 | (const_int -1))) | |
43b68ce5 DE |
14152 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14153 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14154 | "TARGET_32BIT" |
0ad91047 DE |
14155 | "* |
14156 | { | |
14157 | if (which_alternative != 0) | |
14158 | return \"#\"; | |
856a6884 | 14159 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14160 | return \"{bdn|bdnz} %l0\"; |
14161 | else | |
f607bc57 | 14162 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14163 | }" |
14164 | [(set_attr "type" "branch") | |
5a195cb5 | 14165 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14166 | |
14167 | (define_insn "*ctrdi_internal5" | |
14168 | [(set (pc) | |
43b68ce5 | 14169 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14170 | (const_int 1)) |
14171 | (label_ref (match_operand 0 "" "")) | |
14172 | (pc))) | |
b150f4f3 | 14173 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14174 | (plus:DI (match_dup 1) |
14175 | (const_int -1))) | |
43b68ce5 DE |
14176 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14177 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14178 | "TARGET_64BIT" |
0ad91047 DE |
14179 | "* |
14180 | { | |
14181 | if (which_alternative != 0) | |
14182 | return \"#\"; | |
856a6884 | 14183 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14184 | return \"bdz %l0\"; |
14185 | else | |
f607bc57 | 14186 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14187 | }" |
14188 | [(set_attr "type" "branch") | |
5a195cb5 | 14189 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14190 | |
14191 | (define_insn "*ctrdi_internal6" | |
14192 | [(set (pc) | |
43b68ce5 | 14193 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14194 | (const_int 1)) |
14195 | (pc) | |
14196 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14197 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14198 | (plus:DI (match_dup 1) |
14199 | (const_int -1))) | |
43b68ce5 DE |
14200 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14201 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14202 | "TARGET_64BIT" |
5f81043f RK |
14203 | "* |
14204 | { | |
14205 | if (which_alternative != 0) | |
14206 | return \"#\"; | |
856a6884 | 14207 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14208 | return \"{bdn|bdnz} %l0\"; |
14209 | else | |
f607bc57 | 14210 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
14211 | }" |
14212 | [(set_attr "type" "branch") | |
5a195cb5 | 14213 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14214 | |
0ad91047 DE |
14215 | ;; Now the splitters if we could not allocate the CTR register |
14216 | ||
1fd4e8c1 RK |
14217 | (define_split |
14218 | [(set (pc) | |
14219 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14220 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14221 | (const_int 1)]) |
14222 | (match_operand 5 "" "") | |
14223 | (match_operand 6 "" ""))) | |
cd2b37d9 | 14224 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
14225 | (plus:SI (match_dup 1) |
14226 | (const_int -1))) | |
1fd4e8c1 RK |
14227 | (clobber (match_scratch:CC 3 "")) |
14228 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14229 | "TARGET_32BIT && reload_completed" |
1fd4e8c1 | 14230 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14231 | (compare:CC (plus:SI (match_dup 1) |
14232 | (const_int -1)) | |
1fd4e8c1 | 14233 | (const_int 0))) |
5f81043f RK |
14234 | (set (match_dup 0) |
14235 | (plus:SI (match_dup 1) | |
14236 | (const_int -1)))]) | |
14237 | (set (pc) (if_then_else (match_dup 7) | |
14238 | (match_dup 5) | |
14239 | (match_dup 6)))] | |
1fd4e8c1 | 14240 | " |
0f4c242b KH |
14241 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14242 | operands[3], const0_rtx); }") | |
1fd4e8c1 RK |
14243 | |
14244 | (define_split | |
14245 | [(set (pc) | |
14246 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14247 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14248 | (const_int 1)]) |
14249 | (match_operand 5 "" "") | |
14250 | (match_operand 6 "" ""))) | |
9ebbca7d | 14251 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
14252 | (plus:SI (match_dup 1) (const_int -1))) |
14253 | (clobber (match_scratch:CC 3 "")) | |
14254 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14255 | "TARGET_32BIT && reload_completed |
0ad91047 | 14256 | && ! gpc_reg_operand (operands[0], SImode)" |
1fd4e8c1 | 14257 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14258 | (compare:CC (plus:SI (match_dup 1) |
14259 | (const_int -1)) | |
1fd4e8c1 | 14260 | (const_int 0))) |
5f81043f RK |
14261 | (set (match_dup 4) |
14262 | (plus:SI (match_dup 1) | |
14263 | (const_int -1)))]) | |
14264 | (set (match_dup 0) | |
14265 | (match_dup 4)) | |
14266 | (set (pc) (if_then_else (match_dup 7) | |
14267 | (match_dup 5) | |
14268 | (match_dup 6)))] | |
1fd4e8c1 | 14269 | " |
0f4c242b KH |
14270 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14271 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14272 | (define_split |
14273 | [(set (pc) | |
14274 | (if_then_else (match_operator 2 "comparison_operator" | |
14275 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14276 | (const_int 1)]) | |
61c07d3c DE |
14277 | (match_operand 5 "" "") |
14278 | (match_operand 6 "" ""))) | |
0ad91047 DE |
14279 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
14280 | (plus:DI (match_dup 1) | |
14281 | (const_int -1))) | |
14282 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14283 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14284 | "TARGET_64BIT && reload_completed" |
0ad91047 DE |
14285 | [(parallel [(set (match_dup 3) |
14286 | (compare:CC (plus:DI (match_dup 1) | |
14287 | (const_int -1)) | |
14288 | (const_int 0))) | |
14289 | (set (match_dup 0) | |
14290 | (plus:DI (match_dup 1) | |
14291 | (const_int -1)))]) | |
61c07d3c DE |
14292 | (set (pc) (if_then_else (match_dup 7) |
14293 | (match_dup 5) | |
14294 | (match_dup 6)))] | |
0ad91047 | 14295 | " |
0f4c242b KH |
14296 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14297 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14298 | |
14299 | (define_split | |
14300 | [(set (pc) | |
14301 | (if_then_else (match_operator 2 "comparison_operator" | |
14302 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14303 | (const_int 1)]) | |
61c07d3c DE |
14304 | (match_operand 5 "" "") |
14305 | (match_operand 6 "" ""))) | |
9ebbca7d | 14306 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
14307 | (plus:DI (match_dup 1) (const_int -1))) |
14308 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14309 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14310 | "TARGET_64BIT && reload_completed |
0ad91047 DE |
14311 | && ! gpc_reg_operand (operands[0], DImode)" |
14312 | [(parallel [(set (match_dup 3) | |
14313 | (compare:CC (plus:DI (match_dup 1) | |
14314 | (const_int -1)) | |
14315 | (const_int 0))) | |
14316 | (set (match_dup 4) | |
14317 | (plus:DI (match_dup 1) | |
14318 | (const_int -1)))]) | |
14319 | (set (match_dup 0) | |
14320 | (match_dup 4)) | |
61c07d3c DE |
14321 | (set (pc) (if_then_else (match_dup 7) |
14322 | (match_dup 5) | |
14323 | (match_dup 6)))] | |
0ad91047 | 14324 | " |
0f4c242b KH |
14325 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14326 | operands[3], const0_rtx); }") | |
e0cd0770 JC |
14327 | \f |
14328 | (define_insn "trap" | |
14329 | [(trap_if (const_int 1) (const_int 0))] | |
14330 | "" | |
14331 | "{t 31,0,0|trap}") | |
14332 | ||
14333 | (define_expand "conditional_trap" | |
14334 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14335 | [(match_dup 2) (match_dup 3)]) | |
14336 | (match_operand 1 "const_int_operand" ""))] | |
14337 | "" | |
14338 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14339 | operands[2] = rs6000_compare_op0; | |
14340 | operands[3] = rs6000_compare_op1;") | |
14341 | ||
14342 | (define_insn "" | |
14343 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14344 | [(match_operand:SI 1 "register_operand" "r") | |
14345 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14346 | (const_int 0))] | |
14347 | "" | |
a157febd GK |
14348 | "{t|tw}%V0%I2 %1,%2") |
14349 | ||
14350 | (define_insn "" | |
14351 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14352 | [(match_operand:DI 1 "register_operand" "r") | |
14353 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14354 | (const_int 0))] | |
14355 | "TARGET_POWERPC64" | |
14356 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14357 | \f |
14358 | ;; Insns related to generating the function prologue and epilogue. | |
14359 | ||
14360 | (define_expand "prologue" | |
14361 | [(use (const_int 0))] | |
14362 | "TARGET_SCHED_PROLOG" | |
14363 | " | |
14364 | { | |
14365 | rs6000_emit_prologue (); | |
14366 | DONE; | |
14367 | }") | |
14368 | ||
2c4a9cff DE |
14369 | (define_insn "*movesi_from_cr_one" |
14370 | [(match_parallel 0 "mfcr_operation" | |
14371 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14372 | (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") | |
14373 | (match_operand 3 "immediate_operand" "n")] | |
14374 | UNSPEC_MOVESI_FROM_CR))])] | |
14375 | "TARGET_MFCRF" | |
14376 | "* | |
14377 | { | |
14378 | int mask = 0; | |
14379 | int i; | |
14380 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14381 | { | |
14382 | mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14383 | operands[4] = GEN_INT (mask); | |
14384 | output_asm_insn (\"mfcr %1,%4\", operands); | |
14385 | } | |
14386 | return \"\"; | |
14387 | }" | |
14388 | [(set_attr "type" "mfcrf")]) | |
14389 | ||
9ebbca7d GK |
14390 | (define_insn "movesi_from_cr" |
14391 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 14392 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) |
615158e2 JJ |
14393 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] |
14394 | UNSPEC_MOVESI_FROM_CR))] | |
9ebbca7d | 14395 | "" |
309323c2 | 14396 | "mfcr %0" |
b54cf83a | 14397 | [(set_attr "type" "mfcr")]) |
9ebbca7d GK |
14398 | |
14399 | (define_insn "*stmw" | |
e033a023 DE |
14400 | [(match_parallel 0 "stmw_operation" |
14401 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14402 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14403 | "TARGET_MULTIPLE" | |
14404 | "{stm|stmw} %2,%1") | |
6ae08853 | 14405 | |
9ebbca7d | 14406 | (define_insn "*save_fpregs_si" |
85d346f1 | 14407 | [(match_parallel 0 "any_parallel_operand" |
e033a023 DE |
14408 | [(clobber (match_operand:SI 1 "register_operand" "=l")) |
14409 | (use (match_operand:SI 2 "call_operand" "s")) | |
14410 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14411 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14412 | "TARGET_32BIT" | |
14413 | "bl %z2" | |
14414 | [(set_attr "type" "branch") | |
14415 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14416 | |
14417 | (define_insn "*save_fpregs_di" | |
85d346f1 | 14418 | [(match_parallel 0 "any_parallel_operand" |
e033a023 DE |
14419 | [(clobber (match_operand:DI 1 "register_operand" "=l")) |
14420 | (use (match_operand:DI 2 "call_operand" "s")) | |
14421 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14422 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14423 | "TARGET_64BIT" | |
14424 | "bl %z2" | |
14425 | [(set_attr "type" "branch") | |
14426 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14427 | |
14428 | ; These are to explain that changes to the stack pointer should | |
14429 | ; not be moved over stores to stack memory. | |
14430 | (define_insn "stack_tie" | |
14431 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
615158e2 | 14432 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] |
9ebbca7d GK |
14433 | "" |
14434 | "" | |
14435 | [(set_attr "length" "0")]) | |
14436 | ||
14437 | ||
14438 | (define_expand "epilogue" | |
14439 | [(use (const_int 0))] | |
14440 | "TARGET_SCHED_PROLOG" | |
14441 | " | |
14442 | { | |
14443 | rs6000_emit_epilogue (FALSE); | |
14444 | DONE; | |
14445 | }") | |
14446 | ||
14447 | ; On some processors, doing the mtcrf one CC register at a time is | |
14448 | ; faster (like on the 604e). On others, doing them all at once is | |
14449 | ; faster; for instance, on the 601 and 750. | |
14450 | ||
14451 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
14452 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14453 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 | 14454 | (match_dup 2)] UNSPEC_MOVESI_TO_CR))] |
35aba846 DE |
14455 | "" |
14456 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
14457 | |
14458 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
14459 | [(match_parallel 0 "mtcrf_operation" |
14460 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
14461 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
14462 | (match_operand 3 "immediate_operand" "n")] | |
615158e2 | 14463 | UNSPEC_MOVESI_TO_CR))])] |
9ebbca7d | 14464 | "" |
e35b9579 GK |
14465 | "* |
14466 | { | |
14467 | int mask = 0; | |
14468 | int i; | |
14469 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14470 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14471 | operands[4] = GEN_INT (mask); | |
14472 | return \"mtcrf %4,%2\"; | |
309323c2 | 14473 | }" |
b54cf83a | 14474 | [(set_attr "type" "mtcr")]) |
9ebbca7d | 14475 | |
b54cf83a | 14476 | (define_insn "*mtcrfsi" |
309323c2 DE |
14477 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14478 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 JJ |
14479 | (match_operand 2 "immediate_operand" "n")] |
14480 | UNSPEC_MOVESI_TO_CR))] | |
6ae08853 | 14481 | "GET_CODE (operands[0]) == REG |
309323c2 DE |
14482 | && CR_REGNO_P (REGNO (operands[0])) |
14483 | && GET_CODE (operands[2]) == CONST_INT | |
14484 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14485 | "mtcrf %R0,%1" | |
b54cf83a | 14486 | [(set_attr "type" "mtcr")]) |
9ebbca7d GK |
14487 | |
14488 | ; The load-multiple instructions have similar properties. | |
14489 | ; Note that "load_multiple" is a name known to the machine-independent | |
14490 | ; code that actually corresponds to the powerpc load-string. | |
14491 | ||
14492 | (define_insn "*lmw" | |
35aba846 DE |
14493 | [(match_parallel 0 "lmw_operation" |
14494 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14495 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14496 | "TARGET_MULTIPLE" | |
14497 | "{lm|lmw} %1,%2") | |
6ae08853 | 14498 | |
9ebbca7d | 14499 | (define_insn "*return_internal_si" |
e35b9579 GK |
14500 | [(return) |
14501 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 14502 | "TARGET_32BIT" |
cccf3bdc | 14503 | "b%T0" |
9ebbca7d GK |
14504 | [(set_attr "type" "jmpreg")]) |
14505 | ||
14506 | (define_insn "*return_internal_di" | |
e35b9579 GK |
14507 | [(return) |
14508 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 14509 | "TARGET_64BIT" |
cccf3bdc | 14510 | "b%T0" |
9ebbca7d GK |
14511 | [(set_attr "type" "jmpreg")]) |
14512 | ||
14513 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
85d346f1 | 14514 | ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible... |
9ebbca7d GK |
14515 | |
14516 | (define_insn "*return_and_restore_fpregs_si" | |
85d346f1 | 14517 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 GK |
14518 | [(return) |
14519 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
14520 | (use (match_operand:SI 2 "call_operand" "s")) |
14521 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14522 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14523 | "TARGET_32BIT" | |
14524 | "b %z2") | |
14525 | ||
14526 | (define_insn "*return_and_restore_fpregs_di" | |
85d346f1 | 14527 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 GK |
14528 | [(return) |
14529 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
14530 | (use (match_operand:DI 2 "call_operand" "s")) |
14531 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14532 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14533 | "TARGET_64BIT" | |
14534 | "b %z2") | |
14535 | ||
83720594 RH |
14536 | ; This is used in compiling the unwind routines. |
14537 | (define_expand "eh_return" | |
34dc173c | 14538 | [(use (match_operand 0 "general_operand" ""))] |
9ebbca7d GK |
14539 | "" |
14540 | " | |
14541 | { | |
83720594 | 14542 | if (TARGET_32BIT) |
34dc173c | 14543 | emit_insn (gen_eh_set_lr_si (operands[0])); |
9ebbca7d | 14544 | else |
34dc173c | 14545 | emit_insn (gen_eh_set_lr_di (operands[0])); |
9ebbca7d GK |
14546 | DONE; |
14547 | }") | |
14548 | ||
83720594 RH |
14549 | ; We can't expand this before we know where the link register is stored. |
14550 | (define_insn "eh_set_lr_si" | |
615158e2 JJ |
14551 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] |
14552 | UNSPECV_EH_RR) | |
466eb3e0 | 14553 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
14554 | "TARGET_32BIT" |
14555 | "#") | |
14556 | ||
14557 | (define_insn "eh_set_lr_di" | |
615158e2 JJ |
14558 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
14559 | UNSPECV_EH_RR) | |
466eb3e0 | 14560 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
14561 | "TARGET_64BIT" |
14562 | "#") | |
9ebbca7d GK |
14563 | |
14564 | (define_split | |
615158e2 | 14565 | [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) |
83720594 RH |
14566 | (clobber (match_scratch 1 ""))] |
14567 | "reload_completed" | |
14568 | [(const_int 0)] | |
9ebbca7d GK |
14569 | " |
14570 | { | |
d1d0c603 | 14571 | rs6000_emit_eh_reg_restore (operands[0], operands[1]); |
83720594 RH |
14572 | DONE; |
14573 | }") | |
0ac081f6 | 14574 | |
01a2ccd0 DE |
14575 | (define_insn "prefetch" |
14576 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
14577 | (match_operand:SI 1 "const_int_operand" "n") |
14578 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 14579 | "TARGET_POWERPC" |
6041bf2f DE |
14580 | "* |
14581 | { | |
01a2ccd0 DE |
14582 | if (GET_CODE (operands[0]) == REG) |
14583 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
14584 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
14585 | }" |
14586 | [(set_attr "type" "load")]) | |
a3170dc6 | 14587 | |
10ed84db | 14588 | (include "altivec.md") |
a3170dc6 | 14589 | (include "spe.md") |