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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
409f61cd | 3 | ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 | 5 | |
5de601cf | 6 | ;; This file is part of GCC. |
1fd4e8c1 | 7 | |
5de601cf NC |
8 | ;; GCC is free software; you can redistribute it and/or modify it |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
1fd4e8c1 | 12 | |
5de601cf NC |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
1fd4e8c1 RK |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
5de601cf NC |
19 | ;; along with GCC; see the file COPYING. If not, write to the |
20 | ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | ;; MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d | 24 | |
615158e2 JJ |
25 | ;; |
26 | ;; UNSPEC usage | |
27 | ;; | |
28 | ||
29 | (define_constants | |
30 | [(UNSPEC_FRSP 0) ; frsp for POWER machines | |
31 | (UNSPEC_TIE 5) ; tie stack contents and stack pointer | |
32 | (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC | |
33 | (UNSPEC_TOC 7) ; address of the TOC (more-or-less) | |
34 | (UNSPEC_MOVSI_GOT 8) | |
35 | (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit | |
36 | (UNSPEC_FCTIWZ 10) | |
37 | (UNSPEC_LD_MPIC 15) ; load_macho_picbase | |
38 | (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic | |
39 | (UNSPEC_TLSGD 17) | |
40 | (UNSPEC_TLSLD 18) | |
41 | (UNSPEC_MOVESI_FROM_CR 19) | |
42 | (UNSPEC_MOVESI_TO_CR 20) | |
43 | (UNSPEC_TLSDTPREL 21) | |
44 | (UNSPEC_TLSDTPRELHA 22) | |
45 | (UNSPEC_TLSDTPRELLO 23) | |
46 | (UNSPEC_TLSGOTDTPREL 24) | |
47 | (UNSPEC_TLSTPREL 25) | |
48 | (UNSPEC_TLSTPRELHA 26) | |
49 | (UNSPEC_TLSTPRELLO 27) | |
50 | (UNSPEC_TLSGOTTPREL 28) | |
51 | (UNSPEC_TLSTLS 29) | |
ecb62ae7 | 52 | (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero |
6b1fedc3 | 53 | (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit |
615158e2 JJ |
54 | ]) |
55 | ||
56 | ;; | |
57 | ;; UNSPEC_VOLATILE usage | |
58 | ;; | |
59 | ||
60 | (define_constants | |
61 | [(UNSPECV_BLOCK 0) | |
62 | (UNSPECV_EH_RR 9) ; eh_reg_restore | |
63 | ]) | |
1fd4e8c1 RK |
64 | \f |
65 | ;; Define an insn type attribute. This is used in function unit delay | |
66 | ;; computations. | |
943c15ed | 67 | (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" |
1fd4e8c1 RK |
68 | (const_string "integer")) |
69 | ||
b19003d8 | 70 | ;; Length (in bytes). |
6ae08853 | 71 | ; '(pc)' in the following doesn't include the instruction itself; it is |
6cbadf36 | 72 | ; calculated as if the instruction had zero size. |
b19003d8 RK |
73 | (define_attr "length" "" |
74 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 75 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 76 | (const_int -32768)) |
6cbadf36 GK |
77 | (lt (minus (match_dup 0) (pc)) |
78 | (const_int 32764))) | |
39a10a29 GK |
79 | (const_int 4) |
80 | (const_int 8)) | |
b19003d8 RK |
81 | (const_int 4))) |
82 | ||
cfb557c4 RK |
83 | ;; Processor type -- this attribute must exactly match the processor_type |
84 | ;; enumeration in rs6000.h. | |
85 | ||
ec507f2d | 86 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" |
cfb557c4 RK |
87 | (const (symbol_ref "rs6000_cpu_attr"))) |
88 | ||
b54cf83a DE |
89 | (automata_option "ndfa") |
90 | ||
91 | (include "rios1.md") | |
92 | (include "rios2.md") | |
93 | (include "rs64.md") | |
94 | (include "mpc.md") | |
95 | (include "40x.md") | |
02ca7595 | 96 | (include "440.md") |
b54cf83a DE |
97 | (include "603.md") |
98 | (include "6xx.md") | |
99 | (include "7xx.md") | |
100 | (include "7450.md") | |
5e8006fa | 101 | (include "8540.md") |
b54cf83a | 102 | (include "power4.md") |
ec507f2d | 103 | (include "power5.md") |
48d72335 DE |
104 | |
105 | (include "predicates.md") | |
106 | ||
ac9e2cff | 107 | (include "darwin.md") |
309323c2 | 108 | |
1fd4e8c1 | 109 | \f |
2e6c9641 FJ |
110 | ;; This mode macro allows :P to be used for patterns that operate on |
111 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
112 | (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) | |
113 | ||
1fd4e8c1 RK |
114 | ;; Start with fixed-point load and store insns. Here we put only the more |
115 | ;; complex forms. Basic data transfer is done later. | |
116 | ||
51b8fc2c RK |
117 | (define_expand "zero_extendqidi2" |
118 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
119 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
120 | "TARGET_POWERPC64" | |
121 | "") | |
122 | ||
123 | (define_insn "" | |
124 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
125 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
126 | "TARGET_POWERPC64" | |
127 | "@ | |
128 | lbz%U1%X1 %0,%1 | |
4371f8af | 129 | rldicl %0,%1,0,56" |
51b8fc2c RK |
130 | [(set_attr "type" "load,*")]) |
131 | ||
132 | (define_insn "" | |
9ebbca7d GK |
133 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
134 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 135 | (const_int 0))) |
9ebbca7d | 136 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 137 | "TARGET_64BIT" |
9ebbca7d GK |
138 | "@ |
139 | rldicl. %2,%1,0,56 | |
140 | #" | |
141 | [(set_attr "type" "compare") | |
142 | (set_attr "length" "4,8")]) | |
143 | ||
144 | (define_split | |
145 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
146 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
147 | (const_int 0))) | |
148 | (clobber (match_scratch:DI 2 ""))] | |
149 | "TARGET_POWERPC64 && reload_completed" | |
150 | [(set (match_dup 2) | |
151 | (zero_extend:DI (match_dup 1))) | |
152 | (set (match_dup 0) | |
153 | (compare:CC (match_dup 2) | |
154 | (const_int 0)))] | |
155 | "") | |
51b8fc2c RK |
156 | |
157 | (define_insn "" | |
9ebbca7d GK |
158 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
159 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 160 | (const_int 0))) |
9ebbca7d | 161 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 162 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 163 | "TARGET_64BIT" |
9ebbca7d GK |
164 | "@ |
165 | rldicl. %0,%1,0,56 | |
166 | #" | |
167 | [(set_attr "type" "compare") | |
168 | (set_attr "length" "4,8")]) | |
169 | ||
170 | (define_split | |
171 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
172 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
173 | (const_int 0))) | |
174 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
175 | (zero_extend:DI (match_dup 1)))] | |
176 | "TARGET_POWERPC64 && reload_completed" | |
177 | [(set (match_dup 0) | |
178 | (zero_extend:DI (match_dup 1))) | |
179 | (set (match_dup 2) | |
180 | (compare:CC (match_dup 0) | |
181 | (const_int 0)))] | |
182 | "") | |
51b8fc2c | 183 | |
2bee0449 RK |
184 | (define_insn "extendqidi2" |
185 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
186 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 187 | "TARGET_POWERPC64" |
2bee0449 | 188 | "extsb %0,%1") |
51b8fc2c RK |
189 | |
190 | (define_insn "" | |
9ebbca7d GK |
191 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
192 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 193 | (const_int 0))) |
9ebbca7d | 194 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 195 | "TARGET_64BIT" |
9ebbca7d GK |
196 | "@ |
197 | extsb. %2,%1 | |
198 | #" | |
199 | [(set_attr "type" "compare") | |
200 | (set_attr "length" "4,8")]) | |
201 | ||
202 | (define_split | |
203 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
204 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
205 | (const_int 0))) | |
206 | (clobber (match_scratch:DI 2 ""))] | |
207 | "TARGET_POWERPC64 && reload_completed" | |
208 | [(set (match_dup 2) | |
209 | (sign_extend:DI (match_dup 1))) | |
210 | (set (match_dup 0) | |
211 | (compare:CC (match_dup 2) | |
212 | (const_int 0)))] | |
213 | "") | |
51b8fc2c RK |
214 | |
215 | (define_insn "" | |
9ebbca7d GK |
216 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
217 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 218 | (const_int 0))) |
9ebbca7d | 219 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 220 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 221 | "TARGET_64BIT" |
9ebbca7d GK |
222 | "@ |
223 | extsb. %0,%1 | |
224 | #" | |
225 | [(set_attr "type" "compare") | |
226 | (set_attr "length" "4,8")]) | |
227 | ||
228 | (define_split | |
229 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
230 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
231 | (const_int 0))) | |
232 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
233 | (sign_extend:DI (match_dup 1)))] | |
234 | "TARGET_POWERPC64 && reload_completed" | |
235 | [(set (match_dup 0) | |
236 | (sign_extend:DI (match_dup 1))) | |
237 | (set (match_dup 2) | |
238 | (compare:CC (match_dup 0) | |
239 | (const_int 0)))] | |
240 | "") | |
51b8fc2c RK |
241 | |
242 | (define_expand "zero_extendhidi2" | |
243 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
244 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
245 | "TARGET_POWERPC64" | |
246 | "") | |
247 | ||
248 | (define_insn "" | |
249 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
250 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
251 | "TARGET_POWERPC64" | |
252 | "@ | |
253 | lhz%U1%X1 %0,%1 | |
4371f8af | 254 | rldicl %0,%1,0,48" |
51b8fc2c RK |
255 | [(set_attr "type" "load,*")]) |
256 | ||
257 | (define_insn "" | |
9ebbca7d GK |
258 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
259 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 260 | (const_int 0))) |
9ebbca7d | 261 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 262 | "TARGET_64BIT" |
9ebbca7d GK |
263 | "@ |
264 | rldicl. %2,%1,0,48 | |
265 | #" | |
266 | [(set_attr "type" "compare") | |
267 | (set_attr "length" "4,8")]) | |
268 | ||
269 | (define_split | |
270 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
271 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
272 | (const_int 0))) | |
273 | (clobber (match_scratch:DI 2 ""))] | |
274 | "TARGET_POWERPC64 && reload_completed" | |
275 | [(set (match_dup 2) | |
276 | (zero_extend:DI (match_dup 1))) | |
277 | (set (match_dup 0) | |
278 | (compare:CC (match_dup 2) | |
279 | (const_int 0)))] | |
280 | "") | |
51b8fc2c RK |
281 | |
282 | (define_insn "" | |
9ebbca7d GK |
283 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
284 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 285 | (const_int 0))) |
9ebbca7d | 286 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 287 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 288 | "TARGET_64BIT" |
9ebbca7d GK |
289 | "@ |
290 | rldicl. %0,%1,0,48 | |
291 | #" | |
292 | [(set_attr "type" "compare") | |
293 | (set_attr "length" "4,8")]) | |
294 | ||
295 | (define_split | |
296 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
297 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
298 | (const_int 0))) | |
299 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
300 | (zero_extend:DI (match_dup 1)))] | |
301 | "TARGET_POWERPC64 && reload_completed" | |
302 | [(set (match_dup 0) | |
303 | (zero_extend:DI (match_dup 1))) | |
304 | (set (match_dup 2) | |
305 | (compare:CC (match_dup 0) | |
306 | (const_int 0)))] | |
307 | "") | |
51b8fc2c RK |
308 | |
309 | (define_expand "extendhidi2" | |
310 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
311 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
312 | "TARGET_POWERPC64" | |
313 | "") | |
314 | ||
315 | (define_insn "" | |
316 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
317 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
318 | "TARGET_POWERPC64" | |
319 | "@ | |
320 | lha%U1%X1 %0,%1 | |
321 | extsh %0,%1" | |
b54cf83a | 322 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
323 | |
324 | (define_insn "" | |
9ebbca7d GK |
325 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
326 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 327 | (const_int 0))) |
9ebbca7d | 328 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 329 | "TARGET_64BIT" |
9ebbca7d GK |
330 | "@ |
331 | extsh. %2,%1 | |
332 | #" | |
333 | [(set_attr "type" "compare") | |
334 | (set_attr "length" "4,8")]) | |
335 | ||
336 | (define_split | |
337 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
338 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
339 | (const_int 0))) | |
340 | (clobber (match_scratch:DI 2 ""))] | |
341 | "TARGET_POWERPC64 && reload_completed" | |
342 | [(set (match_dup 2) | |
343 | (sign_extend:DI (match_dup 1))) | |
344 | (set (match_dup 0) | |
345 | (compare:CC (match_dup 2) | |
346 | (const_int 0)))] | |
347 | "") | |
51b8fc2c RK |
348 | |
349 | (define_insn "" | |
9ebbca7d GK |
350 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
351 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 352 | (const_int 0))) |
9ebbca7d | 353 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 354 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 355 | "TARGET_64BIT" |
9ebbca7d GK |
356 | "@ |
357 | extsh. %0,%1 | |
358 | #" | |
359 | [(set_attr "type" "compare") | |
360 | (set_attr "length" "4,8")]) | |
361 | ||
362 | (define_split | |
363 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
364 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
365 | (const_int 0))) | |
366 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
367 | (sign_extend:DI (match_dup 1)))] | |
368 | "TARGET_POWERPC64 && reload_completed" | |
369 | [(set (match_dup 0) | |
370 | (sign_extend:DI (match_dup 1))) | |
371 | (set (match_dup 2) | |
372 | (compare:CC (match_dup 0) | |
373 | (const_int 0)))] | |
374 | "") | |
51b8fc2c RK |
375 | |
376 | (define_expand "zero_extendsidi2" | |
377 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
378 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
379 | "TARGET_POWERPC64" | |
380 | "") | |
381 | ||
382 | (define_insn "" | |
383 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
384 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
385 | "TARGET_POWERPC64" | |
386 | "@ | |
387 | lwz%U1%X1 %0,%1 | |
388 | rldicl %0,%1,0,32" | |
389 | [(set_attr "type" "load,*")]) | |
390 | ||
391 | (define_insn "" | |
9ebbca7d GK |
392 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
393 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 394 | (const_int 0))) |
9ebbca7d | 395 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 396 | "TARGET_64BIT" |
9ebbca7d GK |
397 | "@ |
398 | rldicl. %2,%1,0,32 | |
399 | #" | |
400 | [(set_attr "type" "compare") | |
401 | (set_attr "length" "4,8")]) | |
402 | ||
403 | (define_split | |
404 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
405 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
406 | (const_int 0))) | |
407 | (clobber (match_scratch:DI 2 ""))] | |
408 | "TARGET_POWERPC64 && reload_completed" | |
409 | [(set (match_dup 2) | |
410 | (zero_extend:DI (match_dup 1))) | |
411 | (set (match_dup 0) | |
412 | (compare:CC (match_dup 2) | |
413 | (const_int 0)))] | |
414 | "") | |
51b8fc2c RK |
415 | |
416 | (define_insn "" | |
9ebbca7d GK |
417 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
418 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 419 | (const_int 0))) |
9ebbca7d | 420 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 421 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 422 | "TARGET_64BIT" |
9ebbca7d GK |
423 | "@ |
424 | rldicl. %0,%1,0,32 | |
425 | #" | |
426 | [(set_attr "type" "compare") | |
427 | (set_attr "length" "4,8")]) | |
428 | ||
429 | (define_split | |
430 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
431 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
432 | (const_int 0))) | |
433 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
434 | (zero_extend:DI (match_dup 1)))] | |
435 | "TARGET_POWERPC64 && reload_completed" | |
436 | [(set (match_dup 0) | |
437 | (zero_extend:DI (match_dup 1))) | |
438 | (set (match_dup 2) | |
439 | (compare:CC (match_dup 0) | |
440 | (const_int 0)))] | |
441 | "") | |
51b8fc2c RK |
442 | |
443 | (define_expand "extendsidi2" | |
444 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
445 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
446 | "TARGET_POWERPC64" | |
447 | "") | |
448 | ||
449 | (define_insn "" | |
450 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 451 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
452 | "TARGET_POWERPC64" |
453 | "@ | |
454 | lwa%U1%X1 %0,%1 | |
455 | extsw %0,%1" | |
b54cf83a | 456 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
457 | |
458 | (define_insn "" | |
9ebbca7d GK |
459 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
460 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 461 | (const_int 0))) |
9ebbca7d | 462 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 463 | "TARGET_64BIT" |
9ebbca7d GK |
464 | "@ |
465 | extsw. %2,%1 | |
466 | #" | |
467 | [(set_attr "type" "compare") | |
468 | (set_attr "length" "4,8")]) | |
469 | ||
470 | (define_split | |
471 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
472 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
473 | (const_int 0))) | |
474 | (clobber (match_scratch:DI 2 ""))] | |
475 | "TARGET_POWERPC64 && reload_completed" | |
476 | [(set (match_dup 2) | |
477 | (sign_extend:DI (match_dup 1))) | |
478 | (set (match_dup 0) | |
479 | (compare:CC (match_dup 2) | |
480 | (const_int 0)))] | |
481 | "") | |
51b8fc2c RK |
482 | |
483 | (define_insn "" | |
9ebbca7d GK |
484 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
485 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 486 | (const_int 0))) |
9ebbca7d | 487 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 488 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 489 | "TARGET_64BIT" |
9ebbca7d GK |
490 | "@ |
491 | extsw. %0,%1 | |
492 | #" | |
493 | [(set_attr "type" "compare") | |
494 | (set_attr "length" "4,8")]) | |
495 | ||
496 | (define_split | |
497 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
498 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
499 | (const_int 0))) | |
500 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
501 | (sign_extend:DI (match_dup 1)))] | |
502 | "TARGET_POWERPC64 && reload_completed" | |
503 | [(set (match_dup 0) | |
504 | (sign_extend:DI (match_dup 1))) | |
505 | (set (match_dup 2) | |
506 | (compare:CC (match_dup 0) | |
507 | (const_int 0)))] | |
508 | "") | |
51b8fc2c | 509 | |
1fd4e8c1 | 510 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
511 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
512 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
513 | "" |
514 | "") | |
515 | ||
516 | (define_insn "" | |
cd2b37d9 | 517 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
518 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
519 | "" | |
520 | "@ | |
521 | lbz%U1%X1 %0,%1 | |
005a35b9 | 522 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
523 | [(set_attr "type" "load,*")]) |
524 | ||
525 | (define_insn "" | |
9ebbca7d GK |
526 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
527 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 528 | (const_int 0))) |
9ebbca7d | 529 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 530 | "" |
9ebbca7d GK |
531 | "@ |
532 | {andil.|andi.} %2,%1,0xff | |
533 | #" | |
534 | [(set_attr "type" "compare") | |
535 | (set_attr "length" "4,8")]) | |
536 | ||
537 | (define_split | |
538 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
539 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
540 | (const_int 0))) | |
541 | (clobber (match_scratch:SI 2 ""))] | |
542 | "reload_completed" | |
543 | [(set (match_dup 2) | |
544 | (zero_extend:SI (match_dup 1))) | |
545 | (set (match_dup 0) | |
546 | (compare:CC (match_dup 2) | |
547 | (const_int 0)))] | |
548 | "") | |
1fd4e8c1 RK |
549 | |
550 | (define_insn "" | |
9ebbca7d GK |
551 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
552 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 553 | (const_int 0))) |
9ebbca7d | 554 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
555 | (zero_extend:SI (match_dup 1)))] |
556 | "" | |
9ebbca7d GK |
557 | "@ |
558 | {andil.|andi.} %0,%1,0xff | |
559 | #" | |
560 | [(set_attr "type" "compare") | |
561 | (set_attr "length" "4,8")]) | |
562 | ||
563 | (define_split | |
564 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
565 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
566 | (const_int 0))) | |
567 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
568 | (zero_extend:SI (match_dup 1)))] | |
569 | "reload_completed" | |
570 | [(set (match_dup 0) | |
571 | (zero_extend:SI (match_dup 1))) | |
572 | (set (match_dup 2) | |
573 | (compare:CC (match_dup 0) | |
574 | (const_int 0)))] | |
575 | "") | |
1fd4e8c1 | 576 | |
51b8fc2c RK |
577 | (define_expand "extendqisi2" |
578 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
579 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
580 | "" | |
581 | " | |
582 | { | |
583 | if (TARGET_POWERPC) | |
584 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
585 | else if (TARGET_POWER) | |
586 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
587 | else | |
588 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
589 | DONE; | |
590 | }") | |
591 | ||
592 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
593 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
594 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 595 | "TARGET_POWERPC" |
2bee0449 | 596 | "extsb %0,%1") |
51b8fc2c RK |
597 | |
598 | (define_insn "" | |
9ebbca7d GK |
599 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
600 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 601 | (const_int 0))) |
9ebbca7d | 602 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 603 | "TARGET_POWERPC" |
9ebbca7d GK |
604 | "@ |
605 | extsb. %2,%1 | |
606 | #" | |
607 | [(set_attr "type" "compare") | |
608 | (set_attr "length" "4,8")]) | |
609 | ||
610 | (define_split | |
611 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
612 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
613 | (const_int 0))) | |
614 | (clobber (match_scratch:SI 2 ""))] | |
615 | "TARGET_POWERPC && reload_completed" | |
616 | [(set (match_dup 2) | |
617 | (sign_extend:SI (match_dup 1))) | |
618 | (set (match_dup 0) | |
619 | (compare:CC (match_dup 2) | |
620 | (const_int 0)))] | |
621 | "") | |
51b8fc2c RK |
622 | |
623 | (define_insn "" | |
9ebbca7d GK |
624 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
625 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 626 | (const_int 0))) |
9ebbca7d | 627 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
628 | (sign_extend:SI (match_dup 1)))] |
629 | "TARGET_POWERPC" | |
9ebbca7d GK |
630 | "@ |
631 | extsb. %0,%1 | |
632 | #" | |
633 | [(set_attr "type" "compare") | |
634 | (set_attr "length" "4,8")]) | |
635 | ||
636 | (define_split | |
637 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
638 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
639 | (const_int 0))) | |
640 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
641 | (sign_extend:SI (match_dup 1)))] | |
642 | "TARGET_POWERPC && reload_completed" | |
643 | [(set (match_dup 0) | |
644 | (sign_extend:SI (match_dup 1))) | |
645 | (set (match_dup 2) | |
646 | (compare:CC (match_dup 0) | |
647 | (const_int 0)))] | |
648 | "") | |
51b8fc2c RK |
649 | |
650 | (define_expand "extendqisi2_power" | |
651 | [(parallel [(set (match_dup 2) | |
652 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
653 | (const_int 24))) | |
654 | (clobber (scratch:SI))]) | |
655 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
656 | (ashiftrt:SI (match_dup 2) | |
657 | (const_int 24))) | |
658 | (clobber (scratch:SI))])] | |
659 | "TARGET_POWER" | |
660 | " | |
661 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
662 | operands[2] = gen_reg_rtx (SImode); }") | |
663 | ||
664 | (define_expand "extendqisi2_no_power" | |
665 | [(set (match_dup 2) | |
666 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
667 | (const_int 24))) | |
668 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
669 | (ashiftrt:SI (match_dup 2) | |
670 | (const_int 24)))] | |
671 | "! TARGET_POWER && ! TARGET_POWERPC" | |
672 | " | |
673 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
674 | operands[2] = gen_reg_rtx (SImode); }") | |
675 | ||
1fd4e8c1 | 676 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
677 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
678 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
679 | "" |
680 | "") | |
681 | ||
682 | (define_insn "" | |
cd2b37d9 | 683 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
684 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
685 | "" | |
686 | "@ | |
687 | lbz%U1%X1 %0,%1 | |
005a35b9 | 688 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
689 | [(set_attr "type" "load,*")]) |
690 | ||
691 | (define_insn "" | |
9ebbca7d GK |
692 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
693 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 694 | (const_int 0))) |
9ebbca7d | 695 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 696 | "" |
9ebbca7d GK |
697 | "@ |
698 | {andil.|andi.} %2,%1,0xff | |
699 | #" | |
700 | [(set_attr "type" "compare") | |
701 | (set_attr "length" "4,8")]) | |
702 | ||
703 | (define_split | |
704 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
705 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
706 | (const_int 0))) | |
707 | (clobber (match_scratch:HI 2 ""))] | |
708 | "reload_completed" | |
709 | [(set (match_dup 2) | |
710 | (zero_extend:HI (match_dup 1))) | |
711 | (set (match_dup 0) | |
712 | (compare:CC (match_dup 2) | |
713 | (const_int 0)))] | |
714 | "") | |
1fd4e8c1 | 715 | |
51b8fc2c | 716 | (define_insn "" |
9ebbca7d GK |
717 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
718 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 719 | (const_int 0))) |
9ebbca7d | 720 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
721 | (zero_extend:HI (match_dup 1)))] |
722 | "" | |
9ebbca7d GK |
723 | "@ |
724 | {andil.|andi.} %0,%1,0xff | |
725 | #" | |
726 | [(set_attr "type" "compare") | |
727 | (set_attr "length" "4,8")]) | |
728 | ||
729 | (define_split | |
730 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
731 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
732 | (const_int 0))) | |
733 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
734 | (zero_extend:HI (match_dup 1)))] | |
735 | "reload_completed" | |
736 | [(set (match_dup 0) | |
737 | (zero_extend:HI (match_dup 1))) | |
738 | (set (match_dup 2) | |
739 | (compare:CC (match_dup 0) | |
740 | (const_int 0)))] | |
741 | "") | |
815cdc52 MM |
742 | |
743 | (define_expand "extendqihi2" | |
744 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
745 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
746 | "" | |
747 | " | |
748 | { | |
749 | if (TARGET_POWERPC) | |
750 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
751 | else if (TARGET_POWER) | |
752 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
753 | else | |
754 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
755 | DONE; | |
756 | }") | |
757 | ||
758 | (define_insn "extendqihi2_ppc" | |
759 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
760 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
761 | "TARGET_POWERPC" | |
762 | "extsb %0,%1") | |
763 | ||
764 | (define_insn "" | |
9ebbca7d GK |
765 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
766 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 767 | (const_int 0))) |
9ebbca7d | 768 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 769 | "TARGET_POWERPC" |
9ebbca7d GK |
770 | "@ |
771 | extsb. %2,%1 | |
772 | #" | |
773 | [(set_attr "type" "compare") | |
774 | (set_attr "length" "4,8")]) | |
775 | ||
776 | (define_split | |
777 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
778 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
779 | (const_int 0))) | |
780 | (clobber (match_scratch:HI 2 ""))] | |
781 | "TARGET_POWERPC && reload_completed" | |
782 | [(set (match_dup 2) | |
783 | (sign_extend:HI (match_dup 1))) | |
784 | (set (match_dup 0) | |
785 | (compare:CC (match_dup 2) | |
786 | (const_int 0)))] | |
787 | "") | |
815cdc52 MM |
788 | |
789 | (define_insn "" | |
9ebbca7d GK |
790 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
791 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 792 | (const_int 0))) |
9ebbca7d | 793 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
794 | (sign_extend:HI (match_dup 1)))] |
795 | "TARGET_POWERPC" | |
9ebbca7d GK |
796 | "@ |
797 | extsb. %0,%1 | |
798 | #" | |
799 | [(set_attr "type" "compare") | |
800 | (set_attr "length" "4,8")]) | |
801 | ||
802 | (define_split | |
803 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
804 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
805 | (const_int 0))) | |
806 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
807 | (sign_extend:HI (match_dup 1)))] | |
808 | "TARGET_POWERPC && reload_completed" | |
809 | [(set (match_dup 0) | |
810 | (sign_extend:HI (match_dup 1))) | |
811 | (set (match_dup 2) | |
812 | (compare:CC (match_dup 0) | |
813 | (const_int 0)))] | |
814 | "") | |
51b8fc2c RK |
815 | |
816 | (define_expand "extendqihi2_power" | |
817 | [(parallel [(set (match_dup 2) | |
818 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
819 | (const_int 24))) | |
820 | (clobber (scratch:SI))]) | |
821 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
822 | (ashiftrt:SI (match_dup 2) | |
823 | (const_int 24))) | |
824 | (clobber (scratch:SI))])] | |
825 | "TARGET_POWER" | |
826 | " | |
827 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
828 | operands[1] = gen_lowpart (SImode, operands[1]); | |
829 | operands[2] = gen_reg_rtx (SImode); }") | |
830 | ||
831 | (define_expand "extendqihi2_no_power" | |
832 | [(set (match_dup 2) | |
833 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
834 | (const_int 24))) | |
835 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
836 | (ashiftrt:SI (match_dup 2) | |
837 | (const_int 24)))] | |
838 | "! TARGET_POWER && ! TARGET_POWERPC" | |
839 | " | |
840 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
841 | operands[1] = gen_lowpart (SImode, operands[1]); | |
842 | operands[2] = gen_reg_rtx (SImode); }") | |
843 | ||
1fd4e8c1 | 844 | (define_expand "zero_extendhisi2" |
5f243543 | 845 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 846 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
847 | "" |
848 | "") | |
849 | ||
850 | (define_insn "" | |
cd2b37d9 | 851 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
852 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
853 | "" | |
854 | "@ | |
855 | lhz%U1%X1 %0,%1 | |
005a35b9 | 856 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
857 | [(set_attr "type" "load,*")]) |
858 | ||
859 | (define_insn "" | |
9ebbca7d GK |
860 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
861 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 862 | (const_int 0))) |
9ebbca7d | 863 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 864 | "" |
9ebbca7d GK |
865 | "@ |
866 | {andil.|andi.} %2,%1,0xffff | |
867 | #" | |
868 | [(set_attr "type" "compare") | |
869 | (set_attr "length" "4,8")]) | |
870 | ||
871 | (define_split | |
872 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
873 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
874 | (const_int 0))) | |
875 | (clobber (match_scratch:SI 2 ""))] | |
876 | "reload_completed" | |
877 | [(set (match_dup 2) | |
878 | (zero_extend:SI (match_dup 1))) | |
879 | (set (match_dup 0) | |
880 | (compare:CC (match_dup 2) | |
881 | (const_int 0)))] | |
882 | "") | |
1fd4e8c1 RK |
883 | |
884 | (define_insn "" | |
9ebbca7d GK |
885 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
886 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 887 | (const_int 0))) |
9ebbca7d | 888 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
889 | (zero_extend:SI (match_dup 1)))] |
890 | "" | |
9ebbca7d GK |
891 | "@ |
892 | {andil.|andi.} %0,%1,0xffff | |
893 | #" | |
894 | [(set_attr "type" "compare") | |
895 | (set_attr "length" "4,8")]) | |
896 | ||
897 | (define_split | |
898 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
899 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
900 | (const_int 0))) | |
901 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
902 | (zero_extend:SI (match_dup 1)))] | |
903 | "reload_completed" | |
904 | [(set (match_dup 0) | |
905 | (zero_extend:SI (match_dup 1))) | |
906 | (set (match_dup 2) | |
907 | (compare:CC (match_dup 0) | |
908 | (const_int 0)))] | |
909 | "") | |
1fd4e8c1 RK |
910 | |
911 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
912 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
913 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
914 | "" |
915 | "") | |
916 | ||
917 | (define_insn "" | |
cd2b37d9 | 918 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
919 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
920 | "" | |
921 | "@ | |
922 | lha%U1%X1 %0,%1 | |
ca7f5001 | 923 | {exts|extsh} %0,%1" |
b54cf83a | 924 | [(set_attr "type" "load_ext,*")]) |
1fd4e8c1 RK |
925 | |
926 | (define_insn "" | |
9ebbca7d GK |
927 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
928 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 929 | (const_int 0))) |
9ebbca7d | 930 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 931 | "" |
9ebbca7d GK |
932 | "@ |
933 | {exts.|extsh.} %2,%1 | |
934 | #" | |
935 | [(set_attr "type" "compare") | |
936 | (set_attr "length" "4,8")]) | |
937 | ||
938 | (define_split | |
939 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
940 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
941 | (const_int 0))) | |
942 | (clobber (match_scratch:SI 2 ""))] | |
943 | "reload_completed" | |
944 | [(set (match_dup 2) | |
945 | (sign_extend:SI (match_dup 1))) | |
946 | (set (match_dup 0) | |
947 | (compare:CC (match_dup 2) | |
948 | (const_int 0)))] | |
949 | "") | |
1fd4e8c1 RK |
950 | |
951 | (define_insn "" | |
9ebbca7d GK |
952 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
953 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 954 | (const_int 0))) |
9ebbca7d | 955 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
956 | (sign_extend:SI (match_dup 1)))] |
957 | "" | |
9ebbca7d GK |
958 | "@ |
959 | {exts.|extsh.} %0,%1 | |
960 | #" | |
961 | [(set_attr "type" "compare") | |
962 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 963 | \f |
9ebbca7d GK |
964 | (define_split |
965 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
966 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
967 | (const_int 0))) | |
968 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
969 | (sign_extend:SI (match_dup 1)))] | |
970 | "reload_completed" | |
971 | [(set (match_dup 0) | |
972 | (sign_extend:SI (match_dup 1))) | |
973 | (set (match_dup 2) | |
974 | (compare:CC (match_dup 0) | |
975 | (const_int 0)))] | |
976 | "") | |
977 | ||
1fd4e8c1 | 978 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
979 | |
980 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
981 | ;; allowing register zero as source. | |
7cd5235b MM |
982 | (define_expand "addsi3" |
983 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
984 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 985 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
986 | "" |
987 | " | |
988 | { | |
677a9668 DE |
989 | if (GET_CODE (operands[2]) == CONST_INT |
990 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 991 | { |
677a9668 | 992 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
993 | ? operands[0] : gen_reg_rtx (SImode)); |
994 | ||
2bfcf297 | 995 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 996 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 997 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
7cd5235b | 998 | |
9ebbca7d GK |
999 | /* The ordering here is important for the prolog expander. |
1000 | When space is allocated from the stack, adding 'low' first may | |
1001 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 1002 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
1003 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
1004 | DONE; | |
1005 | } | |
1006 | }") | |
1007 | ||
1008 | (define_insn "*addsi3_internal1" | |
1009 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1010 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1011 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1012 | "" |
1013 | "@ | |
deb9225a RK |
1014 | {cax|add} %0,%1,%2 |
1015 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1016 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1017 | {cau|addis} %0,%1,%v2" |
1018 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1019 | |
ee890fe2 SS |
1020 | (define_insn "addsi3_high" |
1021 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1022 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1023 | (high:SI (match_operand 2 "" ""))))] | |
1024 | "TARGET_MACHO && !TARGET_64BIT" | |
1025 | "{cau|addis} %0,%1,ha16(%2)" | |
1026 | [(set_attr "length" "4")]) | |
1027 | ||
7cd5235b | 1028 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1029 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1030 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1031 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1032 | (const_int 0))) |
cb8cc086 | 1033 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
4b8a63d6 | 1034 | "TARGET_32BIT" |
deb9225a RK |
1035 | "@ |
1036 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1037 | {ai.|addic.} %3,%1,%2 |
1038 | # | |
1039 | #" | |
a62bfff2 | 1040 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1041 | (set_attr "length" "4,4,8,8")]) |
1042 | ||
1043 | (define_split | |
1044 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1045 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1046 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1047 | (const_int 0))) | |
1048 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 1049 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1050 | [(set (match_dup 3) |
1051 | (plus:SI (match_dup 1) | |
1052 | (match_dup 2))) | |
1053 | (set (match_dup 0) | |
1054 | (compare:CC (match_dup 3) | |
1055 | (const_int 0)))] | |
1056 | "") | |
7e69e155 | 1057 | |
7cd5235b | 1058 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1059 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1060 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1061 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1062 | (const_int 0))) |
cb8cc086 MM |
1063 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1064 | (plus:SI (match_dup 1) | |
1065 | (match_dup 2)))] | |
4b8a63d6 | 1066 | "TARGET_32BIT" |
deb9225a RK |
1067 | "@ |
1068 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1069 | {ai.|addic.} %0,%1,%2 |
1070 | # | |
1071 | #" | |
a62bfff2 | 1072 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1073 | (set_attr "length" "4,4,8,8")]) |
1074 | ||
1075 | (define_split | |
1076 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1077 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1078 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1079 | (const_int 0))) | |
1080 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1081 | (plus:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 1082 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1083 | [(set (match_dup 0) |
1084 | (plus:SI (match_dup 1) | |
1085 | (match_dup 2))) | |
1086 | (set (match_dup 3) | |
1087 | (compare:CC (match_dup 0) | |
1088 | (const_int 0)))] | |
1089 | "") | |
7e69e155 | 1090 | |
f357808b RK |
1091 | ;; Split an add that we can't do in one insn into two insns, each of which |
1092 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1093 | ;; add should be last in case the result gets used in an address. | |
1094 | ||
1095 | (define_split | |
cd2b37d9 RK |
1096 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1097 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1098 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1099 | "" |
f357808b RK |
1100 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1101 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1102 | " | |
1fd4e8c1 | 1103 | { |
2bfcf297 | 1104 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1105 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1106 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
1fd4e8c1 | 1107 | |
2bfcf297 | 1108 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1109 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1110 | }") |
1111 | ||
8de2a197 | 1112 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1113 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1114 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1115 | "" |
ca7f5001 RK |
1116 | "nor %0,%1,%1") |
1117 | ||
1118 | (define_insn "" | |
52d3af72 DE |
1119 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1120 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1121 | (const_int 0))) |
52d3af72 | 1122 | (clobber (match_scratch:SI 2 "=r,r"))] |
4b8a63d6 | 1123 | "TARGET_32BIT" |
52d3af72 DE |
1124 | "@ |
1125 | nor. %2,%1,%1 | |
1126 | #" | |
1127 | [(set_attr "type" "compare") | |
1128 | (set_attr "length" "4,8")]) | |
1129 | ||
1130 | (define_split | |
1131 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1132 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1133 | (const_int 0))) | |
1134 | (clobber (match_scratch:SI 2 ""))] | |
4b8a63d6 | 1135 | "TARGET_32BIT && reload_completed" |
52d3af72 DE |
1136 | [(set (match_dup 2) |
1137 | (not:SI (match_dup 1))) | |
1138 | (set (match_dup 0) | |
1139 | (compare:CC (match_dup 2) | |
1140 | (const_int 0)))] | |
1141 | "") | |
ca7f5001 RK |
1142 | |
1143 | (define_insn "" | |
52d3af72 DE |
1144 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1145 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1146 | (const_int 0))) |
52d3af72 | 1147 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1148 | (not:SI (match_dup 1)))] |
4b8a63d6 | 1149 | "TARGET_32BIT" |
52d3af72 DE |
1150 | "@ |
1151 | nor. %0,%1,%1 | |
1152 | #" | |
1153 | [(set_attr "type" "compare") | |
1154 | (set_attr "length" "4,8")]) | |
1155 | ||
1156 | (define_split | |
1157 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1158 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1159 | (const_int 0))) | |
1cb18e3c | 1160 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1161 | (not:SI (match_dup 1)))] |
4b8a63d6 | 1162 | "TARGET_32BIT && reload_completed" |
52d3af72 DE |
1163 | [(set (match_dup 0) |
1164 | (not:SI (match_dup 1))) | |
1165 | (set (match_dup 2) | |
1166 | (compare:CC (match_dup 0) | |
1167 | (const_int 0)))] | |
1168 | "") | |
1fd4e8c1 RK |
1169 | |
1170 | (define_insn "" | |
3d91674b RK |
1171 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1172 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1173 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1174 | "! TARGET_POWERPC" |
ca7f5001 | 1175 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1176 | |
deb9225a RK |
1177 | (define_insn "" |
1178 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1179 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1180 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1181 | "TARGET_POWERPC" | |
1182 | "@ | |
1183 | subf %0,%2,%1 | |
1184 | subfic %0,%2,%1") | |
1185 | ||
1fd4e8c1 | 1186 | (define_insn "" |
cb8cc086 MM |
1187 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1188 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1189 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1190 | (const_int 0))) |
cb8cc086 | 1191 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1192 | "! TARGET_POWERPC" |
cb8cc086 MM |
1193 | "@ |
1194 | {sf.|subfc.} %3,%2,%1 | |
1195 | #" | |
1196 | [(set_attr "type" "compare") | |
1197 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1198 | |
deb9225a | 1199 | (define_insn "" |
cb8cc086 MM |
1200 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1201 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1202 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1203 | (const_int 0))) |
cb8cc086 | 1204 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 1205 | "TARGET_POWERPC && TARGET_32BIT" |
cb8cc086 MM |
1206 | "@ |
1207 | subf. %3,%2,%1 | |
1208 | #" | |
a62bfff2 | 1209 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1210 | (set_attr "length" "4,8")]) |
1211 | ||
1212 | (define_split | |
1213 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1214 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1215 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1216 | (const_int 0))) | |
1217 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 1218 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1219 | [(set (match_dup 3) |
1220 | (minus:SI (match_dup 1) | |
1221 | (match_dup 2))) | |
1222 | (set (match_dup 0) | |
1223 | (compare:CC (match_dup 3) | |
1224 | (const_int 0)))] | |
1225 | "") | |
deb9225a | 1226 | |
1fd4e8c1 | 1227 | (define_insn "" |
cb8cc086 MM |
1228 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1229 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1230 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1231 | (const_int 0))) |
cb8cc086 | 1232 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1233 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1234 | "! TARGET_POWERPC" |
cb8cc086 MM |
1235 | "@ |
1236 | {sf.|subfc.} %0,%2,%1 | |
1237 | #" | |
1238 | [(set_attr "type" "compare") | |
1239 | (set_attr "length" "4,8")]) | |
815cdc52 | 1240 | |
29ae5b89 | 1241 | (define_insn "" |
cb8cc086 MM |
1242 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1243 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1244 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1245 | (const_int 0))) |
cb8cc086 MM |
1246 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1247 | (minus:SI (match_dup 1) | |
1248 | (match_dup 2)))] | |
4b8a63d6 | 1249 | "TARGET_POWERPC && TARGET_32BIT" |
90612787 DE |
1250 | "@ |
1251 | subf. %0,%2,%1 | |
1252 | #" | |
a62bfff2 | 1253 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1254 | (set_attr "length" "4,8")]) |
1255 | ||
1256 | (define_split | |
1257 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1258 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1259 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1260 | (const_int 0))) | |
1261 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1262 | (minus:SI (match_dup 1) | |
1263 | (match_dup 2)))] | |
4b8a63d6 | 1264 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1265 | [(set (match_dup 0) |
1266 | (minus:SI (match_dup 1) | |
1267 | (match_dup 2))) | |
1268 | (set (match_dup 3) | |
1269 | (compare:CC (match_dup 0) | |
1270 | (const_int 0)))] | |
1271 | "") | |
deb9225a | 1272 | |
1fd4e8c1 | 1273 | (define_expand "subsi3" |
cd2b37d9 | 1274 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1275 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1276 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1277 | "" |
a0044fb1 RK |
1278 | " |
1279 | { | |
1280 | if (GET_CODE (operands[2]) == CONST_INT) | |
1281 | { | |
1282 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1283 | negate_rtx (SImode, operands[2]))); | |
1284 | DONE; | |
1285 | } | |
1286 | }") | |
1fd4e8c1 RK |
1287 | |
1288 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1289 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1290 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1291 | ;; combine. | |
1fd4e8c1 RK |
1292 | |
1293 | (define_expand "sminsi3" | |
1294 | [(set (match_dup 3) | |
cd2b37d9 | 1295 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1296 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1297 | (const_int 0) | |
1298 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1299 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1300 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1301 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1302 | " |
a3170dc6 AH |
1303 | { |
1304 | if (TARGET_ISEL) | |
1305 | { | |
1306 | operands[2] = force_reg (SImode, operands[2]); | |
1307 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
1308 | DONE; | |
1309 | } | |
1310 | ||
1311 | operands[3] = gen_reg_rtx (SImode); | |
1312 | }") | |
1fd4e8c1 | 1313 | |
95ac8e67 RK |
1314 | (define_split |
1315 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1316 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1317 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1318 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1319 | "TARGET_POWER" |
95ac8e67 RK |
1320 | [(set (match_dup 3) |
1321 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1322 | (const_int 0) | |
1323 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1324 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1325 | "") | |
1326 | ||
1fd4e8c1 RK |
1327 | (define_expand "smaxsi3" |
1328 | [(set (match_dup 3) | |
cd2b37d9 | 1329 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1330 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1331 | (const_int 0) | |
1332 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1333 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1334 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1335 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1336 | " |
a3170dc6 AH |
1337 | { |
1338 | if (TARGET_ISEL) | |
1339 | { | |
1340 | operands[2] = force_reg (SImode, operands[2]); | |
1341 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
1342 | DONE; | |
1343 | } | |
1344 | operands[3] = gen_reg_rtx (SImode); | |
1345 | }") | |
1fd4e8c1 | 1346 | |
95ac8e67 RK |
1347 | (define_split |
1348 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1349 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1350 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1351 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1352 | "TARGET_POWER" |
95ac8e67 RK |
1353 | [(set (match_dup 3) |
1354 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1355 | (const_int 0) | |
1356 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1357 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1358 | "") | |
1359 | ||
1fd4e8c1 | 1360 | (define_expand "uminsi3" |
cd2b37d9 | 1361 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1362 | (match_dup 5))) |
cd2b37d9 | 1363 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1364 | (match_dup 5))) |
1fd4e8c1 RK |
1365 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1366 | (const_int 0) | |
1367 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1368 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1369 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1370 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1371 | " |
bb68ff55 | 1372 | { |
a3170dc6 AH |
1373 | if (TARGET_ISEL) |
1374 | { | |
1375 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
1376 | DONE; | |
1377 | } | |
bb68ff55 MM |
1378 | operands[3] = gen_reg_rtx (SImode); |
1379 | operands[4] = gen_reg_rtx (SImode); | |
1380 | operands[5] = GEN_INT (-2147483647 - 1); | |
1381 | }") | |
1fd4e8c1 RK |
1382 | |
1383 | (define_expand "umaxsi3" | |
cd2b37d9 | 1384 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1385 | (match_dup 5))) |
cd2b37d9 | 1386 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1387 | (match_dup 5))) |
1fd4e8c1 RK |
1388 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1389 | (const_int 0) | |
1390 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1391 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1392 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1393 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1394 | " |
bb68ff55 | 1395 | { |
a3170dc6 AH |
1396 | if (TARGET_ISEL) |
1397 | { | |
1398 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
1399 | DONE; | |
1400 | } | |
bb68ff55 MM |
1401 | operands[3] = gen_reg_rtx (SImode); |
1402 | operands[4] = gen_reg_rtx (SImode); | |
1403 | operands[5] = GEN_INT (-2147483647 - 1); | |
1404 | }") | |
1fd4e8c1 RK |
1405 | |
1406 | (define_insn "" | |
cd2b37d9 RK |
1407 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1408 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1409 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1410 | (const_int 0) |
1411 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1412 | "TARGET_POWER" |
1fd4e8c1 RK |
1413 | "doz%I2 %0,%1,%2") |
1414 | ||
1415 | (define_insn "" | |
9ebbca7d | 1416 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1417 | (compare:CC |
9ebbca7d GK |
1418 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1419 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1420 | (const_int 0) |
1421 | (minus:SI (match_dup 2) (match_dup 1))) | |
1422 | (const_int 0))) | |
9ebbca7d | 1423 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1424 | "TARGET_POWER" |
9ebbca7d GK |
1425 | "@ |
1426 | doz%I2. %3,%1,%2 | |
1427 | #" | |
1428 | [(set_attr "type" "delayed_compare") | |
1429 | (set_attr "length" "4,8")]) | |
1430 | ||
1431 | (define_split | |
1432 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1433 | (compare:CC | |
1434 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1435 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1436 | (const_int 0) | |
1437 | (minus:SI (match_dup 2) (match_dup 1))) | |
1438 | (const_int 0))) | |
1439 | (clobber (match_scratch:SI 3 ""))] | |
1440 | "TARGET_POWER && reload_completed" | |
1441 | [(set (match_dup 3) | |
1442 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1443 | (const_int 0) | |
1444 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1445 | (set (match_dup 0) | |
1446 | (compare:CC (match_dup 3) | |
1447 | (const_int 0)))] | |
1448 | "") | |
1fd4e8c1 RK |
1449 | |
1450 | (define_insn "" | |
9ebbca7d | 1451 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1452 | (compare:CC |
9ebbca7d GK |
1453 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1454 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1455 | (const_int 0) |
1456 | (minus:SI (match_dup 2) (match_dup 1))) | |
1457 | (const_int 0))) | |
9ebbca7d | 1458 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1459 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1460 | (const_int 0) | |
1461 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1462 | "TARGET_POWER" |
9ebbca7d GK |
1463 | "@ |
1464 | doz%I2. %0,%1,%2 | |
1465 | #" | |
1466 | [(set_attr "type" "delayed_compare") | |
1467 | (set_attr "length" "4,8")]) | |
1468 | ||
1469 | (define_split | |
1470 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1471 | (compare:CC | |
1472 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1473 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1474 | (const_int 0) | |
1475 | (minus:SI (match_dup 2) (match_dup 1))) | |
1476 | (const_int 0))) | |
1477 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1478 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1479 | (const_int 0) | |
1480 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1481 | "TARGET_POWER && reload_completed" | |
1482 | [(set (match_dup 0) | |
1483 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1484 | (const_int 0) | |
1485 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1486 | (set (match_dup 3) | |
1487 | (compare:CC (match_dup 0) | |
1488 | (const_int 0)))] | |
1489 | "") | |
1fd4e8c1 RK |
1490 | |
1491 | ;; We don't need abs with condition code because such comparisons should | |
1492 | ;; never be done. | |
ea9be077 MM |
1493 | (define_expand "abssi2" |
1494 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1495 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1496 | "" | |
1497 | " | |
1498 | { | |
a3170dc6 AH |
1499 | if (TARGET_ISEL) |
1500 | { | |
1501 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
1502 | DONE; | |
1503 | } | |
1504 | else if (! TARGET_POWER) | |
ea9be077 MM |
1505 | { |
1506 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1507 | DONE; | |
1508 | } | |
1509 | }") | |
1510 | ||
ea112fc4 | 1511 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
1512 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1513 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1514 | "TARGET_POWER" |
1fd4e8c1 RK |
1515 | "abs %0,%1") |
1516 | ||
a3170dc6 AH |
1517 | (define_insn_and_split "abssi2_isel" |
1518 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1519 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8c48b6f5 | 1520 | (clobber (match_scratch:SI 2 "=&b")) |
a3170dc6 AH |
1521 | (clobber (match_scratch:CC 3 "=y"))] |
1522 | "TARGET_ISEL" | |
1523 | "#" | |
1524 | "&& reload_completed" | |
1525 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
1526 | (set (match_dup 3) | |
1527 | (compare:CC (match_dup 1) | |
1528 | (const_int 0))) | |
1529 | (set (match_dup 0) | |
1530 | (if_then_else:SI (ge (match_dup 3) | |
1531 | (const_int 0)) | |
1532 | (match_dup 1) | |
1533 | (match_dup 2)))] | |
1534 | "") | |
1535 | ||
ea112fc4 | 1536 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 1537 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1538 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 1539 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 1540 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
1541 | "#" |
1542 | "&& reload_completed" | |
ea9be077 MM |
1543 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1544 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1545 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1546 | "") |
1547 | ||
463b558b | 1548 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1549 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1550 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1551 | "TARGET_POWER" |
1fd4e8c1 RK |
1552 | "nabs %0,%1") |
1553 | ||
ea112fc4 | 1554 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 1555 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1556 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 1557 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 1558 | "! TARGET_POWER" |
ea112fc4 DE |
1559 | "#" |
1560 | "&& reload_completed" | |
ea9be077 MM |
1561 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1562 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1563 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1564 | "") |
1565 | ||
1fd4e8c1 | 1566 | (define_insn "negsi2" |
cd2b37d9 RK |
1567 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1568 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1569 | "" |
1570 | "neg %0,%1") | |
1571 | ||
1572 | (define_insn "" | |
9ebbca7d GK |
1573 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1574 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1575 | (const_int 0))) |
9ebbca7d | 1576 | (clobber (match_scratch:SI 2 "=r,r"))] |
4b8a63d6 | 1577 | "TARGET_32BIT" |
9ebbca7d GK |
1578 | "@ |
1579 | neg. %2,%1 | |
1580 | #" | |
a62bfff2 | 1581 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1582 | (set_attr "length" "4,8")]) |
1583 | ||
1584 | (define_split | |
1585 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1586 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1587 | (const_int 0))) | |
1588 | (clobber (match_scratch:SI 2 ""))] | |
4b8a63d6 | 1589 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
1590 | [(set (match_dup 2) |
1591 | (neg:SI (match_dup 1))) | |
1592 | (set (match_dup 0) | |
1593 | (compare:CC (match_dup 2) | |
1594 | (const_int 0)))] | |
1595 | "") | |
1fd4e8c1 RK |
1596 | |
1597 | (define_insn "" | |
9ebbca7d GK |
1598 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1599 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1600 | (const_int 0))) |
9ebbca7d | 1601 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1602 | (neg:SI (match_dup 1)))] |
4b8a63d6 | 1603 | "TARGET_32BIT" |
9ebbca7d GK |
1604 | "@ |
1605 | neg. %0,%1 | |
1606 | #" | |
a62bfff2 | 1607 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1608 | (set_attr "length" "4,8")]) |
1609 | ||
1610 | (define_split | |
1611 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1612 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1613 | (const_int 0))) | |
1614 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1615 | (neg:SI (match_dup 1)))] | |
4b8a63d6 | 1616 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
1617 | [(set (match_dup 0) |
1618 | (neg:SI (match_dup 1))) | |
1619 | (set (match_dup 2) | |
1620 | (compare:CC (match_dup 0) | |
1621 | (const_int 0)))] | |
1622 | "") | |
1fd4e8c1 | 1623 | |
1b1edcfa DE |
1624 | (define_insn "clzsi2" |
1625 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1626 | (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1627 | "" | |
1628 | "{cntlz|cntlzw} %0,%1") | |
1629 | ||
1630 | (define_expand "ctzsi2" | |
4977bab6 | 1631 | [(set (match_dup 2) |
1b1edcfa | 1632 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 1633 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) |
1b1edcfa DE |
1634 | (match_dup 2))) |
1635 | (clobber (scratch:CC))]) | |
d865b122 | 1636 | (set (match_dup 4) (clz:SI (match_dup 3))) |
4977bab6 | 1637 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 1638 | (minus:SI (const_int 31) (match_dup 4)))] |
1fd4e8c1 | 1639 | "" |
4977bab6 ZW |
1640 | { |
1641 | operands[2] = gen_reg_rtx (SImode); | |
1642 | operands[3] = gen_reg_rtx (SImode); | |
1643 | operands[4] = gen_reg_rtx (SImode); | |
1644 | }) | |
6ae08853 | 1645 | |
1b1edcfa DE |
1646 | (define_expand "ffssi2" |
1647 | [(set (match_dup 2) | |
1648 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
1649 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) | |
1650 | (match_dup 2))) | |
1651 | (clobber (scratch:CC))]) | |
1652 | (set (match_dup 4) (clz:SI (match_dup 3))) | |
1653 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1654 | (minus:SI (const_int 32) (match_dup 4)))] | |
4977bab6 | 1655 | "" |
1b1edcfa DE |
1656 | { |
1657 | operands[2] = gen_reg_rtx (SImode); | |
1658 | operands[3] = gen_reg_rtx (SImode); | |
1659 | operands[4] = gen_reg_rtx (SImode); | |
1660 | }) | |
6ae08853 | 1661 | |
ca7f5001 RK |
1662 | (define_expand "mulsi3" |
1663 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1664 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1665 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1666 | "" | |
1667 | " | |
1668 | { | |
1669 | if (TARGET_POWER) | |
68b40e7e | 1670 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1671 | else |
68b40e7e | 1672 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1673 | DONE; |
1674 | }") | |
1675 | ||
68b40e7e | 1676 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1677 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1678 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1679 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1680 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1681 | "TARGET_POWER" |
1682 | "@ | |
1683 | {muls|mullw} %0,%1,%2 | |
1684 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1685 | [(set (attr "type") |
c859cda6 DJ |
1686 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1687 | (const_string "imul3") | |
6ae08853 | 1688 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1689 | (const_string "imul2")] |
1690 | (const_string "imul")))]) | |
ca7f5001 | 1691 | |
68b40e7e | 1692 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1693 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1694 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1695 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1696 | "! TARGET_POWER" |
1fd4e8c1 | 1697 | "@ |
d904e9ed RK |
1698 | {muls|mullw} %0,%1,%2 |
1699 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1700 | [(set (attr "type") |
c859cda6 DJ |
1701 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1702 | (const_string "imul3") | |
6ae08853 | 1703 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1704 | (const_string "imul2")] |
1705 | (const_string "imul")))]) | |
1fd4e8c1 | 1706 | |
9259f3b0 | 1707 | (define_insn "*mulsi3_mq_internal1" |
9ebbca7d GK |
1708 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1709 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1710 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1711 | (const_int 0))) |
9ebbca7d GK |
1712 | (clobber (match_scratch:SI 3 "=r,r")) |
1713 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 1714 | "TARGET_POWER" |
9ebbca7d GK |
1715 | "@ |
1716 | {muls.|mullw.} %3,%1,%2 | |
1717 | #" | |
9259f3b0 | 1718 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1719 | (set_attr "length" "4,8")]) |
1720 | ||
1721 | (define_split | |
1722 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1723 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1724 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1725 | (const_int 0))) | |
1726 | (clobber (match_scratch:SI 3 "")) | |
1727 | (clobber (match_scratch:SI 4 ""))] | |
1728 | "TARGET_POWER && reload_completed" | |
1729 | [(parallel [(set (match_dup 3) | |
1730 | (mult:SI (match_dup 1) (match_dup 2))) | |
1731 | (clobber (match_dup 4))]) | |
1732 | (set (match_dup 0) | |
1733 | (compare:CC (match_dup 3) | |
1734 | (const_int 0)))] | |
1735 | "") | |
ca7f5001 | 1736 | |
9259f3b0 | 1737 | (define_insn "*mulsi3_no_mq_internal1" |
9ebbca7d GK |
1738 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1739 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1740 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1741 | (const_int 0))) |
9ebbca7d | 1742 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 1743 | "! TARGET_POWER" |
9ebbca7d GK |
1744 | "@ |
1745 | {muls.|mullw.} %3,%1,%2 | |
1746 | #" | |
9259f3b0 | 1747 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1748 | (set_attr "length" "4,8")]) |
1749 | ||
1750 | (define_split | |
1751 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1752 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1753 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1754 | (const_int 0))) | |
1755 | (clobber (match_scratch:SI 3 ""))] | |
1756 | "! TARGET_POWER && reload_completed" | |
1757 | [(set (match_dup 3) | |
1758 | (mult:SI (match_dup 1) (match_dup 2))) | |
1759 | (set (match_dup 0) | |
1760 | (compare:CC (match_dup 3) | |
1761 | (const_int 0)))] | |
1762 | "") | |
1fd4e8c1 | 1763 | |
9259f3b0 | 1764 | (define_insn "*mulsi3_mq_internal2" |
9ebbca7d GK |
1765 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1766 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1767 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1768 | (const_int 0))) |
9ebbca7d | 1769 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 1770 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 1771 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 1772 | "TARGET_POWER" |
9ebbca7d GK |
1773 | "@ |
1774 | {muls.|mullw.} %0,%1,%2 | |
1775 | #" | |
9259f3b0 | 1776 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1777 | (set_attr "length" "4,8")]) |
1778 | ||
1779 | (define_split | |
1780 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1781 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1782 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1783 | (const_int 0))) | |
1784 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1785 | (mult:SI (match_dup 1) (match_dup 2))) | |
1786 | (clobber (match_scratch:SI 4 ""))] | |
1787 | "TARGET_POWER && reload_completed" | |
1788 | [(parallel [(set (match_dup 0) | |
1789 | (mult:SI (match_dup 1) (match_dup 2))) | |
1790 | (clobber (match_dup 4))]) | |
1791 | (set (match_dup 3) | |
1792 | (compare:CC (match_dup 0) | |
1793 | (const_int 0)))] | |
1794 | "") | |
ca7f5001 | 1795 | |
9259f3b0 | 1796 | (define_insn "*mulsi3_no_mq_internal2" |
9ebbca7d GK |
1797 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1798 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1799 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1800 | (const_int 0))) |
9ebbca7d | 1801 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 1802 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1803 | "! TARGET_POWER" |
9ebbca7d GK |
1804 | "@ |
1805 | {muls.|mullw.} %0,%1,%2 | |
1806 | #" | |
9259f3b0 | 1807 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1808 | (set_attr "length" "4,8")]) |
1809 | ||
1810 | (define_split | |
1811 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1812 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1813 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1814 | (const_int 0))) | |
1815 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1816 | (mult:SI (match_dup 1) (match_dup 2)))] | |
1817 | "! TARGET_POWER && reload_completed" | |
1818 | [(set (match_dup 0) | |
1819 | (mult:SI (match_dup 1) (match_dup 2))) | |
1820 | (set (match_dup 3) | |
1821 | (compare:CC (match_dup 0) | |
1822 | (const_int 0)))] | |
1823 | "") | |
1fd4e8c1 RK |
1824 | |
1825 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1826 | ;; 0 and remainder to operand 3. | |
1827 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1828 | ||
8ffd9c51 RK |
1829 | (define_expand "divmodsi4" |
1830 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1831 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1832 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 1833 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
1834 | (mod:SI (match_dup 1) (match_dup 2)))])] |
1835 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1836 | " | |
1837 | { | |
1838 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1839 | { | |
39403d82 DE |
1840 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1841 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1842 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1843 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1844 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1845 | DONE; |
1846 | } | |
1847 | }") | |
deb9225a | 1848 | |
bb157ff4 | 1849 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
1850 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1851 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1852 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 1853 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 1854 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1855 | "TARGET_POWER" |
cfb557c4 RK |
1856 | "divs %0,%1,%2" |
1857 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1858 | |
8ffd9c51 RK |
1859 | (define_expand "udivsi3" |
1860 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1861 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1862 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1863 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1864 | " | |
1865 | { | |
1866 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1867 | { | |
39403d82 DE |
1868 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1869 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1870 | emit_insn (gen_quous_call ()); |
39403d82 | 1871 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1872 | DONE; |
1873 | } | |
f192bf8b DE |
1874 | else if (TARGET_POWER) |
1875 | { | |
1876 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1877 | DONE; | |
1878 | } | |
8ffd9c51 | 1879 | }") |
deb9225a | 1880 | |
f192bf8b DE |
1881 | (define_insn "udivsi3_mq" |
1882 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1883 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1884 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1885 | (clobber (match_scratch:SI 3 "=q"))] | |
1886 | "TARGET_POWERPC && TARGET_POWER" | |
1887 | "divwu %0,%1,%2" | |
1888 | [(set_attr "type" "idiv")]) | |
1889 | ||
1890 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1891 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1892 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1893 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1894 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1895 | "divwu %0,%1,%2" |
ca7f5001 RK |
1896 | [(set_attr "type" "idiv")]) |
1897 | ||
1fd4e8c1 | 1898 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1899 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1900 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1901 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1902 | (define_expand "divsi3" |
cd2b37d9 RK |
1903 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1904 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1905 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1906 | "" | |
1907 | " | |
1908 | { | |
ca7f5001 | 1909 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 1910 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
1911 | && exact_log2 (INTVAL (operands[2])) >= 0) |
1912 | ; | |
b6c9286a | 1913 | else if (TARGET_POWERPC) |
f192bf8b DE |
1914 | { |
1915 | operands[2] = force_reg (SImode, operands[2]); | |
1916 | if (TARGET_POWER) | |
1917 | { | |
1918 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1919 | DONE; | |
1920 | } | |
1921 | } | |
b6c9286a | 1922 | else if (TARGET_POWER) |
1fd4e8c1 | 1923 | FAIL; |
405c5495 | 1924 | else |
8ffd9c51 | 1925 | { |
39403d82 DE |
1926 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1927 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1928 | emit_insn (gen_quoss_call ()); |
39403d82 | 1929 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1930 | DONE; |
1931 | } | |
1fd4e8c1 RK |
1932 | }") |
1933 | ||
f192bf8b DE |
1934 | (define_insn "divsi3_mq" |
1935 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1936 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1937 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1938 | (clobber (match_scratch:SI 3 "=q"))] | |
1939 | "TARGET_POWERPC && TARGET_POWER" | |
1940 | "divw %0,%1,%2" | |
1941 | [(set_attr "type" "idiv")]) | |
1942 | ||
1943 | (define_insn "*divsi3_no_mq" | |
1944 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1945 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1946 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1947 | "TARGET_POWERPC && ! TARGET_POWER" | |
1948 | "divw %0,%1,%2" | |
1949 | [(set_attr "type" "idiv")]) | |
1950 | ||
1fd4e8c1 | 1951 | (define_expand "modsi3" |
85644414 RK |
1952 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1953 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1954 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1955 | "" |
1fd4e8c1 RK |
1956 | " |
1957 | { | |
481c7efa | 1958 | int i; |
39b52ba2 RK |
1959 | rtx temp1; |
1960 | rtx temp2; | |
1961 | ||
2bfcf297 | 1962 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 1963 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 1964 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
1965 | FAIL; |
1966 | ||
1967 | temp1 = gen_reg_rtx (SImode); | |
1968 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1969 | |
85644414 | 1970 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1971 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1972 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1973 | DONE; | |
1fd4e8c1 RK |
1974 | }") |
1975 | ||
1976 | (define_insn "" | |
cd2b37d9 RK |
1977 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1978 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
1979 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
1980 | "" | |
ca7f5001 | 1981 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
943c15ed DE |
1982 | [(set_attr "type" "two") |
1983 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
1984 | |
1985 | (define_insn "" | |
9ebbca7d GK |
1986 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1987 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 1988 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 1989 | (const_int 0))) |
9ebbca7d | 1990 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 1991 | "" |
9ebbca7d GK |
1992 | "@ |
1993 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
1994 | #" | |
b19003d8 | 1995 | [(set_attr "type" "compare") |
9ebbca7d GK |
1996 | (set_attr "length" "8,12")]) |
1997 | ||
1998 | (define_split | |
1999 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2000 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2001 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2002 | (const_int 0))) |
2003 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 2004 | "reload_completed" |
9ebbca7d GK |
2005 | [(set (match_dup 3) |
2006 | (div:SI (match_dup 1) (match_dup 2))) | |
2007 | (set (match_dup 0) | |
2008 | (compare:CC (match_dup 3) | |
2009 | (const_int 0)))] | |
2010 | "") | |
1fd4e8c1 RK |
2011 | |
2012 | (define_insn "" | |
9ebbca7d GK |
2013 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2014 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2015 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2016 | (const_int 0))) |
9ebbca7d | 2017 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2018 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2019 | "" |
9ebbca7d GK |
2020 | "@ |
2021 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2022 | #" | |
b19003d8 | 2023 | [(set_attr "type" "compare") |
9ebbca7d GK |
2024 | (set_attr "length" "8,12")]) |
2025 | ||
2026 | (define_split | |
2027 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2028 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2029 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2030 | (const_int 0))) |
2031 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2032 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2033 | "reload_completed" |
9ebbca7d GK |
2034 | [(set (match_dup 0) |
2035 | (div:SI (match_dup 1) (match_dup 2))) | |
2036 | (set (match_dup 3) | |
2037 | (compare:CC (match_dup 0) | |
2038 | (const_int 0)))] | |
2039 | "") | |
1fd4e8c1 RK |
2040 | |
2041 | (define_insn "" | |
cd2b37d9 | 2042 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2043 | (udiv:SI |
996a5f59 | 2044 | (plus:DI (ashift:DI |
cd2b37d9 | 2045 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2046 | (const_int 32)) |
23a900dc | 2047 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2048 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2049 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2050 | (umod:SI |
996a5f59 | 2051 | (plus:DI (ashift:DI |
1fd4e8c1 | 2052 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2053 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2054 | (match_dup 3)))] |
ca7f5001 | 2055 | "TARGET_POWER" |
cfb557c4 RK |
2056 | "div %0,%1,%3" |
2057 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2058 | |
2059 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2060 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2061 | ;; have to worry about the branches. So make a few subroutines here. | |
2062 | ;; | |
2063 | ;; First comes the normal case. | |
2064 | (define_expand "udivmodsi4_normal" | |
2065 | [(set (match_dup 4) (const_int 0)) | |
2066 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2067 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2068 | (const_int 32)) |
2069 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2070 | (match_operand:SI 2 "" ""))) | |
2071 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2072 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2073 | (const_int 32)) |
2074 | (zero_extend:DI (match_dup 1))) | |
2075 | (match_dup 2)))])] | |
ca7f5001 | 2076 | "TARGET_POWER" |
1fd4e8c1 RK |
2077 | " |
2078 | { operands[4] = gen_reg_rtx (SImode); }") | |
2079 | ||
2080 | ;; This handles the branches. | |
2081 | (define_expand "udivmodsi4_tests" | |
2082 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2083 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2084 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2085 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2086 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2087 | (set (match_dup 0) (const_int 1)) | |
2088 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2089 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2090 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2091 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2092 | "TARGET_POWER" |
1fd4e8c1 RK |
2093 | " |
2094 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2095 | operands[6] = gen_reg_rtx (CCmode); | |
2096 | }") | |
2097 | ||
2098 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2099 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2100 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2101 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2102 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2103 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2104 | "" |
1fd4e8c1 RK |
2105 | " |
2106 | { | |
2107 | rtx label = 0; | |
2108 | ||
8ffd9c51 | 2109 | if (! TARGET_POWER) |
c4d38ccb MM |
2110 | { |
2111 | if (! TARGET_POWERPC) | |
2112 | { | |
39403d82 DE |
2113 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2114 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2115 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2116 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2117 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2118 | DONE; |
2119 | } | |
2120 | else | |
2121 | FAIL; | |
2122 | } | |
0081a354 | 2123 | |
1fd4e8c1 RK |
2124 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2125 | { | |
2126 | operands[2] = force_reg (SImode, operands[2]); | |
2127 | label = gen_label_rtx (); | |
2128 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2129 | operands[3], label)); | |
2130 | } | |
2131 | else | |
2132 | operands[2] = force_reg (SImode, operands[2]); | |
2133 | ||
2134 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2135 | operands[3])); | |
2136 | if (label) | |
2137 | emit_label (label); | |
2138 | ||
2139 | DONE; | |
2140 | }") | |
0081a354 | 2141 | |
fada905b MM |
2142 | ;; AIX architecture-independent common-mode multiply (DImode), |
2143 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2144 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2145 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2146 | ;; assumed unused if generating common-mode, so ignore. | |
2147 | (define_insn "mulh_call" | |
2148 | [(set (reg:SI 3) | |
2149 | (truncate:SI | |
2150 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2151 | (sign_extend:DI (reg:SI 4))) | |
2152 | (const_int 32)))) | |
cf27b467 | 2153 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2154 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2155 | "bla __mulh" |
2156 | [(set_attr "type" "imul")]) | |
fada905b MM |
2157 | |
2158 | (define_insn "mull_call" | |
2159 | [(set (reg:DI 3) | |
2160 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2161 | (sign_extend:DI (reg:SI 4)))) | |
2162 | (clobber (match_scratch:SI 0 "=l")) | |
2163 | (clobber (reg:SI 0))] | |
2164 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2165 | "bla __mull" |
2166 | [(set_attr "type" "imul")]) | |
fada905b MM |
2167 | |
2168 | (define_insn "divss_call" | |
2169 | [(set (reg:SI 3) | |
2170 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2171 | (set (reg:SI 4) | |
2172 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2173 | (clobber (match_scratch:SI 0 "=l")) | |
2174 | (clobber (reg:SI 0))] | |
2175 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2176 | "bla __divss" |
2177 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2178 | |
2179 | (define_insn "divus_call" | |
8ffd9c51 RK |
2180 | [(set (reg:SI 3) |
2181 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2182 | (set (reg:SI 4) | |
2183 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2184 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2185 | (clobber (reg:SI 0)) |
2186 | (clobber (match_scratch:CC 1 "=x")) | |
2187 | (clobber (reg:CC 69))] | |
2188 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2189 | "bla __divus" |
2190 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2191 | |
2192 | (define_insn "quoss_call" | |
2193 | [(set (reg:SI 3) | |
2194 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2195 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2196 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2197 | "bla __quoss" |
2198 | [(set_attr "type" "idiv")]) | |
0081a354 | 2199 | |
fada905b MM |
2200 | (define_insn "quous_call" |
2201 | [(set (reg:SI 3) | |
2202 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2203 | (clobber (match_scratch:SI 0 "=l")) | |
2204 | (clobber (reg:SI 0)) | |
2205 | (clobber (match_scratch:CC 1 "=x")) | |
2206 | (clobber (reg:CC 69))] | |
2207 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2208 | "bla __quous" |
2209 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2210 | \f |
bb21487f | 2211 | ;; Logical instructions |
dfbdccdb GK |
2212 | ;; The logical instructions are mostly combined by using match_operator, |
2213 | ;; but the plain AND insns are somewhat different because there is no | |
2214 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2215 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2216 | ||
29ae5b89 JL |
2217 | (define_insn "andsi3" |
2218 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2219 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2220 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2221 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2222 | "" |
2223 | "@ | |
2224 | and %0,%1,%2 | |
ca7f5001 RK |
2225 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2226 | {andil.|andi.} %0,%1,%b2 | |
520308bc DE |
2227 | {andiu.|andis.} %0,%1,%u2" |
2228 | [(set_attr "type" "*,*,compare,compare")]) | |
52d3af72 DE |
2229 | |
2230 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2231 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2232 | ;; machines causes an execution serialization |
1fd4e8c1 | 2233 | |
7cd5235b | 2234 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2235 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2236 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2237 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2238 | (const_int 0))) |
52d3af72 DE |
2239 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2240 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2241 | "TARGET_32BIT" |
1fd4e8c1 RK |
2242 | "@ |
2243 | and. %3,%1,%2 | |
ca7f5001 RK |
2244 | {andil.|andi.} %3,%1,%b2 |
2245 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2246 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2247 | # | |
2248 | # | |
2249 | # | |
2250 | #" | |
2251 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2252 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2253 | |
0ba1b2ff AM |
2254 | (define_insn "*andsi3_internal3" |
2255 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2256 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2257 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2258 | (const_int 0))) | |
2259 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2260 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2261 | "TARGET_64BIT" |
0ba1b2ff AM |
2262 | "@ |
2263 | # | |
2264 | {andil.|andi.} %3,%1,%b2 | |
2265 | {andiu.|andis.} %3,%1,%u2 | |
2266 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2267 | # | |
2268 | # | |
2269 | # | |
2270 | #" | |
2271 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2272 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2273 | ||
52d3af72 DE |
2274 | (define_split |
2275 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2276 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2277 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2278 | (const_int 0))) |
52d3af72 DE |
2279 | (clobber (match_scratch:SI 3 "")) |
2280 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2281 | "reload_completed" |
52d3af72 DE |
2282 | [(parallel [(set (match_dup 3) |
2283 | (and:SI (match_dup 1) | |
2284 | (match_dup 2))) | |
2285 | (clobber (match_dup 4))]) | |
2286 | (set (match_dup 0) | |
2287 | (compare:CC (match_dup 3) | |
2288 | (const_int 0)))] | |
2289 | "") | |
2290 | ||
0ba1b2ff AM |
2291 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2292 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2293 | ||
2294 | (define_split | |
2295 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2296 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2297 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2298 | (const_int 0))) | |
2299 | (clobber (match_scratch:SI 3 "")) | |
2300 | (clobber (match_scratch:CC 4 ""))] | |
2301 | "TARGET_POWERPC64 && reload_completed" | |
2302 | [(parallel [(set (match_dup 3) | |
2303 | (and:SI (match_dup 1) | |
2304 | (match_dup 2))) | |
2305 | (clobber (match_dup 4))]) | |
2306 | (set (match_dup 0) | |
2307 | (compare:CC (match_dup 3) | |
2308 | (const_int 0)))] | |
2309 | "") | |
2310 | ||
2311 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2312 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2313 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2314 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2315 | (const_int 0))) |
2316 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2317 | (and:SI (match_dup 1) | |
2318 | (match_dup 2))) | |
2319 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2320 | "TARGET_32BIT" |
1fd4e8c1 RK |
2321 | "@ |
2322 | and. %0,%1,%2 | |
ca7f5001 RK |
2323 | {andil.|andi.} %0,%1,%b2 |
2324 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2325 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2326 | # | |
2327 | # | |
2328 | # | |
2329 | #" | |
2330 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2331 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2332 | ||
0ba1b2ff AM |
2333 | (define_insn "*andsi3_internal5" |
2334 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2335 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2336 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2337 | (const_int 0))) | |
2338 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2339 | (and:SI (match_dup 1) | |
2340 | (match_dup 2))) | |
2341 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2342 | "TARGET_64BIT" |
0ba1b2ff AM |
2343 | "@ |
2344 | # | |
2345 | {andil.|andi.} %0,%1,%b2 | |
2346 | {andiu.|andis.} %0,%1,%u2 | |
2347 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
2348 | # | |
2349 | # | |
2350 | # | |
2351 | #" | |
2352 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2353 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2354 | ||
52d3af72 DE |
2355 | (define_split |
2356 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2357 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2358 | (match_operand:SI 2 "and_operand" "")) | |
2359 | (const_int 0))) | |
2360 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2361 | (and:SI (match_dup 1) | |
2362 | (match_dup 2))) | |
2363 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2364 | "reload_completed" |
52d3af72 DE |
2365 | [(parallel [(set (match_dup 0) |
2366 | (and:SI (match_dup 1) | |
2367 | (match_dup 2))) | |
2368 | (clobber (match_dup 4))]) | |
2369 | (set (match_dup 3) | |
2370 | (compare:CC (match_dup 0) | |
2371 | (const_int 0)))] | |
2372 | "") | |
1fd4e8c1 | 2373 | |
0ba1b2ff AM |
2374 | (define_split |
2375 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
2376 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2377 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2378 | (const_int 0))) | |
2379 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2380 | (and:SI (match_dup 1) | |
2381 | (match_dup 2))) | |
2382 | (clobber (match_scratch:CC 4 ""))] | |
2383 | "TARGET_POWERPC64 && reload_completed" | |
2384 | [(parallel [(set (match_dup 0) | |
2385 | (and:SI (match_dup 1) | |
2386 | (match_dup 2))) | |
2387 | (clobber (match_dup 4))]) | |
2388 | (set (match_dup 3) | |
2389 | (compare:CC (match_dup 0) | |
2390 | (const_int 0)))] | |
2391 | "") | |
2392 | ||
2393 | ;; Handle the PowerPC64 rlwinm corner case | |
2394 | ||
2395 | (define_insn_and_split "*andsi3_internal6" | |
2396 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2397 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2398 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
2399 | "TARGET_POWERPC64" | |
2400 | "#" | |
2401 | "TARGET_POWERPC64" | |
2402 | [(set (match_dup 0) | |
2403 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
2404 | (match_dup 4))) | |
2405 | (set (match_dup 0) | |
2406 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
2407 | " | |
2408 | { | |
2409 | int mb = extract_MB (operands[2]); | |
2410 | int me = extract_ME (operands[2]); | |
2411 | operands[3] = GEN_INT (me + 1); | |
2412 | operands[5] = GEN_INT (32 - (me + 1)); | |
2413 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2414 | }" | |
2415 | [(set_attr "length" "8")]) | |
2416 | ||
7cd5235b | 2417 | (define_expand "iorsi3" |
cd2b37d9 | 2418 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2419 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2420 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2421 | "" |
f357808b RK |
2422 | " |
2423 | { | |
7cd5235b | 2424 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2425 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2426 | { |
2427 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2428 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2429 | ? operands[0] : gen_reg_rtx (SImode)); |
2430 | ||
a260abc9 DE |
2431 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2432 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2433 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2434 | DONE; |
2435 | } | |
f357808b RK |
2436 | }") |
2437 | ||
7cd5235b | 2438 | (define_expand "xorsi3" |
cd2b37d9 | 2439 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2440 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2441 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2442 | "" |
7cd5235b | 2443 | " |
1fd4e8c1 | 2444 | { |
7cd5235b | 2445 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2446 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2447 | { |
2448 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2449 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2450 | ? operands[0] : gen_reg_rtx (SImode)); |
2451 | ||
a260abc9 DE |
2452 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2453 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2454 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2455 | DONE; |
2456 | } | |
1fd4e8c1 RK |
2457 | }") |
2458 | ||
dfbdccdb | 2459 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2460 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2461 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2462 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2463 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2464 | "" |
2465 | "@ | |
dfbdccdb GK |
2466 | %q3 %0,%1,%2 |
2467 | {%q3il|%q3i} %0,%1,%b2 | |
2468 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2469 | |
dfbdccdb | 2470 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2471 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2472 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2473 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2474 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2475 | (const_int 0))) | |
52d3af72 | 2476 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2477 | "TARGET_32BIT" |
52d3af72 | 2478 | "@ |
dfbdccdb | 2479 | %q4. %3,%1,%2 |
52d3af72 DE |
2480 | #" |
2481 | [(set_attr "type" "compare") | |
2482 | (set_attr "length" "4,8")]) | |
2483 | ||
2484 | (define_split | |
2485 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2486 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2487 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2488 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2489 | (const_int 0))) |
52d3af72 | 2490 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2491 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2492 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2493 | (set (match_dup 0) |
2494 | (compare:CC (match_dup 3) | |
2495 | (const_int 0)))] | |
2496 | "") | |
815cdc52 | 2497 | |
dfbdccdb | 2498 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2499 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2500 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2501 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2502 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2503 | (const_int 0))) | |
52d3af72 | 2504 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2505 | (match_dup 4))] |
4b8a63d6 | 2506 | "TARGET_32BIT" |
52d3af72 | 2507 | "@ |
dfbdccdb | 2508 | %q4. %0,%1,%2 |
52d3af72 DE |
2509 | #" |
2510 | [(set_attr "type" "compare") | |
2511 | (set_attr "length" "4,8")]) | |
2512 | ||
2513 | (define_split | |
e72247f4 | 2514 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2515 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2516 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2517 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2518 | (const_int 0))) |
75540af0 | 2519 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2520 | (match_dup 4))] |
4b8a63d6 | 2521 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2522 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2523 | (set (match_dup 3) |
2524 | (compare:CC (match_dup 0) | |
2525 | (const_int 0)))] | |
2526 | "") | |
1fd4e8c1 | 2527 | |
6ae08853 | 2528 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 2529 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
2530 | |
2531 | (define_split | |
2532 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2533 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2534 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2535 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2536 | "" |
dfbdccdb GK |
2537 | [(set (match_dup 0) (match_dup 4)) |
2538 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2539 | " |
2540 | { | |
dfbdccdb GK |
2541 | rtx i; |
2542 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
1c563bed | 2543 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2544 | operands[1], i); |
dfbdccdb | 2545 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1c563bed | 2546 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2547 | operands[0], i); |
a260abc9 DE |
2548 | }") |
2549 | ||
dfbdccdb | 2550 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2551 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2552 | (match_operator:SI 3 "boolean_operator" |
2553 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2554 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2555 | "" |
dfbdccdb | 2556 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2557 | |
dfbdccdb | 2558 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2559 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2560 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2561 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2562 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2563 | (const_int 0))) | |
52d3af72 | 2564 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2565 | "TARGET_32BIT" |
52d3af72 | 2566 | "@ |
dfbdccdb | 2567 | %q4. %3,%2,%1 |
52d3af72 DE |
2568 | #" |
2569 | [(set_attr "type" "compare") | |
2570 | (set_attr "length" "4,8")]) | |
2571 | ||
2572 | (define_split | |
2573 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2574 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2575 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2576 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2577 | (const_int 0))) |
52d3af72 | 2578 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2579 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2580 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2581 | (set (match_dup 0) |
2582 | (compare:CC (match_dup 3) | |
2583 | (const_int 0)))] | |
2584 | "") | |
1fd4e8c1 | 2585 | |
dfbdccdb | 2586 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2587 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2588 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2589 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2590 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2591 | (const_int 0))) | |
52d3af72 | 2592 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2593 | (match_dup 4))] |
4b8a63d6 | 2594 | "TARGET_32BIT" |
52d3af72 | 2595 | "@ |
dfbdccdb | 2596 | %q4. %0,%2,%1 |
52d3af72 DE |
2597 | #" |
2598 | [(set_attr "type" "compare") | |
2599 | (set_attr "length" "4,8")]) | |
2600 | ||
2601 | (define_split | |
e72247f4 | 2602 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2603 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2604 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2605 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2606 | (const_int 0))) |
75540af0 | 2607 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2608 | (match_dup 4))] |
4b8a63d6 | 2609 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2610 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2611 | (set (match_dup 3) |
2612 | (compare:CC (match_dup 0) | |
2613 | (const_int 0)))] | |
2614 | "") | |
2615 | ||
dfbdccdb | 2616 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2617 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2618 | (match_operator:SI 3 "boolean_operator" |
2619 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2620 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2621 | "" |
dfbdccdb | 2622 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2623 | |
dfbdccdb | 2624 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2625 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2626 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2627 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2628 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2629 | (const_int 0))) | |
52d3af72 | 2630 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2631 | "TARGET_32BIT" |
52d3af72 | 2632 | "@ |
dfbdccdb | 2633 | %q4. %3,%1,%2 |
52d3af72 DE |
2634 | #" |
2635 | [(set_attr "type" "compare") | |
2636 | (set_attr "length" "4,8")]) | |
2637 | ||
2638 | (define_split | |
2639 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2640 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2641 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2642 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2643 | (const_int 0))) |
52d3af72 | 2644 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2645 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2646 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2647 | (set (match_dup 0) |
2648 | (compare:CC (match_dup 3) | |
2649 | (const_int 0)))] | |
2650 | "") | |
1fd4e8c1 | 2651 | |
dfbdccdb | 2652 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2653 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2654 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2655 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2656 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2657 | (const_int 0))) | |
52d3af72 | 2658 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2659 | (match_dup 4))] |
4b8a63d6 | 2660 | "TARGET_32BIT" |
52d3af72 | 2661 | "@ |
dfbdccdb | 2662 | %q4. %0,%1,%2 |
52d3af72 DE |
2663 | #" |
2664 | [(set_attr "type" "compare") | |
2665 | (set_attr "length" "4,8")]) | |
2666 | ||
2667 | (define_split | |
e72247f4 | 2668 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2669 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2670 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2671 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2672 | (const_int 0))) |
75540af0 | 2673 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2674 | (match_dup 4))] |
4b8a63d6 | 2675 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2676 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2677 | (set (match_dup 3) |
2678 | (compare:CC (match_dup 0) | |
2679 | (const_int 0)))] | |
2680 | "") | |
1fd4e8c1 RK |
2681 | |
2682 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2683 | ;; orders. Don't define forms that only set CR fields because these | |
2684 | ;; would modify an input register. | |
2685 | ||
7cd5235b | 2686 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2687 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2688 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2689 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2690 | (and:SI (match_dup 2) | |
cd2b37d9 | 2691 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2692 | "TARGET_POWER" |
01def764 | 2693 | "maskir %0,%3,%2") |
1fd4e8c1 | 2694 | |
7cd5235b | 2695 | (define_insn "*maskir_internal2" |
242e8072 | 2696 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2697 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2698 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2699 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2700 | (match_dup 2))))] |
ca7f5001 | 2701 | "TARGET_POWER" |
01def764 | 2702 | "maskir %0,%3,%2") |
1fd4e8c1 | 2703 | |
7cd5235b | 2704 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2705 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2706 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2707 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2708 | (and:SI (not:SI (match_dup 2)) |
2709 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2710 | "TARGET_POWER" |
01def764 | 2711 | "maskir %0,%3,%2") |
1fd4e8c1 | 2712 | |
7cd5235b | 2713 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2714 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2715 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2716 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2717 | (and:SI (not:SI (match_dup 2)) | |
2718 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2719 | "TARGET_POWER" |
01def764 | 2720 | "maskir %0,%3,%2") |
1fd4e8c1 | 2721 | |
7cd5235b | 2722 | (define_insn "*maskir_internal5" |
9ebbca7d | 2723 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2724 | (compare:CC |
9ebbca7d GK |
2725 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2726 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2727 | (and:SI (match_dup 2) |
9ebbca7d | 2728 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2729 | (const_int 0))) |
9ebbca7d | 2730 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2731 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2732 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2733 | "TARGET_POWER" |
9ebbca7d GK |
2734 | "@ |
2735 | maskir. %0,%3,%2 | |
2736 | #" | |
2737 | [(set_attr "type" "compare") | |
2738 | (set_attr "length" "4,8")]) | |
2739 | ||
2740 | (define_split | |
2741 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2742 | (compare:CC | |
2743 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2744 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2745 | (and:SI (match_dup 2) | |
2746 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2747 | (const_int 0))) | |
2748 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2749 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2750 | (and:SI (match_dup 2) (match_dup 3))))] | |
2751 | "TARGET_POWER && reload_completed" | |
2752 | [(set (match_dup 0) | |
2753 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2754 | (and:SI (match_dup 2) (match_dup 3)))) | |
2755 | (set (match_dup 4) | |
2756 | (compare:CC (match_dup 0) | |
2757 | (const_int 0)))] | |
2758 | "") | |
1fd4e8c1 | 2759 | |
7cd5235b | 2760 | (define_insn "*maskir_internal6" |
9ebbca7d | 2761 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2762 | (compare:CC |
9ebbca7d GK |
2763 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2764 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2765 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2766 | (match_dup 2))) |
1fd4e8c1 | 2767 | (const_int 0))) |
9ebbca7d | 2768 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2769 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2770 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2771 | "TARGET_POWER" |
9ebbca7d GK |
2772 | "@ |
2773 | maskir. %0,%3,%2 | |
2774 | #" | |
2775 | [(set_attr "type" "compare") | |
2776 | (set_attr "length" "4,8")]) | |
2777 | ||
2778 | (define_split | |
2779 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2780 | (compare:CC | |
2781 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2782 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2783 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2784 | (match_dup 2))) | |
2785 | (const_int 0))) | |
2786 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2787 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2788 | (and:SI (match_dup 3) (match_dup 2))))] | |
2789 | "TARGET_POWER && reload_completed" | |
2790 | [(set (match_dup 0) | |
2791 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2792 | (and:SI (match_dup 3) (match_dup 2)))) | |
2793 | (set (match_dup 4) | |
2794 | (compare:CC (match_dup 0) | |
2795 | (const_int 0)))] | |
2796 | "") | |
1fd4e8c1 | 2797 | |
7cd5235b | 2798 | (define_insn "*maskir_internal7" |
9ebbca7d | 2799 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 2800 | (compare:CC |
9ebbca7d GK |
2801 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
2802 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2803 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2804 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 2805 | (const_int 0))) |
9ebbca7d | 2806 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
2807 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2808 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2809 | "TARGET_POWER" | |
9ebbca7d GK |
2810 | "@ |
2811 | maskir. %0,%3,%2 | |
2812 | #" | |
2813 | [(set_attr "type" "compare") | |
2814 | (set_attr "length" "4,8")]) | |
2815 | ||
2816 | (define_split | |
2817 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2818 | (compare:CC | |
2819 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
2820 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
2821 | (and:SI (not:SI (match_dup 2)) | |
2822 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2823 | (const_int 0))) | |
2824 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2825 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2826 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2827 | "TARGET_POWER && reload_completed" | |
2828 | [(set (match_dup 0) | |
2829 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2830 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2831 | (set (match_dup 4) | |
2832 | (compare:CC (match_dup 0) | |
2833 | (const_int 0)))] | |
2834 | "") | |
1fd4e8c1 | 2835 | |
7cd5235b | 2836 | (define_insn "*maskir_internal8" |
9ebbca7d | 2837 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2838 | (compare:CC |
9ebbca7d GK |
2839 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
2840 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 2841 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2842 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 2843 | (const_int 0))) |
9ebbca7d | 2844 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2845 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2846 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2847 | "TARGET_POWER" |
9ebbca7d GK |
2848 | "@ |
2849 | maskir. %0,%3,%2 | |
2850 | #" | |
2851 | [(set_attr "type" "compare") | |
2852 | (set_attr "length" "4,8")]) | |
fcce224d | 2853 | |
9ebbca7d GK |
2854 | (define_split |
2855 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2856 | (compare:CC | |
2857 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2858 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2859 | (and:SI (not:SI (match_dup 2)) | |
2860 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2861 | (const_int 0))) | |
2862 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2863 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2864 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2865 | "TARGET_POWER && reload_completed" | |
2866 | [(set (match_dup 0) | |
2867 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2868 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2869 | (set (match_dup 4) | |
2870 | (compare:CC (match_dup 0) | |
2871 | (const_int 0)))] | |
2872 | "") | |
fcce224d | 2873 | \f |
1fd4e8c1 RK |
2874 | ;; Rotate and shift insns, in all their variants. These support shifts, |
2875 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2876 | (define_expand "insv" |
0ad91047 DE |
2877 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2878 | (match_operand:SI 1 "const_int_operand" "") | |
2879 | (match_operand:SI 2 "const_int_operand" "")) | |
2880 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2881 | "" |
2882 | " | |
2883 | { | |
2884 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2885 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2886 | compiler if the address of the structure is taken later. */ | |
2887 | if (GET_CODE (operands[0]) == SUBREG | |
2888 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2889 | FAIL; | |
a78e33fc DE |
2890 | |
2891 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2892 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2893 | else | |
2894 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2895 | DONE; | |
034c1be0 MM |
2896 | }") |
2897 | ||
a78e33fc | 2898 | (define_insn "insvsi" |
cd2b37d9 | 2899 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2900 | (match_operand:SI 1 "const_int_operand" "i") |
2901 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2902 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2903 | "" |
2904 | "* | |
2905 | { | |
2906 | int start = INTVAL (operands[2]) & 31; | |
2907 | int size = INTVAL (operands[1]) & 31; | |
2908 | ||
89e9f3a8 MM |
2909 | operands[4] = GEN_INT (32 - start - size); |
2910 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2911 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2912 | }" |
2913 | [(set_attr "type" "insert_word")]) | |
1fd4e8c1 | 2914 | |
a78e33fc | 2915 | (define_insn "*insvsi_internal1" |
d56d506a RK |
2916 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2917 | (match_operand:SI 1 "const_int_operand" "i") | |
2918 | (match_operand:SI 2 "const_int_operand" "i")) | |
2919 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2920 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2921 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2922 | "* |
2923 | { | |
2924 | int shift = INTVAL (operands[4]) & 31; | |
2925 | int start = INTVAL (operands[2]) & 31; | |
2926 | int size = INTVAL (operands[1]) & 31; | |
2927 | ||
89e9f3a8 MM |
2928 | operands[4] = GEN_INT (shift - start - size); |
2929 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2930 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2931 | }" |
2932 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2933 | |
a78e33fc | 2934 | (define_insn "*insvsi_internal2" |
d56d506a RK |
2935 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2936 | (match_operand:SI 1 "const_int_operand" "i") | |
2937 | (match_operand:SI 2 "const_int_operand" "i")) | |
2938 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2939 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2940 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2941 | "* |
2942 | { | |
2943 | int shift = INTVAL (operands[4]) & 31; | |
2944 | int start = INTVAL (operands[2]) & 31; | |
2945 | int size = INTVAL (operands[1]) & 31; | |
2946 | ||
89e9f3a8 MM |
2947 | operands[4] = GEN_INT (32 - shift - start - size); |
2948 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2949 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2950 | }" |
2951 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2952 | |
a78e33fc | 2953 | (define_insn "*insvsi_internal3" |
d56d506a RK |
2954 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2955 | (match_operand:SI 1 "const_int_operand" "i") | |
2956 | (match_operand:SI 2 "const_int_operand" "i")) | |
2957 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2958 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 2959 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2960 | "* |
2961 | { | |
2962 | int shift = INTVAL (operands[4]) & 31; | |
2963 | int start = INTVAL (operands[2]) & 31; | |
2964 | int size = INTVAL (operands[1]) & 31; | |
2965 | ||
89e9f3a8 MM |
2966 | operands[4] = GEN_INT (32 - shift - start - size); |
2967 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2968 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2969 | }" |
2970 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2971 | |
a78e33fc | 2972 | (define_insn "*insvsi_internal4" |
d56d506a RK |
2973 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2974 | (match_operand:SI 1 "const_int_operand" "i") | |
2975 | (match_operand:SI 2 "const_int_operand" "i")) | |
2976 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2977 | (match_operand:SI 4 "const_int_operand" "i") | |
2978 | (match_operand:SI 5 "const_int_operand" "i")))] | |
2979 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
2980 | "* | |
2981 | { | |
2982 | int extract_start = INTVAL (operands[5]) & 31; | |
2983 | int extract_size = INTVAL (operands[4]) & 31; | |
2984 | int insert_start = INTVAL (operands[2]) & 31; | |
2985 | int insert_size = INTVAL (operands[1]) & 31; | |
2986 | ||
2987 | /* Align extract field with insert field */ | |
3a598fbe | 2988 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 2989 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 2990 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
8e8238f1 DE |
2991 | }" |
2992 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2993 | |
f241bf89 EC |
2994 | ;; combine patterns for rlwimi |
2995 | (define_insn "*insvsi_internal5" | |
2996 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2997 | (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
2998 | (match_operand:SI 1 "mask_operand" "i")) | |
2999 | (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3000 | (match_operand:SI 2 "const_int_operand" "i")) | |
3001 | (match_operand:SI 5 "mask_operand" "i"))))] | |
3002 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3003 | "* | |
3004 | { | |
3005 | int me = extract_ME(operands[5]); | |
3006 | int mb = extract_MB(operands[5]); | |
3007 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3008 | operands[2] = GEN_INT(mb); | |
3009 | operands[1] = GEN_INT(me); | |
3010 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3011 | }" | |
3012 | [(set_attr "type" "insert_word")]) | |
3013 | ||
3014 | (define_insn "*insvsi_internal6" | |
3015 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3016 | (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3017 | (match_operand:SI 2 "const_int_operand" "i")) | |
3018 | (match_operand:SI 5 "mask_operand" "i")) | |
3019 | (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
3020 | (match_operand:SI 1 "mask_operand" "i"))))] | |
3021 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3022 | "* | |
3023 | { | |
3024 | int me = extract_ME(operands[5]); | |
3025 | int mb = extract_MB(operands[5]); | |
3026 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3027 | operands[2] = GEN_INT(mb); | |
3028 | operands[1] = GEN_INT(me); | |
3029 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3030 | }" | |
3031 | [(set_attr "type" "insert_word")]) | |
3032 | ||
a78e33fc | 3033 | (define_insn "insvdi" |
685f3906 | 3034 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3035 | (match_operand:SI 1 "const_int_operand" "i") |
3036 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3037 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3038 | "TARGET_POWERPC64" | |
3039 | "* | |
3040 | { | |
3041 | int start = INTVAL (operands[2]) & 63; | |
3042 | int size = INTVAL (operands[1]) & 63; | |
3043 | ||
a78e33fc DE |
3044 | operands[1] = GEN_INT (64 - start - size); |
3045 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3046 | }") |
3047 | ||
11ac38b2 DE |
3048 | (define_insn "*insvdi_internal2" |
3049 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3050 | (match_operand:SI 1 "const_int_operand" "i") | |
3051 | (match_operand:SI 2 "const_int_operand" "i")) | |
3052 | (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3053 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3054 | "TARGET_POWERPC64 | |
3055 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3056 | "* | |
3057 | { | |
3058 | int shift = INTVAL (operands[4]) & 63; | |
3059 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3060 | int size = INTVAL (operands[1]) & 63; | |
3061 | ||
3062 | operands[4] = GEN_INT (64 - shift - start - size); | |
3063 | operands[2] = GEN_INT (start); | |
3064 | operands[1] = GEN_INT (start + size - 1); | |
3065 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3066 | }") | |
3067 | ||
3068 | (define_insn "*insvdi_internal3" | |
3069 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3070 | (match_operand:SI 1 "const_int_operand" "i") | |
3071 | (match_operand:SI 2 "const_int_operand" "i")) | |
3072 | (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3073 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3074 | "TARGET_POWERPC64 | |
3075 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3076 | "* | |
3077 | { | |
3078 | int shift = INTVAL (operands[4]) & 63; | |
3079 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3080 | int size = INTVAL (operands[1]) & 63; | |
3081 | ||
3082 | operands[4] = GEN_INT (64 - shift - start - size); | |
3083 | operands[2] = GEN_INT (start); | |
3084 | operands[1] = GEN_INT (start + size - 1); | |
3085 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3086 | }") | |
3087 | ||
034c1be0 | 3088 | (define_expand "extzv" |
0ad91047 DE |
3089 | [(set (match_operand 0 "gpc_reg_operand" "") |
3090 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3091 | (match_operand:SI 2 "const_int_operand" "") | |
3092 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3093 | "" |
3094 | " | |
3095 | { | |
3096 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3097 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3098 | compiler if the address of the structure is taken later. */ | |
3099 | if (GET_CODE (operands[0]) == SUBREG | |
3100 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3101 | FAIL; | |
a78e33fc DE |
3102 | |
3103 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3104 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3105 | else | |
3106 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3107 | DONE; | |
034c1be0 MM |
3108 | }") |
3109 | ||
a78e33fc | 3110 | (define_insn "extzvsi" |
cd2b37d9 RK |
3111 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3112 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3113 | (match_operand:SI 2 "const_int_operand" "i") |
3114 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3115 | "" | |
3116 | "* | |
3117 | { | |
3118 | int start = INTVAL (operands[3]) & 31; | |
3119 | int size = INTVAL (operands[2]) & 31; | |
3120 | ||
3121 | if (start + size >= 32) | |
3122 | operands[3] = const0_rtx; | |
3123 | else | |
89e9f3a8 | 3124 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3125 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3126 | }") |
3127 | ||
a78e33fc | 3128 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3129 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3130 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3131 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3132 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3133 | (const_int 0))) |
9ebbca7d | 3134 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3135 | "" |
1fd4e8c1 RK |
3136 | "* |
3137 | { | |
3138 | int start = INTVAL (operands[3]) & 31; | |
3139 | int size = INTVAL (operands[2]) & 31; | |
3140 | ||
9ebbca7d GK |
3141 | /* Force split for non-cc0 compare. */ |
3142 | if (which_alternative == 1) | |
3143 | return \"#\"; | |
3144 | ||
43a88a8c | 3145 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3146 | word, it is possible to use andiu. or andil. to test it. This is |
3147 | useful because the condition register set-use delay is smaller for | |
3148 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3149 | position is 0 because the LT and GT bits may be set wrong. */ | |
3150 | ||
3151 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3152 | { |
3a598fbe | 3153 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3154 | - (1 << (16 - (start & 15) - size)))); |
3155 | if (start < 16) | |
ca7f5001 | 3156 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3157 | else |
ca7f5001 | 3158 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3159 | } |
7e69e155 | 3160 | |
1fd4e8c1 RK |
3161 | if (start + size >= 32) |
3162 | operands[3] = const0_rtx; | |
3163 | else | |
89e9f3a8 | 3164 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3165 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3166 | }" |
9ebbca7d GK |
3167 | [(set_attr "type" "compare") |
3168 | (set_attr "length" "4,8")]) | |
3169 | ||
3170 | (define_split | |
3171 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3172 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3173 | (match_operand:SI 2 "const_int_operand" "") | |
3174 | (match_operand:SI 3 "const_int_operand" "")) | |
3175 | (const_int 0))) | |
3176 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3177 | "reload_completed" |
9ebbca7d GK |
3178 | [(set (match_dup 4) |
3179 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3180 | (match_dup 3))) | |
3181 | (set (match_dup 0) | |
3182 | (compare:CC (match_dup 4) | |
3183 | (const_int 0)))] | |
3184 | "") | |
1fd4e8c1 | 3185 | |
a78e33fc | 3186 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3187 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3188 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3189 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3190 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3191 | (const_int 0))) |
9ebbca7d | 3192 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3193 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3194 | "" |
1fd4e8c1 RK |
3195 | "* |
3196 | { | |
3197 | int start = INTVAL (operands[3]) & 31; | |
3198 | int size = INTVAL (operands[2]) & 31; | |
3199 | ||
9ebbca7d GK |
3200 | /* Force split for non-cc0 compare. */ |
3201 | if (which_alternative == 1) | |
3202 | return \"#\"; | |
3203 | ||
bc401279 | 3204 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3205 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3206 | if (start >= 16 && start + size == 32) |
df031c43 | 3207 | { |
bc401279 AM |
3208 | operands[3] = GEN_INT ((1 << size) - 1); |
3209 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3210 | } |
7e69e155 | 3211 | |
1fd4e8c1 RK |
3212 | if (start + size >= 32) |
3213 | operands[3] = const0_rtx; | |
3214 | else | |
89e9f3a8 | 3215 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3216 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3217 | }" |
ce71f754 | 3218 | [(set_attr "type" "compare") |
9ebbca7d GK |
3219 | (set_attr "length" "4,8")]) |
3220 | ||
3221 | (define_split | |
3222 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3223 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3224 | (match_operand:SI 2 "const_int_operand" "") | |
3225 | (match_operand:SI 3 "const_int_operand" "")) | |
3226 | (const_int 0))) | |
3227 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3228 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3229 | "reload_completed" |
9ebbca7d GK |
3230 | [(set (match_dup 0) |
3231 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3232 | (set (match_dup 4) | |
3233 | (compare:CC (match_dup 0) | |
3234 | (const_int 0)))] | |
3235 | "") | |
1fd4e8c1 | 3236 | |
a78e33fc | 3237 | (define_insn "extzvdi" |
685f3906 DE |
3238 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3239 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3240 | (match_operand:SI 2 "const_int_operand" "i") |
3241 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3242 | "TARGET_POWERPC64" |
3243 | "* | |
3244 | { | |
3245 | int start = INTVAL (operands[3]) & 63; | |
3246 | int size = INTVAL (operands[2]) & 63; | |
3247 | ||
3248 | if (start + size >= 64) | |
3249 | operands[3] = const0_rtx; | |
3250 | else | |
89e9f3a8 MM |
3251 | operands[3] = GEN_INT (start + size); |
3252 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3253 | return \"rldicl %0,%1,%3,%2\"; |
3254 | }") | |
3255 | ||
a78e33fc | 3256 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3257 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3258 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3259 | (match_operand:SI 2 "const_int_operand" "i") |
3260 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3261 | (const_int 0))) |
29ae5b89 | 3262 | (clobber (match_scratch:DI 4 "=r"))] |
683bdff7 | 3263 | "TARGET_64BIT" |
685f3906 DE |
3264 | "* |
3265 | { | |
3266 | int start = INTVAL (operands[3]) & 63; | |
3267 | int size = INTVAL (operands[2]) & 63; | |
3268 | ||
3269 | if (start + size >= 64) | |
3270 | operands[3] = const0_rtx; | |
3271 | else | |
89e9f3a8 MM |
3272 | operands[3] = GEN_INT (start + size); |
3273 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3274 | return \"rldicl. %4,%1,%3,%2\"; |
9a3c428b DE |
3275 | }" |
3276 | [(set_attr "type" "compare")]) | |
685f3906 | 3277 | |
a78e33fc | 3278 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3279 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3280 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3281 | (match_operand:SI 2 "const_int_operand" "i") |
3282 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3283 | (const_int 0))) |
29ae5b89 | 3284 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 | 3285 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
683bdff7 | 3286 | "TARGET_64BIT" |
685f3906 DE |
3287 | "* |
3288 | { | |
3289 | int start = INTVAL (operands[3]) & 63; | |
3290 | int size = INTVAL (operands[2]) & 63; | |
3291 | ||
3292 | if (start + size >= 64) | |
3293 | operands[3] = const0_rtx; | |
3294 | else | |
89e9f3a8 MM |
3295 | operands[3] = GEN_INT (start + size); |
3296 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3297 | return \"rldicl. %0,%1,%3,%2\"; |
9a3c428b DE |
3298 | }" |
3299 | [(set_attr "type" "compare")]) | |
685f3906 | 3300 | |
1fd4e8c1 | 3301 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3302 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3303 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3304 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3305 | "" | |
ca7f5001 | 3306 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3307 | |
a260abc9 | 3308 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3309 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3310 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3311 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3312 | (const_int 0))) |
9ebbca7d | 3313 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 3314 | "" |
9ebbca7d GK |
3315 | "@ |
3316 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3317 | #" | |
3318 | [(set_attr "type" "delayed_compare") | |
3319 | (set_attr "length" "4,8")]) | |
3320 | ||
3321 | (define_split | |
3322 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3323 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3324 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3325 | (const_int 0))) | |
3326 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 3327 | "reload_completed" |
9ebbca7d GK |
3328 | [(set (match_dup 3) |
3329 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3330 | (set (match_dup 0) | |
3331 | (compare:CC (match_dup 3) | |
3332 | (const_int 0)))] | |
3333 | "") | |
1fd4e8c1 | 3334 | |
a260abc9 | 3335 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3336 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3337 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3338 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3339 | (const_int 0))) |
9ebbca7d | 3340 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3341 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 3342 | "" |
9ebbca7d GK |
3343 | "@ |
3344 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3345 | #" | |
3346 | [(set_attr "type" "delayed_compare") | |
3347 | (set_attr "length" "4,8")]) | |
3348 | ||
3349 | (define_split | |
3350 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3351 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3352 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3353 | (const_int 0))) | |
3354 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3355 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 3356 | "reload_completed" |
9ebbca7d GK |
3357 | [(set (match_dup 0) |
3358 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3359 | (set (match_dup 3) | |
3360 | (compare:CC (match_dup 0) | |
3361 | (const_int 0)))] | |
3362 | "") | |
1fd4e8c1 | 3363 | |
a260abc9 | 3364 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3365 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3366 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3367 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 3368 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3369 | "" |
ca7f5001 | 3370 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3371 | |
a260abc9 | 3372 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3373 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3374 | (compare:CC (and:SI |
9ebbca7d GK |
3375 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3376 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3377 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3378 | (const_int 0))) |
9ebbca7d | 3379 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3380 | "" |
9ebbca7d GK |
3381 | "@ |
3382 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3383 | #" | |
3384 | [(set_attr "type" "delayed_compare") | |
3385 | (set_attr "length" "4,8")]) | |
3386 | ||
3387 | (define_split | |
3388 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3389 | (compare:CC (and:SI | |
3390 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3391 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3392 | (match_operand:SI 3 "mask_operand" "")) | |
3393 | (const_int 0))) | |
3394 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3395 | "reload_completed" |
9ebbca7d GK |
3396 | [(set (match_dup 4) |
3397 | (and:SI (rotate:SI (match_dup 1) | |
3398 | (match_dup 2)) | |
3399 | (match_dup 3))) | |
3400 | (set (match_dup 0) | |
3401 | (compare:CC (match_dup 4) | |
3402 | (const_int 0)))] | |
3403 | "") | |
1fd4e8c1 | 3404 | |
a260abc9 | 3405 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3406 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3407 | (compare:CC (and:SI |
9ebbca7d GK |
3408 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3409 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3410 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3411 | (const_int 0))) |
9ebbca7d | 3412 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3413 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3414 | "" |
9ebbca7d GK |
3415 | "@ |
3416 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3417 | #" | |
3418 | [(set_attr "type" "delayed_compare") | |
3419 | (set_attr "length" "4,8")]) | |
3420 | ||
3421 | (define_split | |
3422 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3423 | (compare:CC (and:SI | |
3424 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3425 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3426 | (match_operand:SI 3 "mask_operand" "")) | |
3427 | (const_int 0))) | |
3428 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3429 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3430 | "reload_completed" |
9ebbca7d GK |
3431 | [(set (match_dup 0) |
3432 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3433 | (set (match_dup 4) | |
3434 | (compare:CC (match_dup 0) | |
3435 | (const_int 0)))] | |
3436 | "") | |
1fd4e8c1 | 3437 | |
a260abc9 | 3438 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3439 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3440 | (zero_extend:SI |
3441 | (subreg:QI | |
cd2b37d9 | 3442 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3443 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3444 | "" | |
ca7f5001 | 3445 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3446 | |
a260abc9 | 3447 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3448 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3449 | (compare:CC (zero_extend:SI |
3450 | (subreg:QI | |
9ebbca7d GK |
3451 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3452 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3453 | (const_int 0))) |
9ebbca7d | 3454 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3455 | "" |
9ebbca7d GK |
3456 | "@ |
3457 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3458 | #" | |
3459 | [(set_attr "type" "delayed_compare") | |
3460 | (set_attr "length" "4,8")]) | |
3461 | ||
3462 | (define_split | |
3463 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3464 | (compare:CC (zero_extend:SI | |
3465 | (subreg:QI | |
3466 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3467 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3468 | (const_int 0))) | |
3469 | (clobber (match_scratch:SI 3 ""))] | |
3470 | "reload_completed" | |
3471 | [(set (match_dup 3) | |
3472 | (zero_extend:SI (subreg:QI | |
3473 | (rotate:SI (match_dup 1) | |
3474 | (match_dup 2)) 0))) | |
3475 | (set (match_dup 0) | |
3476 | (compare:CC (match_dup 3) | |
3477 | (const_int 0)))] | |
3478 | "") | |
1fd4e8c1 | 3479 | |
a260abc9 | 3480 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3481 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3482 | (compare:CC (zero_extend:SI |
3483 | (subreg:QI | |
9ebbca7d GK |
3484 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3485 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3486 | (const_int 0))) |
9ebbca7d | 3487 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3488 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3489 | "" | |
9ebbca7d GK |
3490 | "@ |
3491 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3492 | #" | |
3493 | [(set_attr "type" "delayed_compare") | |
3494 | (set_attr "length" "4,8")]) | |
3495 | ||
3496 | (define_split | |
3497 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3498 | (compare:CC (zero_extend:SI | |
3499 | (subreg:QI | |
3500 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3501 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3502 | (const_int 0))) | |
3503 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3504 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3505 | "reload_completed" | |
3506 | [(set (match_dup 0) | |
3507 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3508 | (set (match_dup 3) | |
3509 | (compare:CC (match_dup 0) | |
3510 | (const_int 0)))] | |
3511 | "") | |
1fd4e8c1 | 3512 | |
a260abc9 | 3513 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3514 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3515 | (zero_extend:SI |
3516 | (subreg:HI | |
cd2b37d9 | 3517 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3518 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3519 | "" | |
ca7f5001 | 3520 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3521 | |
a260abc9 | 3522 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3523 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3524 | (compare:CC (zero_extend:SI |
3525 | (subreg:HI | |
9ebbca7d GK |
3526 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3527 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3528 | (const_int 0))) |
9ebbca7d | 3529 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3530 | "" |
9ebbca7d GK |
3531 | "@ |
3532 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3533 | #" | |
3534 | [(set_attr "type" "delayed_compare") | |
3535 | (set_attr "length" "4,8")]) | |
3536 | ||
3537 | (define_split | |
3538 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3539 | (compare:CC (zero_extend:SI | |
3540 | (subreg:HI | |
3541 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3542 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3543 | (const_int 0))) | |
3544 | (clobber (match_scratch:SI 3 ""))] | |
3545 | "reload_completed" | |
3546 | [(set (match_dup 3) | |
3547 | (zero_extend:SI (subreg:HI | |
3548 | (rotate:SI (match_dup 1) | |
3549 | (match_dup 2)) 0))) | |
3550 | (set (match_dup 0) | |
3551 | (compare:CC (match_dup 3) | |
3552 | (const_int 0)))] | |
3553 | "") | |
1fd4e8c1 | 3554 | |
a260abc9 | 3555 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3556 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3557 | (compare:CC (zero_extend:SI |
3558 | (subreg:HI | |
9ebbca7d GK |
3559 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3560 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3561 | (const_int 0))) |
9ebbca7d | 3562 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3563 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3564 | "" | |
9ebbca7d GK |
3565 | "@ |
3566 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3567 | #" | |
3568 | [(set_attr "type" "delayed_compare") | |
3569 | (set_attr "length" "4,8")]) | |
3570 | ||
3571 | (define_split | |
3572 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3573 | (compare:CC (zero_extend:SI | |
3574 | (subreg:HI | |
3575 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3576 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3577 | (const_int 0))) | |
3578 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3579 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3580 | "reload_completed" | |
3581 | [(set (match_dup 0) | |
3582 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3583 | (set (match_dup 3) | |
3584 | (compare:CC (match_dup 0) | |
3585 | (const_int 0)))] | |
3586 | "") | |
1fd4e8c1 RK |
3587 | |
3588 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3589 | ;; SHIFT_COUNT_TRUNCATED. | |
3590 | ||
ca7f5001 RK |
3591 | (define_expand "ashlsi3" |
3592 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3593 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3594 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3595 | "" | |
3596 | " | |
3597 | { | |
3598 | if (TARGET_POWER) | |
3599 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3600 | else | |
25c341fa | 3601 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3602 | DONE; |
3603 | }") | |
3604 | ||
3605 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3606 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3607 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3608 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3609 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3610 | "TARGET_POWER" |
1fd4e8c1 RK |
3611 | "@ |
3612 | sle %0,%1,%2 | |
9ebbca7d | 3613 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3614 | |
25c341fa | 3615 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3616 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3617 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3618 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3619 | "! TARGET_POWER" |
9ebbca7d | 3620 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3621 | |
3622 | (define_insn "" | |
9ebbca7d GK |
3623 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3624 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3625 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3626 | (const_int 0))) |
9ebbca7d GK |
3627 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3628 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3629 | "TARGET_POWER" |
1fd4e8c1 RK |
3630 | "@ |
3631 | sle. %3,%1,%2 | |
9ebbca7d GK |
3632 | {sli.|slwi.} %3,%1,%h2 |
3633 | # | |
3634 | #" | |
3635 | [(set_attr "type" "delayed_compare") | |
3636 | (set_attr "length" "4,4,8,8")]) | |
3637 | ||
3638 | (define_split | |
3639 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3640 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3641 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3642 | (const_int 0))) | |
3643 | (clobber (match_scratch:SI 3 "")) | |
3644 | (clobber (match_scratch:SI 4 ""))] | |
3645 | "TARGET_POWER && reload_completed" | |
3646 | [(parallel [(set (match_dup 3) | |
3647 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3648 | (clobber (match_dup 4))]) | |
3649 | (set (match_dup 0) | |
3650 | (compare:CC (match_dup 3) | |
3651 | (const_int 0)))] | |
3652 | "") | |
25c341fa | 3653 | |
ca7f5001 | 3654 | (define_insn "" |
9ebbca7d GK |
3655 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3656 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3657 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3658 | (const_int 0))) |
9ebbca7d | 3659 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 3660 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3661 | "@ |
3662 | {sl|slw}%I2. %3,%1,%h2 | |
3663 | #" | |
3664 | [(set_attr "type" "delayed_compare") | |
3665 | (set_attr "length" "4,8")]) | |
3666 | ||
3667 | (define_split | |
3668 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3669 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3670 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3671 | (const_int 0))) | |
3672 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3673 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3674 | [(set (match_dup 3) |
3675 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3676 | (set (match_dup 0) | |
3677 | (compare:CC (match_dup 3) | |
3678 | (const_int 0)))] | |
3679 | "") | |
1fd4e8c1 RK |
3680 | |
3681 | (define_insn "" | |
9ebbca7d GK |
3682 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3683 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3684 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3685 | (const_int 0))) |
9ebbca7d | 3686 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3687 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3688 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3689 | "TARGET_POWER" |
1fd4e8c1 RK |
3690 | "@ |
3691 | sle. %0,%1,%2 | |
9ebbca7d GK |
3692 | {sli.|slwi.} %0,%1,%h2 |
3693 | # | |
3694 | #" | |
3695 | [(set_attr "type" "delayed_compare") | |
3696 | (set_attr "length" "4,4,8,8")]) | |
3697 | ||
3698 | (define_split | |
3699 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3700 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3701 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3702 | (const_int 0))) | |
3703 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3704 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3705 | (clobber (match_scratch:SI 4 ""))] | |
3706 | "TARGET_POWER && reload_completed" | |
3707 | [(parallel [(set (match_dup 0) | |
3708 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3709 | (clobber (match_dup 4))]) | |
3710 | (set (match_dup 3) | |
3711 | (compare:CC (match_dup 0) | |
3712 | (const_int 0)))] | |
3713 | "") | |
25c341fa | 3714 | |
ca7f5001 | 3715 | (define_insn "" |
9ebbca7d GK |
3716 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3717 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3718 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3719 | (const_int 0))) |
9ebbca7d | 3720 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3721 | (ashift:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3722 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3723 | "@ |
3724 | {sl|slw}%I2. %0,%1,%h2 | |
3725 | #" | |
3726 | [(set_attr "type" "delayed_compare") | |
3727 | (set_attr "length" "4,8")]) | |
3728 | ||
3729 | (define_split | |
3730 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3731 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3732 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3733 | (const_int 0))) | |
3734 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3735 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3736 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3737 | [(set (match_dup 0) |
3738 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3739 | (set (match_dup 3) | |
3740 | (compare:CC (match_dup 0) | |
3741 | (const_int 0)))] | |
3742 | "") | |
1fd4e8c1 RK |
3743 | |
3744 | (define_insn "" | |
cd2b37d9 RK |
3745 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3746 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3747 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3748 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3749 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3750 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3751 | |
3752 | (define_insn "" | |
9ebbca7d | 3753 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3754 | (compare:CC |
9ebbca7d GK |
3755 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3756 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3757 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3758 | (const_int 0))) |
9ebbca7d | 3759 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3760 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3761 | "@ |
3762 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3763 | #" | |
3764 | [(set_attr "type" "delayed_compare") | |
3765 | (set_attr "length" "4,8")]) | |
3766 | ||
3767 | (define_split | |
3768 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3769 | (compare:CC | |
3770 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3771 | (match_operand:SI 2 "const_int_operand" "")) | |
3772 | (match_operand:SI 3 "mask_operand" "")) | |
3773 | (const_int 0))) | |
3774 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3775 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3776 | [(set (match_dup 4) |
3777 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3778 | (match_dup 3))) | |
3779 | (set (match_dup 0) | |
3780 | (compare:CC (match_dup 4) | |
3781 | (const_int 0)))] | |
3782 | "") | |
1fd4e8c1 RK |
3783 | |
3784 | (define_insn "" | |
9ebbca7d | 3785 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3786 | (compare:CC |
9ebbca7d GK |
3787 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3788 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3789 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3790 | (const_int 0))) |
9ebbca7d | 3791 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3792 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3793 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3794 | "@ |
3795 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3796 | #" | |
3797 | [(set_attr "type" "delayed_compare") | |
3798 | (set_attr "length" "4,8")]) | |
3799 | ||
3800 | (define_split | |
3801 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3802 | (compare:CC | |
3803 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3804 | (match_operand:SI 2 "const_int_operand" "")) | |
3805 | (match_operand:SI 3 "mask_operand" "")) | |
3806 | (const_int 0))) | |
3807 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3808 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3809 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3810 | [(set (match_dup 0) |
3811 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3812 | (set (match_dup 4) | |
3813 | (compare:CC (match_dup 0) | |
3814 | (const_int 0)))] | |
3815 | "") | |
1fd4e8c1 | 3816 | |
ca7f5001 | 3817 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3818 | ;; "sli x,x,0". |
ca7f5001 RK |
3819 | (define_expand "lshrsi3" |
3820 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3821 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3822 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3823 | "" | |
3824 | " | |
3825 | { | |
3826 | if (TARGET_POWER) | |
3827 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3828 | else | |
25c341fa | 3829 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3830 | DONE; |
3831 | }") | |
3832 | ||
3833 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3834 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3835 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3836 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3837 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3838 | "TARGET_POWER" |
1fd4e8c1 RK |
3839 | "@ |
3840 | sre %0,%1,%2 | |
bdf423cb | 3841 | mr %0,%1 |
ca7f5001 RK |
3842 | {s%A2i|s%A2wi} %0,%1,%h2") |
3843 | ||
25c341fa | 3844 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3845 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3846 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3847 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3848 | "! TARGET_POWER" |
bdf423cb MM |
3849 | "@ |
3850 | mr %0,%1 | |
3851 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3852 | |
3853 | (define_insn "" | |
9ebbca7d GK |
3854 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3855 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3856 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3857 | (const_int 0))) |
9ebbca7d GK |
3858 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3859 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3860 | "TARGET_POWER" |
1fd4e8c1 | 3861 | "@ |
29ae5b89 JL |
3862 | sre. %3,%1,%2 |
3863 | mr. %1,%1 | |
9ebbca7d GK |
3864 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
3865 | # | |
3866 | # | |
3867 | #" | |
3868 | [(set_attr "type" "delayed_compare") | |
3869 | (set_attr "length" "4,4,4,8,8,8")]) | |
3870 | ||
3871 | (define_split | |
3872 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3873 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3874 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3875 | (const_int 0))) | |
3876 | (clobber (match_scratch:SI 3 "")) | |
3877 | (clobber (match_scratch:SI 4 ""))] | |
3878 | "TARGET_POWER && reload_completed" | |
3879 | [(parallel [(set (match_dup 3) | |
3880 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3881 | (clobber (match_dup 4))]) | |
3882 | (set (match_dup 0) | |
3883 | (compare:CC (match_dup 3) | |
3884 | (const_int 0)))] | |
3885 | "") | |
ca7f5001 RK |
3886 | |
3887 | (define_insn "" | |
9ebbca7d GK |
3888 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3889 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3890 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 3891 | (const_int 0))) |
9ebbca7d | 3892 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
4b8a63d6 | 3893 | "! TARGET_POWER && TARGET_32BIT" |
bdf423cb MM |
3894 | "@ |
3895 | mr. %1,%1 | |
9ebbca7d GK |
3896 | {sr|srw}%I2. %3,%1,%h2 |
3897 | # | |
3898 | #" | |
3899 | [(set_attr "type" "delayed_compare") | |
3900 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 3901 | |
9ebbca7d GK |
3902 | (define_split |
3903 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3904 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3905 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3906 | (const_int 0))) | |
3907 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3908 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3909 | [(set (match_dup 3) |
3910 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3911 | (set (match_dup 0) | |
3912 | (compare:CC (match_dup 3) | |
3913 | (const_int 0)))] | |
3914 | "") | |
3915 | ||
3916 | (define_insn "" | |
3917 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
3918 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3919 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3920 | (const_int 0))) |
9ebbca7d | 3921 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 3922 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3923 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 3924 | "TARGET_POWER" |
1fd4e8c1 | 3925 | "@ |
29ae5b89 JL |
3926 | sre. %0,%1,%2 |
3927 | mr. %0,%1 | |
9ebbca7d GK |
3928 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
3929 | # | |
3930 | # | |
3931 | #" | |
3932 | [(set_attr "type" "delayed_compare") | |
3933 | (set_attr "length" "4,4,4,8,8,8")]) | |
3934 | ||
3935 | (define_split | |
3936 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3937 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3938 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3939 | (const_int 0))) | |
3940 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3941 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3942 | (clobber (match_scratch:SI 4 ""))] | |
3943 | "TARGET_POWER && reload_completed" | |
3944 | [(parallel [(set (match_dup 0) | |
3945 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3946 | (clobber (match_dup 4))]) | |
3947 | (set (match_dup 3) | |
3948 | (compare:CC (match_dup 0) | |
3949 | (const_int 0)))] | |
3950 | "") | |
ca7f5001 RK |
3951 | |
3952 | (define_insn "" | |
9ebbca7d GK |
3953 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3954 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3955 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 3956 | (const_int 0))) |
9ebbca7d | 3957 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 3958 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3959 | "! TARGET_POWER && TARGET_32BIT" |
29ae5b89 JL |
3960 | "@ |
3961 | mr. %0,%1 | |
9ebbca7d GK |
3962 | {sr|srw}%I2. %0,%1,%h2 |
3963 | # | |
3964 | #" | |
3965 | [(set_attr "type" "delayed_compare") | |
3966 | (set_attr "length" "4,4,8,8")]) | |
3967 | ||
3968 | (define_split | |
3969 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3970 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3971 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3972 | (const_int 0))) | |
3973 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3974 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3975 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3976 | [(set (match_dup 0) |
3977 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3978 | (set (match_dup 3) | |
3979 | (compare:CC (match_dup 0) | |
3980 | (const_int 0)))] | |
3981 | "") | |
1fd4e8c1 RK |
3982 | |
3983 | (define_insn "" | |
cd2b37d9 RK |
3984 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3985 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3986 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3987 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3988 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 3989 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
3990 | |
3991 | (define_insn "" | |
9ebbca7d | 3992 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3993 | (compare:CC |
9ebbca7d GK |
3994 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3995 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3996 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3997 | (const_int 0))) |
9ebbca7d | 3998 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3999 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4000 | "@ |
4001 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4002 | #" | |
4003 | [(set_attr "type" "delayed_compare") | |
4004 | (set_attr "length" "4,8")]) | |
4005 | ||
4006 | (define_split | |
4007 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4008 | (compare:CC | |
4009 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4010 | (match_operand:SI 2 "const_int_operand" "")) | |
4011 | (match_operand:SI 3 "mask_operand" "")) | |
4012 | (const_int 0))) | |
4013 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 4014 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4015 | [(set (match_dup 4) |
4016 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4017 | (match_dup 3))) | |
4018 | (set (match_dup 0) | |
4019 | (compare:CC (match_dup 4) | |
4020 | (const_int 0)))] | |
4021 | "") | |
1fd4e8c1 RK |
4022 | |
4023 | (define_insn "" | |
9ebbca7d | 4024 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4025 | (compare:CC |
9ebbca7d GK |
4026 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4027 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4028 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4029 | (const_int 0))) |
9ebbca7d | 4030 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4031 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 4032 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4033 | "@ |
4034 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4035 | #" | |
4036 | [(set_attr "type" "delayed_compare") | |
4037 | (set_attr "length" "4,8")]) | |
4038 | ||
4039 | (define_split | |
4040 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4041 | (compare:CC | |
4042 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4043 | (match_operand:SI 2 "const_int_operand" "")) | |
4044 | (match_operand:SI 3 "mask_operand" "")) | |
4045 | (const_int 0))) | |
4046 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4047 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4048 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4049 | [(set (match_dup 0) |
4050 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4051 | (set (match_dup 4) | |
4052 | (compare:CC (match_dup 0) | |
4053 | (const_int 0)))] | |
4054 | "") | |
1fd4e8c1 RK |
4055 | |
4056 | (define_insn "" | |
cd2b37d9 | 4057 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4058 | (zero_extend:SI |
4059 | (subreg:QI | |
cd2b37d9 | 4060 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4061 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4062 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4063 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4064 | |
4065 | (define_insn "" | |
9ebbca7d | 4066 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4067 | (compare:CC |
4068 | (zero_extend:SI | |
4069 | (subreg:QI | |
9ebbca7d GK |
4070 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4071 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4072 | (const_int 0))) |
9ebbca7d | 4073 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4074 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4075 | "@ |
4076 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4077 | #" | |
4078 | [(set_attr "type" "delayed_compare") | |
4079 | (set_attr "length" "4,8")]) | |
4080 | ||
4081 | (define_split | |
4082 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4083 | (compare:CC | |
4084 | (zero_extend:SI | |
4085 | (subreg:QI | |
4086 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4087 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4088 | (const_int 0))) | |
4089 | (clobber (match_scratch:SI 3 ""))] | |
4090 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4091 | [(set (match_dup 3) | |
4092 | (zero_extend:SI (subreg:QI | |
4093 | (lshiftrt:SI (match_dup 1) | |
4094 | (match_dup 2)) 0))) | |
4095 | (set (match_dup 0) | |
4096 | (compare:CC (match_dup 3) | |
4097 | (const_int 0)))] | |
4098 | "") | |
1fd4e8c1 RK |
4099 | |
4100 | (define_insn "" | |
9ebbca7d | 4101 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4102 | (compare:CC |
4103 | (zero_extend:SI | |
4104 | (subreg:QI | |
9ebbca7d GK |
4105 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4106 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4107 | (const_int 0))) |
9ebbca7d | 4108 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4109 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4110 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4111 | "@ |
4112 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4113 | #" | |
4114 | [(set_attr "type" "delayed_compare") | |
4115 | (set_attr "length" "4,8")]) | |
4116 | ||
4117 | (define_split | |
4118 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4119 | (compare:CC | |
4120 | (zero_extend:SI | |
4121 | (subreg:QI | |
4122 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4123 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4124 | (const_int 0))) | |
4125 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4126 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4127 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4128 | [(set (match_dup 0) | |
4129 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4130 | (set (match_dup 3) | |
4131 | (compare:CC (match_dup 0) | |
4132 | (const_int 0)))] | |
4133 | "") | |
1fd4e8c1 RK |
4134 | |
4135 | (define_insn "" | |
cd2b37d9 | 4136 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4137 | (zero_extend:SI |
4138 | (subreg:HI | |
cd2b37d9 | 4139 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4140 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4141 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4142 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4143 | |
4144 | (define_insn "" | |
9ebbca7d | 4145 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4146 | (compare:CC |
4147 | (zero_extend:SI | |
4148 | (subreg:HI | |
9ebbca7d GK |
4149 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4150 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4151 | (const_int 0))) |
9ebbca7d | 4152 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4153 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4154 | "@ |
4155 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4156 | #" | |
4157 | [(set_attr "type" "delayed_compare") | |
4158 | (set_attr "length" "4,8")]) | |
4159 | ||
4160 | (define_split | |
4161 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4162 | (compare:CC | |
4163 | (zero_extend:SI | |
4164 | (subreg:HI | |
4165 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4166 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4167 | (const_int 0))) | |
4168 | (clobber (match_scratch:SI 3 ""))] | |
4169 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4170 | [(set (match_dup 3) | |
4171 | (zero_extend:SI (subreg:HI | |
4172 | (lshiftrt:SI (match_dup 1) | |
4173 | (match_dup 2)) 0))) | |
4174 | (set (match_dup 0) | |
4175 | (compare:CC (match_dup 3) | |
4176 | (const_int 0)))] | |
4177 | "") | |
1fd4e8c1 RK |
4178 | |
4179 | (define_insn "" | |
9ebbca7d | 4180 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4181 | (compare:CC |
4182 | (zero_extend:SI | |
4183 | (subreg:HI | |
9ebbca7d GK |
4184 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4185 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4186 | (const_int 0))) |
9ebbca7d | 4187 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4188 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4189 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4190 | "@ |
4191 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4192 | #" | |
4193 | [(set_attr "type" "delayed_compare") | |
4194 | (set_attr "length" "4,8")]) | |
4195 | ||
4196 | (define_split | |
4197 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4198 | (compare:CC | |
4199 | (zero_extend:SI | |
4200 | (subreg:HI | |
4201 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4202 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4203 | (const_int 0))) | |
4204 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4205 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4206 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4207 | [(set (match_dup 0) | |
4208 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4209 | (set (match_dup 3) | |
4210 | (compare:CC (match_dup 0) | |
4211 | (const_int 0)))] | |
4212 | "") | |
1fd4e8c1 RK |
4213 | |
4214 | (define_insn "" | |
cd2b37d9 | 4215 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4216 | (const_int 1) |
cd2b37d9 RK |
4217 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4218 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4219 | (const_int 31)))] |
ca7f5001 | 4220 | "TARGET_POWER" |
1fd4e8c1 RK |
4221 | "rrib %0,%1,%2") |
4222 | ||
4223 | (define_insn "" | |
cd2b37d9 | 4224 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4225 | (const_int 1) |
cd2b37d9 RK |
4226 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4227 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4228 | (const_int 31)))] |
ca7f5001 | 4229 | "TARGET_POWER" |
1fd4e8c1 RK |
4230 | "rrib %0,%1,%2") |
4231 | ||
4232 | (define_insn "" | |
cd2b37d9 | 4233 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4234 | (const_int 1) |
cd2b37d9 RK |
4235 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4236 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4237 | (const_int 1) |
4238 | (const_int 0)))] | |
ca7f5001 | 4239 | "TARGET_POWER" |
1fd4e8c1 RK |
4240 | "rrib %0,%1,%2") |
4241 | ||
ca7f5001 RK |
4242 | (define_expand "ashrsi3" |
4243 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4244 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4245 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4246 | "" | |
4247 | " | |
4248 | { | |
4249 | if (TARGET_POWER) | |
4250 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4251 | else | |
25c341fa | 4252 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4253 | DONE; |
4254 | }") | |
4255 | ||
4256 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4257 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4258 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4259 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4260 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4261 | "TARGET_POWER" |
1fd4e8c1 RK |
4262 | "@ |
4263 | srea %0,%1,%2 | |
ca7f5001 RK |
4264 | {srai|srawi} %0,%1,%h2") |
4265 | ||
25c341fa | 4266 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4267 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4268 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4269 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4270 | "! TARGET_POWER" |
d904e9ed | 4271 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4272 | |
4273 | (define_insn "" | |
9ebbca7d GK |
4274 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4275 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4276 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4277 | (const_int 0))) |
9ebbca7d GK |
4278 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4279 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4280 | "TARGET_POWER" |
1fd4e8c1 RK |
4281 | "@ |
4282 | srea. %3,%1,%2 | |
9ebbca7d GK |
4283 | {srai.|srawi.} %3,%1,%h2 |
4284 | # | |
4285 | #" | |
4286 | [(set_attr "type" "delayed_compare") | |
4287 | (set_attr "length" "4,4,8,8")]) | |
4288 | ||
4289 | (define_split | |
4290 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4291 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4292 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4293 | (const_int 0))) | |
4294 | (clobber (match_scratch:SI 3 "")) | |
4295 | (clobber (match_scratch:SI 4 ""))] | |
4296 | "TARGET_POWER && reload_completed" | |
4297 | [(parallel [(set (match_dup 3) | |
4298 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4299 | (clobber (match_dup 4))]) | |
4300 | (set (match_dup 0) | |
4301 | (compare:CC (match_dup 3) | |
4302 | (const_int 0)))] | |
4303 | "") | |
ca7f5001 RK |
4304 | |
4305 | (define_insn "" | |
9ebbca7d GK |
4306 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4307 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4308 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4309 | (const_int 0))) |
9ebbca7d | 4310 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4311 | "! TARGET_POWER" |
9ebbca7d GK |
4312 | "@ |
4313 | {sra|sraw}%I2. %3,%1,%h2 | |
4314 | #" | |
4315 | [(set_attr "type" "delayed_compare") | |
4316 | (set_attr "length" "4,8")]) | |
4317 | ||
4318 | (define_split | |
4319 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4320 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4321 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4322 | (const_int 0))) | |
4323 | (clobber (match_scratch:SI 3 ""))] | |
4324 | "! TARGET_POWER && reload_completed" | |
4325 | [(set (match_dup 3) | |
4326 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4327 | (set (match_dup 0) | |
4328 | (compare:CC (match_dup 3) | |
4329 | (const_int 0)))] | |
4330 | "") | |
1fd4e8c1 RK |
4331 | |
4332 | (define_insn "" | |
9ebbca7d GK |
4333 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4334 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4335 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4336 | (const_int 0))) |
9ebbca7d | 4337 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4338 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4339 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4340 | "TARGET_POWER" |
1fd4e8c1 RK |
4341 | "@ |
4342 | srea. %0,%1,%2 | |
9ebbca7d GK |
4343 | {srai.|srawi.} %0,%1,%h2 |
4344 | # | |
4345 | #" | |
4346 | [(set_attr "type" "delayed_compare") | |
4347 | (set_attr "length" "4,4,8,8")]) | |
4348 | ||
4349 | (define_split | |
4350 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4351 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4352 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4353 | (const_int 0))) | |
4354 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4355 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4356 | (clobber (match_scratch:SI 4 ""))] | |
4357 | "TARGET_POWER && reload_completed" | |
4358 | [(parallel [(set (match_dup 0) | |
4359 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4360 | (clobber (match_dup 4))]) | |
4361 | (set (match_dup 3) | |
4362 | (compare:CC (match_dup 0) | |
4363 | (const_int 0)))] | |
4364 | "") | |
1fd4e8c1 | 4365 | |
ca7f5001 | 4366 | (define_insn "" |
9ebbca7d GK |
4367 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4368 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4369 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4370 | (const_int 0))) |
9ebbca7d | 4371 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4372 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4373 | "! TARGET_POWER" |
9ebbca7d GK |
4374 | "@ |
4375 | {sra|sraw}%I2. %0,%1,%h2 | |
4376 | #" | |
4377 | [(set_attr "type" "delayed_compare") | |
4378 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4379 | \f |
9ebbca7d GK |
4380 | (define_split |
4381 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4382 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4383 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4384 | (const_int 0))) | |
4385 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4386 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4387 | "! TARGET_POWER && reload_completed" | |
4388 | [(set (match_dup 0) | |
4389 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4390 | (set (match_dup 3) | |
4391 | (compare:CC (match_dup 0) | |
4392 | (const_int 0)))] | |
4393 | "") | |
4394 | ||
1fd4e8c1 RK |
4395 | ;; Floating-point insns, excluding normal data motion. |
4396 | ;; | |
ca7f5001 RK |
4397 | ;; PowerPC has a full set of single-precision floating point instructions. |
4398 | ;; | |
4399 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4400 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4401 | ;; The only conversions we will do will be when storing to memory. In that | |
4402 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4403 | ;; |
4404 | ;; Note that when we store into a single-precision memory location, we need to | |
4405 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4406 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4407 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4408 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4409 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4410 | ||
99176a91 AH |
4411 | (define_expand "extendsfdf2" |
4412 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4413 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4414 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4415 | "") | |
4416 | ||
4417 | (define_insn_and_split "*extendsfdf2_fpr" | |
11ac38b2 DE |
4418 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") |
4419 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))] | |
a3170dc6 | 4420 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
11ac38b2 DE |
4421 | "@ |
4422 | # | |
4423 | fmr %0,%1" | |
4424 | "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" | |
4425 | [(const_int 0)] | |
5c30aff8 | 4426 | { |
11ac38b2 DE |
4427 | emit_note (NOTE_INSN_DELETED); |
4428 | DONE; | |
4429 | } | |
e8112008 | 4430 | [(set_attr "type" "fp")]) |
1fd4e8c1 | 4431 | |
7a2f7870 AH |
4432 | (define_expand "truncdfsf2" |
4433 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4434 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4435 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4436 | "") | |
4437 | ||
99176a91 | 4438 | (define_insn "*truncdfsf2_fpr" |
cd2b37d9 RK |
4439 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4440 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4441 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 4442 | "frsp %0,%1" |
1fd4e8c1 RK |
4443 | [(set_attr "type" "fp")]) |
4444 | ||
455350f4 RK |
4445 | (define_insn "aux_truncdfsf2" |
4446 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
615158e2 | 4447 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] |
a3170dc6 | 4448 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
4449 | "frsp %0,%1" |
4450 | [(set_attr "type" "fp")]) | |
4451 | ||
a3170dc6 AH |
4452 | (define_expand "negsf2" |
4453 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4454 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4455 | "TARGET_HARD_FLOAT" | |
4456 | "") | |
4457 | ||
4458 | (define_insn "*negsf2" | |
cd2b37d9 RK |
4459 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4460 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4461 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4462 | "fneg %0,%1" |
4463 | [(set_attr "type" "fp")]) | |
4464 | ||
a3170dc6 AH |
4465 | (define_expand "abssf2" |
4466 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4467 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4468 | "TARGET_HARD_FLOAT" | |
4469 | "") | |
4470 | ||
4471 | (define_insn "*abssf2" | |
cd2b37d9 RK |
4472 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4473 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4474 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4475 | "fabs %0,%1" |
4476 | [(set_attr "type" "fp")]) | |
4477 | ||
4478 | (define_insn "" | |
cd2b37d9 RK |
4479 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4480 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4481 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4482 | "fnabs %0,%1" |
4483 | [(set_attr "type" "fp")]) | |
4484 | ||
ca7f5001 RK |
4485 | (define_expand "addsf3" |
4486 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4487 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4488 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4489 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4490 | "") |
4491 | ||
4492 | (define_insn "" | |
cd2b37d9 RK |
4493 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4494 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4495 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4496 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4497 | "fadds %0,%1,%2" |
ca7f5001 RK |
4498 | [(set_attr "type" "fp")]) |
4499 | ||
4500 | (define_insn "" | |
4501 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4502 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4503 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4504 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4505 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4506 | [(set_attr "type" "fp")]) |
4507 | ||
4508 | (define_expand "subsf3" | |
4509 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4510 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4511 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4512 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4513 | "") |
4514 | ||
4515 | (define_insn "" | |
4516 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4517 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4518 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4519 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4520 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4521 | [(set_attr "type" "fp")]) |
4522 | ||
ca7f5001 | 4523 | (define_insn "" |
cd2b37d9 RK |
4524 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4525 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4526 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4527 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4528 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4529 | [(set_attr "type" "fp")]) |
4530 | ||
4531 | (define_expand "mulsf3" | |
4532 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4533 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4534 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4535 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4536 | "") |
4537 | ||
4538 | (define_insn "" | |
4539 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4540 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4541 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4542 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4543 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4544 | [(set_attr "type" "fp")]) |
4545 | ||
ca7f5001 | 4546 | (define_insn "" |
cd2b37d9 RK |
4547 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4548 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4549 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4550 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4551 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4552 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4553 | |
ca7f5001 RK |
4554 | (define_expand "divsf3" |
4555 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4556 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4557 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4558 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4559 | "") |
4560 | ||
4561 | (define_insn "" | |
cd2b37d9 RK |
4562 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4563 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4564 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4565 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4566 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4567 | [(set_attr "type" "sdiv")]) |
4568 | ||
4569 | (define_insn "" | |
4570 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4571 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4572 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4573 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4574 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4575 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4576 | |
4577 | (define_insn "" | |
cd2b37d9 RK |
4578 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4579 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4580 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4581 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4582 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4583 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4584 | [(set_attr "type" "fp")]) |
4585 | ||
4586 | (define_insn "" | |
4587 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4588 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4589 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4590 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4591 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4592 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4593 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4594 | |
4595 | (define_insn "" | |
cd2b37d9 RK |
4596 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4597 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4598 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4599 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4600 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4601 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4602 | [(set_attr "type" "fp")]) |
4603 | ||
4604 | (define_insn "" | |
4605 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4606 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4607 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4608 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4609 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4610 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4611 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4612 | |
4613 | (define_insn "" | |
cd2b37d9 RK |
4614 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4615 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4616 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4617 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4618 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4619 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4620 | "fnmadds %0,%1,%2,%3" | |
4621 | [(set_attr "type" "fp")]) | |
4622 | ||
4623 | (define_insn "" | |
4624 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4625 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4626 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4627 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4628 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4629 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4630 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4631 | [(set_attr "type" "fp")]) |
4632 | ||
4633 | (define_insn "" | |
4634 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4635 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4636 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4637 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4638 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4639 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4640 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4641 | |
16823694 GK |
4642 | (define_insn "" |
4643 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4644 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4645 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4646 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4647 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4648 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4649 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4650 | [(set_attr "type" "dmul")]) | |
4651 | ||
1fd4e8c1 | 4652 | (define_insn "" |
cd2b37d9 RK |
4653 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4654 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4655 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4656 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4657 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4658 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4659 | "fnmsubs %0,%1,%2,%3" | |
4660 | [(set_attr "type" "fp")]) | |
4661 | ||
4662 | (define_insn "" | |
4663 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4664 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4665 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4666 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4667 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4668 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4669 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4670 | [(set_attr "type" "fp")]) |
4671 | ||
4672 | (define_insn "" | |
4673 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4674 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4675 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4676 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4677 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4678 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4679 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4680 | |
16823694 GK |
4681 | (define_insn "" |
4682 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4683 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4684 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4685 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4686 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4687 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4688 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4689 | [(set_attr "type" "fp")]) | |
4690 | ||
ca7f5001 RK |
4691 | (define_expand "sqrtsf2" |
4692 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4693 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 4694 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4695 | "") |
4696 | ||
4697 | (define_insn "" | |
4698 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4699 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4700 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4701 | "fsqrts %0,%1" |
4702 | [(set_attr "type" "ssqrt")]) | |
4703 | ||
4704 | (define_insn "" | |
4705 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4706 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4707 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4708 | "fsqrt %0,%1" |
4709 | [(set_attr "type" "dsqrt")]) | |
4710 | ||
0530bc70 AP |
4711 | (define_expand "copysignsf3" |
4712 | [(set (match_dup 3) | |
4713 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" ""))) | |
4714 | (set (match_dup 4) | |
4715 | (neg:SF (abs:SF (match_dup 1)))) | |
4716 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
4717 | (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "") | |
4718 | (match_dup 5)) | |
4719 | (match_dup 3) | |
4720 | (match_dup 4)))] | |
4721 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS | |
4722 | && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)" | |
4723 | { | |
4724 | operands[3] = gen_reg_rtx (SFmode); | |
4725 | operands[4] = gen_reg_rtx (SFmode); | |
4726 | operands[5] = CONST0_RTX (SFmode); | |
4727 | }) | |
4728 | ||
4729 | (define_expand "copysigndf3" | |
4730 | [(set (match_dup 3) | |
4731 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" ""))) | |
4732 | (set (match_dup 4) | |
4733 | (neg:DF (abs:DF (match_dup 1)))) | |
4734 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
4735 | (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "") | |
4736 | (match_dup 5)) | |
4737 | (match_dup 3) | |
4738 | (match_dup 4)))] | |
4739 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS | |
4740 | && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)" | |
4741 | { | |
4742 | operands[3] = gen_reg_rtx (DFmode); | |
4743 | operands[4] = gen_reg_rtx (DFmode); | |
4744 | operands[5] = CONST0_RTX (DFmode); | |
4745 | }) | |
4746 | ||
94d7001a RK |
4747 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4748 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4749 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 | 4750 | ;; combine. |
7ae4d8d4 | 4751 | (define_expand "smaxsf3" |
8e871c05 | 4752 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4753 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4754 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4755 | (match_dup 1) |
4756 | (match_dup 2)))] | |
89e73849 | 4757 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4758 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 4759 | |
7ae4d8d4 | 4760 | (define_expand "sminsf3" |
50a0b056 GK |
4761 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4762 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4763 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4764 | (match_dup 2) | |
4765 | (match_dup 1)))] | |
89e73849 | 4766 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4767 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4768 | |
8e871c05 RK |
4769 | (define_split |
4770 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4771 | (match_operator:SF 3 "min_max_operator" |
4772 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4773 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 4774 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
4775 | [(const_int 0)] |
4776 | " | |
6ae08853 | 4777 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
4778 | operands[1], operands[2]); |
4779 | DONE; | |
4780 | }") | |
2f607b94 | 4781 | |
a3170dc6 AH |
4782 | (define_expand "movsicc" |
4783 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4784 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
4785 | (match_operand:SI 2 "gpc_reg_operand" "") | |
4786 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
4787 | "TARGET_ISEL" | |
4788 | " | |
4789 | { | |
4790 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
4791 | DONE; | |
4792 | else | |
4793 | FAIL; | |
4794 | }") | |
4795 | ||
4796 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
4797 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
4798 | ;; because we may switch the operands and rB may end up being rA. | |
4799 | ;; | |
4800 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
4801 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
4802 | ;; change the mode underneath our feet and then gets confused trying | |
4803 | ;; to reload the value. | |
4804 | (define_insn "isel_signed" | |
4805 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4806 | (if_then_else:SI | |
4807 | (match_operator 1 "comparison_operator" | |
4808 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
4809 | (const_int 0)]) | |
4810 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4811 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4812 | "TARGET_ISEL" | |
4813 | "* | |
4814 | { return output_isel (operands); }" | |
4815 | [(set_attr "length" "4")]) | |
4816 | ||
4817 | (define_insn "isel_unsigned" | |
4818 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4819 | (if_then_else:SI | |
4820 | (match_operator 1 "comparison_operator" | |
4821 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
4822 | (const_int 0)]) | |
4823 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4824 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4825 | "TARGET_ISEL" | |
4826 | "* | |
4827 | { return output_isel (operands); }" | |
4828 | [(set_attr "length" "4")]) | |
4829 | ||
94d7001a | 4830 | (define_expand "movsfcc" |
0ad91047 | 4831 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4832 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4833 | (match_operand:SF 2 "gpc_reg_operand" "") |
4834 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4835 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4836 | " |
4837 | { | |
50a0b056 GK |
4838 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4839 | DONE; | |
94d7001a | 4840 | else |
50a0b056 | 4841 | FAIL; |
94d7001a | 4842 | }") |
d56d506a | 4843 | |
50a0b056 | 4844 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4845 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4846 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4847 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4848 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4849 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4850 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4851 | "fsel %0,%1,%2,%3" |
4852 | [(set_attr "type" "fp")]) | |
2f607b94 | 4853 | |
50a0b056 | 4854 | (define_insn "*fseldfsf4" |
94d7001a RK |
4855 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4856 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4857 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4858 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4859 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4860 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4861 | "fsel %0,%1,%2,%3" |
4862 | [(set_attr "type" "fp")]) | |
d56d506a | 4863 | |
7a2f7870 AH |
4864 | (define_expand "negdf2" |
4865 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4866 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4867 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4868 | "") | |
4869 | ||
99176a91 | 4870 | (define_insn "*negdf2_fpr" |
cd2b37d9 RK |
4871 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4872 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4873 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4874 | "fneg %0,%1" |
4875 | [(set_attr "type" "fp")]) | |
4876 | ||
7a2f7870 AH |
4877 | (define_expand "absdf2" |
4878 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4879 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4880 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4881 | "") | |
4882 | ||
99176a91 | 4883 | (define_insn "*absdf2_fpr" |
cd2b37d9 RK |
4884 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4885 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4886 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4887 | "fabs %0,%1" |
4888 | [(set_attr "type" "fp")]) | |
4889 | ||
99176a91 | 4890 | (define_insn "*nabsdf2_fpr" |
cd2b37d9 RK |
4891 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4892 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4893 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4894 | "fnabs %0,%1" |
4895 | [(set_attr "type" "fp")]) | |
4896 | ||
7a2f7870 AH |
4897 | (define_expand "adddf3" |
4898 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4899 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4900 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4901 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4902 | "") | |
4903 | ||
99176a91 | 4904 | (define_insn "*adddf3_fpr" |
cd2b37d9 RK |
4905 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4906 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4907 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4908 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4909 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4910 | [(set_attr "type" "fp")]) |
4911 | ||
7a2f7870 AH |
4912 | (define_expand "subdf3" |
4913 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4914 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4915 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4916 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4917 | "") | |
4918 | ||
99176a91 | 4919 | (define_insn "*subdf3_fpr" |
cd2b37d9 RK |
4920 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4921 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4922 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4923 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4924 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4925 | [(set_attr "type" "fp")]) |
4926 | ||
7a2f7870 AH |
4927 | (define_expand "muldf3" |
4928 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4929 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4930 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4931 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4932 | "") | |
4933 | ||
99176a91 | 4934 | (define_insn "*muldf3_fpr" |
cd2b37d9 RK |
4935 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4936 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4937 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4938 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4939 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4940 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4941 | |
7a2f7870 AH |
4942 | (define_expand "divdf3" |
4943 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4944 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4945 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4946 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4947 | "") | |
4948 | ||
99176a91 | 4949 | (define_insn "*divdf3_fpr" |
cd2b37d9 RK |
4950 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4951 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4952 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4953 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4954 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4955 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4956 | |
4957 | (define_insn "" | |
cd2b37d9 RK |
4958 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4959 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4960 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4961 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4962 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4963 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4964 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4965 | |
4966 | (define_insn "" | |
cd2b37d9 RK |
4967 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4968 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4969 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4970 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4971 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4972 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4973 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4974 | |
4975 | (define_insn "" | |
cd2b37d9 RK |
4976 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4977 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4978 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4979 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4980 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4981 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4982 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4983 | [(set_attr "type" "dmul")]) | |
4984 | ||
4985 | (define_insn "" | |
4986 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4987 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
4988 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4989 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4990 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4991 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 4992 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 4993 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4994 | |
4995 | (define_insn "" | |
cd2b37d9 RK |
4996 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4997 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4998 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4999 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
5000 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
5001 | && HONOR_SIGNED_ZEROS (DFmode)" | |
5002 | "{fnms|fnmsub} %0,%1,%2,%3" | |
5003 | [(set_attr "type" "dmul")]) | |
5004 | ||
5005 | (define_insn "" | |
5006 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5007 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
5008 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5009 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
6ae08853 | 5010 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
16823694 | 5011 | && ! HONOR_SIGNED_ZEROS (DFmode)" |
ca7f5001 | 5012 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5013 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5014 | |
5015 | (define_insn "sqrtdf2" | |
5016 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5017 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5018 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
5019 | "fsqrt %0,%1" |
5020 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5021 | |
50a0b056 | 5022 | ;; The conditional move instructions allow us to perform max and min |
6ae08853 | 5023 | ;; operations even when |
b77dfefc | 5024 | |
7ae4d8d4 | 5025 | (define_expand "smaxdf3" |
8e871c05 | 5026 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5027 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
5028 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5029 | (match_dup 1) |
5030 | (match_dup 2)))] | |
89e73849 | 5031 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5032 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 5033 | |
7ae4d8d4 | 5034 | (define_expand "smindf3" |
50a0b056 GK |
5035 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5036 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
5037 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
5038 | (match_dup 2) | |
5039 | (match_dup 1)))] | |
89e73849 | 5040 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5041 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5042 | |
8e871c05 RK |
5043 | (define_split |
5044 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5045 | (match_operator:DF 3 "min_max_operator" |
5046 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5047 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 5048 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
5049 | [(const_int 0)] |
5050 | " | |
6ae08853 | 5051 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
5052 | operands[1], operands[2]); |
5053 | DONE; | |
5054 | }") | |
b77dfefc | 5055 | |
94d7001a | 5056 | (define_expand "movdfcc" |
0ad91047 | 5057 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5058 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5059 | (match_operand:DF 2 "gpc_reg_operand" "") |
5060 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 5061 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
5062 | " |
5063 | { | |
50a0b056 GK |
5064 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5065 | DONE; | |
94d7001a | 5066 | else |
50a0b056 | 5067 | FAIL; |
94d7001a | 5068 | }") |
d56d506a | 5069 | |
50a0b056 | 5070 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5071 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5072 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5073 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5074 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5075 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5076 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
5077 | "fsel %0,%1,%2,%3" |
5078 | [(set_attr "type" "fp")]) | |
d56d506a | 5079 | |
50a0b056 | 5080 | (define_insn "*fselsfdf4" |
94d7001a RK |
5081 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5082 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5083 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5084 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5085 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5086 | "TARGET_PPC_GFXOPT" | |
5087 | "fsel %0,%1,%2,%3" | |
5088 | [(set_attr "type" "fp")]) | |
1fd4e8c1 | 5089 | \f |
d095928f AH |
5090 | ;; Conversions to and from floating-point. |
5091 | ||
5092 | (define_expand "fixuns_truncsfsi2" | |
5093 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5094 | (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5095 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5096 | "") | |
5097 | ||
5098 | (define_expand "fix_truncsfsi2" | |
5099 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5100 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5101 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5102 | "") | |
5103 | ||
9ebbca7d GK |
5104 | ; For each of these conversions, there is a define_expand, a define_insn |
5105 | ; with a '#' template, and a define_split (with C code). The idea is | |
5106 | ; to allow constant folding with the template of the define_insn, | |
5107 | ; then to have the insns split later (between sched1 and final). | |
5108 | ||
1fd4e8c1 | 5109 | (define_expand "floatsidf2" |
802a0058 MM |
5110 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5111 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5112 | (use (match_dup 2)) | |
5113 | (use (match_dup 3)) | |
208c89ce | 5114 | (clobber (match_dup 4)) |
a7df97e6 | 5115 | (clobber (match_dup 5)) |
9ebbca7d | 5116 | (clobber (match_dup 6))])] |
a3170dc6 | 5117 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5118 | " |
5119 | { | |
99176a91 AH |
5120 | if (TARGET_E500_DOUBLE) |
5121 | { | |
5122 | emit_insn (gen_spe_floatsidf2 (operands[0], operands[1])); | |
5123 | DONE; | |
5124 | } | |
05d49501 AM |
5125 | if (TARGET_POWERPC64) |
5126 | { | |
5127 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5128 | rtx t1 = gen_reg_rtx (DImode); | |
5129 | rtx t2 = gen_reg_rtx (DImode); | |
5130 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
5131 | DONE; | |
5132 | } | |
5133 | ||
802a0058 | 5134 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5135 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5136 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5137 | operands[5] = gen_reg_rtx (DFmode); | |
5138 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5139 | }") |
5140 | ||
802a0058 MM |
5141 | (define_insn "*floatsidf2_internal" |
5142 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5143 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5144 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5145 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5146 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5147 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5148 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5149 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5150 | "#" |
a7df97e6 | 5151 | [(set_attr "length" "24")]) |
802a0058 MM |
5152 | |
5153 | (define_split | |
dbe3df29 | 5154 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5155 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5156 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5157 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5158 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5159 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5160 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
a3170dc6 | 5161 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5162 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5163 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5164 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5165 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5166 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5167 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5168 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5169 | " |
5170 | { | |
9ebbca7d GK |
5171 | rtx lowword, highword; |
5172 | if (GET_CODE (operands[4]) != MEM) | |
5173 | abort(); | |
5174 | highword = XEXP (operands[4], 0); | |
5175 | lowword = plus_constant (highword, 4); | |
5176 | if (! WORDS_BIG_ENDIAN) | |
5177 | { | |
5178 | rtx tmp; | |
5179 | tmp = highword; highword = lowword; lowword = tmp; | |
5180 | } | |
5181 | ||
6ae08853 | 5182 | emit_insn (gen_xorsi3 (operands[6], operands[1], |
9ebbca7d GK |
5183 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); |
5184 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5185 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5186 | emit_move_insn (operands[5], operands[4]); | |
5187 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5188 | DONE; | |
208c89ce | 5189 | }") |
802a0058 | 5190 | |
a3170dc6 AH |
5191 | (define_expand "floatunssisf2" |
5192 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5193 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5194 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5195 | "") | |
5196 | ||
802a0058 MM |
5197 | (define_expand "floatunssidf2" |
5198 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5199 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5200 | (use (match_dup 2)) | |
5201 | (use (match_dup 3)) | |
a7df97e6 | 5202 | (clobber (match_dup 4)) |
9ebbca7d | 5203 | (clobber (match_dup 5))])] |
99176a91 | 5204 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
1fd4e8c1 RK |
5205 | " |
5206 | { | |
99176a91 AH |
5207 | if (TARGET_E500_DOUBLE) |
5208 | { | |
5209 | emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1])); | |
5210 | DONE; | |
5211 | } | |
05d49501 AM |
5212 | if (TARGET_POWERPC64) |
5213 | { | |
5214 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5215 | rtx t1 = gen_reg_rtx (DImode); | |
5216 | rtx t2 = gen_reg_rtx (DImode); | |
5217 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5218 | t1, t2)); | |
5219 | DONE; | |
5220 | } | |
5221 | ||
802a0058 | 5222 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5223 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5224 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5225 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5226 | }") |
5227 | ||
802a0058 MM |
5228 | (define_insn "*floatunssidf2_internal" |
5229 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5230 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5231 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5232 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5233 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5234 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5235 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5236 | "#" |
a7df97e6 | 5237 | [(set_attr "length" "20")]) |
802a0058 MM |
5238 | |
5239 | (define_split | |
5240 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5241 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5242 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5243 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5244 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5245 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
a3170dc6 | 5246 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5247 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5248 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5249 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5250 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5251 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5252 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5253 | " | |
802a0058 | 5254 | { |
9ebbca7d GK |
5255 | rtx lowword, highword; |
5256 | if (GET_CODE (operands[4]) != MEM) | |
5257 | abort(); | |
5258 | highword = XEXP (operands[4], 0); | |
5259 | lowword = plus_constant (highword, 4); | |
5260 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5261 | { |
9ebbca7d GK |
5262 | rtx tmp; |
5263 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5264 | } |
802a0058 | 5265 | |
9ebbca7d GK |
5266 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5267 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5268 | emit_move_insn (operands[5], operands[4]); | |
5269 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5270 | DONE; | |
5271 | }") | |
1fd4e8c1 | 5272 | |
1fd4e8c1 | 5273 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5274 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5275 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5276 | (clobber (match_dup 2)) | |
9ebbca7d | 5277 | (clobber (match_dup 3))])] |
99176a91 AH |
5278 | "(TARGET_POWER2 || TARGET_POWERPC) |
5279 | && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
1fd4e8c1 RK |
5280 | " |
5281 | { | |
99176a91 AH |
5282 | if (TARGET_E500_DOUBLE) |
5283 | { | |
5284 | emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1])); | |
5285 | DONE; | |
5286 | } | |
802a0058 | 5287 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5288 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5289 | }") |
5290 | ||
802a0058 MM |
5291 | (define_insn "*fix_truncdfsi2_internal" |
5292 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5293 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5294 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5295 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5296 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5297 | "#" |
9ebbca7d | 5298 | [(set_attr "length" "16")]) |
802a0058 MM |
5299 | |
5300 | (define_split | |
5301 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5302 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5303 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5304 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
a3170dc6 | 5305 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d | 5306 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5307 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5308 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5309 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5310 | " | |
802a0058 | 5311 | { |
9ebbca7d GK |
5312 | rtx lowword; |
5313 | if (GET_CODE (operands[3]) != MEM) | |
5314 | abort(); | |
5315 | lowword = XEXP (operands[3], 0); | |
5316 | if (WORDS_BIG_ENDIAN) | |
5317 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5318 | |
9ebbca7d GK |
5319 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5320 | emit_move_insn (operands[3], operands[2]); | |
5321 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5322 | DONE; | |
5323 | }") | |
802a0058 | 5324 | |
615158e2 | 5325 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) |
9ebbca7d GK |
5326 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) |
5327 | ; because the first makes it clear that operand 0 is not live | |
5328 | ; before the instruction. | |
5329 | (define_insn "fctiwz" | |
61c07d3c | 5330 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
615158e2 JJ |
5331 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] |
5332 | UNSPEC_FCTIWZ))] | |
a3170dc6 | 5333 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5334 | "{fcirz|fctiwz} %0,%1" |
5335 | [(set_attr "type" "fp")]) | |
5336 | ||
a3170dc6 AH |
5337 | (define_expand "floatsisf2" |
5338 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5339 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5340 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5341 | "") | |
5342 | ||
a473029f RK |
5343 | (define_insn "floatdidf2" |
5344 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5345 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5346 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5347 | "fcfid %0,%1" |
5348 | [(set_attr "type" "fp")]) | |
5349 | ||
05d49501 AM |
5350 | (define_insn_and_split "floatsidf_ppc64" |
5351 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5352 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5353 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5354 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5355 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5356 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5357 | "#" |
ecb62ae7 | 5358 | "&& 1" |
05d49501 AM |
5359 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) |
5360 | (set (match_dup 2) (match_dup 3)) | |
5361 | (set (match_dup 4) (match_dup 2)) | |
5362 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5363 | "") | |
5364 | ||
5365 | (define_insn_and_split "floatunssidf_ppc64" | |
5366 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5367 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5368 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5369 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5370 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5371 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5372 | "#" |
ecb62ae7 | 5373 | "&& 1" |
05d49501 AM |
5374 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) |
5375 | (set (match_dup 2) (match_dup 3)) | |
5376 | (set (match_dup 4) (match_dup 2)) | |
5377 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5378 | "") | |
5379 | ||
a473029f | 5380 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5381 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5382 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5383 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5384 | "fctidz %0,%1" |
5385 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5386 | |
678b7733 AM |
5387 | (define_expand "floatdisf2" |
5388 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5389 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
994cf173 | 5390 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5391 | " |
5392 | { | |
994cf173 | 5393 | rtx val = operands[1]; |
678b7733 AM |
5394 | if (!flag_unsafe_math_optimizations) |
5395 | { | |
5396 | rtx label = gen_label_rtx (); | |
994cf173 AM |
5397 | val = gen_reg_rtx (DImode); |
5398 | emit_insn (gen_floatdisf2_internal2 (val, operands[1], label)); | |
678b7733 AM |
5399 | emit_label (label); |
5400 | } | |
994cf173 | 5401 | emit_insn (gen_floatdisf2_internal1 (operands[0], val)); |
678b7733 AM |
5402 | DONE; |
5403 | }") | |
5404 | ||
5405 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
5406 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
5407 | ;; from double rounding. | |
5408 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 5409 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 5410 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 5411 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 5412 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
5413 | "#" |
5414 | "&& reload_completed" | |
5415 | [(set (match_dup 2) | |
5416 | (float:DF (match_dup 1))) | |
5417 | (set (match_dup 0) | |
5418 | (float_truncate:SF (match_dup 2)))] | |
5419 | "") | |
678b7733 AM |
5420 | |
5421 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 5422 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
5423 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
5424 | ;; rounding position. | |
5425 | (define_expand "floatdisf2_internal2" | |
994cf173 AM |
5426 | [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") |
5427 | (const_int 53))) | |
5428 | (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1) | |
5429 | (const_int 2047))) | |
5430 | (clobber (scratch:CC))]) | |
5431 | (set (match_dup 3) (plus:DI (match_dup 3) | |
5432 | (const_int 1))) | |
5433 | (set (match_dup 0) (plus:DI (match_dup 0) | |
5434 | (const_int 2047))) | |
5435 | (set (match_dup 4) (compare:CCUNS (match_dup 3) | |
5436 | (const_int 3))) | |
5437 | (set (match_dup 0) (ior:DI (match_dup 0) | |
5438 | (match_dup 1))) | |
5439 | (parallel [(set (match_dup 0) (and:DI (match_dup 0) | |
5440 | (const_int -2048))) | |
5441 | (clobber (scratch:CC))]) | |
5442 | (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) | |
5443 | (label_ref (match_operand:DI 2 "" "")) | |
678b7733 | 5444 | (pc))) |
994cf173 AM |
5445 | (set (match_dup 0) (match_dup 1))] |
5446 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
678b7733 AM |
5447 | " |
5448 | { | |
678b7733 | 5449 | operands[3] = gen_reg_rtx (DImode); |
994cf173 | 5450 | operands[4] = gen_reg_rtx (CCUNSmode); |
678b7733 | 5451 | }") |
1fd4e8c1 RK |
5452 | \f |
5453 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5454 | ;; of instructions. The & constraints are to prevent the register |
5455 | ;; allocator from allocating registers that overlap with the inputs | |
5456 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5457 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5458 | |
266eb58a | 5459 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5460 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5461 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5462 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5463 | "! TARGET_POWERPC64" |
0f645302 MM |
5464 | "* |
5465 | { | |
5466 | if (WORDS_BIG_ENDIAN) | |
5467 | return (GET_CODE (operands[2])) != CONST_INT | |
5468 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5469 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5470 | else | |
5471 | return (GET_CODE (operands[2])) != CONST_INT | |
5472 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5473 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5474 | }" | |
943c15ed DE |
5475 | [(set_attr "type" "two") |
5476 | (set_attr "length" "8")]) | |
1fd4e8c1 | 5477 | |
266eb58a | 5478 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5479 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5480 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5481 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5482 | "! TARGET_POWERPC64" |
5502823b RK |
5483 | "* |
5484 | { | |
0f645302 MM |
5485 | if (WORDS_BIG_ENDIAN) |
5486 | return (GET_CODE (operands[1]) != CONST_INT) | |
5487 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5488 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5489 | else | |
5490 | return (GET_CODE (operands[1]) != CONST_INT) | |
5491 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5492 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5493 | }" |
943c15ed DE |
5494 | [(set_attr "type" "two") |
5495 | (set_attr "length" "8")]) | |
ca7f5001 | 5496 | |
266eb58a | 5497 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5498 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5499 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5500 | "! TARGET_POWERPC64" |
5502823b RK |
5501 | "* |
5502 | { | |
5503 | return (WORDS_BIG_ENDIAN) | |
5504 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5505 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5506 | }" | |
943c15ed DE |
5507 | [(set_attr "type" "two") |
5508 | (set_attr "length" "8")]) | |
ca7f5001 | 5509 | |
8ffd9c51 RK |
5510 | (define_expand "mulsidi3" |
5511 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5512 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5513 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5514 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5515 | " |
5516 | { | |
5517 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5518 | { | |
39403d82 DE |
5519 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5520 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5521 | emit_insn (gen_mull_call ()); |
cf27b467 | 5522 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5523 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5524 | else |
5525 | { | |
5526 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5527 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5528 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5529 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5530 | } |
8ffd9c51 RK |
5531 | DONE; |
5532 | } | |
5533 | else if (TARGET_POWER) | |
5534 | { | |
5535 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5536 | DONE; | |
5537 | } | |
5538 | }") | |
deb9225a | 5539 | |
8ffd9c51 | 5540 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5541 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5542 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5543 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5544 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5545 | "TARGET_POWER" |
b19003d8 | 5546 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5547 | [(set_attr "type" "imul") |
5548 | (set_attr "length" "8")]) | |
deb9225a | 5549 | |
f192bf8b | 5550 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5551 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5552 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5553 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5554 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5555 | "* |
5556 | { | |
5557 | return (WORDS_BIG_ENDIAN) | |
5558 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5559 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5560 | }" | |
8ffd9c51 RK |
5561 | [(set_attr "type" "imul") |
5562 | (set_attr "length" "8")]) | |
deb9225a | 5563 | |
ebedb4dd MM |
5564 | (define_split |
5565 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5566 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5567 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5568 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5569 | [(set (match_dup 3) |
5570 | (truncate:SI | |
5571 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5572 | (sign_extend:DI (match_dup 2))) | |
5573 | (const_int 32)))) | |
5574 | (set (match_dup 4) | |
5575 | (mult:SI (match_dup 1) | |
5576 | (match_dup 2)))] | |
5577 | " | |
5578 | { | |
5579 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5580 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5581 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5582 | }") | |
5583 | ||
f192bf8b DE |
5584 | (define_expand "umulsidi3" |
5585 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5586 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5587 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5588 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5589 | " | |
5590 | { | |
5591 | if (TARGET_POWER) | |
5592 | { | |
5593 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5594 | DONE; | |
5595 | } | |
5596 | }") | |
5597 | ||
5598 | (define_insn "umulsidi3_mq" | |
5599 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5600 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5601 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5602 | (clobber (match_scratch:SI 3 "=q"))] | |
5603 | "TARGET_POWERPC && TARGET_POWER" | |
5604 | "* | |
5605 | { | |
5606 | return (WORDS_BIG_ENDIAN) | |
5607 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5608 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5609 | }" | |
5610 | [(set_attr "type" "imul") | |
5611 | (set_attr "length" "8")]) | |
5612 | ||
5613 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5614 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5615 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5616 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5617 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5618 | "* |
5619 | { | |
5620 | return (WORDS_BIG_ENDIAN) | |
5621 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5622 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5623 | }" | |
5624 | [(set_attr "type" "imul") | |
5625 | (set_attr "length" "8")]) | |
5626 | ||
ebedb4dd MM |
5627 | (define_split |
5628 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5629 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5630 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5631 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5632 | [(set (match_dup 3) |
5633 | (truncate:SI | |
5634 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5635 | (zero_extend:DI (match_dup 2))) | |
5636 | (const_int 32)))) | |
5637 | (set (match_dup 4) | |
5638 | (mult:SI (match_dup 1) | |
5639 | (match_dup 2)))] | |
5640 | " | |
5641 | { | |
5642 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5643 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5644 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5645 | }") | |
5646 | ||
8ffd9c51 RK |
5647 | (define_expand "smulsi3_highpart" |
5648 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5649 | (truncate:SI | |
5650 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5651 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5652 | (sign_extend:DI | |
5653 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5654 | (const_int 32))))] | |
5655 | "" | |
5656 | " | |
5657 | { | |
5658 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5659 | { | |
39403d82 DE |
5660 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5661 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5662 | emit_insn (gen_mulh_call ()); |
39403d82 | 5663 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5664 | DONE; |
5665 | } | |
5666 | else if (TARGET_POWER) | |
5667 | { | |
5668 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5669 | DONE; | |
5670 | } | |
5671 | }") | |
deb9225a | 5672 | |
8ffd9c51 RK |
5673 | (define_insn "smulsi3_highpart_mq" |
5674 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5675 | (truncate:SI | |
fada905b MM |
5676 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5677 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5678 | (sign_extend:DI | |
5679 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5680 | (const_int 32)))) |
5681 | (clobber (match_scratch:SI 3 "=q"))] | |
5682 | "TARGET_POWER" | |
5683 | "mul %0,%1,%2" | |
5684 | [(set_attr "type" "imul")]) | |
deb9225a | 5685 | |
f192bf8b | 5686 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5687 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5688 | (truncate:SI | |
fada905b MM |
5689 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5690 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5691 | (sign_extend:DI | |
5692 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5693 | (const_int 32))))] |
f192bf8b | 5694 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5695 | "mulhw %0,%1,%2" |
5696 | [(set_attr "type" "imul")]) | |
deb9225a | 5697 | |
f192bf8b DE |
5698 | (define_expand "umulsi3_highpart" |
5699 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5700 | (truncate:SI | |
5701 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5702 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5703 | (zero_extend:DI | |
5704 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5705 | (const_int 32))))] | |
5706 | "TARGET_POWERPC" | |
5707 | " | |
5708 | { | |
5709 | if (TARGET_POWER) | |
5710 | { | |
5711 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5712 | DONE; | |
5713 | } | |
5714 | }") | |
5715 | ||
5716 | (define_insn "umulsi3_highpart_mq" | |
5717 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5718 | (truncate:SI | |
5719 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5720 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5721 | (zero_extend:DI | |
5722 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5723 | (const_int 32)))) | |
5724 | (clobber (match_scratch:SI 3 "=q"))] | |
5725 | "TARGET_POWERPC && TARGET_POWER" | |
5726 | "mulhwu %0,%1,%2" | |
5727 | [(set_attr "type" "imul")]) | |
5728 | ||
5729 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5730 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5731 | (truncate:SI | |
5732 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5733 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5734 | (zero_extend:DI | |
5735 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5736 | (const_int 32))))] | |
f192bf8b | 5737 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5738 | "mulhwu %0,%1,%2" |
5739 | [(set_attr "type" "imul")]) | |
5740 | ||
5741 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5742 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5743 | ;; why we have the strange constraints below. | |
5744 | (define_insn "ashldi3_power" | |
5745 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5746 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5747 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5748 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5749 | "TARGET_POWER" | |
5750 | "@ | |
5751 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5752 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5753 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5754 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5755 | [(set_attr "length" "8")]) | |
5756 | ||
5757 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5758 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5759 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5760 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5761 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5762 | "TARGET_POWER" | |
5763 | "@ | |
47ad8c61 | 5764 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5765 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5766 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5767 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5768 | [(set_attr "length" "8")]) | |
5769 | ||
5770 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5771 | ;; just handle shifts by constants. | |
5772 | (define_insn "ashrdi3_power" | |
7093ddee | 5773 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5774 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5775 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5776 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5777 | "TARGET_POWER" | |
5778 | "@ | |
5779 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5780 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5781 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
5782 | |
5783 | (define_insn "ashrdi3_no_power" | |
5784 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
5785 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5786 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
97727e85 | 5787 | "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN" |
4aa74a4f FS |
5788 | "@ |
5789 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5790 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
943c15ed DE |
5791 | [(set_attr "type" "two,three") |
5792 | (set_attr "length" "8,12")]) | |
683bdff7 FJ |
5793 | |
5794 | (define_insn "*ashrdisi3_noppc64" | |
5795 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 5796 | (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
683bdff7 FJ |
5797 | (const_int 32)) 4))] |
5798 | "TARGET_32BIT && !TARGET_POWERPC64" | |
5799 | "* | |
5800 | { | |
5801 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
5802 | return \"\"; | |
5803 | else | |
5804 | return \"mr %0,%1\"; | |
5805 | }" | |
6ae08853 | 5806 | [(set_attr "length" "4")]) |
683bdff7 | 5807 | |
266eb58a DE |
5808 | \f |
5809 | ;; PowerPC64 DImode operations. | |
5810 | ||
5811 | (define_expand "adddi3" | |
5812 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5813 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 5814 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
5815 | "" |
5816 | " | |
5817 | { | |
a260abc9 DE |
5818 | if (! TARGET_POWERPC64) |
5819 | { | |
5820 | if (non_short_cint_operand (operands[2], DImode)) | |
5821 | FAIL; | |
5822 | } | |
5823 | else | |
5824 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5825 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5826 | { |
677a9668 | 5827 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5828 | ? operands[0] : gen_reg_rtx (DImode)); |
5829 | ||
2bfcf297 | 5830 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5831 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5832 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
a260abc9 | 5833 | |
2bfcf297 DB |
5834 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
5835 | FAIL; | |
a260abc9 | 5836 | |
2bfcf297 DB |
5837 | /* The ordering here is important for the prolog expander. |
5838 | When space is allocated from the stack, adding 'low' first may | |
5839 | produce a temporary deallocation (which would be bad). */ | |
5840 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
5841 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
5842 | DONE; | |
5843 | } | |
266eb58a DE |
5844 | }") |
5845 | ||
5846 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5847 | ;; allowing register zero as source. | |
5848 | ||
a260abc9 | 5849 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5850 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5851 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5852 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5853 | "TARGET_POWERPC64" |
5854 | "@ | |
5855 | add %0,%1,%2 | |
5856 | addi %0,%1,%2 | |
5857 | addic %0,%1,%2 | |
802a0058 | 5858 | addis %0,%1,%v2") |
266eb58a | 5859 | |
a260abc9 | 5860 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5861 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5862 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5863 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5864 | (const_int 0))) |
9ebbca7d | 5865 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
683bdff7 | 5866 | "TARGET_64BIT" |
266eb58a DE |
5867 | "@ |
5868 | add. %3,%1,%2 | |
9ebbca7d GK |
5869 | addic. %3,%1,%2 |
5870 | # | |
5871 | #" | |
a62bfff2 | 5872 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5873 | (set_attr "length" "4,4,8,8")]) |
5874 | ||
5875 | (define_split | |
5876 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5877 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5878 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5879 | (const_int 0))) | |
5880 | (clobber (match_scratch:DI 3 ""))] | |
5881 | "TARGET_POWERPC64 && reload_completed" | |
5882 | [(set (match_dup 3) | |
5883 | (plus:DI (match_dup 1) (match_dup 2))) | |
5884 | (set (match_dup 0) | |
5885 | (compare:CC (match_dup 3) | |
5886 | (const_int 0)))] | |
5887 | "") | |
266eb58a | 5888 | |
a260abc9 | 5889 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5890 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5891 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5892 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5893 | (const_int 0))) |
9ebbca7d | 5894 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a | 5895 | (plus:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 5896 | "TARGET_64BIT" |
266eb58a DE |
5897 | "@ |
5898 | add. %0,%1,%2 | |
9ebbca7d GK |
5899 | addic. %0,%1,%2 |
5900 | # | |
5901 | #" | |
a62bfff2 | 5902 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5903 | (set_attr "length" "4,4,8,8")]) |
5904 | ||
5905 | (define_split | |
5906 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5907 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5908 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5909 | (const_int 0))) | |
5910 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5911 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5912 | "TARGET_POWERPC64 && reload_completed" | |
5913 | [(set (match_dup 0) | |
5914 | (plus:DI (match_dup 1) (match_dup 2))) | |
5915 | (set (match_dup 3) | |
5916 | (compare:CC (match_dup 0) | |
5917 | (const_int 0)))] | |
5918 | "") | |
266eb58a DE |
5919 | |
5920 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5921 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5922 | ;; add should be last in case the result gets used in an address. | |
5923 | ||
5924 | (define_split | |
5925 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5926 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5927 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5928 | "TARGET_POWERPC64" | |
5929 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5930 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5931 | " | |
5932 | { | |
2bfcf297 | 5933 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5934 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5935 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
266eb58a | 5936 | |
2bfcf297 DB |
5937 | operands[4] = GEN_INT (low); |
5938 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
5939 | operands[3] = GEN_INT (rest); | |
5940 | else if (! no_new_pseudos) | |
38886f37 | 5941 | { |
2bfcf297 DB |
5942 | operands[3] = gen_reg_rtx (DImode); |
5943 | emit_move_insn (operands[3], operands[2]); | |
5944 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
5945 | DONE; | |
38886f37 | 5946 | } |
2bfcf297 DB |
5947 | else |
5948 | FAIL; | |
266eb58a DE |
5949 | }") |
5950 | ||
5951 | (define_insn "one_cmpldi2" | |
5952 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5953 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5954 | "TARGET_POWERPC64" | |
5955 | "nor %0,%1,%1") | |
5956 | ||
5957 | (define_insn "" | |
9ebbca7d GK |
5958 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5959 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5960 | (const_int 0))) |
9ebbca7d | 5961 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 5962 | "TARGET_64BIT" |
9ebbca7d GK |
5963 | "@ |
5964 | nor. %2,%1,%1 | |
5965 | #" | |
5966 | [(set_attr "type" "compare") | |
5967 | (set_attr "length" "4,8")]) | |
5968 | ||
5969 | (define_split | |
5970 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5971 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5972 | (const_int 0))) | |
5973 | (clobber (match_scratch:DI 2 ""))] | |
5974 | "TARGET_POWERPC64 && reload_completed" | |
5975 | [(set (match_dup 2) | |
5976 | (not:DI (match_dup 1))) | |
5977 | (set (match_dup 0) | |
5978 | (compare:CC (match_dup 2) | |
5979 | (const_int 0)))] | |
5980 | "") | |
266eb58a DE |
5981 | |
5982 | (define_insn "" | |
9ebbca7d GK |
5983 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5984 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5985 | (const_int 0))) |
9ebbca7d | 5986 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 5987 | (not:DI (match_dup 1)))] |
683bdff7 | 5988 | "TARGET_64BIT" |
9ebbca7d GK |
5989 | "@ |
5990 | nor. %0,%1,%1 | |
5991 | #" | |
5992 | [(set_attr "type" "compare") | |
5993 | (set_attr "length" "4,8")]) | |
5994 | ||
5995 | (define_split | |
5996 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5997 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5998 | (const_int 0))) | |
5999 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6000 | (not:DI (match_dup 1)))] | |
6001 | "TARGET_POWERPC64 && reload_completed" | |
6002 | [(set (match_dup 0) | |
6003 | (not:DI (match_dup 1))) | |
6004 | (set (match_dup 2) | |
6005 | (compare:CC (match_dup 0) | |
6006 | (const_int 0)))] | |
6007 | "") | |
266eb58a DE |
6008 | |
6009 | (define_insn "" | |
6010 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6011 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
6012 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
6013 | "TARGET_POWERPC64" | |
6014 | "@ | |
6015 | subf %0,%2,%1 | |
6016 | subfic %0,%2,%1") | |
6017 | ||
6018 | (define_insn "" | |
9ebbca7d GK |
6019 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6020 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6021 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6022 | (const_int 0))) |
9ebbca7d | 6023 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6024 | "TARGET_64BIT" |
9ebbca7d GK |
6025 | "@ |
6026 | subf. %3,%2,%1 | |
6027 | #" | |
a62bfff2 | 6028 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6029 | (set_attr "length" "4,8")]) |
6030 | ||
6031 | (define_split | |
6032 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6033 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6034 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6035 | (const_int 0))) | |
6036 | (clobber (match_scratch:DI 3 ""))] | |
6037 | "TARGET_POWERPC64 && reload_completed" | |
6038 | [(set (match_dup 3) | |
6039 | (minus:DI (match_dup 1) (match_dup 2))) | |
6040 | (set (match_dup 0) | |
6041 | (compare:CC (match_dup 3) | |
6042 | (const_int 0)))] | |
6043 | "") | |
266eb58a DE |
6044 | |
6045 | (define_insn "" | |
9ebbca7d GK |
6046 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6047 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6048 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6049 | (const_int 0))) |
9ebbca7d | 6050 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6051 | (minus:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6052 | "TARGET_64BIT" |
9ebbca7d GK |
6053 | "@ |
6054 | subf. %0,%2,%1 | |
6055 | #" | |
a62bfff2 | 6056 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6057 | (set_attr "length" "4,8")]) |
6058 | ||
6059 | (define_split | |
6060 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6061 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6062 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6063 | (const_int 0))) | |
6064 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6065 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6066 | "TARGET_POWERPC64 && reload_completed" | |
6067 | [(set (match_dup 0) | |
6068 | (minus:DI (match_dup 1) (match_dup 2))) | |
6069 | (set (match_dup 3) | |
6070 | (compare:CC (match_dup 0) | |
6071 | (const_int 0)))] | |
6072 | "") | |
266eb58a DE |
6073 | |
6074 | (define_expand "subdi3" | |
6075 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6076 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 6077 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
6078 | "" |
6079 | " | |
6080 | { | |
6081 | if (GET_CODE (operands[2]) == CONST_INT) | |
6082 | { | |
6083 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
6084 | negate_rtx (DImode, operands[2]))); | |
6085 | DONE; | |
6086 | } | |
6087 | }") | |
6088 | ||
ea112fc4 | 6089 | (define_insn_and_split "absdi2" |
266eb58a | 6090 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6091 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
6092 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6093 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6094 | "#" |
6095 | "&& reload_completed" | |
a260abc9 | 6096 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6097 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 6098 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
6099 | "") |
6100 | ||
ea112fc4 | 6101 | (define_insn_and_split "*nabsdi2" |
266eb58a | 6102 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6103 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
6104 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6105 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6106 | "#" |
6107 | "&& reload_completed" | |
a260abc9 | 6108 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6109 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 6110 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
6111 | "") |
6112 | ||
6113 | (define_expand "negdi2" | |
6114 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6115 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
6116 | "" | |
6117 | "") | |
6118 | ||
6119 | (define_insn "" | |
6120 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6121 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6122 | "TARGET_POWERPC64" | |
6123 | "neg %0,%1") | |
6124 | ||
6125 | (define_insn "" | |
9ebbca7d GK |
6126 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6127 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6128 | (const_int 0))) |
9ebbca7d | 6129 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 6130 | "TARGET_64BIT" |
9ebbca7d GK |
6131 | "@ |
6132 | neg. %2,%1 | |
6133 | #" | |
a62bfff2 | 6134 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6135 | (set_attr "length" "4,8")]) |
6136 | ||
6137 | (define_split | |
6138 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6139 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6140 | (const_int 0))) | |
6141 | (clobber (match_scratch:DI 2 ""))] | |
6142 | "TARGET_POWERPC64 && reload_completed" | |
6143 | [(set (match_dup 2) | |
6144 | (neg:DI (match_dup 1))) | |
6145 | (set (match_dup 0) | |
6146 | (compare:CC (match_dup 2) | |
6147 | (const_int 0)))] | |
6148 | "") | |
815cdc52 | 6149 | |
29ae5b89 | 6150 | (define_insn "" |
9ebbca7d GK |
6151 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6152 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6153 | (const_int 0))) |
9ebbca7d | 6154 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6155 | (neg:DI (match_dup 1)))] |
683bdff7 | 6156 | "TARGET_64BIT" |
9ebbca7d GK |
6157 | "@ |
6158 | neg. %0,%1 | |
6159 | #" | |
a62bfff2 | 6160 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6161 | (set_attr "length" "4,8")]) |
6162 | ||
6163 | (define_split | |
6164 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6165 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6166 | (const_int 0))) | |
6167 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6168 | (neg:DI (match_dup 1)))] | |
6169 | "TARGET_POWERPC64 && reload_completed" | |
6170 | [(set (match_dup 0) | |
6171 | (neg:DI (match_dup 1))) | |
6172 | (set (match_dup 2) | |
6173 | (compare:CC (match_dup 0) | |
6174 | (const_int 0)))] | |
6175 | "") | |
266eb58a | 6176 | |
1b1edcfa DE |
6177 | (define_insn "clzdi2" |
6178 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6179 | (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6180 | "TARGET_POWERPC64" | |
6181 | "cntlzd %0,%1") | |
6182 | ||
6183 | (define_expand "ctzdi2" | |
4977bab6 | 6184 | [(set (match_dup 2) |
1b1edcfa | 6185 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
6ae08853 AM |
6186 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
6187 | (match_dup 2))) | |
1b1edcfa | 6188 | (clobber (scratch:CC))]) |
d865b122 | 6189 | (set (match_dup 4) (clz:DI (match_dup 3))) |
4977bab6 | 6190 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 6191 | (minus:DI (const_int 63) (match_dup 4)))] |
266eb58a | 6192 | "TARGET_POWERPC64" |
4977bab6 | 6193 | { |
6ae08853 | 6194 | operands[2] = gen_reg_rtx (DImode); |
4977bab6 ZW |
6195 | operands[3] = gen_reg_rtx (DImode); |
6196 | operands[4] = gen_reg_rtx (DImode); | |
6197 | }) | |
6198 | ||
1b1edcfa DE |
6199 | (define_expand "ffsdi2" |
6200 | [(set (match_dup 2) | |
6201 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
6ae08853 AM |
6202 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
6203 | (match_dup 2))) | |
1b1edcfa DE |
6204 | (clobber (scratch:CC))]) |
6205 | (set (match_dup 4) (clz:DI (match_dup 3))) | |
6206 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6207 | (minus:DI (const_int 64) (match_dup 4)))] | |
4977bab6 | 6208 | "TARGET_POWERPC64" |
1b1edcfa | 6209 | { |
6ae08853 | 6210 | operands[2] = gen_reg_rtx (DImode); |
1b1edcfa DE |
6211 | operands[3] = gen_reg_rtx (DImode); |
6212 | operands[4] = gen_reg_rtx (DImode); | |
6213 | }) | |
266eb58a DE |
6214 | |
6215 | (define_insn "muldi3" | |
6216 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6217 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6218 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6219 | "TARGET_POWERPC64" | |
6220 | "mulld %0,%1,%2" | |
3cb999d8 | 6221 | [(set_attr "type" "lmul")]) |
266eb58a | 6222 | |
9259f3b0 DE |
6223 | (define_insn "*muldi3_internal1" |
6224 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6225 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6226 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6227 | (const_int 0))) | |
6228 | (clobber (match_scratch:DI 3 "=r,r"))] | |
6229 | "TARGET_POWERPC64" | |
6230 | "@ | |
6231 | mulld. %3,%1,%2 | |
6232 | #" | |
6233 | [(set_attr "type" "lmul_compare") | |
6234 | (set_attr "length" "4,8")]) | |
6235 | ||
6236 | (define_split | |
6237 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6238 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6239 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6240 | (const_int 0))) | |
6241 | (clobber (match_scratch:DI 3 ""))] | |
6242 | "TARGET_POWERPC64 && reload_completed" | |
6243 | [(set (match_dup 3) | |
6244 | (mult:DI (match_dup 1) (match_dup 2))) | |
6245 | (set (match_dup 0) | |
6246 | (compare:CC (match_dup 3) | |
6247 | (const_int 0)))] | |
6248 | "") | |
6249 | ||
6250 | (define_insn "*muldi3_internal2" | |
6251 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | |
6252 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6253 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6254 | (const_int 0))) | |
6255 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6256 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6257 | "TARGET_POWERPC64" | |
6258 | "@ | |
6259 | mulld. %0,%1,%2 | |
6260 | #" | |
6261 | [(set_attr "type" "lmul_compare") | |
6262 | (set_attr "length" "4,8")]) | |
6263 | ||
6264 | (define_split | |
6265 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6266 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6267 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6268 | (const_int 0))) | |
6269 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6270 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6271 | "TARGET_POWERPC64 && reload_completed" | |
6272 | [(set (match_dup 0) | |
6273 | (mult:DI (match_dup 1) (match_dup 2))) | |
6274 | (set (match_dup 3) | |
6275 | (compare:CC (match_dup 0) | |
6276 | (const_int 0)))] | |
6277 | "") | |
6278 | ||
266eb58a DE |
6279 | (define_insn "smuldi3_highpart" |
6280 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6281 | (truncate:DI | |
6282 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6283 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6284 | (sign_extend:TI | |
6285 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6286 | (const_int 64))))] | |
6287 | "TARGET_POWERPC64" | |
6288 | "mulhd %0,%1,%2" | |
3cb999d8 | 6289 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6290 | |
6291 | (define_insn "umuldi3_highpart" | |
6292 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6293 | (truncate:DI | |
6294 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6295 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6296 | (zero_extend:TI | |
6297 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6298 | (const_int 64))))] | |
6299 | "TARGET_POWERPC64" | |
6300 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6301 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6302 | |
6303 | (define_expand "divdi3" | |
6304 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6305 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6306 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6307 | "TARGET_POWERPC64" | |
6308 | " | |
6309 | { | |
6310 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6311 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6312 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6313 | ; | |
6314 | else | |
6315 | operands[2] = force_reg (DImode, operands[2]); | |
6316 | }") | |
6317 | ||
6318 | (define_expand "moddi3" | |
6319 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6320 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6321 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6322 | "TARGET_POWERPC64" | |
6323 | " | |
6324 | { | |
2bfcf297 | 6325 | int i; |
266eb58a DE |
6326 | rtx temp1; |
6327 | rtx temp2; | |
6328 | ||
2bfcf297 DB |
6329 | if (GET_CODE (operands[2]) != CONST_INT |
6330 | || INTVAL (operands[2]) <= 0 | |
6331 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6332 | FAIL; |
6333 | ||
6334 | temp1 = gen_reg_rtx (DImode); | |
6335 | temp2 = gen_reg_rtx (DImode); | |
6336 | ||
6337 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6338 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6339 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6340 | DONE; | |
6341 | }") | |
6342 | ||
6343 | (define_insn "" | |
6344 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6345 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6346 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6347 | "TARGET_POWERPC64" | |
266eb58a | 6348 | "sradi %0,%1,%p2\;addze %0,%0" |
943c15ed DE |
6349 | [(set_attr "type" "two") |
6350 | (set_attr "length" "8")]) | |
266eb58a DE |
6351 | |
6352 | (define_insn "" | |
9ebbca7d GK |
6353 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6354 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6355 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6356 | (const_int 0))) |
9ebbca7d | 6357 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6358 | "TARGET_64BIT" |
9ebbca7d GK |
6359 | "@ |
6360 | sradi %3,%1,%p2\;addze. %3,%3 | |
6361 | #" | |
266eb58a | 6362 | [(set_attr "type" "compare") |
9ebbca7d GK |
6363 | (set_attr "length" "8,12")]) |
6364 | ||
6365 | (define_split | |
6366 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6367 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6368 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6369 | (const_int 0))) |
6370 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6371 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6372 | [(set (match_dup 3) |
6373 | (div:DI (match_dup 1) (match_dup 2))) | |
6374 | (set (match_dup 0) | |
6375 | (compare:CC (match_dup 3) | |
6376 | (const_int 0)))] | |
6377 | "") | |
266eb58a DE |
6378 | |
6379 | (define_insn "" | |
9ebbca7d GK |
6380 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6381 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6382 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6383 | (const_int 0))) |
9ebbca7d | 6384 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6385 | (div:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6386 | "TARGET_64BIT" |
9ebbca7d GK |
6387 | "@ |
6388 | sradi %0,%1,%p2\;addze. %0,%0 | |
6389 | #" | |
266eb58a | 6390 | [(set_attr "type" "compare") |
9ebbca7d | 6391 | (set_attr "length" "8,12")]) |
266eb58a | 6392 | |
9ebbca7d GK |
6393 | (define_split |
6394 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6395 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6396 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6397 | (const_int 0))) |
6398 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6399 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6400 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6401 | [(set (match_dup 0) |
6402 | (div:DI (match_dup 1) (match_dup 2))) | |
6403 | (set (match_dup 3) | |
6404 | (compare:CC (match_dup 0) | |
6405 | (const_int 0)))] | |
6406 | "") | |
6407 | ||
6408 | (define_insn "" | |
6409 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6410 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6411 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6412 | "TARGET_POWERPC64" |
6413 | "divd %0,%1,%2" | |
3cb999d8 | 6414 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6415 | |
6416 | (define_insn "udivdi3" | |
6417 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6418 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6419 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6420 | "TARGET_POWERPC64" | |
6421 | "divdu %0,%1,%2" | |
3cb999d8 | 6422 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6423 | |
6424 | (define_insn "rotldi3" | |
6425 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6426 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6427 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6428 | "TARGET_POWERPC64" | |
a66078ee | 6429 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6430 | |
a260abc9 | 6431 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6432 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6433 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6434 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6435 | (const_int 0))) |
9ebbca7d | 6436 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6437 | "TARGET_64BIT" |
9ebbca7d GK |
6438 | "@ |
6439 | rld%I2cl. %3,%1,%H2,0 | |
6440 | #" | |
6441 | [(set_attr "type" "delayed_compare") | |
6442 | (set_attr "length" "4,8")]) | |
6443 | ||
6444 | (define_split | |
6445 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6446 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6447 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6448 | (const_int 0))) | |
6449 | (clobber (match_scratch:DI 3 ""))] | |
6450 | "TARGET_POWERPC64 && reload_completed" | |
6451 | [(set (match_dup 3) | |
6452 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6453 | (set (match_dup 0) | |
6454 | (compare:CC (match_dup 3) | |
6455 | (const_int 0)))] | |
6456 | "") | |
266eb58a | 6457 | |
a260abc9 | 6458 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6459 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6460 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6461 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6462 | (const_int 0))) |
9ebbca7d | 6463 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6464 | (rotate:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6465 | "TARGET_64BIT" |
9ebbca7d GK |
6466 | "@ |
6467 | rld%I2cl. %0,%1,%H2,0 | |
6468 | #" | |
6469 | [(set_attr "type" "delayed_compare") | |
6470 | (set_attr "length" "4,8")]) | |
6471 | ||
6472 | (define_split | |
6473 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6474 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6475 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6476 | (const_int 0))) | |
6477 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6478 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6479 | "TARGET_POWERPC64 && reload_completed" | |
6480 | [(set (match_dup 0) | |
6481 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6482 | (set (match_dup 3) | |
6483 | (compare:CC (match_dup 0) | |
6484 | (const_int 0)))] | |
6485 | "") | |
266eb58a | 6486 | |
a260abc9 DE |
6487 | (define_insn "*rotldi3_internal4" |
6488 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6489 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6490 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
ce71f754 | 6491 | (match_operand:DI 3 "mask64_operand" "n")))] |
a260abc9 DE |
6492 | "TARGET_POWERPC64" |
6493 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6494 | ||
6495 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6496 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6497 | (compare:CC (and:DI |
9ebbca7d GK |
6498 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6499 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6500 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6501 | (const_int 0))) |
9ebbca7d | 6502 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6503 | "TARGET_64BIT" |
9ebbca7d GK |
6504 | "@ |
6505 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6506 | #" | |
6507 | [(set_attr "type" "delayed_compare") | |
6508 | (set_attr "length" "4,8")]) | |
6509 | ||
6510 | (define_split | |
6511 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6512 | (compare:CC (and:DI | |
6513 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6514 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6515 | (match_operand:DI 3 "mask64_operand" "")) | |
6516 | (const_int 0))) | |
6517 | (clobber (match_scratch:DI 4 ""))] | |
6518 | "TARGET_POWERPC64 && reload_completed" | |
6519 | [(set (match_dup 4) | |
6520 | (and:DI (rotate:DI (match_dup 1) | |
6521 | (match_dup 2)) | |
6522 | (match_dup 3))) | |
6523 | (set (match_dup 0) | |
6524 | (compare:CC (match_dup 4) | |
6525 | (const_int 0)))] | |
6526 | "") | |
a260abc9 DE |
6527 | |
6528 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6529 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6530 | (compare:CC (and:DI |
9ebbca7d GK |
6531 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6532 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6533 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6534 | (const_int 0))) |
9ebbca7d | 6535 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6536 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6537 | "TARGET_64BIT" |
9ebbca7d GK |
6538 | "@ |
6539 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6540 | #" | |
6541 | [(set_attr "type" "delayed_compare") | |
6542 | (set_attr "length" "4,8")]) | |
6543 | ||
6544 | (define_split | |
6545 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6546 | (compare:CC (and:DI | |
6547 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6548 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6549 | (match_operand:DI 3 "mask64_operand" "")) | |
6550 | (const_int 0))) | |
6551 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6552 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6553 | "TARGET_POWERPC64 && reload_completed" | |
6554 | [(set (match_dup 0) | |
6555 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6556 | (set (match_dup 4) | |
6557 | (compare:CC (match_dup 0) | |
6558 | (const_int 0)))] | |
6559 | "") | |
a260abc9 DE |
6560 | |
6561 | (define_insn "*rotldi3_internal7" | |
6562 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6563 | (zero_extend:DI | |
6564 | (subreg:QI | |
6565 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6566 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6567 | "TARGET_POWERPC64" | |
6568 | "rld%I2cl %0,%1,%H2,56") | |
6569 | ||
6570 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6571 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6572 | (compare:CC (zero_extend:DI |
6573 | (subreg:QI | |
9ebbca7d GK |
6574 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6575 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6576 | (const_int 0))) |
9ebbca7d | 6577 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6578 | "TARGET_64BIT" |
9ebbca7d GK |
6579 | "@ |
6580 | rld%I2cl. %3,%1,%H2,56 | |
6581 | #" | |
6582 | [(set_attr "type" "delayed_compare") | |
6583 | (set_attr "length" "4,8")]) | |
6584 | ||
6585 | (define_split | |
6586 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6587 | (compare:CC (zero_extend:DI | |
6588 | (subreg:QI | |
6589 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6590 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6591 | (const_int 0))) | |
6592 | (clobber (match_scratch:DI 3 ""))] | |
6593 | "TARGET_POWERPC64 && reload_completed" | |
6594 | [(set (match_dup 3) | |
6595 | (zero_extend:DI (subreg:QI | |
6596 | (rotate:DI (match_dup 1) | |
6597 | (match_dup 2)) 0))) | |
6598 | (set (match_dup 0) | |
6599 | (compare:CC (match_dup 3) | |
6600 | (const_int 0)))] | |
6601 | "") | |
a260abc9 DE |
6602 | |
6603 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6604 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6605 | (compare:CC (zero_extend:DI |
6606 | (subreg:QI | |
9ebbca7d GK |
6607 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6608 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6609 | (const_int 0))) |
9ebbca7d | 6610 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6611 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6612 | "TARGET_64BIT" |
9ebbca7d GK |
6613 | "@ |
6614 | rld%I2cl. %0,%1,%H2,56 | |
6615 | #" | |
6616 | [(set_attr "type" "delayed_compare") | |
6617 | (set_attr "length" "4,8")]) | |
6618 | ||
6619 | (define_split | |
6620 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6621 | (compare:CC (zero_extend:DI | |
6622 | (subreg:QI | |
6623 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6624 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6625 | (const_int 0))) | |
6626 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6627 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6628 | "TARGET_POWERPC64 && reload_completed" | |
6629 | [(set (match_dup 0) | |
6630 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6631 | (set (match_dup 3) | |
6632 | (compare:CC (match_dup 0) | |
6633 | (const_int 0)))] | |
6634 | "") | |
a260abc9 DE |
6635 | |
6636 | (define_insn "*rotldi3_internal10" | |
6637 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6638 | (zero_extend:DI | |
6639 | (subreg:HI | |
6640 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6641 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6642 | "TARGET_POWERPC64" | |
6643 | "rld%I2cl %0,%1,%H2,48") | |
6644 | ||
6645 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6646 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6647 | (compare:CC (zero_extend:DI |
6648 | (subreg:HI | |
9ebbca7d GK |
6649 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6650 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6651 | (const_int 0))) |
9ebbca7d | 6652 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6653 | "TARGET_64BIT" |
9ebbca7d GK |
6654 | "@ |
6655 | rld%I2cl. %3,%1,%H2,48 | |
6656 | #" | |
6657 | [(set_attr "type" "delayed_compare") | |
6658 | (set_attr "length" "4,8")]) | |
6659 | ||
6660 | (define_split | |
6661 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6662 | (compare:CC (zero_extend:DI | |
6663 | (subreg:HI | |
6664 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6665 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6666 | (const_int 0))) | |
6667 | (clobber (match_scratch:DI 3 ""))] | |
6668 | "TARGET_POWERPC64 && reload_completed" | |
6669 | [(set (match_dup 3) | |
6670 | (zero_extend:DI (subreg:HI | |
6671 | (rotate:DI (match_dup 1) | |
6672 | (match_dup 2)) 0))) | |
6673 | (set (match_dup 0) | |
6674 | (compare:CC (match_dup 3) | |
6675 | (const_int 0)))] | |
6676 | "") | |
a260abc9 DE |
6677 | |
6678 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6679 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6680 | (compare:CC (zero_extend:DI |
6681 | (subreg:HI | |
9ebbca7d GK |
6682 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6683 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6684 | (const_int 0))) |
9ebbca7d | 6685 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6686 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6687 | "TARGET_64BIT" |
9ebbca7d GK |
6688 | "@ |
6689 | rld%I2cl. %0,%1,%H2,48 | |
6690 | #" | |
6691 | [(set_attr "type" "delayed_compare") | |
6692 | (set_attr "length" "4,8")]) | |
6693 | ||
6694 | (define_split | |
6695 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6696 | (compare:CC (zero_extend:DI | |
6697 | (subreg:HI | |
6698 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6699 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6700 | (const_int 0))) | |
6701 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6702 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6703 | "TARGET_POWERPC64 && reload_completed" | |
6704 | [(set (match_dup 0) | |
6705 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6706 | (set (match_dup 3) | |
6707 | (compare:CC (match_dup 0) | |
6708 | (const_int 0)))] | |
6709 | "") | |
a260abc9 DE |
6710 | |
6711 | (define_insn "*rotldi3_internal13" | |
6712 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6713 | (zero_extend:DI | |
6714 | (subreg:SI | |
6715 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6716 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6717 | "TARGET_POWERPC64" | |
6718 | "rld%I2cl %0,%1,%H2,32") | |
6719 | ||
6720 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6721 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6722 | (compare:CC (zero_extend:DI |
6723 | (subreg:SI | |
9ebbca7d GK |
6724 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6725 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6726 | (const_int 0))) |
9ebbca7d | 6727 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6728 | "TARGET_64BIT" |
9ebbca7d GK |
6729 | "@ |
6730 | rld%I2cl. %3,%1,%H2,32 | |
6731 | #" | |
6732 | [(set_attr "type" "delayed_compare") | |
6733 | (set_attr "length" "4,8")]) | |
6734 | ||
6735 | (define_split | |
6736 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6737 | (compare:CC (zero_extend:DI | |
6738 | (subreg:SI | |
6739 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6740 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6741 | (const_int 0))) | |
6742 | (clobber (match_scratch:DI 3 ""))] | |
6743 | "TARGET_POWERPC64 && reload_completed" | |
6744 | [(set (match_dup 3) | |
6745 | (zero_extend:DI (subreg:SI | |
6746 | (rotate:DI (match_dup 1) | |
6747 | (match_dup 2)) 0))) | |
6748 | (set (match_dup 0) | |
6749 | (compare:CC (match_dup 3) | |
6750 | (const_int 0)))] | |
6751 | "") | |
a260abc9 DE |
6752 | |
6753 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6754 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6755 | (compare:CC (zero_extend:DI |
6756 | (subreg:SI | |
9ebbca7d GK |
6757 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6758 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6759 | (const_int 0))) |
9ebbca7d | 6760 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6761 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6762 | "TARGET_64BIT" |
9ebbca7d GK |
6763 | "@ |
6764 | rld%I2cl. %0,%1,%H2,32 | |
6765 | #" | |
6766 | [(set_attr "type" "delayed_compare") | |
6767 | (set_attr "length" "4,8")]) | |
6768 | ||
6769 | (define_split | |
6770 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6771 | (compare:CC (zero_extend:DI | |
6772 | (subreg:SI | |
6773 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6774 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6775 | (const_int 0))) | |
6776 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6777 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6778 | "TARGET_POWERPC64 && reload_completed" | |
6779 | [(set (match_dup 0) | |
6780 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6781 | (set (match_dup 3) | |
6782 | (compare:CC (match_dup 0) | |
6783 | (const_int 0)))] | |
6784 | "") | |
a260abc9 | 6785 | |
266eb58a DE |
6786 | (define_expand "ashldi3" |
6787 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6788 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6789 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6790 | "TARGET_POWERPC64 || TARGET_POWER" | |
6791 | " | |
6792 | { | |
6793 | if (TARGET_POWERPC64) | |
6794 | ; | |
6795 | else if (TARGET_POWER) | |
6796 | { | |
6797 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6798 | DONE; | |
6799 | } | |
6800 | else | |
6801 | FAIL; | |
6802 | }") | |
6803 | ||
e2c953b6 | 6804 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6805 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6806 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6807 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6808 | "TARGET_POWERPC64" | |
943c15ed | 6809 | "sld%I2 %0,%1,%H2") |
6ae08853 | 6810 | |
e2c953b6 | 6811 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6812 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6813 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6814 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6815 | (const_int 0))) |
9ebbca7d | 6816 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6817 | "TARGET_64BIT" |
9ebbca7d GK |
6818 | "@ |
6819 | sld%I2. %3,%1,%H2 | |
6820 | #" | |
6821 | [(set_attr "type" "delayed_compare") | |
6822 | (set_attr "length" "4,8")]) | |
6ae08853 | 6823 | |
9ebbca7d GK |
6824 | (define_split |
6825 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6826 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6827 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6828 | (const_int 0))) | |
6829 | (clobber (match_scratch:DI 3 ""))] | |
6830 | "TARGET_POWERPC64 && reload_completed" | |
6831 | [(set (match_dup 3) | |
6832 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6833 | (set (match_dup 0) | |
6834 | (compare:CC (match_dup 3) | |
6835 | (const_int 0)))] | |
6836 | "") | |
6837 | ||
e2c953b6 | 6838 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6839 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6840 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6841 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6842 | (const_int 0))) |
9ebbca7d | 6843 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6844 | (ashift:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6845 | "TARGET_64BIT" |
9ebbca7d GK |
6846 | "@ |
6847 | sld%I2. %0,%1,%H2 | |
6848 | #" | |
6849 | [(set_attr "type" "delayed_compare") | |
6850 | (set_attr "length" "4,8")]) | |
6851 | ||
6852 | (define_split | |
6853 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6854 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6855 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6856 | (const_int 0))) | |
6857 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6858 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6859 | "TARGET_POWERPC64 && reload_completed" | |
6860 | [(set (match_dup 0) | |
6861 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6862 | (set (match_dup 3) | |
6863 | (compare:CC (match_dup 0) | |
6864 | (const_int 0)))] | |
6865 | "") | |
266eb58a | 6866 | |
e2c953b6 | 6867 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6868 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6869 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6870 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6871 | (match_operand:DI 3 "const_int_operand" "n")))] |
6872 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6873 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6874 | |
e2c953b6 | 6875 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6876 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6877 | (compare:CC |
9ebbca7d GK |
6878 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6879 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6880 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6881 | (const_int 0))) |
9ebbca7d | 6882 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6883 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6884 | "@ |
e2c953b6 | 6885 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6886 | #" |
6887 | [(set_attr "type" "delayed_compare") | |
6888 | (set_attr "length" "4,8")]) | |
6889 | ||
6890 | (define_split | |
6891 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6892 | (compare:CC | |
6893 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6894 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6895 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6896 | (const_int 0))) |
6897 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6898 | "TARGET_POWERPC64 && reload_completed |
6899 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6900 | [(set (match_dup 4) |
6901 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6902 | (match_dup 3))) |
9ebbca7d GK |
6903 | (set (match_dup 0) |
6904 | (compare:CC (match_dup 4) | |
6905 | (const_int 0)))] | |
6906 | "") | |
3cb999d8 | 6907 | |
e2c953b6 | 6908 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6909 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6910 | (compare:CC |
9ebbca7d GK |
6911 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6912 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6913 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6914 | (const_int 0))) |
9ebbca7d | 6915 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6916 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6917 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6918 | "@ |
e2c953b6 | 6919 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6920 | #" |
6921 | [(set_attr "type" "delayed_compare") | |
6922 | (set_attr "length" "4,8")]) | |
6923 | ||
6924 | (define_split | |
6925 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6926 | (compare:CC | |
6927 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6928 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6929 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6930 | (const_int 0))) |
6931 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6932 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6933 | "TARGET_POWERPC64 && reload_completed |
6934 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6935 | [(set (match_dup 0) | |
6936 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6937 | (match_dup 3))) | |
6938 | (set (match_dup 4) | |
6939 | (compare:CC (match_dup 0) | |
6940 | (const_int 0)))] | |
6941 | "") | |
6942 | ||
6943 | (define_insn "*ashldi3_internal7" | |
6944 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6945 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6946 | (match_operand:SI 2 "const_int_operand" "i")) | |
ce71f754 | 6947 | (match_operand:DI 3 "mask64_operand" "n")))] |
c5059423 AM |
6948 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
6949 | "rldicr %0,%1,%H2,%S3") | |
6950 | ||
6951 | (define_insn "ashldi3_internal8" | |
6952 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6953 | (compare:CC | |
6954 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6955 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6956 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6957 | (const_int 0))) |
6958 | (clobber (match_scratch:DI 4 "=r,r"))] | |
683bdff7 | 6959 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6960 | "@ |
6961 | rldicr. %4,%1,%H2,%S3 | |
6962 | #" | |
6963 | [(set_attr "type" "delayed_compare") | |
6964 | (set_attr "length" "4,8")]) | |
6965 | ||
6966 | (define_split | |
6967 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6968 | (compare:CC | |
6969 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6970 | (match_operand:SI 2 "const_int_operand" "")) | |
6971 | (match_operand:DI 3 "mask64_operand" "")) | |
6972 | (const_int 0))) | |
6973 | (clobber (match_scratch:DI 4 ""))] | |
6974 | "TARGET_POWERPC64 && reload_completed | |
6975 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6976 | [(set (match_dup 4) | |
6977 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6978 | (match_dup 3))) | |
6979 | (set (match_dup 0) | |
6980 | (compare:CC (match_dup 4) | |
6981 | (const_int 0)))] | |
6982 | "") | |
6983 | ||
6984 | (define_insn "*ashldi3_internal9" | |
6985 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6986 | (compare:CC | |
6987 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6988 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6989 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6990 | (const_int 0))) |
6991 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6992 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 6993 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6994 | "@ |
6995 | rldicr. %0,%1,%H2,%S3 | |
6996 | #" | |
6997 | [(set_attr "type" "delayed_compare") | |
6998 | (set_attr "length" "4,8")]) | |
6999 | ||
7000 | (define_split | |
7001 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
7002 | (compare:CC | |
7003 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7004 | (match_operand:SI 2 "const_int_operand" "")) | |
7005 | (match_operand:DI 3 "mask64_operand" "")) | |
7006 | (const_int 0))) | |
7007 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7008 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
7009 | "TARGET_POWERPC64 && reload_completed | |
7010 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 7011 | [(set (match_dup 0) |
e2c953b6 DE |
7012 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
7013 | (match_dup 3))) | |
9ebbca7d GK |
7014 | (set (match_dup 4) |
7015 | (compare:CC (match_dup 0) | |
7016 | (const_int 0)))] | |
7017 | "") | |
7018 | ||
7019 | (define_expand "lshrdi3" | |
266eb58a DE |
7020 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
7021 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7022 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
7023 | "TARGET_POWERPC64 || TARGET_POWER" | |
7024 | " | |
7025 | { | |
7026 | if (TARGET_POWERPC64) | |
7027 | ; | |
7028 | else if (TARGET_POWER) | |
7029 | { | |
7030 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
7031 | DONE; | |
7032 | } | |
7033 | else | |
7034 | FAIL; | |
7035 | }") | |
7036 | ||
e2c953b6 | 7037 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
7038 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7039 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7040 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7041 | "TARGET_POWERPC64" | |
a66078ee | 7042 | "srd%I2 %0,%1,%H2") |
266eb58a | 7043 | |
e2c953b6 | 7044 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
7045 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7046 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7047 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 7048 | (const_int 0))) |
9ebbca7d | 7049 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7050 | "TARGET_64BIT " |
9ebbca7d GK |
7051 | "@ |
7052 | srd%I2. %3,%1,%H2 | |
7053 | #" | |
7054 | [(set_attr "type" "delayed_compare") | |
7055 | (set_attr "length" "4,8")]) | |
7056 | ||
7057 | (define_split | |
7058 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7059 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7060 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7061 | (const_int 0))) | |
7062 | (clobber (match_scratch:DI 3 ""))] | |
7063 | "TARGET_POWERPC64 && reload_completed" | |
7064 | [(set (match_dup 3) | |
7065 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7066 | (set (match_dup 0) | |
7067 | (compare:CC (match_dup 3) | |
7068 | (const_int 0)))] | |
7069 | "") | |
266eb58a | 7070 | |
e2c953b6 | 7071 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
7072 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7073 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7074 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7075 | (const_int 0))) |
9ebbca7d | 7076 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 7077 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 7078 | "TARGET_64BIT" |
9ebbca7d GK |
7079 | "@ |
7080 | srd%I2. %0,%1,%H2 | |
7081 | #" | |
7082 | [(set_attr "type" "delayed_compare") | |
7083 | (set_attr "length" "4,8")]) | |
7084 | ||
7085 | (define_split | |
7086 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7087 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7088 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7089 | (const_int 0))) | |
7090 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7091 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
7092 | "TARGET_POWERPC64 && reload_completed" | |
7093 | [(set (match_dup 0) | |
7094 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7095 | (set (match_dup 3) | |
7096 | (compare:CC (match_dup 0) | |
7097 | (const_int 0)))] | |
7098 | "") | |
266eb58a DE |
7099 | |
7100 | (define_expand "ashrdi3" | |
7101 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7102 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7103 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
97727e85 | 7104 | "WORDS_BIG_ENDIAN" |
266eb58a DE |
7105 | " |
7106 | { | |
7107 | if (TARGET_POWERPC64) | |
7108 | ; | |
7109 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
7110 | { | |
7111 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
7112 | DONE; | |
7113 | } | |
97727e85 AH |
7114 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT |
7115 | && WORDS_BIG_ENDIAN) | |
4aa74a4f FS |
7116 | { |
7117 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
7118 | DONE; | |
7119 | } | |
266eb58a DE |
7120 | else |
7121 | FAIL; | |
7122 | }") | |
7123 | ||
e2c953b6 | 7124 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
7125 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7126 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7127 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7128 | "TARGET_POWERPC64" | |
375490e0 | 7129 | "srad%I2 %0,%1,%H2") |
266eb58a | 7130 | |
e2c953b6 | 7131 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
7132 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7133 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7134 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7135 | (const_int 0))) |
9ebbca7d | 7136 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7137 | "TARGET_64BIT" |
9ebbca7d GK |
7138 | "@ |
7139 | srad%I2. %3,%1,%H2 | |
7140 | #" | |
7141 | [(set_attr "type" "delayed_compare") | |
7142 | (set_attr "length" "4,8")]) | |
7143 | ||
7144 | (define_split | |
7145 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7146 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7147 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7148 | (const_int 0))) | |
7149 | (clobber (match_scratch:DI 3 ""))] | |
7150 | "TARGET_POWERPC64 && reload_completed" | |
7151 | [(set (match_dup 3) | |
7152 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7153 | (set (match_dup 0) | |
7154 | (compare:CC (match_dup 3) | |
7155 | (const_int 0)))] | |
7156 | "") | |
266eb58a | 7157 | |
e2c953b6 | 7158 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
7159 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7160 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7161 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7162 | (const_int 0))) |
9ebbca7d | 7163 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 7164 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 7165 | "TARGET_64BIT" |
9ebbca7d GK |
7166 | "@ |
7167 | srad%I2. %0,%1,%H2 | |
7168 | #" | |
7169 | [(set_attr "type" "delayed_compare") | |
7170 | (set_attr "length" "4,8")]) | |
7171 | ||
7172 | (define_split | |
7173 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7174 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7175 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7176 | (const_int 0))) | |
7177 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7178 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7179 | "TARGET_POWERPC64 && reload_completed" | |
7180 | [(set (match_dup 0) | |
7181 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7182 | (set (match_dup 3) | |
7183 | (compare:CC (match_dup 0) | |
7184 | (const_int 0)))] | |
7185 | "") | |
815cdc52 | 7186 | |
29ae5b89 | 7187 | (define_insn "anddi3" |
e1e2e653 NS |
7188 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
7189 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") | |
7190 | (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t"))) | |
7191 | (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))] | |
6ffc8580 | 7192 | "TARGET_POWERPC64" |
266eb58a DE |
7193 | "@ |
7194 | and %0,%1,%2 | |
29ae5b89 | 7195 | rldic%B2 %0,%1,0,%S2 |
e1e2e653 | 7196 | rlwinm %0,%1,0,%m2,%M2 |
29ae5b89 | 7197 | andi. %0,%1,%b2 |
0ba1b2ff AM |
7198 | andis. %0,%1,%u2 |
7199 | #" | |
e1e2e653 NS |
7200 | [(set_attr "type" "*,*,*,compare,compare,*") |
7201 | (set_attr "length" "4,4,4,4,4,8")]) | |
0ba1b2ff AM |
7202 | |
7203 | (define_split | |
7204 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7205 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7206 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
7207 | (clobber (match_scratch:CC 3 ""))] | |
7208 | "TARGET_POWERPC64 | |
7209 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7210 | && !mask64_operand (operands[2], DImode)" | |
7211 | [(set (match_dup 0) | |
7212 | (and:DI (rotate:DI (match_dup 1) | |
7213 | (match_dup 4)) | |
7214 | (match_dup 5))) | |
7215 | (set (match_dup 0) | |
7216 | (and:DI (rotate:DI (match_dup 0) | |
7217 | (match_dup 6)) | |
7218 | (match_dup 7)))] | |
0ba1b2ff AM |
7219 | { |
7220 | build_mask64_2_operands (operands[2], &operands[4]); | |
e1e2e653 | 7221 | }) |
266eb58a | 7222 | |
a260abc9 | 7223 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
7224 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7225 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7226 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7227 | (const_int 0))) |
0ba1b2ff AM |
7228 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
7229 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
683bdff7 | 7230 | "TARGET_64BIT" |
266eb58a DE |
7231 | "@ |
7232 | and. %3,%1,%2 | |
6c873122 | 7233 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
7234 | andi. %3,%1,%b2 |
7235 | andis. %3,%1,%u2 | |
9ebbca7d GK |
7236 | # |
7237 | # | |
7238 | # | |
0ba1b2ff AM |
7239 | # |
7240 | # | |
9ebbca7d | 7241 | #" |
0ba1b2ff AM |
7242 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7243 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7244 | |
7245 | (define_split | |
7246 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7247 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7248 | (match_operand:DI 2 "and64_operand" "")) | |
7249 | (const_int 0))) | |
7250 | (clobber (match_scratch:DI 3 "")) | |
7251 | (clobber (match_scratch:CC 4 ""))] | |
7252 | "TARGET_POWERPC64 && reload_completed" | |
7253 | [(parallel [(set (match_dup 3) | |
7254 | (and:DI (match_dup 1) | |
7255 | (match_dup 2))) | |
7256 | (clobber (match_dup 4))]) | |
7257 | (set (match_dup 0) | |
7258 | (compare:CC (match_dup 3) | |
7259 | (const_int 0)))] | |
7260 | "") | |
266eb58a | 7261 | |
0ba1b2ff AM |
7262 | (define_split |
7263 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
7264 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7265 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7266 | (const_int 0))) | |
7267 | (clobber (match_scratch:DI 3 "")) | |
7268 | (clobber (match_scratch:CC 4 ""))] | |
7269 | "TARGET_POWERPC64 && reload_completed | |
7270 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7271 | && !mask64_operand (operands[2], DImode)" | |
7272 | [(set (match_dup 3) | |
7273 | (and:DI (rotate:DI (match_dup 1) | |
7274 | (match_dup 5)) | |
7275 | (match_dup 6))) | |
7276 | (parallel [(set (match_dup 0) | |
7277 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
7278 | (match_dup 7)) | |
7279 | (match_dup 8)) | |
7280 | (const_int 0))) | |
7281 | (clobber (match_dup 3))])] | |
7282 | " | |
7283 | { | |
7284 | build_mask64_2_operands (operands[2], &operands[5]); | |
7285 | }") | |
7286 | ||
a260abc9 | 7287 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
7288 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7289 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7290 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7291 | (const_int 0))) |
0ba1b2ff | 7292 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 7293 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 7294 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
683bdff7 | 7295 | "TARGET_64BIT" |
266eb58a DE |
7296 | "@ |
7297 | and. %0,%1,%2 | |
6c873122 | 7298 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7299 | andi. %0,%1,%b2 |
7300 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7301 | # |
7302 | # | |
7303 | # | |
0ba1b2ff AM |
7304 | # |
7305 | # | |
9ebbca7d | 7306 | #" |
0ba1b2ff AM |
7307 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7308 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7309 | |
7310 | (define_split | |
7311 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7312 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7313 | (match_operand:DI 2 "and64_operand" "")) | |
7314 | (const_int 0))) | |
7315 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7316 | (and:DI (match_dup 1) (match_dup 2))) | |
7317 | (clobber (match_scratch:CC 4 ""))] | |
7318 | "TARGET_POWERPC64 && reload_completed" | |
7319 | [(parallel [(set (match_dup 0) | |
7320 | (and:DI (match_dup 1) (match_dup 2))) | |
7321 | (clobber (match_dup 4))]) | |
7322 | (set (match_dup 3) | |
7323 | (compare:CC (match_dup 0) | |
7324 | (const_int 0)))] | |
7325 | "") | |
266eb58a | 7326 | |
0ba1b2ff AM |
7327 | (define_split |
7328 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
7329 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7330 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7331 | (const_int 0))) | |
7332 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7333 | (and:DI (match_dup 1) (match_dup 2))) | |
7334 | (clobber (match_scratch:CC 4 ""))] | |
7335 | "TARGET_POWERPC64 && reload_completed | |
7336 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7337 | && !mask64_operand (operands[2], DImode)" | |
7338 | [(set (match_dup 0) | |
7339 | (and:DI (rotate:DI (match_dup 1) | |
7340 | (match_dup 5)) | |
7341 | (match_dup 6))) | |
7342 | (parallel [(set (match_dup 3) | |
7343 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
7344 | (match_dup 7)) | |
7345 | (match_dup 8)) | |
7346 | (const_int 0))) | |
7347 | (set (match_dup 0) | |
7348 | (and:DI (rotate:DI (match_dup 0) | |
7349 | (match_dup 7)) | |
7350 | (match_dup 8)))])] | |
7351 | " | |
7352 | { | |
7353 | build_mask64_2_operands (operands[2], &operands[5]); | |
7354 | }") | |
7355 | ||
a260abc9 | 7356 | (define_expand "iordi3" |
266eb58a | 7357 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7358 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7359 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7360 | "TARGET_POWERPC64" |
266eb58a DE |
7361 | " |
7362 | { | |
dfbdccdb | 7363 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7364 | { |
dfbdccdb | 7365 | HOST_WIDE_INT value; |
677a9668 | 7366 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7367 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7368 | |
dfbdccdb GK |
7369 | if (GET_CODE (operands[2]) == CONST_INT) |
7370 | { | |
7371 | value = INTVAL (operands[2]); | |
7372 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7373 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7374 | } | |
e2c953b6 | 7375 | else |
dfbdccdb GK |
7376 | { |
7377 | value = CONST_DOUBLE_LOW (operands[2]); | |
7378 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7379 | immed_double_const (value | |
7380 | & (~ (HOST_WIDE_INT) 0xffff), | |
7381 | 0, DImode))); | |
7382 | } | |
e2c953b6 | 7383 | |
9ebbca7d GK |
7384 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7385 | DONE; | |
7386 | } | |
266eb58a DE |
7387 | }") |
7388 | ||
a260abc9 DE |
7389 | (define_expand "xordi3" |
7390 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7391 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7392 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7393 | "TARGET_POWERPC64" |
7394 | " | |
7395 | { | |
dfbdccdb | 7396 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7397 | { |
dfbdccdb | 7398 | HOST_WIDE_INT value; |
677a9668 | 7399 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7400 | ? operands[0] : gen_reg_rtx (DImode)); |
7401 | ||
dfbdccdb GK |
7402 | if (GET_CODE (operands[2]) == CONST_INT) |
7403 | { | |
7404 | value = INTVAL (operands[2]); | |
7405 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7406 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7407 | } | |
e2c953b6 | 7408 | else |
dfbdccdb GK |
7409 | { |
7410 | value = CONST_DOUBLE_LOW (operands[2]); | |
7411 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7412 | immed_double_const (value | |
7413 | & (~ (HOST_WIDE_INT) 0xffff), | |
7414 | 0, DImode))); | |
7415 | } | |
e2c953b6 | 7416 | |
9ebbca7d GK |
7417 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7418 | DONE; | |
7419 | } | |
a260abc9 DE |
7420 | }") |
7421 | ||
dfbdccdb | 7422 | (define_insn "*booldi3_internal1" |
266eb58a | 7423 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7424 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7425 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7426 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7427 | "TARGET_POWERPC64" |
1fd4e8c1 | 7428 | "@ |
dfbdccdb GK |
7429 | %q3 %0,%1,%2 |
7430 | %q3i %0,%1,%b2 | |
7431 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7432 | |
dfbdccdb | 7433 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7434 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7435 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7436 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7437 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7438 | (const_int 0))) | |
9ebbca7d | 7439 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7440 | "TARGET_64BIT" |
9ebbca7d | 7441 | "@ |
dfbdccdb | 7442 | %q4. %3,%1,%2 |
9ebbca7d GK |
7443 | #" |
7444 | [(set_attr "type" "compare") | |
7445 | (set_attr "length" "4,8")]) | |
7446 | ||
7447 | (define_split | |
7448 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7449 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7450 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7451 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7452 | (const_int 0))) |
9ebbca7d GK |
7453 | (clobber (match_scratch:DI 3 ""))] |
7454 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7455 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7456 | (set (match_dup 0) |
7457 | (compare:CC (match_dup 3) | |
7458 | (const_int 0)))] | |
7459 | "") | |
1fd4e8c1 | 7460 | |
dfbdccdb | 7461 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7462 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7463 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7464 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7465 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7466 | (const_int 0))) | |
9ebbca7d | 7467 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7468 | (match_dup 4))] |
683bdff7 | 7469 | "TARGET_64BIT" |
9ebbca7d | 7470 | "@ |
dfbdccdb | 7471 | %q4. %0,%1,%2 |
9ebbca7d GK |
7472 | #" |
7473 | [(set_attr "type" "compare") | |
7474 | (set_attr "length" "4,8")]) | |
7475 | ||
7476 | (define_split | |
e72247f4 | 7477 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7478 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7479 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7480 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7481 | (const_int 0))) |
75540af0 | 7482 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7483 | (match_dup 4))] |
9ebbca7d | 7484 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7485 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7486 | (set (match_dup 3) |
7487 | (compare:CC (match_dup 0) | |
7488 | (const_int 0)))] | |
7489 | "") | |
1fd4e8c1 | 7490 | |
6ae08853 | 7491 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 7492 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
7493 | |
7494 | (define_split | |
7495 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7496 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7497 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7498 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7499 | "TARGET_POWERPC64" |
dfbdccdb GK |
7500 | [(set (match_dup 0) (match_dup 4)) |
7501 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7502 | " |
7503 | { | |
dfbdccdb | 7504 | rtx i3,i4; |
6ae08853 | 7505 | |
9ebbca7d GK |
7506 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7507 | { | |
7508 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7509 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7510 | 0, DImode); |
dfbdccdb | 7511 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7512 | } |
7513 | else | |
7514 | { | |
dfbdccdb | 7515 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7516 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7517 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7518 | } |
1c563bed | 7519 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7520 | operands[1], i3); |
1c563bed | 7521 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7522 | operands[0], i4); |
1fd4e8c1 RK |
7523 | }") |
7524 | ||
dfbdccdb | 7525 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7526 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7527 | (match_operator:DI 3 "boolean_operator" |
7528 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7529 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7530 | "TARGET_POWERPC64" |
1d328b19 | 7531 | "%q3 %0,%2,%1") |
a473029f | 7532 | |
dfbdccdb | 7533 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7534 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7535 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7536 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7537 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7538 | (const_int 0))) | |
9ebbca7d | 7539 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7540 | "TARGET_64BIT" |
9ebbca7d | 7541 | "@ |
1d328b19 | 7542 | %q4. %3,%2,%1 |
9ebbca7d GK |
7543 | #" |
7544 | [(set_attr "type" "compare") | |
7545 | (set_attr "length" "4,8")]) | |
7546 | ||
7547 | (define_split | |
7548 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7549 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7550 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7551 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7552 | (const_int 0))) |
9ebbca7d GK |
7553 | (clobber (match_scratch:DI 3 ""))] |
7554 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7555 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7556 | (set (match_dup 0) |
7557 | (compare:CC (match_dup 3) | |
7558 | (const_int 0)))] | |
7559 | "") | |
a473029f | 7560 | |
dfbdccdb | 7561 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7562 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7563 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7564 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7565 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7566 | (const_int 0))) | |
9ebbca7d | 7567 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7568 | (match_dup 4))] |
683bdff7 | 7569 | "TARGET_64BIT" |
9ebbca7d | 7570 | "@ |
1d328b19 | 7571 | %q4. %0,%2,%1 |
9ebbca7d GK |
7572 | #" |
7573 | [(set_attr "type" "compare") | |
7574 | (set_attr "length" "4,8")]) | |
7575 | ||
7576 | (define_split | |
e72247f4 | 7577 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7578 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7579 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7580 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7581 | (const_int 0))) |
75540af0 | 7582 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7583 | (match_dup 4))] |
9ebbca7d | 7584 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7585 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7586 | (set (match_dup 3) |
7587 | (compare:CC (match_dup 0) | |
7588 | (const_int 0)))] | |
7589 | "") | |
266eb58a | 7590 | |
dfbdccdb | 7591 | (define_insn "*boolccdi3_internal1" |
a473029f | 7592 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7593 | (match_operator:DI 3 "boolean_operator" |
7594 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7595 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7596 | "TARGET_POWERPC64" |
dfbdccdb | 7597 | "%q3 %0,%1,%2") |
a473029f | 7598 | |
dfbdccdb | 7599 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7600 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7601 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7602 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7603 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7604 | (const_int 0))) | |
9ebbca7d | 7605 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7606 | "TARGET_64BIT" |
9ebbca7d | 7607 | "@ |
dfbdccdb | 7608 | %q4. %3,%1,%2 |
9ebbca7d GK |
7609 | #" |
7610 | [(set_attr "type" "compare") | |
7611 | (set_attr "length" "4,8")]) | |
7612 | ||
7613 | (define_split | |
7614 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7615 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7616 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7617 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7618 | (const_int 0))) |
9ebbca7d GK |
7619 | (clobber (match_scratch:DI 3 ""))] |
7620 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7621 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7622 | (set (match_dup 0) |
7623 | (compare:CC (match_dup 3) | |
7624 | (const_int 0)))] | |
7625 | "") | |
266eb58a | 7626 | |
dfbdccdb | 7627 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7628 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7629 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7630 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7631 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7632 | (const_int 0))) | |
9ebbca7d | 7633 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7634 | (match_dup 4))] |
683bdff7 | 7635 | "TARGET_64BIT" |
9ebbca7d | 7636 | "@ |
dfbdccdb | 7637 | %q4. %0,%1,%2 |
9ebbca7d GK |
7638 | #" |
7639 | [(set_attr "type" "compare") | |
7640 | (set_attr "length" "4,8")]) | |
7641 | ||
7642 | (define_split | |
e72247f4 | 7643 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7644 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7645 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7646 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7647 | (const_int 0))) |
75540af0 | 7648 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7649 | (match_dup 4))] |
9ebbca7d | 7650 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7651 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7652 | (set (match_dup 3) |
7653 | (compare:CC (match_dup 0) | |
7654 | (const_int 0)))] | |
7655 | "") | |
dfbdccdb | 7656 | \f |
1fd4e8c1 | 7657 | ;; Now define ways of moving data around. |
4697a36c MM |
7658 | |
7659 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7660 | ;; The output of this could be r0, but we make a very strong |
7661 | ;; preference for a base register because it will usually | |
7662 | ;; be needed there. | |
4697a36c | 7663 | (define_insn "elf_high" |
9ebbca7d | 7664 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7665 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7666 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7667 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7668 | |
7669 | (define_insn "elf_low" | |
9ebbca7d GK |
7670 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7671 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7672 | (match_operand 2 "" "")))] |
0ad91047 | 7673 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7674 | "@ |
7675 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7676 | {ai|addic} %0,%1,%K2") |
4697a36c | 7677 | |
ee890fe2 | 7678 | |
766a866c MM |
7679 | ;; Set up a register with a value from the GOT table |
7680 | ||
7681 | (define_expand "movsi_got" | |
52d3af72 | 7682 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7683 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
615158e2 | 7684 | (match_dup 2)] UNSPEC_MOVSI_GOT))] |
f607bc57 | 7685 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7686 | " |
7687 | { | |
38c1f2d7 MM |
7688 | if (GET_CODE (operands[1]) == CONST) |
7689 | { | |
7690 | rtx offset = const0_rtx; | |
7691 | HOST_WIDE_INT value; | |
7692 | ||
7693 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7694 | value = INTVAL (offset); | |
7695 | if (value != 0) | |
7696 | { | |
677a9668 | 7697 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7698 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7699 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7700 | DONE; | |
7701 | } | |
7702 | } | |
7703 | ||
c4c40373 | 7704 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7705 | }") |
7706 | ||
84f414bc | 7707 | (define_insn "*movsi_got_internal" |
52d3af72 | 7708 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d | 7709 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7710 | (match_operand:SI 2 "gpc_reg_operand" "b")] |
7711 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7712 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7713 | "{l|lwz} %0,%a1@got(%2)" |
7714 | [(set_attr "type" "load")]) | |
7715 | ||
b22b9b3e JL |
7716 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7717 | ;; didn't get allocated to a hard register. | |
6ae08853 | 7718 | (define_split |
75540af0 | 7719 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7720 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7721 | (match_operand:SI 2 "memory_operand" "")] |
7722 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7723 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7724 | && flag_pic == 1 |
7725 | && (reload_in_progress || reload_completed)" | |
7726 | [(set (match_dup 0) (match_dup 2)) | |
615158e2 JJ |
7727 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] |
7728 | UNSPEC_MOVSI_GOT))] | |
b22b9b3e JL |
7729 | "") |
7730 | ||
1fd4e8c1 RK |
7731 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7732 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7733 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7734 | ;; integers in the TOC. | |
7735 | (define_expand "movsi" | |
7736 | [(set (match_operand:SI 0 "general_operand" "") | |
7737 | (match_operand:SI 1 "any_operand" ""))] | |
7738 | "" | |
fb4d4348 | 7739 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7740 | |
ee890fe2 SS |
7741 | (define_insn "movsi_low" |
7742 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7743 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7744 | (match_operand 2 "" ""))))] |
7745 | "TARGET_MACHO && ! TARGET_64BIT" | |
7746 | "{l|lwz} %0,lo16(%2)(%1)" | |
7747 | [(set_attr "type" "load") | |
7748 | (set_attr "length" "4")]) | |
7749 | ||
acad7ed3 | 7750 | (define_insn "*movsi_internal1" |
165a5bad | 7751 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
a004eb82 | 7752 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] |
19d5775a RK |
7753 | "gpc_reg_operand (operands[0], SImode) |
7754 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7755 | "@ |
deb9225a | 7756 | mr %0,%1 |
b9442c72 | 7757 | {cal|la} %0,%a1 |
ca7f5001 RK |
7758 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7759 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7760 | {lil|li} %0,%1 |
802a0058 | 7761 | {liu|lis} %0,%v1 |
beaec479 | 7762 | # |
aee86b38 | 7763 | {cal|la} %0,%a1 |
1fd4e8c1 | 7764 | mf%1 %0 |
5c23c401 | 7765 | mt%0 %1 |
e76e75bb | 7766 | mt%0 %1 |
a004eb82 | 7767 | mt%0 %1 |
e34eaae5 | 7768 | {cror 0,0,0|nop}" |
02ca7595 | 7769 | [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") |
a004eb82 | 7770 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7771 | |
77fa0940 RK |
7772 | ;; Split a load of a large constant into the appropriate two-insn |
7773 | ;; sequence. | |
7774 | ||
7775 | (define_split | |
7776 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7777 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7778 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7779 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7780 | [(set (match_dup 0) | |
7781 | (match_dup 2)) | |
7782 | (set (match_dup 0) | |
7783 | (ior:SI (match_dup 0) | |
7784 | (match_dup 3)))] | |
7785 | " | |
af8cb5c5 DE |
7786 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
7787 | ||
7788 | if (tem == operands[0]) | |
7789 | DONE; | |
7790 | else | |
7791 | FAIL; | |
77fa0940 RK |
7792 | }") |
7793 | ||
acad7ed3 | 7794 | (define_insn "*movsi_internal2" |
bb84cb12 DE |
7795 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
7796 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r") | |
1fd4e8c1 | 7797 | (const_int 0))) |
bb84cb12 | 7798 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
4b8a63d6 | 7799 | "TARGET_32BIT" |
9ebbca7d | 7800 | "@ |
bb84cb12 | 7801 | {cmpi|cmpwi} %2,%0,0 |
9ebbca7d GK |
7802 | mr. %0,%1 |
7803 | #" | |
bb84cb12 DE |
7804 | [(set_attr "type" "cmp,compare,cmp") |
7805 | (set_attr "length" "4,4,8")]) | |
7806 | ||
9ebbca7d GK |
7807 | (define_split |
7808 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7809 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7810 | (const_int 0))) | |
7811 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
4b8a63d6 | 7812 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
7813 | [(set (match_dup 0) (match_dup 1)) |
7814 | (set (match_dup 2) | |
7815 | (compare:CC (match_dup 0) | |
7816 | (const_int 0)))] | |
7817 | "") | |
bb84cb12 | 7818 | \f |
1fd4e8c1 RK |
7819 | (define_expand "movhi" |
7820 | [(set (match_operand:HI 0 "general_operand" "") | |
7821 | (match_operand:HI 1 "any_operand" ""))] | |
7822 | "" | |
fb4d4348 | 7823 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 | 7824 | |
e34eaae5 | 7825 | (define_insn "*movhi_internal" |
fb81d7ce RK |
7826 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7827 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7828 | "gpc_reg_operand (operands[0], HImode) |
7829 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7830 | "@ |
deb9225a | 7831 | mr %0,%1 |
1fd4e8c1 RK |
7832 | lhz%U1%X1 %0,%1 |
7833 | sth%U0%X0 %1,%0 | |
19d5775a | 7834 | {lil|li} %0,%w1 |
1fd4e8c1 | 7835 | mf%1 %0 |
e76e75bb | 7836 | mt%0 %1 |
fb81d7ce | 7837 | mt%0 %1 |
e34eaae5 | 7838 | {cror 0,0,0|nop}" |
02ca7595 | 7839 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7840 | |
7841 | (define_expand "movqi" | |
7842 | [(set (match_operand:QI 0 "general_operand" "") | |
7843 | (match_operand:QI 1 "any_operand" ""))] | |
7844 | "" | |
fb4d4348 | 7845 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 | 7846 | |
e34eaae5 | 7847 | (define_insn "*movqi_internal" |
fb81d7ce RK |
7848 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7849 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7850 | "gpc_reg_operand (operands[0], QImode) |
7851 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7852 | "@ |
deb9225a | 7853 | mr %0,%1 |
1fd4e8c1 RK |
7854 | lbz%U1%X1 %0,%1 |
7855 | stb%U0%X0 %1,%0 | |
19d5775a | 7856 | {lil|li} %0,%1 |
1fd4e8c1 | 7857 | mf%1 %0 |
e76e75bb | 7858 | mt%0 %1 |
fb81d7ce | 7859 | mt%0 %1 |
e34eaae5 | 7860 | {cror 0,0,0|nop}" |
02ca7595 | 7861 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7862 | \f |
7863 | ;; Here is how to move condition codes around. When we store CC data in | |
7864 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7865 | ;; This lets us not shift in the most common case of CR0. | |
7866 | (define_expand "movcc" | |
7867 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7868 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7869 | "" | |
7870 | "") | |
7871 | ||
a65c591c | 7872 | (define_insn "*movcc_internal1" |
b54cf83a DE |
7873 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") |
7874 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] | |
1fd4e8c1 RK |
7875 | "register_operand (operands[0], CCmode) |
7876 | || register_operand (operands[1], CCmode)" | |
7877 | "@ | |
7878 | mcrf %0,%1 | |
7879 | mtcrf 128,%1 | |
ca7f5001 | 7880 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
2c4a9cff DE |
7881 | mfcr %0%Q1 |
7882 | mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 | |
deb9225a | 7883 | mr %0,%1 |
b54cf83a | 7884 | mf%1 %0 |
b991a865 GK |
7885 | mt%0 %1 |
7886 | mt%0 %1 | |
ca7f5001 RK |
7887 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7888 | {st%U0%U1|stw%U0%U1} %1,%0" | |
2c4a9cff DE |
7889 | [(set (attr "type") |
7890 | (cond [(eq_attr "alternative" "0") | |
7891 | (const_string "cr_logical") | |
7892 | (eq_attr "alternative" "1,2") | |
7893 | (const_string "mtcr") | |
7894 | (eq_attr "alternative" "5,7") | |
7895 | (const_string "integer") | |
7896 | (eq_attr "alternative" "6") | |
7897 | (const_string "mfjmpr") | |
7898 | (eq_attr "alternative" "8") | |
7899 | (const_string "mtjmpr") | |
7900 | (eq_attr "alternative" "9") | |
7901 | (const_string "load") | |
7902 | (eq_attr "alternative" "10") | |
7903 | (const_string "store") | |
7904 | (ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
7905 | (const_string "mfcrf") | |
7906 | ] | |
7907 | (const_string "mfcr"))) | |
b991a865 | 7908 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7909 | \f |
e52e05ca MM |
7910 | ;; For floating-point, we normally deal with the floating-point registers |
7911 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7912 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7913 | ;; value is a simple constant or already in memory, we deal with this by | |
7914 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7915 | (define_expand "movsf" |
7916 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7917 | (match_operand:SF 1 "any_operand" ""))] | |
7918 | "" | |
fb4d4348 | 7919 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7920 | |
1fd4e8c1 | 7921 | (define_split |
cd2b37d9 | 7922 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7923 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7924 | "reload_completed |
5ae4759c MM |
7925 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7926 | || (GET_CODE (operands[0]) == SUBREG | |
7927 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7928 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7929 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7930 | " |
7931 | { | |
7932 | long l; | |
7933 | REAL_VALUE_TYPE rv; | |
7934 | ||
7935 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7936 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7937 | |
f99f88e0 DE |
7938 | if (! TARGET_POWERPC64) |
7939 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7940 | else | |
7941 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7942 | |
2496c7bd | 7943 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7944 | }") |
7945 | ||
c4c40373 | 7946 | (define_insn "*movsf_hardfloat" |
ae6669e7 DJ |
7947 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r") |
7948 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] | |
d14a6d05 | 7949 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7950 | || gpc_reg_operand (operands[1], SFmode)) |
7951 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 7952 | "@ |
f99f88e0 DE |
7953 | mr %0,%1 |
7954 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7955 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7956 | fmr %0,%1 |
7957 | lfs%U1%X1 %0,%1 | |
c4c40373 | 7958 | stfs%U0%X0 %1,%0 |
b991a865 GK |
7959 | mt%0 %1 |
7960 | mt%0 %1 | |
7961 | mf%1 %0 | |
e0740893 | 7962 | {cror 0,0,0|nop} |
c4c40373 MM |
7963 | # |
7964 | #" | |
ae6669e7 DJ |
7965 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*") |
7966 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7967 | |
c4c40373 | 7968 | (define_insn "*movsf_softfloat" |
dd0fbae2 MK |
7969 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") |
7970 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
d14a6d05 | 7971 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7972 | || gpc_reg_operand (operands[1], SFmode)) |
7973 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
7974 | "@ |
7975 | mr %0,%1 | |
b991a865 GK |
7976 | mt%0 %1 |
7977 | mt%0 %1 | |
7978 | mf%1 %0 | |
d14a6d05 MM |
7979 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7980 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7981 | {lil|li} %0,%1 | |
802a0058 | 7982 | {liu|lis} %0,%v1 |
aee86b38 | 7983 | {cal|la} %0,%a1 |
c4c40373 | 7984 | # |
dd0fbae2 MK |
7985 | # |
7986 | {cror 0,0,0|nop}" | |
7987 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") | |
7988 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
d14a6d05 | 7989 | |
1fd4e8c1 RK |
7990 | \f |
7991 | (define_expand "movdf" | |
7992 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7993 | (match_operand:DF 1 "any_operand" ""))] | |
7994 | "" | |
fb4d4348 | 7995 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7996 | |
7997 | (define_split | |
cd2b37d9 | 7998 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7999 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 8000 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8001 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8002 | || (GET_CODE (operands[0]) == SUBREG | |
8003 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8004 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
8005 | [(set (match_dup 2) (match_dup 4)) |
8006 | (set (match_dup 3) (match_dup 1))] | |
8007 | " | |
8008 | { | |
5ae4759c | 8009 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
8010 | HOST_WIDE_INT value = INTVAL (operands[1]); |
8011 | ||
5ae4759c MM |
8012 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
8013 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
8014 | #if HOST_BITS_PER_WIDE_INT == 32 |
8015 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
8016 | #else | |
8017 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 8018 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 8019 | #endif |
c4c40373 MM |
8020 | }") |
8021 | ||
c4c40373 MM |
8022 | (define_split |
8023 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
8024 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 8025 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8026 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8027 | || (GET_CODE (operands[0]) == SUBREG | |
8028 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8029 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
8030 | [(set (match_dup 2) (match_dup 4)) |
8031 | (set (match_dup 3) (match_dup 5))] | |
8032 | " | |
8033 | { | |
5ae4759c | 8034 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
8035 | long l[2]; |
8036 | REAL_VALUE_TYPE rv; | |
8037 | ||
8038 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8039 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8040 | ||
5ae4759c MM |
8041 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
8042 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
8043 | operands[4] = gen_int_mode (l[endian], SImode); |
8044 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
8045 | }") |
8046 | ||
efc08378 DE |
8047 | (define_split |
8048 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 8049 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 8050 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8051 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8052 | || (GET_CODE (operands[0]) == SUBREG | |
8053 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8054 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 8055 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 8056 | " |
a260abc9 DE |
8057 | { |
8058 | int endian = (WORDS_BIG_ENDIAN == 0); | |
8059 | long l[2]; | |
8060 | REAL_VALUE_TYPE rv; | |
4977bab6 | 8061 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 8062 | HOST_WIDE_INT val; |
4977bab6 | 8063 | #endif |
a260abc9 DE |
8064 | |
8065 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8066 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8067 | ||
8068 | operands[2] = gen_lowpart (DImode, operands[0]); | |
8069 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 8070 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
8071 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
8072 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 8073 | |
f5264b52 | 8074 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 8075 | #else |
a260abc9 | 8076 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 8077 | #endif |
a260abc9 | 8078 | }") |
efc08378 | 8079 | |
4eae5fe1 | 8080 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 8081 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
8082 | ;; a non-offsettable memref, but also it is less efficient than loading |
8083 | ;; the constant into an FP register, since it will probably be used there. | |
8084 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
8085 | ;; of handling these non-offsettable values. | |
c4c40373 | 8086 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
8087 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
8088 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 8089 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8090 | && (gpc_reg_operand (operands[0], DFmode) |
8091 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
8092 | "* |
8093 | { | |
8094 | switch (which_alternative) | |
8095 | { | |
a260abc9 | 8096 | default: |
a6c2a102 | 8097 | abort (); |
e7113111 RK |
8098 | case 0: |
8099 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
8100 | the first register operand 0 is the same as the second register |
8101 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 8102 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 8103 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 8104 | else |
deb9225a | 8105 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 8106 | case 1: |
819e019c EC |
8107 | if (GET_CODE (operands[1]) == MEM |
8108 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0), | |
8109 | reload_completed || reload_in_progress) | |
8110 | || GET_CODE (XEXP (operands[1], 0)) == REG | |
8111 | || GET_CODE (XEXP (operands[1], 0)) == LO_SUM | |
69f51a21 | 8112 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC |
819e019c | 8113 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) |
000034eb DE |
8114 | { |
8115 | /* If the low-address word is used in the address, we must load | |
8116 | it last. Otherwise, load it first. Note that we cannot have | |
8117 | auto-increment in that case since the address register is | |
8118 | known to be dead. */ | |
8119 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8120 | operands[1], 0)) | |
8121 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
8122 | else | |
8123 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8124 | } | |
e7113111 | 8125 | else |
000034eb DE |
8126 | { |
8127 | rtx addreg; | |
8128 | ||
000034eb DE |
8129 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
8130 | if (refers_to_regno_p (REGNO (operands[0]), | |
8131 | REGNO (operands[0]) + 1, | |
8132 | operands[1], 0)) | |
8133 | { | |
8134 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 8135 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 8136 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 8137 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
8138 | } |
8139 | else | |
8140 | { | |
2b97222d | 8141 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 8142 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8143 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
8144 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8145 | return \"\"; | |
8146 | } | |
8147 | } | |
e7113111 | 8148 | case 2: |
819e019c EC |
8149 | if (GET_CODE (operands[0]) == MEM |
8150 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0), | |
8151 | reload_completed || reload_in_progress) | |
8152 | || GET_CODE (XEXP (operands[0], 0)) == REG | |
8153 | || GET_CODE (XEXP (operands[0], 0)) == LO_SUM | |
69f51a21 | 8154 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC |
819e019c | 8155 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)) |
000034eb DE |
8156 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8157 | else | |
8158 | { | |
8159 | rtx addreg; | |
8160 | ||
000034eb | 8161 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8162 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8163 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8164 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8165 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8166 | return \"\"; | |
8167 | } | |
e7113111 | 8168 | case 3: |
914a7297 | 8169 | return \"fmr %0,%1\"; |
e7113111 | 8170 | case 4: |
914a7297 | 8171 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 8172 | case 5: |
914a7297 | 8173 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 8174 | case 6: |
c4c40373 | 8175 | case 7: |
c4c40373 | 8176 | case 8: |
914a7297 | 8177 | return \"#\"; |
e7113111 RK |
8178 | } |
8179 | }" | |
943c15ed | 8180 | [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") |
914a7297 | 8181 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) |
51b8fc2c | 8182 | |
c4c40373 | 8183 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8184 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8185 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
7a2f7870 | 8186 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) |
52d3af72 DE |
8187 | && (gpc_reg_operand (operands[0], DFmode) |
8188 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8189 | "* |
8190 | { | |
8191 | switch (which_alternative) | |
8192 | { | |
a260abc9 | 8193 | default: |
a6c2a102 | 8194 | abort (); |
dc4f83ca MM |
8195 | case 0: |
8196 | /* We normally copy the low-numbered register first. However, if | |
8197 | the first register operand 0 is the same as the second register of | |
8198 | operand 1, we must copy in the opposite order. */ | |
8199 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8200 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8201 | else | |
8202 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8203 | case 1: | |
3cb999d8 DE |
8204 | /* If the low-address word is used in the address, we must load |
8205 | it last. Otherwise, load it first. Note that we cannot have | |
8206 | auto-increment in that case since the address register is | |
8207 | known to be dead. */ | |
dc4f83ca | 8208 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8209 | operands[1], 0)) |
dc4f83ca MM |
8210 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8211 | else | |
8212 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8213 | case 2: | |
8214 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8215 | case 3: | |
c4c40373 MM |
8216 | case 4: |
8217 | case 5: | |
dc4f83ca MM |
8218 | return \"#\"; |
8219 | } | |
8220 | }" | |
943c15ed | 8221 | [(set_attr "type" "two,load,store,*,*,*") |
c4c40373 | 8222 | (set_attr "length" "8,8,8,8,12,16")]) |
dc4f83ca | 8223 | |
d2288d5d HP |
8224 | ; ld/std require word-aligned displacements -> 'Y' constraint. |
8225 | ; List Y->r and r->Y before r->r for reload. | |
c4c40373 | 8226 | (define_insn "*movdf_hardfloat64" |
ae6669e7 DJ |
8227 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r") |
8228 | (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] | |
a3170dc6 | 8229 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8230 | && (gpc_reg_operand (operands[0], DFmode) |
8231 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8232 | "@ |
96bb8ed3 | 8233 | std%U0%X0 %1,%0 |
3364872d FJ |
8234 | ld%U1%X1 %0,%1 |
8235 | mr %0,%1 | |
3d5570cb | 8236 | fmr %0,%1 |
f63184ac | 8237 | lfd%U1%X1 %0,%1 |
914a7297 DE |
8238 | stfd%U0%X0 %1,%0 |
8239 | mt%0 %1 | |
8240 | mf%1 %0 | |
e0740893 | 8241 | {cror 0,0,0|nop} |
914a7297 DE |
8242 | # |
8243 | # | |
8244 | #" | |
ae6669e7 DJ |
8245 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*") |
8246 | (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 8247 | |
c4c40373 | 8248 | (define_insn "*movdf_softfloat64" |
d2288d5d HP |
8249 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") |
8250 | (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] | |
a3170dc6 | 8251 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8252 | && (gpc_reg_operand (operands[0], DFmode) |
8253 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca | 8254 | "@ |
d2288d5d HP |
8255 | ld%U1%X1 %0,%1 |
8256 | std%U0%X0 %1,%0 | |
dc4f83ca | 8257 | mr %0,%1 |
914a7297 DE |
8258 | mt%0 %1 |
8259 | mf%1 %0 | |
c4c40373 MM |
8260 | # |
8261 | # | |
e2d0915c | 8262 | # |
e0740893 | 8263 | {cror 0,0,0|nop}" |
d2288d5d | 8264 | [(set_attr "type" "load,store,*,*,*,*,*,*,*") |
e2d0915c | 8265 | (set_attr "length" "4,4,4,4,4,8,12,16,4")]) |
1fd4e8c1 | 8266 | \f |
06f4e019 DE |
8267 | (define_expand "movtf" |
8268 | [(set (match_operand:TF 0 "general_operand" "") | |
8269 | (match_operand:TF 1 "any_operand" ""))] | |
39e63627 GK |
8270 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8271 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8272 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
8273 | ||
a9baceb1 GK |
8274 | ; It's important to list the o->f and f->o moves before f->f because |
8275 | ; otherwise reload, given m->f, will try to pick f->f and reload it, | |
409f61cd | 8276 | ; which doesn't make progress. Likewise r->Y must be before r->r. |
a9baceb1 | 8277 | (define_insn_and_split "*movtf_internal" |
409f61cd AM |
8278 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r") |
8279 | (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))] | |
39e63627 GK |
8280 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8281 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
8282 | && (gpc_reg_operand (operands[0], TFmode) |
8283 | || gpc_reg_operand (operands[1], TFmode))" | |
a9baceb1 | 8284 | "#" |
ecb62ae7 | 8285 | "&& reload_completed" |
a9baceb1 GK |
8286 | [(pc)] |
8287 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } | |
112ccb83 | 8288 | [(set_attr "length" "8,8,8,20,20,16")]) |
06f4e019 | 8289 | |
ecb62ae7 GK |
8290 | (define_expand "extenddftf2" |
8291 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8292 | (float_extend:TF (match_operand:DF 1 "input_operand" ""))) | |
8293 | (use (match_dup 2))])] | |
39e63627 GK |
8294 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8295 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8296 | { |
ecb62ae7 GK |
8297 | operands[2] = CONST0_RTX (DFmode); |
8298 | }) | |
06f4e019 | 8299 | |
ecb62ae7 GK |
8300 | (define_insn_and_split "*extenddftf2_internal" |
8301 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") | |
8302 | (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) | |
8303 | (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))] | |
39e63627 GK |
8304 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8305 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8306 | "#" |
8307 | "&& reload_completed" | |
8308 | [(pc)] | |
06f4e019 | 8309 | { |
ecb62ae7 GK |
8310 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; |
8311 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
8312 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), | |
8313 | operands[1]); | |
8314 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), | |
8315 | operands[2]); | |
8316 | DONE; | |
6ae08853 | 8317 | }) |
ecb62ae7 GK |
8318 | |
8319 | (define_expand "extendsftf2" | |
8320 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8321 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
8322 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8323 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8324 | { | |
8325 | rtx tmp = gen_reg_rtx (DFmode); | |
8326 | emit_insn (gen_extendsfdf2 (tmp, operands[1])); | |
8327 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8328 | DONE; | |
8329 | }) | |
06f4e019 | 8330 | |
8cb320b8 | 8331 | (define_expand "trunctfdf2" |
589b3fda DE |
8332 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
8333 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))] | |
39e63627 GK |
8334 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8335 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
589b3fda | 8336 | "") |
8cb320b8 DE |
8337 | |
8338 | (define_insn_and_split "trunctfdf2_internal1" | |
8339 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") | |
8340 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))] | |
8341 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT | |
8342 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8343 | "@ | |
8344 | # | |
8345 | fmr %0,%1" | |
8346 | "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" | |
8347 | [(const_int 0)] | |
8348 | { | |
8349 | emit_note (NOTE_INSN_DELETED); | |
8350 | DONE; | |
8351 | } | |
8352 | [(set_attr "type" "fp")]) | |
8353 | ||
8354 | (define_insn "trunctfdf2_internal2" | |
8355 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8356 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
8357 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT | |
8358 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8359 | "fadd %0,%1,%L1" |
8cb320b8 | 8360 | [(set_attr "type" "fp")]) |
06f4e019 DE |
8361 | |
8362 | (define_insn_and_split "trunctfsf2" | |
8363 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
8364 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8365 | (clobber (match_scratch:DF 2 "=f"))] | |
39e63627 GK |
8366 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8367 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8368 | "#" |
ea112fc4 | 8369 | "&& reload_completed" |
06f4e019 DE |
8370 | [(set (match_dup 2) |
8371 | (float_truncate:DF (match_dup 1))) | |
8372 | (set (match_dup 0) | |
8373 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 8374 | "") |
06f4e019 | 8375 | |
0c90aa3c | 8376 | (define_expand "floatsitf2" |
ea112fc4 | 8377 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
0c90aa3c | 8378 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))] |
39e63627 GK |
8379 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8380 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
0c90aa3c GK |
8381 | { |
8382 | rtx tmp = gen_reg_rtx (DFmode); | |
8383 | expand_float (tmp, operands[1], false); | |
8384 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8385 | DONE; | |
8386 | }) | |
06f4e019 | 8387 | |
ecb62ae7 GK |
8388 | ; fadd, but rounding towards zero. |
8389 | ; This is probably not the optimal code sequence. | |
8390 | (define_insn "fix_trunc_helper" | |
8391 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8392 | (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] | |
8393 | UNSPEC_FIX_TRUNC_TF)) | |
8394 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] | |
8395 | "TARGET_HARD_FLOAT && TARGET_FPRS" | |
8396 | "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" | |
8397 | [(set_attr "type" "fp") | |
8398 | (set_attr "length" "20")]) | |
8399 | ||
0c90aa3c | 8400 | (define_expand "fix_trunctfsi2" |
ecb62ae7 GK |
8401 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
8402 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) | |
8403 | (clobber (match_dup 2)) | |
8404 | (clobber (match_dup 3)) | |
8405 | (clobber (match_dup 4)) | |
8406 | (clobber (match_dup 5))])] | |
8407 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8408 | && (TARGET_POWER2 || TARGET_POWERPC) | |
8409 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8410 | { | |
8411 | operands[2] = gen_reg_rtx (DFmode); | |
8412 | operands[3] = gen_reg_rtx (DFmode); | |
8413 | operands[4] = gen_reg_rtx (DImode); | |
8414 | operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
8415 | }) | |
8416 | ||
8417 | (define_insn_and_split "*fix_trunctfsi2_internal" | |
61c07d3c | 8418 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ecb62ae7 GK |
8419 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8420 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) | |
8421 | (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) | |
8422 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) | |
8423 | (clobber (match_operand:DI 5 "memory_operand" "=o"))] | |
39e63627 GK |
8424 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8425 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8426 | "#" |
8427 | "&& reload_completed" | |
8428 | [(pc)] | |
0c90aa3c | 8429 | { |
ecb62ae7 GK |
8430 | rtx lowword; |
8431 | emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); | |
8432 | ||
8433 | if (GET_CODE (operands[5]) != MEM) | |
8434 | abort(); | |
8435 | lowword = XEXP (operands[5], 0); | |
8436 | if (WORDS_BIG_ENDIAN) | |
8437 | lowword = plus_constant (lowword, 4); | |
8438 | ||
8439 | emit_insn (gen_fctiwz (operands[4], operands[2])); | |
8440 | emit_move_insn (operands[5], operands[4]); | |
8441 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
0c90aa3c GK |
8442 | DONE; |
8443 | }) | |
06f4e019 DE |
8444 | |
8445 | (define_insn "negtf2" | |
8446 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8447 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8448 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8449 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8450 | "* |
8451 | { | |
8452 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8453 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8454 | else | |
8455 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8456 | }" | |
8457 | [(set_attr "type" "fp") | |
8458 | (set_attr "length" "8")]) | |
8459 | ||
1a402dc1 | 8460 | (define_expand "abstf2" |
06f4e019 DE |
8461 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8462 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8463 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8464 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8465 | " |
06f4e019 | 8466 | { |
1a402dc1 AM |
8467 | rtx label = gen_label_rtx (); |
8468 | emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); | |
8469 | emit_label (label); | |
8470 | DONE; | |
8471 | }") | |
06f4e019 | 8472 | |
1a402dc1 | 8473 | (define_expand "abstf2_internal" |
06f4e019 | 8474 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
1a402dc1 AM |
8475 | (match_operand:TF 1 "gpc_reg_operand" "f")) |
8476 | (set (match_dup 3) (match_dup 5)) | |
8477 | (set (match_dup 5) (abs:DF (match_dup 5))) | |
8478 | (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) | |
8479 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
8480 | (label_ref (match_operand 2 "" "")) | |
8481 | (pc))) | |
8482 | (set (match_dup 6) (neg:DF (match_dup 6)))] | |
39e63627 GK |
8483 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8484 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8485 | " |
06f4e019 | 8486 | { |
1a402dc1 AM |
8487 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); |
8488 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
8489 | operands[3] = gen_reg_rtx (DFmode); | |
8490 | operands[4] = gen_reg_rtx (CCFPmode); | |
8491 | operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
8492 | operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
8493 | }") | |
ca58f2bc RH |
8494 | |
8495 | (define_expand "copysigntf3" | |
8496 | [(match_operand:TF 0 "general_operand" "") | |
8497 | (match_operand:TF 1 "general_operand" "") | |
8498 | (match_operand:TF 2 "general_operand" "")] | |
8499 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8500 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8501 | { | |
8502 | rtx target, op0, op1, temp; | |
8503 | bool op0_is_abs = false; | |
8504 | ||
8505 | target = operands[0]; | |
8506 | op0 = operands[1]; | |
8507 | op1 = operands[2]; | |
8508 | ||
8509 | if (GET_CODE (op0) == CONST_DOUBLE) | |
8510 | { | |
8511 | if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0))) | |
8512 | op0 = simplify_unary_operation (ABS, TFmode, op0, TFmode); | |
8513 | op0_is_abs = true; | |
8514 | } | |
8515 | ||
8516 | temp = expand_copysign_absneg (TFmode, op0, op1, target, 127, op0_is_abs); | |
8517 | if (temp != target) | |
8518 | emit_move_insn (target, temp); | |
8519 | DONE; | |
8520 | }) | |
06f4e019 | 8521 | \f |
1fd4e8c1 RK |
8522 | ;; Next come the multi-word integer load and store and the load and store |
8523 | ;; multiple insns. | |
8524 | (define_expand "movdi" | |
8525 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8526 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 8527 | "" |
fb4d4348 | 8528 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 8529 | |
112ccb83 GK |
8530 | ; List r->r after r->"o<>", otherwise reload will try to reload a |
8531 | ; non-offsettable address by using r->r which won't make progress. | |
acad7ed3 | 8532 | (define_insn "*movdi_internal32" |
343f6bbf | 8533 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r") |
112ccb83 | 8534 | (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] |
a260abc9 | 8535 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8536 | && (gpc_reg_operand (operands[0], DImode) |
8537 | || gpc_reg_operand (operands[1], DImode))" | |
112ccb83 GK |
8538 | "@ |
8539 | # | |
8540 | # | |
8541 | # | |
8542 | fmr %0,%1 | |
8543 | lfd%U1%X1 %0,%1 | |
8544 | stfd%U0%X0 %1,%0 | |
8545 | #" | |
8546 | [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")]) | |
4e74d8ec MM |
8547 | |
8548 | (define_split | |
8549 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8550 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8551 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8552 | [(set (match_dup 2) (match_dup 4)) |
8553 | (set (match_dup 3) (match_dup 1))] | |
8554 | " | |
8555 | { | |
5f59ecb7 | 8556 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8557 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8558 | DImode); | |
8559 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8560 | DImode); | |
75d39459 | 8561 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8562 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8563 | #else |
5f59ecb7 | 8564 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8565 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8566 | #endif |
4e74d8ec MM |
8567 | }") |
8568 | ||
3a1f863f DE |
8569 | (define_split |
8570 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8571 | (match_operand:DI 1 "input_operand" ""))] | |
6ae08853 | 8572 | "reload_completed && !TARGET_POWERPC64 |
3a1f863f | 8573 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8574 | [(pc)] |
8575 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
3a1f863f | 8576 | |
acad7ed3 | 8577 | (define_insn "*movdi_internal64" |
343f6bbf | 8578 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h") |
9615f239 | 8579 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8580 | "TARGET_POWERPC64 |
4e74d8ec MM |
8581 | && (gpc_reg_operand (operands[0], DImode) |
8582 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8583 | "@ |
3d5570cb RK |
8584 | mr %0,%1 |
8585 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8586 | std%U0%X0 %1,%0 |
3d5570cb | 8587 | li %0,%1 |
802a0058 | 8588 | lis %0,%v1 |
e6ca2c17 | 8589 | # |
aee86b38 | 8590 | {cal|la} %0,%a1 |
3d5570cb RK |
8591 | fmr %0,%1 |
8592 | lfd%U1%X1 %0,%1 | |
8593 | stfd%U0%X0 %1,%0 | |
8594 | mf%1 %0 | |
08075ead | 8595 | mt%0 %1 |
e34eaae5 | 8596 | {cror 0,0,0|nop}" |
02ca7595 | 8597 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") |
e6ca2c17 DE |
8598 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8599 | ||
5f59ecb7 | 8600 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8601 | (define_insn "" |
8602 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8603 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8604 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8605 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8606 | && num_insns_constant (operands[1], DImode) == 1" |
8607 | "* | |
8608 | { | |
8609 | return ((unsigned HOST_WIDE_INT) | |
8610 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8611 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8612 | }") | |
8613 | ||
a260abc9 DE |
8614 | ;; Generate all one-bits and clear left or right. |
8615 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8616 | (define_split | |
8617 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8618 | (match_operand:DI 1 "mask64_operand" ""))] | |
8619 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8620 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8621 | (set (match_dup 0) |
a260abc9 DE |
8622 | (and:DI (rotate:DI (match_dup 0) |
8623 | (const_int 0)) | |
8624 | (match_dup 1)))] | |
8625 | "") | |
8626 | ||
8627 | ;; Split a load of a large constant into the appropriate five-instruction | |
8628 | ;; sequence. Handle anything in a constant number of insns. | |
8629 | ;; When non-easy constants can go in the TOC, this should use | |
8630 | ;; easy_fp_constant predicate. | |
8631 | (define_split | |
8632 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8633 | (match_operand:DI 1 "const_int_operand" ""))] |
8634 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8635 | [(set (match_dup 0) (match_dup 2)) | |
8636 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8637 | " |
2bfcf297 DB |
8638 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8639 | ||
8640 | if (tem == operands[0]) | |
8641 | DONE; | |
e8d791dd | 8642 | else |
2bfcf297 | 8643 | FAIL; |
5f59ecb7 | 8644 | }") |
e6ca2c17 | 8645 | |
5f59ecb7 DE |
8646 | (define_split |
8647 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8648 | (match_operand:DI 1 "const_double_operand" ""))] |
8649 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8650 | [(set (match_dup 0) (match_dup 2)) | |
8651 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8652 | " |
2bfcf297 DB |
8653 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8654 | ||
8655 | if (tem == operands[0]) | |
8656 | DONE; | |
8657 | else | |
8658 | FAIL; | |
e6ca2c17 | 8659 | }") |
08075ead | 8660 | |
acad7ed3 | 8661 | (define_insn "*movdi_internal2" |
bb84cb12 DE |
8662 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
8663 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r") | |
08075ead | 8664 | (const_int 0))) |
bb84cb12 | 8665 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
683bdff7 | 8666 | "TARGET_64BIT" |
9ebbca7d | 8667 | "@ |
bb84cb12 | 8668 | cmpdi %2,%0,0 |
9ebbca7d GK |
8669 | mr. %0,%1 |
8670 | #" | |
bb84cb12 DE |
8671 | [(set_attr "type" "cmp,compare,cmp") |
8672 | (set_attr "length" "4,4,8")]) | |
acad7ed3 | 8673 | |
9ebbca7d GK |
8674 | (define_split |
8675 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8676 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8677 | (const_int 0))) | |
8678 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8679 | "TARGET_POWERPC64 && reload_completed" | |
8680 | [(set (match_dup 0) (match_dup 1)) | |
8681 | (set (match_dup 2) | |
8682 | (compare:CC (match_dup 0) | |
8683 | (const_int 0)))] | |
8684 | "") | |
acad7ed3 | 8685 | \f |
1fd4e8c1 RK |
8686 | ;; TImode is similar, except that we usually want to compute the address into |
8687 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8688 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8689 | (define_expand "movti" |
8690 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8691 | (match_operand:TI 1 "general_operand" "")) | |
8692 | (clobber (scratch:SI))])] | |
3a1f863f | 8693 | "" |
fb4d4348 | 8694 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8695 | |
8696 | ;; We say that MQ is clobbered in the last alternative because the first | |
8697 | ;; alternative would never get used otherwise since it would need a reload | |
8698 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8699 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8700 | ;; giving the SCRATCH mq. | |
3a1f863f | 8701 | |
a260abc9 | 8702 | (define_insn "*movti_power" |
7f514158 AM |
8703 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r") |
8704 | (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n")) | |
8705 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))] | |
6ae08853 | 8706 | "TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8707 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8708 | "* |
8709 | { | |
8710 | switch (which_alternative) | |
8711 | { | |
dc4f83ca MM |
8712 | default: |
8713 | abort (); | |
8714 | ||
1fd4e8c1 | 8715 | case 0: |
3a1f863f DE |
8716 | if (TARGET_STRING) |
8717 | return \"{stsi|stswi} %1,%P0,16\"; | |
1fd4e8c1 | 8718 | case 1: |
1fd4e8c1 | 8719 | case 2: |
3a1f863f | 8720 | return \"#\"; |
1fd4e8c1 RK |
8721 | case 3: |
8722 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8723 | fall through to generating four loads. */ | |
e876481c DE |
8724 | if (TARGET_STRING |
8725 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8726 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8727 | /* ... fall through ... */ |
1fd4e8c1 | 8728 | case 4: |
7f514158 | 8729 | case 5: |
3a1f863f | 8730 | return \"#\"; |
1fd4e8c1 RK |
8731 | } |
8732 | }" | |
7f514158 | 8733 | [(set_attr "type" "store,store,*,load,load,*")]) |
51b8fc2c | 8734 | |
a260abc9 | 8735 | (define_insn "*movti_string" |
7f514158 AM |
8736 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r") |
8737 | (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))] | |
3a1f863f | 8738 | "! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8739 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8740 | "* | |
8741 | { | |
8742 | switch (which_alternative) | |
8743 | { | |
8744 | default: | |
8745 | abort (); | |
dc4f83ca | 8746 | case 0: |
3a1f863f DE |
8747 | if (TARGET_STRING) |
8748 | return \"{stsi|stswi} %1,%P0,16\"; | |
dc4f83ca | 8749 | case 1: |
cd1d3445 | 8750 | case 2: |
3a1f863f | 8751 | return \"#\"; |
cd1d3445 DE |
8752 | case 3: |
8753 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8754 | fall through to generating four loads. */ | |
6ae08853 | 8755 | if (TARGET_STRING |
3a1f863f | 8756 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) |
cd1d3445 DE |
8757 | return \"{lsi|lswi} %0,%P1,16\"; |
8758 | /* ... fall through ... */ | |
8759 | case 4: | |
7f514158 | 8760 | case 5: |
3a1f863f | 8761 | return \"#\"; |
dc4f83ca MM |
8762 | } |
8763 | }" | |
7f514158 | 8764 | [(set_attr "type" "store,store,*,load,load,*")]) |
dc4f83ca | 8765 | |
a260abc9 | 8766 | (define_insn "*movti_ppc64" |
112ccb83 GK |
8767 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") |
8768 | (match_operand:TI 1 "input_operand" "r,r,m"))] | |
51b8fc2c RK |
8769 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) |
8770 | || gpc_reg_operand (operands[1], TImode))" | |
112ccb83 | 8771 | "#" |
3a1f863f DE |
8772 | [(set_attr "type" "*,load,store")]) |
8773 | ||
7f514158 AM |
8774 | (define_split |
8775 | [(set (match_operand:TI 0 "gpc_reg_operand" "") | |
8776 | (match_operand:TI 1 "const_double_operand" ""))] | |
8777 | "TARGET_POWERPC64" | |
8778 | [(set (match_dup 2) (match_dup 4)) | |
8779 | (set (match_dup 3) (match_dup 5))] | |
8780 | " | |
8781 | { | |
8782 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, | |
8783 | TImode); | |
8784 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8785 | TImode); | |
8786 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
8787 | { | |
8788 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8789 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8790 | } | |
8791 | else if (GET_CODE (operands[1]) == CONST_INT) | |
8792 | { | |
8793 | operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); | |
8794 | operands[5] = operands[1]; | |
8795 | } | |
8796 | else | |
8797 | FAIL; | |
8798 | }") | |
8799 | ||
3a1f863f DE |
8800 | (define_split |
8801 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
8802 | (match_operand:TI 1 "input_operand" ""))] | |
a9baceb1 | 8803 | "reload_completed |
3a1f863f | 8804 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8805 | [(pc)] |
8806 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
1fd4e8c1 RK |
8807 | \f |
8808 | (define_expand "load_multiple" | |
2f622005 RK |
8809 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8810 | (match_operand:SI 1 "" "")) | |
8811 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8812 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8813 | " |
8814 | { | |
8815 | int regno; | |
8816 | int count; | |
792760b9 | 8817 | rtx op1; |
1fd4e8c1 RK |
8818 | int i; |
8819 | ||
8820 | /* Support only loading a constant number of fixed-point registers from | |
8821 | memory and only bother with this if more than two; the machine | |
8822 | doesn't support more than eight. */ | |
8823 | if (GET_CODE (operands[2]) != CONST_INT | |
8824 | || INTVAL (operands[2]) <= 2 | |
8825 | || INTVAL (operands[2]) > 8 | |
8826 | || GET_CODE (operands[1]) != MEM | |
8827 | || GET_CODE (operands[0]) != REG | |
8828 | || REGNO (operands[0]) >= 32) | |
8829 | FAIL; | |
8830 | ||
8831 | count = INTVAL (operands[2]); | |
8832 | regno = REGNO (operands[0]); | |
8833 | ||
39403d82 | 8834 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8835 | op1 = replace_equiv_address (operands[1], |
8836 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8837 | |
8838 | for (i = 0; i < count; i++) | |
8839 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8840 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 8841 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8842 | }") |
8843 | ||
9caa3eb2 | 8844 | (define_insn "*ldmsi8" |
1fd4e8c1 | 8845 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
8846 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
8847 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8848 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8849 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8850 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8851 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8852 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8853 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8854 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8855 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8856 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8857 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8858 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8859 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
8860 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
8861 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
8862 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 8863 | "* |
9caa3eb2 DE |
8864 | { return rs6000_output_load_multiple (operands); }" |
8865 | [(set_attr "type" "load") | |
8866 | (set_attr "length" "32")]) | |
1fd4e8c1 | 8867 | |
9caa3eb2 DE |
8868 | (define_insn "*ldmsi7" |
8869 | [(match_parallel 0 "load_multiple_operation" | |
8870 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8871 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8872 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8873 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8874 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8875 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8876 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8877 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8878 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8879 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8880 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8881 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8882 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8883 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
8884 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
8885 | "* | |
8886 | { return rs6000_output_load_multiple (operands); }" | |
8887 | [(set_attr "type" "load") | |
8888 | (set_attr "length" "32")]) | |
8889 | ||
8890 | (define_insn "*ldmsi6" | |
8891 | [(match_parallel 0 "load_multiple_operation" | |
8892 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8893 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8894 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8895 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8896 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8897 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8898 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8899 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8900 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8901 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8902 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8903 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
8904 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
8905 | "* | |
8906 | { return rs6000_output_load_multiple (operands); }" | |
8907 | [(set_attr "type" "load") | |
8908 | (set_attr "length" "32")]) | |
8909 | ||
8910 | (define_insn "*ldmsi5" | |
8911 | [(match_parallel 0 "load_multiple_operation" | |
8912 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8913 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8914 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8915 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8916 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8917 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8918 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8919 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8920 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8921 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
8922 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
8923 | "* | |
8924 | { return rs6000_output_load_multiple (operands); }" | |
8925 | [(set_attr "type" "load") | |
8926 | (set_attr "length" "32")]) | |
8927 | ||
8928 | (define_insn "*ldmsi4" | |
8929 | [(match_parallel 0 "load_multiple_operation" | |
8930 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8931 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8932 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8933 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8934 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8935 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8936 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8937 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
8938 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
8939 | "* | |
8940 | { return rs6000_output_load_multiple (operands); }" | |
8941 | [(set_attr "type" "load") | |
8942 | (set_attr "length" "32")]) | |
8943 | ||
8944 | (define_insn "*ldmsi3" | |
8945 | [(match_parallel 0 "load_multiple_operation" | |
8946 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8947 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8948 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8949 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8950 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8951 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
8952 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
8953 | "* | |
8954 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 8955 | [(set_attr "type" "load") |
e82ee4cc | 8956 | (set_attr "length" "32")]) |
b19003d8 | 8957 | |
1fd4e8c1 | 8958 | (define_expand "store_multiple" |
2f622005 RK |
8959 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8960 | (match_operand:SI 1 "" "")) | |
8961 | (clobber (scratch:SI)) | |
8962 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8963 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8964 | " |
8965 | { | |
8966 | int regno; | |
8967 | int count; | |
8968 | rtx to; | |
792760b9 | 8969 | rtx op0; |
1fd4e8c1 RK |
8970 | int i; |
8971 | ||
8972 | /* Support only storing a constant number of fixed-point registers to | |
8973 | memory and only bother with this if more than two; the machine | |
8974 | doesn't support more than eight. */ | |
8975 | if (GET_CODE (operands[2]) != CONST_INT | |
8976 | || INTVAL (operands[2]) <= 2 | |
8977 | || INTVAL (operands[2]) > 8 | |
8978 | || GET_CODE (operands[0]) != MEM | |
8979 | || GET_CODE (operands[1]) != REG | |
8980 | || REGNO (operands[1]) >= 32) | |
8981 | FAIL; | |
8982 | ||
8983 | count = INTVAL (operands[2]); | |
8984 | regno = REGNO (operands[1]); | |
8985 | ||
39403d82 | 8986 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8987 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8988 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8989 | |
8990 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 8991 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 8992 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8993 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8994 | |
8995 | for (i = 1; i < count; i++) | |
8996 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8997 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 8998 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 8999 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
9000 | }") |
9001 | ||
9caa3eb2 | 9002 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
9003 | [(match_parallel 0 "store_multiple_operation" |
9004 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 9005 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9006 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 9007 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
9008 | "{stsi|stswi} %2,%P1,%O0" |
9009 | [(set_attr "type" "store")]) | |
d14a6d05 | 9010 | |
e46e3130 | 9011 | (define_insn "*stmsi8" |
d14a6d05 | 9012 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
9013 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
9014 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9015 | (clobber (match_scratch:SI 3 "X")) | |
9016 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9017 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9018 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9019 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9020 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9021 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9022 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9023 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9024 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9025 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
9026 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
9027 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
9028 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
9029 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
9030 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
9031 | "{stsi|stswi} %2,%1,%O0" | |
9032 | [(set_attr "type" "store")]) | |
9033 | ||
9034 | (define_insn "*stmsi7" | |
9035 | [(match_parallel 0 "store_multiple_operation" | |
9036 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9037 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9038 | (clobber (match_scratch:SI 3 "X")) | |
9039 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9040 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9041 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9042 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9043 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9044 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9045 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9046 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9047 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9048 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
9049 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
9050 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
9051 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
9052 | "{stsi|stswi} %2,%1,%O0" | |
9053 | [(set_attr "type" "store")]) | |
9054 | ||
9055 | (define_insn "*stmsi6" | |
9056 | [(match_parallel 0 "store_multiple_operation" | |
9057 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9058 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9059 | (clobber (match_scratch:SI 3 "X")) | |
9060 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9061 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9062 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9063 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9064 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9065 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9066 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9067 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9068 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9069 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
9070 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
9071 | "{stsi|stswi} %2,%1,%O0" | |
9072 | [(set_attr "type" "store")]) | |
9073 | ||
9074 | (define_insn "*stmsi5" | |
9075 | [(match_parallel 0 "store_multiple_operation" | |
9076 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9077 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9078 | (clobber (match_scratch:SI 3 "X")) | |
9079 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9080 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9081 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9082 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9083 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9084 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9085 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9086 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
9087 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
9088 | "{stsi|stswi} %2,%1,%O0" | |
9089 | [(set_attr "type" "store")]) | |
9090 | ||
9091 | (define_insn "*stmsi4" | |
9092 | [(match_parallel 0 "store_multiple_operation" | |
9093 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9094 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9095 | (clobber (match_scratch:SI 3 "X")) | |
9096 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9097 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9098 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9099 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9100 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9101 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
9102 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
9103 | "{stsi|stswi} %2,%1,%O0" |
9104 | [(set_attr "type" "store")]) | |
7e69e155 | 9105 | |
e46e3130 DJ |
9106 | (define_insn "*stmsi3" |
9107 | [(match_parallel 0 "store_multiple_operation" | |
9108 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9109 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9110 | (clobber (match_scratch:SI 3 "X")) | |
9111 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9112 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9113 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9114 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
9115 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
9116 | "{stsi|stswi} %2,%1,%O0" | |
9117 | [(set_attr "type" "store")]) | |
7e69e155 | 9118 | \f |
fba73eb1 DE |
9119 | (define_expand "clrmemsi" |
9120 | [(parallel [(set (match_operand:BLK 0 "" "") | |
9121 | (const_int 0)) | |
9122 | (use (match_operand:SI 1 "" "")) | |
9123 | (use (match_operand:SI 2 "" ""))])] | |
9124 | "" | |
9125 | " | |
9126 | { | |
9127 | if (expand_block_clear (operands)) | |
9128 | DONE; | |
9129 | else | |
9130 | FAIL; | |
9131 | }") | |
9132 | ||
7e69e155 MM |
9133 | ;; String/block move insn. |
9134 | ;; Argument 0 is the destination | |
9135 | ;; Argument 1 is the source | |
9136 | ;; Argument 2 is the length | |
9137 | ;; Argument 3 is the alignment | |
9138 | ||
70128ad9 | 9139 | (define_expand "movmemsi" |
b6c9286a MM |
9140 | [(parallel [(set (match_operand:BLK 0 "" "") |
9141 | (match_operand:BLK 1 "" "")) | |
9142 | (use (match_operand:SI 2 "" "")) | |
9143 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
9144 | "" |
9145 | " | |
9146 | { | |
9147 | if (expand_block_move (operands)) | |
9148 | DONE; | |
9149 | else | |
9150 | FAIL; | |
9151 | }") | |
9152 | ||
9153 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
9154 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
9155 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9156 | (define_expand "movmemsi_8reg" |
b6c9286a MM |
9157 | [(parallel [(set (match_operand 0 "" "") |
9158 | (match_operand 1 "" "")) | |
9159 | (use (match_operand 2 "" "")) | |
9160 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
9161 | (clobber (reg:SI 5)) |
9162 | (clobber (reg:SI 6)) | |
9163 | (clobber (reg:SI 7)) | |
9164 | (clobber (reg:SI 8)) | |
9165 | (clobber (reg:SI 9)) | |
9166 | (clobber (reg:SI 10)) | |
9167 | (clobber (reg:SI 11)) | |
9168 | (clobber (reg:SI 12)) | |
3c67b673 | 9169 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9170 | "TARGET_STRING" |
9171 | "") | |
9172 | ||
9173 | (define_insn "" | |
52d3af72 DE |
9174 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9175 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9176 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9177 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9178 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9179 | (clobber (reg:SI 6)) |
9180 | (clobber (reg:SI 7)) | |
9181 | (clobber (reg:SI 8)) | |
9182 | (clobber (reg:SI 9)) | |
9183 | (clobber (reg:SI 10)) | |
9184 | (clobber (reg:SI 11)) | |
9185 | (clobber (reg:SI 12)) | |
3c67b673 | 9186 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 9187 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
9188 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9189 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9190 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9191 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9192 | && REGNO (operands[4]) == 5" |
9193 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9194 | [(set_attr "type" "load") |
9195 | (set_attr "length" "8")]) | |
7e69e155 MM |
9196 | |
9197 | (define_insn "" | |
52d3af72 DE |
9198 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9199 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9200 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9201 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9202 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9203 | (clobber (reg:SI 6)) |
9204 | (clobber (reg:SI 7)) | |
9205 | (clobber (reg:SI 8)) | |
9206 | (clobber (reg:SI 9)) | |
9207 | (clobber (reg:SI 10)) | |
9208 | (clobber (reg:SI 11)) | |
9209 | (clobber (reg:SI 12)) | |
3c67b673 | 9210 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9211 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
9212 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9213 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9214 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9215 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9216 | && REGNO (operands[4]) == 5" |
9217 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9218 | [(set_attr "type" "load") |
9219 | (set_attr "length" "8")]) | |
7e69e155 | 9220 | |
09a625f7 TR |
9221 | (define_insn "" |
9222 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9223 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9224 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9225 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9226 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9227 | (clobber (reg:SI 6)) | |
9228 | (clobber (reg:SI 7)) | |
9229 | (clobber (reg:SI 8)) | |
9230 | (clobber (reg:SI 9)) | |
9231 | (clobber (reg:SI 10)) | |
9232 | (clobber (reg:SI 11)) | |
9233 | (clobber (reg:SI 12)) | |
9234 | (clobber (match_scratch:SI 5 "X"))] | |
9235 | "TARGET_STRING && TARGET_POWERPC64 | |
9236 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
9237 | || INTVAL (operands[2]) == 0) | |
9238 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
9239 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
9240 | && REGNO (operands[4]) == 5" | |
9241 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9242 | [(set_attr "type" "load") | |
9243 | (set_attr "length" "8")]) | |
9244 | ||
7e69e155 | 9245 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
9246 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
9247 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9248 | (define_expand "movmemsi_6reg" |
b6c9286a MM |
9249 | [(parallel [(set (match_operand 0 "" "") |
9250 | (match_operand 1 "" "")) | |
9251 | (use (match_operand 2 "" "")) | |
9252 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9253 | (clobber (reg:SI 5)) |
9254 | (clobber (reg:SI 6)) | |
7e69e155 MM |
9255 | (clobber (reg:SI 7)) |
9256 | (clobber (reg:SI 8)) | |
9257 | (clobber (reg:SI 9)) | |
9258 | (clobber (reg:SI 10)) | |
3c67b673 | 9259 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9260 | "TARGET_STRING" |
9261 | "") | |
9262 | ||
9263 | (define_insn "" | |
52d3af72 DE |
9264 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9265 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9266 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9267 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9268 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9269 | (clobber (reg:SI 6)) |
9270 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9271 | (clobber (reg:SI 8)) |
9272 | (clobber (reg:SI 9)) | |
9273 | (clobber (reg:SI 10)) | |
3c67b673 | 9274 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9275 | "TARGET_STRING && TARGET_POWER |
9276 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
9277 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9278 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9279 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9280 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9281 | [(set_attr "type" "load") |
9282 | (set_attr "length" "8")]) | |
7e69e155 MM |
9283 | |
9284 | (define_insn "" | |
52d3af72 DE |
9285 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9286 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9287 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9288 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9289 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9290 | (clobber (reg:SI 6)) |
9291 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9292 | (clobber (reg:SI 8)) |
9293 | (clobber (reg:SI 9)) | |
9294 | (clobber (reg:SI 10)) | |
3c67b673 | 9295 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9296 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9297 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
9298 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9299 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9300 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9301 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9302 | [(set_attr "type" "load") |
9303 | (set_attr "length" "8")]) | |
7e69e155 | 9304 | |
09a625f7 TR |
9305 | (define_insn "" |
9306 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9307 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9308 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9309 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9310 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9311 | (clobber (reg:SI 6)) | |
9312 | (clobber (reg:SI 7)) | |
9313 | (clobber (reg:SI 8)) | |
9314 | (clobber (reg:SI 9)) | |
9315 | (clobber (reg:SI 10)) | |
9316 | (clobber (match_scratch:SI 5 "X"))] | |
9317 | "TARGET_STRING && TARGET_POWERPC64 | |
9318 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
9319 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
9320 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9321 | && REGNO (operands[4]) == 5" | |
9322 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9323 | [(set_attr "type" "load") | |
9324 | (set_attr "length" "8")]) | |
9325 | ||
f9562f27 DE |
9326 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9327 | ;; problems with TImode. | |
9328 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9329 | (define_expand "movmemsi_4reg" |
b6c9286a MM |
9330 | [(parallel [(set (match_operand 0 "" "") |
9331 | (match_operand 1 "" "")) | |
9332 | (use (match_operand 2 "" "")) | |
9333 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9334 | (clobber (reg:SI 5)) |
9335 | (clobber (reg:SI 6)) | |
9336 | (clobber (reg:SI 7)) | |
9337 | (clobber (reg:SI 8)) | |
3c67b673 | 9338 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9339 | "TARGET_STRING" |
9340 | "") | |
9341 | ||
9342 | (define_insn "" | |
52d3af72 DE |
9343 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9344 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9345 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9346 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9347 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9348 | (clobber (reg:SI 6)) |
9349 | (clobber (reg:SI 7)) | |
9350 | (clobber (reg:SI 8)) | |
3c67b673 | 9351 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9352 | "TARGET_STRING && TARGET_POWER |
9353 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9354 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9355 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9356 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9357 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9358 | [(set_attr "type" "load") |
9359 | (set_attr "length" "8")]) | |
7e69e155 MM |
9360 | |
9361 | (define_insn "" | |
52d3af72 DE |
9362 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9363 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9364 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9365 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9366 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9367 | (clobber (reg:SI 6)) |
9368 | (clobber (reg:SI 7)) | |
9369 | (clobber (reg:SI 8)) | |
3c67b673 | 9370 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9371 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9372 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9373 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9374 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9375 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9376 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9377 | [(set_attr "type" "load") |
9378 | (set_attr "length" "8")]) | |
7e69e155 | 9379 | |
09a625f7 TR |
9380 | (define_insn "" |
9381 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9382 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9383 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9384 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9385 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9386 | (clobber (reg:SI 6)) | |
9387 | (clobber (reg:SI 7)) | |
9388 | (clobber (reg:SI 8)) | |
9389 | (clobber (match_scratch:SI 5 "X"))] | |
9390 | "TARGET_STRING && TARGET_POWERPC64 | |
9391 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
9392 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
9393 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9394 | && REGNO (operands[4]) == 5" | |
9395 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9396 | [(set_attr "type" "load") | |
9397 | (set_attr "length" "8")]) | |
9398 | ||
7e69e155 | 9399 | ;; Move up to 8 bytes at a time. |
70128ad9 | 9400 | (define_expand "movmemsi_2reg" |
b6c9286a MM |
9401 | [(parallel [(set (match_operand 0 "" "") |
9402 | (match_operand 1 "" "")) | |
9403 | (use (match_operand 2 "" "")) | |
9404 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9405 | (clobber (match_scratch:DI 4 "")) |
9406 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9407 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9408 | "") |
9409 | ||
9410 | (define_insn "" | |
52d3af72 DE |
9411 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9412 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9413 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9414 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9415 | (clobber (match_scratch:DI 4 "=&r")) | |
9416 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9417 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9418 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9419 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9420 | [(set_attr "type" "load") |
9421 | (set_attr "length" "8")]) | |
7e69e155 MM |
9422 | |
9423 | (define_insn "" | |
52d3af72 DE |
9424 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9425 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9426 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9427 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9428 | (clobber (match_scratch:DI 4 "=&r")) | |
9429 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9430 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9431 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9432 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9433 | [(set_attr "type" "load") |
9434 | (set_attr "length" "8")]) | |
7e69e155 MM |
9435 | |
9436 | ;; Move up to 4 bytes at a time. | |
70128ad9 | 9437 | (define_expand "movmemsi_1reg" |
b6c9286a MM |
9438 | [(parallel [(set (match_operand 0 "" "") |
9439 | (match_operand 1 "" "")) | |
9440 | (use (match_operand 2 "" "")) | |
9441 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9442 | (clobber (match_scratch:SI 4 "")) |
9443 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9444 | "TARGET_STRING" |
9445 | "") | |
9446 | ||
9447 | (define_insn "" | |
52d3af72 DE |
9448 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9449 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9450 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9451 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9452 | (clobber (match_scratch:SI 4 "=&r")) | |
9453 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9454 | "TARGET_STRING && TARGET_POWER |
9455 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9456 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9457 | [(set_attr "type" "load") |
9458 | (set_attr "length" "8")]) | |
7e69e155 MM |
9459 | |
9460 | (define_insn "" | |
52d3af72 DE |
9461 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9462 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9463 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9464 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9465 | (clobber (match_scratch:SI 4 "=&r")) | |
9466 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9467 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9468 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
9469 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
9470 | [(set_attr "type" "load") | |
9471 | (set_attr "length" "8")]) | |
9472 | ||
9473 | (define_insn "" | |
9474 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9475 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9476 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9477 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9478 | (clobber (match_scratch:SI 4 "=&r")) | |
9479 | (clobber (match_scratch:SI 5 "X"))] | |
9480 | "TARGET_STRING && TARGET_POWERPC64 | |
9481 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9482 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9483 | [(set_attr "type" "load") |
9484 | (set_attr "length" "8")]) | |
7e69e155 | 9485 | |
1fd4e8c1 | 9486 | \f |
7e69e155 | 9487 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9488 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9489 | ;; do cases where the increment is not the size of the object. | |
9490 | ;; | |
9491 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9492 | ;; incremented because those are the operands that local-alloc will | |
9493 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9494 | ;; that will benefit the most). | |
9495 | ||
38c1f2d7 | 9496 | (define_insn "*movdi_update1" |
51b8fc2c | 9497 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9498 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9499 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
9500 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
9501 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9502 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9503 | "@ |
9504 | ldux %3,%0,%2 | |
9505 | ldu %3,%2(%0)" | |
b54cf83a | 9506 | [(set_attr "type" "load_ux,load_u")]) |
287f13ff | 9507 | |
2e6c9641 FJ |
9508 | (define_insn "movdi_<mode>_update" |
9509 | [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") | |
9510 | (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) | |
51b8fc2c | 9511 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
2e6c9641 FJ |
9512 | (set (match_operand:P 0 "gpc_reg_operand" "=b,b") |
9513 | (plus:P (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9514 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9515 | "@ |
9516 | stdux %3,%0,%2 | |
b7ff3d82 | 9517 | stdu %3,%2(%0)" |
b54cf83a | 9518 | [(set_attr "type" "store_ux,store_u")]) |
51b8fc2c | 9519 | |
38c1f2d7 | 9520 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9521 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9522 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9523 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9524 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9525 | (plus:SI (match_dup 1) (match_dup 2)))] |
f7b3ab8a | 9526 | "TARGET_UPDATE" |
1fd4e8c1 | 9527 | "@ |
ca7f5001 RK |
9528 | {lux|lwzux} %3,%0,%2 |
9529 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a DE |
9530 | [(set_attr "type" "load_ux,load_u")]) |
9531 | ||
9532 | (define_insn "*movsi_update2" | |
9533 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
9534 | (sign_extend:DI | |
9535 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9536 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9537 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9538 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9539 | "TARGET_POWERPC64" | |
9540 | "lwaux %3,%0,%2" | |
9541 | [(set_attr "type" "load_ext_ux")]) | |
1fd4e8c1 | 9542 | |
4697a36c | 9543 | (define_insn "movsi_update" |
cd2b37d9 | 9544 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9545 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9546 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9547 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9548 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9549 | "TARGET_UPDATE" |
1fd4e8c1 | 9550 | "@ |
ca7f5001 | 9551 | {stux|stwux} %3,%0,%2 |
b7ff3d82 | 9552 | {stu|stwu} %3,%2(%0)" |
b54cf83a | 9553 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9554 | |
b54cf83a | 9555 | (define_insn "*movhi_update1" |
cd2b37d9 RK |
9556 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9557 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9558 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9559 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9560 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9561 | "TARGET_UPDATE" |
1fd4e8c1 | 9562 | "@ |
5f243543 RK |
9563 | lhzux %3,%0,%2 |
9564 | lhzu %3,%2(%0)" | |
b54cf83a | 9565 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9566 | |
38c1f2d7 | 9567 | (define_insn "*movhi_update2" |
cd2b37d9 | 9568 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9569 | (zero_extend:SI |
cd2b37d9 | 9570 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9571 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9572 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9573 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9574 | "TARGET_UPDATE" |
1fd4e8c1 | 9575 | "@ |
5f243543 RK |
9576 | lhzux %3,%0,%2 |
9577 | lhzu %3,%2(%0)" | |
b54cf83a | 9578 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9579 | |
38c1f2d7 | 9580 | (define_insn "*movhi_update3" |
cd2b37d9 | 9581 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9582 | (sign_extend:SI |
cd2b37d9 | 9583 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9584 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9585 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9586 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9587 | "TARGET_UPDATE" |
1fd4e8c1 | 9588 | "@ |
5f243543 RK |
9589 | lhaux %3,%0,%2 |
9590 | lhau %3,%2(%0)" | |
b54cf83a | 9591 | [(set_attr "type" "load_ext_ux,load_ext_u")]) |
1fd4e8c1 | 9592 | |
38c1f2d7 | 9593 | (define_insn "*movhi_update4" |
cd2b37d9 | 9594 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9595 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9596 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9597 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9598 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9599 | "TARGET_UPDATE" |
1fd4e8c1 | 9600 | "@ |
5f243543 | 9601 | sthux %3,%0,%2 |
b7ff3d82 | 9602 | sthu %3,%2(%0)" |
b54cf83a | 9603 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9604 | |
38c1f2d7 | 9605 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9606 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9607 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9608 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9609 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9610 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9611 | "TARGET_UPDATE" |
1fd4e8c1 | 9612 | "@ |
5f243543 RK |
9613 | lbzux %3,%0,%2 |
9614 | lbzu %3,%2(%0)" | |
b54cf83a | 9615 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9616 | |
38c1f2d7 | 9617 | (define_insn "*movqi_update2" |
cd2b37d9 | 9618 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9619 | (zero_extend:SI |
cd2b37d9 | 9620 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9621 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9622 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9623 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9624 | "TARGET_UPDATE" |
1fd4e8c1 | 9625 | "@ |
5f243543 RK |
9626 | lbzux %3,%0,%2 |
9627 | lbzu %3,%2(%0)" | |
b54cf83a | 9628 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9629 | |
38c1f2d7 | 9630 | (define_insn "*movqi_update3" |
cd2b37d9 | 9631 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9632 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9633 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9634 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9635 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9636 | "TARGET_UPDATE" |
1fd4e8c1 | 9637 | "@ |
5f243543 | 9638 | stbux %3,%0,%2 |
b7ff3d82 | 9639 | stbu %3,%2(%0)" |
b54cf83a | 9640 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9641 | |
38c1f2d7 | 9642 | (define_insn "*movsf_update1" |
cd2b37d9 | 9643 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9644 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9645 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9646 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9647 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9648 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9649 | "@ |
5f243543 RK |
9650 | lfsux %3,%0,%2 |
9651 | lfsu %3,%2(%0)" | |
b54cf83a | 9652 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9653 | |
38c1f2d7 | 9654 | (define_insn "*movsf_update2" |
cd2b37d9 | 9655 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9656 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9657 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9658 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9659 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9660 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9661 | "@ |
85fff2f3 | 9662 | stfsux %3,%0,%2 |
b7ff3d82 | 9663 | stfsu %3,%2(%0)" |
b54cf83a | 9664 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
1fd4e8c1 | 9665 | |
38c1f2d7 MM |
9666 | (define_insn "*movsf_update3" |
9667 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9668 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9669 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9670 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9671 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9672 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9673 | "@ |
9674 | {lux|lwzux} %3,%0,%2 | |
9675 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a | 9676 | [(set_attr "type" "load_ux,load_u")]) |
38c1f2d7 MM |
9677 | |
9678 | (define_insn "*movsf_update4" | |
9679 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9680 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9681 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9682 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9683 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9684 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9685 | "@ |
9686 | {stux|stwux} %3,%0,%2 | |
9687 | {stu|stwu} %3,%2(%0)" | |
b54cf83a | 9688 | [(set_attr "type" "store_ux,store_u")]) |
38c1f2d7 MM |
9689 | |
9690 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9691 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9692 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9693 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9694 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9695 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9696 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9697 | "@ |
5f243543 RK |
9698 | lfdux %3,%0,%2 |
9699 | lfdu %3,%2(%0)" | |
b54cf83a | 9700 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9701 | |
38c1f2d7 | 9702 | (define_insn "*movdf_update2" |
cd2b37d9 | 9703 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9704 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9705 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9706 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9707 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9708 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9709 | "@ |
5f243543 | 9710 | stfdux %3,%0,%2 |
b7ff3d82 | 9711 | stfdu %3,%2(%0)" |
b54cf83a | 9712 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
4c70a4f3 RK |
9713 | |
9714 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9715 | ||
90f81f99 AP |
9716 | (define_insn "*lfq_power2" |
9717 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
9718 | (match_operand:TF 1 "memory_operand" ""))] | |
9719 | "TARGET_POWER2 | |
9720 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9721 | "lfq%U1%X1 %0,%1") | |
9722 | ||
9723 | (define_peephole2 | |
9724 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4c70a4f3 | 9725 | (match_operand:DF 1 "memory_operand" "")) |
90f81f99 | 9726 | (set (match_operand:DF 2 "gpc_reg_operand" "") |
4c70a4f3 RK |
9727 | (match_operand:DF 3 "memory_operand" ""))] |
9728 | "TARGET_POWER2 | |
a3170dc6 | 9729 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9730 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
90f81f99 AP |
9731 | && mems_ok_for_quad_peep (operands[1], operands[3])" |
9732 | [(set (match_dup 0) | |
9733 | (match_dup 1))] | |
9734 | "operands[1] = widen_memory_access (operands[1], TFmode, 0); | |
9735 | operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));") | |
4c70a4f3 | 9736 | |
90f81f99 AP |
9737 | (define_insn "*stfq_power2" |
9738 | [(set (match_operand:TF 0 "memory_operand" "") | |
9739 | (match_operand:TF 1 "gpc_reg_operand" "f"))] | |
9740 | "TARGET_POWER2 | |
9741 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9742 | "stfq%U0%X0 %1,%0") | |
9743 | ||
9744 | ||
9745 | (define_peephole2 | |
4c70a4f3 | 9746 | [(set (match_operand:DF 0 "memory_operand" "") |
90f81f99 | 9747 | (match_operand:DF 1 "gpc_reg_operand" "")) |
4c70a4f3 | 9748 | (set (match_operand:DF 2 "memory_operand" "") |
90f81f99 | 9749 | (match_operand:DF 3 "gpc_reg_operand" ""))] |
4c70a4f3 | 9750 | "TARGET_POWER2 |
a3170dc6 | 9751 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9752 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
90f81f99 AP |
9753 | && mems_ok_for_quad_peep (operands[0], operands[2])" |
9754 | [(set (match_dup 0) | |
9755 | (match_dup 1))] | |
9756 | "operands[0] = widen_memory_access (operands[0], TFmode, 0); | |
9757 | operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));") | |
2f4d9502 NS |
9758 | |
9759 | ;; after inserting conditional returns we can sometimes have | |
9760 | ;; unnecessary register moves. Unfortunately we cannot have a | |
9761 | ;; modeless peephole here, because some single SImode sets have early | |
9762 | ;; clobber outputs. Although those sets expand to multi-ppc-insn | |
9763 | ;; sequences, using get_attr_length here will smash the operands | |
9764 | ;; array. Neither is there an early_cobbler_p predicate. | |
9765 | (define_peephole2 | |
9766 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
9767 | (match_operand:DF 1 "any_operand" "")) | |
9768 | (set (match_operand:DF 2 "gpc_reg_operand" "") | |
9769 | (match_dup 0))] | |
9770 | "peep2_reg_dead_p (2, operands[0])" | |
9771 | [(set (match_dup 2) (match_dup 1))]) | |
9772 | ||
9773 | (define_peephole2 | |
9774 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
9775 | (match_operand:SF 1 "any_operand" "")) | |
9776 | (set (match_operand:SF 2 "gpc_reg_operand" "") | |
9777 | (match_dup 0))] | |
9778 | "peep2_reg_dead_p (2, operands[0])" | |
9779 | [(set (match_dup 2) (match_dup 1))]) | |
9780 | ||
1fd4e8c1 | 9781 | \f |
c4501e62 JJ |
9782 | ;; TLS support. |
9783 | ||
9784 | ;; "b" output constraint here and on tls_ld to support tls linker optimization. | |
9785 | (define_insn "tls_gd_32" | |
b150f4f3 DE |
9786 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9787 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9788 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9789 | UNSPEC_TLSGD))] | |
9790 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9791 | "addi %0,%1,%2@got@tlsgd") | |
9792 | ||
9793 | (define_insn "tls_gd_64" | |
b150f4f3 DE |
9794 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9795 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9796 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9797 | UNSPEC_TLSGD))] | |
9798 | "HAVE_AS_TLS && TARGET_64BIT" | |
9799 | "addi %0,%1,%2@got@tlsgd") | |
9800 | ||
9801 | (define_insn "tls_ld_32" | |
b150f4f3 DE |
9802 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9803 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9804 | UNSPEC_TLSLD))] |
9805 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9806 | "addi %0,%1,%&@got@tlsld") | |
9807 | ||
9808 | (define_insn "tls_ld_64" | |
b150f4f3 DE |
9809 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9810 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9811 | UNSPEC_TLSLD))] |
9812 | "HAVE_AS_TLS && TARGET_64BIT" | |
9813 | "addi %0,%1,%&@got@tlsld") | |
9814 | ||
9815 | (define_insn "tls_dtprel_32" | |
b150f4f3 DE |
9816 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9817 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9818 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9819 | UNSPEC_TLSDTPREL))] | |
9820 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9821 | "addi %0,%1,%2@dtprel") | |
9822 | ||
9823 | (define_insn "tls_dtprel_64" | |
b150f4f3 DE |
9824 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9825 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9826 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9827 | UNSPEC_TLSDTPREL))] | |
9828 | "HAVE_AS_TLS && TARGET_64BIT" | |
9829 | "addi %0,%1,%2@dtprel") | |
9830 | ||
9831 | (define_insn "tls_dtprel_ha_32" | |
b150f4f3 DE |
9832 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9833 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9834 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9835 | UNSPEC_TLSDTPRELHA))] | |
9836 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9837 | "addis %0,%1,%2@dtprel@ha") | |
9838 | ||
9839 | (define_insn "tls_dtprel_ha_64" | |
b150f4f3 DE |
9840 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9841 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9842 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9843 | UNSPEC_TLSDTPRELHA))] | |
9844 | "HAVE_AS_TLS && TARGET_64BIT" | |
9845 | "addis %0,%1,%2@dtprel@ha") | |
9846 | ||
9847 | (define_insn "tls_dtprel_lo_32" | |
b150f4f3 DE |
9848 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9849 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9850 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9851 | UNSPEC_TLSDTPRELLO))] | |
9852 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9853 | "addi %0,%1,%2@dtprel@l") | |
9854 | ||
9855 | (define_insn "tls_dtprel_lo_64" | |
b150f4f3 DE |
9856 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9857 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9858 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9859 | UNSPEC_TLSDTPRELLO))] | |
9860 | "HAVE_AS_TLS && TARGET_64BIT" | |
9861 | "addi %0,%1,%2@dtprel@l") | |
9862 | ||
9863 | (define_insn "tls_got_dtprel_32" | |
b150f4f3 DE |
9864 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9865 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9866 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9867 | UNSPEC_TLSGOTDTPREL))] | |
9868 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9869 | "lwz %0,%2@got@dtprel(%1)") | |
9870 | ||
9871 | (define_insn "tls_got_dtprel_64" | |
b150f4f3 DE |
9872 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9873 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9874 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9875 | UNSPEC_TLSGOTDTPREL))] | |
9876 | "HAVE_AS_TLS && TARGET_64BIT" | |
9877 | "ld %0,%2@got@dtprel(%1)") | |
9878 | ||
9879 | (define_insn "tls_tprel_32" | |
b150f4f3 DE |
9880 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9881 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9882 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9883 | UNSPEC_TLSTPREL))] | |
9884 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9885 | "addi %0,%1,%2@tprel") | |
9886 | ||
9887 | (define_insn "tls_tprel_64" | |
b150f4f3 DE |
9888 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9889 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9890 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9891 | UNSPEC_TLSTPREL))] | |
9892 | "HAVE_AS_TLS && TARGET_64BIT" | |
9893 | "addi %0,%1,%2@tprel") | |
9894 | ||
9895 | (define_insn "tls_tprel_ha_32" | |
b150f4f3 DE |
9896 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9897 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9898 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9899 | UNSPEC_TLSTPRELHA))] | |
9900 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9901 | "addis %0,%1,%2@tprel@ha") | |
9902 | ||
9903 | (define_insn "tls_tprel_ha_64" | |
b150f4f3 DE |
9904 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9905 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9906 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9907 | UNSPEC_TLSTPRELHA))] | |
9908 | "HAVE_AS_TLS && TARGET_64BIT" | |
9909 | "addis %0,%1,%2@tprel@ha") | |
9910 | ||
9911 | (define_insn "tls_tprel_lo_32" | |
b150f4f3 DE |
9912 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9913 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9914 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9915 | UNSPEC_TLSTPRELLO))] | |
9916 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9917 | "addi %0,%1,%2@tprel@l") | |
9918 | ||
9919 | (define_insn "tls_tprel_lo_64" | |
b150f4f3 DE |
9920 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9921 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9922 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9923 | UNSPEC_TLSTPRELLO))] | |
9924 | "HAVE_AS_TLS && TARGET_64BIT" | |
9925 | "addi %0,%1,%2@tprel@l") | |
9926 | ||
c1207243 | 9927 | ;; "b" output constraint here and on tls_tls input to support linker tls |
c4501e62 JJ |
9928 | ;; optimization. The linker may edit the instructions emitted by a |
9929 | ;; tls_got_tprel/tls_tls pair to addis,addi. | |
9930 | (define_insn "tls_got_tprel_32" | |
b150f4f3 DE |
9931 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9932 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9933 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9934 | UNSPEC_TLSGOTTPREL))] | |
9935 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9936 | "lwz %0,%2@got@tprel(%1)") | |
9937 | ||
9938 | (define_insn "tls_got_tprel_64" | |
b150f4f3 DE |
9939 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9940 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9941 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9942 | UNSPEC_TLSGOTTPREL))] | |
9943 | "HAVE_AS_TLS && TARGET_64BIT" | |
9944 | "ld %0,%2@got@tprel(%1)") | |
9945 | ||
9946 | (define_insn "tls_tls_32" | |
b150f4f3 DE |
9947 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9948 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9949 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9950 | UNSPEC_TLSTLS))] | |
9951 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9952 | "add %0,%1,%2@tls") | |
9953 | ||
9954 | (define_insn "tls_tls_64" | |
b150f4f3 DE |
9955 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9956 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9957 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9958 | UNSPEC_TLSTLS))] | |
9959 | "HAVE_AS_TLS && TARGET_64BIT" | |
9960 | "add %0,%1,%2@tls") | |
9961 | \f | |
1fd4e8c1 RK |
9962 | ;; Next come insns related to the calling sequence. |
9963 | ;; | |
9964 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9965 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9966 | |
9967 | (define_expand "allocate_stack" | |
52d3af72 | 9968 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9969 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9970 | (set (reg 1) | |
9971 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9972 | "" |
9973 | " | |
4697a36c | 9974 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9975 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9976 | rtx neg_op0; |
1fd4e8c1 RK |
9977 | |
9978 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9979 | |
a157febd GK |
9980 | /* Check stack bounds if necessary. */ |
9981 | if (current_function_limit_stack) | |
9982 | { | |
9983 | rtx available; | |
6ae08853 | 9984 | available = expand_binop (Pmode, sub_optab, |
a157febd GK |
9985 | stack_pointer_rtx, stack_limit_rtx, |
9986 | NULL_RTX, 1, OPTAB_WIDEN); | |
9987 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9988 | } | |
9989 | ||
e9a25f70 JL |
9990 | if (GET_CODE (operands[1]) != CONST_INT |
9991 | || INTVAL (operands[1]) < -32767 | |
9992 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9993 | { |
9994 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9995 | if (TARGET_32BIT) |
e9a25f70 | 9996 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9997 | else |
e9a25f70 | 9998 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9999 | } |
10000 | else | |
e9a25f70 | 10001 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 10002 | |
38c1f2d7 | 10003 | if (TARGET_UPDATE) |
2e6c9641 | 10004 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update)) |
38c1f2d7 | 10005 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); |
4697a36c | 10006 | |
38c1f2d7 MM |
10007 | else |
10008 | { | |
10009 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
10010 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 10011 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 10012 | } |
e9a25f70 JL |
10013 | |
10014 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
10015 | DONE; |
10016 | }") | |
59257ff7 RK |
10017 | |
10018 | ;; These patterns say how to save and restore the stack pointer. We need not | |
10019 | ;; save the stack pointer at function level since we are careful to | |
10020 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10021 | ;; when we restore the stack pointer. | |
10022 | ;; | |
10023 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10024 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10025 | ;; save area is a memory location. | |
10026 | ||
10027 | (define_expand "save_stack_function" | |
ff381587 MM |
10028 | [(match_operand 0 "any_operand" "") |
10029 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 10030 | "" |
ff381587 | 10031 | "DONE;") |
59257ff7 RK |
10032 | |
10033 | (define_expand "restore_stack_function" | |
ff381587 MM |
10034 | [(match_operand 0 "any_operand" "") |
10035 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 10036 | "" |
ff381587 | 10037 | "DONE;") |
59257ff7 RK |
10038 | |
10039 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
10040 | [(use (match_operand 0 "register_operand" "")) |
10041 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 10042 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 10043 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
10044 | "" |
10045 | " | |
dfdfa60f DE |
10046 | { |
10047 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 10048 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 10049 | }") |
59257ff7 RK |
10050 | |
10051 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
10052 | [(match_operand 0 "memory_operand" "") |
10053 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
10054 | "" |
10055 | " | |
10056 | { | |
a260abc9 | 10057 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 10058 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
10059 | |
10060 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 10061 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
39e453d7 DE |
10062 | emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp); |
10063 | emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word), | |
a260abc9 | 10064 | operands[1]); |
59257ff7 RK |
10065 | DONE; |
10066 | }") | |
7e69e155 | 10067 | |
59257ff7 | 10068 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
10069 | [(match_operand 0 "register_operand" "") |
10070 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
10071 | "" |
10072 | " | |
10073 | { | |
a260abc9 | 10074 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 10075 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
10076 | |
10077 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 | 10078 | emit_move_insn (temp, |
39e453d7 | 10079 | adjust_address_nv (operands[1], Pmode, 0)); |
a260abc9 | 10080 | emit_move_insn (operands[0], |
39e453d7 | 10081 | adjust_address_nv (operands[1], Pmode, units_per_word)); |
39403d82 | 10082 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
10083 | DONE; |
10084 | }") | |
9ebbca7d GK |
10085 | \f |
10086 | ;; TOC register handling. | |
b6c9286a | 10087 | |
9ebbca7d | 10088 | ;; Code to initialize the TOC register... |
f0f6a223 | 10089 | |
9ebbca7d | 10090 | (define_insn "load_toc_aix_si" |
e72247f4 | 10091 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
615158e2 | 10092 | (unspec:SI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 10093 | (use (reg:SI 2))])] |
2bfcf297 | 10094 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
10095 | "* |
10096 | { | |
9ebbca7d GK |
10097 | char buf[30]; |
10098 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 10099 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10100 | operands[2] = gen_rtx_REG (Pmode, 2); |
10101 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
10102 | }" |
10103 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
10104 | |
10105 | (define_insn "load_toc_aix_di" | |
e72247f4 | 10106 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
615158e2 | 10107 | (unspec:DI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 10108 | (use (reg:DI 2))])] |
2bfcf297 | 10109 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
10110 | "* |
10111 | { | |
10112 | char buf[30]; | |
f585a356 DE |
10113 | #ifdef TARGET_RELOCATABLE |
10114 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
10115 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
10116 | #else | |
9ebbca7d | 10117 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 10118 | #endif |
2bfcf297 DB |
10119 | if (TARGET_ELF) |
10120 | strcat (buf, \"@toc\"); | |
a8a05998 | 10121 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10122 | operands[2] = gen_rtx_REG (Pmode, 2); |
10123 | return \"ld %0,%1(%2)\"; | |
10124 | }" | |
10125 | [(set_attr "type" "load")]) | |
10126 | ||
10127 | (define_insn "load_toc_v4_pic_si" | |
10128 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 | 10129 | (unspec:SI [(const_int 0)] UNSPEC_TOC))] |
f607bc57 | 10130 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
10131 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
10132 | [(set_attr "type" "branch") | |
10133 | (set_attr "length" "4")]) | |
10134 | ||
9ebbca7d GK |
10135 | (define_insn "load_toc_v4_PIC_1" |
10136 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10137 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 | 10138 | (use (unspec [(match_dup 1)] UNSPEC_TOC))] |
20b71b17 | 10139 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 10140 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
10141 | [(set_attr "type" "branch") |
10142 | (set_attr "length" "4")]) | |
10143 | ||
10144 | (define_insn "load_toc_v4_PIC_1b" | |
10145 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10146 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 JJ |
10147 | (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] |
10148 | UNSPEC_TOCPTR))] | |
20b71b17 | 10149 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
c4501e62 | 10150 | "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1" |
9ebbca7d GK |
10151 | [(set_attr "type" "branch") |
10152 | (set_attr "length" "8")]) | |
10153 | ||
10154 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 10155 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 10156 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
10157 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
10158 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 10159 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
10160 | "{l|lwz} %0,%2-%3(%1)" |
10161 | [(set_attr "type" "load")]) | |
10162 | ||
f51eee6a | 10163 | |
9ebbca7d GK |
10164 | ;; If the TOC is shared over a translation unit, as happens with all |
10165 | ;; the kinds of PIC that we support, we need to restore the TOC | |
10166 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 10167 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
10168 | |
10169 | (define_expand "builtin_setjmp_receiver" | |
10170 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 10171 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
10172 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
10173 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
10174 | " |
10175 | { | |
84d7dd4a | 10176 | #if TARGET_MACHO |
f51eee6a GK |
10177 | if (DEFAULT_ABI == ABI_DARWIN) |
10178 | { | |
d24652ee | 10179 | const char *picbase = machopic_function_base_name (); |
485bad26 | 10180 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); |
f51eee6a GK |
10181 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
10182 | rtx tmplabrtx; | |
10183 | char tmplab[20]; | |
10184 | ||
10185 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
10186 | CODE_LABEL_NUMBER (operands[0])); | |
485bad26 | 10187 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); |
f51eee6a | 10188 | |
b8a55285 AP |
10189 | emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); |
10190 | emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
f51eee6a GK |
10191 | } |
10192 | else | |
84d7dd4a | 10193 | #endif |
f51eee6a | 10194 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
10195 | DONE; |
10196 | }") | |
10197 | \f | |
10198 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
10199 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
10200 | ;; pointer to its TOC, and whose third word contains a value to place in the |
10201 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 10202 | ;; "trampoline" need not have any executable code. |
b6c9286a | 10203 | |
cccf3bdc DE |
10204 | (define_expand "call_indirect_aix32" |
10205 | [(set (match_dup 2) | |
10206 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
10207 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10208 | (reg:SI 2)) | |
10209 | (set (reg:SI 2) | |
10210 | (mem:SI (plus:SI (match_dup 0) | |
10211 | (const_int 4)))) | |
10212 | (set (reg:SI 11) | |
10213 | (mem:SI (plus:SI (match_dup 0) | |
10214 | (const_int 8)))) | |
10215 | (parallel [(call (mem:SI (match_dup 2)) | |
10216 | (match_operand 1 "" "")) | |
10217 | (use (reg:SI 2)) | |
10218 | (use (reg:SI 11)) | |
10219 | (set (reg:SI 2) | |
10220 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10221 | (clobber (scratch:SI))])] | |
10222 | "TARGET_32BIT" | |
10223 | " | |
10224 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10225 | |
cccf3bdc DE |
10226 | (define_expand "call_indirect_aix64" |
10227 | [(set (match_dup 2) | |
10228 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
10229 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10230 | (reg:DI 2)) | |
10231 | (set (reg:DI 2) | |
10232 | (mem:DI (plus:DI (match_dup 0) | |
10233 | (const_int 8)))) | |
10234 | (set (reg:DI 11) | |
10235 | (mem:DI (plus:DI (match_dup 0) | |
10236 | (const_int 16)))) | |
10237 | (parallel [(call (mem:SI (match_dup 2)) | |
10238 | (match_operand 1 "" "")) | |
10239 | (use (reg:DI 2)) | |
10240 | (use (reg:DI 11)) | |
10241 | (set (reg:DI 2) | |
10242 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10243 | (clobber (scratch:SI))])] | |
10244 | "TARGET_64BIT" | |
10245 | " | |
10246 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 10247 | |
cccf3bdc DE |
10248 | (define_expand "call_value_indirect_aix32" |
10249 | [(set (match_dup 3) | |
10250 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10251 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10252 | (reg:SI 2)) | |
10253 | (set (reg:SI 2) | |
10254 | (mem:SI (plus:SI (match_dup 1) | |
10255 | (const_int 4)))) | |
10256 | (set (reg:SI 11) | |
10257 | (mem:SI (plus:SI (match_dup 1) | |
10258 | (const_int 8)))) | |
10259 | (parallel [(set (match_operand 0 "" "") | |
10260 | (call (mem:SI (match_dup 3)) | |
10261 | (match_operand 2 "" ""))) | |
10262 | (use (reg:SI 2)) | |
10263 | (use (reg:SI 11)) | |
10264 | (set (reg:SI 2) | |
10265 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10266 | (clobber (scratch:SI))])] | |
10267 | "TARGET_32BIT" | |
10268 | " | |
10269 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10270 | |
cccf3bdc DE |
10271 | (define_expand "call_value_indirect_aix64" |
10272 | [(set (match_dup 3) | |
10273 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10274 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10275 | (reg:DI 2)) | |
10276 | (set (reg:DI 2) | |
10277 | (mem:DI (plus:DI (match_dup 1) | |
10278 | (const_int 8)))) | |
10279 | (set (reg:DI 11) | |
10280 | (mem:DI (plus:DI (match_dup 1) | |
10281 | (const_int 16)))) | |
10282 | (parallel [(set (match_operand 0 "" "") | |
10283 | (call (mem:SI (match_dup 3)) | |
10284 | (match_operand 2 "" ""))) | |
10285 | (use (reg:DI 2)) | |
10286 | (use (reg:DI 11)) | |
10287 | (set (reg:DI 2) | |
10288 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10289 | (clobber (scratch:SI))])] | |
10290 | "TARGET_64BIT" | |
10291 | " | |
10292 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 10293 | |
b6c9286a | 10294 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 10295 | (define_expand "call" |
a260abc9 | 10296 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 10297 | (match_operand 1 "" "")) |
4697a36c | 10298 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
10299 | (clobber (scratch:SI))])] |
10300 | "" | |
10301 | " | |
10302 | { | |
ee890fe2 | 10303 | #if TARGET_MACHO |
ab82a49f | 10304 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10305 | operands[0] = machopic_indirect_call_target (operands[0]); |
10306 | #endif | |
10307 | ||
1fd4e8c1 RK |
10308 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
10309 | abort (); | |
10310 | ||
10311 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 10312 | |
6a4cee5f | 10313 | if (GET_CODE (operands[0]) != SYMBOL_REF |
473f51b6 | 10314 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) |
efdba735 | 10315 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10316 | { |
6a4cee5f MM |
10317 | if (INTVAL (operands[2]) & CALL_LONG) |
10318 | operands[0] = rs6000_longcall_ref (operands[0]); | |
10319 | ||
cccf3bdc | 10320 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10321 | || DEFAULT_ABI == ABI_DARWIN) |
bbf294a5 | 10322 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10323 | |
cccf3bdc DE |
10324 | else if (DEFAULT_ABI == ABI_AIX) |
10325 | { | |
10326 | /* AIX function pointers are really pointers to a three word | |
10327 | area. */ | |
10328 | emit_call_insn (TARGET_32BIT | |
10329 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
10330 | operands[0]), | |
10331 | operands[1]) | |
10332 | : gen_call_indirect_aix64 (force_reg (DImode, | |
10333 | operands[0]), | |
10334 | operands[1])); | |
10335 | DONE; | |
b6c9286a | 10336 | } |
cccf3bdc DE |
10337 | else |
10338 | abort (); | |
1fd4e8c1 RK |
10339 | } |
10340 | }") | |
10341 | ||
10342 | (define_expand "call_value" | |
10343 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 10344 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 10345 | (match_operand 2 "" ""))) |
4697a36c | 10346 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
10347 | (clobber (scratch:SI))])] |
10348 | "" | |
10349 | " | |
10350 | { | |
ee890fe2 | 10351 | #if TARGET_MACHO |
ab82a49f | 10352 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10353 | operands[1] = machopic_indirect_call_target (operands[1]); |
10354 | #endif | |
10355 | ||
1fd4e8c1 RK |
10356 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
10357 | abort (); | |
10358 | ||
10359 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 10360 | |
6a4cee5f | 10361 | if (GET_CODE (operands[1]) != SYMBOL_REF |
473f51b6 | 10362 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) |
efdba735 | 10363 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10364 | { |
6756293c | 10365 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
10366 | operands[1] = rs6000_longcall_ref (operands[1]); |
10367 | ||
cccf3bdc | 10368 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10369 | || DEFAULT_ABI == ABI_DARWIN) |
bbf294a5 | 10370 | operands[1] = force_reg (Pmode, operands[1]); |
1fd4e8c1 | 10371 | |
cccf3bdc DE |
10372 | else if (DEFAULT_ABI == ABI_AIX) |
10373 | { | |
10374 | /* AIX function pointers are really pointers to a three word | |
10375 | area. */ | |
10376 | emit_call_insn (TARGET_32BIT | |
10377 | ? gen_call_value_indirect_aix32 (operands[0], | |
10378 | force_reg (SImode, | |
10379 | operands[1]), | |
10380 | operands[2]) | |
10381 | : gen_call_value_indirect_aix64 (operands[0], | |
10382 | force_reg (DImode, | |
10383 | operands[1]), | |
10384 | operands[2])); | |
10385 | DONE; | |
b6c9286a | 10386 | } |
cccf3bdc DE |
10387 | else |
10388 | abort (); | |
1fd4e8c1 RK |
10389 | } |
10390 | }") | |
10391 | ||
04780ee7 | 10392 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 10393 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10394 | ;; either the function was not prototyped, or it was prototyped as a |
10395 | ;; variable argument function. It is > 0 if FP registers were passed | |
10396 | ;; and < 0 if they were not. | |
04780ee7 | 10397 | |
a260abc9 | 10398 | (define_insn "*call_local32" |
4697a36c MM |
10399 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
10400 | (match_operand 1 "" "g,g")) | |
10401 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10402 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 10403 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
10404 | "* |
10405 | { | |
6a4cee5f MM |
10406 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
10407 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10408 | ||
10409 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10410 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 10411 | |
a226df46 | 10412 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 10413 | }" |
b7ff3d82 DE |
10414 | [(set_attr "type" "branch") |
10415 | (set_attr "length" "4,8")]) | |
04780ee7 | 10416 | |
a260abc9 DE |
10417 | (define_insn "*call_local64" |
10418 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10419 | (match_operand 1 "" "g,g")) | |
10420 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10421 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10422 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10423 | "* | |
10424 | { | |
10425 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10426 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10427 | ||
10428 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10429 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10430 | ||
10431 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
10432 | }" | |
10433 | [(set_attr "type" "branch") | |
10434 | (set_attr "length" "4,8")]) | |
10435 | ||
cccf3bdc | 10436 | (define_insn "*call_value_local32" |
d18dba68 | 10437 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10438 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
10439 | (match_operand 2 "" "g,g"))) | |
10440 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10441 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10442 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10443 | "* | |
10444 | { | |
10445 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10446 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10447 | ||
10448 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10449 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10450 | ||
10451 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10452 | }" | |
10453 | [(set_attr "type" "branch") | |
10454 | (set_attr "length" "4,8")]) | |
10455 | ||
10456 | ||
cccf3bdc | 10457 | (define_insn "*call_value_local64" |
d18dba68 | 10458 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10459 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
10460 | (match_operand 2 "" "g,g"))) | |
10461 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10462 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10463 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10464 | "* | |
10465 | { | |
10466 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10467 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10468 | ||
10469 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10470 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10471 | ||
10472 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10473 | }" | |
10474 | [(set_attr "type" "branch") | |
10475 | (set_attr "length" "4,8")]) | |
10476 | ||
04780ee7 | 10477 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 10478 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 10479 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10480 | ;; either the function was not prototyped, or it was prototyped as a |
10481 | ;; variable argument function. It is > 0 if FP registers were passed | |
10482 | ;; and < 0 if they were not. | |
04780ee7 | 10483 | |
cccf3bdc DE |
10484 | (define_insn "*call_indirect_nonlocal_aix32" |
10485 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
10486 | (match_operand 1 "" "g")) | |
10487 | (use (reg:SI 2)) | |
10488 | (use (reg:SI 11)) | |
10489 | (set (reg:SI 2) | |
10490 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 10491 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10492 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10493 | "b%T0l\;{l|lwz} 2,20(1)" | |
10494 | [(set_attr "type" "jmpreg") | |
10495 | (set_attr "length" "8")]) | |
10496 | ||
a260abc9 | 10497 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10498 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10499 | (match_operand 1 "" "g")) |
10500 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10501 | (clobber (match_scratch:SI 3 "=l"))] | |
10502 | "TARGET_32BIT | |
10503 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10504 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10505 | "bl %z0\;%." |
b7ff3d82 | 10506 | [(set_attr "type" "branch") |
cccf3bdc DE |
10507 | (set_attr "length" "8")]) |
10508 | ||
10509 | (define_insn "*call_indirect_nonlocal_aix64" | |
10510 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
10511 | (match_operand 1 "" "g")) | |
10512 | (use (reg:DI 2)) | |
10513 | (use (reg:DI 11)) | |
10514 | (set (reg:DI 2) | |
10515 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 10516 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10517 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10518 | "b%T0l\;ld 2,40(1)" | |
10519 | [(set_attr "type" "jmpreg") | |
10520 | (set_attr "length" "8")]) | |
59313e4e | 10521 | |
a260abc9 | 10522 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10523 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10524 | (match_operand 1 "" "g")) |
10525 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10526 | (clobber (match_scratch:SI 3 "=l"))] | |
6ae08853 | 10527 | "TARGET_64BIT |
9ebbca7d | 10528 | && DEFAULT_ABI == ABI_AIX |
a260abc9 | 10529 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10530 | "bl %z0\;%." |
a260abc9 | 10531 | [(set_attr "type" "branch") |
cccf3bdc | 10532 | (set_attr "length" "8")]) |
7509c759 | 10533 | |
cccf3bdc | 10534 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10535 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10536 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
10537 | (match_operand 2 "" "g"))) | |
10538 | (use (reg:SI 2)) | |
10539 | (use (reg:SI 11)) | |
10540 | (set (reg:SI 2) | |
10541 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10542 | (clobber (match_scratch:SI 3 "=l"))] | |
10543 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
10544 | "b%T1l\;{l|lwz} 2,20(1)" | |
10545 | [(set_attr "type" "jmpreg") | |
10546 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10547 | |
cccf3bdc | 10548 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10549 | [(set (match_operand 0 "" "") |
cc4d5fec | 10550 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10551 | (match_operand 2 "" "g"))) |
10552 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10553 | (clobber (match_scratch:SI 4 "=l"))] | |
10554 | "TARGET_32BIT | |
10555 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10556 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10557 | "bl %z1\;%." |
b7ff3d82 | 10558 | [(set_attr "type" "branch") |
cccf3bdc | 10559 | (set_attr "length" "8")]) |
04780ee7 | 10560 | |
cccf3bdc | 10561 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10562 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10563 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
10564 | (match_operand 2 "" "g"))) | |
10565 | (use (reg:DI 2)) | |
10566 | (use (reg:DI 11)) | |
10567 | (set (reg:DI 2) | |
10568 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10569 | (clobber (match_scratch:SI 3 "=l"))] | |
10570 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
10571 | "b%T1l\;ld 2,40(1)" | |
10572 | [(set_attr "type" "jmpreg") | |
10573 | (set_attr "length" "8")]) | |
10574 | ||
10575 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10576 | [(set (match_operand 0 "" "") |
cc4d5fec | 10577 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10578 | (match_operand 2 "" "g"))) |
10579 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10580 | (clobber (match_scratch:SI 4 "=l"))] | |
6ae08853 | 10581 | "TARGET_64BIT |
9ebbca7d | 10582 | && DEFAULT_ABI == ABI_AIX |
5a19791c | 10583 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10584 | "bl %z1\;%." |
10585 | [(set_attr "type" "branch") | |
10586 | (set_attr "length" "8")]) | |
10587 | ||
10588 | ;; A function pointer under System V is just a normal pointer | |
10589 | ;; operands[0] is the function pointer | |
10590 | ;; operands[1] is the stack size to clean up | |
10591 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10592 | ;; which indicates how to set cr1 | |
10593 | ||
a5c76ee6 ZW |
10594 | (define_insn "*call_indirect_nonlocal_sysv" |
10595 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) | |
10596 | (match_operand 1 "" "g,g")) | |
10597 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10598 | (clobber (match_scratch:SI 3 "=l,l"))] | |
50d440bc | 10599 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10600 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10601 | { |
cccf3bdc | 10602 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10603 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10604 | |
cccf3bdc | 10605 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10606 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10607 | |
a5c76ee6 ZW |
10608 | return "b%T0l"; |
10609 | } | |
10610 | [(set_attr "type" "jmpreg,jmpreg") | |
10611 | (set_attr "length" "4,8")]) | |
cccf3bdc | 10612 | |
a5c76ee6 ZW |
10613 | (define_insn "*call_nonlocal_sysv" |
10614 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10615 | (match_operand 1 "" "g,g")) | |
10616 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10617 | (clobber (match_scratch:SI 3 "=l,l"))] | |
efdba735 SH |
10618 | "(DEFAULT_ABI == ABI_DARWIN |
10619 | || (DEFAULT_ABI == ABI_V4 | |
10620 | && (INTVAL (operands[2]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10621 | { |
10622 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10623 | output_asm_insn ("crxor 6,6,6", operands); | |
10624 | ||
10625 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10626 | output_asm_insn ("creqv 6,6,6", operands); | |
10627 | ||
c989f2f7 | 10628 | #if TARGET_MACHO |
efdba735 SH |
10629 | return output_call(insn, operands, 0, 2); |
10630 | #else | |
a5c76ee6 | 10631 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; |
6ae08853 | 10632 | #endif |
a5c76ee6 ZW |
10633 | } |
10634 | [(set_attr "type" "branch,branch") | |
10635 | (set_attr "length" "4,8")]) | |
10636 | ||
10637 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10638 | [(set (match_operand 0 "" "") |
a5c76ee6 ZW |
10639 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) |
10640 | (match_operand 2 "" "g,g"))) | |
10641 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10642 | (clobber (match_scratch:SI 4 "=l,l"))] | |
50d440bc | 10643 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10644 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10645 | { |
6a4cee5f | 10646 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10647 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10648 | |
10649 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10650 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10651 | |
a5c76ee6 ZW |
10652 | return "b%T1l"; |
10653 | } | |
10654 | [(set_attr "type" "jmpreg,jmpreg") | |
10655 | (set_attr "length" "4,8")]) | |
10656 | ||
10657 | (define_insn "*call_value_nonlocal_sysv" | |
10658 | [(set (match_operand 0 "" "") | |
10659 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10660 | (match_operand 2 "" "g,g"))) | |
10661 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10662 | (clobber (match_scratch:SI 4 "=l,l"))] | |
efdba735 SH |
10663 | "(DEFAULT_ABI == ABI_DARWIN |
10664 | || (DEFAULT_ABI == ABI_V4 | |
10665 | && (INTVAL (operands[3]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10666 | { |
10667 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10668 | output_asm_insn ("crxor 6,6,6", operands); | |
10669 | ||
10670 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10671 | output_asm_insn ("creqv 6,6,6", operands); | |
10672 | ||
c989f2f7 | 10673 | #if TARGET_MACHO |
efdba735 SH |
10674 | return output_call(insn, operands, 1, 3); |
10675 | #else | |
a5c76ee6 | 10676 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; |
6ae08853 | 10677 | #endif |
a5c76ee6 ZW |
10678 | } |
10679 | [(set_attr "type" "branch,branch") | |
10680 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10681 | |
10682 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10683 | (define_expand "untyped_call" |
10684 | [(parallel [(call (match_operand 0 "" "") | |
10685 | (const_int 0)) | |
10686 | (match_operand 1 "" "") | |
10687 | (match_operand 2 "" "")])] | |
10688 | "" | |
10689 | " | |
10690 | { | |
10691 | int i; | |
10692 | ||
7d70b8b2 | 10693 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10694 | |
10695 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10696 | { | |
10697 | rtx set = XVECEXP (operands[2], 0, i); | |
10698 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10699 | } | |
10700 | ||
10701 | /* The optimizer does not know that the call sets the function value | |
10702 | registers we stored in the result block. We avoid problems by | |
10703 | claiming that all hard registers are used and clobbered at this | |
10704 | point. */ | |
10705 | emit_insn (gen_blockage ()); | |
10706 | ||
10707 | DONE; | |
10708 | }") | |
10709 | ||
5e1bf043 DJ |
10710 | ;; sibling call patterns |
10711 | (define_expand "sibcall" | |
10712 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
10713 | (match_operand 1 "" "")) | |
10714 | (use (match_operand 2 "" "")) | |
fe352c29 | 10715 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
10716 | (return)])] |
10717 | "" | |
10718 | " | |
10719 | { | |
10720 | #if TARGET_MACHO | |
ab82a49f | 10721 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10722 | operands[0] = machopic_indirect_call_target (operands[0]); |
10723 | #endif | |
10724 | ||
10725 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
10726 | abort (); | |
10727 | ||
10728 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 10729 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10730 | |
10731 | }") | |
10732 | ||
10733 | ;; this and similar patterns must be marked as using LR, otherwise | |
10734 | ;; dataflow will try to delete the store into it. This is true | |
10735 | ;; even when the actual reg to jump to is in CTR, when LR was | |
10736 | ;; saved and restored around the PIC-setting BCL. | |
10737 | (define_insn "*sibcall_local32" | |
10738 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
10739 | (match_operand 1 "" "g,g")) | |
10740 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10741 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10742 | (return)] |
10743 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
10744 | "* | |
10745 | { | |
10746 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10747 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10748 | ||
10749 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10750 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10751 | ||
10752 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10753 | }" | |
10754 | [(set_attr "type" "branch") | |
10755 | (set_attr "length" "4,8")]) | |
10756 | ||
10757 | (define_insn "*sibcall_local64" | |
10758 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10759 | (match_operand 1 "" "g,g")) | |
10760 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10761 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10762 | (return)] |
10763 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10764 | "* | |
10765 | { | |
10766 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10767 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10768 | ||
10769 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10770 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10771 | ||
10772 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10773 | }" | |
10774 | [(set_attr "type" "branch") | |
10775 | (set_attr "length" "4,8")]) | |
10776 | ||
10777 | (define_insn "*sibcall_value_local32" | |
10778 | [(set (match_operand 0 "" "") | |
10779 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
10780 | (match_operand 2 "" "g,g"))) | |
10781 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10782 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10783 | (return)] |
10784 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10785 | "* | |
10786 | { | |
10787 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10788 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10789 | ||
10790 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10791 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10792 | ||
10793 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10794 | }" | |
10795 | [(set_attr "type" "branch") | |
10796 | (set_attr "length" "4,8")]) | |
10797 | ||
10798 | ||
10799 | (define_insn "*sibcall_value_local64" | |
10800 | [(set (match_operand 0 "" "") | |
10801 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
10802 | (match_operand 2 "" "g,g"))) | |
10803 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10804 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10805 | (return)] |
10806 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10807 | "* | |
10808 | { | |
10809 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10810 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10811 | ||
10812 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10813 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10814 | ||
10815 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10816 | }" | |
10817 | [(set_attr "type" "branch") | |
10818 | (set_attr "length" "4,8")]) | |
10819 | ||
10820 | (define_insn "*sibcall_nonlocal_aix32" | |
10821 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
10822 | (match_operand 1 "" "g")) | |
10823 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10824 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10825 | (return)] |
10826 | "TARGET_32BIT | |
10827 | && DEFAULT_ABI == ABI_AIX | |
10828 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10829 | "b %z0" | |
10830 | [(set_attr "type" "branch") | |
10831 | (set_attr "length" "4")]) | |
10832 | ||
10833 | (define_insn "*sibcall_nonlocal_aix64" | |
10834 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
10835 | (match_operand 1 "" "g")) | |
10836 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10837 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 | 10838 | (return)] |
6ae08853 | 10839 | "TARGET_64BIT |
5e1bf043 DJ |
10840 | && DEFAULT_ABI == ABI_AIX |
10841 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10842 | "b %z0" | |
10843 | [(set_attr "type" "branch") | |
10844 | (set_attr "length" "4")]) | |
10845 | ||
10846 | (define_insn "*sibcall_value_nonlocal_aix32" | |
10847 | [(set (match_operand 0 "" "") | |
10848 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
10849 | (match_operand 2 "" "g"))) | |
10850 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10851 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10852 | (return)] |
10853 | "TARGET_32BIT | |
10854 | && DEFAULT_ABI == ABI_AIX | |
10855 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10856 | "b %z1" | |
10857 | [(set_attr "type" "branch") | |
10858 | (set_attr "length" "4")]) | |
10859 | ||
10860 | (define_insn "*sibcall_value_nonlocal_aix64" | |
10861 | [(set (match_operand 0 "" "") | |
10862 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
10863 | (match_operand 2 "" "g"))) | |
10864 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10865 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 | 10866 | (return)] |
6ae08853 | 10867 | "TARGET_64BIT |
5e1bf043 DJ |
10868 | && DEFAULT_ABI == ABI_AIX |
10869 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10870 | "b %z1" | |
10871 | [(set_attr "type" "branch") | |
10872 | (set_attr "length" "4")]) | |
10873 | ||
10874 | (define_insn "*sibcall_nonlocal_sysv" | |
10875 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10876 | (match_operand 1 "" "")) | |
10877 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 10878 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10879 | (return)] |
10880 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10881 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10882 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
10883 | "* | |
10884 | { | |
10885 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10886 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10887 | ||
10888 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10889 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10890 | ||
10891 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; | |
10892 | }" | |
10893 | [(set_attr "type" "branch,branch") | |
10894 | (set_attr "length" "4,8")]) | |
10895 | ||
10896 | (define_expand "sibcall_value" | |
10897 | [(parallel [(set (match_operand 0 "register_operand" "") | |
10898 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
10899 | (match_operand 2 "" ""))) | |
10900 | (use (match_operand 3 "" "")) | |
fe352c29 | 10901 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
10902 | (return)])] |
10903 | "" | |
10904 | " | |
10905 | { | |
10906 | #if TARGET_MACHO | |
ab82a49f | 10907 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10908 | operands[1] = machopic_indirect_call_target (operands[1]); |
10909 | #endif | |
10910 | ||
10911 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
10912 | abort (); | |
10913 | ||
10914 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 10915 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10916 | |
10917 | }") | |
10918 | ||
10919 | (define_insn "*sibcall_value_nonlocal_sysv" | |
10920 | [(set (match_operand 0 "" "") | |
10921 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10922 | (match_operand 2 "" ""))) | |
10923 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10924 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10925 | (return)] |
10926 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10927 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10928 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
10929 | "* | |
10930 | { | |
10931 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10932 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10933 | ||
10934 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10935 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10936 | ||
10937 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; | |
10938 | }" | |
10939 | [(set_attr "type" "branch,branch") | |
10940 | (set_attr "length" "4,8")]) | |
10941 | ||
10942 | (define_expand "sibcall_epilogue" | |
10943 | [(use (const_int 0))] | |
10944 | "TARGET_SCHED_PROLOG" | |
10945 | " | |
10946 | { | |
10947 | rs6000_emit_epilogue (TRUE); | |
10948 | DONE; | |
10949 | }") | |
10950 | ||
e6f948e3 RK |
10951 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
10952 | ;; all of memory. This blocks insns from being moved across this point. | |
10953 | ||
10954 | (define_insn "blockage" | |
615158e2 | 10955 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] |
e6f948e3 RK |
10956 | "" |
10957 | "") | |
1fd4e8c1 RK |
10958 | \f |
10959 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10960 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10961 | ;; |
10962 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10963 | ;; insns, and branches. We store the operands of compares until we see | |
10964 | ;; how it is used. | |
10965 | (define_expand "cmpsi" | |
10966 | [(set (cc0) | |
cd2b37d9 | 10967 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10968 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10969 | "" | |
10970 | " | |
10971 | { | |
10972 | /* Take care of the possibility that operands[1] might be negative but | |
10973 | this might be a logical operation. That insn doesn't exist. */ | |
10974 | if (GET_CODE (operands[1]) == CONST_INT | |
10975 | && INTVAL (operands[1]) < 0) | |
10976 | operands[1] = force_reg (SImode, operands[1]); | |
10977 | ||
10978 | rs6000_compare_op0 = operands[0]; | |
10979 | rs6000_compare_op1 = operands[1]; | |
10980 | rs6000_compare_fp_p = 0; | |
10981 | DONE; | |
10982 | }") | |
10983 | ||
266eb58a DE |
10984 | (define_expand "cmpdi" |
10985 | [(set (cc0) | |
10986 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10987 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10988 | "TARGET_POWERPC64" | |
10989 | " | |
10990 | { | |
10991 | /* Take care of the possibility that operands[1] might be negative but | |
10992 | this might be a logical operation. That insn doesn't exist. */ | |
10993 | if (GET_CODE (operands[1]) == CONST_INT | |
10994 | && INTVAL (operands[1]) < 0) | |
10995 | operands[1] = force_reg (DImode, operands[1]); | |
10996 | ||
10997 | rs6000_compare_op0 = operands[0]; | |
10998 | rs6000_compare_op1 = operands[1]; | |
10999 | rs6000_compare_fp_p = 0; | |
11000 | DONE; | |
11001 | }") | |
11002 | ||
1fd4e8c1 | 11003 | (define_expand "cmpsf" |
cd2b37d9 RK |
11004 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
11005 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 11006 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
11007 | " |
11008 | { | |
11009 | rs6000_compare_op0 = operands[0]; | |
11010 | rs6000_compare_op1 = operands[1]; | |
11011 | rs6000_compare_fp_p = 1; | |
11012 | DONE; | |
11013 | }") | |
11014 | ||
11015 | (define_expand "cmpdf" | |
cd2b37d9 RK |
11016 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
11017 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
7a2f7870 | 11018 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
1fd4e8c1 RK |
11019 | " |
11020 | { | |
11021 | rs6000_compare_op0 = operands[0]; | |
11022 | rs6000_compare_op1 = operands[1]; | |
11023 | rs6000_compare_fp_p = 1; | |
11024 | DONE; | |
11025 | }") | |
11026 | ||
d6f99ca4 | 11027 | (define_expand "cmptf" |
e7a4130e DE |
11028 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
11029 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
39e63627 GK |
11030 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
11031 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
d6f99ca4 DE |
11032 | " |
11033 | { | |
11034 | rs6000_compare_op0 = operands[0]; | |
11035 | rs6000_compare_op1 = operands[1]; | |
11036 | rs6000_compare_fp_p = 1; | |
11037 | DONE; | |
11038 | }") | |
11039 | ||
1fd4e8c1 | 11040 | (define_expand "beq" |
39a10a29 | 11041 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11042 | "" |
39a10a29 | 11043 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11044 | |
11045 | (define_expand "bne" | |
39a10a29 | 11046 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11047 | "" |
39a10a29 | 11048 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 11049 | |
39a10a29 GK |
11050 | (define_expand "bge" |
11051 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11052 | "" |
39a10a29 | 11053 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
11054 | |
11055 | (define_expand "bgt" | |
39a10a29 | 11056 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11057 | "" |
39a10a29 | 11058 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
11059 | |
11060 | (define_expand "ble" | |
39a10a29 | 11061 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11062 | "" |
39a10a29 | 11063 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 11064 | |
39a10a29 GK |
11065 | (define_expand "blt" |
11066 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11067 | "" |
39a10a29 | 11068 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 11069 | |
39a10a29 GK |
11070 | (define_expand "bgeu" |
11071 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11072 | "" |
39a10a29 | 11073 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 11074 | |
39a10a29 GK |
11075 | (define_expand "bgtu" |
11076 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11077 | "" |
39a10a29 | 11078 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 11079 | |
39a10a29 GK |
11080 | (define_expand "bleu" |
11081 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11082 | "" |
39a10a29 | 11083 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 11084 | |
39a10a29 GK |
11085 | (define_expand "bltu" |
11086 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11087 | "" |
39a10a29 | 11088 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11089 | |
1c882ea4 | 11090 | (define_expand "bunordered" |
39a10a29 | 11091 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 11092 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 11093 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11094 | |
11095 | (define_expand "bordered" | |
39a10a29 | 11096 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 11097 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 11098 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11099 | |
11100 | (define_expand "buneq" | |
39a10a29 | 11101 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11102 | "" |
39a10a29 | 11103 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
11104 | |
11105 | (define_expand "bunge" | |
39a10a29 | 11106 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11107 | "" |
39a10a29 | 11108 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
11109 | |
11110 | (define_expand "bungt" | |
39a10a29 | 11111 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11112 | "" |
39a10a29 | 11113 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
11114 | |
11115 | (define_expand "bunle" | |
39a10a29 | 11116 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11117 | "" |
39a10a29 | 11118 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
11119 | |
11120 | (define_expand "bunlt" | |
39a10a29 | 11121 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11122 | "" |
39a10a29 | 11123 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
11124 | |
11125 | (define_expand "bltgt" | |
39a10a29 | 11126 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11127 | "" |
39a10a29 | 11128 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 11129 | |
1fd4e8c1 RK |
11130 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
11131 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
11132 | ;; with an scc insns. However, due to the order that combine see the | |
11133 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
11134 | ;; the cases we don't want to handle. | |
11135 | (define_expand "seq" | |
39a10a29 | 11136 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11137 | "" |
39a10a29 | 11138 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11139 | |
11140 | (define_expand "sne" | |
39a10a29 | 11141 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11142 | "" |
11143 | " | |
6ae08853 | 11144 | { |
39a10a29 | 11145 | if (! rs6000_compare_fp_p) |
1fd4e8c1 RK |
11146 | FAIL; |
11147 | ||
6ae08853 | 11148 | rs6000_emit_sCOND (NE, operands[0]); |
39a10a29 | 11149 | DONE; |
1fd4e8c1 RK |
11150 | }") |
11151 | ||
b7053a3f GK |
11152 | ;; A >= 0 is best done the portable way for A an integer. |
11153 | (define_expand "sge" | |
39a10a29 | 11154 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11155 | "" |
11156 | " | |
5638268e | 11157 | { |
e56d7409 | 11158 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
11159 | FAIL; |
11160 | ||
b7053a3f | 11161 | rs6000_emit_sCOND (GE, operands[0]); |
39a10a29 | 11162 | DONE; |
1fd4e8c1 RK |
11163 | }") |
11164 | ||
b7053a3f GK |
11165 | ;; A > 0 is best done using the portable sequence, so fail in that case. |
11166 | (define_expand "sgt" | |
39a10a29 | 11167 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11168 | "" |
11169 | " | |
5638268e | 11170 | { |
e56d7409 | 11171 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
11172 | FAIL; |
11173 | ||
6ae08853 | 11174 | rs6000_emit_sCOND (GT, operands[0]); |
39a10a29 | 11175 | DONE; |
1fd4e8c1 RK |
11176 | }") |
11177 | ||
b7053a3f GK |
11178 | ;; A <= 0 is best done the portable way for A an integer. |
11179 | (define_expand "sle" | |
39a10a29 | 11180 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11181 | "" |
5638268e DE |
11182 | " |
11183 | { | |
e56d7409 | 11184 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
5638268e DE |
11185 | FAIL; |
11186 | ||
6ae08853 | 11187 | rs6000_emit_sCOND (LE, operands[0]); |
5638268e DE |
11188 | DONE; |
11189 | }") | |
1fd4e8c1 | 11190 | |
b7053a3f GK |
11191 | ;; A < 0 is best done in the portable way for A an integer. |
11192 | (define_expand "slt" | |
39a10a29 | 11193 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11194 | "" |
11195 | " | |
5638268e | 11196 | { |
e56d7409 | 11197 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
11198 | FAIL; |
11199 | ||
6ae08853 | 11200 | rs6000_emit_sCOND (LT, operands[0]); |
39a10a29 | 11201 | DONE; |
1fd4e8c1 RK |
11202 | }") |
11203 | ||
b7053a3f GK |
11204 | (define_expand "sgeu" |
11205 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11206 | "" | |
11207 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") | |
11208 | ||
1fd4e8c1 | 11209 | (define_expand "sgtu" |
39a10a29 | 11210 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11211 | "" |
39a10a29 | 11212 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 11213 | |
b7053a3f GK |
11214 | (define_expand "sleu" |
11215 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11216 | "" | |
11217 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") | |
11218 | ||
1fd4e8c1 | 11219 | (define_expand "sltu" |
39a10a29 | 11220 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11221 | "" |
39a10a29 | 11222 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11223 | |
b7053a3f | 11224 | (define_expand "sunordered" |
39a10a29 | 11225 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
7836a61f | 11226 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
b7053a3f | 11227 | "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") |
1fd4e8c1 | 11228 | |
b7053a3f | 11229 | (define_expand "sordered" |
39a10a29 | 11230 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
7836a61f | 11231 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
b7053a3f GK |
11232 | "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") |
11233 | ||
11234 | (define_expand "suneq" | |
11235 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11236 | "" | |
11237 | "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") | |
11238 | ||
11239 | (define_expand "sunge" | |
11240 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11241 | "" | |
11242 | "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") | |
11243 | ||
11244 | (define_expand "sungt" | |
11245 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11246 | "" | |
11247 | "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") | |
11248 | ||
11249 | (define_expand "sunle" | |
11250 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11251 | "" | |
11252 | "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") | |
11253 | ||
11254 | (define_expand "sunlt" | |
11255 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11256 | "" | |
11257 | "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") | |
11258 | ||
11259 | (define_expand "sltgt" | |
11260 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11261 | "" | |
11262 | "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") | |
11263 | ||
1fd4e8c1 RK |
11264 | \f |
11265 | ;; Here are the actual compare insns. | |
acad7ed3 | 11266 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 11267 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11268 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
11269 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
11270 | "" | |
7f340546 | 11271 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
b54cf83a | 11272 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11273 | |
acad7ed3 | 11274 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
11275 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
11276 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
11277 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11278 | "TARGET_POWERPC64" | |
11279 | "cmpd%I2 %0,%1,%2" | |
b54cf83a | 11280 | [(set_attr "type" "cmp")]) |
266eb58a | 11281 | |
f357808b RK |
11282 | ;; If we are comparing a register for equality with a large constant, |
11283 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
11284 | ;; register for the result of the XOR. | |
11285 | ||
11286 | (define_split | |
11287 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 11288 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 11289 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 11290 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
11291 | "find_single_use (operands[0], insn, 0) |
11292 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
11293 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
11294 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
11295 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
11296 | " | |
11297 | { | |
11298 | /* Get the constant we are comparing against, C, and see what it looks like | |
11299 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
11300 | with C to get the sign-extended value. */ | |
11301 | ||
5f59ecb7 | 11302 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 11303 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 11304 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 11305 | |
89e9f3a8 MM |
11306 | operands[4] = GEN_INT (xorv); |
11307 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
11308 | }") |
11309 | ||
acad7ed3 | 11310 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 11311 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11312 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 11313 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 11314 | "" |
e2c953b6 | 11315 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
b54cf83a | 11316 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11317 | |
acad7ed3 | 11318 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
11319 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
11320 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 11321 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 11322 | "" |
e2c953b6 | 11323 | "cmpld%I2 %0,%1,%b2" |
b54cf83a | 11324 | [(set_attr "type" "cmp")]) |
266eb58a | 11325 | |
1fd4e8c1 RK |
11326 | ;; The following two insns don't exist as single insns, but if we provide |
11327 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
11328 | ;; of the required delay between a compare and branch. We generate code for | |
11329 | ;; them by splitting. | |
11330 | ||
11331 | (define_insn "" | |
11332 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11333 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11334 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 11335 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11336 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11337 | "" | |
baf97f86 RK |
11338 | "#" |
11339 | [(set_attr "length" "8")]) | |
7e69e155 | 11340 | |
1fd4e8c1 RK |
11341 | (define_insn "" |
11342 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11343 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11344 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 11345 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11346 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11347 | "" | |
baf97f86 RK |
11348 | "#" |
11349 | [(set_attr "length" "8")]) | |
7e69e155 | 11350 | |
1fd4e8c1 RK |
11351 | (define_split |
11352 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 11353 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11354 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 11355 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11356 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11357 | "" | |
11358 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
11359 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11360 | ||
11361 | (define_split | |
11362 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 11363 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11364 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 11365 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11366 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11367 | "" | |
11368 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
11369 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11370 | ||
acad7ed3 | 11371 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 11372 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11373 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
11374 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11375 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11376 | "fcmpu %0,%1,%2" |
11377 | [(set_attr "type" "fpcompare")]) | |
11378 | ||
acad7ed3 | 11379 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 11380 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11381 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
11382 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11383 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11384 | "fcmpu %0,%1,%2" |
11385 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
11386 | |
11387 | ;; Only need to compare second words if first words equal | |
11388 | (define_insn "*cmptf_internal1" | |
11389 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11390 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11391 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
de17c25f | 11392 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT |
39e63627 | 11393 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" |
ecb62ae7 | 11394 | "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
11395 | [(set_attr "type" "fpcompare") |
11396 | (set_attr "length" "12")]) | |
de17c25f DE |
11397 | |
11398 | (define_insn_and_split "*cmptf_internal2" | |
11399 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11400 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11401 | (match_operand:TF 2 "gpc_reg_operand" "f"))) | |
11402 | (clobber (match_scratch:DF 3 "=f")) | |
11403 | (clobber (match_scratch:DF 4 "=f")) | |
11404 | (clobber (match_scratch:DF 5 "=f")) | |
11405 | (clobber (match_scratch:DF 6 "=f")) | |
11406 | (clobber (match_scratch:DF 7 "=f")) | |
11407 | (clobber (match_scratch:DF 8 "=f")) | |
11408 | (clobber (match_scratch:DF 9 "=f")) | |
11409 | (clobber (match_scratch:DF 10 "=f"))] | |
11410 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT | |
11411 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
11412 | "#" | |
11413 | "&& reload_completed" | |
11414 | [(set (match_dup 3) (match_dup 13)) | |
11415 | (set (match_dup 4) (match_dup 14)) | |
11416 | (set (match_dup 9) (abs:DF (match_dup 5))) | |
11417 | (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3))) | |
11418 | (set (pc) (if_then_else (ne (match_dup 0) (const_int 0)) | |
11419 | (label_ref (match_dup 11)) | |
11420 | (pc))) | |
11421 | (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7))) | |
11422 | (set (pc) (label_ref (match_dup 12))) | |
11423 | (match_dup 11) | |
11424 | (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7))) | |
11425 | (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8))) | |
11426 | (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9))) | |
11427 | (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4))) | |
11428 | (match_dup 12)] | |
11429 | { | |
11430 | REAL_VALUE_TYPE rv; | |
11431 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
11432 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
11433 | ||
11434 | operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word); | |
11435 | operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word); | |
11436 | operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word); | |
11437 | operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word); | |
11438 | operands[11] = gen_label_rtx (); | |
11439 | operands[12] = gen_label_rtx (); | |
11440 | real_inf (&rv); | |
11441 | operands[13] = force_const_mem (DFmode, | |
11442 | CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode)); | |
11443 | operands[14] = force_const_mem (DFmode, | |
11444 | CONST_DOUBLE_FROM_REAL_VALUE (dconst0, | |
11445 | DFmode)); | |
11446 | if (TARGET_TOC) | |
11447 | { | |
11448 | operands[13] = gen_const_mem (DFmode, | |
11449 | create_TOC_reference (XEXP (operands[13], 0))); | |
11450 | operands[14] = gen_const_mem (DFmode, | |
11451 | create_TOC_reference (XEXP (operands[14], 0))); | |
11452 | set_mem_alias_set (operands[13], get_TOC_alias_set ()); | |
11453 | set_mem_alias_set (operands[14], get_TOC_alias_set ()); | |
11454 | } | |
11455 | }) | |
1fd4e8c1 RK |
11456 | \f |
11457 | ;; Now we have the scc insns. We can do some combinations because of the | |
11458 | ;; way the machine works. | |
11459 | ;; | |
11460 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
11461 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
11462 | ;; cases the insns below which don't use an intermediate CR field will | |
11463 | ;; be used instead. | |
1fd4e8c1 | 11464 | (define_insn "" |
cd2b37d9 | 11465 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11466 | (match_operator:SI 1 "scc_comparison_operator" |
11467 | [(match_operand 2 "cc_reg_operand" "y") | |
11468 | (const_int 0)]))] | |
11469 | "" | |
2c4a9cff DE |
11470 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11471 | [(set (attr "type") | |
11472 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11473 | (const_string "mfcrf") | |
11474 | ] | |
11475 | (const_string "mfcr"))) | |
c1618c0c | 11476 | (set_attr "length" "8")]) |
1fd4e8c1 | 11477 | |
423c1189 | 11478 | ;; Same as above, but get the GT bit. |
6b1fedc3 | 11479 | (define_insn "move_from_CR_eq_bit" |
423c1189 | 11480 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6b1fedc3 | 11481 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))] |
423c1189 AH |
11482 | "TARGET_E500" |
11483 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1" | |
11484 | [(set_attr "type" "mfcr") | |
c1618c0c | 11485 | (set_attr "length" "8")]) |
423c1189 | 11486 | |
a3170dc6 AH |
11487 | ;; Same as above, but get the OV/ORDERED bit. |
11488 | (define_insn "move_from_CR_ov_bit" | |
11489 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
615158e2 | 11490 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] |
a3170dc6 | 11491 | "TARGET_ISEL" |
b7053a3f | 11492 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" |
b54cf83a | 11493 | [(set_attr "type" "mfcr") |
c1618c0c | 11494 | (set_attr "length" "8")]) |
a3170dc6 | 11495 | |
1fd4e8c1 | 11496 | (define_insn "" |
9ebbca7d GK |
11497 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11498 | (match_operator:DI 1 "scc_comparison_operator" | |
11499 | [(match_operand 2 "cc_reg_operand" "y") | |
11500 | (const_int 0)]))] | |
11501 | "TARGET_POWERPC64" | |
2c4a9cff DE |
11502 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11503 | [(set (attr "type") | |
11504 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11505 | (const_string "mfcrf") | |
11506 | ] | |
11507 | (const_string "mfcr"))) | |
c1618c0c | 11508 | (set_attr "length" "8")]) |
9ebbca7d GK |
11509 | |
11510 | (define_insn "" | |
11511 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11512 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 11513 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
11514 | (const_int 0)]) |
11515 | (const_int 0))) | |
9ebbca7d | 11516 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11517 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
4b8a63d6 | 11518 | "TARGET_32BIT" |
9ebbca7d | 11519 | "@ |
2c4a9cff | 11520 | mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 |
9ebbca7d | 11521 | #" |
b19003d8 | 11522 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11523 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11524 | |
11525 | (define_split | |
11526 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11527 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11528 | [(match_operand 2 "cc_reg_operand" "") | |
11529 | (const_int 0)]) | |
11530 | (const_int 0))) | |
11531 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11532 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
4b8a63d6 | 11533 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11534 | [(set (match_dup 3) |
11535 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11536 | (set (match_dup 0) | |
11537 | (compare:CC (match_dup 3) | |
11538 | (const_int 0)))] | |
11539 | "") | |
1fd4e8c1 RK |
11540 | |
11541 | (define_insn "" | |
cd2b37d9 | 11542 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11543 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11544 | [(match_operand 2 "cc_reg_operand" "y") | |
11545 | (const_int 0)]) | |
11546 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11547 | "" | |
11548 | "* | |
11549 | { | |
11550 | int is_bit = ccr_bit (operands[1], 1); | |
11551 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11552 | int count; | |
11553 | ||
11554 | if (is_bit >= put_bit) | |
11555 | count = is_bit - put_bit; | |
11556 | else | |
11557 | count = 32 - (put_bit - is_bit); | |
11558 | ||
89e9f3a8 MM |
11559 | operands[4] = GEN_INT (count); |
11560 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11561 | |
2c4a9cff | 11562 | return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11563 | }" |
2c4a9cff DE |
11564 | [(set (attr "type") |
11565 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11566 | (const_string "mfcrf") | |
11567 | ] | |
11568 | (const_string "mfcr"))) | |
c1618c0c | 11569 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
11570 | |
11571 | (define_insn "" | |
9ebbca7d | 11572 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11573 | (compare:CC |
11574 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11575 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11576 | (const_int 0)]) |
9ebbca7d | 11577 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11578 | (const_int 0))) |
9ebbca7d | 11579 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11580 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11581 | (match_dup 3)))] | |
ce71f754 | 11582 | "" |
1fd4e8c1 RK |
11583 | "* |
11584 | { | |
11585 | int is_bit = ccr_bit (operands[1], 1); | |
11586 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11587 | int count; | |
11588 | ||
9ebbca7d GK |
11589 | /* Force split for non-cc0 compare. */ |
11590 | if (which_alternative == 1) | |
11591 | return \"#\"; | |
11592 | ||
1fd4e8c1 RK |
11593 | if (is_bit >= put_bit) |
11594 | count = is_bit - put_bit; | |
11595 | else | |
11596 | count = 32 - (put_bit - is_bit); | |
11597 | ||
89e9f3a8 MM |
11598 | operands[5] = GEN_INT (count); |
11599 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11600 | |
2c4a9cff | 11601 | return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11602 | }" |
b19003d8 | 11603 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11604 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11605 | |
11606 | (define_split | |
11607 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11608 | (compare:CC | |
11609 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11610 | [(match_operand 2 "cc_reg_operand" "") | |
11611 | (const_int 0)]) | |
11612 | (match_operand:SI 3 "const_int_operand" "")) | |
11613 | (const_int 0))) | |
11614 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11615 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11616 | (match_dup 3)))] | |
ce71f754 | 11617 | "reload_completed" |
9ebbca7d GK |
11618 | [(set (match_dup 4) |
11619 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11620 | (match_dup 3))) | |
11621 | (set (match_dup 0) | |
11622 | (compare:CC (match_dup 4) | |
11623 | (const_int 0)))] | |
11624 | "") | |
1fd4e8c1 | 11625 | |
c5defebb RK |
11626 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11627 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11628 | ||
11629 | (define_peephole | |
cd2b37d9 | 11630 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11631 | (match_operator:SI 1 "scc_comparison_operator" |
11632 | [(match_operand 2 "cc_reg_operand" "y") | |
11633 | (const_int 0)])) | |
cd2b37d9 | 11634 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11635 | (match_operator:SI 4 "scc_comparison_operator" |
11636 | [(match_operand 5 "cc_reg_operand" "y") | |
11637 | (const_int 0)]))] | |
309323c2 | 11638 | "REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11639 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11640 | [(set_attr "type" "mfcr") |
c1618c0c | 11641 | (set_attr "length" "12")]) |
c5defebb | 11642 | |
9ebbca7d GK |
11643 | (define_peephole |
11644 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11645 | (match_operator:DI 1 "scc_comparison_operator" | |
11646 | [(match_operand 2 "cc_reg_operand" "y") | |
11647 | (const_int 0)])) | |
11648 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11649 | (match_operator:DI 4 "scc_comparison_operator" | |
11650 | [(match_operand 5 "cc_reg_operand" "y") | |
11651 | (const_int 0)]))] | |
309323c2 | 11652 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11653 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11654 | [(set_attr "type" "mfcr") |
c1618c0c | 11655 | (set_attr "length" "12")]) |
9ebbca7d | 11656 | |
1fd4e8c1 RK |
11657 | ;; There are some scc insns that can be done directly, without a compare. |
11658 | ;; These are faster because they don't involve the communications between | |
11659 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11660 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11661 | ;; | |
11662 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11663 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11664 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11665 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11666 | ||
11667 | ;; Have reload force a constant into a register for the simple insns that | |
11668 | ;; otherwise won't accept constants. We do this because it is faster than | |
11669 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11670 | ||
11671 | (define_insn "" | |
cd2b37d9 RK |
11672 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11673 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11674 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11675 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
683bdff7 | 11676 | "TARGET_32BIT" |
1fd4e8c1 | 11677 | "@ |
ca7f5001 | 11678 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11679 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11680 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11681 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
11682 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
943c15ed DE |
11683 | [(set_attr "type" "three,two,three,three,three") |
11684 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 | 11685 | |
a260abc9 DE |
11686 | (define_insn "" |
11687 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
11688 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
11689 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
11690 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
683bdff7 | 11691 | "TARGET_64BIT" |
a260abc9 DE |
11692 | "@ |
11693 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11694 | subfic %3,%1,0\;adde %0,%3,%1 | |
11695 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11696 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11697 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
943c15ed DE |
11698 | [(set_attr "type" "three,two,three,three,three") |
11699 | (set_attr "length" "12,8,12,12,12")]) | |
a260abc9 | 11700 | |
1fd4e8c1 | 11701 | (define_insn "" |
9ebbca7d | 11702 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11703 | (compare:CC |
9ebbca7d GK |
11704 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11705 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 11706 | (const_int 0))) |
9ebbca7d | 11707 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11708 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11709 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11710 | "TARGET_32BIT" |
1fd4e8c1 | 11711 | "@ |
ca7f5001 RK |
11712 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11713 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
11714 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
11715 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
11716 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11717 | # | |
11718 | # | |
11719 | # | |
11720 | # | |
11721 | #" | |
b19003d8 | 11722 | [(set_attr "type" "compare") |
9ebbca7d GK |
11723 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11724 | ||
11725 | (define_split | |
11726 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11727 | (compare:CC | |
11728 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11729 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11730 | (const_int 0))) | |
11731 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11732 | (eq:SI (match_dup 1) (match_dup 2))) | |
11733 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11734 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11735 | [(parallel [(set (match_dup 0) |
11736 | (eq:SI (match_dup 1) (match_dup 2))) | |
11737 | (clobber (match_dup 3))]) | |
11738 | (set (match_dup 4) | |
11739 | (compare:CC (match_dup 0) | |
11740 | (const_int 0)))] | |
11741 | "") | |
b19003d8 | 11742 | |
a260abc9 | 11743 | (define_insn "" |
9ebbca7d | 11744 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 11745 | (compare:CC |
9ebbca7d GK |
11746 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11747 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 11748 | (const_int 0))) |
9ebbca7d | 11749 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 11750 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11751 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11752 | "TARGET_64BIT" |
a260abc9 DE |
11753 | "@ |
11754 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11755 | subfic %3,%1,0\;adde. %0,%3,%1 | |
11756 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11757 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
11758 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
11759 | # | |
11760 | # | |
11761 | # | |
11762 | # | |
11763 | #" | |
a260abc9 | 11764 | [(set_attr "type" "compare") |
9ebbca7d GK |
11765 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11766 | ||
11767 | (define_split | |
11768 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11769 | (compare:CC | |
11770 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11771 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
11772 | (const_int 0))) | |
11773 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11774 | (eq:DI (match_dup 1) (match_dup 2))) | |
11775 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11776 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11777 | [(parallel [(set (match_dup 0) |
11778 | (eq:DI (match_dup 1) (match_dup 2))) | |
11779 | (clobber (match_dup 3))]) | |
11780 | (set (match_dup 4) | |
11781 | (compare:CC (match_dup 0) | |
11782 | (const_int 0)))] | |
11783 | "") | |
a260abc9 | 11784 | |
b19003d8 RK |
11785 | ;; We have insns of the form shown by the first define_insn below. If |
11786 | ;; there is something inside the comparison operation, we must split it. | |
11787 | (define_split | |
11788 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11789 | (plus:SI (match_operator 1 "comparison_operator" | |
11790 | [(match_operand:SI 2 "" "") | |
11791 | (match_operand:SI 3 | |
11792 | "reg_or_cint_operand" "")]) | |
11793 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11794 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11795 | "! gpc_reg_operand (operands[2], SImode)" | |
11796 | [(set (match_dup 5) (match_dup 2)) | |
11797 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11798 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11799 | |
11800 | (define_insn "" | |
5276df18 | 11801 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11802 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11803 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 11804 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
683bdff7 | 11805 | "TARGET_32BIT" |
1fd4e8c1 | 11806 | "@ |
5276df18 DE |
11807 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11808 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11809 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11810 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11811 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
943c15ed DE |
11812 | [(set_attr "type" "three,two,three,three,three") |
11813 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 RK |
11814 | |
11815 | (define_insn "" | |
9ebbca7d | 11816 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11817 | (compare:CC |
1fd4e8c1 | 11818 | (plus:SI |
9ebbca7d GK |
11819 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11820 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11821 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11822 | (const_int 0))) |
9ebbca7d | 11823 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
683bdff7 | 11824 | "TARGET_32BIT" |
1fd4e8c1 | 11825 | "@ |
ca7f5001 | 11826 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11827 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11828 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11829 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11830 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11831 | # | |
11832 | # | |
11833 | # | |
11834 | # | |
11835 | #" | |
b19003d8 | 11836 | [(set_attr "type" "compare") |
9ebbca7d GK |
11837 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11838 | ||
11839 | (define_split | |
11840 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11841 | (compare:CC | |
11842 | (plus:SI | |
11843 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11844 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11845 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11846 | (const_int 0))) | |
11847 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11848 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11849 | [(set (match_dup 4) |
11850 | (plus:SI (eq:SI (match_dup 1) | |
11851 | (match_dup 2)) | |
11852 | (match_dup 3))) | |
11853 | (set (match_dup 0) | |
11854 | (compare:CC (match_dup 4) | |
11855 | (const_int 0)))] | |
11856 | "") | |
1fd4e8c1 RK |
11857 | |
11858 | (define_insn "" | |
0387639b | 11859 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11860 | (compare:CC |
1fd4e8c1 | 11861 | (plus:SI |
9ebbca7d GK |
11862 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11863 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11864 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11865 | (const_int 0))) |
0387639b DE |
11866 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11867 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 11868 | "TARGET_32BIT" |
1fd4e8c1 | 11869 | "@ |
0387639b DE |
11870 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11871 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11872 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11873 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11874 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11875 | # |
11876 | # | |
11877 | # | |
11878 | # | |
11879 | #" | |
11880 | [(set_attr "type" "compare") | |
11881 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11882 | ||
11883 | (define_split | |
0387639b | 11884 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11885 | (compare:CC |
11886 | (plus:SI | |
11887 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11888 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11889 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11890 | (const_int 0))) | |
11891 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11892 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 11893 | "TARGET_32BIT && reload_completed" |
0387639b | 11894 | [(set (match_dup 0) |
9ebbca7d | 11895 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11896 | (set (match_dup 4) |
9ebbca7d GK |
11897 | (compare:CC (match_dup 0) |
11898 | (const_int 0)))] | |
11899 | "") | |
11900 | ||
1fd4e8c1 | 11901 | (define_insn "" |
cd2b37d9 | 11902 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11903 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11904 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
683bdff7 | 11905 | "TARGET_32BIT" |
1fd4e8c1 | 11906 | "@ |
ca7f5001 RK |
11907 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11908 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11909 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11910 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11911 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
943c15ed DE |
11912 | [(set_attr "type" "three,two,three,three,three") |
11913 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 | 11914 | |
ea9be077 MM |
11915 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11916 | ;; since it nabs/sr is just as fast. | |
463b558b | 11917 | (define_insn "*ne0" |
b4e95693 | 11918 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11919 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11920 | (const_int 31))) | |
11921 | (clobber (match_scratch:SI 2 "=&r"))] | |
683bdff7 | 11922 | "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" |
ea9be077 | 11923 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
943c15ed DE |
11924 | [(set_attr "type" "two") |
11925 | (set_attr "length" "8")]) | |
ea9be077 | 11926 | |
a260abc9 DE |
11927 | (define_insn "" |
11928 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11929 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11930 | (const_int 63))) | |
11931 | (clobber (match_scratch:DI 2 "=&r"))] | |
683bdff7 | 11932 | "TARGET_64BIT" |
a260abc9 | 11933 | "addic %2,%1,-1\;subfe %0,%2,%1" |
943c15ed DE |
11934 | [(set_attr "type" "two") |
11935 | (set_attr "length" "8")]) | |
a260abc9 | 11936 | |
1fd4e8c1 RK |
11937 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11938 | (define_insn "" | |
cd2b37d9 | 11939 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11940 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11941 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11942 | (const_int 31)) |
cd2b37d9 | 11943 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11944 | (clobber (match_scratch:SI 3 "=&r"))] |
683bdff7 | 11945 | "TARGET_32BIT" |
ca7f5001 | 11946 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
943c15ed DE |
11947 | [(set_attr "type" "two") |
11948 | (set_attr "length" "8")]) | |
1fd4e8c1 | 11949 | |
a260abc9 DE |
11950 | (define_insn "" |
11951 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11952 | (plus:DI (lshiftrt:DI | |
11953 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11954 | (const_int 63)) | |
11955 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11956 | (clobber (match_scratch:DI 3 "=&r"))] | |
683bdff7 | 11957 | "TARGET_64BIT" |
a260abc9 | 11958 | "addic %3,%1,-1\;addze %0,%2" |
943c15ed DE |
11959 | [(set_attr "type" "two") |
11960 | (set_attr "length" "8")]) | |
a260abc9 | 11961 | |
1fd4e8c1 | 11962 | (define_insn "" |
9ebbca7d | 11963 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11964 | (compare:CC |
11965 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11966 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11967 | (const_int 31)) |
9ebbca7d | 11968 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11969 | (const_int 0))) |
889b90a1 GK |
11970 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11971 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
683bdff7 | 11972 | "TARGET_32BIT" |
9ebbca7d GK |
11973 | "@ |
11974 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11975 | #" | |
b19003d8 | 11976 | [(set_attr "type" "compare") |
9ebbca7d GK |
11977 | (set_attr "length" "8,12")]) |
11978 | ||
11979 | (define_split | |
11980 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11981 | (compare:CC | |
11982 | (plus:SI (lshiftrt:SI | |
11983 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11984 | (const_int 31)) | |
11985 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11986 | (const_int 0))) | |
889b90a1 GK |
11987 | (clobber (match_scratch:SI 3 "")) |
11988 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11989 | "TARGET_32BIT && reload_completed" |
889b90a1 | 11990 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
11991 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
11992 | (const_int 31)) | |
11993 | (match_dup 2))) | |
889b90a1 | 11994 | (clobber (match_dup 4))]) |
9ebbca7d GK |
11995 | (set (match_dup 0) |
11996 | (compare:CC (match_dup 3) | |
11997 | (const_int 0)))] | |
11998 | "") | |
1fd4e8c1 | 11999 | |
a260abc9 | 12000 | (define_insn "" |
9ebbca7d | 12001 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
12002 | (compare:CC |
12003 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 12004 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 12005 | (const_int 63)) |
9ebbca7d | 12006 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 12007 | (const_int 0))) |
9ebbca7d | 12008 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 12009 | "TARGET_64BIT" |
9ebbca7d GK |
12010 | "@ |
12011 | addic %3,%1,-1\;addze. %3,%2 | |
12012 | #" | |
a260abc9 | 12013 | [(set_attr "type" "compare") |
9ebbca7d GK |
12014 | (set_attr "length" "8,12")]) |
12015 | ||
12016 | (define_split | |
12017 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12018 | (compare:CC | |
12019 | (plus:DI (lshiftrt:DI | |
12020 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
12021 | (const_int 63)) | |
12022 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12023 | (const_int 0))) | |
12024 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 12025 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12026 | [(set (match_dup 3) |
12027 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
12028 | (const_int 63)) | |
12029 | (match_dup 2))) | |
12030 | (set (match_dup 0) | |
12031 | (compare:CC (match_dup 3) | |
12032 | (const_int 0)))] | |
12033 | "") | |
a260abc9 | 12034 | |
1fd4e8c1 | 12035 | (define_insn "" |
9ebbca7d | 12036 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12037 | (compare:CC |
12038 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 12039 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 12040 | (const_int 31)) |
9ebbca7d | 12041 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12042 | (const_int 0))) |
9ebbca7d | 12043 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
12044 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
12045 | (match_dup 2))) | |
9ebbca7d | 12046 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 12047 | "TARGET_32BIT" |
9ebbca7d GK |
12048 | "@ |
12049 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
12050 | #" | |
b19003d8 | 12051 | [(set_attr "type" "compare") |
9ebbca7d GK |
12052 | (set_attr "length" "8,12")]) |
12053 | ||
12054 | (define_split | |
12055 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12056 | (compare:CC | |
12057 | (plus:SI (lshiftrt:SI | |
12058 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
12059 | (const_int 31)) | |
12060 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12061 | (const_int 0))) | |
12062 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12063 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
12064 | (match_dup 2))) | |
12065 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 12066 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12067 | [(parallel [(set (match_dup 0) |
12068 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
12069 | (match_dup 2))) | |
12070 | (clobber (match_dup 3))]) | |
12071 | (set (match_dup 4) | |
12072 | (compare:CC (match_dup 0) | |
12073 | (const_int 0)))] | |
12074 | "") | |
1fd4e8c1 | 12075 | |
a260abc9 | 12076 | (define_insn "" |
9ebbca7d | 12077 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
12078 | (compare:CC |
12079 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 12080 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 12081 | (const_int 63)) |
9ebbca7d | 12082 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 12083 | (const_int 0))) |
9ebbca7d | 12084 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
12085 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
12086 | (match_dup 2))) | |
9ebbca7d | 12087 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 12088 | "TARGET_64BIT" |
9ebbca7d GK |
12089 | "@ |
12090 | addic %3,%1,-1\;addze. %0,%2 | |
12091 | #" | |
a260abc9 | 12092 | [(set_attr "type" "compare") |
9ebbca7d GK |
12093 | (set_attr "length" "8,12")]) |
12094 | ||
12095 | (define_split | |
12096 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12097 | (compare:CC | |
12098 | (plus:DI (lshiftrt:DI | |
12099 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
12100 | (const_int 63)) | |
12101 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12102 | (const_int 0))) | |
12103 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12104 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
12105 | (match_dup 2))) | |
12106 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 12107 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12108 | [(parallel [(set (match_dup 0) |
12109 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
12110 | (match_dup 2))) | |
12111 | (clobber (match_dup 3))]) | |
12112 | (set (match_dup 4) | |
12113 | (compare:CC (match_dup 0) | |
12114 | (const_int 0)))] | |
12115 | "") | |
a260abc9 | 12116 | |
1fd4e8c1 | 12117 | (define_insn "" |
cd2b37d9 RK |
12118 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12119 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
12120 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
12121 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 12122 | "TARGET_POWER" |
1fd4e8c1 | 12123 | "@ |
ca7f5001 | 12124 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 12125 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12126 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12127 | |
12128 | (define_insn "" | |
9ebbca7d | 12129 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12130 | (compare:CC |
9ebbca7d GK |
12131 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12132 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 12133 | (const_int 0))) |
9ebbca7d | 12134 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12135 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12136 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 12137 | "TARGET_POWER" |
1fd4e8c1 | 12138 | "@ |
ca7f5001 | 12139 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
12140 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
12141 | # | |
12142 | #" | |
12143 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
12144 | (set_attr "length" "12,12,16,16")]) | |
12145 | ||
12146 | (define_split | |
12147 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12148 | (compare:CC | |
12149 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12150 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12151 | (const_int 0))) | |
12152 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12153 | (le:SI (match_dup 1) (match_dup 2))) | |
12154 | (clobber (match_scratch:SI 3 ""))] | |
12155 | "TARGET_POWER && reload_completed" | |
12156 | [(parallel [(set (match_dup 0) | |
12157 | (le:SI (match_dup 1) (match_dup 2))) | |
12158 | (clobber (match_dup 3))]) | |
12159 | (set (match_dup 4) | |
12160 | (compare:CC (match_dup 0) | |
12161 | (const_int 0)))] | |
12162 | "") | |
1fd4e8c1 RK |
12163 | |
12164 | (define_insn "" | |
097657c3 | 12165 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12166 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12167 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 12168 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 12169 | "TARGET_POWER" |
1fd4e8c1 | 12170 | "@ |
097657c3 AM |
12171 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
12172 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 12173 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12174 | |
12175 | (define_insn "" | |
9ebbca7d | 12176 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12177 | (compare:CC |
9ebbca7d GK |
12178 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12179 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12180 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12181 | (const_int 0))) |
9ebbca7d | 12182 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 12183 | "TARGET_POWER" |
1fd4e8c1 | 12184 | "@ |
ca7f5001 | 12185 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12186 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
12187 | # | |
12188 | #" | |
b19003d8 | 12189 | [(set_attr "type" "compare") |
9ebbca7d GK |
12190 | (set_attr "length" "12,12,16,16")]) |
12191 | ||
12192 | (define_split | |
12193 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12194 | (compare:CC | |
12195 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12196 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12197 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12198 | (const_int 0))) | |
12199 | (clobber (match_scratch:SI 4 ""))] | |
12200 | "TARGET_POWER && reload_completed" | |
12201 | [(set (match_dup 4) | |
12202 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12203 | (match_dup 3))) |
9ebbca7d GK |
12204 | (set (match_dup 0) |
12205 | (compare:CC (match_dup 4) | |
12206 | (const_int 0)))] | |
12207 | "") | |
1fd4e8c1 RK |
12208 | |
12209 | (define_insn "" | |
097657c3 | 12210 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12211 | (compare:CC |
9ebbca7d GK |
12212 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12213 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12214 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12215 | (const_int 0))) |
097657c3 AM |
12216 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12217 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12218 | "TARGET_POWER" |
1fd4e8c1 | 12219 | "@ |
097657c3 AM |
12220 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
12221 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12222 | # |
12223 | #" | |
b19003d8 | 12224 | [(set_attr "type" "compare") |
9ebbca7d GK |
12225 | (set_attr "length" "12,12,16,16")]) |
12226 | ||
12227 | (define_split | |
097657c3 | 12228 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12229 | (compare:CC |
12230 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12231 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12232 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12233 | (const_int 0))) | |
12234 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12235 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12236 | "TARGET_POWER && reload_completed" |
097657c3 | 12237 | [(set (match_dup 0) |
9ebbca7d | 12238 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12239 | (set (match_dup 4) |
9ebbca7d GK |
12240 | (compare:CC (match_dup 0) |
12241 | (const_int 0)))] | |
12242 | "") | |
1fd4e8c1 RK |
12243 | |
12244 | (define_insn "" | |
cd2b37d9 RK |
12245 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12246 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12247 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 12248 | "TARGET_POWER" |
1fd4e8c1 | 12249 | "@ |
ca7f5001 RK |
12250 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
12251 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12252 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12253 | |
12254 | (define_insn "" | |
cd2b37d9 RK |
12255 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12256 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12257 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
4b8a63d6 | 12258 | "TARGET_32BIT" |
ca7f5001 | 12259 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
943c15ed DE |
12260 | [(set_attr "type" "three") |
12261 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12262 | |
f9562f27 DE |
12263 | (define_insn "" |
12264 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12265 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12266 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 12267 | "TARGET_64BIT" |
f9562f27 | 12268 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" |
943c15ed DE |
12269 | [(set_attr "type" "three") |
12270 | (set_attr "length" "12")]) | |
f9562f27 DE |
12271 | |
12272 | (define_insn "" | |
9ebbca7d | 12273 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12274 | (compare:CC |
9ebbca7d GK |
12275 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12276 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12277 | (const_int 0))) |
9ebbca7d | 12278 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 12279 | (leu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12280 | "TARGET_64BIT" |
9ebbca7d GK |
12281 | "@ |
12282 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
12283 | #" | |
f9562f27 | 12284 | [(set_attr "type" "compare") |
9ebbca7d GK |
12285 | (set_attr "length" "12,16")]) |
12286 | ||
12287 | (define_split | |
12288 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12289 | (compare:CC | |
12290 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12291 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12292 | (const_int 0))) | |
12293 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12294 | (leu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12295 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12296 | [(set (match_dup 0) |
12297 | (leu:DI (match_dup 1) (match_dup 2))) | |
12298 | (set (match_dup 3) | |
12299 | (compare:CC (match_dup 0) | |
12300 | (const_int 0)))] | |
12301 | "") | |
f9562f27 | 12302 | |
1fd4e8c1 | 12303 | (define_insn "" |
9ebbca7d | 12304 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12305 | (compare:CC |
9ebbca7d GK |
12306 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12307 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12308 | (const_int 0))) |
9ebbca7d | 12309 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12310 | (leu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12311 | "TARGET_32BIT" |
9ebbca7d GK |
12312 | "@ |
12313 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
12314 | #" | |
b19003d8 | 12315 | [(set_attr "type" "compare") |
9ebbca7d GK |
12316 | (set_attr "length" "12,16")]) |
12317 | ||
12318 | (define_split | |
12319 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12320 | (compare:CC | |
12321 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12322 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12323 | (const_int 0))) | |
12324 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12325 | (leu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12326 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12327 | [(set (match_dup 0) |
12328 | (leu:SI (match_dup 1) (match_dup 2))) | |
12329 | (set (match_dup 3) | |
12330 | (compare:CC (match_dup 0) | |
12331 | (const_int 0)))] | |
12332 | "") | |
1fd4e8c1 RK |
12333 | |
12334 | (define_insn "" | |
80103f96 | 12335 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12336 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12337 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 12338 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12339 | "TARGET_32BIT" |
80103f96 | 12340 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
943c15ed DE |
12341 | [(set_attr "type" "two") |
12342 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
12343 | |
12344 | (define_insn "" | |
9ebbca7d | 12345 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12346 | (compare:CC |
9ebbca7d GK |
12347 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12348 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12349 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12350 | (const_int 0))) |
9ebbca7d | 12351 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12352 | "TARGET_32BIT" |
9ebbca7d GK |
12353 | "@ |
12354 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
12355 | #" | |
b19003d8 | 12356 | [(set_attr "type" "compare") |
9ebbca7d GK |
12357 | (set_attr "length" "8,12")]) |
12358 | ||
12359 | (define_split | |
12360 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12361 | (compare:CC | |
12362 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12363 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12364 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12365 | (const_int 0))) | |
12366 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12367 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12368 | [(set (match_dup 4) |
12369 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
12370 | (match_dup 3))) | |
12371 | (set (match_dup 0) | |
12372 | (compare:CC (match_dup 4) | |
12373 | (const_int 0)))] | |
12374 | "") | |
1fd4e8c1 RK |
12375 | |
12376 | (define_insn "" | |
097657c3 | 12377 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12378 | (compare:CC |
9ebbca7d GK |
12379 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12380 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12381 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12382 | (const_int 0))) |
097657c3 AM |
12383 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12384 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12385 | "TARGET_32BIT" |
9ebbca7d | 12386 | "@ |
097657c3 | 12387 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 12388 | #" |
b19003d8 | 12389 | [(set_attr "type" "compare") |
9ebbca7d GK |
12390 | (set_attr "length" "8,12")]) |
12391 | ||
12392 | (define_split | |
097657c3 | 12393 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12394 | (compare:CC |
12395 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12396 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12397 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12398 | (const_int 0))) | |
12399 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12400 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12401 | "TARGET_32BIT && reload_completed" |
097657c3 | 12402 | [(set (match_dup 0) |
9ebbca7d | 12403 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12404 | (set (match_dup 4) |
9ebbca7d GK |
12405 | (compare:CC (match_dup 0) |
12406 | (const_int 0)))] | |
12407 | "") | |
1fd4e8c1 RK |
12408 | |
12409 | (define_insn "" | |
cd2b37d9 RK |
12410 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12411 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12412 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 12413 | "TARGET_32BIT" |
ca7f5001 | 12414 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
943c15ed DE |
12415 | [(set_attr "type" "three") |
12416 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12417 | |
12418 | (define_insn "" | |
097657c3 | 12419 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 12420 | (and:SI (neg:SI |
cd2b37d9 | 12421 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12422 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 12423 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12424 | "TARGET_32BIT" |
097657c3 | 12425 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
943c15ed DE |
12426 | [(set_attr "type" "three") |
12427 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12428 | |
12429 | (define_insn "" | |
9ebbca7d | 12430 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12431 | (compare:CC |
12432 | (and:SI (neg:SI | |
9ebbca7d GK |
12433 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12434 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12435 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12436 | (const_int 0))) |
9ebbca7d | 12437 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12438 | "TARGET_32BIT" |
9ebbca7d GK |
12439 | "@ |
12440 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
12441 | #" | |
12442 | [(set_attr "type" "compare") | |
12443 | (set_attr "length" "12,16")]) | |
12444 | ||
12445 | (define_split | |
12446 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12447 | (compare:CC | |
12448 | (and:SI (neg:SI | |
12449 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12450 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12451 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12452 | (const_int 0))) | |
12453 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12454 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12455 | [(set (match_dup 4) |
097657c3 AM |
12456 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
12457 | (match_dup 3))) | |
9ebbca7d GK |
12458 | (set (match_dup 0) |
12459 | (compare:CC (match_dup 4) | |
12460 | (const_int 0)))] | |
12461 | "") | |
1fd4e8c1 RK |
12462 | |
12463 | (define_insn "" | |
097657c3 | 12464 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12465 | (compare:CC |
12466 | (and:SI (neg:SI | |
9ebbca7d GK |
12467 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12468 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12469 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12470 | (const_int 0))) |
097657c3 AM |
12471 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12472 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12473 | "TARGET_32BIT" |
9ebbca7d | 12474 | "@ |
097657c3 | 12475 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 12476 | #" |
b19003d8 | 12477 | [(set_attr "type" "compare") |
9ebbca7d GK |
12478 | (set_attr "length" "12,16")]) |
12479 | ||
12480 | (define_split | |
097657c3 | 12481 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12482 | (compare:CC |
12483 | (and:SI (neg:SI | |
12484 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12485 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12486 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12487 | (const_int 0))) | |
12488 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12489 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 12490 | "TARGET_32BIT && reload_completed" |
097657c3 AM |
12491 | [(set (match_dup 0) |
12492 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
12493 | (match_dup 3))) | |
12494 | (set (match_dup 4) | |
9ebbca7d GK |
12495 | (compare:CC (match_dup 0) |
12496 | (const_int 0)))] | |
12497 | "") | |
1fd4e8c1 RK |
12498 | |
12499 | (define_insn "" | |
cd2b37d9 RK |
12500 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12501 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12502 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 12503 | "TARGET_POWER" |
7f340546 | 12504 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12505 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12506 | |
12507 | (define_insn "" | |
9ebbca7d | 12508 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12509 | (compare:CC |
9ebbca7d GK |
12510 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12511 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12512 | (const_int 0))) |
9ebbca7d | 12513 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12514 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12515 | "TARGET_POWER" |
9ebbca7d GK |
12516 | "@ |
12517 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12518 | #" | |
29ae5b89 | 12519 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12520 | (set_attr "length" "12,16")]) |
12521 | ||
12522 | (define_split | |
12523 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12524 | (compare:CC | |
12525 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12526 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12527 | (const_int 0))) | |
12528 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12529 | (lt:SI (match_dup 1) (match_dup 2)))] | |
12530 | "TARGET_POWER && reload_completed" | |
12531 | [(set (match_dup 0) | |
12532 | (lt:SI (match_dup 1) (match_dup 2))) | |
12533 | (set (match_dup 3) | |
12534 | (compare:CC (match_dup 0) | |
12535 | (const_int 0)))] | |
12536 | "") | |
1fd4e8c1 RK |
12537 | |
12538 | (define_insn "" | |
097657c3 | 12539 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12540 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12541 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12542 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12543 | "TARGET_POWER" |
097657c3 | 12544 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12545 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12546 | |
12547 | (define_insn "" | |
9ebbca7d | 12548 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12549 | (compare:CC |
9ebbca7d GK |
12550 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12551 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12552 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12553 | (const_int 0))) |
9ebbca7d | 12554 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12555 | "TARGET_POWER" |
9ebbca7d GK |
12556 | "@ |
12557 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12558 | #" | |
b19003d8 | 12559 | [(set_attr "type" "compare") |
9ebbca7d GK |
12560 | (set_attr "length" "12,16")]) |
12561 | ||
12562 | (define_split | |
12563 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12564 | (compare:CC | |
12565 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12566 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12567 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12568 | (const_int 0))) | |
12569 | (clobber (match_scratch:SI 4 ""))] | |
12570 | "TARGET_POWER && reload_completed" | |
12571 | [(set (match_dup 4) | |
12572 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12573 | (match_dup 3))) |
9ebbca7d GK |
12574 | (set (match_dup 0) |
12575 | (compare:CC (match_dup 4) | |
12576 | (const_int 0)))] | |
12577 | "") | |
1fd4e8c1 RK |
12578 | |
12579 | (define_insn "" | |
097657c3 | 12580 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12581 | (compare:CC |
9ebbca7d GK |
12582 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12583 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12584 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12585 | (const_int 0))) |
097657c3 AM |
12586 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12587 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12588 | "TARGET_POWER" |
9ebbca7d | 12589 | "@ |
097657c3 | 12590 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12591 | #" |
b19003d8 | 12592 | [(set_attr "type" "compare") |
9ebbca7d GK |
12593 | (set_attr "length" "12,16")]) |
12594 | ||
12595 | (define_split | |
097657c3 | 12596 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12597 | (compare:CC |
12598 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12599 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12600 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12601 | (const_int 0))) | |
12602 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12603 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12604 | "TARGET_POWER && reload_completed" |
097657c3 | 12605 | [(set (match_dup 0) |
9ebbca7d | 12606 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12607 | (set (match_dup 4) |
9ebbca7d GK |
12608 | (compare:CC (match_dup 0) |
12609 | (const_int 0)))] | |
12610 | "") | |
1fd4e8c1 RK |
12611 | |
12612 | (define_insn "" | |
cd2b37d9 RK |
12613 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12614 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12615 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12616 | "TARGET_POWER" |
12617 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12618 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12619 | |
c0600ecd | 12620 | (define_insn_and_split "" |
cd2b37d9 RK |
12621 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12622 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12623 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12624 | "TARGET_32BIT" |
c0600ecd DE |
12625 | "#" |
12626 | "TARGET_32BIT" | |
12627 | [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) | |
12628 | (set (match_dup 0) (neg:SI (match_dup 0)))] | |
12629 | "") | |
12630 | ||
12631 | (define_insn_and_split "" | |
12632 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12633 | (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12634 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
12635 | "TARGET_64BIT" | |
12636 | "#" | |
12637 | "TARGET_64BIT" | |
12638 | [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) | |
12639 | (set (match_dup 0) (neg:DI (match_dup 0)))] | |
12640 | "") | |
1fd4e8c1 RK |
12641 | |
12642 | (define_insn "" | |
9ebbca7d | 12643 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12644 | (compare:CC |
9ebbca7d GK |
12645 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12646 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12647 | (const_int 0))) |
9ebbca7d | 12648 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12649 | (ltu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12650 | "TARGET_32BIT" |
1fd4e8c1 | 12651 | "@ |
ca7f5001 | 12652 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12653 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12654 | # | |
12655 | #" | |
b19003d8 | 12656 | [(set_attr "type" "compare") |
9ebbca7d GK |
12657 | (set_attr "length" "12,12,16,16")]) |
12658 | ||
12659 | (define_split | |
12660 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12661 | (compare:CC | |
12662 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12663 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12664 | (const_int 0))) | |
12665 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12666 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12667 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12668 | [(set (match_dup 0) |
12669 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12670 | (set (match_dup 3) | |
12671 | (compare:CC (match_dup 0) | |
12672 | (const_int 0)))] | |
12673 | "") | |
1fd4e8c1 | 12674 | |
c0600ecd | 12675 | (define_insn_and_split "" |
04fa46cf | 12676 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
c0600ecd DE |
12677 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12678 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
12679 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] | |
683bdff7 | 12680 | "TARGET_32BIT" |
c0600ecd | 12681 | "#" |
04fa46cf | 12682 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
12683 | [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) |
12684 | (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] | |
12685 | "") | |
12686 | ||
12687 | (define_insn_and_split "" | |
04fa46cf | 12688 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
c0600ecd DE |
12689 | (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12690 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")) | |
12691 | (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))] | |
12692 | "TARGET_64BIT" | |
12693 | "#" | |
04fa46cf | 12694 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
12695 | [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) |
12696 | (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] | |
12697 | "") | |
1fd4e8c1 RK |
12698 | |
12699 | (define_insn "" | |
9ebbca7d | 12700 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12701 | (compare:CC |
9ebbca7d GK |
12702 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12703 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12704 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12705 | (const_int 0))) |
9ebbca7d | 12706 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12707 | "TARGET_32BIT" |
1fd4e8c1 | 12708 | "@ |
c9dbf840 DE |
12709 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 |
12710 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 | |
9ebbca7d GK |
12711 | # |
12712 | #" | |
b19003d8 | 12713 | [(set_attr "type" "compare") |
9ebbca7d GK |
12714 | (set_attr "length" "12,12,16,16")]) |
12715 | ||
12716 | (define_split | |
12717 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12718 | (compare:CC | |
12719 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12720 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12721 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12722 | (const_int 0))) | |
12723 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12724 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12725 | [(set (match_dup 4) |
12726 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12727 | (match_dup 3))) |
9ebbca7d GK |
12728 | (set (match_dup 0) |
12729 | (compare:CC (match_dup 4) | |
12730 | (const_int 0)))] | |
12731 | "") | |
1fd4e8c1 RK |
12732 | |
12733 | (define_insn "" | |
097657c3 | 12734 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12735 | (compare:CC |
9ebbca7d GK |
12736 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12737 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12738 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12739 | (const_int 0))) |
097657c3 AM |
12740 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12741 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12742 | "TARGET_32BIT" |
1fd4e8c1 | 12743 | "@ |
c9dbf840 DE |
12744 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 |
12745 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 | |
9ebbca7d GK |
12746 | # |
12747 | #" | |
b19003d8 | 12748 | [(set_attr "type" "compare") |
9ebbca7d GK |
12749 | (set_attr "length" "12,12,16,16")]) |
12750 | ||
12751 | (define_split | |
097657c3 | 12752 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12753 | (compare:CC |
12754 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12755 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12756 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12757 | (const_int 0))) | |
12758 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12759 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12760 | "TARGET_32BIT && reload_completed" |
097657c3 | 12761 | [(set (match_dup 0) |
9ebbca7d | 12762 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12763 | (set (match_dup 4) |
9ebbca7d GK |
12764 | (compare:CC (match_dup 0) |
12765 | (const_int 0)))] | |
12766 | "") | |
1fd4e8c1 RK |
12767 | |
12768 | (define_insn "" | |
cd2b37d9 RK |
12769 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12770 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12771 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
683bdff7 | 12772 | "TARGET_32BIT" |
1fd4e8c1 | 12773 | "@ |
ca7f5001 RK |
12774 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12775 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
943c15ed | 12776 | [(set_attr "type" "two") |
c0600ecd DE |
12777 | (set_attr "length" "8")]) |
12778 | ||
12779 | (define_insn "" | |
12780 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12781 | (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12782 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))] | |
12783 | "TARGET_64BIT" | |
12784 | "@ | |
12785 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 | |
12786 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
943c15ed | 12787 | [(set_attr "type" "two") |
c0600ecd | 12788 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
12789 | |
12790 | (define_insn "" | |
cd2b37d9 RK |
12791 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12792 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12793 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12794 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12795 | "TARGET_POWER" |
12796 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12797 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12798 | |
9ebbca7d GK |
12799 | (define_insn "" |
12800 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12801 | (compare:CC |
9ebbca7d GK |
12802 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12803 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12804 | (const_int 0))) |
9ebbca7d | 12805 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12806 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12807 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12808 | "TARGET_POWER" |
9ebbca7d GK |
12809 | "@ |
12810 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12811 | #" | |
12812 | [(set_attr "type" "compare") | |
12813 | (set_attr "length" "12,16")]) | |
12814 | ||
12815 | (define_split | |
12816 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12817 | (compare:CC | |
12818 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12819 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12820 | (const_int 0))) | |
12821 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12822 | (ge:SI (match_dup 1) (match_dup 2))) | |
12823 | (clobber (match_scratch:SI 3 ""))] | |
12824 | "TARGET_POWER && reload_completed" | |
12825 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12826 | (ge:SI (match_dup 1) (match_dup 2))) |
12827 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12828 | (set (match_dup 4) |
12829 | (compare:CC (match_dup 0) | |
12830 | (const_int 0)))] | |
12831 | "") | |
12832 | ||
1fd4e8c1 | 12833 | (define_insn "" |
097657c3 | 12834 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12835 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12836 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12837 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12838 | "TARGET_POWER" |
097657c3 | 12839 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12840 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12841 | |
12842 | (define_insn "" | |
9ebbca7d | 12843 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12844 | (compare:CC |
9ebbca7d GK |
12845 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12846 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12847 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12848 | (const_int 0))) |
9ebbca7d | 12849 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12850 | "TARGET_POWER" |
9ebbca7d GK |
12851 | "@ |
12852 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12853 | #" | |
b19003d8 | 12854 | [(set_attr "type" "compare") |
9ebbca7d GK |
12855 | (set_attr "length" "12,16")]) |
12856 | ||
12857 | (define_split | |
12858 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12859 | (compare:CC | |
12860 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12861 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12862 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12863 | (const_int 0))) | |
12864 | (clobber (match_scratch:SI 4 ""))] | |
12865 | "TARGET_POWER && reload_completed" | |
12866 | [(set (match_dup 4) | |
12867 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12868 | (match_dup 3))) |
9ebbca7d GK |
12869 | (set (match_dup 0) |
12870 | (compare:CC (match_dup 4) | |
12871 | (const_int 0)))] | |
12872 | "") | |
1fd4e8c1 RK |
12873 | |
12874 | (define_insn "" | |
097657c3 | 12875 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12876 | (compare:CC |
9ebbca7d GK |
12877 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12878 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12879 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12880 | (const_int 0))) |
097657c3 AM |
12881 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12882 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12883 | "TARGET_POWER" |
9ebbca7d | 12884 | "@ |
097657c3 | 12885 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12886 | #" |
b19003d8 | 12887 | [(set_attr "type" "compare") |
9ebbca7d GK |
12888 | (set_attr "length" "12,16")]) |
12889 | ||
12890 | (define_split | |
097657c3 | 12891 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12892 | (compare:CC |
12893 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12894 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12895 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12896 | (const_int 0))) | |
12897 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12898 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12899 | "TARGET_POWER && reload_completed" |
097657c3 | 12900 | [(set (match_dup 0) |
9ebbca7d | 12901 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12902 | (set (match_dup 4) |
9ebbca7d GK |
12903 | (compare:CC (match_dup 0) |
12904 | (const_int 0)))] | |
12905 | "") | |
1fd4e8c1 RK |
12906 | |
12907 | (define_insn "" | |
cd2b37d9 RK |
12908 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12909 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12910 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12911 | "TARGET_POWER" |
12912 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12913 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12914 | |
1fd4e8c1 | 12915 | (define_insn "" |
cd2b37d9 RK |
12916 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12917 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12918 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12919 | "TARGET_32BIT" |
1fd4e8c1 | 12920 | "@ |
ca7f5001 RK |
12921 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12922 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
943c15ed DE |
12923 | [(set_attr "type" "three") |
12924 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12925 | |
f9562f27 DE |
12926 | (define_insn "" |
12927 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12928 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12929 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
683bdff7 | 12930 | "TARGET_64BIT" |
f9562f27 DE |
12931 | "@ |
12932 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12933 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
943c15ed DE |
12934 | [(set_attr "type" "three") |
12935 | (set_attr "length" "12")]) | |
f9562f27 | 12936 | |
1fd4e8c1 | 12937 | (define_insn "" |
9ebbca7d | 12938 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12939 | (compare:CC |
9ebbca7d GK |
12940 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12941 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12942 | (const_int 0))) |
9ebbca7d | 12943 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12944 | (geu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12945 | "TARGET_32BIT" |
1fd4e8c1 | 12946 | "@ |
ca7f5001 | 12947 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12948 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12949 | # | |
12950 | #" | |
b19003d8 | 12951 | [(set_attr "type" "compare") |
9ebbca7d GK |
12952 | (set_attr "length" "12,12,16,16")]) |
12953 | ||
12954 | (define_split | |
12955 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12956 | (compare:CC | |
12957 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12958 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12959 | (const_int 0))) | |
12960 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12961 | (geu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12962 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12963 | [(set (match_dup 0) |
12964 | (geu:SI (match_dup 1) (match_dup 2))) | |
12965 | (set (match_dup 3) | |
12966 | (compare:CC (match_dup 0) | |
12967 | (const_int 0)))] | |
12968 | "") | |
1fd4e8c1 | 12969 | |
f9562f27 | 12970 | (define_insn "" |
9ebbca7d | 12971 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12972 | (compare:CC |
9ebbca7d GK |
12973 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12974 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12975 | (const_int 0))) |
9ebbca7d | 12976 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12977 | (geu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12978 | "TARGET_64BIT" |
f9562f27 DE |
12979 | "@ |
12980 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12981 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12982 | # | |
12983 | #" | |
f9562f27 | 12984 | [(set_attr "type" "compare") |
9ebbca7d GK |
12985 | (set_attr "length" "12,12,16,16")]) |
12986 | ||
12987 | (define_split | |
12988 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12989 | (compare:CC | |
12990 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12991 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12992 | (const_int 0))) | |
12993 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12994 | (geu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12995 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12996 | [(set (match_dup 0) |
12997 | (geu:DI (match_dup 1) (match_dup 2))) | |
12998 | (set (match_dup 3) | |
12999 | (compare:CC (match_dup 0) | |
13000 | (const_int 0)))] | |
13001 | "") | |
f9562f27 | 13002 | |
1fd4e8c1 | 13003 | (define_insn "" |
80103f96 | 13004 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 13005 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13006 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 13007 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 13008 | "TARGET_32BIT" |
1fd4e8c1 | 13009 | "@ |
80103f96 FS |
13010 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
13011 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
943c15ed DE |
13012 | [(set_attr "type" "two") |
13013 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
13014 | |
13015 | (define_insn "" | |
9ebbca7d | 13016 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13017 | (compare:CC |
9ebbca7d GK |
13018 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13019 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
13020 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13021 | (const_int 0))) |
9ebbca7d | 13022 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13023 | "TARGET_32BIT" |
1fd4e8c1 | 13024 | "@ |
ca7f5001 | 13025 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
13026 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
13027 | # | |
13028 | #" | |
b19003d8 | 13029 | [(set_attr "type" "compare") |
9ebbca7d GK |
13030 | (set_attr "length" "8,8,12,12")]) |
13031 | ||
13032 | (define_split | |
13033 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13034 | (compare:CC | |
13035 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13036 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
13037 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13038 | (const_int 0))) | |
13039 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 13040 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13041 | [(set (match_dup 4) |
13042 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
13043 | (match_dup 3))) | |
13044 | (set (match_dup 0) | |
13045 | (compare:CC (match_dup 4) | |
13046 | (const_int 0)))] | |
13047 | "") | |
1fd4e8c1 RK |
13048 | |
13049 | (define_insn "" | |
097657c3 | 13050 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13051 | (compare:CC |
9ebbca7d GK |
13052 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13053 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
13054 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13055 | (const_int 0))) |
097657c3 AM |
13056 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13057 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13058 | "TARGET_32BIT" |
1fd4e8c1 | 13059 | "@ |
097657c3 AM |
13060 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
13061 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
13062 | # |
13063 | #" | |
b19003d8 | 13064 | [(set_attr "type" "compare") |
9ebbca7d GK |
13065 | (set_attr "length" "8,8,12,12")]) |
13066 | ||
13067 | (define_split | |
097657c3 | 13068 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13069 | (compare:CC |
13070 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13071 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
13072 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13073 | (const_int 0))) | |
13074 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13075 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13076 | "TARGET_32BIT && reload_completed" |
097657c3 | 13077 | [(set (match_dup 0) |
9ebbca7d | 13078 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13079 | (set (match_dup 4) |
9ebbca7d GK |
13080 | (compare:CC (match_dup 0) |
13081 | (const_int 0)))] | |
13082 | "") | |
1fd4e8c1 RK |
13083 | |
13084 | (define_insn "" | |
cd2b37d9 RK |
13085 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
13086 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 13087 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
683bdff7 | 13088 | "TARGET_32BIT" |
1fd4e8c1 | 13089 | "@ |
ca7f5001 | 13090 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 13091 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
943c15ed DE |
13092 | [(set_attr "type" "three") |
13093 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
13094 | |
13095 | (define_insn "" | |
097657c3 | 13096 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 13097 | (and:SI (neg:SI |
cd2b37d9 | 13098 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13099 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 13100 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 13101 | "TARGET_32BIT" |
1fd4e8c1 | 13102 | "@ |
097657c3 AM |
13103 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
13104 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
943c15ed DE |
13105 | [(set_attr "type" "three") |
13106 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
13107 | |
13108 | (define_insn "" | |
9ebbca7d | 13109 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
13110 | (compare:CC |
13111 | (and:SI (neg:SI | |
9ebbca7d GK |
13112 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13113 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
13114 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13115 | (const_int 0))) |
9ebbca7d | 13116 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13117 | "TARGET_32BIT" |
1fd4e8c1 | 13118 | "@ |
ca7f5001 | 13119 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
13120 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
13121 | # | |
13122 | #" | |
b19003d8 | 13123 | [(set_attr "type" "compare") |
9ebbca7d GK |
13124 | (set_attr "length" "12,12,16,16")]) |
13125 | ||
13126 | (define_split | |
13127 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13128 | (compare:CC | |
13129 | (and:SI (neg:SI | |
13130 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13131 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
13132 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13133 | (const_int 0))) | |
13134 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 13135 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 13136 | [(set (match_dup 4) |
097657c3 AM |
13137 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
13138 | (match_dup 3))) | |
9ebbca7d GK |
13139 | (set (match_dup 0) |
13140 | (compare:CC (match_dup 4) | |
13141 | (const_int 0)))] | |
13142 | "") | |
1fd4e8c1 RK |
13143 | |
13144 | (define_insn "" | |
097657c3 | 13145 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
13146 | (compare:CC |
13147 | (and:SI (neg:SI | |
9ebbca7d GK |
13148 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13149 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
13150 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13151 | (const_int 0))) |
097657c3 AM |
13152 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13153 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 13154 | "TARGET_32BIT" |
1fd4e8c1 | 13155 | "@ |
097657c3 AM |
13156 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
13157 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
13158 | # |
13159 | #" | |
b19003d8 | 13160 | [(set_attr "type" "compare") |
9ebbca7d GK |
13161 | (set_attr "length" "12,12,16,16")]) |
13162 | ||
13163 | (define_split | |
097657c3 | 13164 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13165 | (compare:CC |
13166 | (and:SI (neg:SI | |
13167 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13168 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
13169 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13170 | (const_int 0))) | |
13171 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13172 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 13173 | "TARGET_32BIT && reload_completed" |
097657c3 | 13174 | [(set (match_dup 0) |
9ebbca7d | 13175 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 13176 | (set (match_dup 4) |
9ebbca7d GK |
13177 | (compare:CC (match_dup 0) |
13178 | (const_int 0)))] | |
13179 | "") | |
1fd4e8c1 RK |
13180 | |
13181 | (define_insn "" | |
cd2b37d9 RK |
13182 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13183 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13184 | (const_int 0)))] |
683bdff7 | 13185 | "TARGET_32BIT" |
ca7f5001 | 13186 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
943c15ed DE |
13187 | [(set_attr "type" "three") |
13188 | (set_attr "length" "12")]) | |
1fd4e8c1 | 13189 | |
f9562f27 DE |
13190 | (define_insn "" |
13191 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13192 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13193 | (const_int 0)))] | |
683bdff7 | 13194 | "TARGET_64BIT" |
f9562f27 | 13195 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" |
943c15ed DE |
13196 | [(set_attr "type" "three") |
13197 | (set_attr "length" "12")]) | |
f9562f27 | 13198 | |
1fd4e8c1 | 13199 | (define_insn "" |
9ebbca7d | 13200 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13201 | (compare:CC |
9ebbca7d | 13202 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
13203 | (const_int 0)) |
13204 | (const_int 0))) | |
9ebbca7d | 13205 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13206 | (gt:SI (match_dup 1) (const_int 0)))] |
683bdff7 | 13207 | "TARGET_32BIT" |
9ebbca7d GK |
13208 | "@ |
13209 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
13210 | #" | |
29ae5b89 | 13211 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13212 | (set_attr "length" "12,16")]) |
13213 | ||
13214 | (define_split | |
13215 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13216 | (compare:CC | |
13217 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13218 | (const_int 0)) | |
13219 | (const_int 0))) | |
13220 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13221 | (gt:SI (match_dup 1) (const_int 0)))] | |
683bdff7 | 13222 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13223 | [(set (match_dup 0) |
13224 | (gt:SI (match_dup 1) (const_int 0))) | |
13225 | (set (match_dup 2) | |
13226 | (compare:CC (match_dup 0) | |
13227 | (const_int 0)))] | |
13228 | "") | |
1fd4e8c1 | 13229 | |
f9562f27 | 13230 | (define_insn "" |
9ebbca7d | 13231 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 13232 | (compare:CC |
9ebbca7d | 13233 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
13234 | (const_int 0)) |
13235 | (const_int 0))) | |
9ebbca7d | 13236 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13237 | (gt:DI (match_dup 1) (const_int 0)))] |
683bdff7 | 13238 | "TARGET_64BIT" |
9ebbca7d GK |
13239 | "@ |
13240 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
13241 | #" | |
f9562f27 | 13242 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13243 | (set_attr "length" "12,16")]) |
13244 | ||
13245 | (define_split | |
13246 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13247 | (compare:CC | |
13248 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13249 | (const_int 0)) | |
13250 | (const_int 0))) | |
13251 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13252 | (gt:DI (match_dup 1) (const_int 0)))] | |
683bdff7 | 13253 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13254 | [(set (match_dup 0) |
13255 | (gt:DI (match_dup 1) (const_int 0))) | |
13256 | (set (match_dup 2) | |
13257 | (compare:CC (match_dup 0) | |
13258 | (const_int 0)))] | |
13259 | "") | |
f9562f27 | 13260 | |
1fd4e8c1 | 13261 | (define_insn "" |
cd2b37d9 RK |
13262 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13263 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13264 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
13265 | "TARGET_POWER" |
13266 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 13267 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13268 | |
13269 | (define_insn "" | |
9ebbca7d | 13270 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13271 | (compare:CC |
9ebbca7d GK |
13272 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13273 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 13274 | (const_int 0))) |
9ebbca7d | 13275 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13276 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 13277 | "TARGET_POWER" |
9ebbca7d GK |
13278 | "@ |
13279 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
13280 | #" | |
29ae5b89 | 13281 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13282 | (set_attr "length" "12,16")]) |
13283 | ||
13284 | (define_split | |
13285 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13286 | (compare:CC | |
13287 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13288 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13289 | (const_int 0))) | |
13290 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13291 | (gt:SI (match_dup 1) (match_dup 2)))] | |
13292 | "TARGET_POWER && reload_completed" | |
13293 | [(set (match_dup 0) | |
13294 | (gt:SI (match_dup 1) (match_dup 2))) | |
13295 | (set (match_dup 3) | |
13296 | (compare:CC (match_dup 0) | |
13297 | (const_int 0)))] | |
13298 | "") | |
1fd4e8c1 RK |
13299 | |
13300 | (define_insn "" | |
80103f96 | 13301 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13302 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13303 | (const_int 0)) |
80103f96 | 13304 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 13305 | "TARGET_32BIT" |
80103f96 | 13306 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
943c15ed DE |
13307 | [(set_attr "type" "three") |
13308 | (set_attr "length" "12")]) | |
1fd4e8c1 | 13309 | |
f9562f27 | 13310 | (define_insn "" |
097657c3 | 13311 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
13312 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13313 | (const_int 0)) | |
097657c3 | 13314 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 13315 | "TARGET_64BIT" |
097657c3 | 13316 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
943c15ed DE |
13317 | [(set_attr "type" "three") |
13318 | (set_attr "length" "12")]) | |
f9562f27 | 13319 | |
1fd4e8c1 | 13320 | (define_insn "" |
9ebbca7d | 13321 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13322 | (compare:CC |
9ebbca7d | 13323 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13324 | (const_int 0)) |
9ebbca7d | 13325 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 13326 | (const_int 0))) |
9ebbca7d | 13327 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 13328 | "TARGET_32BIT" |
9ebbca7d GK |
13329 | "@ |
13330 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
13331 | #" | |
b19003d8 | 13332 | [(set_attr "type" "compare") |
9ebbca7d GK |
13333 | (set_attr "length" "12,16")]) |
13334 | ||
13335 | (define_split | |
13336 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13337 | (compare:CC | |
13338 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13339 | (const_int 0)) | |
13340 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
13341 | (const_int 0))) | |
13342 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 13343 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13344 | [(set (match_dup 3) |
13345 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
13346 | (match_dup 2))) | |
13347 | (set (match_dup 0) | |
13348 | (compare:CC (match_dup 3) | |
13349 | (const_int 0)))] | |
13350 | "") | |
1fd4e8c1 | 13351 | |
f9562f27 | 13352 | (define_insn "" |
9ebbca7d | 13353 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 13354 | (compare:CC |
9ebbca7d | 13355 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13356 | (const_int 0)) |
9ebbca7d | 13357 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13358 | (const_int 0))) |
9ebbca7d | 13359 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 13360 | "TARGET_64BIT" |
9ebbca7d GK |
13361 | "@ |
13362 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
13363 | #" | |
f9562f27 | 13364 | [(set_attr "type" "compare") |
9ebbca7d GK |
13365 | (set_attr "length" "12,16")]) |
13366 | ||
13367 | (define_split | |
13368 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13369 | (compare:CC | |
13370 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13371 | (const_int 0)) | |
13372 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13373 | (const_int 0))) | |
13374 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 13375 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13376 | [(set (match_dup 3) |
13377 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 13378 | (match_dup 2))) |
9ebbca7d GK |
13379 | (set (match_dup 0) |
13380 | (compare:CC (match_dup 3) | |
13381 | (const_int 0)))] | |
13382 | "") | |
f9562f27 | 13383 | |
1fd4e8c1 | 13384 | (define_insn "" |
097657c3 | 13385 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
13386 | (compare:CC |
13387 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
13388 | (const_int 0)) | |
13389 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
13390 | (const_int 0))) | |
097657c3 AM |
13391 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13392 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13393 | "TARGET_32BIT" |
9ebbca7d | 13394 | "@ |
097657c3 | 13395 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
13396 | #" |
13397 | [(set_attr "type" "compare") | |
13398 | (set_attr "length" "12,16")]) | |
13399 | ||
13400 | (define_split | |
097657c3 | 13401 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 13402 | (compare:CC |
9ebbca7d | 13403 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 13404 | (const_int 0)) |
9ebbca7d | 13405 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 13406 | (const_int 0))) |
9ebbca7d | 13407 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 13408 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13409 | "TARGET_32BIT && reload_completed" |
097657c3 | 13410 | [(set (match_dup 0) |
9ebbca7d | 13411 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13412 | (set (match_dup 3) |
9ebbca7d GK |
13413 | (compare:CC (match_dup 0) |
13414 | (const_int 0)))] | |
13415 | "") | |
1fd4e8c1 | 13416 | |
f9562f27 | 13417 | (define_insn "" |
097657c3 | 13418 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13419 | (compare:CC |
9ebbca7d | 13420 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13421 | (const_int 0)) |
9ebbca7d | 13422 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13423 | (const_int 0))) |
097657c3 AM |
13424 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
13425 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13426 | "TARGET_64BIT" |
9ebbca7d | 13427 | "@ |
097657c3 | 13428 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 13429 | #" |
f9562f27 | 13430 | [(set_attr "type" "compare") |
9ebbca7d GK |
13431 | (set_attr "length" "12,16")]) |
13432 | ||
13433 | (define_split | |
097657c3 | 13434 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13435 | (compare:CC |
13436 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13437 | (const_int 0)) | |
13438 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13439 | (const_int 0))) | |
13440 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13441 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13442 | "TARGET_64BIT && reload_completed" |
097657c3 | 13443 | [(set (match_dup 0) |
9ebbca7d | 13444 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13445 | (set (match_dup 3) |
9ebbca7d GK |
13446 | (compare:CC (match_dup 0) |
13447 | (const_int 0)))] | |
13448 | "") | |
f9562f27 | 13449 | |
1fd4e8c1 | 13450 | (define_insn "" |
097657c3 | 13451 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13452 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13453 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 13454 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 13455 | "TARGET_POWER" |
097657c3 | 13456 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 13457 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13458 | |
13459 | (define_insn "" | |
9ebbca7d | 13460 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13461 | (compare:CC |
9ebbca7d GK |
13462 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13463 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13464 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13465 | (const_int 0))) |
9ebbca7d | 13466 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13467 | "TARGET_POWER" |
9ebbca7d GK |
13468 | "@ |
13469 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
13470 | #" | |
b19003d8 | 13471 | [(set_attr "type" "compare") |
9ebbca7d GK |
13472 | (set_attr "length" "12,16")]) |
13473 | ||
13474 | (define_split | |
13475 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13476 | (compare:CC | |
13477 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13478 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13479 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13480 | (const_int 0))) | |
13481 | (clobber (match_scratch:SI 4 ""))] | |
13482 | "TARGET_POWER && reload_completed" | |
13483 | [(set (match_dup 4) | |
097657c3 | 13484 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
13485 | (set (match_dup 0) |
13486 | (compare:CC (match_dup 4) | |
13487 | (const_int 0)))] | |
13488 | "") | |
1fd4e8c1 RK |
13489 | |
13490 | (define_insn "" | |
097657c3 | 13491 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13492 | (compare:CC |
9ebbca7d GK |
13493 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13494 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13495 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13496 | (const_int 0))) |
097657c3 AM |
13497 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13498 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 13499 | "TARGET_POWER" |
9ebbca7d | 13500 | "@ |
097657c3 | 13501 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 13502 | #" |
b19003d8 | 13503 | [(set_attr "type" "compare") |
9ebbca7d GK |
13504 | (set_attr "length" "12,16")]) |
13505 | ||
13506 | (define_split | |
097657c3 | 13507 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13508 | (compare:CC |
13509 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13510 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13511 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13512 | (const_int 0))) | |
13513 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13514 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13515 | "TARGET_POWER && reload_completed" |
097657c3 | 13516 | [(set (match_dup 0) |
9ebbca7d | 13517 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13518 | (set (match_dup 4) |
9ebbca7d GK |
13519 | (compare:CC (match_dup 0) |
13520 | (const_int 0)))] | |
13521 | "") | |
1fd4e8c1 RK |
13522 | |
13523 | (define_insn "" | |
cd2b37d9 RK |
13524 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13525 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13526 | (const_int 0))))] |
683bdff7 | 13527 | "TARGET_32BIT" |
ca7f5001 | 13528 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
943c15ed DE |
13529 | [(set_attr "type" "three") |
13530 | (set_attr "length" "12")]) | |
1fd4e8c1 | 13531 | |
f9562f27 DE |
13532 | (define_insn "" |
13533 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13534 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13535 | (const_int 0))))] | |
683bdff7 | 13536 | "TARGET_64BIT" |
8377288b | 13537 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
943c15ed DE |
13538 | [(set_attr "type" "three") |
13539 | (set_attr "length" "12")]) | |
f9562f27 | 13540 | |
1fd4e8c1 | 13541 | (define_insn "" |
cd2b37d9 RK |
13542 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13543 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13544 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
13545 | "TARGET_POWER" |
13546 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 13547 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13548 | |
c0600ecd | 13549 | (define_insn_and_split "" |
cd2b37d9 | 13550 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c0600ecd DE |
13551 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
13552 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13553 | "TARGET_32BIT" |
c0600ecd DE |
13554 | "#" |
13555 | "TARGET_32BIT" | |
13556 | [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) | |
13557 | (set (match_dup 0) (neg:SI (match_dup 0)))] | |
13558 | "") | |
1fd4e8c1 | 13559 | |
c0600ecd | 13560 | (define_insn_and_split "" |
f9562f27 | 13561 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
c0600ecd DE |
13562 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13563 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13564 | "TARGET_64BIT" |
c0600ecd DE |
13565 | "#" |
13566 | "TARGET_64BIT" | |
13567 | [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) | |
13568 | (set (match_dup 0) (neg:DI (match_dup 0)))] | |
13569 | "") | |
f9562f27 | 13570 | |
1fd4e8c1 | 13571 | (define_insn "" |
9ebbca7d | 13572 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13573 | (compare:CC |
9ebbca7d GK |
13574 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13575 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13576 | (const_int 0))) |
9ebbca7d | 13577 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13578 | (gtu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13579 | "TARGET_32BIT" |
9ebbca7d GK |
13580 | "@ |
13581 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13582 | #" | |
b19003d8 | 13583 | [(set_attr "type" "compare") |
9ebbca7d GK |
13584 | (set_attr "length" "12,16")]) |
13585 | ||
13586 | (define_split | |
13587 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13588 | (compare:CC | |
13589 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13590 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13591 | (const_int 0))) | |
13592 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13593 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13594 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13595 | [(set (match_dup 0) |
13596 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13597 | (set (match_dup 3) | |
13598 | (compare:CC (match_dup 0) | |
13599 | (const_int 0)))] | |
13600 | "") | |
1fd4e8c1 | 13601 | |
f9562f27 | 13602 | (define_insn "" |
9ebbca7d | 13603 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13604 | (compare:CC |
9ebbca7d GK |
13605 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13606 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13607 | (const_int 0))) |
9ebbca7d | 13608 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13609 | (gtu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13610 | "TARGET_64BIT" |
9ebbca7d GK |
13611 | "@ |
13612 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13613 | #" | |
f9562f27 | 13614 | [(set_attr "type" "compare") |
9ebbca7d GK |
13615 | (set_attr "length" "12,16")]) |
13616 | ||
13617 | (define_split | |
13618 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13619 | (compare:CC | |
13620 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13621 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13622 | (const_int 0))) | |
13623 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13624 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13625 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13626 | [(set (match_dup 0) |
13627 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13628 | (set (match_dup 3) | |
13629 | (compare:CC (match_dup 0) | |
13630 | (const_int 0)))] | |
13631 | "") | |
f9562f27 | 13632 | |
c0600ecd | 13633 | (define_insn_and_split "" |
04fa46cf | 13634 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
c0600ecd DE |
13635 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
13636 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
13637 | (match_operand:SI 3 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13638 | "TARGET_32BIT" |
c0600ecd | 13639 | "#" |
04fa46cf | 13640 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
13641 | [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) |
13642 | (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] | |
13643 | "") | |
1fd4e8c1 | 13644 | |
c0600ecd | 13645 | (define_insn_and_split "" |
04fa46cf | 13646 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
c0600ecd DE |
13647 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13648 | (match_operand:DI 2 "reg_or_short_operand" "rI")) | |
13649 | (match_operand:DI 3 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13650 | "TARGET_64BIT" |
c0600ecd | 13651 | "#" |
04fa46cf | 13652 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
13653 | [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) |
13654 | (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] | |
13655 | "") | |
f9562f27 | 13656 | |
1fd4e8c1 | 13657 | (define_insn "" |
9ebbca7d | 13658 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13659 | (compare:CC |
9ebbca7d GK |
13660 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13661 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13662 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13663 | (const_int 0))) |
9ebbca7d | 13664 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13665 | "TARGET_32BIT" |
00751805 | 13666 | "@ |
19378cf8 | 13667 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
c9dbf840 | 13668 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 |
9ebbca7d GK |
13669 | # |
13670 | #" | |
b19003d8 | 13671 | [(set_attr "type" "compare") |
9ebbca7d GK |
13672 | (set_attr "length" "8,12,12,16")]) |
13673 | ||
13674 | (define_split | |
13675 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13676 | (compare:CC | |
13677 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13678 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13679 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13680 | (const_int 0))) | |
13681 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 13682 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13683 | [(set (match_dup 4) |
13684 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13685 | (match_dup 3))) |
9ebbca7d GK |
13686 | (set (match_dup 0) |
13687 | (compare:CC (match_dup 4) | |
13688 | (const_int 0)))] | |
13689 | "") | |
1fd4e8c1 | 13690 | |
f9562f27 | 13691 | (define_insn "" |
9ebbca7d | 13692 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13693 | (compare:CC |
9ebbca7d GK |
13694 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13695 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13696 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13697 | (const_int 0))) |
9ebbca7d | 13698 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13699 | "TARGET_64BIT" |
f9562f27 DE |
13700 | "@ |
13701 | addic %4,%1,%k2\;addze. %4,%3 | |
c9dbf840 | 13702 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3 |
9ebbca7d GK |
13703 | # |
13704 | #" | |
f9562f27 | 13705 | [(set_attr "type" "compare") |
9ebbca7d GK |
13706 | (set_attr "length" "8,12,12,16")]) |
13707 | ||
13708 | (define_split | |
13709 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13710 | (compare:CC | |
13711 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13712 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13713 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13714 | (const_int 0))) | |
13715 | (clobber (match_scratch:DI 4 ""))] | |
683bdff7 | 13716 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13717 | [(set (match_dup 4) |
13718 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13719 | (match_dup 3))) | |
13720 | (set (match_dup 0) | |
13721 | (compare:CC (match_dup 4) | |
13722 | (const_int 0)))] | |
13723 | "") | |
f9562f27 | 13724 | |
1fd4e8c1 | 13725 | (define_insn "" |
097657c3 | 13726 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13727 | (compare:CC |
9ebbca7d GK |
13728 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13729 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13730 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13731 | (const_int 0))) |
097657c3 AM |
13732 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13733 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13734 | "TARGET_32BIT" |
00751805 | 13735 | "@ |
097657c3 | 13736 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
c9dbf840 | 13737 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 |
9ebbca7d GK |
13738 | # |
13739 | #" | |
b19003d8 | 13740 | [(set_attr "type" "compare") |
9ebbca7d GK |
13741 | (set_attr "length" "8,12,12,16")]) |
13742 | ||
13743 | (define_split | |
097657c3 | 13744 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13745 | (compare:CC |
13746 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13747 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13748 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13749 | (const_int 0))) | |
13750 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13751 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13752 | "TARGET_32BIT && reload_completed" |
097657c3 | 13753 | [(set (match_dup 0) |
9ebbca7d | 13754 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13755 | (set (match_dup 4) |
9ebbca7d GK |
13756 | (compare:CC (match_dup 0) |
13757 | (const_int 0)))] | |
13758 | "") | |
1fd4e8c1 | 13759 | |
f9562f27 | 13760 | (define_insn "" |
097657c3 | 13761 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13762 | (compare:CC |
9ebbca7d GK |
13763 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13764 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13765 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13766 | (const_int 0))) |
097657c3 AM |
13767 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13768 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13769 | "TARGET_64BIT" |
f9562f27 | 13770 | "@ |
097657c3 | 13771 | addic %0,%1,%k2\;addze. %0,%3 |
c9dbf840 | 13772 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3 |
9ebbca7d GK |
13773 | # |
13774 | #" | |
f9562f27 | 13775 | [(set_attr "type" "compare") |
9ebbca7d GK |
13776 | (set_attr "length" "8,12,12,16")]) |
13777 | ||
13778 | (define_split | |
097657c3 | 13779 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13780 | (compare:CC |
13781 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13782 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13783 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13784 | (const_int 0))) | |
13785 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13786 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13787 | "TARGET_64BIT && reload_completed" |
097657c3 | 13788 | [(set (match_dup 0) |
9ebbca7d | 13789 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13790 | (set (match_dup 4) |
9ebbca7d GK |
13791 | (compare:CC (match_dup 0) |
13792 | (const_int 0)))] | |
13793 | "") | |
f9562f27 | 13794 | |
1fd4e8c1 | 13795 | (define_insn "" |
cd2b37d9 RK |
13796 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13797 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13798 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 13799 | "TARGET_32BIT" |
ca7f5001 | 13800 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
943c15ed | 13801 | [(set_attr "type" "two") |
c0600ecd | 13802 | (set_attr "length" "8")]) |
f9562f27 DE |
13803 | |
13804 | (define_insn "" | |
13805 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13806 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13807 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
683bdff7 | 13808 | "TARGET_64BIT" |
f9562f27 | 13809 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" |
943c15ed | 13810 | [(set_attr "type" "two") |
c0600ecd | 13811 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
13812 | \f |
13813 | ;; Define both directions of branch and return. If we need a reload | |
13814 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13815 | ;; register CC value to there. | |
13816 | ||
13817 | (define_insn "" | |
13818 | [(set (pc) | |
13819 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13820 | [(match_operand 2 | |
b54cf83a | 13821 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13822 | (const_int 0)]) |
13823 | (label_ref (match_operand 0 "" "")) | |
13824 | (pc)))] | |
13825 | "" | |
b19003d8 RK |
13826 | "* |
13827 | { | |
12a4e8c5 | 13828 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13829 | }" |
13830 | [(set_attr "type" "branch")]) | |
13831 | ||
1fd4e8c1 RK |
13832 | (define_insn "" |
13833 | [(set (pc) | |
13834 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13835 | [(match_operand 1 | |
b54cf83a | 13836 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13837 | (const_int 0)]) |
13838 | (return) | |
13839 | (pc)))] | |
13840 | "direct_return ()" | |
12a4e8c5 GK |
13841 | "* |
13842 | { | |
13843 | return output_cbranch (operands[0], NULL, 0, insn); | |
13844 | }" | |
b7ff3d82 | 13845 | [(set_attr "type" "branch") |
39a10a29 | 13846 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
13847 | |
13848 | (define_insn "" | |
13849 | [(set (pc) | |
13850 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13851 | [(match_operand 2 | |
b54cf83a | 13852 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13853 | (const_int 0)]) |
13854 | (pc) | |
13855 | (label_ref (match_operand 0 "" ""))))] | |
13856 | "" | |
b19003d8 RK |
13857 | "* |
13858 | { | |
12a4e8c5 | 13859 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13860 | }" |
13861 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13862 | |
13863 | (define_insn "" | |
13864 | [(set (pc) | |
13865 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13866 | [(match_operand 1 | |
b54cf83a | 13867 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13868 | (const_int 0)]) |
13869 | (pc) | |
13870 | (return)))] | |
13871 | "direct_return ()" | |
12a4e8c5 GK |
13872 | "* |
13873 | { | |
13874 | return output_cbranch (operands[0], NULL, 1, insn); | |
13875 | }" | |
b7ff3d82 | 13876 | [(set_attr "type" "branch") |
39a10a29 GK |
13877 | (set_attr "length" "4")]) |
13878 | ||
13879 | ;; Logic on condition register values. | |
13880 | ||
13881 | ; This pattern matches things like | |
13882 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
13883 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
13884 | ; (const_int 1))) | |
13885 | ; which are generated by the branch logic. | |
b54cf83a | 13886 | ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) |
39a10a29 | 13887 | |
423c1189 | 13888 | (define_insn "*cceq_ior_compare" |
b54cf83a | 13889 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13890 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" |
b54cf83a | 13891 | [(match_operator:SI 2 |
39a10a29 GK |
13892 | "branch_positive_comparison_operator" |
13893 | [(match_operand 3 | |
b54cf83a | 13894 | "cc_reg_operand" "y,y") |
39a10a29 | 13895 | (const_int 0)]) |
b54cf83a | 13896 | (match_operator:SI 4 |
39a10a29 GK |
13897 | "branch_positive_comparison_operator" |
13898 | [(match_operand 5 | |
b54cf83a | 13899 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13900 | (const_int 0)])]) |
13901 | (const_int 1)))] | |
24fab1d3 | 13902 | "" |
39a10a29 | 13903 | "cr%q1 %E0,%j2,%j4" |
b54cf83a | 13904 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13905 | |
13906 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
13907 | ; Because ~1 has all but the low bit set. | |
13908 | (define_insn "" | |
b54cf83a | 13909 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13910 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" |
b54cf83a | 13911 | [(not:SI (match_operator:SI 2 |
39a10a29 GK |
13912 | "branch_positive_comparison_operator" |
13913 | [(match_operand 3 | |
b54cf83a | 13914 | "cc_reg_operand" "y,y") |
39a10a29 GK |
13915 | (const_int 0)])) |
13916 | (match_operator:SI 4 | |
13917 | "branch_positive_comparison_operator" | |
13918 | [(match_operand 5 | |
b54cf83a | 13919 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13920 | (const_int 0)])]) |
13921 | (const_int -1)))] | |
13922 | "" | |
13923 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13924 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 | 13925 | |
423c1189 | 13926 | (define_insn "*cceq_rev_compare" |
b54cf83a | 13927 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
6c873122 | 13928 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 13929 | "branch_positive_comparison_operator" |
6c873122 | 13930 | [(match_operand 2 |
b54cf83a | 13931 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13932 | (const_int 0)]) |
13933 | (const_int 0)))] | |
423c1189 | 13934 | "" |
251b3667 | 13935 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
b54cf83a | 13936 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13937 | |
13938 | ;; If we are comparing the result of two comparisons, this can be done | |
13939 | ;; using creqv or crxor. | |
13940 | ||
13941 | (define_insn_and_split "" | |
13942 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13943 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
13944 | [(match_operand 2 "cc_reg_operand" "y") | |
13945 | (const_int 0)]) | |
13946 | (match_operator 3 "branch_comparison_operator" | |
13947 | [(match_operand 4 "cc_reg_operand" "y") | |
13948 | (const_int 0)])))] | |
13949 | "" | |
13950 | "#" | |
13951 | "" | |
13952 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13953 | (match_dup 5)))] | |
13954 | " | |
13955 | { | |
13956 | int positive_1, positive_2; | |
13957 | ||
364849ee DE |
13958 | positive_1 = branch_positive_comparison_operator (operands[1], |
13959 | GET_MODE (operands[1])); | |
13960 | positive_2 = branch_positive_comparison_operator (operands[3], | |
13961 | GET_MODE (operands[3])); | |
39a10a29 GK |
13962 | |
13963 | if (! positive_1) | |
1c563bed | 13964 | operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), |
0f4c242b KH |
13965 | GET_CODE (operands[1])), |
13966 | SImode, | |
13967 | operands[2], const0_rtx); | |
39a10a29 | 13968 | else if (GET_MODE (operands[1]) != SImode) |
0f4c242b KH |
13969 | operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, |
13970 | operands[2], const0_rtx); | |
39a10a29 GK |
13971 | |
13972 | if (! positive_2) | |
1c563bed | 13973 | operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), |
0f4c242b KH |
13974 | GET_CODE (operands[3])), |
13975 | SImode, | |
13976 | operands[4], const0_rtx); | |
39a10a29 | 13977 | else if (GET_MODE (operands[3]) != SImode) |
0f4c242b KH |
13978 | operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
13979 | operands[4], const0_rtx); | |
39a10a29 GK |
13980 | |
13981 | if (positive_1 == positive_2) | |
251b3667 DE |
13982 | { |
13983 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13984 | operands[5] = constm1_rtx; | |
13985 | } | |
13986 | else | |
13987 | { | |
13988 | operands[5] = const1_rtx; | |
13989 | } | |
39a10a29 | 13990 | }") |
1fd4e8c1 RK |
13991 | |
13992 | ;; Unconditional branch and return. | |
13993 | ||
13994 | (define_insn "jump" | |
13995 | [(set (pc) | |
13996 | (label_ref (match_operand 0 "" "")))] | |
13997 | "" | |
b7ff3d82 DE |
13998 | "b %l0" |
13999 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
14000 | |
14001 | (define_insn "return" | |
14002 | [(return)] | |
14003 | "direct_return ()" | |
324e52cc TG |
14004 | "{br|blr}" |
14005 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 14006 | |
0ad91047 DE |
14007 | (define_expand "indirect_jump" |
14008 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 14009 | "" |
0ad91047 DE |
14010 | " |
14011 | { | |
14012 | if (TARGET_32BIT) | |
14013 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
14014 | else | |
14015 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
14016 | DONE; | |
14017 | }") | |
14018 | ||
14019 | (define_insn "indirect_jumpsi" | |
b92b324d | 14020 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 14021 | "TARGET_32BIT" |
b92b324d DE |
14022 | "@ |
14023 | bctr | |
14024 | {br|blr}" | |
324e52cc | 14025 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 14026 | |
0ad91047 | 14027 | (define_insn "indirect_jumpdi" |
b92b324d | 14028 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 14029 | "TARGET_64BIT" |
b92b324d DE |
14030 | "@ |
14031 | bctr | |
14032 | blr" | |
266eb58a DE |
14033 | [(set_attr "type" "jmpreg")]) |
14034 | ||
1fd4e8c1 RK |
14035 | ;; Table jump for switch statements: |
14036 | (define_expand "tablejump" | |
e6ca2c17 DE |
14037 | [(use (match_operand 0 "" "")) |
14038 | (use (label_ref (match_operand 1 "" "")))] | |
14039 | "" | |
14040 | " | |
14041 | { | |
14042 | if (TARGET_32BIT) | |
14043 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
14044 | else | |
14045 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
14046 | DONE; | |
14047 | }") | |
14048 | ||
14049 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
14050 | [(set (match_dup 3) |
14051 | (plus:SI (match_operand:SI 0 "" "") | |
14052 | (match_dup 2))) | |
14053 | (parallel [(set (pc) (match_dup 3)) | |
14054 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 14055 | "TARGET_32BIT" |
1fd4e8c1 RK |
14056 | " |
14057 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 14058 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
14059 | operands[3] = gen_reg_rtx (SImode); |
14060 | }") | |
14061 | ||
e6ca2c17 | 14062 | (define_expand "tablejumpdi" |
6ae08853 | 14063 | [(set (match_dup 4) |
9ebbca7d GK |
14064 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) |
14065 | (set (match_dup 3) | |
14066 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
14067 | (match_dup 2))) |
14068 | (parallel [(set (pc) (match_dup 3)) | |
14069 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 14070 | "TARGET_64BIT" |
e6ca2c17 | 14071 | " |
9ebbca7d | 14072 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 14073 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 14074 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
14075 | }") |
14076 | ||
1fd4e8c1 RK |
14077 | (define_insn "" |
14078 | [(set (pc) | |
c859cda6 | 14079 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 14080 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 14081 | "TARGET_32BIT" |
c859cda6 DJ |
14082 | "@ |
14083 | bctr | |
14084 | {br|blr}" | |
a6845123 | 14085 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 14086 | |
266eb58a DE |
14087 | (define_insn "" |
14088 | [(set (pc) | |
c859cda6 | 14089 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 14090 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 14091 | "TARGET_64BIT" |
c859cda6 DJ |
14092 | "@ |
14093 | bctr | |
14094 | blr" | |
266eb58a DE |
14095 | [(set_attr "type" "jmpreg")]) |
14096 | ||
1fd4e8c1 RK |
14097 | (define_insn "nop" |
14098 | [(const_int 0)] | |
14099 | "" | |
ca7f5001 | 14100 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 14101 | \f |
7e69e155 | 14102 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
14103 | ;; so loop.c knows what to generate. |
14104 | ||
5527bf14 RH |
14105 | (define_expand "doloop_end" |
14106 | [(use (match_operand 0 "" "")) ; loop pseudo | |
14107 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
14108 | (use (match_operand 2 "" "")) ; max iterations | |
14109 | (use (match_operand 3 "" "")) ; loop level | |
14110 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
14111 | "" |
14112 | " | |
14113 | { | |
5527bf14 RH |
14114 | /* Only use this on innermost loops. */ |
14115 | if (INTVAL (operands[3]) > 1) | |
14116 | FAIL; | |
683bdff7 | 14117 | if (TARGET_64BIT) |
5527bf14 RH |
14118 | { |
14119 | if (GET_MODE (operands[0]) != DImode) | |
14120 | FAIL; | |
14121 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
14122 | } | |
0ad91047 | 14123 | else |
5527bf14 RH |
14124 | { |
14125 | if (GET_MODE (operands[0]) != SImode) | |
14126 | FAIL; | |
14127 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
14128 | } | |
0ad91047 DE |
14129 | DONE; |
14130 | }") | |
14131 | ||
14132 | (define_expand "ctrsi" | |
3cb999d8 DE |
14133 | [(parallel [(set (pc) |
14134 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
14135 | (const_int 1)) | |
14136 | (label_ref (match_operand 1 "" "")) | |
14137 | (pc))) | |
b6c9286a MM |
14138 | (set (match_dup 0) |
14139 | (plus:SI (match_dup 0) | |
14140 | (const_int -1))) | |
5f81043f RK |
14141 | (clobber (match_scratch:CC 2 "")) |
14142 | (clobber (match_scratch:SI 3 ""))])] | |
683bdff7 | 14143 | "TARGET_32BIT" |
0ad91047 DE |
14144 | "") |
14145 | ||
14146 | (define_expand "ctrdi" | |
3cb999d8 DE |
14147 | [(parallel [(set (pc) |
14148 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
14149 | (const_int 1)) | |
14150 | (label_ref (match_operand 1 "" "")) | |
14151 | (pc))) | |
0ad91047 DE |
14152 | (set (match_dup 0) |
14153 | (plus:DI (match_dup 0) | |
14154 | (const_int -1))) | |
14155 | (clobber (match_scratch:CC 2 "")) | |
61c07d3c | 14156 | (clobber (match_scratch:DI 3 ""))])] |
683bdff7 | 14157 | "TARGET_64BIT" |
61c07d3c | 14158 | "") |
c225ba7b | 14159 | |
1fd4e8c1 RK |
14160 | ;; We need to be able to do this for any operand, including MEM, or we |
14161 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 14162 | ;; JUMP_INSNs. |
0ad91047 | 14163 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
14164 | ;; label MUST be operand 0. |
14165 | ||
0ad91047 | 14166 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 14167 | [(set (pc) |
43b68ce5 | 14168 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 14169 | (const_int 1)) |
a6845123 | 14170 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14171 | (pc))) |
b150f4f3 | 14172 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14173 | (plus:SI (match_dup 1) |
14174 | (const_int -1))) | |
43b68ce5 DE |
14175 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14176 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14177 | "TARGET_32BIT" |
b19003d8 RK |
14178 | "* |
14179 | { | |
af87a13e | 14180 | if (which_alternative != 0) |
b19003d8 | 14181 | return \"#\"; |
856a6884 | 14182 | else if (get_attr_length (insn) == 4) |
a6845123 | 14183 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 14184 | else |
f607bc57 | 14185 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 14186 | }" |
baf97f86 | 14187 | [(set_attr "type" "branch") |
5a195cb5 | 14188 | (set_attr "length" "*,12,16,16")]) |
7e69e155 | 14189 | |
0ad91047 | 14190 | (define_insn "*ctrsi_internal2" |
5f81043f | 14191 | [(set (pc) |
43b68ce5 | 14192 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
14193 | (const_int 1)) |
14194 | (pc) | |
14195 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14196 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14197 | (plus:SI (match_dup 1) |
14198 | (const_int -1))) | |
43b68ce5 DE |
14199 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14200 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14201 | "TARGET_32BIT" |
0ad91047 DE |
14202 | "* |
14203 | { | |
14204 | if (which_alternative != 0) | |
14205 | return \"#\"; | |
856a6884 | 14206 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14207 | return \"bdz %l0\"; |
14208 | else | |
f607bc57 | 14209 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14210 | }" |
14211 | [(set_attr "type" "branch") | |
5a195cb5 | 14212 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14213 | |
14214 | (define_insn "*ctrdi_internal1" | |
14215 | [(set (pc) | |
43b68ce5 | 14216 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14217 | (const_int 1)) |
14218 | (label_ref (match_operand 0 "" "")) | |
14219 | (pc))) | |
b150f4f3 | 14220 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14221 | (plus:DI (match_dup 1) |
14222 | (const_int -1))) | |
43b68ce5 DE |
14223 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14224 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14225 | "TARGET_64BIT" |
0ad91047 DE |
14226 | "* |
14227 | { | |
14228 | if (which_alternative != 0) | |
14229 | return \"#\"; | |
856a6884 | 14230 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14231 | return \"{bdn|bdnz} %l0\"; |
14232 | else | |
f607bc57 | 14233 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14234 | }" |
14235 | [(set_attr "type" "branch") | |
5a195cb5 | 14236 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14237 | |
14238 | (define_insn "*ctrdi_internal2" | |
14239 | [(set (pc) | |
43b68ce5 | 14240 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14241 | (const_int 1)) |
14242 | (pc) | |
14243 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14244 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14245 | (plus:DI (match_dup 1) |
14246 | (const_int -1))) | |
43b68ce5 DE |
14247 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14248 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14249 | "TARGET_64BIT" |
5f81043f RK |
14250 | "* |
14251 | { | |
14252 | if (which_alternative != 0) | |
14253 | return \"#\"; | |
856a6884 | 14254 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14255 | return \"bdz %l0\"; |
14256 | else | |
f607bc57 | 14257 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
14258 | }" |
14259 | [(set_attr "type" "branch") | |
5a195cb5 | 14260 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14261 | |
0ad91047 DE |
14262 | ;; Similar but use EQ |
14263 | ||
14264 | (define_insn "*ctrsi_internal5" | |
5f81043f | 14265 | [(set (pc) |
43b68ce5 | 14266 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 14267 | (const_int 1)) |
a6845123 | 14268 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14269 | (pc))) |
b150f4f3 | 14270 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14271 | (plus:SI (match_dup 1) |
14272 | (const_int -1))) | |
43b68ce5 DE |
14273 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14274 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14275 | "TARGET_32BIT" |
b19003d8 RK |
14276 | "* |
14277 | { | |
af87a13e | 14278 | if (which_alternative != 0) |
b19003d8 | 14279 | return \"#\"; |
856a6884 | 14280 | else if (get_attr_length (insn) == 4) |
a6845123 | 14281 | return \"bdz %l0\"; |
b19003d8 | 14282 | else |
f607bc57 | 14283 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 14284 | }" |
baf97f86 | 14285 | [(set_attr "type" "branch") |
5a195cb5 | 14286 | (set_attr "length" "*,12,16,16")]) |
1fd4e8c1 | 14287 | |
0ad91047 | 14288 | (define_insn "*ctrsi_internal6" |
5f81043f | 14289 | [(set (pc) |
43b68ce5 | 14290 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
14291 | (const_int 1)) |
14292 | (pc) | |
14293 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14294 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14295 | (plus:SI (match_dup 1) |
14296 | (const_int -1))) | |
43b68ce5 DE |
14297 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14298 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14299 | "TARGET_32BIT" |
0ad91047 DE |
14300 | "* |
14301 | { | |
14302 | if (which_alternative != 0) | |
14303 | return \"#\"; | |
856a6884 | 14304 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14305 | return \"{bdn|bdnz} %l0\"; |
14306 | else | |
f607bc57 | 14307 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14308 | }" |
14309 | [(set_attr "type" "branch") | |
5a195cb5 | 14310 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14311 | |
14312 | (define_insn "*ctrdi_internal5" | |
14313 | [(set (pc) | |
43b68ce5 | 14314 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14315 | (const_int 1)) |
14316 | (label_ref (match_operand 0 "" "")) | |
14317 | (pc))) | |
b150f4f3 | 14318 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14319 | (plus:DI (match_dup 1) |
14320 | (const_int -1))) | |
43b68ce5 DE |
14321 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14322 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14323 | "TARGET_64BIT" |
0ad91047 DE |
14324 | "* |
14325 | { | |
14326 | if (which_alternative != 0) | |
14327 | return \"#\"; | |
856a6884 | 14328 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14329 | return \"bdz %l0\"; |
14330 | else | |
f607bc57 | 14331 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14332 | }" |
14333 | [(set_attr "type" "branch") | |
5a195cb5 | 14334 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14335 | |
14336 | (define_insn "*ctrdi_internal6" | |
14337 | [(set (pc) | |
43b68ce5 | 14338 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14339 | (const_int 1)) |
14340 | (pc) | |
14341 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14342 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14343 | (plus:DI (match_dup 1) |
14344 | (const_int -1))) | |
43b68ce5 DE |
14345 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14346 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14347 | "TARGET_64BIT" |
5f81043f RK |
14348 | "* |
14349 | { | |
14350 | if (which_alternative != 0) | |
14351 | return \"#\"; | |
856a6884 | 14352 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14353 | return \"{bdn|bdnz} %l0\"; |
14354 | else | |
f607bc57 | 14355 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
14356 | }" |
14357 | [(set_attr "type" "branch") | |
5a195cb5 | 14358 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14359 | |
0ad91047 DE |
14360 | ;; Now the splitters if we could not allocate the CTR register |
14361 | ||
1fd4e8c1 RK |
14362 | (define_split |
14363 | [(set (pc) | |
14364 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14365 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14366 | (const_int 1)]) |
14367 | (match_operand 5 "" "") | |
14368 | (match_operand 6 "" ""))) | |
cd2b37d9 | 14369 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
14370 | (plus:SI (match_dup 1) |
14371 | (const_int -1))) | |
1fd4e8c1 RK |
14372 | (clobber (match_scratch:CC 3 "")) |
14373 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14374 | "TARGET_32BIT && reload_completed" |
1fd4e8c1 | 14375 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14376 | (compare:CC (plus:SI (match_dup 1) |
14377 | (const_int -1)) | |
1fd4e8c1 | 14378 | (const_int 0))) |
5f81043f RK |
14379 | (set (match_dup 0) |
14380 | (plus:SI (match_dup 1) | |
14381 | (const_int -1)))]) | |
14382 | (set (pc) (if_then_else (match_dup 7) | |
14383 | (match_dup 5) | |
14384 | (match_dup 6)))] | |
1fd4e8c1 | 14385 | " |
0f4c242b KH |
14386 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14387 | operands[3], const0_rtx); }") | |
1fd4e8c1 RK |
14388 | |
14389 | (define_split | |
14390 | [(set (pc) | |
14391 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14392 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14393 | (const_int 1)]) |
14394 | (match_operand 5 "" "") | |
14395 | (match_operand 6 "" ""))) | |
9ebbca7d | 14396 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
14397 | (plus:SI (match_dup 1) (const_int -1))) |
14398 | (clobber (match_scratch:CC 3 "")) | |
14399 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14400 | "TARGET_32BIT && reload_completed |
0ad91047 | 14401 | && ! gpc_reg_operand (operands[0], SImode)" |
1fd4e8c1 | 14402 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14403 | (compare:CC (plus:SI (match_dup 1) |
14404 | (const_int -1)) | |
1fd4e8c1 | 14405 | (const_int 0))) |
5f81043f RK |
14406 | (set (match_dup 4) |
14407 | (plus:SI (match_dup 1) | |
14408 | (const_int -1)))]) | |
14409 | (set (match_dup 0) | |
14410 | (match_dup 4)) | |
14411 | (set (pc) (if_then_else (match_dup 7) | |
14412 | (match_dup 5) | |
14413 | (match_dup 6)))] | |
1fd4e8c1 | 14414 | " |
0f4c242b KH |
14415 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14416 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14417 | (define_split |
14418 | [(set (pc) | |
14419 | (if_then_else (match_operator 2 "comparison_operator" | |
14420 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14421 | (const_int 1)]) | |
61c07d3c DE |
14422 | (match_operand 5 "" "") |
14423 | (match_operand 6 "" ""))) | |
0ad91047 DE |
14424 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
14425 | (plus:DI (match_dup 1) | |
14426 | (const_int -1))) | |
14427 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14428 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14429 | "TARGET_64BIT && reload_completed" |
0ad91047 DE |
14430 | [(parallel [(set (match_dup 3) |
14431 | (compare:CC (plus:DI (match_dup 1) | |
14432 | (const_int -1)) | |
14433 | (const_int 0))) | |
14434 | (set (match_dup 0) | |
14435 | (plus:DI (match_dup 1) | |
14436 | (const_int -1)))]) | |
61c07d3c DE |
14437 | (set (pc) (if_then_else (match_dup 7) |
14438 | (match_dup 5) | |
14439 | (match_dup 6)))] | |
0ad91047 | 14440 | " |
0f4c242b KH |
14441 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14442 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14443 | |
14444 | (define_split | |
14445 | [(set (pc) | |
14446 | (if_then_else (match_operator 2 "comparison_operator" | |
14447 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14448 | (const_int 1)]) | |
61c07d3c DE |
14449 | (match_operand 5 "" "") |
14450 | (match_operand 6 "" ""))) | |
9ebbca7d | 14451 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
14452 | (plus:DI (match_dup 1) (const_int -1))) |
14453 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14454 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14455 | "TARGET_64BIT && reload_completed |
0ad91047 DE |
14456 | && ! gpc_reg_operand (operands[0], DImode)" |
14457 | [(parallel [(set (match_dup 3) | |
14458 | (compare:CC (plus:DI (match_dup 1) | |
14459 | (const_int -1)) | |
14460 | (const_int 0))) | |
14461 | (set (match_dup 4) | |
14462 | (plus:DI (match_dup 1) | |
14463 | (const_int -1)))]) | |
14464 | (set (match_dup 0) | |
14465 | (match_dup 4)) | |
61c07d3c DE |
14466 | (set (pc) (if_then_else (match_dup 7) |
14467 | (match_dup 5) | |
14468 | (match_dup 6)))] | |
0ad91047 | 14469 | " |
0f4c242b KH |
14470 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14471 | operands[3], const0_rtx); }") | |
e0cd0770 JC |
14472 | \f |
14473 | (define_insn "trap" | |
14474 | [(trap_if (const_int 1) (const_int 0))] | |
14475 | "" | |
14476 | "{t 31,0,0|trap}") | |
14477 | ||
14478 | (define_expand "conditional_trap" | |
14479 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14480 | [(match_dup 2) (match_dup 3)]) | |
14481 | (match_operand 1 "const_int_operand" ""))] | |
14482 | "" | |
14483 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14484 | operands[2] = rs6000_compare_op0; | |
14485 | operands[3] = rs6000_compare_op1;") | |
14486 | ||
14487 | (define_insn "" | |
14488 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14489 | [(match_operand:SI 1 "register_operand" "r") | |
14490 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14491 | (const_int 0))] | |
14492 | "" | |
a157febd GK |
14493 | "{t|tw}%V0%I2 %1,%2") |
14494 | ||
14495 | (define_insn "" | |
14496 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14497 | [(match_operand:DI 1 "register_operand" "r") | |
14498 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14499 | (const_int 0))] | |
14500 | "TARGET_POWERPC64" | |
14501 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14502 | \f |
14503 | ;; Insns related to generating the function prologue and epilogue. | |
14504 | ||
14505 | (define_expand "prologue" | |
14506 | [(use (const_int 0))] | |
14507 | "TARGET_SCHED_PROLOG" | |
14508 | " | |
14509 | { | |
14510 | rs6000_emit_prologue (); | |
14511 | DONE; | |
14512 | }") | |
14513 | ||
2c4a9cff DE |
14514 | (define_insn "*movesi_from_cr_one" |
14515 | [(match_parallel 0 "mfcr_operation" | |
14516 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14517 | (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") | |
14518 | (match_operand 3 "immediate_operand" "n")] | |
14519 | UNSPEC_MOVESI_FROM_CR))])] | |
14520 | "TARGET_MFCRF" | |
14521 | "* | |
14522 | { | |
14523 | int mask = 0; | |
14524 | int i; | |
14525 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14526 | { | |
14527 | mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14528 | operands[4] = GEN_INT (mask); | |
14529 | output_asm_insn (\"mfcr %1,%4\", operands); | |
14530 | } | |
14531 | return \"\"; | |
14532 | }" | |
14533 | [(set_attr "type" "mfcrf")]) | |
14534 | ||
9ebbca7d GK |
14535 | (define_insn "movesi_from_cr" |
14536 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 14537 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) |
615158e2 JJ |
14538 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] |
14539 | UNSPEC_MOVESI_FROM_CR))] | |
9ebbca7d | 14540 | "" |
309323c2 | 14541 | "mfcr %0" |
b54cf83a | 14542 | [(set_attr "type" "mfcr")]) |
9ebbca7d GK |
14543 | |
14544 | (define_insn "*stmw" | |
e033a023 DE |
14545 | [(match_parallel 0 "stmw_operation" |
14546 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14547 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14548 | "TARGET_MULTIPLE" | |
14549 | "{stm|stmw} %2,%1") | |
6ae08853 | 14550 | |
9ebbca7d | 14551 | (define_insn "*save_fpregs_si" |
85d346f1 | 14552 | [(match_parallel 0 "any_parallel_operand" |
e033a023 DE |
14553 | [(clobber (match_operand:SI 1 "register_operand" "=l")) |
14554 | (use (match_operand:SI 2 "call_operand" "s")) | |
14555 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14556 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14557 | "TARGET_32BIT" | |
14558 | "bl %z2" | |
14559 | [(set_attr "type" "branch") | |
14560 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14561 | |
14562 | (define_insn "*save_fpregs_di" | |
85d346f1 | 14563 | [(match_parallel 0 "any_parallel_operand" |
e033a023 DE |
14564 | [(clobber (match_operand:DI 1 "register_operand" "=l")) |
14565 | (use (match_operand:DI 2 "call_operand" "s")) | |
14566 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14567 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14568 | "TARGET_64BIT" | |
14569 | "bl %z2" | |
14570 | [(set_attr "type" "branch") | |
14571 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14572 | |
14573 | ; These are to explain that changes to the stack pointer should | |
14574 | ; not be moved over stores to stack memory. | |
14575 | (define_insn "stack_tie" | |
14576 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
615158e2 | 14577 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] |
9ebbca7d GK |
14578 | "" |
14579 | "" | |
14580 | [(set_attr "length" "0")]) | |
14581 | ||
14582 | ||
14583 | (define_expand "epilogue" | |
14584 | [(use (const_int 0))] | |
14585 | "TARGET_SCHED_PROLOG" | |
14586 | " | |
14587 | { | |
14588 | rs6000_emit_epilogue (FALSE); | |
14589 | DONE; | |
14590 | }") | |
14591 | ||
14592 | ; On some processors, doing the mtcrf one CC register at a time is | |
14593 | ; faster (like on the 604e). On others, doing them all at once is | |
14594 | ; faster; for instance, on the 601 and 750. | |
14595 | ||
14596 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
14597 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14598 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 | 14599 | (match_dup 2)] UNSPEC_MOVESI_TO_CR))] |
35aba846 DE |
14600 | "" |
14601 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
14602 | |
14603 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
14604 | [(match_parallel 0 "mtcrf_operation" |
14605 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
14606 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
14607 | (match_operand 3 "immediate_operand" "n")] | |
615158e2 | 14608 | UNSPEC_MOVESI_TO_CR))])] |
9ebbca7d | 14609 | "" |
e35b9579 GK |
14610 | "* |
14611 | { | |
14612 | int mask = 0; | |
14613 | int i; | |
14614 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14615 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14616 | operands[4] = GEN_INT (mask); | |
14617 | return \"mtcrf %4,%2\"; | |
309323c2 | 14618 | }" |
b54cf83a | 14619 | [(set_attr "type" "mtcr")]) |
9ebbca7d | 14620 | |
b54cf83a | 14621 | (define_insn "*mtcrfsi" |
309323c2 DE |
14622 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14623 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 JJ |
14624 | (match_operand 2 "immediate_operand" "n")] |
14625 | UNSPEC_MOVESI_TO_CR))] | |
6ae08853 | 14626 | "GET_CODE (operands[0]) == REG |
309323c2 DE |
14627 | && CR_REGNO_P (REGNO (operands[0])) |
14628 | && GET_CODE (operands[2]) == CONST_INT | |
14629 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14630 | "mtcrf %R0,%1" | |
b54cf83a | 14631 | [(set_attr "type" "mtcr")]) |
9ebbca7d GK |
14632 | |
14633 | ; The load-multiple instructions have similar properties. | |
14634 | ; Note that "load_multiple" is a name known to the machine-independent | |
14635 | ; code that actually corresponds to the powerpc load-string. | |
14636 | ||
14637 | (define_insn "*lmw" | |
35aba846 DE |
14638 | [(match_parallel 0 "lmw_operation" |
14639 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14640 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14641 | "TARGET_MULTIPLE" | |
14642 | "{lm|lmw} %1,%2") | |
6ae08853 | 14643 | |
9ebbca7d | 14644 | (define_insn "*return_internal_si" |
e35b9579 GK |
14645 | [(return) |
14646 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 14647 | "TARGET_32BIT" |
cccf3bdc | 14648 | "b%T0" |
9ebbca7d GK |
14649 | [(set_attr "type" "jmpreg")]) |
14650 | ||
14651 | (define_insn "*return_internal_di" | |
e35b9579 GK |
14652 | [(return) |
14653 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 14654 | "TARGET_64BIT" |
cccf3bdc | 14655 | "b%T0" |
9ebbca7d GK |
14656 | [(set_attr "type" "jmpreg")]) |
14657 | ||
14658 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
85d346f1 | 14659 | ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible... |
9ebbca7d GK |
14660 | |
14661 | (define_insn "*return_and_restore_fpregs_si" | |
85d346f1 | 14662 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 GK |
14663 | [(return) |
14664 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
14665 | (use (match_operand:SI 2 "call_operand" "s")) |
14666 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14667 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14668 | "TARGET_32BIT" | |
14669 | "b %z2") | |
14670 | ||
14671 | (define_insn "*return_and_restore_fpregs_di" | |
85d346f1 | 14672 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 GK |
14673 | [(return) |
14674 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
14675 | (use (match_operand:DI 2 "call_operand" "s")) |
14676 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14677 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14678 | "TARGET_64BIT" | |
14679 | "b %z2") | |
14680 | ||
83720594 RH |
14681 | ; This is used in compiling the unwind routines. |
14682 | (define_expand "eh_return" | |
34dc173c | 14683 | [(use (match_operand 0 "general_operand" ""))] |
9ebbca7d GK |
14684 | "" |
14685 | " | |
14686 | { | |
83720594 | 14687 | if (TARGET_32BIT) |
34dc173c | 14688 | emit_insn (gen_eh_set_lr_si (operands[0])); |
9ebbca7d | 14689 | else |
34dc173c | 14690 | emit_insn (gen_eh_set_lr_di (operands[0])); |
9ebbca7d GK |
14691 | DONE; |
14692 | }") | |
14693 | ||
83720594 RH |
14694 | ; We can't expand this before we know where the link register is stored. |
14695 | (define_insn "eh_set_lr_si" | |
615158e2 JJ |
14696 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] |
14697 | UNSPECV_EH_RR) | |
466eb3e0 | 14698 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
14699 | "TARGET_32BIT" |
14700 | "#") | |
14701 | ||
14702 | (define_insn "eh_set_lr_di" | |
615158e2 JJ |
14703 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
14704 | UNSPECV_EH_RR) | |
466eb3e0 | 14705 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
14706 | "TARGET_64BIT" |
14707 | "#") | |
9ebbca7d GK |
14708 | |
14709 | (define_split | |
615158e2 | 14710 | [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) |
83720594 RH |
14711 | (clobber (match_scratch 1 ""))] |
14712 | "reload_completed" | |
14713 | [(const_int 0)] | |
9ebbca7d GK |
14714 | " |
14715 | { | |
d1d0c603 | 14716 | rs6000_emit_eh_reg_restore (operands[0], operands[1]); |
83720594 RH |
14717 | DONE; |
14718 | }") | |
0ac081f6 | 14719 | |
01a2ccd0 DE |
14720 | (define_insn "prefetch" |
14721 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
14722 | (match_operand:SI 1 "const_int_operand" "n") |
14723 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 14724 | "TARGET_POWERPC" |
6041bf2f DE |
14725 | "* |
14726 | { | |
01a2ccd0 DE |
14727 | if (GET_CODE (operands[0]) == REG) |
14728 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
14729 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
14730 | }" |
14731 | [(set_attr "type" "load")]) | |
a3170dc6 | 14732 | |
10ed84db | 14733 | (include "altivec.md") |
a3170dc6 | 14734 | (include "spe.md") |