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996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee
GK		 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
996a5f59 4;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 5
5de601cf 6;; This file is part of GCC.
1fd4e8c1 7
5de601cf
NC		 8;; GCC is free software; you can redistribute it and/or modify it
9;; under the terms of the GNU General Public License as published
10;; by the Free Software Foundation; either version 2, or (at your
11;; option) any later version.
1fd4e8c1 12
5de601cf
NC		 13;; GCC is distributed in the hope that it will be useful, but WITHOUT
14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16;; License for more details.
1fd4e8c1
RK		 17
18;; You should have received a copy of the GNU General Public License
5de601cf
NC		 19;; along with GCC; see the file COPYING. If not, write to the
20;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21;; MA 02111-1307, USA.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 24
615158e2
JJ		 25;;
26;; UNSPEC usage
27;;
28
29(define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 ])
53
54;;
55;; UNSPEC_VOLATILE usage
56;;
57
58(define_constants
59 [(UNSPECV_BLOCK 0)
60 (UNSPECV_EH_RR 9) ; eh_reg_restore
61 ])
1fd4e8c1
RK		 62\f
63;; Define an insn type attribute. This is used in function unit delay
64;; computations.
2c4a9cff 65(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
1fd4e8c1
RK		 66 (const_string "integer"))
67
b19003d8 68;; Length (in bytes).
6cbadf36
GK		 69; '(pc)' in the following doesn't include the instruction itself; it is
70; calculated as if the instruction had zero size.
b19003d8
RK		 71(define_attr "length" ""
72 (if_then_else (eq_attr "type" "branch")
6cbadf36 73 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 74 (const_int -32768))
6cbadf36
GK		 75 (lt (minus (match_dup 0) (pc))
76 (const_int 32764)))
39a10a29
GK		 77 (const_int 4)
78 (const_int 8))
b19003d8
RK		 79 (const_int 4)))
80
cfb557c4
RK		 81;; Processor type -- this attribute must exactly match the processor_type
82;; enumeration in rs6000.h.
83
b54cf83a 84(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4"
cfb557c4
RK		 85 (const (symbol_ref "rs6000_cpu_attr")))
86
b54cf83a
DE		 87(automata_option "ndfa")
88
89(include "rios1.md")
90(include "rios2.md")
91(include "rs64.md")
92(include "mpc.md")
93(include "40x.md")
02ca7595 94(include "440.md")
b54cf83a
DE		 95(include "603.md")
96(include "6xx.md")
97(include "7xx.md")
98(include "7450.md")
5e8006fa 99(include "8540.md")
b54cf83a 100(include "power4.md")
309323c2 101
1fd4e8c1
RK		 102\f
103;; Start with fixed-point load and store insns. Here we put only the more
104;; complex forms. Basic data transfer is done later.
105
51b8fc2c
RK		 106(define_expand "zero_extendqidi2"
107 [(set (match_operand:DI 0 "gpc_reg_operand" "")
108 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
109 "TARGET_POWERPC64"
110 "")
111
112(define_insn ""
113 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
114 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
115 "TARGET_POWERPC64"
116 "@
117 lbz%U1%X1 %0,%1
4371f8af 118 rldicl %0,%1,0,56"
51b8fc2c
RK		 119 [(set_attr "type" "load,*")])
120
121(define_insn ""
9ebbca7d
GK		 122 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
123 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 124 (const_int 0)))
9ebbca7d 125 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 126 "TARGET_64BIT"
9ebbca7d
GK		 127 "@
128 rldicl. %2,%1,0,56
129 #"
130 [(set_attr "type" "compare")
131 (set_attr "length" "4,8")])
132
133(define_split
134 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
135 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
136 (const_int 0)))
137 (clobber (match_scratch:DI 2 ""))]
138 "TARGET_POWERPC64 && reload_completed"
139 [(set (match_dup 2)
140 (zero_extend:DI (match_dup 1)))
141 (set (match_dup 0)
142 (compare:CC (match_dup 2)
143 (const_int 0)))]
144 "")
51b8fc2c
RK		 145
146(define_insn ""
9ebbca7d
GK		 147 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
148 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 149 (const_int 0)))
9ebbca7d 150 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 151 (zero_extend:DI (match_dup 1)))]
683bdff7 152 "TARGET_64BIT"
9ebbca7d
GK		 153 "@
154 rldicl. %0,%1,0,56
155 #"
156 [(set_attr "type" "compare")
157 (set_attr "length" "4,8")])
158
159(define_split
160 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
161 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
162 (const_int 0)))
163 (set (match_operand:DI 0 "gpc_reg_operand" "")
164 (zero_extend:DI (match_dup 1)))]
165 "TARGET_POWERPC64 && reload_completed"
166 [(set (match_dup 0)
167 (zero_extend:DI (match_dup 1)))
168 (set (match_dup 2)
169 (compare:CC (match_dup 0)
170 (const_int 0)))]
171 "")
51b8fc2c 172
2bee0449
RK		 173(define_insn "extendqidi2"
174 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
175 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 176 "TARGET_POWERPC64"
2bee0449 177 "extsb %0,%1")
51b8fc2c
RK		 178
179(define_insn ""
9ebbca7d
GK		 180 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
181 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 182 (const_int 0)))
9ebbca7d 183 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 184 "TARGET_64BIT"
9ebbca7d
GK		 185 "@
186 extsb. %2,%1
187 #"
188 [(set_attr "type" "compare")
189 (set_attr "length" "4,8")])
190
191(define_split
192 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
193 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
194 (const_int 0)))
195 (clobber (match_scratch:DI 2 ""))]
196 "TARGET_POWERPC64 && reload_completed"
197 [(set (match_dup 2)
198 (sign_extend:DI (match_dup 1)))
199 (set (match_dup 0)
200 (compare:CC (match_dup 2)
201 (const_int 0)))]
202 "")
51b8fc2c
RK		 203
204(define_insn ""
9ebbca7d
GK		 205 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
206 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 207 (const_int 0)))
9ebbca7d 208 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 209 (sign_extend:DI (match_dup 1)))]
683bdff7 210 "TARGET_64BIT"
9ebbca7d
GK		 211 "@
212 extsb. %0,%1
213 #"
214 [(set_attr "type" "compare")
215 (set_attr "length" "4,8")])
216
217(define_split
218 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
219 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
220 (const_int 0)))
221 (set (match_operand:DI 0 "gpc_reg_operand" "")
222 (sign_extend:DI (match_dup 1)))]
223 "TARGET_POWERPC64 && reload_completed"
224 [(set (match_dup 0)
225 (sign_extend:DI (match_dup 1)))
226 (set (match_dup 2)
227 (compare:CC (match_dup 0)
228 (const_int 0)))]
229 "")
51b8fc2c
RK		 230
231(define_expand "zero_extendhidi2"
232 [(set (match_operand:DI 0 "gpc_reg_operand" "")
233 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
234 "TARGET_POWERPC64"
235 "")
236
237(define_insn ""
238 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
239 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
240 "TARGET_POWERPC64"
241 "@
242 lhz%U1%X1 %0,%1
4371f8af 243 rldicl %0,%1,0,48"
51b8fc2c
RK		 244 [(set_attr "type" "load,*")])
245
246(define_insn ""
9ebbca7d
GK		 247 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
248 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 249 (const_int 0)))
9ebbca7d 250 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 251 "TARGET_64BIT"
9ebbca7d
GK		 252 "@
253 rldicl. %2,%1,0,48
254 #"
255 [(set_attr "type" "compare")
256 (set_attr "length" "4,8")])
257
258(define_split
259 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
260 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
261 (const_int 0)))
262 (clobber (match_scratch:DI 2 ""))]
263 "TARGET_POWERPC64 && reload_completed"
264 [(set (match_dup 2)
265 (zero_extend:DI (match_dup 1)))
266 (set (match_dup 0)
267 (compare:CC (match_dup 2)
268 (const_int 0)))]
269 "")
51b8fc2c
RK		 270
271(define_insn ""
9ebbca7d
GK		 272 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
273 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 274 (const_int 0)))
9ebbca7d 275 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 276 (zero_extend:DI (match_dup 1)))]
683bdff7 277 "TARGET_64BIT"
9ebbca7d
GK		 278 "@
279 rldicl. %0,%1,0,48
280 #"
281 [(set_attr "type" "compare")
282 (set_attr "length" "4,8")])
283
284(define_split
285 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
286 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
287 (const_int 0)))
288 (set (match_operand:DI 0 "gpc_reg_operand" "")
289 (zero_extend:DI (match_dup 1)))]
290 "TARGET_POWERPC64 && reload_completed"
291 [(set (match_dup 0)
292 (zero_extend:DI (match_dup 1)))
293 (set (match_dup 2)
294 (compare:CC (match_dup 0)
295 (const_int 0)))]
296 "")
51b8fc2c
RK		 297
298(define_expand "extendhidi2"
299 [(set (match_operand:DI 0 "gpc_reg_operand" "")
300 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
301 "TARGET_POWERPC64"
302 "")
303
304(define_insn ""
305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
306 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
307 "TARGET_POWERPC64"
308 "@
309 lha%U1%X1 %0,%1
310 extsh %0,%1"
b54cf83a 311 [(set_attr "type" "load_ext,*")])
51b8fc2c
RK		 312
313(define_insn ""
9ebbca7d
GK		 314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
315 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 316 (const_int 0)))
9ebbca7d 317 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 318 "TARGET_64BIT"
9ebbca7d
GK		 319 "@
320 extsh. %2,%1
321 #"
322 [(set_attr "type" "compare")
323 (set_attr "length" "4,8")])
324
325(define_split
326 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
327 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
328 (const_int 0)))
329 (clobber (match_scratch:DI 2 ""))]
330 "TARGET_POWERPC64 && reload_completed"
331 [(set (match_dup 2)
332 (sign_extend:DI (match_dup 1)))
333 (set (match_dup 0)
334 (compare:CC (match_dup 2)
335 (const_int 0)))]
336 "")
51b8fc2c
RK		 337
338(define_insn ""
9ebbca7d
GK		 339 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
340 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 341 (const_int 0)))
9ebbca7d 342 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 343 (sign_extend:DI (match_dup 1)))]
683bdff7 344 "TARGET_64BIT"
9ebbca7d
GK		 345 "@
346 extsh. %0,%1
347 #"
348 [(set_attr "type" "compare")
349 (set_attr "length" "4,8")])
350
351(define_split
352 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
353 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
354 (const_int 0)))
355 (set (match_operand:DI 0 "gpc_reg_operand" "")
356 (sign_extend:DI (match_dup 1)))]
357 "TARGET_POWERPC64 && reload_completed"
358 [(set (match_dup 0)
359 (sign_extend:DI (match_dup 1)))
360 (set (match_dup 2)
361 (compare:CC (match_dup 0)
362 (const_int 0)))]
363 "")
51b8fc2c
RK		 364
365(define_expand "zero_extendsidi2"
366 [(set (match_operand:DI 0 "gpc_reg_operand" "")
367 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
368 "TARGET_POWERPC64"
369 "")
370
371(define_insn ""
372 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
373 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
374 "TARGET_POWERPC64"
375 "@
376 lwz%U1%X1 %0,%1
377 rldicl %0,%1,0,32"
378 [(set_attr "type" "load,*")])
379
380(define_insn ""
9ebbca7d
GK		 381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
382 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 383 (const_int 0)))
9ebbca7d 384 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 385 "TARGET_64BIT"
9ebbca7d
GK		 386 "@
387 rldicl. %2,%1,0,32
388 #"
389 [(set_attr "type" "compare")
390 (set_attr "length" "4,8")])
391
392(define_split
393 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
394 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
395 (const_int 0)))
396 (clobber (match_scratch:DI 2 ""))]
397 "TARGET_POWERPC64 && reload_completed"
398 [(set (match_dup 2)
399 (zero_extend:DI (match_dup 1)))
400 (set (match_dup 0)
401 (compare:CC (match_dup 2)
402 (const_int 0)))]
403 "")
51b8fc2c
RK		 404
405(define_insn ""
9ebbca7d
GK		 406 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
407 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 408 (const_int 0)))
9ebbca7d 409 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 410 (zero_extend:DI (match_dup 1)))]
683bdff7 411 "TARGET_64BIT"
9ebbca7d
GK		 412 "@
413 rldicl. %0,%1,0,32
414 #"
415 [(set_attr "type" "compare")
416 (set_attr "length" "4,8")])
417
418(define_split
419 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
420 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
421 (const_int 0)))
422 (set (match_operand:DI 0 "gpc_reg_operand" "")
423 (zero_extend:DI (match_dup 1)))]
424 "TARGET_POWERPC64 && reload_completed"
425 [(set (match_dup 0)
426 (zero_extend:DI (match_dup 1)))
427 (set (match_dup 2)
428 (compare:CC (match_dup 0)
429 (const_int 0)))]
430 "")
51b8fc2c
RK		 431
432(define_expand "extendsidi2"
433 [(set (match_operand:DI 0 "gpc_reg_operand" "")
434 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
435 "TARGET_POWERPC64"
436 "")
437
438(define_insn ""
439 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 440 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
51b8fc2c
RK		 441 "TARGET_POWERPC64"
442 "@
443 lwa%U1%X1 %0,%1
444 extsw %0,%1"
b54cf83a 445 [(set_attr "type" "load_ext,*")])
51b8fc2c
RK		 446
447(define_insn ""
9ebbca7d
GK		 448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
449 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 450 (const_int 0)))
9ebbca7d 451 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 452 "TARGET_64BIT"
9ebbca7d
GK		 453 "@
454 extsw. %2,%1
455 #"
456 [(set_attr "type" "compare")
457 (set_attr "length" "4,8")])
458
459(define_split
460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
461 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
462 (const_int 0)))
463 (clobber (match_scratch:DI 2 ""))]
464 "TARGET_POWERPC64 && reload_completed"
465 [(set (match_dup 2)
466 (sign_extend:DI (match_dup 1)))
467 (set (match_dup 0)
468 (compare:CC (match_dup 2)
469 (const_int 0)))]
470 "")
51b8fc2c
RK		 471
472(define_insn ""
9ebbca7d
GK		 473 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
474 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 475 (const_int 0)))
9ebbca7d 476 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 477 (sign_extend:DI (match_dup 1)))]
683bdff7 478 "TARGET_64BIT"
9ebbca7d
GK		 479 "@
480 extsw. %0,%1
481 #"
482 [(set_attr "type" "compare")
483 (set_attr "length" "4,8")])
484
485(define_split
486 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
487 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
488 (const_int 0)))
489 (set (match_operand:DI 0 "gpc_reg_operand" "")
490 (sign_extend:DI (match_dup 1)))]
491 "TARGET_POWERPC64 && reload_completed"
492 [(set (match_dup 0)
493 (sign_extend:DI (match_dup 1)))
494 (set (match_dup 2)
495 (compare:CC (match_dup 0)
496 (const_int 0)))]
497 "")
51b8fc2c 498
1fd4e8c1 499(define_expand "zero_extendqisi2"
cd2b37d9
RK		 500 [(set (match_operand:SI 0 "gpc_reg_operand" "")
501 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 502 ""
503 "")
504
505(define_insn ""
cd2b37d9 506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 507 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
508 ""
509 "@
510 lbz%U1%X1 %0,%1
005a35b9 511 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 512 [(set_attr "type" "load,*")])
513
514(define_insn ""
9ebbca7d
GK		 515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
516 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 517 (const_int 0)))
9ebbca7d 518 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 519 ""
9ebbca7d
GK		 520 "@
521 {andil.|andi.} %2,%1,0xff
522 #"
523 [(set_attr "type" "compare")
524 (set_attr "length" "4,8")])
525
526(define_split
527 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
528 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
529 (const_int 0)))
530 (clobber (match_scratch:SI 2 ""))]
531 "reload_completed"
532 [(set (match_dup 2)
533 (zero_extend:SI (match_dup 1)))
534 (set (match_dup 0)
535 (compare:CC (match_dup 2)
536 (const_int 0)))]
537 "")
1fd4e8c1
RK		 538
539(define_insn ""
9ebbca7d
GK		 540 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
541 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 542 (const_int 0)))
9ebbca7d 543 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 544 (zero_extend:SI (match_dup 1)))]
545 ""
9ebbca7d
GK		 546 "@
547 {andil.|andi.} %0,%1,0xff
548 #"
549 [(set_attr "type" "compare")
550 (set_attr "length" "4,8")])
551
552(define_split
553 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
554 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
555 (const_int 0)))
556 (set (match_operand:SI 0 "gpc_reg_operand" "")
557 (zero_extend:SI (match_dup 1)))]
558 "reload_completed"
559 [(set (match_dup 0)
560 (zero_extend:SI (match_dup 1)))
561 (set (match_dup 2)
562 (compare:CC (match_dup 0)
563 (const_int 0)))]
564 "")
1fd4e8c1 565
51b8fc2c
RK		 566(define_expand "extendqisi2"
567 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
568 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
569 ""
570 "
571{
572 if (TARGET_POWERPC)
573 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
574 else if (TARGET_POWER)
575 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
576 else
577 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
578 DONE;
579}")
580
581(define_insn "extendqisi2_ppc"
2bee0449
RK		 582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
583 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 584 "TARGET_POWERPC"
2bee0449 585 "extsb %0,%1")
51b8fc2c
RK		 586
587(define_insn ""
9ebbca7d
GK		 588 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
589 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 590 (const_int 0)))
9ebbca7d 591 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 592 "TARGET_POWERPC"
9ebbca7d
GK		 593 "@
594 extsb. %2,%1
595 #"
596 [(set_attr "type" "compare")
597 (set_attr "length" "4,8")])
598
599(define_split
600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
601 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
602 (const_int 0)))
603 (clobber (match_scratch:SI 2 ""))]
604 "TARGET_POWERPC && reload_completed"
605 [(set (match_dup 2)
606 (sign_extend:SI (match_dup 1)))
607 (set (match_dup 0)
608 (compare:CC (match_dup 2)
609 (const_int 0)))]
610 "")
51b8fc2c
RK		 611
612(define_insn ""
9ebbca7d
GK		 613 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
614 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 615 (const_int 0)))
9ebbca7d 616 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 617 (sign_extend:SI (match_dup 1)))]
618 "TARGET_POWERPC"
9ebbca7d
GK		 619 "@
620 extsb. %0,%1
621 #"
622 [(set_attr "type" "compare")
623 (set_attr "length" "4,8")])
624
625(define_split
626 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
627 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
628 (const_int 0)))
629 (set (match_operand:SI 0 "gpc_reg_operand" "")
630 (sign_extend:SI (match_dup 1)))]
631 "TARGET_POWERPC && reload_completed"
632 [(set (match_dup 0)
633 (sign_extend:SI (match_dup 1)))
634 (set (match_dup 2)
635 (compare:CC (match_dup 0)
636 (const_int 0)))]
637 "")
51b8fc2c
RK		 638
639(define_expand "extendqisi2_power"
640 [(parallel [(set (match_dup 2)
641 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
642 (const_int 24)))
643 (clobber (scratch:SI))])
644 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
645 (ashiftrt:SI (match_dup 2)
646 (const_int 24)))
647 (clobber (scratch:SI))])]
648 "TARGET_POWER"
649 "
650{ operands[1] = gen_lowpart (SImode, operands[1]);
651 operands[2] = gen_reg_rtx (SImode); }")
652
653(define_expand "extendqisi2_no_power"
654 [(set (match_dup 2)
655 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
656 (const_int 24)))
657 (set (match_operand:SI 0 "gpc_reg_operand" "")
658 (ashiftrt:SI (match_dup 2)
659 (const_int 24)))]
660 "! TARGET_POWER && ! TARGET_POWERPC"
661 "
662{ operands[1] = gen_lowpart (SImode, operands[1]);
663 operands[2] = gen_reg_rtx (SImode); }")
664
1fd4e8c1 665(define_expand "zero_extendqihi2"
cd2b37d9
RK		 666 [(set (match_operand:HI 0 "gpc_reg_operand" "")
667 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 668 ""
669 "")
670
671(define_insn ""
cd2b37d9 672 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 673 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
674 ""
675 "@
676 lbz%U1%X1 %0,%1
005a35b9 677 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 678 [(set_attr "type" "load,*")])
679
680(define_insn ""
9ebbca7d
GK		 681 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
682 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 683 (const_int 0)))
9ebbca7d 684 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 685 ""
9ebbca7d
GK		 686 "@
687 {andil.|andi.} %2,%1,0xff
688 #"
689 [(set_attr "type" "compare")
690 (set_attr "length" "4,8")])
691
692(define_split
693 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
694 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
695 (const_int 0)))
696 (clobber (match_scratch:HI 2 ""))]
697 "reload_completed"
698 [(set (match_dup 2)
699 (zero_extend:HI (match_dup 1)))
700 (set (match_dup 0)
701 (compare:CC (match_dup 2)
702 (const_int 0)))]
703 "")
1fd4e8c1 704
51b8fc2c 705(define_insn ""
9ebbca7d
GK		 706 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
707 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 708 (const_int 0)))
9ebbca7d 709 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 710 (zero_extend:HI (match_dup 1)))]
711 ""
9ebbca7d
GK		 712 "@
713 {andil.|andi.} %0,%1,0xff
714 #"
715 [(set_attr "type" "compare")
716 (set_attr "length" "4,8")])
717
718(define_split
719 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
720 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
721 (const_int 0)))
722 (set (match_operand:HI 0 "gpc_reg_operand" "")
723 (zero_extend:HI (match_dup 1)))]
724 "reload_completed"
725 [(set (match_dup 0)
726 (zero_extend:HI (match_dup 1)))
727 (set (match_dup 2)
728 (compare:CC (match_dup 0)
729 (const_int 0)))]
730 "")
815cdc52
MM		 731
732(define_expand "extendqihi2"
733 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
734 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
735 ""
736 "
737{
738 if (TARGET_POWERPC)
739 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
740 else if (TARGET_POWER)
741 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
742 else
743 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
744 DONE;
745}")
746
747(define_insn "extendqihi2_ppc"
748 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
749 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
750 "TARGET_POWERPC"
751 "extsb %0,%1")
752
753(define_insn ""
9ebbca7d
GK		 754 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
755 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 756 (const_int 0)))
9ebbca7d 757 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 758 "TARGET_POWERPC"
9ebbca7d
GK		 759 "@
760 extsb. %2,%1
761 #"
762 [(set_attr "type" "compare")
763 (set_attr "length" "4,8")])
764
765(define_split
766 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
767 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
768 (const_int 0)))
769 (clobber (match_scratch:HI 2 ""))]
770 "TARGET_POWERPC && reload_completed"
771 [(set (match_dup 2)
772 (sign_extend:HI (match_dup 1)))
773 (set (match_dup 0)
774 (compare:CC (match_dup 2)
775 (const_int 0)))]
776 "")
815cdc52
MM		 777
778(define_insn ""
9ebbca7d
GK		 779 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
780 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 781 (const_int 0)))
9ebbca7d 782 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 783 (sign_extend:HI (match_dup 1)))]
784 "TARGET_POWERPC"
9ebbca7d
GK		 785 "@
786 extsb. %0,%1
787 #"
788 [(set_attr "type" "compare")
789 (set_attr "length" "4,8")])
790
791(define_split
792 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
793 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
794 (const_int 0)))
795 (set (match_operand:HI 0 "gpc_reg_operand" "")
796 (sign_extend:HI (match_dup 1)))]
797 "TARGET_POWERPC && reload_completed"
798 [(set (match_dup 0)
799 (sign_extend:HI (match_dup 1)))
800 (set (match_dup 2)
801 (compare:CC (match_dup 0)
802 (const_int 0)))]
803 "")
51b8fc2c
RK		 804
805(define_expand "extendqihi2_power"
806 [(parallel [(set (match_dup 2)
807 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
808 (const_int 24)))
809 (clobber (scratch:SI))])
810 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
811 (ashiftrt:SI (match_dup 2)
812 (const_int 24)))
813 (clobber (scratch:SI))])]
814 "TARGET_POWER"
815 "
816{ operands[0] = gen_lowpart (SImode, operands[0]);
817 operands[1] = gen_lowpart (SImode, operands[1]);
818 operands[2] = gen_reg_rtx (SImode); }")
819
820(define_expand "extendqihi2_no_power"
821 [(set (match_dup 2)
822 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
823 (const_int 24)))
824 (set (match_operand:HI 0 "gpc_reg_operand" "")
825 (ashiftrt:SI (match_dup 2)
826 (const_int 24)))]
827 "! TARGET_POWER && ! TARGET_POWERPC"
828 "
829{ operands[0] = gen_lowpart (SImode, operands[0]);
830 operands[1] = gen_lowpart (SImode, operands[1]);
831 operands[2] = gen_reg_rtx (SImode); }")
832
1fd4e8c1 833(define_expand "zero_extendhisi2"
5f243543 834 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 835 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 836 ""
837 "")
838
839(define_insn ""
cd2b37d9 840 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 841 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
842 ""
843 "@
844 lhz%U1%X1 %0,%1
005a35b9 845 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 846 [(set_attr "type" "load,*")])
847
848(define_insn ""
9ebbca7d
GK		 849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
850 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 851 (const_int 0)))
9ebbca7d 852 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 853 ""
9ebbca7d
GK		 854 "@
855 {andil.|andi.} %2,%1,0xffff
856 #"
857 [(set_attr "type" "compare")
858 (set_attr "length" "4,8")])
859
860(define_split
861 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
862 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
863 (const_int 0)))
864 (clobber (match_scratch:SI 2 ""))]
865 "reload_completed"
866 [(set (match_dup 2)
867 (zero_extend:SI (match_dup 1)))
868 (set (match_dup 0)
869 (compare:CC (match_dup 2)
870 (const_int 0)))]
871 "")
1fd4e8c1
RK		 872
873(define_insn ""
9ebbca7d
GK		 874 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
875 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 876 (const_int 0)))
9ebbca7d 877 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 878 (zero_extend:SI (match_dup 1)))]
879 ""
9ebbca7d
GK		 880 "@
881 {andil.|andi.} %0,%1,0xffff
882 #"
883 [(set_attr "type" "compare")
884 (set_attr "length" "4,8")])
885
886(define_split
887 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
888 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
889 (const_int 0)))
890 (set (match_operand:SI 0 "gpc_reg_operand" "")
891 (zero_extend:SI (match_dup 1)))]
892 "reload_completed"
893 [(set (match_dup 0)
894 (zero_extend:SI (match_dup 1)))
895 (set (match_dup 2)
896 (compare:CC (match_dup 0)
897 (const_int 0)))]
898 "")
1fd4e8c1
RK		 899
900(define_expand "extendhisi2"
cd2b37d9
RK		 901 [(set (match_operand:SI 0 "gpc_reg_operand" "")
902 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 903 ""
904 "")
905
906(define_insn ""
cd2b37d9 907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 908 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
909 ""
910 "@
911 lha%U1%X1 %0,%1
ca7f5001 912 {exts|extsh} %0,%1"
b54cf83a 913 [(set_attr "type" "load_ext,*")])
1fd4e8c1
RK		 914
915(define_insn ""
9ebbca7d
GK		 916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
917 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 918 (const_int 0)))
9ebbca7d 919 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 920 ""
9ebbca7d
GK		 921 "@
922 {exts.|extsh.} %2,%1
923 #"
924 [(set_attr "type" "compare")
925 (set_attr "length" "4,8")])
926
927(define_split
928 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
929 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
930 (const_int 0)))
931 (clobber (match_scratch:SI 2 ""))]
932 "reload_completed"
933 [(set (match_dup 2)
934 (sign_extend:SI (match_dup 1)))
935 (set (match_dup 0)
936 (compare:CC (match_dup 2)
937 (const_int 0)))]
938 "")
1fd4e8c1
RK		 939
940(define_insn ""
9ebbca7d
GK		 941 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
942 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 943 (const_int 0)))
9ebbca7d 944 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 945 (sign_extend:SI (match_dup 1)))]
946 ""
9ebbca7d
GK		 947 "@
948 {exts.|extsh.} %0,%1
949 #"
950 [(set_attr "type" "compare")
951 (set_attr "length" "4,8")])
1fd4e8c1 952\f
9ebbca7d
GK		 953(define_split
954 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
955 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
956 (const_int 0)))
957 (set (match_operand:SI 0 "gpc_reg_operand" "")
958 (sign_extend:SI (match_dup 1)))]
959 "reload_completed"
960 [(set (match_dup 0)
961 (sign_extend:SI (match_dup 1)))
962 (set (match_dup 2)
963 (compare:CC (match_dup 0)
964 (const_int 0)))]
965 "")
966
1fd4e8c1 967;; Fixed-point arithmetic insns.
deb9225a
RK		 968
969;; Discourage ai/addic because of carry but provide it in an alternative
970;; allowing register zero as source.
7cd5235b
MM		 971(define_expand "addsi3"
972 [(set (match_operand:SI 0 "gpc_reg_operand" "")
973 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
f6bf7de2 974 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
7cd5235b
MM		 975 ""
976 "
977{
677a9668
DE		 978 if (GET_CODE (operands[2]) == CONST_INT
979 && ! add_operand (operands[2], SImode))
7cd5235b 980 {
677a9668 981 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 982 ? operands[0] : gen_reg_rtx (SImode));
983
2bfcf297 984 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 985 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 986 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
7cd5235b 987
9ebbca7d
GK		 988 /* The ordering here is important for the prolog expander.
989 When space is allocated from the stack, adding 'low' first may
990 produce a temporary deallocation (which would be bad). */
2bfcf297 991 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
7cd5235b
MM		 992 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
993 DONE;
994 }
995}")
996
997(define_insn "*addsi3_internal1"
998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
999 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
9615f239 1000 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1fd4e8c1
RK		 1001 ""
1002 "@
deb9225a
RK		 1003 {cax|add} %0,%1,%2
1004 {cal %0,%2(%1)|addi %0,%1,%2}
1005 {ai|addic} %0,%1,%2
7cd5235b
MM		 1006 {cau|addis} %0,%1,%v2"
1007 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 1008
ee890fe2
SS		 1009(define_insn "addsi3_high"
1010 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1011 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1012 (high:SI (match_operand 2 "" ""))))]
1013 "TARGET_MACHO && !TARGET_64BIT"
1014 "{cau|addis} %0,%1,ha16(%2)"
1015 [(set_attr "length" "4")])
1016
7cd5235b 1017(define_insn "*addsi3_internal2"
cb8cc086
MM		 1018 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1019 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1020 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1021 (const_int 0)))
cb8cc086 1022 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
0ad91047 1023 "! TARGET_POWERPC64"
deb9225a
RK		 1024 "@
1025 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1026 {ai.|addic.} %3,%1,%2
1027 #
1028 #"
a62bfff2 1029 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1030 (set_attr "length" "4,4,8,8")])
1031
1032(define_split
1033 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1034 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1035 (match_operand:SI 2 "reg_or_short_operand" ""))
1036 (const_int 0)))
1037 (clobber (match_scratch:SI 3 ""))]
0ad91047 1038 "! TARGET_POWERPC64 && reload_completed"
cb8cc086
MM		 1039 [(set (match_dup 3)
1040 (plus:SI (match_dup 1)
1041 (match_dup 2)))
1042 (set (match_dup 0)
1043 (compare:CC (match_dup 3)
1044 (const_int 0)))]
1045 "")
7e69e155 1046
7cd5235b 1047(define_insn "*addsi3_internal3"
cb8cc086
MM		 1048 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1049 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1050 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1051 (const_int 0)))
cb8cc086
MM		 1052 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1053 (plus:SI (match_dup 1)
1054 (match_dup 2)))]
0ad91047 1055 "! TARGET_POWERPC64"
deb9225a
RK		 1056 "@
1057 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1058 {ai.|addic.} %0,%1,%2
1059 #
1060 #"
a62bfff2 1061 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1062 (set_attr "length" "4,4,8,8")])
1063
1064(define_split
1065 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1066 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1067 (match_operand:SI 2 "reg_or_short_operand" ""))
1068 (const_int 0)))
1069 (set (match_operand:SI 0 "gpc_reg_operand" "")
1070 (plus:SI (match_dup 1) (match_dup 2)))]
0ad91047 1071 "! TARGET_POWERPC64 && reload_completed"
cb8cc086
MM		 1072 [(set (match_dup 0)
1073 (plus:SI (match_dup 1)
1074 (match_dup 2)))
1075 (set (match_dup 3)
1076 (compare:CC (match_dup 0)
1077 (const_int 0)))]
1078 "")
7e69e155 1079
f357808b
RK		 1080;; Split an add that we can't do in one insn into two insns, each of which
1081;; does one 16-bit part. This is used by combine. Note that the low-order
1082;; add should be last in case the result gets used in an address.
1083
1084(define_split
cd2b37d9
RK		 1085 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1086 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
f357808b 1087 (match_operand:SI 2 "non_add_cint_operand" "")))]
1fd4e8c1 1088 ""
f357808b
RK		 1089 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1090 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1091"
1fd4e8c1 1092{
2bfcf297 1093 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1094 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 1095 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1fd4e8c1 1096
2bfcf297 1097 operands[3] = GEN_INT (rest);
e6ca2c17 1098 operands[4] = GEN_INT (low);
1fd4e8c1
RK		 1099}")
1100
8de2a197 1101(define_insn "one_cmplsi2"
cd2b37d9
RK		 1102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1103 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1104 ""
ca7f5001
RK		 1105 "nor %0,%1,%1")
1106
1107(define_insn ""
52d3af72
DE		 1108 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1109 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
ca7f5001 1110 (const_int 0)))
52d3af72 1111 (clobber (match_scratch:SI 2 "=r,r"))]
0ad91047 1112 "! TARGET_POWERPC64"
52d3af72
DE		 1113 "@
1114 nor. %2,%1,%1
1115 #"
1116 [(set_attr "type" "compare")
1117 (set_attr "length" "4,8")])
1118
1119(define_split
1120 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1121 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1122 (const_int 0)))
1123 (clobber (match_scratch:SI 2 ""))]
0ad91047 1124 "! TARGET_POWERPC64 && reload_completed"
52d3af72
DE		 1125 [(set (match_dup 2)
1126 (not:SI (match_dup 1)))
1127 (set (match_dup 0)
1128 (compare:CC (match_dup 2)
1129 (const_int 0)))]
1130 "")
ca7f5001
RK		 1131
1132(define_insn ""
52d3af72
DE		 1133 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1134 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
815cdc52 1135 (const_int 0)))
52d3af72 1136 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52 1137 (not:SI (match_dup 1)))]
0ad91047 1138 "! TARGET_POWERPC64"
52d3af72
DE		 1139 "@
1140 nor. %0,%1,%1
1141 #"
1142 [(set_attr "type" "compare")
1143 (set_attr "length" "4,8")])
1144
1145(define_split
1146 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1147 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1148 (const_int 0)))
1cb18e3c 1149 (set (match_operand:SI 0 "gpc_reg_operand" "")
52d3af72 1150 (not:SI (match_dup 1)))]
0ad91047 1151 "! TARGET_POWERPC64 && reload_completed"
52d3af72
DE		 1152 [(set (match_dup 0)
1153 (not:SI (match_dup 1)))
1154 (set (match_dup 2)
1155 (compare:CC (match_dup 0)
1156 (const_int 0)))]
1157 "")
1fd4e8c1
RK		 1158
1159(define_insn ""
3d91674b
RK		 1160 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1161 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1162 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1163 "! TARGET_POWERPC"
ca7f5001 1164 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1165
deb9225a
RK		 1166(define_insn ""
1167 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1168 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1169 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1170 "TARGET_POWERPC"
1171 "@
1172 subf %0,%2,%1
1173 subfic %0,%2,%1")
1174
1fd4e8c1 1175(define_insn ""
cb8cc086
MM		 1176 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1177 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1178 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1179 (const_int 0)))
cb8cc086 1180 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1181 "! TARGET_POWERPC"
cb8cc086
MM		 1182 "@
1183 {sf.|subfc.} %3,%2,%1
1184 #"
1185 [(set_attr "type" "compare")
1186 (set_attr "length" "4,8")])
1fd4e8c1 1187
deb9225a 1188(define_insn ""
cb8cc086
MM		 1189 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1190 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1191 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
deb9225a 1192 (const_int 0)))
cb8cc086 1193 (clobber (match_scratch:SI 3 "=r,r"))]
0ad91047 1194 "TARGET_POWERPC && ! TARGET_POWERPC64"
cb8cc086
MM		 1195 "@
1196 subf. %3,%2,%1
1197 #"
a62bfff2 1198 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1199 (set_attr "length" "4,8")])
1200
1201(define_split
1202 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1203 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1204 (match_operand:SI 2 "gpc_reg_operand" ""))
1205 (const_int 0)))
1206 (clobber (match_scratch:SI 3 ""))]
0ad91047 1207 "! TARGET_POWERPC64 && reload_completed"
cb8cc086
MM		 1208 [(set (match_dup 3)
1209 (minus:SI (match_dup 1)
1210 (match_dup 2)))
1211 (set (match_dup 0)
1212 (compare:CC (match_dup 3)
1213 (const_int 0)))]
1214 "")
deb9225a 1215
1fd4e8c1 1216(define_insn ""
cb8cc086
MM		 1217 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1218 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1219 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1220 (const_int 0)))
cb8cc086 1221 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1222 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1223 "! TARGET_POWERPC"
cb8cc086
MM		 1224 "@
1225 {sf.|subfc.} %0,%2,%1
1226 #"
1227 [(set_attr "type" "compare")
1228 (set_attr "length" "4,8")])
815cdc52 1229
29ae5b89 1230(define_insn ""
cb8cc086
MM		 1231 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1232 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1233 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
815cdc52 1234 (const_int 0)))
cb8cc086
MM		 1235 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1236 (minus:SI (match_dup 1)
1237 (match_dup 2)))]
0ad91047 1238 "TARGET_POWERPC && ! TARGET_POWERPC64"
90612787
DE		 1239 "@
1240 subf. %0,%2,%1
1241 #"
a62bfff2 1242 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1243 (set_attr "length" "4,8")])
1244
1245(define_split
1246 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1247 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1248 (match_operand:SI 2 "gpc_reg_operand" ""))
1249 (const_int 0)))
1250 (set (match_operand:SI 0 "gpc_reg_operand" "")
1251 (minus:SI (match_dup 1)
1252 (match_dup 2)))]
0ad91047 1253 "! TARGET_POWERPC64 && reload_completed"
cb8cc086
MM		 1254 [(set (match_dup 0)
1255 (minus:SI (match_dup 1)
1256 (match_dup 2)))
1257 (set (match_dup 3)
1258 (compare:CC (match_dup 0)
1259 (const_int 0)))]
1260 "")
deb9225a 1261
1fd4e8c1 1262(define_expand "subsi3"
cd2b37d9 1263 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1264 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
f6bf7de2 1265 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1fd4e8c1 1266 ""
a0044fb1
RK		 1267 "
1268{
1269 if (GET_CODE (operands[2]) == CONST_INT)
1270 {
1271 emit_insn (gen_addsi3 (operands[0], operands[1],
1272 negate_rtx (SImode, operands[2])));
1273 DONE;
1274 }
1275}")
1fd4e8c1
RK		 1276
1277;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1278;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1279;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1280;; combine.
1fd4e8c1
RK		 1281
1282(define_expand "sminsi3"
1283 [(set (match_dup 3)
cd2b37d9 1284 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1285 (match_operand:SI 2 "reg_or_short_operand" ""))
1286 (const_int 0)
1287 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1288 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1289 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1290 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1291 "
a3170dc6
AH		 1292{
1293 if (TARGET_ISEL)
1294 {
1295 operands[2] = force_reg (SImode, operands[2]);
1296 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1297 DONE;
1298 }
1299
1300 operands[3] = gen_reg_rtx (SImode);
1301}")
1fd4e8c1 1302
95ac8e67
RK		 1303(define_split
1304 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1305 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1306 (match_operand:SI 2 "reg_or_short_operand" "")))
1307 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1308 "TARGET_POWER"
95ac8e67
RK		 1309 [(set (match_dup 3)
1310 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1311 (const_int 0)
1312 (minus:SI (match_dup 2) (match_dup 1))))
1313 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1314 "")
1315
1fd4e8c1
RK		 1316(define_expand "smaxsi3"
1317 [(set (match_dup 3)
cd2b37d9 1318 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1319 (match_operand:SI 2 "reg_or_short_operand" ""))
1320 (const_int 0)
1321 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1322 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1323 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1324 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1325 "
a3170dc6
AH		 1326{
1327 if (TARGET_ISEL)
1328 {
1329 operands[2] = force_reg (SImode, operands[2]);
1330 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1331 DONE;
1332 }
1333 operands[3] = gen_reg_rtx (SImode);
1334}")
1fd4e8c1 1335
95ac8e67
RK		 1336(define_split
1337 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1338 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1339 (match_operand:SI 2 "reg_or_short_operand" "")))
1340 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1341 "TARGET_POWER"
95ac8e67
RK		 1342 [(set (match_dup 3)
1343 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1344 (const_int 0)
1345 (minus:SI (match_dup 2) (match_dup 1))))
1346 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1347 "")
1348
1fd4e8c1 1349(define_expand "uminsi3"
cd2b37d9 1350 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1351 (match_dup 5)))
cd2b37d9 1352 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1353 (match_dup 5)))
1fd4e8c1
RK		 1354 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1355 (const_int 0)
1356 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1357 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1358 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1359 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1360 "
bb68ff55 1361{
a3170dc6
AH		 1362 if (TARGET_ISEL)
1363 {
1364 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1365 DONE;
1366 }
bb68ff55
MM		 1367 operands[3] = gen_reg_rtx (SImode);
1368 operands[4] = gen_reg_rtx (SImode);
1369 operands[5] = GEN_INT (-2147483647 - 1);
1370}")
1fd4e8c1
RK		 1371
1372(define_expand "umaxsi3"
cd2b37d9 1373 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1374 (match_dup 5)))
cd2b37d9 1375 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1376 (match_dup 5)))
1fd4e8c1
RK		 1377 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1378 (const_int 0)
1379 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1380 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1381 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1382 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1383 "
bb68ff55 1384{
a3170dc6
AH		 1385 if (TARGET_ISEL)
1386 {
1387 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1388 DONE;
1389 }
bb68ff55
MM		 1390 operands[3] = gen_reg_rtx (SImode);
1391 operands[4] = gen_reg_rtx (SImode);
1392 operands[5] = GEN_INT (-2147483647 - 1);
1393}")
1fd4e8c1
RK		 1394
1395(define_insn ""
cd2b37d9
RK		 1396 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1397 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1398 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1399 (const_int 0)
1400 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1401 "TARGET_POWER"
1fd4e8c1
RK		 1402 "doz%I2 %0,%1,%2")
1403
1404(define_insn ""
9ebbca7d 1405 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1406 (compare:CC
9ebbca7d
GK		 1407 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1408 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1409 (const_int 0)
1410 (minus:SI (match_dup 2) (match_dup 1)))
1411 (const_int 0)))
9ebbca7d 1412 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1413 "TARGET_POWER"
9ebbca7d
GK		 1414 "@
1415 doz%I2. %3,%1,%2
1416 #"
1417 [(set_attr "type" "delayed_compare")
1418 (set_attr "length" "4,8")])
1419
1420(define_split
1421 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1422 (compare:CC
1423 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1424 (match_operand:SI 2 "reg_or_short_operand" ""))
1425 (const_int 0)
1426 (minus:SI (match_dup 2) (match_dup 1)))
1427 (const_int 0)))
1428 (clobber (match_scratch:SI 3 ""))]
1429 "TARGET_POWER && reload_completed"
1430 [(set (match_dup 3)
1431 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1432 (const_int 0)
1433 (minus:SI (match_dup 2) (match_dup 1))))
1434 (set (match_dup 0)
1435 (compare:CC (match_dup 3)
1436 (const_int 0)))]
1437 "")
1fd4e8c1
RK		 1438
1439(define_insn ""
9ebbca7d 1440 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1441 (compare:CC
9ebbca7d
GK		 1442 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1443 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1444 (const_int 0)
1445 (minus:SI (match_dup 2) (match_dup 1)))
1446 (const_int 0)))
9ebbca7d 1447 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1448 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1449 (const_int 0)
1450 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1451 "TARGET_POWER"
9ebbca7d
GK		 1452 "@
1453 doz%I2. %0,%1,%2
1454 #"
1455 [(set_attr "type" "delayed_compare")
1456 (set_attr "length" "4,8")])
1457
1458(define_split
1459 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1460 (compare:CC
1461 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1462 (match_operand:SI 2 "reg_or_short_operand" ""))
1463 (const_int 0)
1464 (minus:SI (match_dup 2) (match_dup 1)))
1465 (const_int 0)))
1466 (set (match_operand:SI 0 "gpc_reg_operand" "")
1467 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1468 (const_int 0)
1469 (minus:SI (match_dup 2) (match_dup 1))))]
1470 "TARGET_POWER && reload_completed"
1471 [(set (match_dup 0)
1472 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1473 (const_int 0)
1474 (minus:SI (match_dup 2) (match_dup 1))))
1475 (set (match_dup 3)
1476 (compare:CC (match_dup 0)
1477 (const_int 0)))]
1478 "")
1fd4e8c1
RK		 1479
1480;; We don't need abs with condition code because such comparisons should
1481;; never be done.
ea9be077
MM		 1482(define_expand "abssi2"
1483 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1484 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1485 ""
1486 "
1487{
a3170dc6
AH		 1488 if (TARGET_ISEL)
1489 {
1490 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1491 DONE;
1492 }
1493 else if (! TARGET_POWER)
ea9be077
MM		 1494 {
1495 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1496 DONE;
1497 }
1498}")
1499
ea112fc4 1500(define_insn "*abssi2_power"
cd2b37d9
RK		 1501 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1502 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 1503 "TARGET_POWER"
1fd4e8c1
RK		 1504 "abs %0,%1")
1505
a3170dc6
AH		 1506(define_insn_and_split "abssi2_isel"
1507 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1508 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 1509 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 1510 (clobber (match_scratch:CC 3 "=y"))]
1511 "TARGET_ISEL"
1512 "#"
1513 "&& reload_completed"
1514 [(set (match_dup 2) (neg:SI (match_dup 1)))
1515 (set (match_dup 3)
1516 (compare:CC (match_dup 1)
1517 (const_int 0)))
1518 (set (match_dup 0)
1519 (if_then_else:SI (ge (match_dup 3)
1520 (const_int 0))
1521 (match_dup 1)
1522 (match_dup 2)))]
1523 "")
1524
ea112fc4 1525(define_insn_and_split "abssi2_nopower"
ea9be077 1526 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 1527 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 1528 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 1529 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 1530 "#"
1531 "&& reload_completed"
ea9be077
MM		 1532 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1533 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 1534 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 1535 "")
1536
463b558b 1537(define_insn "*nabs_power"
cd2b37d9
RK		 1538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1539 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 1540 "TARGET_POWER"
1fd4e8c1
RK		 1541 "nabs %0,%1")
1542
ea112fc4 1543(define_insn_and_split "*nabs_nopower"
ea9be077 1544 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 1545 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 1546 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 1547 "! TARGET_POWER"
ea112fc4
DE		 1548 "#"
1549 "&& reload_completed"
ea9be077
MM		 1550 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1551 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 1552 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 1553 "")
1554
1fd4e8c1 1555(define_insn "negsi2"
cd2b37d9
RK		 1556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1557 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 1558 ""
1559 "neg %0,%1")
1560
1561(define_insn ""
9ebbca7d
GK		 1562 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1563 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 1564 (const_int 0)))
9ebbca7d 1565 (clobber (match_scratch:SI 2 "=r,r"))]
0ad91047 1566 "! TARGET_POWERPC64"
9ebbca7d
GK		 1567 "@
1568 neg. %2,%1
1569 #"
a62bfff2 1570 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 1571 (set_attr "length" "4,8")])
1572
1573(define_split
1574 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1575 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1576 (const_int 0)))
1577 (clobber (match_scratch:SI 2 ""))]
1578 "! TARGET_POWERPC64 && reload_completed"
1579 [(set (match_dup 2)
1580 (neg:SI (match_dup 1)))
1581 (set (match_dup 0)
1582 (compare:CC (match_dup 2)
1583 (const_int 0)))]
1584 "")
1fd4e8c1
RK		 1585
1586(define_insn ""
9ebbca7d
GK		 1587 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1588 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
815cdc52 1589 (const_int 0)))
9ebbca7d 1590 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52 1591 (neg:SI (match_dup 1)))]
0ad91047 1592 "! TARGET_POWERPC64"
9ebbca7d
GK		 1593 "@
1594 neg. %0,%1
1595 #"
a62bfff2 1596 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 1597 (set_attr "length" "4,8")])
1598
1599(define_split
1600 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1601 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1602 (const_int 0)))
1603 (set (match_operand:SI 0 "gpc_reg_operand" "")
1604 (neg:SI (match_dup 1)))]
1605 "! TARGET_POWERPC64 && reload_completed"
1606 [(set (match_dup 0)
1607 (neg:SI (match_dup 1)))
1608 (set (match_dup 2)
1609 (compare:CC (match_dup 0)
1610 (const_int 0)))]
1611 "")
1fd4e8c1 1612
1b1edcfa
DE		 1613(define_insn "clzsi2"
1614 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1615 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1616 ""
1617 "{cntlz|cntlzw} %0,%1")
1618
1619(define_expand "ctzsi2"
4977bab6 1620 [(set (match_dup 2)
1b1edcfa 1621 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
4977bab6 1622 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1b1edcfa
DE		 1623 (match_dup 2)))
1624 (clobber (scratch:CC))])
d865b122 1625 (set (match_dup 4) (clz:SI (match_dup 3)))
4977bab6 1626 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1b1edcfa 1627 (minus:SI (const_int 31) (match_dup 4)))]
1fd4e8c1 1628 ""
4977bab6
ZW		 1629 {
1630 operands[2] = gen_reg_rtx (SImode);
1631 operands[3] = gen_reg_rtx (SImode);
1632 operands[4] = gen_reg_rtx (SImode);
1633 })
1634
1b1edcfa
DE		 1635(define_expand "ffssi2"
1636 [(set (match_dup 2)
1637 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1638 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1639 (match_dup 2)))
1640 (clobber (scratch:CC))])
1641 (set (match_dup 4) (clz:SI (match_dup 3)))
1642 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1643 (minus:SI (const_int 32) (match_dup 4)))]
4977bab6 1644 ""
1b1edcfa
DE		 1645 {
1646 operands[2] = gen_reg_rtx (SImode);
1647 operands[3] = gen_reg_rtx (SImode);
1648 operands[4] = gen_reg_rtx (SImode);
1649 })
1650
ca7f5001
RK		 1651(define_expand "mulsi3"
1652 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1653 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1654 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1655 ""
1656 "
1657{
1658 if (TARGET_POWER)
68b40e7e 1659 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 1660 else
68b40e7e 1661 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 1662 DONE;
1663}")
1664
68b40e7e 1665(define_insn "mulsi3_mq"
cd2b37d9
RK		 1666 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1667 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 1668 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1669 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 1670 "TARGET_POWER"
1671 "@
1672 {muls|mullw} %0,%1,%2
1673 {muli|mulli} %0,%1,%2"
c859cda6
DJ		 1674 [(set (attr "type")
1675 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1676 (const_string "imul3")
1677 (match_operand:SI 2 "short_cint_operand" "")
1678 (const_string "imul2")]
1679 (const_string "imul")))])
ca7f5001 1680
68b40e7e 1681(define_insn "mulsi3_no_mq"
ca7f5001
RK		 1682 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1683 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1684 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 1685 "! TARGET_POWER"
1fd4e8c1 1686 "@
d904e9ed
RK		 1687 {muls|mullw} %0,%1,%2
1688 {muli|mulli} %0,%1,%2"
c859cda6
DJ		 1689 [(set (attr "type")
1690 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1691 (const_string "imul3")
1692 (match_operand:SI 2 "short_cint_operand" "")
1693 (const_string "imul2")]
1694 (const_string "imul")))])
1fd4e8c1 1695
9259f3b0 1696(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 1697 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1698 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1699 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1700 (const_int 0)))
9ebbca7d
GK		 1701 (clobber (match_scratch:SI 3 "=r,r"))
1702 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 1703 "TARGET_POWER"
9ebbca7d
GK		 1704 "@
1705 {muls.|mullw.} %3,%1,%2
1706 #"
9259f3b0 1707 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1708 (set_attr "length" "4,8")])
1709
1710(define_split
1711 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1712 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1713 (match_operand:SI 2 "gpc_reg_operand" ""))
1714 (const_int 0)))
1715 (clobber (match_scratch:SI 3 ""))
1716 (clobber (match_scratch:SI 4 ""))]
1717 "TARGET_POWER && reload_completed"
1718 [(parallel [(set (match_dup 3)
1719 (mult:SI (match_dup 1) (match_dup 2)))
1720 (clobber (match_dup 4))])
1721 (set (match_dup 0)
1722 (compare:CC (match_dup 3)
1723 (const_int 0)))]
1724 "")
ca7f5001 1725
9259f3b0 1726(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 1727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1728 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1729 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 1730 (const_int 0)))
9ebbca7d 1731 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 1732 "! TARGET_POWER"
9ebbca7d
GK		 1733 "@
1734 {muls.|mullw.} %3,%1,%2
1735 #"
9259f3b0 1736 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1737 (set_attr "length" "4,8")])
1738
1739(define_split
1740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1741 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1742 (match_operand:SI 2 "gpc_reg_operand" ""))
1743 (const_int 0)))
1744 (clobber (match_scratch:SI 3 ""))]
1745 "! TARGET_POWER && reload_completed"
1746 [(set (match_dup 3)
1747 (mult:SI (match_dup 1) (match_dup 2)))
1748 (set (match_dup 0)
1749 (compare:CC (match_dup 3)
1750 (const_int 0)))]
1751 "")
1fd4e8c1 1752
9259f3b0 1753(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 1754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1755 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1756 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1757 (const_int 0)))
9ebbca7d 1758 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 1759 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 1760 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 1761 "TARGET_POWER"
9ebbca7d
GK		 1762 "@
1763 {muls.|mullw.} %0,%1,%2
1764 #"
9259f3b0 1765 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1766 (set_attr "length" "4,8")])
1767
1768(define_split
1769 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1770 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1771 (match_operand:SI 2 "gpc_reg_operand" ""))
1772 (const_int 0)))
1773 (set (match_operand:SI 0 "gpc_reg_operand" "")
1774 (mult:SI (match_dup 1) (match_dup 2)))
1775 (clobber (match_scratch:SI 4 ""))]
1776 "TARGET_POWER && reload_completed"
1777 [(parallel [(set (match_dup 0)
1778 (mult:SI (match_dup 1) (match_dup 2)))
1779 (clobber (match_dup 4))])
1780 (set (match_dup 3)
1781 (compare:CC (match_dup 0)
1782 (const_int 0)))]
1783 "")
ca7f5001 1784
9259f3b0 1785(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 1786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1787 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1788 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 1789 (const_int 0)))
9ebbca7d 1790 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 1791 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 1792 "! TARGET_POWER"
9ebbca7d
GK		 1793 "@
1794 {muls.|mullw.} %0,%1,%2
1795 #"
9259f3b0 1796 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1797 (set_attr "length" "4,8")])
1798
1799(define_split
1800 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1801 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1802 (match_operand:SI 2 "gpc_reg_operand" ""))
1803 (const_int 0)))
1804 (set (match_operand:SI 0 "gpc_reg_operand" "")
1805 (mult:SI (match_dup 1) (match_dup 2)))]
1806 "! TARGET_POWER && reload_completed"
1807 [(set (match_dup 0)
1808 (mult:SI (match_dup 1) (match_dup 2)))
1809 (set (match_dup 3)
1810 (compare:CC (match_dup 0)
1811 (const_int 0)))]
1812 "")
1fd4e8c1
RK		 1813
1814;; Operand 1 is divided by operand 2; quotient goes to operand
1815;; 0 and remainder to operand 3.
1816;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1817
8ffd9c51
RK		 1818(define_expand "divmodsi4"
1819 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1820 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1821 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 1822 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 1823 (mod:SI (match_dup 1) (match_dup 2)))])]
1824 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1825 "
1826{
1827 if (! TARGET_POWER && ! TARGET_POWERPC)
1828 {
39403d82
DE		 1829 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1830 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1831 emit_insn (gen_divss_call ());
39403d82
DE		 1832 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1833 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 1834 DONE;
1835 }
1836}")
deb9225a 1837
bb157ff4 1838(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 1839 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1840 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1841 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 1842 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 1843 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 1844 "TARGET_POWER"
cfb557c4
RK		 1845 "divs %0,%1,%2"
1846 [(set_attr "type" "idiv")])
1fd4e8c1 1847
8ffd9c51
RK		 1848(define_expand "udivsi3"
1849 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1850 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1851 (match_operand:SI 2 "gpc_reg_operand" "")))]
1852 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1853 "
1854{
1855 if (! TARGET_POWER && ! TARGET_POWERPC)
1856 {
39403d82
DE		 1857 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1858 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1859 emit_insn (gen_quous_call ());
39403d82 1860 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 1861 DONE;
1862 }
f192bf8b
DE		 1863 else if (TARGET_POWER)
1864 {
1865 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1866 DONE;
1867 }
8ffd9c51 1868}")
deb9225a 1869
f192bf8b
DE		 1870(define_insn "udivsi3_mq"
1871 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1872 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1873 (match_operand:SI 2 "gpc_reg_operand" "r")))
1874 (clobber (match_scratch:SI 3 "=q"))]
1875 "TARGET_POWERPC && TARGET_POWER"
1876 "divwu %0,%1,%2"
1877 [(set_attr "type" "idiv")])
1878
1879(define_insn "*udivsi3_no_mq"
ca7f5001
RK		 1880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1881 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1882 (match_operand:SI 2 "gpc_reg_operand" "r")))]
f192bf8b 1883 "TARGET_POWERPC && ! TARGET_POWER"
a473029f 1884 "divwu %0,%1,%2"
ca7f5001
RK		 1885 [(set_attr "type" "idiv")])
1886
1fd4e8c1 1887;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 1888;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 1889;; used; for PowerPC, force operands into register and do a normal divide;
1890;; for AIX common-mode, use quoss call on register operands.
1fd4e8c1 1891(define_expand "divsi3"
cd2b37d9
RK		 1892 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1893 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1894 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1895 ""
1896 "
1897{
ca7f5001 1898 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 1899 && INTVAL (operands[2]) > 0
ca7f5001
RK		 1900 && exact_log2 (INTVAL (operands[2])) >= 0)
1901 ;
b6c9286a 1902 else if (TARGET_POWERPC)
f192bf8b
DE		 1903 {
1904 operands[2] = force_reg (SImode, operands[2]);
1905 if (TARGET_POWER)
1906 {
1907 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1908 DONE;
1909 }
1910 }
b6c9286a 1911 else if (TARGET_POWER)
1fd4e8c1 1912 FAIL;
405c5495 1913 else
8ffd9c51 1914 {
39403d82
DE		 1915 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1916 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1917 emit_insn (gen_quoss_call ());
39403d82 1918 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 1919 DONE;
1920 }
1fd4e8c1
RK		 1921}")
1922
f192bf8b
DE		 1923(define_insn "divsi3_mq"
1924 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1925 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1926 (match_operand:SI 2 "gpc_reg_operand" "r")))
1927 (clobber (match_scratch:SI 3 "=q"))]
1928 "TARGET_POWERPC && TARGET_POWER"
1929 "divw %0,%1,%2"
1930 [(set_attr "type" "idiv")])
1931
1932(define_insn "*divsi3_no_mq"
1933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1934 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1935 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1936 "TARGET_POWERPC && ! TARGET_POWER"
1937 "divw %0,%1,%2"
1938 [(set_attr "type" "idiv")])
1939
1fd4e8c1 1940(define_expand "modsi3"
85644414
RK		 1941 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1942 (use (match_operand:SI 1 "gpc_reg_operand" ""))
405c5495 1943 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
39b52ba2 1944 ""
1fd4e8c1
RK		 1945 "
1946{
481c7efa 1947 int i;
39b52ba2
RK		 1948 rtx temp1;
1949 rtx temp2;
1950
2bfcf297 1951 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 1952 || INTVAL (operands[2]) <= 0
2bfcf297 1953 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 1954 FAIL;
1955
1956 temp1 = gen_reg_rtx (SImode);
1957 temp2 = gen_reg_rtx (SImode);
1fd4e8c1 1958
85644414 1959 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
39b52ba2 1960 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
85644414
RK		 1961 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1962 DONE;
1fd4e8c1
RK		 1963}")
1964
1965(define_insn ""
cd2b37d9
RK		 1966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1967 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2bfcf297
DB		 1968 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1969 ""
ca7f5001 1970 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
b19003d8 1971 [(set_attr "length" "8")])
1fd4e8c1
RK		 1972
1973(define_insn ""
9ebbca7d
GK		 1974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1975 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2bfcf297 1976 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
b6b12107 1977 (const_int 0)))
9ebbca7d 1978 (clobber (match_scratch:SI 3 "=r,r"))]
2bfcf297 1979 ""
9ebbca7d
GK		 1980 "@
1981 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1982 #"
b19003d8 1983 [(set_attr "type" "compare")
9ebbca7d
GK		 1984 (set_attr "length" "8,12")])
1985
1986(define_split
1987 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1988 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2bfcf297 1989 (match_operand:SI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 1990 (const_int 0)))
1991 (clobber (match_scratch:SI 3 ""))]
2bfcf297 1992 "reload_completed"
9ebbca7d
GK		 1993 [(set (match_dup 3)
1994 (div:SI (match_dup 1) (match_dup 2)))
1995 (set (match_dup 0)
1996 (compare:CC (match_dup 3)
1997 (const_int 0)))]
1998 "")
1fd4e8c1
RK		 1999
2000(define_insn ""
9ebbca7d
GK		 2001 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2002 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2bfcf297 2003 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2004 (const_int 0)))
9ebbca7d 2005 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 2006 (div:SI (match_dup 1) (match_dup 2)))]
2bfcf297 2007 ""
9ebbca7d
GK		 2008 "@
2009 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2010 #"
b19003d8 2011 [(set_attr "type" "compare")
9ebbca7d
GK		 2012 (set_attr "length" "8,12")])
2013
2014(define_split
2015 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2016 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2bfcf297 2017 (match_operand:SI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 2018 (const_int 0)))
2019 (set (match_operand:SI 0 "gpc_reg_operand" "")
2020 (div:SI (match_dup 1) (match_dup 2)))]
2bfcf297 2021 "reload_completed"
9ebbca7d
GK		 2022 [(set (match_dup 0)
2023 (div:SI (match_dup 1) (match_dup 2)))
2024 (set (match_dup 3)
2025 (compare:CC (match_dup 0)
2026 (const_int 0)))]
2027 "")
1fd4e8c1
RK		 2028
2029(define_insn ""
cd2b37d9 2030 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2031 (udiv:SI
996a5f59 2032 (plus:DI (ashift:DI
cd2b37d9 2033 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2034 (const_int 32))
23a900dc 2035 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2036 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2037 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2038 (umod:SI
996a5f59 2039 (plus:DI (ashift:DI
1fd4e8c1 2040 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2041 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2042 (match_dup 3)))]
ca7f5001 2043 "TARGET_POWER"
cfb557c4
RK		 2044 "div %0,%1,%3"
2045 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2046
2047;; To do unsigned divide we handle the cases of the divisor looking like a
2048;; negative number. If it is a constant that is less than 2**31, we don't
2049;; have to worry about the branches. So make a few subroutines here.
2050;;
2051;; First comes the normal case.
2052(define_expand "udivmodsi4_normal"
2053 [(set (match_dup 4) (const_int 0))
2054 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2055 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2056 (const_int 32))
2057 (zero_extend:DI (match_operand:SI 1 "" "")))
2058 (match_operand:SI 2 "" "")))
2059 (set (match_operand:SI 3 "" "")
996a5f59 2060 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2061 (const_int 32))
2062 (zero_extend:DI (match_dup 1)))
2063 (match_dup 2)))])]
ca7f5001 2064 "TARGET_POWER"
1fd4e8c1
RK		 2065 "
2066{ operands[4] = gen_reg_rtx (SImode); }")
2067
2068;; This handles the branches.
2069(define_expand "udivmodsi4_tests"
2070 [(set (match_operand:SI 0 "" "") (const_int 0))
2071 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2072 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2073 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2074 (label_ref (match_operand:SI 4 "" "")) (pc)))
2075 (set (match_dup 0) (const_int 1))
2076 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2077 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2078 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2079 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2080 "TARGET_POWER"
1fd4e8c1
RK		 2081 "
2082{ operands[5] = gen_reg_rtx (CCUNSmode);
2083 operands[6] = gen_reg_rtx (CCmode);
2084}")
2085
2086(define_expand "udivmodsi4"
cd2b37d9
RK		 2087 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2088 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2089 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2090 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2091 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2092 ""
1fd4e8c1
RK		 2093 "
2094{
2095 rtx label = 0;
2096
8ffd9c51 2097 if (! TARGET_POWER)
c4d38ccb
MM		 2098 {
2099 if (! TARGET_POWERPC)
2100 {
39403d82
DE		 2101 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2102 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2103 emit_insn (gen_divus_call ());
39403d82
DE		 2104 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2105 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2106 DONE;
2107 }
2108 else
2109 FAIL;
2110 }
0081a354 2111
1fd4e8c1
RK		 2112 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2113 {
2114 operands[2] = force_reg (SImode, operands[2]);
2115 label = gen_label_rtx ();
2116 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2117 operands[3], label));
2118 }
2119 else
2120 operands[2] = force_reg (SImode, operands[2]);
2121
2122 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2123 operands[3]));
2124 if (label)
2125 emit_label (label);
2126
2127 DONE;
2128}")
0081a354 2129
fada905b
MM		 2130;; AIX architecture-independent common-mode multiply (DImode),
2131;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2132;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2133;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2134;; assumed unused if generating common-mode, so ignore.
2135(define_insn "mulh_call"
2136 [(set (reg:SI 3)
2137 (truncate:SI
2138 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2139 (sign_extend:DI (reg:SI 4)))
2140 (const_int 32))))
cf27b467 2141 (clobber (match_scratch:SI 0 "=l"))]
fada905b 2142 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2143 "bla __mulh"
2144 [(set_attr "type" "imul")])
fada905b
MM		 2145
2146(define_insn "mull_call"
2147 [(set (reg:DI 3)
2148 (mult:DI (sign_extend:DI (reg:SI 3))
2149 (sign_extend:DI (reg:SI 4))))
2150 (clobber (match_scratch:SI 0 "=l"))
2151 (clobber (reg:SI 0))]
2152 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2153 "bla __mull"
2154 [(set_attr "type" "imul")])
fada905b
MM		 2155
2156(define_insn "divss_call"
2157 [(set (reg:SI 3)
2158 (div:SI (reg:SI 3) (reg:SI 4)))
2159 (set (reg:SI 4)
2160 (mod:SI (reg:SI 3) (reg:SI 4)))
2161 (clobber (match_scratch:SI 0 "=l"))
2162 (clobber (reg:SI 0))]
2163 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2164 "bla __divss"
2165 [(set_attr "type" "idiv")])
fada905b
MM		 2166
2167(define_insn "divus_call"
8ffd9c51
RK		 2168 [(set (reg:SI 3)
2169 (udiv:SI (reg:SI 3) (reg:SI 4)))
2170 (set (reg:SI 4)
2171 (umod:SI (reg:SI 3) (reg:SI 4)))
2172 (clobber (match_scratch:SI 0 "=l"))
fada905b
MM		 2173 (clobber (reg:SI 0))
2174 (clobber (match_scratch:CC 1 "=x"))
2175 (clobber (reg:CC 69))]
2176 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2177 "bla __divus"
2178 [(set_attr "type" "idiv")])
fada905b
MM		 2179
2180(define_insn "quoss_call"
2181 [(set (reg:SI 3)
2182 (div:SI (reg:SI 3) (reg:SI 4)))
cf27b467 2183 (clobber (match_scratch:SI 0 "=l"))]
8ffd9c51 2184 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2185 "bla __quoss"
2186 [(set_attr "type" "idiv")])
0081a354 2187
fada905b
MM		 2188(define_insn "quous_call"
2189 [(set (reg:SI 3)
2190 (udiv:SI (reg:SI 3) (reg:SI 4)))
2191 (clobber (match_scratch:SI 0 "=l"))
2192 (clobber (reg:SI 0))
2193 (clobber (match_scratch:CC 1 "=x"))
2194 (clobber (reg:CC 69))]
2195 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2196 "bla __quous"
2197 [(set_attr "type" "idiv")])
8ffd9c51 2198\f
bb21487f 2199;; Logical instructions
dfbdccdb
GK		 2200;; The logical instructions are mostly combined by using match_operator,
2201;; but the plain AND insns are somewhat different because there is no
2202;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2203;; those rotate-and-mask operations. Thus, the AND insns come first.
2204
29ae5b89
JL		 2205(define_insn "andsi3"
2206 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2207 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2208 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2209 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1fd4e8c1
RK		 2210 ""
2211 "@
2212 and %0,%1,%2
ca7f5001
RK		 2213 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2214 {andil.|andi.} %0,%1,%b2
9ebbca7d 2215 {andiu.|andis.} %0,%1,%u2")
52d3af72
DE		 2216
2217;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2218;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2219;; machines causes an execution serialization
1fd4e8c1 2220
7cd5235b 2221(define_insn "*andsi3_internal2"
52d3af72
DE		 2222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2223 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2224 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2225 (const_int 0)))
52d3af72
DE		 2226 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2227 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
0ad91047 2228 "! TARGET_POWERPC64"
1fd4e8c1
RK		 2229 "@
2230 and. %3,%1,%2
ca7f5001
RK		 2231 {andil.|andi.} %3,%1,%b2
2232 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2233 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2234 #
2235 #
2236 #
2237 #"
2238 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2239 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2240
0ba1b2ff
AM		 2241(define_insn "*andsi3_internal3"
2242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2243 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2244 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2245 (const_int 0)))
2246 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2247 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2248 "TARGET_64BIT"
0ba1b2ff
AM		 2249 "@
2250 #
2251 {andil.|andi.} %3,%1,%b2
2252 {andiu.|andis.} %3,%1,%u2
2253 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2254 #
2255 #
2256 #
2257 #"
2258 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2259 (set_attr "length" "8,4,4,4,8,8,8,8")])
2260
52d3af72
DE		 2261(define_split
2262 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2263 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2264 (match_operand:SI 2 "and_operand" ""))
1fd4e8c1 2265 (const_int 0)))
52d3af72
DE		 2266 (clobber (match_scratch:SI 3 ""))
2267 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2268 "reload_completed"
52d3af72
DE		 2269 [(parallel [(set (match_dup 3)
2270 (and:SI (match_dup 1)
2271 (match_dup 2)))
2272 (clobber (match_dup 4))])
2273 (set (match_dup 0)
2274 (compare:CC (match_dup 3)
2275 (const_int 0)))]
2276 "")
2277
0ba1b2ff
AM		 2278;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2279;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2280
2281(define_split
2282 [(set (match_operand:CC 0 "cc_reg_operand" "")
2283 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2284 (match_operand:SI 2 "gpc_reg_operand" ""))
2285 (const_int 0)))
2286 (clobber (match_scratch:SI 3 ""))
2287 (clobber (match_scratch:CC 4 ""))]
2288 "TARGET_POWERPC64 && reload_completed"
2289 [(parallel [(set (match_dup 3)
2290 (and:SI (match_dup 1)
2291 (match_dup 2)))
2292 (clobber (match_dup 4))])
2293 (set (match_dup 0)
2294 (compare:CC (match_dup 3)
2295 (const_int 0)))]
2296 "")
2297
2298(define_insn "*andsi3_internal4"
52d3af72
DE		 2299 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2300 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2301 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2302 (const_int 0)))
2303 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2304 (and:SI (match_dup 1)
2305 (match_dup 2)))
2306 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
0ad91047 2307 "! TARGET_POWERPC64"
1fd4e8c1
RK		 2308 "@
2309 and. %0,%1,%2
ca7f5001
RK		 2310 {andil.|andi.} %0,%1,%b2
2311 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2312 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2313 #
2314 #
2315 #
2316 #"
2317 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2318 (set_attr "length" "4,4,4,4,8,8,8,8")])
2319
0ba1b2ff
AM		 2320(define_insn "*andsi3_internal5"
2321 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2322 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2323 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2324 (const_int 0)))
2325 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2326 (and:SI (match_dup 1)
2327 (match_dup 2)))
2328 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2329 "TARGET_64BIT"
0ba1b2ff
AM		 2330 "@
2331 #
2332 {andil.|andi.} %0,%1,%b2
2333 {andiu.|andis.} %0,%1,%u2
2334 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2335 #
2336 #
2337 #
2338 #"
2339 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2340 (set_attr "length" "8,4,4,4,8,8,8,8")])
2341
52d3af72
DE		 2342(define_split
2343 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2344 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2345 (match_operand:SI 2 "and_operand" ""))
2346 (const_int 0)))
2347 (set (match_operand:SI 0 "gpc_reg_operand" "")
2348 (and:SI (match_dup 1)
2349 (match_dup 2)))
2350 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2351 "reload_completed"
52d3af72
DE		 2352 [(parallel [(set (match_dup 0)
2353 (and:SI (match_dup 1)
2354 (match_dup 2)))
2355 (clobber (match_dup 4))])
2356 (set (match_dup 3)
2357 (compare:CC (match_dup 0)
2358 (const_int 0)))]
2359 "")
1fd4e8c1 2360
0ba1b2ff
AM		 2361(define_split
2362 [(set (match_operand:CC 3 "cc_reg_operand" "")
2363 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2364 (match_operand:SI 2 "gpc_reg_operand" ""))
2365 (const_int 0)))
2366 (set (match_operand:SI 0 "gpc_reg_operand" "")
2367 (and:SI (match_dup 1)
2368 (match_dup 2)))
2369 (clobber (match_scratch:CC 4 ""))]
2370 "TARGET_POWERPC64 && reload_completed"
2371 [(parallel [(set (match_dup 0)
2372 (and:SI (match_dup 1)
2373 (match_dup 2)))
2374 (clobber (match_dup 4))])
2375 (set (match_dup 3)
2376 (compare:CC (match_dup 0)
2377 (const_int 0)))]
2378 "")
2379
2380;; Handle the PowerPC64 rlwinm corner case
2381
2382(define_insn_and_split "*andsi3_internal6"
2383 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2384 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2385 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2386 "TARGET_POWERPC64"
2387 "#"
2388 "TARGET_POWERPC64"
2389 [(set (match_dup 0)
2390 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2391 (match_dup 4)))
2392 (set (match_dup 0)
2393 (rotate:SI (match_dup 0) (match_dup 5)))]
2394 "
2395{
2396 int mb = extract_MB (operands[2]);
2397 int me = extract_ME (operands[2]);
2398 operands[3] = GEN_INT (me + 1);
2399 operands[5] = GEN_INT (32 - (me + 1));
2400 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2401}"
2402 [(set_attr "length" "8")])
2403
2404(define_insn_and_split "*andsi3_internal7"
2405 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2406 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
2407 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
2408 (const_int 0)))
2409 (clobber (match_scratch:SI 3 "=r,r"))]
2410 "TARGET_POWERPC64"
2411 "#"
2412 "TARGET_POWERPC64"
2413 [(parallel [(set (match_dup 2)
2414 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
2415 (match_dup 5))
2416 (const_int 0)))
2417 (clobber (match_dup 3))])]
2418 "
2419{
2420 int mb = extract_MB (operands[1]);
2421 int me = extract_ME (operands[1]);
2422 operands[4] = GEN_INT (me + 1);
2423 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2424}"
2425 [(set_attr "type" "delayed_compare,compare")
2426 (set_attr "length" "4,8")])
2427
2428(define_insn_and_split "*andsi3_internal8"
2429 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2430 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2431 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
2432 (const_int 0)))
2433 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2434 (and:SI (match_dup 1)
2435 (match_dup 2)))]
2436 "TARGET_POWERPC64"
2437 "#"
2438 "TARGET_POWERPC64"
2439 [(parallel [(set (match_dup 3)
2440 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2441 (match_dup 5))
2442 (const_int 0)))
2443 (set (match_dup 0)
2444 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2445 (match_dup 5)))])
2446 (set (match_dup 0)
2447 (rotate:SI (match_dup 0) (match_dup 6)))]
2448 "
2449{
2450 int mb = extract_MB (operands[2]);
2451 int me = extract_ME (operands[2]);
2452 operands[4] = GEN_INT (me + 1);
2453 operands[6] = GEN_INT (32 - (me + 1));
2454 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2455}"
2456 [(set_attr "type" "delayed_compare,compare")
2457 (set_attr "length" "8,12")])
2458
7cd5235b 2459(define_expand "iorsi3"
cd2b37d9 2460 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 2461 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 2462 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 2463 ""
f357808b
RK		 2464 "
2465{
7cd5235b 2466 if (GET_CODE (operands[2]) == CONST_INT
677a9668 2467 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 2468 {
2469 HOST_WIDE_INT value = INTVAL (operands[2]);
677a9668 2470 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 2471 ? operands[0] : gen_reg_rtx (SImode));
2472
a260abc9
DE		 2473 emit_insn (gen_iorsi3 (tmp, operands[1],
2474 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2475 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 2476 DONE;
2477 }
f357808b
RK		 2478}")
2479
7cd5235b 2480(define_expand "xorsi3"
cd2b37d9 2481 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 2482 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 2483 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 2484 ""
7cd5235b 2485 "
1fd4e8c1 2486{
7cd5235b 2487 if (GET_CODE (operands[2]) == CONST_INT
677a9668 2488 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 2489 {
2490 HOST_WIDE_INT value = INTVAL (operands[2]);
677a9668 2491 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 2492 ? operands[0] : gen_reg_rtx (SImode));
2493
a260abc9
DE		 2494 emit_insn (gen_xorsi3 (tmp, operands[1],
2495 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2496 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 2497 DONE;
2498 }
1fd4e8c1
RK		 2499}")
2500
dfbdccdb 2501(define_insn "*boolsi3_internal1"
7cd5235b 2502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 2503 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 2504 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2505 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 2506 ""
2507 "@
dfbdccdb
GK		 2508 %q3 %0,%1,%2
2509 {%q3il|%q3i} %0,%1,%b2
2510 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 2511
dfbdccdb 2512(define_insn "*boolsi3_internal2"
52d3af72 2513 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 2514 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 2515 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2516 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2517 (const_int 0)))
52d3af72 2518 (clobber (match_scratch:SI 3 "=r,r"))]
0ad91047 2519 "! TARGET_POWERPC64"
52d3af72 2520 "@
dfbdccdb 2521 %q4. %3,%1,%2
52d3af72
DE		 2522 #"
2523 [(set_attr "type" "compare")
2524 (set_attr "length" "4,8")])
2525
2526(define_split
2527 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2528 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2529 [(match_operand:SI 1 "gpc_reg_operand" "")
2530 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2531 (const_int 0)))
52d3af72 2532 (clobber (match_scratch:SI 3 ""))]
0ad91047 2533 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2534 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2535 (set (match_dup 0)
2536 (compare:CC (match_dup 3)
2537 (const_int 0)))]
2538 "")
815cdc52 2539
dfbdccdb 2540(define_insn "*boolsi3_internal3"
52d3af72 2541 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2542 (compare:CC (match_operator:SI 4 "boolean_operator"
2543 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2544 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2545 (const_int 0)))
52d3af72 2546 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2547 (match_dup 4))]
0ad91047 2548 "! TARGET_POWERPC64"
52d3af72 2549 "@
dfbdccdb 2550 %q4. %0,%1,%2
52d3af72
DE		 2551 #"
2552 [(set_attr "type" "compare")
2553 (set_attr "length" "4,8")])
2554
2555(define_split
e72247f4 2556 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2557 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2558 [(match_operand:SI 1 "gpc_reg_operand" "")
2559 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2560 (const_int 0)))
75540af0 2561 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2562 (match_dup 4))]
0ad91047 2563 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2564 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2565 (set (match_dup 3)
2566 (compare:CC (match_dup 0)
2567 (const_int 0)))]
2568 "")
1fd4e8c1 2569
5bdc5878 2570;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 2571;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 2572
2573(define_split
2574 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 2575 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 2576 [(match_operand:SI 1 "gpc_reg_operand" "")
2577 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 2578 ""
dfbdccdb
GK		 2579 [(set (match_dup 0) (match_dup 4))
2580 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 2581"
2582{
dfbdccdb
GK		 2583 rtx i;
2584 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2585 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2586 operands[1], i);
2587 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2588 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2589 operands[0], i);
a260abc9
DE		 2590}")
2591
dfbdccdb 2592(define_insn "*boolcsi3_internal1"
cd2b37d9 2593 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 2594 (match_operator:SI 3 "boolean_operator"
2595 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 2596 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 2597 ""
dfbdccdb 2598 "%q3 %0,%2,%1")
1fd4e8c1 2599
dfbdccdb 2600(define_insn "*boolcsi3_internal2"
52d3af72 2601 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2602 (compare:CC (match_operator:SI 4 "boolean_operator"
2603 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2604 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2605 (const_int 0)))
52d3af72 2606 (clobber (match_scratch:SI 3 "=r,r"))]
0ad91047 2607 "! TARGET_POWERPC64"
52d3af72 2608 "@
dfbdccdb 2609 %q4. %3,%2,%1
52d3af72
DE		 2610 #"
2611 [(set_attr "type" "compare")
2612 (set_attr "length" "4,8")])
2613
2614(define_split
2615 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2616 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2617 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2618 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2619 (const_int 0)))
52d3af72 2620 (clobber (match_scratch:SI 3 ""))]
0ad91047 2621 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2622 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2623 (set (match_dup 0)
2624 (compare:CC (match_dup 3)
2625 (const_int 0)))]
2626 "")
1fd4e8c1 2627
dfbdccdb 2628(define_insn "*boolcsi3_internal3"
52d3af72 2629 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2630 (compare:CC (match_operator:SI 4 "boolean_operator"
2631 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2632 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2633 (const_int 0)))
52d3af72 2634 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2635 (match_dup 4))]
0ad91047 2636 "! TARGET_POWERPC64"
52d3af72 2637 "@
dfbdccdb 2638 %q4. %0,%2,%1
52d3af72
DE		 2639 #"
2640 [(set_attr "type" "compare")
2641 (set_attr "length" "4,8")])
2642
2643(define_split
e72247f4 2644 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2645 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2646 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2647 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2648 (const_int 0)))
75540af0 2649 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2650 (match_dup 4))]
0ad91047 2651 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2652 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2653 (set (match_dup 3)
2654 (compare:CC (match_dup 0)
2655 (const_int 0)))]
2656 "")
2657
dfbdccdb 2658(define_insn "*boolccsi3_internal1"
cd2b37d9 2659 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 2660 (match_operator:SI 3 "boolean_operator"
2661 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 2662 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 2663 ""
dfbdccdb 2664 "%q3 %0,%1,%2")
1fd4e8c1 2665
dfbdccdb 2666(define_insn "*boolccsi3_internal2"
52d3af72 2667 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2668 (compare:CC (match_operator:SI 4 "boolean_operator"
2669 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2670 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2671 (const_int 0)))
52d3af72 2672 (clobber (match_scratch:SI 3 "=r,r"))]
0ad91047 2673 "! TARGET_POWERPC64"
52d3af72 2674 "@
dfbdccdb 2675 %q4. %3,%1,%2
52d3af72
DE		 2676 #"
2677 [(set_attr "type" "compare")
2678 (set_attr "length" "4,8")])
2679
2680(define_split
2681 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2682 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2683 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2684 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 2685 (const_int 0)))
52d3af72 2686 (clobber (match_scratch:SI 3 ""))]
0ad91047 2687 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2688 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2689 (set (match_dup 0)
2690 (compare:CC (match_dup 3)
2691 (const_int 0)))]
2692 "")
1fd4e8c1 2693
dfbdccdb 2694(define_insn "*boolccsi3_internal3"
52d3af72 2695 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2696 (compare:CC (match_operator:SI 4 "boolean_operator"
2697 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2698 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2699 (const_int 0)))
52d3af72 2700 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2701 (match_dup 4))]
0ad91047 2702 "! TARGET_POWERPC64"
52d3af72 2703 "@
dfbdccdb 2704 %q4. %0,%1,%2
52d3af72
DE		 2705 #"
2706 [(set_attr "type" "compare")
2707 (set_attr "length" "4,8")])
2708
2709(define_split
e72247f4 2710 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2711 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2712 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2713 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 2714 (const_int 0)))
75540af0 2715 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2716 (match_dup 4))]
0ad91047 2717 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2718 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2719 (set (match_dup 3)
2720 (compare:CC (match_dup 0)
2721 (const_int 0)))]
2722 "")
1fd4e8c1
RK		 2723
2724;; maskir insn. We need four forms because things might be in arbitrary
2725;; orders. Don't define forms that only set CR fields because these
2726;; would modify an input register.
2727
7cd5235b 2728(define_insn "*maskir_internal1"
cd2b37d9 2729 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 2730 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2731 (match_operand:SI 1 "gpc_reg_operand" "0"))
2732 (and:SI (match_dup 2)
cd2b37d9 2733 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 2734 "TARGET_POWER"
01def764 2735 "maskir %0,%3,%2")
1fd4e8c1 2736
7cd5235b 2737(define_insn "*maskir_internal2"
242e8072 2738 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 2739 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2740 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 2741 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 2742 (match_dup 2))))]
ca7f5001 2743 "TARGET_POWER"
01def764 2744 "maskir %0,%3,%2")
1fd4e8c1 2745
7cd5235b 2746(define_insn "*maskir_internal3"
cd2b37d9 2747 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 2748 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 2749 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 2750 (and:SI (not:SI (match_dup 2))
2751 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 2752 "TARGET_POWER"
01def764 2753 "maskir %0,%3,%2")
1fd4e8c1 2754
7cd5235b 2755(define_insn "*maskir_internal4"
cd2b37d9
RK		 2756 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2757 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 2758 (match_operand:SI 2 "gpc_reg_operand" "r"))
2759 (and:SI (not:SI (match_dup 2))
2760 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 2761 "TARGET_POWER"
01def764 2762 "maskir %0,%3,%2")
1fd4e8c1 2763
7cd5235b 2764(define_insn "*maskir_internal5"
9ebbca7d 2765 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2766 (compare:CC
9ebbca7d
GK		 2767 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2768 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 2769 (and:SI (match_dup 2)
9ebbca7d 2770 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 2771 (const_int 0)))
9ebbca7d 2772 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2773 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2774 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 2775 "TARGET_POWER"
9ebbca7d
GK		 2776 "@
2777 maskir. %0,%3,%2
2778 #"
2779 [(set_attr "type" "compare")
2780 (set_attr "length" "4,8")])
2781
2782(define_split
2783 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2784 (compare:CC
2785 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2786 (match_operand:SI 1 "gpc_reg_operand" ""))
2787 (and:SI (match_dup 2)
2788 (match_operand:SI 3 "gpc_reg_operand" "")))
2789 (const_int 0)))
2790 (set (match_operand:SI 0 "gpc_reg_operand" "")
2791 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2792 (and:SI (match_dup 2) (match_dup 3))))]
2793 "TARGET_POWER && reload_completed"
2794 [(set (match_dup 0)
2795 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2796 (and:SI (match_dup 2) (match_dup 3))))
2797 (set (match_dup 4)
2798 (compare:CC (match_dup 0)
2799 (const_int 0)))]
2800 "")
1fd4e8c1 2801
7cd5235b 2802(define_insn "*maskir_internal6"
9ebbca7d 2803 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2804 (compare:CC
9ebbca7d
GK		 2805 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2806 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2807 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 2808 (match_dup 2)))
1fd4e8c1 2809 (const_int 0)))
9ebbca7d 2810 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2811 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2812 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 2813 "TARGET_POWER"
9ebbca7d
GK		 2814 "@
2815 maskir. %0,%3,%2
2816 #"
2817 [(set_attr "type" "compare")
2818 (set_attr "length" "4,8")])
2819
2820(define_split
2821 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2822 (compare:CC
2823 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2824 (match_operand:SI 1 "gpc_reg_operand" ""))
2825 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2826 (match_dup 2)))
2827 (const_int 0)))
2828 (set (match_operand:SI 0 "gpc_reg_operand" "")
2829 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2830 (and:SI (match_dup 3) (match_dup 2))))]
2831 "TARGET_POWER && reload_completed"
2832 [(set (match_dup 0)
2833 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2834 (and:SI (match_dup 3) (match_dup 2))))
2835 (set (match_dup 4)
2836 (compare:CC (match_dup 0)
2837 (const_int 0)))]
2838 "")
1fd4e8c1 2839
7cd5235b 2840(define_insn "*maskir_internal7"
9ebbca7d 2841 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 2842 (compare:CC
9ebbca7d
GK		 2843 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2844 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 2845 (and:SI (not:SI (match_dup 2))
9ebbca7d 2846 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 2847 (const_int 0)))
9ebbca7d 2848 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 2849 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2850 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2851 "TARGET_POWER"
9ebbca7d
GK		 2852 "@
2853 maskir. %0,%3,%2
2854 #"
2855 [(set_attr "type" "compare")
2856 (set_attr "length" "4,8")])
2857
2858(define_split
2859 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2860 (compare:CC
2861 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2862 (match_operand:SI 3 "gpc_reg_operand" ""))
2863 (and:SI (not:SI (match_dup 2))
2864 (match_operand:SI 1 "gpc_reg_operand" "")))
2865 (const_int 0)))
2866 (set (match_operand:SI 0 "gpc_reg_operand" "")
2867 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2868 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2869 "TARGET_POWER && reload_completed"
2870 [(set (match_dup 0)
2871 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2872 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2873 (set (match_dup 4)
2874 (compare:CC (match_dup 0)
2875 (const_int 0)))]
2876 "")
1fd4e8c1 2877
7cd5235b 2878(define_insn "*maskir_internal8"
9ebbca7d 2879 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2880 (compare:CC
9ebbca7d
GK		 2881 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2882 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 2883 (and:SI (not:SI (match_dup 2))
9ebbca7d 2884 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 2885 (const_int 0)))
9ebbca7d 2886 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2887 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2888 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 2889 "TARGET_POWER"
9ebbca7d
GK		 2890 "@
2891 maskir. %0,%3,%2
2892 #"
2893 [(set_attr "type" "compare")
2894 (set_attr "length" "4,8")])
fcce224d 2895
9ebbca7d
GK		 2896(define_split
2897 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2898 (compare:CC
2899 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2900 (match_operand:SI 2 "gpc_reg_operand" ""))
2901 (and:SI (not:SI (match_dup 2))
2902 (match_operand:SI 1 "gpc_reg_operand" "")))
2903 (const_int 0)))
2904 (set (match_operand:SI 0 "gpc_reg_operand" "")
2905 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2906 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2907 "TARGET_POWER && reload_completed"
2908 [(set (match_dup 0)
2909 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2910 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2911 (set (match_dup 4)
2912 (compare:CC (match_dup 0)
2913 (const_int 0)))]
2914 "")
fcce224d 2915\f
1fd4e8c1
RK		 2916;; Rotate and shift insns, in all their variants. These support shifts,
2917;; field inserts and extracts, and various combinations thereof.
034c1be0 2918(define_expand "insv"
0ad91047
DE		 2919 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2920 (match_operand:SI 1 "const_int_operand" "")
2921 (match_operand:SI 2 "const_int_operand" ""))
2922 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 2923 ""
2924 "
2925{
2926 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2927 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2928 compiler if the address of the structure is taken later. */
2929 if (GET_CODE (operands[0]) == SUBREG
2930 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2931 FAIL;
a78e33fc
DE		 2932
2933 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2934 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2935 else
2936 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2937 DONE;
034c1be0
MM		 2938}")
2939
a78e33fc 2940(define_insn "insvsi"
cd2b37d9 2941 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 2942 (match_operand:SI 1 "const_int_operand" "i")
2943 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 2944 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 2945 ""
2946 "*
2947{
2948 int start = INTVAL (operands[2]) & 31;
2949 int size = INTVAL (operands[1]) & 31;
2950
89e9f3a8
MM		 2951 operands[4] = GEN_INT (32 - start - size);
2952 operands[1] = GEN_INT (start + size - 1);
a66078ee 2953 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 2954}"
2955 [(set_attr "type" "insert_word")])
1fd4e8c1 2956
a78e33fc 2957(define_insn "*insvsi_internal1"
d56d506a
RK		 2958 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2959 (match_operand:SI 1 "const_int_operand" "i")
2960 (match_operand:SI 2 "const_int_operand" "i"))
2961 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2962 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 2963 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 2964 "*
2965{
2966 int shift = INTVAL (operands[4]) & 31;
2967 int start = INTVAL (operands[2]) & 31;
2968 int size = INTVAL (operands[1]) & 31;
2969
89e9f3a8
MM		 2970 operands[4] = GEN_INT (shift - start - size);
2971 operands[1] = GEN_INT (start + size - 1);
a66078ee 2972 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 2973}"
2974 [(set_attr "type" "insert_word")])
d56d506a 2975
a78e33fc 2976(define_insn "*insvsi_internal2"
d56d506a
RK		 2977 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2978 (match_operand:SI 1 "const_int_operand" "i")
2979 (match_operand:SI 2 "const_int_operand" "i"))
2980 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2981 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 2982 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 2983 "*
2984{
2985 int shift = INTVAL (operands[4]) & 31;
2986 int start = INTVAL (operands[2]) & 31;
2987 int size = INTVAL (operands[1]) & 31;
2988
89e9f3a8
MM		 2989 operands[4] = GEN_INT (32 - shift - start - size);
2990 operands[1] = GEN_INT (start + size - 1);
a66078ee 2991 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 2992}"
2993 [(set_attr "type" "insert_word")])
d56d506a 2994
a78e33fc 2995(define_insn "*insvsi_internal3"
d56d506a
RK		 2996 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2997 (match_operand:SI 1 "const_int_operand" "i")
2998 (match_operand:SI 2 "const_int_operand" "i"))
2999 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3000 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 3001 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3002 "*
3003{
3004 int shift = INTVAL (operands[4]) & 31;
3005 int start = INTVAL (operands[2]) & 31;
3006 int size = INTVAL (operands[1]) & 31;
3007
89e9f3a8
MM		 3008 operands[4] = GEN_INT (32 - shift - start - size);
3009 operands[1] = GEN_INT (start + size - 1);
a66078ee 3010 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3011}"
3012 [(set_attr "type" "insert_word")])
d56d506a 3013
a78e33fc 3014(define_insn "*insvsi_internal4"
d56d506a
RK		 3015 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3016 (match_operand:SI 1 "const_int_operand" "i")
3017 (match_operand:SI 2 "const_int_operand" "i"))
3018 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3019 (match_operand:SI 4 "const_int_operand" "i")
3020 (match_operand:SI 5 "const_int_operand" "i")))]
3021 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3022 "*
3023{
3024 int extract_start = INTVAL (operands[5]) & 31;
3025 int extract_size = INTVAL (operands[4]) & 31;
3026 int insert_start = INTVAL (operands[2]) & 31;
3027 int insert_size = INTVAL (operands[1]) & 31;
3028
3029/* Align extract field with insert field */
3a598fbe 3030 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3031 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3032 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 3033}"
3034 [(set_attr "type" "insert_word")])
d56d506a 3035
a78e33fc 3036(define_insn "insvdi"
685f3906 3037 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3038 (match_operand:SI 1 "const_int_operand" "i")
3039 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3040 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3041 "TARGET_POWERPC64"
3042 "*
3043{
3044 int start = INTVAL (operands[2]) & 63;
3045 int size = INTVAL (operands[1]) & 63;
3046
a78e33fc
DE		 3047 operands[1] = GEN_INT (64 - start - size);
3048 return \"rldimi %0,%3,%H1,%H2\";
685f3906
DE		 3049}")
3050
034c1be0 3051(define_expand "extzv"
0ad91047
DE		 3052 [(set (match_operand 0 "gpc_reg_operand" "")
3053 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3054 (match_operand:SI 2 "const_int_operand" "")
3055 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3056 ""
3057 "
3058{
3059 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3060 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3061 compiler if the address of the structure is taken later. */
3062 if (GET_CODE (operands[0]) == SUBREG
3063 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3064 FAIL;
a78e33fc
DE		 3065
3066 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3067 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3068 else
3069 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3070 DONE;
034c1be0
MM		 3071}")
3072
a78e33fc 3073(define_insn "extzvsi"
cd2b37d9
RK		 3074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3075 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3076 (match_operand:SI 2 "const_int_operand" "i")
3077 (match_operand:SI 3 "const_int_operand" "i")))]
3078 ""
3079 "*
3080{
3081 int start = INTVAL (operands[3]) & 31;
3082 int size = INTVAL (operands[2]) & 31;
3083
3084 if (start + size >= 32)
3085 operands[3] = const0_rtx;
3086 else
89e9f3a8 3087 operands[3] = GEN_INT (start + size);
ca7f5001 3088 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3089}")
3090
a78e33fc 3091(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3092 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3093 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3094 (match_operand:SI 2 "const_int_operand" "i,i")
3095 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3096 (const_int 0)))
9ebbca7d 3097 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3098 ""
1fd4e8c1
RK		 3099 "*
3100{
3101 int start = INTVAL (operands[3]) & 31;
3102 int size = INTVAL (operands[2]) & 31;
3103
9ebbca7d
GK		 3104 /* Force split for non-cc0 compare. */
3105 if (which_alternative == 1)
3106 return \"#\";
3107
43a88a8c 3108 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3109 word, it is possible to use andiu. or andil. to test it. This is
3110 useful because the condition register set-use delay is smaller for
3111 andi[ul]. than for rlinm. This doesn't work when the starting bit
3112 position is 0 because the LT and GT bits may be set wrong. */
3113
3114 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3115 {
3a598fbe 3116 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3117 - (1 << (16 - (start & 15) - size))));
3118 if (start < 16)
ca7f5001 3119 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3120 else
ca7f5001 3121 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3122 }
7e69e155 3123
1fd4e8c1
RK		 3124 if (start + size >= 32)
3125 operands[3] = const0_rtx;
3126 else
89e9f3a8 3127 operands[3] = GEN_INT (start + size);
ca7f5001 3128 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3129}"
9ebbca7d
GK		 3130 [(set_attr "type" "compare")
3131 (set_attr "length" "4,8")])
3132
3133(define_split
3134 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3135 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3136 (match_operand:SI 2 "const_int_operand" "")
3137 (match_operand:SI 3 "const_int_operand" ""))
3138 (const_int 0)))
3139 (clobber (match_scratch:SI 4 ""))]
ce71f754 3140 "reload_completed"
9ebbca7d
GK		 3141 [(set (match_dup 4)
3142 (zero_extract:SI (match_dup 1) (match_dup 2)
3143 (match_dup 3)))
3144 (set (match_dup 0)
3145 (compare:CC (match_dup 4)
3146 (const_int 0)))]
3147 "")
1fd4e8c1 3148
a78e33fc 3149(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3150 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3151 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3152 (match_operand:SI 2 "const_int_operand" "i,i")
3153 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3154 (const_int 0)))
9ebbca7d 3155 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3156 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3157 ""
1fd4e8c1
RK		 3158 "*
3159{
3160 int start = INTVAL (operands[3]) & 31;
3161 int size = INTVAL (operands[2]) & 31;
3162
9ebbca7d
GK		 3163 /* Force split for non-cc0 compare. */
3164 if (which_alternative == 1)
3165 return \"#\";
3166
bc401279 3167 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3168 a shift. The bit-field must end at the LSB. */
bc401279 3169 if (start >= 16 && start + size == 32)
df031c43 3170 {
bc401279
AM		 3171 operands[3] = GEN_INT ((1 << size) - 1);
3172 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3173 }
7e69e155 3174
1fd4e8c1
RK		 3175 if (start + size >= 32)
3176 operands[3] = const0_rtx;
3177 else
89e9f3a8 3178 operands[3] = GEN_INT (start + size);
ca7f5001 3179 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3180}"
ce71f754 3181 [(set_attr "type" "compare")
9ebbca7d
GK		 3182 (set_attr "length" "4,8")])
3183
3184(define_split
3185 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3186 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3187 (match_operand:SI 2 "const_int_operand" "")
3188 (match_operand:SI 3 "const_int_operand" ""))
3189 (const_int 0)))
3190 (set (match_operand:SI 0 "gpc_reg_operand" "")
3191 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3192 "reload_completed"
9ebbca7d
GK		 3193 [(set (match_dup 0)
3194 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3195 (set (match_dup 4)
3196 (compare:CC (match_dup 0)
3197 (const_int 0)))]
3198 "")
1fd4e8c1 3199
a78e33fc 3200(define_insn "extzvdi"
685f3906
DE		 3201 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3202 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3203 (match_operand:SI 2 "const_int_operand" "i")
3204 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3205 "TARGET_POWERPC64"
3206 "*
3207{
3208 int start = INTVAL (operands[3]) & 63;
3209 int size = INTVAL (operands[2]) & 63;
3210
3211 if (start + size >= 64)
3212 operands[3] = const0_rtx;
3213 else
89e9f3a8
MM		 3214 operands[3] = GEN_INT (start + size);
3215 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3216 return \"rldicl %0,%1,%3,%2\";
3217}")
3218
a78e33fc 3219(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3220 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3221 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3222 (match_operand:SI 2 "const_int_operand" "i")
3223 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3224 (const_int 0)))
29ae5b89 3225 (clobber (match_scratch:DI 4 "=r"))]
683bdff7 3226 "TARGET_64BIT"
685f3906
DE		 3227 "*
3228{
3229 int start = INTVAL (operands[3]) & 63;
3230 int size = INTVAL (operands[2]) & 63;
3231
3232 if (start + size >= 64)
3233 operands[3] = const0_rtx;
3234 else
89e9f3a8
MM		 3235 operands[3] = GEN_INT (start + size);
3236 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3237 return \"rldicl. %4,%1,%3,%2\";
3238}")
3239
a78e33fc 3240(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3241 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3242 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3243 (match_operand:SI 2 "const_int_operand" "i")
3244 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3245 (const_int 0)))
29ae5b89 3246 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3247 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
683bdff7 3248 "TARGET_64BIT"
685f3906
DE		 3249 "*
3250{
3251 int start = INTVAL (operands[3]) & 63;
3252 int size = INTVAL (operands[2]) & 63;
3253
3254 if (start + size >= 64)
3255 operands[3] = const0_rtx;
3256 else
89e9f3a8
MM		 3257 operands[3] = GEN_INT (start + size);
3258 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3259 return \"rldicl. %0,%1,%3,%2\";
3260}")
3261
1fd4e8c1 3262(define_insn "rotlsi3"
cd2b37d9
RK		 3263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3264 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3265 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3266 ""
ca7f5001 3267 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
1fd4e8c1 3268
a260abc9 3269(define_insn "*rotlsi3_internal2"
9ebbca7d
GK		 3270 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3271 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3272 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
1fd4e8c1 3273 (const_int 0)))
9ebbca7d 3274 (clobber (match_scratch:SI 3 "=r,r"))]
ce71f754 3275 ""
9ebbca7d
GK		 3276 "@
3277 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3278 #"
3279 [(set_attr "type" "delayed_compare")
3280 (set_attr "length" "4,8")])
3281
3282(define_split
3283 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3284 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3285 (match_operand:SI 2 "reg_or_cint_operand" ""))
3286 (const_int 0)))
3287 (clobber (match_scratch:SI 3 ""))]
ce71f754 3288 "reload_completed"
9ebbca7d
GK		 3289 [(set (match_dup 3)
3290 (rotate:SI (match_dup 1) (match_dup 2)))
3291 (set (match_dup 0)
3292 (compare:CC (match_dup 3)
3293 (const_int 0)))]
3294 "")
1fd4e8c1 3295
a260abc9 3296(define_insn "*rotlsi3_internal3"
9ebbca7d
GK		 3297 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3298 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3299 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
1fd4e8c1 3300 (const_int 0)))
9ebbca7d 3301 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3302 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3303 ""
9ebbca7d
GK		 3304 "@
3305 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3306 #"
3307 [(set_attr "type" "delayed_compare")
3308 (set_attr "length" "4,8")])
3309
3310(define_split
3311 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3312 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3313 (match_operand:SI 2 "reg_or_cint_operand" ""))
3314 (const_int 0)))
3315 (set (match_operand:SI 0 "gpc_reg_operand" "")
3316 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3317 "reload_completed"
9ebbca7d
GK		 3318 [(set (match_dup 0)
3319 (rotate:SI (match_dup 1) (match_dup 2)))
3320 (set (match_dup 3)
3321 (compare:CC (match_dup 0)
3322 (const_int 0)))]
3323 "")
1fd4e8c1 3324
a260abc9 3325(define_insn "*rotlsi3_internal4"
cd2b37d9
RK		 3326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3327 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3328 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
ce71f754 3329 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3330 ""
ca7f5001 3331 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
1fd4e8c1 3332
a260abc9 3333(define_insn "*rotlsi3_internal5"
9ebbca7d 3334 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3335 (compare:CC (and:SI
9ebbca7d
GK		 3336 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3337 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 3338 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3339 (const_int 0)))
9ebbca7d 3340 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3341 ""
9ebbca7d
GK		 3342 "@
3343 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3344 #"
3345 [(set_attr "type" "delayed_compare")
3346 (set_attr "length" "4,8")])
3347
3348(define_split
3349 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3350 (compare:CC (and:SI
3351 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3352 (match_operand:SI 2 "reg_or_cint_operand" ""))
3353 (match_operand:SI 3 "mask_operand" ""))
3354 (const_int 0)))
3355 (clobber (match_scratch:SI 4 ""))]
ce71f754 3356 "reload_completed"
9ebbca7d
GK		 3357 [(set (match_dup 4)
3358 (and:SI (rotate:SI (match_dup 1)
3359 (match_dup 2))
3360 (match_dup 3)))
3361 (set (match_dup 0)
3362 (compare:CC (match_dup 4)
3363 (const_int 0)))]
3364 "")
1fd4e8c1 3365
a260abc9 3366(define_insn "*rotlsi3_internal6"
9ebbca7d 3367 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3368 (compare:CC (and:SI
9ebbca7d
GK		 3369 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3370 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 3371 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3372 (const_int 0)))
9ebbca7d 3373 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3374 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3375 ""
9ebbca7d
GK		 3376 "@
3377 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3378 #"
3379 [(set_attr "type" "delayed_compare")
3380 (set_attr "length" "4,8")])
3381
3382(define_split
3383 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3384 (compare:CC (and:SI
3385 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3386 (match_operand:SI 2 "reg_or_cint_operand" ""))
3387 (match_operand:SI 3 "mask_operand" ""))
3388 (const_int 0)))
3389 (set (match_operand:SI 0 "gpc_reg_operand" "")
3390 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3391 "reload_completed"
9ebbca7d
GK		 3392 [(set (match_dup 0)
3393 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3394 (set (match_dup 4)
3395 (compare:CC (match_dup 0)
3396 (const_int 0)))]
3397 "")
1fd4e8c1 3398
a260abc9 3399(define_insn "*rotlsi3_internal7"
cd2b37d9 3400 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 3401 (zero_extend:SI
3402 (subreg:QI
cd2b37d9 3403 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3404 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3405 ""
ca7f5001 3406 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1 3407
a260abc9 3408(define_insn "*rotlsi3_internal8"
9ebbca7d 3409 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3410 (compare:CC (zero_extend:SI
3411 (subreg:QI
9ebbca7d
GK		 3412 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3413 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3414 (const_int 0)))
9ebbca7d 3415 (clobber (match_scratch:SI 3 "=r,r"))]
1fd4e8c1 3416 ""
9ebbca7d
GK		 3417 "@
3418 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3419 #"
3420 [(set_attr "type" "delayed_compare")
3421 (set_attr "length" "4,8")])
3422
3423(define_split
3424 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3425 (compare:CC (zero_extend:SI
3426 (subreg:QI
3427 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3428 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3429 (const_int 0)))
3430 (clobber (match_scratch:SI 3 ""))]
3431 "reload_completed"
3432 [(set (match_dup 3)
3433 (zero_extend:SI (subreg:QI
3434 (rotate:SI (match_dup 1)
3435 (match_dup 2)) 0)))
3436 (set (match_dup 0)
3437 (compare:CC (match_dup 3)
3438 (const_int 0)))]
3439 "")
1fd4e8c1 3440
a260abc9 3441(define_insn "*rotlsi3_internal9"
9ebbca7d 3442 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3443 (compare:CC (zero_extend:SI
3444 (subreg:QI
9ebbca7d
GK		 3445 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3446 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3447 (const_int 0)))
9ebbca7d 3448 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 3449 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3450 ""
9ebbca7d
GK		 3451 "@
3452 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3453 #"
3454 [(set_attr "type" "delayed_compare")
3455 (set_attr "length" "4,8")])
3456
3457(define_split
3458 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3459 (compare:CC (zero_extend:SI
3460 (subreg:QI
3461 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3462 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3463 (const_int 0)))
3464 (set (match_operand:SI 0 "gpc_reg_operand" "")
3465 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3466 "reload_completed"
3467 [(set (match_dup 0)
3468 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3469 (set (match_dup 3)
3470 (compare:CC (match_dup 0)
3471 (const_int 0)))]
3472 "")
1fd4e8c1 3473
a260abc9 3474(define_insn "*rotlsi3_internal10"
cd2b37d9 3475 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 3476 (zero_extend:SI
3477 (subreg:HI
cd2b37d9 3478 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3479 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3480 ""
ca7f5001 3481 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
1fd4e8c1 3482
a260abc9 3483(define_insn "*rotlsi3_internal11"
9ebbca7d 3484 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3485 (compare:CC (zero_extend:SI
3486 (subreg:HI
9ebbca7d
GK		 3487 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3488 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3489 (const_int 0)))
9ebbca7d 3490 (clobber (match_scratch:SI 3 "=r,r"))]
1fd4e8c1 3491 ""
9ebbca7d
GK		 3492 "@
3493 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3494 #"
3495 [(set_attr "type" "delayed_compare")
3496 (set_attr "length" "4,8")])
3497
3498(define_split
3499 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3500 (compare:CC (zero_extend:SI
3501 (subreg:HI
3502 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3503 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3504 (const_int 0)))
3505 (clobber (match_scratch:SI 3 ""))]
3506 "reload_completed"
3507 [(set (match_dup 3)
3508 (zero_extend:SI (subreg:HI
3509 (rotate:SI (match_dup 1)
3510 (match_dup 2)) 0)))
3511 (set (match_dup 0)
3512 (compare:CC (match_dup 3)
3513 (const_int 0)))]
3514 "")
1fd4e8c1 3515
a260abc9 3516(define_insn "*rotlsi3_internal12"
9ebbca7d 3517 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3518 (compare:CC (zero_extend:SI
3519 (subreg:HI
9ebbca7d
GK		 3520 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3521 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3522 (const_int 0)))
9ebbca7d 3523 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 3524 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3525 ""
9ebbca7d
GK		 3526 "@
3527 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3528 #"
3529 [(set_attr "type" "delayed_compare")
3530 (set_attr "length" "4,8")])
3531
3532(define_split
3533 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3534 (compare:CC (zero_extend:SI
3535 (subreg:HI
3536 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3537 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3538 (const_int 0)))
3539 (set (match_operand:SI 0 "gpc_reg_operand" "")
3540 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3541 "reload_completed"
3542 [(set (match_dup 0)
3543 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3544 (set (match_dup 3)
3545 (compare:CC (match_dup 0)
3546 (const_int 0)))]
3547 "")
1fd4e8c1
RK		 3548
3549;; Note that we use "sle." instead of "sl." so that we can set
3550;; SHIFT_COUNT_TRUNCATED.
3551
ca7f5001
RK		 3552(define_expand "ashlsi3"
3553 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3554 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3555 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3556 ""
3557 "
3558{
3559 if (TARGET_POWER)
3560 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3561 else
25c341fa 3562 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 3563 DONE;
3564}")
3565
3566(define_insn "ashlsi3_power"
cd2b37d9
RK		 3567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3568 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 3569 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3570 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 3571 "TARGET_POWER"
1fd4e8c1
RK		 3572 "@
3573 sle %0,%1,%2
9ebbca7d 3574 {sli|slwi} %0,%1,%h2")
ca7f5001 3575
25c341fa 3576(define_insn "ashlsi3_no_power"
ca7f5001
RK		 3577 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3578 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3579 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 3580 "! TARGET_POWER"
9ebbca7d 3581 "{sl|slw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 3582
3583(define_insn ""
9ebbca7d
GK		 3584 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3585 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3586 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3587 (const_int 0)))
9ebbca7d
GK		 3588 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3589 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 3590 "TARGET_POWER"
1fd4e8c1
RK		 3591 "@
3592 sle. %3,%1,%2
9ebbca7d
GK		 3593 {sli.|slwi.} %3,%1,%h2
3594 #
3595 #"
3596 [(set_attr "type" "delayed_compare")
3597 (set_attr "length" "4,4,8,8")])
3598
3599(define_split
3600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3601 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3602 (match_operand:SI 2 "reg_or_cint_operand" ""))
3603 (const_int 0)))
3604 (clobber (match_scratch:SI 3 ""))
3605 (clobber (match_scratch:SI 4 ""))]
3606 "TARGET_POWER && reload_completed"
3607 [(parallel [(set (match_dup 3)
3608 (ashift:SI (match_dup 1) (match_dup 2)))
3609 (clobber (match_dup 4))])
3610 (set (match_dup 0)
3611 (compare:CC (match_dup 3)
3612 (const_int 0)))]
3613 "")
25c341fa 3614
ca7f5001 3615(define_insn ""
9ebbca7d
GK		 3616 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3617 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3618 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 3619 (const_int 0)))
9ebbca7d 3620 (clobber (match_scratch:SI 3 "=r,r"))]
0ad91047 3621 "! TARGET_POWER && ! TARGET_POWERPC64"
9ebbca7d
GK		 3622 "@
3623 {sl|slw}%I2. %3,%1,%h2
3624 #"
3625 [(set_attr "type" "delayed_compare")
3626 (set_attr "length" "4,8")])
3627
3628(define_split
3629 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3630 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3631 (match_operand:SI 2 "reg_or_cint_operand" ""))
3632 (const_int 0)))
3633 (clobber (match_scratch:SI 3 ""))]
3634 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3635 [(set (match_dup 3)
3636 (ashift:SI (match_dup 1) (match_dup 2)))
3637 (set (match_dup 0)
3638 (compare:CC (match_dup 3)
3639 (const_int 0)))]
3640 "")
1fd4e8c1
RK		 3641
3642(define_insn ""
9ebbca7d
GK		 3643 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3644 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3645 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3646 (const_int 0)))
9ebbca7d 3647 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3648 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 3649 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 3650 "TARGET_POWER"
1fd4e8c1
RK		 3651 "@
3652 sle. %0,%1,%2
9ebbca7d
GK		 3653 {sli.|slwi.} %0,%1,%h2
3654 #
3655 #"
3656 [(set_attr "type" "delayed_compare")
3657 (set_attr "length" "4,4,8,8")])
3658
3659(define_split
3660 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3661 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3662 (match_operand:SI 2 "reg_or_cint_operand" ""))
3663 (const_int 0)))
3664 (set (match_operand:SI 0 "gpc_reg_operand" "")
3665 (ashift:SI (match_dup 1) (match_dup 2)))
3666 (clobber (match_scratch:SI 4 ""))]
3667 "TARGET_POWER && reload_completed"
3668 [(parallel [(set (match_dup 0)
3669 (ashift:SI (match_dup 1) (match_dup 2)))
3670 (clobber (match_dup 4))])
3671 (set (match_dup 3)
3672 (compare:CC (match_dup 0)
3673 (const_int 0)))]
3674 "")
25c341fa 3675
ca7f5001 3676(define_insn ""
9ebbca7d
GK		 3677 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3678 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3679 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 3680 (const_int 0)))
9ebbca7d 3681 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 3682 (ashift:SI (match_dup 1) (match_dup 2)))]
0ad91047 3683 "! TARGET_POWER && ! TARGET_POWERPC64"
9ebbca7d
GK		 3684 "@
3685 {sl|slw}%I2. %0,%1,%h2
3686 #"
3687 [(set_attr "type" "delayed_compare")
3688 (set_attr "length" "4,8")])
3689
3690(define_split
3691 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3692 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3693 (match_operand:SI 2 "reg_or_cint_operand" ""))
3694 (const_int 0)))
3695 (set (match_operand:SI 0 "gpc_reg_operand" "")
3696 (ashift:SI (match_dup 1) (match_dup 2)))]
3697 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3698 [(set (match_dup 0)
3699 (ashift:SI (match_dup 1) (match_dup 2)))
3700 (set (match_dup 3)
3701 (compare:CC (match_dup 0)
3702 (const_int 0)))]
3703 "")
1fd4e8c1
RK		 3704
3705(define_insn ""
cd2b37d9
RK		 3706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3707 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3708 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 3709 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3710 "includes_lshift_p (operands[2], operands[3])"
d56d506a 3711 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 3712
3713(define_insn ""
9ebbca7d 3714 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3715 (compare:CC
9ebbca7d
GK		 3716 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3717 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3718 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3719 (const_int 0)))
9ebbca7d 3720 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3721 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3722 "@
3723 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3724 #"
3725 [(set_attr "type" "delayed_compare")
3726 (set_attr "length" "4,8")])
3727
3728(define_split
3729 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3730 (compare:CC
3731 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3732 (match_operand:SI 2 "const_int_operand" ""))
3733 (match_operand:SI 3 "mask_operand" ""))
3734 (const_int 0)))
3735 (clobber (match_scratch:SI 4 ""))]
ce71f754 3736 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3737 [(set (match_dup 4)
3738 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3739 (match_dup 3)))
3740 (set (match_dup 0)
3741 (compare:CC (match_dup 4)
3742 (const_int 0)))]
3743 "")
1fd4e8c1
RK		 3744
3745(define_insn ""
9ebbca7d 3746 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3747 (compare:CC
9ebbca7d
GK		 3748 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3749 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3750 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3751 (const_int 0)))
9ebbca7d 3752 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3753 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3754 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3755 "@
3756 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3757 #"
3758 [(set_attr "type" "delayed_compare")
3759 (set_attr "length" "4,8")])
3760
3761(define_split
3762 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3763 (compare:CC
3764 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3765 (match_operand:SI 2 "const_int_operand" ""))
3766 (match_operand:SI 3 "mask_operand" ""))
3767 (const_int 0)))
3768 (set (match_operand:SI 0 "gpc_reg_operand" "")
3769 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3770 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3771 [(set (match_dup 0)
3772 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3773 (set (match_dup 4)
3774 (compare:CC (match_dup 0)
3775 (const_int 0)))]
3776 "")
1fd4e8c1 3777
ca7f5001 3778;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 3779;; "sli x,x,0".
ca7f5001
RK		 3780(define_expand "lshrsi3"
3781 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3782 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3783 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3784 ""
3785 "
3786{
3787 if (TARGET_POWER)
3788 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3789 else
25c341fa 3790 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 3791 DONE;
3792}")
3793
3794(define_insn "lshrsi3_power"
bdf423cb
MM		 3795 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3796 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3797 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3798 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 3799 "TARGET_POWER"
1fd4e8c1
RK		 3800 "@
3801 sre %0,%1,%2
bdf423cb 3802 mr %0,%1
ca7f5001
RK		 3803 {s%A2i|s%A2wi} %0,%1,%h2")
3804
25c341fa 3805(define_insn "lshrsi3_no_power"
bdf423cb
MM		 3806 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3807 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3808 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
25c341fa 3809 "! TARGET_POWER"
bdf423cb
MM		 3810 "@
3811 mr %0,%1
3812 {sr|srw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 3813
3814(define_insn ""
9ebbca7d
GK		 3815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3816 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3817 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 3818 (const_int 0)))
9ebbca7d
GK		 3819 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3820 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 3821 "TARGET_POWER"
1fd4e8c1 3822 "@
29ae5b89
JL		 3823 sre. %3,%1,%2
3824 mr. %1,%1
9ebbca7d
GK		 3825 {s%A2i.|s%A2wi.} %3,%1,%h2
3826 #
3827 #
3828 #"
3829 [(set_attr "type" "delayed_compare")
3830 (set_attr "length" "4,4,4,8,8,8")])
3831
3832(define_split
3833 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3834 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3835 (match_operand:SI 2 "reg_or_cint_operand" ""))
3836 (const_int 0)))
3837 (clobber (match_scratch:SI 3 ""))
3838 (clobber (match_scratch:SI 4 ""))]
3839 "TARGET_POWER && reload_completed"
3840 [(parallel [(set (match_dup 3)
3841 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3842 (clobber (match_dup 4))])
3843 (set (match_dup 0)
3844 (compare:CC (match_dup 3)
3845 (const_int 0)))]
3846 "")
ca7f5001
RK		 3847
3848(define_insn ""
9ebbca7d
GK		 3849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3850 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3851 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
ca7f5001 3852 (const_int 0)))
9ebbca7d 3853 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
0ad91047 3854 "! TARGET_POWER && ! TARGET_POWERPC64"
bdf423cb
MM		 3855 "@
3856 mr. %1,%1
9ebbca7d
GK		 3857 {sr|srw}%I2. %3,%1,%h2
3858 #
3859 #"
3860 [(set_attr "type" "delayed_compare")
3861 (set_attr "length" "4,4,8,8")])
1fd4e8c1 3862
9ebbca7d
GK		 3863(define_split
3864 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3865 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3866 (match_operand:SI 2 "reg_or_cint_operand" ""))
3867 (const_int 0)))
3868 (clobber (match_scratch:SI 3 ""))]
3869 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3870 [(set (match_dup 3)
3871 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3872 (set (match_dup 0)
3873 (compare:CC (match_dup 3)
3874 (const_int 0)))]
3875 "")
3876
3877(define_insn ""
3878 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3879 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3880 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 3881 (const_int 0)))
9ebbca7d 3882 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 3883 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 3884 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 3885 "TARGET_POWER"
1fd4e8c1 3886 "@
29ae5b89
JL		 3887 sre. %0,%1,%2
3888 mr. %0,%1
9ebbca7d
GK		 3889 {s%A2i.|s%A2wi.} %0,%1,%h2
3890 #
3891 #
3892 #"
3893 [(set_attr "type" "delayed_compare")
3894 (set_attr "length" "4,4,4,8,8,8")])
3895
3896(define_split
3897 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3898 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3899 (match_operand:SI 2 "reg_or_cint_operand" ""))
3900 (const_int 0)))
3901 (set (match_operand:SI 0 "gpc_reg_operand" "")
3902 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3903 (clobber (match_scratch:SI 4 ""))]
3904 "TARGET_POWER && reload_completed"
3905 [(parallel [(set (match_dup 0)
3906 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3907 (clobber (match_dup 4))])
3908 (set (match_dup 3)
3909 (compare:CC (match_dup 0)
3910 (const_int 0)))]
3911 "")
ca7f5001
RK		 3912
3913(define_insn ""
9ebbca7d
GK		 3914 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3915 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3916 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
815cdc52 3917 (const_int 0)))
9ebbca7d 3918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 3919 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
0ad91047 3920 "! TARGET_POWER && ! TARGET_POWERPC64"
29ae5b89
JL		 3921 "@
3922 mr. %0,%1
9ebbca7d
GK		 3923 {sr|srw}%I2. %0,%1,%h2
3924 #
3925 #"
3926 [(set_attr "type" "delayed_compare")
3927 (set_attr "length" "4,4,8,8")])
3928
3929(define_split
3930 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3931 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3932 (match_operand:SI 2 "reg_or_cint_operand" ""))
3933 (const_int 0)))
3934 (set (match_operand:SI 0 "gpc_reg_operand" "")
3935 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3936 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3937 [(set (match_dup 0)
3938 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3939 (set (match_dup 3)
3940 (compare:CC (match_dup 0)
3941 (const_int 0)))]
3942 "")
1fd4e8c1
RK		 3943
3944(define_insn ""
cd2b37d9
RK		 3945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3946 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3947 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 3948 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3949 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 3950 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 3951
3952(define_insn ""
9ebbca7d 3953 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3954 (compare:CC
9ebbca7d
GK		 3955 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3956 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3957 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3958 (const_int 0)))
9ebbca7d 3959 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3960 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3961 "@
3962 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3963 #"
3964 [(set_attr "type" "delayed_compare")
3965 (set_attr "length" "4,8")])
3966
3967(define_split
3968 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3969 (compare:CC
3970 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3971 (match_operand:SI 2 "const_int_operand" ""))
3972 (match_operand:SI 3 "mask_operand" ""))
3973 (const_int 0)))
3974 (clobber (match_scratch:SI 4 ""))]
ce71f754 3975 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3976 [(set (match_dup 4)
3977 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3978 (match_dup 3)))
3979 (set (match_dup 0)
3980 (compare:CC (match_dup 4)
3981 (const_int 0)))]
3982 "")
1fd4e8c1
RK		 3983
3984(define_insn ""
9ebbca7d 3985 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3986 (compare:CC
9ebbca7d
GK		 3987 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3988 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3989 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3990 (const_int 0)))
9ebbca7d 3991 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3992 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3993 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3994 "@
3995 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
3996 #"
3997 [(set_attr "type" "delayed_compare")
3998 (set_attr "length" "4,8")])
3999
4000(define_split
4001 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4002 (compare:CC
4003 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4004 (match_operand:SI 2 "const_int_operand" ""))
4005 (match_operand:SI 3 "mask_operand" ""))
4006 (const_int 0)))
4007 (set (match_operand:SI 0 "gpc_reg_operand" "")
4008 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4009 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4010 [(set (match_dup 0)
4011 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4012 (set (match_dup 4)
4013 (compare:CC (match_dup 0)
4014 (const_int 0)))]
4015 "")
1fd4e8c1
RK		 4016
4017(define_insn ""
cd2b37d9 4018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4019 (zero_extend:SI
4020 (subreg:QI
cd2b37d9 4021 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4022 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4023 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4024 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4025
4026(define_insn ""
9ebbca7d 4027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4028 (compare:CC
4029 (zero_extend:SI
4030 (subreg:QI
9ebbca7d
GK		 4031 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4032 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4033 (const_int 0)))
9ebbca7d 4034 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4035 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4036 "@
4037 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4038 #"
4039 [(set_attr "type" "delayed_compare")
4040 (set_attr "length" "4,8")])
4041
4042(define_split
4043 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4044 (compare:CC
4045 (zero_extend:SI
4046 (subreg:QI
4047 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4048 (match_operand:SI 2 "const_int_operand" "")) 0))
4049 (const_int 0)))
4050 (clobber (match_scratch:SI 3 ""))]
4051 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4052 [(set (match_dup 3)
4053 (zero_extend:SI (subreg:QI
4054 (lshiftrt:SI (match_dup 1)
4055 (match_dup 2)) 0)))
4056 (set (match_dup 0)
4057 (compare:CC (match_dup 3)
4058 (const_int 0)))]
4059 "")
1fd4e8c1
RK		 4060
4061(define_insn ""
9ebbca7d 4062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4063 (compare:CC
4064 (zero_extend:SI
4065 (subreg:QI
9ebbca7d
GK		 4066 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4067 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4068 (const_int 0)))
9ebbca7d 4069 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4070 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4071 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4072 "@
4073 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4074 #"
4075 [(set_attr "type" "delayed_compare")
4076 (set_attr "length" "4,8")])
4077
4078(define_split
4079 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4080 (compare:CC
4081 (zero_extend:SI
4082 (subreg:QI
4083 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4084 (match_operand:SI 2 "const_int_operand" "")) 0))
4085 (const_int 0)))
4086 (set (match_operand:SI 0 "gpc_reg_operand" "")
4087 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4088 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4089 [(set (match_dup 0)
4090 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4091 (set (match_dup 3)
4092 (compare:CC (match_dup 0)
4093 (const_int 0)))]
4094 "")
1fd4e8c1
RK		 4095
4096(define_insn ""
cd2b37d9 4097 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4098 (zero_extend:SI
4099 (subreg:HI
cd2b37d9 4100 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4101 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4102 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4103 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4104
4105(define_insn ""
9ebbca7d 4106 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4107 (compare:CC
4108 (zero_extend:SI
4109 (subreg:HI
9ebbca7d
GK		 4110 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4111 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4112 (const_int 0)))
9ebbca7d 4113 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4114 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4115 "@
4116 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4117 #"
4118 [(set_attr "type" "delayed_compare")
4119 (set_attr "length" "4,8")])
4120
4121(define_split
4122 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4123 (compare:CC
4124 (zero_extend:SI
4125 (subreg:HI
4126 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4127 (match_operand:SI 2 "const_int_operand" "")) 0))
4128 (const_int 0)))
4129 (clobber (match_scratch:SI 3 ""))]
4130 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4131 [(set (match_dup 3)
4132 (zero_extend:SI (subreg:HI
4133 (lshiftrt:SI (match_dup 1)
4134 (match_dup 2)) 0)))
4135 (set (match_dup 0)
4136 (compare:CC (match_dup 3)
4137 (const_int 0)))]
4138 "")
1fd4e8c1
RK		 4139
4140(define_insn ""
9ebbca7d 4141 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4142 (compare:CC
4143 (zero_extend:SI
4144 (subreg:HI
9ebbca7d
GK		 4145 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4146 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4147 (const_int 0)))
9ebbca7d 4148 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4149 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4150 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4151 "@
4152 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4153 #"
4154 [(set_attr "type" "delayed_compare")
4155 (set_attr "length" "4,8")])
4156
4157(define_split
4158 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4159 (compare:CC
4160 (zero_extend:SI
4161 (subreg:HI
4162 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4163 (match_operand:SI 2 "const_int_operand" "")) 0))
4164 (const_int 0)))
4165 (set (match_operand:SI 0 "gpc_reg_operand" "")
4166 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4167 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4168 [(set (match_dup 0)
4169 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4170 (set (match_dup 3)
4171 (compare:CC (match_dup 0)
4172 (const_int 0)))]
4173 "")
1fd4e8c1
RK		 4174
4175(define_insn ""
cd2b37d9 4176 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4177 (const_int 1)
cd2b37d9
RK		 4178 (match_operand:SI 1 "gpc_reg_operand" "r"))
4179 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4180 (const_int 31)))]
ca7f5001 4181 "TARGET_POWER"
1fd4e8c1
RK		 4182 "rrib %0,%1,%2")
4183
4184(define_insn ""
cd2b37d9 4185 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4186 (const_int 1)
cd2b37d9
RK		 4187 (match_operand:SI 1 "gpc_reg_operand" "r"))
4188 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4189 (const_int 31)))]
ca7f5001 4190 "TARGET_POWER"
1fd4e8c1
RK		 4191 "rrib %0,%1,%2")
4192
4193(define_insn ""
cd2b37d9 4194 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4195 (const_int 1)
cd2b37d9
RK		 4196 (match_operand:SI 1 "gpc_reg_operand" "r"))
4197 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4198 (const_int 1)
4199 (const_int 0)))]
ca7f5001 4200 "TARGET_POWER"
1fd4e8c1
RK		 4201 "rrib %0,%1,%2")
4202
ca7f5001
RK		 4203(define_expand "ashrsi3"
4204 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4205 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4206 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4207 ""
4208 "
4209{
4210 if (TARGET_POWER)
4211 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4212 else
25c341fa 4213 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4214 DONE;
4215}")
4216
4217(define_insn "ashrsi3_power"
cd2b37d9
RK		 4218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4219 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4220 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4221 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4222 "TARGET_POWER"
1fd4e8c1
RK		 4223 "@
4224 srea %0,%1,%2
ca7f5001
RK		 4225 {srai|srawi} %0,%1,%h2")
4226
25c341fa 4227(define_insn "ashrsi3_no_power"
ca7f5001
RK		 4228 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4229 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4230 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 4231 "! TARGET_POWER"
d904e9ed 4232 "{sra|sraw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 4233
4234(define_insn ""
9ebbca7d
GK		 4235 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4236 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4237 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4238 (const_int 0)))
9ebbca7d
GK		 4239 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4240 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4241 "TARGET_POWER"
1fd4e8c1
RK		 4242 "@
4243 srea. %3,%1,%2
9ebbca7d
GK		 4244 {srai.|srawi.} %3,%1,%h2
4245 #
4246 #"
4247 [(set_attr "type" "delayed_compare")
4248 (set_attr "length" "4,4,8,8")])
4249
4250(define_split
4251 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4252 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4253 (match_operand:SI 2 "reg_or_cint_operand" ""))
4254 (const_int 0)))
4255 (clobber (match_scratch:SI 3 ""))
4256 (clobber (match_scratch:SI 4 ""))]
4257 "TARGET_POWER && reload_completed"
4258 [(parallel [(set (match_dup 3)
4259 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4260 (clobber (match_dup 4))])
4261 (set (match_dup 0)
4262 (compare:CC (match_dup 3)
4263 (const_int 0)))]
4264 "")
ca7f5001
RK		 4265
4266(define_insn ""
9ebbca7d
GK		 4267 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4268 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4269 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 4270 (const_int 0)))
9ebbca7d 4271 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 4272 "! TARGET_POWER"
9ebbca7d
GK		 4273 "@
4274 {sra|sraw}%I2. %3,%1,%h2
4275 #"
4276 [(set_attr "type" "delayed_compare")
4277 (set_attr "length" "4,8")])
4278
4279(define_split
4280 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4281 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4282 (match_operand:SI 2 "reg_or_cint_operand" ""))
4283 (const_int 0)))
4284 (clobber (match_scratch:SI 3 ""))]
4285 "! TARGET_POWER && reload_completed"
4286 [(set (match_dup 3)
4287 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4288 (set (match_dup 0)
4289 (compare:CC (match_dup 3)
4290 (const_int 0)))]
4291 "")
1fd4e8c1
RK		 4292
4293(define_insn ""
9ebbca7d
GK		 4294 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4295 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4296 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4297 (const_int 0)))
9ebbca7d 4298 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4299 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4300 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4301 "TARGET_POWER"
1fd4e8c1
RK		 4302 "@
4303 srea. %0,%1,%2
9ebbca7d
GK		 4304 {srai.|srawi.} %0,%1,%h2
4305 #
4306 #"
4307 [(set_attr "type" "delayed_compare")
4308 (set_attr "length" "4,4,8,8")])
4309
4310(define_split
4311 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4312 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4313 (match_operand:SI 2 "reg_or_cint_operand" ""))
4314 (const_int 0)))
4315 (set (match_operand:SI 0 "gpc_reg_operand" "")
4316 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4317 (clobber (match_scratch:SI 4 ""))]
4318 "TARGET_POWER && reload_completed"
4319 [(parallel [(set (match_dup 0)
4320 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4321 (clobber (match_dup 4))])
4322 (set (match_dup 3)
4323 (compare:CC (match_dup 0)
4324 (const_int 0)))]
4325 "")
1fd4e8c1 4326
ca7f5001 4327(define_insn ""
9ebbca7d
GK		 4328 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4329 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4330 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 4331 (const_int 0)))
9ebbca7d 4332 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 4333 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 4334 "! TARGET_POWER"
9ebbca7d
GK		 4335 "@
4336 {sra|sraw}%I2. %0,%1,%h2
4337 #"
4338 [(set_attr "type" "delayed_compare")
4339 (set_attr "length" "4,8")])
1fd4e8c1 4340\f
9ebbca7d
GK		 4341(define_split
4342 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4343 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4344 (match_operand:SI 2 "reg_or_cint_operand" ""))
4345 (const_int 0)))
4346 (set (match_operand:SI 0 "gpc_reg_operand" "")
4347 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4348 "! TARGET_POWER && reload_completed"
4349 [(set (match_dup 0)
4350 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4351 (set (match_dup 3)
4352 (compare:CC (match_dup 0)
4353 (const_int 0)))]
4354 "")
4355
1fd4e8c1
RK		 4356;; Floating-point insns, excluding normal data motion.
4357;;
ca7f5001
RK		 4358;; PowerPC has a full set of single-precision floating point instructions.
4359;;
4360;; For the POWER architecture, we pretend that we have both SFmode and
4361;; DFmode insns, while, in fact, all fp insns are actually done in double.
4362;; The only conversions we will do will be when storing to memory. In that
4363;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 4364;;
4365;; Note that when we store into a single-precision memory location, we need to
4366;; use the frsp insn first. If the register being stored isn't dead, we
4367;; need a scratch register for the frsp. But this is difficult when the store
4368;; is done by reload. It is not incorrect to do the frsp on the register in
4369;; this case, we just lose precision that we would have otherwise gotten but
4370;; is not guaranteed. Perhaps this should be tightened up at some point.
4371
e8112008 4372(define_insn "extendsfdf2"
cd2b37d9 4373 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
e8112008 4374 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4375 "TARGET_HARD_FLOAT && TARGET_FPRS"
e8112008 4376 "*
5c30aff8 4377{
e8112008
RK		 4378 if (REGNO (operands[0]) == REGNO (operands[1]))
4379 return \"\";
4380 else
4381 return \"fmr %0,%1\";
4382}"
4383 [(set_attr "type" "fp")])
1fd4e8c1
RK		 4384
4385(define_insn "truncdfsf2"
cd2b37d9
RK		 4386 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4387 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4388 "TARGET_HARD_FLOAT && TARGET_FPRS"
dcac138d 4389 "frsp %0,%1"
1fd4e8c1
RK		 4390 [(set_attr "type" "fp")])
4391
455350f4
RK		 4392(define_insn "aux_truncdfsf2"
4393 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 4394 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
a3170dc6 4395 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 4396 "frsp %0,%1"
4397 [(set_attr "type" "fp")])
4398
a3170dc6
AH		 4399(define_expand "negsf2"
4400 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4401 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4402 "TARGET_HARD_FLOAT"
4403 "")
4404
4405(define_insn "*negsf2"
cd2b37d9
RK		 4406 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4407 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4408 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4409 "fneg %0,%1"
4410 [(set_attr "type" "fp")])
4411
a3170dc6
AH		 4412(define_expand "abssf2"
4413 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4414 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4415 "TARGET_HARD_FLOAT"
4416 "")
4417
4418(define_insn "*abssf2"
cd2b37d9
RK		 4419 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4420 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4421 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4422 "fabs %0,%1"
4423 [(set_attr "type" "fp")])
4424
4425(define_insn ""
cd2b37d9
RK		 4426 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4427 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
a3170dc6 4428 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4429 "fnabs %0,%1"
4430 [(set_attr "type" "fp")])
4431
ca7f5001
RK		 4432(define_expand "addsf3"
4433 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4434 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4435 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4436 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4437 "")
4438
4439(define_insn ""
cd2b37d9
RK		 4440 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4441 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4442 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4443 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4444 "fadds %0,%1,%2"
ca7f5001
RK		 4445 [(set_attr "type" "fp")])
4446
4447(define_insn ""
4448 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4449 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4450 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4451 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4452 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 4453 [(set_attr "type" "fp")])
4454
4455(define_expand "subsf3"
4456 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4457 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4458 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4459 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4460 "")
4461
4462(define_insn ""
4463 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4464 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4465 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4466 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4467 "fsubs %0,%1,%2"
1fd4e8c1
RK		 4468 [(set_attr "type" "fp")])
4469
ca7f5001 4470(define_insn ""
cd2b37d9
RK		 4471 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4472 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4473 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4474 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4475 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 4476 [(set_attr "type" "fp")])
4477
4478(define_expand "mulsf3"
4479 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4480 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4481 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4482 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4483 "")
4484
4485(define_insn ""
4486 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4487 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4488 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4489 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4490 "fmuls %0,%1,%2"
1fd4e8c1
RK		 4491 [(set_attr "type" "fp")])
4492
ca7f5001 4493(define_insn ""
cd2b37d9
RK		 4494 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4495 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4496 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4497 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4498 "{fm|fmul} %0,%1,%2"
0780f386 4499 [(set_attr "type" "dmul")])
1fd4e8c1 4500
ca7f5001
RK		 4501(define_expand "divsf3"
4502 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4503 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4504 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4505 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4506 "")
4507
4508(define_insn ""
cd2b37d9
RK		 4509 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4510 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4511 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4512 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4513 "fdivs %0,%1,%2"
ca7f5001
RK		 4514 [(set_attr "type" "sdiv")])
4515
4516(define_insn ""
4517 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4518 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4519 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4520 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4521 "{fd|fdiv} %0,%1,%2"
0780f386 4522 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 4523
4524(define_insn ""
cd2b37d9
RK		 4525 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4526 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4527 (match_operand:SF 2 "gpc_reg_operand" "f"))
4528 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4529 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4530 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 4531 [(set_attr "type" "fp")])
4532
4533(define_insn ""
4534 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4535 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4536 (match_operand:SF 2 "gpc_reg_operand" "f"))
4537 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4538 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4539 "{fma|fmadd} %0,%1,%2,%3"
cf27b467 4540 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4541
4542(define_insn ""
cd2b37d9
RK		 4543 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4544 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4545 (match_operand:SF 2 "gpc_reg_operand" "f"))
4546 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4547 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4548 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 4549 [(set_attr "type" "fp")])
4550
4551(define_insn ""
4552 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4553 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4554 (match_operand:SF 2 "gpc_reg_operand" "f"))
4555 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4556 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4557 "{fms|fmsub} %0,%1,%2,%3"
cf27b467 4558 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4559
4560(define_insn ""
cd2b37d9
RK		 4561 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4562 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4563 (match_operand:SF 2 "gpc_reg_operand" "f"))
4564 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4565 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4566 && HONOR_SIGNED_ZEROS (SFmode)"
4567 "fnmadds %0,%1,%2,%3"
4568 [(set_attr "type" "fp")])
4569
4570(define_insn ""
4571 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4572 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4573 (match_operand:SF 2 "gpc_reg_operand" "f"))
4574 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4575 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4576 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 4577 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 4578 [(set_attr "type" "fp")])
4579
4580(define_insn ""
4581 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4582 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4583 (match_operand:SF 2 "gpc_reg_operand" "f"))
4584 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 4585 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4586 "{fnma|fnmadd} %0,%1,%2,%3"
cf27b467 4587 [(set_attr "type" "dmul")])
1fd4e8c1 4588
16823694
GK		 4589(define_insn ""
4590 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4591 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4592 (match_operand:SF 2 "gpc_reg_operand" "f"))
4593 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4594 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4595 && ! HONOR_SIGNED_ZEROS (SFmode)"
4596 "{fnma|fnmadd} %0,%1,%2,%3"
4597 [(set_attr "type" "dmul")])
4598
1fd4e8c1 4599(define_insn ""
cd2b37d9
RK		 4600 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4601 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4602 (match_operand:SF 2 "gpc_reg_operand" "f"))
4603 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4604 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4605 && HONOR_SIGNED_ZEROS (SFmode)"
4606 "fnmsubs %0,%1,%2,%3"
4607 [(set_attr "type" "fp")])
4608
4609(define_insn ""
4610 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4611 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4612 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4613 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4614 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4615 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 4616 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 4617 [(set_attr "type" "fp")])
4618
4619(define_insn ""
4620 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4621 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4622 (match_operand:SF 2 "gpc_reg_operand" "f"))
4623 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 4624 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4625 "{fnms|fnmsub} %0,%1,%2,%3"
cf27b467 4626 [(set_attr "type" "dmul")])
1fd4e8c1 4627
16823694
GK		 4628(define_insn ""
4629 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4630 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4631 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4632 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4633 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4634 && ! HONOR_SIGNED_ZEROS (SFmode)"
4635 "{fnms|fnmsub} %0,%1,%2,%3"
4636 [(set_attr "type" "fp")])
4637
ca7f5001
RK		 4638(define_expand "sqrtsf2"
4639 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4640 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
a3170dc6 4641 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4642 "")
4643
4644(define_insn ""
4645 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4646 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4647 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4648 "fsqrts %0,%1"
4649 [(set_attr "type" "ssqrt")])
4650
4651(define_insn ""
4652 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4653 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4654 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4655 "fsqrt %0,%1"
4656 [(set_attr "type" "dsqrt")])
4657
94d7001a
RK		 4658;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4659;; fsel instruction and some auxiliary computations. Then we just have a
4660;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05
RK		 4661;; combine.
4662(define_expand "maxsf3"
8e871c05 4663 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 4664 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4665 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 4666 (match_dup 1)
4667 (match_dup 2)))]
a3170dc6 4668 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4669 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 4670
8e871c05 4671(define_expand "minsf3"
50a0b056
GK		 4672 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4673 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4674 (match_operand:SF 2 "gpc_reg_operand" ""))
4675 (match_dup 2)
4676 (match_dup 1)))]
a3170dc6 4677 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4678 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 4679
8e871c05
RK		 4680(define_split
4681 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 4682 (match_operator:SF 3 "min_max_operator"
4683 [(match_operand:SF 1 "gpc_reg_operand" "")
4684 (match_operand:SF 2 "gpc_reg_operand" "")]))]
a3170dc6 4685 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056
GK		 4686 [(const_int 0)]
4687 "
4688{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4689 operands[1], operands[2]);
4690 DONE;
4691}")
2f607b94 4692
a3170dc6
AH		 4693(define_expand "movsicc"
4694 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4695 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4696 (match_operand:SI 2 "gpc_reg_operand" "")
4697 (match_operand:SI 3 "gpc_reg_operand" "")))]
4698 "TARGET_ISEL"
4699 "
4700{
4701 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4702 DONE;
4703 else
4704 FAIL;
4705}")
4706
4707;; We use the BASE_REGS for the isel input operands because, if rA is
4708;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4709;; because we may switch the operands and rB may end up being rA.
4710;;
4711;; We need 2 patterns: an unsigned and a signed pattern. We could
4712;; leave out the mode in operand 4 and use one pattern, but reload can
4713;; change the mode underneath our feet and then gets confused trying
4714;; to reload the value.
4715(define_insn "isel_signed"
4716 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4717 (if_then_else:SI
4718 (match_operator 1 "comparison_operator"
4719 [(match_operand:CC 4 "cc_reg_operand" "y")
4720 (const_int 0)])
4721 (match_operand:SI 2 "gpc_reg_operand" "b")
4722 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4723 "TARGET_ISEL"
4724 "*
4725{ return output_isel (operands); }"
4726 [(set_attr "length" "4")])
4727
4728(define_insn "isel_unsigned"
4729 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4730 (if_then_else:SI
4731 (match_operator 1 "comparison_operator"
4732 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4733 (const_int 0)])
4734 (match_operand:SI 2 "gpc_reg_operand" "b")
4735 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4736 "TARGET_ISEL"
4737 "*
4738{ return output_isel (operands); }"
4739 [(set_attr "length" "4")])
4740
94d7001a 4741(define_expand "movsfcc"
0ad91047 4742 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 4743 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 4744 (match_operand:SF 2 "gpc_reg_operand" "")
4745 (match_operand:SF 3 "gpc_reg_operand" "")))]
a3170dc6 4746 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4747 "
4748{
50a0b056
GK		 4749 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4750 DONE;
94d7001a 4751 else
50a0b056 4752 FAIL;
94d7001a 4753}")
d56d506a 4754
50a0b056 4755(define_insn "*fselsfsf4"
8e871c05
RK		 4756 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4757 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 4758 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 4759 (match_operand:SF 2 "gpc_reg_operand" "f")
4760 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4761 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 4762 "fsel %0,%1,%2,%3"
4763 [(set_attr "type" "fp")])
2f607b94 4764
50a0b056 4765(define_insn "*fseldfsf4"
94d7001a
RK		 4766 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4767 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 4768 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 4769 (match_operand:SF 2 "gpc_reg_operand" "f")
4770 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4771 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4772 "fsel %0,%1,%2,%3"
4773 [(set_attr "type" "fp")])
d56d506a 4774
1fd4e8c1 4775(define_insn "negdf2"
cd2b37d9
RK		 4776 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4777 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4778 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4779 "fneg %0,%1"
4780 [(set_attr "type" "fp")])
4781
4782(define_insn "absdf2"
cd2b37d9
RK		 4783 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4784 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4785 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4786 "fabs %0,%1"
4787 [(set_attr "type" "fp")])
4788
4789(define_insn ""
cd2b37d9
RK		 4790 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4791 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
a3170dc6 4792 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4793 "fnabs %0,%1"
4794 [(set_attr "type" "fp")])
4795
4796(define_insn "adddf3"
cd2b37d9
RK		 4797 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4798 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4799 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4800 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4801 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 4802 [(set_attr "type" "fp")])
4803
4804(define_insn "subdf3"
cd2b37d9
RK		 4805 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4806 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4807 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4808 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4809 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 4810 [(set_attr "type" "fp")])
4811
4812(define_insn "muldf3"
cd2b37d9
RK		 4813 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4814 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4815 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4816 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4817 "{fm|fmul} %0,%1,%2"
cfb557c4 4818 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4819
4820(define_insn "divdf3"
cd2b37d9
RK		 4821 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4822 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4823 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4824 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4825 "{fd|fdiv} %0,%1,%2"
cfb557c4 4826 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 4827
4828(define_insn ""
cd2b37d9
RK		 4829 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4830 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4831 (match_operand:DF 2 "gpc_reg_operand" "f"))
4832 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4833 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 4834 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 4835 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4836
4837(define_insn ""
cd2b37d9
RK		 4838 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4839 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4840 (match_operand:DF 2 "gpc_reg_operand" "f"))
4841 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4842 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 4843 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 4844 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4845
4846(define_insn ""
cd2b37d9
RK		 4847 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4848 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4849 (match_operand:DF 2 "gpc_reg_operand" "f"))
4850 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4851 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4852 && HONOR_SIGNED_ZEROS (DFmode)"
4853 "{fnma|fnmadd} %0,%1,%2,%3"
4854 [(set_attr "type" "dmul")])
4855
4856(define_insn ""
4857 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4858 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4859 (match_operand:DF 2 "gpc_reg_operand" "f"))
4860 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4861 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4862 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 4863 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 4864 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4865
4866(define_insn ""
cd2b37d9
RK		 4867 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4868 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4869 (match_operand:DF 2 "gpc_reg_operand" "f"))
4870 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4871 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4872 && HONOR_SIGNED_ZEROS (DFmode)"
4873 "{fnms|fnmsub} %0,%1,%2,%3"
4874 [(set_attr "type" "dmul")])
4875
4876(define_insn ""
4877 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4878 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4879 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4880 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4881 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4882 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 4883 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 4884 [(set_attr "type" "dmul")])
ca7f5001
RK		 4885
4886(define_insn "sqrtdf2"
4887 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4888 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4889 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4890 "fsqrt %0,%1"
4891 [(set_attr "type" "dsqrt")])
b77dfefc 4892
50a0b056
GK		 4893;; The conditional move instructions allow us to perform max and min
4894;; operations even when
b77dfefc 4895
8e871c05 4896(define_expand "maxdf3"
8e871c05 4897 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 4898 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4899 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 4900 (match_dup 1)
4901 (match_dup 2)))]
a3170dc6 4902 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4903 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 4904
8e871c05 4905(define_expand "mindf3"
50a0b056
GK		 4906 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4907 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4908 (match_operand:DF 2 "gpc_reg_operand" ""))
4909 (match_dup 2)
4910 (match_dup 1)))]
a3170dc6 4911 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4912 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 4913
8e871c05
RK		 4914(define_split
4915 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 4916 (match_operator:DF 3 "min_max_operator"
4917 [(match_operand:DF 1 "gpc_reg_operand" "")
4918 (match_operand:DF 2 "gpc_reg_operand" "")]))]
a3170dc6 4919 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056
GK		 4920 [(const_int 0)]
4921 "
4922{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4923 operands[1], operands[2]);
4924 DONE;
4925}")
b77dfefc 4926
94d7001a 4927(define_expand "movdfcc"
0ad91047 4928 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 4929 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 4930 (match_operand:DF 2 "gpc_reg_operand" "")
4931 (match_operand:DF 3 "gpc_reg_operand" "")))]
a3170dc6 4932 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4933 "
4934{
50a0b056
GK		 4935 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4936 DONE;
94d7001a 4937 else
50a0b056 4938 FAIL;
94d7001a 4939}")
d56d506a 4940
50a0b056 4941(define_insn "*fseldfdf4"
8e871c05
RK		 4942 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4943 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 4944 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 4945 (match_operand:DF 2 "gpc_reg_operand" "f")
4946 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4947 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 4948 "fsel %0,%1,%2,%3"
4949 [(set_attr "type" "fp")])
d56d506a 4950
50a0b056 4951(define_insn "*fselsfdf4"
94d7001a
RK		 4952 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4953 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 4954 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 4955 (match_operand:DF 2 "gpc_reg_operand" "f")
4956 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4957 "TARGET_PPC_GFXOPT"
4958 "fsel %0,%1,%2,%3"
4959 [(set_attr "type" "fp")])
1fd4e8c1
RK		 4960\f
4961;; Conversions to and from floating-point.
802a0058 4962
a3170dc6
AH		 4963(define_expand "fixunssfsi2"
4964 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4965 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" ""))))]
4966 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4967 "")
4968
4969(define_expand "fix_truncsfsi2"
4970 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4971 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4972 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4973 "")
4974
9ebbca7d
GK		 4975; For each of these conversions, there is a define_expand, a define_insn
4976; with a '#' template, and a define_split (with C code). The idea is
4977; to allow constant folding with the template of the define_insn,
4978; then to have the insns split later (between sched1 and final).
4979
1fd4e8c1 4980(define_expand "floatsidf2"
802a0058
MM		 4981 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4982 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4983 (use (match_dup 2))
4984 (use (match_dup 3))
208c89ce 4985 (clobber (match_dup 4))
a7df97e6 4986 (clobber (match_dup 5))
9ebbca7d 4987 (clobber (match_dup 6))])]
a3170dc6 4988 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4989 "
4990{
05d49501
AM		 4991 if (TARGET_POWERPC64)
4992 {
4993 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
4994 rtx t1 = gen_reg_rtx (DImode);
4995 rtx t2 = gen_reg_rtx (DImode);
4996 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
4997 DONE;
4998 }
4999
802a0058 5000 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5001 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5002 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5003 operands[5] = gen_reg_rtx (DFmode);
5004 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5005}")
5006
802a0058
MM		 5007(define_insn "*floatsidf2_internal"
5008 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5009 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5010 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5011 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5012 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5
DJ		 5013 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5014 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
a3170dc6 5015 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5016 "#"
a7df97e6 5017 [(set_attr "length" "24")])
802a0058
MM		 5018
5019(define_split
dbe3df29 5020 [(set (match_operand:DF 0 "gpc_reg_operand" "")
802a0058
MM		 5021 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5022 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5023 (use (match_operand:DF 3 "gpc_reg_operand" ""))
9ebbca7d
GK		 5024 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5025 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5026 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
a3170dc6 5027 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
9ebbca7d
GK		 5028 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5029 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5030 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5031 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5032 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5033 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5034 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
208c89ce
MM		 5035 "
5036{
9ebbca7d
GK		 5037 rtx lowword, highword;
5038 if (GET_CODE (operands[4]) != MEM)
5039 abort();
5040 highword = XEXP (operands[4], 0);
5041 lowword = plus_constant (highword, 4);
5042 if (! WORDS_BIG_ENDIAN)
5043 {
5044 rtx tmp;
5045 tmp = highword; highword = lowword; lowword = tmp;
5046 }
5047
5048 emit_insn (gen_xorsi3 (operands[6], operands[1],
5049 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5050 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5051 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5052 emit_move_insn (operands[5], operands[4]);
5053 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5054 DONE;
208c89ce 5055}")
802a0058 5056
a3170dc6
AH		 5057(define_expand "floatunssisf2"
5058 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5059 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5060 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5061 "")
5062
802a0058
MM		 5063(define_expand "floatunssidf2"
5064 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5065 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5066 (use (match_dup 2))
5067 (use (match_dup 3))
a7df97e6 5068 (clobber (match_dup 4))
9ebbca7d 5069 (clobber (match_dup 5))])]
a3170dc6 5070 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5071 "
5072{
05d49501
AM		 5073 if (TARGET_POWERPC64)
5074 {
5075 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5076 rtx t1 = gen_reg_rtx (DImode);
5077 rtx t2 = gen_reg_rtx (DImode);
5078 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5079 t1, t2));
5080 DONE;
5081 }
5082
802a0058 5083 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5084 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 5085 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5086 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 5087}")
5088
802a0058
MM		 5089(define_insn "*floatunssidf2_internal"
5090 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5091 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5092 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5093 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5094 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5 5095 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
a3170dc6 5096 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5097 "#"
a7df97e6 5098 [(set_attr "length" "20")])
802a0058
MM		 5099
5100(define_split
5101 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5102 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5103 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5104 (use (match_operand:DF 3 "gpc_reg_operand" ""))
9ebbca7d
GK		 5105 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5106 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
a3170dc6 5107 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
9ebbca7d
GK		 5108 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5109 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5110 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5111 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5112 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5113 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5114 "
802a0058 5115{
9ebbca7d
GK		 5116 rtx lowword, highword;
5117 if (GET_CODE (operands[4]) != MEM)
5118 abort();
5119 highword = XEXP (operands[4], 0);
5120 lowword = plus_constant (highword, 4);
5121 if (! WORDS_BIG_ENDIAN)
f6968f59 5122 {
9ebbca7d
GK		 5123 rtx tmp;
5124 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 5125 }
802a0058 5126
9ebbca7d
GK		 5127 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5128 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5129 emit_move_insn (operands[5], operands[4]);
5130 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5131 DONE;
5132}")
1fd4e8c1 5133
1fd4e8c1 5134(define_expand "fix_truncdfsi2"
802a0058
MM		 5135 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5136 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5137 (clobber (match_dup 2))
9ebbca7d 5138 (clobber (match_dup 3))])]
a3170dc6 5139 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5140 "
5141{
802a0058 5142 operands[2] = gen_reg_rtx (DImode);
9ebbca7d 5143 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 5144}")
5145
802a0058
MM		 5146(define_insn "*fix_truncdfsi2_internal"
5147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5148 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 5149 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
9ebbca7d 5150 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
a3170dc6 5151 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5152 "#"
9ebbca7d 5153 [(set_attr "length" "16")])
802a0058
MM		 5154
5155(define_split
5156 [(set (match_operand:SI 0 "gpc_reg_operand" "")
75540af0 5157 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
802a0058 5158 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
9ebbca7d 5159 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
a3170dc6 5160 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
9ebbca7d 5161 [(set (match_operand:SI 0 "gpc_reg_operand" "")
75540af0 5162 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
9ebbca7d
GK		 5163 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5164 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5165 "
802a0058 5166{
9ebbca7d
GK		 5167 rtx lowword;
5168 if (GET_CODE (operands[3]) != MEM)
5169 abort();
5170 lowword = XEXP (operands[3], 0);
5171 if (WORDS_BIG_ENDIAN)
5172 lowword = plus_constant (lowword, 4);
802a0058 5173
9ebbca7d
GK		 5174 emit_insn (gen_fctiwz (operands[2], operands[1]));
5175 emit_move_insn (operands[3], operands[2]);
5176 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5177 DONE;
5178}")
802a0058 5179
615158e2 5180; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 5181; rather than (set (subreg:SI (reg)) (fix:SI ...))
5182; because the first makes it clear that operand 0 is not live
5183; before the instruction.
5184(define_insn "fctiwz"
61c07d3c 5185 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
615158e2
JJ		 5186 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5187 UNSPEC_FCTIWZ))]
a3170dc6 5188 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
a260abc9
DE		 5189 "{fcirz|fctiwz} %0,%1"
5190 [(set_attr "type" "fp")])
5191
a3170dc6
AH		 5192(define_expand "floatsisf2"
5193 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5194 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5195 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5196 "")
5197
a473029f
RK		 5198(define_insn "floatdidf2"
5199 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
61c07d3c 5200 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
a3170dc6 5201 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 5202 "fcfid %0,%1"
5203 [(set_attr "type" "fp")])
5204
05d49501
AM		 5205(define_insn_and_split "floatsidf_ppc64"
5206 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5207 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5208 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5209 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5210 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 5211 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501
AM		 5212 "#"
5213 ""
5214 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5215 (set (match_dup 2) (match_dup 3))
5216 (set (match_dup 4) (match_dup 2))
5217 (set (match_dup 0) (float:DF (match_dup 4)))]
5218 "")
5219
5220(define_insn_and_split "floatunssidf_ppc64"
5221 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5222 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5223 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5224 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5225 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 5226 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501
AM		 5227 "#"
5228 ""
5229 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5230 (set (match_dup 2) (match_dup 3))
5231 (set (match_dup 4) (match_dup 2))
5232 (set (match_dup 0) (float:DF (match_dup 4)))]
5233 "")
5234
a473029f 5235(define_insn "fix_truncdfdi2"
61c07d3c 5236 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
a473029f 5237 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5238 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 5239 "fctidz %0,%1"
5240 [(set_attr "type" "fp")])
ea112fc4 5241
678b7733
AM		 5242(define_expand "floatdisf2"
5243 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5244 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
683bdff7 5245 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 5246 "
5247{
5248 if (!flag_unsafe_math_optimizations)
5249 {
5250 rtx label = gen_label_rtx ();
5251 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5252 emit_label (label);
5253 }
5254 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5255 DONE;
5256}")
5257
5258;; This is not IEEE compliant if rounding mode is "round to nearest".
5259;; If the DI->DF conversion is inexact, then it's possible to suffer
5260;; from double rounding.
5261(define_insn_and_split "floatdisf2_internal1"
ea112fc4 5262 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
61c07d3c 5263 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
ea112fc4 5264 (clobber (match_scratch:DF 2 "=f"))]
678b7733 5265 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
ea112fc4
DE		 5266 "#"
5267 "&& reload_completed"
5268 [(set (match_dup 2)
5269 (float:DF (match_dup 1)))
5270 (set (match_dup 0)
5271 (float_truncate:SF (match_dup 2)))]
5272 "")
678b7733
AM		 5273
5274;; Twiddles bits to avoid double rounding.
b6d08ca1 5275;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 5276;; by a bit that won't be lost at that stage, but is below the SFmode
5277;; rounding position.
5278(define_expand "floatdisf2_internal2"
42a6388c
AM		 5279 [(parallel [(set (match_dup 4)
5280 (compare:CC (and:DI (match_operand:DI 0 "" "")
5281 (const_int 2047))
5282 (const_int 0)))
5283 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
5284 (clobber (match_scratch:CC 7 ""))])
678b7733
AM		 5285 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
5286 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
5287 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
5288 (label_ref (match_operand:DI 1 "" ""))
5289 (pc)))
5290 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
5291 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
5292 (label_ref (match_dup 1))
5293 (pc)))
5294 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
5295 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
683bdff7 5296 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 5297 "
5298{
5299 operands[2] = gen_reg_rtx (DImode);
5300 operands[3] = gen_reg_rtx (DImode);
5301 operands[4] = gen_reg_rtx (CCmode);
5302 operands[5] = gen_reg_rtx (CCUNSmode);
5303}")
1fd4e8c1
RK		 5304\f
5305;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 5306;; of instructions. The & constraints are to prevent the register
5307;; allocator from allocating registers that overlap with the inputs
5308;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 5309;; also allow for the output being the same as one of the inputs.
a6ec530c 5310
266eb58a 5311(define_insn "*adddi3_noppc64"
a6ec530c
RK		 5312 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5313 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5314 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 5315 "! TARGET_POWERPC64"
0f645302
MM		 5316 "*
5317{
5318 if (WORDS_BIG_ENDIAN)
5319 return (GET_CODE (operands[2])) != CONST_INT
5320 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5321 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5322 else
5323 return (GET_CODE (operands[2])) != CONST_INT
5324 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5325 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5326}"
b19003d8 5327 [(set_attr "length" "8")])
1fd4e8c1 5328
266eb58a 5329(define_insn "*subdi3_noppc64"
e7e5df70
RK		 5330 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5331 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5332 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 5333 "! TARGET_POWERPC64"
5502823b
RK		 5334 "*
5335{
0f645302
MM		 5336 if (WORDS_BIG_ENDIAN)
5337 return (GET_CODE (operands[1]) != CONST_INT)
5338 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5339 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5340 else
5341 return (GET_CODE (operands[1]) != CONST_INT)
5342 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5343 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 5344}"
ca7f5001
RK		 5345 [(set_attr "length" "8")])
5346
266eb58a 5347(define_insn "*negdi2_noppc64"
a6ec530c
RK		 5348 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5349 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 5350 "! TARGET_POWERPC64"
5502823b
RK		 5351 "*
5352{
5353 return (WORDS_BIG_ENDIAN)
5354 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5355 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5356}"
ca7f5001
RK		 5357 [(set_attr "length" "8")])
5358
8ffd9c51
RK		 5359(define_expand "mulsidi3"
5360 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5361 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5362 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 5363 "! TARGET_POWERPC64"
8ffd9c51
RK		 5364 "
5365{
5366 if (! TARGET_POWER && ! TARGET_POWERPC)
5367 {
39403d82
DE		 5368 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5369 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 5370 emit_insn (gen_mull_call ());
cf27b467 5371 if (WORDS_BIG_ENDIAN)
39403d82 5372 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 5373 else
5374 {
5375 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 5376 gen_rtx_REG (SImode, 3));
cf27b467 5377 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 5378 gen_rtx_REG (SImode, 4));
cf27b467 5379 }
8ffd9c51
RK		 5380 DONE;
5381 }
5382 else if (TARGET_POWER)
5383 {
5384 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5385 DONE;
5386 }
5387}")
deb9225a 5388
8ffd9c51 5389(define_insn "mulsidi3_mq"
cd2b37d9 5390 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 5391 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 5392 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 5393 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 5394 "TARGET_POWER"
b19003d8 5395 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 5396 [(set_attr "type" "imul")
5397 (set_attr "length" "8")])
deb9225a 5398
f192bf8b 5399(define_insn "*mulsidi3_no_mq"
425c176f 5400 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 5401 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5402 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 5403 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 5404 "*
5405{
5406 return (WORDS_BIG_ENDIAN)
5407 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5408 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5409}"
8ffd9c51
RK		 5410 [(set_attr "type" "imul")
5411 (set_attr "length" "8")])
deb9225a 5412
ebedb4dd
MM		 5413(define_split
5414 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5415 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5416 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 5417 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 5418 [(set (match_dup 3)
5419 (truncate:SI
5420 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5421 (sign_extend:DI (match_dup 2)))
5422 (const_int 32))))
5423 (set (match_dup 4)
5424 (mult:SI (match_dup 1)
5425 (match_dup 2)))]
5426 "
5427{
5428 int endian = (WORDS_BIG_ENDIAN == 0);
5429 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5430 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5431}")
5432
f192bf8b
DE		 5433(define_expand "umulsidi3"
5434 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5435 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5436 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5437 "TARGET_POWERPC && ! TARGET_POWERPC64"
5438 "
5439{
5440 if (TARGET_POWER)
5441 {
5442 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5443 DONE;
5444 }
5445}")
5446
5447(define_insn "umulsidi3_mq"
5448 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5449 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5450 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5451 (clobber (match_scratch:SI 3 "=q"))]
5452 "TARGET_POWERPC && TARGET_POWER"
5453 "*
5454{
5455 return (WORDS_BIG_ENDIAN)
5456 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5457 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5458}"
5459 [(set_attr "type" "imul")
5460 (set_attr "length" "8")])
5461
5462(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 5463 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5464 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5465 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 5466 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 5467 "*
5468{
5469 return (WORDS_BIG_ENDIAN)
5470 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5471 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5472}"
5473 [(set_attr "type" "imul")
5474 (set_attr "length" "8")])
5475
ebedb4dd
MM		 5476(define_split
5477 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5478 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5479 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 5480 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 5481 [(set (match_dup 3)
5482 (truncate:SI
5483 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5484 (zero_extend:DI (match_dup 2)))
5485 (const_int 32))))
5486 (set (match_dup 4)
5487 (mult:SI (match_dup 1)
5488 (match_dup 2)))]
5489 "
5490{
5491 int endian = (WORDS_BIG_ENDIAN == 0);
5492 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5493 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5494}")
5495
8ffd9c51
RK		 5496(define_expand "smulsi3_highpart"
5497 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5498 (truncate:SI
5499 (lshiftrt:DI (mult:DI (sign_extend:DI
5500 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5501 (sign_extend:DI
5502 (match_operand:SI 2 "gpc_reg_operand" "r")))
5503 (const_int 32))))]
5504 ""
5505 "
5506{
5507 if (! TARGET_POWER && ! TARGET_POWERPC)
5508 {
39403d82
DE		 5509 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5510 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 5511 emit_insn (gen_mulh_call ());
39403d82 5512 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 5513 DONE;
5514 }
5515 else if (TARGET_POWER)
5516 {
5517 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5518 DONE;
5519 }
5520}")
deb9225a 5521
8ffd9c51
RK		 5522(define_insn "smulsi3_highpart_mq"
5523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5524 (truncate:SI
fada905b
MM		 5525 (lshiftrt:DI (mult:DI (sign_extend:DI
5526 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5527 (sign_extend:DI
5528 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 5529 (const_int 32))))
5530 (clobber (match_scratch:SI 3 "=q"))]
5531 "TARGET_POWER"
5532 "mul %0,%1,%2"
5533 [(set_attr "type" "imul")])
deb9225a 5534
f192bf8b 5535(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 5536 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5537 (truncate:SI
fada905b
MM		 5538 (lshiftrt:DI (mult:DI (sign_extend:DI
5539 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5540 (sign_extend:DI
5541 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 5542 (const_int 32))))]
f192bf8b 5543 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 5544 "mulhw %0,%1,%2"
5545 [(set_attr "type" "imul")])
deb9225a 5546
f192bf8b
DE		 5547(define_expand "umulsi3_highpart"
5548 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5549 (truncate:SI
5550 (lshiftrt:DI (mult:DI (zero_extend:DI
5551 (match_operand:SI 1 "gpc_reg_operand" ""))
5552 (zero_extend:DI
5553 (match_operand:SI 2 "gpc_reg_operand" "")))
5554 (const_int 32))))]
5555 "TARGET_POWERPC"
5556 "
5557{
5558 if (TARGET_POWER)
5559 {
5560 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5561 DONE;
5562 }
5563}")
5564
5565(define_insn "umulsi3_highpart_mq"
5566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5567 (truncate:SI
5568 (lshiftrt:DI (mult:DI (zero_extend:DI
5569 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5570 (zero_extend:DI
5571 (match_operand:SI 2 "gpc_reg_operand" "r")))
5572 (const_int 32))))
5573 (clobber (match_scratch:SI 3 "=q"))]
5574 "TARGET_POWERPC && TARGET_POWER"
5575 "mulhwu %0,%1,%2"
5576 [(set_attr "type" "imul")])
5577
5578(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 5579 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5580 (truncate:SI
5581 (lshiftrt:DI (mult:DI (zero_extend:DI
5582 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5583 (zero_extend:DI
5584 (match_operand:SI 2 "gpc_reg_operand" "r")))
5585 (const_int 32))))]
f192bf8b 5586 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 5587 "mulhwu %0,%1,%2"
5588 [(set_attr "type" "imul")])
5589
5590;; If operands 0 and 2 are in the same register, we have a problem. But
5591;; operands 0 and 1 (the usual case) can be in the same register. That's
5592;; why we have the strange constraints below.
5593(define_insn "ashldi3_power"
5594 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5595 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5596 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5597 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5598 "TARGET_POWER"
5599 "@
5600 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5601 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5602 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5603 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5604 [(set_attr "length" "8")])
5605
5606(define_insn "lshrdi3_power"
47ad8c61 5607 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 5608 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5609 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5610 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5611 "TARGET_POWER"
5612 "@
47ad8c61 5613 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 5614 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5615 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5616 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5617 [(set_attr "length" "8")])
5618
5619;; Shift by a variable amount is too complex to be worth open-coding. We
5620;; just handle shifts by constants.
5621(define_insn "ashrdi3_power"
7093ddee 5622 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 5623 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5624 (match_operand:SI 2 "const_int_operand" "M,i")))
5625 (clobber (match_scratch:SI 3 "=X,q"))]
5626 "TARGET_POWER"
5627 "@
5628 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5629 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5630 [(set_attr "length" "8")])
4aa74a4f
FS		 5631
5632(define_insn "ashrdi3_no_power"
5633 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5634 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5635 (match_operand:SI 2 "const_int_operand" "M,i")))]
683bdff7 5636 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER"
4aa74a4f
FS		 5637 "@
5638 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5639 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5640 [(set_attr "length" "8,12")])
683bdff7
FJ		 5641
5642(define_insn "*ashrdisi3_noppc64"
5643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5644 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5645 (const_int 32)) 4))]
5646 "TARGET_32BIT && !TARGET_POWERPC64"
5647 "*
5648{
5649 if (REGNO (operands[0]) == REGNO (operands[1]))
5650 return \"\";
5651 else
5652 return \"mr %0,%1\";
5653}"
5654 [(set_attr "length" "4")])
5655
266eb58a
DE		 5656\f
5657;; PowerPC64 DImode operations.
5658
5659(define_expand "adddi3"
5660 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5661 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
2bfcf297 5662 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
266eb58a
DE		 5663 ""
5664 "
5665{
a260abc9
DE		 5666 if (! TARGET_POWERPC64)
5667 {
5668 if (non_short_cint_operand (operands[2], DImode))
5669 FAIL;
5670 }
5671 else
5672 if (GET_CODE (operands[2]) == CONST_INT
677a9668 5673 && ! add_operand (operands[2], DImode))
a260abc9 5674 {
677a9668 5675 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 5676 ? operands[0] : gen_reg_rtx (DImode));
5677
2bfcf297 5678 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 5679 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 5680 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
a260abc9 5681
2bfcf297
DB		 5682 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5683 FAIL;
a260abc9 5684
2bfcf297
DB		 5685 /* The ordering here is important for the prolog expander.
5686 When space is allocated from the stack, adding 'low' first may
5687 produce a temporary deallocation (which would be bad). */
5688 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
a260abc9
DE		 5689 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5690 DONE;
5691 }
266eb58a
DE		 5692}")
5693
5694;; Discourage ai/addic because of carry but provide it in an alternative
5695;; allowing register zero as source.
5696
a260abc9 5697(define_insn "*adddi3_internal1"
266eb58a
DE		 5698 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5699 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
9615f239 5700 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
266eb58a
DE		 5701 "TARGET_POWERPC64"
5702 "@
5703 add %0,%1,%2
5704 addi %0,%1,%2
5705 addic %0,%1,%2
802a0058 5706 addis %0,%1,%v2")
266eb58a 5707
a260abc9 5708(define_insn "*adddi3_internal2"
9ebbca7d
GK		 5709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5710 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5711 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
266eb58a 5712 (const_int 0)))
9ebbca7d 5713 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 5714 "TARGET_64BIT"
266eb58a
DE		 5715 "@
5716 add. %3,%1,%2
9ebbca7d
GK		 5717 addic. %3,%1,%2
5718 #
5719 #"
a62bfff2 5720 [(set_attr "type" "fast_compare,compare,compare,compare")
9ebbca7d
GK		 5721 (set_attr "length" "4,4,8,8")])
5722
5723(define_split
5724 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5725 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5726 (match_operand:DI 2 "reg_or_short_operand" ""))
5727 (const_int 0)))
5728 (clobber (match_scratch:DI 3 ""))]
5729 "TARGET_POWERPC64 && reload_completed"
5730 [(set (match_dup 3)
5731 (plus:DI (match_dup 1) (match_dup 2)))
5732 (set (match_dup 0)
5733 (compare:CC (match_dup 3)
5734 (const_int 0)))]
5735 "")
266eb58a 5736
a260abc9 5737(define_insn "*adddi3_internal3"
9ebbca7d
GK		 5738 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5739 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5740 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
266eb58a 5741 (const_int 0)))
9ebbca7d 5742 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 5743 (plus:DI (match_dup 1) (match_dup 2)))]
683bdff7 5744 "TARGET_64BIT"
266eb58a
DE		 5745 "@
5746 add. %0,%1,%2
9ebbca7d
GK		 5747 addic. %0,%1,%2
5748 #
5749 #"
a62bfff2 5750 [(set_attr "type" "fast_compare,compare,compare,compare")
9ebbca7d
GK		 5751 (set_attr "length" "4,4,8,8")])
5752
5753(define_split
5754 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5755 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5756 (match_operand:DI 2 "reg_or_short_operand" ""))
5757 (const_int 0)))
5758 (set (match_operand:DI 0 "gpc_reg_operand" "")
5759 (plus:DI (match_dup 1) (match_dup 2)))]
5760 "TARGET_POWERPC64 && reload_completed"
5761 [(set (match_dup 0)
5762 (plus:DI (match_dup 1) (match_dup 2)))
5763 (set (match_dup 3)
5764 (compare:CC (match_dup 0)
5765 (const_int 0)))]
5766 "")
266eb58a
DE		 5767
5768;; Split an add that we can't do in one insn into two insns, each of which
5769;; does one 16-bit part. This is used by combine. Note that the low-order
5770;; add should be last in case the result gets used in an address.
5771
5772(define_split
5773 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5774 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5775 (match_operand:DI 2 "non_add_cint_operand" "")))]
5776 "TARGET_POWERPC64"
5777 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5778 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5779"
5780{
2bfcf297 5781 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 5782 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 5783 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
266eb58a 5784
2bfcf297
DB		 5785 operands[4] = GEN_INT (low);
5786 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5787 operands[3] = GEN_INT (rest);
5788 else if (! no_new_pseudos)
38886f37 5789 {
2bfcf297
DB		 5790 operands[3] = gen_reg_rtx (DImode);
5791 emit_move_insn (operands[3], operands[2]);
5792 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5793 DONE;
38886f37 5794 }
2bfcf297
DB		 5795 else
5796 FAIL;
266eb58a
DE		 5797}")
5798
5799(define_insn "one_cmpldi2"
5800 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5801 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5802 "TARGET_POWERPC64"
5803 "nor %0,%1,%1")
5804
5805(define_insn ""
9ebbca7d
GK		 5806 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5807 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
266eb58a 5808 (const_int 0)))
9ebbca7d 5809 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 5810 "TARGET_64BIT"
9ebbca7d
GK		 5811 "@
5812 nor. %2,%1,%1
5813 #"
5814 [(set_attr "type" "compare")
5815 (set_attr "length" "4,8")])
5816
5817(define_split
5818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5819 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5820 (const_int 0)))
5821 (clobber (match_scratch:DI 2 ""))]
5822 "TARGET_POWERPC64 && reload_completed"
5823 [(set (match_dup 2)
5824 (not:DI (match_dup 1)))
5825 (set (match_dup 0)
5826 (compare:CC (match_dup 2)
5827 (const_int 0)))]
5828 "")
266eb58a
DE		 5829
5830(define_insn ""
9ebbca7d
GK		 5831 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5832 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
266eb58a 5833 (const_int 0)))
9ebbca7d 5834 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 5835 (not:DI (match_dup 1)))]
683bdff7 5836 "TARGET_64BIT"
9ebbca7d
GK		 5837 "@
5838 nor. %0,%1,%1
5839 #"
5840 [(set_attr "type" "compare")
5841 (set_attr "length" "4,8")])
5842
5843(define_split
5844 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5845 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5846 (const_int 0)))
5847 (set (match_operand:DI 0 "gpc_reg_operand" "")
5848 (not:DI (match_dup 1)))]
5849 "TARGET_POWERPC64 && reload_completed"
5850 [(set (match_dup 0)
5851 (not:DI (match_dup 1)))
5852 (set (match_dup 2)
5853 (compare:CC (match_dup 0)
5854 (const_int 0)))]
5855 "")
266eb58a
DE		 5856
5857(define_insn ""
5858 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5859 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5860 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5861 "TARGET_POWERPC64"
5862 "@
5863 subf %0,%2,%1
5864 subfic %0,%2,%1")
5865
5866(define_insn ""
9ebbca7d
GK		 5867 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5868 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5869 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
266eb58a 5870 (const_int 0)))
9ebbca7d 5871 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 5872 "TARGET_64BIT"
9ebbca7d
GK		 5873 "@
5874 subf. %3,%2,%1
5875 #"
a62bfff2 5876 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 5877 (set_attr "length" "4,8")])
5878
5879(define_split
5880 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5881 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5882 (match_operand:DI 2 "gpc_reg_operand" ""))
5883 (const_int 0)))
5884 (clobber (match_scratch:DI 3 ""))]
5885 "TARGET_POWERPC64 && reload_completed"
5886 [(set (match_dup 3)
5887 (minus:DI (match_dup 1) (match_dup 2)))
5888 (set (match_dup 0)
5889 (compare:CC (match_dup 3)
5890 (const_int 0)))]
5891 "")
266eb58a
DE		 5892
5893(define_insn ""
9ebbca7d
GK		 5894 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5895 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5896 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
266eb58a 5897 (const_int 0)))
9ebbca7d 5898 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 5899 (minus:DI (match_dup 1) (match_dup 2)))]
683bdff7 5900 "TARGET_64BIT"
9ebbca7d
GK		 5901 "@
5902 subf. %0,%2,%1
5903 #"
a62bfff2 5904 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 5905 (set_attr "length" "4,8")])
5906
5907(define_split
5908 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5909 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5910 (match_operand:DI 2 "gpc_reg_operand" ""))
5911 (const_int 0)))
5912 (set (match_operand:DI 0 "gpc_reg_operand" "")
5913 (minus:DI (match_dup 1) (match_dup 2)))]
5914 "TARGET_POWERPC64 && reload_completed"
5915 [(set (match_dup 0)
5916 (minus:DI (match_dup 1) (match_dup 2)))
5917 (set (match_dup 3)
5918 (compare:CC (match_dup 0)
5919 (const_int 0)))]
5920 "")
266eb58a
DE		 5921
5922(define_expand "subdi3"
5923 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5924 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
2bfcf297 5925 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
266eb58a
DE		 5926 ""
5927 "
5928{
5929 if (GET_CODE (operands[2]) == CONST_INT)
5930 {
5931 emit_insn (gen_adddi3 (operands[0], operands[1],
5932 negate_rtx (DImode, operands[2])));
5933 DONE;
5934 }
5935}")
5936
ea112fc4 5937(define_insn_and_split "absdi2"
266eb58a 5938 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 5939 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 5940 (clobber (match_scratch:DI 2 "=&r,&r"))]
5941 "TARGET_POWERPC64"
ea112fc4
DE		 5942 "#"
5943 "&& reload_completed"
a260abc9 5944 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 5945 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 5946 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 5947 "")
5948
ea112fc4 5949(define_insn_and_split "*nabsdi2"
266eb58a 5950 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 5951 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 5952 (clobber (match_scratch:DI 2 "=&r,&r"))]
5953 "TARGET_POWERPC64"
ea112fc4
DE		 5954 "#"
5955 "&& reload_completed"
a260abc9 5956 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 5957 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 5958 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 5959 "")
5960
5961(define_expand "negdi2"
5962 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5963 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5964 ""
5965 "")
5966
5967(define_insn ""
5968 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5969 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5970 "TARGET_POWERPC64"
5971 "neg %0,%1")
5972
5973(define_insn ""
9ebbca7d
GK		 5974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5975 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
266eb58a 5976 (const_int 0)))
9ebbca7d 5977 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 5978 "TARGET_64BIT"
9ebbca7d
GK		 5979 "@
5980 neg. %2,%1
5981 #"
a62bfff2 5982 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 5983 (set_attr "length" "4,8")])
5984
5985(define_split
5986 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5987 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5988 (const_int 0)))
5989 (clobber (match_scratch:DI 2 ""))]
5990 "TARGET_POWERPC64 && reload_completed"
5991 [(set (match_dup 2)
5992 (neg:DI (match_dup 1)))
5993 (set (match_dup 0)
5994 (compare:CC (match_dup 2)
5995 (const_int 0)))]
5996 "")
815cdc52 5997
29ae5b89 5998(define_insn ""
9ebbca7d
GK		 5999 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6000 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
815cdc52 6001 (const_int 0)))
9ebbca7d 6002 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
815cdc52 6003 (neg:DI (match_dup 1)))]
683bdff7 6004 "TARGET_64BIT"
9ebbca7d
GK		 6005 "@
6006 neg. %0,%1
6007 #"
a62bfff2 6008 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 6009 (set_attr "length" "4,8")])
6010
6011(define_split
6012 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6013 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6014 (const_int 0)))
6015 (set (match_operand:DI 0 "gpc_reg_operand" "")
6016 (neg:DI (match_dup 1)))]
6017 "TARGET_POWERPC64 && reload_completed"
6018 [(set (match_dup 0)
6019 (neg:DI (match_dup 1)))
6020 (set (match_dup 2)
6021 (compare:CC (match_dup 0)
6022 (const_int 0)))]
6023 "")
266eb58a 6024
1b1edcfa
DE		 6025(define_insn "clzdi2"
6026 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6027 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6028 "TARGET_POWERPC64"
6029 "cntlzd %0,%1")
6030
6031(define_expand "ctzdi2"
4977bab6 6032 [(set (match_dup 2)
1b1edcfa 6033 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
4977bab6 6034 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
1b1edcfa
DE		 6035 (match_dup 2)))
6036 (clobber (scratch:CC))])
d865b122 6037 (set (match_dup 4) (clz:DI (match_dup 3)))
4977bab6 6038 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
1b1edcfa 6039 (minus:DI (const_int 63) (match_dup 4)))]
266eb58a 6040 "TARGET_POWERPC64"
4977bab6
ZW		 6041 {
6042 operands[2] = gen_reg_rtx (DImode);
6043 operands[3] = gen_reg_rtx (DImode);
6044 operands[4] = gen_reg_rtx (DImode);
6045 })
6046
1b1edcfa
DE		 6047(define_expand "ffsdi2"
6048 [(set (match_dup 2)
6049 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6050 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6051 (match_dup 2)))
6052 (clobber (scratch:CC))])
6053 (set (match_dup 4) (clz:DI (match_dup 3)))
6054 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6055 (minus:DI (const_int 64) (match_dup 4)))]
4977bab6 6056 "TARGET_POWERPC64"
1b1edcfa
DE		 6057 {
6058 operands[2] = gen_reg_rtx (DImode);
6059 operands[3] = gen_reg_rtx (DImode);
6060 operands[4] = gen_reg_rtx (DImode);
6061 })
266eb58a
DE		 6062
6063(define_insn "muldi3"
6064 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6065 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6066 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6067 "TARGET_POWERPC64"
6068 "mulld %0,%1,%2"
3cb999d8 6069 [(set_attr "type" "lmul")])
266eb58a 6070
9259f3b0
DE		 6071(define_insn "*muldi3_internal1"
6072 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6073 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6074 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6075 (const_int 0)))
6076 (clobber (match_scratch:DI 3 "=r,r"))]
6077 "TARGET_POWERPC64"
6078 "@
6079 mulld. %3,%1,%2
6080 #"
6081 [(set_attr "type" "lmul_compare")
6082 (set_attr "length" "4,8")])
6083
6084(define_split
6085 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6086 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6087 (match_operand:DI 2 "gpc_reg_operand" ""))
6088 (const_int 0)))
6089 (clobber (match_scratch:DI 3 ""))]
6090 "TARGET_POWERPC64 && reload_completed"
6091 [(set (match_dup 3)
6092 (mult:DI (match_dup 1) (match_dup 2)))
6093 (set (match_dup 0)
6094 (compare:CC (match_dup 3)
6095 (const_int 0)))]
6096 "")
6097
6098(define_insn "*muldi3_internal2"
6099 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6100 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6101 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6102 (const_int 0)))
6103 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6104 (mult:DI (match_dup 1) (match_dup 2)))]
6105 "TARGET_POWERPC64"
6106 "@
6107 mulld. %0,%1,%2
6108 #"
6109 [(set_attr "type" "lmul_compare")
6110 (set_attr "length" "4,8")])
6111
6112(define_split
6113 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6114 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6115 (match_operand:DI 2 "gpc_reg_operand" ""))
6116 (const_int 0)))
6117 (set (match_operand:DI 0 "gpc_reg_operand" "")
6118 (mult:DI (match_dup 1) (match_dup 2)))]
6119 "TARGET_POWERPC64 && reload_completed"
6120 [(set (match_dup 0)
6121 (mult:DI (match_dup 1) (match_dup 2)))
6122 (set (match_dup 3)
6123 (compare:CC (match_dup 0)
6124 (const_int 0)))]
6125 "")
6126
266eb58a
DE		 6127(define_insn "smuldi3_highpart"
6128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6129 (truncate:DI
6130 (lshiftrt:TI (mult:TI (sign_extend:TI
6131 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6132 (sign_extend:TI
6133 (match_operand:DI 2 "gpc_reg_operand" "r")))
6134 (const_int 64))))]
6135 "TARGET_POWERPC64"
6136 "mulhd %0,%1,%2"
3cb999d8 6137 [(set_attr "type" "lmul")])
266eb58a
DE		 6138
6139(define_insn "umuldi3_highpart"
6140 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6141 (truncate:DI
6142 (lshiftrt:TI (mult:TI (zero_extend:TI
6143 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6144 (zero_extend:TI
6145 (match_operand:DI 2 "gpc_reg_operand" "r")))
6146 (const_int 64))))]
6147 "TARGET_POWERPC64"
6148 "mulhdu %0,%1,%2"
3cb999d8 6149 [(set_attr "type" "lmul")])
266eb58a
DE		 6150
6151(define_expand "divdi3"
6152 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6153 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6154 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6155 "TARGET_POWERPC64"
6156 "
6157{
6158 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 6159 && INTVAL (operands[2]) > 0
266eb58a
DE		 6160 && exact_log2 (INTVAL (operands[2])) >= 0)
6161 ;
6162 else
6163 operands[2] = force_reg (DImode, operands[2]);
6164}")
6165
6166(define_expand "moddi3"
6167 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6168 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6169 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6170 "TARGET_POWERPC64"
6171 "
6172{
2bfcf297 6173 int i;
266eb58a
DE		 6174 rtx temp1;
6175 rtx temp2;
6176
2bfcf297
DB		 6177 if (GET_CODE (operands[2]) != CONST_INT
6178 || INTVAL (operands[2]) <= 0
6179 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
266eb58a
DE		 6180 FAIL;
6181
6182 temp1 = gen_reg_rtx (DImode);
6183 temp2 = gen_reg_rtx (DImode);
6184
6185 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6186 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6187 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6188 DONE;
6189}")
6190
6191(define_insn ""
6192 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6193 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2bfcf297
DB		 6194 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6195 "TARGET_POWERPC64"
266eb58a
DE		 6196 "sradi %0,%1,%p2\;addze %0,%0"
6197 [(set_attr "length" "8")])
6198
6199(define_insn ""
9ebbca7d
GK		 6200 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6201 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
2bfcf297 6202 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
266eb58a 6203 (const_int 0)))
9ebbca7d 6204 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6205 "TARGET_64BIT"
9ebbca7d
GK		 6206 "@
6207 sradi %3,%1,%p2\;addze. %3,%3
6208 #"
266eb58a 6209 [(set_attr "type" "compare")
9ebbca7d
GK		 6210 (set_attr "length" "8,12")])
6211
6212(define_split
6213 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6214 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
2bfcf297 6215 (match_operand:DI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 6216 (const_int 0)))
6217 (clobber (match_scratch:DI 3 ""))]
2bfcf297 6218 "TARGET_POWERPC64 && reload_completed"
9ebbca7d
GK		 6219 [(set (match_dup 3)
6220 (div:DI (match_dup 1) (match_dup 2)))
6221 (set (match_dup 0)
6222 (compare:CC (match_dup 3)
6223 (const_int 0)))]
6224 "")
266eb58a
DE		 6225
6226(define_insn ""
9ebbca7d
GK		 6227 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6228 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
2bfcf297 6229 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
266eb58a 6230 (const_int 0)))
9ebbca7d 6231 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 6232 (div:DI (match_dup 1) (match_dup 2)))]
683bdff7 6233 "TARGET_64BIT"
9ebbca7d
GK		 6234 "@
6235 sradi %0,%1,%p2\;addze. %0,%0
6236 #"
266eb58a 6237 [(set_attr "type" "compare")
9ebbca7d 6238 (set_attr "length" "8,12")])
266eb58a 6239
9ebbca7d
GK		 6240(define_split
6241 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6242 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
2bfcf297 6243 (match_operand:DI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 6244 (const_int 0)))
6245 (set (match_operand:DI 0 "gpc_reg_operand" "")
6246 (div:DI (match_dup 1) (match_dup 2)))]
2bfcf297 6247 "TARGET_POWERPC64 && reload_completed"
9ebbca7d
GK		 6248 [(set (match_dup 0)
6249 (div:DI (match_dup 1) (match_dup 2)))
6250 (set (match_dup 3)
6251 (compare:CC (match_dup 0)
6252 (const_int 0)))]
6253 "")
6254
6255(define_insn ""
6256 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
266eb58a 6257 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a260abc9 6258 (match_operand:DI 2 "gpc_reg_operand" "r")))]
266eb58a
DE		 6259 "TARGET_POWERPC64"
6260 "divd %0,%1,%2"
3cb999d8 6261 [(set_attr "type" "ldiv")])
266eb58a
DE		 6262
6263(define_insn "udivdi3"
6264 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6265 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6266 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6267 "TARGET_POWERPC64"
6268 "divdu %0,%1,%2"
3cb999d8 6269 [(set_attr "type" "ldiv")])
266eb58a
DE		 6270
6271(define_insn "rotldi3"
6272 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6273 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6274 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6275 "TARGET_POWERPC64"
a66078ee 6276 "rld%I2cl %0,%1,%H2,0")
266eb58a 6277
a260abc9 6278(define_insn "*rotldi3_internal2"
9ebbca7d
GK		 6279 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6280 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6281 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6282 (const_int 0)))
9ebbca7d 6283 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6284 "TARGET_64BIT"
9ebbca7d
GK		 6285 "@
6286 rld%I2cl. %3,%1,%H2,0
6287 #"
6288 [(set_attr "type" "delayed_compare")
6289 (set_attr "length" "4,8")])
6290
6291(define_split
6292 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6293 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6294 (match_operand:DI 2 "reg_or_cint_operand" ""))
6295 (const_int 0)))
6296 (clobber (match_scratch:DI 3 ""))]
6297 "TARGET_POWERPC64 && reload_completed"
6298 [(set (match_dup 3)
6299 (rotate:DI (match_dup 1) (match_dup 2)))
6300 (set (match_dup 0)
6301 (compare:CC (match_dup 3)
6302 (const_int 0)))]
6303 "")
266eb58a 6304
a260abc9 6305(define_insn "*rotldi3_internal3"
9ebbca7d
GK		 6306 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6307 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6308 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6309 (const_int 0)))
9ebbca7d 6310 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 6311 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 6312 "TARGET_64BIT"
9ebbca7d
GK		 6313 "@
6314 rld%I2cl. %0,%1,%H2,0
6315 #"
6316 [(set_attr "type" "delayed_compare")
6317 (set_attr "length" "4,8")])
6318
6319(define_split
6320 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6321 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6322 (match_operand:DI 2 "reg_or_cint_operand" ""))
6323 (const_int 0)))
6324 (set (match_operand:DI 0 "gpc_reg_operand" "")
6325 (rotate:DI (match_dup 1) (match_dup 2)))]
6326 "TARGET_POWERPC64 && reload_completed"
6327 [(set (match_dup 0)
6328 (rotate:DI (match_dup 1) (match_dup 2)))
6329 (set (match_dup 3)
6330 (compare:CC (match_dup 0)
6331 (const_int 0)))]
6332 "")
266eb58a 6333
a260abc9
DE		 6334(define_insn "*rotldi3_internal4"
6335 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6336 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6337 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
ce71f754 6338 (match_operand:DI 3 "mask64_operand" "n")))]
a260abc9
DE		 6339 "TARGET_POWERPC64"
6340 "rld%I2c%B3 %0,%1,%H2,%S3")
6341
6342(define_insn "*rotldi3_internal5"
9ebbca7d 6343 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9 6344 (compare:CC (and:DI
9ebbca7d
GK		 6345 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6346 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 6347 (match_operand:DI 3 "mask64_operand" "n,n"))
a260abc9 6348 (const_int 0)))
9ebbca7d 6349 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 6350 "TARGET_64BIT"
9ebbca7d
GK		 6351 "@
6352 rld%I2c%B3. %4,%1,%H2,%S3
6353 #"
6354 [(set_attr "type" "delayed_compare")
6355 (set_attr "length" "4,8")])
6356
6357(define_split
6358 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6359 (compare:CC (and:DI
6360 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6361 (match_operand:DI 2 "reg_or_cint_operand" ""))
6362 (match_operand:DI 3 "mask64_operand" ""))
6363 (const_int 0)))
6364 (clobber (match_scratch:DI 4 ""))]
6365 "TARGET_POWERPC64 && reload_completed"
6366 [(set (match_dup 4)
6367 (and:DI (rotate:DI (match_dup 1)
6368 (match_dup 2))
6369 (match_dup 3)))
6370 (set (match_dup 0)
6371 (compare:CC (match_dup 4)
6372 (const_int 0)))]
6373 "")
a260abc9
DE		 6374
6375(define_insn "*rotldi3_internal6"
9ebbca7d 6376 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9 6377 (compare:CC (and:DI
9ebbca7d
GK		 6378 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6379 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 6380 (match_operand:DI 3 "mask64_operand" "n,n"))
a260abc9 6381 (const_int 0)))
9ebbca7d 6382 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6383 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6384 "TARGET_64BIT"
9ebbca7d
GK		 6385 "@
6386 rld%I2c%B3. %0,%1,%H2,%S3
6387 #"
6388 [(set_attr "type" "delayed_compare")
6389 (set_attr "length" "4,8")])
6390
6391(define_split
6392 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6393 (compare:CC (and:DI
6394 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6395 (match_operand:DI 2 "reg_or_cint_operand" ""))
6396 (match_operand:DI 3 "mask64_operand" ""))
6397 (const_int 0)))
6398 (set (match_operand:DI 0 "gpc_reg_operand" "")
6399 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6400 "TARGET_POWERPC64 && reload_completed"
6401 [(set (match_dup 0)
6402 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6403 (set (match_dup 4)
6404 (compare:CC (match_dup 0)
6405 (const_int 0)))]
6406 "")
a260abc9
DE		 6407
6408(define_insn "*rotldi3_internal7"
6409 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6410 (zero_extend:DI
6411 (subreg:QI
6412 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6413 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6414 "TARGET_POWERPC64"
6415 "rld%I2cl %0,%1,%H2,56")
6416
6417(define_insn "*rotldi3_internal8"
9ebbca7d 6418 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6419 (compare:CC (zero_extend:DI
6420 (subreg:QI
9ebbca7d
GK		 6421 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6422 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6423 (const_int 0)))
9ebbca7d 6424 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6425 "TARGET_64BIT"
9ebbca7d
GK		 6426 "@
6427 rld%I2cl. %3,%1,%H2,56
6428 #"
6429 [(set_attr "type" "delayed_compare")
6430 (set_attr "length" "4,8")])
6431
6432(define_split
6433 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6434 (compare:CC (zero_extend:DI
6435 (subreg:QI
6436 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6437 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6438 (const_int 0)))
6439 (clobber (match_scratch:DI 3 ""))]
6440 "TARGET_POWERPC64 && reload_completed"
6441 [(set (match_dup 3)
6442 (zero_extend:DI (subreg:QI
6443 (rotate:DI (match_dup 1)
6444 (match_dup 2)) 0)))
6445 (set (match_dup 0)
6446 (compare:CC (match_dup 3)
6447 (const_int 0)))]
6448 "")
a260abc9
DE		 6449
6450(define_insn "*rotldi3_internal9"
9ebbca7d 6451 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6452 (compare:CC (zero_extend:DI
6453 (subreg:QI
9ebbca7d
GK		 6454 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6455 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6456 (const_int 0)))
9ebbca7d 6457 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6458 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6459 "TARGET_64BIT"
9ebbca7d
GK		 6460 "@
6461 rld%I2cl. %0,%1,%H2,56
6462 #"
6463 [(set_attr "type" "delayed_compare")
6464 (set_attr "length" "4,8")])
6465
6466(define_split
6467 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6468 (compare:CC (zero_extend:DI
6469 (subreg:QI
6470 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6471 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6472 (const_int 0)))
6473 (set (match_operand:DI 0 "gpc_reg_operand" "")
6474 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6475 "TARGET_POWERPC64 && reload_completed"
6476 [(set (match_dup 0)
6477 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6478 (set (match_dup 3)
6479 (compare:CC (match_dup 0)
6480 (const_int 0)))]
6481 "")
a260abc9
DE		 6482
6483(define_insn "*rotldi3_internal10"
6484 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6485 (zero_extend:DI
6486 (subreg:HI
6487 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6488 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6489 "TARGET_POWERPC64"
6490 "rld%I2cl %0,%1,%H2,48")
6491
6492(define_insn "*rotldi3_internal11"
9ebbca7d 6493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6494 (compare:CC (zero_extend:DI
6495 (subreg:HI
9ebbca7d
GK		 6496 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6497 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6498 (const_int 0)))
9ebbca7d 6499 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6500 "TARGET_64BIT"
9ebbca7d
GK		 6501 "@
6502 rld%I2cl. %3,%1,%H2,48
6503 #"
6504 [(set_attr "type" "delayed_compare")
6505 (set_attr "length" "4,8")])
6506
6507(define_split
6508 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6509 (compare:CC (zero_extend:DI
6510 (subreg:HI
6511 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6512 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6513 (const_int 0)))
6514 (clobber (match_scratch:DI 3 ""))]
6515 "TARGET_POWERPC64 && reload_completed"
6516 [(set (match_dup 3)
6517 (zero_extend:DI (subreg:HI
6518 (rotate:DI (match_dup 1)
6519 (match_dup 2)) 0)))
6520 (set (match_dup 0)
6521 (compare:CC (match_dup 3)
6522 (const_int 0)))]
6523 "")
a260abc9
DE		 6524
6525(define_insn "*rotldi3_internal12"
9ebbca7d 6526 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6527 (compare:CC (zero_extend:DI
6528 (subreg:HI
9ebbca7d
GK		 6529 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6530 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6531 (const_int 0)))
9ebbca7d 6532 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6533 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6534 "TARGET_64BIT"
9ebbca7d
GK		 6535 "@
6536 rld%I2cl. %0,%1,%H2,48
6537 #"
6538 [(set_attr "type" "delayed_compare")
6539 (set_attr "length" "4,8")])
6540
6541(define_split
6542 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6543 (compare:CC (zero_extend:DI
6544 (subreg:HI
6545 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6546 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6547 (const_int 0)))
6548 (set (match_operand:DI 0 "gpc_reg_operand" "")
6549 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6550 "TARGET_POWERPC64 && reload_completed"
6551 [(set (match_dup 0)
6552 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6553 (set (match_dup 3)
6554 (compare:CC (match_dup 0)
6555 (const_int 0)))]
6556 "")
a260abc9
DE		 6557
6558(define_insn "*rotldi3_internal13"
6559 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6560 (zero_extend:DI
6561 (subreg:SI
6562 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6563 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6564 "TARGET_POWERPC64"
6565 "rld%I2cl %0,%1,%H2,32")
6566
6567(define_insn "*rotldi3_internal14"
9ebbca7d 6568 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6569 (compare:CC (zero_extend:DI
6570 (subreg:SI
9ebbca7d
GK		 6571 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6572 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6573 (const_int 0)))
9ebbca7d 6574 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6575 "TARGET_64BIT"
9ebbca7d
GK		 6576 "@
6577 rld%I2cl. %3,%1,%H2,32
6578 #"
6579 [(set_attr "type" "delayed_compare")
6580 (set_attr "length" "4,8")])
6581
6582(define_split
6583 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6584 (compare:CC (zero_extend:DI
6585 (subreg:SI
6586 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6587 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6588 (const_int 0)))
6589 (clobber (match_scratch:DI 3 ""))]
6590 "TARGET_POWERPC64 && reload_completed"
6591 [(set (match_dup 3)
6592 (zero_extend:DI (subreg:SI
6593 (rotate:DI (match_dup 1)
6594 (match_dup 2)) 0)))
6595 (set (match_dup 0)
6596 (compare:CC (match_dup 3)
6597 (const_int 0)))]
6598 "")
a260abc9
DE		 6599
6600(define_insn "*rotldi3_internal15"
9ebbca7d 6601 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6602 (compare:CC (zero_extend:DI
6603 (subreg:SI
9ebbca7d
GK		 6604 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6605 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6606 (const_int 0)))
9ebbca7d 6607 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6608 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6609 "TARGET_64BIT"
9ebbca7d
GK		 6610 "@
6611 rld%I2cl. %0,%1,%H2,32
6612 #"
6613 [(set_attr "type" "delayed_compare")
6614 (set_attr "length" "4,8")])
6615
6616(define_split
6617 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6618 (compare:CC (zero_extend:DI
6619 (subreg:SI
6620 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6621 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6622 (const_int 0)))
6623 (set (match_operand:DI 0 "gpc_reg_operand" "")
6624 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6625 "TARGET_POWERPC64 && reload_completed"
6626 [(set (match_dup 0)
6627 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6628 (set (match_dup 3)
6629 (compare:CC (match_dup 0)
6630 (const_int 0)))]
6631 "")
a260abc9 6632
266eb58a
DE		 6633(define_expand "ashldi3"
6634 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6635 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6636 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6637 "TARGET_POWERPC64 || TARGET_POWER"
6638 "
6639{
6640 if (TARGET_POWERPC64)
6641 ;
6642 else if (TARGET_POWER)
6643 {
6644 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6645 DONE;
6646 }
6647 else
6648 FAIL;
6649}")
6650
e2c953b6 6651(define_insn "*ashldi3_internal1"
266eb58a
DE		 6652 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6653 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6654 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6655 "TARGET_POWERPC64"
a66078ee 6656 "sld%I2 %0,%1,%H2"
266eb58a
DE		 6657 [(set_attr "length" "8")])
6658
e2c953b6 6659(define_insn "*ashldi3_internal2"
9ebbca7d
GK		 6660 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6661 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6662 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6663 (const_int 0)))
9ebbca7d 6664 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6665 "TARGET_64BIT"
9ebbca7d
GK		 6666 "@
6667 sld%I2. %3,%1,%H2
6668 #"
6669 [(set_attr "type" "delayed_compare")
6670 (set_attr "length" "4,8")])
29ae5b89 6671
9ebbca7d
GK		 6672(define_split
6673 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6674 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6675 (match_operand:SI 2 "reg_or_cint_operand" ""))
6676 (const_int 0)))
6677 (clobber (match_scratch:DI 3 ""))]
6678 "TARGET_POWERPC64 && reload_completed"
6679 [(set (match_dup 3)
6680 (ashift:DI (match_dup 1) (match_dup 2)))
6681 (set (match_dup 0)
6682 (compare:CC (match_dup 3)
6683 (const_int 0)))]
6684 "")
6685
e2c953b6 6686(define_insn "*ashldi3_internal3"
9ebbca7d
GK		 6687 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6688 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6689 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6690 (const_int 0)))
9ebbca7d 6691 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 6692 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 6693 "TARGET_64BIT"
9ebbca7d
GK		 6694 "@
6695 sld%I2. %0,%1,%H2
6696 #"
6697 [(set_attr "type" "delayed_compare")
6698 (set_attr "length" "4,8")])
6699
6700(define_split
6701 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6702 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6703 (match_operand:SI 2 "reg_or_cint_operand" ""))
6704 (const_int 0)))
6705 (set (match_operand:DI 0 "gpc_reg_operand" "")
6706 (ashift:DI (match_dup 1) (match_dup 2)))]
6707 "TARGET_POWERPC64 && reload_completed"
6708 [(set (match_dup 0)
6709 (ashift:DI (match_dup 1) (match_dup 2)))
6710 (set (match_dup 3)
6711 (compare:CC (match_dup 0)
6712 (const_int 0)))]
6713 "")
266eb58a 6714
e2c953b6 6715(define_insn "*ashldi3_internal4"
3cb999d8
DE		 6716 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6717 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6718 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 6719 (match_operand:DI 3 "const_int_operand" "n")))]
6720 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 6721 "rldic %0,%1,%H2,%W3")
3cb999d8 6722
e2c953b6 6723(define_insn "ashldi3_internal5"
9ebbca7d 6724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 6725 (compare:CC
9ebbca7d
GK		 6726 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6727 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 6728 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 6729 (const_int 0)))
9ebbca7d 6730 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 6731 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 6732 "@
e2c953b6 6733 rldic. %4,%1,%H2,%W3
9ebbca7d
GK		 6734 #"
6735 [(set_attr "type" "delayed_compare")
6736 (set_attr "length" "4,8")])
6737
6738(define_split
6739 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6740 (compare:CC
6741 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6742 (match_operand:SI 2 "const_int_operand" ""))
c5059423 6743 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 6744 (const_int 0)))
6745 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 6746 "TARGET_POWERPC64 && reload_completed
6747 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 6748 [(set (match_dup 4)
6749 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 6750 (match_dup 3)))
9ebbca7d
GK		 6751 (set (match_dup 0)
6752 (compare:CC (match_dup 4)
6753 (const_int 0)))]
6754 "")
3cb999d8 6755
e2c953b6 6756(define_insn "*ashldi3_internal6"
9ebbca7d 6757 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 6758 (compare:CC
9ebbca7d
GK		 6759 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6760 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 6761 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 6762 (const_int 0)))
9ebbca7d 6763 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 6764 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6765 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 6766 "@
e2c953b6 6767 rldic. %0,%1,%H2,%W3
9ebbca7d
GK		 6768 #"
6769 [(set_attr "type" "delayed_compare")
6770 (set_attr "length" "4,8")])
6771
6772(define_split
6773 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6774 (compare:CC
6775 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6776 (match_operand:SI 2 "const_int_operand" ""))
c5059423 6777 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 6778 (const_int 0)))
6779 (set (match_operand:DI 0 "gpc_reg_operand" "")
6780 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 6781 "TARGET_POWERPC64 && reload_completed
6782 && includes_rldic_lshift_p (operands[2], operands[3])"
6783 [(set (match_dup 0)
6784 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6785 (match_dup 3)))
6786 (set (match_dup 4)
6787 (compare:CC (match_dup 0)
6788 (const_int 0)))]
6789 "")
6790
6791(define_insn "*ashldi3_internal7"
6792 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6793 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6794 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 6795 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 6796 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6797 "rldicr %0,%1,%H2,%S3")
6798
6799(define_insn "ashldi3_internal8"
6800 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6801 (compare:CC
6802 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6803 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 6804 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 6805 (const_int 0)))
6806 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 6807 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 6808 "@
6809 rldicr. %4,%1,%H2,%S3
6810 #"
6811 [(set_attr "type" "delayed_compare")
6812 (set_attr "length" "4,8")])
6813
6814(define_split
6815 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6816 (compare:CC
6817 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6818 (match_operand:SI 2 "const_int_operand" ""))
6819 (match_operand:DI 3 "mask64_operand" ""))
6820 (const_int 0)))
6821 (clobber (match_scratch:DI 4 ""))]
6822 "TARGET_POWERPC64 && reload_completed
6823 && includes_rldicr_lshift_p (operands[2], operands[3])"
6824 [(set (match_dup 4)
6825 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6826 (match_dup 3)))
6827 (set (match_dup 0)
6828 (compare:CC (match_dup 4)
6829 (const_int 0)))]
6830 "")
6831
6832(define_insn "*ashldi3_internal9"
6833 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6834 (compare:CC
6835 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6836 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 6837 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 6838 (const_int 0)))
6839 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6840 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6841 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 6842 "@
6843 rldicr. %0,%1,%H2,%S3
6844 #"
6845 [(set_attr "type" "delayed_compare")
6846 (set_attr "length" "4,8")])
6847
6848(define_split
6849 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6850 (compare:CC
6851 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6852 (match_operand:SI 2 "const_int_operand" ""))
6853 (match_operand:DI 3 "mask64_operand" ""))
6854 (const_int 0)))
6855 (set (match_operand:DI 0 "gpc_reg_operand" "")
6856 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6857 "TARGET_POWERPC64 && reload_completed
6858 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 6859 [(set (match_dup 0)
e2c953b6
DE		 6860 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6861 (match_dup 3)))
9ebbca7d
GK		 6862 (set (match_dup 4)
6863 (compare:CC (match_dup 0)
6864 (const_int 0)))]
6865 "")
6866
6867(define_expand "lshrdi3"
266eb58a
DE		 6868 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6869 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6870 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6871 "TARGET_POWERPC64 || TARGET_POWER"
6872 "
6873{
6874 if (TARGET_POWERPC64)
6875 ;
6876 else if (TARGET_POWER)
6877 {
6878 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6879 DONE;
6880 }
6881 else
6882 FAIL;
6883}")
6884
e2c953b6 6885(define_insn "*lshrdi3_internal1"
266eb58a
DE		 6886 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6887 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6888 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6889 "TARGET_POWERPC64"
a66078ee 6890 "srd%I2 %0,%1,%H2")
266eb58a 6891
e2c953b6 6892(define_insn "*lshrdi3_internal2"
9ebbca7d
GK		 6893 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6894 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6895 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
29ae5b89 6896 (const_int 0)))
9ebbca7d 6897 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6898 "TARGET_64BIT "
9ebbca7d
GK		 6899 "@
6900 srd%I2. %3,%1,%H2
6901 #"
6902 [(set_attr "type" "delayed_compare")
6903 (set_attr "length" "4,8")])
6904
6905(define_split
6906 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6907 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6908 (match_operand:SI 2 "reg_or_cint_operand" ""))
6909 (const_int 0)))
6910 (clobber (match_scratch:DI 3 ""))]
6911 "TARGET_POWERPC64 && reload_completed"
6912 [(set (match_dup 3)
6913 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6914 (set (match_dup 0)
6915 (compare:CC (match_dup 3)
6916 (const_int 0)))]
6917 "")
266eb58a 6918
e2c953b6 6919(define_insn "*lshrdi3_internal3"
9ebbca7d
GK		 6920 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6921 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6922 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6923 (const_int 0)))
9ebbca7d 6924 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
29ae5b89 6925 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 6926 "TARGET_64BIT"
9ebbca7d
GK		 6927 "@
6928 srd%I2. %0,%1,%H2
6929 #"
6930 [(set_attr "type" "delayed_compare")
6931 (set_attr "length" "4,8")])
6932
6933(define_split
6934 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6935 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6936 (match_operand:SI 2 "reg_or_cint_operand" ""))
6937 (const_int 0)))
6938 (set (match_operand:DI 0 "gpc_reg_operand" "")
6939 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6940 "TARGET_POWERPC64 && reload_completed"
6941 [(set (match_dup 0)
6942 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6943 (set (match_dup 3)
6944 (compare:CC (match_dup 0)
6945 (const_int 0)))]
6946 "")
266eb58a
DE		 6947
6948(define_expand "ashrdi3"
6949 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6950 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6951 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4aa74a4f 6952 ""
266eb58a
DE		 6953 "
6954{
6955 if (TARGET_POWERPC64)
6956 ;
6957 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6958 {
6959 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6960 DONE;
6961 }
4aa74a4f
FS		 6962 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT)
6963 {
6964 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6965 DONE;
6966 }
266eb58a
DE		 6967 else
6968 FAIL;
6969}")
6970
e2c953b6 6971(define_insn "*ashrdi3_internal1"
266eb58a
DE		 6972 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6973 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6974 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6975 "TARGET_POWERPC64"
375490e0 6976 "srad%I2 %0,%1,%H2")
266eb58a 6977
e2c953b6 6978(define_insn "*ashrdi3_internal2"
9ebbca7d
GK		 6979 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6980 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6981 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6982 (const_int 0)))
9ebbca7d 6983 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6984 "TARGET_64BIT"
9ebbca7d
GK		 6985 "@
6986 srad%I2. %3,%1,%H2
6987 #"
6988 [(set_attr "type" "delayed_compare")
6989 (set_attr "length" "4,8")])
6990
6991(define_split
6992 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6993 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6994 (match_operand:SI 2 "reg_or_cint_operand" ""))
6995 (const_int 0)))
6996 (clobber (match_scratch:DI 3 ""))]
6997 "TARGET_POWERPC64 && reload_completed"
6998 [(set (match_dup 3)
6999 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7000 (set (match_dup 0)
7001 (compare:CC (match_dup 3)
7002 (const_int 0)))]
7003 "")
266eb58a 7004
e2c953b6 7005(define_insn "*ashrdi3_internal3"
9ebbca7d
GK		 7006 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7007 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7008 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 7009 (const_int 0)))
9ebbca7d 7010 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 7011 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7012 "TARGET_64BIT"
9ebbca7d
GK		 7013 "@
7014 srad%I2. %0,%1,%H2
7015 #"
7016 [(set_attr "type" "delayed_compare")
7017 (set_attr "length" "4,8")])
7018
7019(define_split
7020 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7021 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7022 (match_operand:SI 2 "reg_or_cint_operand" ""))
7023 (const_int 0)))
7024 (set (match_operand:DI 0 "gpc_reg_operand" "")
7025 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7026 "TARGET_POWERPC64 && reload_completed"
7027 [(set (match_dup 0)
7028 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7029 (set (match_dup 3)
7030 (compare:CC (match_dup 0)
7031 (const_int 0)))]
7032 "")
815cdc52 7033
29ae5b89 7034(define_insn "anddi3"
0ba1b2ff
AM		 7035 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
7036 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
7037 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
7038 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
6ffc8580 7039 "TARGET_POWERPC64"
266eb58a
DE		 7040 "@
7041 and %0,%1,%2
29ae5b89
JL		 7042 rldic%B2 %0,%1,0,%S2
7043 andi. %0,%1,%b2
0ba1b2ff
AM		 7044 andis. %0,%1,%u2
7045 #"
7046 [(set_attr "length" "4,4,4,4,8")])
7047
7048(define_split
7049 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7050 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7051 (match_operand:DI 2 "mask64_2_operand" "")))
7052 (clobber (match_scratch:CC 3 ""))]
7053 "TARGET_POWERPC64
7054 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7055 && !mask64_operand (operands[2], DImode)"
7056 [(set (match_dup 0)
7057 (and:DI (rotate:DI (match_dup 1)
7058 (match_dup 4))
7059 (match_dup 5)))
7060 (set (match_dup 0)
7061 (and:DI (rotate:DI (match_dup 0)
7062 (match_dup 6))
7063 (match_dup 7)))]
7064 "
7065{
7066 build_mask64_2_operands (operands[2], &operands[4]);
7067}")
266eb58a 7068
a260abc9 7069(define_insn "*anddi3_internal2"
0ba1b2ff
AM		 7070 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7071 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7072 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
266eb58a 7073 (const_int 0)))
0ba1b2ff
AM		 7074 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7075 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7076 "TARGET_64BIT"
266eb58a
DE		 7077 "@
7078 and. %3,%1,%2
6c873122 7079 rldic%B2. %3,%1,0,%S2
6ffc8580
MM		 7080 andi. %3,%1,%b2
7081 andis. %3,%1,%u2
9ebbca7d
GK		 7082 #
7083 #
7084 #
0ba1b2ff
AM		 7085 #
7086 #
9ebbca7d 7087 #"
0ba1b2ff
AM		 7088 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7089 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
9ebbca7d
GK		 7090
7091(define_split
7092 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7093 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7094 (match_operand:DI 2 "and64_operand" ""))
7095 (const_int 0)))
7096 (clobber (match_scratch:DI 3 ""))
7097 (clobber (match_scratch:CC 4 ""))]
7098 "TARGET_POWERPC64 && reload_completed"
7099 [(parallel [(set (match_dup 3)
7100 (and:DI (match_dup 1)
7101 (match_dup 2)))
7102 (clobber (match_dup 4))])
7103 (set (match_dup 0)
7104 (compare:CC (match_dup 3)
7105 (const_int 0)))]
7106 "")
266eb58a 7107
0ba1b2ff
AM		 7108(define_split
7109 [(set (match_operand:CC 0 "cc_reg_operand" "")
7110 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7111 (match_operand:DI 2 "mask64_2_operand" ""))
7112 (const_int 0)))
7113 (clobber (match_scratch:DI 3 ""))
7114 (clobber (match_scratch:CC 4 ""))]
7115 "TARGET_POWERPC64 && reload_completed
7116 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7117 && !mask64_operand (operands[2], DImode)"
7118 [(set (match_dup 3)
7119 (and:DI (rotate:DI (match_dup 1)
7120 (match_dup 5))
7121 (match_dup 6)))
7122 (parallel [(set (match_dup 0)
7123 (compare:CC (and:DI (rotate:DI (match_dup 3)
7124 (match_dup 7))
7125 (match_dup 8))
7126 (const_int 0)))
7127 (clobber (match_dup 3))])]
7128 "
7129{
7130 build_mask64_2_operands (operands[2], &operands[5]);
7131}")
7132
a260abc9 7133(define_insn "*anddi3_internal3"
0ba1b2ff
AM		 7134 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7135 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7136 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
266eb58a 7137 (const_int 0)))
0ba1b2ff 7138 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7139 (and:DI (match_dup 1) (match_dup 2)))
0ba1b2ff 7140 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7141 "TARGET_64BIT"
266eb58a
DE		 7142 "@
7143 and. %0,%1,%2
6c873122 7144 rldic%B2. %0,%1,0,%S2
6ffc8580
MM		 7145 andi. %0,%1,%b2
7146 andis. %0,%1,%u2
9ebbca7d
GK		 7147 #
7148 #
7149 #
0ba1b2ff
AM		 7150 #
7151 #
9ebbca7d 7152 #"
0ba1b2ff
AM		 7153 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7154 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
9ebbca7d
GK		 7155
7156(define_split
7157 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7158 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7159 (match_operand:DI 2 "and64_operand" ""))
7160 (const_int 0)))
7161 (set (match_operand:DI 0 "gpc_reg_operand" "")
7162 (and:DI (match_dup 1) (match_dup 2)))
7163 (clobber (match_scratch:CC 4 ""))]
7164 "TARGET_POWERPC64 && reload_completed"
7165 [(parallel [(set (match_dup 0)
7166 (and:DI (match_dup 1) (match_dup 2)))
7167 (clobber (match_dup 4))])
7168 (set (match_dup 3)
7169 (compare:CC (match_dup 0)
7170 (const_int 0)))]
7171 "")
266eb58a 7172
0ba1b2ff
AM		 7173(define_split
7174 [(set (match_operand:CC 3 "cc_reg_operand" "")
7175 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7176 (match_operand:DI 2 "mask64_2_operand" ""))
7177 (const_int 0)))
7178 (set (match_operand:DI 0 "gpc_reg_operand" "")
7179 (and:DI (match_dup 1) (match_dup 2)))
7180 (clobber (match_scratch:CC 4 ""))]
7181 "TARGET_POWERPC64 && reload_completed
7182 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7183 && !mask64_operand (operands[2], DImode)"
7184 [(set (match_dup 0)
7185 (and:DI (rotate:DI (match_dup 1)
7186 (match_dup 5))
7187 (match_dup 6)))
7188 (parallel [(set (match_dup 3)
7189 (compare:CC (and:DI (rotate:DI (match_dup 0)
7190 (match_dup 7))
7191 (match_dup 8))
7192 (const_int 0)))
7193 (set (match_dup 0)
7194 (and:DI (rotate:DI (match_dup 0)
7195 (match_dup 7))
7196 (match_dup 8)))])]
7197 "
7198{
7199 build_mask64_2_operands (operands[2], &operands[5]);
7200}")
7201
a260abc9 7202(define_expand "iordi3"
266eb58a 7203 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7204 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7205 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7206 "TARGET_POWERPC64"
266eb58a
DE		 7207 "
7208{
dfbdccdb 7209 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7210 {
dfbdccdb 7211 HOST_WIDE_INT value;
677a9668 7212 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9 7213 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7214
dfbdccdb
GK		 7215 if (GET_CODE (operands[2]) == CONST_INT)
7216 {
7217 value = INTVAL (operands[2]);
7218 emit_insn (gen_iordi3 (tmp, operands[1],
7219 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7220 }
e2c953b6 7221 else
dfbdccdb
GK		 7222 {
7223 value = CONST_DOUBLE_LOW (operands[2]);
7224 emit_insn (gen_iordi3 (tmp, operands[1],
7225 immed_double_const (value
7226 & (~ (HOST_WIDE_INT) 0xffff),
7227 0, DImode)));
7228 }
e2c953b6 7229
9ebbca7d
GK		 7230 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7231 DONE;
7232 }
266eb58a
DE		 7233}")
7234
a260abc9
DE		 7235(define_expand "xordi3"
7236 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7237 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7238 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7239 "TARGET_POWERPC64"
7240 "
7241{
dfbdccdb 7242 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7243 {
dfbdccdb 7244 HOST_WIDE_INT value;
677a9668 7245 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7246 ? operands[0] : gen_reg_rtx (DImode));
7247
dfbdccdb
GK		 7248 if (GET_CODE (operands[2]) == CONST_INT)
7249 {
7250 value = INTVAL (operands[2]);
7251 emit_insn (gen_xordi3 (tmp, operands[1],
7252 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7253 }
e2c953b6 7254 else
dfbdccdb
GK		 7255 {
7256 value = CONST_DOUBLE_LOW (operands[2]);
7257 emit_insn (gen_xordi3 (tmp, operands[1],
7258 immed_double_const (value
7259 & (~ (HOST_WIDE_INT) 0xffff),
7260 0, DImode)));
7261 }
e2c953b6 7262
9ebbca7d
GK		 7263 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7264 DONE;
7265 }
a260abc9
DE		 7266}")
7267
dfbdccdb 7268(define_insn "*booldi3_internal1"
266eb58a 7269 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7270 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7271 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7272 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7273 "TARGET_POWERPC64"
1fd4e8c1 7274 "@
dfbdccdb
GK		 7275 %q3 %0,%1,%2
7276 %q3i %0,%1,%b2
7277 %q3is %0,%1,%u2")
1fd4e8c1 7278
dfbdccdb 7279(define_insn "*booldi3_internal2"
9ebbca7d 7280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7281 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7282 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7283 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7284 (const_int 0)))
9ebbca7d 7285 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7286 "TARGET_64BIT"
9ebbca7d 7287 "@
dfbdccdb 7288 %q4. %3,%1,%2
9ebbca7d
GK		 7289 #"
7290 [(set_attr "type" "compare")
7291 (set_attr "length" "4,8")])
7292
7293(define_split
7294 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7295 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7296 [(match_operand:DI 1 "gpc_reg_operand" "")
7297 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7298 (const_int 0)))
9ebbca7d
GK		 7299 (clobber (match_scratch:DI 3 ""))]
7300 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7301 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7302 (set (match_dup 0)
7303 (compare:CC (match_dup 3)
7304 (const_int 0)))]
7305 "")
1fd4e8c1 7306
dfbdccdb 7307(define_insn "*booldi3_internal3"
9ebbca7d 7308 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7309 (compare:CC (match_operator:DI 4 "boolean_operator"
7310 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7311 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7312 (const_int 0)))
9ebbca7d 7313 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7314 (match_dup 4))]
683bdff7 7315 "TARGET_64BIT"
9ebbca7d 7316 "@
dfbdccdb 7317 %q4. %0,%1,%2
9ebbca7d
GK		 7318 #"
7319 [(set_attr "type" "compare")
7320 (set_attr "length" "4,8")])
7321
7322(define_split
e72247f4 7323 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7324 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7325 [(match_operand:DI 1 "gpc_reg_operand" "")
7326 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7327 (const_int 0)))
75540af0 7328 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7329 (match_dup 4))]
9ebbca7d 7330 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7331 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7332 (set (match_dup 3)
7333 (compare:CC (match_dup 0)
7334 (const_int 0)))]
7335 "")
1fd4e8c1 7336
5bdc5878 7337;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7338;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7339
7340(define_split
7341 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7342 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7343 [(match_operand:DI 1 "gpc_reg_operand" "")
7344 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7345 "TARGET_POWERPC64"
dfbdccdb
GK		 7346 [(set (match_dup 0) (match_dup 4))
7347 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7348"
7349{
dfbdccdb
GK		 7350 rtx i3,i4;
7351
9ebbca7d
GK		 7352 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7353 {
7354 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7355 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7356 0, DImode);
dfbdccdb 7357 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7358 }
7359 else
7360 {
dfbdccdb 7361 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7362 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7363 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7364 }
dfbdccdb
GK		 7365 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7366 operands[1], i3);
7367 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7368 operands[0], i4);
1fd4e8c1
RK		 7369}")
7370
dfbdccdb 7371(define_insn "*boolcdi3_internal1"
9ebbca7d 7372 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7373 (match_operator:DI 3 "boolean_operator"
7374 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7375 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7376 "TARGET_POWERPC64"
1d328b19 7377 "%q3 %0,%2,%1")
a473029f 7378
dfbdccdb 7379(define_insn "*boolcdi3_internal2"
9ebbca7d 7380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7381 (compare:CC (match_operator:DI 4 "boolean_operator"
7382 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7383 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7384 (const_int 0)))
9ebbca7d 7385 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7386 "TARGET_64BIT"
9ebbca7d 7387 "@
1d328b19 7388 %q4. %3,%2,%1
9ebbca7d
GK		 7389 #"
7390 [(set_attr "type" "compare")
7391 (set_attr "length" "4,8")])
7392
7393(define_split
7394 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7395 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7396 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7397 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7398 (const_int 0)))
9ebbca7d
GK		 7399 (clobber (match_scratch:DI 3 ""))]
7400 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7401 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7402 (set (match_dup 0)
7403 (compare:CC (match_dup 3)
7404 (const_int 0)))]
7405 "")
a473029f 7406
dfbdccdb 7407(define_insn "*boolcdi3_internal3"
9ebbca7d 7408 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7409 (compare:CC (match_operator:DI 4 "boolean_operator"
7410 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7411 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7412 (const_int 0)))
9ebbca7d 7413 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7414 (match_dup 4))]
683bdff7 7415 "TARGET_64BIT"
9ebbca7d 7416 "@
1d328b19 7417 %q4. %0,%2,%1
9ebbca7d
GK		 7418 #"
7419 [(set_attr "type" "compare")
7420 (set_attr "length" "4,8")])
7421
7422(define_split
e72247f4 7423 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7424 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7425 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7426 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7427 (const_int 0)))
75540af0 7428 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7429 (match_dup 4))]
9ebbca7d 7430 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7431 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7432 (set (match_dup 3)
7433 (compare:CC (match_dup 0)
7434 (const_int 0)))]
7435 "")
266eb58a 7436
dfbdccdb 7437(define_insn "*boolccdi3_internal1"
a473029f 7438 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7439 (match_operator:DI 3 "boolean_operator"
7440 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7441 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 7442 "TARGET_POWERPC64"
dfbdccdb 7443 "%q3 %0,%1,%2")
a473029f 7444
dfbdccdb 7445(define_insn "*boolccdi3_internal2"
9ebbca7d 7446 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7447 (compare:CC (match_operator:DI 4 "boolean_operator"
7448 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7449 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7450 (const_int 0)))
9ebbca7d 7451 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7452 "TARGET_64BIT"
9ebbca7d 7453 "@
dfbdccdb 7454 %q4. %3,%1,%2
9ebbca7d
GK		 7455 #"
7456 [(set_attr "type" "compare")
7457 (set_attr "length" "4,8")])
7458
7459(define_split
7460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7461 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7462 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7463 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7464 (const_int 0)))
9ebbca7d
GK		 7465 (clobber (match_scratch:DI 3 ""))]
7466 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7467 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7468 (set (match_dup 0)
7469 (compare:CC (match_dup 3)
7470 (const_int 0)))]
7471 "")
266eb58a 7472
dfbdccdb 7473(define_insn "*boolccdi3_internal3"
9ebbca7d 7474 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7475 (compare:CC (match_operator:DI 4 "boolean_operator"
7476 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7477 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7478 (const_int 0)))
9ebbca7d 7479 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7480 (match_dup 4))]
683bdff7 7481 "TARGET_64BIT"
9ebbca7d 7482 "@
dfbdccdb 7483 %q4. %0,%1,%2
9ebbca7d
GK		 7484 #"
7485 [(set_attr "type" "compare")
7486 (set_attr "length" "4,8")])
7487
7488(define_split
e72247f4 7489 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7490 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7491 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7492 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7493 (const_int 0)))
75540af0 7494 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7495 (match_dup 4))]
9ebbca7d 7496 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7497 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7498 (set (match_dup 3)
7499 (compare:CC (match_dup 0)
7500 (const_int 0)))]
7501 "")
dfbdccdb 7502\f
1fd4e8c1 7503;; Now define ways of moving data around.
4697a36c
MM		 7504
7505;; Elf specific ways of loading addresses for non-PIC code.
9ebbca7d
GK		 7506;; The output of this could be r0, but we make a very strong
7507;; preference for a base register because it will usually
7508;; be needed there.
4697a36c 7509(define_insn "elf_high"
9ebbca7d 7510 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
4697a36c 7511 (high:SI (match_operand 1 "" "")))]
0ad91047 7512 "TARGET_ELF && ! TARGET_64BIT"
a6c2a102 7513 "{liu|lis} %0,%1@ha")
4697a36c
MM		 7514
7515(define_insn "elf_low"
9ebbca7d
GK		 7516 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7517 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
4697a36c 7518 (match_operand 2 "" "")))]
0ad91047 7519 "TARGET_ELF && ! TARGET_64BIT"
9ebbca7d
GK		 7520 "@
7521 {cal|la} %0,%2@l(%1)
81eace42 7522 {ai|addic} %0,%1,%K2")
4697a36c 7523
ee890fe2
SS		 7524;; Mach-O PIC trickery.
7525(define_insn "macho_high"
7526 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7527 (high:SI (match_operand 1 "" "")))]
7528 "TARGET_MACHO && ! TARGET_64BIT"
7529 "{liu|lis} %0,ha16(%1)")
7530
7531(define_insn "macho_low"
7532 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7533 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7534 (match_operand 2 "" "")))]
7535 "TARGET_MACHO && ! TARGET_64BIT"
7536 "@
7537 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7538 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7539
766a866c
MM		 7540;; Set up a register with a value from the GOT table
7541
7542(define_expand "movsi_got"
52d3af72 7543 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7544 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 7545 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 7546 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7547 "
7548{
38c1f2d7
MM		 7549 if (GET_CODE (operands[1]) == CONST)
7550 {
7551 rtx offset = const0_rtx;
7552 HOST_WIDE_INT value;
7553
7554 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7555 value = INTVAL (offset);
7556 if (value != 0)
7557 {
677a9668 7558 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
38c1f2d7
MM		 7559 emit_insn (gen_movsi_got (tmp, operands[1]));
7560 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7561 DONE;
7562 }
7563 }
7564
c4c40373 7565 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 7566}")
7567
84f414bc 7568(define_insn "*movsi_got_internal"
52d3af72 7569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 7570 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 7571 (match_operand:SI 2 "gpc_reg_operand" "b")]
7572 UNSPEC_MOVSI_GOT))]
f607bc57 7573 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7574 "{l|lwz} %0,%a1@got(%2)"
7575 [(set_attr "type" "load")])
7576
b22b9b3e
JL		 7577;; Used by sched, shorten_branches and final when the GOT pseudo reg
7578;; didn't get allocated to a hard register.
7579(define_split
75540af0 7580 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7581 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 7582 (match_operand:SI 2 "memory_operand" "")]
7583 UNSPEC_MOVSI_GOT))]
f607bc57 7584 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 7585 && flag_pic == 1
7586 && (reload_in_progress || reload_completed)"
7587 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 7588 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7589 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 7590 "")
7591
1fd4e8c1
RK		 7592;; For SI, we special-case integers that can't be loaded in one insn. We
7593;; do the load 16-bits at a time. We could do this by loading from memory,
7594;; and this is even supposed to be faster, but it is simpler not to get
7595;; integers in the TOC.
7596(define_expand "movsi"
7597 [(set (match_operand:SI 0 "general_operand" "")
7598 (match_operand:SI 1 "any_operand" ""))]
7599 ""
fb4d4348 7600 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
1fd4e8c1 7601
ee890fe2
SS		 7602(define_insn "movsi_low"
7603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 7604 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 7605 (match_operand 2 "" ""))))]
7606 "TARGET_MACHO && ! TARGET_64BIT"
7607 "{l|lwz} %0,lo16(%2)(%1)"
7608 [(set_attr "type" "load")
7609 (set_attr "length" "4")])
7610
c859cda6 7611(define_insn "movsi_low_st"
f585a356 7612 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
c859cda6
DJ		 7613 (match_operand 2 "" "")))
7614 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7615 "TARGET_MACHO && ! TARGET_64BIT"
7616 "{st|stw} %0,lo16(%2)(%1)"
7617 [(set_attr "type" "store")
7618 (set_attr "length" "4")])
7619
7620(define_insn "movdf_low"
234e114c 7621 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
f585a356 7622 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
c859cda6 7623 (match_operand 2 "" ""))))]
a3170dc6 7624 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
234e114c
DJ		 7625 "*
7626{
7627 switch (which_alternative)
7628 {
7629 case 0:
7630 return \"lfd %0,lo16(%2)(%1)\";
7631 case 1:
7632 {
7633 rtx operands2[4];
7634 operands2[0] = operands[0];
7635 operands2[1] = operands[1];
7636 operands2[2] = operands[2];
683bdff7
FJ		 7637 if (TARGET_POWERPC64 && TARGET_32BIT)
7638 /* Note, old assemblers didn't support relocation here. */
7639 return \"ld %0,lo16(%2)(%1)\";
ab82a49f 7640 else
683bdff7
FJ		 7641 {
7642 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7643 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7644#if TARGET_MACHO
7645 if (MACHO_DYNAMIC_NO_PIC_P)
7646 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
7647 else
7648 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7649 although in practice it almost always is. */
7650 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
ab82a49f 7651#endif
683bdff7
FJ		 7652 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7653 }
234e114c
DJ		 7654 }
7655 default:
7656 abort();
7657 }
7658}"
c859cda6 7659 [(set_attr "type" "load")
234e114c 7660 (set_attr "length" "4,12")])
c859cda6
DJ		 7661
7662(define_insn "movdf_low_st"
f585a356 7663 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
c859cda6
DJ		 7664 (match_operand 2 "" "")))
7665 (match_operand:DF 0 "gpc_reg_operand" "f"))]
a3170dc6 7666 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
c859cda6
DJ		 7667 "stfd %0,lo16(%2)(%1)"
7668 [(set_attr "type" "store")
7669 (set_attr "length" "4")])
7670
7671(define_insn "movsf_low"
fd3b43f2 7672 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
f585a356 7673 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
c859cda6 7674 (match_operand 2 "" ""))))]
a3170dc6 7675 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
fd3b43f2
DJ		 7676 "@
7677 lfs %0,lo16(%2)(%1)
7678 {l|lwz} %0,lo16(%2)(%1)"
c859cda6
DJ		 7679 [(set_attr "type" "load")
7680 (set_attr "length" "4")])
7681
7682(define_insn "movsf_low_st"
f585a356 7683 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
c859cda6 7684 (match_operand 2 "" "")))
fd3b43f2 7685 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
a3170dc6 7686 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
fd3b43f2
DJ		 7687 "@
7688 stfs %0,lo16(%2)(%1)
7689 {st|stw} %0,lo16(%2)(%1)"
c859cda6
DJ		 7690 [(set_attr "type" "store")
7691 (set_attr "length" "4")])
7692
acad7ed3 7693(define_insn "*movsi_internal1"
a004eb82
AH		 7694 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7695 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
19d5775a
RK		 7696 "gpc_reg_operand (operands[0], SImode)
7697 || gpc_reg_operand (operands[1], SImode)"
1fd4e8c1 7698 "@
deb9225a 7699 mr %0,%1
b9442c72 7700 {cal|la} %0,%a1
ca7f5001
RK		 7701 {l%U1%X1|lwz%U1%X1} %0,%1
7702 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 7703 {lil|li} %0,%1
802a0058 7704 {liu|lis} %0,%v1
beaec479 7705 #
aee86b38 7706 {cal|la} %0,%a1
1fd4e8c1 7707 mf%1 %0
5c23c401 7708 mt%0 %1
e76e75bb 7709 mt%0 %1
a004eb82 7710 mt%0 %1
e34eaae5 7711 {cror 0,0,0|nop}"
02ca7595 7712 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 7713 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 7714
77fa0940
RK		 7715;; Split a load of a large constant into the appropriate two-insn
7716;; sequence.
7717
7718(define_split
7719 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7720 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 7721 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 7722 && (INTVAL (operands[1]) & 0xffff) != 0"
7723 [(set (match_dup 0)
7724 (match_dup 2))
7725 (set (match_dup 0)
7726 (ior:SI (match_dup 0)
7727 (match_dup 3)))]
7728 "
af8cb5c5
DE		 7729{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7730
7731 if (tem == operands[0])
7732 DONE;
7733 else
7734 FAIL;
77fa0940
RK		 7735}")
7736
acad7ed3 7737(define_insn "*movsi_internal2"
bb84cb12
DE		 7738 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7739 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 7740 (const_int 0)))
bb84cb12 7741 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
0ad91047 7742 "! TARGET_POWERPC64"
9ebbca7d 7743 "@
bb84cb12 7744 {cmpi|cmpwi} %2,%0,0
9ebbca7d
GK		 7745 mr. %0,%1
7746 #"
bb84cb12
DE		 7747 [(set_attr "type" "cmp,compare,cmp")
7748 (set_attr "length" "4,4,8")])
7749
9ebbca7d
GK		 7750(define_split
7751 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7752 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7753 (const_int 0)))
7754 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7755 "! TARGET_POWERPC64 && reload_completed"
7756 [(set (match_dup 0) (match_dup 1))
7757 (set (match_dup 2)
7758 (compare:CC (match_dup 0)
7759 (const_int 0)))]
7760 "")
bb84cb12 7761\f
1fd4e8c1
RK		 7762(define_expand "movhi"
7763 [(set (match_operand:HI 0 "general_operand" "")
7764 (match_operand:HI 1 "any_operand" ""))]
7765 ""
fb4d4348 7766 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
1fd4e8c1 7767
e34eaae5 7768(define_insn "*movhi_internal"
fb81d7ce
RK		 7769 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7770 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 7771 "gpc_reg_operand (operands[0], HImode)
7772 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 7773 "@
deb9225a 7774 mr %0,%1
1fd4e8c1
RK		 7775 lhz%U1%X1 %0,%1
7776 sth%U0%X0 %1,%0
19d5775a 7777 {lil|li} %0,%w1
1fd4e8c1 7778 mf%1 %0
e76e75bb 7779 mt%0 %1
fb81d7ce 7780 mt%0 %1
e34eaae5 7781 {cror 0,0,0|nop}"
02ca7595 7782 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 7783
7784(define_expand "movqi"
7785 [(set (match_operand:QI 0 "general_operand" "")
7786 (match_operand:QI 1 "any_operand" ""))]
7787 ""
fb4d4348 7788 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
1fd4e8c1 7789
e34eaae5 7790(define_insn "*movqi_internal"
fb81d7ce
RK		 7791 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7792 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 7793 "gpc_reg_operand (operands[0], QImode)
7794 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 7795 "@
deb9225a 7796 mr %0,%1
1fd4e8c1
RK		 7797 lbz%U1%X1 %0,%1
7798 stb%U0%X0 %1,%0
19d5775a 7799 {lil|li} %0,%1
1fd4e8c1 7800 mf%1 %0
e76e75bb 7801 mt%0 %1
fb81d7ce 7802 mt%0 %1
e34eaae5 7803 {cror 0,0,0|nop}"
02ca7595 7804 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 7805\f
7806;; Here is how to move condition codes around. When we store CC data in
7807;; an integer register or memory, we store just the high-order 4 bits.
7808;; This lets us not shift in the most common case of CR0.
7809(define_expand "movcc"
7810 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7811 (match_operand:CC 1 "nonimmediate_operand" ""))]
7812 ""
7813 "")
7814
a65c591c 7815(define_insn "*movcc_internal1"
b54cf83a
DE		 7816 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7817 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
1fd4e8c1
RK		 7818 "register_operand (operands[0], CCmode)
7819 || register_operand (operands[1], CCmode)"
7820 "@
7821 mcrf %0,%1
7822 mtcrf 128,%1
ca7f5001 7823 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
2c4a9cff
DE		 7824 mfcr %0%Q1
7825 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 7826 mr %0,%1
b54cf83a 7827 mf%1 %0
b991a865
GK		 7828 mt%0 %1
7829 mt%0 %1
ca7f5001
RK		 7830 {l%U1%X1|lwz%U1%X1} %0,%1
7831 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff
DE		 7832 [(set (attr "type")
7833 (cond [(eq_attr "alternative" "0")
7834 (const_string "cr_logical")
7835 (eq_attr "alternative" "1,2")
7836 (const_string "mtcr")
7837 (eq_attr "alternative" "5,7")
7838 (const_string "integer")
7839 (eq_attr "alternative" "6")
7840 (const_string "mfjmpr")
7841 (eq_attr "alternative" "8")
7842 (const_string "mtjmpr")
7843 (eq_attr "alternative" "9")
7844 (const_string "load")
7845 (eq_attr "alternative" "10")
7846 (const_string "store")
7847 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7848 (const_string "mfcrf")
7849 ]
7850 (const_string "mfcr")))
b991a865 7851 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
1fd4e8c1 7852\f
e52e05ca
MM		 7853;; For floating-point, we normally deal with the floating-point registers
7854;; unless -msoft-float is used. The sole exception is that parameter passing
7855;; can produce floating-point values in fixed-point registers. Unless the
7856;; value is a simple constant or already in memory, we deal with this by
7857;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 7858(define_expand "movsf"
7859 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7860 (match_operand:SF 1 "any_operand" ""))]
7861 ""
fb4d4348 7862 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 7863
1fd4e8c1 7864(define_split
cd2b37d9 7865 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 7866 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 7867 "reload_completed
5ae4759c
MM		 7868 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7869 || (GET_CODE (operands[0]) == SUBREG
7870 && GET_CODE (SUBREG_REG (operands[0])) == REG
7871 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 7872 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 7873 "
7874{
7875 long l;
7876 REAL_VALUE_TYPE rv;
7877
7878 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7879 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 7880
f99f88e0
DE		 7881 if (! TARGET_POWERPC64)
7882 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7883 else
7884 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 7885
2496c7bd 7886 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 7887}")
7888
c4c40373 7889(define_insn "*movsf_hardfloat"
b991a865
GK		 7890 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
7891 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
d14a6d05 7892 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 7893 || gpc_reg_operand (operands[1], SFmode))
7894 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
1fd4e8c1 7895 "@
f99f88e0
DE		 7896 mr %0,%1
7897 {l%U1%X1|lwz%U1%X1} %0,%1
7898 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 7899 fmr %0,%1
7900 lfs%U1%X1 %0,%1
c4c40373 7901 stfs%U0%X0 %1,%0
b991a865
GK		 7902 mt%0 %1
7903 mt%0 %1
7904 mf%1 %0
c4c40373
MM		 7905 #
7906 #"
b991a865
GK		 7907 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
7908 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 7909
c4c40373 7910(define_insn "*movsf_softfloat"
dd0fbae2
MK		 7911 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7912 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 7913 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 7914 || gpc_reg_operand (operands[1], SFmode))
7915 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 7916 "@
7917 mr %0,%1
b991a865
GK		 7918 mt%0 %1
7919 mt%0 %1
7920 mf%1 %0
d14a6d05
MM		 7921 {l%U1%X1|lwz%U1%X1} %0,%1
7922 {st%U0%X0|stw%U0%X0} %1,%0
7923 {lil|li} %0,%1
802a0058 7924 {liu|lis} %0,%v1
aee86b38 7925 {cal|la} %0,%a1
c4c40373 7926 #
dd0fbae2
MK		 7927 #
7928 {cror 0,0,0|nop}"
7929 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7930 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 7931
1fd4e8c1
RK		 7932\f
7933(define_expand "movdf"
7934 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7935 (match_operand:DF 1 "any_operand" ""))]
7936 ""
fb4d4348 7937 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 7938
7939(define_split
cd2b37d9 7940 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 7941 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 7942 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7943 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7944 || (GET_CODE (operands[0]) == SUBREG
7945 && GET_CODE (SUBREG_REG (operands[0])) == REG
7946 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 7947 [(set (match_dup 2) (match_dup 4))
7948 (set (match_dup 3) (match_dup 1))]
7949 "
7950{
5ae4759c 7951 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 7952 HOST_WIDE_INT value = INTVAL (operands[1]);
7953
5ae4759c
MM		 7954 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7955 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 7956#if HOST_BITS_PER_WIDE_INT == 32
7957 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7958#else
7959 operands[4] = GEN_INT (value >> 32);
a65c591c 7960 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 7961#endif
c4c40373
MM		 7962}")
7963
c4c40373
MM		 7964(define_split
7965 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7966 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 7967 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7968 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7969 || (GET_CODE (operands[0]) == SUBREG
7970 && GET_CODE (SUBREG_REG (operands[0])) == REG
7971 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 7972 [(set (match_dup 2) (match_dup 4))
7973 (set (match_dup 3) (match_dup 5))]
7974 "
7975{
5ae4759c 7976 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 7977 long l[2];
7978 REAL_VALUE_TYPE rv;
7979
7980 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7981 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7982
5ae4759c
MM		 7983 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7984 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 7985 operands[4] = gen_int_mode (l[endian], SImode);
7986 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 7987}")
7988
efc08378
DE		 7989(define_split
7990 [(set (match_operand:DF 0 "gpc_reg_operand" "")
685f3906 7991 (match_operand:DF 1 "easy_fp_constant" ""))]
a260abc9 7992 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7993 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7994 || (GET_CODE (operands[0]) == SUBREG
7995 && GET_CODE (SUBREG_REG (operands[0])) == REG
7996 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 7997 [(set (match_dup 2) (match_dup 3))]
5ae4759c 7998 "
a260abc9
DE		 7999{
8000 int endian = (WORDS_BIG_ENDIAN == 0);
8001 long l[2];
8002 REAL_VALUE_TYPE rv;
4977bab6 8003#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 8004 HOST_WIDE_INT val;
4977bab6 8005#endif
a260abc9
DE		 8006
8007 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8008 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8009
8010 operands[2] = gen_lowpart (DImode, operands[0]);
8011 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 8012#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8013 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8014 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 8015
f5264b52 8016 operands[3] = gen_int_mode (val, DImode);
5b029315 8017#else
a260abc9 8018 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 8019#endif
a260abc9 8020}")
efc08378 8021
4eae5fe1 8022;; Don't have reload use general registers to load a constant. First,
1427100a 8023;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 8024;; a non-offsettable memref, but also it is less efficient than loading
8025;; the constant into an FP register, since it will probably be used there.
8026;; The "??" is a kludge until we can figure out a more reasonable way
8027;; of handling these non-offsettable values.
c4c40373 8028(define_insn "*movdf_hardfloat32"
914a7297
DE		 8029 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8030 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
a3170dc6 8031 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8032 && (gpc_reg_operand (operands[0], DFmode)
8033 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 8034 "*
8035{
8036 switch (which_alternative)
8037 {
a260abc9 8038 default:
a6c2a102 8039 abort ();
e7113111
RK		 8040 case 0:
8041 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 8042 the first register operand 0 is the same as the second register
8043 of operand 1, we must copy in the opposite order. */
e7113111 8044 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8045 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 8046 else
deb9225a 8047 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 8048 case 1:
2b97222d
DE		 8049 if (offsettable_memref_p (operands[1])
8050 || (GET_CODE (operands[1]) == MEM
69f51a21
DE		 8051 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8052 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8053 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
000034eb
DE		 8054 {
8055 /* If the low-address word is used in the address, we must load
8056 it last. Otherwise, load it first. Note that we cannot have
8057 auto-increment in that case since the address register is
8058 known to be dead. */
8059 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8060 operands[1], 0))
8061 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8062 else
8063 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8064 }
e7113111 8065 else
000034eb
DE		 8066 {
8067 rtx addreg;
8068
000034eb
DE		 8069 addreg = find_addr_reg (XEXP (operands[1], 0));
8070 if (refers_to_regno_p (REGNO (operands[0]),
8071 REGNO (operands[0]) + 1,
8072 operands[1], 0))
8073 {
8074 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 8075 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
000034eb 8076 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2b97222d 8077 return \"{lx|lwzx} %0,%1\";
000034eb
DE		 8078 }
8079 else
8080 {
2b97222d 8081 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
000034eb 8082 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 8083 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
000034eb
DE		 8084 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8085 return \"\";
8086 }
8087 }
e7113111 8088 case 2:
2b97222d
DE		 8089 if (offsettable_memref_p (operands[0])
8090 || (GET_CODE (operands[0]) == MEM
69f51a21
DE		 8091 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8092 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8093 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
000034eb
DE		 8094 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8095 else
8096 {
8097 rtx addreg;
8098
000034eb 8099 addreg = find_addr_reg (XEXP (operands[0], 0));
2b97222d 8100 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
000034eb 8101 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 8102 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
000034eb
DE		 8103 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8104 return \"\";
8105 }
e7113111 8106 case 3:
914a7297 8107 return \"fmr %0,%1\";
e7113111 8108 case 4:
914a7297 8109 return \"lfd%U1%X1 %0,%1\";
e7113111 8110 case 5:
914a7297 8111 return \"stfd%U0%X0 %1,%0\";
e7113111 8112 case 6:
c4c40373 8113 case 7:
c4c40373 8114 case 8:
914a7297 8115 return \"#\";
e7113111
RK		 8116 }
8117}"
914a7297
DE		 8118 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
8119 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 8120
c4c40373 8121(define_insn "*movdf_softfloat32"
1427100a
DE		 8122 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8123 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
a3170dc6 8124 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8125 && (gpc_reg_operand (operands[0], DFmode)
8126 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8127 "*
8128{
8129 switch (which_alternative)
8130 {
a260abc9 8131 default:
a6c2a102 8132 abort ();
dc4f83ca
MM		 8133 case 0:
8134 /* We normally copy the low-numbered register first. However, if
8135 the first register operand 0 is the same as the second register of
8136 operand 1, we must copy in the opposite order. */
8137 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8138 return \"mr %L0,%L1\;mr %0,%1\";
8139 else
8140 return \"mr %0,%1\;mr %L0,%L1\";
8141 case 1:
3cb999d8
DE		 8142 /* If the low-address word is used in the address, we must load
8143 it last. Otherwise, load it first. Note that we cannot have
8144 auto-increment in that case since the address register is
8145 known to be dead. */
dc4f83ca 8146 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8147 operands[1], 0))
dc4f83ca
MM		 8148 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8149 else
8150 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8151 case 2:
8152 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8153 case 3:
c4c40373
MM		 8154 case 4:
8155 case 5:
dc4f83ca
MM		 8156 return \"#\";
8157 }
8158}"
c4c40373
MM		 8159 [(set_attr "type" "*,load,store,*,*,*")
8160 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8161
c4c40373 8162(define_insn "*movdf_hardfloat64"
914a7297
DE		 8163 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r")
8164 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))]
a3170dc6 8165 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8166 && (gpc_reg_operand (operands[0], DFmode)
8167 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8168 "@
3d5570cb
RK		 8169 mr %0,%1
8170 ld%U1%X1 %0,%1
96bb8ed3 8171 std%U0%X0 %1,%0
3d5570cb 8172 fmr %0,%1
f63184ac 8173 lfd%U1%X1 %0,%1
914a7297
DE		 8174 stfd%U0%X0 %1,%0
8175 mt%0 %1
8176 mf%1 %0
8177 #
8178 #
8179 #"
8180 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*")
8181 (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8182
c4c40373 8183(define_insn "*movdf_softfloat64"
e2d0915c
AM		 8184 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,*h")
8185 (match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F,0"))]
a3170dc6 8186 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8187 && (gpc_reg_operand (operands[0], DFmode)
8188 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8189 "@
8190 mr %0,%1
914a7297
DE		 8191 mt%0 %1
8192 mf%1 %0
dc4f83ca 8193 ld%U1%X1 %0,%1
96bb8ed3 8194 std%U0%X0 %1,%0
c4c40373
MM		 8195 #
8196 #
e2d0915c
AM		 8197 #
8198 nop"
8199 [(set_attr "type" "*,*,*,load,store,*,*,*,*")
8200 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 8201\f
06f4e019
DE		 8202(define_expand "movtf"
8203 [(set (match_operand:TF 0 "general_operand" "")
8204 (match_operand:TF 1 "any_operand" ""))]
39e63627
GK		 8205 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8206 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8207 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8208
8209(define_insn "*movtf_internal"
8210 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r")
8211 (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))]
39e63627
GK		 8212 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8213 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8214 && (gpc_reg_operand (operands[0], TFmode)
8215 || gpc_reg_operand (operands[1], TFmode))"
8216 "*
8217{
8218 switch (which_alternative)
8219 {
8220 default:
8221 abort ();
8222 case 0:
8223 /* We normally copy the low-numbered register first. However, if
8224 the first register operand 0 is the same as the second register of
8225 operand 1, we must copy in the opposite order. */
8226 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8227 return \"fmr %L0,%L1\;fmr %0,%1\";
8228 else
8229 return \"fmr %0,%1\;fmr %L0,%L1\";
8230 case 1:
f5264b52 8231 return \"lfd %0,%1\;lfd %L0,%Y1\";
06f4e019 8232 case 2:
f5264b52 8233 return \"stfd %1,%0\;stfd %L1,%Y0\";
06f4e019
DE		 8234 case 3:
8235 case 4:
8236 case 5:
8237 return \"#\";
8238 }
8239}"
8240 [(set_attr "type" "fp,fpload,fpstore,*,*,*")
8241 (set_attr "length" "8,8,8,12,16,20")])
8242
8243(define_split
8244 [(set (match_operand:TF 0 "gpc_reg_operand" "")
f5264b52 8245 (match_operand:TF 1 "easy_fp_constant" ""))]
fcce224d
DE		 8246 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8247 && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_POWERPC64
8248 && TARGET_LONG_DOUBLE_128 && reload_completed
8249 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8250 || (GET_CODE (operands[0]) == SUBREG
8251 && GET_CODE (SUBREG_REG (operands[0])) == REG
8252 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8253 [(set (match_dup 2) (match_dup 6))
8254 (set (match_dup 3) (match_dup 7))
8255 (set (match_dup 4) (match_dup 8))
8256 (set (match_dup 5) (match_dup 9))]
8257 "
8258{
8259 long l[4];
8260 REAL_VALUE_TYPE rv;
8261
8262 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8263 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l);
8264
8265 operands[2] = operand_subword (operands[0], 0, 0, TFmode);
8266 operands[3] = operand_subword (operands[0], 1, 0, TFmode);
8267 operands[4] = operand_subword (operands[0], 2, 0, TFmode);
8268 operands[5] = operand_subword (operands[0], 3, 0, TFmode);
8269 operands[6] = gen_int_mode (l[0], SImode);
8270 operands[7] = gen_int_mode (l[1], SImode);
8271 operands[8] = gen_int_mode (l[2], SImode);
8272 operands[9] = gen_int_mode (l[3], SImode);
8273}")
8274
8275(define_split
8276 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8277 (match_operand:TF 1 "easy_fp_constant" ""))]
8278 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8279 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8280 && TARGET_LONG_DOUBLE_128 && reload_completed
8281 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8282 || (GET_CODE (operands[0]) == SUBREG
8283 && GET_CODE (SUBREG_REG (operands[0])) == REG
8284 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8285 [(set (match_dup 2) (match_dup 4))
8286 (set (match_dup 3) (match_dup 5))]
06f4e019
DE		 8287 "
8288{
fcce224d
DE		 8289 long l[4];
8290 REAL_VALUE_TYPE rv;
d24652ee 8291#if HOST_BITS_PER_WIDE_INT >= 64
f5264b52 8292 HOST_WIDE_INT val;
d24652ee 8293#endif
fcce224d
DE		 8294
8295 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8296 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l);
8297
f5264b52
DE		 8298 operands[2] = gen_lowpart (DImode, operands[0]);
8299 operands[3] = gen_highpart (DImode, operands[0]);
8300#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8301 val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32
8302 | ((HOST_WIDE_INT)(unsigned long)l[1]));
f5264b52
DE		 8303 operands[4] = gen_int_mode (val, DImode);
8304
a2419b96
DE		 8305 val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32
8306 | ((HOST_WIDE_INT)(unsigned long)l[3]));
f5264b52
DE		 8307 operands[5] = gen_int_mode (val, DImode);
8308#else
8309 operands[4] = immed_double_const (l[1], l[0], DImode);
8310 operands[5] = immed_double_const (l[3], l[2], DImode);
8311#endif
06f4e019
DE		 8312}")
8313
a2419b96 8314(define_insn "extenddftf2"
06f4e019
DE		 8315 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8316 (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))]
39e63627
GK		 8317 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8318 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
a2419b96 8319 "*
06f4e019 8320{
a2419b96
DE		 8321 if (REGNO (operands[0]) == REGNO (operands[1]))
8322 return \"fsub %L0,%L0,%L0\";
8323 else
8324 return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
8325}"
8326 [(set_attr "type" "fp")])
06f4e019 8327
a2419b96 8328(define_insn "extendsftf2"
06f4e019
DE		 8329 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8330 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))]
39e63627
GK		 8331 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8332 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
a2419b96 8333 "*
06f4e019 8334{
a2419b96
DE		 8335 if (REGNO (operands[0]) == REGNO (operands[1]))
8336 return \"fsub %L0,%L0,%L0\";
8337 else
8338 return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
8339}"
8340 [(set_attr "type" "fp")])
06f4e019
DE		 8341
8342(define_insn "trunctfdf2"
8343 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8344 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
39e63627
GK		 8345 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8346 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8347 "fadd %0,%1,%L1"
8348 [(set_attr "type" "fp")
8349 (set_attr "length" "8")])
8350
8351(define_insn_and_split "trunctfsf2"
8352 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 8353 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8354 (clobber (match_scratch:DF 2 "=f"))]
39e63627
GK		 8355 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8356 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8357 "#"
ea112fc4 8358 "&& reload_completed"
06f4e019
DE		 8359 [(set (match_dup 2)
8360 (float_truncate:DF (match_dup 1)))
8361 (set (match_dup 0)
8362 (float_truncate:SF (match_dup 2)))]
ea112fc4 8363 "")
06f4e019 8364
ea112fc4
DE		 8365(define_insn_and_split "floatditf2"
8366 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
61c07d3c 8367 (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f")))
ea112fc4 8368 (clobber (match_scratch:DF 2 "=f"))]
39e63627
GK		 8369 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8370 && TARGET_POWERPC64
a3170dc6 8371 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ea112fc4
DE		 8372 "#"
8373 "&& reload_completed"
06f4e019 8374 [(set (match_dup 2)
a2419b96
DE		 8375 (float:DF (match_dup 1)))
8376 (set (match_dup 0)
06f4e019 8377 (float_extend:TF (match_dup 2)))]
ea112fc4 8378 "")
06f4e019 8379
ea112fc4
DE		 8380(define_insn_and_split "floatsitf2"
8381 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
61c07d3c 8382 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))
ea112fc4 8383 (clobber (match_scratch:DF 2 "=f"))]
39e63627
GK		 8384 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8385 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ea112fc4
DE		 8386 "#"
8387 "&& reload_completed"
06f4e019 8388 [(set (match_dup 2)
a2419b96
DE		 8389 (float:DF (match_dup 1)))
8390 (set (match_dup 0)
06f4e019 8391 (float_extend:TF (match_dup 2)))]
ea112fc4 8392 "")
06f4e019 8393
ea112fc4 8394(define_insn_and_split "fix_trunctfdi2"
61c07d3c 8395 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
a2419b96
DE		 8396 (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))
8397 (clobber (match_scratch:DF 2 "=f"))]
39e63627
GK		 8398 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8399 && TARGET_POWERPC64
a3170dc6 8400 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ea112fc4
DE		 8401 "#"
8402 "&& reload_completed"
06f4e019 8403 [(set (match_dup 2)
a2419b96
DE		 8404 (float_truncate:DF (match_dup 1)))
8405 (set (match_dup 0)
8406 (fix:DI (match_dup 2)))]
ea112fc4 8407 "")
06f4e019 8408
ea112fc4 8409(define_insn_and_split "fix_trunctfsi2"
61c07d3c 8410 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2419b96
DE		 8411 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8412 (clobber (match_scratch:DF 2 "=f"))]
39e63627
GK		 8413 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8414 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ea112fc4
DE		 8415 "#"
8416 "&& reload_completed"
06f4e019 8417 [(set (match_dup 2)
a2419b96
DE		 8418 (float_truncate:DF (match_dup 1)))
8419 (set (match_dup 0)
06f4e019 8420 (fix:SI (match_dup 2)))]
ea112fc4 8421 "")
06f4e019
DE		 8422
8423(define_insn "negtf2"
8424 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8425 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
39e63627
GK		 8426 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8427 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8428 "*
8429{
8430 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8431 return \"fneg %L0,%L1\;fneg %0,%1\";
8432 else
8433 return \"fneg %0,%1\;fneg %L0,%L1\";
8434}"
8435 [(set_attr "type" "fp")
8436 (set_attr "length" "8")])
8437
8438(define_insn "abstf2"
8439 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8440 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
39e63627
GK		 8441 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8442 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8443 "*
8444{
8445 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8446 return \"fabs %L0,%L1\;fabs %0,%1\";
8447 else
8448 return \"fabs %0,%1\;fabs %L0,%L1\";
8449}"
8450 [(set_attr "type" "fp")
8451 (set_attr "length" "8")])
8452
8453(define_insn ""
8454 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8455 (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))]
39e63627
GK		 8456 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8457 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8458 "*
8459{
8460 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8461 return \"fnabs %L0,%L1\;fnabs %0,%1\";
8462 else
8463 return \"fnabs %0,%1\;fnabs %L0,%L1\";
8464}"
8465 [(set_attr "type" "fp")
8466 (set_attr "length" "8")])
8467\f
1fd4e8c1
RK		 8468;; Next come the multi-word integer load and store and the load and store
8469;; multiple insns.
8470(define_expand "movdi"
8471 [(set (match_operand:DI 0 "general_operand" "")
e6ca2c17 8472 (match_operand:DI 1 "any_operand" ""))]
1fd4e8c1 8473 ""
fb4d4348 8474 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
1fd4e8c1 8475
acad7ed3 8476(define_insn "*movdi_internal32"
4e74d8ec
MM		 8477 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8478 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
a260abc9 8479 "! TARGET_POWERPC64
4e74d8ec
MM		 8480 && (gpc_reg_operand (operands[0], DImode)
8481 || gpc_reg_operand (operands[1], DImode))"
1fd4e8c1
RK		 8482 "*
8483{
8484 switch (which_alternative)
8485 {
a260abc9 8486 default:
a6c2a102 8487 abort ();
1fd4e8c1 8488 case 0:
1fd4e8c1 8489 case 1:
1fd4e8c1 8490 case 2:
3a1f863f 8491 return \"#\";
8ffd9c51
RK		 8492 case 3:
8493 return \"fmr %0,%1\";
8494 case 4:
8495 return \"lfd%U1%X1 %0,%1\";
8496 case 5:
8497 return \"stfd%U0%X0 %1,%0\";
4e74d8ec
MM		 8498 case 6:
8499 case 7:
8500 case 8:
8501 case 9:
8502 case 10:
8503 return \"#\";
1fd4e8c1
RK		 8504 }
8505}"
3a1f863f 8506 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")])
4e74d8ec
MM		 8507
8508(define_split
8509 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8510 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 8511 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8512 [(set (match_dup 2) (match_dup 4))
8513 (set (match_dup 3) (match_dup 1))]
8514 "
8515{
5f59ecb7 8516 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 8517 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8518 DImode);
8519 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8520 DImode);
75d39459 8521#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 8522 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 8523#else
5f59ecb7 8524 operands[4] = GEN_INT (value >> 32);
a65c591c 8525 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 8526#endif
4e74d8ec
MM		 8527}")
8528
4e74d8ec
MM		 8529(define_split
8530 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8531 (match_operand:DI 1 "const_double_operand" ""))]
75d39459 8532 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8533 [(set (match_dup 2) (match_dup 4))
8534 (set (match_dup 3) (match_dup 5))]
8535 "
8536{
bdaa0181
GK		 8537 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8538 DImode);
8539 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8540 DImode);
f6968f59
MM		 8541 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8542 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4e74d8ec
MM		 8543}")
8544
3a1f863f
DE		 8545(define_split
8546 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8547 (match_operand:DI 1 "input_operand" ""))]
8548 "reload_completed && !TARGET_POWERPC64
8549 && gpr_or_gpr_p (operands[0], operands[1])"
8550 [(set (match_dup 2) (match_dup 4))
8551 (set (match_dup 3) (match_dup 5))]
8552"{
8553 rs6000_split_multireg_move (operands);
8554}")
8555
6fc19dc9
AM		 8556(define_split
8557 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8558 (match_operand:TI 1 "const_double_operand" ""))]
8559 "TARGET_POWERPC64"
8560 [(set (match_dup 2) (match_dup 4))
8561 (set (match_dup 3) (match_dup 5))]
8562 "
8563{
8564 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8565 TImode);
8566 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8567 TImode);
8568 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8569 {
8570 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8571 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8572 }
8573 else if (GET_CODE (operands[1]) == CONST_INT)
8574 {
8575 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8576 operands[5] = operands[1];
8577 }
8578 else
8579 FAIL;
8580}")
8581
acad7ed3 8582(define_insn "*movdi_internal64"
5d7e6254 8583 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
9615f239 8584 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
a260abc9 8585 "TARGET_POWERPC64
4e74d8ec
MM		 8586 && (gpc_reg_operand (operands[0], DImode)
8587 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 8588 "@
3d5570cb
RK		 8589 mr %0,%1
8590 ld%U1%X1 %0,%1
96bb8ed3 8591 std%U0%X0 %1,%0
3d5570cb 8592 li %0,%1
802a0058 8593 lis %0,%v1
e6ca2c17 8594 #
aee86b38 8595 {cal|la} %0,%a1
3d5570cb
RK		 8596 fmr %0,%1
8597 lfd%U1%X1 %0,%1
8598 stfd%U0%X0 %1,%0
8599 mf%1 %0
08075ead 8600 mt%0 %1
e34eaae5 8601 {cror 0,0,0|nop}"
02ca7595 8602 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 8603 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8604
5f59ecb7 8605;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 8606(define_insn ""
8607 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8608 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 8609 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8610 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 8611 && num_insns_constant (operands[1], DImode) == 1"
8612 "*
8613{
8614 return ((unsigned HOST_WIDE_INT)
8615 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8616 ? \"li %0,%1\" : \"lis %0,%v1\";
8617}")
8618
a260abc9
DE		 8619;; Generate all one-bits and clear left or right.
8620;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8621(define_split
8622 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8623 (match_operand:DI 1 "mask64_operand" ""))]
8624 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8625 [(set (match_dup 0) (const_int -1))
e6ca2c17 8626 (set (match_dup 0)
a260abc9
DE		 8627 (and:DI (rotate:DI (match_dup 0)
8628 (const_int 0))
8629 (match_dup 1)))]
8630 "")
8631
8632;; Split a load of a large constant into the appropriate five-instruction
8633;; sequence. Handle anything in a constant number of insns.
8634;; When non-easy constants can go in the TOC, this should use
8635;; easy_fp_constant predicate.
8636(define_split
8637 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 8638 (match_operand:DI 1 "const_int_operand" ""))]
8639 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8640 [(set (match_dup 0) (match_dup 2))
8641 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 8642 "
2bfcf297
DB		 8643{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8644
8645 if (tem == operands[0])
8646 DONE;
e8d791dd 8647 else
2bfcf297 8648 FAIL;
5f59ecb7 8649}")
e6ca2c17 8650
5f59ecb7
DE		 8651(define_split
8652 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 8653 (match_operand:DI 1 "const_double_operand" ""))]
8654 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8655 [(set (match_dup 0) (match_dup 2))
8656 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 8657 "
2bfcf297
DB		 8658{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8659
8660 if (tem == operands[0])
8661 DONE;
8662 else
8663 FAIL;
e6ca2c17 8664}")
08075ead 8665
acad7ed3 8666(define_insn "*movdi_internal2"
bb84cb12
DE		 8667 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8668 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
08075ead 8669 (const_int 0)))
bb84cb12 8670 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
683bdff7 8671 "TARGET_64BIT"
9ebbca7d 8672 "@
bb84cb12 8673 cmpdi %2,%0,0
9ebbca7d
GK		 8674 mr. %0,%1
8675 #"
bb84cb12
DE		 8676 [(set_attr "type" "cmp,compare,cmp")
8677 (set_attr "length" "4,4,8")])
acad7ed3 8678
9ebbca7d
GK		 8679(define_split
8680 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8681 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8682 (const_int 0)))
8683 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8684 "TARGET_POWERPC64 && reload_completed"
8685 [(set (match_dup 0) (match_dup 1))
8686 (set (match_dup 2)
8687 (compare:CC (match_dup 0)
8688 (const_int 0)))]
8689 "")
acad7ed3 8690\f
1fd4e8c1
RK		 8691;; TImode is similar, except that we usually want to compute the address into
8692;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 8693;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 8694(define_expand "movti"
8695 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8696 (match_operand:TI 1 "general_operand" ""))
8697 (clobber (scratch:SI))])]
3a1f863f 8698 ""
fb4d4348 8699 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
1fd4e8c1
RK		 8700
8701;; We say that MQ is clobbered in the last alternative because the first
8702;; alternative would never get used otherwise since it would need a reload
8703;; while the 2nd alternative would not. We put memory cases first so they
8704;; are preferred. Otherwise, we'd try to reload the output instead of
8705;; giving the SCRATCH mq.
3a1f863f 8706
a260abc9 8707(define_insn "*movti_power"
e1469d0d 8708 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
1fd4e8c1
RK		 8709 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8710 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
683bdff7 8711 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 8712 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 8713 "*
8714{
8715 switch (which_alternative)
8716 {
dc4f83ca
MM		 8717 default:
8718 abort ();
8719
1fd4e8c1 8720 case 0:
3a1f863f
DE		 8721 if (TARGET_STRING)
8722 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 8723 case 1:
1fd4e8c1 8724 case 2:
3a1f863f 8725 return \"#\";
1fd4e8c1
RK		 8726 case 3:
8727 /* If the address is not used in the output, we can use lsi. Otherwise,
8728 fall through to generating four loads. */
e876481c
DE		 8729 if (TARGET_STRING
8730 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 8731 return \"{lsi|lswi} %0,%P1,16\";
82e41834 8732 /* ... fall through ... */
1fd4e8c1 8733 case 4:
3a1f863f 8734 return \"#\";
1fd4e8c1
RK		 8735 }
8736}"
3a1f863f 8737 [(set_attr "type" "store,store,*,load,load")])
51b8fc2c 8738
a260abc9 8739(define_insn "*movti_string"
cd1d3445 8740 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
27dc0551 8741 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
3a1f863f 8742 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 8743 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8744 "*
8745{
8746 switch (which_alternative)
8747 {
8748 default:
8749 abort ();
dc4f83ca 8750 case 0:
3a1f863f
DE		 8751 if (TARGET_STRING)
8752 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 8753 case 1:
cd1d3445 8754 case 2:
3a1f863f 8755 return \"#\";
cd1d3445
DE		 8756 case 3:
8757 /* If the address is not used in the output, we can use lsi. Otherwise,
8758 fall through to generating four loads. */
3a1f863f
DE		 8759 if (TARGET_STRING
8760 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 8761 return \"{lsi|lswi} %0,%P1,16\";
8762 /* ... fall through ... */
8763 case 4:
3a1f863f 8764 return \"#\";
dc4f83ca
MM		 8765 }
8766}"
3a1f863f 8767 [(set_attr "type" "store,store,*,load,load")])
dc4f83ca 8768
a260abc9 8769(define_insn "*movti_ppc64"
3a1f863f
DE		 8770 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r")
8771 (match_operand:TI 1 "input_operand" "r,r,o"))]
51b8fc2c
RK		 8772 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8773 || gpc_reg_operand (operands[1], TImode))"
3a1f863f
DE		 8774 "@
8775 #
8776 #
8777 #"
8778 [(set_attr "type" "*,load,store")])
8779
8780(define_split
8781 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8782 (match_operand:TI 1 "input_operand" ""))]
8783 "reload_completed && TARGET_POWERPC64
8784 && gpr_or_gpr_p (operands[0], operands[1])"
8785 [(set (match_dup 2) (match_dup 4))
8786 (set (match_dup 3) (match_dup 5))]
8787"{
8788 rs6000_split_multireg_move (operands);
8789}")
8790
8791(define_split
8792 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8793 (match_operand:TI 1 "input_operand" ""))]
8794 "reload_completed && !TARGET_POWERPC64
8795 && gpr_or_gpr_p (operands[0], operands[1])"
8796 [(set (match_dup 2) (match_dup 6))
8797 (set (match_dup 3) (match_dup 7))
8798 (set (match_dup 4) (match_dup 8))
8799 (set (match_dup 5) (match_dup 9))]
8800"{
8801 rs6000_split_multireg_move (operands);
8802}")
8803
8804
1fd4e8c1
RK		 8805\f
8806(define_expand "load_multiple"
2f622005
RK		 8807 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8808 (match_operand:SI 1 "" ""))
8809 (use (match_operand:SI 2 "" ""))])]
09a625f7 8810 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 8811 "
8812{
8813 int regno;
8814 int count;
792760b9 8815 rtx op1;
1fd4e8c1
RK		 8816 int i;
8817
8818 /* Support only loading a constant number of fixed-point registers from
8819 memory and only bother with this if more than two; the machine
8820 doesn't support more than eight. */
8821 if (GET_CODE (operands[2]) != CONST_INT
8822 || INTVAL (operands[2]) <= 2
8823 || INTVAL (operands[2]) > 8
8824 || GET_CODE (operands[1]) != MEM
8825 || GET_CODE (operands[0]) != REG
8826 || REGNO (operands[0]) >= 32)
8827 FAIL;
8828
8829 count = INTVAL (operands[2]);
8830 regno = REGNO (operands[0]);
8831
39403d82 8832 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 8833 op1 = replace_equiv_address (operands[1],
8834 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 8835
8836 for (i = 0; i < count; i++)
8837 XVECEXP (operands[3], 0, i)
39403d82 8838 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 8839 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 8840}")
8841
9caa3eb2 8842(define_insn "*ldmsi8"
1fd4e8c1 8843 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 8844 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8845 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8846 (set (match_operand:SI 3 "gpc_reg_operand" "")
8847 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8848 (set (match_operand:SI 4 "gpc_reg_operand" "")
8849 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8850 (set (match_operand:SI 5 "gpc_reg_operand" "")
8851 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8852 (set (match_operand:SI 6 "gpc_reg_operand" "")
8853 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8854 (set (match_operand:SI 7 "gpc_reg_operand" "")
8855 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8856 (set (match_operand:SI 8 "gpc_reg_operand" "")
8857 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8858 (set (match_operand:SI 9 "gpc_reg_operand" "")
8859 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8860 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 8861 "*
9caa3eb2
DE		 8862{ return rs6000_output_load_multiple (operands); }"
8863 [(set_attr "type" "load")
8864 (set_attr "length" "32")])
1fd4e8c1 8865
9caa3eb2
DE		 8866(define_insn "*ldmsi7"
8867 [(match_parallel 0 "load_multiple_operation"
8868 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8869 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8870 (set (match_operand:SI 3 "gpc_reg_operand" "")
8871 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8872 (set (match_operand:SI 4 "gpc_reg_operand" "")
8873 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8874 (set (match_operand:SI 5 "gpc_reg_operand" "")
8875 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8876 (set (match_operand:SI 6 "gpc_reg_operand" "")
8877 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8878 (set (match_operand:SI 7 "gpc_reg_operand" "")
8879 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8880 (set (match_operand:SI 8 "gpc_reg_operand" "")
8881 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8882 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8883 "*
8884{ return rs6000_output_load_multiple (operands); }"
8885 [(set_attr "type" "load")
8886 (set_attr "length" "32")])
8887
8888(define_insn "*ldmsi6"
8889 [(match_parallel 0 "load_multiple_operation"
8890 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8891 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8892 (set (match_operand:SI 3 "gpc_reg_operand" "")
8893 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8894 (set (match_operand:SI 4 "gpc_reg_operand" "")
8895 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8896 (set (match_operand:SI 5 "gpc_reg_operand" "")
8897 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8898 (set (match_operand:SI 6 "gpc_reg_operand" "")
8899 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8900 (set (match_operand:SI 7 "gpc_reg_operand" "")
8901 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8902 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8903 "*
8904{ return rs6000_output_load_multiple (operands); }"
8905 [(set_attr "type" "load")
8906 (set_attr "length" "32")])
8907
8908(define_insn "*ldmsi5"
8909 [(match_parallel 0 "load_multiple_operation"
8910 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8911 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8912 (set (match_operand:SI 3 "gpc_reg_operand" "")
8913 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8914 (set (match_operand:SI 4 "gpc_reg_operand" "")
8915 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8916 (set (match_operand:SI 5 "gpc_reg_operand" "")
8917 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8918 (set (match_operand:SI 6 "gpc_reg_operand" "")
8919 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8920 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8921 "*
8922{ return rs6000_output_load_multiple (operands); }"
8923 [(set_attr "type" "load")
8924 (set_attr "length" "32")])
8925
8926(define_insn "*ldmsi4"
8927 [(match_parallel 0 "load_multiple_operation"
8928 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8929 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8930 (set (match_operand:SI 3 "gpc_reg_operand" "")
8931 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8932 (set (match_operand:SI 4 "gpc_reg_operand" "")
8933 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8934 (set (match_operand:SI 5 "gpc_reg_operand" "")
8935 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8936 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8937 "*
8938{ return rs6000_output_load_multiple (operands); }"
8939 [(set_attr "type" "load")
8940 (set_attr "length" "32")])
8941
8942(define_insn "*ldmsi3"
8943 [(match_parallel 0 "load_multiple_operation"
8944 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8945 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8946 (set (match_operand:SI 3 "gpc_reg_operand" "")
8947 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8948 (set (match_operand:SI 4 "gpc_reg_operand" "")
8949 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8950 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8951 "*
8952{ return rs6000_output_load_multiple (operands); }"
b19003d8 8953 [(set_attr "type" "load")
e82ee4cc 8954 (set_attr "length" "32")])
b19003d8 8955
1fd4e8c1 8956(define_expand "store_multiple"
2f622005
RK		 8957 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8958 (match_operand:SI 1 "" ""))
8959 (clobber (scratch:SI))
8960 (use (match_operand:SI 2 "" ""))])]
09a625f7 8961 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 8962 "
8963{
8964 int regno;
8965 int count;
8966 rtx to;
792760b9 8967 rtx op0;
1fd4e8c1
RK		 8968 int i;
8969
8970 /* Support only storing a constant number of fixed-point registers to
8971 memory and only bother with this if more than two; the machine
8972 doesn't support more than eight. */
8973 if (GET_CODE (operands[2]) != CONST_INT
8974 || INTVAL (operands[2]) <= 2
8975 || INTVAL (operands[2]) > 8
8976 || GET_CODE (operands[0]) != MEM
8977 || GET_CODE (operands[1]) != REG
8978 || REGNO (operands[1]) >= 32)
8979 FAIL;
8980
8981 count = INTVAL (operands[2]);
8982 regno = REGNO (operands[1]);
8983
39403d82 8984 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 8985 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 8986 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 8987
8988 XVECEXP (operands[3], 0, 0)
7ef788f0 8989 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 8990 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 8991 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 8992
8993 for (i = 1; i < count; i++)
8994 XVECEXP (operands[3], 0, i + 1)
39403d82 8995 = gen_rtx_SET (VOIDmode,
7ef788f0 8996 adjust_address_nv (op0, SImode, i * 4),
c5c76735 8997 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 8998}")
8999
9caa3eb2 9000(define_insn "*store_multiple_power"
1fd4e8c1
RK		 9001 [(match_parallel 0 "store_multiple_operation"
9002 [(set (match_operand:SI 1 "indirect_operand" "=Q")
cd2b37d9 9003 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 9004 (clobber (match_scratch:SI 3 "=q"))])]
7e69e155 9005 "TARGET_STRING && TARGET_POWER"
b7ff3d82
DE		 9006 "{stsi|stswi} %2,%P1,%O0"
9007 [(set_attr "type" "store")])
d14a6d05 9008
e46e3130 9009(define_insn "*stmsi8"
d14a6d05 9010 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 9011 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9012 (match_operand:SI 2 "gpc_reg_operand" "r"))
9013 (clobber (match_scratch:SI 3 "X"))
9014 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9015 (match_operand:SI 4 "gpc_reg_operand" "r"))
9016 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9017 (match_operand:SI 5 "gpc_reg_operand" "r"))
9018 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9019 (match_operand:SI 6 "gpc_reg_operand" "r"))
9020 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9021 (match_operand:SI 7 "gpc_reg_operand" "r"))
9022 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9023 (match_operand:SI 8 "gpc_reg_operand" "r"))
9024 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9025 (match_operand:SI 9 "gpc_reg_operand" "r"))
9026 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9027 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9028 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9029 "{stsi|stswi} %2,%1,%O0"
9030 [(set_attr "type" "store")])
9031
9032(define_insn "*stmsi7"
9033 [(match_parallel 0 "store_multiple_operation"
9034 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9035 (match_operand:SI 2 "gpc_reg_operand" "r"))
9036 (clobber (match_scratch:SI 3 "X"))
9037 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9038 (match_operand:SI 4 "gpc_reg_operand" "r"))
9039 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9040 (match_operand:SI 5 "gpc_reg_operand" "r"))
9041 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9042 (match_operand:SI 6 "gpc_reg_operand" "r"))
9043 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9044 (match_operand:SI 7 "gpc_reg_operand" "r"))
9045 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9046 (match_operand:SI 8 "gpc_reg_operand" "r"))
9047 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9048 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9049 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9050 "{stsi|stswi} %2,%1,%O0"
9051 [(set_attr "type" "store")])
9052
9053(define_insn "*stmsi6"
9054 [(match_parallel 0 "store_multiple_operation"
9055 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9056 (match_operand:SI 2 "gpc_reg_operand" "r"))
9057 (clobber (match_scratch:SI 3 "X"))
9058 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9059 (match_operand:SI 4 "gpc_reg_operand" "r"))
9060 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9061 (match_operand:SI 5 "gpc_reg_operand" "r"))
9062 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9063 (match_operand:SI 6 "gpc_reg_operand" "r"))
9064 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9065 (match_operand:SI 7 "gpc_reg_operand" "r"))
9066 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9067 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9068 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9069 "{stsi|stswi} %2,%1,%O0"
9070 [(set_attr "type" "store")])
9071
9072(define_insn "*stmsi5"
9073 [(match_parallel 0 "store_multiple_operation"
9074 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9075 (match_operand:SI 2 "gpc_reg_operand" "r"))
9076 (clobber (match_scratch:SI 3 "X"))
9077 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9078 (match_operand:SI 4 "gpc_reg_operand" "r"))
9079 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9080 (match_operand:SI 5 "gpc_reg_operand" "r"))
9081 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9082 (match_operand:SI 6 "gpc_reg_operand" "r"))
9083 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9084 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9085 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9086 "{stsi|stswi} %2,%1,%O0"
9087 [(set_attr "type" "store")])
9088
9089(define_insn "*stmsi4"
9090 [(match_parallel 0 "store_multiple_operation"
9091 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9092 (match_operand:SI 2 "gpc_reg_operand" "r"))
9093 (clobber (match_scratch:SI 3 "X"))
9094 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9095 (match_operand:SI 4 "gpc_reg_operand" "r"))
9096 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9097 (match_operand:SI 5 "gpc_reg_operand" "r"))
9098 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9099 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9100 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82
DE		 9101 "{stsi|stswi} %2,%1,%O0"
9102 [(set_attr "type" "store")])
7e69e155 9103
e46e3130
DJ		 9104(define_insn "*stmsi3"
9105 [(match_parallel 0 "store_multiple_operation"
9106 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9107 (match_operand:SI 2 "gpc_reg_operand" "r"))
9108 (clobber (match_scratch:SI 3 "X"))
9109 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9110 (match_operand:SI 4 "gpc_reg_operand" "r"))
9111 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9112 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9113 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9114 "{stsi|stswi} %2,%1,%O0"
9115 [(set_attr "type" "store")])
7e69e155
MM		 9116\f
9117;; String/block move insn.
9118;; Argument 0 is the destination
9119;; Argument 1 is the source
9120;; Argument 2 is the length
9121;; Argument 3 is the alignment
9122
9123(define_expand "movstrsi"
b6c9286a
MM		 9124 [(parallel [(set (match_operand:BLK 0 "" "")
9125 (match_operand:BLK 1 "" ""))
9126 (use (match_operand:SI 2 "" ""))
9127 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9128 ""
9129 "
9130{
9131 if (expand_block_move (operands))
9132 DONE;
9133 else
9134 FAIL;
9135}")
9136
9137;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9138;; register allocator doesn't have a clue about allocating 8 word registers.
9139;; rD/rS = r5 is preferred, efficient form.
7e69e155 9140(define_expand "movstrsi_8reg"
b6c9286a
MM		 9141 [(parallel [(set (match_operand 0 "" "")
9142 (match_operand 1 "" ""))
9143 (use (match_operand 2 "" ""))
9144 (use (match_operand 3 "" ""))
7e69e155
MM		 9145 (clobber (reg:SI 5))
9146 (clobber (reg:SI 6))
9147 (clobber (reg:SI 7))
9148 (clobber (reg:SI 8))
9149 (clobber (reg:SI 9))
9150 (clobber (reg:SI 10))
9151 (clobber (reg:SI 11))
9152 (clobber (reg:SI 12))
3c67b673 9153 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9154 "TARGET_STRING"
9155 "")
9156
9157(define_insn ""
52d3af72
DE		 9158 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9159 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9160 (use (match_operand:SI 2 "immediate_operand" "i"))
9161 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9162 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9163 (clobber (reg:SI 6))
9164 (clobber (reg:SI 7))
9165 (clobber (reg:SI 8))
9166 (clobber (reg:SI 9))
9167 (clobber (reg:SI 10))
9168 (clobber (reg:SI 11))
9169 (clobber (reg:SI 12))
3c67b673 9170 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9171 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9172 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9173 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9174 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9175 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9176 && REGNO (operands[4]) == 5"
9177 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9178 [(set_attr "type" "load")
9179 (set_attr "length" "8")])
7e69e155
MM		 9180
9181(define_insn ""
52d3af72
DE		 9182 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9183 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9184 (use (match_operand:SI 2 "immediate_operand" "i"))
9185 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9186 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9187 (clobber (reg:SI 6))
9188 (clobber (reg:SI 7))
9189 (clobber (reg:SI 8))
9190 (clobber (reg:SI 9))
9191 (clobber (reg:SI 10))
9192 (clobber (reg:SI 11))
9193 (clobber (reg:SI 12))
3c67b673 9194 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9195 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9196 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9197 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9198 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9199 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9200 && REGNO (operands[4]) == 5"
9201 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9202 [(set_attr "type" "load")
9203 (set_attr "length" "8")])
7e69e155 9204
09a625f7
TR		 9205(define_insn ""
9206 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9207 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9208 (use (match_operand:SI 2 "immediate_operand" "i"))
9209 (use (match_operand:SI 3 "immediate_operand" "i"))
9210 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9211 (clobber (reg:SI 6))
9212 (clobber (reg:SI 7))
9213 (clobber (reg:SI 8))
9214 (clobber (reg:SI 9))
9215 (clobber (reg:SI 10))
9216 (clobber (reg:SI 11))
9217 (clobber (reg:SI 12))
9218 (clobber (match_scratch:SI 5 "X"))]
9219 "TARGET_STRING && TARGET_POWERPC64
9220 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9221 || INTVAL (operands[2]) == 0)
9222 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9223 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9224 && REGNO (operands[4]) == 5"
9225 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9226 [(set_attr "type" "load")
9227 (set_attr "length" "8")])
9228
7e69e155 9229;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9230;; register allocator doesn't have a clue about allocating 6 word registers.
9231;; rD/rS = r5 is preferred, efficient form.
7e69e155 9232(define_expand "movstrsi_6reg"
b6c9286a
MM		 9233 [(parallel [(set (match_operand 0 "" "")
9234 (match_operand 1 "" ""))
9235 (use (match_operand 2 "" ""))
9236 (use (match_operand 3 "" ""))
f9562f27
DE		 9237 (clobber (reg:SI 5))
9238 (clobber (reg:SI 6))
7e69e155
MM		 9239 (clobber (reg:SI 7))
9240 (clobber (reg:SI 8))
9241 (clobber (reg:SI 9))
9242 (clobber (reg:SI 10))
3c67b673 9243 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9244 "TARGET_STRING"
9245 "")
9246
9247(define_insn ""
52d3af72
DE		 9248 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9249 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9250 (use (match_operand:SI 2 "immediate_operand" "i"))
9251 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9252 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9253 (clobber (reg:SI 6))
9254 (clobber (reg:SI 7))
7e69e155
MM		 9255 (clobber (reg:SI 8))
9256 (clobber (reg:SI 9))
9257 (clobber (reg:SI 10))
3c67b673 9258 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9259 "TARGET_STRING && TARGET_POWER
9260 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9261 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9262 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9263 && REGNO (operands[4]) == 5"
3c67b673 9264 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9265 [(set_attr "type" "load")
9266 (set_attr "length" "8")])
7e69e155
MM		 9267
9268(define_insn ""
52d3af72
DE		 9269 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9270 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9271 (use (match_operand:SI 2 "immediate_operand" "i"))
9272 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9273 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9274 (clobber (reg:SI 6))
9275 (clobber (reg:SI 7))
7e69e155
MM		 9276 (clobber (reg:SI 8))
9277 (clobber (reg:SI 9))
9278 (clobber (reg:SI 10))
3c67b673 9279 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9280 "TARGET_STRING && ! TARGET_POWER
7e69e155 9281 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9282 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9283 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9284 && REGNO (operands[4]) == 5"
3c67b673 9285 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9286 [(set_attr "type" "load")
9287 (set_attr "length" "8")])
7e69e155 9288
09a625f7
TR		 9289(define_insn ""
9290 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9291 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9292 (use (match_operand:SI 2 "immediate_operand" "i"))
9293 (use (match_operand:SI 3 "immediate_operand" "i"))
9294 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9295 (clobber (reg:SI 6))
9296 (clobber (reg:SI 7))
9297 (clobber (reg:SI 8))
9298 (clobber (reg:SI 9))
9299 (clobber (reg:SI 10))
9300 (clobber (match_scratch:SI 5 "X"))]
9301 "TARGET_STRING && TARGET_POWERPC64
9302 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9303 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9304 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9305 && REGNO (operands[4]) == 5"
9306 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9307 [(set_attr "type" "load")
9308 (set_attr "length" "8")])
9309
f9562f27
DE		 9310;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9311;; problems with TImode.
9312;; rD/rS = r5 is preferred, efficient form.
7e69e155 9313(define_expand "movstrsi_4reg"
b6c9286a
MM		 9314 [(parallel [(set (match_operand 0 "" "")
9315 (match_operand 1 "" ""))
9316 (use (match_operand 2 "" ""))
9317 (use (match_operand 3 "" ""))
f9562f27
DE		 9318 (clobber (reg:SI 5))
9319 (clobber (reg:SI 6))
9320 (clobber (reg:SI 7))
9321 (clobber (reg:SI 8))
3c67b673 9322 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9323 "TARGET_STRING"
9324 "")
9325
9326(define_insn ""
52d3af72
DE		 9327 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9328 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9329 (use (match_operand:SI 2 "immediate_operand" "i"))
9330 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9331 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9332 (clobber (reg:SI 6))
9333 (clobber (reg:SI 7))
9334 (clobber (reg:SI 8))
3c67b673 9335 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9336 "TARGET_STRING && TARGET_POWER
9337 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9338 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9339 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9340 && REGNO (operands[4]) == 5"
3c67b673 9341 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9342 [(set_attr "type" "load")
9343 (set_attr "length" "8")])
7e69e155
MM		 9344
9345(define_insn ""
52d3af72
DE		 9346 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9347 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9348 (use (match_operand:SI 2 "immediate_operand" "i"))
9349 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9350 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9351 (clobber (reg:SI 6))
9352 (clobber (reg:SI 7))
9353 (clobber (reg:SI 8))
3c67b673 9354 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9355 "TARGET_STRING && ! TARGET_POWER
7e69e155 9356 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9357 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9358 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9359 && REGNO (operands[4]) == 5"
3c67b673 9360 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9361 [(set_attr "type" "load")
9362 (set_attr "length" "8")])
7e69e155 9363
09a625f7
TR		 9364(define_insn ""
9365 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9366 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9367 (use (match_operand:SI 2 "immediate_operand" "i"))
9368 (use (match_operand:SI 3 "immediate_operand" "i"))
9369 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9370 (clobber (reg:SI 6))
9371 (clobber (reg:SI 7))
9372 (clobber (reg:SI 8))
9373 (clobber (match_scratch:SI 5 "X"))]
9374 "TARGET_STRING && TARGET_POWERPC64
9375 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9376 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9377 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9378 && REGNO (operands[4]) == 5"
9379 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9380 [(set_attr "type" "load")
9381 (set_attr "length" "8")])
9382
7e69e155
MM		 9383;; Move up to 8 bytes at a time.
9384(define_expand "movstrsi_2reg"
b6c9286a
MM		 9385 [(parallel [(set (match_operand 0 "" "")
9386 (match_operand 1 "" ""))
9387 (use (match_operand 2 "" ""))
9388 (use (match_operand 3 "" ""))
3c67b673
RK		 9389 (clobber (match_scratch:DI 4 ""))
9390 (clobber (match_scratch:SI 5 ""))])]
f9562f27 9391 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 9392 "")
9393
9394(define_insn ""
52d3af72
DE		 9395 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9396 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9397 (use (match_operand:SI 2 "immediate_operand" "i"))
9398 (use (match_operand:SI 3 "immediate_operand" "i"))
9399 (clobber (match_scratch:DI 4 "=&r"))
9400 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 9401 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 9402 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9403 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9404 [(set_attr "type" "load")
9405 (set_attr "length" "8")])
7e69e155
MM		 9406
9407(define_insn ""
52d3af72
DE		 9408 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9409 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9410 (use (match_operand:SI 2 "immediate_operand" "i"))
9411 (use (match_operand:SI 3 "immediate_operand" "i"))
9412 (clobber (match_scratch:DI 4 "=&r"))
9413 (clobber (match_scratch:SI 5 "X"))]
f9562f27 9414 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 9415 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 9416 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9417 [(set_attr "type" "load")
9418 (set_attr "length" "8")])
7e69e155
MM		 9419
9420;; Move up to 4 bytes at a time.
9421(define_expand "movstrsi_1reg"
b6c9286a
MM		 9422 [(parallel [(set (match_operand 0 "" "")
9423 (match_operand 1 "" ""))
9424 (use (match_operand 2 "" ""))
9425 (use (match_operand 3 "" ""))
3c67b673
RK		 9426 (clobber (match_scratch:SI 4 ""))
9427 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 9428 "TARGET_STRING"
9429 "")
9430
9431(define_insn ""
52d3af72
DE		 9432 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9433 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9434 (use (match_operand:SI 2 "immediate_operand" "i"))
9435 (use (match_operand:SI 3 "immediate_operand" "i"))
9436 (clobber (match_scratch:SI 4 "=&r"))
9437 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9438 "TARGET_STRING && TARGET_POWER
9439 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9440 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9441 [(set_attr "type" "load")
9442 (set_attr "length" "8")])
7e69e155
MM		 9443
9444(define_insn ""
52d3af72
DE		 9445 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9446 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9447 (use (match_operand:SI 2 "immediate_operand" "i"))
9448 (use (match_operand:SI 3 "immediate_operand" "i"))
9449 (clobber (match_scratch:SI 4 "=&r"))
9450 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9451 "TARGET_STRING && ! TARGET_POWER
7e69e155 9452 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7
TR		 9453 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9454 [(set_attr "type" "load")
9455 (set_attr "length" "8")])
9456
9457(define_insn ""
9458 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9459 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9460 (use (match_operand:SI 2 "immediate_operand" "i"))
9461 (use (match_operand:SI 3 "immediate_operand" "i"))
9462 (clobber (match_scratch:SI 4 "=&r"))
9463 (clobber (match_scratch:SI 5 "X"))]
9464 "TARGET_STRING && TARGET_POWERPC64
9465 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9466 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9467 [(set_attr "type" "load")
9468 (set_attr "length" "8")])
7e69e155 9469
1fd4e8c1 9470\f
7e69e155 9471;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 9472;; get by using pre-decrement or pre-increment, but the hardware can also
9473;; do cases where the increment is not the size of the object.
9474;;
9475;; In all these cases, we use operands 0 and 1 for the register being
9476;; incremented because those are the operands that local-alloc will
9477;; tie and these are the pair most likely to be tieable (and the ones
9478;; that will benefit the most).
9479
38c1f2d7 9480(define_insn "*movdi_update1"
51b8fc2c 9481 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 9482 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9483 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 9484 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9485 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9486 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9487 "@
9488 ldux %3,%0,%2
9489 ldu %3,%2(%0)"
b54cf83a 9490 [(set_attr "type" "load_ux,load_u")])
287f13ff 9491
4697a36c 9492(define_insn "movdi_update"
51b8fc2c 9493 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9494 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c
RK		 9495 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9496 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9497 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9498 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9499 "@
9500 stdux %3,%0,%2
b7ff3d82 9501 stdu %3,%2(%0)"
b54cf83a 9502 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 9503
38c1f2d7 9504(define_insn "*movsi_update1"
cd2b37d9
RK		 9505 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9506 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9507 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9508 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9509 (plus:SI (match_dup 1) (match_dup 2)))]
f7b3ab8a 9510 "TARGET_UPDATE"
1fd4e8c1 9511 "@
ca7f5001
RK		 9512 {lux|lwzux} %3,%0,%2
9513 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 9514 [(set_attr "type" "load_ux,load_u")])
9515
9516(define_insn "*movsi_update2"
9517 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9518 (sign_extend:DI
9519 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9520 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9521 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9522 (plus:DI (match_dup 1) (match_dup 2)))]
9523 "TARGET_POWERPC64"
9524 "lwaux %3,%0,%2"
9525 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 9526
4697a36c 9527(define_insn "movsi_update"
cd2b37d9 9528 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9529 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9530 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9531 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9532 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9533 "TARGET_UPDATE"
1fd4e8c1 9534 "@
ca7f5001 9535 {stux|stwux} %3,%0,%2
b7ff3d82 9536 {stu|stwu} %3,%2(%0)"
b54cf83a 9537 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9538
b54cf83a 9539(define_insn "*movhi_update1"
cd2b37d9
RK		 9540 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9541 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9542 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9543 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9544 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9545 "TARGET_UPDATE"
1fd4e8c1 9546 "@
5f243543
RK		 9547 lhzux %3,%0,%2
9548 lhzu %3,%2(%0)"
b54cf83a 9549 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9550
38c1f2d7 9551(define_insn "*movhi_update2"
cd2b37d9 9552 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9553 (zero_extend:SI
cd2b37d9 9554 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9555 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9556 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9557 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9558 "TARGET_UPDATE"
1fd4e8c1 9559 "@
5f243543
RK		 9560 lhzux %3,%0,%2
9561 lhzu %3,%2(%0)"
b54cf83a 9562 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9563
38c1f2d7 9564(define_insn "*movhi_update3"
cd2b37d9 9565 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9566 (sign_extend:SI
cd2b37d9 9567 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9568 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9569 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9570 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9571 "TARGET_UPDATE"
1fd4e8c1 9572 "@
5f243543
RK		 9573 lhaux %3,%0,%2
9574 lhau %3,%2(%0)"
b54cf83a 9575 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 9576
38c1f2d7 9577(define_insn "*movhi_update4"
cd2b37d9 9578 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9579 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9580 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9581 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9582 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9583 "TARGET_UPDATE"
1fd4e8c1 9584 "@
5f243543 9585 sthux %3,%0,%2
b7ff3d82 9586 sthu %3,%2(%0)"
b54cf83a 9587 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9588
38c1f2d7 9589(define_insn "*movqi_update1"
cd2b37d9
RK		 9590 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9591 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9592 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9593 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9594 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9595 "TARGET_UPDATE"
1fd4e8c1 9596 "@
5f243543
RK		 9597 lbzux %3,%0,%2
9598 lbzu %3,%2(%0)"
b54cf83a 9599 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9600
38c1f2d7 9601(define_insn "*movqi_update2"
cd2b37d9 9602 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9603 (zero_extend:SI
cd2b37d9 9604 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9605 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9606 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9607 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9608 "TARGET_UPDATE"
1fd4e8c1 9609 "@
5f243543
RK		 9610 lbzux %3,%0,%2
9611 lbzu %3,%2(%0)"
b54cf83a 9612 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9613
38c1f2d7 9614(define_insn "*movqi_update3"
cd2b37d9 9615 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9616 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9617 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9618 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9619 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9620 "TARGET_UPDATE"
1fd4e8c1 9621 "@
5f243543 9622 stbux %3,%0,%2
b7ff3d82 9623 stbu %3,%2(%0)"
b54cf83a 9624 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9625
38c1f2d7 9626(define_insn "*movsf_update1"
cd2b37d9 9627 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 9628 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9629 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9630 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9631 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9632 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9633 "@
5f243543
RK		 9634 lfsux %3,%0,%2
9635 lfsu %3,%2(%0)"
b54cf83a 9636 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 9637
38c1f2d7 9638(define_insn "*movsf_update2"
cd2b37d9 9639 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9640 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9641 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9642 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9643 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9644 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9645 "@
85fff2f3 9646 stfsux %3,%0,%2
b7ff3d82 9647 stfsu %3,%2(%0)"
b54cf83a 9648 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 9649
38c1f2d7
MM		 9650(define_insn "*movsf_update3"
9651 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9652 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9653 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9654 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9655 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9656 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 9657 "@
9658 {lux|lwzux} %3,%0,%2
9659 {lu|lwzu} %3,%2(%0)"
b54cf83a 9660 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 9661
9662(define_insn "*movsf_update4"
9663 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9664 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9665 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9666 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9667 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9668 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 9669 "@
9670 {stux|stwux} %3,%0,%2
9671 {stu|stwu} %3,%2(%0)"
b54cf83a 9672 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 9673
9674(define_insn "*movdf_update1"
cd2b37d9
RK		 9675 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9676 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9677 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9678 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9679 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9680 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9681 "@
5f243543
RK		 9682 lfdux %3,%0,%2
9683 lfdu %3,%2(%0)"
b54cf83a 9684 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 9685
38c1f2d7 9686(define_insn "*movdf_update2"
cd2b37d9 9687 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9688 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9689 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9690 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9691 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9692 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9693 "@
5f243543 9694 stfdux %3,%0,%2
b7ff3d82 9695 stfdu %3,%2(%0)"
b54cf83a 9696 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 9697
9698;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9699
9700(define_peephole
9701 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9702 (match_operand:DF 1 "memory_operand" ""))
9703 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9704 (match_operand:DF 3 "memory_operand" ""))]
9705 "TARGET_POWER2
a3170dc6 9706 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3
RK		 9707 && registers_ok_for_quad_peep (operands[0], operands[2])
9708 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9709 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9710 "lfq%U1%X1 %0,%1")
9711
9712(define_peephole
9713 [(set (match_operand:DF 0 "memory_operand" "")
9714 (match_operand:DF 1 "gpc_reg_operand" "f"))
9715 (set (match_operand:DF 2 "memory_operand" "")
9716 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9717 "TARGET_POWER2
a3170dc6 9718 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3
RK		 9719 && registers_ok_for_quad_peep (operands[1], operands[3])
9720 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9721 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9722 "stfq%U0%X0 %1,%0")
1fd4e8c1 9723\f
c4501e62
JJ		 9724;; TLS support.
9725
9726;; "b" output constraint here and on tls_ld to support tls linker optimization.
9727(define_insn "tls_gd_32"
9728 [(set (match_operand:SI 0 "register_operand" "=b")
9729 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9730 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9731 UNSPEC_TLSGD))]
9732 "HAVE_AS_TLS && !TARGET_64BIT"
9733 "addi %0,%1,%2@got@tlsgd")
9734
9735(define_insn "tls_gd_64"
9736 [(set (match_operand:DI 0 "register_operand" "=b")
9737 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9738 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9739 UNSPEC_TLSGD))]
9740 "HAVE_AS_TLS && TARGET_64BIT"
9741 "addi %0,%1,%2@got@tlsgd")
9742
9743(define_insn "tls_ld_32"
9744 [(set (match_operand:SI 0 "register_operand" "=b")
9745 (unspec:SI [(match_operand:SI 1 "register_operand" "b")]
9746 UNSPEC_TLSLD))]
9747 "HAVE_AS_TLS && !TARGET_64BIT"
9748 "addi %0,%1,%&@got@tlsld")
9749
9750(define_insn "tls_ld_64"
9751 [(set (match_operand:DI 0 "register_operand" "=b")
9752 (unspec:DI [(match_operand:DI 1 "register_operand" "b")]
9753 UNSPEC_TLSLD))]
9754 "HAVE_AS_TLS && TARGET_64BIT"
9755 "addi %0,%1,%&@got@tlsld")
9756
9757(define_insn "tls_dtprel_32"
9758 [(set (match_operand:SI 0 "register_operand" "=r")
9759 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9760 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9761 UNSPEC_TLSDTPREL))]
9762 "HAVE_AS_TLS && !TARGET_64BIT"
9763 "addi %0,%1,%2@dtprel")
9764
9765(define_insn "tls_dtprel_64"
9766 [(set (match_operand:DI 0 "register_operand" "=r")
9767 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9768 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9769 UNSPEC_TLSDTPREL))]
9770 "HAVE_AS_TLS && TARGET_64BIT"
9771 "addi %0,%1,%2@dtprel")
9772
9773(define_insn "tls_dtprel_ha_32"
9774 [(set (match_operand:SI 0 "register_operand" "=r")
9775 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9776 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9777 UNSPEC_TLSDTPRELHA))]
9778 "HAVE_AS_TLS && !TARGET_64BIT"
9779 "addis %0,%1,%2@dtprel@ha")
9780
9781(define_insn "tls_dtprel_ha_64"
9782 [(set (match_operand:DI 0 "register_operand" "=r")
9783 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9784 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9785 UNSPEC_TLSDTPRELHA))]
9786 "HAVE_AS_TLS && TARGET_64BIT"
9787 "addis %0,%1,%2@dtprel@ha")
9788
9789(define_insn "tls_dtprel_lo_32"
9790 [(set (match_operand:SI 0 "register_operand" "=r")
9791 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9792 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9793 UNSPEC_TLSDTPRELLO))]
9794 "HAVE_AS_TLS && !TARGET_64BIT"
9795 "addi %0,%1,%2@dtprel@l")
9796
9797(define_insn "tls_dtprel_lo_64"
9798 [(set (match_operand:DI 0 "register_operand" "=r")
9799 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9800 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9801 UNSPEC_TLSDTPRELLO))]
9802 "HAVE_AS_TLS && TARGET_64BIT"
9803 "addi %0,%1,%2@dtprel@l")
9804
9805(define_insn "tls_got_dtprel_32"
9806 [(set (match_operand:SI 0 "register_operand" "=r")
9807 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9808 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9809 UNSPEC_TLSGOTDTPREL))]
9810 "HAVE_AS_TLS && !TARGET_64BIT"
9811 "lwz %0,%2@got@dtprel(%1)")
9812
9813(define_insn "tls_got_dtprel_64"
9814 [(set (match_operand:DI 0 "register_operand" "=r")
9815 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9816 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9817 UNSPEC_TLSGOTDTPREL))]
9818 "HAVE_AS_TLS && TARGET_64BIT"
9819 "ld %0,%2@got@dtprel(%1)")
9820
9821(define_insn "tls_tprel_32"
9822 [(set (match_operand:SI 0 "register_operand" "=r")
9823 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9824 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9825 UNSPEC_TLSTPREL))]
9826 "HAVE_AS_TLS && !TARGET_64BIT"
9827 "addi %0,%1,%2@tprel")
9828
9829(define_insn "tls_tprel_64"
9830 [(set (match_operand:DI 0 "register_operand" "=r")
9831 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9832 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9833 UNSPEC_TLSTPREL))]
9834 "HAVE_AS_TLS && TARGET_64BIT"
9835 "addi %0,%1,%2@tprel")
9836
9837(define_insn "tls_tprel_ha_32"
9838 [(set (match_operand:SI 0 "register_operand" "=r")
9839 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9840 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9841 UNSPEC_TLSTPRELHA))]
9842 "HAVE_AS_TLS && !TARGET_64BIT"
9843 "addis %0,%1,%2@tprel@ha")
9844
9845(define_insn "tls_tprel_ha_64"
9846 [(set (match_operand:DI 0 "register_operand" "=r")
9847 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9848 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9849 UNSPEC_TLSTPRELHA))]
9850 "HAVE_AS_TLS && TARGET_64BIT"
9851 "addis %0,%1,%2@tprel@ha")
9852
9853(define_insn "tls_tprel_lo_32"
9854 [(set (match_operand:SI 0 "register_operand" "=r")
9855 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9856 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9857 UNSPEC_TLSTPRELLO))]
9858 "HAVE_AS_TLS && !TARGET_64BIT"
9859 "addi %0,%1,%2@tprel@l")
9860
9861(define_insn "tls_tprel_lo_64"
9862 [(set (match_operand:DI 0 "register_operand" "=r")
9863 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9864 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9865 UNSPEC_TLSTPRELLO))]
9866 "HAVE_AS_TLS && TARGET_64BIT"
9867 "addi %0,%1,%2@tprel@l")
9868
c1207243 9869;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 9870;; optimization. The linker may edit the instructions emitted by a
9871;; tls_got_tprel/tls_tls pair to addis,addi.
9872(define_insn "tls_got_tprel_32"
9873 [(set (match_operand:SI 0 "register_operand" "=b")
9874 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9875 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9876 UNSPEC_TLSGOTTPREL))]
9877 "HAVE_AS_TLS && !TARGET_64BIT"
9878 "lwz %0,%2@got@tprel(%1)")
9879
9880(define_insn "tls_got_tprel_64"
9881 [(set (match_operand:DI 0 "register_operand" "=b")
9882 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9883 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9884 UNSPEC_TLSGOTTPREL))]
9885 "HAVE_AS_TLS && TARGET_64BIT"
9886 "ld %0,%2@got@tprel(%1)")
9887
9888(define_insn "tls_tls_32"
9889 [(set (match_operand:SI 0 "register_operand" "=r")
9890 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9891 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9892 UNSPEC_TLSTLS))]
9893 "HAVE_AS_TLS && !TARGET_64BIT"
9894 "add %0,%1,%2@tls")
9895
9896(define_insn "tls_tls_64"
9897 [(set (match_operand:DI 0 "register_operand" "=r")
9898 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9899 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9900 UNSPEC_TLSTLS))]
9901 "HAVE_AS_TLS && TARGET_64BIT"
9902 "add %0,%1,%2@tls")
9903\f
1fd4e8c1
RK		 9904;; Next come insns related to the calling sequence.
9905;;
9906;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 9907;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 9908
9909(define_expand "allocate_stack"
52d3af72 9910 [(set (match_operand 0 "gpc_reg_operand" "=r")
a260abc9
DE		 9911 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9912 (set (reg 1)
9913 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 9914 ""
9915 "
4697a36c 9916{ rtx chain = gen_reg_rtx (Pmode);
39403d82 9917 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 9918 rtx neg_op0;
1fd4e8c1
RK		 9919
9920 emit_move_insn (chain, stack_bot);
4697a36c 9921
a157febd
GK		 9922 /* Check stack bounds if necessary. */
9923 if (current_function_limit_stack)
9924 {
9925 rtx available;
9926 available = expand_binop (Pmode, sub_optab,
9927 stack_pointer_rtx, stack_limit_rtx,
9928 NULL_RTX, 1, OPTAB_WIDEN);
9929 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9930 }
9931
e9a25f70
JL		 9932 if (GET_CODE (operands[1]) != CONST_INT
9933 || INTVAL (operands[1]) < -32767
9934 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 9935 {
9936 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 9937 if (TARGET_32BIT)
e9a25f70 9938 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 9939 else
e9a25f70 9940 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 9941 }
9942 else
e9a25f70 9943 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 9944
38c1f2d7
MM		 9945 if (TARGET_UPDATE)
9946 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9947 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
4697a36c 9948
38c1f2d7
MM		 9949 else
9950 {
9951 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9952 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
39403d82 9953 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
38c1f2d7 9954 }
e9a25f70
JL		 9955
9956 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 9957 DONE;
9958}")
59257ff7
RK		 9959
9960;; These patterns say how to save and restore the stack pointer. We need not
9961;; save the stack pointer at function level since we are careful to
9962;; preserve the backchain. At block level, we have to restore the backchain
9963;; when we restore the stack pointer.
9964;;
9965;; For nonlocal gotos, we must save both the stack pointer and its
9966;; backchain and restore both. Note that in the nonlocal case, the
9967;; save area is a memory location.
9968
9969(define_expand "save_stack_function"
ff381587
MM		 9970 [(match_operand 0 "any_operand" "")
9971 (match_operand 1 "any_operand" "")]
59257ff7 9972 ""
ff381587 9973 "DONE;")
59257ff7
RK		 9974
9975(define_expand "restore_stack_function"
ff381587
MM		 9976 [(match_operand 0 "any_operand" "")
9977 (match_operand 1 "any_operand" "")]
59257ff7 9978 ""
ff381587 9979 "DONE;")
59257ff7
RK		 9980
9981(define_expand "restore_stack_block"
dfdfa60f
DE		 9982 [(use (match_operand 0 "register_operand" ""))
9983 (set (match_dup 2) (match_dup 3))
a260abc9 9984 (set (match_dup 0) (match_operand 1 "register_operand" ""))
dfdfa60f 9985 (set (match_dup 3) (match_dup 2))]
59257ff7
RK		 9986 ""
9987 "
dfdfa60f
DE		 9988{
9989 operands[2] = gen_reg_rtx (Pmode);
39403d82 9990 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
dfdfa60f 9991}")
59257ff7
RK		 9992
9993(define_expand "save_stack_nonlocal"
a260abc9
DE		 9994 [(match_operand 0 "memory_operand" "")
9995 (match_operand 1 "register_operand" "")]
59257ff7
RK		 9996 ""
9997 "
9998{
a260abc9 9999 rtx temp = gen_reg_rtx (Pmode);
59257ff7
RK		 10000
10001 /* Copy the backchain to the first word, sp to the second. */
39403d82 10002 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
c5c76735
JL		 10003 emit_move_insn (operand_subword (operands[0], 0, 0,
10004 (TARGET_32BIT ? DImode : TImode)),
a260abc9
DE		 10005 temp);
10006 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
10007 operands[1]);
59257ff7
RK		 10008 DONE;
10009}")
7e69e155 10010
59257ff7 10011(define_expand "restore_stack_nonlocal"
a260abc9
DE		 10012 [(match_operand 0 "register_operand" "")
10013 (match_operand 1 "memory_operand" "")]
59257ff7
RK		 10014 ""
10015 "
10016{
a260abc9 10017 rtx temp = gen_reg_rtx (Pmode);
59257ff7
RK		 10018
10019 /* Restore the backchain from the first word, sp from the second. */
a260abc9
DE		 10020 emit_move_insn (temp,
10021 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
10022 emit_move_insn (operands[0],
c5c76735
JL		 10023 operand_subword (operands[1], 1, 0,
10024 (TARGET_32BIT ? DImode : TImode)));
39403d82 10025 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
59257ff7
RK		 10026 DONE;
10027}")
9ebbca7d
GK		 10028\f
10029;; TOC register handling.
b6c9286a 10030
9ebbca7d 10031;; Code to initialize the TOC register...
f0f6a223 10032
9ebbca7d 10033(define_insn "load_toc_aix_si"
e72247f4 10034 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 10035 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10036 (use (reg:SI 2))])]
2bfcf297 10037 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 10038 "*
10039{
9ebbca7d
GK		 10040 char buf[30];
10041 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 10042 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10043 operands[2] = gen_rtx_REG (Pmode, 2);
10044 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 10045}"
10046 [(set_attr "type" "load")])
9ebbca7d
GK		 10047
10048(define_insn "load_toc_aix_di"
e72247f4 10049 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 10050 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10051 (use (reg:DI 2))])]
2bfcf297 10052 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 10053 "*
10054{
10055 char buf[30];
f585a356
DE		 10056#ifdef TARGET_RELOCATABLE
10057 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10058 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10059#else
9ebbca7d 10060 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 10061#endif
2bfcf297
DB		 10062 if (TARGET_ELF)
10063 strcat (buf, \"@toc\");
a8a05998 10064 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10065 operands[2] = gen_rtx_REG (Pmode, 2);
10066 return \"ld %0,%1(%2)\";
10067}"
10068 [(set_attr "type" "load")])
10069
10070(define_insn "load_toc_v4_pic_si"
10071 [(set (match_operand:SI 0 "register_operand" "=l")
615158e2 10072 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 10073 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 10074 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10075 [(set_attr "type" "branch")
10076 (set_attr "length" "4")])
10077
9ebbca7d
GK		 10078(define_insn "load_toc_v4_PIC_1"
10079 [(set (match_operand:SI 0 "register_operand" "=l")
10080 (match_operand:SI 1 "immediate_operand" "s"))
c4501e62 10081 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
20b71b17 10082 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
df7a8989 10083 "bcl 20,31,%1\\n%1:"
9ebbca7d
GK		 10084 [(set_attr "type" "branch")
10085 (set_attr "length" "4")])
10086
10087(define_insn "load_toc_v4_PIC_1b"
10088 [(set (match_operand:SI 0 "register_operand" "=l")
10089 (match_operand:SI 1 "immediate_operand" "s"))
c4501e62
JJ		 10090 (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
10091 UNSPEC_TOCPTR))]
20b71b17 10092 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
c4501e62 10093 "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
9ebbca7d
GK		 10094 [(set_attr "type" "branch")
10095 (set_attr "length" "8")])
10096
10097(define_insn "load_toc_v4_PIC_2"
f585a356 10098 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 10099 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 10100 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10101 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 10102 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 10103 "{l|lwz} %0,%2-%3(%1)"
10104 [(set_attr "type" "load")])
10105
ee890fe2
SS		 10106(define_insn "load_macho_picbase"
10107 [(set (match_operand:SI 0 "register_operand" "=l")
615158e2
JJ		 10108 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10109 UNSPEC_LD_MPIC))]
ee890fe2 10110 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
f51eee6a 10111 "bcl 20,31,%1\\n%1:"
ee890fe2
SS		 10112 [(set_attr "type" "branch")
10113 (set_attr "length" "4")])
10114
f51eee6a
GK		 10115(define_insn "macho_correct_pic"
10116 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8291cc0e 10117 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
f51eee6a
GK		 10118 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
10119 (match_operand:SI 3 "immediate_operand" "s")]
615158e2 10120 UNSPEC_MPIC_CORRECT)))]
f51eee6a 10121 "DEFAULT_ABI == ABI_DARWIN"
8291cc0e 10122 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
f51eee6a
GK		 10123 [(set_attr "length" "8")])
10124
9ebbca7d
GK		 10125;; If the TOC is shared over a translation unit, as happens with all
10126;; the kinds of PIC that we support, we need to restore the TOC
10127;; pointer only when jumping over units of translation.
f51eee6a 10128;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 10129
10130(define_expand "builtin_setjmp_receiver"
10131 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 10132 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 10133 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10134 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 10135 "
10136{
84d7dd4a 10137#if TARGET_MACHO
f51eee6a
GK		 10138 if (DEFAULT_ABI == ABI_DARWIN)
10139 {
d24652ee 10140 const char *picbase = machopic_function_base_name ();
485bad26 10141 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
f51eee6a
GK		 10142 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10143 rtx tmplabrtx;
10144 char tmplab[20];
10145
10146 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10147 CODE_LABEL_NUMBER (operands[0]));
485bad26 10148 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a
GK		 10149
10150 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10151 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10152 }
10153 else
84d7dd4a 10154#endif
f51eee6a 10155 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 10156 DONE;
10157}")
10158\f
10159;; A function pointer under AIX is a pointer to a data area whose first word
10160;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 10161;; pointer to its TOC, and whose third word contains a value to place in the
10162;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 10163;; "trampoline" need not have any executable code.
b6c9286a 10164
cccf3bdc
DE		 10165(define_expand "call_indirect_aix32"
10166 [(set (match_dup 2)
10167 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10168 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10169 (reg:SI 2))
10170 (set (reg:SI 2)
10171 (mem:SI (plus:SI (match_dup 0)
10172 (const_int 4))))
10173 (set (reg:SI 11)
10174 (mem:SI (plus:SI (match_dup 0)
10175 (const_int 8))))
10176 (parallel [(call (mem:SI (match_dup 2))
10177 (match_operand 1 "" ""))
10178 (use (reg:SI 2))
10179 (use (reg:SI 11))
10180 (set (reg:SI 2)
10181 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10182 (clobber (scratch:SI))])]
10183 "TARGET_32BIT"
10184 "
10185{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 10186
cccf3bdc
DE		 10187(define_expand "call_indirect_aix64"
10188 [(set (match_dup 2)
10189 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10190 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10191 (reg:DI 2))
10192 (set (reg:DI 2)
10193 (mem:DI (plus:DI (match_dup 0)
10194 (const_int 8))))
10195 (set (reg:DI 11)
10196 (mem:DI (plus:DI (match_dup 0)
10197 (const_int 16))))
10198 (parallel [(call (mem:SI (match_dup 2))
10199 (match_operand 1 "" ""))
10200 (use (reg:DI 2))
10201 (use (reg:DI 11))
10202 (set (reg:DI 2)
10203 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10204 (clobber (scratch:SI))])]
10205 "TARGET_64BIT"
10206 "
10207{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 10208
cccf3bdc
DE		 10209(define_expand "call_value_indirect_aix32"
10210 [(set (match_dup 3)
10211 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10212 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10213 (reg:SI 2))
10214 (set (reg:SI 2)
10215 (mem:SI (plus:SI (match_dup 1)
10216 (const_int 4))))
10217 (set (reg:SI 11)
10218 (mem:SI (plus:SI (match_dup 1)
10219 (const_int 8))))
10220 (parallel [(set (match_operand 0 "" "")
10221 (call (mem:SI (match_dup 3))
10222 (match_operand 2 "" "")))
10223 (use (reg:SI 2))
10224 (use (reg:SI 11))
10225 (set (reg:SI 2)
10226 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10227 (clobber (scratch:SI))])]
10228 "TARGET_32BIT"
10229 "
10230{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 10231
cccf3bdc
DE		 10232(define_expand "call_value_indirect_aix64"
10233 [(set (match_dup 3)
10234 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10235 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10236 (reg:DI 2))
10237 (set (reg:DI 2)
10238 (mem:DI (plus:DI (match_dup 1)
10239 (const_int 8))))
10240 (set (reg:DI 11)
10241 (mem:DI (plus:DI (match_dup 1)
10242 (const_int 16))))
10243 (parallel [(set (match_operand 0 "" "")
10244 (call (mem:SI (match_dup 3))
10245 (match_operand 2 "" "")))
10246 (use (reg:DI 2))
10247 (use (reg:DI 11))
10248 (set (reg:DI 2)
10249 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10250 (clobber (scratch:SI))])]
10251 "TARGET_64BIT"
10252 "
10253{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 10254
b6c9286a 10255;; Now the definitions for the call and call_value insns
1fd4e8c1 10256(define_expand "call"
a260abc9 10257 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 10258 (match_operand 1 "" ""))
4697a36c 10259 (use (match_operand 2 "" ""))
1fd4e8c1
RK		 10260 (clobber (scratch:SI))])]
10261 ""
10262 "
10263{
ee890fe2 10264#if TARGET_MACHO
ab82a49f 10265 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10266 operands[0] = machopic_indirect_call_target (operands[0]);
10267#endif
10268
1fd4e8c1
RK		 10269 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10270 abort ();
10271
10272 operands[0] = XEXP (operands[0], 0);
7509c759 10273
6a4cee5f 10274 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 10275 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
6a4cee5f 10276 || (INTVAL (operands[2]) & CALL_LONG) != 0)
1fd4e8c1 10277 {
6a4cee5f
MM		 10278 if (INTVAL (operands[2]) & CALL_LONG)
10279 operands[0] = rs6000_longcall_ref (operands[0]);
10280
cccf3bdc 10281 if (DEFAULT_ABI == ABI_V4
f607bc57 10282 || DEFAULT_ABI == ABI_DARWIN)
cccf3bdc 10283 operands[0] = force_reg (Pmode, operands[0]);
1fd4e8c1 10284
cccf3bdc
DE		 10285 else if (DEFAULT_ABI == ABI_AIX)
10286 {
10287 /* AIX function pointers are really pointers to a three word
10288 area. */
10289 emit_call_insn (TARGET_32BIT
10290 ? gen_call_indirect_aix32 (force_reg (SImode,
10291 operands[0]),
10292 operands[1])
10293 : gen_call_indirect_aix64 (force_reg (DImode,
10294 operands[0]),
10295 operands[1]));
10296 DONE;
b6c9286a 10297 }
cccf3bdc
DE		 10298 else
10299 abort ();
1fd4e8c1
RK		 10300 }
10301}")
10302
10303(define_expand "call_value"
10304 [(parallel [(set (match_operand 0 "" "")
a260abc9 10305 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 10306 (match_operand 2 "" "")))
4697a36c 10307 (use (match_operand 3 "" ""))
1fd4e8c1
RK		 10308 (clobber (scratch:SI))])]
10309 ""
10310 "
10311{
ee890fe2 10312#if TARGET_MACHO
ab82a49f 10313 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10314 operands[1] = machopic_indirect_call_target (operands[1]);
10315#endif
10316
1fd4e8c1
RK		 10317 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10318 abort ();
10319
10320 operands[1] = XEXP (operands[1], 0);
7509c759 10321
6a4cee5f 10322 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 10323 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
6a4cee5f 10324 || (INTVAL (operands[3]) & CALL_LONG) != 0)
1fd4e8c1 10325 {
6756293c 10326 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 10327 operands[1] = rs6000_longcall_ref (operands[1]);
10328
cccf3bdc 10329 if (DEFAULT_ABI == ABI_V4
f607bc57 10330 || DEFAULT_ABI == ABI_DARWIN)
cccf3bdc 10331 operands[0] = force_reg (Pmode, operands[0]);
1fd4e8c1 10332
cccf3bdc
DE		 10333 else if (DEFAULT_ABI == ABI_AIX)
10334 {
10335 /* AIX function pointers are really pointers to a three word
10336 area. */
10337 emit_call_insn (TARGET_32BIT
10338 ? gen_call_value_indirect_aix32 (operands[0],
10339 force_reg (SImode,
10340 operands[1]),
10341 operands[2])
10342 : gen_call_value_indirect_aix64 (operands[0],
10343 force_reg (DImode,
10344 operands[1]),
10345 operands[2]));
10346 DONE;
b6c9286a 10347 }
cccf3bdc
DE		 10348 else
10349 abort ();
1fd4e8c1
RK		 10350 }
10351}")
10352
04780ee7 10353;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 10354;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10355;; either the function was not prototyped, or it was prototyped as a
10356;; variable argument function. It is > 0 if FP registers were passed
10357;; and < 0 if they were not.
04780ee7 10358
a260abc9 10359(define_insn "*call_local32"
4697a36c
MM		 10360 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10361 (match_operand 1 "" "g,g"))
10362 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10363 (clobber (match_scratch:SI 3 "=l,l"))]
5a19791c 10364 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 10365 "*
10366{
6a4cee5f
MM		 10367 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10368 output_asm_insn (\"crxor 6,6,6\", operands);
10369
10370 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10371 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 10372
a226df46 10373 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 10374}"
b7ff3d82
DE		 10375 [(set_attr "type" "branch")
10376 (set_attr "length" "4,8")])
04780ee7 10377
a260abc9
DE		 10378(define_insn "*call_local64"
10379 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10380 (match_operand 1 "" "g,g"))
10381 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10382 (clobber (match_scratch:SI 3 "=l,l"))]
10383 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10384 "*
10385{
10386 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10387 output_asm_insn (\"crxor 6,6,6\", operands);
10388
10389 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10390 output_asm_insn (\"creqv 6,6,6\", operands);
10391
10392 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10393}"
10394 [(set_attr "type" "branch")
10395 (set_attr "length" "4,8")])
10396
cccf3bdc 10397(define_insn "*call_value_local32"
d18dba68 10398 [(set (match_operand 0 "" "")
a260abc9
DE		 10399 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10400 (match_operand 2 "" "g,g")))
10401 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10402 (clobber (match_scratch:SI 4 "=l,l"))]
10403 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10404 "*
10405{
10406 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10407 output_asm_insn (\"crxor 6,6,6\", operands);
10408
10409 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10410 output_asm_insn (\"creqv 6,6,6\", operands);
10411
10412 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10413}"
10414 [(set_attr "type" "branch")
10415 (set_attr "length" "4,8")])
10416
10417
cccf3bdc 10418(define_insn "*call_value_local64"
d18dba68 10419 [(set (match_operand 0 "" "")
a260abc9
DE		 10420 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10421 (match_operand 2 "" "g,g")))
10422 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10423 (clobber (match_scratch:SI 4 "=l,l"))]
10424 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10425 "*
10426{
10427 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10428 output_asm_insn (\"crxor 6,6,6\", operands);
10429
10430 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10431 output_asm_insn (\"creqv 6,6,6\", operands);
10432
10433 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10434}"
10435 [(set_attr "type" "branch")
10436 (set_attr "length" "4,8")])
10437
04780ee7 10438;; Call to function which may be in another module. Restore the TOC
911f679c 10439;; pointer (r2) after the call unless this is System V.
a0ab749a 10440;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10441;; either the function was not prototyped, or it was prototyped as a
10442;; variable argument function. It is > 0 if FP registers were passed
10443;; and < 0 if they were not.
04780ee7 10444
cccf3bdc
DE		 10445(define_insn "*call_indirect_nonlocal_aix32"
10446 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10447 (match_operand 1 "" "g"))
10448 (use (reg:SI 2))
10449 (use (reg:SI 11))
10450 (set (reg:SI 2)
10451 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
c77e04ae 10452 (clobber (match_scratch:SI 2 "=l"))]
cccf3bdc
DE		 10453 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10454 "b%T0l\;{l|lwz} 2,20(1)"
10455 [(set_attr "type" "jmpreg")
10456 (set_attr "length" "8")])
10457
a260abc9 10458(define_insn "*call_nonlocal_aix32"
cc4d5fec 10459 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10460 (match_operand 1 "" "g"))
10461 (use (match_operand:SI 2 "immediate_operand" "O"))
10462 (clobber (match_scratch:SI 3 "=l"))]
10463 "TARGET_32BIT
10464 && DEFAULT_ABI == ABI_AIX
5a19791c 10465 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10466 "bl %z0\;%."
b7ff3d82 10467 [(set_attr "type" "branch")
cccf3bdc
DE		 10468 (set_attr "length" "8")])
10469
10470(define_insn "*call_indirect_nonlocal_aix64"
10471 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10472 (match_operand 1 "" "g"))
10473 (use (reg:DI 2))
10474 (use (reg:DI 11))
10475 (set (reg:DI 2)
10476 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
c77e04ae 10477 (clobber (match_scratch:SI 2 "=l"))]
cccf3bdc
DE		 10478 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10479 "b%T0l\;ld 2,40(1)"
10480 [(set_attr "type" "jmpreg")
10481 (set_attr "length" "8")])
59313e4e 10482
a260abc9 10483(define_insn "*call_nonlocal_aix64"
cc4d5fec 10484 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10485 (match_operand 1 "" "g"))
10486 (use (match_operand:SI 2 "immediate_operand" "O"))
10487 (clobber (match_scratch:SI 3 "=l"))]
9ebbca7d
GK		 10488 "TARGET_64BIT
10489 && DEFAULT_ABI == ABI_AIX
a260abc9 10490 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10491 "bl %z0\;%."
a260abc9 10492 [(set_attr "type" "branch")
cccf3bdc 10493 (set_attr "length" "8")])
7509c759 10494
cccf3bdc 10495(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 10496 [(set (match_operand 0 "" "")
cccf3bdc
DE		 10497 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10498 (match_operand 2 "" "g")))
10499 (use (reg:SI 2))
10500 (use (reg:SI 11))
10501 (set (reg:SI 2)
10502 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10503 (clobber (match_scratch:SI 3 "=l"))]
10504 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10505 "b%T1l\;{l|lwz} 2,20(1)"
10506 [(set_attr "type" "jmpreg")
10507 (set_attr "length" "8")])
1fd4e8c1 10508
cccf3bdc 10509(define_insn "*call_value_nonlocal_aix32"
d18dba68 10510 [(set (match_operand 0 "" "")
cc4d5fec 10511 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10512 (match_operand 2 "" "g")))
10513 (use (match_operand:SI 3 "immediate_operand" "O"))
10514 (clobber (match_scratch:SI 4 "=l"))]
10515 "TARGET_32BIT
10516 && DEFAULT_ABI == ABI_AIX
a260abc9 10517 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 10518 "bl %z1\;%."
b7ff3d82 10519 [(set_attr "type" "branch")
cccf3bdc 10520 (set_attr "length" "8")])
04780ee7 10521
cccf3bdc 10522(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 10523 [(set (match_operand 0 "" "")
cccf3bdc
DE		 10524 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10525 (match_operand 2 "" "g")))
10526 (use (reg:DI 2))
10527 (use (reg:DI 11))
10528 (set (reg:DI 2)
10529 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10530 (clobber (match_scratch:SI 3 "=l"))]
10531 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10532 "b%T1l\;ld 2,40(1)"
10533 [(set_attr "type" "jmpreg")
10534 (set_attr "length" "8")])
10535
10536(define_insn "*call_value_nonlocal_aix64"
d18dba68 10537 [(set (match_operand 0 "" "")
cc4d5fec 10538 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10539 (match_operand 2 "" "g")))
10540 (use (match_operand:SI 3 "immediate_operand" "O"))
10541 (clobber (match_scratch:SI 4 "=l"))]
9ebbca7d
GK		 10542 "TARGET_64BIT
10543 && DEFAULT_ABI == ABI_AIX
5a19791c 10544 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 10545 "bl %z1\;%."
10546 [(set_attr "type" "branch")
10547 (set_attr "length" "8")])
10548
10549;; A function pointer under System V is just a normal pointer
10550;; operands[0] is the function pointer
10551;; operands[1] is the stack size to clean up
10552;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10553;; which indicates how to set cr1
10554
a5c76ee6
ZW		 10555(define_insn "*call_indirect_nonlocal_sysv"
10556 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10557 (match_operand 1 "" "g,g"))
10558 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10559 (clobber (match_scratch:SI 3 "=l,l"))]
50d440bc 10560 "DEFAULT_ABI == ABI_V4
f607bc57 10561 || DEFAULT_ABI == ABI_DARWIN"
911f679c 10562{
cccf3bdc 10563 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 10564 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 10565
cccf3bdc 10566 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 10567 output_asm_insn ("creqv 6,6,6", operands);
7509c759 10568
a5c76ee6
ZW		 10569 return "b%T0l";
10570}
10571 [(set_attr "type" "jmpreg,jmpreg")
10572 (set_attr "length" "4,8")])
cccf3bdc 10573
a5c76ee6
ZW		 10574(define_insn "*call_nonlocal_sysv"
10575 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10576 (match_operand 1 "" "g,g"))
10577 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10578 (clobber (match_scratch:SI 3 "=l,l"))]
50d440bc 10579 "(DEFAULT_ABI == ABI_V4
a5c76ee6
ZW		 10580 || DEFAULT_ABI == ABI_DARWIN)
10581 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10582{
10583 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10584 output_asm_insn ("crxor 6,6,6", operands);
10585
10586 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10587 output_asm_insn ("creqv 6,6,6", operands);
10588
10589 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10590}
10591 [(set_attr "type" "branch,branch")
10592 (set_attr "length" "4,8")])
10593
10594(define_insn "*call_value_indirect_nonlocal_sysv"
d18dba68 10595 [(set (match_operand 0 "" "")
a5c76ee6
ZW		 10596 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10597 (match_operand 2 "" "g,g")))
10598 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10599 (clobber (match_scratch:SI 4 "=l,l"))]
50d440bc 10600 "DEFAULT_ABI == ABI_V4
f607bc57 10601 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 10602{
6a4cee5f 10603 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 10604 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 10605
10606 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 10607 output_asm_insn ("creqv 6,6,6", operands);
7509c759 10608
a5c76ee6
ZW		 10609 return "b%T1l";
10610}
10611 [(set_attr "type" "jmpreg,jmpreg")
10612 (set_attr "length" "4,8")])
10613
10614(define_insn "*call_value_nonlocal_sysv"
10615 [(set (match_operand 0 "" "")
10616 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10617 (match_operand 2 "" "g,g")))
10618 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10619 (clobber (match_scratch:SI 4 "=l,l"))]
50d440bc 10620 "(DEFAULT_ABI == ABI_V4
a5c76ee6
ZW		 10621 || DEFAULT_ABI == ABI_DARWIN)
10622 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10623{
10624 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10625 output_asm_insn ("crxor 6,6,6", operands);
10626
10627 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10628 output_asm_insn ("creqv 6,6,6", operands);
10629
10630 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10631}
10632 [(set_attr "type" "branch,branch")
10633 (set_attr "length" "4,8")])
e6f948e3
RK		 10634
10635;; Call subroutine returning any type.
e6f948e3
RK		 10636(define_expand "untyped_call"
10637 [(parallel [(call (match_operand 0 "" "")
10638 (const_int 0))
10639 (match_operand 1 "" "")
10640 (match_operand 2 "" "")])]
10641 ""
10642 "
10643{
10644 int i;
10645
7d70b8b2 10646 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 10647
10648 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10649 {
10650 rtx set = XVECEXP (operands[2], 0, i);
10651 emit_move_insn (SET_DEST (set), SET_SRC (set));
10652 }
10653
10654 /* The optimizer does not know that the call sets the function value
10655 registers we stored in the result block. We avoid problems by
10656 claiming that all hard registers are used and clobbered at this
10657 point. */
10658 emit_insn (gen_blockage ());
10659
10660 DONE;
10661}")
10662
5e1bf043
DJ		 10663;; sibling call patterns
10664(define_expand "sibcall"
10665 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10666 (match_operand 1 "" ""))
10667 (use (match_operand 2 "" ""))
fe352c29 10668 (use (match_operand 3 "" ""))
5e1bf043
DJ		 10669 (return)])]
10670 ""
10671 "
10672{
10673#if TARGET_MACHO
ab82a49f 10674 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 10675 operands[0] = machopic_indirect_call_target (operands[0]);
10676#endif
10677
10678 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10679 abort ();
10680
10681 operands[0] = XEXP (operands[0], 0);
fe352c29 10682 operands[3] = gen_reg_rtx (SImode);
5e1bf043
DJ		 10683
10684}")
10685
10686;; this and similar patterns must be marked as using LR, otherwise
10687;; dataflow will try to delete the store into it. This is true
10688;; even when the actual reg to jump to is in CTR, when LR was
10689;; saved and restored around the PIC-setting BCL.
10690(define_insn "*sibcall_local32"
10691 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10692 (match_operand 1 "" "g,g"))
10693 (use (match_operand:SI 2 "immediate_operand" "O,n"))
fe352c29 10694 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10695 (return)]
10696 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10697 "*
10698{
10699 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10700 output_asm_insn (\"crxor 6,6,6\", operands);
10701
10702 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10703 output_asm_insn (\"creqv 6,6,6\", operands);
10704
10705 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10706}"
10707 [(set_attr "type" "branch")
10708 (set_attr "length" "4,8")])
10709
10710(define_insn "*sibcall_local64"
10711 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10712 (match_operand 1 "" "g,g"))
10713 (use (match_operand:SI 2 "immediate_operand" "O,n"))
fe352c29 10714 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10715 (return)]
10716 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10717 "*
10718{
10719 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10720 output_asm_insn (\"crxor 6,6,6\", operands);
10721
10722 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10723 output_asm_insn (\"creqv 6,6,6\", operands);
10724
10725 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10726}"
10727 [(set_attr "type" "branch")
10728 (set_attr "length" "4,8")])
10729
10730(define_insn "*sibcall_value_local32"
10731 [(set (match_operand 0 "" "")
10732 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10733 (match_operand 2 "" "g,g")))
10734 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10735 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10736 (return)]
10737 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10738 "*
10739{
10740 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10741 output_asm_insn (\"crxor 6,6,6\", operands);
10742
10743 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10744 output_asm_insn (\"creqv 6,6,6\", operands);
10745
10746 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10747}"
10748 [(set_attr "type" "branch")
10749 (set_attr "length" "4,8")])
10750
10751
10752(define_insn "*sibcall_value_local64"
10753 [(set (match_operand 0 "" "")
10754 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10755 (match_operand 2 "" "g,g")))
10756 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10757 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10758 (return)]
10759 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10760 "*
10761{
10762 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10763 output_asm_insn (\"crxor 6,6,6\", operands);
10764
10765 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10766 output_asm_insn (\"creqv 6,6,6\", operands);
10767
10768 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10769}"
10770 [(set_attr "type" "branch")
10771 (set_attr "length" "4,8")])
10772
10773(define_insn "*sibcall_nonlocal_aix32"
10774 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10775 (match_operand 1 "" "g"))
10776 (use (match_operand:SI 2 "immediate_operand" "O"))
fe352c29 10777 (use (match_operand:SI 3 "register_operand" "l"))
5e1bf043
DJ		 10778 (return)]
10779 "TARGET_32BIT
10780 && DEFAULT_ABI == ABI_AIX
10781 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10782 "b %z0"
10783 [(set_attr "type" "branch")
10784 (set_attr "length" "4")])
10785
10786(define_insn "*sibcall_nonlocal_aix64"
10787 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10788 (match_operand 1 "" "g"))
10789 (use (match_operand:SI 2 "immediate_operand" "O"))
fe352c29 10790 (use (match_operand:SI 3 "register_operand" "l"))
5e1bf043
DJ		 10791 (return)]
10792 "TARGET_64BIT
10793 && DEFAULT_ABI == ABI_AIX
10794 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10795 "b %z0"
10796 [(set_attr "type" "branch")
10797 (set_attr "length" "4")])
10798
10799(define_insn "*sibcall_value_nonlocal_aix32"
10800 [(set (match_operand 0 "" "")
10801 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10802 (match_operand 2 "" "g")))
10803 (use (match_operand:SI 3 "immediate_operand" "O"))
fe352c29 10804 (use (match_operand:SI 4 "register_operand" "l"))
5e1bf043
DJ		 10805 (return)]
10806 "TARGET_32BIT
10807 && DEFAULT_ABI == ABI_AIX
10808 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10809 "b %z1"
10810 [(set_attr "type" "branch")
10811 (set_attr "length" "4")])
10812
10813(define_insn "*sibcall_value_nonlocal_aix64"
10814 [(set (match_operand 0 "" "")
10815 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10816 (match_operand 2 "" "g")))
10817 (use (match_operand:SI 3 "immediate_operand" "O"))
fe352c29 10818 (use (match_operand:SI 4 "register_operand" "l"))
5e1bf043
DJ		 10819 (return)]
10820 "TARGET_64BIT
10821 && DEFAULT_ABI == ABI_AIX
10822 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10823 "b %z1"
10824 [(set_attr "type" "branch")
10825 (set_attr "length" "4")])
10826
10827(define_insn "*sibcall_nonlocal_sysv"
10828 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10829 (match_operand 1 "" ""))
10830 (use (match_operand 2 "immediate_operand" "O,n"))
fe352c29 10831 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10832 (return)]
10833 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 10834 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 10835 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10836 "*
10837{
10838 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10839 output_asm_insn (\"crxor 6,6,6\", operands);
10840
10841 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10842 output_asm_insn (\"creqv 6,6,6\", operands);
10843
10844 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10845}"
10846 [(set_attr "type" "branch,branch")
10847 (set_attr "length" "4,8")])
10848
10849(define_expand "sibcall_value"
10850 [(parallel [(set (match_operand 0 "register_operand" "")
10851 (call (mem:SI (match_operand 1 "address_operand" ""))
10852 (match_operand 2 "" "")))
10853 (use (match_operand 3 "" ""))
fe352c29 10854 (use (match_operand 4 "" ""))
5e1bf043
DJ		 10855 (return)])]
10856 ""
10857 "
10858{
10859#if TARGET_MACHO
ab82a49f 10860 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 10861 operands[1] = machopic_indirect_call_target (operands[1]);
10862#endif
10863
10864 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10865 abort ();
10866
10867 operands[1] = XEXP (operands[1], 0);
fe352c29 10868 operands[4] = gen_reg_rtx (SImode);
5e1bf043
DJ		 10869
10870}")
10871
10872(define_insn "*sibcall_value_nonlocal_sysv"
10873 [(set (match_operand 0 "" "")
10874 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10875 (match_operand 2 "" "")))
10876 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10877 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10878 (return)]
10879 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 10880 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 10881 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10882 "*
10883{
10884 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10885 output_asm_insn (\"crxor 6,6,6\", operands);
10886
10887 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10888 output_asm_insn (\"creqv 6,6,6\", operands);
10889
10890 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10891}"
10892 [(set_attr "type" "branch,branch")
10893 (set_attr "length" "4,8")])
10894
10895(define_expand "sibcall_epilogue"
10896 [(use (const_int 0))]
10897 "TARGET_SCHED_PROLOG"
10898 "
10899{
10900 rs6000_emit_epilogue (TRUE);
10901 DONE;
10902}")
10903
e6f948e3
RK		 10904;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10905;; all of memory. This blocks insns from being moved across this point.
10906
10907(define_insn "blockage"
615158e2 10908 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 10909 ""
10910 "")
1fd4e8c1
RK		 10911\f
10912;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 10913;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 10914;;
10915;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10916;; insns, and branches. We store the operands of compares until we see
10917;; how it is used.
10918(define_expand "cmpsi"
10919 [(set (cc0)
cd2b37d9 10920 (compare (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 10921 (match_operand:SI 1 "reg_or_short_operand" "")))]
10922 ""
10923 "
10924{
10925 /* Take care of the possibility that operands[1] might be negative but
10926 this might be a logical operation. That insn doesn't exist. */
10927 if (GET_CODE (operands[1]) == CONST_INT
10928 && INTVAL (operands[1]) < 0)
10929 operands[1] = force_reg (SImode, operands[1]);
10930
10931 rs6000_compare_op0 = operands[0];
10932 rs6000_compare_op1 = operands[1];
10933 rs6000_compare_fp_p = 0;
10934 DONE;
10935}")
10936
266eb58a
DE		 10937(define_expand "cmpdi"
10938 [(set (cc0)
10939 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10940 (match_operand:DI 1 "reg_or_short_operand" "")))]
10941 "TARGET_POWERPC64"
10942 "
10943{
10944 /* Take care of the possibility that operands[1] might be negative but
10945 this might be a logical operation. That insn doesn't exist. */
10946 if (GET_CODE (operands[1]) == CONST_INT
10947 && INTVAL (operands[1]) < 0)
10948 operands[1] = force_reg (DImode, operands[1]);
10949
10950 rs6000_compare_op0 = operands[0];
10951 rs6000_compare_op1 = operands[1];
10952 rs6000_compare_fp_p = 0;
10953 DONE;
10954}")
10955
1fd4e8c1 10956(define_expand "cmpsf"
cd2b37d9
RK		 10957 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10958 (match_operand:SF 1 "gpc_reg_operand" "")))]
d14a6d05 10959 "TARGET_HARD_FLOAT"
1fd4e8c1
RK		 10960 "
10961{
10962 rs6000_compare_op0 = operands[0];
10963 rs6000_compare_op1 = operands[1];
10964 rs6000_compare_fp_p = 1;
10965 DONE;
10966}")
10967
10968(define_expand "cmpdf"
cd2b37d9
RK		 10969 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10970 (match_operand:DF 1 "gpc_reg_operand" "")))]
a3170dc6 10971 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 10972 "
10973{
10974 rs6000_compare_op0 = operands[0];
10975 rs6000_compare_op1 = operands[1];
10976 rs6000_compare_fp_p = 1;
10977 DONE;
10978}")
10979
d6f99ca4 10980(define_expand "cmptf"
e7a4130e
DE		 10981 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10982 (match_operand:TF 1 "gpc_reg_operand" "")))]
39e63627
GK		 10983 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10984 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
d6f99ca4
DE		 10985 "
10986{
10987 rs6000_compare_op0 = operands[0];
10988 rs6000_compare_op1 = operands[1];
10989 rs6000_compare_fp_p = 1;
10990 DONE;
10991}")
10992
1fd4e8c1 10993(define_expand "beq"
39a10a29 10994 [(use (match_operand 0 "" ""))]
1fd4e8c1 10995 ""
39a10a29 10996 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 10997
10998(define_expand "bne"
39a10a29 10999 [(use (match_operand 0 "" ""))]
1fd4e8c1 11000 ""
39a10a29 11001 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
1fd4e8c1 11002
39a10a29
GK		 11003(define_expand "bge"
11004 [(use (match_operand 0 "" ""))]
1fd4e8c1 11005 ""
39a10a29 11006 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
1fd4e8c1
RK		 11007
11008(define_expand "bgt"
39a10a29 11009 [(use (match_operand 0 "" ""))]
1fd4e8c1 11010 ""
39a10a29 11011 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
1fd4e8c1
RK		 11012
11013(define_expand "ble"
39a10a29 11014 [(use (match_operand 0 "" ""))]
1fd4e8c1 11015 ""
39a10a29 11016 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
1fd4e8c1 11017
39a10a29
GK		 11018(define_expand "blt"
11019 [(use (match_operand 0 "" ""))]
1fd4e8c1 11020 ""
39a10a29 11021 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
1fd4e8c1 11022
39a10a29
GK		 11023(define_expand "bgeu"
11024 [(use (match_operand 0 "" ""))]
1fd4e8c1 11025 ""
39a10a29 11026 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
1fd4e8c1 11027
39a10a29
GK		 11028(define_expand "bgtu"
11029 [(use (match_operand 0 "" ""))]
1fd4e8c1 11030 ""
39a10a29 11031 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
1fd4e8c1 11032
39a10a29
GK		 11033(define_expand "bleu"
11034 [(use (match_operand 0 "" ""))]
1fd4e8c1 11035 ""
39a10a29 11036 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
1fd4e8c1 11037
39a10a29
GK		 11038(define_expand "bltu"
11039 [(use (match_operand 0 "" ""))]
1fd4e8c1 11040 ""
39a10a29 11041 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
1fd4e8c1 11042
1c882ea4 11043(define_expand "bunordered"
39a10a29 11044 [(use (match_operand 0 "" ""))]
1c882ea4 11045 ""
39a10a29 11046 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11047
11048(define_expand "bordered"
39a10a29 11049 [(use (match_operand 0 "" ""))]
1c882ea4 11050 ""
39a10a29 11051 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11052
11053(define_expand "buneq"
39a10a29 11054 [(use (match_operand 0 "" ""))]
1c882ea4 11055 ""
39a10a29 11056 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
1c882ea4
GK		 11057
11058(define_expand "bunge"
39a10a29 11059 [(use (match_operand 0 "" ""))]
1c882ea4 11060 ""
39a10a29 11061 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
1c882ea4
GK		 11062
11063(define_expand "bungt"
39a10a29 11064 [(use (match_operand 0 "" ""))]
1c882ea4 11065 ""
39a10a29 11066 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
1c882ea4
GK		 11067
11068(define_expand "bunle"
39a10a29 11069 [(use (match_operand 0 "" ""))]
1c882ea4 11070 ""
39a10a29 11071 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
1c882ea4
GK		 11072
11073(define_expand "bunlt"
39a10a29 11074 [(use (match_operand 0 "" ""))]
1c882ea4 11075 ""
39a10a29 11076 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
1c882ea4
GK		 11077
11078(define_expand "bltgt"
39a10a29 11079 [(use (match_operand 0 "" ""))]
1c882ea4 11080 ""
39a10a29 11081 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
1c882ea4 11082
1fd4e8c1
RK		 11083;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11084;; For SEQ, likewise, except that comparisons with zero should be done
11085;; with an scc insns. However, due to the order that combine see the
11086;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11087;; the cases we don't want to handle.
11088(define_expand "seq"
39a10a29 11089 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11090 ""
39a10a29 11091 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11092
11093(define_expand "sne"
39a10a29 11094 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11095 ""
11096 "
39a10a29
GK		 11097{
11098 if (! rs6000_compare_fp_p)
1fd4e8c1
RK		 11099 FAIL;
11100
39a10a29
GK		 11101 rs6000_emit_sCOND (NE, operands[0]);
11102 DONE;
1fd4e8c1
RK		 11103}")
11104
b7053a3f
GK		 11105;; A >= 0 is best done the portable way for A an integer.
11106(define_expand "sge"
39a10a29 11107 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11108 ""
11109 "
5638268e
DE		 11110{
11111 if (! rs6000_compare_fp_p
11112 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
1fd4e8c1
RK		 11113 FAIL;
11114
b7053a3f 11115 rs6000_emit_sCOND (GE, operands[0]);
39a10a29 11116 DONE;
1fd4e8c1
RK		 11117}")
11118
b7053a3f
GK		 11119;; A > 0 is best done using the portable sequence, so fail in that case.
11120(define_expand "sgt"
39a10a29 11121 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11122 ""
11123 "
5638268e 11124{
b7053a3f 11125 if (! rs6000_compare_fp_p
5638268e 11126 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
1fd4e8c1
RK		 11127 FAIL;
11128
b7053a3f 11129 rs6000_emit_sCOND (GT, operands[0]);
39a10a29 11130 DONE;
1fd4e8c1
RK		 11131}")
11132
b7053a3f
GK		 11133;; A <= 0 is best done the portable way for A an integer.
11134(define_expand "sle"
39a10a29 11135 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11136 ""
5638268e
DE		 11137 "
11138{
11139 if (! rs6000_compare_fp_p
11140 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11141 FAIL;
11142
b7053a3f 11143 rs6000_emit_sCOND (LE, operands[0]);
5638268e
DE		 11144 DONE;
11145}")
1fd4e8c1 11146
b7053a3f
GK		 11147;; A < 0 is best done in the portable way for A an integer.
11148(define_expand "slt"
39a10a29 11149 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11150 ""
11151 "
5638268e 11152{
b7053a3f 11153 if (! rs6000_compare_fp_p
5638268e 11154 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
1fd4e8c1
RK		 11155 FAIL;
11156
b7053a3f 11157 rs6000_emit_sCOND (LT, operands[0]);
39a10a29 11158 DONE;
1fd4e8c1
RK		 11159}")
11160
b7053a3f
GK		 11161(define_expand "sgeu"
11162 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11163 ""
11164 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11165
1fd4e8c1 11166(define_expand "sgtu"
39a10a29 11167 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11168 ""
39a10a29 11169 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
1fd4e8c1 11170
b7053a3f
GK		 11171(define_expand "sleu"
11172 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11173 ""
11174 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11175
1fd4e8c1 11176(define_expand "sltu"
39a10a29 11177 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11178 ""
39a10a29 11179 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
1fd4e8c1 11180
b7053a3f 11181(define_expand "sunordered"
39a10a29 11182 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11183 ""
b7053a3f 11184 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
1fd4e8c1 11185
b7053a3f 11186(define_expand "sordered"
39a10a29 11187 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11188 ""
b7053a3f
GK		 11189 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11190
11191(define_expand "suneq"
11192 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11193 ""
11194 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11195
11196(define_expand "sunge"
11197 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11198 ""
11199 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11200
11201(define_expand "sungt"
11202 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11203 ""
11204 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11205
11206(define_expand "sunle"
11207 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11208 ""
11209 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11210
11211(define_expand "sunlt"
11212 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11213 ""
11214 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11215
11216(define_expand "sltgt"
11217 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11218 ""
11219 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11220
1fd4e8c1
RK		 11221\f
11222;; Here are the actual compare insns.
acad7ed3 11223(define_insn "*cmpsi_internal1"
1fd4e8c1 11224 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
cd2b37d9 11225 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 11226 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11227 ""
7f340546 11228 "{cmp%I2|cmpw%I2} %0,%1,%2"
b54cf83a 11229 [(set_attr "type" "cmp")])
1fd4e8c1 11230
acad7ed3 11231(define_insn "*cmpdi_internal1"
266eb58a
DE		 11232 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11233 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11234 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11235 "TARGET_POWERPC64"
11236 "cmpd%I2 %0,%1,%2"
b54cf83a 11237 [(set_attr "type" "cmp")])
266eb58a 11238
f357808b
RK		 11239;; If we are comparing a register for equality with a large constant,
11240;; we can do this with an XOR followed by a compare. But we need a scratch
11241;; register for the result of the XOR.
11242
11243(define_split
11244 [(set (match_operand:CC 0 "cc_reg_operand" "")
cd2b37d9 11245 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
f357808b 11246 (match_operand:SI 2 "non_short_cint_operand" "")))
cd2b37d9 11247 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
f357808b
RK		 11248 "find_single_use (operands[0], insn, 0)
11249 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11250 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11251 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11252 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11253 "
11254{
11255 /* Get the constant we are comparing against, C, and see what it looks like
11256 sign-extended to 16 bits. Then see what constant could be XOR'ed
11257 with C to get the sign-extended value. */
11258
5f59ecb7 11259 HOST_WIDE_INT c = INTVAL (operands[2]);
a65c591c 11260 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 11261 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 11262
89e9f3a8
MM		 11263 operands[4] = GEN_INT (xorv);
11264 operands[5] = GEN_INT (sextc);
f357808b
RK		 11265}")
11266
acad7ed3 11267(define_insn "*cmpsi_internal2"
1fd4e8c1 11268 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 11269 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 11270 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 11271 ""
e2c953b6 11272 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 11273 [(set_attr "type" "cmp")])
1fd4e8c1 11274
acad7ed3 11275(define_insn "*cmpdi_internal2"
266eb58a
DE		 11276 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11277 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 11278 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 11279 ""
e2c953b6 11280 "cmpld%I2 %0,%1,%b2"
b54cf83a 11281 [(set_attr "type" "cmp")])
266eb58a 11282
1fd4e8c1
RK		 11283;; The following two insns don't exist as single insns, but if we provide
11284;; them, we can swap an add and compare, which will enable us to overlap more
11285;; of the required delay between a compare and branch. We generate code for
11286;; them by splitting.
11287
11288(define_insn ""
11289 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 11290 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11291 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 11292 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11293 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11294 ""
baf97f86
RK		 11295 "#"
11296 [(set_attr "length" "8")])
7e69e155 11297
1fd4e8c1
RK		 11298(define_insn ""
11299 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 11300 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11301 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 11302 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11303 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11304 ""
baf97f86
RK		 11305 "#"
11306 [(set_attr "length" "8")])
7e69e155 11307
1fd4e8c1
RK		 11308(define_split
11309 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 11310 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11311 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 11312 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11313 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11314 ""
11315 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11316 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11317
11318(define_split
11319 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 11320 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11321 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 11322 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11323 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11324 ""
11325 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11326 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11327
acad7ed3 11328(define_insn "*cmpsf_internal1"
1fd4e8c1 11329 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11330 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11331 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 11332 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11333 "fcmpu %0,%1,%2"
11334 [(set_attr "type" "fpcompare")])
11335
acad7ed3 11336(define_insn "*cmpdf_internal1"
1fd4e8c1 11337 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11338 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11339 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 11340 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11341 "fcmpu %0,%1,%2"
11342 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 11343
11344;; Only need to compare second words if first words equal
11345(define_insn "*cmptf_internal1"
11346 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11347 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11348 (match_operand:TF 2 "gpc_reg_operand" "f")))]
39e63627
GK		 11349 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11350 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
2e7d5318 11351 "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 11352 [(set_attr "type" "fpcompare")
11353 (set_attr "length" "12")])
1fd4e8c1
RK		 11354\f
11355;; Now we have the scc insns. We can do some combinations because of the
11356;; way the machine works.
11357;;
11358;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 11359;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11360;; cases the insns below which don't use an intermediate CR field will
11361;; be used instead.
1fd4e8c1 11362(define_insn ""
cd2b37d9 11363 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11364 (match_operator:SI 1 "scc_comparison_operator"
11365 [(match_operand 2 "cc_reg_operand" "y")
11366 (const_int 0)]))]
11367 ""
2c4a9cff
DE		 11368 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11369 [(set (attr "type")
11370 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11371 (const_string "mfcrf")
11372 ]
11373 (const_string "mfcr")))
309323c2 11374 (set_attr "length" "12")])
1fd4e8c1 11375
a3170dc6
AH		 11376;; Same as above, but get the OV/ORDERED bit.
11377(define_insn "move_from_CR_ov_bit"
11378 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 11379 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 11380 "TARGET_ISEL"
b7053a3f 11381 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a
DE		 11382 [(set_attr "type" "mfcr")
11383 (set_attr "length" "12")])
a3170dc6 11384
1fd4e8c1 11385(define_insn ""
9ebbca7d
GK		 11386 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11387 (match_operator:DI 1 "scc_comparison_operator"
11388 [(match_operand 2 "cc_reg_operand" "y")
11389 (const_int 0)]))]
11390 "TARGET_POWERPC64"
2c4a9cff
DE		 11391 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11392 [(set (attr "type")
11393 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11394 (const_string "mfcrf")
11395 ]
11396 (const_string "mfcr")))
309323c2 11397 (set_attr "length" "12")])
9ebbca7d
GK		 11398
11399(define_insn ""
11400 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 11401 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 11402 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 11403 (const_int 0)])
11404 (const_int 0)))
9ebbca7d 11405 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 11406 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
0ad91047 11407 "! TARGET_POWERPC64"
9ebbca7d 11408 "@
2c4a9cff 11409 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 11410 #"
b19003d8 11411 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 11412 (set_attr "length" "12,16")])
11413
11414(define_split
11415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11416 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11417 [(match_operand 2 "cc_reg_operand" "")
11418 (const_int 0)])
11419 (const_int 0)))
11420 (set (match_operand:SI 3 "gpc_reg_operand" "")
11421 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11422 "! TARGET_POWERPC64 && reload_completed"
11423 [(set (match_dup 3)
11424 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11425 (set (match_dup 0)
11426 (compare:CC (match_dup 3)
11427 (const_int 0)))]
11428 "")
1fd4e8c1
RK		 11429
11430(define_insn ""
cd2b37d9 11431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11432 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11433 [(match_operand 2 "cc_reg_operand" "y")
11434 (const_int 0)])
11435 (match_operand:SI 3 "const_int_operand" "n")))]
11436 ""
11437 "*
11438{
11439 int is_bit = ccr_bit (operands[1], 1);
11440 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11441 int count;
11442
11443 if (is_bit >= put_bit)
11444 count = is_bit - put_bit;
11445 else
11446 count = 32 - (put_bit - is_bit);
11447
89e9f3a8
MM		 11448 operands[4] = GEN_INT (count);
11449 operands[5] = GEN_INT (put_bit);
1fd4e8c1 11450
2c4a9cff 11451 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 11452}"
2c4a9cff
DE		 11453 [(set (attr "type")
11454 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11455 (const_string "mfcrf")
11456 ]
11457 (const_string "mfcr")))
309323c2 11458 (set_attr "length" "12")])
1fd4e8c1
RK		 11459
11460(define_insn ""
9ebbca7d 11461 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11462 (compare:CC
11463 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 11464 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 11465 (const_int 0)])
9ebbca7d 11466 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 11467 (const_int 0)))
9ebbca7d 11468 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 11469 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11470 (match_dup 3)))]
ce71f754 11471 ""
1fd4e8c1
RK		 11472 "*
11473{
11474 int is_bit = ccr_bit (operands[1], 1);
11475 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11476 int count;
11477
9ebbca7d
GK		 11478 /* Force split for non-cc0 compare. */
11479 if (which_alternative == 1)
11480 return \"#\";
11481
1fd4e8c1
RK		 11482 if (is_bit >= put_bit)
11483 count = is_bit - put_bit;
11484 else
11485 count = 32 - (put_bit - is_bit);
11486
89e9f3a8
MM		 11487 operands[5] = GEN_INT (count);
11488 operands[6] = GEN_INT (put_bit);
1fd4e8c1 11489
2c4a9cff 11490 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 11491}"
b19003d8 11492 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 11493 (set_attr "length" "12,16")])
11494
11495(define_split
11496 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11497 (compare:CC
11498 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11499 [(match_operand 2 "cc_reg_operand" "")
11500 (const_int 0)])
11501 (match_operand:SI 3 "const_int_operand" ""))
11502 (const_int 0)))
11503 (set (match_operand:SI 4 "gpc_reg_operand" "")
11504 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11505 (match_dup 3)))]
ce71f754 11506 "reload_completed"
9ebbca7d
GK		 11507 [(set (match_dup 4)
11508 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11509 (match_dup 3)))
11510 (set (match_dup 0)
11511 (compare:CC (match_dup 4)
11512 (const_int 0)))]
11513 "")
1fd4e8c1 11514
c5defebb
RK		 11515;; There is a 3 cycle delay between consecutive mfcr instructions
11516;; so it is useful to combine 2 scc instructions to use only one mfcr.
11517
11518(define_peephole
cd2b37d9 11519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 11520 (match_operator:SI 1 "scc_comparison_operator"
11521 [(match_operand 2 "cc_reg_operand" "y")
11522 (const_int 0)]))
cd2b37d9 11523 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 11524 (match_operator:SI 4 "scc_comparison_operator"
11525 [(match_operand 5 "cc_reg_operand" "y")
11526 (const_int 0)]))]
309323c2 11527 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 11528 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 11529 [(set_attr "type" "mfcr")
309323c2 11530 (set_attr "length" "20")])
c5defebb 11531
9ebbca7d
GK		 11532(define_peephole
11533 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11534 (match_operator:DI 1 "scc_comparison_operator"
11535 [(match_operand 2 "cc_reg_operand" "y")
11536 (const_int 0)]))
11537 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11538 (match_operator:DI 4 "scc_comparison_operator"
11539 [(match_operand 5 "cc_reg_operand" "y")
11540 (const_int 0)]))]
309323c2 11541 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 11542 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 11543 [(set_attr "type" "mfcr")
309323c2 11544 (set_attr "length" "20")])
9ebbca7d 11545
1fd4e8c1
RK		 11546;; There are some scc insns that can be done directly, without a compare.
11547;; These are faster because they don't involve the communications between
11548;; the FXU and branch units. In fact, we will be replacing all of the
11549;; integer scc insns here or in the portable methods in emit_store_flag.
11550;;
11551;; Also support (neg (scc ..)) since that construct is used to replace
11552;; branches, (plus (scc ..) ..) since that construct is common and
11553;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11554;; cases where it is no more expensive than (neg (scc ..)).
11555
11556;; Have reload force a constant into a register for the simple insns that
11557;; otherwise won't accept constants. We do this because it is faster than
11558;; the cmp/mfcr sequence we would otherwise generate.
11559
11560(define_insn ""
cd2b37d9
RK		 11561 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11562 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5f59ecb7 11563 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
1fd4e8c1 11564 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
683bdff7 11565 "TARGET_32BIT"
1fd4e8c1 11566 "@
ca7f5001 11567 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
71d2371f 11568 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
ca7f5001
RK		 11569 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11570 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11571 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
b19003d8 11572 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1 11573
a260abc9
DE		 11574(define_insn ""
11575 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11576 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11577 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11578 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
683bdff7 11579 "TARGET_64BIT"
a260abc9
DE		 11580 "@
11581 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11582 subfic %3,%1,0\;adde %0,%3,%1
11583 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11584 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11585 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11586 [(set_attr "length" "12,8,12,12,12")])
11587
1fd4e8c1 11588(define_insn ""
9ebbca7d 11589 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11590 (compare:CC
9ebbca7d
GK		 11591 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11592 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
1fd4e8c1 11593 (const_int 0)))
9ebbca7d 11594 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
1fd4e8c1 11595 (eq:SI (match_dup 1) (match_dup 2)))
9ebbca7d 11596 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
683bdff7 11597 "TARGET_32BIT"
1fd4e8c1 11598 "@
ca7f5001
RK		 11599 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11600 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11601 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11602 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
9ebbca7d
GK		 11603 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11604 #
11605 #
11606 #
11607 #
11608 #"
b19003d8 11609 [(set_attr "type" "compare")
9ebbca7d
GK		 11610 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11611
11612(define_split
11613 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11614 (compare:CC
11615 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11616 (match_operand:SI 2 "reg_or_cint_operand" ""))
11617 (const_int 0)))
11618 (set (match_operand:SI 0 "gpc_reg_operand" "")
11619 (eq:SI (match_dup 1) (match_dup 2)))
11620 (clobber (match_scratch:SI 3 ""))]
683bdff7 11621 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 11622 [(parallel [(set (match_dup 0)
11623 (eq:SI (match_dup 1) (match_dup 2)))
11624 (clobber (match_dup 3))])
11625 (set (match_dup 4)
11626 (compare:CC (match_dup 0)
11627 (const_int 0)))]
11628 "")
b19003d8 11629
a260abc9 11630(define_insn ""
9ebbca7d 11631 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
a260abc9 11632 (compare:CC
9ebbca7d
GK		 11633 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11634 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
a260abc9 11635 (const_int 0)))
9ebbca7d 11636 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
a260abc9 11637 (eq:DI (match_dup 1) (match_dup 2)))
9ebbca7d 11638 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
683bdff7 11639 "TARGET_64BIT"
a260abc9
DE		 11640 "@
11641 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11642 subfic %3,%1,0\;adde. %0,%3,%1
11643 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11644 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
9ebbca7d
GK		 11645 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11646 #
11647 #
11648 #
11649 #
11650 #"
a260abc9 11651 [(set_attr "type" "compare")
9ebbca7d
GK		 11652 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11653
11654(define_split
11655 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11656 (compare:CC
11657 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11658 (match_operand:DI 2 "reg_or_cint_operand" ""))
11659 (const_int 0)))
11660 (set (match_operand:DI 0 "gpc_reg_operand" "")
11661 (eq:DI (match_dup 1) (match_dup 2)))
11662 (clobber (match_scratch:DI 3 ""))]
683bdff7 11663 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 11664 [(parallel [(set (match_dup 0)
11665 (eq:DI (match_dup 1) (match_dup 2)))
11666 (clobber (match_dup 3))])
11667 (set (match_dup 4)
11668 (compare:CC (match_dup 0)
11669 (const_int 0)))]
11670 "")
a260abc9 11671
b19003d8
RK		 11672;; We have insns of the form shown by the first define_insn below. If
11673;; there is something inside the comparison operation, we must split it.
11674(define_split
11675 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11676 (plus:SI (match_operator 1 "comparison_operator"
11677 [(match_operand:SI 2 "" "")
11678 (match_operand:SI 3
11679 "reg_or_cint_operand" "")])
11680 (match_operand:SI 4 "gpc_reg_operand" "")))
11681 (clobber (match_operand:SI 5 "register_operand" ""))]
11682 "! gpc_reg_operand (operands[2], SImode)"
11683 [(set (match_dup 5) (match_dup 2))
11684 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11685 (match_dup 4)))])
1fd4e8c1
RK		 11686
11687(define_insn ""
5276df18 11688 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 11689 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5f59ecb7 11690 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
5276df18 11691 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
683bdff7 11692 "TARGET_32BIT"
1fd4e8c1 11693 "@
5276df18
DE		 11694 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11695 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11696 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11697 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11698 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 11699 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1
RK		 11700
11701(define_insn ""
9ebbca7d 11702 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11703 (compare:CC
1fd4e8c1 11704 (plus:SI
9ebbca7d
GK		 11705 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11706 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11707 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 11708 (const_int 0)))
9ebbca7d 11709 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
683bdff7 11710 "TARGET_32BIT"
1fd4e8c1 11711 "@
ca7f5001 11712 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 11713 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 11714 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11715 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 11716 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11717 #
11718 #
11719 #
11720 #
11721 #"
b19003d8 11722 [(set_attr "type" "compare")
9ebbca7d
GK		 11723 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11724
11725(define_split
11726 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11727 (compare:CC
11728 (plus:SI
11729 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11730 (match_operand:SI 2 "reg_or_cint_operand" ""))
11731 (match_operand:SI 3 "gpc_reg_operand" ""))
11732 (const_int 0)))
11733 (clobber (match_scratch:SI 4 ""))]
683bdff7 11734 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 11735 [(set (match_dup 4)
11736 (plus:SI (eq:SI (match_dup 1)
11737 (match_dup 2))
11738 (match_dup 3)))
11739 (set (match_dup 0)
11740 (compare:CC (match_dup 4)
11741 (const_int 0)))]
11742 "")
1fd4e8c1
RK		 11743
11744(define_insn ""
0387639b 11745 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11746 (compare:CC
1fd4e8c1 11747 (plus:SI
9ebbca7d
GK		 11748 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11749 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11750 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 11751 (const_int 0)))
0387639b
DE		 11752 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11753 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 11754 "TARGET_32BIT"
1fd4e8c1 11755 "@
0387639b
DE		 11756 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11757 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11758 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11759 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11760 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 11761 #
11762 #
11763 #
11764 #
11765 #"
11766 [(set_attr "type" "compare")
11767 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11768
11769(define_split
0387639b 11770 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 11771 (compare:CC
11772 (plus:SI
11773 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11774 (match_operand:SI 2 "reg_or_cint_operand" ""))
11775 (match_operand:SI 3 "gpc_reg_operand" ""))
11776 (const_int 0)))
11777 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 11778 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 11779 "TARGET_32BIT && reload_completed"
0387639b 11780 [(set (match_dup 0)
9ebbca7d 11781 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 11782 (set (match_dup 4)
9ebbca7d
GK		 11783 (compare:CC (match_dup 0)
11784 (const_int 0)))]
11785 "")
11786
1fd4e8c1 11787(define_insn ""
cd2b37d9 11788 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
deb9225a 11789 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5f59ecb7 11790 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
683bdff7 11791 "TARGET_32BIT"
1fd4e8c1 11792 "@
ca7f5001
RK		 11793 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11794 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11795 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11796 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11797 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 11798 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1 11799
ea9be077
MM		 11800;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11801;; since it nabs/sr is just as fast.
463b558b 11802(define_insn "*ne0"
b4e95693 11803 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 11804 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11805 (const_int 31)))
11806 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 11807 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077
MM		 11808 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11809 [(set_attr "length" "8")])
11810
a260abc9
DE		 11811(define_insn ""
11812 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11813 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11814 (const_int 63)))
11815 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 11816 "TARGET_64BIT"
a260abc9
DE		 11817 "addic %2,%1,-1\;subfe %0,%2,%1"
11818 [(set_attr "length" "8")])
11819
1fd4e8c1
RK		 11820;; This is what (plus (ne X (const_int 0)) Y) looks like.
11821(define_insn ""
cd2b37d9 11822 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 11823 (plus:SI (lshiftrt:SI
cd2b37d9 11824 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 11825 (const_int 31))
cd2b37d9 11826 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 11827 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 11828 "TARGET_32BIT"
ca7f5001 11829 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
b19003d8 11830 [(set_attr "length" "8")])
1fd4e8c1 11831
a260abc9
DE		 11832(define_insn ""
11833 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11834 (plus:DI (lshiftrt:DI
11835 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11836 (const_int 63))
11837 (match_operand:DI 2 "gpc_reg_operand" "r")))
11838 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 11839 "TARGET_64BIT"
a260abc9
DE		 11840 "addic %3,%1,-1\;addze %0,%2"
11841 [(set_attr "length" "8")])
11842
1fd4e8c1 11843(define_insn ""
9ebbca7d 11844 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11845 (compare:CC
11846 (plus:SI (lshiftrt:SI
9ebbca7d 11847 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 11848 (const_int 31))
9ebbca7d 11849 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 11850 (const_int 0)))
889b90a1
GK		 11851 (clobber (match_scratch:SI 3 "=&r,&r"))
11852 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 11853 "TARGET_32BIT"
9ebbca7d
GK		 11854 "@
11855 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11856 #"
b19003d8 11857 [(set_attr "type" "compare")
9ebbca7d
GK		 11858 (set_attr "length" "8,12")])
11859
11860(define_split
11861 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11862 (compare:CC
11863 (plus:SI (lshiftrt:SI
11864 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11865 (const_int 31))
11866 (match_operand:SI 2 "gpc_reg_operand" ""))
11867 (const_int 0)))
889b90a1
GK		 11868 (clobber (match_scratch:SI 3 ""))
11869 (clobber (match_scratch:SI 4 ""))]
683bdff7 11870 "TARGET_32BIT && reload_completed"
889b90a1 11871 [(parallel [(set (match_dup 3)
ce71f754
AM		 11872 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11873 (const_int 31))
11874 (match_dup 2)))
889b90a1 11875 (clobber (match_dup 4))])
9ebbca7d
GK		 11876 (set (match_dup 0)
11877 (compare:CC (match_dup 3)
11878 (const_int 0)))]
11879 "")
1fd4e8c1 11880
a260abc9 11881(define_insn ""
9ebbca7d 11882 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 11883 (compare:CC
11884 (plus:DI (lshiftrt:DI
9ebbca7d 11885 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 11886 (const_int 63))
9ebbca7d 11887 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 11888 (const_int 0)))
9ebbca7d 11889 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 11890 "TARGET_64BIT"
9ebbca7d
GK		 11891 "@
11892 addic %3,%1,-1\;addze. %3,%2
11893 #"
a260abc9 11894 [(set_attr "type" "compare")
9ebbca7d
GK		 11895 (set_attr "length" "8,12")])
11896
11897(define_split
11898 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11899 (compare:CC
11900 (plus:DI (lshiftrt:DI
11901 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11902 (const_int 63))
11903 (match_operand:DI 2 "gpc_reg_operand" ""))
11904 (const_int 0)))
11905 (clobber (match_scratch:DI 3 ""))]
683bdff7 11906 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 11907 [(set (match_dup 3)
11908 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11909 (const_int 63))
11910 (match_dup 2)))
11911 (set (match_dup 0)
11912 (compare:CC (match_dup 3)
11913 (const_int 0)))]
11914 "")
a260abc9 11915
1fd4e8c1 11916(define_insn ""
9ebbca7d 11917 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11918 (compare:CC
11919 (plus:SI (lshiftrt:SI
9ebbca7d 11920 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 11921 (const_int 31))
9ebbca7d 11922 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 11923 (const_int 0)))
9ebbca7d 11924 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 11925 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11926 (match_dup 2)))
9ebbca7d 11927 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 11928 "TARGET_32BIT"
9ebbca7d
GK		 11929 "@
11930 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11931 #"
b19003d8 11932 [(set_attr "type" "compare")
9ebbca7d
GK		 11933 (set_attr "length" "8,12")])
11934
11935(define_split
11936 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11937 (compare:CC
11938 (plus:SI (lshiftrt:SI
11939 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11940 (const_int 31))
11941 (match_operand:SI 2 "gpc_reg_operand" ""))
11942 (const_int 0)))
11943 (set (match_operand:SI 0 "gpc_reg_operand" "")
11944 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11945 (match_dup 2)))
11946 (clobber (match_scratch:SI 3 ""))]
683bdff7 11947 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 11948 [(parallel [(set (match_dup 0)
11949 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11950 (match_dup 2)))
11951 (clobber (match_dup 3))])
11952 (set (match_dup 4)
11953 (compare:CC (match_dup 0)
11954 (const_int 0)))]
11955 "")
1fd4e8c1 11956
a260abc9 11957(define_insn ""
9ebbca7d 11958 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 11959 (compare:CC
11960 (plus:DI (lshiftrt:DI
9ebbca7d 11961 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 11962 (const_int 63))
9ebbca7d 11963 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 11964 (const_int 0)))
9ebbca7d 11965 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 11966 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11967 (match_dup 2)))
9ebbca7d 11968 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 11969 "TARGET_64BIT"
9ebbca7d
GK		 11970 "@
11971 addic %3,%1,-1\;addze. %0,%2
11972 #"
a260abc9 11973 [(set_attr "type" "compare")
9ebbca7d
GK		 11974 (set_attr "length" "8,12")])
11975
11976(define_split
11977 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11978 (compare:CC
11979 (plus:DI (lshiftrt:DI
11980 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11981 (const_int 63))
11982 (match_operand:DI 2 "gpc_reg_operand" ""))
11983 (const_int 0)))
11984 (set (match_operand:DI 0 "gpc_reg_operand" "")
11985 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11986 (match_dup 2)))
11987 (clobber (match_scratch:DI 3 ""))]
683bdff7 11988 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 11989 [(parallel [(set (match_dup 0)
11990 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11991 (match_dup 2)))
11992 (clobber (match_dup 3))])
11993 (set (match_dup 4)
11994 (compare:CC (match_dup 0)
11995 (const_int 0)))]
11996 "")
a260abc9 11997
1fd4e8c1 11998(define_insn ""
cd2b37d9
RK		 11999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12000 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 12001 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12002 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 12003 "TARGET_POWER"
1fd4e8c1 12004 "@
ca7f5001 12005 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 12006 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12007 [(set_attr "length" "12")])
1fd4e8c1
RK		 12008
12009(define_insn ""
9ebbca7d 12010 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12011 (compare:CC
9ebbca7d
GK		 12012 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12013 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 12014 (const_int 0)))
9ebbca7d 12015 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12016 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12017 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 12018 "TARGET_POWER"
1fd4e8c1 12019 "@
ca7f5001 12020 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 12021 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12022 #
12023 #"
12024 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12025 (set_attr "length" "12,12,16,16")])
12026
12027(define_split
12028 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12029 (compare:CC
12030 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12031 (match_operand:SI 2 "reg_or_short_operand" ""))
12032 (const_int 0)))
12033 (set (match_operand:SI 0 "gpc_reg_operand" "")
12034 (le:SI (match_dup 1) (match_dup 2)))
12035 (clobber (match_scratch:SI 3 ""))]
12036 "TARGET_POWER && reload_completed"
12037 [(parallel [(set (match_dup 0)
12038 (le:SI (match_dup 1) (match_dup 2)))
12039 (clobber (match_dup 3))])
12040 (set (match_dup 4)
12041 (compare:CC (match_dup 0)
12042 (const_int 0)))]
12043 "")
1fd4e8c1
RK		 12044
12045(define_insn ""
097657c3 12046 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12047 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12048 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 12049 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 12050 "TARGET_POWER"
1fd4e8c1 12051 "@
097657c3
AM		 12052 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12053 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 12054 [(set_attr "length" "12")])
1fd4e8c1
RK		 12055
12056(define_insn ""
9ebbca7d 12057 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12058 (compare:CC
9ebbca7d
GK		 12059 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12060 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12061 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12062 (const_int 0)))
9ebbca7d 12063 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 12064 "TARGET_POWER"
1fd4e8c1 12065 "@
ca7f5001 12066 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12067 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12068 #
12069 #"
b19003d8 12070 [(set_attr "type" "compare")
9ebbca7d
GK		 12071 (set_attr "length" "12,12,16,16")])
12072
12073(define_split
12074 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12075 (compare:CC
12076 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12077 (match_operand:SI 2 "reg_or_short_operand" ""))
12078 (match_operand:SI 3 "gpc_reg_operand" ""))
12079 (const_int 0)))
12080 (clobber (match_scratch:SI 4 ""))]
12081 "TARGET_POWER && reload_completed"
12082 [(set (match_dup 4)
12083 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 12084 (match_dup 3)))
9ebbca7d
GK		 12085 (set (match_dup 0)
12086 (compare:CC (match_dup 4)
12087 (const_int 0)))]
12088 "")
1fd4e8c1
RK		 12089
12090(define_insn ""
097657c3 12091 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12092 (compare:CC
9ebbca7d
GK		 12093 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12094 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12095 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12096 (const_int 0)))
097657c3
AM		 12097 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12098 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12099 "TARGET_POWER"
1fd4e8c1 12100 "@
097657c3
AM		 12101 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12102 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12103 #
12104 #"
b19003d8 12105 [(set_attr "type" "compare")
9ebbca7d
GK		 12106 (set_attr "length" "12,12,16,16")])
12107
12108(define_split
097657c3 12109 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12110 (compare:CC
12111 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12112 (match_operand:SI 2 "reg_or_short_operand" ""))
12113 (match_operand:SI 3 "gpc_reg_operand" ""))
12114 (const_int 0)))
12115 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12116 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12117 "TARGET_POWER && reload_completed"
097657c3 12118 [(set (match_dup 0)
9ebbca7d 12119 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12120 (set (match_dup 4)
9ebbca7d
GK		 12121 (compare:CC (match_dup 0)
12122 (const_int 0)))]
12123 "")
1fd4e8c1
RK		 12124
12125(define_insn ""
cd2b37d9
RK		 12126 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12127 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12128 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 12129 "TARGET_POWER"
1fd4e8c1 12130 "@
ca7f5001
RK		 12131 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12132 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12133 [(set_attr "length" "12")])
1fd4e8c1
RK		 12134
12135(define_insn ""
cd2b37d9
RK		 12136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12137 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12138 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
f9562f27 12139 "! TARGET_POWERPC64"
ca7f5001 12140 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
b19003d8 12141 [(set_attr "length" "12")])
1fd4e8c1 12142
f9562f27
DE		 12143(define_insn ""
12144 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12145 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12146 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
683bdff7 12147 "TARGET_64BIT"
f9562f27
DE		 12148 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12149 [(set_attr "length" "12")])
12150
12151(define_insn ""
9ebbca7d 12152 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 12153 (compare:CC
9ebbca7d
GK		 12154 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12155 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
f9562f27 12156 (const_int 0)))
9ebbca7d 12157 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
f9562f27 12158 (leu:DI (match_dup 1) (match_dup 2)))]
683bdff7 12159 "TARGET_64BIT"
9ebbca7d
GK		 12160 "@
12161 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12162 #"
f9562f27 12163 [(set_attr "type" "compare")
9ebbca7d
GK		 12164 (set_attr "length" "12,16")])
12165
12166(define_split
12167 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12168 (compare:CC
12169 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12170 (match_operand:DI 2 "reg_or_short_operand" ""))
12171 (const_int 0)))
12172 (set (match_operand:DI 0 "gpc_reg_operand" "")
12173 (leu:DI (match_dup 1) (match_dup 2)))]
683bdff7 12174 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12175 [(set (match_dup 0)
12176 (leu:DI (match_dup 1) (match_dup 2)))
12177 (set (match_dup 3)
12178 (compare:CC (match_dup 0)
12179 (const_int 0)))]
12180 "")
f9562f27 12181
1fd4e8c1 12182(define_insn ""
9ebbca7d 12183 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12184 (compare:CC
9ebbca7d
GK		 12185 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12186 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12187 (const_int 0)))
9ebbca7d 12188 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12189 (leu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12190 "TARGET_32BIT"
9ebbca7d
GK		 12191 "@
12192 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12193 #"
b19003d8 12194 [(set_attr "type" "compare")
9ebbca7d
GK		 12195 (set_attr "length" "12,16")])
12196
12197(define_split
12198 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12199 (compare:CC
12200 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12201 (match_operand:SI 2 "reg_or_short_operand" ""))
12202 (const_int 0)))
12203 (set (match_operand:SI 0 "gpc_reg_operand" "")
12204 (leu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12205 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12206 [(set (match_dup 0)
12207 (leu:SI (match_dup 1) (match_dup 2)))
12208 (set (match_dup 3)
12209 (compare:CC (match_dup 0)
12210 (const_int 0)))]
12211 "")
1fd4e8c1
RK		 12212
12213(define_insn ""
80103f96 12214 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12215 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12216 (match_operand:SI 2 "reg_or_short_operand" "rI"))
80103f96 12217 (match_operand:SI 3 "gpc_reg_operand" "r")))]
683bdff7 12218 "TARGET_32BIT"
80103f96 12219 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
b19003d8 12220 [(set_attr "length" "8")])
1fd4e8c1
RK		 12221
12222(define_insn ""
9ebbca7d 12223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12224 (compare:CC
9ebbca7d
GK		 12225 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12226 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12227 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12228 (const_int 0)))
9ebbca7d 12229 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12230 "TARGET_32BIT"
9ebbca7d
GK		 12231 "@
12232 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12233 #"
b19003d8 12234 [(set_attr "type" "compare")
9ebbca7d
GK		 12235 (set_attr "length" "8,12")])
12236
12237(define_split
12238 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12239 (compare:CC
12240 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12241 (match_operand:SI 2 "reg_or_short_operand" ""))
12242 (match_operand:SI 3 "gpc_reg_operand" ""))
12243 (const_int 0)))
12244 (clobber (match_scratch:SI 4 ""))]
683bdff7 12245 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12246 [(set (match_dup 4)
12247 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12248 (match_dup 3)))
12249 (set (match_dup 0)
12250 (compare:CC (match_dup 4)
12251 (const_int 0)))]
12252 "")
1fd4e8c1
RK		 12253
12254(define_insn ""
097657c3 12255 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12256 (compare:CC
9ebbca7d
GK		 12257 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12258 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12259 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12260 (const_int 0)))
097657c3
AM		 12261 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12262 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12263 "TARGET_32BIT"
9ebbca7d 12264 "@
097657c3 12265 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 12266 #"
b19003d8 12267 [(set_attr "type" "compare")
9ebbca7d
GK		 12268 (set_attr "length" "8,12")])
12269
12270(define_split
097657c3 12271 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12272 (compare:CC
12273 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12274 (match_operand:SI 2 "reg_or_short_operand" ""))
12275 (match_operand:SI 3 "gpc_reg_operand" ""))
12276 (const_int 0)))
12277 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12278 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12279 "TARGET_32BIT && reload_completed"
097657c3 12280 [(set (match_dup 0)
9ebbca7d 12281 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12282 (set (match_dup 4)
9ebbca7d
GK		 12283 (compare:CC (match_dup 0)
12284 (const_int 0)))]
12285 "")
1fd4e8c1
RK		 12286
12287(define_insn ""
cd2b37d9
RK		 12288 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12289 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12290 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
683bdff7 12291 "TARGET_32BIT"
ca7f5001 12292 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
b19003d8 12293 [(set_attr "length" "12")])
1fd4e8c1
RK		 12294
12295(define_insn ""
097657c3 12296 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1fd4e8c1 12297 (and:SI (neg:SI
cd2b37d9 12298 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12299 (match_operand:SI 2 "reg_or_short_operand" "rI")))
097657c3 12300 (match_operand:SI 3 "gpc_reg_operand" "r")))]
683bdff7 12301 "TARGET_32BIT"
097657c3 12302 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
b19003d8 12303 [(set_attr "length" "12")])
1fd4e8c1
RK		 12304
12305(define_insn ""
9ebbca7d 12306 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12307 (compare:CC
12308 (and:SI (neg:SI
9ebbca7d
GK		 12309 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12310 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12311 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12312 (const_int 0)))
9ebbca7d 12313 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12314 "TARGET_32BIT"
9ebbca7d
GK		 12315 "@
12316 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12317 #"
12318 [(set_attr "type" "compare")
12319 (set_attr "length" "12,16")])
12320
12321(define_split
12322 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12323 (compare:CC
12324 (and:SI (neg:SI
12325 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12326 (match_operand:SI 2 "reg_or_short_operand" "")))
12327 (match_operand:SI 3 "gpc_reg_operand" ""))
12328 (const_int 0)))
12329 (clobber (match_scratch:SI 4 ""))]
683bdff7 12330 "TARGET_32BIT && reload_completed"
9ebbca7d 12331 [(set (match_dup 4)
097657c3
AM		 12332 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12333 (match_dup 3)))
9ebbca7d
GK		 12334 (set (match_dup 0)
12335 (compare:CC (match_dup 4)
12336 (const_int 0)))]
12337 "")
1fd4e8c1
RK		 12338
12339(define_insn ""
097657c3 12340 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12341 (compare:CC
12342 (and:SI (neg:SI
9ebbca7d
GK		 12343 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12344 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12345 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12346 (const_int 0)))
097657c3
AM		 12347 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12348 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12349 "TARGET_32BIT"
9ebbca7d 12350 "@
097657c3 12351 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 12352 #"
b19003d8 12353 [(set_attr "type" "compare")
9ebbca7d
GK		 12354 (set_attr "length" "12,16")])
12355
12356(define_split
097657c3 12357 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12358 (compare:CC
12359 (and:SI (neg:SI
12360 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12361 (match_operand:SI 2 "reg_or_short_operand" "")))
12362 (match_operand:SI 3 "gpc_reg_operand" ""))
12363 (const_int 0)))
12364 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12365 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12366 "TARGET_32BIT && reload_completed"
097657c3
AM		 12367 [(set (match_dup 0)
12368 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12369 (match_dup 3)))
12370 (set (match_dup 4)
9ebbca7d
GK		 12371 (compare:CC (match_dup 0)
12372 (const_int 0)))]
12373 "")
1fd4e8c1
RK		 12374
12375(define_insn ""
cd2b37d9
RK		 12376 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12377 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12378 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 12379 "TARGET_POWER"
7f340546 12380 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12381 [(set_attr "length" "12")])
1fd4e8c1
RK		 12382
12383(define_insn ""
9ebbca7d 12384 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12385 (compare:CC
9ebbca7d
GK		 12386 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12387 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12388 (const_int 0)))
9ebbca7d 12389 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12390 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 12391 "TARGET_POWER"
9ebbca7d
GK		 12392 "@
12393 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12394 #"
29ae5b89 12395 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 12396 (set_attr "length" "12,16")])
12397
12398(define_split
12399 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12400 (compare:CC
12401 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12402 (match_operand:SI 2 "reg_or_short_operand" ""))
12403 (const_int 0)))
12404 (set (match_operand:SI 0 "gpc_reg_operand" "")
12405 (lt:SI (match_dup 1) (match_dup 2)))]
12406 "TARGET_POWER && reload_completed"
12407 [(set (match_dup 0)
12408 (lt:SI (match_dup 1) (match_dup 2)))
12409 (set (match_dup 3)
12410 (compare:CC (match_dup 0)
12411 (const_int 0)))]
12412 "")
1fd4e8c1
RK		 12413
12414(define_insn ""
097657c3 12415 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12416 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12417 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 12418 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 12419 "TARGET_POWER"
097657c3 12420 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 12421 [(set_attr "length" "12")])
1fd4e8c1
RK		 12422
12423(define_insn ""
9ebbca7d 12424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12425 (compare:CC
9ebbca7d
GK		 12426 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12427 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12428 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12429 (const_int 0)))
9ebbca7d 12430 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 12431 "TARGET_POWER"
9ebbca7d
GK		 12432 "@
12433 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12434 #"
b19003d8 12435 [(set_attr "type" "compare")
9ebbca7d
GK		 12436 (set_attr "length" "12,16")])
12437
12438(define_split
12439 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12440 (compare:CC
12441 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12442 (match_operand:SI 2 "reg_or_short_operand" ""))
12443 (match_operand:SI 3 "gpc_reg_operand" ""))
12444 (const_int 0)))
12445 (clobber (match_scratch:SI 4 ""))]
12446 "TARGET_POWER && reload_completed"
12447 [(set (match_dup 4)
12448 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 12449 (match_dup 3)))
9ebbca7d
GK		 12450 (set (match_dup 0)
12451 (compare:CC (match_dup 4)
12452 (const_int 0)))]
12453 "")
1fd4e8c1
RK		 12454
12455(define_insn ""
097657c3 12456 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12457 (compare:CC
9ebbca7d
GK		 12458 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12459 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12460 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12461 (const_int 0)))
097657c3
AM		 12462 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12463 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12464 "TARGET_POWER"
9ebbca7d 12465 "@
097657c3 12466 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 12467 #"
b19003d8 12468 [(set_attr "type" "compare")
9ebbca7d
GK		 12469 (set_attr "length" "12,16")])
12470
12471(define_split
097657c3 12472 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12473 (compare:CC
12474 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12475 (match_operand:SI 2 "reg_or_short_operand" ""))
12476 (match_operand:SI 3 "gpc_reg_operand" ""))
12477 (const_int 0)))
12478 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12479 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12480 "TARGET_POWER && reload_completed"
097657c3 12481 [(set (match_dup 0)
9ebbca7d 12482 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12483 (set (match_dup 4)
9ebbca7d
GK		 12484 (compare:CC (match_dup 0)
12485 (const_int 0)))]
12486 "")
1fd4e8c1
RK		 12487
12488(define_insn ""
cd2b37d9
RK		 12489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12490 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12491 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 12492 "TARGET_POWER"
12493 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12494 [(set_attr "length" "12")])
1fd4e8c1
RK		 12495
12496(define_insn ""
cd2b37d9
RK		 12497 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12498 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12499 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
683bdff7 12500 "TARGET_32BIT"
1fd4e8c1 12501 "@
ca7f5001
RK		 12502 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12503 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
b19003d8 12504 [(set_attr "length" "12")])
1fd4e8c1
RK		 12505
12506(define_insn ""
9ebbca7d 12507 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12508 (compare:CC
9ebbca7d
GK		 12509 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12510 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 12511 (const_int 0)))
9ebbca7d 12512 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12513 (ltu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12514 "TARGET_32BIT"
1fd4e8c1 12515 "@
ca7f5001 12516 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
9ebbca7d
GK		 12517 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12518 #
12519 #"
b19003d8 12520 [(set_attr "type" "compare")
9ebbca7d
GK		 12521 (set_attr "length" "12,12,16,16")])
12522
12523(define_split
12524 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12525 (compare:CC
12526 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12527 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12528 (const_int 0)))
12529 (set (match_operand:SI 0 "gpc_reg_operand" "")
12530 (ltu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12531 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12532 [(set (match_dup 0)
12533 (ltu:SI (match_dup 1) (match_dup 2)))
12534 (set (match_dup 3)
12535 (compare:CC (match_dup 0)
12536 (const_int 0)))]
12537 "")
1fd4e8c1
RK		 12538
12539(define_insn ""
80103f96 12540 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
19378cf8
MM		 12541 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12542 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
80103f96 12543 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
683bdff7 12544 "TARGET_32BIT"
1fd4e8c1 12545 "@
80103f96
FS		 12546 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12547 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
b19003d8 12548 [(set_attr "length" "12")])
1fd4e8c1
RK		 12549
12550(define_insn ""
9ebbca7d 12551 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12552 (compare:CC
9ebbca7d
GK		 12553 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12554 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12555 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12556 (const_int 0)))
9ebbca7d 12557 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 12558 "TARGET_32BIT"
1fd4e8c1 12559 "@
ca7f5001 12560 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
9ebbca7d
GK		 12561 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12562 #
12563 #"
b19003d8 12564 [(set_attr "type" "compare")
9ebbca7d
GK		 12565 (set_attr "length" "12,12,16,16")])
12566
12567(define_split
12568 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12569 (compare:CC
12570 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12571 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12572 (match_operand:SI 3 "gpc_reg_operand" ""))
12573 (const_int 0)))
12574 (clobber (match_scratch:SI 4 ""))]
683bdff7 12575 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12576 [(set (match_dup 4)
12577 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
097657c3 12578 (match_dup 3)))
9ebbca7d
GK		 12579 (set (match_dup 0)
12580 (compare:CC (match_dup 4)
12581 (const_int 0)))]
12582 "")
1fd4e8c1
RK		 12583
12584(define_insn ""
097657c3 12585 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12586 (compare:CC
9ebbca7d
GK		 12587 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12588 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12589 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12590 (const_int 0)))
097657c3
AM		 12591 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12592 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12593 "TARGET_32BIT"
1fd4e8c1 12594 "@
097657c3
AM		 12595 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12596 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
9ebbca7d
GK		 12597 #
12598 #"
b19003d8 12599 [(set_attr "type" "compare")
9ebbca7d
GK		 12600 (set_attr "length" "12,12,16,16")])
12601
12602(define_split
097657c3 12603 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12604 (compare:CC
12605 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12606 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12607 (match_operand:SI 3 "gpc_reg_operand" ""))
12608 (const_int 0)))
12609 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12610 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12611 "TARGET_32BIT && reload_completed"
097657c3 12612 [(set (match_dup 0)
9ebbca7d 12613 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12614 (set (match_dup 4)
9ebbca7d
GK		 12615 (compare:CC (match_dup 0)
12616 (const_int 0)))]
12617 "")
1fd4e8c1
RK		 12618
12619(define_insn ""
cd2b37d9
RK		 12620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12621 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12622 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
683bdff7 12623 "TARGET_32BIT"
1fd4e8c1 12624 "@
ca7f5001
RK		 12625 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12626 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
b19003d8 12627 [(set_attr "length" "8")])
1fd4e8c1
RK		 12628
12629(define_insn ""
cd2b37d9
RK		 12630 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12631 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 12632 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12633 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 12634 "TARGET_POWER"
12635 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 12636 [(set_attr "length" "12")])
1fd4e8c1 12637
9ebbca7d
GK		 12638(define_insn ""
12639 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12640 (compare:CC
9ebbca7d
GK		 12641 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12642 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12643 (const_int 0)))
9ebbca7d 12644 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12645 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12646 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 12647 "TARGET_POWER"
9ebbca7d
GK		 12648 "@
12649 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12650 #"
12651 [(set_attr "type" "compare")
12652 (set_attr "length" "12,16")])
12653
12654(define_split
12655 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12656 (compare:CC
12657 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12658 (match_operand:SI 2 "reg_or_short_operand" ""))
12659 (const_int 0)))
12660 (set (match_operand:SI 0 "gpc_reg_operand" "")
12661 (ge:SI (match_dup 1) (match_dup 2)))
12662 (clobber (match_scratch:SI 3 ""))]
12663 "TARGET_POWER && reload_completed"
12664 [(parallel [(set (match_dup 0)
097657c3
AM		 12665 (ge:SI (match_dup 1) (match_dup 2)))
12666 (clobber (match_dup 3))])
9ebbca7d
GK		 12667 (set (match_dup 4)
12668 (compare:CC (match_dup 0)
12669 (const_int 0)))]
12670 "")
12671
1fd4e8c1 12672(define_insn ""
097657c3 12673 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12674 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12675 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 12676 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 12677 "TARGET_POWER"
097657c3 12678 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 12679 [(set_attr "length" "12")])
1fd4e8c1
RK		 12680
12681(define_insn ""
9ebbca7d 12682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12683 (compare:CC
9ebbca7d
GK		 12684 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12685 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12686 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12687 (const_int 0)))
9ebbca7d 12688 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 12689 "TARGET_POWER"
9ebbca7d
GK		 12690 "@
12691 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12692 #"
b19003d8 12693 [(set_attr "type" "compare")
9ebbca7d
GK		 12694 (set_attr "length" "12,16")])
12695
12696(define_split
12697 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12698 (compare:CC
12699 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12700 (match_operand:SI 2 "reg_or_short_operand" ""))
12701 (match_operand:SI 3 "gpc_reg_operand" ""))
12702 (const_int 0)))
12703 (clobber (match_scratch:SI 4 ""))]
12704 "TARGET_POWER && reload_completed"
12705 [(set (match_dup 4)
12706 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 12707 (match_dup 3)))
9ebbca7d
GK		 12708 (set (match_dup 0)
12709 (compare:CC (match_dup 4)
12710 (const_int 0)))]
12711 "")
1fd4e8c1
RK		 12712
12713(define_insn ""
097657c3 12714 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12715 (compare:CC
9ebbca7d
GK		 12716 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12717 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12718 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12719 (const_int 0)))
097657c3
AM		 12720 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12721 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12722 "TARGET_POWER"
9ebbca7d 12723 "@
097657c3 12724 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 12725 #"
b19003d8 12726 [(set_attr "type" "compare")
9ebbca7d
GK		 12727 (set_attr "length" "12,16")])
12728
12729(define_split
097657c3 12730 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12731 (compare:CC
12732 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12733 (match_operand:SI 2 "reg_or_short_operand" ""))
12734 (match_operand:SI 3 "gpc_reg_operand" ""))
12735 (const_int 0)))
12736 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12737 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12738 "TARGET_POWER && reload_completed"
097657c3 12739 [(set (match_dup 0)
9ebbca7d 12740 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12741 (set (match_dup 4)
9ebbca7d
GK		 12742 (compare:CC (match_dup 0)
12743 (const_int 0)))]
12744 "")
1fd4e8c1
RK		 12745
12746(define_insn ""
cd2b37d9
RK		 12747 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12748 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12749 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 12750 "TARGET_POWER"
12751 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 12752 [(set_attr "length" "12")])
1fd4e8c1 12753
1fd4e8c1 12754(define_insn ""
cd2b37d9
RK		 12755 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12756 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12757 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
683bdff7 12758 "TARGET_32BIT"
1fd4e8c1 12759 "@
ca7f5001
RK		 12760 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12761 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
b19003d8 12762 [(set_attr "length" "12")])
1fd4e8c1 12763
f9562f27
DE		 12764(define_insn ""
12765 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12766 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12767 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
683bdff7 12768 "TARGET_64BIT"
f9562f27
DE		 12769 "@
12770 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12771 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12772 [(set_attr "length" "12")])
12773
1fd4e8c1 12774(define_insn ""
9ebbca7d 12775 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12776 (compare:CC
9ebbca7d
GK		 12777 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12778 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 12779 (const_int 0)))
9ebbca7d 12780 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12781 (geu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12782 "TARGET_32BIT"
1fd4e8c1 12783 "@
ca7f5001 12784 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 12785 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12786 #
12787 #"
b19003d8 12788 [(set_attr "type" "compare")
9ebbca7d
GK		 12789 (set_attr "length" "12,12,16,16")])
12790
12791(define_split
12792 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12793 (compare:CC
12794 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12795 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12796 (const_int 0)))
12797 (set (match_operand:SI 0 "gpc_reg_operand" "")
12798 (geu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12799 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12800 [(set (match_dup 0)
12801 (geu:SI (match_dup 1) (match_dup 2)))
12802 (set (match_dup 3)
12803 (compare:CC (match_dup 0)
12804 (const_int 0)))]
12805 "")
1fd4e8c1 12806
f9562f27 12807(define_insn ""
9ebbca7d 12808 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 12809 (compare:CC
9ebbca7d
GK		 12810 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12811 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
f9562f27 12812 (const_int 0)))
9ebbca7d 12813 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
f9562f27 12814 (geu:DI (match_dup 1) (match_dup 2)))]
683bdff7 12815 "TARGET_64BIT"
f9562f27
DE		 12816 "@
12817 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
9ebbca7d
GK		 12818 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12819 #
12820 #"
f9562f27 12821 [(set_attr "type" "compare")
9ebbca7d
GK		 12822 (set_attr "length" "12,12,16,16")])
12823
12824(define_split
12825 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12826 (compare:CC
12827 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12828 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12829 (const_int 0)))
12830 (set (match_operand:DI 0 "gpc_reg_operand" "")
12831 (geu:DI (match_dup 1) (match_dup 2)))]
683bdff7 12832 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12833 [(set (match_dup 0)
12834 (geu:DI (match_dup 1) (match_dup 2)))
12835 (set (match_dup 3)
12836 (compare:CC (match_dup 0)
12837 (const_int 0)))]
12838 "")
f9562f27 12839
1fd4e8c1 12840(define_insn ""
80103f96 12841 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12842 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12843 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
80103f96 12844 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
683bdff7 12845 "TARGET_32BIT"
1fd4e8c1 12846 "@
80103f96
FS		 12847 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12848 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
b19003d8 12849 [(set_attr "length" "8")])
1fd4e8c1
RK		 12850
12851(define_insn ""
9ebbca7d 12852 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12853 (compare:CC
9ebbca7d
GK		 12854 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12855 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12856 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12857 (const_int 0)))
9ebbca7d 12858 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 12859 "TARGET_32BIT"
1fd4e8c1 12860 "@
ca7f5001 12861 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12862 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12863 #
12864 #"
b19003d8 12865 [(set_attr "type" "compare")
9ebbca7d
GK		 12866 (set_attr "length" "8,8,12,12")])
12867
12868(define_split
12869 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12870 (compare:CC
12871 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12872 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12873 (match_operand:SI 3 "gpc_reg_operand" ""))
12874 (const_int 0)))
12875 (clobber (match_scratch:SI 4 ""))]
683bdff7 12876 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12877 [(set (match_dup 4)
12878 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12879 (match_dup 3)))
12880 (set (match_dup 0)
12881 (compare:CC (match_dup 4)
12882 (const_int 0)))]
12883 "")
1fd4e8c1
RK		 12884
12885(define_insn ""
097657c3 12886 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12887 (compare:CC
9ebbca7d
GK		 12888 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12889 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12890 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12891 (const_int 0)))
097657c3
AM		 12892 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12893 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12894 "TARGET_32BIT"
1fd4e8c1 12895 "@
097657c3
AM		 12896 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12897 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12898 #
12899 #"
b19003d8 12900 [(set_attr "type" "compare")
9ebbca7d
GK		 12901 (set_attr "length" "8,8,12,12")])
12902
12903(define_split
097657c3 12904 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12905 (compare:CC
12906 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12907 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12908 (match_operand:SI 3 "gpc_reg_operand" ""))
12909 (const_int 0)))
12910 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12911 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12912 "TARGET_32BIT && reload_completed"
097657c3 12913 [(set (match_dup 0)
9ebbca7d 12914 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12915 (set (match_dup 4)
9ebbca7d
GK		 12916 (compare:CC (match_dup 0)
12917 (const_int 0)))]
12918 "")
1fd4e8c1
RK		 12919
12920(define_insn ""
cd2b37d9
RK		 12921 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12922 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12923 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
683bdff7 12924 "TARGET_32BIT"
1fd4e8c1 12925 "@
ca7f5001 12926 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 12927 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
b19003d8 12928 [(set_attr "length" "12")])
1fd4e8c1
RK		 12929
12930(define_insn ""
097657c3 12931 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
1fd4e8c1 12932 (and:SI (neg:SI
cd2b37d9 12933 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12934 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
097657c3 12935 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
683bdff7 12936 "TARGET_32BIT"
1fd4e8c1 12937 "@
097657c3
AM		 12938 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12939 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
b19003d8 12940 [(set_attr "length" "12")])
1fd4e8c1
RK		 12941
12942(define_insn ""
9ebbca7d 12943 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 12944 (compare:CC
12945 (and:SI (neg:SI
9ebbca7d
GK		 12946 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12947 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12948 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12949 (const_int 0)))
9ebbca7d 12950 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 12951 "TARGET_32BIT"
1fd4e8c1 12952 "@
ca7f5001 12953 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 12954 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12955 #
12956 #"
b19003d8 12957 [(set_attr "type" "compare")
9ebbca7d
GK		 12958 (set_attr "length" "12,12,16,16")])
12959
12960(define_split
12961 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12962 (compare:CC
12963 (and:SI (neg:SI
12964 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12965 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12966 (match_operand:SI 3 "gpc_reg_operand" ""))
12967 (const_int 0)))
12968 (clobber (match_scratch:SI 4 ""))]
683bdff7 12969 "TARGET_32BIT && reload_completed"
9ebbca7d 12970 [(set (match_dup 4)
097657c3
AM		 12971 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12972 (match_dup 3)))
9ebbca7d
GK		 12973 (set (match_dup 0)
12974 (compare:CC (match_dup 4)
12975 (const_int 0)))]
12976 "")
1fd4e8c1
RK		 12977
12978(define_insn ""
097657c3 12979 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 12980 (compare:CC
12981 (and:SI (neg:SI
9ebbca7d
GK		 12982 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12983 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12984 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12985 (const_int 0)))
097657c3
AM		 12986 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12987 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12988 "TARGET_32BIT"
1fd4e8c1 12989 "@
097657c3
AM		 12990 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12991 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 12992 #
12993 #"
b19003d8 12994 [(set_attr "type" "compare")
9ebbca7d
GK		 12995 (set_attr "length" "12,12,16,16")])
12996
12997(define_split
097657c3 12998 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12999 (compare:CC
13000 (and:SI (neg:SI
13001 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13002 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13003 (match_operand:SI 3 "gpc_reg_operand" ""))
13004 (const_int 0)))
13005 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13006 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13007 "TARGET_32BIT && reload_completed"
097657c3 13008 [(set (match_dup 0)
9ebbca7d 13009 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 13010 (set (match_dup 4)
9ebbca7d
GK		 13011 (compare:CC (match_dup 0)
13012 (const_int 0)))]
13013 "")
1fd4e8c1
RK		 13014
13015(define_insn ""
cd2b37d9
RK		 13016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13017 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13018 (const_int 0)))]
683bdff7 13019 "TARGET_32BIT"
ca7f5001 13020 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13021 [(set_attr "length" "12")])
1fd4e8c1 13022
f9562f27
DE		 13023(define_insn ""
13024 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13025 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13026 (const_int 0)))]
683bdff7 13027 "TARGET_64BIT"
f9562f27
DE		 13028 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
13029 [(set_attr "length" "12")])
13030
1fd4e8c1 13031(define_insn ""
9ebbca7d 13032 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1fd4e8c1 13033 (compare:CC
9ebbca7d 13034 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 13035 (const_int 0))
13036 (const_int 0)))
9ebbca7d 13037 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13038 (gt:SI (match_dup 1) (const_int 0)))]
683bdff7 13039 "TARGET_32BIT"
9ebbca7d
GK		 13040 "@
13041 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13042 #"
29ae5b89 13043 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13044 (set_attr "length" "12,16")])
13045
13046(define_split
13047 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13048 (compare:CC
13049 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13050 (const_int 0))
13051 (const_int 0)))
13052 (set (match_operand:SI 0 "gpc_reg_operand" "")
13053 (gt:SI (match_dup 1) (const_int 0)))]
683bdff7 13054 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13055 [(set (match_dup 0)
13056 (gt:SI (match_dup 1) (const_int 0)))
13057 (set (match_dup 2)
13058 (compare:CC (match_dup 0)
13059 (const_int 0)))]
13060 "")
1fd4e8c1 13061
f9562f27 13062(define_insn ""
9ebbca7d 13063 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
f9562f27 13064 (compare:CC
9ebbca7d 13065 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27
DE		 13066 (const_int 0))
13067 (const_int 0)))
9ebbca7d 13068 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
f9562f27 13069 (gt:DI (match_dup 1) (const_int 0)))]
683bdff7 13070 "TARGET_64BIT"
9ebbca7d
GK		 13071 "@
13072 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13073 #"
f9562f27 13074 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13075 (set_attr "length" "12,16")])
13076
13077(define_split
13078 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13079 (compare:CC
13080 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13081 (const_int 0))
13082 (const_int 0)))
13083 (set (match_operand:DI 0 "gpc_reg_operand" "")
13084 (gt:DI (match_dup 1) (const_int 0)))]
683bdff7 13085 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13086 [(set (match_dup 0)
13087 (gt:DI (match_dup 1) (const_int 0)))
13088 (set (match_dup 2)
13089 (compare:CC (match_dup 0)
13090 (const_int 0)))]
13091 "")
f9562f27 13092
1fd4e8c1 13093(define_insn ""
cd2b37d9
RK		 13094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13095 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13096 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 13097 "TARGET_POWER"
13098 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13099 [(set_attr "length" "12")])
1fd4e8c1
RK		 13100
13101(define_insn ""
9ebbca7d 13102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13103 (compare:CC
9ebbca7d
GK		 13104 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13105 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 13106 (const_int 0)))
9ebbca7d 13107 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13108 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13109 "TARGET_POWER"
9ebbca7d
GK		 13110 "@
13111 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13112 #"
29ae5b89 13113 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13114 (set_attr "length" "12,16")])
13115
13116(define_split
13117 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13118 (compare:CC
13119 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13120 (match_operand:SI 2 "reg_or_short_operand" ""))
13121 (const_int 0)))
13122 (set (match_operand:SI 0 "gpc_reg_operand" "")
13123 (gt:SI (match_dup 1) (match_dup 2)))]
13124 "TARGET_POWER && reload_completed"
13125 [(set (match_dup 0)
13126 (gt:SI (match_dup 1) (match_dup 2)))
13127 (set (match_dup 3)
13128 (compare:CC (match_dup 0)
13129 (const_int 0)))]
13130 "")
1fd4e8c1
RK		 13131
13132(define_insn ""
80103f96 13133 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13134 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13135 (const_int 0))
80103f96 13136 (match_operand:SI 2 "gpc_reg_operand" "r")))]
683bdff7 13137 "TARGET_32BIT"
80103f96 13138 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
b19003d8 13139 [(set_attr "length" "12")])
1fd4e8c1 13140
f9562f27 13141(define_insn ""
097657c3 13142 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
f9562f27
DE		 13143 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13144 (const_int 0))
097657c3 13145 (match_operand:DI 2 "gpc_reg_operand" "r")))]
683bdff7 13146 "TARGET_64BIT"
097657c3 13147 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
f9562f27
DE		 13148 [(set_attr "length" "12")])
13149
1fd4e8c1 13150(define_insn ""
9ebbca7d 13151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13152 (compare:CC
9ebbca7d 13153 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13154 (const_int 0))
9ebbca7d 13155 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 13156 (const_int 0)))
9ebbca7d 13157 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 13158 "TARGET_32BIT"
9ebbca7d
GK		 13159 "@
13160 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13161 #"
b19003d8 13162 [(set_attr "type" "compare")
9ebbca7d
GK		 13163 (set_attr "length" "12,16")])
13164
13165(define_split
13166 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13167 (compare:CC
13168 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13169 (const_int 0))
13170 (match_operand:SI 2 "gpc_reg_operand" ""))
13171 (const_int 0)))
13172 (clobber (match_scratch:SI 3 ""))]
683bdff7 13173 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13174 [(set (match_dup 3)
13175 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13176 (match_dup 2)))
13177 (set (match_dup 0)
13178 (compare:CC (match_dup 3)
13179 (const_int 0)))]
13180 "")
1fd4e8c1 13181
f9562f27 13182(define_insn ""
9ebbca7d 13183 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 13184 (compare:CC
9ebbca7d 13185 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13186 (const_int 0))
9ebbca7d 13187 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13188 (const_int 0)))
9ebbca7d 13189 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 13190 "TARGET_64BIT"
9ebbca7d
GK		 13191 "@
13192 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13193 #"
f9562f27 13194 [(set_attr "type" "compare")
9ebbca7d
GK		 13195 (set_attr "length" "12,16")])
13196
13197(define_split
13198 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13199 (compare:CC
13200 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13201 (const_int 0))
13202 (match_operand:DI 2 "gpc_reg_operand" ""))
13203 (const_int 0)))
13204 (clobber (match_scratch:DI 3 ""))]
683bdff7 13205 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13206 [(set (match_dup 3)
13207 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 13208 (match_dup 2)))
9ebbca7d
GK		 13209 (set (match_dup 0)
13210 (compare:CC (match_dup 3)
13211 (const_int 0)))]
13212 "")
f9562f27 13213
1fd4e8c1 13214(define_insn ""
097657c3 13215 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 13216 (compare:CC
13217 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13218 (const_int 0))
13219 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13220 (const_int 0)))
097657c3
AM		 13221 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13222 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13223 "TARGET_32BIT"
9ebbca7d 13224 "@
097657c3 13225 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 13226 #"
13227 [(set_attr "type" "compare")
13228 (set_attr "length" "12,16")])
13229
13230(define_split
097657c3 13231 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 13232 (compare:CC
9ebbca7d 13233 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 13234 (const_int 0))
9ebbca7d 13235 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 13236 (const_int 0)))
9ebbca7d 13237 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13238 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13239 "TARGET_32BIT && reload_completed"
097657c3 13240 [(set (match_dup 0)
9ebbca7d 13241 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13242 (set (match_dup 3)
9ebbca7d
GK		 13243 (compare:CC (match_dup 0)
13244 (const_int 0)))]
13245 "")
1fd4e8c1 13246
f9562f27 13247(define_insn ""
097657c3 13248 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13249 (compare:CC
9ebbca7d 13250 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13251 (const_int 0))
9ebbca7d 13252 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13253 (const_int 0)))
097657c3
AM		 13254 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13255 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13256 "TARGET_64BIT"
9ebbca7d 13257 "@
097657c3 13258 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 13259 #"
f9562f27 13260 [(set_attr "type" "compare")
9ebbca7d
GK		 13261 (set_attr "length" "12,16")])
13262
13263(define_split
097657c3 13264 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13265 (compare:CC
13266 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13267 (const_int 0))
13268 (match_operand:DI 2 "gpc_reg_operand" ""))
13269 (const_int 0)))
13270 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13271 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13272 "TARGET_64BIT && reload_completed"
097657c3 13273 [(set (match_dup 0)
9ebbca7d 13274 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13275 (set (match_dup 3)
9ebbca7d
GK		 13276 (compare:CC (match_dup 0)
13277 (const_int 0)))]
13278 "")
f9562f27 13279
1fd4e8c1 13280(define_insn ""
097657c3 13281 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13282 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13283 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 13284 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13285 "TARGET_POWER"
097657c3 13286 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13287 [(set_attr "length" "12")])
1fd4e8c1
RK		 13288
13289(define_insn ""
9ebbca7d 13290 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13291 (compare:CC
9ebbca7d
GK		 13292 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13293 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13294 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13295 (const_int 0)))
9ebbca7d 13296 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13297 "TARGET_POWER"
9ebbca7d
GK		 13298 "@
13299 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13300 #"
b19003d8 13301 [(set_attr "type" "compare")
9ebbca7d
GK		 13302 (set_attr "length" "12,16")])
13303
13304(define_split
13305 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13306 (compare:CC
13307 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13308 (match_operand:SI 2 "reg_or_short_operand" ""))
13309 (match_operand:SI 3 "gpc_reg_operand" ""))
13310 (const_int 0)))
13311 (clobber (match_scratch:SI 4 ""))]
13312 "TARGET_POWER && reload_completed"
13313 [(set (match_dup 4)
097657c3 13314 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 13315 (set (match_dup 0)
13316 (compare:CC (match_dup 4)
13317 (const_int 0)))]
13318 "")
1fd4e8c1
RK		 13319
13320(define_insn ""
097657c3 13321 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13322 (compare:CC
9ebbca7d
GK		 13323 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13324 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13325 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13326 (const_int 0)))
097657c3
AM		 13327 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13328 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13329 "TARGET_POWER"
9ebbca7d 13330 "@
097657c3 13331 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13332 #"
b19003d8 13333 [(set_attr "type" "compare")
9ebbca7d
GK		 13334 (set_attr "length" "12,16")])
13335
13336(define_split
097657c3 13337 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13338 (compare:CC
13339 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13340 (match_operand:SI 2 "reg_or_short_operand" ""))
13341 (match_operand:SI 3 "gpc_reg_operand" ""))
13342 (const_int 0)))
13343 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13344 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13345 "TARGET_POWER && reload_completed"
097657c3 13346 [(set (match_dup 0)
9ebbca7d 13347 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13348 (set (match_dup 4)
9ebbca7d
GK		 13349 (compare:CC (match_dup 0)
13350 (const_int 0)))]
13351 "")
1fd4e8c1
RK		 13352
13353(define_insn ""
cd2b37d9
RK		 13354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13355 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13356 (const_int 0))))]
683bdff7 13357 "TARGET_32BIT"
ca7f5001 13358 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13359 [(set_attr "length" "12")])
1fd4e8c1 13360
f9562f27
DE		 13361(define_insn ""
13362 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13363 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13364 (const_int 0))))]
683bdff7 13365 "TARGET_64BIT"
8377288b 13366 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
f9562f27
DE		 13367 [(set_attr "length" "12")])
13368
1fd4e8c1 13369(define_insn ""
cd2b37d9
RK		 13370 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13371 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13372 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 13373 "TARGET_POWER"
13374 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13375 [(set_attr "length" "12")])
1fd4e8c1
RK		 13376
13377(define_insn ""
cd2b37d9
RK		 13378 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13379 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13380 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
683bdff7 13381 "TARGET_32BIT"
ca7f5001 13382 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
b19003d8 13383 [(set_attr "length" "12")])
1fd4e8c1 13384
f9562f27
DE		 13385(define_insn ""
13386 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13387 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13388 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
683bdff7 13389 "TARGET_64BIT"
f9562f27
DE		 13390 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13391 [(set_attr "length" "12")])
13392
1fd4e8c1 13393(define_insn ""
9ebbca7d 13394 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13395 (compare:CC
9ebbca7d
GK		 13396 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13397 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13398 (const_int 0)))
9ebbca7d 13399 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13400 (gtu:SI (match_dup 1) (match_dup 2)))]
683bdff7 13401 "TARGET_32BIT"
9ebbca7d
GK		 13402 "@
13403 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13404 #"
b19003d8 13405 [(set_attr "type" "compare")
9ebbca7d
GK		 13406 (set_attr "length" "12,16")])
13407
13408(define_split
13409 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13410 (compare:CC
13411 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13412 (match_operand:SI 2 "reg_or_short_operand" ""))
13413 (const_int 0)))
13414 (set (match_operand:SI 0 "gpc_reg_operand" "")
13415 (gtu:SI (match_dup 1) (match_dup 2)))]
683bdff7 13416 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13417 [(set (match_dup 0)
13418 (gtu:SI (match_dup 1) (match_dup 2)))
13419 (set (match_dup 3)
13420 (compare:CC (match_dup 0)
13421 (const_int 0)))]
13422 "")
1fd4e8c1 13423
f9562f27 13424(define_insn ""
9ebbca7d 13425 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13426 (compare:CC
9ebbca7d
GK		 13427 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13428 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
f9562f27 13429 (const_int 0)))
9ebbca7d 13430 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
f9562f27 13431 (gtu:DI (match_dup 1) (match_dup 2)))]
683bdff7 13432 "TARGET_64BIT"
9ebbca7d
GK		 13433 "@
13434 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13435 #"
f9562f27 13436 [(set_attr "type" "compare")
9ebbca7d
GK		 13437 (set_attr "length" "12,16")])
13438
13439(define_split
13440 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13441 (compare:CC
13442 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13443 (match_operand:DI 2 "reg_or_short_operand" ""))
13444 (const_int 0)))
13445 (set (match_operand:DI 0 "gpc_reg_operand" "")
13446 (gtu:DI (match_dup 1) (match_dup 2)))]
683bdff7 13447 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13448 [(set (match_dup 0)
13449 (gtu:DI (match_dup 1) (match_dup 2)))
13450 (set (match_dup 3)
13451 (compare:CC (match_dup 0)
13452 (const_int 0)))]
13453 "")
f9562f27 13454
1fd4e8c1 13455(define_insn ""
80103f96 13456 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
19378cf8
MM		 13457 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13458 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
80103f96 13459 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
683bdff7 13460 "TARGET_32BIT"
00751805 13461 "@
80103f96
FS		 13462 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13463 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
19378cf8 13464 [(set_attr "length" "8,12")])
1fd4e8c1 13465
f9562f27 13466(define_insn ""
097657c3 13467 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
f9562f27
DE		 13468 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13469 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
097657c3 13470 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
683bdff7 13471 "TARGET_64BIT"
f9562f27 13472 "@
097657c3
AM		 13473 addic %0,%1,%k2\;addze %0,%3
13474 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
f9562f27
DE		 13475 [(set_attr "length" "8,12")])
13476
1fd4e8c1 13477(define_insn ""
9ebbca7d 13478 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13479 (compare:CC
9ebbca7d
GK		 13480 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13481 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13482 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13483 (const_int 0)))
9ebbca7d 13484 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13485 "TARGET_32BIT"
00751805 13486 "@
19378cf8 13487 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13488 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13489 #
13490 #"
b19003d8 13491 [(set_attr "type" "compare")
9ebbca7d
GK		 13492 (set_attr "length" "8,12,12,16")])
13493
13494(define_split
13495 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13496 (compare:CC
13497 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13498 (match_operand:SI 2 "reg_or_short_operand" ""))
13499 (match_operand:SI 3 "gpc_reg_operand" ""))
13500 (const_int 0)))
13501 (clobber (match_scratch:SI 4 ""))]
683bdff7 13502 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13503 [(set (match_dup 4)
13504 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
097657c3 13505 (match_dup 3)))
9ebbca7d
GK		 13506 (set (match_dup 0)
13507 (compare:CC (match_dup 4)
13508 (const_int 0)))]
13509 "")
1fd4e8c1 13510
f9562f27 13511(define_insn ""
9ebbca7d 13512 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13513 (compare:CC
9ebbca7d
GK		 13514 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13515 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13516 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13517 (const_int 0)))
9ebbca7d 13518 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
683bdff7 13519 "TARGET_64BIT"
f9562f27
DE		 13520 "@
13521 addic %4,%1,%k2\;addze. %4,%3
9ebbca7d
GK		 13522 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13523 #
13524 #"
f9562f27 13525 [(set_attr "type" "compare")
9ebbca7d
GK		 13526 (set_attr "length" "8,12,12,16")])
13527
13528(define_split
13529 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13530 (compare:CC
13531 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13532 (match_operand:DI 2 "reg_or_short_operand" ""))
13533 (match_operand:DI 3 "gpc_reg_operand" ""))
13534 (const_int 0)))
13535 (clobber (match_scratch:DI 4 ""))]
683bdff7 13536 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13537 [(set (match_dup 4)
13538 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13539 (match_dup 3)))
13540 (set (match_dup 0)
13541 (compare:CC (match_dup 4)
13542 (const_int 0)))]
13543 "")
f9562f27 13544
1fd4e8c1 13545(define_insn ""
097657c3 13546 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13547 (compare:CC
9ebbca7d
GK		 13548 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13549 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13550 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13551 (const_int 0)))
097657c3
AM		 13552 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13553 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13554 "TARGET_32BIT"
00751805 13555 "@
097657c3
AM		 13556 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13557 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
9ebbca7d
GK		 13558 #
13559 #"
b19003d8 13560 [(set_attr "type" "compare")
9ebbca7d
GK		 13561 (set_attr "length" "8,12,12,16")])
13562
13563(define_split
097657c3 13564 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13565 (compare:CC
13566 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13567 (match_operand:SI 2 "reg_or_short_operand" ""))
13568 (match_operand:SI 3 "gpc_reg_operand" ""))
13569 (const_int 0)))
13570 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13571 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13572 "TARGET_32BIT && reload_completed"
097657c3 13573 [(set (match_dup 0)
9ebbca7d 13574 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13575 (set (match_dup 4)
9ebbca7d
GK		 13576 (compare:CC (match_dup 0)
13577 (const_int 0)))]
13578 "")
1fd4e8c1 13579
f9562f27 13580(define_insn ""
097657c3 13581 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13582 (compare:CC
9ebbca7d
GK		 13583 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13584 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13585 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13586 (const_int 0)))
097657c3
AM		 13587 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13588 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13589 "TARGET_64BIT"
f9562f27 13590 "@
097657c3
AM		 13591 addic %0,%1,%k2\;addze. %0,%3
13592 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
9ebbca7d
GK		 13593 #
13594 #"
f9562f27 13595 [(set_attr "type" "compare")
9ebbca7d
GK		 13596 (set_attr "length" "8,12,12,16")])
13597
13598(define_split
097657c3 13599 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13600 (compare:CC
13601 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13602 (match_operand:DI 2 "reg_or_short_operand" ""))
13603 (match_operand:DI 3 "gpc_reg_operand" ""))
13604 (const_int 0)))
13605 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13606 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13607 "TARGET_64BIT && reload_completed"
097657c3 13608 [(set (match_dup 0)
9ebbca7d 13609 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13610 (set (match_dup 4)
9ebbca7d
GK		 13611 (compare:CC (match_dup 0)
13612 (const_int 0)))]
13613 "")
f9562f27 13614
1fd4e8c1 13615(define_insn ""
cd2b37d9
RK		 13616 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13617 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13618 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
683bdff7 13619 "TARGET_32BIT"
ca7f5001 13620 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
b19003d8 13621 [(set_attr "length" "8")])
f9562f27
DE		 13622
13623(define_insn ""
13624 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13625 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13626 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
683bdff7 13627 "TARGET_64BIT"
f9562f27
DE		 13628 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13629 [(set_attr "length" "8")])
1fd4e8c1
RK		 13630\f
13631;; Define both directions of branch and return. If we need a reload
13632;; register, we'd rather use CR0 since it is much easier to copy a
13633;; register CC value to there.
13634
13635(define_insn ""
13636 [(set (pc)
13637 (if_then_else (match_operator 1 "branch_comparison_operator"
13638 [(match_operand 2
b54cf83a 13639 "cc_reg_operand" "y")
1fd4e8c1
RK		 13640 (const_int 0)])
13641 (label_ref (match_operand 0 "" ""))
13642 (pc)))]
13643 ""
b19003d8
RK		 13644 "*
13645{
12a4e8c5 13646 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 13647}"
13648 [(set_attr "type" "branch")])
13649
1fd4e8c1
RK		 13650(define_insn ""
13651 [(set (pc)
13652 (if_then_else (match_operator 0 "branch_comparison_operator"
13653 [(match_operand 1
b54cf83a 13654 "cc_reg_operand" "y")
1fd4e8c1
RK		 13655 (const_int 0)])
13656 (return)
13657 (pc)))]
13658 "direct_return ()"
12a4e8c5
GK		 13659 "*
13660{
13661 return output_cbranch (operands[0], NULL, 0, insn);
13662}"
b7ff3d82 13663 [(set_attr "type" "branch")
39a10a29 13664 (set_attr "length" "4")])
1fd4e8c1
RK		 13665
13666(define_insn ""
13667 [(set (pc)
13668 (if_then_else (match_operator 1 "branch_comparison_operator"
13669 [(match_operand 2
b54cf83a 13670 "cc_reg_operand" "y")
1fd4e8c1
RK		 13671 (const_int 0)])
13672 (pc)
13673 (label_ref (match_operand 0 "" ""))))]
13674 ""
b19003d8
RK		 13675 "*
13676{
12a4e8c5 13677 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 13678}"
13679 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13680
13681(define_insn ""
13682 [(set (pc)
13683 (if_then_else (match_operator 0 "branch_comparison_operator"
13684 [(match_operand 1
b54cf83a 13685 "cc_reg_operand" "y")
1fd4e8c1
RK		 13686 (const_int 0)])
13687 (pc)
13688 (return)))]
13689 "direct_return ()"
12a4e8c5
GK		 13690 "*
13691{
13692 return output_cbranch (operands[0], NULL, 1, insn);
13693}"
b7ff3d82 13694 [(set_attr "type" "branch")
39a10a29
GK		 13695 (set_attr "length" "4")])
13696
13697;; Logic on condition register values.
13698
13699; This pattern matches things like
13700; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13701; (eq:SI (reg:CCFP 68) (const_int 0)))
13702; (const_int 1)))
13703; which are generated by the branch logic.
b54cf83a 13704; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29
GK		 13705
13706(define_insn ""
b54cf83a 13707 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13708 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 13709 [(match_operator:SI 2
39a10a29
GK		 13710 "branch_positive_comparison_operator"
13711 [(match_operand 3
b54cf83a 13712 "cc_reg_operand" "y,y")
39a10a29 13713 (const_int 0)])
b54cf83a 13714 (match_operator:SI 4
39a10a29
GK		 13715 "branch_positive_comparison_operator"
13716 [(match_operand 5
b54cf83a 13717 "cc_reg_operand" "0,y")
39a10a29
GK		 13718 (const_int 0)])])
13719 (const_int 1)))]
13720 ""
13721 "cr%q1 %E0,%j2,%j4"
b54cf83a 13722 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13723
13724; Why is the constant -1 here, but 1 in the previous pattern?
13725; Because ~1 has all but the low bit set.
13726(define_insn ""
b54cf83a 13727 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13728 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 13729 [(not:SI (match_operator:SI 2
39a10a29
GK		 13730 "branch_positive_comparison_operator"
13731 [(match_operand 3
b54cf83a 13732 "cc_reg_operand" "y,y")
39a10a29
GK		 13733 (const_int 0)]))
13734 (match_operator:SI 4
13735 "branch_positive_comparison_operator"
13736 [(match_operand 5
b54cf83a 13737 "cc_reg_operand" "0,y")
39a10a29
GK		 13738 (const_int 0)])])
13739 (const_int -1)))]
13740 ""
13741 "cr%q1 %E0,%j2,%j4"
b54cf83a 13742 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13743
13744(define_insn ""
b54cf83a 13745 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 13746 (compare:CCEQ (match_operator:SI 1
39a10a29 13747 "branch_positive_comparison_operator"
6c873122 13748 [(match_operand 2
b54cf83a 13749 "cc_reg_operand" "0,y")
39a10a29
GK		 13750 (const_int 0)])
13751 (const_int 0)))]
fe6b547a 13752 "!TARGET_SPE"
251b3667 13753 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 13754 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13755
13756;; If we are comparing the result of two comparisons, this can be done
13757;; using creqv or crxor.
13758
13759(define_insn_and_split ""
13760 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13761 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13762 [(match_operand 2 "cc_reg_operand" "y")
13763 (const_int 0)])
13764 (match_operator 3 "branch_comparison_operator"
13765 [(match_operand 4 "cc_reg_operand" "y")
13766 (const_int 0)])))]
13767 ""
13768 "#"
13769 ""
13770 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13771 (match_dup 5)))]
13772 "
13773{
13774 int positive_1, positive_2;
13775
13776 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13777 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13778
13779 if (! positive_1)
2d4368e6 13780 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]),
39a10a29 13781 GET_CODE (operands[1])),
2d4368e6
DE		 13782 SImode,
13783 operands[2], const0_rtx);
39a10a29 13784 else if (GET_MODE (operands[1]) != SImode)
2d4368e6
DE		 13785 operands[1] = gen_rtx (GET_CODE (operands[1]),
13786 SImode,
13787 operands[2], const0_rtx);
39a10a29
GK		 13788
13789 if (! positive_2)
2d4368e6 13790 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]),
39a10a29 13791 GET_CODE (operands[3])),
2d4368e6
DE		 13792 SImode,
13793 operands[4], const0_rtx);
39a10a29 13794 else if (GET_MODE (operands[3]) != SImode)
2d4368e6
DE		 13795 operands[3] = gen_rtx (GET_CODE (operands[3]),
13796 SImode,
13797 operands[4], const0_rtx);
39a10a29
GK		 13798
13799 if (positive_1 == positive_2)
251b3667
DE		 13800 {
13801 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13802 operands[5] = constm1_rtx;
13803 }
13804 else
13805 {
13806 operands[5] = const1_rtx;
13807 }
39a10a29 13808}")
1fd4e8c1
RK		 13809
13810;; Unconditional branch and return.
13811
13812(define_insn "jump"
13813 [(set (pc)
13814 (label_ref (match_operand 0 "" "")))]
13815 ""
b7ff3d82
DE		 13816 "b %l0"
13817 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13818
13819(define_insn "return"
13820 [(return)]
13821 "direct_return ()"
324e52cc
TG		 13822 "{br|blr}"
13823 [(set_attr "type" "jmpreg")])
1fd4e8c1 13824
0ad91047
DE		 13825(define_expand "indirect_jump"
13826 [(set (pc) (match_operand 0 "register_operand" ""))]
1fd4e8c1 13827 ""
0ad91047
DE		 13828 "
13829{
13830 if (TARGET_32BIT)
13831 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13832 else
13833 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13834 DONE;
13835}")
13836
13837(define_insn "indirect_jumpsi"
b92b324d 13838 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
0ad91047 13839 "TARGET_32BIT"
b92b324d
DE		 13840 "@
13841 bctr
13842 {br|blr}"
324e52cc 13843 [(set_attr "type" "jmpreg")])
1fd4e8c1 13844
0ad91047 13845(define_insn "indirect_jumpdi"
b92b324d 13846 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
0ad91047 13847 "TARGET_64BIT"
b92b324d
DE		 13848 "@
13849 bctr
13850 blr"
266eb58a
DE		 13851 [(set_attr "type" "jmpreg")])
13852
1fd4e8c1
RK		 13853;; Table jump for switch statements:
13854(define_expand "tablejump"
e6ca2c17
DE		 13855 [(use (match_operand 0 "" ""))
13856 (use (label_ref (match_operand 1 "" "")))]
13857 ""
13858 "
13859{
13860 if (TARGET_32BIT)
13861 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13862 else
13863 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13864 DONE;
13865}")
13866
13867(define_expand "tablejumpsi"
1fd4e8c1
RK		 13868 [(set (match_dup 3)
13869 (plus:SI (match_operand:SI 0 "" "")
13870 (match_dup 2)))
13871 (parallel [(set (pc) (match_dup 3))
13872 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 13873 "TARGET_32BIT"
1fd4e8c1
RK		 13874 "
13875{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 13876 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 13877 operands[3] = gen_reg_rtx (SImode);
13878}")
13879
e6ca2c17 13880(define_expand "tablejumpdi"
9ebbca7d
GK		 13881 [(set (match_dup 4)
13882 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13883 (set (match_dup 3)
13884 (plus:DI (match_dup 4)
e6ca2c17
DE		 13885 (match_dup 2)))
13886 (parallel [(set (pc) (match_dup 3))
13887 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 13888 "TARGET_64BIT"
e6ca2c17 13889 "
9ebbca7d 13890{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 13891 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 13892 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 13893}")
13894
1fd4e8c1
RK		 13895(define_insn ""
13896 [(set (pc)
c859cda6 13897 (match_operand:SI 0 "register_operand" "c,*l"))
1fd4e8c1 13898 (use (label_ref (match_operand 1 "" "")))]
0ad91047 13899 "TARGET_32BIT"
c859cda6
DJ		 13900 "@
13901 bctr
13902 {br|blr}"
a6845123 13903 [(set_attr "type" "jmpreg")])
1fd4e8c1 13904
266eb58a
DE		 13905(define_insn ""
13906 [(set (pc)
c859cda6 13907 (match_operand:DI 0 "register_operand" "c,*l"))
266eb58a 13908 (use (label_ref (match_operand 1 "" "")))]
0ad91047 13909 "TARGET_64BIT"
c859cda6
DJ		 13910 "@
13911 bctr
13912 blr"
266eb58a
DE		 13913 [(set_attr "type" "jmpreg")])
13914
1fd4e8c1
RK		 13915(define_insn "nop"
13916 [(const_int 0)]
13917 ""
ca7f5001 13918 "{cror 0,0,0|nop}")
1fd4e8c1 13919\f
7e69e155 13920;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 13921;; so loop.c knows what to generate.
13922
5527bf14
RH		 13923(define_expand "doloop_end"
13924 [(use (match_operand 0 "" "")) ; loop pseudo
13925 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13926 (use (match_operand 2 "" "")) ; max iterations
13927 (use (match_operand 3 "" "")) ; loop level
13928 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 13929 ""
13930 "
13931{
5527bf14
RH		 13932 /* Only use this on innermost loops. */
13933 if (INTVAL (operands[3]) > 1)
13934 FAIL;
683bdff7 13935 if (TARGET_64BIT)
5527bf14
RH		 13936 {
13937 if (GET_MODE (operands[0]) != DImode)
13938 FAIL;
13939 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13940 }
0ad91047 13941 else
5527bf14
RH		 13942 {
13943 if (GET_MODE (operands[0]) != SImode)
13944 FAIL;
13945 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13946 }
0ad91047
DE		 13947 DONE;
13948}")
13949
13950(define_expand "ctrsi"
3cb999d8
DE		 13951 [(parallel [(set (pc)
13952 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13953 (const_int 1))
13954 (label_ref (match_operand 1 "" ""))
13955 (pc)))
b6c9286a
MM		 13956 (set (match_dup 0)
13957 (plus:SI (match_dup 0)
13958 (const_int -1)))
5f81043f
RK		 13959 (clobber (match_scratch:CC 2 ""))
13960 (clobber (match_scratch:SI 3 ""))])]
683bdff7 13961 "TARGET_32BIT"
0ad91047
DE		 13962 "")
13963
13964(define_expand "ctrdi"
3cb999d8
DE		 13965 [(parallel [(set (pc)
13966 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13967 (const_int 1))
13968 (label_ref (match_operand 1 "" ""))
13969 (pc)))
0ad91047
DE		 13970 (set (match_dup 0)
13971 (plus:DI (match_dup 0)
13972 (const_int -1)))
13973 (clobber (match_scratch:CC 2 ""))
61c07d3c 13974 (clobber (match_scratch:DI 3 ""))])]
683bdff7 13975 "TARGET_64BIT"
61c07d3c 13976 "")
c225ba7b 13977
1fd4e8c1
RK		 13978;; We need to be able to do this for any operand, including MEM, or we
13979;; will cause reload to blow up since we don't allow output reloads on
7e69e155 13980;; JUMP_INSNs.
0ad91047 13981;; For the length attribute to be calculated correctly, the
5f81043f
RK		 13982;; label MUST be operand 0.
13983
0ad91047 13984(define_insn "*ctrsi_internal1"
1fd4e8c1 13985 [(set (pc)
43b68ce5 13986 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 13987 (const_int 1))
a6845123 13988 (label_ref (match_operand 0 "" ""))
1fd4e8c1 13989 (pc)))
43b68ce5 13990 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 13991 (plus:SI (match_dup 1)
13992 (const_int -1)))
43b68ce5
DE		 13993 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13994 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 13995 "TARGET_32BIT"
b19003d8
RK		 13996 "*
13997{
af87a13e 13998 if (which_alternative != 0)
b19003d8 13999 return \"#\";
856a6884 14000 else if (get_attr_length (insn) == 4)
a6845123 14001 return \"{bdn|bdnz} %l0\";
b19003d8 14002 else
f607bc57 14003 return \"bdz $+8\;b %l0\";
b19003d8 14004}"
baf97f86 14005 [(set_attr "type" "branch")
5a195cb5 14006 (set_attr "length" "*,12,16,16")])
7e69e155 14007
0ad91047 14008(define_insn "*ctrsi_internal2"
5f81043f 14009 [(set (pc)
43b68ce5 14010 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
5f81043f
RK		 14011 (const_int 1))
14012 (pc)
14013 (label_ref (match_operand 0 "" ""))))
43b68ce5 14014 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 14015 (plus:SI (match_dup 1)
14016 (const_int -1)))
43b68ce5
DE		 14017 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14018 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 14019 "TARGET_32BIT"
0ad91047
DE		 14020 "*
14021{
14022 if (which_alternative != 0)
14023 return \"#\";
856a6884 14024 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14025 return \"bdz %l0\";
14026 else
f607bc57 14027 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14028}"
14029 [(set_attr "type" "branch")
5a195cb5 14030 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 14031
14032(define_insn "*ctrdi_internal1"
14033 [(set (pc)
43b68ce5 14034 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14035 (const_int 1))
14036 (label_ref (match_operand 0 "" ""))
14037 (pc)))
43b68ce5 14038 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 14039 (plus:DI (match_dup 1)
14040 (const_int -1)))
43b68ce5
DE		 14041 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14042 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 14043 "TARGET_64BIT"
0ad91047
DE		 14044 "*
14045{
14046 if (which_alternative != 0)
14047 return \"#\";
856a6884 14048 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14049 return \"{bdn|bdnz} %l0\";
14050 else
f607bc57 14051 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14052}"
14053 [(set_attr "type" "branch")
5a195cb5 14054 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 14055
14056(define_insn "*ctrdi_internal2"
14057 [(set (pc)
43b68ce5 14058 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14059 (const_int 1))
14060 (pc)
14061 (label_ref (match_operand 0 "" ""))))
43b68ce5 14062 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 14063 (plus:DI (match_dup 1)
14064 (const_int -1)))
43b68ce5
DE		 14065 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14066 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 14067 "TARGET_64BIT"
5f81043f
RK		 14068 "*
14069{
14070 if (which_alternative != 0)
14071 return \"#\";
856a6884 14072 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14073 return \"bdz %l0\";
14074 else
f607bc57 14075 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14076}"
14077 [(set_attr "type" "branch")
5a195cb5 14078 (set_attr "length" "*,12,16,16")])
5f81043f 14079
c225ba7b 14080;; Similar, but we can use GE since we have a REG_NONNEG.
0ad91047
DE		 14081
14082(define_insn "*ctrsi_internal3"
1fd4e8c1 14083 [(set (pc)
43b68ce5 14084 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14085 (const_int 0))
a6845123 14086 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14087 (pc)))
43b68ce5 14088 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 14089 (plus:SI (match_dup 1)
14090 (const_int -1)))
43b68ce5
DE		 14091 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14092 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 14093 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
b19003d8
RK		 14094 "*
14095{
af87a13e 14096 if (which_alternative != 0)
b19003d8 14097 return \"#\";
856a6884 14098 else if (get_attr_length (insn) == 4)
a6845123 14099 return \"{bdn|bdnz} %l0\";
b19003d8 14100 else
f607bc57 14101 return \"bdz $+8\;b %l0\";
b19003d8 14102}"
baf97f86 14103 [(set_attr "type" "branch")
5a195cb5 14104 (set_attr "length" "*,12,16,16")])
7e69e155 14105
0ad91047 14106(define_insn "*ctrsi_internal4"
1fd4e8c1 14107 [(set (pc)
43b68ce5 14108 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
5f81043f
RK		 14109 (const_int 0))
14110 (pc)
14111 (label_ref (match_operand 0 "" ""))))
43b68ce5 14112 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 14113 (plus:SI (match_dup 1)
14114 (const_int -1)))
43b68ce5
DE		 14115 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14116 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 14117 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
5f81043f
RK		 14118 "*
14119{
14120 if (which_alternative != 0)
14121 return \"#\";
856a6884 14122 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14123 return \"bdz %l0\";
14124 else
f607bc57 14125 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14126}"
14127 [(set_attr "type" "branch")
5a195cb5 14128 (set_attr "length" "*,12,16,16")])
5f81043f 14129
0ad91047
DE		 14130(define_insn "*ctrdi_internal3"
14131 [(set (pc)
43b68ce5 14132 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14133 (const_int 0))
14134 (label_ref (match_operand 0 "" ""))
14135 (pc)))
43b68ce5 14136 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 14137 (plus:DI (match_dup 1)
14138 (const_int -1)))
43b68ce5
DE		 14139 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14140 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 14141 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
0ad91047
DE		 14142 "*
14143{
14144 if (which_alternative != 0)
14145 return \"#\";
856a6884 14146 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14147 return \"{bdn|bdnz} %l0\";
14148 else
f607bc57 14149 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14150}"
14151 [(set_attr "type" "branch")
5a195cb5 14152 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 14153
14154(define_insn "*ctrdi_internal4"
14155 [(set (pc)
43b68ce5 14156 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14157 (const_int 0))
14158 (pc)
14159 (label_ref (match_operand 0 "" ""))))
43b68ce5 14160 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 14161 (plus:DI (match_dup 1)
14162 (const_int -1)))
43b68ce5
DE		 14163 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14164 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 14165 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
0ad91047
DE		 14166 "*
14167{
14168 if (which_alternative != 0)
14169 return \"#\";
856a6884 14170 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14171 return \"bdz %l0\";
14172 else
f607bc57 14173 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14174}"
14175 [(set_attr "type" "branch")
5a195cb5 14176 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 14177
14178;; Similar but use EQ
14179
14180(define_insn "*ctrsi_internal5"
5f81043f 14181 [(set (pc)
43b68ce5 14182 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14183 (const_int 1))
a6845123 14184 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14185 (pc)))
43b68ce5 14186 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 14187 (plus:SI (match_dup 1)
14188 (const_int -1)))
43b68ce5
DE		 14189 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14190 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 14191 "TARGET_32BIT"
b19003d8
RK		 14192 "*
14193{
af87a13e 14194 if (which_alternative != 0)
b19003d8 14195 return \"#\";
856a6884 14196 else if (get_attr_length (insn) == 4)
a6845123 14197 return \"bdz %l0\";
b19003d8 14198 else
f607bc57 14199 return \"{bdn|bdnz} $+8\;b %l0\";
b19003d8 14200}"
baf97f86 14201 [(set_attr "type" "branch")
5a195cb5 14202 (set_attr "length" "*,12,16,16")])
1fd4e8c1 14203
0ad91047 14204(define_insn "*ctrsi_internal6"
5f81043f 14205 [(set (pc)
43b68ce5 14206 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
5f81043f
RK		 14207 (const_int 1))
14208 (pc)
14209 (label_ref (match_operand 0 "" ""))))
43b68ce5 14210 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 14211 (plus:SI (match_dup 1)
14212 (const_int -1)))
43b68ce5
DE		 14213 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14214 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 14215 "TARGET_32BIT"
0ad91047
DE		 14216 "*
14217{
14218 if (which_alternative != 0)
14219 return \"#\";
856a6884 14220 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14221 return \"{bdn|bdnz} %l0\";
14222 else
f607bc57 14223 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14224}"
14225 [(set_attr "type" "branch")
5a195cb5 14226 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 14227
14228(define_insn "*ctrdi_internal5"
14229 [(set (pc)
43b68ce5 14230 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14231 (const_int 1))
14232 (label_ref (match_operand 0 "" ""))
14233 (pc)))
43b68ce5 14234 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 14235 (plus:DI (match_dup 1)
14236 (const_int -1)))
43b68ce5
DE		 14237 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14238 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 14239 "TARGET_64BIT"
0ad91047
DE		 14240 "*
14241{
14242 if (which_alternative != 0)
14243 return \"#\";
856a6884 14244 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14245 return \"bdz %l0\";
14246 else
f607bc57 14247 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14248}"
14249 [(set_attr "type" "branch")
5a195cb5 14250 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 14251
14252(define_insn "*ctrdi_internal6"
14253 [(set (pc)
43b68ce5 14254 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14255 (const_int 1))
14256 (pc)
14257 (label_ref (match_operand 0 "" ""))))
43b68ce5 14258 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 14259 (plus:DI (match_dup 1)
14260 (const_int -1)))
43b68ce5
DE		 14261 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14262 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 14263 "TARGET_64BIT"
5f81043f
RK		 14264 "*
14265{
14266 if (which_alternative != 0)
14267 return \"#\";
856a6884 14268 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14269 return \"{bdn|bdnz} %l0\";
14270 else
f607bc57 14271 return \"bdz $+8\;b %l0\";
5f81043f
RK		 14272}"
14273 [(set_attr "type" "branch")
5a195cb5 14274 (set_attr "length" "*,12,16,16")])
5f81043f 14275
0ad91047
DE		 14276;; Now the splitters if we could not allocate the CTR register
14277
1fd4e8c1
RK		 14278(define_split
14279 [(set (pc)
14280 (if_then_else (match_operator 2 "comparison_operator"
cd2b37d9 14281 [(match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 14282 (const_int 1)])
14283 (match_operand 5 "" "")
14284 (match_operand 6 "" "")))
cd2b37d9 14285 (set (match_operand:SI 0 "gpc_reg_operand" "")
5f81043f
RK		 14286 (plus:SI (match_dup 1)
14287 (const_int -1)))
1fd4e8c1
RK		 14288 (clobber (match_scratch:CC 3 ""))
14289 (clobber (match_scratch:SI 4 ""))]
0ad91047 14290 "! TARGET_POWERPC64 && reload_completed"
1fd4e8c1 14291 [(parallel [(set (match_dup 3)
5f81043f
RK		 14292 (compare:CC (plus:SI (match_dup 1)
14293 (const_int -1))
1fd4e8c1 14294 (const_int 0)))
5f81043f
RK		 14295 (set (match_dup 0)
14296 (plus:SI (match_dup 1)
14297 (const_int -1)))])
14298 (set (pc) (if_then_else (match_dup 7)
14299 (match_dup 5)
14300 (match_dup 6)))]
1fd4e8c1
RK		 14301 "
14302{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14303 const0_rtx); }")
14304
14305(define_split
14306 [(set (pc)
14307 (if_then_else (match_operator 2 "comparison_operator"
cd2b37d9 14308 [(match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 14309 (const_int 1)])
14310 (match_operand 5 "" "")
14311 (match_operand 6 "" "")))
9ebbca7d 14312 (set (match_operand:SI 0 "nonimmediate_operand" "")
1fd4e8c1
RK		 14313 (plus:SI (match_dup 1) (const_int -1)))
14314 (clobber (match_scratch:CC 3 ""))
14315 (clobber (match_scratch:SI 4 ""))]
0ad91047
DE		 14316 "! TARGET_POWERPC64 && reload_completed
14317 && ! gpc_reg_operand (operands[0], SImode)"
1fd4e8c1 14318 [(parallel [(set (match_dup 3)
5f81043f
RK		 14319 (compare:CC (plus:SI (match_dup 1)
14320 (const_int -1))
1fd4e8c1 14321 (const_int 0)))
5f81043f
RK		 14322 (set (match_dup 4)
14323 (plus:SI (match_dup 1)
14324 (const_int -1)))])
14325 (set (match_dup 0)
14326 (match_dup 4))
14327 (set (pc) (if_then_else (match_dup 7)
14328 (match_dup 5)
14329 (match_dup 6)))]
1fd4e8c1
RK		 14330 "
14331{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14332 const0_rtx); }")
0ad91047
DE		 14333(define_split
14334 [(set (pc)
14335 (if_then_else (match_operator 2 "comparison_operator"
14336 [(match_operand:DI 1 "gpc_reg_operand" "")
14337 (const_int 1)])
61c07d3c
DE		 14338 (match_operand 5 "" "")
14339 (match_operand 6 "" "")))
0ad91047
DE		 14340 (set (match_operand:DI 0 "gpc_reg_operand" "")
14341 (plus:DI (match_dup 1)
14342 (const_int -1)))
14343 (clobber (match_scratch:CC 3 ""))
61c07d3c 14344 (clobber (match_scratch:DI 4 ""))]
683bdff7 14345 "TARGET_64BIT && reload_completed"
0ad91047
DE		 14346 [(parallel [(set (match_dup 3)
14347 (compare:CC (plus:DI (match_dup 1)
14348 (const_int -1))
14349 (const_int 0)))
14350 (set (match_dup 0)
14351 (plus:DI (match_dup 1)
14352 (const_int -1)))])
61c07d3c
DE		 14353 (set (pc) (if_then_else (match_dup 7)
14354 (match_dup 5)
14355 (match_dup 6)))]
0ad91047 14356 "
61c07d3c 14357{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
0ad91047
DE		 14358 const0_rtx); }")
14359
14360(define_split
14361 [(set (pc)
14362 (if_then_else (match_operator 2 "comparison_operator"
14363 [(match_operand:DI 1 "gpc_reg_operand" "")
14364 (const_int 1)])
61c07d3c
DE		 14365 (match_operand 5 "" "")
14366 (match_operand 6 "" "")))
9ebbca7d 14367 (set (match_operand:DI 0 "nonimmediate_operand" "")
0ad91047
DE		 14368 (plus:DI (match_dup 1) (const_int -1)))
14369 (clobber (match_scratch:CC 3 ""))
61c07d3c 14370 (clobber (match_scratch:DI 4 ""))]
683bdff7 14371 "TARGET_64BIT && reload_completed
0ad91047
DE		 14372 && ! gpc_reg_operand (operands[0], DImode)"
14373 [(parallel [(set (match_dup 3)
14374 (compare:CC (plus:DI (match_dup 1)
14375 (const_int -1))
14376 (const_int 0)))
14377 (set (match_dup 4)
14378 (plus:DI (match_dup 1)
14379 (const_int -1)))])
14380 (set (match_dup 0)
14381 (match_dup 4))
61c07d3c
DE		 14382 (set (pc) (if_then_else (match_dup 7)
14383 (match_dup 5)
14384 (match_dup 6)))]
0ad91047 14385 "
61c07d3c 14386{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
0ad91047 14387 const0_rtx); }")
c94ccb87 14388
683bdff7
FJ		 14389; These two are for 64-bit hardware running 32-bit mode.
14390; We don't use the add. instruction in this mode.
14391(define_split
14392 [(set (pc)
14393 (if_then_else (match_operator 2 "comparison_operator"
14394 [(match_operand:SI 1 "gpc_reg_operand" "")
14395 (const_int 1)])
14396 (match_operand 5 "" "")
14397 (match_operand 6 "" "")))
14398 (set (match_operand:SI 0 "gpc_reg_operand" "")
14399 (plus:SI (match_dup 1)
14400 (const_int -1)))
14401 (clobber (match_scratch:CC 3 ""))
14402 (clobber (match_scratch:SI 4 ""))]
14403 "TARGET_POWERPC64 && TARGET_32BIT && reload_completed"
14404 [(set (match_dup 0)
14405 (plus:SI (match_dup 1)
14406 (const_int -1)))
14407 (set (match_dup 3)
14408 (compare:CC (match_dup 0)
14409 (const_int 0)))
14410 (set (pc) (if_then_else (match_dup 7)
14411 (match_dup 5)
14412 (match_dup 6)))]
14413 "
14414{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14415 const0_rtx); }")
14416
14417(define_split
14418 [(set (pc)
14419 (if_then_else (match_operator 2 "comparison_operator"
14420 [(match_operand:SI 1 "gpc_reg_operand" "")
14421 (const_int 1)])
14422 (match_operand 5 "" "")
14423 (match_operand 6 "" "")))
14424 (set (match_operand:SI 0 "nonimmediate_operand" "")
14425 (plus:SI (match_dup 1) (const_int -1)))
14426 (clobber (match_scratch:CC 3 ""))
14427 (clobber (match_scratch:SI 4 ""))]
14428 "TARGET_POWERPC64 && TARGET_32BIT && reload_completed
14429 && ! gpc_reg_operand (operands[0], SImode)"
14430 [(set (match_dup 4)
14431 (plus:SI (match_dup 1)
14432 (const_int -1)))
14433 (set (match_dup 3)
14434 (compare:CC (match_dup 4)
14435 (const_int 0)))
14436 (set (match_dup 0)
14437 (match_dup 4))
14438 (set (pc) (if_then_else (match_dup 7)
14439 (match_dup 5)
14440 (match_dup 6)))]
14441 "
14442{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14443 const0_rtx); }")
14444
e0cd0770
JC		 14445\f
14446(define_insn "trap"
14447 [(trap_if (const_int 1) (const_int 0))]
14448 ""
14449 "{t 31,0,0|trap}")
14450
14451(define_expand "conditional_trap"
14452 [(trap_if (match_operator 0 "trap_comparison_operator"
14453 [(match_dup 2) (match_dup 3)])
14454 (match_operand 1 "const_int_operand" ""))]
14455 ""
14456 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14457 operands[2] = rs6000_compare_op0;
14458 operands[3] = rs6000_compare_op1;")
14459
14460(define_insn ""
14461 [(trap_if (match_operator 0 "trap_comparison_operator"
14462 [(match_operand:SI 1 "register_operand" "r")
14463 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14464 (const_int 0))]
14465 ""
a157febd
GK		 14466 "{t|tw}%V0%I2 %1,%2")
14467
14468(define_insn ""
14469 [(trap_if (match_operator 0 "trap_comparison_operator"
14470 [(match_operand:DI 1 "register_operand" "r")
14471 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14472 (const_int 0))]
14473 "TARGET_POWERPC64"
14474 "td%V0%I2 %1,%2")
9ebbca7d
GK		 14475\f
14476;; Insns related to generating the function prologue and epilogue.
14477
14478(define_expand "prologue"
14479 [(use (const_int 0))]
14480 "TARGET_SCHED_PROLOG"
14481 "
14482{
14483 rs6000_emit_prologue ();
14484 DONE;
14485}")
14486
2c4a9cff
DE		 14487(define_insn "*movesi_from_cr_one"
14488 [(match_parallel 0 "mfcr_operation"
14489 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14490 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14491 (match_operand 3 "immediate_operand" "n")]
14492 UNSPEC_MOVESI_FROM_CR))])]
14493 "TARGET_MFCRF"
14494 "*
14495{
14496 int mask = 0;
14497 int i;
14498 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14499 {
14500 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14501 operands[4] = GEN_INT (mask);
14502 output_asm_insn (\"mfcr %1,%4\", operands);
14503 }
14504 return \"\";
14505}"
14506 [(set_attr "type" "mfcrf")])
14507
9ebbca7d
GK		 14508(define_insn "movesi_from_cr"
14509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14510 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
615158e2
JJ		 14511 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14512 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 14513 ""
309323c2 14514 "mfcr %0"
b54cf83a 14515 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14516
14517(define_insn "*stmw"
e033a023
DE		 14518 [(match_parallel 0 "stmw_operation"
14519 [(set (match_operand:SI 1 "memory_operand" "=m")
14520 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14521 "TARGET_MULTIPLE"
14522 "{stm|stmw} %2,%1")
9ebbca7d
GK		 14523
14524(define_insn "*save_fpregs_si"
e033a023
DE		 14525 [(match_parallel 0 "any_operand"
14526 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14527 (use (match_operand:SI 2 "call_operand" "s"))
14528 (set (match_operand:DF 3 "memory_operand" "=m")
14529 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14530 "TARGET_32BIT"
14531 "bl %z2"
14532 [(set_attr "type" "branch")
14533 (set_attr "length" "4")])
9ebbca7d
GK		 14534
14535(define_insn "*save_fpregs_di"
e033a023
DE		 14536 [(match_parallel 0 "any_operand"
14537 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14538 (use (match_operand:DI 2 "call_operand" "s"))
14539 (set (match_operand:DF 3 "memory_operand" "=m")
14540 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14541 "TARGET_64BIT"
14542 "bl %z2"
14543 [(set_attr "type" "branch")
14544 (set_attr "length" "4")])
9ebbca7d
GK		 14545
14546; These are to explain that changes to the stack pointer should
14547; not be moved over stores to stack memory.
14548(define_insn "stack_tie"
14549 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 14550 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 14551 ""
14552 ""
14553 [(set_attr "length" "0")])
14554
14555
14556(define_expand "epilogue"
14557 [(use (const_int 0))]
14558 "TARGET_SCHED_PROLOG"
14559 "
14560{
14561 rs6000_emit_epilogue (FALSE);
14562 DONE;
14563}")
14564
14565; On some processors, doing the mtcrf one CC register at a time is
14566; faster (like on the 604e). On others, doing them all at once is
14567; faster; for instance, on the 601 and 750.
14568
14569(define_expand "movsi_to_cr_one"
35aba846
DE		 14570 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14571 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2 14572 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 14573 ""
14574 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14575
14576(define_insn "*movsi_to_cr"
35aba846
DE		 14577 [(match_parallel 0 "mtcrf_operation"
14578 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14579 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14580 (match_operand 3 "immediate_operand" "n")]
615158e2 14581 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 14582 ""
e35b9579
GK		 14583 "*
14584{
14585 int mask = 0;
14586 int i;
14587 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14588 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14589 operands[4] = GEN_INT (mask);
14590 return \"mtcrf %4,%2\";
309323c2 14591}"
b54cf83a 14592 [(set_attr "type" "mtcr")])
9ebbca7d 14593
b54cf83a 14594(define_insn "*mtcrfsi"
309323c2
DE		 14595 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14596 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 14597 (match_operand 2 "immediate_operand" "n")]
14598 UNSPEC_MOVESI_TO_CR))]
309323c2
DE		 14599 "GET_CODE (operands[0]) == REG
14600 && CR_REGNO_P (REGNO (operands[0]))
14601 && GET_CODE (operands[2]) == CONST_INT
14602 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14603 "mtcrf %R0,%1"
b54cf83a 14604 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14605
14606; The load-multiple instructions have similar properties.
14607; Note that "load_multiple" is a name known to the machine-independent
14608; code that actually corresponds to the powerpc load-string.
14609
14610(define_insn "*lmw"
35aba846
DE		 14611 [(match_parallel 0 "lmw_operation"
14612 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14613 (match_operand:SI 2 "memory_operand" "m"))])]
14614 "TARGET_MULTIPLE"
14615 "{lm|lmw} %1,%2")
9ebbca7d
GK		 14616
14617(define_insn "*return_internal_si"
e35b9579
GK		 14618 [(return)
14619 (use (match_operand:SI 0 "register_operand" "lc"))]
9ebbca7d 14620 "TARGET_32BIT"
cccf3bdc 14621 "b%T0"
9ebbca7d
GK		 14622 [(set_attr "type" "jmpreg")])
14623
14624(define_insn "*return_internal_di"
e35b9579
GK		 14625 [(return)
14626 (use (match_operand:DI 0 "register_operand" "lc"))]
9ebbca7d 14627 "TARGET_64BIT"
cccf3bdc 14628 "b%T0"
9ebbca7d
GK		 14629 [(set_attr "type" "jmpreg")])
14630
14631; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14632; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14633
14634(define_insn "*return_and_restore_fpregs_si"
14635 [(match_parallel 0 "any_operand"
e35b9579
GK		 14636 [(return)
14637 (use (match_operand:SI 1 "register_operand" "l"))
9ebbca7d
GK		 14638 (use (match_operand:SI 2 "call_operand" "s"))
14639 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14640 (match_operand:DF 4 "memory_operand" "m"))])]
14641 "TARGET_32BIT"
14642 "b %z2")
14643
14644(define_insn "*return_and_restore_fpregs_di"
14645 [(match_parallel 0 "any_operand"
e35b9579
GK		 14646 [(return)
14647 (use (match_operand:DI 1 "register_operand" "l"))
9ebbca7d
GK		 14648 (use (match_operand:DI 2 "call_operand" "s"))
14649 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14650 (match_operand:DF 4 "memory_operand" "m"))])]
14651 "TARGET_64BIT"
14652 "b %z2")
14653
83720594
RH		 14654; This is used in compiling the unwind routines.
14655(define_expand "eh_return"
34dc173c 14656 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 14657 ""
14658 "
14659{
83720594 14660 if (TARGET_32BIT)
34dc173c 14661 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 14662 else
34dc173c 14663 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 14664 DONE;
14665}")
14666
83720594
RH		 14667; We can't expand this before we know where the link register is stored.
14668(define_insn "eh_set_lr_si"
615158e2
JJ		 14669 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14670 UNSPECV_EH_RR)
466eb3e0 14671 (clobber (match_scratch:SI 1 "=&b"))]
83720594
RH		 14672 "TARGET_32BIT"
14673 "#")
14674
14675(define_insn "eh_set_lr_di"
615158e2
JJ		 14676 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14677 UNSPECV_EH_RR)
466eb3e0 14678 (clobber (match_scratch:DI 1 "=&b"))]
83720594
RH		 14679 "TARGET_64BIT"
14680 "#")
9ebbca7d
GK		 14681
14682(define_split
615158e2 14683 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 14684 (clobber (match_scratch 1 ""))]
14685 "reload_completed"
14686 [(const_int 0)]
9ebbca7d
GK		 14687 "
14688{
d1d0c603 14689 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 14690 DONE;
14691}")
0ac081f6 14692
01a2ccd0
DE		 14693(define_insn "prefetch"
14694 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
6041bf2f
DE		 14695 (match_operand:SI 1 "const_int_operand" "n")
14696 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14697 "TARGET_POWERPC"
6041bf2f
DE		 14698 "*
14699{
01a2ccd0
DE		 14700 if (GET_CODE (operands[0]) == REG)
14701 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14702 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14703}"
14704 [(set_attr "type" "load")])
a3170dc6 14705
10ed84db 14706(include "altivec.md")
a3170dc6 14707(include "spe.md")
Mirror of https://gcc.gnu.org/git/gcc.git