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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
9ebbca7d GK |
2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | ;; 1999, 2000 Free Software Foundation, Inc. | |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
5 | |
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d GK |
24 | |
25 | ;; `unspec' values used in rs6000.md: | |
26 | ;; Number Use | |
27 | ;; 0 frsp for POWER machines | |
28 | ;; 0/v blockage | |
29 | ;; 5 used to tie the stack contents and the stack pointer | |
30 | ;; 6 address of a word pointing to the TOC | |
31 | ;; 7 address of the TOC (more-or-less) | |
32 | ;; 8 movsi_got | |
33 | ;; 9/v eh_reg_restore | |
34 | ;; 10 fctiwz | |
35 | ;; 19 movesi_from_cr | |
36 | ;; 20 movesi_to_cr | |
1fd4e8c1 RK |
37 | \f |
38 | ;; Define an insn type attribute. This is used in function unit delay | |
39 | ;; computations. | |
39a10a29 | 40 | (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" |
1fd4e8c1 RK |
41 | (const_string "integer")) |
42 | ||
b19003d8 | 43 | ;; Length (in bytes). |
6cbadf36 GK |
44 | ; '(pc)' in the following doesn't include the instruction itself; it is |
45 | ; calculated as if the instruction had zero size. | |
b19003d8 RK |
46 | (define_attr "length" "" |
47 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 48 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 49 | (const_int -32768)) |
6cbadf36 GK |
50 | (lt (minus (match_dup 0) (pc)) |
51 | (const_int 32764))) | |
39a10a29 GK |
52 | (const_int 4) |
53 | (const_int 8)) | |
b19003d8 RK |
54 | (const_int 4))) |
55 | ||
cfb557c4 RK |
56 | ;; Processor type -- this attribute must exactly match the processor_type |
57 | ;; enumeration in rs6000.h. | |
58 | ||
3cb999d8 | 59 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750" |
cfb557c4 RK |
60 | (const (symbol_ref "rs6000_cpu_attr"))) |
61 | ||
62 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
63 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
64 | ||
b7ff3d82 | 65 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 66 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
67 | (define_function_unit "lsu" 1 0 |
68 | (and (eq_attr "type" "load") | |
3cb999d8 | 69 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 70 | 2 1) |
cfb557c4 RK |
71 | |
72 | (define_function_unit "lsu" 1 0 | |
b7ff3d82 | 73 | (and (eq_attr "type" "store,fpstore") |
3cb999d8 | 74 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 75 | 1 1) |
b6c9286a MM |
76 | |
77 | (define_function_unit "lsu" 1 0 | |
78 | (and (eq_attr "type" "fpload") | |
bef84347 | 79 | (eq_attr "cpu" "mpccore,ppc603,ppc750")) |
b6c9286a | 80 | 2 1) |
cfb557c4 | 81 | |
b7ff3d82 DE |
82 | (define_function_unit "lsu" 1 0 |
83 | (and (eq_attr "type" "fpload") | |
3cb999d8 | 84 | (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 DE |
85 | 3 1) |
86 | ||
cfb557c4 RK |
87 | (define_function_unit "iu" 1 0 |
88 | (and (eq_attr "type" "load") | |
b7ff3d82 | 89 | (eq_attr "cpu" "rios1,ppc403,ppc601")) |
b6c9286a | 90 | 2 1) |
cfb557c4 RK |
91 | |
92 | (define_function_unit "iu" 1 0 | |
b7ff3d82 DE |
93 | (and (eq_attr "type" "store,fpstore") |
94 | (eq_attr "cpu" "rios1,ppc403,ppc601")) | |
95 | 1 1) | |
96 | ||
97 | (define_function_unit "fpu" 1 0 | |
98 | (and (eq_attr "type" "fpstore") | |
3624a679 | 99 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 100 | 0 1) |
cfb557c4 | 101 | |
49a0b204 | 102 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 103 | (and (eq_attr "type" "fpload") |
b6c9286a | 104 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
105 | 2 1) |
106 | ||
107 | (define_function_unit "iu" 1 0 | |
108 | (and (eq_attr "type" "fpload") | |
109 | (eq_attr "cpu" "ppc601")) | |
110 | 3 1) | |
111 | ||
112 | (define_function_unit "iu2" 2 0 | |
113 | (and (eq_attr "type" "load,fpload") | |
114 | (eq_attr "cpu" "rios2")) | |
115 | 2 1) | |
116 | ||
117 | (define_function_unit "iu2" 2 0 | |
118 | (and (eq_attr "type" "store,fpstore") | |
119 | (eq_attr "cpu" "rios2")) | |
120 | 1 1) | |
121 | ||
3cb999d8 | 122 | ; Integer Unit (RIOS1, PPC601, PPC603, RS64a) |
b7ff3d82 DE |
123 | (define_function_unit "iu" 1 0 |
124 | (and (eq_attr "type" "integer") | |
3cb999d8 | 125 | (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603")) |
b7ff3d82 | 126 | 1 1) |
49a0b204 | 127 | |
39a10a29 GK |
128 | (define_function_unit "iu" 1 0 |
129 | (and (eq_attr "type" "cr_logical") | |
5638268e | 130 | (eq_attr "cpu" "mpccore,ppc403,ppc601")) |
39a10a29 GK |
131 | 1 1) |
132 | ||
da0ae67f MM |
133 | (define_function_unit "iu" 1 0 |
134 | (and (eq_attr "type" "imul") | |
135 | (eq_attr "cpu" "ppc403")) | |
136 | 4 4) | |
137 | ||
cfb557c4 RK |
138 | (define_function_unit "iu" 1 0 |
139 | (and (eq_attr "type" "imul") | |
b7ff3d82 | 140 | (eq_attr "cpu" "rios1,ppc601,ppc603")) |
51b8fc2c | 141 | 5 5) |
cfb557c4 | 142 | |
3cb999d8 DE |
143 | (define_function_unit "iu" 1 0 |
144 | (and (eq_attr "type" "imul") | |
145 | (eq_attr "cpu" "rs64a")) | |
146 | 20 14) | |
147 | ||
148 | (define_function_unit "iu" 1 0 | |
149 | (and (eq_attr "type" "lmul") | |
150 | (eq_attr "cpu" "rs64a")) | |
151 | 34 34) | |
152 | ||
cfb557c4 RK |
153 | (define_function_unit "iu" 1 0 |
154 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 155 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 156 | 19 19) |
cfb557c4 | 157 | |
3cb999d8 DE |
158 | (define_function_unit "iu" 1 0 |
159 | (and (eq_attr "type" "idiv") | |
160 | (eq_attr "cpu" "rs64a")) | |
161 | 66 66) | |
162 | ||
163 | (define_function_unit "iu" 1 0 | |
164 | (and (eq_attr "type" "ldiv") | |
165 | (eq_attr "cpu" "rs64a")) | |
166 | 66 66) | |
167 | ||
cfb557c4 RK |
168 | (define_function_unit "iu" 1 0 |
169 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
170 | (eq_attr "cpu" "ppc403")) |
171 | 33 33) | |
51b8fc2c | 172 | |
da0ae67f MM |
173 | (define_function_unit "iu" 1 0 |
174 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
175 | (eq_attr "cpu" "ppc601")) |
176 | 36 36) | |
da0ae67f | 177 | |
51b8fc2c RK |
178 | (define_function_unit "iu" 1 0 |
179 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 180 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
181 | 37 36) |
182 | ||
183 | ; RIOS2 has two integer units: a primary one which can perform all | |
184 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
185 | ; and can perform "simple" integer operations. |
186 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
187 | ; for the complex insns. | |
51b8fc2c RK |
188 | (define_function_unit "iu2" 2 0 |
189 | (and (eq_attr "type" "integer") | |
190 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 191 | 1 1) |
b6c9286a MM |
192 | |
193 | (define_function_unit "iu2" 2 0 | |
194 | (and (eq_attr "type" "imul") | |
195 | (eq_attr "cpu" "rios2")) | |
196 | 2 2) | |
197 | ||
198 | (define_function_unit "iu2" 2 0 | |
199 | (and (eq_attr "type" "idiv") | |
200 | (eq_attr "cpu" "rios2")) | |
201 | 13 13) | |
51b8fc2c RK |
202 | |
203 | (define_function_unit "imuldiv" 1 0 | |
204 | (and (eq_attr "type" "imul") | |
205 | (eq_attr "cpu" "rios2")) | |
b6c9286a MM |
206 | 2 2) |
207 | ||
51b8fc2c RK |
208 | (define_function_unit "imuldiv" 1 0 |
209 | (and (eq_attr "type" "idiv") | |
210 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 211 | 13 13) |
51b8fc2c | 212 | |
cf27b467 MM |
213 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
214 | ; Divide latency varies greatly from 2-11, use 6 as average | |
215 | (define_function_unit "imuldiv" 1 0 | |
216 | (and (eq_attr "type" "imul") | |
217 | (eq_attr "cpu" "mpccore")) | |
218 | 2 1) | |
219 | ||
220 | (define_function_unit "imuldiv" 1 0 | |
221 | (and (eq_attr "type" "idiv") | |
222 | (eq_attr "cpu" "mpccore")) | |
223 | 6 6) | |
224 | ||
cac8ce95 | 225 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
226 | ; and one unit for divide/multiply operations (and move |
227 | ; from/to spr). | |
228 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 229 | (and (eq_attr "type" "integer") |
3cb999d8 | 230 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 231 | 1 1) |
51b8fc2c RK |
232 | |
233 | (define_function_unit "imuldiv" 1 0 | |
234 | (and (eq_attr "type" "imul") | |
3cb999d8 | 235 | (eq_attr "cpu" "ppc604")) |
b7ff3d82 | 236 | 4 2) |
51b8fc2c | 237 | |
3cb999d8 DE |
238 | (define_function_unit "imuldiv" 1 0 |
239 | (and (eq_attr "type" "imul") | |
240 | (eq_attr "cpu" "ppc620,ppc630")) | |
241 | 5 3) | |
242 | ||
243 | (define_function_unit "imuldiv" 1 0 | |
244 | (and (eq_attr "type" "lmul") | |
245 | (eq_attr "cpu" "ppc620,ppc630")) | |
246 | 5 3) | |
247 | ||
cac8ce95 DE |
248 | (define_function_unit "imuldiv" 1 0 |
249 | (and (eq_attr "type" "imul") | |
250 | (eq_attr "cpu" "ppc604e")) | |
251 | 2 1) | |
252 | ||
51b8fc2c RK |
253 | (define_function_unit "imuldiv" 1 0 |
254 | (and (eq_attr "type" "idiv") | |
3cb999d8 | 255 | (eq_attr "cpu" "ppc604,ppc604e")) |
b7ff3d82 | 256 | 20 19) |
cfb557c4 | 257 | |
3cb999d8 DE |
258 | (define_function_unit "imuldiv" 1 0 |
259 | (and (eq_attr "type" "idiv") | |
260 | (eq_attr "cpu" "ppc620")) | |
261 | 37 36) | |
262 | ||
263 | (define_function_unit "imuldiv" 1 0 | |
264 | (and (eq_attr "type" "idiv") | |
265 | (eq_attr "cpu" "ppc630")) | |
266 | 21 20) | |
267 | ||
268 | (define_function_unit "imuldiv" 1 0 | |
269 | (and (eq_attr "type" "ldiv") | |
270 | (eq_attr "cpu" "ppc620,ppc630")) | |
271 | 37 36) | |
272 | ||
bef84347 VM |
273 | ; PPC750 has two integer units: a primary one which can perform all |
274 | ; operations and a secondary one which is fed in lock step with the first | |
275 | ; and can perform "simple" integer operations. | |
276 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
277 | ; for the complex insns. | |
278 | (define_function_unit "iu2" 2 0 | |
279 | (and (eq_attr "type" "integer") | |
280 | (eq_attr "cpu" "ppc750")) | |
281 | 1 1) | |
282 | ||
283 | (define_function_unit "iu2" 2 0 | |
284 | (and (eq_attr "type" "imul") | |
285 | (eq_attr "cpu" "ppc750")) | |
286 | 4 2) | |
287 | ||
288 | (define_function_unit "imuldiv" 1 0 | |
289 | (and (eq_attr "type" "imul") | |
290 | (eq_attr "cpu" "ppc750")) | |
291 | 4 2) | |
292 | ||
293 | (define_function_unit "imuldiv" 1 0 | |
294 | (and (eq_attr "type" "idiv") | |
295 | (eq_attr "cpu" "ppc750")) | |
296 | 19 19) | |
297 | ||
39a10a29 GK |
298 | ; CR-logical operations are execute-serialized, that is they don't |
299 | ; start (and block the function unit) until all preceding operations | |
300 | ; have finished. They don't block dispatch of other insns, though. | |
301 | ; I've imitated this by giving them longer latency. | |
302 | (define_function_unit "sru" 1 0 | |
303 | (and (eq_attr "type" "cr_logical") | |
304 | (eq_attr "cpu" "ppc603,ppc750")) | |
305 | 3 2) | |
306 | ||
b6c9286a | 307 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 308 | ; execute on the branch unit. |
b6c9286a MM |
309 | (define_function_unit "iu" 1 0 |
310 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
311 | (eq_attr "cpu" "rios1")) |
312 | 4 1) | |
313 | ||
314 | (define_function_unit "iu" 1 0 | |
315 | (and (eq_attr "type" "delayed_compare") | |
316 | (eq_attr "cpu" "rios1")) | |
317 | 5 1) | |
318 | ||
319 | (define_function_unit "iu" 1 0 | |
320 | (and (eq_attr "type" "compare,delayed_compare") | |
3cb999d8 | 321 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 322 | 3 1) |
b6c9286a MM |
323 | |
324 | (define_function_unit "iu2" 2 0 | |
b7ff3d82 | 325 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 326 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 327 | 3 1) |
b6c9286a | 328 | |
b6c9286a | 329 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 330 | (and (eq_attr "type" "compare,delayed_compare") |
3cb999d8 | 331 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 332 | 1 1) |
cfb557c4 | 333 | |
b6c9286a MM |
334 | ; fp compare uses fp unit |
335 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 336 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 337 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 338 | 9 1) |
cfb557c4 | 339 | |
b6c9286a MM |
340 | ; rios1 and rios2 have different fpcompare delays |
341 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 342 | (and (eq_attr "type" "fpcompare") |
3cb999d8 | 343 | (eq_attr "cpu" "rios2,ppc630")) |
b6c9286a MM |
344 | 5 1) |
345 | ||
346 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
347 | ; the integer unit | |
348 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 349 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
350 | (define_function_unit "iu" 1 0 |
351 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 352 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
353 | 0 2) |
354 | ||
355 | ; fp compare uses fp unit | |
356 | (define_function_unit "fpu" 1 0 | |
357 | (and (eq_attr "type" "fpcompare") | |
5638268e | 358 | (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 359 | 5 1) |
cfb557c4 | 360 | |
cf27b467 MM |
361 | (define_function_unit "fpu" 1 0 |
362 | (and (eq_attr "type" "fpcompare") | |
363 | (eq_attr "cpu" "mpccore")) | |
364 | 1 1) | |
365 | ||
cfb557c4 | 366 | (define_function_unit "bpu" 1 0 |
324e52cc | 367 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 368 | (eq_attr "cpu" "rios1,rios2,rs64a")) |
b7ff3d82 | 369 | 5 1) |
cfb557c4 RK |
370 | |
371 | (define_function_unit "bpu" 1 0 | |
324e52cc | 372 | (and (eq_attr "type" "mtjmpr") |
5638268e | 373 | (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 374 | 4 1) |
cfb557c4 | 375 | |
39a10a29 GK |
376 | (define_function_unit "bpu" 1 0 |
377 | (and (eq_attr "type" "cr_logical") | |
5638268e | 378 | (eq_attr "cpu" "rios1,rios2,ppc604")) |
39a10a29 GK |
379 | 4 1) |
380 | ||
381 | (define_function_unit "cru" 1 0 | |
382 | (and (eq_attr "type" "cr_logical") | |
5638268e DE |
383 | (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a")) |
384 | 1 1) | |
39a10a29 | 385 | |
b6c9286a MM |
386 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
387 | (define_function_unit "bpu" 1 0 | |
388 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 389 | 1 1) |
b6c9286a MM |
390 | |
391 | (define_function_unit "bpu" 1 0 | |
392 | (eq_attr "type" "branch") | |
b7ff3d82 | 393 | 1 1) |
b6c9286a | 394 | |
cf27b467 | 395 | ; Floating Point Unit |
cfb557c4 | 396 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 397 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 398 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 399 | 2 1) |
cfb557c4 | 400 | |
cf27b467 MM |
401 | (define_function_unit "fpu" 1 0 |
402 | (and (eq_attr "type" "fp") | |
3cb999d8 DE |
403 | (eq_attr "cpu" "rs64a,mpccore")) |
404 | 4 2) | |
cf27b467 | 405 | |
cfb557c4 RK |
406 | (define_function_unit "fpu" 1 0 |
407 | (and (eq_attr "type" "fp") | |
51b8fc2c | 408 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 409 | 4 1) |
cfb557c4 | 410 | |
51b8fc2c RK |
411 | (define_function_unit "fpu" 1 0 |
412 | (and (eq_attr "type" "fp") | |
3cb999d8 | 413 | (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620")) |
b6c9286a | 414 | 3 1) |
51b8fc2c | 415 | |
3cb999d8 DE |
416 | (define_function_unit "fpu" 1 0 |
417 | (and (eq_attr "type" "dmul") | |
418 | (eq_attr "cpu" "rs64a")) | |
419 | 7 2) | |
420 | ||
cf27b467 MM |
421 | (define_function_unit "fpu" 1 0 |
422 | (and (eq_attr "type" "dmul") | |
423 | (eq_attr "cpu" "mpccore")) | |
424 | 5 5) | |
425 | ||
cfb557c4 RK |
426 | (define_function_unit "fpu" 1 0 |
427 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 428 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 429 | 5 2) |
cfb557c4 | 430 | |
b6c9286a | 431 | ; is this true? |
cfb557c4 RK |
432 | (define_function_unit "fpu" 1 0 |
433 | (and (eq_attr "type" "dmul") | |
bef84347 | 434 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 435 | 4 2) |
cfb557c4 RK |
436 | |
437 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 438 | (and (eq_attr "type" "dmul") |
cac8ce95 | 439 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b6c9286a | 440 | 3 1) |
51b8fc2c RK |
441 | |
442 | (define_function_unit "fpu" 1 0 | |
443 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 444 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 445 | 19 19) |
cfb557c4 | 446 | |
3cb999d8 DE |
447 | (define_function_unit "fpu" 1 0 |
448 | (and (eq_attr "type" "sdiv") | |
449 | (eq_attr "cpu" "rs64a")) | |
450 | 31 31) | |
451 | ||
cfb557c4 RK |
452 | (define_function_unit "fpu" 1 0 |
453 | (and (eq_attr "type" "sdiv") | |
51b8fc2c RK |
454 | (eq_attr "cpu" "ppc601")) |
455 | 17 17) | |
456 | ||
cf27b467 MM |
457 | (define_function_unit "fpu" 1 0 |
458 | (and (eq_attr "type" "sdiv") | |
459 | (eq_attr "cpu" "mpccore")) | |
460 | 10 10) | |
461 | ||
51b8fc2c RK |
462 | (define_function_unit "fpu" 1 0 |
463 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 464 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 465 | 18 18) |
cfb557c4 | 466 | |
cf27b467 MM |
467 | (define_function_unit "fpu" 1 0 |
468 | (and (eq_attr "type" "ddiv") | |
469 | (eq_attr "cpu" "mpccore")) | |
470 | 17 17) | |
471 | ||
cfb557c4 RK |
472 | (define_function_unit "fpu" 1 0 |
473 | (and (eq_attr "type" "ddiv") | |
3cb999d8 | 474 | (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620")) |
51b8fc2c | 475 | 31 31) |
cfb557c4 RK |
476 | |
477 | (define_function_unit "fpu" 1 0 | |
478 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 479 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 480 | 33 33) |
cfb557c4 RK |
481 | |
482 | (define_function_unit "fpu" 1 0 | |
483 | (and (eq_attr "type" "ssqrt") | |
a473029f | 484 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 485 | 31 31) |
cfb557c4 RK |
486 | |
487 | (define_function_unit "fpu" 1 0 | |
488 | (and (eq_attr "type" "dsqrt") | |
a473029f | 489 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 490 | 31 31) |
b73d04f2 | 491 | |
51b8fc2c | 492 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 RK |
493 | (define_function_unit "fpu2" 2 0 |
494 | (and (eq_attr "type" "fp") | |
4652f1d4 | 495 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 496 | 2 1) |
cfb557c4 | 497 | |
3cb999d8 DE |
498 | (define_function_unit "fpu2" 2 0 |
499 | (and (eq_attr "type" "fp") | |
500 | (eq_attr "cpu" "ppc630")) | |
501 | 3 1) | |
502 | ||
cfb557c4 RK |
503 | (define_function_unit "fpu2" 2 0 |
504 | (and (eq_attr "type" "dmul") | |
505 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 506 | 2 1) |
cfb557c4 | 507 | |
3cb999d8 DE |
508 | (define_function_unit "fpu2" 2 0 |
509 | (and (eq_attr "type" "dmul") | |
510 | (eq_attr "cpu" "ppc630")) | |
511 | 3 1) | |
512 | ||
cfb557c4 | 513 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 514 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 515 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 516 | 17 17) |
ca7f5001 | 517 | |
3cb999d8 DE |
518 | (define_function_unit "fpu2" 2 0 |
519 | (and (eq_attr "type" "sdiv") | |
520 | (eq_attr "cpu" "ppc630")) | |
521 | 17 17) | |
522 | ||
523 | (define_function_unit "fpu2" 2 0 | |
524 | (and (eq_attr "type" "ddiv") | |
525 | (eq_attr "cpu" "ppc630")) | |
526 | 21 21) | |
527 | ||
ca7f5001 | 528 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 529 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 530 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 531 | 26 26) |
b6c9286a | 532 | |
3cb999d8 DE |
533 | (define_function_unit "fpu2" 2 0 |
534 | (and (eq_attr "type" "ssqrt") | |
535 | (eq_attr "cpu" "ppc630")) | |
536 | 18 18) | |
537 | ||
538 | (define_function_unit "fpu2" 2 0 | |
539 | (and (eq_attr "type" "dsqrt") | |
540 | (eq_attr "cpu" "ppc630")) | |
541 | 26 26) | |
542 | ||
1fd4e8c1 RK |
543 | \f |
544 | ;; Start with fixed-point load and store insns. Here we put only the more | |
545 | ;; complex forms. Basic data transfer is done later. | |
546 | ||
51b8fc2c RK |
547 | (define_expand "zero_extendqidi2" |
548 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
549 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
550 | "TARGET_POWERPC64" | |
551 | "") | |
552 | ||
553 | (define_insn "" | |
554 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
555 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
556 | "TARGET_POWERPC64" | |
557 | "@ | |
558 | lbz%U1%X1 %0,%1 | |
4371f8af | 559 | rldicl %0,%1,0,56" |
51b8fc2c RK |
560 | [(set_attr "type" "load,*")]) |
561 | ||
562 | (define_insn "" | |
9ebbca7d GK |
563 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
564 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 565 | (const_int 0))) |
9ebbca7d | 566 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 567 | "TARGET_POWERPC64" |
9ebbca7d GK |
568 | "@ |
569 | rldicl. %2,%1,0,56 | |
570 | #" | |
571 | [(set_attr "type" "compare") | |
572 | (set_attr "length" "4,8")]) | |
573 | ||
574 | (define_split | |
575 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
576 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
577 | (const_int 0))) | |
578 | (clobber (match_scratch:DI 2 ""))] | |
579 | "TARGET_POWERPC64 && reload_completed" | |
580 | [(set (match_dup 2) | |
581 | (zero_extend:DI (match_dup 1))) | |
582 | (set (match_dup 0) | |
583 | (compare:CC (match_dup 2) | |
584 | (const_int 0)))] | |
585 | "") | |
51b8fc2c RK |
586 | |
587 | (define_insn "" | |
9ebbca7d GK |
588 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
589 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 590 | (const_int 0))) |
9ebbca7d | 591 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 592 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 593 | "TARGET_POWERPC64" |
9ebbca7d GK |
594 | "@ |
595 | rldicl. %0,%1,0,56 | |
596 | #" | |
597 | [(set_attr "type" "compare") | |
598 | (set_attr "length" "4,8")]) | |
599 | ||
600 | (define_split | |
601 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
602 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
603 | (const_int 0))) | |
604 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
605 | (zero_extend:DI (match_dup 1)))] | |
606 | "TARGET_POWERPC64 && reload_completed" | |
607 | [(set (match_dup 0) | |
608 | (zero_extend:DI (match_dup 1))) | |
609 | (set (match_dup 2) | |
610 | (compare:CC (match_dup 0) | |
611 | (const_int 0)))] | |
612 | "") | |
51b8fc2c | 613 | |
2bee0449 RK |
614 | (define_insn "extendqidi2" |
615 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
616 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 617 | "TARGET_POWERPC64" |
2bee0449 | 618 | "extsb %0,%1") |
51b8fc2c RK |
619 | |
620 | (define_insn "" | |
9ebbca7d GK |
621 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
622 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 623 | (const_int 0))) |
9ebbca7d | 624 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 625 | "TARGET_POWERPC64" |
9ebbca7d GK |
626 | "@ |
627 | extsb. %2,%1 | |
628 | #" | |
629 | [(set_attr "type" "compare") | |
630 | (set_attr "length" "4,8")]) | |
631 | ||
632 | (define_split | |
633 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
634 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
635 | (const_int 0))) | |
636 | (clobber (match_scratch:DI 2 ""))] | |
637 | "TARGET_POWERPC64 && reload_completed" | |
638 | [(set (match_dup 2) | |
639 | (sign_extend:DI (match_dup 1))) | |
640 | (set (match_dup 0) | |
641 | (compare:CC (match_dup 2) | |
642 | (const_int 0)))] | |
643 | "") | |
51b8fc2c RK |
644 | |
645 | (define_insn "" | |
9ebbca7d GK |
646 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
647 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 648 | (const_int 0))) |
9ebbca7d | 649 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
650 | (sign_extend:DI (match_dup 1)))] |
651 | "TARGET_POWERPC64" | |
9ebbca7d GK |
652 | "@ |
653 | extsb. %0,%1 | |
654 | #" | |
655 | [(set_attr "type" "compare") | |
656 | (set_attr "length" "4,8")]) | |
657 | ||
658 | (define_split | |
659 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
660 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
661 | (const_int 0))) | |
662 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
663 | (sign_extend:DI (match_dup 1)))] | |
664 | "TARGET_POWERPC64 && reload_completed" | |
665 | [(set (match_dup 0) | |
666 | (sign_extend:DI (match_dup 1))) | |
667 | (set (match_dup 2) | |
668 | (compare:CC (match_dup 0) | |
669 | (const_int 0)))] | |
670 | "") | |
51b8fc2c RK |
671 | |
672 | (define_expand "zero_extendhidi2" | |
673 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
674 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
675 | "TARGET_POWERPC64" | |
676 | "") | |
677 | ||
678 | (define_insn "" | |
679 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
680 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
681 | "TARGET_POWERPC64" | |
682 | "@ | |
683 | lhz%U1%X1 %0,%1 | |
4371f8af | 684 | rldicl %0,%1,0,48" |
51b8fc2c RK |
685 | [(set_attr "type" "load,*")]) |
686 | ||
687 | (define_insn "" | |
9ebbca7d GK |
688 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
689 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 690 | (const_int 0))) |
9ebbca7d | 691 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 692 | "TARGET_POWERPC64" |
9ebbca7d GK |
693 | "@ |
694 | rldicl. %2,%1,0,48 | |
695 | #" | |
696 | [(set_attr "type" "compare") | |
697 | (set_attr "length" "4,8")]) | |
698 | ||
699 | (define_split | |
700 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
701 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
702 | (const_int 0))) | |
703 | (clobber (match_scratch:DI 2 ""))] | |
704 | "TARGET_POWERPC64 && reload_completed" | |
705 | [(set (match_dup 2) | |
706 | (zero_extend:DI (match_dup 1))) | |
707 | (set (match_dup 0) | |
708 | (compare:CC (match_dup 2) | |
709 | (const_int 0)))] | |
710 | "") | |
51b8fc2c RK |
711 | |
712 | (define_insn "" | |
9ebbca7d GK |
713 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
714 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 715 | (const_int 0))) |
9ebbca7d | 716 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
717 | (zero_extend:DI (match_dup 1)))] |
718 | "TARGET_POWERPC64" | |
9ebbca7d GK |
719 | "@ |
720 | rldicl. %0,%1,0,48 | |
721 | #" | |
722 | [(set_attr "type" "compare") | |
723 | (set_attr "length" "4,8")]) | |
724 | ||
725 | (define_split | |
726 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
727 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
728 | (const_int 0))) | |
729 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
730 | (zero_extend:DI (match_dup 1)))] | |
731 | "TARGET_POWERPC64 && reload_completed" | |
732 | [(set (match_dup 0) | |
733 | (zero_extend:DI (match_dup 1))) | |
734 | (set (match_dup 2) | |
735 | (compare:CC (match_dup 0) | |
736 | (const_int 0)))] | |
737 | "") | |
51b8fc2c RK |
738 | |
739 | (define_expand "extendhidi2" | |
740 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
741 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
742 | "TARGET_POWERPC64" | |
743 | "") | |
744 | ||
745 | (define_insn "" | |
746 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
747 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
748 | "TARGET_POWERPC64" | |
749 | "@ | |
750 | lha%U1%X1 %0,%1 | |
751 | extsh %0,%1" | |
752 | [(set_attr "type" "load,*")]) | |
753 | ||
754 | (define_insn "" | |
9ebbca7d GK |
755 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
756 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 757 | (const_int 0))) |
9ebbca7d | 758 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 759 | "TARGET_POWERPC64" |
9ebbca7d GK |
760 | "@ |
761 | extsh. %2,%1 | |
762 | #" | |
763 | [(set_attr "type" "compare") | |
764 | (set_attr "length" "4,8")]) | |
765 | ||
766 | (define_split | |
767 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
768 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
769 | (const_int 0))) | |
770 | (clobber (match_scratch:DI 2 ""))] | |
771 | "TARGET_POWERPC64 && reload_completed" | |
772 | [(set (match_dup 2) | |
773 | (sign_extend:DI (match_dup 1))) | |
774 | (set (match_dup 0) | |
775 | (compare:CC (match_dup 2) | |
776 | (const_int 0)))] | |
777 | "") | |
51b8fc2c RK |
778 | |
779 | (define_insn "" | |
9ebbca7d GK |
780 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
781 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 782 | (const_int 0))) |
9ebbca7d | 783 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
784 | (sign_extend:DI (match_dup 1)))] |
785 | "TARGET_POWERPC64" | |
9ebbca7d GK |
786 | "@ |
787 | extsh. %0,%1 | |
788 | #" | |
789 | [(set_attr "type" "compare") | |
790 | (set_attr "length" "4,8")]) | |
791 | ||
792 | (define_split | |
793 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
794 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
795 | (const_int 0))) | |
796 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
797 | (sign_extend:DI (match_dup 1)))] | |
798 | "TARGET_POWERPC64 && reload_completed" | |
799 | [(set (match_dup 0) | |
800 | (sign_extend:DI (match_dup 1))) | |
801 | (set (match_dup 2) | |
802 | (compare:CC (match_dup 0) | |
803 | (const_int 0)))] | |
804 | "") | |
51b8fc2c RK |
805 | |
806 | (define_expand "zero_extendsidi2" | |
807 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
808 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
809 | "TARGET_POWERPC64" | |
810 | "") | |
811 | ||
812 | (define_insn "" | |
813 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
814 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
815 | "TARGET_POWERPC64" | |
816 | "@ | |
817 | lwz%U1%X1 %0,%1 | |
818 | rldicl %0,%1,0,32" | |
819 | [(set_attr "type" "load,*")]) | |
820 | ||
821 | (define_insn "" | |
9ebbca7d GK |
822 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
823 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 824 | (const_int 0))) |
9ebbca7d | 825 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 826 | "TARGET_POWERPC64" |
9ebbca7d GK |
827 | "@ |
828 | rldicl. %2,%1,0,32 | |
829 | #" | |
830 | [(set_attr "type" "compare") | |
831 | (set_attr "length" "4,8")]) | |
832 | ||
833 | (define_split | |
834 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
835 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
836 | (const_int 0))) | |
837 | (clobber (match_scratch:DI 2 ""))] | |
838 | "TARGET_POWERPC64 && reload_completed" | |
839 | [(set (match_dup 2) | |
840 | (zero_extend:DI (match_dup 1))) | |
841 | (set (match_dup 0) | |
842 | (compare:CC (match_dup 2) | |
843 | (const_int 0)))] | |
844 | "") | |
51b8fc2c RK |
845 | |
846 | (define_insn "" | |
9ebbca7d GK |
847 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
848 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 849 | (const_int 0))) |
9ebbca7d | 850 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
851 | (zero_extend:DI (match_dup 1)))] |
852 | "TARGET_POWERPC64" | |
9ebbca7d GK |
853 | "@ |
854 | rldicl. %0,%1,0,32 | |
855 | #" | |
856 | [(set_attr "type" "compare") | |
857 | (set_attr "length" "4,8")]) | |
858 | ||
859 | (define_split | |
860 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
861 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
862 | (const_int 0))) | |
863 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
864 | (zero_extend:DI (match_dup 1)))] | |
865 | "TARGET_POWERPC64 && reload_completed" | |
866 | [(set (match_dup 0) | |
867 | (zero_extend:DI (match_dup 1))) | |
868 | (set (match_dup 2) | |
869 | (compare:CC (match_dup 0) | |
870 | (const_int 0)))] | |
871 | "") | |
51b8fc2c RK |
872 | |
873 | (define_expand "extendsidi2" | |
874 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
875 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
876 | "TARGET_POWERPC64" | |
877 | "") | |
878 | ||
879 | (define_insn "" | |
880 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 881 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
882 | "TARGET_POWERPC64" |
883 | "@ | |
884 | lwa%U1%X1 %0,%1 | |
885 | extsw %0,%1" | |
886 | [(set_attr "type" "load,*")]) | |
887 | ||
888 | (define_insn "" | |
9ebbca7d GK |
889 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
890 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 891 | (const_int 0))) |
9ebbca7d | 892 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 893 | "TARGET_POWERPC64" |
9ebbca7d GK |
894 | "@ |
895 | extsw. %2,%1 | |
896 | #" | |
897 | [(set_attr "type" "compare") | |
898 | (set_attr "length" "4,8")]) | |
899 | ||
900 | (define_split | |
901 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
902 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
903 | (const_int 0))) | |
904 | (clobber (match_scratch:DI 2 ""))] | |
905 | "TARGET_POWERPC64 && reload_completed" | |
906 | [(set (match_dup 2) | |
907 | (sign_extend:DI (match_dup 1))) | |
908 | (set (match_dup 0) | |
909 | (compare:CC (match_dup 2) | |
910 | (const_int 0)))] | |
911 | "") | |
51b8fc2c RK |
912 | |
913 | (define_insn "" | |
9ebbca7d GK |
914 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
915 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 916 | (const_int 0))) |
9ebbca7d | 917 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
918 | (sign_extend:DI (match_dup 1)))] |
919 | "TARGET_POWERPC64" | |
9ebbca7d GK |
920 | "@ |
921 | extsw. %0,%1 | |
922 | #" | |
923 | [(set_attr "type" "compare") | |
924 | (set_attr "length" "4,8")]) | |
925 | ||
926 | (define_split | |
927 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
928 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
929 | (const_int 0))) | |
930 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
931 | (sign_extend:DI (match_dup 1)))] | |
932 | "TARGET_POWERPC64 && reload_completed" | |
933 | [(set (match_dup 0) | |
934 | (sign_extend:DI (match_dup 1))) | |
935 | (set (match_dup 2) | |
936 | (compare:CC (match_dup 0) | |
937 | (const_int 0)))] | |
938 | "") | |
51b8fc2c | 939 | |
1fd4e8c1 | 940 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
941 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
942 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
943 | "" |
944 | "") | |
945 | ||
946 | (define_insn "" | |
cd2b37d9 | 947 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
948 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
949 | "" | |
950 | "@ | |
951 | lbz%U1%X1 %0,%1 | |
005a35b9 | 952 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
953 | [(set_attr "type" "load,*")]) |
954 | ||
955 | (define_insn "" | |
9ebbca7d GK |
956 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
957 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 958 | (const_int 0))) |
9ebbca7d | 959 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 960 | "" |
9ebbca7d GK |
961 | "@ |
962 | {andil.|andi.} %2,%1,0xff | |
963 | #" | |
964 | [(set_attr "type" "compare") | |
965 | (set_attr "length" "4,8")]) | |
966 | ||
967 | (define_split | |
968 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
969 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
970 | (const_int 0))) | |
971 | (clobber (match_scratch:SI 2 ""))] | |
972 | "reload_completed" | |
973 | [(set (match_dup 2) | |
974 | (zero_extend:SI (match_dup 1))) | |
975 | (set (match_dup 0) | |
976 | (compare:CC (match_dup 2) | |
977 | (const_int 0)))] | |
978 | "") | |
1fd4e8c1 RK |
979 | |
980 | (define_insn "" | |
9ebbca7d GK |
981 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
982 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 983 | (const_int 0))) |
9ebbca7d | 984 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
985 | (zero_extend:SI (match_dup 1)))] |
986 | "" | |
9ebbca7d GK |
987 | "@ |
988 | {andil.|andi.} %0,%1,0xff | |
989 | #" | |
990 | [(set_attr "type" "compare") | |
991 | (set_attr "length" "4,8")]) | |
992 | ||
993 | (define_split | |
994 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
995 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
996 | (const_int 0))) | |
997 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
998 | (zero_extend:SI (match_dup 1)))] | |
999 | "reload_completed" | |
1000 | [(set (match_dup 0) | |
1001 | (zero_extend:SI (match_dup 1))) | |
1002 | (set (match_dup 2) | |
1003 | (compare:CC (match_dup 0) | |
1004 | (const_int 0)))] | |
1005 | "") | |
1fd4e8c1 | 1006 | |
51b8fc2c RK |
1007 | (define_expand "extendqisi2" |
1008 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1009 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1010 | "" | |
1011 | " | |
1012 | { | |
1013 | if (TARGET_POWERPC) | |
1014 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
1015 | else if (TARGET_POWER) | |
1016 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
1017 | else | |
1018 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
1019 | DONE; | |
1020 | }") | |
1021 | ||
1022 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
1023 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1024 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 1025 | "TARGET_POWERPC" |
2bee0449 | 1026 | "extsb %0,%1") |
51b8fc2c RK |
1027 | |
1028 | (define_insn "" | |
9ebbca7d GK |
1029 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1030 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1031 | (const_int 0))) |
9ebbca7d | 1032 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 1033 | "TARGET_POWERPC" |
9ebbca7d GK |
1034 | "@ |
1035 | extsb. %2,%1 | |
1036 | #" | |
1037 | [(set_attr "type" "compare") | |
1038 | (set_attr "length" "4,8")]) | |
1039 | ||
1040 | (define_split | |
1041 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1042 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1043 | (const_int 0))) | |
1044 | (clobber (match_scratch:SI 2 ""))] | |
1045 | "TARGET_POWERPC && reload_completed" | |
1046 | [(set (match_dup 2) | |
1047 | (sign_extend:SI (match_dup 1))) | |
1048 | (set (match_dup 0) | |
1049 | (compare:CC (match_dup 2) | |
1050 | (const_int 0)))] | |
1051 | "") | |
51b8fc2c RK |
1052 | |
1053 | (define_insn "" | |
9ebbca7d GK |
1054 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1055 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1056 | (const_int 0))) |
9ebbca7d | 1057 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1058 | (sign_extend:SI (match_dup 1)))] |
1059 | "TARGET_POWERPC" | |
9ebbca7d GK |
1060 | "@ |
1061 | extsb. %0,%1 | |
1062 | #" | |
1063 | [(set_attr "type" "compare") | |
1064 | (set_attr "length" "4,8")]) | |
1065 | ||
1066 | (define_split | |
1067 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1068 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1069 | (const_int 0))) | |
1070 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1071 | (sign_extend:SI (match_dup 1)))] | |
1072 | "TARGET_POWERPC && reload_completed" | |
1073 | [(set (match_dup 0) | |
1074 | (sign_extend:SI (match_dup 1))) | |
1075 | (set (match_dup 2) | |
1076 | (compare:CC (match_dup 0) | |
1077 | (const_int 0)))] | |
1078 | "") | |
51b8fc2c RK |
1079 | |
1080 | (define_expand "extendqisi2_power" | |
1081 | [(parallel [(set (match_dup 2) | |
1082 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1083 | (const_int 24))) | |
1084 | (clobber (scratch:SI))]) | |
1085 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1086 | (ashiftrt:SI (match_dup 2) | |
1087 | (const_int 24))) | |
1088 | (clobber (scratch:SI))])] | |
1089 | "TARGET_POWER" | |
1090 | " | |
1091 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1092 | operands[2] = gen_reg_rtx (SImode); }") | |
1093 | ||
1094 | (define_expand "extendqisi2_no_power" | |
1095 | [(set (match_dup 2) | |
1096 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1097 | (const_int 24))) | |
1098 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1099 | (ashiftrt:SI (match_dup 2) | |
1100 | (const_int 24)))] | |
1101 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1102 | " | |
1103 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1104 | operands[2] = gen_reg_rtx (SImode); }") | |
1105 | ||
1fd4e8c1 | 1106 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
1107 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
1108 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1109 | "" |
1110 | "") | |
1111 | ||
1112 | (define_insn "" | |
cd2b37d9 | 1113 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1114 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1115 | "" | |
1116 | "@ | |
1117 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1118 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
1119 | [(set_attr "type" "load,*")]) |
1120 | ||
1121 | (define_insn "" | |
9ebbca7d GK |
1122 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1123 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1124 | (const_int 0))) |
9ebbca7d | 1125 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 1126 | "" |
9ebbca7d GK |
1127 | "@ |
1128 | {andil.|andi.} %2,%1,0xff | |
1129 | #" | |
1130 | [(set_attr "type" "compare") | |
1131 | (set_attr "length" "4,8")]) | |
1132 | ||
1133 | (define_split | |
1134 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1135 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1136 | (const_int 0))) | |
1137 | (clobber (match_scratch:HI 2 ""))] | |
1138 | "reload_completed" | |
1139 | [(set (match_dup 2) | |
1140 | (zero_extend:HI (match_dup 1))) | |
1141 | (set (match_dup 0) | |
1142 | (compare:CC (match_dup 2) | |
1143 | (const_int 0)))] | |
1144 | "") | |
1fd4e8c1 | 1145 | |
51b8fc2c | 1146 | (define_insn "" |
9ebbca7d GK |
1147 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1148 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1149 | (const_int 0))) |
9ebbca7d | 1150 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
1151 | (zero_extend:HI (match_dup 1)))] |
1152 | "" | |
9ebbca7d GK |
1153 | "@ |
1154 | {andil.|andi.} %0,%1,0xff | |
1155 | #" | |
1156 | [(set_attr "type" "compare") | |
1157 | (set_attr "length" "4,8")]) | |
1158 | ||
1159 | (define_split | |
1160 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1161 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1162 | (const_int 0))) | |
1163 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1164 | (zero_extend:HI (match_dup 1)))] | |
1165 | "reload_completed" | |
1166 | [(set (match_dup 0) | |
1167 | (zero_extend:HI (match_dup 1))) | |
1168 | (set (match_dup 2) | |
1169 | (compare:CC (match_dup 0) | |
1170 | (const_int 0)))] | |
1171 | "") | |
815cdc52 MM |
1172 | |
1173 | (define_expand "extendqihi2" | |
1174 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
1175 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1176 | "" | |
1177 | " | |
1178 | { | |
1179 | if (TARGET_POWERPC) | |
1180 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
1181 | else if (TARGET_POWER) | |
1182 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
1183 | else | |
1184 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
1185 | DONE; | |
1186 | }") | |
1187 | ||
1188 | (define_insn "extendqihi2_ppc" | |
1189 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
1190 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
1191 | "TARGET_POWERPC" | |
1192 | "extsb %0,%1") | |
1193 | ||
1194 | (define_insn "" | |
9ebbca7d GK |
1195 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1196 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1197 | (const_int 0))) |
9ebbca7d | 1198 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 1199 | "TARGET_POWERPC" |
9ebbca7d GK |
1200 | "@ |
1201 | extsb. %2,%1 | |
1202 | #" | |
1203 | [(set_attr "type" "compare") | |
1204 | (set_attr "length" "4,8")]) | |
1205 | ||
1206 | (define_split | |
1207 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1208 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1209 | (const_int 0))) | |
1210 | (clobber (match_scratch:HI 2 ""))] | |
1211 | "TARGET_POWERPC && reload_completed" | |
1212 | [(set (match_dup 2) | |
1213 | (sign_extend:HI (match_dup 1))) | |
1214 | (set (match_dup 0) | |
1215 | (compare:CC (match_dup 2) | |
1216 | (const_int 0)))] | |
1217 | "") | |
815cdc52 MM |
1218 | |
1219 | (define_insn "" | |
9ebbca7d GK |
1220 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1221 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1222 | (const_int 0))) |
9ebbca7d | 1223 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1224 | (sign_extend:HI (match_dup 1)))] |
1225 | "TARGET_POWERPC" | |
9ebbca7d GK |
1226 | "@ |
1227 | extsb. %0,%1 | |
1228 | #" | |
1229 | [(set_attr "type" "compare") | |
1230 | (set_attr "length" "4,8")]) | |
1231 | ||
1232 | (define_split | |
1233 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1234 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1235 | (const_int 0))) | |
1236 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1237 | (sign_extend:HI (match_dup 1)))] | |
1238 | "TARGET_POWERPC && reload_completed" | |
1239 | [(set (match_dup 0) | |
1240 | (sign_extend:HI (match_dup 1))) | |
1241 | (set (match_dup 2) | |
1242 | (compare:CC (match_dup 0) | |
1243 | (const_int 0)))] | |
1244 | "") | |
51b8fc2c RK |
1245 | |
1246 | (define_expand "extendqihi2_power" | |
1247 | [(parallel [(set (match_dup 2) | |
1248 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1249 | (const_int 24))) | |
1250 | (clobber (scratch:SI))]) | |
1251 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
1252 | (ashiftrt:SI (match_dup 2) | |
1253 | (const_int 24))) | |
1254 | (clobber (scratch:SI))])] | |
1255 | "TARGET_POWER" | |
1256 | " | |
1257 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1258 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1259 | operands[2] = gen_reg_rtx (SImode); }") | |
1260 | ||
1261 | (define_expand "extendqihi2_no_power" | |
1262 | [(set (match_dup 2) | |
1263 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1264 | (const_int 24))) | |
1265 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1266 | (ashiftrt:SI (match_dup 2) | |
1267 | (const_int 24)))] | |
1268 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1269 | " | |
1270 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1271 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1272 | operands[2] = gen_reg_rtx (SImode); }") | |
1273 | ||
1fd4e8c1 | 1274 | (define_expand "zero_extendhisi2" |
5f243543 | 1275 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 1276 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
1277 | "" |
1278 | "") | |
1279 | ||
1280 | (define_insn "" | |
cd2b37d9 | 1281 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1282 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1283 | "" | |
1284 | "@ | |
1285 | lhz%U1%X1 %0,%1 | |
005a35b9 | 1286 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
1287 | [(set_attr "type" "load,*")]) |
1288 | ||
1289 | (define_insn "" | |
9ebbca7d GK |
1290 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1291 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1292 | (const_int 0))) |
9ebbca7d | 1293 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1294 | "" |
9ebbca7d GK |
1295 | "@ |
1296 | {andil.|andi.} %2,%1,0xffff | |
1297 | #" | |
1298 | [(set_attr "type" "compare") | |
1299 | (set_attr "length" "4,8")]) | |
1300 | ||
1301 | (define_split | |
1302 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1303 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1304 | (const_int 0))) | |
1305 | (clobber (match_scratch:SI 2 ""))] | |
1306 | "reload_completed" | |
1307 | [(set (match_dup 2) | |
1308 | (zero_extend:SI (match_dup 1))) | |
1309 | (set (match_dup 0) | |
1310 | (compare:CC (match_dup 2) | |
1311 | (const_int 0)))] | |
1312 | "") | |
1fd4e8c1 RK |
1313 | |
1314 | (define_insn "" | |
9ebbca7d GK |
1315 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1316 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1317 | (const_int 0))) |
9ebbca7d | 1318 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1319 | (zero_extend:SI (match_dup 1)))] |
1320 | "" | |
9ebbca7d GK |
1321 | "@ |
1322 | {andil.|andi.} %0,%1,0xffff | |
1323 | #" | |
1324 | [(set_attr "type" "compare") | |
1325 | (set_attr "length" "4,8")]) | |
1326 | ||
1327 | (define_split | |
1328 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1329 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1330 | (const_int 0))) | |
1331 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1332 | (zero_extend:SI (match_dup 1)))] | |
1333 | "reload_completed" | |
1334 | [(set (match_dup 0) | |
1335 | (zero_extend:SI (match_dup 1))) | |
1336 | (set (match_dup 2) | |
1337 | (compare:CC (match_dup 0) | |
1338 | (const_int 0)))] | |
1339 | "") | |
1fd4e8c1 RK |
1340 | |
1341 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
1342 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1343 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1344 | "" |
1345 | "") | |
1346 | ||
1347 | (define_insn "" | |
cd2b37d9 | 1348 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1349 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1350 | "" | |
1351 | "@ | |
1352 | lha%U1%X1 %0,%1 | |
ca7f5001 | 1353 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
1354 | [(set_attr "type" "load,*")]) |
1355 | ||
1356 | (define_insn "" | |
9ebbca7d GK |
1357 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1358 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1359 | (const_int 0))) |
9ebbca7d | 1360 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1361 | "" |
9ebbca7d GK |
1362 | "@ |
1363 | {exts.|extsh.} %2,%1 | |
1364 | #" | |
1365 | [(set_attr "type" "compare") | |
1366 | (set_attr "length" "4,8")]) | |
1367 | ||
1368 | (define_split | |
1369 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1370 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1371 | (const_int 0))) | |
1372 | (clobber (match_scratch:SI 2 ""))] | |
1373 | "reload_completed" | |
1374 | [(set (match_dup 2) | |
1375 | (sign_extend:SI (match_dup 1))) | |
1376 | (set (match_dup 0) | |
1377 | (compare:CC (match_dup 2) | |
1378 | (const_int 0)))] | |
1379 | "") | |
1fd4e8c1 RK |
1380 | |
1381 | (define_insn "" | |
9ebbca7d GK |
1382 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1383 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1384 | (const_int 0))) |
9ebbca7d | 1385 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1386 | (sign_extend:SI (match_dup 1)))] |
1387 | "" | |
9ebbca7d GK |
1388 | "@ |
1389 | {exts.|extsh.} %0,%1 | |
1390 | #" | |
1391 | [(set_attr "type" "compare") | |
1392 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1393 | \f |
9ebbca7d GK |
1394 | (define_split |
1395 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1396 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1397 | (const_int 0))) | |
1398 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1399 | (sign_extend:SI (match_dup 1)))] | |
1400 | "reload_completed" | |
1401 | [(set (match_dup 0) | |
1402 | (sign_extend:SI (match_dup 1))) | |
1403 | (set (match_dup 2) | |
1404 | (compare:CC (match_dup 0) | |
1405 | (const_int 0)))] | |
1406 | "") | |
1407 | ||
1fd4e8c1 | 1408 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
1409 | |
1410 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
1411 | ;; allowing register zero as source. | |
7cd5235b MM |
1412 | (define_expand "addsi3" |
1413 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1414 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 1415 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
1416 | "" |
1417 | " | |
1418 | { | |
677a9668 DE |
1419 | if (GET_CODE (operands[2]) == CONST_INT |
1420 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 1421 | { |
677a9668 | 1422 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
1423 | ? operands[0] : gen_reg_rtx (SImode)); |
1424 | ||
1425 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
1426 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
1427 | ||
1428 | if (low & 0x8000) | |
38886f37 AO |
1429 | { |
1430 | high = trunc_int_for_mode (high + 0x10000, SImode); | |
1431 | low = trunc_int_for_mode (low, HImode); | |
1432 | } | |
7cd5235b | 1433 | |
9ebbca7d GK |
1434 | /* The ordering here is important for the prolog expander. |
1435 | When space is allocated from the stack, adding 'low' first may | |
1436 | produce a temporary deallocation (which would be bad). */ | |
7cd5235b MM |
1437 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high))); |
1438 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); | |
1439 | DONE; | |
1440 | } | |
1441 | }") | |
1442 | ||
1443 | (define_insn "*addsi3_internal1" | |
1444 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1445 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1446 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1447 | "" |
1448 | "@ | |
deb9225a RK |
1449 | {cax|add} %0,%1,%2 |
1450 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1451 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1452 | {cau|addis} %0,%1,%v2" |
1453 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1454 | |
ee890fe2 SS |
1455 | (define_insn "addsi3_high" |
1456 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1457 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1458 | (high:SI (match_operand 2 "" ""))))] | |
1459 | "TARGET_MACHO && !TARGET_64BIT" | |
1460 | "{cau|addis} %0,%1,ha16(%2)" | |
1461 | [(set_attr "length" "4")]) | |
1462 | ||
7cd5235b | 1463 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1464 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1465 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1466 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1467 | (const_int 0))) |
cb8cc086 | 1468 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1469 | "! TARGET_POWERPC64" |
deb9225a RK |
1470 | "@ |
1471 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1472 | {ai.|addic.} %3,%1,%2 |
1473 | # | |
1474 | #" | |
1475 | [(set_attr "type" "compare") | |
1476 | (set_attr "length" "4,4,8,8")]) | |
1477 | ||
1478 | (define_split | |
1479 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1480 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1481 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1482 | (const_int 0))) | |
1483 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1484 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1485 | [(set (match_dup 3) |
1486 | (plus:SI (match_dup 1) | |
1487 | (match_dup 2))) | |
1488 | (set (match_dup 0) | |
1489 | (compare:CC (match_dup 3) | |
1490 | (const_int 0)))] | |
1491 | "") | |
7e69e155 | 1492 | |
7cd5235b | 1493 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1494 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1495 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1496 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1497 | (const_int 0))) |
cb8cc086 MM |
1498 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1499 | (plus:SI (match_dup 1) | |
1500 | (match_dup 2)))] | |
0ad91047 | 1501 | "! TARGET_POWERPC64" |
deb9225a RK |
1502 | "@ |
1503 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1504 | {ai.|addic.} %0,%1,%2 |
1505 | # | |
1506 | #" | |
1507 | [(set_attr "type" "compare") | |
1508 | (set_attr "length" "4,4,8,8")]) | |
1509 | ||
1510 | (define_split | |
1511 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1512 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1513 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1514 | (const_int 0))) | |
1515 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1516 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1517 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1518 | [(set (match_dup 0) |
1519 | (plus:SI (match_dup 1) | |
1520 | (match_dup 2))) | |
1521 | (set (match_dup 3) | |
1522 | (compare:CC (match_dup 0) | |
1523 | (const_int 0)))] | |
1524 | "") | |
7e69e155 | 1525 | |
f357808b RK |
1526 | ;; Split an add that we can't do in one insn into two insns, each of which |
1527 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1528 | ;; add should be last in case the result gets used in an address. | |
1529 | ||
1530 | (define_split | |
cd2b37d9 RK |
1531 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1532 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1533 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1534 | "" |
f357808b RK |
1535 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1536 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1537 | " | |
1fd4e8c1 | 1538 | { |
e6ca2c17 DE |
1539 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
1540 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
1fd4e8c1 | 1541 | |
f357808b | 1542 | if (low & 0x8000) |
38886f37 AO |
1543 | { |
1544 | high = trunc_int_for_mode (high + 0x10000, SImode); | |
1545 | low = trunc_int_for_mode (low, HImode); | |
1546 | } | |
1fd4e8c1 | 1547 | |
e6ca2c17 DE |
1548 | operands[3] = GEN_INT (high); |
1549 | operands[4] = GEN_INT (low); | |
1fd4e8c1 RK |
1550 | }") |
1551 | ||
8de2a197 | 1552 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1553 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1554 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1555 | "" |
ca7f5001 RK |
1556 | "nor %0,%1,%1") |
1557 | ||
1558 | (define_insn "" | |
52d3af72 DE |
1559 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1560 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1561 | (const_int 0))) |
52d3af72 | 1562 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1563 | "! TARGET_POWERPC64" |
52d3af72 DE |
1564 | "@ |
1565 | nor. %2,%1,%1 | |
1566 | #" | |
1567 | [(set_attr "type" "compare") | |
1568 | (set_attr "length" "4,8")]) | |
1569 | ||
1570 | (define_split | |
1571 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1572 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1573 | (const_int 0))) | |
1574 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1575 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1576 | [(set (match_dup 2) |
1577 | (not:SI (match_dup 1))) | |
1578 | (set (match_dup 0) | |
1579 | (compare:CC (match_dup 2) | |
1580 | (const_int 0)))] | |
1581 | "") | |
ca7f5001 RK |
1582 | |
1583 | (define_insn "" | |
52d3af72 DE |
1584 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1585 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1586 | (const_int 0))) |
52d3af72 | 1587 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1588 | (not:SI (match_dup 1)))] |
0ad91047 | 1589 | "! TARGET_POWERPC64" |
52d3af72 DE |
1590 | "@ |
1591 | nor. %0,%1,%1 | |
1592 | #" | |
1593 | [(set_attr "type" "compare") | |
1594 | (set_attr "length" "4,8")]) | |
1595 | ||
1596 | (define_split | |
1597 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1598 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1599 | (const_int 0))) | |
1600 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1601 | (not:SI (match_dup 1)))] | |
0ad91047 | 1602 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1603 | [(set (match_dup 0) |
1604 | (not:SI (match_dup 1))) | |
1605 | (set (match_dup 2) | |
1606 | (compare:CC (match_dup 0) | |
1607 | (const_int 0)))] | |
1608 | "") | |
1fd4e8c1 RK |
1609 | |
1610 | (define_insn "" | |
3d91674b RK |
1611 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1612 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1613 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1614 | "! TARGET_POWERPC" |
ca7f5001 | 1615 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1616 | |
deb9225a RK |
1617 | (define_insn "" |
1618 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1619 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1620 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1621 | "TARGET_POWERPC" | |
1622 | "@ | |
1623 | subf %0,%2,%1 | |
1624 | subfic %0,%2,%1") | |
1625 | ||
1fd4e8c1 | 1626 | (define_insn "" |
cb8cc086 MM |
1627 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1628 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1629 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1630 | (const_int 0))) |
cb8cc086 | 1631 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1632 | "! TARGET_POWERPC" |
cb8cc086 MM |
1633 | "@ |
1634 | {sf.|subfc.} %3,%2,%1 | |
1635 | #" | |
1636 | [(set_attr "type" "compare") | |
1637 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1638 | |
deb9225a | 1639 | (define_insn "" |
cb8cc086 MM |
1640 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1641 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1642 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1643 | (const_int 0))) |
cb8cc086 | 1644 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1645 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1646 | "@ |
1647 | subf. %3,%2,%1 | |
1648 | #" | |
1649 | [(set_attr "type" "compare") | |
1650 | (set_attr "length" "4,8")]) | |
1651 | ||
1652 | (define_split | |
1653 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1654 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1655 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1656 | (const_int 0))) | |
1657 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1658 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1659 | [(set (match_dup 3) |
1660 | (minus:SI (match_dup 1) | |
1661 | (match_dup 2))) | |
1662 | (set (match_dup 0) | |
1663 | (compare:CC (match_dup 3) | |
1664 | (const_int 0)))] | |
1665 | "") | |
deb9225a | 1666 | |
1fd4e8c1 | 1667 | (define_insn "" |
cb8cc086 MM |
1668 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1669 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1670 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1671 | (const_int 0))) |
cb8cc086 | 1672 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1673 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1674 | "! TARGET_POWERPC" |
cb8cc086 MM |
1675 | "@ |
1676 | {sf.|subfc.} %0,%2,%1 | |
1677 | #" | |
1678 | [(set_attr "type" "compare") | |
1679 | (set_attr "length" "4,8")]) | |
815cdc52 | 1680 | |
29ae5b89 | 1681 | (define_insn "" |
cb8cc086 MM |
1682 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1683 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1684 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1685 | (const_int 0))) |
cb8cc086 MM |
1686 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1687 | (minus:SI (match_dup 1) | |
1688 | (match_dup 2)))] | |
0ad91047 | 1689 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1690 | "@ |
1691 | subf. %0,%2,%1 | |
1692 | #" | |
cb8cc086 MM |
1693 | [(set_attr "type" "compare") |
1694 | (set_attr "length" "4,8")]) | |
1695 | ||
1696 | (define_split | |
1697 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1698 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1699 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1700 | (const_int 0))) | |
1701 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1702 | (minus:SI (match_dup 1) | |
1703 | (match_dup 2)))] | |
0ad91047 | 1704 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1705 | [(set (match_dup 0) |
1706 | (minus:SI (match_dup 1) | |
1707 | (match_dup 2))) | |
1708 | (set (match_dup 3) | |
1709 | (compare:CC (match_dup 0) | |
1710 | (const_int 0)))] | |
1711 | "") | |
deb9225a | 1712 | |
1fd4e8c1 | 1713 | (define_expand "subsi3" |
cd2b37d9 | 1714 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1715 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1716 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1717 | "" |
a0044fb1 RK |
1718 | " |
1719 | { | |
1720 | if (GET_CODE (operands[2]) == CONST_INT) | |
1721 | { | |
1722 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1723 | negate_rtx (SImode, operands[2]))); | |
1724 | DONE; | |
1725 | } | |
1726 | }") | |
1fd4e8c1 RK |
1727 | |
1728 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1729 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1730 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1731 | ;; combine. | |
1fd4e8c1 RK |
1732 | |
1733 | (define_expand "sminsi3" | |
1734 | [(set (match_dup 3) | |
cd2b37d9 | 1735 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1736 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1737 | (const_int 0) | |
1738 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1739 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1740 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1741 | "TARGET_POWER" |
1fd4e8c1 RK |
1742 | " |
1743 | { operands[3] = gen_reg_rtx (SImode); }") | |
1744 | ||
95ac8e67 RK |
1745 | (define_split |
1746 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1747 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1748 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1749 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1750 | "TARGET_POWER" |
95ac8e67 RK |
1751 | [(set (match_dup 3) |
1752 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1753 | (const_int 0) | |
1754 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1755 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1756 | "") | |
1757 | ||
1fd4e8c1 RK |
1758 | (define_expand "smaxsi3" |
1759 | [(set (match_dup 3) | |
cd2b37d9 | 1760 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1761 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1762 | (const_int 0) | |
1763 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1764 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1765 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1766 | "TARGET_POWER" |
1fd4e8c1 RK |
1767 | " |
1768 | { operands[3] = gen_reg_rtx (SImode); }") | |
1769 | ||
95ac8e67 RK |
1770 | (define_split |
1771 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1772 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1773 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1774 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1775 | "TARGET_POWER" |
95ac8e67 RK |
1776 | [(set (match_dup 3) |
1777 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1778 | (const_int 0) | |
1779 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1780 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1781 | "") | |
1782 | ||
1fd4e8c1 | 1783 | (define_expand "uminsi3" |
cd2b37d9 | 1784 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1785 | (match_dup 5))) |
cd2b37d9 | 1786 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1787 | (match_dup 5))) |
1fd4e8c1 RK |
1788 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1789 | (const_int 0) | |
1790 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1791 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1792 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1793 | "TARGET_POWER" |
1fd4e8c1 | 1794 | " |
bb68ff55 MM |
1795 | { |
1796 | operands[3] = gen_reg_rtx (SImode); | |
1797 | operands[4] = gen_reg_rtx (SImode); | |
1798 | operands[5] = GEN_INT (-2147483647 - 1); | |
1799 | }") | |
1fd4e8c1 RK |
1800 | |
1801 | (define_expand "umaxsi3" | |
cd2b37d9 | 1802 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1803 | (match_dup 5))) |
cd2b37d9 | 1804 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1805 | (match_dup 5))) |
1fd4e8c1 RK |
1806 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1807 | (const_int 0) | |
1808 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1809 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1810 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1811 | "TARGET_POWER" |
1fd4e8c1 | 1812 | " |
bb68ff55 MM |
1813 | { |
1814 | operands[3] = gen_reg_rtx (SImode); | |
1815 | operands[4] = gen_reg_rtx (SImode); | |
1816 | operands[5] = GEN_INT (-2147483647 - 1); | |
1817 | }") | |
1fd4e8c1 RK |
1818 | |
1819 | (define_insn "" | |
cd2b37d9 RK |
1820 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1821 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1822 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1823 | (const_int 0) |
1824 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1825 | "TARGET_POWER" |
1fd4e8c1 RK |
1826 | "doz%I2 %0,%1,%2") |
1827 | ||
1828 | (define_insn "" | |
9ebbca7d | 1829 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1830 | (compare:CC |
9ebbca7d GK |
1831 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1832 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1833 | (const_int 0) |
1834 | (minus:SI (match_dup 2) (match_dup 1))) | |
1835 | (const_int 0))) | |
9ebbca7d | 1836 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1837 | "TARGET_POWER" |
9ebbca7d GK |
1838 | "@ |
1839 | doz%I2. %3,%1,%2 | |
1840 | #" | |
1841 | [(set_attr "type" "delayed_compare") | |
1842 | (set_attr "length" "4,8")]) | |
1843 | ||
1844 | (define_split | |
1845 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1846 | (compare:CC | |
1847 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1848 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1849 | (const_int 0) | |
1850 | (minus:SI (match_dup 2) (match_dup 1))) | |
1851 | (const_int 0))) | |
1852 | (clobber (match_scratch:SI 3 ""))] | |
1853 | "TARGET_POWER && reload_completed" | |
1854 | [(set (match_dup 3) | |
1855 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1856 | (const_int 0) | |
1857 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1858 | (set (match_dup 0) | |
1859 | (compare:CC (match_dup 3) | |
1860 | (const_int 0)))] | |
1861 | "") | |
1fd4e8c1 RK |
1862 | |
1863 | (define_insn "" | |
9ebbca7d | 1864 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1865 | (compare:CC |
9ebbca7d GK |
1866 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1867 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1868 | (const_int 0) |
1869 | (minus:SI (match_dup 2) (match_dup 1))) | |
1870 | (const_int 0))) | |
9ebbca7d | 1871 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1872 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1873 | (const_int 0) | |
1874 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1875 | "TARGET_POWER" |
9ebbca7d GK |
1876 | "@ |
1877 | doz%I2. %0,%1,%2 | |
1878 | #" | |
1879 | [(set_attr "type" "delayed_compare") | |
1880 | (set_attr "length" "4,8")]) | |
1881 | ||
1882 | (define_split | |
1883 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1884 | (compare:CC | |
1885 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1886 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1887 | (const_int 0) | |
1888 | (minus:SI (match_dup 2) (match_dup 1))) | |
1889 | (const_int 0))) | |
1890 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1891 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1892 | (const_int 0) | |
1893 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1894 | "TARGET_POWER && reload_completed" | |
1895 | [(set (match_dup 0) | |
1896 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1897 | (const_int 0) | |
1898 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1899 | (set (match_dup 3) | |
1900 | (compare:CC (match_dup 0) | |
1901 | (const_int 0)))] | |
1902 | "") | |
1fd4e8c1 RK |
1903 | |
1904 | ;; We don't need abs with condition code because such comparisons should | |
1905 | ;; never be done. | |
ea9be077 MM |
1906 | (define_expand "abssi2" |
1907 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1908 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1909 | "" | |
1910 | " | |
1911 | { | |
0ad91047 | 1912 | if (! TARGET_POWER) |
ea9be077 MM |
1913 | { |
1914 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1915 | DONE; | |
1916 | } | |
1917 | }") | |
1918 | ||
1919 | (define_insn "abssi2_power" | |
cd2b37d9 RK |
1920 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1921 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1922 | "TARGET_POWER" |
1fd4e8c1 RK |
1923 | "abs %0,%1") |
1924 | ||
ea9be077 MM |
1925 | (define_insn "abssi2_nopower" |
1926 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1927 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1928 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1929 | "! TARGET_POWER" |
3595d104 MM |
1930 | "* |
1931 | { | |
1932 | return (TARGET_POWERPC) | |
1933 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" | |
1934 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; | |
1935 | }" | |
ea9be077 MM |
1936 | [(set_attr "length" "12")]) |
1937 | ||
1938 | (define_split | |
1939 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1940 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1941 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1942 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
1943 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1944 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1945 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1946 | "") |
1947 | ||
463b558b | 1948 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1949 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1950 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1951 | "TARGET_POWER" |
1fd4e8c1 RK |
1952 | "nabs %0,%1") |
1953 | ||
463b558b | 1954 | (define_insn "*nabs_no_power" |
ea9be077 MM |
1955 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
1956 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1957 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1958 | "! TARGET_POWER" |
3595d104 MM |
1959 | "* |
1960 | { | |
1961 | return (TARGET_POWERPC) | |
1962 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" | |
1963 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; | |
1964 | }" | |
ea9be077 MM |
1965 | [(set_attr "length" "12")]) |
1966 | ||
1967 | (define_split | |
1968 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1969 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1970 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1971 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
1972 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1973 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1974 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1975 | "") |
1976 | ||
1fd4e8c1 | 1977 | (define_insn "negsi2" |
cd2b37d9 RK |
1978 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1979 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1980 | "" |
1981 | "neg %0,%1") | |
1982 | ||
1983 | (define_insn "" | |
9ebbca7d GK |
1984 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1985 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1986 | (const_int 0))) |
9ebbca7d | 1987 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1988 | "! TARGET_POWERPC64" |
9ebbca7d GK |
1989 | "@ |
1990 | neg. %2,%1 | |
1991 | #" | |
1992 | [(set_attr "type" "compare") | |
1993 | (set_attr "length" "4,8")]) | |
1994 | ||
1995 | (define_split | |
1996 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1997 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1998 | (const_int 0))) | |
1999 | (clobber (match_scratch:SI 2 ""))] | |
2000 | "! TARGET_POWERPC64 && reload_completed" | |
2001 | [(set (match_dup 2) | |
2002 | (neg:SI (match_dup 1))) | |
2003 | (set (match_dup 0) | |
2004 | (compare:CC (match_dup 2) | |
2005 | (const_int 0)))] | |
2006 | "") | |
1fd4e8c1 RK |
2007 | |
2008 | (define_insn "" | |
9ebbca7d GK |
2009 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
2010 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2011 | (const_int 0))) |
9ebbca7d | 2012 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 2013 | (neg:SI (match_dup 1)))] |
0ad91047 | 2014 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2015 | "@ |
2016 | neg. %0,%1 | |
2017 | #" | |
2018 | [(set_attr "type" "compare") | |
2019 | (set_attr "length" "4,8")]) | |
2020 | ||
2021 | (define_split | |
2022 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
2023 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2024 | (const_int 0))) | |
2025 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2026 | (neg:SI (match_dup 1)))] | |
2027 | "! TARGET_POWERPC64 && reload_completed" | |
2028 | [(set (match_dup 0) | |
2029 | (neg:SI (match_dup 1))) | |
2030 | (set (match_dup 2) | |
2031 | (compare:CC (match_dup 0) | |
2032 | (const_int 0)))] | |
2033 | "") | |
1fd4e8c1 RK |
2034 | |
2035 | (define_insn "ffssi2" | |
242e8072 RK |
2036 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
2037 | (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 2038 | "" |
7f340546 | 2039 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 2040 | [(set_attr "length" "16")]) |
1fd4e8c1 | 2041 | |
ca7f5001 RK |
2042 | (define_expand "mulsi3" |
2043 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2044 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2045 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
2046 | "" | |
2047 | " | |
2048 | { | |
2049 | if (TARGET_POWER) | |
68b40e7e | 2050 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 2051 | else |
68b40e7e | 2052 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2053 | DONE; |
2054 | }") | |
2055 | ||
68b40e7e | 2056 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
2057 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2058 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
2059 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
2060 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
2061 | "TARGET_POWER" |
2062 | "@ | |
2063 | {muls|mullw} %0,%1,%2 | |
2064 | {muli|mulli} %0,%1,%2" | |
2065 | [(set_attr "type" "imul")]) | |
2066 | ||
68b40e7e | 2067 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
2068 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2069 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2070 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 2071 | "! TARGET_POWER" |
1fd4e8c1 | 2072 | "@ |
d904e9ed RK |
2073 | {muls|mullw} %0,%1,%2 |
2074 | {muli|mulli} %0,%1,%2" | |
cfb557c4 | 2075 | [(set_attr "type" "imul")]) |
1fd4e8c1 RK |
2076 | |
2077 | (define_insn "" | |
9ebbca7d GK |
2078 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2079 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2080 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2081 | (const_int 0))) |
9ebbca7d GK |
2082 | (clobber (match_scratch:SI 3 "=r,r")) |
2083 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 2084 | "TARGET_POWER" |
9ebbca7d GK |
2085 | "@ |
2086 | {muls.|mullw.} %3,%1,%2 | |
2087 | #" | |
2088 | [(set_attr "type" "delayed_compare") | |
2089 | (set_attr "length" "4,8")]) | |
2090 | ||
2091 | (define_split | |
2092 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2093 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2094 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2095 | (const_int 0))) | |
2096 | (clobber (match_scratch:SI 3 "")) | |
2097 | (clobber (match_scratch:SI 4 ""))] | |
2098 | "TARGET_POWER && reload_completed" | |
2099 | [(parallel [(set (match_dup 3) | |
2100 | (mult:SI (match_dup 1) (match_dup 2))) | |
2101 | (clobber (match_dup 4))]) | |
2102 | (set (match_dup 0) | |
2103 | (compare:CC (match_dup 3) | |
2104 | (const_int 0)))] | |
2105 | "") | |
ca7f5001 RK |
2106 | |
2107 | (define_insn "" | |
9ebbca7d GK |
2108 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2109 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2110 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2111 | (const_int 0))) |
9ebbca7d | 2112 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 2113 | "! TARGET_POWER" |
9ebbca7d GK |
2114 | "@ |
2115 | {muls.|mullw.} %3,%1,%2 | |
2116 | #" | |
2117 | [(set_attr "type" "delayed_compare") | |
2118 | (set_attr "length" "4,8")]) | |
2119 | ||
2120 | (define_split | |
2121 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2122 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2123 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2124 | (const_int 0))) | |
2125 | (clobber (match_scratch:SI 3 ""))] | |
2126 | "! TARGET_POWER && reload_completed" | |
2127 | [(set (match_dup 3) | |
2128 | (mult:SI (match_dup 1) (match_dup 2))) | |
2129 | (set (match_dup 0) | |
2130 | (compare:CC (match_dup 3) | |
2131 | (const_int 0)))] | |
2132 | "") | |
1fd4e8c1 RK |
2133 | |
2134 | (define_insn "" | |
9ebbca7d GK |
2135 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2136 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2137 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2138 | (const_int 0))) |
9ebbca7d | 2139 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2140 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 2141 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 2142 | "TARGET_POWER" |
9ebbca7d GK |
2143 | "@ |
2144 | {muls.|mullw.} %0,%1,%2 | |
2145 | #" | |
2146 | [(set_attr "type" "delayed_compare") | |
2147 | (set_attr "length" "4,8")]) | |
2148 | ||
2149 | (define_split | |
2150 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2151 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2152 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2153 | (const_int 0))) | |
2154 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2155 | (mult:SI (match_dup 1) (match_dup 2))) | |
2156 | (clobber (match_scratch:SI 4 ""))] | |
2157 | "TARGET_POWER && reload_completed" | |
2158 | [(parallel [(set (match_dup 0) | |
2159 | (mult:SI (match_dup 1) (match_dup 2))) | |
2160 | (clobber (match_dup 4))]) | |
2161 | (set (match_dup 3) | |
2162 | (compare:CC (match_dup 0) | |
2163 | (const_int 0)))] | |
2164 | "") | |
ca7f5001 RK |
2165 | |
2166 | (define_insn "" | |
9ebbca7d GK |
2167 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2168 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2169 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2170 | (const_int 0))) |
9ebbca7d | 2171 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 2172 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 2173 | "! TARGET_POWER" |
9ebbca7d GK |
2174 | "@ |
2175 | {muls.|mullw.} %0,%1,%2 | |
2176 | #" | |
2177 | [(set_attr "type" "delayed_compare") | |
2178 | (set_attr "length" "4,8")]) | |
2179 | ||
2180 | (define_split | |
2181 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2182 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2183 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2184 | (const_int 0))) | |
2185 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2186 | (mult:SI (match_dup 1) (match_dup 2)))] | |
2187 | "! TARGET_POWER && reload_completed" | |
2188 | [(set (match_dup 0) | |
2189 | (mult:SI (match_dup 1) (match_dup 2))) | |
2190 | (set (match_dup 3) | |
2191 | (compare:CC (match_dup 0) | |
2192 | (const_int 0)))] | |
2193 | "") | |
1fd4e8c1 RK |
2194 | |
2195 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
2196 | ;; 0 and remainder to operand 3. | |
2197 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
2198 | ||
8ffd9c51 RK |
2199 | (define_expand "divmodsi4" |
2200 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2201 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2202 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2203 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
2204 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
2205 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2206 | " | |
2207 | { | |
2208 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2209 | { | |
39403d82 DE |
2210 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2211 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2212 | emit_insn (gen_divss_call ()); |
39403d82 DE |
2213 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2214 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
2215 | DONE; |
2216 | } | |
2217 | }") | |
deb9225a | 2218 | |
fada905b | 2219 | (define_insn "" |
cd2b37d9 RK |
2220 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2221 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2222 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2223 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 2224 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 2225 | "TARGET_POWER" |
cfb557c4 RK |
2226 | "divs %0,%1,%2" |
2227 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 2228 | |
8ffd9c51 RK |
2229 | (define_expand "udivsi3" |
2230 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2231 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2232 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
2233 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2234 | " | |
2235 | { | |
2236 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2237 | { | |
39403d82 DE |
2238 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2239 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2240 | emit_insn (gen_quous_call ()); |
39403d82 | 2241 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2242 | DONE; |
2243 | } | |
f192bf8b DE |
2244 | else if (TARGET_POWER) |
2245 | { | |
2246 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
2247 | DONE; | |
2248 | } | |
8ffd9c51 | 2249 | }") |
deb9225a | 2250 | |
f192bf8b DE |
2251 | (define_insn "udivsi3_mq" |
2252 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2253 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2254 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2255 | (clobber (match_scratch:SI 3 "=q"))] | |
2256 | "TARGET_POWERPC && TARGET_POWER" | |
2257 | "divwu %0,%1,%2" | |
2258 | [(set_attr "type" "idiv")]) | |
2259 | ||
2260 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
2261 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2262 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2263 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 2264 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 2265 | "divwu %0,%1,%2" |
ca7f5001 RK |
2266 | [(set_attr "type" "idiv")]) |
2267 | ||
1fd4e8c1 | 2268 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 2269 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
2270 | ;; used; for PowerPC, force operands into register and do a normal divide; |
2271 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 2272 | (define_expand "divsi3" |
cd2b37d9 RK |
2273 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2274 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
2275 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
2276 | "" | |
2277 | " | |
2278 | { | |
ca7f5001 RK |
2279 | if (GET_CODE (operands[2]) == CONST_INT |
2280 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
2281 | ; | |
b6c9286a | 2282 | else if (TARGET_POWERPC) |
f192bf8b DE |
2283 | { |
2284 | operands[2] = force_reg (SImode, operands[2]); | |
2285 | if (TARGET_POWER) | |
2286 | { | |
2287 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
2288 | DONE; | |
2289 | } | |
2290 | } | |
b6c9286a | 2291 | else if (TARGET_POWER) |
1fd4e8c1 | 2292 | FAIL; |
405c5495 | 2293 | else |
8ffd9c51 | 2294 | { |
39403d82 DE |
2295 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2296 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2297 | emit_insn (gen_quoss_call ()); |
39403d82 | 2298 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2299 | DONE; |
2300 | } | |
1fd4e8c1 RK |
2301 | }") |
2302 | ||
f192bf8b DE |
2303 | (define_insn "divsi3_mq" |
2304 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2305 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2306 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2307 | (clobber (match_scratch:SI 3 "=q"))] | |
2308 | "TARGET_POWERPC && TARGET_POWER" | |
2309 | "divw %0,%1,%2" | |
2310 | [(set_attr "type" "idiv")]) | |
2311 | ||
2312 | (define_insn "*divsi3_no_mq" | |
2313 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2314 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2315 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
2316 | "TARGET_POWERPC && ! TARGET_POWER" | |
2317 | "divw %0,%1,%2" | |
2318 | [(set_attr "type" "idiv")]) | |
2319 | ||
1fd4e8c1 | 2320 | (define_expand "modsi3" |
85644414 RK |
2321 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
2322 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 2323 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 2324 | "" |
1fd4e8c1 RK |
2325 | " |
2326 | { | |
481c7efa | 2327 | int i; |
39b52ba2 RK |
2328 | rtx temp1; |
2329 | rtx temp2; | |
2330 | ||
481c7efa FS |
2331 | if (GET_CODE (operands[2]) != CONST_INT) |
2332 | FAIL; | |
2333 | ||
2334 | i = exact_log2 (INTVAL (operands[2])); | |
2335 | ||
2336 | if (i < 0) | |
39b52ba2 RK |
2337 | FAIL; |
2338 | ||
2339 | temp1 = gen_reg_rtx (SImode); | |
2340 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 2341 | |
85644414 | 2342 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 2343 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
2344 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
2345 | DONE; | |
1fd4e8c1 RK |
2346 | }") |
2347 | ||
2348 | (define_insn "" | |
cd2b37d9 RK |
2349 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2350 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2351 | (match_operand:SI 2 "const_int_operand" "N")))] |
2352 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
ca7f5001 | 2353 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 2354 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
2355 | |
2356 | (define_insn "" | |
9ebbca7d GK |
2357 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2358 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2359 | (match_operand:SI 2 "const_int_operand" "N,N")) | |
b6b12107 | 2360 | (const_int 0))) |
9ebbca7d | 2361 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 2362 | "exact_log2 (INTVAL (operands[2])) >= 0" |
9ebbca7d GK |
2363 | "@ |
2364 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
2365 | #" | |
b19003d8 | 2366 | [(set_attr "type" "compare") |
9ebbca7d GK |
2367 | (set_attr "length" "8,12")]) |
2368 | ||
2369 | (define_split | |
2370 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2371 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2372 | (match_operand:SI 2 "const_int_operand" "")) | |
2373 | (const_int 0))) | |
2374 | (clobber (match_scratch:SI 3 ""))] | |
2375 | "exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
2376 | [(set (match_dup 3) | |
2377 | (div:SI (match_dup 1) (match_dup 2))) | |
2378 | (set (match_dup 0) | |
2379 | (compare:CC (match_dup 3) | |
2380 | (const_int 0)))] | |
2381 | "") | |
1fd4e8c1 RK |
2382 | |
2383 | (define_insn "" | |
9ebbca7d GK |
2384 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2385 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2386 | (match_operand:SI 2 "const_int_operand" "N,N")) | |
b6b12107 | 2387 | (const_int 0))) |
9ebbca7d | 2388 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2389 | (div:SI (match_dup 1) (match_dup 2)))] |
1fd4e8c1 | 2390 | "exact_log2 (INTVAL (operands[2])) >= 0" |
9ebbca7d GK |
2391 | "@ |
2392 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2393 | #" | |
b19003d8 | 2394 | [(set_attr "type" "compare") |
9ebbca7d GK |
2395 | (set_attr "length" "8,12")]) |
2396 | ||
2397 | (define_split | |
2398 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2399 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2400 | (match_operand:SI 2 "const_int_operand" "")) | |
2401 | (const_int 0))) | |
2402 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2403 | (div:SI (match_dup 1) (match_dup 2)))] | |
2404 | "exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
2405 | [(set (match_dup 0) | |
2406 | (div:SI (match_dup 1) (match_dup 2))) | |
2407 | (set (match_dup 3) | |
2408 | (compare:CC (match_dup 0) | |
2409 | (const_int 0)))] | |
2410 | "") | |
1fd4e8c1 RK |
2411 | |
2412 | (define_insn "" | |
cd2b37d9 | 2413 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2414 | (udiv:SI |
996a5f59 | 2415 | (plus:DI (ashift:DI |
cd2b37d9 | 2416 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2417 | (const_int 32)) |
23a900dc | 2418 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2419 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2420 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2421 | (umod:SI |
996a5f59 | 2422 | (plus:DI (ashift:DI |
1fd4e8c1 | 2423 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2424 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2425 | (match_dup 3)))] |
ca7f5001 | 2426 | "TARGET_POWER" |
cfb557c4 RK |
2427 | "div %0,%1,%3" |
2428 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2429 | |
2430 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2431 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2432 | ;; have to worry about the branches. So make a few subroutines here. | |
2433 | ;; | |
2434 | ;; First comes the normal case. | |
2435 | (define_expand "udivmodsi4_normal" | |
2436 | [(set (match_dup 4) (const_int 0)) | |
2437 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2438 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2439 | (const_int 32)) |
2440 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2441 | (match_operand:SI 2 "" ""))) | |
2442 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2443 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2444 | (const_int 32)) |
2445 | (zero_extend:DI (match_dup 1))) | |
2446 | (match_dup 2)))])] | |
ca7f5001 | 2447 | "TARGET_POWER" |
1fd4e8c1 RK |
2448 | " |
2449 | { operands[4] = gen_reg_rtx (SImode); }") | |
2450 | ||
2451 | ;; This handles the branches. | |
2452 | (define_expand "udivmodsi4_tests" | |
2453 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2454 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2455 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2456 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2457 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2458 | (set (match_dup 0) (const_int 1)) | |
2459 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2460 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2461 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2462 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2463 | "TARGET_POWER" |
1fd4e8c1 RK |
2464 | " |
2465 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2466 | operands[6] = gen_reg_rtx (CCmode); | |
2467 | }") | |
2468 | ||
2469 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2470 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2471 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2472 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2473 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2474 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2475 | "" |
1fd4e8c1 RK |
2476 | " |
2477 | { | |
2478 | rtx label = 0; | |
2479 | ||
8ffd9c51 | 2480 | if (! TARGET_POWER) |
c4d38ccb MM |
2481 | { |
2482 | if (! TARGET_POWERPC) | |
2483 | { | |
39403d82 DE |
2484 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2485 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2486 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2487 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2488 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2489 | DONE; |
2490 | } | |
2491 | else | |
2492 | FAIL; | |
2493 | } | |
0081a354 | 2494 | |
1fd4e8c1 RK |
2495 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2496 | { | |
2497 | operands[2] = force_reg (SImode, operands[2]); | |
2498 | label = gen_label_rtx (); | |
2499 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2500 | operands[3], label)); | |
2501 | } | |
2502 | else | |
2503 | operands[2] = force_reg (SImode, operands[2]); | |
2504 | ||
2505 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2506 | operands[3])); | |
2507 | if (label) | |
2508 | emit_label (label); | |
2509 | ||
2510 | DONE; | |
2511 | }") | |
0081a354 | 2512 | |
fada905b MM |
2513 | ;; AIX architecture-independent common-mode multiply (DImode), |
2514 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2515 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2516 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2517 | ;; assumed unused if generating common-mode, so ignore. | |
2518 | (define_insn "mulh_call" | |
2519 | [(set (reg:SI 3) | |
2520 | (truncate:SI | |
2521 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2522 | (sign_extend:DI (reg:SI 4))) | |
2523 | (const_int 32)))) | |
cf27b467 | 2524 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2525 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2526 | "bla __mulh" |
2527 | [(set_attr "type" "imul")]) | |
fada905b MM |
2528 | |
2529 | (define_insn "mull_call" | |
2530 | [(set (reg:DI 3) | |
2531 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2532 | (sign_extend:DI (reg:SI 4)))) | |
2533 | (clobber (match_scratch:SI 0 "=l")) | |
2534 | (clobber (reg:SI 0))] | |
2535 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2536 | "bla __mull" |
2537 | [(set_attr "type" "imul")]) | |
fada905b MM |
2538 | |
2539 | (define_insn "divss_call" | |
2540 | [(set (reg:SI 3) | |
2541 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2542 | (set (reg:SI 4) | |
2543 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2544 | (clobber (match_scratch:SI 0 "=l")) | |
2545 | (clobber (reg:SI 0))] | |
2546 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2547 | "bla __divss" |
2548 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2549 | |
2550 | (define_insn "divus_call" | |
8ffd9c51 RK |
2551 | [(set (reg:SI 3) |
2552 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2553 | (set (reg:SI 4) | |
2554 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2555 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2556 | (clobber (reg:SI 0)) |
2557 | (clobber (match_scratch:CC 1 "=x")) | |
2558 | (clobber (reg:CC 69))] | |
2559 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2560 | "bla __divus" |
2561 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2562 | |
2563 | (define_insn "quoss_call" | |
2564 | [(set (reg:SI 3) | |
2565 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2566 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2567 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2568 | "bla __quoss" |
2569 | [(set_attr "type" "idiv")]) | |
0081a354 | 2570 | |
fada905b MM |
2571 | (define_insn "quous_call" |
2572 | [(set (reg:SI 3) | |
2573 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2574 | (clobber (match_scratch:SI 0 "=l")) | |
2575 | (clobber (reg:SI 0)) | |
2576 | (clobber (match_scratch:CC 1 "=x")) | |
2577 | (clobber (reg:CC 69))] | |
2578 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2579 | "bla __quous" |
2580 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2581 | \f |
bb21487f | 2582 | ;; Logical instructions |
dfbdccdb GK |
2583 | ;; The logical instructions are mostly combined by using match_operator, |
2584 | ;; but the plain AND insns are somewhat different because there is no | |
2585 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2586 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2587 | ||
29ae5b89 JL |
2588 | (define_insn "andsi3" |
2589 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2590 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2591 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2592 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2593 | "" |
2594 | "@ | |
2595 | and %0,%1,%2 | |
ca7f5001 RK |
2596 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2597 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2598 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2599 | |
2600 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
2601 | ;; the test again -- this avoids a mcrf which on the higher end | |
2602 | ;; machines causes an execution serialization | |
1fd4e8c1 | 2603 | |
7cd5235b | 2604 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2605 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2606 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2607 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2608 | (const_int 0))) |
52d3af72 DE |
2609 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2610 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2611 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2612 | "@ |
2613 | and. %3,%1,%2 | |
ca7f5001 RK |
2614 | {andil.|andi.} %3,%1,%b2 |
2615 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2616 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2617 | # | |
2618 | # | |
2619 | # | |
2620 | #" | |
2621 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2622 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2623 | |
52d3af72 DE |
2624 | (define_split |
2625 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2626 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2627 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2628 | (const_int 0))) |
52d3af72 DE |
2629 | (clobber (match_scratch:SI 3 "")) |
2630 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2631 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2632 | [(parallel [(set (match_dup 3) |
2633 | (and:SI (match_dup 1) | |
2634 | (match_dup 2))) | |
2635 | (clobber (match_dup 4))]) | |
2636 | (set (match_dup 0) | |
2637 | (compare:CC (match_dup 3) | |
2638 | (const_int 0)))] | |
2639 | "") | |
2640 | ||
2641 | (define_insn "*andsi3_internal3" | |
2642 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2643 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2644 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2645 | (const_int 0))) |
2646 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2647 | (and:SI (match_dup 1) | |
2648 | (match_dup 2))) | |
2649 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2650 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2651 | "@ |
2652 | and. %0,%1,%2 | |
ca7f5001 RK |
2653 | {andil.|andi.} %0,%1,%b2 |
2654 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2655 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2656 | # | |
2657 | # | |
2658 | # | |
2659 | #" | |
2660 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2661 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2662 | ||
2663 | (define_split | |
2664 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2665 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2666 | (match_operand:SI 2 "and_operand" "")) | |
2667 | (const_int 0))) | |
2668 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2669 | (and:SI (match_dup 1) | |
2670 | (match_dup 2))) | |
2671 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2672 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2673 | [(parallel [(set (match_dup 0) |
2674 | (and:SI (match_dup 1) | |
2675 | (match_dup 2))) | |
2676 | (clobber (match_dup 4))]) | |
2677 | (set (match_dup 3) | |
2678 | (compare:CC (match_dup 0) | |
2679 | (const_int 0)))] | |
2680 | "") | |
1fd4e8c1 | 2681 | |
7cd5235b | 2682 | (define_expand "iorsi3" |
cd2b37d9 | 2683 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2684 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2685 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2686 | "" |
f357808b RK |
2687 | " |
2688 | { | |
7cd5235b | 2689 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2690 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2691 | { |
2692 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2693 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2694 | ? operands[0] : gen_reg_rtx (SImode)); |
2695 | ||
a260abc9 DE |
2696 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2697 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2698 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2699 | DONE; |
2700 | } | |
f357808b RK |
2701 | }") |
2702 | ||
7cd5235b | 2703 | (define_expand "xorsi3" |
cd2b37d9 | 2704 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2705 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2706 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2707 | "" |
7cd5235b | 2708 | " |
1fd4e8c1 | 2709 | { |
7cd5235b | 2710 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2711 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2712 | { |
2713 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2714 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2715 | ? operands[0] : gen_reg_rtx (SImode)); |
2716 | ||
a260abc9 DE |
2717 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2718 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2719 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2720 | DONE; |
2721 | } | |
1fd4e8c1 RK |
2722 | }") |
2723 | ||
dfbdccdb | 2724 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2725 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2726 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2727 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2728 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2729 | "" |
2730 | "@ | |
dfbdccdb GK |
2731 | %q3 %0,%1,%2 |
2732 | {%q3il|%q3i} %0,%1,%b2 | |
2733 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2734 | |
dfbdccdb | 2735 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2736 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2737 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2738 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2739 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2740 | (const_int 0))) | |
52d3af72 | 2741 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2742 | "! TARGET_POWERPC64" |
52d3af72 | 2743 | "@ |
dfbdccdb | 2744 | %q4. %3,%1,%2 |
52d3af72 DE |
2745 | #" |
2746 | [(set_attr "type" "compare") | |
2747 | (set_attr "length" "4,8")]) | |
2748 | ||
2749 | (define_split | |
2750 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2751 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2752 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2753 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2754 | (const_int 0))) | |
52d3af72 | 2755 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2756 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2757 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2758 | (set (match_dup 0) |
2759 | (compare:CC (match_dup 3) | |
2760 | (const_int 0)))] | |
2761 | "") | |
815cdc52 | 2762 | |
dfbdccdb | 2763 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2764 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2765 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2766 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2767 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2768 | (const_int 0))) | |
52d3af72 | 2769 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2770 | (match_dup 4))] |
0ad91047 | 2771 | "! TARGET_POWERPC64" |
52d3af72 | 2772 | "@ |
dfbdccdb | 2773 | %q4. %0,%1,%2 |
52d3af72 DE |
2774 | #" |
2775 | [(set_attr "type" "compare") | |
2776 | (set_attr "length" "4,8")]) | |
2777 | ||
2778 | (define_split | |
dfbdccdb GK |
2779 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2780 | (compare:CC (match_operator:SI 4 "boolean_operator" | |
2781 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2782 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2783 | (const_int 0))) | |
2784 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
2785 | (match_dup 4))] | |
0ad91047 | 2786 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2787 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2788 | (set (match_dup 3) |
2789 | (compare:CC (match_dup 0) | |
2790 | (const_int 0)))] | |
2791 | "") | |
1fd4e8c1 | 2792 | |
dfbdccdb GK |
2793 | ;; Split an logical operation that we can't do in one insn into two insns, |
2794 | ;; each of which does one 16-bit part. This is used by combine. | |
a260abc9 DE |
2795 | |
2796 | (define_split | |
2797 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2798 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2799 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2800 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2801 | "" |
dfbdccdb GK |
2802 | [(set (match_dup 0) (match_dup 4)) |
2803 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2804 | " |
2805 | { | |
dfbdccdb GK |
2806 | rtx i; |
2807 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2808 | operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2809 | operands[1], i); | |
2810 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2811 | operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2812 | operands[0], i); | |
a260abc9 DE |
2813 | }") |
2814 | ||
dfbdccdb | 2815 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2816 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2817 | (match_operator:SI 3 "boolean_operator" |
2818 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2819 | (match_operand:SI 2 "logical_operand" "r")]))] | |
1fd4e8c1 | 2820 | "" |
dfbdccdb | 2821 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2822 | |
dfbdccdb | 2823 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2824 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2825 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2826 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2827 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2828 | (const_int 0))) | |
52d3af72 | 2829 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2830 | "! TARGET_POWERPC64" |
52d3af72 | 2831 | "@ |
dfbdccdb | 2832 | %q4. %3,%2,%1 |
52d3af72 DE |
2833 | #" |
2834 | [(set_attr "type" "compare") | |
2835 | (set_attr "length" "4,8")]) | |
2836 | ||
2837 | (define_split | |
2838 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2839 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2840 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2841 | (match_operand:SI 2 "gpc_reg_operand" "r")]) | |
2842 | (const_int 0))) | |
52d3af72 | 2843 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2844 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2845 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2846 | (set (match_dup 0) |
2847 | (compare:CC (match_dup 3) | |
2848 | (const_int 0)))] | |
2849 | "") | |
1fd4e8c1 | 2850 | |
dfbdccdb | 2851 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2852 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2853 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2854 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2855 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2856 | (const_int 0))) | |
52d3af72 | 2857 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2858 | (match_dup 4))] |
0ad91047 | 2859 | "! TARGET_POWERPC64" |
52d3af72 | 2860 | "@ |
dfbdccdb | 2861 | %q4. %0,%2,%1 |
52d3af72 DE |
2862 | #" |
2863 | [(set_attr "type" "compare") | |
2864 | (set_attr "length" "4,8")]) | |
2865 | ||
2866 | (define_split | |
52d3af72 | 2867 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2868 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2869 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2870 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2871 | (const_int 0))) | |
52d3af72 | 2872 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2873 | (match_dup 4))] |
0ad91047 | 2874 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2875 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2876 | (set (match_dup 3) |
2877 | (compare:CC (match_dup 0) | |
2878 | (const_int 0)))] | |
2879 | "") | |
2880 | ||
dfbdccdb | 2881 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2882 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2883 | (match_operator:SI 3 "boolean_operator" |
2884 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2885 | (not:SI (match_operand:SI 2 "logical_operand" "r"))]))] | |
1fd4e8c1 | 2886 | "" |
dfbdccdb | 2887 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2888 | |
dfbdccdb | 2889 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2890 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2891 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2892 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2893 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2894 | (const_int 0))) | |
52d3af72 | 2895 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2896 | "! TARGET_POWERPC64" |
52d3af72 | 2897 | "@ |
dfbdccdb | 2898 | %q4. %3,%1,%2 |
52d3af72 DE |
2899 | #" |
2900 | [(set_attr "type" "compare") | |
2901 | (set_attr "length" "4,8")]) | |
2902 | ||
2903 | (define_split | |
2904 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2905 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2906 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2907 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]) | |
2908 | (const_int 0))) | |
52d3af72 | 2909 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2910 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2911 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2912 | (set (match_dup 0) |
2913 | (compare:CC (match_dup 3) | |
2914 | (const_int 0)))] | |
2915 | "") | |
1fd4e8c1 | 2916 | |
dfbdccdb | 2917 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2918 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2919 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2920 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2921 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2922 | (const_int 0))) | |
52d3af72 | 2923 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2924 | (match_dup 4))] |
0ad91047 | 2925 | "! TARGET_POWERPC64" |
52d3af72 | 2926 | "@ |
dfbdccdb | 2927 | %q4. %0,%1,%2 |
52d3af72 DE |
2928 | #" |
2929 | [(set_attr "type" "compare") | |
2930 | (set_attr "length" "4,8")]) | |
2931 | ||
2932 | (define_split | |
52d3af72 | 2933 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2934 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2935 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2936 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2937 | (const_int 0))) | |
52d3af72 | 2938 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2939 | (match_dup 4))] |
0ad91047 | 2940 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2941 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2942 | (set (match_dup 3) |
2943 | (compare:CC (match_dup 0) | |
2944 | (const_int 0)))] | |
2945 | "") | |
1fd4e8c1 RK |
2946 | |
2947 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2948 | ;; orders. Don't define forms that only set CR fields because these | |
2949 | ;; would modify an input register. | |
2950 | ||
7cd5235b | 2951 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2952 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2953 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2954 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2955 | (and:SI (match_dup 2) | |
cd2b37d9 | 2956 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2957 | "TARGET_POWER" |
01def764 | 2958 | "maskir %0,%3,%2") |
1fd4e8c1 | 2959 | |
7cd5235b | 2960 | (define_insn "*maskir_internal2" |
242e8072 | 2961 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2962 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2963 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2964 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2965 | (match_dup 2))))] |
ca7f5001 | 2966 | "TARGET_POWER" |
01def764 | 2967 | "maskir %0,%3,%2") |
1fd4e8c1 | 2968 | |
7cd5235b | 2969 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2970 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2971 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2972 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2973 | (and:SI (not:SI (match_dup 2)) |
2974 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2975 | "TARGET_POWER" |
01def764 | 2976 | "maskir %0,%3,%2") |
1fd4e8c1 | 2977 | |
7cd5235b | 2978 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2979 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2980 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2981 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2982 | (and:SI (not:SI (match_dup 2)) | |
2983 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2984 | "TARGET_POWER" |
01def764 | 2985 | "maskir %0,%3,%2") |
1fd4e8c1 | 2986 | |
7cd5235b | 2987 | (define_insn "*maskir_internal5" |
9ebbca7d | 2988 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2989 | (compare:CC |
9ebbca7d GK |
2990 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2991 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2992 | (and:SI (match_dup 2) |
9ebbca7d | 2993 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2994 | (const_int 0))) |
9ebbca7d | 2995 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2996 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2997 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2998 | "TARGET_POWER" |
9ebbca7d GK |
2999 | "@ |
3000 | maskir. %0,%3,%2 | |
3001 | #" | |
3002 | [(set_attr "type" "compare") | |
3003 | (set_attr "length" "4,8")]) | |
3004 | ||
3005 | (define_split | |
3006 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3007 | (compare:CC | |
3008 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3009 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3010 | (and:SI (match_dup 2) | |
3011 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
3012 | (const_int 0))) | |
3013 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3014 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3015 | (and:SI (match_dup 2) (match_dup 3))))] | |
3016 | "TARGET_POWER && reload_completed" | |
3017 | [(set (match_dup 0) | |
3018 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3019 | (and:SI (match_dup 2) (match_dup 3)))) | |
3020 | (set (match_dup 4) | |
3021 | (compare:CC (match_dup 0) | |
3022 | (const_int 0)))] | |
3023 | "") | |
1fd4e8c1 | 3024 | |
7cd5235b | 3025 | (define_insn "*maskir_internal6" |
9ebbca7d | 3026 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3027 | (compare:CC |
9ebbca7d GK |
3028 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3029 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
3030 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 3031 | (match_dup 2))) |
1fd4e8c1 | 3032 | (const_int 0))) |
9ebbca7d | 3033 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3034 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3035 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 3036 | "TARGET_POWER" |
9ebbca7d GK |
3037 | "@ |
3038 | maskir. %0,%3,%2 | |
3039 | #" | |
3040 | [(set_attr "type" "compare") | |
3041 | (set_attr "length" "4,8")]) | |
3042 | ||
3043 | (define_split | |
3044 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3045 | (compare:CC | |
3046 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3047 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3048 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3049 | (match_dup 2))) | |
3050 | (const_int 0))) | |
3051 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3052 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3053 | (and:SI (match_dup 3) (match_dup 2))))] | |
3054 | "TARGET_POWER && reload_completed" | |
3055 | [(set (match_dup 0) | |
3056 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3057 | (and:SI (match_dup 3) (match_dup 2)))) | |
3058 | (set (match_dup 4) | |
3059 | (compare:CC (match_dup 0) | |
3060 | (const_int 0)))] | |
3061 | "") | |
1fd4e8c1 | 3062 | |
7cd5235b | 3063 | (define_insn "*maskir_internal7" |
9ebbca7d | 3064 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 3065 | (compare:CC |
9ebbca7d GK |
3066 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
3067 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 3068 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3069 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 3070 | (const_int 0))) |
9ebbca7d | 3071 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
3072 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
3073 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3074 | "TARGET_POWER" | |
9ebbca7d GK |
3075 | "@ |
3076 | maskir. %0,%3,%2 | |
3077 | #" | |
3078 | [(set_attr "type" "compare") | |
3079 | (set_attr "length" "4,8")]) | |
3080 | ||
3081 | (define_split | |
3082 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3083 | (compare:CC | |
3084 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
3085 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
3086 | (and:SI (not:SI (match_dup 2)) | |
3087 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3088 | (const_int 0))) | |
3089 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3090 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3091 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3092 | "TARGET_POWER && reload_completed" | |
3093 | [(set (match_dup 0) | |
3094 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3095 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3096 | (set (match_dup 4) | |
3097 | (compare:CC (match_dup 0) | |
3098 | (const_int 0)))] | |
3099 | "") | |
1fd4e8c1 | 3100 | |
7cd5235b | 3101 | (define_insn "*maskir_internal8" |
9ebbca7d | 3102 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3103 | (compare:CC |
9ebbca7d GK |
3104 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
3105 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 3106 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3107 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 3108 | (const_int 0))) |
9ebbca7d | 3109 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3110 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
3111 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 3112 | "TARGET_POWER" |
9ebbca7d GK |
3113 | "@ |
3114 | maskir. %0,%3,%2 | |
3115 | #" | |
3116 | [(set_attr "type" "compare") | |
3117 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 3118 | \f |
9ebbca7d GK |
3119 | (define_split |
3120 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3121 | (compare:CC | |
3122 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3123 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3124 | (and:SI (not:SI (match_dup 2)) | |
3125 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3126 | (const_int 0))) | |
3127 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3128 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3129 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3130 | "TARGET_POWER && reload_completed" | |
3131 | [(set (match_dup 0) | |
3132 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3133 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3134 | (set (match_dup 4) | |
3135 | (compare:CC (match_dup 0) | |
3136 | (const_int 0)))] | |
3137 | "") | |
3138 | ||
1fd4e8c1 RK |
3139 | ;; Rotate and shift insns, in all their variants. These support shifts, |
3140 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 3141 | (define_expand "insv" |
0ad91047 DE |
3142 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
3143 | (match_operand:SI 1 "const_int_operand" "") | |
3144 | (match_operand:SI 2 "const_int_operand" "")) | |
3145 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
3146 | "" |
3147 | " | |
3148 | { | |
3149 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3150 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3151 | compiler if the address of the structure is taken later. */ | |
3152 | if (GET_CODE (operands[0]) == SUBREG | |
3153 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3154 | FAIL; | |
a78e33fc DE |
3155 | |
3156 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
3157 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
3158 | else | |
3159 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
3160 | DONE; | |
034c1be0 MM |
3161 | }") |
3162 | ||
a78e33fc | 3163 | (define_insn "insvsi" |
cd2b37d9 | 3164 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
3165 | (match_operand:SI 1 "const_int_operand" "i") |
3166 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 3167 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
3168 | "" |
3169 | "* | |
3170 | { | |
3171 | int start = INTVAL (operands[2]) & 31; | |
3172 | int size = INTVAL (operands[1]) & 31; | |
3173 | ||
89e9f3a8 MM |
3174 | operands[4] = GEN_INT (32 - start - size); |
3175 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3176 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
3177 | }") |
3178 | ||
a78e33fc | 3179 | (define_insn "*insvsi_internal1" |
d56d506a RK |
3180 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3181 | (match_operand:SI 1 "const_int_operand" "i") | |
3182 | (match_operand:SI 2 "const_int_operand" "i")) | |
3183 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3184 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3185 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3186 | "* |
3187 | { | |
3188 | int shift = INTVAL (operands[4]) & 31; | |
3189 | int start = INTVAL (operands[2]) & 31; | |
3190 | int size = INTVAL (operands[1]) & 31; | |
3191 | ||
89e9f3a8 MM |
3192 | operands[4] = GEN_INT (shift - start - size); |
3193 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3194 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3195 | }") |
3196 | ||
a78e33fc | 3197 | (define_insn "*insvsi_internal2" |
d56d506a RK |
3198 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3199 | (match_operand:SI 1 "const_int_operand" "i") | |
3200 | (match_operand:SI 2 "const_int_operand" "i")) | |
3201 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3202 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3203 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3204 | "* |
3205 | { | |
3206 | int shift = INTVAL (operands[4]) & 31; | |
3207 | int start = INTVAL (operands[2]) & 31; | |
3208 | int size = INTVAL (operands[1]) & 31; | |
3209 | ||
89e9f3a8 MM |
3210 | operands[4] = GEN_INT (32 - shift - start - size); |
3211 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3212 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3213 | }") |
3214 | ||
a78e33fc | 3215 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3216 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3217 | (match_operand:SI 1 "const_int_operand" "i") | |
3218 | (match_operand:SI 2 "const_int_operand" "i")) | |
3219 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3220 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3221 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3222 | "* |
3223 | { | |
3224 | int shift = INTVAL (operands[4]) & 31; | |
3225 | int start = INTVAL (operands[2]) & 31; | |
3226 | int size = INTVAL (operands[1]) & 31; | |
3227 | ||
89e9f3a8 MM |
3228 | operands[4] = GEN_INT (32 - shift - start - size); |
3229 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3230 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3231 | }") |
3232 | ||
a78e33fc | 3233 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3234 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3235 | (match_operand:SI 1 "const_int_operand" "i") | |
3236 | (match_operand:SI 2 "const_int_operand" "i")) | |
3237 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3238 | (match_operand:SI 4 "const_int_operand" "i") | |
3239 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3240 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3241 | "* | |
3242 | { | |
3243 | int extract_start = INTVAL (operands[5]) & 31; | |
3244 | int extract_size = INTVAL (operands[4]) & 31; | |
3245 | int insert_start = INTVAL (operands[2]) & 31; | |
3246 | int insert_size = INTVAL (operands[1]) & 31; | |
3247 | ||
3248 | /* Align extract field with insert field */ | |
3a598fbe | 3249 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3250 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3251 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
3252 | }") |
3253 | ||
a78e33fc | 3254 | (define_insn "insvdi" |
685f3906 | 3255 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3256 | (match_operand:SI 1 "const_int_operand" "i") |
3257 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3258 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3259 | "TARGET_POWERPC64" | |
3260 | "* | |
3261 | { | |
3262 | int start = INTVAL (operands[2]) & 63; | |
3263 | int size = INTVAL (operands[1]) & 63; | |
3264 | ||
a78e33fc DE |
3265 | operands[1] = GEN_INT (64 - start - size); |
3266 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3267 | }") |
3268 | ||
034c1be0 | 3269 | (define_expand "extzv" |
0ad91047 DE |
3270 | [(set (match_operand 0 "gpc_reg_operand" "") |
3271 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3272 | (match_operand:SI 2 "const_int_operand" "") | |
3273 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3274 | "" |
3275 | " | |
3276 | { | |
3277 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3278 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3279 | compiler if the address of the structure is taken later. */ | |
3280 | if (GET_CODE (operands[0]) == SUBREG | |
3281 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3282 | FAIL; | |
a78e33fc DE |
3283 | |
3284 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3285 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3286 | else | |
3287 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3288 | DONE; | |
034c1be0 MM |
3289 | }") |
3290 | ||
a78e33fc | 3291 | (define_insn "extzvsi" |
cd2b37d9 RK |
3292 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3293 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3294 | (match_operand:SI 2 "const_int_operand" "i") |
3295 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3296 | "" | |
3297 | "* | |
3298 | { | |
3299 | int start = INTVAL (operands[3]) & 31; | |
3300 | int size = INTVAL (operands[2]) & 31; | |
3301 | ||
3302 | if (start + size >= 32) | |
3303 | operands[3] = const0_rtx; | |
3304 | else | |
89e9f3a8 | 3305 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3306 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3307 | }") |
3308 | ||
a78e33fc | 3309 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3310 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3311 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3312 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3313 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3314 | (const_int 0))) |
9ebbca7d | 3315 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3316 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3317 | "* |
3318 | { | |
3319 | int start = INTVAL (operands[3]) & 31; | |
3320 | int size = INTVAL (operands[2]) & 31; | |
3321 | ||
9ebbca7d GK |
3322 | /* Force split for non-cc0 compare. */ |
3323 | if (which_alternative == 1) | |
3324 | return \"#\"; | |
3325 | ||
a7a975e1 RK |
3326 | /* If the bitfield being tested fits in the upper or lower half of a |
3327 | word, it is possible to use andiu. or andil. to test it. This is | |
3328 | useful because the condition register set-use delay is smaller for | |
3329 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3330 | position is 0 because the LT and GT bits may be set wrong. */ | |
3331 | ||
3332 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3333 | { |
3a598fbe | 3334 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3335 | - (1 << (16 - (start & 15) - size)))); |
3336 | if (start < 16) | |
ca7f5001 | 3337 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3338 | else |
ca7f5001 | 3339 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3340 | } |
7e69e155 | 3341 | |
1fd4e8c1 RK |
3342 | if (start + size >= 32) |
3343 | operands[3] = const0_rtx; | |
3344 | else | |
89e9f3a8 | 3345 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3346 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3347 | }" |
9ebbca7d GK |
3348 | [(set_attr "type" "compare") |
3349 | (set_attr "length" "4,8")]) | |
3350 | ||
3351 | (define_split | |
3352 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3353 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3354 | (match_operand:SI 2 "const_int_operand" "") | |
3355 | (match_operand:SI 3 "const_int_operand" "")) | |
3356 | (const_int 0))) | |
3357 | (clobber (match_scratch:SI 4 ""))] | |
3358 | "! TARGET_POWERPC64 && reload_completed" | |
3359 | [(set (match_dup 4) | |
3360 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3361 | (match_dup 3))) | |
3362 | (set (match_dup 0) | |
3363 | (compare:CC (match_dup 4) | |
3364 | (const_int 0)))] | |
3365 | "") | |
1fd4e8c1 | 3366 | |
a78e33fc | 3367 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3368 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3369 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3370 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3371 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3372 | (const_int 0))) |
9ebbca7d | 3373 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3374 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
0ad91047 | 3375 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3376 | "* |
3377 | { | |
3378 | int start = INTVAL (operands[3]) & 31; | |
3379 | int size = INTVAL (operands[2]) & 31; | |
3380 | ||
9ebbca7d GK |
3381 | /* Force split for non-cc0 compare. */ |
3382 | if (which_alternative == 1) | |
3383 | return \"#\"; | |
3384 | ||
a7a975e1 | 3385 | if (start >= 16 && start + size == 32) |
df031c43 | 3386 | { |
89e9f3a8 | 3387 | operands[3] = GEN_INT ((1 << (32 - start)) - 1); |
ca7f5001 | 3388 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 | 3389 | } |
7e69e155 | 3390 | |
1fd4e8c1 RK |
3391 | if (start + size >= 32) |
3392 | operands[3] = const0_rtx; | |
3393 | else | |
89e9f3a8 | 3394 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3395 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3396 | }" |
9ebbca7d GK |
3397 | [(set_attr "type" "delayed_compare") |
3398 | (set_attr "length" "4,8")]) | |
3399 | ||
3400 | (define_split | |
3401 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3402 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3403 | (match_operand:SI 2 "const_int_operand" "") | |
3404 | (match_operand:SI 3 "const_int_operand" "")) | |
3405 | (const_int 0))) | |
3406 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3407 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
3408 | "! TARGET_POWERPC64 && reload_completed" | |
3409 | [(set (match_dup 0) | |
3410 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3411 | (set (match_dup 4) | |
3412 | (compare:CC (match_dup 0) | |
3413 | (const_int 0)))] | |
3414 | "") | |
1fd4e8c1 | 3415 | |
a78e33fc | 3416 | (define_insn "extzvdi" |
685f3906 DE |
3417 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3418 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3419 | (match_operand:SI 2 "const_int_operand" "i") |
3420 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3421 | "TARGET_POWERPC64" |
3422 | "* | |
3423 | { | |
3424 | int start = INTVAL (operands[3]) & 63; | |
3425 | int size = INTVAL (operands[2]) & 63; | |
3426 | ||
3427 | if (start + size >= 64) | |
3428 | operands[3] = const0_rtx; | |
3429 | else | |
89e9f3a8 MM |
3430 | operands[3] = GEN_INT (start + size); |
3431 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3432 | return \"rldicl %0,%1,%3,%2\"; |
3433 | }") | |
3434 | ||
a78e33fc | 3435 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3436 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3437 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3438 | (match_operand:SI 2 "const_int_operand" "i") |
3439 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3440 | (const_int 0))) |
29ae5b89 | 3441 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
3442 | "TARGET_POWERPC64" |
3443 | "* | |
3444 | { | |
3445 | int start = INTVAL (operands[3]) & 63; | |
3446 | int size = INTVAL (operands[2]) & 63; | |
3447 | ||
3448 | if (start + size >= 64) | |
3449 | operands[3] = const0_rtx; | |
3450 | else | |
89e9f3a8 MM |
3451 | operands[3] = GEN_INT (start + size); |
3452 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3453 | return \"rldicl. %4,%1,%3,%2\"; |
3454 | }") | |
3455 | ||
a78e33fc | 3456 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3457 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3458 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3459 | (match_operand:SI 2 "const_int_operand" "i") |
3460 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3461 | (const_int 0))) |
29ae5b89 | 3462 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
3463 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
3464 | "TARGET_POWERPC64" | |
3465 | "* | |
3466 | { | |
3467 | int start = INTVAL (operands[3]) & 63; | |
3468 | int size = INTVAL (operands[2]) & 63; | |
3469 | ||
3470 | if (start + size >= 64) | |
3471 | operands[3] = const0_rtx; | |
3472 | else | |
89e9f3a8 MM |
3473 | operands[3] = GEN_INT (start + size); |
3474 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3475 | return \"rldicl. %0,%1,%3,%2\"; |
3476 | }") | |
3477 | ||
1fd4e8c1 | 3478 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3479 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3480 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3481 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3482 | "" | |
ca7f5001 | 3483 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3484 | |
a260abc9 | 3485 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3486 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3487 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3488 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3489 | (const_int 0))) |
9ebbca7d | 3490 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3491 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3492 | "@ |
3493 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3494 | #" | |
3495 | [(set_attr "type" "delayed_compare") | |
3496 | (set_attr "length" "4,8")]) | |
3497 | ||
3498 | (define_split | |
3499 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3500 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3501 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3502 | (const_int 0))) | |
3503 | (clobber (match_scratch:SI 3 ""))] | |
3504 | "! TARGET_POWERPC64 && reload_completed" | |
3505 | [(set (match_dup 3) | |
3506 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3507 | (set (match_dup 0) | |
3508 | (compare:CC (match_dup 3) | |
3509 | (const_int 0)))] | |
3510 | "") | |
1fd4e8c1 | 3511 | |
a260abc9 | 3512 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3513 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3514 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3515 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3516 | (const_int 0))) |
9ebbca7d | 3517 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3518 | (rotate:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3519 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3520 | "@ |
3521 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3522 | #" | |
3523 | [(set_attr "type" "delayed_compare") | |
3524 | (set_attr "length" "4,8")]) | |
3525 | ||
3526 | (define_split | |
3527 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3528 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3529 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3530 | (const_int 0))) | |
3531 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3532 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
3533 | "! TARGET_POWERPC64 && reload_completed" | |
3534 | [(set (match_dup 0) | |
3535 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3536 | (set (match_dup 3) | |
3537 | (compare:CC (match_dup 0) | |
3538 | (const_int 0)))] | |
3539 | "") | |
1fd4e8c1 | 3540 | |
a260abc9 | 3541 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3542 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3543 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3544 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
9615f239 | 3545 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3546 | "" |
ca7f5001 | 3547 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3548 | |
a260abc9 | 3549 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3550 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3551 | (compare:CC (and:SI |
9ebbca7d GK |
3552 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3553 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3554 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3555 | (const_int 0))) |
9ebbca7d | 3556 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3557 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3558 | "@ |
3559 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3560 | #" | |
3561 | [(set_attr "type" "delayed_compare") | |
3562 | (set_attr "length" "4,8")]) | |
3563 | ||
3564 | (define_split | |
3565 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3566 | (compare:CC (and:SI | |
3567 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3568 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3569 | (match_operand:SI 3 "mask_operand" "")) | |
3570 | (const_int 0))) | |
3571 | (clobber (match_scratch:SI 4 ""))] | |
3572 | "! TARGET_POWERPC64 && reload_completed" | |
3573 | [(set (match_dup 4) | |
3574 | (and:SI (rotate:SI (match_dup 1) | |
3575 | (match_dup 2)) | |
3576 | (match_dup 3))) | |
3577 | (set (match_dup 0) | |
3578 | (compare:CC (match_dup 4) | |
3579 | (const_int 0)))] | |
3580 | "") | |
1fd4e8c1 | 3581 | |
a260abc9 | 3582 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3583 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3584 | (compare:CC (and:SI |
9ebbca7d GK |
3585 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3586 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3587 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3588 | (const_int 0))) |
9ebbca7d | 3589 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3590 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3591 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3592 | "@ |
3593 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3594 | #" | |
3595 | [(set_attr "type" "delayed_compare") | |
3596 | (set_attr "length" "4,8")]) | |
3597 | ||
3598 | (define_split | |
3599 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3600 | (compare:CC (and:SI | |
3601 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3602 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3603 | (match_operand:SI 3 "mask_operand" "")) | |
3604 | (const_int 0))) | |
3605 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3606 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
3607 | "! TARGET_POWERPC64 && reload_completed" | |
3608 | [(set (match_dup 0) | |
3609 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3610 | (set (match_dup 4) | |
3611 | (compare:CC (match_dup 0) | |
3612 | (const_int 0)))] | |
3613 | "") | |
1fd4e8c1 | 3614 | |
a260abc9 | 3615 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3616 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3617 | (zero_extend:SI |
3618 | (subreg:QI | |
cd2b37d9 | 3619 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3620 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3621 | "" | |
ca7f5001 | 3622 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3623 | |
a260abc9 | 3624 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3625 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3626 | (compare:CC (zero_extend:SI |
3627 | (subreg:QI | |
9ebbca7d GK |
3628 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3629 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3630 | (const_int 0))) |
9ebbca7d | 3631 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3632 | "" |
9ebbca7d GK |
3633 | "@ |
3634 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3635 | #" | |
3636 | [(set_attr "type" "delayed_compare") | |
3637 | (set_attr "length" "4,8")]) | |
3638 | ||
3639 | (define_split | |
3640 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3641 | (compare:CC (zero_extend:SI | |
3642 | (subreg:QI | |
3643 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3644 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3645 | (const_int 0))) | |
3646 | (clobber (match_scratch:SI 3 ""))] | |
3647 | "reload_completed" | |
3648 | [(set (match_dup 3) | |
3649 | (zero_extend:SI (subreg:QI | |
3650 | (rotate:SI (match_dup 1) | |
3651 | (match_dup 2)) 0))) | |
3652 | (set (match_dup 0) | |
3653 | (compare:CC (match_dup 3) | |
3654 | (const_int 0)))] | |
3655 | "") | |
1fd4e8c1 | 3656 | |
a260abc9 | 3657 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3658 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3659 | (compare:CC (zero_extend:SI |
3660 | (subreg:QI | |
9ebbca7d GK |
3661 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3662 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3663 | (const_int 0))) |
9ebbca7d | 3664 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3665 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3666 | "" | |
9ebbca7d GK |
3667 | "@ |
3668 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3669 | #" | |
3670 | [(set_attr "type" "delayed_compare") | |
3671 | (set_attr "length" "4,8")]) | |
3672 | ||
3673 | (define_split | |
3674 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3675 | (compare:CC (zero_extend:SI | |
3676 | (subreg:QI | |
3677 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3678 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3679 | (const_int 0))) | |
3680 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3681 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3682 | "reload_completed" | |
3683 | [(set (match_dup 0) | |
3684 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3685 | (set (match_dup 3) | |
3686 | (compare:CC (match_dup 0) | |
3687 | (const_int 0)))] | |
3688 | "") | |
1fd4e8c1 | 3689 | |
a260abc9 | 3690 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3691 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3692 | (zero_extend:SI |
3693 | (subreg:HI | |
cd2b37d9 | 3694 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3695 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3696 | "" | |
ca7f5001 | 3697 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3698 | |
a260abc9 | 3699 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3700 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3701 | (compare:CC (zero_extend:SI |
3702 | (subreg:HI | |
9ebbca7d GK |
3703 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3704 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3705 | (const_int 0))) |
9ebbca7d | 3706 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3707 | "" |
9ebbca7d GK |
3708 | "@ |
3709 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3710 | #" | |
3711 | [(set_attr "type" "delayed_compare") | |
3712 | (set_attr "length" "4,8")]) | |
3713 | ||
3714 | (define_split | |
3715 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3716 | (compare:CC (zero_extend:SI | |
3717 | (subreg:HI | |
3718 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3719 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3720 | (const_int 0))) | |
3721 | (clobber (match_scratch:SI 3 ""))] | |
3722 | "reload_completed" | |
3723 | [(set (match_dup 3) | |
3724 | (zero_extend:SI (subreg:HI | |
3725 | (rotate:SI (match_dup 1) | |
3726 | (match_dup 2)) 0))) | |
3727 | (set (match_dup 0) | |
3728 | (compare:CC (match_dup 3) | |
3729 | (const_int 0)))] | |
3730 | "") | |
1fd4e8c1 | 3731 | |
a260abc9 | 3732 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3733 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3734 | (compare:CC (zero_extend:SI |
3735 | (subreg:HI | |
9ebbca7d GK |
3736 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3737 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3738 | (const_int 0))) |
9ebbca7d | 3739 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3740 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3741 | "" | |
9ebbca7d GK |
3742 | "@ |
3743 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3744 | #" | |
3745 | [(set_attr "type" "delayed_compare") | |
3746 | (set_attr "length" "4,8")]) | |
3747 | ||
3748 | (define_split | |
3749 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3750 | (compare:CC (zero_extend:SI | |
3751 | (subreg:HI | |
3752 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3753 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3754 | (const_int 0))) | |
3755 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3756 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3757 | "reload_completed" | |
3758 | [(set (match_dup 0) | |
3759 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3760 | (set (match_dup 3) | |
3761 | (compare:CC (match_dup 0) | |
3762 | (const_int 0)))] | |
3763 | "") | |
1fd4e8c1 RK |
3764 | |
3765 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3766 | ;; SHIFT_COUNT_TRUNCATED. | |
3767 | ||
ca7f5001 RK |
3768 | (define_expand "ashlsi3" |
3769 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3770 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3771 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3772 | "" | |
3773 | " | |
3774 | { | |
3775 | if (TARGET_POWER) | |
3776 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3777 | else | |
25c341fa | 3778 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3779 | DONE; |
3780 | }") | |
3781 | ||
3782 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3783 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3784 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3785 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3786 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3787 | "TARGET_POWER" |
1fd4e8c1 RK |
3788 | "@ |
3789 | sle %0,%1,%2 | |
9ebbca7d | 3790 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3791 | |
25c341fa | 3792 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3793 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3794 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3795 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3796 | "! TARGET_POWER" |
9ebbca7d | 3797 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3798 | |
3799 | (define_insn "" | |
9ebbca7d GK |
3800 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3801 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3802 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3803 | (const_int 0))) |
9ebbca7d GK |
3804 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3805 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3806 | "TARGET_POWER" |
1fd4e8c1 RK |
3807 | "@ |
3808 | sle. %3,%1,%2 | |
9ebbca7d GK |
3809 | {sli.|slwi.} %3,%1,%h2 |
3810 | # | |
3811 | #" | |
3812 | [(set_attr "type" "delayed_compare") | |
3813 | (set_attr "length" "4,4,8,8")]) | |
3814 | ||
3815 | (define_split | |
3816 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3817 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3818 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3819 | (const_int 0))) | |
3820 | (clobber (match_scratch:SI 3 "")) | |
3821 | (clobber (match_scratch:SI 4 ""))] | |
3822 | "TARGET_POWER && reload_completed" | |
3823 | [(parallel [(set (match_dup 3) | |
3824 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3825 | (clobber (match_dup 4))]) | |
3826 | (set (match_dup 0) | |
3827 | (compare:CC (match_dup 3) | |
3828 | (const_int 0)))] | |
3829 | "") | |
25c341fa | 3830 | |
ca7f5001 | 3831 | (define_insn "" |
9ebbca7d GK |
3832 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3833 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3834 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3835 | (const_int 0))) |
9ebbca7d | 3836 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3837 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3838 | "@ |
3839 | {sl|slw}%I2. %3,%1,%h2 | |
3840 | #" | |
3841 | [(set_attr "type" "delayed_compare") | |
3842 | (set_attr "length" "4,8")]) | |
3843 | ||
3844 | (define_split | |
3845 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3846 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3847 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3848 | (const_int 0))) | |
3849 | (clobber (match_scratch:SI 3 ""))] | |
3850 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3851 | [(set (match_dup 3) | |
3852 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3853 | (set (match_dup 0) | |
3854 | (compare:CC (match_dup 3) | |
3855 | (const_int 0)))] | |
3856 | "") | |
1fd4e8c1 RK |
3857 | |
3858 | (define_insn "" | |
9ebbca7d GK |
3859 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3860 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3861 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3862 | (const_int 0))) |
9ebbca7d | 3863 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3864 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3865 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3866 | "TARGET_POWER" |
1fd4e8c1 RK |
3867 | "@ |
3868 | sle. %0,%1,%2 | |
9ebbca7d GK |
3869 | {sli.|slwi.} %0,%1,%h2 |
3870 | # | |
3871 | #" | |
3872 | [(set_attr "type" "delayed_compare") | |
3873 | (set_attr "length" "4,4,8,8")]) | |
3874 | ||
3875 | (define_split | |
3876 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3877 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3878 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3879 | (const_int 0))) | |
3880 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3881 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3882 | (clobber (match_scratch:SI 4 ""))] | |
3883 | "TARGET_POWER && reload_completed" | |
3884 | [(parallel [(set (match_dup 0) | |
3885 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3886 | (clobber (match_dup 4))]) | |
3887 | (set (match_dup 3) | |
3888 | (compare:CC (match_dup 0) | |
3889 | (const_int 0)))] | |
3890 | "") | |
25c341fa | 3891 | |
ca7f5001 | 3892 | (define_insn "" |
9ebbca7d GK |
3893 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3894 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3895 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3896 | (const_int 0))) |
9ebbca7d | 3897 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3898 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3899 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3900 | "@ |
3901 | {sl|slw}%I2. %0,%1,%h2 | |
3902 | #" | |
3903 | [(set_attr "type" "delayed_compare") | |
3904 | (set_attr "length" "4,8")]) | |
3905 | ||
3906 | (define_split | |
3907 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3908 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3909 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3910 | (const_int 0))) | |
3911 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3912 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
3913 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3914 | [(set (match_dup 0) | |
3915 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3916 | (set (match_dup 3) | |
3917 | (compare:CC (match_dup 0) | |
3918 | (const_int 0)))] | |
3919 | "") | |
1fd4e8c1 RK |
3920 | |
3921 | (define_insn "" | |
cd2b37d9 RK |
3922 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3923 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3924 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 3925 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3926 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3927 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3928 | |
3929 | (define_insn "" | |
9ebbca7d | 3930 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3931 | (compare:CC |
9ebbca7d GK |
3932 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3933 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
3934 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3935 | (const_int 0))) |
9ebbca7d | 3936 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3937 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3938 | "@ |
3939 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3940 | #" | |
3941 | [(set_attr "type" "delayed_compare") | |
3942 | (set_attr "length" "4,8")]) | |
3943 | ||
3944 | (define_split | |
3945 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3946 | (compare:CC | |
3947 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3948 | (match_operand:SI 2 "const_int_operand" "")) | |
3949 | (match_operand:SI 3 "mask_operand" "")) | |
3950 | (const_int 0))) | |
3951 | (clobber (match_scratch:SI 4 ""))] | |
3952 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
3953 | [(set (match_dup 4) | |
3954 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3955 | (match_dup 3))) | |
3956 | (set (match_dup 0) | |
3957 | (compare:CC (match_dup 4) | |
3958 | (const_int 0)))] | |
3959 | "") | |
1fd4e8c1 RK |
3960 | |
3961 | (define_insn "" | |
9ebbca7d | 3962 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3963 | (compare:CC |
9ebbca7d GK |
3964 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3965 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
3966 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3967 | (const_int 0))) |
9ebbca7d | 3968 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3969 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3970 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3971 | "@ |
3972 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3973 | #" | |
3974 | [(set_attr "type" "delayed_compare") | |
3975 | (set_attr "length" "4,8")]) | |
3976 | ||
3977 | (define_split | |
3978 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3979 | (compare:CC | |
3980 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3981 | (match_operand:SI 2 "const_int_operand" "")) | |
3982 | (match_operand:SI 3 "mask_operand" "")) | |
3983 | (const_int 0))) | |
3984 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3985 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
3986 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
3987 | [(set (match_dup 0) | |
3988 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3989 | (set (match_dup 4) | |
3990 | (compare:CC (match_dup 0) | |
3991 | (const_int 0)))] | |
3992 | "") | |
1fd4e8c1 | 3993 | |
ca7f5001 | 3994 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3995 | ;; "sli x,x,0". |
ca7f5001 RK |
3996 | (define_expand "lshrsi3" |
3997 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3998 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3999 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
4000 | "" | |
4001 | " | |
4002 | { | |
4003 | if (TARGET_POWER) | |
4004 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
4005 | else | |
25c341fa | 4006 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4007 | DONE; |
4008 | }") | |
4009 | ||
4010 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
4011 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
4012 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
4013 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
4014 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 4015 | "TARGET_POWER" |
1fd4e8c1 RK |
4016 | "@ |
4017 | sre %0,%1,%2 | |
bdf423cb | 4018 | mr %0,%1 |
ca7f5001 RK |
4019 | {s%A2i|s%A2wi} %0,%1,%h2") |
4020 | ||
25c341fa | 4021 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
4022 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4023 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4024 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 4025 | "! TARGET_POWER" |
bdf423cb MM |
4026 | "@ |
4027 | mr %0,%1 | |
4028 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
4029 | |
4030 | (define_insn "" | |
9ebbca7d GK |
4031 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
4032 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4033 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4034 | (const_int 0))) |
9ebbca7d GK |
4035 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
4036 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 4037 | "TARGET_POWER" |
1fd4e8c1 | 4038 | "@ |
29ae5b89 JL |
4039 | sre. %3,%1,%2 |
4040 | mr. %1,%1 | |
9ebbca7d GK |
4041 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
4042 | # | |
4043 | # | |
4044 | #" | |
4045 | [(set_attr "type" "delayed_compare") | |
4046 | (set_attr "length" "4,4,4,8,8,8")]) | |
4047 | ||
4048 | (define_split | |
4049 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4050 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4051 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4052 | (const_int 0))) | |
4053 | (clobber (match_scratch:SI 3 "")) | |
4054 | (clobber (match_scratch:SI 4 ""))] | |
4055 | "TARGET_POWER && reload_completed" | |
4056 | [(parallel [(set (match_dup 3) | |
4057 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4058 | (clobber (match_dup 4))]) | |
4059 | (set (match_dup 0) | |
4060 | (compare:CC (match_dup 3) | |
4061 | (const_int 0)))] | |
4062 | "") | |
ca7f5001 RK |
4063 | |
4064 | (define_insn "" | |
9ebbca7d GK |
4065 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4066 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4067 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 4068 | (const_int 0))) |
9ebbca7d | 4069 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
0ad91047 | 4070 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
4071 | "@ |
4072 | mr. %1,%1 | |
9ebbca7d GK |
4073 | {sr|srw}%I2. %3,%1,%h2 |
4074 | # | |
4075 | #" | |
4076 | [(set_attr "type" "delayed_compare") | |
4077 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 4078 | |
9ebbca7d GK |
4079 | (define_split |
4080 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4081 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4082 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4083 | (const_int 0))) | |
4084 | (clobber (match_scratch:SI 3 ""))] | |
4085 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4086 | [(set (match_dup 3) | |
4087 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4088 | (set (match_dup 0) | |
4089 | (compare:CC (match_dup 3) | |
4090 | (const_int 0)))] | |
4091 | "") | |
4092 | ||
4093 | (define_insn "" | |
4094 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
4095 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4096 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4097 | (const_int 0))) |
9ebbca7d | 4098 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 4099 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4100 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 4101 | "TARGET_POWER" |
1fd4e8c1 | 4102 | "@ |
29ae5b89 JL |
4103 | sre. %0,%1,%2 |
4104 | mr. %0,%1 | |
9ebbca7d GK |
4105 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
4106 | # | |
4107 | # | |
4108 | #" | |
4109 | [(set_attr "type" "delayed_compare") | |
4110 | (set_attr "length" "4,4,4,8,8,8")]) | |
4111 | ||
4112 | (define_split | |
4113 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4114 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4115 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4116 | (const_int 0))) | |
4117 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4118 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4119 | (clobber (match_scratch:SI 4 ""))] | |
4120 | "TARGET_POWER && reload_completed" | |
4121 | [(parallel [(set (match_dup 0) | |
4122 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4123 | (clobber (match_dup 4))]) | |
4124 | (set (match_dup 3) | |
4125 | (compare:CC (match_dup 0) | |
4126 | (const_int 0)))] | |
4127 | "") | |
ca7f5001 RK |
4128 | |
4129 | (define_insn "" | |
9ebbca7d GK |
4130 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4131 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4132 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4133 | (const_int 0))) |
9ebbca7d | 4134 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4135 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4136 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
4137 | "@ |
4138 | mr. %0,%1 | |
9ebbca7d GK |
4139 | {sr|srw}%I2. %0,%1,%h2 |
4140 | # | |
4141 | #" | |
4142 | [(set_attr "type" "delayed_compare") | |
4143 | (set_attr "length" "4,4,8,8")]) | |
4144 | ||
4145 | (define_split | |
4146 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4147 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4148 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4149 | (const_int 0))) | |
4150 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4151 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4152 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4153 | [(set (match_dup 0) | |
4154 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4155 | (set (match_dup 3) | |
4156 | (compare:CC (match_dup 0) | |
4157 | (const_int 0)))] | |
4158 | "") | |
1fd4e8c1 RK |
4159 | |
4160 | (define_insn "" | |
cd2b37d9 RK |
4161 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4162 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4163 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 4164 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 4165 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4166 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4167 | |
4168 | (define_insn "" | |
9ebbca7d | 4169 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4170 | (compare:CC |
9ebbca7d GK |
4171 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4172 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4173 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4174 | (const_int 0))) |
9ebbca7d | 4175 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4176 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4177 | "@ |
4178 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4179 | #" | |
4180 | [(set_attr "type" "delayed_compare") | |
4181 | (set_attr "length" "4,8")]) | |
4182 | ||
4183 | (define_split | |
4184 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4185 | (compare:CC | |
4186 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4187 | (match_operand:SI 2 "const_int_operand" "")) | |
4188 | (match_operand:SI 3 "mask_operand" "")) | |
4189 | (const_int 0))) | |
4190 | (clobber (match_scratch:SI 4 ""))] | |
4191 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4192 | [(set (match_dup 4) | |
4193 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4194 | (match_dup 3))) | |
4195 | (set (match_dup 0) | |
4196 | (compare:CC (match_dup 4) | |
4197 | (const_int 0)))] | |
4198 | "") | |
1fd4e8c1 RK |
4199 | |
4200 | (define_insn "" | |
9ebbca7d | 4201 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4202 | (compare:CC |
9ebbca7d GK |
4203 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4204 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4205 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4206 | (const_int 0))) |
9ebbca7d | 4207 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4208 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4209 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4210 | "@ |
4211 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4212 | #" | |
4213 | [(set_attr "type" "delayed_compare") | |
4214 | (set_attr "length" "4,8")]) | |
4215 | ||
4216 | (define_split | |
4217 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4218 | (compare:CC | |
4219 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4220 | (match_operand:SI 2 "const_int_operand" "")) | |
4221 | (match_operand:SI 3 "mask_operand" "")) | |
4222 | (const_int 0))) | |
4223 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4224 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4225 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4226 | [(set (match_dup 0) | |
4227 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4228 | (set (match_dup 4) | |
4229 | (compare:CC (match_dup 0) | |
4230 | (const_int 0)))] | |
4231 | "") | |
1fd4e8c1 RK |
4232 | |
4233 | (define_insn "" | |
cd2b37d9 | 4234 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4235 | (zero_extend:SI |
4236 | (subreg:QI | |
cd2b37d9 | 4237 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4238 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4239 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4240 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4241 | |
4242 | (define_insn "" | |
9ebbca7d | 4243 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4244 | (compare:CC |
4245 | (zero_extend:SI | |
4246 | (subreg:QI | |
9ebbca7d GK |
4247 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4248 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4249 | (const_int 0))) |
9ebbca7d | 4250 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4251 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4252 | "@ |
4253 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4254 | #" | |
4255 | [(set_attr "type" "delayed_compare") | |
4256 | (set_attr "length" "4,8")]) | |
4257 | ||
4258 | (define_split | |
4259 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4260 | (compare:CC | |
4261 | (zero_extend:SI | |
4262 | (subreg:QI | |
4263 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4264 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4265 | (const_int 0))) | |
4266 | (clobber (match_scratch:SI 3 ""))] | |
4267 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4268 | [(set (match_dup 3) | |
4269 | (zero_extend:SI (subreg:QI | |
4270 | (lshiftrt:SI (match_dup 1) | |
4271 | (match_dup 2)) 0))) | |
4272 | (set (match_dup 0) | |
4273 | (compare:CC (match_dup 3) | |
4274 | (const_int 0)))] | |
4275 | "") | |
1fd4e8c1 RK |
4276 | |
4277 | (define_insn "" | |
9ebbca7d | 4278 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4279 | (compare:CC |
4280 | (zero_extend:SI | |
4281 | (subreg:QI | |
9ebbca7d GK |
4282 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4283 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4284 | (const_int 0))) |
9ebbca7d | 4285 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4286 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4287 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4288 | "@ |
4289 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4290 | #" | |
4291 | [(set_attr "type" "delayed_compare") | |
4292 | (set_attr "length" "4,8")]) | |
4293 | ||
4294 | (define_split | |
4295 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4296 | (compare:CC | |
4297 | (zero_extend:SI | |
4298 | (subreg:QI | |
4299 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4300 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4301 | (const_int 0))) | |
4302 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4303 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4304 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4305 | [(set (match_dup 0) | |
4306 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4307 | (set (match_dup 3) | |
4308 | (compare:CC (match_dup 0) | |
4309 | (const_int 0)))] | |
4310 | "") | |
1fd4e8c1 RK |
4311 | |
4312 | (define_insn "" | |
cd2b37d9 | 4313 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4314 | (zero_extend:SI |
4315 | (subreg:HI | |
cd2b37d9 | 4316 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4317 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4318 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4319 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4320 | |
4321 | (define_insn "" | |
9ebbca7d | 4322 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4323 | (compare:CC |
4324 | (zero_extend:SI | |
4325 | (subreg:HI | |
9ebbca7d GK |
4326 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4327 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4328 | (const_int 0))) |
9ebbca7d | 4329 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4330 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4331 | "@ |
4332 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4333 | #" | |
4334 | [(set_attr "type" "delayed_compare") | |
4335 | (set_attr "length" "4,8")]) | |
4336 | ||
4337 | (define_split | |
4338 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4339 | (compare:CC | |
4340 | (zero_extend:SI | |
4341 | (subreg:HI | |
4342 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4343 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4344 | (const_int 0))) | |
4345 | (clobber (match_scratch:SI 3 ""))] | |
4346 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4347 | [(set (match_dup 3) | |
4348 | (zero_extend:SI (subreg:HI | |
4349 | (lshiftrt:SI (match_dup 1) | |
4350 | (match_dup 2)) 0))) | |
4351 | (set (match_dup 0) | |
4352 | (compare:CC (match_dup 3) | |
4353 | (const_int 0)))] | |
4354 | "") | |
1fd4e8c1 RK |
4355 | |
4356 | (define_insn "" | |
9ebbca7d | 4357 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4358 | (compare:CC |
4359 | (zero_extend:SI | |
4360 | (subreg:HI | |
9ebbca7d GK |
4361 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4362 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4363 | (const_int 0))) |
9ebbca7d | 4364 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4365 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4366 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4367 | "@ |
4368 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4369 | #" | |
4370 | [(set_attr "type" "delayed_compare") | |
4371 | (set_attr "length" "4,8")]) | |
4372 | ||
4373 | (define_split | |
4374 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4375 | (compare:CC | |
4376 | (zero_extend:SI | |
4377 | (subreg:HI | |
4378 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4379 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4380 | (const_int 0))) | |
4381 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4382 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4383 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4384 | [(set (match_dup 0) | |
4385 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4386 | (set (match_dup 3) | |
4387 | (compare:CC (match_dup 0) | |
4388 | (const_int 0)))] | |
4389 | "") | |
1fd4e8c1 RK |
4390 | |
4391 | (define_insn "" | |
cd2b37d9 | 4392 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4393 | (const_int 1) |
cd2b37d9 RK |
4394 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4395 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4396 | (const_int 31)))] |
ca7f5001 | 4397 | "TARGET_POWER" |
1fd4e8c1 RK |
4398 | "rrib %0,%1,%2") |
4399 | ||
4400 | (define_insn "" | |
cd2b37d9 | 4401 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4402 | (const_int 1) |
cd2b37d9 RK |
4403 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4404 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4405 | (const_int 31)))] |
ca7f5001 | 4406 | "TARGET_POWER" |
1fd4e8c1 RK |
4407 | "rrib %0,%1,%2") |
4408 | ||
4409 | (define_insn "" | |
cd2b37d9 | 4410 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4411 | (const_int 1) |
cd2b37d9 RK |
4412 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4413 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4414 | (const_int 1) |
4415 | (const_int 0)))] | |
ca7f5001 | 4416 | "TARGET_POWER" |
1fd4e8c1 RK |
4417 | "rrib %0,%1,%2") |
4418 | ||
ca7f5001 RK |
4419 | (define_expand "ashrsi3" |
4420 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4421 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4422 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4423 | "" | |
4424 | " | |
4425 | { | |
4426 | if (TARGET_POWER) | |
4427 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4428 | else | |
25c341fa | 4429 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4430 | DONE; |
4431 | }") | |
4432 | ||
4433 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4434 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4435 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4436 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4437 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4438 | "TARGET_POWER" |
1fd4e8c1 RK |
4439 | "@ |
4440 | srea %0,%1,%2 | |
ca7f5001 RK |
4441 | {srai|srawi} %0,%1,%h2") |
4442 | ||
25c341fa | 4443 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4444 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4445 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4446 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4447 | "! TARGET_POWER" |
d904e9ed | 4448 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4449 | |
4450 | (define_insn "" | |
9ebbca7d GK |
4451 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4452 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4453 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4454 | (const_int 0))) |
9ebbca7d GK |
4455 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4456 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4457 | "TARGET_POWER" |
1fd4e8c1 RK |
4458 | "@ |
4459 | srea. %3,%1,%2 | |
9ebbca7d GK |
4460 | {srai.|srawi.} %3,%1,%h2 |
4461 | # | |
4462 | #" | |
4463 | [(set_attr "type" "delayed_compare") | |
4464 | (set_attr "length" "4,4,8,8")]) | |
4465 | ||
4466 | (define_split | |
4467 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4468 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4469 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4470 | (const_int 0))) | |
4471 | (clobber (match_scratch:SI 3 "")) | |
4472 | (clobber (match_scratch:SI 4 ""))] | |
4473 | "TARGET_POWER && reload_completed" | |
4474 | [(parallel [(set (match_dup 3) | |
4475 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4476 | (clobber (match_dup 4))]) | |
4477 | (set (match_dup 0) | |
4478 | (compare:CC (match_dup 3) | |
4479 | (const_int 0)))] | |
4480 | "") | |
ca7f5001 RK |
4481 | |
4482 | (define_insn "" | |
9ebbca7d GK |
4483 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4484 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4485 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4486 | (const_int 0))) |
9ebbca7d | 4487 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4488 | "! TARGET_POWER" |
9ebbca7d GK |
4489 | "@ |
4490 | {sra|sraw}%I2. %3,%1,%h2 | |
4491 | #" | |
4492 | [(set_attr "type" "delayed_compare") | |
4493 | (set_attr "length" "4,8")]) | |
4494 | ||
4495 | (define_split | |
4496 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4497 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4498 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4499 | (const_int 0))) | |
4500 | (clobber (match_scratch:SI 3 ""))] | |
4501 | "! TARGET_POWER && reload_completed" | |
4502 | [(set (match_dup 3) | |
4503 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4504 | (set (match_dup 0) | |
4505 | (compare:CC (match_dup 3) | |
4506 | (const_int 0)))] | |
4507 | "") | |
1fd4e8c1 RK |
4508 | |
4509 | (define_insn "" | |
9ebbca7d GK |
4510 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4511 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4512 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4513 | (const_int 0))) |
9ebbca7d | 4514 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4515 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4516 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4517 | "TARGET_POWER" |
1fd4e8c1 RK |
4518 | "@ |
4519 | srea. %0,%1,%2 | |
9ebbca7d GK |
4520 | {srai.|srawi.} %0,%1,%h2 |
4521 | # | |
4522 | #" | |
4523 | [(set_attr "type" "delayed_compare") | |
4524 | (set_attr "length" "4,4,8,8")]) | |
4525 | ||
4526 | (define_split | |
4527 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4528 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4529 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4530 | (const_int 0))) | |
4531 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4532 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4533 | (clobber (match_scratch:SI 4 ""))] | |
4534 | "TARGET_POWER && reload_completed" | |
4535 | [(parallel [(set (match_dup 0) | |
4536 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4537 | (clobber (match_dup 4))]) | |
4538 | (set (match_dup 3) | |
4539 | (compare:CC (match_dup 0) | |
4540 | (const_int 0)))] | |
4541 | "") | |
1fd4e8c1 | 4542 | |
ca7f5001 | 4543 | (define_insn "" |
9ebbca7d GK |
4544 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4545 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4546 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4547 | (const_int 0))) |
9ebbca7d | 4548 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4549 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4550 | "! TARGET_POWER" |
9ebbca7d GK |
4551 | "@ |
4552 | {sra|sraw}%I2. %0,%1,%h2 | |
4553 | #" | |
4554 | [(set_attr "type" "delayed_compare") | |
4555 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4556 | \f |
9ebbca7d GK |
4557 | (define_split |
4558 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4559 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4560 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4561 | (const_int 0))) | |
4562 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4563 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4564 | "! TARGET_POWER && reload_completed" | |
4565 | [(set (match_dup 0) | |
4566 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4567 | (set (match_dup 3) | |
4568 | (compare:CC (match_dup 0) | |
4569 | (const_int 0)))] | |
4570 | "") | |
4571 | ||
1fd4e8c1 RK |
4572 | ;; Floating-point insns, excluding normal data motion. |
4573 | ;; | |
ca7f5001 RK |
4574 | ;; PowerPC has a full set of single-precision floating point instructions. |
4575 | ;; | |
4576 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4577 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4578 | ;; The only conversions we will do will be when storing to memory. In that | |
4579 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4580 | ;; |
4581 | ;; Note that when we store into a single-precision memory location, we need to | |
4582 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4583 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4584 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4585 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4586 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4587 | ||
e8112008 | 4588 | (define_insn "extendsfdf2" |
cd2b37d9 | 4589 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 4590 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 4591 | "TARGET_HARD_FLOAT" |
e8112008 | 4592 | "* |
5c30aff8 | 4593 | { |
e8112008 RK |
4594 | if (REGNO (operands[0]) == REGNO (operands[1])) |
4595 | return \"\"; | |
4596 | else | |
4597 | return \"fmr %0,%1\"; | |
4598 | }" | |
4599 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4600 | |
4601 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
4602 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4603 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4604 | "TARGET_HARD_FLOAT" |
dcac138d | 4605 | "frsp %0,%1" |
1fd4e8c1 RK |
4606 | [(set_attr "type" "fp")]) |
4607 | ||
455350f4 RK |
4608 | (define_insn "aux_truncdfsf2" |
4609 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4610 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
4611 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" | |
4612 | "frsp %0,%1" | |
4613 | [(set_attr "type" "fp")]) | |
4614 | ||
1fd4e8c1 | 4615 | (define_insn "negsf2" |
cd2b37d9 RK |
4616 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4617 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4618 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4619 | "fneg %0,%1" |
4620 | [(set_attr "type" "fp")]) | |
4621 | ||
4622 | (define_insn "abssf2" | |
cd2b37d9 RK |
4623 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4624 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4625 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4626 | "fabs %0,%1" |
4627 | [(set_attr "type" "fp")]) | |
4628 | ||
4629 | (define_insn "" | |
cd2b37d9 RK |
4630 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4631 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4632 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4633 | "fnabs %0,%1" |
4634 | [(set_attr "type" "fp")]) | |
4635 | ||
ca7f5001 RK |
4636 | (define_expand "addsf3" |
4637 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4638 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4639 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4640 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4641 | "") |
4642 | ||
4643 | (define_insn "" | |
cd2b37d9 RK |
4644 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4645 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4646 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4647 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4648 | "fadds %0,%1,%2" |
ca7f5001 RK |
4649 | [(set_attr "type" "fp")]) |
4650 | ||
4651 | (define_insn "" | |
4652 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4653 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4654 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4655 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4656 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4657 | [(set_attr "type" "fp")]) |
4658 | ||
4659 | (define_expand "subsf3" | |
4660 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4661 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4662 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4663 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4664 | "") |
4665 | ||
4666 | (define_insn "" | |
4667 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4668 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4669 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4670 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4671 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4672 | [(set_attr "type" "fp")]) |
4673 | ||
ca7f5001 | 4674 | (define_insn "" |
cd2b37d9 RK |
4675 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4676 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4677 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4678 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4679 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4680 | [(set_attr "type" "fp")]) |
4681 | ||
4682 | (define_expand "mulsf3" | |
4683 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4684 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4685 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4686 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4687 | "") |
4688 | ||
4689 | (define_insn "" | |
4690 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4691 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4692 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4693 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4694 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4695 | [(set_attr "type" "fp")]) |
4696 | ||
ca7f5001 | 4697 | (define_insn "" |
cd2b37d9 RK |
4698 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4699 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4700 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4701 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4702 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4703 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4704 | |
ca7f5001 RK |
4705 | (define_expand "divsf3" |
4706 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4707 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4708 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4709 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4710 | "") |
4711 | ||
4712 | (define_insn "" | |
cd2b37d9 RK |
4713 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4714 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4715 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4716 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4717 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4718 | [(set_attr "type" "sdiv")]) |
4719 | ||
4720 | (define_insn "" | |
4721 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4722 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4723 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4724 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4725 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4726 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4727 | |
4728 | (define_insn "" | |
cd2b37d9 RK |
4729 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4730 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4731 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4732 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4733 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4734 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4735 | [(set_attr "type" "fp")]) |
4736 | ||
4737 | (define_insn "" | |
4738 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4739 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4740 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4741 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4742 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4743 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4744 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4745 | |
4746 | (define_insn "" | |
cd2b37d9 RK |
4747 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4748 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4749 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4750 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4751 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4752 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4753 | [(set_attr "type" "fp")]) |
4754 | ||
4755 | (define_insn "" | |
4756 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4757 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4758 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4759 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4760 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4761 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4762 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4763 | |
4764 | (define_insn "" | |
cd2b37d9 RK |
4765 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4766 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4767 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4768 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4769 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4770 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4771 | [(set_attr "type" "fp")]) |
4772 | ||
4773 | (define_insn "" | |
4774 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4775 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4776 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4777 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4778 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4779 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4780 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4781 | |
4782 | (define_insn "" | |
cd2b37d9 RK |
4783 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4784 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4785 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4786 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4787 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4788 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4789 | [(set_attr "type" "fp")]) |
4790 | ||
4791 | (define_insn "" | |
4792 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4793 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4794 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4795 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4796 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4797 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4798 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4799 | |
ca7f5001 RK |
4800 | (define_expand "sqrtsf2" |
4801 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4802 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 4803 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4804 | "") |
4805 | ||
4806 | (define_insn "" | |
4807 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4808 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4809 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4810 | "fsqrts %0,%1" |
4811 | [(set_attr "type" "ssqrt")]) | |
4812 | ||
4813 | (define_insn "" | |
4814 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4815 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4816 | "TARGET_POWER2 && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4817 | "fsqrt %0,%1" |
4818 | [(set_attr "type" "dsqrt")]) | |
4819 | ||
94d7001a RK |
4820 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4821 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4822 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4823 | ;; combine. |
4824 | (define_expand "maxsf3" | |
4825 | [(set (match_dup 3) | |
4826 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4827 | (match_operand:SF 2 "gpc_reg_operand" ""))) | |
4828 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
4829 | (if_then_else:SF (ge (match_dup 3) | |
4830 | (const_int 0)) | |
4831 | (match_dup 1) | |
4832 | (match_dup 2)))] | |
d14a6d05 | 4833 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4834 | " |
4835 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 4836 | |
8e871c05 RK |
4837 | (define_split |
4838 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4839 | (smax:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 4840 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 4841 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 4842 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4843 | [(set (match_dup 3) |
4844 | (minus:SF (match_dup 1) (match_dup 2))) | |
a81bd72f | 4845 | (set (match_dup 0) |
8e871c05 RK |
4846 | (if_then_else:SF (ge (match_dup 3) |
4847 | (const_int 0)) | |
4848 | (match_dup 1) | |
4849 | (match_dup 2)))] | |
4850 | "") | |
2f607b94 | 4851 | |
8e871c05 RK |
4852 | (define_expand "minsf3" |
4853 | [(set (match_dup 3) | |
4854 | (minus:SF (match_operand:SF 2 "gpc_reg_operand" "") | |
4855 | (match_operand:SF 1 "gpc_reg_operand" ""))) | |
4856 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
4857 | (if_then_else:SF (ge (match_dup 3) | |
4858 | (const_int 0)) | |
4859 | (match_dup 1) | |
4860 | (match_dup 2)))] | |
d14a6d05 | 4861 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4862 | " |
4863 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 4864 | |
8e871c05 RK |
4865 | (define_split |
4866 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4867 | (smin:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 4868 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 4869 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 4870 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4871 | [(set (match_dup 3) |
4872 | (minus:SF (match_dup 2) (match_dup 1))) | |
a81bd72f | 4873 | (set (match_dup 0) |
8e871c05 RK |
4874 | (if_then_else:SF (ge (match_dup 3) |
4875 | (const_int 0)) | |
4876 | (match_dup 1) | |
4877 | (match_dup 2)))] | |
4878 | "") | |
2f607b94 | 4879 | |
94d7001a | 4880 | (define_expand "movsfcc" |
0ad91047 | 4881 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4882 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4883 | (match_operand:SF 2 "gpc_reg_operand" "") |
4884 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 4885 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4886 | " |
4887 | { | |
4888 | rtx temp, op0, op1; | |
4889 | enum rtx_code code = GET_CODE (operands[1]); | |
4890 | if (! rs6000_compare_fp_p) | |
4891 | FAIL; | |
4892 | switch (code) | |
4893 | { | |
4894 | case GE: case EQ: case NE: | |
4895 | op0 = rs6000_compare_op0; | |
4896 | op1 = rs6000_compare_op1; | |
4897 | break; | |
4898 | case GT: | |
4899 | op0 = rs6000_compare_op1; | |
4900 | op1 = rs6000_compare_op0; | |
4901 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
4902 | break; | |
4903 | case LE: | |
4904 | op0 = rs6000_compare_op1; | |
4905 | op1 = rs6000_compare_op0; | |
4906 | break; | |
4907 | case LT: | |
4908 | op0 = rs6000_compare_op0; | |
4909 | op1 = rs6000_compare_op1; | |
4910 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
4911 | break; | |
4912 | default: | |
4913 | FAIL; | |
4914 | } | |
4915 | if (GET_MODE (rs6000_compare_op0) == DFmode) | |
4916 | { | |
4917 | temp = gen_reg_rtx (DFmode); | |
4918 | emit_insn (gen_subdf3 (temp, op0, op1)); | |
4919 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3])); | |
4920 | if (code == EQ) | |
4921 | { | |
4922 | emit_insn (gen_negdf2 (temp, temp)); | |
4923 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3])); | |
4924 | } | |
a6c2a102 | 4925 | else if (code == NE) |
94d7001a RK |
4926 | { |
4927 | emit_insn (gen_negdf2 (temp, temp)); | |
4928 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0])); | |
4929 | } | |
4930 | } | |
4931 | else | |
4932 | { | |
4933 | temp = gen_reg_rtx (SFmode); | |
4934 | emit_insn (gen_subsf3 (temp, op0, op1)); | |
4935 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3])); | |
4936 | if (code == EQ) | |
4937 | { | |
4938 | emit_insn (gen_negsf2 (temp, temp)); | |
4939 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3])); | |
4940 | } | |
a6c2a102 | 4941 | else if (code == NE) |
94d7001a RK |
4942 | { |
4943 | emit_insn (gen_negsf2 (temp, temp)); | |
4944 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0])); | |
4945 | } | |
4946 | } | |
4947 | DONE; | |
4948 | }") | |
d56d506a | 4949 | |
94d7001a | 4950 | (define_insn "fselsfsf4" |
8e871c05 RK |
4951 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4952 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
4953 | (const_int 0)) | |
4954 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
4955 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4956 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4957 | "fsel %0,%1,%2,%3" |
4958 | [(set_attr "type" "fp")]) | |
2f607b94 | 4959 | |
94d7001a RK |
4960 | (define_insn "fseldfsf4" |
4961 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4962 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
4963 | (const_int 0)) | |
4964 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
4965 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4966 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4967 | "fsel %0,%1,%2,%3" |
4968 | [(set_attr "type" "fp")]) | |
d56d506a | 4969 | |
1fd4e8c1 | 4970 | (define_insn "negdf2" |
cd2b37d9 RK |
4971 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4972 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4973 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4974 | "fneg %0,%1" |
4975 | [(set_attr "type" "fp")]) | |
4976 | ||
4977 | (define_insn "absdf2" | |
cd2b37d9 RK |
4978 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4979 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4980 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4981 | "fabs %0,%1" |
4982 | [(set_attr "type" "fp")]) | |
4983 | ||
4984 | (define_insn "" | |
cd2b37d9 RK |
4985 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4986 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4987 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4988 | "fnabs %0,%1" |
4989 | [(set_attr "type" "fp")]) | |
4990 | ||
4991 | (define_insn "adddf3" | |
cd2b37d9 RK |
4992 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4993 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4994 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4995 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4996 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4997 | [(set_attr "type" "fp")]) |
4998 | ||
4999 | (define_insn "subdf3" | |
cd2b37d9 RK |
5000 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5001 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5002 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5003 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5004 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
5005 | [(set_attr "type" "fp")]) |
5006 | ||
5007 | (define_insn "muldf3" | |
cd2b37d9 RK |
5008 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5009 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5010 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5011 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5012 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 5013 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5014 | |
5015 | (define_insn "divdf3" | |
cd2b37d9 RK |
5016 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5017 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5018 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5019 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5020 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 5021 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
5022 | |
5023 | (define_insn "" | |
cd2b37d9 RK |
5024 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5025 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5026 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5027 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 5028 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5029 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 5030 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5031 | |
5032 | (define_insn "" | |
cd2b37d9 RK |
5033 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5034 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5035 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5036 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 5037 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5038 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 5039 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5040 | |
5041 | (define_insn "" | |
cd2b37d9 RK |
5042 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5043 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5044 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5045 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 5046 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5047 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 5048 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5049 | |
5050 | (define_insn "" | |
cd2b37d9 RK |
5051 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5052 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5053 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5054 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 5055 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5056 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5057 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5058 | |
5059 | (define_insn "sqrtdf2" | |
5060 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5061 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5062 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5063 | "fsqrt %0,%1" |
5064 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5065 | |
94d7001a RK |
5066 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
5067 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
5068 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 | 5069 | ;; combine. |
b77dfefc | 5070 | |
8e871c05 RK |
5071 | (define_expand "maxdf3" |
5072 | [(set (match_dup 3) | |
5073 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
5074 | (match_operand:DF 2 "gpc_reg_operand" ""))) | |
5075 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
5076 | (if_then_else:DF (ge (match_dup 3) | |
5077 | (const_int 0)) | |
5078 | (match_dup 1) | |
5079 | (match_dup 2)))] | |
d14a6d05 | 5080 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5081 | " |
5082 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 5083 | |
8e871c05 RK |
5084 | (define_split |
5085 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5086 | (smax:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 5087 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 5088 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 5089 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5090 | [(set (match_dup 3) |
5091 | (minus:DF (match_dup 1) (match_dup 2))) | |
a81bd72f | 5092 | (set (match_dup 0) |
8e871c05 RK |
5093 | (if_then_else:DF (ge (match_dup 3) |
5094 | (const_int 0)) | |
5095 | (match_dup 1) | |
5096 | (match_dup 2)))] | |
5097 | "") | |
b77dfefc | 5098 | |
8e871c05 RK |
5099 | (define_expand "mindf3" |
5100 | [(set (match_dup 3) | |
5101 | (minus:DF (match_operand:DF 2 "gpc_reg_operand" "") | |
5102 | (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5103 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
5104 | (if_then_else:DF (ge (match_dup 3) | |
5105 | (const_int 0)) | |
5106 | (match_dup 1) | |
5107 | (match_dup 2)))] | |
d14a6d05 | 5108 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5109 | " |
5110 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 5111 | |
8e871c05 RK |
5112 | (define_split |
5113 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5114 | (smin:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 5115 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 5116 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 5117 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5118 | [(set (match_dup 3) |
5119 | (minus:DF (match_dup 2) (match_dup 1))) | |
a81bd72f | 5120 | (set (match_dup 0) |
8e871c05 RK |
5121 | (if_then_else:DF (ge (match_dup 3) |
5122 | (const_int 0)) | |
5123 | (match_dup 1) | |
5124 | (match_dup 2)))] | |
5125 | "") | |
b77dfefc | 5126 | |
94d7001a | 5127 | (define_expand "movdfcc" |
0ad91047 | 5128 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5129 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5130 | (match_operand:DF 2 "gpc_reg_operand" "") |
5131 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 5132 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5133 | " |
5134 | { | |
5135 | rtx temp, op0, op1; | |
5136 | enum rtx_code code = GET_CODE (operands[1]); | |
5137 | if (! rs6000_compare_fp_p) | |
5138 | FAIL; | |
5139 | switch (code) | |
5140 | { | |
5141 | case GE: case EQ: case NE: | |
5142 | op0 = rs6000_compare_op0; | |
5143 | op1 = rs6000_compare_op1; | |
5144 | break; | |
5145 | case GT: | |
5146 | op0 = rs6000_compare_op1; | |
5147 | op1 = rs6000_compare_op0; | |
5148 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
5149 | break; | |
5150 | case LE: | |
5151 | op0 = rs6000_compare_op1; | |
5152 | op1 = rs6000_compare_op0; | |
5153 | break; | |
5154 | case LT: | |
5155 | op0 = rs6000_compare_op0; | |
5156 | op1 = rs6000_compare_op1; | |
5157 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
5158 | break; | |
5159 | default: | |
5160 | FAIL; | |
5161 | } | |
5162 | if (GET_MODE (rs6000_compare_op0) == DFmode) | |
5163 | { | |
5164 | temp = gen_reg_rtx (DFmode); | |
5165 | emit_insn (gen_subdf3 (temp, op0, op1)); | |
5166 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3])); | |
5167 | if (code == EQ) | |
5168 | { | |
5169 | emit_insn (gen_negdf2 (temp, temp)); | |
5170 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3])); | |
5171 | } | |
a6c2a102 | 5172 | else if (code == NE) |
94d7001a RK |
5173 | { |
5174 | emit_insn (gen_negdf2 (temp, temp)); | |
5175 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0])); | |
5176 | } | |
5177 | } | |
5178 | else | |
5179 | { | |
5180 | temp = gen_reg_rtx (SFmode); | |
5181 | emit_insn (gen_subsf3 (temp, op0, op1)); | |
5182 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3])); | |
5183 | if (code == EQ) | |
5184 | { | |
5185 | emit_insn (gen_negsf2 (temp, temp)); | |
5186 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3])); | |
5187 | } | |
a6c2a102 | 5188 | else if (code == NE) |
94d7001a RK |
5189 | { |
5190 | emit_insn (gen_negsf2 (temp, temp)); | |
5191 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0])); | |
5192 | } | |
5193 | } | |
5194 | DONE; | |
5195 | }") | |
d56d506a | 5196 | |
94d7001a | 5197 | (define_insn "fseldfdf4" |
8e871c05 RK |
5198 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5199 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
5200 | (const_int 0)) | |
5201 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
5202 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5203 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5204 | "fsel %0,%1,%2,%3" |
5205 | [(set_attr "type" "fp")]) | |
d56d506a | 5206 | |
94d7001a RK |
5207 | (define_insn "fselsfdf4" |
5208 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5209 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
5210 | (const_int 0)) | |
5211 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
5212 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5213 | "TARGET_PPC_GFXOPT" | |
5214 | "fsel %0,%1,%2,%3" | |
5215 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5216 | \f |
5217 | ;; Conversions to and from floating-point. | |
802a0058 | 5218 | |
9ebbca7d GK |
5219 | ; For each of these conversions, there is a define_expand, a define_insn |
5220 | ; with a '#' template, and a define_split (with C code). The idea is | |
5221 | ; to allow constant folding with the template of the define_insn, | |
5222 | ; then to have the insns split later (between sched1 and final). | |
5223 | ||
1fd4e8c1 | 5224 | (define_expand "floatsidf2" |
802a0058 MM |
5225 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5226 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5227 | (use (match_dup 2)) | |
5228 | (use (match_dup 3)) | |
208c89ce | 5229 | (clobber (match_dup 4)) |
a7df97e6 | 5230 | (clobber (match_dup 5)) |
9ebbca7d | 5231 | (clobber (match_dup 6))])] |
31bfaa0b | 5232 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5233 | " |
5234 | { | |
802a0058 MM |
5235 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5236 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); | |
9ebbca7d GK |
5237 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5238 | operands[5] = gen_reg_rtx (DFmode); | |
5239 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5240 | }") |
5241 | ||
802a0058 MM |
5242 | (define_insn "*floatsidf2_internal" |
5243 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5244 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5245 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5246 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5247 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5248 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f")) | |
5249 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))] | |
31bfaa0b | 5250 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5251 | "#" |
a7df97e6 | 5252 | [(set_attr "length" "24")]) |
802a0058 MM |
5253 | |
5254 | (define_split | |
dbe3df29 | 5255 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5256 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5257 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5258 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5259 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5260 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5261 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
31bfaa0b | 5262 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5263 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5264 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5265 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5266 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5267 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5268 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5269 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5270 | " |
5271 | { | |
9ebbca7d GK |
5272 | rtx lowword, highword; |
5273 | if (GET_CODE (operands[4]) != MEM) | |
5274 | abort(); | |
5275 | highword = XEXP (operands[4], 0); | |
5276 | lowword = plus_constant (highword, 4); | |
5277 | if (! WORDS_BIG_ENDIAN) | |
5278 | { | |
5279 | rtx tmp; | |
5280 | tmp = highword; highword = lowword; lowword = tmp; | |
5281 | } | |
5282 | ||
5283 | emit_insn (gen_xorsi3 (operands[6], operands[1], | |
5284 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); | |
5285 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5286 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5287 | emit_move_insn (operands[5], operands[4]); | |
5288 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5289 | DONE; | |
208c89ce | 5290 | }") |
802a0058 MM |
5291 | |
5292 | (define_expand "floatunssidf2" | |
5293 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5294 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5295 | (use (match_dup 2)) | |
5296 | (use (match_dup 3)) | |
a7df97e6 | 5297 | (clobber (match_dup 4)) |
9ebbca7d | 5298 | (clobber (match_dup 5))])] |
31bfaa0b | 5299 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5300 | " |
5301 | { | |
802a0058 MM |
5302 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5303 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); | |
9ebbca7d GK |
5304 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5305 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5306 | }") |
5307 | ||
802a0058 MM |
5308 | (define_insn "*floatunssidf2_internal" |
5309 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5310 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5311 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5312 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5313 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5314 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))] | |
31bfaa0b | 5315 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5316 | "#" |
a7df97e6 | 5317 | [(set_attr "length" "20")]) |
802a0058 MM |
5318 | |
5319 | (define_split | |
5320 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5321 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5322 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5323 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5324 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5325 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
31bfaa0b | 5326 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5327 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5328 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5329 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5330 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5331 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5332 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5333 | " | |
802a0058 | 5334 | { |
9ebbca7d GK |
5335 | rtx lowword, highword; |
5336 | if (GET_CODE (operands[4]) != MEM) | |
5337 | abort(); | |
5338 | highword = XEXP (operands[4], 0); | |
5339 | lowword = plus_constant (highword, 4); | |
5340 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5341 | { |
9ebbca7d GK |
5342 | rtx tmp; |
5343 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5344 | } |
802a0058 | 5345 | |
9ebbca7d GK |
5346 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5347 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5348 | emit_move_insn (operands[5], operands[4]); | |
5349 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5350 | DONE; | |
5351 | }") | |
1fd4e8c1 | 5352 | |
1fd4e8c1 | 5353 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5354 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5355 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5356 | (clobber (match_dup 2)) | |
9ebbca7d | 5357 | (clobber (match_dup 3))])] |
9cb8fcaf | 5358 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5359 | " |
5360 | { | |
802a0058 | 5361 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5362 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5363 | }") |
5364 | ||
802a0058 MM |
5365 | (define_insn "*fix_truncdfsi2_internal" |
5366 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5367 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5368 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) | |
9ebbca7d | 5369 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
9cb8fcaf | 5370 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
802a0058 | 5371 | "#" |
9ebbca7d | 5372 | [(set_attr "length" "16")]) |
802a0058 MM |
5373 | |
5374 | (define_split | |
5375 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5376 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5377 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
9ebbca7d | 5378 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
9cb8fcaf | 5379 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5380 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5381 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5382 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
5383 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5384 | " | |
802a0058 | 5385 | { |
9ebbca7d GK |
5386 | rtx lowword; |
5387 | if (GET_CODE (operands[3]) != MEM) | |
5388 | abort(); | |
5389 | lowword = XEXP (operands[3], 0); | |
5390 | if (WORDS_BIG_ENDIAN) | |
5391 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5392 | |
9ebbca7d GK |
5393 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5394 | emit_move_insn (operands[3], operands[2]); | |
5395 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5396 | DONE; | |
5397 | }") | |
802a0058 | 5398 | |
9ebbca7d GK |
5399 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10)) |
5400 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) | |
5401 | ; because the first makes it clear that operand 0 is not live | |
5402 | ; before the instruction. | |
5403 | (define_insn "fctiwz" | |
5404 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5405 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] | |
a260abc9 DE |
5406 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
5407 | "{fcirz|fctiwz} %0,%1" | |
5408 | [(set_attr "type" "fp")]) | |
5409 | ||
a473029f RK |
5410 | (define_insn "floatdidf2" |
5411 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5412 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5413 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5414 | "fcfid %0,%1" |
5415 | [(set_attr "type" "fp")]) | |
5416 | ||
5417 | (define_insn "fix_truncdfdi2" | |
5418 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5419 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5420 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5421 | "fctidz %0,%1" |
5422 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5423 | \f |
5424 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5425 | ;; of instructions. The & constraints are to prevent the register |
5426 | ;; allocator from allocating registers that overlap with the inputs | |
5427 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5428 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5429 | |
266eb58a | 5430 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5431 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5432 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5433 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5434 | "! TARGET_POWERPC64" |
0f645302 MM |
5435 | "* |
5436 | { | |
5437 | if (WORDS_BIG_ENDIAN) | |
5438 | return (GET_CODE (operands[2])) != CONST_INT | |
5439 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5440 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5441 | else | |
5442 | return (GET_CODE (operands[2])) != CONST_INT | |
5443 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5444 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5445 | }" | |
b19003d8 | 5446 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5447 | |
266eb58a | 5448 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5449 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5450 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5451 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5452 | "! TARGET_POWERPC64" |
5502823b RK |
5453 | "* |
5454 | { | |
0f645302 MM |
5455 | if (WORDS_BIG_ENDIAN) |
5456 | return (GET_CODE (operands[1]) != CONST_INT) | |
5457 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5458 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5459 | else | |
5460 | return (GET_CODE (operands[1]) != CONST_INT) | |
5461 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5462 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5463 | }" |
ca7f5001 RK |
5464 | [(set_attr "length" "8")]) |
5465 | ||
266eb58a | 5466 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5467 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5468 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5469 | "! TARGET_POWERPC64" |
5502823b RK |
5470 | "* |
5471 | { | |
5472 | return (WORDS_BIG_ENDIAN) | |
5473 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5474 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5475 | }" | |
ca7f5001 RK |
5476 | [(set_attr "length" "8")]) |
5477 | ||
8ffd9c51 RK |
5478 | (define_expand "mulsidi3" |
5479 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5480 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5481 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5482 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5483 | " |
5484 | { | |
5485 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5486 | { | |
39403d82 DE |
5487 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5488 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5489 | emit_insn (gen_mull_call ()); |
cf27b467 | 5490 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5491 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5492 | else |
5493 | { | |
5494 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5495 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5496 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5497 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5498 | } |
8ffd9c51 RK |
5499 | DONE; |
5500 | } | |
5501 | else if (TARGET_POWER) | |
5502 | { | |
5503 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5504 | DONE; | |
5505 | } | |
5506 | }") | |
deb9225a | 5507 | |
8ffd9c51 | 5508 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5509 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5510 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5511 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5512 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5513 | "TARGET_POWER" |
b19003d8 | 5514 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5515 | [(set_attr "type" "imul") |
5516 | (set_attr "length" "8")]) | |
deb9225a | 5517 | |
f192bf8b | 5518 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5519 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5520 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5521 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5522 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5523 | "* |
5524 | { | |
5525 | return (WORDS_BIG_ENDIAN) | |
5526 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5527 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5528 | }" | |
8ffd9c51 RK |
5529 | [(set_attr "type" "imul") |
5530 | (set_attr "length" "8")]) | |
deb9225a | 5531 | |
ebedb4dd MM |
5532 | (define_split |
5533 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5534 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5535 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5536 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5537 | [(set (match_dup 3) |
5538 | (truncate:SI | |
5539 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5540 | (sign_extend:DI (match_dup 2))) | |
5541 | (const_int 32)))) | |
5542 | (set (match_dup 4) | |
5543 | (mult:SI (match_dup 1) | |
5544 | (match_dup 2)))] | |
5545 | " | |
5546 | { | |
5547 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5548 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5549 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5550 | }") | |
5551 | ||
f192bf8b DE |
5552 | (define_expand "umulsidi3" |
5553 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5554 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5555 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5556 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5557 | " | |
5558 | { | |
5559 | if (TARGET_POWER) | |
5560 | { | |
5561 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5562 | DONE; | |
5563 | } | |
5564 | }") | |
5565 | ||
5566 | (define_insn "umulsidi3_mq" | |
5567 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5568 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5569 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5570 | (clobber (match_scratch:SI 3 "=q"))] | |
5571 | "TARGET_POWERPC && TARGET_POWER" | |
5572 | "* | |
5573 | { | |
5574 | return (WORDS_BIG_ENDIAN) | |
5575 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5576 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5577 | }" | |
5578 | [(set_attr "type" "imul") | |
5579 | (set_attr "length" "8")]) | |
5580 | ||
5581 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5582 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5583 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5584 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5585 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5586 | "* |
5587 | { | |
5588 | return (WORDS_BIG_ENDIAN) | |
5589 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5590 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5591 | }" | |
5592 | [(set_attr "type" "imul") | |
5593 | (set_attr "length" "8")]) | |
5594 | ||
ebedb4dd MM |
5595 | (define_split |
5596 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5597 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5598 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5599 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5600 | [(set (match_dup 3) |
5601 | (truncate:SI | |
5602 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5603 | (zero_extend:DI (match_dup 2))) | |
5604 | (const_int 32)))) | |
5605 | (set (match_dup 4) | |
5606 | (mult:SI (match_dup 1) | |
5607 | (match_dup 2)))] | |
5608 | " | |
5609 | { | |
5610 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5611 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5612 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5613 | }") | |
5614 | ||
8ffd9c51 RK |
5615 | (define_expand "smulsi3_highpart" |
5616 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5617 | (truncate:SI | |
5618 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5619 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5620 | (sign_extend:DI | |
5621 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5622 | (const_int 32))))] | |
5623 | "" | |
5624 | " | |
5625 | { | |
5626 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5627 | { | |
39403d82 DE |
5628 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5629 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5630 | emit_insn (gen_mulh_call ()); |
39403d82 | 5631 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5632 | DONE; |
5633 | } | |
5634 | else if (TARGET_POWER) | |
5635 | { | |
5636 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5637 | DONE; | |
5638 | } | |
5639 | }") | |
deb9225a | 5640 | |
8ffd9c51 RK |
5641 | (define_insn "smulsi3_highpart_mq" |
5642 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5643 | (truncate:SI | |
fada905b MM |
5644 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5645 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5646 | (sign_extend:DI | |
5647 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5648 | (const_int 32)))) |
5649 | (clobber (match_scratch:SI 3 "=q"))] | |
5650 | "TARGET_POWER" | |
5651 | "mul %0,%1,%2" | |
5652 | [(set_attr "type" "imul")]) | |
deb9225a | 5653 | |
f192bf8b | 5654 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5655 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5656 | (truncate:SI | |
fada905b MM |
5657 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5658 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5659 | (sign_extend:DI | |
5660 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5661 | (const_int 32))))] |
f192bf8b | 5662 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5663 | "mulhw %0,%1,%2" |
5664 | [(set_attr "type" "imul")]) | |
deb9225a | 5665 | |
f192bf8b DE |
5666 | (define_expand "umulsi3_highpart" |
5667 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5668 | (truncate:SI | |
5669 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5670 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5671 | (zero_extend:DI | |
5672 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5673 | (const_int 32))))] | |
5674 | "TARGET_POWERPC" | |
5675 | " | |
5676 | { | |
5677 | if (TARGET_POWER) | |
5678 | { | |
5679 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5680 | DONE; | |
5681 | } | |
5682 | }") | |
5683 | ||
5684 | (define_insn "umulsi3_highpart_mq" | |
5685 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5686 | (truncate:SI | |
5687 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5688 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5689 | (zero_extend:DI | |
5690 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5691 | (const_int 32)))) | |
5692 | (clobber (match_scratch:SI 3 "=q"))] | |
5693 | "TARGET_POWERPC && TARGET_POWER" | |
5694 | "mulhwu %0,%1,%2" | |
5695 | [(set_attr "type" "imul")]) | |
5696 | ||
5697 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5698 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5699 | (truncate:SI | |
5700 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5701 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5702 | (zero_extend:DI | |
5703 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5704 | (const_int 32))))] | |
f192bf8b | 5705 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5706 | "mulhwu %0,%1,%2" |
5707 | [(set_attr "type" "imul")]) | |
5708 | ||
5709 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5710 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5711 | ;; why we have the strange constraints below. | |
5712 | (define_insn "ashldi3_power" | |
5713 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5714 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5715 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5716 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5717 | "TARGET_POWER" | |
5718 | "@ | |
5719 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5720 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5721 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5722 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5723 | [(set_attr "length" "8")]) | |
5724 | ||
5725 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5726 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5727 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5728 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5729 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5730 | "TARGET_POWER" | |
5731 | "@ | |
47ad8c61 | 5732 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5733 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5734 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5735 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5736 | [(set_attr "length" "8")]) | |
5737 | ||
5738 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5739 | ;; just handle shifts by constants. | |
5740 | (define_insn "ashrdi3_power" | |
7093ddee | 5741 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5742 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5743 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5744 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5745 | "TARGET_POWER" | |
5746 | "@ | |
5747 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5748 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5749 | [(set_attr "length" "8")]) | |
5750 | \f | |
5751 | ;; PowerPC64 DImode operations. | |
5752 | ||
5753 | (define_expand "adddi3" | |
5754 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5755 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 5756 | (match_operand:DI 2 "reg_or_arith_cint_operand" "")))] |
266eb58a DE |
5757 | "" |
5758 | " | |
5759 | { | |
a260abc9 DE |
5760 | if (! TARGET_POWERPC64) |
5761 | { | |
5762 | if (non_short_cint_operand (operands[2], DImode)) | |
5763 | FAIL; | |
5764 | } | |
5765 | else | |
5766 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5767 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5768 | { |
677a9668 | 5769 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5770 | ? operands[0] : gen_reg_rtx (DImode)); |
5771 | ||
5772 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
5773 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
5774 | ||
5775 | if (low & 0x8000) | |
38886f37 AO |
5776 | { |
5777 | high = trunc_int_for_mode (high + 0x10000, SImode); | |
5778 | low = trunc_int_for_mode (low, HImode); | |
5779 | } | |
a260abc9 DE |
5780 | |
5781 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high))); | |
5782 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); | |
5783 | DONE; | |
5784 | } | |
266eb58a DE |
5785 | }") |
5786 | ||
5787 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5788 | ;; allowing register zero as source. | |
5789 | ||
a260abc9 | 5790 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5791 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5792 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5793 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5794 | "TARGET_POWERPC64" |
5795 | "@ | |
5796 | add %0,%1,%2 | |
5797 | addi %0,%1,%2 | |
5798 | addic %0,%1,%2 | |
802a0058 | 5799 | addis %0,%1,%v2") |
266eb58a | 5800 | |
a260abc9 | 5801 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5802 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5803 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5804 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5805 | (const_int 0))) |
9ebbca7d | 5806 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
266eb58a DE |
5807 | "TARGET_POWERPC64" |
5808 | "@ | |
5809 | add. %3,%1,%2 | |
9ebbca7d GK |
5810 | addic. %3,%1,%2 |
5811 | # | |
5812 | #" | |
5813 | [(set_attr "type" "compare") | |
5814 | (set_attr "length" "4,4,8,8")]) | |
5815 | ||
5816 | (define_split | |
5817 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5818 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5819 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5820 | (const_int 0))) | |
5821 | (clobber (match_scratch:DI 3 ""))] | |
5822 | "TARGET_POWERPC64 && reload_completed" | |
5823 | [(set (match_dup 3) | |
5824 | (plus:DI (match_dup 1) (match_dup 2))) | |
5825 | (set (match_dup 0) | |
5826 | (compare:CC (match_dup 3) | |
5827 | (const_int 0)))] | |
5828 | "") | |
266eb58a | 5829 | |
a260abc9 | 5830 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5831 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5832 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5833 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5834 | (const_int 0))) |
9ebbca7d | 5835 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a DE |
5836 | (plus:DI (match_dup 1) (match_dup 2)))] |
5837 | "TARGET_POWERPC64" | |
5838 | "@ | |
5839 | add. %0,%1,%2 | |
9ebbca7d GK |
5840 | addic. %0,%1,%2 |
5841 | # | |
5842 | #" | |
5843 | [(set_attr "type" "compare") | |
5844 | (set_attr "length" "4,4,8,8")]) | |
5845 | ||
5846 | (define_split | |
5847 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5848 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5849 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5850 | (const_int 0))) | |
5851 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5852 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5853 | "TARGET_POWERPC64 && reload_completed" | |
5854 | [(set (match_dup 0) | |
5855 | (plus:DI (match_dup 1) (match_dup 2))) | |
5856 | (set (match_dup 3) | |
5857 | (compare:CC (match_dup 0) | |
5858 | (const_int 0)))] | |
5859 | "") | |
266eb58a DE |
5860 | |
5861 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5862 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5863 | ;; add should be last in case the result gets used in an address. | |
5864 | ||
5865 | (define_split | |
5866 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5867 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5868 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5869 | "TARGET_POWERPC64" | |
5870 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5871 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5872 | " | |
5873 | { | |
e6ca2c17 DE |
5874 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
5875 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
266eb58a DE |
5876 | |
5877 | if (low & 0x8000) | |
38886f37 AO |
5878 | { |
5879 | high = trunc_int_for_mode (high + 0x10000, SImode); | |
5880 | low = trunc_int_for_mode (low, HImode); | |
5881 | } | |
266eb58a | 5882 | |
e6ca2c17 DE |
5883 | operands[3] = GEN_INT (high); |
5884 | operands[4] = GEN_INT (low); | |
266eb58a DE |
5885 | }") |
5886 | ||
5887 | (define_insn "one_cmpldi2" | |
5888 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5889 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5890 | "TARGET_POWERPC64" | |
5891 | "nor %0,%1,%1") | |
5892 | ||
5893 | (define_insn "" | |
9ebbca7d GK |
5894 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5895 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5896 | (const_int 0))) |
9ebbca7d | 5897 | (clobber (match_scratch:DI 2 "=r,r"))] |
266eb58a | 5898 | "TARGET_POWERPC64" |
9ebbca7d GK |
5899 | "@ |
5900 | nor. %2,%1,%1 | |
5901 | #" | |
5902 | [(set_attr "type" "compare") | |
5903 | (set_attr "length" "4,8")]) | |
5904 | ||
5905 | (define_split | |
5906 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5907 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5908 | (const_int 0))) | |
5909 | (clobber (match_scratch:DI 2 ""))] | |
5910 | "TARGET_POWERPC64 && reload_completed" | |
5911 | [(set (match_dup 2) | |
5912 | (not:DI (match_dup 1))) | |
5913 | (set (match_dup 0) | |
5914 | (compare:CC (match_dup 2) | |
5915 | (const_int 0)))] | |
5916 | "") | |
266eb58a DE |
5917 | |
5918 | (define_insn "" | |
9ebbca7d GK |
5919 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5920 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5921 | (const_int 0))) |
9ebbca7d | 5922 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5923 | (not:DI (match_dup 1)))] |
5924 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5925 | "@ |
5926 | nor. %0,%1,%1 | |
5927 | #" | |
5928 | [(set_attr "type" "compare") | |
5929 | (set_attr "length" "4,8")]) | |
5930 | ||
5931 | (define_split | |
5932 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5933 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5934 | (const_int 0))) | |
5935 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5936 | (not:DI (match_dup 1)))] | |
5937 | "TARGET_POWERPC64 && reload_completed" | |
5938 | [(set (match_dup 0) | |
5939 | (not:DI (match_dup 1))) | |
5940 | (set (match_dup 2) | |
5941 | (compare:CC (match_dup 0) | |
5942 | (const_int 0)))] | |
5943 | "") | |
266eb58a DE |
5944 | |
5945 | (define_insn "" | |
5946 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5947 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5948 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5949 | "TARGET_POWERPC64" | |
5950 | "@ | |
5951 | subf %0,%2,%1 | |
5952 | subfic %0,%2,%1") | |
5953 | ||
5954 | (define_insn "" | |
9ebbca7d GK |
5955 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5956 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5957 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5958 | (const_int 0))) |
9ebbca7d | 5959 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 5960 | "TARGET_POWERPC64" |
9ebbca7d GK |
5961 | "@ |
5962 | subf. %3,%2,%1 | |
5963 | #" | |
5964 | [(set_attr "type" "compare") | |
5965 | (set_attr "length" "4,8")]) | |
5966 | ||
5967 | (define_split | |
5968 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5969 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5970 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5971 | (const_int 0))) | |
5972 | (clobber (match_scratch:DI 3 ""))] | |
5973 | "TARGET_POWERPC64 && reload_completed" | |
5974 | [(set (match_dup 3) | |
5975 | (minus:DI (match_dup 1) (match_dup 2))) | |
5976 | (set (match_dup 0) | |
5977 | (compare:CC (match_dup 3) | |
5978 | (const_int 0)))] | |
5979 | "") | |
266eb58a DE |
5980 | |
5981 | (define_insn "" | |
9ebbca7d GK |
5982 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5983 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5984 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5985 | (const_int 0))) |
9ebbca7d | 5986 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5987 | (minus:DI (match_dup 1) (match_dup 2)))] |
5988 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5989 | "@ |
5990 | subf. %0,%2,%1 | |
5991 | #" | |
5992 | [(set_attr "type" "compare") | |
5993 | (set_attr "length" "4,8")]) | |
5994 | ||
5995 | (define_split | |
5996 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5997 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5998 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5999 | (const_int 0))) | |
6000 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6001 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6002 | "TARGET_POWERPC64 && reload_completed" | |
6003 | [(set (match_dup 0) | |
6004 | (minus:DI (match_dup 1) (match_dup 2))) | |
6005 | (set (match_dup 3) | |
6006 | (compare:CC (match_dup 0) | |
6007 | (const_int 0)))] | |
6008 | "") | |
266eb58a DE |
6009 | |
6010 | (define_expand "subdi3" | |
6011 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6012 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
f6bf7de2 | 6013 | (match_operand:DI 2 "reg_or_arith_cint_operand" "")))] |
266eb58a DE |
6014 | "" |
6015 | " | |
6016 | { | |
6017 | if (GET_CODE (operands[2]) == CONST_INT) | |
6018 | { | |
6019 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
6020 | negate_rtx (DImode, operands[2]))); | |
6021 | DONE; | |
6022 | } | |
6023 | }") | |
6024 | ||
6025 | (define_insn "absdi2" | |
6026 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
6027 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
6028 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
6029 | "TARGET_POWERPC64" | |
a260abc9 | 6030 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" |
266eb58a DE |
6031 | [(set_attr "length" "12")]) |
6032 | ||
6033 | (define_split | |
6034 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
6035 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
6036 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
6037 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 6038 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6039 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 6040 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
6041 | "") |
6042 | ||
19ba8161 | 6043 | (define_insn "*nabsdi2" |
266eb58a DE |
6044 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
6045 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
6046 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
6047 | "TARGET_POWERPC64" | |
a260abc9 | 6048 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" |
266eb58a DE |
6049 | [(set_attr "length" "12")]) |
6050 | ||
6051 | (define_split | |
6052 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
6053 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
6054 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
6055 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 6056 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6057 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 6058 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
6059 | "") |
6060 | ||
6061 | (define_expand "negdi2" | |
6062 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6063 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
6064 | "" | |
6065 | "") | |
6066 | ||
6067 | (define_insn "" | |
6068 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6069 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6070 | "TARGET_POWERPC64" | |
6071 | "neg %0,%1") | |
6072 | ||
6073 | (define_insn "" | |
9ebbca7d GK |
6074 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6075 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6076 | (const_int 0))) |
9ebbca7d | 6077 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 6078 | "TARGET_POWERPC64" |
9ebbca7d GK |
6079 | "@ |
6080 | neg. %2,%1 | |
6081 | #" | |
6082 | [(set_attr "type" "compare") | |
6083 | (set_attr "length" "4,8")]) | |
6084 | ||
6085 | (define_split | |
6086 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6087 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6088 | (const_int 0))) | |
6089 | (clobber (match_scratch:DI 2 ""))] | |
6090 | "TARGET_POWERPC64 && reload_completed" | |
6091 | [(set (match_dup 2) | |
6092 | (neg:DI (match_dup 1))) | |
6093 | (set (match_dup 0) | |
6094 | (compare:CC (match_dup 2) | |
6095 | (const_int 0)))] | |
6096 | "") | |
815cdc52 | 6097 | |
29ae5b89 | 6098 | (define_insn "" |
9ebbca7d GK |
6099 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6100 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6101 | (const_int 0))) |
9ebbca7d | 6102 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6103 | (neg:DI (match_dup 1)))] |
29ae5b89 | 6104 | "TARGET_POWERPC64" |
9ebbca7d GK |
6105 | "@ |
6106 | neg. %0,%1 | |
6107 | #" | |
6108 | [(set_attr "type" "compare") | |
6109 | (set_attr "length" "4,8")]) | |
6110 | ||
6111 | (define_split | |
6112 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6113 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6114 | (const_int 0))) | |
6115 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6116 | (neg:DI (match_dup 1)))] | |
6117 | "TARGET_POWERPC64 && reload_completed" | |
6118 | [(set (match_dup 0) | |
6119 | (neg:DI (match_dup 1))) | |
6120 | (set (match_dup 2) | |
6121 | (compare:CC (match_dup 0) | |
6122 | (const_int 0)))] | |
6123 | "") | |
266eb58a DE |
6124 | |
6125 | (define_insn "ffsdi2" | |
6126 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
6127 | (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6128 | "TARGET_POWERPC64" | |
6129 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
6130 | [(set_attr "length" "16")]) | |
6131 | ||
6132 | (define_insn "muldi3" | |
6133 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6134 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6135 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6136 | "TARGET_POWERPC64" | |
6137 | "mulld %0,%1,%2" | |
3cb999d8 | 6138 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6139 | |
6140 | (define_insn "smuldi3_highpart" | |
6141 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6142 | (truncate:DI | |
6143 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6144 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6145 | (sign_extend:TI | |
6146 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6147 | (const_int 64))))] | |
6148 | "TARGET_POWERPC64" | |
6149 | "mulhd %0,%1,%2" | |
3cb999d8 | 6150 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6151 | |
6152 | (define_insn "umuldi3_highpart" | |
6153 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6154 | (truncate:DI | |
6155 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6156 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6157 | (zero_extend:TI | |
6158 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6159 | (const_int 64))))] | |
6160 | "TARGET_POWERPC64" | |
6161 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6162 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6163 | |
6164 | (define_expand "divdi3" | |
6165 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6166 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6167 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6168 | "TARGET_POWERPC64" | |
6169 | " | |
6170 | { | |
6171 | if (GET_CODE (operands[2]) == CONST_INT | |
6172 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
6173 | ; | |
6174 | else | |
6175 | operands[2] = force_reg (DImode, operands[2]); | |
6176 | }") | |
6177 | ||
6178 | (define_expand "moddi3" | |
6179 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6180 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6181 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6182 | "TARGET_POWERPC64" | |
6183 | " | |
6184 | { | |
6185 | int i = exact_log2 (INTVAL (operands[2])); | |
6186 | rtx temp1; | |
6187 | rtx temp2; | |
6188 | ||
6189 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) | |
6190 | FAIL; | |
6191 | ||
6192 | temp1 = gen_reg_rtx (DImode); | |
6193 | temp2 = gen_reg_rtx (DImode); | |
6194 | ||
6195 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6196 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6197 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6198 | DONE; | |
6199 | }") | |
6200 | ||
6201 | (define_insn "" | |
6202 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6203 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6204 | (match_operand:DI 2 "const_int_operand" "N")))] | |
6205 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
6206 | "sradi %0,%1,%p2\;addze %0,%0" | |
6207 | [(set_attr "length" "8")]) | |
6208 | ||
6209 | (define_insn "" | |
9ebbca7d GK |
6210 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6211 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6212 | (match_operand:DI 2 "const_int_operand" "N,N")) | |
266eb58a | 6213 | (const_int 0))) |
9ebbca7d | 6214 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6215 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" |
9ebbca7d GK |
6216 | "@ |
6217 | sradi %3,%1,%p2\;addze. %3,%3 | |
6218 | #" | |
266eb58a | 6219 | [(set_attr "type" "compare") |
9ebbca7d GK |
6220 | (set_attr "length" "8,12")]) |
6221 | ||
6222 | (define_split | |
6223 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6224 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6225 | (match_operand:DI 2 "const_int_operand" "")) | |
6226 | (const_int 0))) | |
6227 | (clobber (match_scratch:DI 3 ""))] | |
6228 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
6229 | [(set (match_dup 3) | |
6230 | (div:DI (match_dup 1) (match_dup 2))) | |
6231 | (set (match_dup 0) | |
6232 | (compare:CC (match_dup 3) | |
6233 | (const_int 0)))] | |
6234 | "") | |
266eb58a DE |
6235 | |
6236 | (define_insn "" | |
9ebbca7d GK |
6237 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6238 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6239 | (match_operand:DI 2 "const_int_operand" "N,N")) | |
266eb58a | 6240 | (const_int 0))) |
9ebbca7d | 6241 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6242 | (div:DI (match_dup 1) (match_dup 2)))] |
6243 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
9ebbca7d GK |
6244 | "@ |
6245 | sradi %0,%1,%p2\;addze. %0,%0 | |
6246 | #" | |
266eb58a | 6247 | [(set_attr "type" "compare") |
9ebbca7d | 6248 | (set_attr "length" "8,12")]) |
266eb58a | 6249 | |
9ebbca7d GK |
6250 | (define_split |
6251 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6252 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6253 | (match_operand:DI 2 "const_int_operand" "")) | |
6254 | (const_int 0))) | |
6255 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6256 | (div:DI (match_dup 1) (match_dup 2)))] | |
6257 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
6258 | [(set (match_dup 0) | |
6259 | (div:DI (match_dup 1) (match_dup 2))) | |
6260 | (set (match_dup 3) | |
6261 | (compare:CC (match_dup 0) | |
6262 | (const_int 0)))] | |
6263 | "") | |
6264 | ||
6265 | (define_insn "" | |
6266 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6267 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6268 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6269 | "TARGET_POWERPC64" |
6270 | "divd %0,%1,%2" | |
3cb999d8 | 6271 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6272 | |
6273 | (define_insn "udivdi3" | |
6274 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6275 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6276 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6277 | "TARGET_POWERPC64" | |
6278 | "divdu %0,%1,%2" | |
3cb999d8 | 6279 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6280 | |
6281 | (define_insn "rotldi3" | |
6282 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6283 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6284 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6285 | "TARGET_POWERPC64" | |
a66078ee | 6286 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6287 | |
a260abc9 | 6288 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6289 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6290 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6291 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6292 | (const_int 0))) |
9ebbca7d | 6293 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6294 | "TARGET_POWERPC64" |
9ebbca7d GK |
6295 | "@ |
6296 | rld%I2cl. %3,%1,%H2,0 | |
6297 | #" | |
6298 | [(set_attr "type" "delayed_compare") | |
6299 | (set_attr "length" "4,8")]) | |
6300 | ||
6301 | (define_split | |
6302 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6303 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6304 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6305 | (const_int 0))) | |
6306 | (clobber (match_scratch:DI 3 ""))] | |
6307 | "TARGET_POWERPC64 && reload_completed" | |
6308 | [(set (match_dup 3) | |
6309 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6310 | (set (match_dup 0) | |
6311 | (compare:CC (match_dup 3) | |
6312 | (const_int 0)))] | |
6313 | "") | |
266eb58a | 6314 | |
a260abc9 | 6315 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6316 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6317 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6318 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6319 | (const_int 0))) |
9ebbca7d | 6320 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6321 | (rotate:DI (match_dup 1) (match_dup 2)))] |
6322 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6323 | "@ |
6324 | rld%I2cl. %0,%1,%H2,0 | |
6325 | #" | |
6326 | [(set_attr "type" "delayed_compare") | |
6327 | (set_attr "length" "4,8")]) | |
6328 | ||
6329 | (define_split | |
6330 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6331 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6332 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6333 | (const_int 0))) | |
6334 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6335 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6336 | "TARGET_POWERPC64 && reload_completed" | |
6337 | [(set (match_dup 0) | |
6338 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6339 | (set (match_dup 3) | |
6340 | (compare:CC (match_dup 0) | |
6341 | (const_int 0)))] | |
6342 | "") | |
266eb58a | 6343 | |
a260abc9 DE |
6344 | (define_insn "*rotldi3_internal4" |
6345 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6346 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6347 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
6348 | (match_operand:DI 3 "mask64_operand" "S")))] | |
6349 | "TARGET_POWERPC64" | |
6350 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6351 | ||
6352 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6353 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6354 | (compare:CC (and:DI |
9ebbca7d GK |
6355 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6356 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6357 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6358 | (const_int 0))) |
9ebbca7d | 6359 | (clobber (match_scratch:DI 4 "=r,r"))] |
a260abc9 | 6360 | "TARGET_POWERPC64" |
9ebbca7d GK |
6361 | "@ |
6362 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6363 | #" | |
6364 | [(set_attr "type" "delayed_compare") | |
6365 | (set_attr "length" "4,8")]) | |
6366 | ||
6367 | (define_split | |
6368 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6369 | (compare:CC (and:DI | |
6370 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6371 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6372 | (match_operand:DI 3 "mask64_operand" "")) | |
6373 | (const_int 0))) | |
6374 | (clobber (match_scratch:DI 4 ""))] | |
6375 | "TARGET_POWERPC64 && reload_completed" | |
6376 | [(set (match_dup 4) | |
6377 | (and:DI (rotate:DI (match_dup 1) | |
6378 | (match_dup 2)) | |
6379 | (match_dup 3))) | |
6380 | (set (match_dup 0) | |
6381 | (compare:CC (match_dup 4) | |
6382 | (const_int 0)))] | |
6383 | "") | |
a260abc9 DE |
6384 | |
6385 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6386 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6387 | (compare:CC (and:DI |
9ebbca7d GK |
6388 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6389 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6390 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6391 | (const_int 0))) |
9ebbca7d | 6392 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6393 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
6394 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6395 | "@ |
6396 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6397 | #" | |
6398 | [(set_attr "type" "delayed_compare") | |
6399 | (set_attr "length" "4,8")]) | |
6400 | ||
6401 | (define_split | |
6402 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6403 | (compare:CC (and:DI | |
6404 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6405 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6406 | (match_operand:DI 3 "mask64_operand" "")) | |
6407 | (const_int 0))) | |
6408 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6409 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6410 | "TARGET_POWERPC64 && reload_completed" | |
6411 | [(set (match_dup 0) | |
6412 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6413 | (set (match_dup 4) | |
6414 | (compare:CC (match_dup 0) | |
6415 | (const_int 0)))] | |
6416 | "") | |
a260abc9 DE |
6417 | |
6418 | (define_insn "*rotldi3_internal7" | |
6419 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6420 | (zero_extend:DI | |
6421 | (subreg:QI | |
6422 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6423 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6424 | "TARGET_POWERPC64" | |
6425 | "rld%I2cl %0,%1,%H2,56") | |
6426 | ||
6427 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6428 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6429 | (compare:CC (zero_extend:DI |
6430 | (subreg:QI | |
9ebbca7d GK |
6431 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6432 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6433 | (const_int 0))) |
9ebbca7d | 6434 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6435 | "TARGET_POWERPC64" |
9ebbca7d GK |
6436 | "@ |
6437 | rld%I2cl. %3,%1,%H2,56 | |
6438 | #" | |
6439 | [(set_attr "type" "delayed_compare") | |
6440 | (set_attr "length" "4,8")]) | |
6441 | ||
6442 | (define_split | |
6443 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6444 | (compare:CC (zero_extend:DI | |
6445 | (subreg:QI | |
6446 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6447 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6448 | (const_int 0))) | |
6449 | (clobber (match_scratch:DI 3 ""))] | |
6450 | "TARGET_POWERPC64 && reload_completed" | |
6451 | [(set (match_dup 3) | |
6452 | (zero_extend:DI (subreg:QI | |
6453 | (rotate:DI (match_dup 1) | |
6454 | (match_dup 2)) 0))) | |
6455 | (set (match_dup 0) | |
6456 | (compare:CC (match_dup 3) | |
6457 | (const_int 0)))] | |
6458 | "") | |
a260abc9 DE |
6459 | |
6460 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6461 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6462 | (compare:CC (zero_extend:DI |
6463 | (subreg:QI | |
9ebbca7d GK |
6464 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6465 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6466 | (const_int 0))) |
9ebbca7d | 6467 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6468 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6469 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6470 | "@ |
6471 | rld%I2cl. %0,%1,%H2,56 | |
6472 | #" | |
6473 | [(set_attr "type" "delayed_compare") | |
6474 | (set_attr "length" "4,8")]) | |
6475 | ||
6476 | (define_split | |
6477 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6478 | (compare:CC (zero_extend:DI | |
6479 | (subreg:QI | |
6480 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6481 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6482 | (const_int 0))) | |
6483 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6484 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6485 | "TARGET_POWERPC64 && reload_completed" | |
6486 | [(set (match_dup 0) | |
6487 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6488 | (set (match_dup 3) | |
6489 | (compare:CC (match_dup 0) | |
6490 | (const_int 0)))] | |
6491 | "") | |
a260abc9 DE |
6492 | |
6493 | (define_insn "*rotldi3_internal10" | |
6494 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6495 | (zero_extend:DI | |
6496 | (subreg:HI | |
6497 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6498 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6499 | "TARGET_POWERPC64" | |
6500 | "rld%I2cl %0,%1,%H2,48") | |
6501 | ||
6502 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6503 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6504 | (compare:CC (zero_extend:DI |
6505 | (subreg:HI | |
9ebbca7d GK |
6506 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6507 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6508 | (const_int 0))) |
9ebbca7d | 6509 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6510 | "TARGET_POWERPC64" |
9ebbca7d GK |
6511 | "@ |
6512 | rld%I2cl. %3,%1,%H2,48 | |
6513 | #" | |
6514 | [(set_attr "type" "delayed_compare") | |
6515 | (set_attr "length" "4,8")]) | |
6516 | ||
6517 | (define_split | |
6518 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6519 | (compare:CC (zero_extend:DI | |
6520 | (subreg:HI | |
6521 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6522 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6523 | (const_int 0))) | |
6524 | (clobber (match_scratch:DI 3 ""))] | |
6525 | "TARGET_POWERPC64 && reload_completed" | |
6526 | [(set (match_dup 3) | |
6527 | (zero_extend:DI (subreg:HI | |
6528 | (rotate:DI (match_dup 1) | |
6529 | (match_dup 2)) 0))) | |
6530 | (set (match_dup 0) | |
6531 | (compare:CC (match_dup 3) | |
6532 | (const_int 0)))] | |
6533 | "") | |
a260abc9 DE |
6534 | |
6535 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6536 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6537 | (compare:CC (zero_extend:DI |
6538 | (subreg:HI | |
9ebbca7d GK |
6539 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6540 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6541 | (const_int 0))) |
9ebbca7d | 6542 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6543 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6544 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6545 | "@ |
6546 | rld%I2cl. %0,%1,%H2,48 | |
6547 | #" | |
6548 | [(set_attr "type" "delayed_compare") | |
6549 | (set_attr "length" "4,8")]) | |
6550 | ||
6551 | (define_split | |
6552 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6553 | (compare:CC (zero_extend:DI | |
6554 | (subreg:HI | |
6555 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6556 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6557 | (const_int 0))) | |
6558 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6559 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6560 | "TARGET_POWERPC64 && reload_completed" | |
6561 | [(set (match_dup 0) | |
6562 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6563 | (set (match_dup 3) | |
6564 | (compare:CC (match_dup 0) | |
6565 | (const_int 0)))] | |
6566 | "") | |
a260abc9 DE |
6567 | |
6568 | (define_insn "*rotldi3_internal13" | |
6569 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6570 | (zero_extend:DI | |
6571 | (subreg:SI | |
6572 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6573 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6574 | "TARGET_POWERPC64" | |
6575 | "rld%I2cl %0,%1,%H2,32") | |
6576 | ||
6577 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6578 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6579 | (compare:CC (zero_extend:DI |
6580 | (subreg:SI | |
9ebbca7d GK |
6581 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6582 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6583 | (const_int 0))) |
9ebbca7d | 6584 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6585 | "TARGET_POWERPC64" |
9ebbca7d GK |
6586 | "@ |
6587 | rld%I2cl. %3,%1,%H2,32 | |
6588 | #" | |
6589 | [(set_attr "type" "delayed_compare") | |
6590 | (set_attr "length" "4,8")]) | |
6591 | ||
6592 | (define_split | |
6593 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6594 | (compare:CC (zero_extend:DI | |
6595 | (subreg:SI | |
6596 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6597 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6598 | (const_int 0))) | |
6599 | (clobber (match_scratch:DI 3 ""))] | |
6600 | "TARGET_POWERPC64 && reload_completed" | |
6601 | [(set (match_dup 3) | |
6602 | (zero_extend:DI (subreg:SI | |
6603 | (rotate:DI (match_dup 1) | |
6604 | (match_dup 2)) 0))) | |
6605 | (set (match_dup 0) | |
6606 | (compare:CC (match_dup 3) | |
6607 | (const_int 0)))] | |
6608 | "") | |
a260abc9 DE |
6609 | |
6610 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6611 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6612 | (compare:CC (zero_extend:DI |
6613 | (subreg:SI | |
9ebbca7d GK |
6614 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6615 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6616 | (const_int 0))) |
9ebbca7d | 6617 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6618 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6619 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6620 | "@ |
6621 | rld%I2cl. %0,%1,%H2,32 | |
6622 | #" | |
6623 | [(set_attr "type" "delayed_compare") | |
6624 | (set_attr "length" "4,8")]) | |
6625 | ||
6626 | (define_split | |
6627 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6628 | (compare:CC (zero_extend:DI | |
6629 | (subreg:SI | |
6630 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6631 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6632 | (const_int 0))) | |
6633 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6634 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6635 | "TARGET_POWERPC64 && reload_completed" | |
6636 | [(set (match_dup 0) | |
6637 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6638 | (set (match_dup 3) | |
6639 | (compare:CC (match_dup 0) | |
6640 | (const_int 0)))] | |
6641 | "") | |
a260abc9 | 6642 | |
266eb58a DE |
6643 | (define_expand "ashldi3" |
6644 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6645 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6646 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6647 | "TARGET_POWERPC64 || TARGET_POWER" | |
6648 | " | |
6649 | { | |
6650 | if (TARGET_POWERPC64) | |
6651 | ; | |
6652 | else if (TARGET_POWER) | |
6653 | { | |
6654 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6655 | DONE; | |
6656 | } | |
6657 | else | |
6658 | FAIL; | |
6659 | }") | |
6660 | ||
e2c953b6 | 6661 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6662 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6663 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6664 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6665 | "TARGET_POWERPC64" | |
a66078ee | 6666 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
6667 | [(set_attr "length" "8")]) |
6668 | ||
e2c953b6 | 6669 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6670 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6671 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6672 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6673 | (const_int 0))) |
9ebbca7d | 6674 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6675 | "TARGET_POWERPC64" |
9ebbca7d GK |
6676 | "@ |
6677 | sld%I2. %3,%1,%H2 | |
6678 | #" | |
6679 | [(set_attr "type" "delayed_compare") | |
6680 | (set_attr "length" "4,8")]) | |
29ae5b89 | 6681 | |
9ebbca7d GK |
6682 | (define_split |
6683 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6684 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6685 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6686 | (const_int 0))) | |
6687 | (clobber (match_scratch:DI 3 ""))] | |
6688 | "TARGET_POWERPC64 && reload_completed" | |
6689 | [(set (match_dup 3) | |
6690 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6691 | (set (match_dup 0) | |
6692 | (compare:CC (match_dup 3) | |
6693 | (const_int 0)))] | |
6694 | "") | |
6695 | ||
e2c953b6 | 6696 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6697 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6698 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6699 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6700 | (const_int 0))) |
9ebbca7d | 6701 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6702 | (ashift:DI (match_dup 1) (match_dup 2)))] |
6703 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6704 | "@ |
6705 | sld%I2. %0,%1,%H2 | |
6706 | #" | |
6707 | [(set_attr "type" "delayed_compare") | |
6708 | (set_attr "length" "4,8")]) | |
6709 | ||
6710 | (define_split | |
6711 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6712 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6713 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6714 | (const_int 0))) | |
6715 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6716 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6717 | "TARGET_POWERPC64 && reload_completed" | |
6718 | [(set (match_dup 0) | |
6719 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6720 | (set (match_dup 3) | |
6721 | (compare:CC (match_dup 0) | |
6722 | (const_int 0)))] | |
6723 | "") | |
266eb58a | 6724 | |
e2c953b6 | 6725 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6726 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6727 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6728 | (match_operand:SI 2 "const_int_operand" "i")) | |
e2c953b6 DE |
6729 | (match_operand:DI 3 "rldic_operand" "n")))] |
6730 | "includes_lshift64_p (operands[2], operands[3])" | |
6731 | "rldic %0,%1,%H2,%W3") | |
3cb999d8 | 6732 | |
e2c953b6 | 6733 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6734 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6735 | (compare:CC |
9ebbca7d GK |
6736 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6737 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
e2c953b6 | 6738 | (match_operand:DI 3 "rldic_operand" "n,n")) |
3cb999d8 | 6739 | (const_int 0))) |
9ebbca7d | 6740 | (clobber (match_scratch:DI 4 "=r,r"))] |
e2c953b6 | 6741 | "includes_lshift64_p (operands[2], operands[3])" |
9ebbca7d | 6742 | "@ |
e2c953b6 | 6743 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6744 | #" |
6745 | [(set_attr "type" "delayed_compare") | |
6746 | (set_attr "length" "4,8")]) | |
6747 | ||
6748 | (define_split | |
6749 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6750 | (compare:CC | |
6751 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6752 | (match_operand:SI 2 "const_int_operand" "")) | |
e2c953b6 | 6753 | (match_operand:DI 3 "rldic_operand" "")) |
9ebbca7d GK |
6754 | (const_int 0))) |
6755 | (clobber (match_scratch:DI 4 ""))] | |
e2c953b6 | 6756 | "includes_lshift64_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
6757 | [(set (match_dup 4) |
6758 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6759 | (match_dup 3))) |
9ebbca7d GK |
6760 | (set (match_dup 0) |
6761 | (compare:CC (match_dup 4) | |
6762 | (const_int 0)))] | |
6763 | "") | |
3cb999d8 | 6764 | |
e2c953b6 | 6765 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6766 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6767 | (compare:CC |
9ebbca7d GK |
6768 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6769 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
e2c953b6 | 6770 | (match_operand:DI 3 "rldic_operand" "n,n")) |
3cb999d8 | 6771 | (const_int 0))) |
9ebbca7d | 6772 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6773 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
e2c953b6 | 6774 | "includes_lshift64_p (operands[2], operands[3])" |
9ebbca7d | 6775 | "@ |
e2c953b6 | 6776 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6777 | #" |
6778 | [(set_attr "type" "delayed_compare") | |
6779 | (set_attr "length" "4,8")]) | |
6780 | ||
6781 | (define_split | |
6782 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6783 | (compare:CC | |
6784 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6785 | (match_operand:SI 2 "const_int_operand" "")) | |
e2c953b6 | 6786 | (match_operand:DI 3 "rldic_operand" "")) |
9ebbca7d GK |
6787 | (const_int 0))) |
6788 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6789 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
e2c953b6 | 6790 | "includes_lshift64_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d | 6791 | [(set (match_dup 0) |
e2c953b6 DE |
6792 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6793 | (match_dup 3))) | |
9ebbca7d GK |
6794 | (set (match_dup 4) |
6795 | (compare:CC (match_dup 0) | |
6796 | (const_int 0)))] | |
6797 | "") | |
6798 | ||
6799 | (define_expand "lshrdi3" | |
266eb58a DE |
6800 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6801 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6802 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6803 | "TARGET_POWERPC64 || TARGET_POWER" | |
6804 | " | |
6805 | { | |
6806 | if (TARGET_POWERPC64) | |
6807 | ; | |
6808 | else if (TARGET_POWER) | |
6809 | { | |
6810 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6811 | DONE; | |
6812 | } | |
6813 | else | |
6814 | FAIL; | |
6815 | }") | |
6816 | ||
e2c953b6 | 6817 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6818 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6819 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6820 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6821 | "TARGET_POWERPC64" | |
a66078ee | 6822 | "srd%I2 %0,%1,%H2") |
266eb58a | 6823 | |
e2c953b6 | 6824 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6825 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6826 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6827 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6828 | (const_int 0))) |
9ebbca7d | 6829 | (clobber (match_scratch:DI 3 "=r,r"))] |
29ae5b89 | 6830 | "TARGET_POWERPC64" |
9ebbca7d GK |
6831 | "@ |
6832 | srd%I2. %3,%1,%H2 | |
6833 | #" | |
6834 | [(set_attr "type" "delayed_compare") | |
6835 | (set_attr "length" "4,8")]) | |
6836 | ||
6837 | (define_split | |
6838 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6839 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6840 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6841 | (const_int 0))) | |
6842 | (clobber (match_scratch:DI 3 ""))] | |
6843 | "TARGET_POWERPC64 && reload_completed" | |
6844 | [(set (match_dup 3) | |
6845 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6846 | (set (match_dup 0) | |
6847 | (compare:CC (match_dup 3) | |
6848 | (const_int 0)))] | |
6849 | "") | |
266eb58a | 6850 | |
e2c953b6 | 6851 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6852 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6853 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6854 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6855 | (const_int 0))) |
9ebbca7d | 6856 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 JL |
6857 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
6858 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6859 | "@ |
6860 | srd%I2. %0,%1,%H2 | |
6861 | #" | |
6862 | [(set_attr "type" "delayed_compare") | |
6863 | (set_attr "length" "4,8")]) | |
6864 | ||
6865 | (define_split | |
6866 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6867 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6868 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6869 | (const_int 0))) | |
6870 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6871 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6872 | "TARGET_POWERPC64 && reload_completed" | |
6873 | [(set (match_dup 0) | |
6874 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6875 | (set (match_dup 3) | |
6876 | (compare:CC (match_dup 0) | |
6877 | (const_int 0)))] | |
6878 | "") | |
266eb58a DE |
6879 | |
6880 | (define_expand "ashrdi3" | |
6881 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6882 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6883 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6884 | "TARGET_POWERPC64 || TARGET_POWER" | |
6885 | " | |
6886 | { | |
6887 | if (TARGET_POWERPC64) | |
6888 | ; | |
6889 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6890 | { | |
6891 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6892 | DONE; | |
6893 | } | |
6894 | else | |
6895 | FAIL; | |
6896 | }") | |
6897 | ||
e2c953b6 | 6898 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
6899 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6900 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6901 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6902 | "TARGET_POWERPC64" | |
375490e0 | 6903 | "srad%I2 %0,%1,%H2") |
266eb58a | 6904 | |
e2c953b6 | 6905 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
6906 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6907 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6908 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6909 | (const_int 0))) |
9ebbca7d | 6910 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6911 | "TARGET_POWERPC64" |
9ebbca7d GK |
6912 | "@ |
6913 | srad%I2. %3,%1,%H2 | |
6914 | #" | |
6915 | [(set_attr "type" "delayed_compare") | |
6916 | (set_attr "length" "4,8")]) | |
6917 | ||
6918 | (define_split | |
6919 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6920 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6921 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6922 | (const_int 0))) | |
6923 | (clobber (match_scratch:DI 3 ""))] | |
6924 | "TARGET_POWERPC64 && reload_completed" | |
6925 | [(set (match_dup 3) | |
6926 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6927 | (set (match_dup 0) | |
6928 | (compare:CC (match_dup 3) | |
6929 | (const_int 0)))] | |
6930 | "") | |
266eb58a | 6931 | |
e2c953b6 | 6932 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
6933 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6934 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6935 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6936 | (const_int 0))) |
9ebbca7d | 6937 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6938 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6939 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6940 | "@ |
6941 | srad%I2. %0,%1,%H2 | |
6942 | #" | |
6943 | [(set_attr "type" "delayed_compare") | |
6944 | (set_attr "length" "4,8")]) | |
6945 | ||
6946 | (define_split | |
6947 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6948 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6949 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6950 | (const_int 0))) | |
6951 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6952 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
6953 | "TARGET_POWERPC64 && reload_completed" | |
6954 | [(set (match_dup 0) | |
6955 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6956 | (set (match_dup 3) | |
6957 | (compare:CC (match_dup 0) | |
6958 | (const_int 0)))] | |
6959 | "") | |
815cdc52 | 6960 | |
29ae5b89 JL |
6961 | (define_insn "anddi3" |
6962 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") | |
6963 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
6964 | (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) | |
6965 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
6ffc8580 | 6966 | "TARGET_POWERPC64" |
266eb58a DE |
6967 | "@ |
6968 | and %0,%1,%2 | |
29ae5b89 JL |
6969 | rldic%B2 %0,%1,0,%S2 |
6970 | andi. %0,%1,%b2 | |
6971 | andis. %0,%1,%u2") | |
266eb58a | 6972 | |
a260abc9 | 6973 | (define_insn "*anddi3_internal2" |
6c873122 | 6974 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") |
9ebbca7d | 6975 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,") |
6c873122 | 6976 | (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) |
266eb58a | 6977 | (const_int 0))) |
9ebbca7d | 6978 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r")) |
6c873122 | 6979 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] |
6ffc8580 | 6980 | "TARGET_POWERPC64" |
266eb58a DE |
6981 | "@ |
6982 | and. %3,%1,%2 | |
6c873122 | 6983 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
6984 | andi. %3,%1,%b2 |
6985 | andis. %3,%1,%u2 | |
9ebbca7d GK |
6986 | # |
6987 | # | |
6988 | # | |
6989 | #" | |
6c873122 | 6990 | [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") |
9ebbca7d GK |
6991 | (set_attr "length" "4,4,4,4,8,8,8,8")]) |
6992 | ||
6993 | (define_split | |
6994 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6995 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6996 | (match_operand:DI 2 "and64_operand" "")) | |
6997 | (const_int 0))) | |
6998 | (clobber (match_scratch:DI 3 "")) | |
6999 | (clobber (match_scratch:CC 4 ""))] | |
7000 | "TARGET_POWERPC64 && reload_completed" | |
7001 | [(parallel [(set (match_dup 3) | |
7002 | (and:DI (match_dup 1) | |
7003 | (match_dup 2))) | |
7004 | (clobber (match_dup 4))]) | |
7005 | (set (match_dup 0) | |
7006 | (compare:CC (match_dup 3) | |
7007 | (const_int 0)))] | |
7008 | "") | |
266eb58a | 7009 | |
a260abc9 | 7010 | (define_insn "*anddi3_internal3" |
6c873122 | 7011 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") |
9ebbca7d | 7012 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") |
6c873122 | 7013 | (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) |
266eb58a | 7014 | (const_int 0))) |
9ebbca7d GK |
7015 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") |
7016 | (and:DI (match_dup 1) (match_dup 2))) | |
6c873122 | 7017 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] |
6ffc8580 | 7018 | "TARGET_POWERPC64" |
266eb58a DE |
7019 | "@ |
7020 | and. %0,%1,%2 | |
6c873122 | 7021 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7022 | andi. %0,%1,%b2 |
7023 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7024 | # |
7025 | # | |
7026 | # | |
7027 | #" | |
6c873122 | 7028 | [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") |
9ebbca7d GK |
7029 | (set_attr "length" "4,4,4,4,8,8,8,8")]) |
7030 | ||
7031 | (define_split | |
7032 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7033 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7034 | (match_operand:DI 2 "and64_operand" "")) | |
7035 | (const_int 0))) | |
7036 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7037 | (and:DI (match_dup 1) (match_dup 2))) | |
7038 | (clobber (match_scratch:CC 4 ""))] | |
7039 | "TARGET_POWERPC64 && reload_completed" | |
7040 | [(parallel [(set (match_dup 0) | |
7041 | (and:DI (match_dup 1) (match_dup 2))) | |
7042 | (clobber (match_dup 4))]) | |
7043 | (set (match_dup 3) | |
7044 | (compare:CC (match_dup 0) | |
7045 | (const_int 0)))] | |
7046 | "") | |
266eb58a | 7047 | |
a260abc9 | 7048 | (define_expand "iordi3" |
266eb58a | 7049 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7050 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7051 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7052 | "TARGET_POWERPC64" |
266eb58a DE |
7053 | " |
7054 | { | |
dfbdccdb | 7055 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7056 | { |
dfbdccdb | 7057 | HOST_WIDE_INT value; |
677a9668 | 7058 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7059 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7060 | |
dfbdccdb GK |
7061 | if (GET_CODE (operands[2]) == CONST_INT) |
7062 | { | |
7063 | value = INTVAL (operands[2]); | |
7064 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7065 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7066 | } | |
e2c953b6 | 7067 | else |
dfbdccdb GK |
7068 | { |
7069 | value = CONST_DOUBLE_LOW (operands[2]); | |
7070 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7071 | immed_double_const (value | |
7072 | & (~ (HOST_WIDE_INT) 0xffff), | |
7073 | 0, DImode))); | |
7074 | } | |
e2c953b6 | 7075 | |
9ebbca7d GK |
7076 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7077 | DONE; | |
7078 | } | |
266eb58a DE |
7079 | }") |
7080 | ||
a260abc9 DE |
7081 | (define_expand "xordi3" |
7082 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7083 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7084 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7085 | "TARGET_POWERPC64" |
7086 | " | |
7087 | { | |
dfbdccdb | 7088 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7089 | { |
dfbdccdb | 7090 | HOST_WIDE_INT value; |
677a9668 | 7091 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7092 | ? operands[0] : gen_reg_rtx (DImode)); |
7093 | ||
dfbdccdb GK |
7094 | if (GET_CODE (operands[2]) == CONST_INT) |
7095 | { | |
7096 | value = INTVAL (operands[2]); | |
7097 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7098 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7099 | } | |
e2c953b6 | 7100 | else |
dfbdccdb GK |
7101 | { |
7102 | value = CONST_DOUBLE_LOW (operands[2]); | |
7103 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7104 | immed_double_const (value | |
7105 | & (~ (HOST_WIDE_INT) 0xffff), | |
7106 | 0, DImode))); | |
7107 | } | |
e2c953b6 | 7108 | |
9ebbca7d GK |
7109 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7110 | DONE; | |
7111 | } | |
a260abc9 DE |
7112 | }") |
7113 | ||
dfbdccdb | 7114 | (define_insn "*booldi3_internal1" |
266eb58a | 7115 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7116 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7117 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7118 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7119 | "TARGET_POWERPC64" |
1fd4e8c1 | 7120 | "@ |
dfbdccdb GK |
7121 | %q3 %0,%1,%2 |
7122 | %q3i %0,%1,%b2 | |
7123 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7124 | |
dfbdccdb | 7125 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7126 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7127 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7128 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7129 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7130 | (const_int 0))) | |
9ebbca7d | 7131 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7132 | "TARGET_POWERPC64" |
9ebbca7d | 7133 | "@ |
dfbdccdb | 7134 | %q4. %3,%1,%2 |
9ebbca7d GK |
7135 | #" |
7136 | [(set_attr "type" "compare") | |
7137 | (set_attr "length" "4,8")]) | |
7138 | ||
7139 | (define_split | |
7140 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
7141 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7142 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7143 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7144 | (const_int 0))) | |
9ebbca7d GK |
7145 | (clobber (match_scratch:DI 3 ""))] |
7146 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7147 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7148 | (set (match_dup 0) |
7149 | (compare:CC (match_dup 3) | |
7150 | (const_int 0)))] | |
7151 | "") | |
1fd4e8c1 | 7152 | |
dfbdccdb | 7153 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7154 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7155 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7156 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7157 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7158 | (const_int 0))) | |
9ebbca7d | 7159 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7160 | (match_dup 4))] |
266eb58a | 7161 | "TARGET_POWERPC64" |
9ebbca7d | 7162 | "@ |
dfbdccdb | 7163 | %q4. %0,%1,%2 |
9ebbca7d GK |
7164 | #" |
7165 | [(set_attr "type" "compare") | |
7166 | (set_attr "length" "4,8")]) | |
7167 | ||
7168 | (define_split | |
dfbdccdb GK |
7169 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7170 | (compare:CC (match_operator:DI 4 "boolean_operator" | |
7171 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7172 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7173 | (const_int 0))) | |
7174 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
7175 | (match_dup 4))] | |
9ebbca7d | 7176 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7177 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7178 | (set (match_dup 3) |
7179 | (compare:CC (match_dup 0) | |
7180 | (const_int 0)))] | |
7181 | "") | |
1fd4e8c1 | 7182 | |
dfbdccdb GK |
7183 | ;; Split an logical operation that we can't do in one insn into two insns, |
7184 | ;; each of which does one 16-bit part. This is used by combine. | |
266eb58a DE |
7185 | |
7186 | (define_split | |
7187 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7188 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7189 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7190 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7191 | "TARGET_POWERPC64" |
dfbdccdb GK |
7192 | [(set (match_dup 0) (match_dup 4)) |
7193 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7194 | " |
7195 | { | |
dfbdccdb GK |
7196 | rtx i3,i4; |
7197 | ||
9ebbca7d GK |
7198 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7199 | { | |
7200 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7201 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7202 | 0, DImode); |
dfbdccdb | 7203 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7204 | } |
7205 | else | |
7206 | { | |
dfbdccdb | 7207 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7208 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7209 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7210 | } |
dfbdccdb GK |
7211 | operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, |
7212 | operands[1], i3); | |
7213 | operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, | |
7214 | operands[0], i4); | |
1fd4e8c1 RK |
7215 | }") |
7216 | ||
dfbdccdb | 7217 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7218 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7219 | (match_operator:DI 3 "boolean_operator" |
7220 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7221 | (match_operand:DI 2 "logical_operand" "r")]))] | |
a473029f | 7222 | "TARGET_POWERPC64" |
1d328b19 | 7223 | "%q3 %0,%2,%1") |
a473029f | 7224 | |
dfbdccdb | 7225 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7226 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7227 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7228 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7229 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7230 | (const_int 0))) | |
9ebbca7d | 7231 | (clobber (match_scratch:DI 3 "=r,r"))] |
a473029f | 7232 | "TARGET_POWERPC64" |
9ebbca7d | 7233 | "@ |
1d328b19 | 7234 | %q4. %3,%2,%1 |
9ebbca7d GK |
7235 | #" |
7236 | [(set_attr "type" "compare") | |
7237 | (set_attr "length" "4,8")]) | |
7238 | ||
7239 | (define_split | |
7240 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
7241 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7242 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7243 | (match_operand:DI 2 "gpc_reg_operand" "r")]) | |
7244 | (const_int 0))) | |
9ebbca7d GK |
7245 | (clobber (match_scratch:DI 3 ""))] |
7246 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7247 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7248 | (set (match_dup 0) |
7249 | (compare:CC (match_dup 3) | |
7250 | (const_int 0)))] | |
7251 | "") | |
a473029f | 7252 | |
dfbdccdb | 7253 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7254 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7255 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7256 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7257 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7258 | (const_int 0))) | |
9ebbca7d | 7259 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7260 | (match_dup 4))] |
a473029f | 7261 | "TARGET_POWERPC64" |
9ebbca7d | 7262 | "@ |
1d328b19 | 7263 | %q4. %0,%2,%1 |
9ebbca7d GK |
7264 | #" |
7265 | [(set_attr "type" "compare") | |
7266 | (set_attr "length" "4,8")]) | |
7267 | ||
7268 | (define_split | |
9ebbca7d | 7269 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7270 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7271 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7272 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7273 | (const_int 0))) | |
9ebbca7d | 7274 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7275 | (match_dup 4))] |
9ebbca7d | 7276 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7277 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7278 | (set (match_dup 3) |
7279 | (compare:CC (match_dup 0) | |
7280 | (const_int 0)))] | |
7281 | "") | |
266eb58a | 7282 | |
dfbdccdb | 7283 | (define_insn "*boolccdi3_internal1" |
a473029f | 7284 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7285 | (match_operator:DI 3 "boolean_operator" |
7286 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7287 | (not:DI (match_operand:DI 2 "logical_operand" "r"))]))] | |
a473029f | 7288 | "TARGET_POWERPC64" |
dfbdccdb | 7289 | "%q3 %0,%1,%2") |
a473029f | 7290 | |
dfbdccdb | 7291 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7292 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7293 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7294 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7295 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7296 | (const_int 0))) | |
9ebbca7d | 7297 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7298 | "TARGET_POWERPC64" |
9ebbca7d | 7299 | "@ |
dfbdccdb | 7300 | %q4. %3,%1,%2 |
9ebbca7d GK |
7301 | #" |
7302 | [(set_attr "type" "compare") | |
7303 | (set_attr "length" "4,8")]) | |
7304 | ||
7305 | (define_split | |
7306 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
7307 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7308 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7309 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]) | |
7310 | (const_int 0))) | |
9ebbca7d GK |
7311 | (clobber (match_scratch:DI 3 ""))] |
7312 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7313 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7314 | (set (match_dup 0) |
7315 | (compare:CC (match_dup 3) | |
7316 | (const_int 0)))] | |
7317 | "") | |
266eb58a | 7318 | |
dfbdccdb | 7319 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7320 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7321 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7322 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7323 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7324 | (const_int 0))) | |
9ebbca7d | 7325 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7326 | (match_dup 4))] |
29ae5b89 | 7327 | "TARGET_POWERPC64" |
9ebbca7d | 7328 | "@ |
dfbdccdb | 7329 | %q4. %0,%1,%2 |
9ebbca7d GK |
7330 | #" |
7331 | [(set_attr "type" "compare") | |
7332 | (set_attr "length" "4,8")]) | |
7333 | ||
7334 | (define_split | |
9ebbca7d | 7335 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7336 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7337 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7338 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7339 | (const_int 0))) | |
9ebbca7d | 7340 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7341 | (match_dup 4))] |
9ebbca7d | 7342 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7343 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7344 | (set (match_dup 3) |
7345 | (compare:CC (match_dup 0) | |
7346 | (const_int 0)))] | |
7347 | "") | |
dfbdccdb | 7348 | \f |
1fd4e8c1 | 7349 | ;; Now define ways of moving data around. |
4697a36c MM |
7350 | |
7351 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7352 | ;; The output of this could be r0, but we make a very strong |
7353 | ;; preference for a base register because it will usually | |
7354 | ;; be needed there. | |
4697a36c | 7355 | (define_insn "elf_high" |
9ebbca7d | 7356 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7357 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7358 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7359 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7360 | |
7361 | (define_insn "elf_low" | |
9ebbca7d GK |
7362 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7363 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7364 | (match_operand 2 "" "")))] |
0ad91047 | 7365 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7366 | "@ |
7367 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7368 | {ai|addic} %0,%1,%K2") |
4697a36c | 7369 | |
ee890fe2 SS |
7370 | ;; Mach-O PIC trickery. |
7371 | (define_insn "macho_high" | |
7372 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
7373 | (high:SI (match_operand 1 "" "")))] | |
7374 | "TARGET_MACHO && ! TARGET_64BIT" | |
7375 | "{liu|lis} %0,ha16(%1)") | |
7376 | ||
7377 | (define_insn "macho_low" | |
7378 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
7379 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
7380 | (match_operand 2 "" "")))] | |
7381 | "TARGET_MACHO && ! TARGET_64BIT" | |
7382 | "@ | |
7383 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
7384 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
7385 | ||
766a866c MM |
7386 | ;; Set up a register with a value from the GOT table |
7387 | ||
7388 | (define_expand "movsi_got" | |
52d3af72 | 7389 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d GK |
7390 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
7391 | (match_dup 2)] 8))] | |
58307bcd | 7392 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
7393 | " |
7394 | { | |
38c1f2d7 MM |
7395 | if (GET_CODE (operands[1]) == CONST) |
7396 | { | |
7397 | rtx offset = const0_rtx; | |
7398 | HOST_WIDE_INT value; | |
7399 | ||
7400 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7401 | value = INTVAL (offset); | |
7402 | if (value != 0) | |
7403 | { | |
677a9668 | 7404 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7405 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7406 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7407 | DONE; | |
7408 | } | |
7409 | } | |
7410 | ||
c4c40373 | 7411 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7412 | }") |
7413 | ||
84f414bc | 7414 | (define_insn "*movsi_got_internal" |
52d3af72 | 7415 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7416 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7417 | (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] | |
c81bebd7 | 7418 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
7419 | "{l|lwz} %0,%a1@got(%2)" |
7420 | [(set_attr "type" "load")]) | |
7421 | ||
b22b9b3e JL |
7422 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7423 | ;; didn't get allocated to a hard register. | |
7424 | (define_split | |
52d3af72 | 7425 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7426 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7427 | (match_operand:SI 2 "memory_operand" "m")] 8))] | |
b22b9b3e JL |
7428 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
7429 | && flag_pic == 1 | |
7430 | && (reload_in_progress || reload_completed)" | |
7431 | [(set (match_dup 0) (match_dup 2)) | |
9ebbca7d | 7432 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))] |
b22b9b3e JL |
7433 | "") |
7434 | ||
1fd4e8c1 RK |
7435 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7436 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7437 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7438 | ;; integers in the TOC. | |
7439 | (define_expand "movsi" | |
7440 | [(set (match_operand:SI 0 "general_operand" "") | |
7441 | (match_operand:SI 1 "any_operand" ""))] | |
7442 | "" | |
fb4d4348 | 7443 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7444 | |
ee890fe2 SS |
7445 | (define_insn "movsi_low" |
7446 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
7447 | (mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "b") | |
7448 | (match_operand 2 "" ""))))] | |
7449 | "TARGET_MACHO && ! TARGET_64BIT" | |
7450 | "{l|lwz} %0,lo16(%2)(%1)" | |
7451 | [(set_attr "type" "load") | |
7452 | (set_attr "length" "4")]) | |
7453 | ||
acad7ed3 | 7454 | (define_insn "*movsi_internal1" |
a260abc9 | 7455 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h") |
9615f239 | 7456 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))] |
19d5775a RK |
7457 | "gpc_reg_operand (operands[0], SImode) |
7458 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7459 | "@ |
deb9225a | 7460 | mr %0,%1 |
b9442c72 | 7461 | {cal|la} %0,%a1 |
ca7f5001 RK |
7462 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7463 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7464 | {lil|li} %0,%1 |
802a0058 | 7465 | {liu|lis} %0,%v1 |
beaec479 | 7466 | # |
aee86b38 | 7467 | {cal|la} %0,%a1 |
1fd4e8c1 | 7468 | mf%1 %0 |
5c23c401 | 7469 | mt%0 %1 |
e76e75bb RK |
7470 | mt%0 %1 |
7471 | cror 0,0,0" | |
a260abc9 DE |
7472 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*") |
7473 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")]) | |
1fd4e8c1 | 7474 | |
77fa0940 RK |
7475 | ;; Split a load of a large constant into the appropriate two-insn |
7476 | ;; sequence. | |
7477 | ||
7478 | (define_split | |
7479 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7480 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7481 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7482 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7483 | [(set (match_dup 0) | |
7484 | (match_dup 2)) | |
7485 | (set (match_dup 0) | |
7486 | (ior:SI (match_dup 0) | |
7487 | (match_dup 3)))] | |
7488 | " | |
7489 | { | |
5f59ecb7 | 7490 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 7491 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
77fa0940 RK |
7492 | }") |
7493 | ||
acad7ed3 | 7494 | (define_insn "*movsi_internal2" |
9ebbca7d GK |
7495 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
7496 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 7497 | (const_int 0))) |
9ebbca7d | 7498 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
0ad91047 | 7499 | "! TARGET_POWERPC64" |
9ebbca7d GK |
7500 | "@ |
7501 | mr. %0,%1 | |
7502 | #" | |
7503 | [(set_attr "type" "compare") | |
7504 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 7505 | \f |
9ebbca7d GK |
7506 | (define_split |
7507 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7508 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7509 | (const_int 0))) | |
7510 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
7511 | "! TARGET_POWERPC64 && reload_completed" | |
7512 | [(set (match_dup 0) (match_dup 1)) | |
7513 | (set (match_dup 2) | |
7514 | (compare:CC (match_dup 0) | |
7515 | (const_int 0)))] | |
7516 | "") | |
7517 | ||
1fd4e8c1 RK |
7518 | (define_expand "movhi" |
7519 | [(set (match_operand:HI 0 "general_operand" "") | |
7520 | (match_operand:HI 1 "any_operand" ""))] | |
7521 | "" | |
fb4d4348 | 7522 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 RK |
7523 | |
7524 | (define_insn "" | |
fb81d7ce RK |
7525 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7526 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7527 | "gpc_reg_operand (operands[0], HImode) |
7528 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7529 | "@ |
deb9225a | 7530 | mr %0,%1 |
1fd4e8c1 RK |
7531 | lhz%U1%X1 %0,%1 |
7532 | sth%U0%X0 %1,%0 | |
19d5775a | 7533 | {lil|li} %0,%w1 |
1fd4e8c1 | 7534 | mf%1 %0 |
e76e75bb | 7535 | mt%0 %1 |
fb81d7ce | 7536 | mt%0 %1 |
e76e75bb | 7537 | cror 0,0,0" |
b7ff3d82 | 7538 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7539 | |
7540 | (define_expand "movqi" | |
7541 | [(set (match_operand:QI 0 "general_operand" "") | |
7542 | (match_operand:QI 1 "any_operand" ""))] | |
7543 | "" | |
fb4d4348 | 7544 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 RK |
7545 | |
7546 | (define_insn "" | |
fb81d7ce RK |
7547 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7548 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7549 | "gpc_reg_operand (operands[0], QImode) |
7550 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7551 | "@ |
deb9225a | 7552 | mr %0,%1 |
1fd4e8c1 RK |
7553 | lbz%U1%X1 %0,%1 |
7554 | stb%U0%X0 %1,%0 | |
19d5775a | 7555 | {lil|li} %0,%1 |
1fd4e8c1 | 7556 | mf%1 %0 |
e76e75bb | 7557 | mt%0 %1 |
fb81d7ce | 7558 | mt%0 %1 |
e76e75bb | 7559 | cror 0,0,0" |
b7ff3d82 | 7560 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7561 | \f |
7562 | ;; Here is how to move condition codes around. When we store CC data in | |
7563 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7564 | ;; This lets us not shift in the most common case of CR0. | |
7565 | (define_expand "movcc" | |
7566 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7567 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7568 | "" | |
7569 | "") | |
7570 | ||
7571 | (define_insn "" | |
7572 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") | |
7573 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
7574 | "register_operand (operands[0], CCmode) | |
7575 | || register_operand (operands[1], CCmode)" | |
7576 | "@ | |
7577 | mcrf %0,%1 | |
7578 | mtcrf 128,%1 | |
ca7f5001 | 7579 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 7580 | mfcr %0 |
ca7f5001 | 7581 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 7582 | mr %0,%1 |
ca7f5001 RK |
7583 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7584 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b7ff3d82 | 7585 | [(set_attr "type" "*,*,*,compare,*,*,load,store") |
b19003d8 | 7586 | (set_attr "length" "*,*,12,*,8,*,*,*")]) |
1fd4e8c1 | 7587 | \f |
e52e05ca MM |
7588 | ;; For floating-point, we normally deal with the floating-point registers |
7589 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7590 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7591 | ;; value is a simple constant or already in memory, we deal with this by | |
7592 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7593 | (define_expand "movsf" |
7594 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7595 | (match_operand:SF 1 "any_operand" ""))] | |
7596 | "" | |
fb4d4348 | 7597 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7598 | |
1fd4e8c1 | 7599 | (define_split |
cd2b37d9 | 7600 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7601 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7602 | "reload_completed |
5ae4759c MM |
7603 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7604 | || (GET_CODE (operands[0]) == SUBREG | |
7605 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7606 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7607 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7608 | " |
7609 | { | |
7610 | long l; | |
7611 | REAL_VALUE_TYPE rv; | |
7612 | ||
7613 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7614 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7615 | |
f99f88e0 DE |
7616 | if (! TARGET_POWERPC64) |
7617 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7618 | else | |
7619 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7620 | |
38886f37 | 7621 | operands[3] = GEN_INT (trunc_int_for_mode (l, SImode)); |
a260abc9 DE |
7622 | }") |
7623 | ||
c4c40373 | 7624 | (define_insn "*movsf_hardfloat" |
f99f88e0 DE |
7625 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") |
7626 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] | |
d14a6d05 MM |
7627 | "(gpc_reg_operand (operands[0], SFmode) |
7628 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" | |
1fd4e8c1 | 7629 | "@ |
f99f88e0 DE |
7630 | mr %0,%1 |
7631 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7632 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7633 | fmr %0,%1 |
7634 | lfs%U1%X1 %0,%1 | |
c4c40373 MM |
7635 | stfs%U0%X0 %1,%0 |
7636 | # | |
7637 | #" | |
f99f88e0 DE |
7638 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") |
7639 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7640 | |
c4c40373 MM |
7641 | (define_insn "*movsf_softfloat" |
7642 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") | |
9615f239 | 7643 | (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))] |
d14a6d05 MM |
7644 | "(gpc_reg_operand (operands[0], SFmode) |
7645 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" | |
7646 | "@ | |
7647 | mr %0,%1 | |
7648 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7649 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7650 | {lil|li} %0,%1 | |
802a0058 | 7651 | {liu|lis} %0,%v1 |
aee86b38 | 7652 | {cal|la} %0,%a1 |
c4c40373 MM |
7653 | # |
7654 | #" | |
7655 | [(set_attr "type" "*,load,store,*,*,*,*,*") | |
7656 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7657 | |
1fd4e8c1 RK |
7658 | \f |
7659 | (define_expand "movdf" | |
7660 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7661 | (match_operand:DF 1 "any_operand" ""))] | |
7662 | "" | |
fb4d4348 | 7663 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7664 | |
7665 | (define_split | |
cd2b37d9 | 7666 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7667 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7668 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7669 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7670 | || (GET_CODE (operands[0]) == SUBREG | |
7671 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7672 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7673 | [(set (match_dup 2) (match_dup 4)) |
7674 | (set (match_dup 3) (match_dup 1))] | |
7675 | " | |
7676 | { | |
5ae4759c | 7677 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7678 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7679 | ||
5ae4759c MM |
7680 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7681 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7682 | #if HOST_BITS_PER_WIDE_INT == 32 |
7683 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7684 | #else | |
7685 | operands[4] = GEN_INT (value >> 32); | |
7686 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
7687 | #endif | |
c4c40373 MM |
7688 | }") |
7689 | ||
c4c40373 MM |
7690 | (define_split |
7691 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7692 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7693 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7694 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7695 | || (GET_CODE (operands[0]) == SUBREG | |
7696 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7697 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7698 | [(set (match_dup 2) (match_dup 4)) |
7699 | (set (match_dup 3) (match_dup 5))] | |
7700 | " | |
7701 | { | |
5ae4759c | 7702 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7703 | long l[2]; |
7704 | REAL_VALUE_TYPE rv; | |
7705 | ||
7706 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7707 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7708 | ||
5ae4759c MM |
7709 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7710 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
38886f37 AO |
7711 | operands[4] = GEN_INT (trunc_int_for_mode (l[endian], SImode)); |
7712 | operands[5] = GEN_INT (trunc_int_for_mode (l[1 - endian], SImode)); | |
c4c40373 MM |
7713 | }") |
7714 | ||
efc08378 DE |
7715 | (define_split |
7716 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7717 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7718 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7719 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7720 | || (GET_CODE (operands[0]) == SUBREG | |
7721 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7722 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7723 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7724 | " |
a260abc9 DE |
7725 | { |
7726 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7727 | long l[2]; | |
7728 | REAL_VALUE_TYPE rv; | |
7729 | ||
7730 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7731 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7732 | ||
7733 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7734 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
7735 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); | |
7736 | }") | |
efc08378 | 7737 | |
4eae5fe1 | 7738 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7739 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7740 | ;; a non-offsettable memref, but also it is less efficient than loading |
7741 | ;; the constant into an FP register, since it will probably be used there. | |
7742 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7743 | ;; of handling these non-offsettable values. | |
c4c40373 | 7744 | (define_insn "*movdf_hardfloat32" |
000034eb DE |
7745 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
7746 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 7747 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
7748 | && (gpc_reg_operand (operands[0], DFmode) |
7749 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7750 | "* |
7751 | { | |
7752 | switch (which_alternative) | |
7753 | { | |
a260abc9 | 7754 | default: |
a6c2a102 | 7755 | abort (); |
e7113111 RK |
7756 | case 0: |
7757 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
7758 | the first register operand 0 is the same as the second register |
7759 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 7760 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 7761 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 7762 | else |
deb9225a | 7763 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 7764 | case 1: |
2b97222d DE |
7765 | if (offsettable_memref_p (operands[1]) |
7766 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
7767 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
7768 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
7769 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
7770 | { |
7771 | /* If the low-address word is used in the address, we must load | |
7772 | it last. Otherwise, load it first. Note that we cannot have | |
7773 | auto-increment in that case since the address register is | |
7774 | known to be dead. */ | |
7775 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7776 | operands[1], 0)) | |
7777 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
7778 | else | |
7779 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7780 | } | |
e7113111 | 7781 | else |
000034eb DE |
7782 | { |
7783 | rtx addreg; | |
7784 | ||
000034eb DE |
7785 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
7786 | if (refers_to_regno_p (REGNO (operands[0]), | |
7787 | REGNO (operands[0]) + 1, | |
7788 | operands[1], 0)) | |
7789 | { | |
7790 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 7791 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 7792 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 7793 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
7794 | } |
7795 | else | |
7796 | { | |
2b97222d | 7797 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 7798 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7799 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
7800 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7801 | return \"\"; | |
7802 | } | |
7803 | } | |
e7113111 | 7804 | case 2: |
2b97222d DE |
7805 | if (offsettable_memref_p (operands[0]) |
7806 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
7807 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
7808 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
7809 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
7810 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
7811 | else | |
7812 | { | |
7813 | rtx addreg; | |
7814 | ||
000034eb | 7815 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 7816 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 7817 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7818 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
7819 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7820 | return \"\"; | |
7821 | } | |
e7113111 | 7822 | case 3: |
e7113111 | 7823 | case 4: |
e7113111 | 7824 | case 5: |
c4c40373 | 7825 | return \"#\"; |
e7113111 | 7826 | case 6: |
c4c40373 MM |
7827 | return \"fmr %0,%1\"; |
7828 | case 7: | |
7829 | return \"lfd%U1%X1 %0,%1\"; | |
7830 | case 8: | |
e7113111 RK |
7831 | return \"stfd%U0%X0 %1,%0\"; |
7832 | } | |
7833 | }" | |
c4c40373 | 7834 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
2f76d42c | 7835 | (set_attr "length" "8,16,16,8,12,16,*,*,*")]) |
51b8fc2c | 7836 | |
c4c40373 | 7837 | (define_insn "*movdf_softfloat32" |
1427100a DE |
7838 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7839 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 7840 | "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
7841 | && (gpc_reg_operand (operands[0], DFmode) |
7842 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7843 | "* |
7844 | { | |
7845 | switch (which_alternative) | |
7846 | { | |
a260abc9 | 7847 | default: |
a6c2a102 | 7848 | abort (); |
dc4f83ca MM |
7849 | case 0: |
7850 | /* We normally copy the low-numbered register first. However, if | |
7851 | the first register operand 0 is the same as the second register of | |
7852 | operand 1, we must copy in the opposite order. */ | |
7853 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
7854 | return \"mr %L0,%L1\;mr %0,%1\"; | |
7855 | else | |
7856 | return \"mr %0,%1\;mr %L0,%L1\"; | |
7857 | case 1: | |
3cb999d8 DE |
7858 | /* If the low-address word is used in the address, we must load |
7859 | it last. Otherwise, load it first. Note that we cannot have | |
7860 | auto-increment in that case since the address register is | |
7861 | known to be dead. */ | |
dc4f83ca | 7862 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 7863 | operands[1], 0)) |
dc4f83ca MM |
7864 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
7865 | else | |
7866 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7867 | case 2: | |
7868 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
7869 | case 3: | |
c4c40373 MM |
7870 | case 4: |
7871 | case 5: | |
dc4f83ca MM |
7872 | return \"#\"; |
7873 | } | |
7874 | }" | |
c4c40373 MM |
7875 | [(set_attr "type" "*,load,store,*,*,*") |
7876 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 7877 | |
c4c40373 | 7878 | (define_insn "*movdf_hardfloat64" |
1427100a DE |
7879 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
7880 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 7881 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
7882 | && (gpc_reg_operand (operands[0], DFmode) |
7883 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 7884 | "@ |
3d5570cb RK |
7885 | mr %0,%1 |
7886 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 7887 | std%U0%X0 %1,%0 |
3d5570cb | 7888 | # |
c4c40373 MM |
7889 | # |
7890 | # | |
3d5570cb | 7891 | fmr %0,%1 |
f63184ac | 7892 | lfd%U1%X1 %0,%1 |
3d5570cb | 7893 | stfd%U0%X0 %1,%0" |
c4c40373 MM |
7894 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
7895 | (set_attr "length" "4,4,4,8,12,16,4,4,4")]) | |
dc4f83ca | 7896 | |
c4c40373 | 7897 | (define_insn "*movdf_softfloat64" |
1427100a DE |
7898 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7899 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 7900 | "TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
7901 | && (gpc_reg_operand (operands[0], DFmode) |
7902 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7903 | "@ |
7904 | mr %0,%1 | |
7905 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 7906 | std%U0%X0 %1,%0 |
c4c40373 MM |
7907 | # |
7908 | # | |
dc4f83ca | 7909 | #" |
c4c40373 MM |
7910 | [(set_attr "type" "*,load,store,*,*,*") |
7911 | (set_attr "length" "*,*,*,8,12,16")]) | |
1fd4e8c1 RK |
7912 | \f |
7913 | ;; Next come the multi-word integer load and store and the load and store | |
7914 | ;; multiple insns. | |
7915 | (define_expand "movdi" | |
7916 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 7917 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 7918 | "" |
fb4d4348 | 7919 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 7920 | |
acad7ed3 | 7921 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
7922 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
7923 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 7924 | "! TARGET_POWERPC64 |
4e74d8ec MM |
7925 | && (gpc_reg_operand (operands[0], DImode) |
7926 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
7927 | "* |
7928 | { | |
7929 | switch (which_alternative) | |
7930 | { | |
a260abc9 | 7931 | default: |
a6c2a102 | 7932 | abort (); |
1fd4e8c1 RK |
7933 | case 0: |
7934 | /* We normally copy the low-numbered register first. However, if | |
7935 | the first register operand 0 is the same as the second register of | |
7936 | operand 1, we must copy in the opposite order. */ | |
7937 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 7938 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 7939 | else |
deb9225a | 7940 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
7941 | case 1: |
7942 | /* If the low-address word is used in the address, we must load it | |
7943 | last. Otherwise, load it first. Note that we cannot have | |
7944 | auto-increment in that case since the address register is known to be | |
7945 | dead. */ | |
7946 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 7947 | operands[1], 0)) |
ca7f5001 | 7948 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 7949 | else |
ca7f5001 | 7950 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 7951 | case 2: |
ca7f5001 | 7952 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
7953 | case 3: |
7954 | return \"fmr %0,%1\"; | |
7955 | case 4: | |
7956 | return \"lfd%U1%X1 %0,%1\"; | |
7957 | case 5: | |
7958 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
7959 | case 6: |
7960 | case 7: | |
7961 | case 8: | |
7962 | case 9: | |
7963 | case 10: | |
7964 | return \"#\"; | |
1fd4e8c1 RK |
7965 | } |
7966 | }" | |
4e74d8ec MM |
7967 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
7968 | (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) | |
7969 | ||
7970 | (define_split | |
7971 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7972 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 7973 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
7974 | [(set (match_dup 2) (match_dup 4)) |
7975 | (set (match_dup 3) (match_dup 1))] | |
7976 | " | |
7977 | { | |
5f59ecb7 | 7978 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
7979 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
7980 | DImode); | |
7981 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
7982 | DImode); | |
75d39459 | 7983 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 7984 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 7985 | #else |
5f59ecb7 DE |
7986 | operands[4] = GEN_INT (value >> 32); |
7987 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
75d39459 | 7988 | #endif |
4e74d8ec MM |
7989 | }") |
7990 | ||
4e74d8ec MM |
7991 | (define_split |
7992 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7993 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 7994 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
7995 | [(set (match_dup 2) (match_dup 4)) |
7996 | (set (match_dup 3) (match_dup 5))] | |
7997 | " | |
7998 | { | |
bdaa0181 GK |
7999 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8000 | DImode); | |
8001 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8002 | DImode); | |
f6968f59 MM |
8003 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
8004 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
8005 | }") |
8006 | ||
acad7ed3 | 8007 | (define_insn "*movdi_internal64" |
e6ca2c17 | 8008 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") |
9615f239 | 8009 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8010 | "TARGET_POWERPC64 |
4e74d8ec MM |
8011 | && (gpc_reg_operand (operands[0], DImode) |
8012 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8013 | "@ |
3d5570cb RK |
8014 | mr %0,%1 |
8015 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8016 | std%U0%X0 %1,%0 |
3d5570cb | 8017 | li %0,%1 |
802a0058 | 8018 | lis %0,%v1 |
e6ca2c17 | 8019 | # |
aee86b38 | 8020 | {cal|la} %0,%a1 |
3d5570cb RK |
8021 | fmr %0,%1 |
8022 | lfd%U1%X1 %0,%1 | |
8023 | stfd%U0%X0 %1,%0 | |
8024 | mf%1 %0 | |
08075ead DE |
8025 | mt%0 %1 |
8026 | cror 0,0,0" | |
b7ff3d82 | 8027 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
8028 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8029 | ||
5f59ecb7 | 8030 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8031 | (define_insn "" |
8032 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8033 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8034 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8035 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8036 | && num_insns_constant (operands[1], DImode) == 1" |
8037 | "* | |
8038 | { | |
8039 | return ((unsigned HOST_WIDE_INT) | |
8040 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8041 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8042 | }") | |
8043 | ||
5f59ecb7 | 8044 | ;; sign-extended 32-bit value |
a260abc9 DE |
8045 | (define_split |
8046 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8047 | (match_operand:DI 1 "const_int_operand" ""))] | |
8048 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
8049 | && num_insns_constant (operands[1], DImode) > 1" | |
8050 | [(set (match_dup 0) | |
8051 | (match_dup 2)) | |
8052 | (set (match_dup 0) | |
8053 | (ior:DI (match_dup 0) | |
8054 | (match_dup 3)))] | |
8055 | " | |
8056 | { | |
38886f37 | 8057 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
a260abc9 DE |
8058 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
8059 | }") | |
e6ca2c17 DE |
8060 | |
8061 | (define_split | |
8062 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8063 | (match_operand:DI 1 "const_double_operand" ""))] | |
a260abc9 DE |
8064 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8065 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
8066 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
8067 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) | |
5f59ecb7 | 8068 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 |
a260abc9 | 8069 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))" |
e6ca2c17 DE |
8070 | [(set (match_dup 0) |
8071 | (match_dup 2)) | |
8072 | (set (match_dup 0) | |
8073 | (ior:DI (match_dup 0) | |
a260abc9 DE |
8074 | (match_dup 3)))] |
8075 | " | |
8076 | { | |
38886f37 | 8077 | operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
a260abc9 DE |
8078 | operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff); |
8079 | }") | |
8080 | ||
5f59ecb7 DE |
8081 | (define_split |
8082 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8083 | (match_operand:DI 1 "const_int_operand" ""))] | |
8084 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
8085 | && GET_CODE (operands[1]) == CONST_INT | |
8086 | && (((INTVAL (operands[1]) >> 32) == 0 | |
8087 | && (INTVAL (operands[1]) & 0x80000000) == 0) | |
8088 | || ((INTVAL (operands[1]) >> 32) == -1 | |
8089 | && (INTVAL (operands[1]) & 0x80000000) != 0)) | |
8090 | && num_insns_constant (operands[1], DImode) > 1" | |
8091 | [(set (match_dup 0) | |
8092 | (match_dup 2)) | |
8093 | (set (match_dup 0) | |
8094 | (ior:DI (match_dup 0) | |
8095 | (match_dup 3)))] | |
8096 | " | |
8097 | { | |
38886f37 | 8098 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
5f59ecb7 DE |
8099 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
8100 | }") | |
8101 | ||
8102 | ;; zero-extended 32-bit value | |
a260abc9 DE |
8103 | (define_split |
8104 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8105 | (match_operand:DI 1 "const_double_operand" ""))] | |
8106 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
8107 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
8108 | && CONST_DOUBLE_HIGH (operands[1]) == 0 | |
8109 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0" | |
8110 | [(set (match_dup 0) | |
8111 | (match_dup 2)) | |
8112 | (set (match_dup 0) | |
e53ca51f | 8113 | (zero_extend:DI (match_dup 3)))] |
a260abc9 | 8114 | " |
e53ca51f GK |
8115 | { |
8116 | operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8117 | operands[3] = gen_lowpart_common (SImode, operands[0]); | |
8118 | }") | |
a260abc9 | 8119 | |
5f59ecb7 DE |
8120 | (define_split |
8121 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8122 | (match_operand:DI 1 "const_int_operand" ""))] | |
8123 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
8124 | && GET_CODE (operands[1]) == CONST_INT | |
8125 | && INTVAL (operands[1]) >> 32 == 0 | |
8126 | && (INTVAL (operands[1]) & 0x80000000) != 0 | |
8127 | && num_insns_constant (operands[1], DImode) > 1" | |
8128 | [(set (match_dup 0) | |
8129 | (match_dup 2)) | |
8130 | (set (match_dup 0) | |
e53ca51f | 8131 | (zero_extend:DI (match_dup 3)))] |
5f59ecb7 | 8132 | " |
9ebbca7d GK |
8133 | { |
8134 | #if HOST_BITS_PER_WIDE_INT != 32 | |
e53ca51f | 8135 | operands[2] = GEN_INT ((INTVAL (operands[1]) << 32) >> 32); |
9ebbca7d | 8136 | #endif |
e53ca51f | 8137 | operands[3] = gen_lowpart_common (SImode, operands[0]); |
9ebbca7d | 8138 | }") |
5f59ecb7 DE |
8139 | |
8140 | ;; 32-bit value in upper half of doubleword | |
a260abc9 DE |
8141 | (define_split |
8142 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8143 | (match_operand:DI 1 "const_double_operand" ""))] | |
8144 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
8145 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
8146 | && CONST_DOUBLE_LOW (operands[1]) == 0" | |
8147 | [(set (match_dup 0) | |
8148 | (match_dup 2)) | |
e6ca2c17 DE |
8149 | (set (match_dup 0) |
8150 | (ashift:DI (match_dup 0) | |
a260abc9 DE |
8151 | (const_int 32)))] |
8152 | " | |
8153 | { operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }") | |
8154 | ||
5f59ecb7 DE |
8155 | (define_split |
8156 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8157 | (match_operand:DI 1 "const_int_operand" ""))] | |
8158 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
8159 | && GET_CODE (operands[1]) == CONST_INT | |
9ebbca7d | 8160 | && (INTVAL (operands[1]) & 0xffffffff) == 0" |
5f59ecb7 DE |
8161 | [(set (match_dup 0) |
8162 | (match_dup 2)) | |
8163 | (set (match_dup 0) | |
8164 | (ashift:DI (match_dup 0) | |
8165 | (const_int 32)))] | |
8166 | " | |
9ebbca7d GK |
8167 | { |
8168 | #if HOST_BITS_PER_WIDE_INT != 32 | |
8169 | operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); | |
8170 | #endif | |
8171 | }") | |
5f59ecb7 | 8172 | |
a260abc9 DE |
8173 | ;; Generate all one-bits and clear left or right. |
8174 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8175 | (define_split | |
8176 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8177 | (match_operand:DI 1 "mask64_operand" ""))] | |
8178 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8179 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8180 | (set (match_dup 0) |
a260abc9 DE |
8181 | (and:DI (rotate:DI (match_dup 0) |
8182 | (const_int 0)) | |
8183 | (match_dup 1)))] | |
8184 | "") | |
8185 | ||
8186 | ;; Split a load of a large constant into the appropriate five-instruction | |
8187 | ;; sequence. Handle anything in a constant number of insns. | |
8188 | ;; When non-easy constants can go in the TOC, this should use | |
8189 | ;; easy_fp_constant predicate. | |
8190 | (define_split | |
8191 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8192 | (match_operand:DI 1 "const_double_operand" ""))] | |
5f59ecb7 DE |
8193 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8194 | && num_insns_constant (operands[1], DImode) > 1" | |
a260abc9 DE |
8195 | [(set (match_dup 0) |
8196 | (match_dup 2)) | |
8197 | (set (match_dup 0) | |
8198 | (ashift:DI (match_dup 0) | |
8199 | (const_int 32))) | |
e6ca2c17 DE |
8200 | (set (match_dup 0) |
8201 | (ior:DI (match_dup 0) | |
a260abc9 | 8202 | (match_dup 3)))] |
e6ca2c17 DE |
8203 | " |
8204 | { | |
e6ca2c17 DE |
8205 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
8206 | { | |
5f59ecb7 | 8207 | operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
9ebbca7d GK |
8208 | operands[3] = immed_double_const (CONST_DOUBLE_LOW (operands[1]), |
8209 | 0, DImode); | |
e6ca2c17 | 8210 | } |
e8d791dd | 8211 | else |
e6ca2c17 | 8212 | { |
5f59ecb7 DE |
8213 | HOST_WIDE_INT value = INTVAL (operands[1]); |
8214 | operands[2] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
9ebbca7d | 8215 | operands[3] = immed_double_const (value, 0, DImode); |
e6ca2c17 | 8216 | } |
5f59ecb7 | 8217 | }") |
e6ca2c17 | 8218 | |
5f59ecb7 DE |
8219 | (define_split |
8220 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8221 | (match_operand:DI 1 "const_int_operand" ""))] | |
8222 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
8223 | && num_insns_constant (operands[1], DImode) > 1" | |
8224 | [(set (match_dup 0) | |
8225 | (match_dup 2)) | |
8226 | (set (match_dup 0) | |
8227 | (ashift:DI (match_dup 0) | |
8228 | (const_int 32))) | |
8229 | (set (match_dup 0) | |
8230 | (ior:DI (match_dup 0) | |
8231 | (match_dup 3)))] | |
8232 | " | |
8233 | { | |
9ebbca7d | 8234 | #if HOST_BITS_PER_WIDE_INT != 32 |
5f59ecb7 DE |
8235 | HOST_WIDE_INT value = INTVAL (operands[1]); |
8236 | operands[2] = GEN_INT (value >> 32); | |
8237 | operands[3] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
9ebbca7d | 8238 | #endif |
e6ca2c17 | 8239 | }") |
08075ead | 8240 | |
acad7ed3 | 8241 | (define_insn "*movdi_internal2" |
9ebbca7d GK |
8242 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
8243 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
08075ead | 8244 | (const_int 0))) |
9ebbca7d | 8245 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
08075ead | 8246 | "TARGET_POWERPC64" |
9ebbca7d GK |
8247 | "@ |
8248 | mr. %0,%1 | |
8249 | #" | |
8250 | [(set_attr "type" "compare") | |
8251 | (set_attr "length" "4,8")]) | |
acad7ed3 | 8252 | |
9ebbca7d GK |
8253 | (define_split |
8254 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8255 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8256 | (const_int 0))) | |
8257 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8258 | "TARGET_POWERPC64 && reload_completed" | |
8259 | [(set (match_dup 0) (match_dup 1)) | |
8260 | (set (match_dup 2) | |
8261 | (compare:CC (match_dup 0) | |
8262 | (const_int 0)))] | |
8263 | "") | |
acad7ed3 | 8264 | \f |
1fd4e8c1 RK |
8265 | ;; TImode is similar, except that we usually want to compute the address into |
8266 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8267 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8268 | (define_expand "movti" |
8269 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8270 | (match_operand:TI 1 "general_operand" "")) | |
8271 | (clobber (scratch:SI))])] | |
7e69e155 | 8272 | "TARGET_STRING || TARGET_POWERPC64" |
fb4d4348 | 8273 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8274 | |
8275 | ;; We say that MQ is clobbered in the last alternative because the first | |
8276 | ;; alternative would never get used otherwise since it would need a reload | |
8277 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8278 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8279 | ;; giving the SCRATCH mq. | |
a260abc9 | 8280 | (define_insn "*movti_power" |
e1469d0d | 8281 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8282 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8283 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 8284 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8285 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8286 | "* |
8287 | { | |
8288 | switch (which_alternative) | |
8289 | { | |
dc4f83ca MM |
8290 | default: |
8291 | abort (); | |
8292 | ||
1fd4e8c1 | 8293 | case 0: |
ca7f5001 | 8294 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
8295 | |
8296 | case 1: | |
ca7f5001 | 8297 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
8298 | |
8299 | case 2: | |
8300 | /* Normally copy registers with lowest numbered register copied first. | |
8301 | But copy in the other order if the first register of the output | |
8302 | is the second, third, or fourth register in the input. */ | |
8303 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8304 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 8305 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8306 | else |
deb9225a | 8307 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
8308 | case 3: |
8309 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8310 | fall through to generating four loads. */ | |
8311 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8312 | return \"{lsi|lswi} %0,%P1,16\"; |
1fd4e8c1 RK |
8313 | /* ... fall through ... */ |
8314 | case 4: | |
8315 | /* If the address register is the same as the register for the lowest- | |
8316 | addressed word, load it last. Similarly for the next two words. | |
8317 | Otherwise load lowest address to highest. */ | |
8318 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8319 | operands[1], 0)) | |
ca7f5001 | 8320 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
8321 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
8322 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 8323 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
8324 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
8325 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 8326 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 8327 | else |
ca7f5001 | 8328 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
8329 | } |
8330 | }" | |
b7ff3d82 | 8331 | [(set_attr "type" "store,store,*,load,load") |
b19003d8 | 8332 | (set_attr "length" "*,16,16,*,16")]) |
51b8fc2c | 8333 | |
a260abc9 | 8334 | (define_insn "*movti_string" |
dc4f83ca MM |
8335 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") |
8336 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) | |
8337 | (clobber (match_scratch:SI 2 "=X,X,X"))] | |
0ad91047 | 8338 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8339 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8340 | "* | |
8341 | { | |
8342 | switch (which_alternative) | |
8343 | { | |
8344 | default: | |
8345 | abort (); | |
8346 | ||
8347 | case 0: | |
8348 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; | |
8349 | ||
8350 | case 1: | |
8351 | /* Normally copy registers with lowest numbered register copied first. | |
8352 | But copy in the other order if the first register of the output | |
8353 | is the second, third, or fourth register in the input. */ | |
8354 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8355 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
8356 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
8357 | else | |
8358 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
8359 | case 2: | |
8360 | /* If the address register is the same as the register for the lowest- | |
8361 | addressed word, load it last. Similarly for the next two words. | |
8362 | Otherwise load lowest address to highest. */ | |
8363 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8364 | operands[1], 0)) | |
8365 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
8366 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
8367 | REGNO (operands[0]) + 2, operands[1], 0)) | |
8368 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
8369 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
8370 | REGNO (operands[0]) + 3, operands[1], 0)) | |
8371 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
8372 | else | |
8373 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
8374 | } | |
8375 | }" | |
b7ff3d82 | 8376 | [(set_attr "type" "store,*,load") |
dc4f83ca MM |
8377 | (set_attr "length" "16,16,16")]) |
8378 | ||
a260abc9 | 8379 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
8380 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
8381 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
8382 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
8383 | || gpc_reg_operand (operands[1], TImode))" | |
8384 | "* | |
8385 | { | |
8386 | switch (which_alternative) | |
8387 | { | |
a260abc9 | 8388 | default: |
a6c2a102 | 8389 | abort (); |
51b8fc2c RK |
8390 | case 0: |
8391 | /* We normally copy the low-numbered register first. However, if | |
8392 | the first register operand 0 is the same as the second register of | |
8393 | operand 1, we must copy in the opposite order. */ | |
8394 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8395 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8396 | else | |
8397 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8398 | case 1: | |
8399 | /* If the low-address word is used in the address, we must load it | |
8400 | last. Otherwise, load it first. Note that we cannot have | |
8401 | auto-increment in that case since the address register is known to be | |
8402 | dead. */ | |
8403 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8404 | operands[1], 0)) |
51b8fc2c RK |
8405 | return \"ld %L0,%L1\;ld %0,%1\"; |
8406 | else | |
8407 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
8408 | case 2: | |
8409 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
8410 | } | |
8411 | }" | |
b7ff3d82 | 8412 | [(set_attr "type" "*,load,store") |
51b8fc2c | 8413 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
8414 | \f |
8415 | (define_expand "load_multiple" | |
2f622005 RK |
8416 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8417 | (match_operand:SI 1 "" "")) | |
8418 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 8419 | "TARGET_STRING" |
1fd4e8c1 RK |
8420 | " |
8421 | { | |
8422 | int regno; | |
8423 | int count; | |
8424 | rtx from; | |
8425 | int i; | |
8426 | ||
8427 | /* Support only loading a constant number of fixed-point registers from | |
8428 | memory and only bother with this if more than two; the machine | |
8429 | doesn't support more than eight. */ | |
8430 | if (GET_CODE (operands[2]) != CONST_INT | |
8431 | || INTVAL (operands[2]) <= 2 | |
8432 | || INTVAL (operands[2]) > 8 | |
8433 | || GET_CODE (operands[1]) != MEM | |
8434 | || GET_CODE (operands[0]) != REG | |
8435 | || REGNO (operands[0]) >= 32) | |
8436 | FAIL; | |
8437 | ||
8438 | count = INTVAL (operands[2]); | |
8439 | regno = REGNO (operands[0]); | |
8440 | ||
39403d82 | 8441 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
1fd4e8c1 RK |
8442 | from = force_reg (SImode, XEXP (operands[1], 0)); |
8443 | ||
8444 | for (i = 0; i < count; i++) | |
8445 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8446 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
c5c76735 JL |
8447 | change_address (operands[1], SImode, |
8448 | plus_constant (from, i * 4))); | |
1fd4e8c1 RK |
8449 | }") |
8450 | ||
8451 | (define_insn "" | |
8452 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 8453 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
52d3af72 | 8454 | (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] |
7e69e155 | 8455 | "TARGET_STRING" |
1fd4e8c1 RK |
8456 | "* |
8457 | { | |
8458 | /* We have to handle the case where the pseudo used to contain the address | |
e82ee4cc RK |
8459 | is assigned to one of the output registers. */ |
8460 | int i, j; | |
8461 | int words = XVECLEN (operands[0], 0); | |
8462 | rtx xop[10]; | |
8463 | ||
8464 | if (XVECLEN (operands[0], 0) == 1) | |
8465 | return \"{l|lwz} %1,0(%2)\"; | |
1fd4e8c1 | 8466 | |
e82ee4cc | 8467 | for (i = 0; i < words; i++) |
1fd4e8c1 RK |
8468 | if (refers_to_regno_p (REGNO (operands[1]) + i, |
8469 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
8470 | { | |
e82ee4cc RK |
8471 | if (i == words-1) |
8472 | { | |
8473 | xop[0] = operands[1]; | |
8474 | xop[1] = operands[2]; | |
8475 | xop[2] = GEN_INT (4 * (words-1)); | |
d89ddcfd | 8476 | output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); |
e82ee4cc RK |
8477 | return \"\"; |
8478 | } | |
8479 | else if (i == 0) | |
8480 | { | |
8481 | xop[0] = operands[1]; | |
39403d82 | 8482 | xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
e82ee4cc RK |
8483 | xop[2] = GEN_INT (4 * (words-1)); |
8484 | output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); | |
8485 | return \"\"; | |
8486 | } | |
8487 | else | |
8488 | { | |
8489 | for (j = 0; j < words; j++) | |
8490 | if (j != i) | |
8491 | { | |
39403d82 | 8492 | xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); |
e82ee4cc RK |
8493 | xop[1] = operands[2]; |
8494 | xop[2] = GEN_INT (j * 4); | |
8495 | output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); | |
8496 | } | |
8497 | xop[0] = operands[2]; | |
8498 | xop[1] = GEN_INT (i * 4); | |
8499 | output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); | |
8500 | return \"\"; | |
8501 | } | |
1fd4e8c1 RK |
8502 | } |
8503 | ||
e82ee4cc | 8504 | return \"{lsi|lswi} %1,%2,%N0\"; |
1fd4e8c1 | 8505 | }" |
b19003d8 | 8506 | [(set_attr "type" "load") |
e82ee4cc | 8507 | (set_attr "length" "32")]) |
b19003d8 | 8508 | |
b7ff3d82 | 8509 | \f |
1fd4e8c1 | 8510 | (define_expand "store_multiple" |
2f622005 RK |
8511 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8512 | (match_operand:SI 1 "" "")) | |
8513 | (clobber (scratch:SI)) | |
8514 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 8515 | "TARGET_STRING" |
1fd4e8c1 RK |
8516 | " |
8517 | { | |
8518 | int regno; | |
8519 | int count; | |
8520 | rtx to; | |
8521 | int i; | |
8522 | ||
8523 | /* Support only storing a constant number of fixed-point registers to | |
8524 | memory and only bother with this if more than two; the machine | |
8525 | doesn't support more than eight. */ | |
8526 | if (GET_CODE (operands[2]) != CONST_INT | |
8527 | || INTVAL (operands[2]) <= 2 | |
8528 | || INTVAL (operands[2]) > 8 | |
8529 | || GET_CODE (operands[0]) != MEM | |
8530 | || GET_CODE (operands[1]) != REG | |
8531 | || REGNO (operands[1]) >= 32) | |
8532 | FAIL; | |
8533 | ||
8534 | count = INTVAL (operands[2]); | |
8535 | regno = REGNO (operands[1]); | |
8536 | ||
39403d82 | 8537 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 RK |
8538 | to = force_reg (SImode, XEXP (operands[0], 0)); |
8539 | ||
8540 | XVECEXP (operands[3], 0, 0) | |
39403d82 | 8541 | = gen_rtx_SET (VOIDmode, change_address (operands[0], SImode, to), |
c5c76735 | 8542 | operands[1]); |
39403d82 | 8543 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8544 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8545 | |
8546 | for (i = 1; i < count; i++) | |
8547 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8548 | = gen_rtx_SET (VOIDmode, |
c5c76735 JL |
8549 | change_address (operands[0], SImode, |
8550 | plus_constant (to, i * 4)), | |
8551 | gen_rtx_REG (SImode, regno + i)); | |
1fd4e8c1 RK |
8552 | }") |
8553 | ||
8554 | (define_insn "" | |
8555 | [(match_parallel 0 "store_multiple_operation" | |
8556 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8557 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8558 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8559 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8560 | "{stsi|stswi} %2,%P1,%O0" |
8561 | [(set_attr "type" "store")]) | |
d14a6d05 MM |
8562 | |
8563 | (define_insn "" | |
8564 | [(match_parallel 0 "store_multiple_operation" | |
52d3af72 | 8565 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
d14a6d05 MM |
8566 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
8567 | (clobber (match_scratch:SI 3 "X"))])] | |
0ad91047 | 8568 | "TARGET_STRING && ! TARGET_POWER" |
b7ff3d82 DE |
8569 | "{stsi|stswi} %2,%1,%O0" |
8570 | [(set_attr "type" "store")]) | |
7e69e155 MM |
8571 | |
8572 | \f | |
8573 | ;; String/block move insn. | |
8574 | ;; Argument 0 is the destination | |
8575 | ;; Argument 1 is the source | |
8576 | ;; Argument 2 is the length | |
8577 | ;; Argument 3 is the alignment | |
8578 | ||
8579 | (define_expand "movstrsi" | |
b6c9286a MM |
8580 | [(parallel [(set (match_operand:BLK 0 "" "") |
8581 | (match_operand:BLK 1 "" "")) | |
8582 | (use (match_operand:SI 2 "" "")) | |
8583 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
8584 | "" |
8585 | " | |
8586 | { | |
8587 | if (expand_block_move (operands)) | |
8588 | DONE; | |
8589 | else | |
8590 | FAIL; | |
8591 | }") | |
8592 | ||
8593 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8594 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
8595 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8596 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
8597 | [(parallel [(set (match_operand 0 "" "") |
8598 | (match_operand 1 "" "")) | |
8599 | (use (match_operand 2 "" "")) | |
8600 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
8601 | (clobber (reg:SI 5)) |
8602 | (clobber (reg:SI 6)) | |
8603 | (clobber (reg:SI 7)) | |
8604 | (clobber (reg:SI 8)) | |
8605 | (clobber (reg:SI 9)) | |
8606 | (clobber (reg:SI 10)) | |
8607 | (clobber (reg:SI 11)) | |
8608 | (clobber (reg:SI 12)) | |
3c67b673 | 8609 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8610 | "TARGET_STRING" |
8611 | "") | |
8612 | ||
8613 | (define_insn "" | |
52d3af72 DE |
8614 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8615 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8616 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8617 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8618 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8619 | (clobber (reg:SI 6)) |
8620 | (clobber (reg:SI 7)) | |
8621 | (clobber (reg:SI 8)) | |
8622 | (clobber (reg:SI 9)) | |
8623 | (clobber (reg:SI 10)) | |
8624 | (clobber (reg:SI 11)) | |
8625 | (clobber (reg:SI 12)) | |
3c67b673 | 8626 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 8627 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
8628 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8629 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8630 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8631 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8632 | && REGNO (operands[4]) == 5" |
8633 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8634 | [(set_attr "type" "load") |
8635 | (set_attr "length" "8")]) | |
7e69e155 MM |
8636 | |
8637 | (define_insn "" | |
52d3af72 DE |
8638 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8639 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8640 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8641 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8642 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8643 | (clobber (reg:SI 6)) |
8644 | (clobber (reg:SI 7)) | |
8645 | (clobber (reg:SI 8)) | |
8646 | (clobber (reg:SI 9)) | |
8647 | (clobber (reg:SI 10)) | |
8648 | (clobber (reg:SI 11)) | |
8649 | (clobber (reg:SI 12)) | |
3c67b673 | 8650 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8651 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
8652 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8653 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8654 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8655 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8656 | && REGNO (operands[4]) == 5" |
8657 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8658 | [(set_attr "type" "load") |
8659 | (set_attr "length" "8")]) | |
7e69e155 MM |
8660 | |
8661 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8662 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
8663 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8664 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
8665 | [(parallel [(set (match_operand 0 "" "") |
8666 | (match_operand 1 "" "")) | |
8667 | (use (match_operand 2 "" "")) | |
8668 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8669 | (clobber (reg:SI 5)) |
8670 | (clobber (reg:SI 6)) | |
7e69e155 MM |
8671 | (clobber (reg:SI 7)) |
8672 | (clobber (reg:SI 8)) | |
8673 | (clobber (reg:SI 9)) | |
8674 | (clobber (reg:SI 10)) | |
3c67b673 | 8675 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8676 | "TARGET_STRING" |
8677 | "") | |
8678 | ||
8679 | (define_insn "" | |
52d3af72 DE |
8680 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8681 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8682 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8683 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8684 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8685 | (clobber (reg:SI 6)) |
8686 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8687 | (clobber (reg:SI 8)) |
8688 | (clobber (reg:SI 9)) | |
8689 | (clobber (reg:SI 10)) | |
3c67b673 | 8690 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8691 | "TARGET_STRING && TARGET_POWER |
8692 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
8693 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8694 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8695 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8696 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8697 | [(set_attr "type" "load") |
8698 | (set_attr "length" "8")]) | |
7e69e155 MM |
8699 | |
8700 | (define_insn "" | |
52d3af72 DE |
8701 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8702 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8703 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8704 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8705 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8706 | (clobber (reg:SI 6)) |
8707 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8708 | (clobber (reg:SI 8)) |
8709 | (clobber (reg:SI 9)) | |
8710 | (clobber (reg:SI 10)) | |
3c67b673 | 8711 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8712 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8713 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
8714 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8715 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8716 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8717 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8718 | [(set_attr "type" "load") |
8719 | (set_attr "length" "8")]) | |
7e69e155 | 8720 | |
f9562f27 DE |
8721 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
8722 | ;; problems with TImode. | |
8723 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8724 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
8725 | [(parallel [(set (match_operand 0 "" "") |
8726 | (match_operand 1 "" "")) | |
8727 | (use (match_operand 2 "" "")) | |
8728 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8729 | (clobber (reg:SI 5)) |
8730 | (clobber (reg:SI 6)) | |
8731 | (clobber (reg:SI 7)) | |
8732 | (clobber (reg:SI 8)) | |
3c67b673 | 8733 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8734 | "TARGET_STRING" |
8735 | "") | |
8736 | ||
8737 | (define_insn "" | |
52d3af72 DE |
8738 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8739 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8740 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8741 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8742 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8743 | (clobber (reg:SI 6)) |
8744 | (clobber (reg:SI 7)) | |
8745 | (clobber (reg:SI 8)) | |
3c67b673 | 8746 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8747 | "TARGET_STRING && TARGET_POWER |
8748 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
8749 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8750 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8751 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8752 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8753 | [(set_attr "type" "load") |
8754 | (set_attr "length" "8")]) | |
7e69e155 MM |
8755 | |
8756 | (define_insn "" | |
52d3af72 DE |
8757 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8758 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8759 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8760 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8761 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8762 | (clobber (reg:SI 6)) |
8763 | (clobber (reg:SI 7)) | |
8764 | (clobber (reg:SI 8)) | |
3c67b673 | 8765 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8766 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8767 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
8768 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8769 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8770 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8771 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8772 | [(set_attr "type" "load") |
8773 | (set_attr "length" "8")]) | |
7e69e155 MM |
8774 | |
8775 | ;; Move up to 8 bytes at a time. | |
8776 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
8777 | [(parallel [(set (match_operand 0 "" "") |
8778 | (match_operand 1 "" "")) | |
8779 | (use (match_operand 2 "" "")) | |
8780 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8781 | (clobber (match_scratch:DI 4 "")) |
8782 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 8783 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
8784 | "") |
8785 | ||
8786 | (define_insn "" | |
52d3af72 DE |
8787 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8788 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8789 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8790 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8791 | (clobber (match_scratch:DI 4 "=&r")) | |
8792 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 8793 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
8794 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
8795 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8796 | [(set_attr "type" "load") |
8797 | (set_attr "length" "8")]) | |
7e69e155 MM |
8798 | |
8799 | (define_insn "" | |
52d3af72 DE |
8800 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8801 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8802 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8803 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8804 | (clobber (match_scratch:DI 4 "=&r")) | |
8805 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 8806 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 8807 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 8808 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8809 | [(set_attr "type" "load") |
8810 | (set_attr "length" "8")]) | |
7e69e155 MM |
8811 | |
8812 | ;; Move up to 4 bytes at a time. | |
8813 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
8814 | [(parallel [(set (match_operand 0 "" "") |
8815 | (match_operand 1 "" "")) | |
8816 | (use (match_operand 2 "" "")) | |
8817 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8818 | (clobber (match_scratch:SI 4 "")) |
8819 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
8820 | "TARGET_STRING" |
8821 | "") | |
8822 | ||
8823 | (define_insn "" | |
52d3af72 DE |
8824 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8825 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8826 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8827 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8828 | (clobber (match_scratch:SI 4 "=&r")) | |
8829 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
8830 | "TARGET_STRING && TARGET_POWER |
8831 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 8832 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8833 | [(set_attr "type" "load") |
8834 | (set_attr "length" "8")]) | |
7e69e155 MM |
8835 | |
8836 | (define_insn "" | |
52d3af72 DE |
8837 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8838 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8839 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8840 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8841 | (clobber (match_scratch:SI 4 "=&r")) | |
8842 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 8843 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8844 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
3c67b673 | 8845 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8846 | [(set_attr "type" "load") |
8847 | (set_attr "length" "8")]) | |
7e69e155 | 8848 | |
1fd4e8c1 | 8849 | \f |
7e69e155 | 8850 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
8851 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
8852 | ;; do cases where the increment is not the size of the object. | |
8853 | ;; | |
8854 | ;; In all these cases, we use operands 0 and 1 for the register being | |
8855 | ;; incremented because those are the operands that local-alloc will | |
8856 | ;; tie and these are the pair most likely to be tieable (and the ones | |
8857 | ;; that will benefit the most). | |
8858 | ||
38c1f2d7 | 8859 | (define_insn "*movdi_update1" |
51b8fc2c | 8860 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 8861 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
51b8fc2c RK |
8862 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))) |
8863 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
8864 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8865 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8866 | "@ |
8867 | ldux %3,%0,%2 | |
8868 | ldu %3,%2(%0)" | |
8869 | [(set_attr "type" "load")]) | |
8870 | ||
38c1f2d7 | 8871 | (define_insn "*movdi_update2" |
287f13ff RK |
8872 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
8873 | (sign_extend:DI | |
8874 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
8875 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
8876 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
8877 | (plus:DI (match_dup 1) (match_dup 2)))] | |
8878 | "TARGET_POWERPC64" | |
8879 | "lwaux %3,%0,%2" | |
8880 | [(set_attr "type" "load")]) | |
8881 | ||
4697a36c | 8882 | (define_insn "movdi_update" |
51b8fc2c RK |
8883 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
8884 | (match_operand:DI 2 "reg_or_short_operand" "r,I"))) | |
8885 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) | |
8886 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
8887 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8888 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8889 | "@ |
8890 | stdux %3,%0,%2 | |
b7ff3d82 DE |
8891 | stdu %3,%2(%0)" |
8892 | [(set_attr "type" "store")]) | |
51b8fc2c | 8893 | |
38c1f2d7 | 8894 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
8895 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
8896 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8897 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8898 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
8899 | (plus:SI (match_dup 1) (match_dup 2)))] |
8900 | "" | |
8901 | "@ | |
ca7f5001 RK |
8902 | {lux|lwzux} %3,%0,%2 |
8903 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 8904 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8905 | |
4697a36c | 8906 | (define_insn "movsi_update" |
cd2b37d9 | 8907 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8908 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8909 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
8910 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8911 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8912 | "TARGET_UPDATE" |
1fd4e8c1 | 8913 | "@ |
ca7f5001 | 8914 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
8915 | {stu|stwu} %3,%2(%0)" |
8916 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8917 | |
38c1f2d7 | 8918 | (define_insn "*movhi_update" |
cd2b37d9 RK |
8919 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
8920 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8921 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8922 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8923 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8924 | "TARGET_UPDATE" |
1fd4e8c1 | 8925 | "@ |
5f243543 RK |
8926 | lhzux %3,%0,%2 |
8927 | lhzu %3,%2(%0)" | |
cfb557c4 | 8928 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8929 | |
38c1f2d7 | 8930 | (define_insn "*movhi_update2" |
cd2b37d9 | 8931 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8932 | (zero_extend:SI |
cd2b37d9 | 8933 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8934 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8935 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8936 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8937 | "TARGET_UPDATE" |
1fd4e8c1 | 8938 | "@ |
5f243543 RK |
8939 | lhzux %3,%0,%2 |
8940 | lhzu %3,%2(%0)" | |
cfb557c4 | 8941 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8942 | |
38c1f2d7 | 8943 | (define_insn "*movhi_update3" |
cd2b37d9 | 8944 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8945 | (sign_extend:SI |
cd2b37d9 | 8946 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8947 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8948 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8949 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8950 | "TARGET_UPDATE" |
1fd4e8c1 | 8951 | "@ |
5f243543 RK |
8952 | lhaux %3,%0,%2 |
8953 | lhau %3,%2(%0)" | |
cfb557c4 | 8954 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8955 | |
38c1f2d7 | 8956 | (define_insn "*movhi_update4" |
cd2b37d9 | 8957 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8958 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8959 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
8960 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8961 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8962 | "TARGET_UPDATE" |
1fd4e8c1 | 8963 | "@ |
5f243543 | 8964 | sthux %3,%0,%2 |
b7ff3d82 DE |
8965 | sthu %3,%2(%0)" |
8966 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8967 | |
38c1f2d7 | 8968 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
8969 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
8970 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8971 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8972 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8973 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8974 | "TARGET_UPDATE" |
1fd4e8c1 | 8975 | "@ |
5f243543 RK |
8976 | lbzux %3,%0,%2 |
8977 | lbzu %3,%2(%0)" | |
cfb557c4 | 8978 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8979 | |
38c1f2d7 | 8980 | (define_insn "*movqi_update2" |
cd2b37d9 | 8981 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8982 | (zero_extend:SI |
cd2b37d9 | 8983 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8984 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8985 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8986 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8987 | "TARGET_UPDATE" |
1fd4e8c1 | 8988 | "@ |
5f243543 RK |
8989 | lbzux %3,%0,%2 |
8990 | lbzu %3,%2(%0)" | |
cfb557c4 | 8991 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8992 | |
38c1f2d7 | 8993 | (define_insn "*movqi_update3" |
cd2b37d9 | 8994 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8995 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8996 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
8997 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8998 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8999 | "TARGET_UPDATE" |
1fd4e8c1 | 9000 | "@ |
5f243543 | 9001 | stbux %3,%0,%2 |
b7ff3d82 DE |
9002 | stbu %3,%2(%0)" |
9003 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 9004 | |
38c1f2d7 | 9005 | (define_insn "*movsf_update1" |
cd2b37d9 | 9006 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9007 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9008 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9009 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9010 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9011 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9012 | "@ |
5f243543 RK |
9013 | lfsux %3,%0,%2 |
9014 | lfsu %3,%2(%0)" | |
cfb557c4 | 9015 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 9016 | |
38c1f2d7 | 9017 | (define_insn "*movsf_update2" |
cd2b37d9 | 9018 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9019 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9020 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9021 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9022 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9023 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9024 | "@ |
85fff2f3 | 9025 | stfsux %3,%0,%2 |
b7ff3d82 DE |
9026 | stfsu %3,%2(%0)" |
9027 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 9028 | |
38c1f2d7 MM |
9029 | (define_insn "*movsf_update3" |
9030 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9031 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9032 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9033 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9034 | (plus:SI (match_dup 1) (match_dup 2)))] | |
9035 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
9036 | "@ | |
9037 | {lux|lwzux} %3,%0,%2 | |
9038 | {lu|lwzu} %3,%2(%0)" | |
9039 | [(set_attr "type" "load")]) | |
9040 | ||
9041 | (define_insn "*movsf_update4" | |
9042 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9043 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9044 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9045 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9046 | (plus:SI (match_dup 1) (match_dup 2)))] | |
9047 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
9048 | "@ | |
9049 | {stux|stwux} %3,%0,%2 | |
9050 | {stu|stwu} %3,%2(%0)" | |
9051 | [(set_attr "type" "store")]) | |
9052 | ||
9053 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9054 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9055 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9056 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9057 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9058 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9059 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9060 | "@ |
5f243543 RK |
9061 | lfdux %3,%0,%2 |
9062 | lfdu %3,%2(%0)" | |
cfb557c4 | 9063 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 9064 | |
38c1f2d7 | 9065 | (define_insn "*movdf_update2" |
cd2b37d9 | 9066 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9067 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9068 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9069 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9070 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9071 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9072 | "@ |
5f243543 | 9073 | stfdux %3,%0,%2 |
b7ff3d82 DE |
9074 | stfdu %3,%2(%0)" |
9075 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
9076 | |
9077 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9078 | ||
9079 | (define_peephole | |
9080 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
9081 | (match_operand:DF 1 "memory_operand" "")) | |
9082 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
9083 | (match_operand:DF 3 "memory_operand" ""))] | |
9084 | "TARGET_POWER2 | |
d14a6d05 | 9085 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
9086 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
9087 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
9088 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
9089 | "lfq%U1%X1 %0,%1") | |
9090 | ||
9091 | (define_peephole | |
9092 | [(set (match_operand:DF 0 "memory_operand" "") | |
9093 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
9094 | (set (match_operand:DF 2 "memory_operand" "") | |
9095 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
9096 | "TARGET_POWER2 | |
d14a6d05 | 9097 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
9098 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
9099 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
9100 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
9101 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
9102 | \f |
9103 | ;; Next come insns related to the calling sequence. | |
9104 | ;; | |
9105 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9106 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9107 | |
9108 | (define_expand "allocate_stack" | |
52d3af72 | 9109 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9110 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9111 | (set (reg 1) | |
9112 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9113 | "" |
9114 | " | |
4697a36c | 9115 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9116 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9117 | rtx neg_op0; |
1fd4e8c1 RK |
9118 | |
9119 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9120 | |
a157febd GK |
9121 | /* Check stack bounds if necessary. */ |
9122 | if (current_function_limit_stack) | |
9123 | { | |
9124 | rtx available; | |
9125 | available = expand_binop (Pmode, sub_optab, | |
9126 | stack_pointer_rtx, stack_limit_rtx, | |
9127 | NULL_RTX, 1, OPTAB_WIDEN); | |
9128 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9129 | } | |
9130 | ||
e9a25f70 JL |
9131 | if (GET_CODE (operands[1]) != CONST_INT |
9132 | || INTVAL (operands[1]) < -32767 | |
9133 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9134 | { |
9135 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9136 | if (TARGET_32BIT) |
e9a25f70 | 9137 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9138 | else |
e9a25f70 | 9139 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9140 | } |
9141 | else | |
e9a25f70 | 9142 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9143 | |
38c1f2d7 MM |
9144 | if (TARGET_UPDATE) |
9145 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
9146 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 9147 | |
38c1f2d7 MM |
9148 | else |
9149 | { | |
9150 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9151 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9152 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9153 | } |
e9a25f70 JL |
9154 | |
9155 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9156 | DONE; |
9157 | }") | |
59257ff7 RK |
9158 | |
9159 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9160 | ;; save the stack pointer at function level since we are careful to | |
9161 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9162 | ;; when we restore the stack pointer. | |
9163 | ;; | |
9164 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9165 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9166 | ;; save area is a memory location. | |
9167 | ||
9168 | (define_expand "save_stack_function" | |
ff381587 MM |
9169 | [(match_operand 0 "any_operand" "") |
9170 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9171 | "" |
ff381587 | 9172 | "DONE;") |
59257ff7 RK |
9173 | |
9174 | (define_expand "restore_stack_function" | |
ff381587 MM |
9175 | [(match_operand 0 "any_operand" "") |
9176 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9177 | "" |
ff381587 | 9178 | "DONE;") |
59257ff7 RK |
9179 | |
9180 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9181 | [(use (match_operand 0 "register_operand" "")) |
9182 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9183 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9184 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9185 | "" |
9186 | " | |
dfdfa60f DE |
9187 | { |
9188 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9189 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9190 | }") |
59257ff7 RK |
9191 | |
9192 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9193 | [(match_operand 0 "memory_operand" "") |
9194 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9195 | "" |
9196 | " | |
9197 | { | |
a260abc9 | 9198 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9199 | |
9200 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9201 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
9202 | emit_move_insn (operand_subword (operands[0], 0, 0, |
9203 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
9204 | temp); |
9205 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
9206 | operands[1]); | |
59257ff7 RK |
9207 | DONE; |
9208 | }") | |
7e69e155 | 9209 | |
59257ff7 | 9210 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9211 | [(match_operand 0 "register_operand" "") |
9212 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9213 | "" |
9214 | " | |
9215 | { | |
a260abc9 | 9216 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9217 | |
9218 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
9219 | emit_move_insn (temp, |
9220 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
9221 | emit_move_insn (operands[0], | |
c5c76735 JL |
9222 | operand_subword (operands[1], 1, 0, |
9223 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 9224 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9225 | DONE; |
9226 | }") | |
9ebbca7d GK |
9227 | \f |
9228 | ;; TOC register handling. | |
b6c9286a | 9229 | |
9ebbca7d | 9230 | ;; Code to initialize the TOC register... |
f0f6a223 | 9231 | |
9ebbca7d GK |
9232 | (define_insn "load_toc_aix_si" |
9233 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9234 | (unspec:SI [(const_int 0)] 7))] | |
9235 | "! TARGET_ELF && TARGET_32BIT" | |
f0f6a223 RK |
9236 | "* |
9237 | { | |
9ebbca7d GK |
9238 | char buf[30]; |
9239 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9240 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9241 | operands[2] = gen_rtx_REG (Pmode, 2); |
9242 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9243 | }" |
9244 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9245 | |
9246 | (define_insn "load_toc_aix_di" | |
9247 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9248 | (unspec:DI [(const_int 0)] 7))] | |
9249 | "! TARGET_ELF && TARGET_64BIT" | |
9250 | "* | |
9251 | { | |
9252 | char buf[30]; | |
9253 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9254 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9255 | operands[2] = gen_rtx_REG (Pmode, 2); |
9256 | return \"ld %0,%1(%2)\"; | |
9257 | }" | |
9258 | [(set_attr "type" "load")]) | |
9259 | ||
9260 | (define_insn "load_toc_v4_pic_si" | |
9261 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9262 | (unspec:SI [(const_int 0)] 7))] | |
9263 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1 | |
9264 | && TARGET_32BIT" | |
9265 | "bl _GLOBAL_OFFSET_TABLE_@local-4" | |
9266 | [(set_attr "type" "branch") | |
9267 | (set_attr "length" "4")]) | |
9268 | ||
9269 | (define_insn "load_toc_v4_pic_di" | |
9270 | [(set (match_operand:DI 0 "register_operand" "=l") | |
9271 | (unspec:DI [(const_int 0)] 7))] | |
9272 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1 | |
9273 | && TARGET_64BIT" | |
9274 | "bl _GLOBAL_OFFSET_TABLE_@local-4" | |
9275 | [(set_attr "type" "branch") | |
9276 | (set_attr "length" "4")]) | |
9277 | ||
9278 | (define_insn "load_toc_v4_PIC_1" | |
9279 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9280 | (match_operand:SI 1 "immediate_operand" "s")) | |
9281 | (unspec [(match_dup 1)] 7)] | |
9282 | "TARGET_ELF && flag_pic == 2" | |
9283 | "bl %1\\n%1:" | |
9284 | [(set_attr "type" "branch") | |
9285 | (set_attr "length" "4")]) | |
9286 | ||
9287 | (define_insn "load_toc_v4_PIC_1b" | |
9288 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9289 | (match_operand:SI 1 "immediate_operand" "s")) | |
9290 | (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] | |
9291 | "TARGET_ELF && flag_pic == 2" | |
9292 | "bl %1\\n\\t.long %2-%1+4\\n%1:" | |
9293 | [(set_attr "type" "branch") | |
9294 | (set_attr "length" "8")]) | |
9295 | ||
9296 | (define_insn "load_toc_v4_PIC_2" | |
9297 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9298 | (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") | |
9299 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") | |
9300 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
9301 | "TARGET_ELF && flag_pic == 2" | |
9302 | "{l|lwz} %0,%2-%3(%1)" | |
9303 | [(set_attr "type" "load")]) | |
9304 | ||
ee890fe2 SS |
9305 | (define_insn "load_macho_picbase" |
9306 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9307 | (unspec:SI [(const_int 0)] 15))] | |
9308 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" | |
9309 | "* | |
9310 | { | |
9311 | #if TARGET_MACHO | |
9312 | char *picbase = machopic_function_base_name (); | |
9313 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); | |
9314 | #endif | |
9315 | return \"bcl 20,31,%1\\n%1:\"; | |
9316 | }" | |
9317 | [(set_attr "type" "branch") | |
9318 | (set_attr "length" "4")]) | |
9319 | ||
9ebbca7d GK |
9320 | ;; If the TOC is shared over a translation unit, as happens with all |
9321 | ;; the kinds of PIC that we support, we need to restore the TOC | |
9322 | ;; pointer only when jumping over units of translation. | |
9323 | ||
9324 | (define_expand "builtin_setjmp_receiver" | |
9325 | [(use (label_ref (match_operand 0 "" "")))] | |
9326 | "((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1) | |
9327 | || (TARGET_TOC && TARGET_MINIMAL_TOC)" | |
9328 | " | |
9329 | { | |
9330 | rs6000_emit_load_toc_table (FALSE); | |
9331 | DONE; | |
9332 | }") | |
9333 | \f | |
9334 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
9335 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
9336 | ;; pointer to its TOC, and whose third word contains a value to place in the |
9337 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 9338 | ;; "trampoline" need not have any executable code. |
b6c9286a | 9339 | |
cccf3bdc DE |
9340 | (define_expand "call_indirect_aix32" |
9341 | [(set (match_dup 2) | |
9342 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
9343 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9344 | (reg:SI 2)) | |
9345 | (set (reg:SI 2) | |
9346 | (mem:SI (plus:SI (match_dup 0) | |
9347 | (const_int 4)))) | |
9348 | (set (reg:SI 11) | |
9349 | (mem:SI (plus:SI (match_dup 0) | |
9350 | (const_int 8)))) | |
9351 | (parallel [(call (mem:SI (match_dup 2)) | |
9352 | (match_operand 1 "" "")) | |
9353 | (use (reg:SI 2)) | |
9354 | (use (reg:SI 11)) | |
9355 | (set (reg:SI 2) | |
9356 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9357 | (clobber (scratch:SI))])] | |
9358 | "TARGET_32BIT" | |
9359 | " | |
9360 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9361 | |
cccf3bdc DE |
9362 | (define_expand "call_indirect_aix64" |
9363 | [(set (match_dup 2) | |
9364 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
9365 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9366 | (reg:DI 2)) | |
9367 | (set (reg:DI 2) | |
9368 | (mem:DI (plus:DI (match_dup 0) | |
9369 | (const_int 8)))) | |
9370 | (set (reg:DI 11) | |
9371 | (mem:DI (plus:DI (match_dup 0) | |
9372 | (const_int 16)))) | |
9373 | (parallel [(call (mem:SI (match_dup 2)) | |
9374 | (match_operand 1 "" "")) | |
9375 | (use (reg:DI 2)) | |
9376 | (use (reg:DI 11)) | |
9377 | (set (reg:DI 2) | |
9378 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9379 | (clobber (scratch:SI))])] | |
9380 | "TARGET_64BIT" | |
9381 | " | |
9382 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 9383 | |
cccf3bdc DE |
9384 | (define_expand "call_value_indirect_aix32" |
9385 | [(set (match_dup 3) | |
9386 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
9387 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9388 | (reg:SI 2)) | |
9389 | (set (reg:SI 2) | |
9390 | (mem:SI (plus:SI (match_dup 1) | |
9391 | (const_int 4)))) | |
9392 | (set (reg:SI 11) | |
9393 | (mem:SI (plus:SI (match_dup 1) | |
9394 | (const_int 8)))) | |
9395 | (parallel [(set (match_operand 0 "" "") | |
9396 | (call (mem:SI (match_dup 3)) | |
9397 | (match_operand 2 "" ""))) | |
9398 | (use (reg:SI 2)) | |
9399 | (use (reg:SI 11)) | |
9400 | (set (reg:SI 2) | |
9401 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9402 | (clobber (scratch:SI))])] | |
9403 | "TARGET_32BIT" | |
9404 | " | |
9405 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9406 | |
cccf3bdc DE |
9407 | (define_expand "call_value_indirect_aix64" |
9408 | [(set (match_dup 3) | |
9409 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
9410 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9411 | (reg:DI 2)) | |
9412 | (set (reg:DI 2) | |
9413 | (mem:DI (plus:DI (match_dup 1) | |
9414 | (const_int 8)))) | |
9415 | (set (reg:DI 11) | |
9416 | (mem:DI (plus:DI (match_dup 1) | |
9417 | (const_int 16)))) | |
9418 | (parallel [(set (match_operand 0 "" "") | |
9419 | (call (mem:SI (match_dup 3)) | |
9420 | (match_operand 2 "" ""))) | |
9421 | (use (reg:DI 2)) | |
9422 | (use (reg:DI 11)) | |
9423 | (set (reg:DI 2) | |
9424 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9425 | (clobber (scratch:SI))])] | |
9426 | "TARGET_64BIT" | |
9427 | " | |
9428 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 9429 | |
b6c9286a | 9430 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 9431 | (define_expand "call" |
a260abc9 | 9432 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 9433 | (match_operand 1 "" "")) |
4697a36c | 9434 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
9435 | (clobber (scratch:SI))])] |
9436 | "" | |
9437 | " | |
9438 | { | |
ee890fe2 SS |
9439 | #if TARGET_MACHO |
9440 | if (flag_pic) | |
9441 | operands[0] = machopic_indirect_call_target (operands[0]); | |
9442 | #endif | |
9443 | ||
1fd4e8c1 RK |
9444 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
9445 | abort (); | |
9446 | ||
9447 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 9448 | |
6a4cee5f MM |
9449 | if (GET_CODE (operands[0]) != SYMBOL_REF |
9450 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9451 | { |
6a4cee5f MM |
9452 | if (INTVAL (operands[2]) & CALL_LONG) |
9453 | operands[0] = rs6000_longcall_ref (operands[0]); | |
9454 | ||
cccf3bdc DE |
9455 | if (DEFAULT_ABI == ABI_V4 |
9456 | || DEFAULT_ABI == ABI_AIX_NODESC | |
ee890fe2 | 9457 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc DE |
9458 | || DEFAULT_ABI == ABI_SOLARIS) |
9459 | operands[0] = force_reg (Pmode, operands[0]); | |
1fd4e8c1 | 9460 | |
cccf3bdc DE |
9461 | else if (DEFAULT_ABI == ABI_AIX) |
9462 | { | |
9463 | /* AIX function pointers are really pointers to a three word | |
9464 | area. */ | |
9465 | emit_call_insn (TARGET_32BIT | |
9466 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
9467 | operands[0]), | |
9468 | operands[1]) | |
9469 | : gen_call_indirect_aix64 (force_reg (DImode, | |
9470 | operands[0]), | |
9471 | operands[1])); | |
9472 | DONE; | |
b6c9286a | 9473 | } |
cccf3bdc DE |
9474 | else |
9475 | abort (); | |
1fd4e8c1 RK |
9476 | } |
9477 | }") | |
9478 | ||
9479 | (define_expand "call_value" | |
9480 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 9481 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 9482 | (match_operand 2 "" ""))) |
4697a36c | 9483 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
9484 | (clobber (scratch:SI))])] |
9485 | "" | |
9486 | " | |
9487 | { | |
ee890fe2 SS |
9488 | #if TARGET_MACHO |
9489 | if (flag_pic) | |
9490 | operands[1] = machopic_indirect_call_target (operands[1]); | |
9491 | #endif | |
9492 | ||
1fd4e8c1 RK |
9493 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
9494 | abort (); | |
9495 | ||
9496 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 9497 | |
6a4cee5f MM |
9498 | if (GET_CODE (operands[1]) != SYMBOL_REF |
9499 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9500 | { |
6756293c | 9501 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
9502 | operands[1] = rs6000_longcall_ref (operands[1]); |
9503 | ||
cccf3bdc DE |
9504 | if (DEFAULT_ABI == ABI_V4 |
9505 | || DEFAULT_ABI == ABI_AIX_NODESC | |
ee890fe2 | 9506 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc DE |
9507 | || DEFAULT_ABI == ABI_SOLARIS) |
9508 | operands[0] = force_reg (Pmode, operands[0]); | |
1fd4e8c1 | 9509 | |
cccf3bdc DE |
9510 | else if (DEFAULT_ABI == ABI_AIX) |
9511 | { | |
9512 | /* AIX function pointers are really pointers to a three word | |
9513 | area. */ | |
9514 | emit_call_insn (TARGET_32BIT | |
9515 | ? gen_call_value_indirect_aix32 (operands[0], | |
9516 | force_reg (SImode, | |
9517 | operands[1]), | |
9518 | operands[2]) | |
9519 | : gen_call_value_indirect_aix64 (operands[0], | |
9520 | force_reg (DImode, | |
9521 | operands[1]), | |
9522 | operands[2])); | |
9523 | DONE; | |
b6c9286a | 9524 | } |
cccf3bdc DE |
9525 | else |
9526 | abort (); | |
1fd4e8c1 RK |
9527 | } |
9528 | }") | |
9529 | ||
04780ee7 | 9530 | ;; Call to function in current module. No TOC pointer reload needed. |
4697a36c MM |
9531 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9532 | ;; either the function was not prototyped, or it was prototyped as a | |
9533 | ;; variable argument function. It is > 0 if FP registers were passed | |
9534 | ;; and < 0 if they were not. | |
04780ee7 | 9535 | |
a260abc9 | 9536 | (define_insn "*call_local32" |
4697a36c MM |
9537 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
9538 | (match_operand 1 "" "g,g")) | |
9539 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9540 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 9541 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
9542 | "* |
9543 | { | |
6a4cee5f MM |
9544 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9545 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9546 | ||
9547 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9548 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 9549 | |
a226df46 | 9550 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 9551 | }" |
b7ff3d82 DE |
9552 | [(set_attr "type" "branch") |
9553 | (set_attr "length" "4,8")]) | |
04780ee7 | 9554 | |
a260abc9 DE |
9555 | (define_insn "*call_local64" |
9556 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
9557 | (match_operand 1 "" "g,g")) | |
9558 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9559 | (clobber (match_scratch:SI 3 "=l,l"))] | |
9560 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
9561 | "* | |
9562 | { | |
9563 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
9564 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9565 | ||
9566 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9567 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9568 | ||
9569 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
9570 | }" | |
9571 | [(set_attr "type" "branch") | |
9572 | (set_attr "length" "4,8")]) | |
9573 | ||
cccf3bdc | 9574 | (define_insn "*call_value_local32" |
a260abc9 DE |
9575 | [(set (match_operand 0 "" "=fg,fg") |
9576 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
9577 | (match_operand 2 "" "g,g"))) | |
9578 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9579 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9580 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
9581 | "* | |
9582 | { | |
9583 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9584 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9585 | ||
9586 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9587 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9588 | ||
9589 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9590 | }" | |
9591 | [(set_attr "type" "branch") | |
9592 | (set_attr "length" "4,8")]) | |
9593 | ||
9594 | ||
cccf3bdc | 9595 | (define_insn "*call_value_local64" |
a260abc9 DE |
9596 | [(set (match_operand 0 "" "=fg,fg") |
9597 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
9598 | (match_operand 2 "" "g,g"))) | |
9599 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9600 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9601 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
9602 | "* | |
9603 | { | |
9604 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9605 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9606 | ||
9607 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9608 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9609 | ||
9610 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9611 | }" | |
9612 | [(set_attr "type" "branch") | |
9613 | (set_attr "length" "4,8")]) | |
9614 | ||
04780ee7 | 9615 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 9616 | ;; pointer (r2) after the call unless this is System V. |
4697a36c MM |
9617 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9618 | ;; either the function was not prototyped, or it was prototyped as a | |
9619 | ;; variable argument function. It is > 0 if FP registers were passed | |
9620 | ;; and < 0 if they were not. | |
04780ee7 | 9621 | |
cccf3bdc DE |
9622 | (define_insn "*call_indirect_nonlocal_aix32" |
9623 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
9624 | (match_operand 1 "" "g")) | |
9625 | (use (reg:SI 2)) | |
9626 | (use (reg:SI 11)) | |
9627 | (set (reg:SI 2) | |
9628 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 9629 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
9630 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
9631 | "b%T0l\;{l|lwz} 2,20(1)" | |
9632 | [(set_attr "type" "jmpreg") | |
9633 | (set_attr "length" "8")]) | |
9634 | ||
a260abc9 | 9635 | (define_insn "*call_nonlocal_aix32" |
cccf3bdc DE |
9636 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s")) |
9637 | (match_operand 1 "" "g")) | |
9638 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9639 | (clobber (match_scratch:SI 3 "=l"))] | |
9640 | "TARGET_32BIT | |
9641 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 9642 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9643 | "bl %z0\;%." |
b7ff3d82 | 9644 | [(set_attr "type" "branch") |
cccf3bdc DE |
9645 | (set_attr "length" "8")]) |
9646 | ||
9647 | (define_insn "*call_indirect_nonlocal_aix64" | |
9648 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
9649 | (match_operand 1 "" "g")) | |
9650 | (use (reg:DI 2)) | |
9651 | (use (reg:DI 11)) | |
9652 | (set (reg:DI 2) | |
9653 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 9654 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
9655 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
9656 | "b%T0l\;ld 2,40(1)" | |
9657 | [(set_attr "type" "jmpreg") | |
9658 | (set_attr "length" "8")]) | |
59313e4e | 9659 | |
a260abc9 | 9660 | (define_insn "*call_nonlocal_aix64" |
cccf3bdc DE |
9661 | [(call (mem:SI (match_operand:DI 0 "call_operand" "s")) |
9662 | (match_operand 1 "" "g")) | |
9663 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9664 | (clobber (match_scratch:SI 3 "=l"))] | |
9ebbca7d GK |
9665 | "TARGET_64BIT |
9666 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 9667 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9668 | "bl %z0\;%." |
a260abc9 | 9669 | [(set_attr "type" "branch") |
cccf3bdc | 9670 | (set_attr "length" "8")]) |
7509c759 | 9671 | |
cccf3bdc DE |
9672 | (define_insn "*call_value_indirect_nonlocal_aix32" |
9673 | [(set (match_operand 0 "" "=fg") | |
9674 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) | |
9675 | (match_operand 2 "" "g"))) | |
9676 | (use (reg:SI 2)) | |
9677 | (use (reg:SI 11)) | |
9678 | (set (reg:SI 2) | |
9679 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9680 | (clobber (match_scratch:SI 3 "=l"))] | |
9681 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
9682 | "b%T1l\;{l|lwz} 2,20(1)" | |
9683 | [(set_attr "type" "jmpreg") | |
9684 | (set_attr "length" "8")]) | |
1fd4e8c1 | 9685 | |
cccf3bdc DE |
9686 | (define_insn "*call_value_nonlocal_aix32" |
9687 | [(set (match_operand 0 "" "=fg") | |
9688 | (call (mem:SI (match_operand:SI 1 "call_operand" "s")) | |
9689 | (match_operand 2 "" "g"))) | |
9690 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
9691 | (clobber (match_scratch:SI 4 "=l"))] | |
9692 | "TARGET_32BIT | |
9693 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 9694 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 9695 | "bl %z1\;%." |
b7ff3d82 | 9696 | [(set_attr "type" "branch") |
cccf3bdc | 9697 | (set_attr "length" "8")]) |
04780ee7 | 9698 | |
cccf3bdc DE |
9699 | (define_insn "*call_value_indirect_nonlocal_aix64" |
9700 | [(set (match_operand 0 "" "=fg") | |
9701 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) | |
9702 | (match_operand 2 "" "g"))) | |
9703 | (use (reg:DI 2)) | |
9704 | (use (reg:DI 11)) | |
9705 | (set (reg:DI 2) | |
9706 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9707 | (clobber (match_scratch:SI 3 "=l"))] | |
9708 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
9709 | "b%T1l\;ld 2,40(1)" | |
9710 | [(set_attr "type" "jmpreg") | |
9711 | (set_attr "length" "8")]) | |
9712 | ||
9713 | (define_insn "*call_value_nonlocal_aix64" | |
9714 | [(set (match_operand 0 "" "=fg") | |
9715 | (call (mem:SI (match_operand:DI 1 "call_operand" "s")) | |
9716 | (match_operand 2 "" "g"))) | |
9717 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
9718 | (clobber (match_scratch:SI 4 "=l"))] | |
9ebbca7d GK |
9719 | "TARGET_64BIT |
9720 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 9721 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
9722 | "bl %z1\;%." |
9723 | [(set_attr "type" "branch") | |
9724 | (set_attr "length" "8")]) | |
9725 | ||
9726 | ;; A function pointer under System V is just a normal pointer | |
9727 | ;; operands[0] is the function pointer | |
9728 | ;; operands[1] is the stack size to clean up | |
9729 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
9730 | ;; which indicates how to set cr1 | |
9731 | ||
9732 | (define_insn "*call_nonlocal_sysv" | |
9733 | [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s")) | |
9734 | (match_operand 1 "" "g,g,g,g")) | |
9735 | (use (match_operand:SI 2 "immediate_operand" "O,n,O,n")) | |
9736 | (clobber (match_scratch:SI 3 "=l,l,l,l"))] | |
9737 | "DEFAULT_ABI == ABI_AIX_NODESC | |
9738 | || DEFAULT_ABI == ABI_V4 | |
ee890fe2 | 9739 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc | 9740 | || DEFAULT_ABI == ABI_SOLARIS" |
911f679c MM |
9741 | "* |
9742 | { | |
cccf3bdc | 9743 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
6a4cee5f MM |
9744 | output_asm_insn (\"crxor 6,6,6\", operands); |
9745 | ||
cccf3bdc | 9746 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
6a4cee5f | 9747 | output_asm_insn (\"creqv 6,6,6\", operands); |
7509c759 | 9748 | |
cccf3bdc DE |
9749 | switch (which_alternative) |
9750 | { | |
9751 | default: | |
9752 | abort (); | |
9753 | case 0: | |
9754 | case 1: | |
9755 | return \"b%T0l\"; | |
9756 | case 2: | |
9757 | case 3: | |
9758 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; | |
9759 | } | |
b6c9286a | 9760 | }" |
cccf3bdc DE |
9761 | [(set_attr "type" "jmpreg,jmpreg,branch,branch") |
9762 | (set_attr "length" "4,8,4,8")]) | |
9763 | ||
9764 | (define_insn "*call_value_nonlocal_sysv" | |
9765 | [(set (match_operand 0 "" "=fg,fg,fg,fg") | |
9766 | (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s")) | |
9767 | (match_operand 2 "" "g,g,g,g"))) | |
9768 | (use (match_operand:SI 3 "immediate_operand" "O,n,O,n")) | |
9769 | (clobber (match_scratch:SI 4 "=l,l,l,l"))] | |
9770 | "DEFAULT_ABI == ABI_AIX_NODESC | |
9771 | || DEFAULT_ABI == ABI_V4 | |
ee890fe2 | 9772 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc | 9773 | || DEFAULT_ABI == ABI_SOLARIS" |
b6c9286a MM |
9774 | "* |
9775 | { | |
6a4cee5f MM |
9776 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
9777 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9778 | ||
9779 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9780 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 9781 | |
cccf3bdc DE |
9782 | switch (which_alternative) |
9783 | { | |
9784 | default: | |
9785 | abort (); | |
9786 | case 0: | |
9787 | case 1: | |
9788 | return \"b%T1l\"; | |
9789 | case 2: | |
9790 | case 3: | |
9791 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; | |
9792 | } | |
911f679c | 9793 | }" |
cccf3bdc DE |
9794 | [(set_attr "type" "jmpreg,jmpreg,branch,branch") |
9795 | (set_attr "length" "4,8,4,8")]) | |
e6f948e3 RK |
9796 | |
9797 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
9798 | (define_expand "untyped_call" |
9799 | [(parallel [(call (match_operand 0 "" "") | |
9800 | (const_int 0)) | |
9801 | (match_operand 1 "" "") | |
9802 | (match_operand 2 "" "")])] | |
9803 | "" | |
9804 | " | |
9805 | { | |
9806 | int i; | |
9807 | ||
7d70b8b2 | 9808 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
9809 | |
9810 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9811 | { | |
9812 | rtx set = XVECEXP (operands[2], 0, i); | |
9813 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9814 | } | |
9815 | ||
9816 | /* The optimizer does not know that the call sets the function value | |
9817 | registers we stored in the result block. We avoid problems by | |
9818 | claiming that all hard registers are used and clobbered at this | |
9819 | point. */ | |
9820 | emit_insn (gen_blockage ()); | |
9821 | ||
9822 | DONE; | |
9823 | }") | |
9824 | ||
9825 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9826 | ;; all of memory. This blocks insns from being moved across this point. | |
9827 | ||
9828 | (define_insn "blockage" | |
9829 | [(unspec_volatile [(const_int 0)] 0)] | |
9830 | "" | |
9831 | "") | |
1fd4e8c1 RK |
9832 | \f |
9833 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 9834 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
9835 | ;; |
9836 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
9837 | ;; insns, and branches. We store the operands of compares until we see | |
9838 | ;; how it is used. | |
9839 | (define_expand "cmpsi" | |
9840 | [(set (cc0) | |
cd2b37d9 | 9841 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
9842 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
9843 | "" | |
9844 | " | |
9845 | { | |
9846 | /* Take care of the possibility that operands[1] might be negative but | |
9847 | this might be a logical operation. That insn doesn't exist. */ | |
9848 | if (GET_CODE (operands[1]) == CONST_INT | |
9849 | && INTVAL (operands[1]) < 0) | |
9850 | operands[1] = force_reg (SImode, operands[1]); | |
9851 | ||
9852 | rs6000_compare_op0 = operands[0]; | |
9853 | rs6000_compare_op1 = operands[1]; | |
9854 | rs6000_compare_fp_p = 0; | |
9855 | DONE; | |
9856 | }") | |
9857 | ||
266eb58a DE |
9858 | (define_expand "cmpdi" |
9859 | [(set (cc0) | |
9860 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
9861 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
9862 | "TARGET_POWERPC64" | |
9863 | " | |
9864 | { | |
9865 | /* Take care of the possibility that operands[1] might be negative but | |
9866 | this might be a logical operation. That insn doesn't exist. */ | |
9867 | if (GET_CODE (operands[1]) == CONST_INT | |
9868 | && INTVAL (operands[1]) < 0) | |
9869 | operands[1] = force_reg (DImode, operands[1]); | |
9870 | ||
9871 | rs6000_compare_op0 = operands[0]; | |
9872 | rs6000_compare_op1 = operands[1]; | |
9873 | rs6000_compare_fp_p = 0; | |
9874 | DONE; | |
9875 | }") | |
9876 | ||
1fd4e8c1 | 9877 | (define_expand "cmpsf" |
cd2b37d9 RK |
9878 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
9879 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 9880 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9881 | " |
9882 | { | |
9883 | rs6000_compare_op0 = operands[0]; | |
9884 | rs6000_compare_op1 = operands[1]; | |
9885 | rs6000_compare_fp_p = 1; | |
9886 | DONE; | |
9887 | }") | |
9888 | ||
9889 | (define_expand "cmpdf" | |
cd2b37d9 RK |
9890 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
9891 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 9892 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9893 | " |
9894 | { | |
9895 | rs6000_compare_op0 = operands[0]; | |
9896 | rs6000_compare_op1 = operands[1]; | |
9897 | rs6000_compare_fp_p = 1; | |
9898 | DONE; | |
9899 | }") | |
9900 | ||
9901 | (define_expand "beq" | |
39a10a29 | 9902 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9903 | "" |
39a10a29 | 9904 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
9905 | |
9906 | (define_expand "bne" | |
39a10a29 | 9907 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9908 | "" |
39a10a29 | 9909 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 9910 | |
39a10a29 GK |
9911 | (define_expand "bge" |
9912 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9913 | "" |
39a10a29 | 9914 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
9915 | |
9916 | (define_expand "bgt" | |
39a10a29 | 9917 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9918 | "" |
39a10a29 | 9919 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
9920 | |
9921 | (define_expand "ble" | |
39a10a29 | 9922 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9923 | "" |
39a10a29 | 9924 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 9925 | |
39a10a29 GK |
9926 | (define_expand "blt" |
9927 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9928 | "" |
39a10a29 | 9929 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 9930 | |
39a10a29 GK |
9931 | (define_expand "bgeu" |
9932 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9933 | "" |
39a10a29 | 9934 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 9935 | |
39a10a29 GK |
9936 | (define_expand "bgtu" |
9937 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9938 | "" |
39a10a29 | 9939 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 9940 | |
39a10a29 GK |
9941 | (define_expand "bleu" |
9942 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9943 | "" |
39a10a29 | 9944 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 9945 | |
39a10a29 GK |
9946 | (define_expand "bltu" |
9947 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9948 | "" |
39a10a29 | 9949 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 9950 | |
1c882ea4 | 9951 | (define_expand "bunordered" |
39a10a29 | 9952 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9953 | "" |
39a10a29 | 9954 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
9955 | |
9956 | (define_expand "bordered" | |
39a10a29 | 9957 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9958 | "" |
39a10a29 | 9959 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
9960 | |
9961 | (define_expand "buneq" | |
39a10a29 | 9962 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9963 | "" |
39a10a29 | 9964 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
9965 | |
9966 | (define_expand "bunge" | |
39a10a29 | 9967 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9968 | "" |
39a10a29 | 9969 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
9970 | |
9971 | (define_expand "bungt" | |
39a10a29 | 9972 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9973 | "" |
39a10a29 | 9974 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
9975 | |
9976 | (define_expand "bunle" | |
39a10a29 | 9977 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9978 | "" |
39a10a29 | 9979 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
9980 | |
9981 | (define_expand "bunlt" | |
39a10a29 | 9982 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9983 | "" |
39a10a29 | 9984 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
9985 | |
9986 | (define_expand "bltgt" | |
39a10a29 | 9987 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9988 | "" |
39a10a29 | 9989 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 9990 | |
1fd4e8c1 RK |
9991 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
9992 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
9993 | ;; with an scc insns. However, due to the order that combine see the | |
9994 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
9995 | ;; the cases we don't want to handle. | |
9996 | (define_expand "seq" | |
39a10a29 | 9997 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9998 | "" |
39a10a29 | 9999 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10000 | |
10001 | (define_expand "sne" | |
39a10a29 | 10002 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10003 | "" |
10004 | " | |
39a10a29 GK |
10005 | { |
10006 | if (! rs6000_compare_fp_p) | |
1fd4e8c1 RK |
10007 | FAIL; |
10008 | ||
39a10a29 GK |
10009 | rs6000_emit_sCOND (NE, operands[0]); |
10010 | DONE; | |
1fd4e8c1 RK |
10011 | }") |
10012 | ||
10013 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
10014 | (define_expand "sgt" | |
39a10a29 | 10015 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10016 | "" |
10017 | " | |
5638268e DE |
10018 | { |
10019 | if (! rs6000_compare_fp_p | |
10020 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10021 | FAIL; |
10022 | ||
39a10a29 GK |
10023 | rs6000_emit_sCOND (GT, operands[0]); |
10024 | DONE; | |
1fd4e8c1 RK |
10025 | }") |
10026 | ||
10027 | ;; A < 0 is best done in the portable way for A an integer. | |
10028 | (define_expand "slt" | |
39a10a29 | 10029 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10030 | "" |
10031 | " | |
5638268e DE |
10032 | { |
10033 | if (! rs6000_compare_fp_p | |
10034 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10035 | FAIL; |
10036 | ||
39a10a29 GK |
10037 | rs6000_emit_sCOND (LT, operands[0]); |
10038 | DONE; | |
1fd4e8c1 RK |
10039 | }") |
10040 | ||
5638268e | 10041 | ;; A >= 0 is best done the portable way for A an integer. |
1fd4e8c1 | 10042 | (define_expand "sge" |
39a10a29 | 10043 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10044 | "" |
5638268e DE |
10045 | " |
10046 | { | |
10047 | if (! rs6000_compare_fp_p | |
10048 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
10049 | FAIL; | |
10050 | ||
10051 | rs6000_emit_sCOND (GE, operands[0]); | |
10052 | DONE; | |
10053 | }") | |
1fd4e8c1 RK |
10054 | |
10055 | ;; A <= 0 is best done the portable way for A an integer. | |
10056 | (define_expand "sle" | |
39a10a29 | 10057 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10058 | "" |
10059 | " | |
5638268e DE |
10060 | { |
10061 | if (! rs6000_compare_fp_p | |
10062 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10063 | FAIL; |
10064 | ||
39a10a29 GK |
10065 | rs6000_emit_sCOND (LE, operands[0]); |
10066 | DONE; | |
1fd4e8c1 RK |
10067 | }") |
10068 | ||
10069 | (define_expand "sgtu" | |
39a10a29 | 10070 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10071 | "" |
39a10a29 | 10072 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10073 | |
10074 | (define_expand "sltu" | |
39a10a29 | 10075 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10076 | "" |
39a10a29 | 10077 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10078 | |
10079 | (define_expand "sgeu" | |
39a10a29 | 10080 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10081 | "" |
39a10a29 | 10082 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10083 | |
10084 | (define_expand "sleu" | |
39a10a29 | 10085 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10086 | "" |
39a10a29 | 10087 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10088 | \f |
10089 | ;; Here are the actual compare insns. | |
acad7ed3 | 10090 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 10091 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10092 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
10093 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
10094 | "" | |
7f340546 | 10095 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
10096 | [(set_attr "type" "compare")]) |
10097 | ||
acad7ed3 | 10098 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
10099 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
10100 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
10101 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
10102 | "TARGET_POWERPC64" | |
10103 | "cmpd%I2 %0,%1,%2" | |
10104 | [(set_attr "type" "compare")]) | |
10105 | ||
f357808b RK |
10106 | ;; If we are comparing a register for equality with a large constant, |
10107 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
10108 | ;; register for the result of the XOR. | |
10109 | ||
10110 | (define_split | |
10111 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 10112 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 10113 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 10114 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
10115 | "find_single_use (operands[0], insn, 0) |
10116 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
10117 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
10118 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
10119 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
10120 | " | |
10121 | { | |
10122 | /* Get the constant we are comparing against, C, and see what it looks like | |
10123 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
10124 | with C to get the sign-extended value. */ | |
10125 | ||
5f59ecb7 DE |
10126 | HOST_WIDE_INT c = INTVAL (operands[2]); |
10127 | HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000); | |
10128 | HOST_WIDE_INT xorv = c ^ sextc; | |
f357808b | 10129 | |
89e9f3a8 MM |
10130 | operands[4] = GEN_INT (xorv); |
10131 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
10132 | }") |
10133 | ||
acad7ed3 | 10134 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 10135 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10136 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 10137 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 10138 | "" |
e2c953b6 | 10139 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
1fd4e8c1 RK |
10140 | [(set_attr "type" "compare")]) |
10141 | ||
acad7ed3 | 10142 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
10143 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
10144 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 10145 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 10146 | "" |
e2c953b6 | 10147 | "cmpld%I2 %0,%1,%b2" |
266eb58a DE |
10148 | [(set_attr "type" "compare")]) |
10149 | ||
1fd4e8c1 RK |
10150 | ;; The following two insns don't exist as single insns, but if we provide |
10151 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
10152 | ;; of the required delay between a compare and branch. We generate code for | |
10153 | ;; them by splitting. | |
10154 | ||
10155 | (define_insn "" | |
10156 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10157 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10158 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 10159 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10160 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10161 | "" | |
baf97f86 RK |
10162 | "#" |
10163 | [(set_attr "length" "8")]) | |
7e69e155 | 10164 | |
1fd4e8c1 RK |
10165 | (define_insn "" |
10166 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10167 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10168 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 10169 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10170 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10171 | "" | |
baf97f86 RK |
10172 | "#" |
10173 | [(set_attr "length" "8")]) | |
7e69e155 | 10174 | |
1fd4e8c1 RK |
10175 | (define_split |
10176 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 10177 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10178 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 10179 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10180 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10181 | "" | |
10182 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
10183 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10184 | ||
10185 | (define_split | |
10186 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 10187 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10188 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 10189 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10190 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10191 | "" | |
10192 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
10193 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10194 | ||
acad7ed3 | 10195 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 10196 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10197 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
10198 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10199 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10200 | "fcmpu %0,%1,%2" |
10201 | [(set_attr "type" "fpcompare")]) | |
10202 | ||
acad7ed3 | 10203 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 10204 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10205 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
10206 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10207 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10208 | "fcmpu %0,%1,%2" |
10209 | [(set_attr "type" "fpcompare")]) | |
10210 | \f | |
10211 | ;; Now we have the scc insns. We can do some combinations because of the | |
10212 | ;; way the machine works. | |
10213 | ;; | |
10214 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
10215 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
10216 | ;; cases the insns below which don't use an intermediate CR field will | |
10217 | ;; be used instead. | |
1fd4e8c1 | 10218 | (define_insn "" |
cd2b37d9 | 10219 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10220 | (match_operator:SI 1 "scc_comparison_operator" |
10221 | [(match_operand 2 "cc_reg_operand" "y") | |
10222 | (const_int 0)]))] | |
10223 | "" | |
ca7f5001 | 10224 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b19003d8 | 10225 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10226 | |
10227 | (define_insn "" | |
9ebbca7d GK |
10228 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
10229 | (match_operator:DI 1 "scc_comparison_operator" | |
10230 | [(match_operand 2 "cc_reg_operand" "y") | |
10231 | (const_int 0)]))] | |
10232 | "TARGET_POWERPC64" | |
10233 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" | |
10234 | [(set_attr "length" "12")]) | |
10235 | ||
10236 | (define_insn "" | |
10237 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 10238 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 10239 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
10240 | (const_int 0)]) |
10241 | (const_int 0))) | |
9ebbca7d | 10242 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10243 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 10244 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10245 | "@ |
10246 | %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 | |
10247 | #" | |
b19003d8 | 10248 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10249 | (set_attr "length" "12,16")]) |
10250 | ||
10251 | (define_split | |
10252 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10253 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
10254 | [(match_operand 2 "cc_reg_operand" "") | |
10255 | (const_int 0)]) | |
10256 | (const_int 0))) | |
10257 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
10258 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
10259 | "! TARGET_POWERPC64 && reload_completed" | |
10260 | [(set (match_dup 3) | |
10261 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
10262 | (set (match_dup 0) | |
10263 | (compare:CC (match_dup 3) | |
10264 | (const_int 0)))] | |
10265 | "") | |
1fd4e8c1 RK |
10266 | |
10267 | (define_insn "" | |
cd2b37d9 | 10268 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10269 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
10270 | [(match_operand 2 "cc_reg_operand" "y") | |
10271 | (const_int 0)]) | |
10272 | (match_operand:SI 3 "const_int_operand" "n")))] | |
10273 | "" | |
10274 | "* | |
10275 | { | |
10276 | int is_bit = ccr_bit (operands[1], 1); | |
10277 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
10278 | int count; | |
10279 | ||
10280 | if (is_bit >= put_bit) | |
10281 | count = is_bit - put_bit; | |
10282 | else | |
10283 | count = 32 - (put_bit - is_bit); | |
10284 | ||
89e9f3a8 MM |
10285 | operands[4] = GEN_INT (count); |
10286 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 10287 | |
ca7f5001 | 10288 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 RK |
10289 | }" |
10290 | [(set_attr "length" "12")]) | |
1fd4e8c1 RK |
10291 | |
10292 | (define_insn "" | |
9ebbca7d | 10293 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10294 | (compare:CC |
10295 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 10296 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 10297 | (const_int 0)]) |
9ebbca7d | 10298 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 10299 | (const_int 0))) |
9ebbca7d | 10300 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
10301 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
10302 | (match_dup 3)))] | |
9ebbca7d | 10303 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
10304 | "* |
10305 | { | |
10306 | int is_bit = ccr_bit (operands[1], 1); | |
10307 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
10308 | int count; | |
10309 | ||
9ebbca7d GK |
10310 | /* Force split for non-cc0 compare. */ |
10311 | if (which_alternative == 1) | |
10312 | return \"#\"; | |
10313 | ||
1fd4e8c1 RK |
10314 | if (is_bit >= put_bit) |
10315 | count = is_bit - put_bit; | |
10316 | else | |
10317 | count = 32 - (put_bit - is_bit); | |
10318 | ||
89e9f3a8 MM |
10319 | operands[5] = GEN_INT (count); |
10320 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 10321 | |
ca7f5001 | 10322 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 10323 | }" |
b19003d8 | 10324 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10325 | (set_attr "length" "12,16")]) |
10326 | ||
10327 | (define_split | |
10328 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10329 | (compare:CC | |
10330 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
10331 | [(match_operand 2 "cc_reg_operand" "") | |
10332 | (const_int 0)]) | |
10333 | (match_operand:SI 3 "const_int_operand" "")) | |
10334 | (const_int 0))) | |
10335 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
10336 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10337 | (match_dup 3)))] | |
10338 | "! TARGET_POWERPC64 && reload_completed" | |
10339 | [(set (match_dup 4) | |
10340 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10341 | (match_dup 3))) | |
10342 | (set (match_dup 0) | |
10343 | (compare:CC (match_dup 4) | |
10344 | (const_int 0)))] | |
10345 | "") | |
1fd4e8c1 | 10346 | |
c5defebb RK |
10347 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
10348 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
10349 | ||
10350 | (define_peephole | |
cd2b37d9 | 10351 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
10352 | (match_operator:SI 1 "scc_comparison_operator" |
10353 | [(match_operand 2 "cc_reg_operand" "y") | |
10354 | (const_int 0)])) | |
cd2b37d9 | 10355 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
10356 | (match_operator:SI 4 "scc_comparison_operator" |
10357 | [(match_operand 5 "cc_reg_operand" "y") | |
10358 | (const_int 0)]))] | |
10359 | "REGNO (operands[2]) != REGNO (operands[5])" | |
ca7f5001 | 10360 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b19003d8 | 10361 | [(set_attr "length" "20")]) |
c5defebb | 10362 | |
9ebbca7d GK |
10363 | (define_peephole |
10364 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10365 | (match_operator:DI 1 "scc_comparison_operator" | |
10366 | [(match_operand 2 "cc_reg_operand" "y") | |
10367 | (const_int 0)])) | |
10368 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
10369 | (match_operator:DI 4 "scc_comparison_operator" | |
10370 | [(match_operand 5 "cc_reg_operand" "y") | |
10371 | (const_int 0)]))] | |
10372 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" | |
10373 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
10374 | [(set_attr "length" "20")]) | |
10375 | ||
1fd4e8c1 RK |
10376 | ;; There are some scc insns that can be done directly, without a compare. |
10377 | ;; These are faster because they don't involve the communications between | |
10378 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
10379 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
10380 | ;; | |
10381 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
10382 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
10383 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
10384 | ;; cases where it is no more expensive than (neg (scc ..)). | |
10385 | ||
10386 | ;; Have reload force a constant into a register for the simple insns that | |
10387 | ;; otherwise won't accept constants. We do this because it is faster than | |
10388 | ;; the cmp/mfcr sequence we would otherwise generate. | |
10389 | ||
10390 | (define_insn "" | |
cd2b37d9 RK |
10391 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
10392 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 10393 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 10394 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
f9562f27 | 10395 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10396 | "@ |
ca7f5001 | 10397 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 10398 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
10399 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
10400 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
10401 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 10402 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 10403 | |
a260abc9 DE |
10404 | (define_insn "" |
10405 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
10406 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
10407 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
10408 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
10409 | "TARGET_POWERPC64" | |
10410 | "@ | |
10411 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10412 | subfic %3,%1,0\;adde %0,%3,%1 | |
10413 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10414 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10415 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
10416 | [(set_attr "length" "12,8,12,12,12")]) | |
10417 | ||
1fd4e8c1 | 10418 | (define_insn "" |
9ebbca7d | 10419 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10420 | (compare:CC |
9ebbca7d GK |
10421 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10422 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 10423 | (const_int 0))) |
9ebbca7d | 10424 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 10425 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10426 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
f9562f27 | 10427 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10428 | "@ |
ca7f5001 RK |
10429 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
10430 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
10431 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
10432 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
10433 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
10434 | # | |
10435 | # | |
10436 | # | |
10437 | # | |
10438 | #" | |
b19003d8 | 10439 | [(set_attr "type" "compare") |
9ebbca7d GK |
10440 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10441 | ||
10442 | (define_split | |
10443 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10444 | (compare:CC | |
10445 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10446 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10447 | (const_int 0))) | |
10448 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10449 | (eq:SI (match_dup 1) (match_dup 2))) | |
10450 | (clobber (match_scratch:SI 3 ""))] | |
10451 | "! TARGET_POWERPC64 && reload_completed" | |
10452 | [(parallel [(set (match_dup 0) | |
10453 | (eq:SI (match_dup 1) (match_dup 2))) | |
10454 | (clobber (match_dup 3))]) | |
10455 | (set (match_dup 4) | |
10456 | (compare:CC (match_dup 0) | |
10457 | (const_int 0)))] | |
10458 | "") | |
b19003d8 | 10459 | |
a260abc9 | 10460 | (define_insn "" |
9ebbca7d | 10461 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 10462 | (compare:CC |
9ebbca7d GK |
10463 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10464 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 10465 | (const_int 0))) |
9ebbca7d | 10466 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 10467 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10468 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
a260abc9 DE |
10469 | "TARGET_POWERPC64" |
10470 | "@ | |
10471 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
10472 | subfic %3,%1,0\;adde. %0,%3,%1 | |
10473 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
10474 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
10475 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
10476 | # | |
10477 | # | |
10478 | # | |
10479 | # | |
10480 | #" | |
a260abc9 | 10481 | [(set_attr "type" "compare") |
9ebbca7d GK |
10482 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10483 | ||
10484 | (define_split | |
10485 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10486 | (compare:CC | |
10487 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
10488 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
10489 | (const_int 0))) | |
10490 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10491 | (eq:DI (match_dup 1) (match_dup 2))) | |
10492 | (clobber (match_scratch:DI 3 ""))] | |
10493 | "TARGET_POWERPC64 && reload_completed" | |
10494 | [(parallel [(set (match_dup 0) | |
10495 | (eq:DI (match_dup 1) (match_dup 2))) | |
10496 | (clobber (match_dup 3))]) | |
10497 | (set (match_dup 4) | |
10498 | (compare:CC (match_dup 0) | |
10499 | (const_int 0)))] | |
10500 | "") | |
a260abc9 | 10501 | |
b19003d8 RK |
10502 | ;; We have insns of the form shown by the first define_insn below. If |
10503 | ;; there is something inside the comparison operation, we must split it. | |
10504 | (define_split | |
10505 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
10506 | (plus:SI (match_operator 1 "comparison_operator" | |
10507 | [(match_operand:SI 2 "" "") | |
10508 | (match_operand:SI 3 | |
10509 | "reg_or_cint_operand" "")]) | |
10510 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
10511 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
10512 | "! gpc_reg_operand (operands[2], SImode)" | |
10513 | [(set (match_dup 5) (match_dup 2)) | |
10514 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
10515 | (match_dup 4)))]) | |
1fd4e8c1 RK |
10516 | |
10517 | (define_insn "" | |
cd2b37d9 RK |
10518 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
10519 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 10520 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
cd2b37d9 | 10521 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) |
1fd4e8c1 | 10522 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
f9562f27 | 10523 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10524 | "@ |
ca7f5001 RK |
10525 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
10526 | {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 | |
10527 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
10528 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
d9d934ef | 10529 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" |
b19003d8 | 10530 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
10531 | |
10532 | (define_insn "" | |
9ebbca7d | 10533 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10534 | (compare:CC |
1fd4e8c1 | 10535 | (plus:SI |
9ebbca7d GK |
10536 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10537 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
10538 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 10539 | (const_int 0))) |
9ebbca7d | 10540 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 10541 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10542 | "@ |
ca7f5001 | 10543 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 10544 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
10545 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
10546 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
10547 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
10548 | # | |
10549 | # | |
10550 | # | |
10551 | # | |
10552 | #" | |
b19003d8 | 10553 | [(set_attr "type" "compare") |
9ebbca7d GK |
10554 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10555 | ||
10556 | (define_split | |
10557 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10558 | (compare:CC | |
10559 | (plus:SI | |
10560 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10561 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10562 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10563 | (const_int 0))) | |
10564 | (clobber (match_scratch:SI 4 ""))] | |
10565 | "! TARGET_POWERPC64 && reload_completed" | |
10566 | [(set (match_dup 4) | |
10567 | (plus:SI (eq:SI (match_dup 1) | |
10568 | (match_dup 2)) | |
10569 | (match_dup 3))) | |
10570 | (set (match_dup 0) | |
10571 | (compare:CC (match_dup 4) | |
10572 | (const_int 0)))] | |
10573 | "") | |
1fd4e8c1 RK |
10574 | |
10575 | (define_insn "" | |
9ebbca7d | 10576 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10577 | (compare:CC |
1fd4e8c1 | 10578 | (plus:SI |
9ebbca7d GK |
10579 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10580 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
10581 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 10582 | (const_int 0))) |
9ebbca7d | 10583 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 10584 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10585 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 10586 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10587 | "@ |
ca7f5001 | 10588 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
19378cf8 | 10589 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 |
ca7f5001 RK |
10590 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
10591 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
10592 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
10593 | # | |
10594 | # | |
10595 | # | |
10596 | # | |
10597 | #" | |
10598 | [(set_attr "type" "compare") | |
10599 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
10600 | ||
10601 | (define_split | |
10602 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10603 | (compare:CC | |
10604 | (plus:SI | |
10605 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10606 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10607 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10608 | (const_int 0))) | |
10609 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10610 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10611 | (clobber (match_scratch:SI 4 ""))] | |
10612 | "! TARGET_POWERPC64 && reload_completed" | |
10613 | [(parallel [(set (match_dup 0) | |
10614 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10615 | (clobber (match_dup 4))]) | |
10616 | (set (match_dup 5) | |
10617 | (compare:CC (match_dup 0) | |
10618 | (const_int 0)))] | |
10619 | "") | |
10620 | ||
1fd4e8c1 | 10621 | (define_insn "" |
cd2b37d9 | 10622 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 10623 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 10624 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
f9562f27 | 10625 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10626 | "@ |
ca7f5001 RK |
10627 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
10628 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
10629 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
10630 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
10631 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 10632 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 10633 | |
ea9be077 MM |
10634 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
10635 | ;; since it nabs/sr is just as fast. | |
463b558b | 10636 | (define_insn "*ne0" |
b4e95693 | 10637 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
10638 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
10639 | (const_int 31))) | |
10640 | (clobber (match_scratch:SI 2 "=&r"))] | |
9ebbca7d | 10641 | "! TARGET_POWER && ! TARGET_POWERPC64" |
ea9be077 MM |
10642 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
10643 | [(set_attr "length" "8")]) | |
10644 | ||
a260abc9 DE |
10645 | (define_insn "" |
10646 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10647 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
10648 | (const_int 63))) | |
10649 | (clobber (match_scratch:DI 2 "=&r"))] | |
10650 | "TARGET_POWERPC64" | |
10651 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
10652 | [(set_attr "length" "8")]) | |
10653 | ||
1fd4e8c1 RK |
10654 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
10655 | (define_insn "" | |
cd2b37d9 | 10656 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10657 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 10658 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10659 | (const_int 31)) |
cd2b37d9 | 10660 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10661 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 10662 | "! TARGET_POWERPC64" |
ca7f5001 | 10663 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 10664 | [(set_attr "length" "8")]) |
1fd4e8c1 | 10665 | |
a260abc9 DE |
10666 | (define_insn "" |
10667 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10668 | (plus:DI (lshiftrt:DI | |
10669 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
10670 | (const_int 63)) | |
10671 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
10672 | (clobber (match_scratch:DI 3 "=&r"))] | |
10673 | "TARGET_POWERPC64" | |
10674 | "addic %3,%1,-1\;addze %0,%2" | |
10675 | [(set_attr "length" "8")]) | |
10676 | ||
1fd4e8c1 | 10677 | (define_insn "" |
9ebbca7d | 10678 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10679 | (compare:CC |
10680 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 10681 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10682 | (const_int 31)) |
9ebbca7d | 10683 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 10684 | (const_int 0))) |
9ebbca7d | 10685 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 10686 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10687 | "@ |
10688 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
10689 | #" | |
b19003d8 | 10690 | [(set_attr "type" "compare") |
9ebbca7d GK |
10691 | (set_attr "length" "8,12")]) |
10692 | ||
10693 | (define_split | |
10694 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10695 | (compare:CC | |
10696 | (plus:SI (lshiftrt:SI | |
10697 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10698 | (const_int 31)) | |
10699 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
10700 | (const_int 0))) | |
10701 | (clobber (match_scratch:SI 3 ""))] | |
10702 | "! TARGET_POWERPC64 && reload_completed" | |
10703 | [(set (match_dup 3) | |
10704 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) | |
10705 | (const_int 31)) | |
10706 | (match_dup 2))) | |
10707 | (set (match_dup 0) | |
10708 | (compare:CC (match_dup 3) | |
10709 | (const_int 0)))] | |
10710 | "") | |
1fd4e8c1 | 10711 | |
a260abc9 | 10712 | (define_insn "" |
9ebbca7d | 10713 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
10714 | (compare:CC |
10715 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 10716 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 10717 | (const_int 63)) |
9ebbca7d | 10718 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 10719 | (const_int 0))) |
9ebbca7d | 10720 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 10721 | "TARGET_POWERPC64" |
9ebbca7d GK |
10722 | "@ |
10723 | addic %3,%1,-1\;addze. %3,%2 | |
10724 | #" | |
a260abc9 | 10725 | [(set_attr "type" "compare") |
9ebbca7d GK |
10726 | (set_attr "length" "8,12")]) |
10727 | ||
10728 | (define_split | |
10729 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10730 | (compare:CC | |
10731 | (plus:DI (lshiftrt:DI | |
10732 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10733 | (const_int 63)) | |
10734 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
10735 | (const_int 0))) | |
10736 | (clobber (match_scratch:DI 3 ""))] | |
10737 | "TARGET_POWERPC64 && reload_completed" | |
10738 | [(set (match_dup 3) | |
10739 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
10740 | (const_int 63)) | |
10741 | (match_dup 2))) | |
10742 | (set (match_dup 0) | |
10743 | (compare:CC (match_dup 3) | |
10744 | (const_int 0)))] | |
10745 | "") | |
a260abc9 | 10746 | |
1fd4e8c1 | 10747 | (define_insn "" |
9ebbca7d | 10748 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10749 | (compare:CC |
10750 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 10751 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10752 | (const_int 31)) |
9ebbca7d | 10753 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 10754 | (const_int 0))) |
9ebbca7d | 10755 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
10756 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
10757 | (match_dup 2))) | |
9ebbca7d | 10758 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 10759 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10760 | "@ |
10761 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
10762 | #" | |
b19003d8 | 10763 | [(set_attr "type" "compare") |
9ebbca7d GK |
10764 | (set_attr "length" "8,12")]) |
10765 | ||
10766 | (define_split | |
10767 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10768 | (compare:CC | |
10769 | (plus:SI (lshiftrt:SI | |
10770 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10771 | (const_int 31)) | |
10772 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
10773 | (const_int 0))) | |
10774 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10775 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
10776 | (match_dup 2))) | |
10777 | (clobber (match_scratch:SI 3 ""))] | |
10778 | "! TARGET_POWERPC64 && reload_completed" | |
10779 | [(parallel [(set (match_dup 0) | |
10780 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
10781 | (match_dup 2))) | |
10782 | (clobber (match_dup 3))]) | |
10783 | (set (match_dup 4) | |
10784 | (compare:CC (match_dup 0) | |
10785 | (const_int 0)))] | |
10786 | "") | |
1fd4e8c1 | 10787 | |
a260abc9 | 10788 | (define_insn "" |
9ebbca7d | 10789 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
10790 | (compare:CC |
10791 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 10792 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 10793 | (const_int 63)) |
9ebbca7d | 10794 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 10795 | (const_int 0))) |
9ebbca7d | 10796 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
10797 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
10798 | (match_dup 2))) | |
9ebbca7d | 10799 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 10800 | "TARGET_POWERPC64" |
9ebbca7d GK |
10801 | "@ |
10802 | addic %3,%1,-1\;addze. %0,%2 | |
10803 | #" | |
a260abc9 | 10804 | [(set_attr "type" "compare") |
9ebbca7d GK |
10805 | (set_attr "length" "8,12")]) |
10806 | ||
10807 | (define_split | |
10808 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10809 | (compare:CC | |
10810 | (plus:DI (lshiftrt:DI | |
10811 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10812 | (const_int 63)) | |
10813 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
10814 | (const_int 0))) | |
10815 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10816 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
10817 | (match_dup 2))) | |
10818 | (clobber (match_scratch:DI 3 ""))] | |
10819 | "TARGET_POWERPC64 && reload_completed" | |
10820 | [(parallel [(set (match_dup 0) | |
10821 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
10822 | (match_dup 2))) | |
10823 | (clobber (match_dup 3))]) | |
10824 | (set (match_dup 4) | |
10825 | (compare:CC (match_dup 0) | |
10826 | (const_int 0)))] | |
10827 | "") | |
a260abc9 | 10828 | |
1fd4e8c1 | 10829 | (define_insn "" |
cd2b37d9 RK |
10830 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10831 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
10832 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
10833 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 10834 | "TARGET_POWER" |
1fd4e8c1 | 10835 | "@ |
ca7f5001 | 10836 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 10837 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 10838 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10839 | |
10840 | (define_insn "" | |
9ebbca7d | 10841 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10842 | (compare:CC |
9ebbca7d GK |
10843 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10844 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 10845 | (const_int 0))) |
9ebbca7d | 10846 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 10847 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10848 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 10849 | "TARGET_POWER" |
1fd4e8c1 | 10850 | "@ |
ca7f5001 | 10851 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
10852 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
10853 | # | |
10854 | #" | |
10855 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
10856 | (set_attr "length" "12,12,16,16")]) | |
10857 | ||
10858 | (define_split | |
10859 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10860 | (compare:CC | |
10861 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10862 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10863 | (const_int 0))) | |
10864 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10865 | (le:SI (match_dup 1) (match_dup 2))) | |
10866 | (clobber (match_scratch:SI 3 ""))] | |
10867 | "TARGET_POWER && reload_completed" | |
10868 | [(parallel [(set (match_dup 0) | |
10869 | (le:SI (match_dup 1) (match_dup 2))) | |
10870 | (clobber (match_dup 3))]) | |
10871 | (set (match_dup 4) | |
10872 | (compare:CC (match_dup 0) | |
10873 | (const_int 0)))] | |
10874 | "") | |
1fd4e8c1 RK |
10875 | |
10876 | (define_insn "" | |
cd2b37d9 RK |
10877 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10878 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 10879 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 10880 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10881 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 10882 | "TARGET_POWER" |
1fd4e8c1 | 10883 | "@ |
ca7f5001 RK |
10884 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
10885 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" | |
b19003d8 | 10886 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10887 | |
10888 | (define_insn "" | |
9ebbca7d | 10889 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10890 | (compare:CC |
9ebbca7d GK |
10891 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10892 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
10893 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 10894 | (const_int 0))) |
9ebbca7d | 10895 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 10896 | "TARGET_POWER" |
1fd4e8c1 | 10897 | "@ |
ca7f5001 | 10898 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
10899 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
10900 | # | |
10901 | #" | |
b19003d8 | 10902 | [(set_attr "type" "compare") |
9ebbca7d GK |
10903 | (set_attr "length" "12,12,16,16")]) |
10904 | ||
10905 | (define_split | |
10906 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10907 | (compare:CC | |
10908 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10909 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10910 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10911 | (const_int 0))) | |
10912 | (clobber (match_scratch:SI 4 ""))] | |
10913 | "TARGET_POWER && reload_completed" | |
10914 | [(set (match_dup 4) | |
10915 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
10916 | (match_dup 3))) | |
10917 | (set (match_dup 0) | |
10918 | (compare:CC (match_dup 4) | |
10919 | (const_int 0)))] | |
10920 | "") | |
1fd4e8c1 RK |
10921 | |
10922 | (define_insn "" | |
9ebbca7d | 10923 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10924 | (compare:CC |
9ebbca7d GK |
10925 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10926 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
10927 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 10928 | (const_int 0))) |
9ebbca7d | 10929 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 10930 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10931 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 10932 | "TARGET_POWER" |
1fd4e8c1 | 10933 | "@ |
ca7f5001 | 10934 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
10935 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3 |
10936 | # | |
10937 | #" | |
b19003d8 | 10938 | [(set_attr "type" "compare") |
9ebbca7d GK |
10939 | (set_attr "length" "12,12,16,16")]) |
10940 | ||
10941 | (define_split | |
10942 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10943 | (compare:CC | |
10944 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10945 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10946 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10947 | (const_int 0))) | |
10948 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10949 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10950 | (clobber (match_scratch:SI 4 ""))] | |
10951 | "TARGET_POWER && reload_completed" | |
10952 | [(parallel [(set (match_dup 0) | |
10953 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10954 | (clobber (match_dup 4))]) | |
10955 | (set (match_dup 5) | |
10956 | (compare:CC (match_dup 0) | |
10957 | (const_int 0)))] | |
10958 | "") | |
1fd4e8c1 RK |
10959 | |
10960 | (define_insn "" | |
cd2b37d9 RK |
10961 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10962 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 10963 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 10964 | "TARGET_POWER" |
1fd4e8c1 | 10965 | "@ |
ca7f5001 RK |
10966 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
10967 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 10968 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10969 | |
10970 | (define_insn "" | |
cd2b37d9 RK |
10971 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10972 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10973 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 10974 | "! TARGET_POWERPC64" |
ca7f5001 | 10975 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 10976 | [(set_attr "length" "12")]) |
1fd4e8c1 | 10977 | |
f9562f27 DE |
10978 | (define_insn "" |
10979 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10980 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
10981 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
10982 | "TARGET_POWERPC64" | |
10983 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" | |
10984 | [(set_attr "length" "12")]) | |
10985 | ||
10986 | (define_insn "" | |
9ebbca7d | 10987 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 10988 | (compare:CC |
9ebbca7d GK |
10989 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
10990 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 10991 | (const_int 0))) |
9ebbca7d | 10992 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
10993 | (leu:DI (match_dup 1) (match_dup 2)))] |
10994 | "TARGET_POWERPC64" | |
9ebbca7d GK |
10995 | "@ |
10996 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
10997 | #" | |
f9562f27 | 10998 | [(set_attr "type" "compare") |
9ebbca7d GK |
10999 | (set_attr "length" "12,16")]) |
11000 | ||
11001 | (define_split | |
11002 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11003 | (compare:CC | |
11004 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11005 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
11006 | (const_int 0))) | |
11007 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11008 | (leu:DI (match_dup 1) (match_dup 2)))] | |
11009 | "TARGET_POWERPC64 && reload_completed" | |
11010 | [(set (match_dup 0) | |
11011 | (leu:DI (match_dup 1) (match_dup 2))) | |
11012 | (set (match_dup 3) | |
11013 | (compare:CC (match_dup 0) | |
11014 | (const_int 0)))] | |
11015 | "") | |
f9562f27 | 11016 | |
1fd4e8c1 | 11017 | (define_insn "" |
9ebbca7d | 11018 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11019 | (compare:CC |
9ebbca7d GK |
11020 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11021 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11022 | (const_int 0))) |
9ebbca7d | 11023 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11024 | (leu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11025 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11026 | "@ |
11027 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
11028 | #" | |
b19003d8 | 11029 | [(set_attr "type" "compare") |
9ebbca7d GK |
11030 | (set_attr "length" "12,16")]) |
11031 | ||
11032 | (define_split | |
11033 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11034 | (compare:CC | |
11035 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11036 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11037 | (const_int 0))) | |
11038 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11039 | (leu:SI (match_dup 1) (match_dup 2)))] | |
11040 | "! TARGET_POWERPC64 && reload_completed" | |
11041 | [(set (match_dup 0) | |
11042 | (leu:SI (match_dup 1) (match_dup 2))) | |
11043 | (set (match_dup 3) | |
11044 | (compare:CC (match_dup 0) | |
11045 | (const_int 0)))] | |
11046 | "") | |
1fd4e8c1 | 11047 | |
f9562f27 | 11048 | (define_insn "" |
9ebbca7d | 11049 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11050 | (compare:CC |
9ebbca7d GK |
11051 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11052 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11053 | (const_int 0))) |
9ebbca7d | 11054 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11055 | (leu:DI (match_dup 1) (match_dup 2)))] |
11056 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11057 | "@ |
11058 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11059 | #" | |
f9562f27 | 11060 | [(set_attr "type" "compare") |
9ebbca7d | 11061 | (set_attr "length" "12,16")]) |
f9562f27 | 11062 | |
1fd4e8c1 | 11063 | (define_insn "" |
cd2b37d9 RK |
11064 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11065 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11066 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11067 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11068 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 11069 | "! TARGET_POWERPC64" |
ca7f5001 | 11070 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 11071 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11072 | |
11073 | (define_insn "" | |
9ebbca7d | 11074 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11075 | (compare:CC |
9ebbca7d GK |
11076 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11077 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11078 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11079 | (const_int 0))) |
9ebbca7d | 11080 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11081 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11082 | "@ |
11083 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
11084 | #" | |
b19003d8 | 11085 | [(set_attr "type" "compare") |
9ebbca7d GK |
11086 | (set_attr "length" "8,12")]) |
11087 | ||
11088 | (define_split | |
11089 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11090 | (compare:CC | |
11091 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11092 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11093 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11094 | (const_int 0))) | |
11095 | (clobber (match_scratch:SI 4 ""))] | |
11096 | "! TARGET_POWERPC64 && reload_completed" | |
11097 | [(set (match_dup 4) | |
11098 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
11099 | (match_dup 3))) | |
11100 | (set (match_dup 0) | |
11101 | (compare:CC (match_dup 4) | |
11102 | (const_int 0)))] | |
11103 | "") | |
1fd4e8c1 RK |
11104 | |
11105 | (define_insn "" | |
9ebbca7d | 11106 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11107 | (compare:CC |
9ebbca7d GK |
11108 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11109 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11110 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11111 | (const_int 0))) |
9ebbca7d | 11112 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11113 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11114 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11115 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11116 | "@ |
11117 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3 | |
11118 | #" | |
b19003d8 | 11119 | [(set_attr "type" "compare") |
9ebbca7d GK |
11120 | (set_attr "length" "8,12")]) |
11121 | ||
11122 | (define_split | |
11123 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11124 | (compare:CC | |
11125 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11126 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11127 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11128 | (const_int 0))) | |
11129 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11130 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11131 | (clobber (match_scratch:SI 4 ""))] | |
11132 | "! TARGET_POWERPC64 && reload_completed" | |
11133 | [(parallel [(set (match_dup 0) | |
11134 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11135 | (clobber (match_dup 4))]) | |
11136 | (set (match_dup 5) | |
11137 | (compare:CC (match_dup 0) | |
11138 | (const_int 0)))] | |
11139 | "") | |
1fd4e8c1 RK |
11140 | |
11141 | (define_insn "" | |
cd2b37d9 RK |
11142 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11143 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11144 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 11145 | "! TARGET_POWERPC64" |
ca7f5001 | 11146 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 11147 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11148 | |
11149 | (define_insn "" | |
cd2b37d9 | 11150 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11151 | (and:SI (neg:SI |
cd2b37d9 | 11152 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11153 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 11154 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11155 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 11156 | "! TARGET_POWERPC64" |
ca7f5001 | 11157 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" |
b19003d8 | 11158 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11159 | |
11160 | (define_insn "" | |
9ebbca7d | 11161 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11162 | (compare:CC |
11163 | (and:SI (neg:SI | |
9ebbca7d GK |
11164 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11165 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11166 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11167 | (const_int 0))) |
9ebbca7d | 11168 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11169 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11170 | "@ |
11171 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
11172 | #" | |
11173 | [(set_attr "type" "compare") | |
11174 | (set_attr "length" "12,16")]) | |
11175 | ||
11176 | (define_split | |
11177 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11178 | (compare:CC | |
11179 | (and:SI (neg:SI | |
11180 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11181 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11182 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11183 | (const_int 0))) | |
11184 | (clobber (match_scratch:SI 4 ""))] | |
11185 | "! TARGET_POWERPC64 && reload_completed" | |
11186 | [(set (match_dup 4) | |
11187 | (and:SI (neg:SI (leu:SI (match_dup 1) | |
11188 | (match_dup 2))) | |
11189 | (match_dup 3))) | |
11190 | (set (match_dup 0) | |
11191 | (compare:CC (match_dup 4) | |
11192 | (const_int 0)))] | |
11193 | "") | |
1fd4e8c1 RK |
11194 | |
11195 | (define_insn "" | |
9ebbca7d | 11196 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11197 | (compare:CC |
11198 | (and:SI (neg:SI | |
9ebbca7d GK |
11199 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11200 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11201 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11202 | (const_int 0))) |
9ebbca7d | 11203 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11204 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 11205 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11206 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11207 | "@ |
11208 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 | |
11209 | #" | |
b19003d8 | 11210 | [(set_attr "type" "compare") |
9ebbca7d GK |
11211 | (set_attr "length" "12,16")]) |
11212 | ||
11213 | (define_split | |
11214 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11215 | (compare:CC | |
11216 | (and:SI (neg:SI | |
11217 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11218 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11219 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11220 | (const_int 0))) | |
11221 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11222 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11223 | (clobber (match_scratch:SI 4 ""))] | |
11224 | "! TARGET_POWERPC64 && reload_completed" | |
11225 | [(parallel [(set (match_dup 0) | |
11226 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11227 | (clobber (match_dup 4))]) | |
11228 | (set (match_dup 5) | |
11229 | (compare:CC (match_dup 0) | |
11230 | (const_int 0)))] | |
11231 | "") | |
1fd4e8c1 RK |
11232 | |
11233 | (define_insn "" | |
cd2b37d9 RK |
11234 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11235 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11236 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 11237 | "TARGET_POWER" |
7f340546 | 11238 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11239 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11240 | |
11241 | (define_insn "" | |
9ebbca7d | 11242 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11243 | (compare:CC |
9ebbca7d GK |
11244 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11245 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11246 | (const_int 0))) |
9ebbca7d | 11247 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11248 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11249 | "TARGET_POWER" |
9ebbca7d GK |
11250 | "@ |
11251 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11252 | #" | |
29ae5b89 | 11253 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11254 | (set_attr "length" "12,16")]) |
11255 | ||
11256 | (define_split | |
11257 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11258 | (compare:CC | |
11259 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11260 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11261 | (const_int 0))) | |
11262 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11263 | (lt:SI (match_dup 1) (match_dup 2)))] | |
11264 | "TARGET_POWER && reload_completed" | |
11265 | [(set (match_dup 0) | |
11266 | (lt:SI (match_dup 1) (match_dup 2))) | |
11267 | (set (match_dup 3) | |
11268 | (compare:CC (match_dup 0) | |
11269 | (const_int 0)))] | |
11270 | "") | |
1fd4e8c1 RK |
11271 | |
11272 | (define_insn "" | |
cd2b37d9 RK |
11273 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11274 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11275 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11276 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11277 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11278 | "TARGET_POWER" |
11279 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 11280 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11281 | |
11282 | (define_insn "" | |
9ebbca7d | 11283 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11284 | (compare:CC |
9ebbca7d GK |
11285 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11286 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11287 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11288 | (const_int 0))) |
9ebbca7d | 11289 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11290 | "TARGET_POWER" |
9ebbca7d GK |
11291 | "@ |
11292 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
11293 | #" | |
b19003d8 | 11294 | [(set_attr "type" "compare") |
9ebbca7d GK |
11295 | (set_attr "length" "12,16")]) |
11296 | ||
11297 | (define_split | |
11298 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11299 | (compare:CC | |
11300 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11301 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11302 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11303 | (const_int 0))) | |
11304 | (clobber (match_scratch:SI 4 ""))] | |
11305 | "TARGET_POWER && reload_completed" | |
11306 | [(set (match_dup 4) | |
11307 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
11308 | (match_dup 3))) | |
11309 | (set (match_dup 0) | |
11310 | (compare:CC (match_dup 4) | |
11311 | (const_int 0)))] | |
11312 | "") | |
1fd4e8c1 RK |
11313 | |
11314 | (define_insn "" | |
9ebbca7d | 11315 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11316 | (compare:CC |
9ebbca7d GK |
11317 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11318 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11319 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11320 | (const_int 0))) |
9ebbca7d | 11321 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11322 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11323 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11324 | "TARGET_POWER" |
9ebbca7d GK |
11325 | "@ |
11326 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
11327 | #" | |
b19003d8 | 11328 | [(set_attr "type" "compare") |
9ebbca7d GK |
11329 | (set_attr "length" "12,16")]) |
11330 | ||
11331 | (define_split | |
11332 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11333 | (compare:CC | |
11334 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11335 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11336 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11337 | (const_int 0))) | |
11338 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11339 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11340 | (clobber (match_scratch:SI 4 ""))] | |
11341 | "TARGET_POWER && reload_completed" | |
11342 | [(parallel [(set (match_dup 0) | |
11343 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11344 | (clobber (match_dup 4))]) | |
11345 | (set (match_dup 5) | |
11346 | (compare:CC (match_dup 0) | |
11347 | (const_int 0)))] | |
11348 | "") | |
1fd4e8c1 RK |
11349 | |
11350 | (define_insn "" | |
cd2b37d9 RK |
11351 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11352 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11353 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11354 | "TARGET_POWER" |
11355 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11356 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11357 | |
11358 | (define_insn "" | |
cd2b37d9 RK |
11359 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11360 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11361 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11362 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11363 | "@ |
ca7f5001 RK |
11364 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
11365 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 11366 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11367 | |
11368 | (define_insn "" | |
9ebbca7d | 11369 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11370 | (compare:CC |
9ebbca7d GK |
11371 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11372 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 11373 | (const_int 0))) |
9ebbca7d | 11374 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11375 | (ltu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11376 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11377 | "@ |
ca7f5001 | 11378 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
11379 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
11380 | # | |
11381 | #" | |
b19003d8 | 11382 | [(set_attr "type" "compare") |
9ebbca7d GK |
11383 | (set_attr "length" "12,12,16,16")]) |
11384 | ||
11385 | (define_split | |
11386 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11387 | (compare:CC | |
11388 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11389 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11390 | (const_int 0))) | |
11391 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11392 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
11393 | "! TARGET_POWERPC64 && reload_completed" | |
11394 | [(set (match_dup 0) | |
11395 | (ltu:SI (match_dup 1) (match_dup 2))) | |
11396 | (set (match_dup 3) | |
11397 | (compare:CC (match_dup 0) | |
11398 | (const_int 0)))] | |
11399 | "") | |
1fd4e8c1 RK |
11400 | |
11401 | (define_insn "" | |
19378cf8 MM |
11402 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11403 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
11404 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
11405 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI"))) | |
11406 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 11407 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11408 | "@ |
ca7f5001 | 11409 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 |
04be6346 | 11410 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
b19003d8 | 11411 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11412 | |
11413 | (define_insn "" | |
9ebbca7d | 11414 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11415 | (compare:CC |
9ebbca7d GK |
11416 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11417 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11418 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11419 | (const_int 0))) |
9ebbca7d | 11420 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11421 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11422 | "@ |
ca7f5001 | 11423 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
11424 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
11425 | # | |
11426 | #" | |
b19003d8 | 11427 | [(set_attr "type" "compare") |
9ebbca7d GK |
11428 | (set_attr "length" "12,12,16,16")]) |
11429 | ||
11430 | (define_split | |
11431 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11432 | (compare:CC | |
11433 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11434 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11435 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11436 | (const_int 0))) | |
11437 | (clobber (match_scratch:SI 4 ""))] | |
11438 | "! TARGET_POWERPC64 && reload_completed" | |
11439 | [(set (match_dup 4) | |
11440 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
11441 | (match_dup 3))) | |
11442 | (set (match_dup 0) | |
11443 | (compare:CC (match_dup 4) | |
11444 | (const_int 0)))] | |
11445 | "") | |
1fd4e8c1 RK |
11446 | |
11447 | (define_insn "" | |
9ebbca7d | 11448 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11449 | (compare:CC |
9ebbca7d GK |
11450 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11451 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11452 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11453 | (const_int 0))) |
9ebbca7d | 11454 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11455 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11456 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11457 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11458 | "@ |
ca7f5001 | 11459 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
9ebbca7d GK |
11460 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
11461 | # | |
11462 | #" | |
b19003d8 | 11463 | [(set_attr "type" "compare") |
9ebbca7d GK |
11464 | (set_attr "length" "12,12,16,16")]) |
11465 | ||
11466 | (define_split | |
11467 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11468 | (compare:CC | |
11469 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11470 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11471 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11472 | (const_int 0))) | |
11473 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11474 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11475 | (clobber (match_scratch:SI 4 ""))] | |
11476 | "! TARGET_POWERPC64 && reload_completed" | |
11477 | [(parallel [(set (match_dup 0) | |
11478 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11479 | (clobber (match_dup 4))]) | |
11480 | (set (match_dup 5) | |
11481 | (compare:CC (match_dup 0) | |
11482 | (const_int 0)))] | |
11483 | "") | |
1fd4e8c1 RK |
11484 | |
11485 | (define_insn "" | |
cd2b37d9 RK |
11486 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11487 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11488 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
f9562f27 | 11489 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11490 | "@ |
ca7f5001 RK |
11491 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
11492 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11493 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11494 | |
11495 | (define_insn "" | |
cd2b37d9 RK |
11496 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11497 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
11498 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
11499 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
11500 | "TARGET_POWER" |
11501 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 11502 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11503 | |
9ebbca7d GK |
11504 | (define_insn "" |
11505 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11506 | (compare:CC |
9ebbca7d GK |
11507 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11508 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11509 | (const_int 0))) |
9ebbca7d | 11510 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11511 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11512 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 11513 | "TARGET_POWER" |
9ebbca7d GK |
11514 | "@ |
11515 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
11516 | #" | |
11517 | [(set_attr "type" "compare") | |
11518 | (set_attr "length" "12,16")]) | |
11519 | ||
11520 | (define_split | |
11521 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11522 | (compare:CC | |
11523 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11524 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11525 | (const_int 0))) | |
11526 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11527 | (ge:SI (match_dup 1) (match_dup 2))) | |
11528 | (clobber (match_scratch:SI 3 ""))] | |
11529 | "TARGET_POWER && reload_completed" | |
11530 | [(parallel [(set (match_dup 0) | |
11531 | (ge:SI (match_dup 1) (match_dup 2))) | |
11532 | (clobber (match_dup 3))]) | |
11533 | (set (match_dup 4) | |
11534 | (compare:CC (match_dup 0) | |
11535 | (const_int 0)))] | |
11536 | "") | |
11537 | ||
1fd4e8c1 | 11538 | (define_insn "" |
cd2b37d9 RK |
11539 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11540 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11541 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11542 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11543 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11544 | "TARGET_POWER" |
11545 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" | |
b19003d8 | 11546 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11547 | |
11548 | (define_insn "" | |
9ebbca7d | 11549 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11550 | (compare:CC |
9ebbca7d GK |
11551 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11552 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11553 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11554 | (const_int 0))) |
9ebbca7d | 11555 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11556 | "TARGET_POWER" |
9ebbca7d GK |
11557 | "@ |
11558 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
11559 | #" | |
b19003d8 | 11560 | [(set_attr "type" "compare") |
9ebbca7d GK |
11561 | (set_attr "length" "12,16")]) |
11562 | ||
11563 | (define_split | |
11564 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11565 | (compare:CC | |
11566 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11567 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11568 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11569 | (const_int 0))) | |
11570 | (clobber (match_scratch:SI 4 ""))] | |
11571 | "TARGET_POWER && reload_completed" | |
11572 | [(set (match_dup 4) | |
11573 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
11574 | (match_dup 3))) | |
11575 | (set (match_dup 0) | |
11576 | (compare:CC (match_dup 4) | |
11577 | (const_int 0)))] | |
11578 | "") | |
1fd4e8c1 RK |
11579 | |
11580 | (define_insn "" | |
9ebbca7d | 11581 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11582 | (compare:CC |
9ebbca7d GK |
11583 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11584 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11585 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11586 | (const_int 0))) |
9ebbca7d | 11587 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11588 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11589 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11590 | "TARGET_POWER" |
9ebbca7d GK |
11591 | "@ |
11592 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
11593 | #" | |
b19003d8 | 11594 | [(set_attr "type" "compare") |
9ebbca7d GK |
11595 | (set_attr "length" "12,16")]) |
11596 | ||
11597 | (define_split | |
11598 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11599 | (compare:CC | |
11600 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11601 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11602 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11603 | (const_int 0))) | |
11604 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11605 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11606 | (clobber (match_scratch:SI 4 ""))] | |
11607 | "TARGET_POWER && reload_completed" | |
11608 | [(parallel [(set (match_dup 0) | |
11609 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11610 | (clobber (match_dup 4))]) | |
11611 | (set (match_dup 5) | |
11612 | (compare:CC (match_dup 0) | |
11613 | (const_int 0)))] | |
11614 | "") | |
1fd4e8c1 RK |
11615 | |
11616 | (define_insn "" | |
cd2b37d9 RK |
11617 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11618 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11619 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11620 | "TARGET_POWER" |
11621 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11622 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11623 | |
1fd4e8c1 | 11624 | (define_insn "" |
cd2b37d9 RK |
11625 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11626 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11627 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11628 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11629 | "@ |
ca7f5001 RK |
11630 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
11631 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 11632 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11633 | |
f9562f27 DE |
11634 | (define_insn "" |
11635 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
11636 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
11637 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
11638 | "TARGET_POWERPC64" | |
11639 | "@ | |
11640 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
11641 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
11642 | [(set_attr "length" "12")]) | |
11643 | ||
1fd4e8c1 | 11644 | (define_insn "" |
9ebbca7d | 11645 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11646 | (compare:CC |
9ebbca7d GK |
11647 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11648 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 11649 | (const_int 0))) |
9ebbca7d | 11650 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11651 | (geu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11652 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11653 | "@ |
ca7f5001 | 11654 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
11655 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
11656 | # | |
11657 | #" | |
b19003d8 | 11658 | [(set_attr "type" "compare") |
9ebbca7d GK |
11659 | (set_attr "length" "12,12,16,16")]) |
11660 | ||
11661 | (define_split | |
11662 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11663 | (compare:CC | |
11664 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11665 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11666 | (const_int 0))) | |
11667 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11668 | (geu:SI (match_dup 1) (match_dup 2)))] | |
11669 | "! TARGET_POWERPC64 && reload_completed" | |
11670 | [(set (match_dup 0) | |
11671 | (geu:SI (match_dup 1) (match_dup 2))) | |
11672 | (set (match_dup 3) | |
11673 | (compare:CC (match_dup 0) | |
11674 | (const_int 0)))] | |
11675 | "") | |
1fd4e8c1 | 11676 | |
f9562f27 | 11677 | (define_insn "" |
9ebbca7d | 11678 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 11679 | (compare:CC |
9ebbca7d GK |
11680 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
11681 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 11682 | (const_int 0))) |
9ebbca7d | 11683 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 DE |
11684 | (geu:DI (match_dup 1) (match_dup 2)))] |
11685 | "TARGET_POWERPC64" | |
11686 | "@ | |
11687 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
11688 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
11689 | # | |
11690 | #" | |
f9562f27 | 11691 | [(set_attr "type" "compare") |
9ebbca7d GK |
11692 | (set_attr "length" "12,12,16,16")]) |
11693 | ||
11694 | (define_split | |
11695 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11696 | (compare:CC | |
11697 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11698 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
11699 | (const_int 0))) | |
11700 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11701 | (geu:DI (match_dup 1) (match_dup 2)))] | |
11702 | "TARGET_POWERPC64 && reload_completed" | |
11703 | [(set (match_dup 0) | |
11704 | (geu:DI (match_dup 1) (match_dup 2))) | |
11705 | (set (match_dup 3) | |
11706 | (compare:CC (match_dup 0) | |
11707 | (const_int 0)))] | |
11708 | "") | |
f9562f27 | 11709 | |
1fd4e8c1 | 11710 | (define_insn "" |
cd2b37d9 RK |
11711 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11712 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11713 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 11714 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11715 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11716 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11717 | "@ |
ca7f5001 RK |
11718 | {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 |
11719 | {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 11720 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11721 | |
11722 | (define_insn "" | |
9ebbca7d | 11723 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11724 | (compare:CC |
9ebbca7d GK |
11725 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11726 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11727 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11728 | (const_int 0))) |
9ebbca7d | 11729 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11730 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11731 | "@ |
ca7f5001 | 11732 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11733 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
11734 | # | |
11735 | #" | |
b19003d8 | 11736 | [(set_attr "type" "compare") |
9ebbca7d GK |
11737 | (set_attr "length" "8,8,12,12")]) |
11738 | ||
11739 | (define_split | |
11740 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11741 | (compare:CC | |
11742 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11743 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11744 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11745 | (const_int 0))) | |
11746 | (clobber (match_scratch:SI 4 ""))] | |
11747 | "! TARGET_POWERPC64 && reload_completed" | |
11748 | [(set (match_dup 4) | |
11749 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
11750 | (match_dup 3))) | |
11751 | (set (match_dup 0) | |
11752 | (compare:CC (match_dup 4) | |
11753 | (const_int 0)))] | |
11754 | "") | |
1fd4e8c1 RK |
11755 | |
11756 | (define_insn "" | |
9ebbca7d | 11757 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11758 | (compare:CC |
9ebbca7d GK |
11759 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11760 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11761 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11762 | (const_int 0))) |
9ebbca7d | 11763 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11764 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11765 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11766 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11767 | "@ |
ca7f5001 | 11768 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
11769 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3 |
11770 | # | |
11771 | #" | |
b19003d8 | 11772 | [(set_attr "type" "compare") |
9ebbca7d GK |
11773 | (set_attr "length" "8,8,12,12")]) |
11774 | ||
11775 | (define_split | |
11776 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11777 | (compare:CC | |
11778 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11779 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11780 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11781 | (const_int 0))) | |
11782 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11783 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11784 | (clobber (match_scratch:SI 4 ""))] | |
11785 | "! TARGET_POWERPC64 && reload_completed" | |
11786 | [(parallel [(set (match_dup 0) | |
11787 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11788 | (clobber (match_dup 4))]) | |
11789 | (set (match_dup 5) | |
11790 | (compare:CC (match_dup 0) | |
11791 | (const_int 0)))] | |
11792 | "") | |
1fd4e8c1 RK |
11793 | |
11794 | (define_insn "" | |
cd2b37d9 RK |
11795 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11796 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11797 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
f9562f27 | 11798 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11799 | "@ |
ca7f5001 | 11800 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 11801 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 11802 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11803 | |
11804 | (define_insn "" | |
cd2b37d9 | 11805 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11806 | (and:SI (neg:SI |
cd2b37d9 | 11807 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11808 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 11809 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11810 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11811 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11812 | "@ |
ca7f5001 RK |
11813 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 |
11814 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" | |
b19003d8 | 11815 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11816 | |
11817 | (define_insn "" | |
9ebbca7d | 11818 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
11819 | (compare:CC |
11820 | (and:SI (neg:SI | |
9ebbca7d GK |
11821 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11822 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
11823 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11824 | (const_int 0))) |
9ebbca7d | 11825 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11826 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11827 | "@ |
ca7f5001 | 11828 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
11829 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
11830 | # | |
11831 | #" | |
b19003d8 | 11832 | [(set_attr "type" "compare") |
9ebbca7d GK |
11833 | (set_attr "length" "12,12,16,16")]) |
11834 | ||
11835 | (define_split | |
11836 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11837 | (compare:CC | |
11838 | (and:SI (neg:SI | |
11839 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11840 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
11841 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11842 | (const_int 0))) | |
11843 | (clobber (match_scratch:SI 4 ""))] | |
11844 | "! TARGET_POWERPC64 && reload_completed" | |
11845 | [(set (match_dup 4) | |
11846 | (and:SI (neg:SI (geu:SI (match_dup 1) | |
11847 | (match_dup 2))) | |
11848 | (match_dup 3))) | |
11849 | (set (match_dup 0) | |
11850 | (compare:CC (match_dup 4) | |
11851 | (const_int 0)))] | |
11852 | "") | |
1fd4e8c1 RK |
11853 | |
11854 | (define_insn "" | |
9ebbca7d | 11855 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
11856 | (compare:CC |
11857 | (and:SI (neg:SI | |
9ebbca7d GK |
11858 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11859 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
11860 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11861 | (const_int 0))) |
9ebbca7d | 11862 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11863 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 11864 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11865 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11866 | "@ |
ca7f5001 | 11867 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
9ebbca7d GK |
11868 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
11869 | # | |
11870 | #" | |
b19003d8 | 11871 | [(set_attr "type" "compare") |
9ebbca7d GK |
11872 | (set_attr "length" "12,12,16,16")]) |
11873 | ||
11874 | (define_split | |
11875 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11876 | (compare:CC | |
11877 | (and:SI (neg:SI | |
11878 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11879 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
11880 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11881 | (const_int 0))) | |
11882 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11883 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11884 | (clobber (match_scratch:SI 4 ""))] | |
11885 | "! TARGET_POWERPC64 && reload_completed" | |
11886 | [(parallel [(set (match_dup 0) | |
11887 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11888 | (clobber (match_dup 4))]) | |
11889 | (set (match_dup 5) | |
11890 | (compare:CC (match_dup 0) | |
11891 | (const_int 0)))] | |
11892 | "") | |
1fd4e8c1 RK |
11893 | |
11894 | (define_insn "" | |
cd2b37d9 RK |
11895 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11896 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11897 | (const_int 0)))] |
f9562f27 | 11898 | "! TARGET_POWERPC64" |
ca7f5001 | 11899 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11900 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11901 | |
f9562f27 DE |
11902 | (define_insn "" |
11903 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11904 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11905 | (const_int 0)))] | |
11906 | "TARGET_POWERPC64" | |
11907 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" | |
11908 | [(set_attr "length" "12")]) | |
11909 | ||
1fd4e8c1 | 11910 | (define_insn "" |
9ebbca7d | 11911 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11912 | (compare:CC |
9ebbca7d | 11913 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
11914 | (const_int 0)) |
11915 | (const_int 0))) | |
9ebbca7d | 11916 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11917 | (gt:SI (match_dup 1) (const_int 0)))] |
f9562f27 | 11918 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11919 | "@ |
11920 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
11921 | #" | |
29ae5b89 | 11922 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11923 | (set_attr "length" "12,16")]) |
11924 | ||
11925 | (define_split | |
11926 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
11927 | (compare:CC | |
11928 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11929 | (const_int 0)) | |
11930 | (const_int 0))) | |
11931 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11932 | (gt:SI (match_dup 1) (const_int 0)))] | |
11933 | "! TARGET_POWERPC64 && reload_completed" | |
11934 | [(set (match_dup 0) | |
11935 | (gt:SI (match_dup 1) (const_int 0))) | |
11936 | (set (match_dup 2) | |
11937 | (compare:CC (match_dup 0) | |
11938 | (const_int 0)))] | |
11939 | "") | |
1fd4e8c1 | 11940 | |
f9562f27 | 11941 | (define_insn "" |
9ebbca7d | 11942 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 11943 | (compare:CC |
9ebbca7d | 11944 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
11945 | (const_int 0)) |
11946 | (const_int 0))) | |
9ebbca7d | 11947 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11948 | (gt:DI (match_dup 1) (const_int 0)))] |
11949 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11950 | "@ |
11951 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
11952 | #" | |
f9562f27 | 11953 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11954 | (set_attr "length" "12,16")]) |
11955 | ||
11956 | (define_split | |
11957 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
11958 | (compare:CC | |
11959 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11960 | (const_int 0)) | |
11961 | (const_int 0))) | |
11962 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11963 | (gt:DI (match_dup 1) (const_int 0)))] | |
11964 | "TARGET_POWERPC64 && reload_completed" | |
11965 | [(set (match_dup 0) | |
11966 | (gt:DI (match_dup 1) (const_int 0))) | |
11967 | (set (match_dup 2) | |
11968 | (compare:CC (match_dup 0) | |
11969 | (const_int 0)))] | |
11970 | "") | |
f9562f27 | 11971 | |
1fd4e8c1 | 11972 | (define_insn "" |
cd2b37d9 RK |
11973 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11974 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11975 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
11976 | "TARGET_POWER" |
11977 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 11978 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11979 | |
11980 | (define_insn "" | |
9ebbca7d | 11981 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11982 | (compare:CC |
9ebbca7d GK |
11983 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11984 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 11985 | (const_int 0))) |
9ebbca7d | 11986 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11987 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11988 | "TARGET_POWER" |
9ebbca7d GK |
11989 | "@ |
11990 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11991 | #" | |
29ae5b89 | 11992 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11993 | (set_attr "length" "12,16")]) |
11994 | ||
11995 | (define_split | |
11996 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11997 | (compare:CC | |
11998 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11999 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12000 | (const_int 0))) | |
12001 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12002 | (gt:SI (match_dup 1) (match_dup 2)))] | |
12003 | "TARGET_POWER && reload_completed" | |
12004 | [(set (match_dup 0) | |
12005 | (gt:SI (match_dup 1) (match_dup 2))) | |
12006 | (set (match_dup 3) | |
12007 | (compare:CC (match_dup 0) | |
12008 | (const_int 0)))] | |
12009 | "") | |
1fd4e8c1 RK |
12010 | |
12011 | (define_insn "" | |
cd2b37d9 RK |
12012 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12013 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12014 | (const_int 0)) |
cd2b37d9 | 12015 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 12016 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 12017 | "! TARGET_POWERPC64" |
ca7f5001 | 12018 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" |
b19003d8 | 12019 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12020 | |
f9562f27 DE |
12021 | (define_insn "" |
12022 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12023 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12024 | (const_int 0)) | |
12025 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
12026 | (clobber (match_scratch:DI 3 "=&r"))] | |
12027 | "TARGET_POWERPC64" | |
12028 | "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2" | |
12029 | [(set_attr "length" "12")]) | |
12030 | ||
1fd4e8c1 | 12031 | (define_insn "" |
9ebbca7d | 12032 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12033 | (compare:CC |
9ebbca7d | 12034 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12035 | (const_int 0)) |
9ebbca7d | 12036 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12037 | (const_int 0))) |
9ebbca7d | 12038 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 12039 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12040 | "@ |
12041 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
12042 | #" | |
b19003d8 | 12043 | [(set_attr "type" "compare") |
9ebbca7d GK |
12044 | (set_attr "length" "12,16")]) |
12045 | ||
12046 | (define_split | |
12047 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12048 | (compare:CC | |
12049 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12050 | (const_int 0)) | |
12051 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12052 | (const_int 0))) | |
12053 | (clobber (match_scratch:SI 3 ""))] | |
12054 | "! TARGET_POWERPC64 && reload_completed" | |
12055 | [(set (match_dup 3) | |
12056 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
12057 | (match_dup 2))) | |
12058 | (set (match_dup 0) | |
12059 | (compare:CC (match_dup 3) | |
12060 | (const_int 0)))] | |
12061 | "") | |
1fd4e8c1 | 12062 | |
f9562f27 | 12063 | (define_insn "" |
9ebbca7d | 12064 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 12065 | (compare:CC |
9ebbca7d | 12066 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12067 | (const_int 0)) |
9ebbca7d | 12068 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12069 | (const_int 0))) |
9ebbca7d | 12070 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 12071 | "TARGET_POWERPC64" |
9ebbca7d GK |
12072 | "@ |
12073 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
12074 | #" | |
f9562f27 | 12075 | [(set_attr "type" "compare") |
9ebbca7d GK |
12076 | (set_attr "length" "12,16")]) |
12077 | ||
12078 | (define_split | |
12079 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12080 | (compare:CC | |
12081 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12082 | (const_int 0)) | |
12083 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12084 | (const_int 0))) | |
12085 | (clobber (match_scratch:DI 3 ""))] | |
12086 | "TARGET_POWERPC64 && reload_completed" | |
12087 | [(set (match_dup 3) | |
12088 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
12089 | (match_dup 2))) | |
12090 | (set (match_dup 0) | |
12091 | (compare:CC (match_dup 3) | |
12092 | (const_int 0)))] | |
12093 | "") | |
f9562f27 | 12094 | |
1fd4e8c1 | 12095 | (define_insn "" |
9ebbca7d GK |
12096 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
12097 | (compare:CC | |
12098 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12099 | (const_int 0)) | |
12100 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
12101 | (const_int 0))) | |
12102 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
12103 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
12104 | (clobber (match_scratch:SI 3 "=&r,&r"))] | |
12105 | "! TARGET_POWERPC64" | |
12106 | "@ | |
12107 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2 | |
12108 | #" | |
12109 | [(set_attr "type" "compare") | |
12110 | (set_attr "length" "12,16")]) | |
12111 | ||
12112 | (define_split | |
12113 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
1fd4e8c1 | 12114 | (compare:CC |
9ebbca7d | 12115 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 12116 | (const_int 0)) |
9ebbca7d | 12117 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 12118 | (const_int 0))) |
9ebbca7d | 12119 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 12120 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d GK |
12121 | (clobber (match_scratch:SI 3 ""))] |
12122 | "! TARGET_POWERPC64 && reload_completed" | |
12123 | [(parallel [(set (match_dup 0) | |
12124 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
12125 | (clobber (match_dup 3))]) | |
12126 | (set (match_dup 4) | |
12127 | (compare:CC (match_dup 0) | |
12128 | (const_int 0)))] | |
12129 | "") | |
1fd4e8c1 | 12130 | |
f9562f27 | 12131 | (define_insn "" |
9ebbca7d | 12132 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
f9562f27 | 12133 | (compare:CC |
9ebbca7d | 12134 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12135 | (const_int 0)) |
9ebbca7d | 12136 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12137 | (const_int 0))) |
9ebbca7d | 12138 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 12139 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d | 12140 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 12141 | "TARGET_POWERPC64" |
9ebbca7d GK |
12142 | "@ |
12143 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2 | |
12144 | #" | |
f9562f27 | 12145 | [(set_attr "type" "compare") |
9ebbca7d GK |
12146 | (set_attr "length" "12,16")]) |
12147 | ||
12148 | (define_split | |
12149 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12150 | (compare:CC | |
12151 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12152 | (const_int 0)) | |
12153 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12154 | (const_int 0))) | |
12155 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12156 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
12157 | (clobber (match_scratch:DI 3 ""))] | |
12158 | "TARGET_POWERPC64 && reload_completed" | |
12159 | [(parallel [(set (match_dup 0) | |
12160 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
12161 | (clobber (match_dup 3))]) | |
12162 | (set (match_dup 4) | |
12163 | (compare:CC (match_dup 0) | |
12164 | (const_int 0)))] | |
12165 | "") | |
f9562f27 | 12166 | |
1fd4e8c1 | 12167 | (define_insn "" |
cd2b37d9 RK |
12168 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12169 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12170 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 12171 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 12172 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
12173 | "TARGET_POWER" |
12174 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 12175 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12176 | |
12177 | (define_insn "" | |
9ebbca7d | 12178 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12179 | (compare:CC |
9ebbca7d GK |
12180 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12181 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12182 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12183 | (const_int 0))) |
9ebbca7d | 12184 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12185 | "TARGET_POWER" |
9ebbca7d GK |
12186 | "@ |
12187 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12188 | #" | |
b19003d8 | 12189 | [(set_attr "type" "compare") |
9ebbca7d GK |
12190 | (set_attr "length" "12,16")]) |
12191 | ||
12192 | (define_split | |
12193 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12194 | (compare:CC | |
12195 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12196 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12197 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12198 | (const_int 0))) | |
12199 | (clobber (match_scratch:SI 4 ""))] | |
12200 | "TARGET_POWER && reload_completed" | |
12201 | [(set (match_dup 4) | |
12202 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) | |
12203 | (match_dup 3))) | |
12204 | (set (match_dup 0) | |
12205 | (compare:CC (match_dup 4) | |
12206 | (const_int 0)))] | |
12207 | "") | |
1fd4e8c1 RK |
12208 | |
12209 | (define_insn "" | |
9ebbca7d | 12210 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12211 | (compare:CC |
9ebbca7d GK |
12212 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12213 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12214 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12215 | (const_int 0))) |
9ebbca7d | 12216 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12217 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12218 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12219 | "TARGET_POWER" |
9ebbca7d GK |
12220 | "@ |
12221 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
12222 | #" | |
b19003d8 | 12223 | [(set_attr "type" "compare") |
9ebbca7d GK |
12224 | (set_attr "length" "12,16")]) |
12225 | ||
12226 | (define_split | |
12227 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12228 | (compare:CC | |
12229 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12230 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12231 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12232 | (const_int 0))) | |
12233 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12234 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12235 | (clobber (match_scratch:SI 4 ""))] | |
12236 | "TARGET_POWER && reload_completed" | |
12237 | [(parallel [(set (match_dup 0) | |
12238 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12239 | (clobber (match_dup 4))]) | |
12240 | (set (match_dup 5) | |
12241 | (compare:CC (match_dup 0) | |
12242 | (const_int 0)))] | |
12243 | "") | |
1fd4e8c1 RK |
12244 | |
12245 | (define_insn "" | |
cd2b37d9 RK |
12246 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12247 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12248 | (const_int 0))))] |
f9562f27 | 12249 | "! TARGET_POWERPC64" |
ca7f5001 | 12250 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 12251 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12252 | |
f9562f27 DE |
12253 | (define_insn "" |
12254 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12255 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12256 | (const_int 0))))] | |
12257 | "TARGET_POWERPC64" | |
12258 | "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63" | |
12259 | [(set_attr "length" "12")]) | |
12260 | ||
1fd4e8c1 | 12261 | (define_insn "" |
cd2b37d9 RK |
12262 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12263 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12264 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
12265 | "TARGET_POWER" |
12266 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12267 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12268 | |
12269 | (define_insn "" | |
cd2b37d9 RK |
12270 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12271 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12272 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 12273 | "! TARGET_POWERPC64" |
ca7f5001 | 12274 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 12275 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12276 | |
f9562f27 DE |
12277 | (define_insn "" |
12278 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12279 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12280 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
12281 | "TARGET_POWERPC64" | |
12282 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" | |
12283 | [(set_attr "length" "12")]) | |
12284 | ||
1fd4e8c1 | 12285 | (define_insn "" |
9ebbca7d | 12286 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12287 | (compare:CC |
9ebbca7d GK |
12288 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12289 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12290 | (const_int 0))) |
9ebbca7d | 12291 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12292 | (gtu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12293 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12294 | "@ |
12295 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
12296 | #" | |
b19003d8 | 12297 | [(set_attr "type" "compare") |
9ebbca7d GK |
12298 | (set_attr "length" "12,16")]) |
12299 | ||
12300 | (define_split | |
12301 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12302 | (compare:CC | |
12303 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12304 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12305 | (const_int 0))) | |
12306 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12307 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
12308 | "! TARGET_POWERPC64 && reload_completed" | |
12309 | [(set (match_dup 0) | |
12310 | (gtu:SI (match_dup 1) (match_dup 2))) | |
12311 | (set (match_dup 3) | |
12312 | (compare:CC (match_dup 0) | |
12313 | (const_int 0)))] | |
12314 | "") | |
1fd4e8c1 | 12315 | |
f9562f27 | 12316 | (define_insn "" |
9ebbca7d | 12317 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12318 | (compare:CC |
9ebbca7d GK |
12319 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12320 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12321 | (const_int 0))) |
9ebbca7d | 12322 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12323 | (gtu:DI (match_dup 1) (match_dup 2)))] |
12324 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12325 | "@ |
12326 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
12327 | #" | |
f9562f27 | 12328 | [(set_attr "type" "compare") |
9ebbca7d GK |
12329 | (set_attr "length" "12,16")]) |
12330 | ||
12331 | (define_split | |
12332 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12333 | (compare:CC | |
12334 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12335 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12336 | (const_int 0))) | |
12337 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12338 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
12339 | "TARGET_POWERPC64 && reload_completed" | |
12340 | [(set (match_dup 0) | |
12341 | (gtu:DI (match_dup 1) (match_dup 2))) | |
12342 | (set (match_dup 3) | |
12343 | (compare:CC (match_dup 0) | |
12344 | (const_int 0)))] | |
12345 | "") | |
f9562f27 | 12346 | |
1fd4e8c1 | 12347 | (define_insn "" |
19378cf8 MM |
12348 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12349 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12350 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
12351 | (match_operand:SI 3 "reg_or_short_operand" "r,rI"))) | |
12352 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 12353 | "! TARGET_POWERPC64" |
00751805 | 12354 | "@ |
ca7f5001 | 12355 | {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 |
ca7f5001 | 12356 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
19378cf8 | 12357 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 12358 | |
f9562f27 DE |
12359 | (define_insn "" |
12360 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12361 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12362 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
12363 | (match_operand:DI 3 "reg_or_short_operand" "r,rI"))) | |
12364 | (clobber (match_scratch:DI 4 "=&r,&r"))] | |
12365 | "TARGET_POWERPC64" | |
12366 | "@ | |
12367 | addic %4,%1,%k2\;addze %0,%3 | |
12368 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3" | |
12369 | [(set_attr "length" "8,12")]) | |
12370 | ||
1fd4e8c1 | 12371 | (define_insn "" |
9ebbca7d | 12372 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12373 | (compare:CC |
9ebbca7d GK |
12374 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12375 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
12376 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12377 | (const_int 0))) |
9ebbca7d | 12378 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12379 | "! TARGET_POWERPC64" |
00751805 | 12380 | "@ |
19378cf8 | 12381 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12382 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12383 | # | |
12384 | #" | |
b19003d8 | 12385 | [(set_attr "type" "compare") |
9ebbca7d GK |
12386 | (set_attr "length" "8,12,12,16")]) |
12387 | ||
12388 | (define_split | |
12389 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12390 | (compare:CC | |
12391 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12392 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12393 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12394 | (const_int 0))) | |
12395 | (clobber (match_scratch:SI 4 ""))] | |
12396 | "! TARGET_POWERPC64 && reload_completed" | |
12397 | [(set (match_dup 4) | |
12398 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
12399 | (match_dup 3))) | |
12400 | (set (match_dup 0) | |
12401 | (compare:CC (match_dup 4) | |
12402 | (const_int 0)))] | |
12403 | "") | |
1fd4e8c1 | 12404 | |
f9562f27 | 12405 | (define_insn "" |
9ebbca7d | 12406 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12407 | (compare:CC |
9ebbca7d GK |
12408 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12409 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
12410 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12411 | (const_int 0))) |
9ebbca7d | 12412 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
12413 | "TARGET_POWERPC64" |
12414 | "@ | |
12415 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
12416 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
12417 | # | |
12418 | #" | |
f9562f27 | 12419 | [(set_attr "type" "compare") |
9ebbca7d GK |
12420 | (set_attr "length" "8,12,12,16")]) |
12421 | ||
12422 | (define_split | |
12423 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12424 | (compare:CC | |
12425 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12426 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12427 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
12428 | (const_int 0))) | |
12429 | (clobber (match_scratch:DI 4 ""))] | |
12430 | "TARGET_POWERPC64 && reload_completed" | |
12431 | [(set (match_dup 4) | |
12432 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
12433 | (match_dup 3))) | |
12434 | (set (match_dup 0) | |
12435 | (compare:CC (match_dup 4) | |
12436 | (const_int 0)))] | |
12437 | "") | |
f9562f27 | 12438 | |
1fd4e8c1 | 12439 | (define_insn "" |
9ebbca7d | 12440 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12441 | (compare:CC |
9ebbca7d GK |
12442 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12443 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
12444 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12445 | (const_int 0))) |
9ebbca7d | 12446 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12447 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12448 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12449 | "! TARGET_POWERPC64" |
00751805 | 12450 | "@ |
ca7f5001 | 12451 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
12452 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
12453 | # | |
12454 | #" | |
b19003d8 | 12455 | [(set_attr "type" "compare") |
9ebbca7d GK |
12456 | (set_attr "length" "8,12,12,16")]) |
12457 | ||
12458 | (define_split | |
12459 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12460 | (compare:CC | |
12461 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12462 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12463 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12464 | (const_int 0))) | |
12465 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12466 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12467 | (clobber (match_scratch:SI 4 ""))] | |
12468 | "! TARGET_POWERPC64 && reload_completed" | |
12469 | [(parallel [(set (match_dup 0) | |
12470 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12471 | (clobber (match_dup 4))]) | |
12472 | (set (match_dup 5) | |
12473 | (compare:CC (match_dup 0) | |
12474 | (const_int 0)))] | |
12475 | "") | |
1fd4e8c1 | 12476 | |
f9562f27 | 12477 | (define_insn "" |
9ebbca7d | 12478 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12479 | (compare:CC |
9ebbca7d GK |
12480 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12481 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
12482 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12483 | (const_int 0))) |
9ebbca7d | 12484 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12485 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12486 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
12487 | "TARGET_POWERPC64" |
12488 | "@ | |
12489 | addic %4,%1,%k2\;addze. %0,%3 | |
9ebbca7d GK |
12490 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3 |
12491 | # | |
12492 | #" | |
f9562f27 | 12493 | [(set_attr "type" "compare") |
9ebbca7d GK |
12494 | (set_attr "length" "8,12,12,16")]) |
12495 | ||
12496 | (define_split | |
12497 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12498 | (compare:CC | |
12499 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12500 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12501 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
12502 | (const_int 0))) | |
12503 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12504 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12505 | (clobber (match_scratch:DI 4 ""))] | |
12506 | "TARGET_POWERPC64 && reload_completed" | |
12507 | [(parallel [(set (match_dup 0) | |
12508 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12509 | (clobber (match_dup 4))]) | |
12510 | (set (match_dup 5) | |
12511 | (compare:CC (match_dup 0) | |
12512 | (const_int 0)))] | |
12513 | "") | |
f9562f27 | 12514 | |
1fd4e8c1 | 12515 | (define_insn "" |
cd2b37d9 RK |
12516 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12517 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12518 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 12519 | "! TARGET_POWERPC64" |
ca7f5001 | 12520 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12521 | [(set_attr "length" "8")]) |
f9562f27 DE |
12522 | |
12523 | (define_insn "" | |
12524 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12525 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12526 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
12527 | "TARGET_POWERPC64" | |
12528 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" | |
12529 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
12530 | \f |
12531 | ;; Define both directions of branch and return. If we need a reload | |
12532 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
12533 | ;; register CC value to there. | |
12534 | ||
12535 | (define_insn "" | |
12536 | [(set (pc) | |
12537 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12538 | [(match_operand 2 | |
12539 | "cc_reg_operand" "x,?y") | |
12540 | (const_int 0)]) | |
12541 | (label_ref (match_operand 0 "" "")) | |
12542 | (pc)))] | |
12543 | "" | |
b19003d8 RK |
12544 | "* |
12545 | { | |
12a4e8c5 | 12546 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
12547 | }" |
12548 | [(set_attr "type" "branch")]) | |
12549 | ||
1fd4e8c1 RK |
12550 | (define_insn "" |
12551 | [(set (pc) | |
12552 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12553 | [(match_operand 1 | |
12554 | "cc_reg_operand" "x,?y") | |
12555 | (const_int 0)]) | |
12556 | (return) | |
12557 | (pc)))] | |
12558 | "direct_return ()" | |
12a4e8c5 GK |
12559 | "* |
12560 | { | |
12561 | return output_cbranch (operands[0], NULL, 0, insn); | |
12562 | }" | |
b7ff3d82 | 12563 | [(set_attr "type" "branch") |
39a10a29 | 12564 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
12565 | |
12566 | (define_insn "" | |
12567 | [(set (pc) | |
12568 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12569 | [(match_operand 2 | |
12570 | "cc_reg_operand" "x,?y") | |
12571 | (const_int 0)]) | |
12572 | (pc) | |
12573 | (label_ref (match_operand 0 "" ""))))] | |
12574 | "" | |
b19003d8 RK |
12575 | "* |
12576 | { | |
12a4e8c5 | 12577 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
12578 | }" |
12579 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12580 | |
12581 | (define_insn "" | |
12582 | [(set (pc) | |
12583 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12584 | [(match_operand 1 | |
12585 | "cc_reg_operand" "x,?y") | |
12586 | (const_int 0)]) | |
12587 | (pc) | |
12588 | (return)))] | |
12589 | "direct_return ()" | |
12a4e8c5 GK |
12590 | "* |
12591 | { | |
12592 | return output_cbranch (operands[0], NULL, 1, insn); | |
12593 | }" | |
b7ff3d82 | 12594 | [(set_attr "type" "branch") |
39a10a29 GK |
12595 | (set_attr "length" "4")]) |
12596 | ||
12597 | ;; Logic on condition register values. | |
12598 | ||
12599 | ; This pattern matches things like | |
12600 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
12601 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
12602 | ; (const_int 1))) | |
12603 | ; which are generated by the branch logic. | |
12604 | ||
12605 | (define_insn "" | |
12606 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12607 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" | |
12608 | [(match_operator:SI 2 | |
12609 | "branch_positive_comparison_operator" | |
12610 | [(match_operand 3 | |
12611 | "cc_reg_operand" "y") | |
12612 | (const_int 0)]) | |
12613 | (match_operator:SI 4 | |
12614 | "branch_positive_comparison_operator" | |
12615 | [(match_operand 5 | |
12616 | "cc_reg_operand" "y") | |
12617 | (const_int 0)])]) | |
12618 | (const_int 1)))] | |
12619 | "" | |
12620 | "cr%q1 %E0,%j2,%j4" | |
12621 | [(set_attr "type" "cr_logical")]) | |
12622 | ||
12623 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
12624 | ; Because ~1 has all but the low bit set. | |
12625 | (define_insn "" | |
12626 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12627 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" | |
12628 | [(not:SI (match_operator:SI 2 | |
12629 | "branch_positive_comparison_operator" | |
12630 | [(match_operand 3 | |
12631 | "cc_reg_operand" "y") | |
12632 | (const_int 0)])) | |
12633 | (match_operator:SI 4 | |
12634 | "branch_positive_comparison_operator" | |
12635 | [(match_operand 5 | |
12636 | "cc_reg_operand" "y") | |
12637 | (const_int 0)])]) | |
12638 | (const_int -1)))] | |
12639 | "" | |
12640 | "cr%q1 %E0,%j2,%j4" | |
12641 | [(set_attr "type" "cr_logical")]) | |
12642 | ||
12643 | (define_insn "" | |
12644 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
6c873122 | 12645 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 12646 | "branch_positive_comparison_operator" |
6c873122 | 12647 | [(match_operand 2 |
39a10a29 GK |
12648 | "cc_reg_operand" "y") |
12649 | (const_int 0)]) | |
12650 | (const_int 0)))] | |
12651 | "" | |
251b3667 | 12652 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
39a10a29 GK |
12653 | [(set_attr "type" "cr_logical")]) |
12654 | ||
12655 | ;; If we are comparing the result of two comparisons, this can be done | |
12656 | ;; using creqv or crxor. | |
12657 | ||
12658 | (define_insn_and_split "" | |
12659 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12660 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
12661 | [(match_operand 2 "cc_reg_operand" "y") | |
12662 | (const_int 0)]) | |
12663 | (match_operator 3 "branch_comparison_operator" | |
12664 | [(match_operand 4 "cc_reg_operand" "y") | |
12665 | (const_int 0)])))] | |
12666 | "" | |
12667 | "#" | |
12668 | "" | |
12669 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
12670 | (match_dup 5)))] | |
12671 | " | |
12672 | { | |
12673 | int positive_1, positive_2; | |
12674 | ||
12675 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
12676 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
12677 | ||
12678 | if (! positive_1) | |
12679 | operands[1] = gen_rtx (SImode, | |
12680 | rs6000_reverse_condition (GET_MODE (operands[2]), | |
12681 | GET_CODE (operands[1])), | |
12682 | operands[2]); | |
12683 | else if (GET_MODE (operands[1]) != SImode) | |
12684 | operands[1] = gen_rtx (SImode, | |
12685 | GET_CODE (operands[1]), | |
12686 | operands[2]); | |
12687 | ||
12688 | if (! positive_2) | |
12689 | operands[3] = gen_rtx (SImode, | |
12690 | rs6000_reverse_condition (GET_MODE (operands[4]), | |
12691 | GET_CODE (operands[3])), | |
12692 | operands[4]); | |
12693 | else if (GET_MODE (operands[3]) != SImode) | |
12694 | operands[3] = gen_rtx (SImode, | |
12695 | GET_CODE (operands[3]), | |
12696 | operands[4]); | |
12697 | ||
12698 | if (positive_1 == positive_2) | |
251b3667 DE |
12699 | { |
12700 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
12701 | operands[5] = constm1_rtx; | |
12702 | } | |
12703 | else | |
12704 | { | |
12705 | operands[5] = const1_rtx; | |
12706 | } | |
39a10a29 | 12707 | }") |
1fd4e8c1 RK |
12708 | |
12709 | ;; Unconditional branch and return. | |
12710 | ||
12711 | (define_insn "jump" | |
12712 | [(set (pc) | |
12713 | (label_ref (match_operand 0 "" "")))] | |
12714 | "" | |
b7ff3d82 DE |
12715 | "b %l0" |
12716 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12717 | |
12718 | (define_insn "return" | |
12719 | [(return)] | |
12720 | "direct_return ()" | |
324e52cc TG |
12721 | "{br|blr}" |
12722 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 12723 | |
0ad91047 DE |
12724 | (define_expand "indirect_jump" |
12725 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 12726 | "" |
0ad91047 DE |
12727 | " |
12728 | { | |
12729 | if (TARGET_32BIT) | |
12730 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
12731 | else | |
12732 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
12733 | DONE; | |
12734 | }") | |
12735 | ||
12736 | (define_insn "indirect_jumpsi" | |
cccf3bdc | 12737 | [(set (pc) (match_operand:SI 0 "register_operand" "cl"))] |
0ad91047 | 12738 | "TARGET_32BIT" |
cccf3bdc | 12739 | "b%T0" |
324e52cc | 12740 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 12741 | |
0ad91047 | 12742 | (define_insn "indirect_jumpdi" |
cccf3bdc | 12743 | [(set (pc) (match_operand:DI 0 "register_operand" "cl"))] |
0ad91047 | 12744 | "TARGET_64BIT" |
cccf3bdc | 12745 | "b%T0" |
266eb58a DE |
12746 | [(set_attr "type" "jmpreg")]) |
12747 | ||
1fd4e8c1 RK |
12748 | ;; Table jump for switch statements: |
12749 | (define_expand "tablejump" | |
e6ca2c17 DE |
12750 | [(use (match_operand 0 "" "")) |
12751 | (use (label_ref (match_operand 1 "" "")))] | |
12752 | "" | |
12753 | " | |
12754 | { | |
12755 | if (TARGET_32BIT) | |
12756 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
12757 | else | |
12758 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
12759 | DONE; | |
12760 | }") | |
12761 | ||
12762 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
12763 | [(set (match_dup 3) |
12764 | (plus:SI (match_operand:SI 0 "" "") | |
12765 | (match_dup 2))) | |
12766 | (parallel [(set (pc) (match_dup 3)) | |
12767 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 12768 | "TARGET_32BIT" |
1fd4e8c1 RK |
12769 | " |
12770 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 12771 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
12772 | operands[3] = gen_reg_rtx (SImode); |
12773 | }") | |
12774 | ||
e6ca2c17 | 12775 | (define_expand "tablejumpdi" |
9ebbca7d GK |
12776 | [(set (match_dup 4) |
12777 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) | |
12778 | (set (match_dup 3) | |
12779 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
12780 | (match_dup 2))) |
12781 | (parallel [(set (pc) (match_dup 3)) | |
12782 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 12783 | "TARGET_64BIT" |
e6ca2c17 | 12784 | " |
9ebbca7d | 12785 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 12786 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 12787 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
12788 | }") |
12789 | ||
1fd4e8c1 RK |
12790 | (define_insn "" |
12791 | [(set (pc) | |
cccf3bdc | 12792 | (match_operand:SI 0 "register_operand" "cl")) |
1fd4e8c1 | 12793 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 12794 | "TARGET_32BIT" |
cccf3bdc | 12795 | "b%T0" |
a6845123 | 12796 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 12797 | |
266eb58a DE |
12798 | (define_insn "" |
12799 | [(set (pc) | |
cccf3bdc | 12800 | (match_operand:DI 0 "register_operand" "cl")) |
266eb58a | 12801 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 12802 | "TARGET_64BIT" |
cccf3bdc | 12803 | "b%T0" |
266eb58a DE |
12804 | [(set_attr "type" "jmpreg")]) |
12805 | ||
1fd4e8c1 RK |
12806 | (define_insn "nop" |
12807 | [(const_int 0)] | |
12808 | "" | |
ca7f5001 | 12809 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 12810 | \f |
7e69e155 | 12811 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
12812 | ;; so loop.c knows what to generate. |
12813 | ||
5527bf14 RH |
12814 | (define_expand "doloop_end" |
12815 | [(use (match_operand 0 "" "")) ; loop pseudo | |
12816 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
12817 | (use (match_operand 2 "" "")) ; max iterations | |
12818 | (use (match_operand 3 "" "")) ; loop level | |
12819 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
12820 | "" |
12821 | " | |
12822 | { | |
5527bf14 RH |
12823 | /* Only use this on innermost loops. */ |
12824 | if (INTVAL (operands[3]) > 1) | |
12825 | FAIL; | |
0ad91047 | 12826 | if (TARGET_POWERPC64) |
5527bf14 RH |
12827 | { |
12828 | if (GET_MODE (operands[0]) != DImode) | |
12829 | FAIL; | |
12830 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
12831 | } | |
0ad91047 | 12832 | else |
5527bf14 RH |
12833 | { |
12834 | if (GET_MODE (operands[0]) != SImode) | |
12835 | FAIL; | |
12836 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
12837 | } | |
0ad91047 DE |
12838 | DONE; |
12839 | }") | |
12840 | ||
12841 | (define_expand "ctrsi" | |
3cb999d8 DE |
12842 | [(parallel [(set (pc) |
12843 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
12844 | (const_int 1)) | |
12845 | (label_ref (match_operand 1 "" "")) | |
12846 | (pc))) | |
b6c9286a MM |
12847 | (set (match_dup 0) |
12848 | (plus:SI (match_dup 0) | |
12849 | (const_int -1))) | |
5f81043f RK |
12850 | (clobber (match_scratch:CC 2 "")) |
12851 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
12852 | "! TARGET_POWERPC64" |
12853 | "") | |
12854 | ||
12855 | (define_expand "ctrdi" | |
3cb999d8 DE |
12856 | [(parallel [(set (pc) |
12857 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
12858 | (const_int 1)) | |
12859 | (label_ref (match_operand 1 "" "")) | |
12860 | (pc))) | |
0ad91047 DE |
12861 | (set (match_dup 0) |
12862 | (plus:DI (match_dup 0) | |
12863 | (const_int -1))) | |
12864 | (clobber (match_scratch:CC 2 "")) | |
12865 | (clobber (match_scratch:DI 3 ""))])] | |
12866 | "TARGET_POWERPC64" | |
c225ba7b RK |
12867 | "") |
12868 | ||
1fd4e8c1 RK |
12869 | ;; We need to be able to do this for any operand, including MEM, or we |
12870 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 12871 | ;; JUMP_INSNs. |
0ad91047 | 12872 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
12873 | ;; label MUST be operand 0. |
12874 | ||
0ad91047 | 12875 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 12876 | [(set (pc) |
5f81043f | 12877 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 12878 | (const_int 1)) |
a6845123 | 12879 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12880 | (pc))) |
5f81043f RK |
12881 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12882 | (plus:SI (match_dup 1) | |
12883 | (const_int -1))) | |
1fd4e8c1 RK |
12884 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
12885 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12886 | "! TARGET_POWERPC64" |
b19003d8 RK |
12887 | "* |
12888 | { | |
af87a13e | 12889 | if (which_alternative != 0) |
b19003d8 RK |
12890 | return \"#\"; |
12891 | else if (get_attr_length (insn) == 8) | |
a6845123 | 12892 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 12893 | else |
c81bebd7 | 12894 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 12895 | }" |
baf97f86 RK |
12896 | [(set_attr "type" "branch") |
12897 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 12898 | |
0ad91047 | 12899 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
12900 | [(set (pc) |
12901 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
12902 | (const_int 1)) | |
12903 | (pc) | |
12904 | (label_ref (match_operand 0 "" "")))) | |
12905 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
12906 | (plus:SI (match_dup 1) | |
12907 | (const_int -1))) | |
12908 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12909 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
12910 | "! TARGET_POWERPC64" |
12911 | "* | |
12912 | { | |
12913 | if (which_alternative != 0) | |
12914 | return \"#\"; | |
12915 | else if (get_attr_length (insn) == 8) | |
12916 | return \"bdz %l0\"; | |
12917 | else | |
12918 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
12919 | }" | |
12920 | [(set_attr "type" "branch") | |
12921 | (set_attr "length" "*,12,16")]) | |
12922 | ||
12923 | (define_insn "*ctrdi_internal1" | |
12924 | [(set (pc) | |
12925 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12926 | (const_int 1)) | |
12927 | (label_ref (match_operand 0 "" "")) | |
12928 | (pc))) | |
12929 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12930 | (plus:DI (match_dup 1) | |
12931 | (const_int -1))) | |
12932 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12933 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12934 | "TARGET_POWERPC64" | |
12935 | "* | |
12936 | { | |
12937 | if (which_alternative != 0) | |
12938 | return \"#\"; | |
12939 | else if (get_attr_length (insn) == 8) | |
12940 | return \"{bdn|bdnz} %l0\"; | |
12941 | else | |
12942 | return \"bdz %$+8\;b %l0\"; | |
12943 | }" | |
12944 | [(set_attr "type" "branch") | |
12945 | (set_attr "length" "*,12,16")]) | |
12946 | ||
12947 | (define_insn "*ctrdi_internal2" | |
12948 | [(set (pc) | |
12949 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12950 | (const_int 1)) | |
12951 | (pc) | |
12952 | (label_ref (match_operand 0 "" "")))) | |
12953 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12954 | (plus:DI (match_dup 1) | |
12955 | (const_int -1))) | |
12956 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12957 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12958 | "TARGET_POWERPC64" | |
5f81043f RK |
12959 | "* |
12960 | { | |
12961 | if (which_alternative != 0) | |
12962 | return \"#\"; | |
12963 | else if (get_attr_length (insn) == 8) | |
12964 | return \"bdz %l0\"; | |
12965 | else | |
c81bebd7 | 12966 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
12967 | }" |
12968 | [(set_attr "type" "branch") | |
12969 | (set_attr "length" "*,12,16")]) | |
12970 | ||
c225ba7b | 12971 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
12972 | |
12973 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 12974 | [(set (pc) |
5f81043f | 12975 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 12976 | (const_int 0)) |
a6845123 | 12977 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12978 | (pc))) |
5f81043f RK |
12979 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12980 | (plus:SI (match_dup 1) | |
12981 | (const_int -1))) | |
1fd4e8c1 RK |
12982 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
12983 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12984 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
12985 | "* |
12986 | { | |
af87a13e | 12987 | if (which_alternative != 0) |
b19003d8 RK |
12988 | return \"#\"; |
12989 | else if (get_attr_length (insn) == 8) | |
a6845123 | 12990 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 12991 | else |
c81bebd7 | 12992 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 12993 | }" |
baf97f86 RK |
12994 | [(set_attr "type" "branch") |
12995 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 12996 | |
0ad91047 | 12997 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 12998 | [(set (pc) |
5f81043f RK |
12999 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
13000 | (const_int 0)) | |
13001 | (pc) | |
13002 | (label_ref (match_operand 0 "" "")))) | |
13003 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13004 | (plus:SI (match_dup 1) | |
13005 | (const_int -1))) | |
13006 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
13007 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13008 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
13009 | "* |
13010 | { | |
13011 | if (which_alternative != 0) | |
13012 | return \"#\"; | |
13013 | else if (get_attr_length (insn) == 8) | |
13014 | return \"bdz %l0\"; | |
13015 | else | |
c81bebd7 | 13016 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
13017 | }" |
13018 | [(set_attr "type" "branch") | |
13019 | (set_attr "length" "*,12,16")]) | |
13020 | ||
0ad91047 DE |
13021 | (define_insn "*ctrdi_internal3" |
13022 | [(set (pc) | |
13023 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
13024 | (const_int 0)) | |
13025 | (label_ref (match_operand 0 "" "")) | |
13026 | (pc))) | |
13027 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
13028 | (plus:DI (match_dup 1) | |
13029 | (const_int -1))) | |
13030 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
13031 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
13032 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
13033 | "* | |
13034 | { | |
13035 | if (which_alternative != 0) | |
13036 | return \"#\"; | |
13037 | else if (get_attr_length (insn) == 8) | |
13038 | return \"{bdn|bdnz} %l0\"; | |
13039 | else | |
13040 | return \"bdz %$+8\;b %l0\"; | |
13041 | }" | |
13042 | [(set_attr "type" "branch") | |
13043 | (set_attr "length" "*,12,16")]) | |
13044 | ||
13045 | (define_insn "*ctrdi_internal4" | |
13046 | [(set (pc) | |
13047 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
13048 | (const_int 0)) | |
13049 | (pc) | |
13050 | (label_ref (match_operand 0 "" "")))) | |
13051 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
13052 | (plus:DI (match_dup 1) | |
13053 | (const_int -1))) | |
13054 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
13055 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
13056 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
13057 | "* | |
13058 | { | |
13059 | if (which_alternative != 0) | |
13060 | return \"#\"; | |
13061 | else if (get_attr_length (insn) == 8) | |
13062 | return \"bdz %l0\"; | |
13063 | else | |
13064 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
13065 | }" | |
13066 | [(set_attr "type" "branch") | |
13067 | (set_attr "length" "*,12,16")]) | |
13068 | ||
13069 | ;; Similar but use EQ | |
13070 | ||
13071 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
13072 | [(set (pc) |
13073 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 13074 | (const_int 1)) |
a6845123 | 13075 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13076 | (pc))) |
5f81043f RK |
13077 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13078 | (plus:SI (match_dup 1) | |
13079 | (const_int -1))) | |
1fd4e8c1 RK |
13080 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13081 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13082 | "! TARGET_POWERPC64" |
b19003d8 RK |
13083 | "* |
13084 | { | |
af87a13e | 13085 | if (which_alternative != 0) |
b19003d8 RK |
13086 | return \"#\"; |
13087 | else if (get_attr_length (insn) == 8) | |
a6845123 | 13088 | return \"bdz %l0\"; |
b19003d8 | 13089 | else |
c81bebd7 | 13090 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
b19003d8 | 13091 | }" |
baf97f86 RK |
13092 | [(set_attr "type" "branch") |
13093 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 13094 | |
0ad91047 | 13095 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
13096 | [(set (pc) |
13097 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
13098 | (const_int 1)) | |
13099 | (pc) | |
13100 | (label_ref (match_operand 0 "" "")))) | |
13101 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13102 | (plus:SI (match_dup 1) | |
13103 | (const_int -1))) | |
13104 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13105 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
13106 | "! TARGET_POWERPC64" |
13107 | "* | |
13108 | { | |
13109 | if (which_alternative != 0) | |
13110 | return \"#\"; | |
13111 | else if (get_attr_length (insn) == 8) | |
13112 | return \"{bdn|bdnz} %l0\"; | |
13113 | else | |
13114 | return \"bdz %$+8\;b %l0\"; | |
13115 | }" | |
13116 | [(set_attr "type" "branch") | |
13117 | (set_attr "length" "*,12,16")]) | |
13118 | ||
13119 | (define_insn "*ctrdi_internal5" | |
13120 | [(set (pc) | |
13121 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
13122 | (const_int 1)) | |
13123 | (label_ref (match_operand 0 "" "")) | |
13124 | (pc))) | |
13125 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
13126 | (plus:DI (match_dup 1) | |
13127 | (const_int -1))) | |
13128 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13129 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
13130 | "TARGET_POWERPC64" | |
13131 | "* | |
13132 | { | |
13133 | if (which_alternative != 0) | |
13134 | return \"#\"; | |
13135 | else if (get_attr_length (insn) == 8) | |
13136 | return \"bdz %l0\"; | |
13137 | else | |
13138 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
13139 | }" | |
13140 | [(set_attr "type" "branch") | |
13141 | (set_attr "length" "*,12,16")]) | |
13142 | ||
13143 | (define_insn "*ctrdi_internal6" | |
13144 | [(set (pc) | |
13145 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
13146 | (const_int 1)) | |
13147 | (pc) | |
13148 | (label_ref (match_operand 0 "" "")))) | |
13149 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
13150 | (plus:DI (match_dup 1) | |
13151 | (const_int -1))) | |
13152 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13153 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
13154 | "TARGET_POWERPC64" | |
5f81043f RK |
13155 | "* |
13156 | { | |
13157 | if (which_alternative != 0) | |
13158 | return \"#\"; | |
13159 | else if (get_attr_length (insn) == 8) | |
13160 | return \"{bdn|bdnz} %l0\"; | |
13161 | else | |
c81bebd7 | 13162 | return \"bdz %$+8\;b %l0\"; |
5f81043f RK |
13163 | }" |
13164 | [(set_attr "type" "branch") | |
13165 | (set_attr "length" "*,12,16")]) | |
13166 | ||
0ad91047 DE |
13167 | ;; Now the splitters if we could not allocate the CTR register |
13168 | ||
1fd4e8c1 RK |
13169 | (define_split |
13170 | [(set (pc) | |
13171 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13172 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13173 | (const_int 1)]) |
13174 | (match_operand 5 "" "") | |
13175 | (match_operand 6 "" ""))) | |
cd2b37d9 | 13176 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
13177 | (plus:SI (match_dup 1) |
13178 | (const_int -1))) | |
1fd4e8c1 RK |
13179 | (clobber (match_scratch:CC 3 "")) |
13180 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 13181 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 13182 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13183 | (compare:CC (plus:SI (match_dup 1) |
13184 | (const_int -1)) | |
1fd4e8c1 | 13185 | (const_int 0))) |
5f81043f RK |
13186 | (set (match_dup 0) |
13187 | (plus:SI (match_dup 1) | |
13188 | (const_int -1)))]) | |
13189 | (set (pc) (if_then_else (match_dup 7) | |
13190 | (match_dup 5) | |
13191 | (match_dup 6)))] | |
1fd4e8c1 RK |
13192 | " |
13193 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13194 | const0_rtx); }") | |
13195 | ||
13196 | (define_split | |
13197 | [(set (pc) | |
13198 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13199 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13200 | (const_int 1)]) |
13201 | (match_operand 5 "" "") | |
13202 | (match_operand 6 "" ""))) | |
9ebbca7d | 13203 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
13204 | (plus:SI (match_dup 1) (const_int -1))) |
13205 | (clobber (match_scratch:CC 3 "")) | |
13206 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
13207 | "! TARGET_POWERPC64 && reload_completed |
13208 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 13209 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13210 | (compare:CC (plus:SI (match_dup 1) |
13211 | (const_int -1)) | |
1fd4e8c1 | 13212 | (const_int 0))) |
5f81043f RK |
13213 | (set (match_dup 4) |
13214 | (plus:SI (match_dup 1) | |
13215 | (const_int -1)))]) | |
13216 | (set (match_dup 0) | |
13217 | (match_dup 4)) | |
13218 | (set (pc) (if_then_else (match_dup 7) | |
13219 | (match_dup 5) | |
13220 | (match_dup 6)))] | |
1fd4e8c1 RK |
13221 | " |
13222 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13223 | const0_rtx); }") | |
0ad91047 DE |
13224 | (define_split |
13225 | [(set (pc) | |
13226 | (if_then_else (match_operator 2 "comparison_operator" | |
13227 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13228 | (const_int 1)]) | |
13229 | (match_operand 5 "" "") | |
13230 | (match_operand 6 "" ""))) | |
13231 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13232 | (plus:DI (match_dup 1) | |
13233 | (const_int -1))) | |
13234 | (clobber (match_scratch:CC 3 "")) | |
13235 | (clobber (match_scratch:DI 4 ""))] | |
13236 | "TARGET_POWERPC64 && reload_completed" | |
13237 | [(parallel [(set (match_dup 3) | |
13238 | (compare:CC (plus:DI (match_dup 1) | |
13239 | (const_int -1)) | |
13240 | (const_int 0))) | |
13241 | (set (match_dup 0) | |
13242 | (plus:DI (match_dup 1) | |
13243 | (const_int -1)))]) | |
13244 | (set (pc) (if_then_else (match_dup 7) | |
13245 | (match_dup 5) | |
13246 | (match_dup 6)))] | |
13247 | " | |
13248 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13249 | const0_rtx); }") | |
13250 | ||
13251 | (define_split | |
13252 | [(set (pc) | |
13253 | (if_then_else (match_operator 2 "comparison_operator" | |
13254 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13255 | (const_int 1)]) | |
13256 | (match_operand 5 "" "") | |
13257 | (match_operand 6 "" ""))) | |
9ebbca7d | 13258 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
13259 | (plus:DI (match_dup 1) (const_int -1))) |
13260 | (clobber (match_scratch:CC 3 "")) | |
13261 | (clobber (match_scratch:DI 4 ""))] | |
13262 | "TARGET_POWERPC64 && reload_completed | |
13263 | && ! gpc_reg_operand (operands[0], DImode)" | |
13264 | [(parallel [(set (match_dup 3) | |
13265 | (compare:CC (plus:DI (match_dup 1) | |
13266 | (const_int -1)) | |
13267 | (const_int 0))) | |
13268 | (set (match_dup 4) | |
13269 | (plus:DI (match_dup 1) | |
13270 | (const_int -1)))]) | |
13271 | (set (match_dup 0) | |
13272 | (match_dup 4)) | |
13273 | (set (pc) (if_then_else (match_dup 7) | |
13274 | (match_dup 5) | |
13275 | (match_dup 6)))] | |
13276 | " | |
13277 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13278 | const0_rtx); }") | |
e0cd0770 JC |
13279 | \f |
13280 | (define_insn "trap" | |
13281 | [(trap_if (const_int 1) (const_int 0))] | |
13282 | "" | |
13283 | "{t 31,0,0|trap}") | |
13284 | ||
13285 | (define_expand "conditional_trap" | |
13286 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13287 | [(match_dup 2) (match_dup 3)]) | |
13288 | (match_operand 1 "const_int_operand" ""))] | |
13289 | "" | |
13290 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
13291 | operands[2] = rs6000_compare_op0; | |
13292 | operands[3] = rs6000_compare_op1;") | |
13293 | ||
13294 | (define_insn "" | |
13295 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13296 | [(match_operand:SI 1 "register_operand" "r") | |
13297 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
13298 | (const_int 0))] | |
13299 | "" | |
a157febd GK |
13300 | "{t|tw}%V0%I2 %1,%2") |
13301 | ||
13302 | (define_insn "" | |
13303 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13304 | [(match_operand:DI 1 "register_operand" "r") | |
13305 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
13306 | (const_int 0))] | |
13307 | "TARGET_POWERPC64" | |
13308 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
13309 | \f |
13310 | ;; Insns related to generating the function prologue and epilogue. | |
13311 | ||
13312 | (define_expand "prologue" | |
13313 | [(use (const_int 0))] | |
13314 | "TARGET_SCHED_PROLOG" | |
13315 | " | |
13316 | { | |
13317 | rs6000_emit_prologue (); | |
13318 | DONE; | |
13319 | }") | |
13320 | ||
13321 | (define_insn "movesi_from_cr" | |
13322 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
13323 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) | |
13324 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))] | |
13325 | "" | |
13326 | "mfcr %0") | |
13327 | ||
13328 | (define_insn "*stmw" | |
13329 | [(match_parallel 0 "stmw_operation" | |
13330 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
13331 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
13332 | "TARGET_MULTIPLE" | |
13333 | "{stm|stmw} %2,%1") | |
13334 | ||
13335 | (define_insn "*save_fpregs_si" | |
13336 | [(match_parallel 0 "any_operand" | |
13337 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
13338 | (use (match_operand:SI 2 "call_operand" "s")) | |
13339 | (set (match_operand:DF 3 "memory_operand" "=m") | |
13340 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
13341 | "TARGET_32BIT" | |
13342 | "bl %z2") | |
13343 | ||
13344 | (define_insn "*save_fpregs_di" | |
13345 | [(match_parallel 0 "any_operand" | |
13346 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
13347 | (use (match_operand:DI 2 "call_operand" "s")) | |
13348 | (set (match_operand:DF 3 "memory_operand" "=m") | |
13349 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
13350 | "TARGET_64BIT" | |
13351 | "bl %z2") | |
13352 | ||
13353 | ; These are to explain that changes to the stack pointer should | |
13354 | ; not be moved over stores to stack memory. | |
13355 | (define_insn "stack_tie" | |
13356 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
13357 | (unspec:BLK [(match_dup 0)] 5))] | |
13358 | "" | |
13359 | "" | |
13360 | [(set_attr "length" "0")]) | |
13361 | ||
13362 | ||
13363 | (define_expand "epilogue" | |
13364 | [(use (const_int 0))] | |
13365 | "TARGET_SCHED_PROLOG" | |
13366 | " | |
13367 | { | |
13368 | rs6000_emit_epilogue (FALSE); | |
13369 | DONE; | |
13370 | }") | |
13371 | ||
13372 | ; On some processors, doing the mtcrf one CC register at a time is | |
13373 | ; faster (like on the 604e). On others, doing them all at once is | |
13374 | ; faster; for instance, on the 601 and 750. | |
13375 | ||
13376 | (define_expand "movsi_to_cr_one" | |
13377 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
13378 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
13379 | (match_dup 2)] 20))] | |
13380 | "" | |
13381 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
13382 | ||
13383 | (define_insn "*movsi_to_cr" | |
13384 | [(match_parallel 0 "mtcrf_operation" | |
e35b9579 GK |
13385 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") |
13386 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
13387 | (match_operand 3 "immediate_operand" "n")] | |
9ebbca7d GK |
13388 | 20))])] |
13389 | "" | |
e35b9579 GK |
13390 | "* |
13391 | { | |
13392 | int mask = 0; | |
13393 | int i; | |
13394 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
13395 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
13396 | operands[4] = GEN_INT (mask); | |
13397 | return \"mtcrf %4,%2\"; | |
13398 | }") | |
9ebbca7d GK |
13399 | |
13400 | (define_insn "" | |
13401 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
13402 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
13403 | (match_operand 2 "immediate_operand" "n")] 20))] | |
13404 | "GET_CODE (operands[0]) == REG | |
13405 | && CR_REGNO_P (REGNO (operands[0])) | |
13406 | && GET_CODE (operands[2]) == CONST_INT | |
13407 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
13408 | "mtcrf %R0,%1") | |
13409 | ||
13410 | ; The load-multiple instructions have similar properties. | |
13411 | ; Note that "load_multiple" is a name known to the machine-independent | |
13412 | ; code that actually corresponds to the powerpc load-string. | |
13413 | ||
13414 | (define_insn "*lmw" | |
13415 | [(match_parallel 0 "lmw_operation" | |
13416 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
13417 | (match_operand:SI 2 "memory_operand" "m"))])] | |
13418 | "TARGET_MULTIPLE" | |
13419 | "{lm|lmw} %1,%2") | |
13420 | ||
13421 | (define_insn "*return_internal_si" | |
e35b9579 GK |
13422 | [(return) |
13423 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 13424 | "TARGET_32BIT" |
cccf3bdc | 13425 | "b%T0" |
9ebbca7d GK |
13426 | [(set_attr "type" "jmpreg")]) |
13427 | ||
13428 | (define_insn "*return_internal_di" | |
e35b9579 GK |
13429 | [(return) |
13430 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 13431 | "TARGET_64BIT" |
cccf3bdc | 13432 | "b%T0" |
9ebbca7d GK |
13433 | [(set_attr "type" "jmpreg")]) |
13434 | ||
13435 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
13436 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
13437 | ||
13438 | (define_insn "*return_and_restore_fpregs_si" | |
13439 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
13440 | [(return) |
13441 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
13442 | (use (match_operand:SI 2 "call_operand" "s")) |
13443 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
13444 | (match_operand:DF 4 "memory_operand" "m"))])] | |
13445 | "TARGET_32BIT" | |
13446 | "b %z2") | |
13447 | ||
13448 | (define_insn "*return_and_restore_fpregs_di" | |
13449 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
13450 | [(return) |
13451 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
13452 | (use (match_operand:DI 2 "call_operand" "s")) |
13453 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
13454 | (match_operand:DF 4 "memory_operand" "m"))])] | |
13455 | "TARGET_64BIT" | |
13456 | "b %z2") | |
13457 | ||
83720594 RH |
13458 | ; This is used in compiling the unwind routines. |
13459 | (define_expand "eh_return" | |
13460 | [(use (match_operand 0 "general_operand" "")) | |
13461 | (use (match_operand 1 "general_operand" ""))] | |
9ebbca7d GK |
13462 | "" |
13463 | " | |
13464 | { | |
3553b09d | 13465 | #if TARGET_AIX |
83720594 | 13466 | rs6000_emit_eh_toc_restore (operands[0]); |
3553b09d | 13467 | #endif |
83720594 RH |
13468 | if (TARGET_32BIT) |
13469 | emit_insn (gen_eh_set_lr_si (operands[1])); | |
9ebbca7d | 13470 | else |
83720594 RH |
13471 | emit_insn (gen_eh_set_lr_di (operands[1])); |
13472 | emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]); | |
9ebbca7d GK |
13473 | DONE; |
13474 | }") | |
13475 | ||
83720594 RH |
13476 | ; We can't expand this before we know where the link register is stored. |
13477 | (define_insn "eh_set_lr_si" | |
13478 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9) | |
13479 | (clobber (match_scratch:SI 1 "=&r"))] | |
13480 | "TARGET_32BIT" | |
13481 | "#") | |
13482 | ||
13483 | (define_insn "eh_set_lr_di" | |
13484 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9) | |
13485 | (clobber (match_scratch:DI 1 "=&r"))] | |
13486 | "TARGET_64BIT" | |
13487 | "#") | |
9ebbca7d GK |
13488 | |
13489 | (define_split | |
83720594 RH |
13490 | [(unspec_volatile [(match_operand 0 "register_operand" "")] 9) |
13491 | (clobber (match_scratch 1 ""))] | |
13492 | "reload_completed" | |
13493 | [(const_int 0)] | |
9ebbca7d GK |
13494 | " |
13495 | { | |
83720594 | 13496 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d | 13497 | |
83720594 RH |
13498 | if (info->lr_save_p) |
13499 | { | |
13500 | rtx frame_rtx = stack_pointer_rtx; | |
13501 | int sp_offset = 0; | |
13502 | rtx tmp; | |
9ebbca7d | 13503 | |
83720594 RH |
13504 | if (frame_pointer_needed |
13505 | || current_function_calls_alloca | |
13506 | || info->total_size > 32767) | |
13507 | { | |
13508 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
13509 | frame_rtx = operands[1]; | |
13510 | } | |
13511 | else if (info->push_p) | |
13512 | sp_offset = info->total_size; | |
9ebbca7d | 13513 | |
83720594 RH |
13514 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); |
13515 | tmp = gen_rtx_MEM (Pmode, tmp); | |
13516 | emit_move_insn (tmp, operands[0]); | |
13517 | } | |
13518 | else | |
13519 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
13520 | DONE; | |
13521 | }") |