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cpp.c (cpp_define_builtins): Fixed warning about comment.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
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996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
8ef65e3d 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
602ea4d3 4;; Free Software Foundation, Inc.
996a5f59 5;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 6
5de601cf 7;; This file is part of GCC.
1fd4e8c1 8
5de601cf
NC		 9;; GCC is free software; you can redistribute it and/or modify it
10;; under the terms of the GNU General Public License as published
2f83c7d6 11;; by the Free Software Foundation; either version 3, or (at your
5de601cf 12;; option) any later version.
1fd4e8c1 13
5de601cf
NC		 14;; GCC is distributed in the hope that it will be useful, but WITHOUT
15;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17;; License for more details.
1fd4e8c1
RK		 18
19;; You should have received a copy of the GNU General Public License
2f83c7d6
NC		 20;; along with GCC; see the file COPYING3. If not see
21;; <http://www.gnu.org/licenses/>.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 24
1de43f85
DE		 25;;
26;; REGNOS
27;;
28
29(define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
615158e2
JJ		 52;;
53;; UNSPEC usage
54;;
55
56(define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
9719f3b7
DE		 64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
615158e2
JJ		 68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
ecb62ae7 83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
cef6b86c 84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
da4c340c 85 (UNSPEC_STFIWX 32)
9f0076e5
DE		 86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
716019c0
JM		 98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
9c78b944 101 (UNSPEC_RSQRT 48)
615158e2
JJ		 102 ])
103
104;;
105;; UNSPEC_VOLATILE usage
106;;
107
108(define_constants
109 [(UNSPECV_BLOCK 0)
b52110d4
DE		 110 (UNSPECV_LL 1) ; load-locked
111 (UNSPECV_SC 2) ; store-conditional
615158e2
JJ		 112 (UNSPECV_EH_RR 9) ; eh_reg_restore
113 ])
1fd4e8c1
RK		 114\f
115;; Define an insn type attribute. This is used in function unit delay
116;; computations.
44cd321e 117(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
1fd4e8c1
RK		 118 (const_string "integer"))
119
b19003d8 120;; Length (in bytes).
6ae08853 121; '(pc)' in the following doesn't include the instruction itself; it is
6cbadf36 122; calculated as if the instruction had zero size.
b19003d8
RK		 123(define_attr "length" ""
124 (if_then_else (eq_attr "type" "branch")
6cbadf36 125 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 126 (const_int -32768))
6cbadf36
GK		 127 (lt (minus (match_dup 0) (pc))
128 (const_int 32764)))
39a10a29
GK		 129 (const_int 4)
130 (const_int 8))
b19003d8
RK		 131 (const_int 4)))
132
cfb557c4
RK		 133;; Processor type -- this attribute must exactly match the processor_type
134;; enumeration in rs6000.h.
135
fa41c305 136(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5,power6,cell"
cfb557c4
RK		 137 (const (symbol_ref "rs6000_cpu_attr")))
138
d296e02e
AP		 139
140;; If this instruction is microcoded on the CELL processor
141; The default for load and stores is conditional
142; The default for load extended and the recorded instructions is always microcoded
143(define_attr "cell_micro" "not,conditional,always"
144 (if_then_else (ior (ior (eq_attr "type" "load")
145 (eq_attr "type" "store"))
146 (ior (eq_attr "type" "fpload")
147 (eq_attr "type" "fpstore")))
148 (const_string "conditional")
149 (if_then_else (ior (eq_attr "type" "load_ext")
150 (ior (eq_attr "type" "compare")
151 (eq_attr "type" "delayed_compare")))
152 (const_string "always")
153 (const_string "not"))))
154
155
b54cf83a
DE		 156(automata_option "ndfa")
157
158(include "rios1.md")
159(include "rios2.md")
160(include "rs64.md")
161(include "mpc.md")
162(include "40x.md")
02ca7595 163(include "440.md")
b54cf83a
DE		 164(include "603.md")
165(include "6xx.md")
166(include "7xx.md")
167(include "7450.md")
5e8006fa 168(include "8540.md")
fa41c305 169(include "e300c2c3.md")
b54cf83a 170(include "power4.md")
ec507f2d 171(include "power5.md")
44cd321e 172(include "power6.md")
d296e02e 173(include "cell.md")
48d72335
DE		 174
175(include "predicates.md")
279bb624 176(include "constraints.md")
48d72335 177
ac9e2cff 178(include "darwin.md")
309323c2 179
1fd4e8c1 180\f
3abcb3a7 181;; Mode iterators
915167f5 182
3abcb3a7 183; This mode iterator allows :GPR to be used to indicate the allowable size
915167f5 184; of whole values in GPRs.
3abcb3a7 185(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
915167f5 186
0354e5d8 187; Any supported integer mode.
3abcb3a7 188(define_mode_iterator INT [QI HI SI DI TI])
915167f5 189
0354e5d8 190; Any supported integer mode that fits in one register.
3abcb3a7 191(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
915167f5 192
b5568f07 193; extend modes for DImode
3abcb3a7 194(define_mode_iterator QHSI [QI HI SI])
b5568f07 195
0354e5d8 196; SImode or DImode, even if DImode doesn't fit in GPRs.
3abcb3a7 197(define_mode_iterator SDI [SI DI])
0354e5d8
GK		 198
199; The size of a pointer. Also, the size of the value that a record-condition
200; (one with a '.') will compare.
3abcb3a7 201(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
2e6c9641 202
4ae234b0 203; Any hardware-supported floating-point mode
3abcb3a7 204(define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
4ae234b0 205 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
602ea4d3 206 (TF "!TARGET_IEEEQUAD
17caeff2
JM		 207 && TARGET_HARD_FLOAT
208 && (TARGET_FPRS || TARGET_E500_DOUBLE)
6ef9a246
JJ		 209 && TARGET_LONG_DOUBLE_128")
210 (DD "TARGET_DFP")
211 (TD "TARGET_DFP")])
4ae234b0 212
915167f5 213; Various instructions that come in SI and DI forms.
0354e5d8 214; A generic w/d attribute, for things like cmpw/cmpd.
b5568f07
DE		 215(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
216
217; DImode bits
218(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
915167f5
GK		 219
220\f
1fd4e8c1
RK		 221;; Start with fixed-point load and store insns. Here we put only the more
222;; complex forms. Basic data transfer is done later.
223
b5568f07 224(define_expand "zero_extend<mode>di2"
51b8fc2c 225 [(set (match_operand:DI 0 "gpc_reg_operand" "")
b5568f07 226 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
51b8fc2c
RK		 227 "TARGET_POWERPC64"
228 "")
229
b5568f07 230(define_insn "*zero_extend<mode>di2_internal1"
51b8fc2c 231 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
b5568f07 232 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
51b8fc2c
RK		 233 "TARGET_POWERPC64"
234 "@
b5568f07
DE		 235 l<wd>z%U1%X1 %0,%1
236 rldicl %0,%1,0,<dbits>"
51b8fc2c
RK		 237 [(set_attr "type" "load,*")])
238
b5568f07 239(define_insn "*zero_extend<mode>di2_internal2"
9ebbca7d 240 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
b5568f07 241 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
815cdc52 242 (const_int 0)))
9ebbca7d 243 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 244 "TARGET_64BIT"
9ebbca7d 245 "@
b5568f07 246 rldicl. %2,%1,0,<dbits>
9ebbca7d
GK		 247 #"
248 [(set_attr "type" "compare")
249 (set_attr "length" "4,8")])
250
251(define_split
252 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
b5568f07 253 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 254 (const_int 0)))
255 (clobber (match_scratch:DI 2 ""))]
256 "TARGET_POWERPC64 && reload_completed"
257 [(set (match_dup 2)
258 (zero_extend:DI (match_dup 1)))
259 (set (match_dup 0)
260 (compare:CC (match_dup 2)
261 (const_int 0)))]
262 "")
51b8fc2c 263
b5568f07 264(define_insn "*zero_extend<mode>di2_internal3"
9ebbca7d 265 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
b5568f07 266 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 267 (const_int 0)))
9ebbca7d 268 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 269 (zero_extend:DI (match_dup 1)))]
683bdff7 270 "TARGET_64BIT"
9ebbca7d 271 "@
b5568f07 272 rldicl. %0,%1,0,<dbits>
9ebbca7d
GK		 273 #"
274 [(set_attr "type" "compare")
275 (set_attr "length" "4,8")])
276
277(define_split
278 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
b5568f07 279 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 280 (const_int 0)))
281 (set (match_operand:DI 0 "gpc_reg_operand" "")
282 (zero_extend:DI (match_dup 1)))]
283 "TARGET_POWERPC64 && reload_completed"
284 [(set (match_dup 0)
285 (zero_extend:DI (match_dup 1)))
286 (set (match_dup 2)
287 (compare:CC (match_dup 0)
288 (const_int 0)))]
289 "")
51b8fc2c 290
2bee0449
RK		 291(define_insn "extendqidi2"
292 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
293 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 294 "TARGET_POWERPC64"
44cd321e
PS		 295 "extsb %0,%1"
296 [(set_attr "type" "exts")])
51b8fc2c
RK		 297
298(define_insn ""
9ebbca7d
GK		 299 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
300 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 301 (const_int 0)))
9ebbca7d 302 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 303 "TARGET_64BIT"
9ebbca7d
GK		 304 "@
305 extsb. %2,%1
306 #"
307 [(set_attr "type" "compare")
308 (set_attr "length" "4,8")])
309
310(define_split
311 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
312 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
313 (const_int 0)))
314 (clobber (match_scratch:DI 2 ""))]
315 "TARGET_POWERPC64 && reload_completed"
316 [(set (match_dup 2)
317 (sign_extend:DI (match_dup 1)))
318 (set (match_dup 0)
319 (compare:CC (match_dup 2)
320 (const_int 0)))]
321 "")
51b8fc2c
RK		 322
323(define_insn ""
9ebbca7d
GK		 324 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
325 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 326 (const_int 0)))
9ebbca7d 327 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 328 (sign_extend:DI (match_dup 1)))]
683bdff7 329 "TARGET_64BIT"
9ebbca7d
GK		 330 "@
331 extsb. %0,%1
332 #"
333 [(set_attr "type" "compare")
334 (set_attr "length" "4,8")])
335
336(define_split
337 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
338 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
339 (const_int 0)))
340 (set (match_operand:DI 0 "gpc_reg_operand" "")
341 (sign_extend:DI (match_dup 1)))]
342 "TARGET_POWERPC64 && reload_completed"
343 [(set (match_dup 0)
344 (sign_extend:DI (match_dup 1)))
345 (set (match_dup 2)
346 (compare:CC (match_dup 0)
347 (const_int 0)))]
348 "")
51b8fc2c 349
51b8fc2c
RK		 350(define_expand "extendhidi2"
351 [(set (match_operand:DI 0 "gpc_reg_operand" "")
352 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
353 "TARGET_POWERPC64"
354 "")
355
356(define_insn ""
357 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
358 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
359 "TARGET_POWERPC64"
360 "@
361 lha%U1%X1 %0,%1
362 extsh %0,%1"
44cd321e 363 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 364
365(define_insn ""
9ebbca7d
GK		 366 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
367 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 368 (const_int 0)))
9ebbca7d 369 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 370 "TARGET_64BIT"
9ebbca7d
GK		 371 "@
372 extsh. %2,%1
373 #"
374 [(set_attr "type" "compare")
375 (set_attr "length" "4,8")])
376
377(define_split
378 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
379 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
380 (const_int 0)))
381 (clobber (match_scratch:DI 2 ""))]
382 "TARGET_POWERPC64 && reload_completed"
383 [(set (match_dup 2)
384 (sign_extend:DI (match_dup 1)))
385 (set (match_dup 0)
386 (compare:CC (match_dup 2)
387 (const_int 0)))]
388 "")
51b8fc2c
RK		 389
390(define_insn ""
9ebbca7d
GK		 391 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
392 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 393 (const_int 0)))
9ebbca7d 394 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 395 (sign_extend:DI (match_dup 1)))]
683bdff7 396 "TARGET_64BIT"
9ebbca7d
GK		 397 "@
398 extsh. %0,%1
399 #"
400 [(set_attr "type" "compare")
401 (set_attr "length" "4,8")])
402
403(define_split
404 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
405 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
406 (const_int 0)))
407 (set (match_operand:DI 0 "gpc_reg_operand" "")
408 (sign_extend:DI (match_dup 1)))]
409 "TARGET_POWERPC64 && reload_completed"
410 [(set (match_dup 0)
411 (sign_extend:DI (match_dup 1)))
412 (set (match_dup 2)
413 (compare:CC (match_dup 0)
414 (const_int 0)))]
415 "")
51b8fc2c 416
51b8fc2c
RK		 417(define_expand "extendsidi2"
418 [(set (match_operand:DI 0 "gpc_reg_operand" "")
419 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
420 "TARGET_POWERPC64"
421 "")
422
423(define_insn ""
424 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 425 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
51b8fc2c
RK		 426 "TARGET_POWERPC64"
427 "@
428 lwa%U1%X1 %0,%1
429 extsw %0,%1"
44cd321e 430 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 431
432(define_insn ""
9ebbca7d
GK		 433 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
434 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 435 (const_int 0)))
9ebbca7d 436 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 437 "TARGET_64BIT"
9ebbca7d
GK		 438 "@
439 extsw. %2,%1
440 #"
441 [(set_attr "type" "compare")
442 (set_attr "length" "4,8")])
443
444(define_split
445 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
446 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
447 (const_int 0)))
448 (clobber (match_scratch:DI 2 ""))]
449 "TARGET_POWERPC64 && reload_completed"
450 [(set (match_dup 2)
451 (sign_extend:DI (match_dup 1)))
452 (set (match_dup 0)
453 (compare:CC (match_dup 2)
454 (const_int 0)))]
455 "")
51b8fc2c
RK		 456
457(define_insn ""
9ebbca7d
GK		 458 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
459 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 460 (const_int 0)))
9ebbca7d 461 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 462 (sign_extend:DI (match_dup 1)))]
683bdff7 463 "TARGET_64BIT"
9ebbca7d
GK		 464 "@
465 extsw. %0,%1
466 #"
467 [(set_attr "type" "compare")
468 (set_attr "length" "4,8")])
469
470(define_split
471 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
472 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
473 (const_int 0)))
474 (set (match_operand:DI 0 "gpc_reg_operand" "")
475 (sign_extend:DI (match_dup 1)))]
476 "TARGET_POWERPC64 && reload_completed"
477 [(set (match_dup 0)
478 (sign_extend:DI (match_dup 1)))
479 (set (match_dup 2)
480 (compare:CC (match_dup 0)
481 (const_int 0)))]
482 "")
51b8fc2c 483
1fd4e8c1 484(define_expand "zero_extendqisi2"
cd2b37d9
RK		 485 [(set (match_operand:SI 0 "gpc_reg_operand" "")
486 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 487 ""
488 "")
489
490(define_insn ""
cd2b37d9 491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 492 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
493 ""
494 "@
495 lbz%U1%X1 %0,%1
005a35b9 496 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 497 [(set_attr "type" "load,*")])
498
499(define_insn ""
9ebbca7d
GK		 500 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
501 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 502 (const_int 0)))
9ebbca7d 503 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 504 ""
9ebbca7d
GK		 505 "@
506 {andil.|andi.} %2,%1,0xff
507 #"
508 [(set_attr "type" "compare")
509 (set_attr "length" "4,8")])
510
511(define_split
512 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
513 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
514 (const_int 0)))
515 (clobber (match_scratch:SI 2 ""))]
516 "reload_completed"
517 [(set (match_dup 2)
518 (zero_extend:SI (match_dup 1)))
519 (set (match_dup 0)
520 (compare:CC (match_dup 2)
521 (const_int 0)))]
522 "")
1fd4e8c1
RK		 523
524(define_insn ""
9ebbca7d
GK		 525 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
526 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 527 (const_int 0)))
9ebbca7d 528 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 529 (zero_extend:SI (match_dup 1)))]
530 ""
9ebbca7d
GK		 531 "@
532 {andil.|andi.} %0,%1,0xff
533 #"
534 [(set_attr "type" "compare")
535 (set_attr "length" "4,8")])
536
537(define_split
538 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
539 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
540 (const_int 0)))
541 (set (match_operand:SI 0 "gpc_reg_operand" "")
542 (zero_extend:SI (match_dup 1)))]
543 "reload_completed"
544 [(set (match_dup 0)
545 (zero_extend:SI (match_dup 1)))
546 (set (match_dup 2)
547 (compare:CC (match_dup 0)
548 (const_int 0)))]
549 "")
1fd4e8c1 550
51b8fc2c
RK		 551(define_expand "extendqisi2"
552 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
553 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
554 ""
555 "
556{
557 if (TARGET_POWERPC)
558 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
559 else if (TARGET_POWER)
560 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
561 else
562 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
563 DONE;
564}")
565
566(define_insn "extendqisi2_ppc"
2bee0449
RK		 567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
568 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 569 "TARGET_POWERPC"
44cd321e
PS		 570 "extsb %0,%1"
571 [(set_attr "type" "exts")])
51b8fc2c
RK		 572
573(define_insn ""
9ebbca7d
GK		 574 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
575 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 576 (const_int 0)))
9ebbca7d 577 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 578 "TARGET_POWERPC"
9ebbca7d
GK		 579 "@
580 extsb. %2,%1
581 #"
582 [(set_attr "type" "compare")
583 (set_attr "length" "4,8")])
584
585(define_split
586 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
587 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
588 (const_int 0)))
589 (clobber (match_scratch:SI 2 ""))]
590 "TARGET_POWERPC && reload_completed"
591 [(set (match_dup 2)
592 (sign_extend:SI (match_dup 1)))
593 (set (match_dup 0)
594 (compare:CC (match_dup 2)
595 (const_int 0)))]
596 "")
51b8fc2c
RK		 597
598(define_insn ""
9ebbca7d
GK		 599 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
600 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 601 (const_int 0)))
9ebbca7d 602 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 603 (sign_extend:SI (match_dup 1)))]
604 "TARGET_POWERPC"
9ebbca7d
GK		 605 "@
606 extsb. %0,%1
607 #"
608 [(set_attr "type" "compare")
609 (set_attr "length" "4,8")])
610
611(define_split
612 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
613 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
614 (const_int 0)))
615 (set (match_operand:SI 0 "gpc_reg_operand" "")
616 (sign_extend:SI (match_dup 1)))]
617 "TARGET_POWERPC && reload_completed"
618 [(set (match_dup 0)
619 (sign_extend:SI (match_dup 1)))
620 (set (match_dup 2)
621 (compare:CC (match_dup 0)
622 (const_int 0)))]
623 "")
51b8fc2c
RK		 624
625(define_expand "extendqisi2_power"
626 [(parallel [(set (match_dup 2)
627 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
628 (const_int 24)))
629 (clobber (scratch:SI))])
630 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
631 (ashiftrt:SI (match_dup 2)
632 (const_int 24)))
633 (clobber (scratch:SI))])]
634 "TARGET_POWER"
635 "
636{ operands[1] = gen_lowpart (SImode, operands[1]);
637 operands[2] = gen_reg_rtx (SImode); }")
638
639(define_expand "extendqisi2_no_power"
640 [(set (match_dup 2)
641 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
642 (const_int 24)))
643 (set (match_operand:SI 0 "gpc_reg_operand" "")
644 (ashiftrt:SI (match_dup 2)
645 (const_int 24)))]
646 "! TARGET_POWER && ! TARGET_POWERPC"
647 "
648{ operands[1] = gen_lowpart (SImode, operands[1]);
649 operands[2] = gen_reg_rtx (SImode); }")
650
1fd4e8c1 651(define_expand "zero_extendqihi2"
cd2b37d9
RK		 652 [(set (match_operand:HI 0 "gpc_reg_operand" "")
653 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 654 ""
655 "")
656
657(define_insn ""
cd2b37d9 658 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 659 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
660 ""
661 "@
662 lbz%U1%X1 %0,%1
005a35b9 663 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 664 [(set_attr "type" "load,*")])
665
666(define_insn ""
9ebbca7d
GK		 667 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
668 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 669 (const_int 0)))
9ebbca7d 670 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 671 ""
9ebbca7d
GK		 672 "@
673 {andil.|andi.} %2,%1,0xff
674 #"
675 [(set_attr "type" "compare")
676 (set_attr "length" "4,8")])
677
678(define_split
679 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
680 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
681 (const_int 0)))
682 (clobber (match_scratch:HI 2 ""))]
683 "reload_completed"
684 [(set (match_dup 2)
685 (zero_extend:HI (match_dup 1)))
686 (set (match_dup 0)
687 (compare:CC (match_dup 2)
688 (const_int 0)))]
689 "")
1fd4e8c1 690
51b8fc2c 691(define_insn ""
9ebbca7d
GK		 692 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
693 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 694 (const_int 0)))
9ebbca7d 695 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 696 (zero_extend:HI (match_dup 1)))]
697 ""
9ebbca7d
GK		 698 "@
699 {andil.|andi.} %0,%1,0xff
700 #"
701 [(set_attr "type" "compare")
702 (set_attr "length" "4,8")])
703
704(define_split
705 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
706 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
707 (const_int 0)))
708 (set (match_operand:HI 0 "gpc_reg_operand" "")
709 (zero_extend:HI (match_dup 1)))]
710 "reload_completed"
711 [(set (match_dup 0)
712 (zero_extend:HI (match_dup 1)))
713 (set (match_dup 2)
714 (compare:CC (match_dup 0)
715 (const_int 0)))]
716 "")
815cdc52
MM		 717
718(define_expand "extendqihi2"
719 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
720 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
721 ""
722 "
723{
724 if (TARGET_POWERPC)
725 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
726 else if (TARGET_POWER)
727 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
728 else
729 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
730 DONE;
731}")
732
733(define_insn "extendqihi2_ppc"
734 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
735 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
736 "TARGET_POWERPC"
44cd321e
PS		 737 "extsb %0,%1"
738 [(set_attr "type" "exts")])
815cdc52
MM		 739
740(define_insn ""
9ebbca7d
GK		 741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
742 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 743 (const_int 0)))
9ebbca7d 744 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 745 "TARGET_POWERPC"
9ebbca7d
GK		 746 "@
747 extsb. %2,%1
748 #"
749 [(set_attr "type" "compare")
750 (set_attr "length" "4,8")])
751
752(define_split
753 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
754 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
755 (const_int 0)))
756 (clobber (match_scratch:HI 2 ""))]
757 "TARGET_POWERPC && reload_completed"
758 [(set (match_dup 2)
759 (sign_extend:HI (match_dup 1)))
760 (set (match_dup 0)
761 (compare:CC (match_dup 2)
762 (const_int 0)))]
763 "")
815cdc52
MM		 764
765(define_insn ""
9ebbca7d
GK		 766 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
767 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 768 (const_int 0)))
9ebbca7d 769 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 770 (sign_extend:HI (match_dup 1)))]
771 "TARGET_POWERPC"
9ebbca7d
GK		 772 "@
773 extsb. %0,%1
774 #"
775 [(set_attr "type" "compare")
776 (set_attr "length" "4,8")])
777
778(define_split
779 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
780 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
781 (const_int 0)))
782 (set (match_operand:HI 0 "gpc_reg_operand" "")
783 (sign_extend:HI (match_dup 1)))]
784 "TARGET_POWERPC && reload_completed"
785 [(set (match_dup 0)
786 (sign_extend:HI (match_dup 1)))
787 (set (match_dup 2)
788 (compare:CC (match_dup 0)
789 (const_int 0)))]
790 "")
51b8fc2c
RK		 791
792(define_expand "extendqihi2_power"
793 [(parallel [(set (match_dup 2)
794 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
795 (const_int 24)))
796 (clobber (scratch:SI))])
797 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
798 (ashiftrt:SI (match_dup 2)
799 (const_int 24)))
800 (clobber (scratch:SI))])]
801 "TARGET_POWER"
802 "
803{ operands[0] = gen_lowpart (SImode, operands[0]);
804 operands[1] = gen_lowpart (SImode, operands[1]);
805 operands[2] = gen_reg_rtx (SImode); }")
806
807(define_expand "extendqihi2_no_power"
808 [(set (match_dup 2)
809 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
810 (const_int 24)))
811 (set (match_operand:HI 0 "gpc_reg_operand" "")
812 (ashiftrt:SI (match_dup 2)
813 (const_int 24)))]
814 "! TARGET_POWER && ! TARGET_POWERPC"
815 "
816{ operands[0] = gen_lowpart (SImode, operands[0]);
817 operands[1] = gen_lowpart (SImode, operands[1]);
818 operands[2] = gen_reg_rtx (SImode); }")
819
1fd4e8c1 820(define_expand "zero_extendhisi2"
5f243543 821 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 822 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 823 ""
824 "")
825
826(define_insn ""
cd2b37d9 827 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 828 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
829 ""
830 "@
831 lhz%U1%X1 %0,%1
005a35b9 832 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 833 [(set_attr "type" "load,*")])
834
835(define_insn ""
9ebbca7d
GK		 836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
837 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 838 (const_int 0)))
9ebbca7d 839 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 840 ""
9ebbca7d
GK		 841 "@
842 {andil.|andi.} %2,%1,0xffff
843 #"
844 [(set_attr "type" "compare")
845 (set_attr "length" "4,8")])
846
847(define_split
848 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
849 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
850 (const_int 0)))
851 (clobber (match_scratch:SI 2 ""))]
852 "reload_completed"
853 [(set (match_dup 2)
854 (zero_extend:SI (match_dup 1)))
855 (set (match_dup 0)
856 (compare:CC (match_dup 2)
857 (const_int 0)))]
858 "")
1fd4e8c1
RK		 859
860(define_insn ""
9ebbca7d
GK		 861 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
862 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 863 (const_int 0)))
9ebbca7d 864 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 865 (zero_extend:SI (match_dup 1)))]
866 ""
9ebbca7d
GK		 867 "@
868 {andil.|andi.} %0,%1,0xffff
869 #"
870 [(set_attr "type" "compare")
871 (set_attr "length" "4,8")])
872
873(define_split
874 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
875 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
876 (const_int 0)))
877 (set (match_operand:SI 0 "gpc_reg_operand" "")
878 (zero_extend:SI (match_dup 1)))]
879 "reload_completed"
880 [(set (match_dup 0)
881 (zero_extend:SI (match_dup 1)))
882 (set (match_dup 2)
883 (compare:CC (match_dup 0)
884 (const_int 0)))]
885 "")
1fd4e8c1
RK		 886
887(define_expand "extendhisi2"
cd2b37d9
RK		 888 [(set (match_operand:SI 0 "gpc_reg_operand" "")
889 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 890 ""
891 "")
892
893(define_insn ""
cd2b37d9 894 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 895 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
896 ""
897 "@
898 lha%U1%X1 %0,%1
ca7f5001 899 {exts|extsh} %0,%1"
44cd321e 900 [(set_attr "type" "load_ext,exts")])
1fd4e8c1
RK		 901
902(define_insn ""
9ebbca7d
GK		 903 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
904 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 905 (const_int 0)))
9ebbca7d 906 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 907 ""
9ebbca7d
GK		 908 "@
909 {exts.|extsh.} %2,%1
910 #"
911 [(set_attr "type" "compare")
912 (set_attr "length" "4,8")])
913
914(define_split
915 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
916 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
917 (const_int 0)))
918 (clobber (match_scratch:SI 2 ""))]
919 "reload_completed"
920 [(set (match_dup 2)
921 (sign_extend:SI (match_dup 1)))
922 (set (match_dup 0)
923 (compare:CC (match_dup 2)
924 (const_int 0)))]
925 "")
1fd4e8c1
RK		 926
927(define_insn ""
9ebbca7d
GK		 928 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
929 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 930 (const_int 0)))
9ebbca7d 931 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 932 (sign_extend:SI (match_dup 1)))]
933 ""
9ebbca7d
GK		 934 "@
935 {exts.|extsh.} %0,%1
936 #"
937 [(set_attr "type" "compare")
938 (set_attr "length" "4,8")])
1fd4e8c1 939\f
4adf8008 940;; IBM 405, 440 and 464 half-word multiplication operations.
131aeb82
JM		 941
942(define_insn "*macchwc"
943 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
944 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
945 (match_operand:SI 2 "gpc_reg_operand" "r")
946 (const_int 16))
947 (sign_extend:SI
948 (match_operand:HI 1 "gpc_reg_operand" "r")))
949 (match_operand:SI 4 "gpc_reg_operand" "0"))
950 (const_int 0)))
951 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
952 (plus:SI (mult:SI (ashiftrt:SI
953 (match_dup 2)
954 (const_int 16))
955 (sign_extend:SI
956 (match_dup 1)))
957 (match_dup 4)))]
958 "TARGET_MULHW"
959 "macchw. %0, %1, %2"
960 [(set_attr "type" "imul3")])
961
962(define_insn "*macchw"
963 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
964 (plus:SI (mult:SI (ashiftrt:SI
965 (match_operand:SI 2 "gpc_reg_operand" "r")
966 (const_int 16))
967 (sign_extend:SI
968 (match_operand:HI 1 "gpc_reg_operand" "r")))
969 (match_operand:SI 3 "gpc_reg_operand" "0")))]
970 "TARGET_MULHW"
971 "macchw %0, %1, %2"
972 [(set_attr "type" "imul3")])
973
974(define_insn "*macchwuc"
975 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
976 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
977 (match_operand:SI 2 "gpc_reg_operand" "r")
978 (const_int 16))
979 (zero_extend:SI
980 (match_operand:HI 1 "gpc_reg_operand" "r")))
981 (match_operand:SI 4 "gpc_reg_operand" "0"))
982 (const_int 0)))
983 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
984 (plus:SI (mult:SI (lshiftrt:SI
985 (match_dup 2)
986 (const_int 16))
987 (zero_extend:SI
988 (match_dup 1)))
989 (match_dup 4)))]
990 "TARGET_MULHW"
991 "macchwu. %0, %1, %2"
992 [(set_attr "type" "imul3")])
993
994(define_insn "*macchwu"
995 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
996 (plus:SI (mult:SI (lshiftrt:SI
997 (match_operand:SI 2 "gpc_reg_operand" "r")
998 (const_int 16))
999 (zero_extend:SI
1000 (match_operand:HI 1 "gpc_reg_operand" "r")))
1001 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1002 "TARGET_MULHW"
1003 "macchwu %0, %1, %2"
1004 [(set_attr "type" "imul3")])
1005
1006(define_insn "*machhwc"
1007 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1008 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1009 (match_operand:SI 1 "gpc_reg_operand" "%r")
1010 (const_int 16))
1011 (ashiftrt:SI
1012 (match_operand:SI 2 "gpc_reg_operand" "r")
1013 (const_int 16)))
1014 (match_operand:SI 4 "gpc_reg_operand" "0"))
1015 (const_int 0)))
1016 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1017 (plus:SI (mult:SI (ashiftrt:SI
1018 (match_dup 1)
1019 (const_int 16))
1020 (ashiftrt:SI
1021 (match_dup 2)
1022 (const_int 16)))
1023 (match_dup 4)))]
1024 "TARGET_MULHW"
1025 "machhw. %0, %1, %2"
1026 [(set_attr "type" "imul3")])
1027
1028(define_insn "*machhw"
1029 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1030 (plus:SI (mult:SI (ashiftrt:SI
1031 (match_operand:SI 1 "gpc_reg_operand" "%r")
1032 (const_int 16))
1033 (ashiftrt:SI
1034 (match_operand:SI 2 "gpc_reg_operand" "r")
1035 (const_int 16)))
1036 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1037 "TARGET_MULHW"
1038 "machhw %0, %1, %2"
1039 [(set_attr "type" "imul3")])
1040
1041(define_insn "*machhwuc"
1042 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1043 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1044 (match_operand:SI 1 "gpc_reg_operand" "%r")
1045 (const_int 16))
1046 (lshiftrt:SI
1047 (match_operand:SI 2 "gpc_reg_operand" "r")
1048 (const_int 16)))
1049 (match_operand:SI 4 "gpc_reg_operand" "0"))
1050 (const_int 0)))
1051 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (lshiftrt:SI
1053 (match_dup 1)
1054 (const_int 16))
1055 (lshiftrt:SI
1056 (match_dup 2)
1057 (const_int 16)))
1058 (match_dup 4)))]
1059 "TARGET_MULHW"
1060 "machhwu. %0, %1, %2"
1061 [(set_attr "type" "imul3")])
1062
1063(define_insn "*machhwu"
1064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1065 (plus:SI (mult:SI (lshiftrt:SI
1066 (match_operand:SI 1 "gpc_reg_operand" "%r")
1067 (const_int 16))
1068 (lshiftrt:SI
1069 (match_operand:SI 2 "gpc_reg_operand" "r")
1070 (const_int 16)))
1071 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1072 "TARGET_MULHW"
1073 "machhwu %0, %1, %2"
1074 [(set_attr "type" "imul3")])
1075
1076(define_insn "*maclhwc"
1077 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1078 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1079 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1080 (sign_extend:SI
1081 (match_operand:HI 2 "gpc_reg_operand" "r")))
1082 (match_operand:SI 4 "gpc_reg_operand" "0"))
1083 (const_int 0)))
1084 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1085 (plus:SI (mult:SI (sign_extend:SI
1086 (match_dup 1))
1087 (sign_extend:SI
1088 (match_dup 2)))
1089 (match_dup 4)))]
1090 "TARGET_MULHW"
1091 "maclhw. %0, %1, %2"
1092 [(set_attr "type" "imul3")])
1093
1094(define_insn "*maclhw"
1095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1096 (plus:SI (mult:SI (sign_extend:SI
1097 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1098 (sign_extend:SI
1099 (match_operand:HI 2 "gpc_reg_operand" "r")))
1100 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1101 "TARGET_MULHW"
1102 "maclhw %0, %1, %2"
1103 [(set_attr "type" "imul3")])
1104
1105(define_insn "*maclhwuc"
1106 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1107 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1108 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1109 (zero_extend:SI
1110 (match_operand:HI 2 "gpc_reg_operand" "r")))
1111 (match_operand:SI 4 "gpc_reg_operand" "0"))
1112 (const_int 0)))
1113 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1114 (plus:SI (mult:SI (zero_extend:SI
1115 (match_dup 1))
1116 (zero_extend:SI
1117 (match_dup 2)))
1118 (match_dup 4)))]
1119 "TARGET_MULHW"
1120 "maclhwu. %0, %1, %2"
1121 [(set_attr "type" "imul3")])
1122
1123(define_insn "*maclhwu"
1124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1125 (plus:SI (mult:SI (zero_extend:SI
1126 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1127 (zero_extend:SI
1128 (match_operand:HI 2 "gpc_reg_operand" "r")))
1129 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1130 "TARGET_MULHW"
1131 "maclhwu %0, %1, %2"
1132 [(set_attr "type" "imul3")])
1133
1134(define_insn "*nmacchwc"
1135 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1136 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1137 (mult:SI (ashiftrt:SI
1138 (match_operand:SI 2 "gpc_reg_operand" "r")
1139 (const_int 16))
1140 (sign_extend:SI
1141 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1142 (const_int 0)))
1143 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1144 (minus:SI (match_dup 4)
1145 (mult:SI (ashiftrt:SI
1146 (match_dup 2)
1147 (const_int 16))
1148 (sign_extend:SI
1149 (match_dup 1)))))]
1150 "TARGET_MULHW"
1151 "nmacchw. %0, %1, %2"
1152 [(set_attr "type" "imul3")])
1153
1154(define_insn "*nmacchw"
1155 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1156 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1157 (mult:SI (ashiftrt:SI
1158 (match_operand:SI 2 "gpc_reg_operand" "r")
1159 (const_int 16))
1160 (sign_extend:SI
1161 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1162 "TARGET_MULHW"
1163 "nmacchw %0, %1, %2"
1164 [(set_attr "type" "imul3")])
1165
1166(define_insn "*nmachhwc"
1167 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1168 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1169 (mult:SI (ashiftrt:SI
1170 (match_operand:SI 1 "gpc_reg_operand" "%r")
1171 (const_int 16))
1172 (ashiftrt:SI
1173 (match_operand:SI 2 "gpc_reg_operand" "r")
1174 (const_int 16))))
1175 (const_int 0)))
1176 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1177 (minus:SI (match_dup 4)
1178 (mult:SI (ashiftrt:SI
1179 (match_dup 1)
1180 (const_int 16))
1181 (ashiftrt:SI
1182 (match_dup 2)
1183 (const_int 16)))))]
1184 "TARGET_MULHW"
1185 "nmachhw. %0, %1, %2"
1186 [(set_attr "type" "imul3")])
1187
1188(define_insn "*nmachhw"
1189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1190 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1191 (mult:SI (ashiftrt:SI
1192 (match_operand:SI 1 "gpc_reg_operand" "%r")
1193 (const_int 16))
1194 (ashiftrt:SI
1195 (match_operand:SI 2 "gpc_reg_operand" "r")
1196 (const_int 16)))))]
1197 "TARGET_MULHW"
1198 "nmachhw %0, %1, %2"
1199 [(set_attr "type" "imul3")])
1200
1201(define_insn "*nmaclhwc"
1202 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1203 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1204 (mult:SI (sign_extend:SI
1205 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1206 (sign_extend:SI
1207 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1208 (const_int 0)))
1209 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1210 (minus:SI (match_dup 4)
1211 (mult:SI (sign_extend:SI
1212 (match_dup 1))
1213 (sign_extend:SI
1214 (match_dup 2)))))]
1215 "TARGET_MULHW"
1216 "nmaclhw. %0, %1, %2"
1217 [(set_attr "type" "imul3")])
1218
1219(define_insn "*nmaclhw"
1220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1221 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1222 (mult:SI (sign_extend:SI
1223 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1224 (sign_extend:SI
1225 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1226 "TARGET_MULHW"
1227 "nmaclhw %0, %1, %2"
1228 [(set_attr "type" "imul3")])
1229
1230(define_insn "*mulchwc"
1231 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1232 (compare:CC (mult:SI (ashiftrt:SI
1233 (match_operand:SI 2 "gpc_reg_operand" "r")
1234 (const_int 16))
1235 (sign_extend:SI
1236 (match_operand:HI 1 "gpc_reg_operand" "r")))
1237 (const_int 0)))
1238 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1239 (mult:SI (ashiftrt:SI
1240 (match_dup 2)
1241 (const_int 16))
1242 (sign_extend:SI
1243 (match_dup 1))))]
1244 "TARGET_MULHW"
1245 "mulchw. %0, %1, %2"
1246 [(set_attr "type" "imul3")])
1247
1248(define_insn "*mulchw"
1249 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1250 (mult:SI (ashiftrt:SI
1251 (match_operand:SI 2 "gpc_reg_operand" "r")
1252 (const_int 16))
1253 (sign_extend:SI
1254 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1255 "TARGET_MULHW"
1256 "mulchw %0, %1, %2"
1257 [(set_attr "type" "imul3")])
1258
1259(define_insn "*mulchwuc"
1260 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1261 (compare:CC (mult:SI (lshiftrt:SI
1262 (match_operand:SI 2 "gpc_reg_operand" "r")
1263 (const_int 16))
1264 (zero_extend:SI
1265 (match_operand:HI 1 "gpc_reg_operand" "r")))
1266 (const_int 0)))
1267 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1268 (mult:SI (lshiftrt:SI
1269 (match_dup 2)
1270 (const_int 16))
1271 (zero_extend:SI
1272 (match_dup 1))))]
1273 "TARGET_MULHW"
1274 "mulchwu. %0, %1, %2"
1275 [(set_attr "type" "imul3")])
1276
1277(define_insn "*mulchwu"
1278 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1279 (mult:SI (lshiftrt:SI
1280 (match_operand:SI 2 "gpc_reg_operand" "r")
1281 (const_int 16))
1282 (zero_extend:SI
1283 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1284 "TARGET_MULHW"
1285 "mulchwu %0, %1, %2"
1286 [(set_attr "type" "imul3")])
1287
1288(define_insn "*mulhhwc"
1289 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1290 (compare:CC (mult:SI (ashiftrt:SI
1291 (match_operand:SI 1 "gpc_reg_operand" "%r")
1292 (const_int 16))
1293 (ashiftrt:SI
1294 (match_operand:SI 2 "gpc_reg_operand" "r")
1295 (const_int 16)))
1296 (const_int 0)))
1297 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1298 (mult:SI (ashiftrt:SI
1299 (match_dup 1)
1300 (const_int 16))
1301 (ashiftrt:SI
1302 (match_dup 2)
1303 (const_int 16))))]
1304 "TARGET_MULHW"
1305 "mulhhw. %0, %1, %2"
1306 [(set_attr "type" "imul3")])
1307
1308(define_insn "*mulhhw"
1309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1310 (mult:SI (ashiftrt:SI
1311 (match_operand:SI 1 "gpc_reg_operand" "%r")
1312 (const_int 16))
1313 (ashiftrt:SI
1314 (match_operand:SI 2 "gpc_reg_operand" "r")
1315 (const_int 16))))]
1316 "TARGET_MULHW"
1317 "mulhhw %0, %1, %2"
1318 [(set_attr "type" "imul3")])
1319
1320(define_insn "*mulhhwuc"
1321 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1322 (compare:CC (mult:SI (lshiftrt:SI
1323 (match_operand:SI 1 "gpc_reg_operand" "%r")
1324 (const_int 16))
1325 (lshiftrt:SI
1326 (match_operand:SI 2 "gpc_reg_operand" "r")
1327 (const_int 16)))
1328 (const_int 0)))
1329 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1330 (mult:SI (lshiftrt:SI
1331 (match_dup 1)
1332 (const_int 16))
1333 (lshiftrt:SI
1334 (match_dup 2)
1335 (const_int 16))))]
1336 "TARGET_MULHW"
1337 "mulhhwu. %0, %1, %2"
1338 [(set_attr "type" "imul3")])
1339
1340(define_insn "*mulhhwu"
1341 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1342 (mult:SI (lshiftrt:SI
1343 (match_operand:SI 1 "gpc_reg_operand" "%r")
1344 (const_int 16))
1345 (lshiftrt:SI
1346 (match_operand:SI 2 "gpc_reg_operand" "r")
1347 (const_int 16))))]
1348 "TARGET_MULHW"
1349 "mulhhwu %0, %1, %2"
1350 [(set_attr "type" "imul3")])
1351
1352(define_insn "*mullhwc"
1353 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1354 (compare:CC (mult:SI (sign_extend:SI
1355 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1356 (sign_extend:SI
1357 (match_operand:HI 2 "gpc_reg_operand" "r")))
1358 (const_int 0)))
1359 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1360 (mult:SI (sign_extend:SI
1361 (match_dup 1))
1362 (sign_extend:SI
1363 (match_dup 2))))]
1364 "TARGET_MULHW"
1365 "mullhw. %0, %1, %2"
1366 [(set_attr "type" "imul3")])
1367
1368(define_insn "*mullhw"
1369 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1370 (mult:SI (sign_extend:SI
1371 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1372 (sign_extend:SI
1373 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1374 "TARGET_MULHW"
1375 "mullhw %0, %1, %2"
1376 [(set_attr "type" "imul3")])
1377
1378(define_insn "*mullhwuc"
1379 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1380 (compare:CC (mult:SI (zero_extend:SI
1381 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1382 (zero_extend:SI
1383 (match_operand:HI 2 "gpc_reg_operand" "r")))
1384 (const_int 0)))
1385 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1386 (mult:SI (zero_extend:SI
1387 (match_dup 1))
1388 (zero_extend:SI
1389 (match_dup 2))))]
1390 "TARGET_MULHW"
1391 "mullhwu. %0, %1, %2"
1392 [(set_attr "type" "imul3")])
1393
1394(define_insn "*mullhwu"
1395 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1396 (mult:SI (zero_extend:SI
1397 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1398 (zero_extend:SI
1399 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1400 "TARGET_MULHW"
1401 "mullhwu %0, %1, %2"
1402 [(set_attr "type" "imul3")])
1403\f
4adf8008 1404;; IBM 405, 440 and 464 string-search dlmzb instruction support.
716019c0
JM		 1405(define_insn "dlmzb"
1406 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1407 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1408 (match_operand:SI 2 "gpc_reg_operand" "r")]
1409 UNSPEC_DLMZB_CR))
1410 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1411 (unspec:SI [(match_dup 1)
1412 (match_dup 2)]
1413 UNSPEC_DLMZB))]
1414 "TARGET_DLMZB"
1415 "dlmzb. %0, %1, %2")
1416
1417(define_expand "strlensi"
1418 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1419 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1420 (match_operand:QI 2 "const_int_operand" "")
1421 (match_operand 3 "const_int_operand" "")]
1422 UNSPEC_DLMZB_STRLEN))
1423 (clobber (match_scratch:CC 4 "=x"))]
1424 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1425{
1426 rtx result = operands[0];
1427 rtx src = operands[1];
1428 rtx search_char = operands[2];
1429 rtx align = operands[3];
1430 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1431 rtx loop_label, end_label, mem, cr0, cond;
1432 if (search_char != const0_rtx
1433 || GET_CODE (align) != CONST_INT
1434 || INTVAL (align) < 8)
1435 FAIL;
1436 word1 = gen_reg_rtx (SImode);
1437 word2 = gen_reg_rtx (SImode);
1438 scratch_dlmzb = gen_reg_rtx (SImode);
1439 scratch_string = gen_reg_rtx (Pmode);
1440 loop_label = gen_label_rtx ();
1441 end_label = gen_label_rtx ();
1442 addr = force_reg (Pmode, XEXP (src, 0));
1443 emit_move_insn (scratch_string, addr);
1444 emit_label (loop_label);
1445 mem = change_address (src, SImode, scratch_string);
1446 emit_move_insn (word1, mem);
1447 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1448 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1449 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1450 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1451 emit_jump_insn (gen_rtx_SET (VOIDmode,
1452 pc_rtx,
1453 gen_rtx_IF_THEN_ELSE (VOIDmode,
1454 cond,
1455 gen_rtx_LABEL_REF
1456 (VOIDmode,
1457 end_label),
1458 pc_rtx)));
1459 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1460 emit_jump_insn (gen_rtx_SET (VOIDmode,
1461 pc_rtx,
1462 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
ea5bd0d8 1463 emit_barrier ();
716019c0
JM		 1464 emit_label (end_label);
1465 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1466 emit_insn (gen_subsi3 (result, scratch_string, addr));
1467 emit_insn (gen_subsi3 (result, result, const1_rtx));
1468 DONE;
1469})
1470\f
9ebbca7d
GK		 1471(define_split
1472 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1473 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1474 (const_int 0)))
1475 (set (match_operand:SI 0 "gpc_reg_operand" "")
1476 (sign_extend:SI (match_dup 1)))]
1477 "reload_completed"
1478 [(set (match_dup 0)
1479 (sign_extend:SI (match_dup 1)))
1480 (set (match_dup 2)
1481 (compare:CC (match_dup 0)
1482 (const_int 0)))]
1483 "")
1484
1fd4e8c1 1485;; Fixed-point arithmetic insns.
deb9225a 1486
0354e5d8
GK		 1487(define_expand "add<mode>3"
1488 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1489 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
4ae234b0 1490 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
7cd5235b 1491 ""
7cd5235b 1492{
0354e5d8
GK		 1493 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1494 {
1495 if (non_short_cint_operand (operands[2], DImode))
1496 FAIL;
1497 }
1498 else if (GET_CODE (operands[2]) == CONST_INT
1499 && ! add_operand (operands[2], <MODE>mode))
7cd5235b 1500 {
b3a13419
ILT		 1501 rtx tmp = ((!can_create_pseudo_p ()
1502 || rtx_equal_p (operands[0], operands[1]))
0354e5d8 1503 ? operands[0] : gen_reg_rtx (<MODE>mode));
7cd5235b 1504
2bfcf297 1505 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1506 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8
GK		 1507 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1508
279bb624 1509 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1510 FAIL;
7cd5235b 1511
9ebbca7d
GK		 1512 /* The ordering here is important for the prolog expander.
1513 When space is allocated from the stack, adding 'low' first may
1514 produce a temporary deallocation (which would be bad). */
0354e5d8
GK		 1515 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1516 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
7cd5235b
MM		 1517 DONE;
1518 }
279bb624 1519})
7cd5235b 1520
0354e5d8
GK		 1521;; Discourage ai/addic because of carry but provide it in an alternative
1522;; allowing register zero as source.
1523(define_insn "*add<mode>3_internal1"
1524 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1525 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1526 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
7393f7f8 1527 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1fd4e8c1 1528 "@
deb9225a
RK		 1529 {cax|add} %0,%1,%2
1530 {cal %0,%2(%1)|addi %0,%1,%2}
1531 {ai|addic} %0,%1,%2
7cd5235b
MM		 1532 {cau|addis} %0,%1,%v2"
1533 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 1534
ee890fe2
SS		 1535(define_insn "addsi3_high"
1536 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1537 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1538 (high:SI (match_operand 2 "" ""))))]
1539 "TARGET_MACHO && !TARGET_64BIT"
1540 "{cau|addis} %0,%1,ha16(%2)"
1541 [(set_attr "length" "4")])
1542
0354e5d8 1543(define_insn "*add<mode>3_internal2"
cb8cc086 1544 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1545 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1546 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1547 (const_int 0)))
0354e5d8
GK		 1548 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1549 ""
deb9225a
RK		 1550 "@
1551 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1552 {ai.|addic.} %3,%1,%2
1553 #
1554 #"
a62bfff2 1555 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1556 (set_attr "length" "4,4,8,8")])
1557
1558(define_split
1559 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1560 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1561 (match_operand:GPR 2 "reg_or_short_operand" ""))
cb8cc086 1562 (const_int 0)))
0354e5d8
GK		 1563 (clobber (match_scratch:GPR 3 ""))]
1564 "reload_completed"
cb8cc086 1565 [(set (match_dup 3)
0354e5d8 1566 (plus:GPR (match_dup 1)
cb8cc086
MM		 1567 (match_dup 2)))
1568 (set (match_dup 0)
1569 (compare:CC (match_dup 3)
1570 (const_int 0)))]
1571 "")
7e69e155 1572
0354e5d8 1573(define_insn "*add<mode>3_internal3"
cb8cc086 1574 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1575 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1576 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1577 (const_int 0)))
0354e5d8
GK		 1578 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1579 (plus:P (match_dup 1)
1580 (match_dup 2)))]
1581 ""
deb9225a
RK		 1582 "@
1583 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1584 {ai.|addic.} %0,%1,%2
1585 #
1586 #"
a62bfff2 1587 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1588 (set_attr "length" "4,4,8,8")])
1589
1590(define_split
1591 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1592 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1593 (match_operand:P 2 "reg_or_short_operand" ""))
cb8cc086 1594 (const_int 0)))
0354e5d8
GK		 1595 (set (match_operand:P 0 "gpc_reg_operand" "")
1596 (plus:P (match_dup 1) (match_dup 2)))]
1597 "reload_completed"
cb8cc086 1598 [(set (match_dup 0)
0354e5d8
GK		 1599 (plus:P (match_dup 1)
1600 (match_dup 2)))
cb8cc086
MM		 1601 (set (match_dup 3)
1602 (compare:CC (match_dup 0)
1603 (const_int 0)))]
1604 "")
7e69e155 1605
f357808b
RK		 1606;; Split an add that we can't do in one insn into two insns, each of which
1607;; does one 16-bit part. This is used by combine. Note that the low-order
1608;; add should be last in case the result gets used in an address.
1609
1610(define_split
0354e5d8
GK		 1611 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1612 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1613 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1fd4e8c1 1614 ""
0354e5d8
GK		 1615 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1616 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1fd4e8c1 1617{
2bfcf297 1618 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1619 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8 1620 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1fd4e8c1 1621
e6ca2c17 1622 operands[4] = GEN_INT (low);
279bb624 1623 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1624 operands[3] = GEN_INT (rest);
b3a13419 1625 else if (can_create_pseudo_p ())
0354e5d8
GK		 1626 {
1627 operands[3] = gen_reg_rtx (DImode);
1628 emit_move_insn (operands[3], operands[2]);
1629 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1630 DONE;
1631 }
1632 else
1633 FAIL;
279bb624 1634})
1fd4e8c1 1635
0354e5d8
GK		 1636(define_insn "one_cmpl<mode>2"
1637 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1638 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1639 ""
ca7f5001
RK		 1640 "nor %0,%1,%1")
1641
1642(define_insn ""
52d3af72 1643 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 1644 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
ca7f5001 1645 (const_int 0)))
0354e5d8
GK		 1646 (clobber (match_scratch:P 2 "=r,r"))]
1647 ""
52d3af72
DE		 1648 "@
1649 nor. %2,%1,%1
1650 #"
1651 [(set_attr "type" "compare")
1652 (set_attr "length" "4,8")])
1653
1654(define_split
1655 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 1656 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1657 (const_int 0)))
0354e5d8
GK		 1658 (clobber (match_scratch:P 2 ""))]
1659 "reload_completed"
52d3af72 1660 [(set (match_dup 2)
0354e5d8 1661 (not:P (match_dup 1)))
52d3af72
DE		 1662 (set (match_dup 0)
1663 (compare:CC (match_dup 2)
1664 (const_int 0)))]
1665 "")
ca7f5001
RK		 1666
1667(define_insn ""
52d3af72 1668 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 1669 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 1670 (const_int 0)))
0354e5d8
GK		 1671 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1672 (not:P (match_dup 1)))]
1673 ""
52d3af72
DE		 1674 "@
1675 nor. %0,%1,%1
1676 #"
1677 [(set_attr "type" "compare")
1678 (set_attr "length" "4,8")])
1679
1680(define_split
1681 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 1682 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1683 (const_int 0)))
0354e5d8
GK		 1684 (set (match_operand:P 0 "gpc_reg_operand" "")
1685 (not:P (match_dup 1)))]
1686 "reload_completed"
52d3af72 1687 [(set (match_dup 0)
0354e5d8 1688 (not:P (match_dup 1)))
52d3af72
DE		 1689 (set (match_dup 2)
1690 (compare:CC (match_dup 0)
1691 (const_int 0)))]
1692 "")
1fd4e8c1
RK		 1693
1694(define_insn ""
3d91674b
RK		 1695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1696 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1697 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1698 "! TARGET_POWERPC"
ca7f5001 1699 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1700
deb9225a 1701(define_insn ""
0354e5d8
GK		 1702 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1703 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1704 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
deb9225a
RK		 1705 "TARGET_POWERPC"
1706 "@
1707 subf %0,%2,%1
1708 subfic %0,%2,%1")
1709
1fd4e8c1 1710(define_insn ""
cb8cc086
MM		 1711 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1712 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1713 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1714 (const_int 0)))
cb8cc086 1715 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1716 "! TARGET_POWERPC"
cb8cc086
MM		 1717 "@
1718 {sf.|subfc.} %3,%2,%1
1719 #"
1720 [(set_attr "type" "compare")
1721 (set_attr "length" "4,8")])
1fd4e8c1 1722
deb9225a 1723(define_insn ""
cb8cc086 1724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1725 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1726 (match_operand:P 2 "gpc_reg_operand" "r,r"))
deb9225a 1727 (const_int 0)))
0354e5d8
GK		 1728 (clobber (match_scratch:P 3 "=r,r"))]
1729 "TARGET_POWERPC"
cb8cc086
MM		 1730 "@
1731 subf. %3,%2,%1
1732 #"
a62bfff2 1733 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1734 (set_attr "length" "4,8")])
1735
1736(define_split
1737 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1738 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1739 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1740 (const_int 0)))
0354e5d8
GK		 1741 (clobber (match_scratch:P 3 ""))]
1742 "reload_completed"
cb8cc086 1743 [(set (match_dup 3)
0354e5d8 1744 (minus:P (match_dup 1)
cb8cc086
MM		 1745 (match_dup 2)))
1746 (set (match_dup 0)
1747 (compare:CC (match_dup 3)
1748 (const_int 0)))]
1749 "")
deb9225a 1750
1fd4e8c1 1751(define_insn ""
cb8cc086
MM		 1752 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1753 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1754 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1755 (const_int 0)))
cb8cc086 1756 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1757 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1758 "! TARGET_POWERPC"
cb8cc086
MM		 1759 "@
1760 {sf.|subfc.} %0,%2,%1
1761 #"
1762 [(set_attr "type" "compare")
1763 (set_attr "length" "4,8")])
815cdc52 1764
29ae5b89 1765(define_insn ""
cb8cc086 1766 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1767 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1768 (match_operand:P 2 "gpc_reg_operand" "r,r"))
815cdc52 1769 (const_int 0)))
0354e5d8
GK		 1770 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1771 (minus:P (match_dup 1)
cb8cc086 1772 (match_dup 2)))]
0354e5d8 1773 "TARGET_POWERPC"
90612787
DE		 1774 "@
1775 subf. %0,%2,%1
1776 #"
a62bfff2 1777 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1778 (set_attr "length" "4,8")])
1779
1780(define_split
1781 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1782 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1783 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1784 (const_int 0)))
0354e5d8
GK		 1785 (set (match_operand:P 0 "gpc_reg_operand" "")
1786 (minus:P (match_dup 1)
cb8cc086 1787 (match_dup 2)))]
0354e5d8 1788 "reload_completed"
cb8cc086 1789 [(set (match_dup 0)
0354e5d8 1790 (minus:P (match_dup 1)
cb8cc086
MM		 1791 (match_dup 2)))
1792 (set (match_dup 3)
1793 (compare:CC (match_dup 0)
1794 (const_int 0)))]
1795 "")
deb9225a 1796
0354e5d8
GK		 1797(define_expand "sub<mode>3"
1798 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1799 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
4ae234b0 1800 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1fd4e8c1 1801 ""
a0044fb1
RK		 1802 "
1803{
1804 if (GET_CODE (operands[2]) == CONST_INT)
1805 {
0354e5d8
GK		 1806 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1807 negate_rtx (<MODE>mode, operands[2])));
a0044fb1
RK		 1808 DONE;
1809 }
1810}")
1fd4e8c1
RK		 1811
1812;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1813;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1814;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1815;; combine.
1fd4e8c1
RK		 1816
1817(define_expand "sminsi3"
1818 [(set (match_dup 3)
cd2b37d9 1819 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1820 (match_operand:SI 2 "reg_or_short_operand" ""))
1821 (const_int 0)
1822 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1823 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1824 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1825 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1826 "
a3170dc6
AH		 1827{
1828 if (TARGET_ISEL)
1829 {
1830 operands[2] = force_reg (SImode, operands[2]);
1831 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1832 DONE;
1833 }
1834
1835 operands[3] = gen_reg_rtx (SImode);
1836}")
1fd4e8c1 1837
95ac8e67
RK		 1838(define_split
1839 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1840 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1841 (match_operand:SI 2 "reg_or_short_operand" "")))
1842 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1843 "TARGET_POWER"
95ac8e67
RK		 1844 [(set (match_dup 3)
1845 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1846 (const_int 0)
1847 (minus:SI (match_dup 2) (match_dup 1))))
1848 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1849 "")
1850
1fd4e8c1
RK		 1851(define_expand "smaxsi3"
1852 [(set (match_dup 3)
cd2b37d9 1853 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1854 (match_operand:SI 2 "reg_or_short_operand" ""))
1855 (const_int 0)
1856 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1857 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1858 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1859 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1860 "
a3170dc6
AH		 1861{
1862 if (TARGET_ISEL)
1863 {
1864 operands[2] = force_reg (SImode, operands[2]);
1865 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1866 DONE;
1867 }
1868 operands[3] = gen_reg_rtx (SImode);
1869}")
1fd4e8c1 1870
95ac8e67
RK		 1871(define_split
1872 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1873 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1874 (match_operand:SI 2 "reg_or_short_operand" "")))
1875 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1876 "TARGET_POWER"
95ac8e67
RK		 1877 [(set (match_dup 3)
1878 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1879 (const_int 0)
1880 (minus:SI (match_dup 2) (match_dup 1))))
1881 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1882 "")
1883
1fd4e8c1 1884(define_expand "uminsi3"
cd2b37d9 1885 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1886 (match_dup 5)))
cd2b37d9 1887 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1888 (match_dup 5)))
1fd4e8c1
RK		 1889 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1890 (const_int 0)
1891 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1892 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1893 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1894 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1895 "
bb68ff55 1896{
a3170dc6
AH		 1897 if (TARGET_ISEL)
1898 {
1899 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1900 DONE;
1901 }
bb68ff55
MM		 1902 operands[3] = gen_reg_rtx (SImode);
1903 operands[4] = gen_reg_rtx (SImode);
1904 operands[5] = GEN_INT (-2147483647 - 1);
1905}")
1fd4e8c1
RK		 1906
1907(define_expand "umaxsi3"
cd2b37d9 1908 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1909 (match_dup 5)))
cd2b37d9 1910 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1911 (match_dup 5)))
1fd4e8c1
RK		 1912 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1913 (const_int 0)
1914 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1915 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1916 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1917 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1918 "
bb68ff55 1919{
a3170dc6
AH		 1920 if (TARGET_ISEL)
1921 {
1922 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1923 DONE;
1924 }
bb68ff55
MM		 1925 operands[3] = gen_reg_rtx (SImode);
1926 operands[4] = gen_reg_rtx (SImode);
1927 operands[5] = GEN_INT (-2147483647 - 1);
1928}")
1fd4e8c1
RK		 1929
1930(define_insn ""
cd2b37d9
RK		 1931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1932 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1933 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1934 (const_int 0)
1935 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1936 "TARGET_POWER"
1fd4e8c1
RK		 1937 "doz%I2 %0,%1,%2")
1938
1939(define_insn ""
9ebbca7d 1940 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1941 (compare:CC
9ebbca7d
GK		 1942 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1943 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1944 (const_int 0)
1945 (minus:SI (match_dup 2) (match_dup 1)))
1946 (const_int 0)))
9ebbca7d 1947 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1948 "TARGET_POWER"
9ebbca7d
GK		 1949 "@
1950 doz%I2. %3,%1,%2
1951 #"
1952 [(set_attr "type" "delayed_compare")
1953 (set_attr "length" "4,8")])
1954
1955(define_split
1956 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1957 (compare:CC
1958 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1959 (match_operand:SI 2 "reg_or_short_operand" ""))
1960 (const_int 0)
1961 (minus:SI (match_dup 2) (match_dup 1)))
1962 (const_int 0)))
1963 (clobber (match_scratch:SI 3 ""))]
1964 "TARGET_POWER && reload_completed"
1965 [(set (match_dup 3)
1966 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1967 (const_int 0)
1968 (minus:SI (match_dup 2) (match_dup 1))))
1969 (set (match_dup 0)
1970 (compare:CC (match_dup 3)
1971 (const_int 0)))]
1972 "")
1fd4e8c1
RK		 1973
1974(define_insn ""
9ebbca7d 1975 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1976 (compare:CC
9ebbca7d
GK		 1977 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1978 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1979 (const_int 0)
1980 (minus:SI (match_dup 2) (match_dup 1)))
1981 (const_int 0)))
9ebbca7d 1982 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1983 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1984 (const_int 0)
1985 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1986 "TARGET_POWER"
9ebbca7d
GK		 1987 "@
1988 doz%I2. %0,%1,%2
1989 #"
1990 [(set_attr "type" "delayed_compare")
1991 (set_attr "length" "4,8")])
1992
1993(define_split
1994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1995 (compare:CC
1996 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1997 (match_operand:SI 2 "reg_or_short_operand" ""))
1998 (const_int 0)
1999 (minus:SI (match_dup 2) (match_dup 1)))
2000 (const_int 0)))
2001 (set (match_operand:SI 0 "gpc_reg_operand" "")
2002 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2003 (const_int 0)
2004 (minus:SI (match_dup 2) (match_dup 1))))]
2005 "TARGET_POWER && reload_completed"
2006 [(set (match_dup 0)
2007 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2008 (const_int 0)
2009 (minus:SI (match_dup 2) (match_dup 1))))
2010 (set (match_dup 3)
2011 (compare:CC (match_dup 0)
2012 (const_int 0)))]
2013 "")
1fd4e8c1
RK		 2014
2015;; We don't need abs with condition code because such comparisons should
2016;; never be done.
ea9be077
MM		 2017(define_expand "abssi2"
2018 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2019 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2020 ""
2021 "
2022{
a3170dc6
AH		 2023 if (TARGET_ISEL)
2024 {
2025 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2026 DONE;
2027 }
2028 else if (! TARGET_POWER)
ea9be077
MM		 2029 {
2030 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2031 DONE;
2032 }
2033}")
2034
ea112fc4 2035(define_insn "*abssi2_power"
cd2b37d9
RK		 2036 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2037 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 2038 "TARGET_POWER"
1fd4e8c1
RK		 2039 "abs %0,%1")
2040
a3170dc6
AH		 2041(define_insn_and_split "abssi2_isel"
2042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2043 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 2044 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 2045 (clobber (match_scratch:CC 3 "=y"))]
2046 "TARGET_ISEL"
2047 "#"
2048 "&& reload_completed"
2049 [(set (match_dup 2) (neg:SI (match_dup 1)))
2050 (set (match_dup 3)
2051 (compare:CC (match_dup 1)
2052 (const_int 0)))
2053 (set (match_dup 0)
2054 (if_then_else:SI (ge (match_dup 3)
2055 (const_int 0))
2056 (match_dup 1)
2057 (match_dup 2)))]
2058 "")
2059
ea112fc4 2060(define_insn_and_split "abssi2_nopower"
ea9be077 2061 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2062 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 2063 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 2064 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 2065 "#"
2066 "&& reload_completed"
ea9be077
MM		 2067 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2068 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2069 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 2070 "")
2071
463b558b 2072(define_insn "*nabs_power"
cd2b37d9
RK		 2073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2074 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 2075 "TARGET_POWER"
1fd4e8c1
RK		 2076 "nabs %0,%1")
2077
ea112fc4 2078(define_insn_and_split "*nabs_nopower"
ea9be077 2079 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2080 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 2081 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 2082 "! TARGET_POWER"
ea112fc4
DE		 2083 "#"
2084 "&& reload_completed"
ea9be077
MM		 2085 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2086 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2087 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 2088 "")
2089
0354e5d8
GK		 2090(define_expand "neg<mode>2"
2091 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2092 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2093 ""
2094 "")
2095
2096(define_insn "*neg<mode>2_internal"
2097 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2098 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 2099 ""
2100 "neg %0,%1")
2101
2102(define_insn ""
9ebbca7d 2103 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 2104 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 2105 (const_int 0)))
0354e5d8
GK		 2106 (clobber (match_scratch:P 2 "=r,r"))]
2107 ""
9ebbca7d
GK		 2108 "@
2109 neg. %2,%1
2110 #"
a62bfff2 2111 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2112 (set_attr "length" "4,8")])
2113
2114(define_split
2115 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 2116 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2117 (const_int 0)))
0354e5d8
GK		 2118 (clobber (match_scratch:P 2 ""))]
2119 "reload_completed"
9ebbca7d 2120 [(set (match_dup 2)
0354e5d8 2121 (neg:P (match_dup 1)))
9ebbca7d
GK		 2122 (set (match_dup 0)
2123 (compare:CC (match_dup 2)
2124 (const_int 0)))]
2125 "")
1fd4e8c1
RK		 2126
2127(define_insn ""
9ebbca7d 2128 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 2129 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 2130 (const_int 0)))
0354e5d8
GK		 2131 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2132 (neg:P (match_dup 1)))]
2133 ""
9ebbca7d
GK		 2134 "@
2135 neg. %0,%1
2136 #"
a62bfff2 2137 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2138 (set_attr "length" "4,8")])
2139
2140(define_split
2141 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 2142 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2143 (const_int 0)))
0354e5d8
GK		 2144 (set (match_operand:P 0 "gpc_reg_operand" "")
2145 (neg:P (match_dup 1)))]
66859ace 2146 "reload_completed"
9ebbca7d 2147 [(set (match_dup 0)
0354e5d8 2148 (neg:P (match_dup 1)))
9ebbca7d
GK		 2149 (set (match_dup 2)
2150 (compare:CC (match_dup 0)
2151 (const_int 0)))]
2152 "")
1fd4e8c1 2153
0354e5d8
GK		 2154(define_insn "clz<mode>2"
2155 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2156 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1b1edcfa 2157 ""
44cd321e
PS		 2158 "{cntlz|cntlz<wd>} %0,%1"
2159 [(set_attr "type" "cntlz")])
1b1edcfa 2160
0354e5d8 2161(define_expand "ctz<mode>2"
4977bab6 2162 [(set (match_dup 2)
e42ac3de 2163 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2164 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2165 (match_dup 2)))
1b1edcfa 2166 (clobber (scratch:CC))])
0354e5d8 2167 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2168 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2169 (minus:GPR (match_dup 5) (match_dup 4)))]
1fd4e8c1 2170 ""
4977bab6 2171 {
0354e5d8
GK		 2172 operands[2] = gen_reg_rtx (<MODE>mode);
2173 operands[3] = gen_reg_rtx (<MODE>mode);
2174 operands[4] = gen_reg_rtx (<MODE>mode);
2175 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
4977bab6 2176 })
6ae08853 2177
0354e5d8 2178(define_expand "ffs<mode>2"
1b1edcfa 2179 [(set (match_dup 2)
e42ac3de 2180 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2181 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2182 (match_dup 2)))
1b1edcfa 2183 (clobber (scratch:CC))])
0354e5d8 2184 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2185 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2186 (minus:GPR (match_dup 5) (match_dup 4)))]
4977bab6 2187 ""
1b1edcfa 2188 {
0354e5d8
GK		 2189 operands[2] = gen_reg_rtx (<MODE>mode);
2190 operands[3] = gen_reg_rtx (<MODE>mode);
2191 operands[4] = gen_reg_rtx (<MODE>mode);
2192 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1b1edcfa 2193 })
6ae08853 2194
432218ba
DE		 2195(define_insn "popcntb<mode>2"
2196 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2197 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2198 UNSPEC_POPCNTB))]
2199 "TARGET_POPCNTB"
2200 "popcntb %0,%1")
2201
565ef4ba 2202(define_expand "popcount<mode>2"
e42ac3de
RS		 2203 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2204 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2205 "TARGET_POPCNTB"
2206 {
2207 rs6000_emit_popcount (operands[0], operands[1]);
2208 DONE;
2209 })
2210
2211(define_expand "parity<mode>2"
e42ac3de
RS		 2212 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2213 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2214 "TARGET_POPCNTB"
2215 {
2216 rs6000_emit_parity (operands[0], operands[1]);
2217 DONE;
2218 })
2219
03f79051
DE		 2220(define_insn "bswapsi2"
2221 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2222 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2223 ""
2224 "@
2225 {lbrx|lwbrx} %0,%y1
2226 {stbrx|stwbrx} %1,%y0
2227 #"
2228 [(set_attr "length" "4,4,12")])
2229
2230(define_split
2231 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2232 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2233 "reload_completed"
2234 [(set (match_dup 0)
2235 (rotate:SI (match_dup 1) (const_int 8)))
2236 (set (zero_extract:SI (match_dup 0)
2237 (const_int 8)
2238 (const_int 0))
2239 (match_dup 1))
2240 (set (zero_extract:SI (match_dup 0)
2241 (const_int 8)
2242 (const_int 16))
2243 (rotate:SI (match_dup 1)
2244 (const_int 16)))]
2245 "")
2246
ca7f5001
RK		 2247(define_expand "mulsi3"
2248 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2249 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2250 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2251 ""
2252 "
2253{
2254 if (TARGET_POWER)
68b40e7e 2255 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 2256 else
68b40e7e 2257 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 2258 DONE;
2259}")
2260
68b40e7e 2261(define_insn "mulsi3_mq"
cd2b37d9
RK		 2262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2263 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 2264 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2265 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 2266 "TARGET_POWER"
2267 "@
2268 {muls|mullw} %0,%1,%2
2269 {muli|mulli} %0,%1,%2"
6ae08853 2270 [(set (attr "type")
c859cda6
DJ		 2271 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2272 (const_string "imul3")
6ae08853 2273 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2274 (const_string "imul2")]
2275 (const_string "imul")))])
ca7f5001 2276
68b40e7e 2277(define_insn "mulsi3_no_mq"
ca7f5001
RK		 2278 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2279 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2280 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 2281 "! TARGET_POWER"
1fd4e8c1 2282 "@
d904e9ed
RK		 2283 {muls|mullw} %0,%1,%2
2284 {muli|mulli} %0,%1,%2"
6ae08853 2285 [(set (attr "type")
c859cda6
DJ		 2286 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2287 (const_string "imul3")
6ae08853 2288 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2289 (const_string "imul2")]
2290 (const_string "imul")))])
1fd4e8c1 2291
9259f3b0 2292(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 2293 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2294 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2295 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2296 (const_int 0)))
9ebbca7d
GK		 2297 (clobber (match_scratch:SI 3 "=r,r"))
2298 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2299 "TARGET_POWER"
9ebbca7d
GK		 2300 "@
2301 {muls.|mullw.} %3,%1,%2
2302 #"
9259f3b0 2303 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2304 (set_attr "length" "4,8")])
2305
2306(define_split
2307 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2308 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2309 (match_operand:SI 2 "gpc_reg_operand" ""))
2310 (const_int 0)))
2311 (clobber (match_scratch:SI 3 ""))
2312 (clobber (match_scratch:SI 4 ""))]
2313 "TARGET_POWER && reload_completed"
2314 [(parallel [(set (match_dup 3)
2315 (mult:SI (match_dup 1) (match_dup 2)))
2316 (clobber (match_dup 4))])
2317 (set (match_dup 0)
2318 (compare:CC (match_dup 3)
2319 (const_int 0)))]
2320 "")
ca7f5001 2321
9259f3b0 2322(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 2323 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2324 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2325 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2326 (const_int 0)))
9ebbca7d 2327 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 2328 "! TARGET_POWER"
9ebbca7d
GK		 2329 "@
2330 {muls.|mullw.} %3,%1,%2
2331 #"
9259f3b0 2332 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2333 (set_attr "length" "4,8")])
2334
2335(define_split
2336 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2337 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2338 (match_operand:SI 2 "gpc_reg_operand" ""))
2339 (const_int 0)))
2340 (clobber (match_scratch:SI 3 ""))]
2341 "! TARGET_POWER && reload_completed"
2342 [(set (match_dup 3)
2343 (mult:SI (match_dup 1) (match_dup 2)))
2344 (set (match_dup 0)
2345 (compare:CC (match_dup 3)
2346 (const_int 0)))]
2347 "")
1fd4e8c1 2348
9259f3b0 2349(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 2350 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2351 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2352 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2353 (const_int 0)))
9ebbca7d 2354 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 2355 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 2356 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2357 "TARGET_POWER"
9ebbca7d
GK		 2358 "@
2359 {muls.|mullw.} %0,%1,%2
2360 #"
9259f3b0 2361 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2362 (set_attr "length" "4,8")])
2363
2364(define_split
2365 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2366 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2367 (match_operand:SI 2 "gpc_reg_operand" ""))
2368 (const_int 0)))
2369 (set (match_operand:SI 0 "gpc_reg_operand" "")
2370 (mult:SI (match_dup 1) (match_dup 2)))
2371 (clobber (match_scratch:SI 4 ""))]
2372 "TARGET_POWER && reload_completed"
2373 [(parallel [(set (match_dup 0)
2374 (mult:SI (match_dup 1) (match_dup 2)))
2375 (clobber (match_dup 4))])
2376 (set (match_dup 3)
2377 (compare:CC (match_dup 0)
2378 (const_int 0)))]
2379 "")
ca7f5001 2380
9259f3b0 2381(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 2382 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2383 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2384 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2385 (const_int 0)))
9ebbca7d 2386 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 2387 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 2388 "! TARGET_POWER"
9ebbca7d
GK		 2389 "@
2390 {muls.|mullw.} %0,%1,%2
2391 #"
9259f3b0 2392 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2393 (set_attr "length" "4,8")])
2394
2395(define_split
2396 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2397 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2398 (match_operand:SI 2 "gpc_reg_operand" ""))
2399 (const_int 0)))
2400 (set (match_operand:SI 0 "gpc_reg_operand" "")
2401 (mult:SI (match_dup 1) (match_dup 2)))]
2402 "! TARGET_POWER && reload_completed"
2403 [(set (match_dup 0)
2404 (mult:SI (match_dup 1) (match_dup 2)))
2405 (set (match_dup 3)
2406 (compare:CC (match_dup 0)
2407 (const_int 0)))]
2408 "")
1fd4e8c1
RK		 2409
2410;; Operand 1 is divided by operand 2; quotient goes to operand
2411;; 0 and remainder to operand 3.
2412;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2413
8ffd9c51
RK		 2414(define_expand "divmodsi4"
2415 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2416 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2417 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 2418 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 2419 (mod:SI (match_dup 1) (match_dup 2)))])]
2420 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2421 "
2422{
2423 if (! TARGET_POWER && ! TARGET_POWERPC)
2424 {
39403d82
DE		 2425 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2426 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2427 emit_insn (gen_divss_call ());
39403d82
DE		 2428 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2429 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 2430 DONE;
2431 }
2432}")
deb9225a 2433
bb157ff4 2434(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 2435 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2436 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2437 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 2438 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 2439 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 2440 "TARGET_POWER"
cfb557c4
RK		 2441 "divs %0,%1,%2"
2442 [(set_attr "type" "idiv")])
1fd4e8c1 2443
4ae234b0
GK		 2444(define_expand "udiv<mode>3"
2445 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2446 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2447 (match_operand:GPR 2 "gpc_reg_operand" "")))]
8ffd9c51
RK		 2448 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2449 "
2450{
2451 if (! TARGET_POWER && ! TARGET_POWERPC)
2452 {
39403d82
DE		 2453 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2454 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2455 emit_insn (gen_quous_call ());
39403d82 2456 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2457 DONE;
2458 }
f192bf8b
DE		 2459 else if (TARGET_POWER)
2460 {
2461 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2462 DONE;
2463 }
8ffd9c51 2464}")
deb9225a 2465
f192bf8b
DE		 2466(define_insn "udivsi3_mq"
2467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2468 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2469 (match_operand:SI 2 "gpc_reg_operand" "r")))
2470 (clobber (match_scratch:SI 3 "=q"))]
2471 "TARGET_POWERPC && TARGET_POWER"
2472 "divwu %0,%1,%2"
2473 [(set_attr "type" "idiv")])
2474
2475(define_insn "*udivsi3_no_mq"
4ae234b0
GK		 2476 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2477 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2478 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2479 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2480 "div<wd>u %0,%1,%2"
44cd321e
PS		 2481 [(set (attr "type")
2482 (cond [(match_operand:SI 0 "" "")
2483 (const_string "idiv")]
2484 (const_string "ldiv")))])
2485
ca7f5001 2486
1fd4e8c1 2487;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 2488;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 2489;; used; for PowerPC, force operands into register and do a normal divide;
2490;; for AIX common-mode, use quoss call on register operands.
4ae234b0
GK		 2491(define_expand "div<mode>3"
2492 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2493 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2494 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1fd4e8c1
RK		 2495 ""
2496 "
2497{
ca7f5001 2498 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 2499 && INTVAL (operands[2]) > 0
ca7f5001
RK		 2500 && exact_log2 (INTVAL (operands[2])) >= 0)
2501 ;
b6c9286a 2502 else if (TARGET_POWERPC)
f192bf8b 2503 {
99e8e649 2504 operands[2] = force_reg (<MODE>mode, operands[2]);
f192bf8b
DE		 2505 if (TARGET_POWER)
2506 {
2507 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2508 DONE;
2509 }
2510 }
b6c9286a 2511 else if (TARGET_POWER)
1fd4e8c1 2512 FAIL;
405c5495 2513 else
8ffd9c51 2514 {
39403d82
DE		 2515 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2516 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2517 emit_insn (gen_quoss_call ());
39403d82 2518 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2519 DONE;
2520 }
1fd4e8c1
RK		 2521}")
2522
f192bf8b
DE		 2523(define_insn "divsi3_mq"
2524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2525 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2526 (match_operand:SI 2 "gpc_reg_operand" "r")))
2527 (clobber (match_scratch:SI 3 "=q"))]
2528 "TARGET_POWERPC && TARGET_POWER"
2529 "divw %0,%1,%2"
2530 [(set_attr "type" "idiv")])
2531
4ae234b0
GK		 2532(define_insn "*div<mode>3_no_mq"
2533 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2534 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2535 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2536 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2537 "div<wd> %0,%1,%2"
44cd321e
PS		 2538 [(set (attr "type")
2539 (cond [(match_operand:SI 0 "" "")
2540 (const_string "idiv")]
2541 (const_string "ldiv")))])
f192bf8b 2542
4ae234b0
GK		 2543(define_expand "mod<mode>3"
2544 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2545 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2546 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
39b52ba2 2547 ""
1fd4e8c1
RK		 2548 "
2549{
481c7efa 2550 int i;
39b52ba2
RK		 2551 rtx temp1;
2552 rtx temp2;
2553
2bfcf297 2554 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 2555 || INTVAL (operands[2]) <= 0
2bfcf297 2556 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 2557 FAIL;
2558
4ae234b0
GK		 2559 temp1 = gen_reg_rtx (<MODE>mode);
2560 temp2 = gen_reg_rtx (<MODE>mode);
1fd4e8c1 2561
4ae234b0
GK		 2562 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2563 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2564 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
85644414 2565 DONE;
1fd4e8c1
RK		 2566}")
2567
2568(define_insn ""
4ae234b0
GK		 2569 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2570 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2571 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2bfcf297 2572 ""
4ae234b0 2573 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
943c15ed
DE		 2574 [(set_attr "type" "two")
2575 (set_attr "length" "8")])
1fd4e8c1
RK		 2576
2577(define_insn ""
9ebbca7d 2578 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2579 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2580 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2581 (const_int 0)))
4ae234b0 2582 (clobber (match_scratch:P 3 "=r,r"))]
2bfcf297 2583 ""
9ebbca7d 2584 "@
4ae234b0 2585 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
9ebbca7d 2586 #"
b19003d8 2587 [(set_attr "type" "compare")
9ebbca7d
GK		 2588 (set_attr "length" "8,12")])
2589
2590(define_split
2591 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2592 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2593 (match_operand:GPR 2 "exact_log2_cint_operand"
2594 ""))
9ebbca7d 2595 (const_int 0)))
4ae234b0 2596 (clobber (match_scratch:GPR 3 ""))]
2bfcf297 2597 "reload_completed"
9ebbca7d 2598 [(set (match_dup 3)
4ae234b0 2599 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2600 (set (match_dup 0)
2601 (compare:CC (match_dup 3)
2602 (const_int 0)))]
2603 "")
1fd4e8c1
RK		 2604
2605(define_insn ""
9ebbca7d 2606 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2607 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2608 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2609 (const_int 0)))
4ae234b0
GK		 2610 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2611 (div:P (match_dup 1) (match_dup 2)))]
2bfcf297 2612 ""
9ebbca7d 2613 "@
4ae234b0 2614 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
9ebbca7d 2615 #"
b19003d8 2616 [(set_attr "type" "compare")
9ebbca7d
GK		 2617 (set_attr "length" "8,12")])
2618
2619(define_split
2620 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2621 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2622 (match_operand:GPR 2 "exact_log2_cint_operand"
2623 ""))
9ebbca7d 2624 (const_int 0)))
4ae234b0
GK		 2625 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2626 (div:GPR (match_dup 1) (match_dup 2)))]
2bfcf297 2627 "reload_completed"
9ebbca7d 2628 [(set (match_dup 0)
4ae234b0 2629 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2630 (set (match_dup 3)
2631 (compare:CC (match_dup 0)
2632 (const_int 0)))]
2633 "")
1fd4e8c1
RK		 2634
2635(define_insn ""
cd2b37d9 2636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2637 (udiv:SI
996a5f59 2638 (plus:DI (ashift:DI
cd2b37d9 2639 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2640 (const_int 32))
23a900dc 2641 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2642 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2643 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2644 (umod:SI
996a5f59 2645 (plus:DI (ashift:DI
1fd4e8c1 2646 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2647 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2648 (match_dup 3)))]
ca7f5001 2649 "TARGET_POWER"
cfb557c4
RK		 2650 "div %0,%1,%3"
2651 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2652
2653;; To do unsigned divide we handle the cases of the divisor looking like a
2654;; negative number. If it is a constant that is less than 2**31, we don't
2655;; have to worry about the branches. So make a few subroutines here.
2656;;
2657;; First comes the normal case.
2658(define_expand "udivmodsi4_normal"
2659 [(set (match_dup 4) (const_int 0))
2660 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2661 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2662 (const_int 32))
2663 (zero_extend:DI (match_operand:SI 1 "" "")))
2664 (match_operand:SI 2 "" "")))
2665 (set (match_operand:SI 3 "" "")
996a5f59 2666 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2667 (const_int 32))
2668 (zero_extend:DI (match_dup 1)))
2669 (match_dup 2)))])]
ca7f5001 2670 "TARGET_POWER"
1fd4e8c1
RK		 2671 "
2672{ operands[4] = gen_reg_rtx (SImode); }")
2673
2674;; This handles the branches.
2675(define_expand "udivmodsi4_tests"
2676 [(set (match_operand:SI 0 "" "") (const_int 0))
2677 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2678 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2679 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2680 (label_ref (match_operand:SI 4 "" "")) (pc)))
2681 (set (match_dup 0) (const_int 1))
2682 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2683 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2684 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2685 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2686 "TARGET_POWER"
1fd4e8c1
RK		 2687 "
2688{ operands[5] = gen_reg_rtx (CCUNSmode);
2689 operands[6] = gen_reg_rtx (CCmode);
2690}")
2691
2692(define_expand "udivmodsi4"
cd2b37d9
RK		 2693 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2694 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2695 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2696 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2697 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2698 ""
1fd4e8c1
RK		 2699 "
2700{
2701 rtx label = 0;
2702
8ffd9c51 2703 if (! TARGET_POWER)
c4d38ccb
MM		 2704 {
2705 if (! TARGET_POWERPC)
2706 {
39403d82
DE		 2707 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2708 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2709 emit_insn (gen_divus_call ());
39403d82
DE		 2710 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2711 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2712 DONE;
2713 }
2714 else
2715 FAIL;
2716 }
0081a354 2717
1fd4e8c1
RK		 2718 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2719 {
2720 operands[2] = force_reg (SImode, operands[2]);
2721 label = gen_label_rtx ();
2722 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2723 operands[3], label));
2724 }
2725 else
2726 operands[2] = force_reg (SImode, operands[2]);
2727
2728 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2729 operands[3]));
2730 if (label)
2731 emit_label (label);
2732
2733 DONE;
2734}")
0081a354 2735
fada905b
MM		 2736;; AIX architecture-independent common-mode multiply (DImode),
2737;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2738;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2739;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2740;; assumed unused if generating common-mode, so ignore.
2741(define_insn "mulh_call"
2742 [(set (reg:SI 3)
2743 (truncate:SI
2744 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2745 (sign_extend:DI (reg:SI 4)))
2746 (const_int 32))))
1de43f85 2747 (clobber (reg:SI LR_REGNO))]
fada905b 2748 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2749 "bla __mulh"
2750 [(set_attr "type" "imul")])
fada905b
MM		 2751
2752(define_insn "mull_call"
2753 [(set (reg:DI 3)
2754 (mult:DI (sign_extend:DI (reg:SI 3))
2755 (sign_extend:DI (reg:SI 4))))
1de43f85 2756 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2757 (clobber (reg:SI 0))]
2758 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2759 "bla __mull"
2760 [(set_attr "type" "imul")])
fada905b
MM		 2761
2762(define_insn "divss_call"
2763 [(set (reg:SI 3)
2764 (div:SI (reg:SI 3) (reg:SI 4)))
2765 (set (reg:SI 4)
2766 (mod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2767 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2768 (clobber (reg:SI 0))]
2769 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2770 "bla __divss"
2771 [(set_attr "type" "idiv")])
fada905b
MM		 2772
2773(define_insn "divus_call"
8ffd9c51
RK		 2774 [(set (reg:SI 3)
2775 (udiv:SI (reg:SI 3) (reg:SI 4)))
2776 (set (reg:SI 4)
2777 (umod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2778 (clobber (reg:SI LR_REGNO))
fada905b 2779 (clobber (reg:SI 0))
e65a3857 2780 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2781 (clobber (reg:CC CR1_REGNO))]
fada905b 2782 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2783 "bla __divus"
2784 [(set_attr "type" "idiv")])
fada905b
MM		 2785
2786(define_insn "quoss_call"
2787 [(set (reg:SI 3)
2788 (div:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2789 (clobber (reg:SI LR_REGNO))]
8ffd9c51 2790 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2791 "bla __quoss"
2792 [(set_attr "type" "idiv")])
0081a354 2793
fada905b
MM		 2794(define_insn "quous_call"
2795 [(set (reg:SI 3)
2796 (udiv:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2797 (clobber (reg:SI LR_REGNO))
fada905b 2798 (clobber (reg:SI 0))
e65a3857 2799 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2800 (clobber (reg:CC CR1_REGNO))]
fada905b 2801 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2802 "bla __quous"
2803 [(set_attr "type" "idiv")])
8ffd9c51 2804\f
bb21487f 2805;; Logical instructions
dfbdccdb
GK		 2806;; The logical instructions are mostly combined by using match_operator,
2807;; but the plain AND insns are somewhat different because there is no
2808;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2809;; those rotate-and-mask operations. Thus, the AND insns come first.
2810
29ae5b89
JL		 2811(define_insn "andsi3"
2812 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2813 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2814 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2815 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1fd4e8c1
RK		 2816 ""
2817 "@
2818 and %0,%1,%2
ca7f5001
RK		 2819 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2820 {andil.|andi.} %0,%1,%b2
520308bc
DE		 2821 {andiu.|andis.} %0,%1,%u2"
2822 [(set_attr "type" "*,*,compare,compare")])
52d3af72
DE		 2823
2824;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2825;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2826;; machines causes an execution serialization
1fd4e8c1 2827
7cd5235b 2828(define_insn "*andsi3_internal2"
52d3af72
DE		 2829 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2830 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2831 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2832 (const_int 0)))
52d3af72
DE		 2833 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2834 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2835 "TARGET_32BIT"
1fd4e8c1
RK		 2836 "@
2837 and. %3,%1,%2
ca7f5001
RK		 2838 {andil.|andi.} %3,%1,%b2
2839 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2840 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2841 #
2842 #
2843 #
2844 #"
2845 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2846 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2847
0ba1b2ff
AM		 2848(define_insn "*andsi3_internal3"
2849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2850 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2851 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2852 (const_int 0)))
2853 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2854 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2855 "TARGET_64BIT"
0ba1b2ff
AM		 2856 "@
2857 #
2858 {andil.|andi.} %3,%1,%b2
2859 {andiu.|andis.} %3,%1,%u2
2860 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2861 #
2862 #
2863 #
2864 #"
2865 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2866 (set_attr "length" "8,4,4,4,8,8,8,8")])
2867
52d3af72
DE		 2868(define_split
2869 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2870 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2871 (match_operand:GPR 2 "and_operand" ""))
1fd4e8c1 2872 (const_int 0)))
4ae234b0 2873 (clobber (match_scratch:GPR 3 ""))
52d3af72 2874 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2875 "reload_completed"
52d3af72 2876 [(parallel [(set (match_dup 3)
4ae234b0
GK		 2877 (and:<MODE> (match_dup 1)
2878 (match_dup 2)))
52d3af72
DE		 2879 (clobber (match_dup 4))])
2880 (set (match_dup 0)
2881 (compare:CC (match_dup 3)
2882 (const_int 0)))]
2883 "")
2884
0ba1b2ff
AM		 2885;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2886;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2887
2888(define_split
2889 [(set (match_operand:CC 0 "cc_reg_operand" "")
2890 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2891 (match_operand:SI 2 "gpc_reg_operand" ""))
2892 (const_int 0)))
2893 (clobber (match_scratch:SI 3 ""))
2894 (clobber (match_scratch:CC 4 ""))]
2895 "TARGET_POWERPC64 && reload_completed"
2896 [(parallel [(set (match_dup 3)
2897 (and:SI (match_dup 1)
2898 (match_dup 2)))
2899 (clobber (match_dup 4))])
2900 (set (match_dup 0)
2901 (compare:CC (match_dup 3)
2902 (const_int 0)))]
2903 "")
2904
2905(define_insn "*andsi3_internal4"
52d3af72
DE		 2906 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2907 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2908 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2909 (const_int 0)))
2910 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2911 (and:SI (match_dup 1)
2912 (match_dup 2)))
2913 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2914 "TARGET_32BIT"
1fd4e8c1
RK		 2915 "@
2916 and. %0,%1,%2
ca7f5001
RK		 2917 {andil.|andi.} %0,%1,%b2
2918 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2919 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2920 #
2921 #
2922 #
2923 #"
2924 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2925 (set_attr "length" "4,4,4,4,8,8,8,8")])
2926
0ba1b2ff
AM		 2927(define_insn "*andsi3_internal5"
2928 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2929 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2930 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2931 (const_int 0)))
2932 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2933 (and:SI (match_dup 1)
2934 (match_dup 2)))
2935 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2936 "TARGET_64BIT"
0ba1b2ff
AM		 2937 "@
2938 #
2939 {andil.|andi.} %0,%1,%b2
2940 {andiu.|andis.} %0,%1,%u2
2941 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2942 #
2943 #
2944 #
2945 #"
2946 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2947 (set_attr "length" "8,4,4,4,8,8,8,8")])
2948
52d3af72
DE		 2949(define_split
2950 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2951 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2952 (match_operand:SI 2 "and_operand" ""))
2953 (const_int 0)))
2954 (set (match_operand:SI 0 "gpc_reg_operand" "")
2955 (and:SI (match_dup 1)
2956 (match_dup 2)))
2957 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2958 "reload_completed"
52d3af72
DE		 2959 [(parallel [(set (match_dup 0)
2960 (and:SI (match_dup 1)
2961 (match_dup 2)))
2962 (clobber (match_dup 4))])
2963 (set (match_dup 3)
2964 (compare:CC (match_dup 0)
2965 (const_int 0)))]
2966 "")
1fd4e8c1 2967
0ba1b2ff
AM		 2968(define_split
2969 [(set (match_operand:CC 3 "cc_reg_operand" "")
2970 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2971 (match_operand:SI 2 "gpc_reg_operand" ""))
2972 (const_int 0)))
2973 (set (match_operand:SI 0 "gpc_reg_operand" "")
2974 (and:SI (match_dup 1)
2975 (match_dup 2)))
2976 (clobber (match_scratch:CC 4 ""))]
2977 "TARGET_POWERPC64 && reload_completed"
2978 [(parallel [(set (match_dup 0)
2979 (and:SI (match_dup 1)
2980 (match_dup 2)))
2981 (clobber (match_dup 4))])
2982 (set (match_dup 3)
2983 (compare:CC (match_dup 0)
2984 (const_int 0)))]
2985 "")
2986
2987;; Handle the PowerPC64 rlwinm corner case
2988
2989(define_insn_and_split "*andsi3_internal6"
2990 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2991 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2992 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2993 "TARGET_POWERPC64"
2994 "#"
2995 "TARGET_POWERPC64"
2996 [(set (match_dup 0)
2997 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2998 (match_dup 4)))
2999 (set (match_dup 0)
3000 (rotate:SI (match_dup 0) (match_dup 5)))]
3001 "
3002{
3003 int mb = extract_MB (operands[2]);
3004 int me = extract_ME (operands[2]);
3005 operands[3] = GEN_INT (me + 1);
3006 operands[5] = GEN_INT (32 - (me + 1));
3007 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3008}"
3009 [(set_attr "length" "8")])
3010
7cd5235b 3011(define_expand "iorsi3"
cd2b37d9 3012 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3013 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3014 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 3015 ""
f357808b
RK		 3016 "
3017{
7cd5235b 3018 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3019 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3020 {
3021 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3022 rtx tmp = ((!can_create_pseudo_p ()
3023 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3024 ? operands[0] : gen_reg_rtx (SImode));
3025
a260abc9
DE		 3026 emit_insn (gen_iorsi3 (tmp, operands[1],
3027 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3028 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3029 DONE;
3030 }
f357808b
RK		 3031}")
3032
7cd5235b 3033(define_expand "xorsi3"
cd2b37d9 3034 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3035 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3036 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 3037 ""
7cd5235b 3038 "
1fd4e8c1 3039{
7cd5235b 3040 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3041 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3042 {
3043 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3044 rtx tmp = ((!can_create_pseudo_p ()
3045 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3046 ? operands[0] : gen_reg_rtx (SImode));
3047
a260abc9
DE		 3048 emit_insn (gen_xorsi3 (tmp, operands[1],
3049 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3050 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3051 DONE;
3052 }
1fd4e8c1
RK		 3053}")
3054
dfbdccdb 3055(define_insn "*boolsi3_internal1"
7cd5235b 3056 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 3057 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3058 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3059 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 3060 ""
3061 "@
dfbdccdb
GK		 3062 %q3 %0,%1,%2
3063 {%q3il|%q3i} %0,%1,%b2
3064 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 3065
dfbdccdb 3066(define_insn "*boolsi3_internal2"
52d3af72 3067 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 3068 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 3069 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3070 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3071 (const_int 0)))
52d3af72 3072 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3073 "TARGET_32BIT"
52d3af72 3074 "@
dfbdccdb 3075 %q4. %3,%1,%2
52d3af72
DE		 3076 #"
3077 [(set_attr "type" "compare")
3078 (set_attr "length" "4,8")])
3079
3080(define_split
3081 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3082 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3083 [(match_operand:SI 1 "gpc_reg_operand" "")
3084 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3085 (const_int 0)))
52d3af72 3086 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3087 "TARGET_32BIT && reload_completed"
dfbdccdb 3088 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3089 (set (match_dup 0)
3090 (compare:CC (match_dup 3)
3091 (const_int 0)))]
3092 "")
815cdc52 3093
dfbdccdb 3094(define_insn "*boolsi3_internal3"
52d3af72 3095 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3096 (compare:CC (match_operator:SI 4 "boolean_operator"
3097 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3098 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3099 (const_int 0)))
52d3af72 3100 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3101 (match_dup 4))]
4b8a63d6 3102 "TARGET_32BIT"
52d3af72 3103 "@
dfbdccdb 3104 %q4. %0,%1,%2
52d3af72
DE		 3105 #"
3106 [(set_attr "type" "compare")
3107 (set_attr "length" "4,8")])
3108
3109(define_split
e72247f4 3110 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3111 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3112 [(match_operand:SI 1 "gpc_reg_operand" "")
3113 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3114 (const_int 0)))
75540af0 3115 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3116 (match_dup 4))]
4b8a63d6 3117 "TARGET_32BIT && reload_completed"
dfbdccdb 3118 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3119 (set (match_dup 3)
3120 (compare:CC (match_dup 0)
3121 (const_int 0)))]
3122 "")
1fd4e8c1 3123
6ae08853 3124;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 3125;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 3126
3127(define_split
3128 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 3129 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3130 [(match_operand:SI 1 "gpc_reg_operand" "")
3131 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 3132 ""
dfbdccdb
GK		 3133 [(set (match_dup 0) (match_dup 4))
3134 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 3135"
3136{
dfbdccdb
GK		 3137 rtx i;
3138 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1c563bed 3139 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3140 operands[1], i);
dfbdccdb 3141 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
1c563bed 3142 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3143 operands[0], i);
a260abc9
DE		 3144}")
3145
dfbdccdb 3146(define_insn "*boolcsi3_internal1"
cd2b37d9 3147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3148 (match_operator:SI 3 "boolean_operator"
3149 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3150 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 3151 ""
dfbdccdb 3152 "%q3 %0,%2,%1")
1fd4e8c1 3153
dfbdccdb 3154(define_insn "*boolcsi3_internal2"
52d3af72 3155 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3156 (compare:CC (match_operator:SI 4 "boolean_operator"
3157 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3158 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3159 (const_int 0)))
52d3af72 3160 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3161 "TARGET_32BIT"
52d3af72 3162 "@
dfbdccdb 3163 %q4. %3,%2,%1
52d3af72
DE		 3164 #"
3165 [(set_attr "type" "compare")
3166 (set_attr "length" "4,8")])
3167
3168(define_split
3169 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3170 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3171 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3172 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3173 (const_int 0)))
52d3af72 3174 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3175 "TARGET_32BIT && reload_completed"
dfbdccdb 3176 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3177 (set (match_dup 0)
3178 (compare:CC (match_dup 3)
3179 (const_int 0)))]
3180 "")
1fd4e8c1 3181
dfbdccdb 3182(define_insn "*boolcsi3_internal3"
52d3af72 3183 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3184 (compare:CC (match_operator:SI 4 "boolean_operator"
3185 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3186 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3187 (const_int 0)))
52d3af72 3188 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3189 (match_dup 4))]
4b8a63d6 3190 "TARGET_32BIT"
52d3af72 3191 "@
dfbdccdb 3192 %q4. %0,%2,%1
52d3af72
DE		 3193 #"
3194 [(set_attr "type" "compare")
3195 (set_attr "length" "4,8")])
3196
3197(define_split
e72247f4 3198 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3199 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3200 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3201 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3202 (const_int 0)))
75540af0 3203 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3204 (match_dup 4))]
4b8a63d6 3205 "TARGET_32BIT && reload_completed"
dfbdccdb 3206 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3207 (set (match_dup 3)
3208 (compare:CC (match_dup 0)
3209 (const_int 0)))]
3210 "")
3211
dfbdccdb 3212(define_insn "*boolccsi3_internal1"
cd2b37d9 3213 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3214 (match_operator:SI 3 "boolean_operator"
3215 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3216 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 3217 ""
dfbdccdb 3218 "%q3 %0,%1,%2")
1fd4e8c1 3219
dfbdccdb 3220(define_insn "*boolccsi3_internal2"
52d3af72 3221 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3222 (compare:CC (match_operator:SI 4 "boolean_operator"
3223 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3224 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3225 (const_int 0)))
52d3af72 3226 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3227 "TARGET_32BIT"
52d3af72 3228 "@
dfbdccdb 3229 %q4. %3,%1,%2
52d3af72
DE		 3230 #"
3231 [(set_attr "type" "compare")
3232 (set_attr "length" "4,8")])
3233
3234(define_split
3235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3236 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3237 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3238 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3239 (const_int 0)))
52d3af72 3240 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3241 "TARGET_32BIT && reload_completed"
dfbdccdb 3242 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3243 (set (match_dup 0)
3244 (compare:CC (match_dup 3)
3245 (const_int 0)))]
3246 "")
1fd4e8c1 3247
dfbdccdb 3248(define_insn "*boolccsi3_internal3"
52d3af72 3249 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3250 (compare:CC (match_operator:SI 4 "boolean_operator"
3251 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3252 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3253 (const_int 0)))
52d3af72 3254 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3255 (match_dup 4))]
4b8a63d6 3256 "TARGET_32BIT"
52d3af72 3257 "@
dfbdccdb 3258 %q4. %0,%1,%2
52d3af72
DE		 3259 #"
3260 [(set_attr "type" "compare")
3261 (set_attr "length" "4,8")])
3262
3263(define_split
e72247f4 3264 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3265 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3266 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3267 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3268 (const_int 0)))
75540af0 3269 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3270 (match_dup 4))]
4b8a63d6 3271 "TARGET_32BIT && reload_completed"
dfbdccdb 3272 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3273 (set (match_dup 3)
3274 (compare:CC (match_dup 0)
3275 (const_int 0)))]
3276 "")
1fd4e8c1
RK		 3277
3278;; maskir insn. We need four forms because things might be in arbitrary
3279;; orders. Don't define forms that only set CR fields because these
3280;; would modify an input register.
3281
7cd5235b 3282(define_insn "*maskir_internal1"
cd2b37d9 3283 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3284 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3285 (match_operand:SI 1 "gpc_reg_operand" "0"))
3286 (and:SI (match_dup 2)
cd2b37d9 3287 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 3288 "TARGET_POWER"
01def764 3289 "maskir %0,%3,%2")
1fd4e8c1 3290
7cd5235b 3291(define_insn "*maskir_internal2"
242e8072 3292 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3293 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3294 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 3295 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 3296 (match_dup 2))))]
ca7f5001 3297 "TARGET_POWER"
01def764 3298 "maskir %0,%3,%2")
1fd4e8c1 3299
7cd5235b 3300(define_insn "*maskir_internal3"
cd2b37d9 3301 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 3302 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 3303 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 3304 (and:SI (not:SI (match_dup 2))
3305 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3306 "TARGET_POWER"
01def764 3307 "maskir %0,%3,%2")
1fd4e8c1 3308
7cd5235b 3309(define_insn "*maskir_internal4"
cd2b37d9
RK		 3310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3311 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 3312 (match_operand:SI 2 "gpc_reg_operand" "r"))
3313 (and:SI (not:SI (match_dup 2))
3314 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3315 "TARGET_POWER"
01def764 3316 "maskir %0,%3,%2")
1fd4e8c1 3317
7cd5235b 3318(define_insn "*maskir_internal5"
9ebbca7d 3319 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3320 (compare:CC
9ebbca7d
GK		 3321 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3322 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 3323 (and:SI (match_dup 2)
9ebbca7d 3324 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 3325 (const_int 0)))
9ebbca7d 3326 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3327 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3328 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 3329 "TARGET_POWER"
9ebbca7d
GK		 3330 "@
3331 maskir. %0,%3,%2
3332 #"
3333 [(set_attr "type" "compare")
3334 (set_attr "length" "4,8")])
3335
3336(define_split
3337 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3338 (compare:CC
3339 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3340 (match_operand:SI 1 "gpc_reg_operand" ""))
3341 (and:SI (match_dup 2)
3342 (match_operand:SI 3 "gpc_reg_operand" "")))
3343 (const_int 0)))
3344 (set (match_operand:SI 0 "gpc_reg_operand" "")
3345 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3346 (and:SI (match_dup 2) (match_dup 3))))]
3347 "TARGET_POWER && reload_completed"
3348 [(set (match_dup 0)
3349 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3350 (and:SI (match_dup 2) (match_dup 3))))
3351 (set (match_dup 4)
3352 (compare:CC (match_dup 0)
3353 (const_int 0)))]
3354 "")
1fd4e8c1 3355
7cd5235b 3356(define_insn "*maskir_internal6"
9ebbca7d 3357 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3358 (compare:CC
9ebbca7d
GK		 3359 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3360 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3361 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 3362 (match_dup 2)))
1fd4e8c1 3363 (const_int 0)))
9ebbca7d 3364 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3365 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3366 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 3367 "TARGET_POWER"
9ebbca7d
GK		 3368 "@
3369 maskir. %0,%3,%2
3370 #"
3371 [(set_attr "type" "compare")
3372 (set_attr "length" "4,8")])
3373
3374(define_split
3375 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3376 (compare:CC
3377 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3378 (match_operand:SI 1 "gpc_reg_operand" ""))
3379 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3380 (match_dup 2)))
3381 (const_int 0)))
3382 (set (match_operand:SI 0 "gpc_reg_operand" "")
3383 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3384 (and:SI (match_dup 3) (match_dup 2))))]
3385 "TARGET_POWER && reload_completed"
3386 [(set (match_dup 0)
3387 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3388 (and:SI (match_dup 3) (match_dup 2))))
3389 (set (match_dup 4)
3390 (compare:CC (match_dup 0)
3391 (const_int 0)))]
3392 "")
1fd4e8c1 3393
7cd5235b 3394(define_insn "*maskir_internal7"
9ebbca7d 3395 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 3396 (compare:CC
9ebbca7d
GK		 3397 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3398 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 3399 (and:SI (not:SI (match_dup 2))
9ebbca7d 3400 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 3401 (const_int 0)))
9ebbca7d 3402 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 3403 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3404 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3405 "TARGET_POWER"
9ebbca7d
GK		 3406 "@
3407 maskir. %0,%3,%2
3408 #"
3409 [(set_attr "type" "compare")
3410 (set_attr "length" "4,8")])
3411
3412(define_split
3413 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3414 (compare:CC
3415 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3416 (match_operand:SI 3 "gpc_reg_operand" ""))
3417 (and:SI (not:SI (match_dup 2))
3418 (match_operand:SI 1 "gpc_reg_operand" "")))
3419 (const_int 0)))
3420 (set (match_operand:SI 0 "gpc_reg_operand" "")
3421 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3422 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3423 "TARGET_POWER && reload_completed"
3424 [(set (match_dup 0)
3425 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3426 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3427 (set (match_dup 4)
3428 (compare:CC (match_dup 0)
3429 (const_int 0)))]
3430 "")
1fd4e8c1 3431
7cd5235b 3432(define_insn "*maskir_internal8"
9ebbca7d 3433 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3434 (compare:CC
9ebbca7d
GK		 3435 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3436 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 3437 (and:SI (not:SI (match_dup 2))
9ebbca7d 3438 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 3439 (const_int 0)))
9ebbca7d 3440 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3441 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3442 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 3443 "TARGET_POWER"
9ebbca7d
GK		 3444 "@
3445 maskir. %0,%3,%2
3446 #"
3447 [(set_attr "type" "compare")
3448 (set_attr "length" "4,8")])
fcce224d 3449
9ebbca7d
GK		 3450(define_split
3451 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3452 (compare:CC
3453 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3454 (match_operand:SI 2 "gpc_reg_operand" ""))
3455 (and:SI (not:SI (match_dup 2))
3456 (match_operand:SI 1 "gpc_reg_operand" "")))
3457 (const_int 0)))
3458 (set (match_operand:SI 0 "gpc_reg_operand" "")
3459 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3460 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3461 "TARGET_POWER && reload_completed"
3462 [(set (match_dup 0)
3463 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3464 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3465 (set (match_dup 4)
3466 (compare:CC (match_dup 0)
3467 (const_int 0)))]
3468 "")
fcce224d 3469\f
1fd4e8c1
RK		 3470;; Rotate and shift insns, in all their variants. These support shifts,
3471;; field inserts and extracts, and various combinations thereof.
034c1be0 3472(define_expand "insv"
0ad91047
DE		 3473 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3474 (match_operand:SI 1 "const_int_operand" "")
3475 (match_operand:SI 2 "const_int_operand" ""))
3476 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 3477 ""
3478 "
3479{
3480 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3481 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
14502dad
JM		 3482 compiler if the address of the structure is taken later. Likewise, do
3483 not handle invalid E500 subregs. */
034c1be0 3484 if (GET_CODE (operands[0]) == SUBREG
14502dad
JM		 3485 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3486 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3487 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
034c1be0 3488 FAIL;
a78e33fc
DE		 3489
3490 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3491 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3492 else
3493 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3494 DONE;
034c1be0
MM		 3495}")
3496
a78e33fc 3497(define_insn "insvsi"
cd2b37d9 3498 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 3499 (match_operand:SI 1 "const_int_operand" "i")
3500 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 3501 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 3502 ""
3503 "*
3504{
3505 int start = INTVAL (operands[2]) & 31;
3506 int size = INTVAL (operands[1]) & 31;
3507
89e9f3a8
MM		 3508 operands[4] = GEN_INT (32 - start - size);
3509 operands[1] = GEN_INT (start + size - 1);
a66078ee 3510 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3511}"
3512 [(set_attr "type" "insert_word")])
1fd4e8c1 3513
a78e33fc 3514(define_insn "*insvsi_internal1"
d56d506a
RK		 3515 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3516 (match_operand:SI 1 "const_int_operand" "i")
3517 (match_operand:SI 2 "const_int_operand" "i"))
6d0a8091 3518 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
d56d506a 3519 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3520 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3521 "*
3522{
3523 int shift = INTVAL (operands[4]) & 31;
3524 int start = INTVAL (operands[2]) & 31;
3525 int size = INTVAL (operands[1]) & 31;
3526
89e9f3a8 3527 operands[4] = GEN_INT (shift - start - size);
6d0a8091 3528 operands[1] = GEN_INT (start + size - 1);
a66078ee 3529 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3530}"
3531 [(set_attr "type" "insert_word")])
d56d506a 3532
a78e33fc 3533(define_insn "*insvsi_internal2"
d56d506a
RK		 3534 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3535 (match_operand:SI 1 "const_int_operand" "i")
3536 (match_operand:SI 2 "const_int_operand" "i"))
3537 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3538 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3539 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3540 "*
3541{
3542 int shift = INTVAL (operands[4]) & 31;
3543 int start = INTVAL (operands[2]) & 31;
3544 int size = INTVAL (operands[1]) & 31;
3545
89e9f3a8
MM		 3546 operands[4] = GEN_INT (32 - shift - start - size);
3547 operands[1] = GEN_INT (start + size - 1);
a66078ee 3548 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3549}"
3550 [(set_attr "type" "insert_word")])
d56d506a 3551
a78e33fc 3552(define_insn "*insvsi_internal3"
d56d506a
RK		 3553 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3554 (match_operand:SI 1 "const_int_operand" "i")
3555 (match_operand:SI 2 "const_int_operand" "i"))
3556 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3557 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 3558 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3559 "*
3560{
3561 int shift = INTVAL (operands[4]) & 31;
3562 int start = INTVAL (operands[2]) & 31;
3563 int size = INTVAL (operands[1]) & 31;
3564
89e9f3a8
MM		 3565 operands[4] = GEN_INT (32 - shift - start - size);
3566 operands[1] = GEN_INT (start + size - 1);
a66078ee 3567 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3568}"
3569 [(set_attr "type" "insert_word")])
d56d506a 3570
a78e33fc 3571(define_insn "*insvsi_internal4"
d56d506a
RK		 3572 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3573 (match_operand:SI 1 "const_int_operand" "i")
3574 (match_operand:SI 2 "const_int_operand" "i"))
3575 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3576 (match_operand:SI 4 "const_int_operand" "i")
3577 (match_operand:SI 5 "const_int_operand" "i")))]
3578 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3579 "*
3580{
3581 int extract_start = INTVAL (operands[5]) & 31;
3582 int extract_size = INTVAL (operands[4]) & 31;
3583 int insert_start = INTVAL (operands[2]) & 31;
3584 int insert_size = INTVAL (operands[1]) & 31;
3585
3586/* Align extract field with insert field */
3a598fbe 3587 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3588 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3589 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 3590}"
3591 [(set_attr "type" "insert_word")])
d56d506a 3592
f241bf89
EC		 3593;; combine patterns for rlwimi
3594(define_insn "*insvsi_internal5"
3595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3596 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3597 (match_operand:SI 1 "mask_operand" "i"))
3598 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3599 (match_operand:SI 2 "const_int_operand" "i"))
3600 (match_operand:SI 5 "mask_operand" "i"))))]
3601 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3602 "*
3603{
3604 int me = extract_ME(operands[5]);
3605 int mb = extract_MB(operands[5]);
3606 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3607 operands[2] = GEN_INT(mb);
3608 operands[1] = GEN_INT(me);
3609 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3610}"
3611 [(set_attr "type" "insert_word")])
3612
3613(define_insn "*insvsi_internal6"
3614 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3615 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3616 (match_operand:SI 2 "const_int_operand" "i"))
3617 (match_operand:SI 5 "mask_operand" "i"))
3618 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3619 (match_operand:SI 1 "mask_operand" "i"))))]
3620 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3621 "*
3622{
3623 int me = extract_ME(operands[5]);
3624 int mb = extract_MB(operands[5]);
3625 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3626 operands[2] = GEN_INT(mb);
3627 operands[1] = GEN_INT(me);
3628 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3629}"
3630 [(set_attr "type" "insert_word")])
3631
a78e33fc 3632(define_insn "insvdi"
685f3906 3633 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3634 (match_operand:SI 1 "const_int_operand" "i")
3635 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3636 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3637 "TARGET_POWERPC64"
3638 "*
3639{
3640 int start = INTVAL (operands[2]) & 63;
3641 int size = INTVAL (operands[1]) & 63;
3642
a78e33fc
DE		 3643 operands[1] = GEN_INT (64 - start - size);
3644 return \"rldimi %0,%3,%H1,%H2\";
44cd321e
PS		 3645}"
3646 [(set_attr "type" "insert_dword")])
685f3906 3647
11ac38b2
DE		 3648(define_insn "*insvdi_internal2"
3649 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3650 (match_operand:SI 1 "const_int_operand" "i")
3651 (match_operand:SI 2 "const_int_operand" "i"))
3652 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3653 (match_operand:SI 4 "const_int_operand" "i")))]
3654 "TARGET_POWERPC64
3655 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3656 "*
3657{
3658 int shift = INTVAL (operands[4]) & 63;
3659 int start = (INTVAL (operands[2]) & 63) - 32;
3660 int size = INTVAL (operands[1]) & 63;
3661
3662 operands[4] = GEN_INT (64 - shift - start - size);
3663 operands[2] = GEN_INT (start);
3664 operands[1] = GEN_INT (start + size - 1);
3665 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3666}")
3667
3668(define_insn "*insvdi_internal3"
3669 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3670 (match_operand:SI 1 "const_int_operand" "i")
3671 (match_operand:SI 2 "const_int_operand" "i"))
3672 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3673 (match_operand:SI 4 "const_int_operand" "i")))]
3674 "TARGET_POWERPC64
3675 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3676 "*
3677{
3678 int shift = INTVAL (operands[4]) & 63;
3679 int start = (INTVAL (operands[2]) & 63) - 32;
3680 int size = INTVAL (operands[1]) & 63;
3681
3682 operands[4] = GEN_INT (64 - shift - start - size);
3683 operands[2] = GEN_INT (start);
3684 operands[1] = GEN_INT (start + size - 1);
3685 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3686}")
3687
034c1be0 3688(define_expand "extzv"
0ad91047
DE		 3689 [(set (match_operand 0 "gpc_reg_operand" "")
3690 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3691 (match_operand:SI 2 "const_int_operand" "")
3692 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3693 ""
3694 "
3695{
3696 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3697 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3698 compiler if the address of the structure is taken later. */
3699 if (GET_CODE (operands[0]) == SUBREG
3700 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3701 FAIL;
a78e33fc
DE		 3702
3703 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3704 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3705 else
3706 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3707 DONE;
034c1be0
MM		 3708}")
3709
a78e33fc 3710(define_insn "extzvsi"
cd2b37d9
RK		 3711 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3712 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3713 (match_operand:SI 2 "const_int_operand" "i")
3714 (match_operand:SI 3 "const_int_operand" "i")))]
3715 ""
3716 "*
3717{
3718 int start = INTVAL (operands[3]) & 31;
3719 int size = INTVAL (operands[2]) & 31;
3720
3721 if (start + size >= 32)
3722 operands[3] = const0_rtx;
3723 else
89e9f3a8 3724 operands[3] = GEN_INT (start + size);
ca7f5001 3725 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3726}")
3727
a78e33fc 3728(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3729 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3730 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3731 (match_operand:SI 2 "const_int_operand" "i,i")
3732 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3733 (const_int 0)))
9ebbca7d 3734 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3735 ""
1fd4e8c1
RK		 3736 "*
3737{
3738 int start = INTVAL (operands[3]) & 31;
3739 int size = INTVAL (operands[2]) & 31;
3740
9ebbca7d
GK		 3741 /* Force split for non-cc0 compare. */
3742 if (which_alternative == 1)
3743 return \"#\";
3744
43a88a8c 3745 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3746 word, it is possible to use andiu. or andil. to test it. This is
3747 useful because the condition register set-use delay is smaller for
3748 andi[ul]. than for rlinm. This doesn't work when the starting bit
3749 position is 0 because the LT and GT bits may be set wrong. */
3750
3751 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3752 {
3a598fbe 3753 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3754 - (1 << (16 - (start & 15) - size))));
3755 if (start < 16)
ca7f5001 3756 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3757 else
ca7f5001 3758 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3759 }
7e69e155 3760
1fd4e8c1
RK		 3761 if (start + size >= 32)
3762 operands[3] = const0_rtx;
3763 else
89e9f3a8 3764 operands[3] = GEN_INT (start + size);
ca7f5001 3765 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3766}"
44cd321e 3767 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3768 (set_attr "length" "4,8")])
3769
3770(define_split
3771 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3772 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3773 (match_operand:SI 2 "const_int_operand" "")
3774 (match_operand:SI 3 "const_int_operand" ""))
3775 (const_int 0)))
3776 (clobber (match_scratch:SI 4 ""))]
ce71f754 3777 "reload_completed"
9ebbca7d
GK		 3778 [(set (match_dup 4)
3779 (zero_extract:SI (match_dup 1) (match_dup 2)
3780 (match_dup 3)))
3781 (set (match_dup 0)
3782 (compare:CC (match_dup 4)
3783 (const_int 0)))]
3784 "")
1fd4e8c1 3785
a78e33fc 3786(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3787 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3788 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3789 (match_operand:SI 2 "const_int_operand" "i,i")
3790 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3791 (const_int 0)))
9ebbca7d 3792 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3793 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3794 ""
1fd4e8c1
RK		 3795 "*
3796{
3797 int start = INTVAL (operands[3]) & 31;
3798 int size = INTVAL (operands[2]) & 31;
3799
9ebbca7d
GK		 3800 /* Force split for non-cc0 compare. */
3801 if (which_alternative == 1)
3802 return \"#\";
3803
bc401279 3804 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3805 a shift. The bit-field must end at the LSB. */
bc401279 3806 if (start >= 16 && start + size == 32)
df031c43 3807 {
bc401279
AM		 3808 operands[3] = GEN_INT ((1 << size) - 1);
3809 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3810 }
7e69e155 3811
1fd4e8c1
RK		 3812 if (start + size >= 32)
3813 operands[3] = const0_rtx;
3814 else
89e9f3a8 3815 operands[3] = GEN_INT (start + size);
ca7f5001 3816 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3817}"
44cd321e 3818 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3819 (set_attr "length" "4,8")])
3820
3821(define_split
3822 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3823 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3824 (match_operand:SI 2 "const_int_operand" "")
3825 (match_operand:SI 3 "const_int_operand" ""))
3826 (const_int 0)))
3827 (set (match_operand:SI 0 "gpc_reg_operand" "")
3828 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3829 "reload_completed"
9ebbca7d
GK		 3830 [(set (match_dup 0)
3831 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3832 (set (match_dup 4)
3833 (compare:CC (match_dup 0)
3834 (const_int 0)))]
3835 "")
1fd4e8c1 3836
a78e33fc 3837(define_insn "extzvdi"
685f3906
DE		 3838 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3839 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3840 (match_operand:SI 2 "const_int_operand" "i")
3841 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3842 "TARGET_POWERPC64"
3843 "*
3844{
3845 int start = INTVAL (operands[3]) & 63;
3846 int size = INTVAL (operands[2]) & 63;
3847
3848 if (start + size >= 64)
3849 operands[3] = const0_rtx;
3850 else
89e9f3a8
MM		 3851 operands[3] = GEN_INT (start + size);
3852 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3853 return \"rldicl %0,%1,%3,%2\";
3854}")
3855
a78e33fc 3856(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3857 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3858 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3859 (match_operand:SI 2 "const_int_operand" "i")
3860 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3861 (const_int 0)))
29ae5b89 3862 (clobber (match_scratch:DI 4 "=r"))]
683bdff7 3863 "TARGET_64BIT"
685f3906
DE		 3864 "*
3865{
3866 int start = INTVAL (operands[3]) & 63;
3867 int size = INTVAL (operands[2]) & 63;
3868
3869 if (start + size >= 64)
3870 operands[3] = const0_rtx;
3871 else
89e9f3a8
MM		 3872 operands[3] = GEN_INT (start + size);
3873 operands[2] = GEN_INT (64 - size);
685f3906 3874 return \"rldicl. %4,%1,%3,%2\";
9a3c428b
DE		 3875}"
3876 [(set_attr "type" "compare")])
685f3906 3877
a78e33fc 3878(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3879 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3880 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3881 (match_operand:SI 2 "const_int_operand" "i")
3882 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3883 (const_int 0)))
29ae5b89 3884 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3885 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
683bdff7 3886 "TARGET_64BIT"
685f3906
DE		 3887 "*
3888{
3889 int start = INTVAL (operands[3]) & 63;
3890 int size = INTVAL (operands[2]) & 63;
3891
3892 if (start + size >= 64)
3893 operands[3] = const0_rtx;
3894 else
89e9f3a8
MM		 3895 operands[3] = GEN_INT (start + size);
3896 operands[2] = GEN_INT (64 - size);
685f3906 3897 return \"rldicl. %0,%1,%3,%2\";
9a3c428b
DE		 3898}"
3899 [(set_attr "type" "compare")])
685f3906 3900
1fd4e8c1 3901(define_insn "rotlsi3"
44cd321e
PS		 3902 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3903 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3904 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
1fd4e8c1 3905 ""
44cd321e
PS		 3906 "@
3907 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3908 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3909 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3910
a260abc9 3911(define_insn "*rotlsi3_internal2"
44cd321e
PS		 3912 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3913 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3914 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3915 (const_int 0)))
44cd321e 3916 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
ce71f754 3917 ""
9ebbca7d 3918 "@
44cd321e
PS		 3919 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3920 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3921 #
9ebbca7d 3922 #"
44cd321e
PS		 3923 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3924 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3925
3926(define_split
3927 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3928 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3929 (match_operand:SI 2 "reg_or_cint_operand" ""))
3930 (const_int 0)))
3931 (clobber (match_scratch:SI 3 ""))]
ce71f754 3932 "reload_completed"
9ebbca7d
GK		 3933 [(set (match_dup 3)
3934 (rotate:SI (match_dup 1) (match_dup 2)))
3935 (set (match_dup 0)
3936 (compare:CC (match_dup 3)
3937 (const_int 0)))]
3938 "")
1fd4e8c1 3939
a260abc9 3940(define_insn "*rotlsi3_internal3"
44cd321e
PS		 3941 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3942 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3943 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3944 (const_int 0)))
44cd321e 3945 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3946 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3947 ""
9ebbca7d 3948 "@
44cd321e
PS		 3949 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3950 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3951 #
9ebbca7d 3952 #"
44cd321e
PS		 3953 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3954 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3955
3956(define_split
3957 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3958 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3959 (match_operand:SI 2 "reg_or_cint_operand" ""))
3960 (const_int 0)))
3961 (set (match_operand:SI 0 "gpc_reg_operand" "")
3962 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3963 "reload_completed"
9ebbca7d
GK		 3964 [(set (match_dup 0)
3965 (rotate:SI (match_dup 1) (match_dup 2)))
3966 (set (match_dup 3)
3967 (compare:CC (match_dup 0)
3968 (const_int 0)))]
3969 "")
1fd4e8c1 3970
a260abc9 3971(define_insn "*rotlsi3_internal4"
44cd321e
PS		 3972 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3973 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3974 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3975 (match_operand:SI 3 "mask_operand" "n,n")))]
1fd4e8c1 3976 ""
44cd321e
PS		 3977 "@
3978 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3979 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3980 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3981
a260abc9 3982(define_insn "*rotlsi3_internal5"
44cd321e 3983 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 3984 (compare:CC (and:SI
44cd321e
PS		 3985 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3986 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3987 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 3988 (const_int 0)))
44cd321e 3989 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
ce71f754 3990 ""
9ebbca7d 3991 "@
44cd321e
PS		 3992 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3993 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3994 #
9ebbca7d 3995 #"
44cd321e
PS		 3996 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3997 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3998
3999(define_split
4000 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4001 (compare:CC (and:SI
4002 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4003 (match_operand:SI 2 "reg_or_cint_operand" ""))
4004 (match_operand:SI 3 "mask_operand" ""))
4005 (const_int 0)))
4006 (clobber (match_scratch:SI 4 ""))]
ce71f754 4007 "reload_completed"
9ebbca7d
GK		 4008 [(set (match_dup 4)
4009 (and:SI (rotate:SI (match_dup 1)
4010 (match_dup 2))
4011 (match_dup 3)))
4012 (set (match_dup 0)
4013 (compare:CC (match_dup 4)
4014 (const_int 0)))]
4015 "")
1fd4e8c1 4016
a260abc9 4017(define_insn "*rotlsi3_internal6"
44cd321e 4018 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 4019 (compare:CC (and:SI
44cd321e
PS		 4020 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4021 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4022 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 4023 (const_int 0)))
44cd321e 4024 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4025 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4026 ""
9ebbca7d 4027 "@
44cd321e
PS		 4028 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4029 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4030 #
9ebbca7d 4031 #"
44cd321e
PS		 4032 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4033 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4034
4035(define_split
4036 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4037 (compare:CC (and:SI
4038 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4039 (match_operand:SI 2 "reg_or_cint_operand" ""))
4040 (match_operand:SI 3 "mask_operand" ""))
4041 (const_int 0)))
4042 (set (match_operand:SI 0 "gpc_reg_operand" "")
4043 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4044 "reload_completed"
9ebbca7d
GK		 4045 [(set (match_dup 0)
4046 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4047 (set (match_dup 4)
4048 (compare:CC (match_dup 0)
4049 (const_int 0)))]
4050 "")
1fd4e8c1 4051
a260abc9 4052(define_insn "*rotlsi3_internal7"
cd2b37d9 4053 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4054 (zero_extend:SI
4055 (subreg:QI
cd2b37d9 4056 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4057 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4058 ""
ca7f5001 4059 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1 4060
a260abc9 4061(define_insn "*rotlsi3_internal8"
44cd321e 4062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4063 (compare:CC (zero_extend:SI
4064 (subreg:QI
44cd321e
PS		 4065 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4066 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4067 (const_int 0)))
44cd321e 4068 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4069 ""
9ebbca7d 4070 "@
44cd321e
PS		 4071 {rlnm.|rlwnm.} %3,%1,%2,0xff
4072 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4073 #
9ebbca7d 4074 #"
44cd321e
PS		 4075 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4076 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4077
4078(define_split
4079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4080 (compare:CC (zero_extend:SI
4081 (subreg:QI
4082 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4083 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4084 (const_int 0)))
4085 (clobber (match_scratch:SI 3 ""))]
4086 "reload_completed"
4087 [(set (match_dup 3)
4088 (zero_extend:SI (subreg:QI
4089 (rotate:SI (match_dup 1)
4090 (match_dup 2)) 0)))
4091 (set (match_dup 0)
4092 (compare:CC (match_dup 3)
4093 (const_int 0)))]
4094 "")
1fd4e8c1 4095
a260abc9 4096(define_insn "*rotlsi3_internal9"
44cd321e 4097 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4098 (compare:CC (zero_extend:SI
4099 (subreg:QI
44cd321e
PS		 4100 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4101 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4102 (const_int 0)))
44cd321e 4103 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4104 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4105 ""
9ebbca7d 4106 "@
44cd321e
PS		 4107 {rlnm.|rlwnm.} %0,%1,%2,0xff
4108 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4109 #
9ebbca7d 4110 #"
44cd321e
PS		 4111 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4112 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4113
4114(define_split
4115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4116 (compare:CC (zero_extend:SI
4117 (subreg:QI
4118 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4119 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4120 (const_int 0)))
4121 (set (match_operand:SI 0 "gpc_reg_operand" "")
4122 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4123 "reload_completed"
4124 [(set (match_dup 0)
4125 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4126 (set (match_dup 3)
4127 (compare:CC (match_dup 0)
4128 (const_int 0)))]
4129 "")
1fd4e8c1 4130
a260abc9 4131(define_insn "*rotlsi3_internal10"
44cd321e 4132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4133 (zero_extend:SI
4134 (subreg:HI
44cd321e
PS		 4135 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4136 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
1fd4e8c1 4137 ""
44cd321e
PS		 4138 "@
4139 {rlnm|rlwnm} %0,%1,%2,0xffff
4140 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4141 [(set_attr "type" "var_shift_rotate,integer")])
4142
1fd4e8c1 4143
a260abc9 4144(define_insn "*rotlsi3_internal11"
44cd321e 4145 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4146 (compare:CC (zero_extend:SI
4147 (subreg:HI
44cd321e
PS		 4148 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4149 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4150 (const_int 0)))
44cd321e 4151 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4152 ""
9ebbca7d 4153 "@
44cd321e
PS		 4154 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4155 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4156 #
9ebbca7d 4157 #"
44cd321e
PS		 4158 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4159 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4160
4161(define_split
4162 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4163 (compare:CC (zero_extend:SI
4164 (subreg:HI
4165 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4166 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4167 (const_int 0)))
4168 (clobber (match_scratch:SI 3 ""))]
4169 "reload_completed"
4170 [(set (match_dup 3)
4171 (zero_extend:SI (subreg:HI
4172 (rotate:SI (match_dup 1)
4173 (match_dup 2)) 0)))
4174 (set (match_dup 0)
4175 (compare:CC (match_dup 3)
4176 (const_int 0)))]
4177 "")
1fd4e8c1 4178
a260abc9 4179(define_insn "*rotlsi3_internal12"
44cd321e 4180 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4181 (compare:CC (zero_extend:SI
4182 (subreg:HI
44cd321e
PS		 4183 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4184 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4185 (const_int 0)))
44cd321e 4186 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4187 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4188 ""
9ebbca7d 4189 "@
44cd321e
PS		 4190 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4191 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4192 #
9ebbca7d 4193 #"
44cd321e
PS		 4194 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4195 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4196
4197(define_split
4198 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4199 (compare:CC (zero_extend:SI
4200 (subreg:HI
4201 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4202 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4203 (const_int 0)))
4204 (set (match_operand:SI 0 "gpc_reg_operand" "")
4205 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4206 "reload_completed"
4207 [(set (match_dup 0)
4208 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4209 (set (match_dup 3)
4210 (compare:CC (match_dup 0)
4211 (const_int 0)))]
4212 "")
1fd4e8c1
RK		 4213
4214;; Note that we use "sle." instead of "sl." so that we can set
4215;; SHIFT_COUNT_TRUNCATED.
4216
ca7f5001
RK		 4217(define_expand "ashlsi3"
4218 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4219 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4220 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4221 ""
4222 "
4223{
4224 if (TARGET_POWER)
4225 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4226 else
25c341fa 4227 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4228 DONE;
4229}")
4230
4231(define_insn "ashlsi3_power"
cd2b37d9
RK		 4232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4233 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4234 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4235 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4236 "TARGET_POWER"
1fd4e8c1
RK		 4237 "@
4238 sle %0,%1,%2
9ebbca7d 4239 {sli|slwi} %0,%1,%h2")
ca7f5001 4240
25c341fa 4241(define_insn "ashlsi3_no_power"
44cd321e
PS		 4242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4243 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4244 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4245 "! TARGET_POWER"
44cd321e
PS		 4246 "@
4247 {sl|slw} %0,%1,%2
4248 {sli|slwi} %0,%1,%h2"
4249 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4250
4251(define_insn ""
9ebbca7d
GK		 4252 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4253 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4254 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4255 (const_int 0)))
9ebbca7d
GK		 4256 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4257 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4258 "TARGET_POWER"
1fd4e8c1
RK		 4259 "@
4260 sle. %3,%1,%2
9ebbca7d
GK		 4261 {sli.|slwi.} %3,%1,%h2
4262 #
4263 #"
4264 [(set_attr "type" "delayed_compare")
4265 (set_attr "length" "4,4,8,8")])
4266
4267(define_split
4268 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4269 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4270 (match_operand:SI 2 "reg_or_cint_operand" ""))
4271 (const_int 0)))
4272 (clobber (match_scratch:SI 3 ""))
4273 (clobber (match_scratch:SI 4 ""))]
4274 "TARGET_POWER && reload_completed"
4275 [(parallel [(set (match_dup 3)
4276 (ashift:SI (match_dup 1) (match_dup 2)))
4277 (clobber (match_dup 4))])
4278 (set (match_dup 0)
4279 (compare:CC (match_dup 3)
4280 (const_int 0)))]
4281 "")
25c341fa 4282
ca7f5001 4283(define_insn ""
44cd321e
PS		 4284 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4285 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4286 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4287 (const_int 0)))
44cd321e 4288 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4b8a63d6 4289 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4290 "@
44cd321e
PS		 4291 {sl.|slw.} %3,%1,%2
4292 {sli.|slwi.} %3,%1,%h2
4293 #
9ebbca7d 4294 #"
44cd321e
PS		 4295 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4296 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4297
4298(define_split
4299 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4300 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4301 (match_operand:SI 2 "reg_or_cint_operand" ""))
4302 (const_int 0)))
4303 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4304 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4305 [(set (match_dup 3)
4306 (ashift:SI (match_dup 1) (match_dup 2)))
4307 (set (match_dup 0)
4308 (compare:CC (match_dup 3)
4309 (const_int 0)))]
4310 "")
1fd4e8c1
RK		 4311
4312(define_insn ""
9ebbca7d
GK		 4313 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4314 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4315 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4316 (const_int 0)))
9ebbca7d 4317 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4318 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4319 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4320 "TARGET_POWER"
1fd4e8c1
RK		 4321 "@
4322 sle. %0,%1,%2
9ebbca7d
GK		 4323 {sli.|slwi.} %0,%1,%h2
4324 #
4325 #"
4326 [(set_attr "type" "delayed_compare")
4327 (set_attr "length" "4,4,8,8")])
4328
4329(define_split
4330 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4331 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4332 (match_operand:SI 2 "reg_or_cint_operand" ""))
4333 (const_int 0)))
4334 (set (match_operand:SI 0 "gpc_reg_operand" "")
4335 (ashift:SI (match_dup 1) (match_dup 2)))
4336 (clobber (match_scratch:SI 4 ""))]
4337 "TARGET_POWER && reload_completed"
4338 [(parallel [(set (match_dup 0)
4339 (ashift:SI (match_dup 1) (match_dup 2)))
4340 (clobber (match_dup 4))])
4341 (set (match_dup 3)
4342 (compare:CC (match_dup 0)
4343 (const_int 0)))]
4344 "")
25c341fa 4345
ca7f5001 4346(define_insn ""
44cd321e
PS		 4347 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4348 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4349 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4350 (const_int 0)))
44cd321e 4351 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 4352 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4353 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4354 "@
44cd321e
PS		 4355 {sl.|slw.} %0,%1,%2
4356 {sli.|slwi.} %0,%1,%h2
4357 #
9ebbca7d 4358 #"
44cd321e
PS		 4359 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4360 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4361
4362(define_split
4363 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4364 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4365 (match_operand:SI 2 "reg_or_cint_operand" ""))
4366 (const_int 0)))
4367 (set (match_operand:SI 0 "gpc_reg_operand" "")
4368 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4369 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4370 [(set (match_dup 0)
4371 (ashift:SI (match_dup 1) (match_dup 2)))
4372 (set (match_dup 3)
4373 (compare:CC (match_dup 0)
4374 (const_int 0)))]
4375 "")
1fd4e8c1 4376
915167f5 4377(define_insn "rlwinm"
cd2b37d9
RK		 4378 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4379 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4380 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4381 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4382 "includes_lshift_p (operands[2], operands[3])"
d56d506a 4383 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 4384
4385(define_insn ""
9ebbca7d 4386 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4387 (compare:CC
9ebbca7d
GK		 4388 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4389 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4390 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4391 (const_int 0)))
9ebbca7d 4392 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4393 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4394 "@
4395 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4396 #"
4397 [(set_attr "type" "delayed_compare")
4398 (set_attr "length" "4,8")])
4399
4400(define_split
4401 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4402 (compare:CC
4403 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4404 (match_operand:SI 2 "const_int_operand" ""))
4405 (match_operand:SI 3 "mask_operand" ""))
4406 (const_int 0)))
4407 (clobber (match_scratch:SI 4 ""))]
ce71f754 4408 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4409 [(set (match_dup 4)
4410 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4411 (match_dup 3)))
4412 (set (match_dup 0)
4413 (compare:CC (match_dup 4)
4414 (const_int 0)))]
4415 "")
1fd4e8c1
RK		 4416
4417(define_insn ""
9ebbca7d 4418 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4419 (compare:CC
9ebbca7d
GK		 4420 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4421 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4422 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4423 (const_int 0)))
9ebbca7d 4424 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4425 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4426 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4427 "@
4428 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4429 #"
4430 [(set_attr "type" "delayed_compare")
4431 (set_attr "length" "4,8")])
4432
4433(define_split
4434 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4435 (compare:CC
4436 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4437 (match_operand:SI 2 "const_int_operand" ""))
4438 (match_operand:SI 3 "mask_operand" ""))
4439 (const_int 0)))
4440 (set (match_operand:SI 0 "gpc_reg_operand" "")
4441 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4442 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4443 [(set (match_dup 0)
4444 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4445 (set (match_dup 4)
4446 (compare:CC (match_dup 0)
4447 (const_int 0)))]
4448 "")
1fd4e8c1 4449
ca7f5001 4450;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 4451;; "sli x,x,0".
ca7f5001
RK		 4452(define_expand "lshrsi3"
4453 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4454 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4455 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4456 ""
4457 "
4458{
4459 if (TARGET_POWER)
4460 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4461 else
25c341fa 4462 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4463 DONE;
4464}")
4465
4466(define_insn "lshrsi3_power"
bdf423cb
MM		 4467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4468 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4469 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4470 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 4471 "TARGET_POWER"
1fd4e8c1
RK		 4472 "@
4473 sre %0,%1,%2
bdf423cb 4474 mr %0,%1
ca7f5001
RK		 4475 {s%A2i|s%A2wi} %0,%1,%h2")
4476
25c341fa 4477(define_insn "lshrsi3_no_power"
44cd321e
PS		 4478 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4479 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4480 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
25c341fa 4481 "! TARGET_POWER"
bdf423cb
MM		 4482 "@
4483 mr %0,%1
44cd321e
PS		 4484 {sr|srw} %0,%1,%2
4485 {sri|srwi} %0,%1,%h2"
4486 [(set_attr "type" "integer,var_shift_rotate,shift")])
1fd4e8c1
RK		 4487
4488(define_insn ""
9ebbca7d
GK		 4489 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4490 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4491 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4492 (const_int 0)))
9ebbca7d
GK		 4493 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4494 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4495 "TARGET_POWER"
1fd4e8c1 4496 "@
29ae5b89
JL		 4497 sre. %3,%1,%2
4498 mr. %1,%1
9ebbca7d
GK		 4499 {s%A2i.|s%A2wi.} %3,%1,%h2
4500 #
4501 #
4502 #"
4503 [(set_attr "type" "delayed_compare")
4504 (set_attr "length" "4,4,4,8,8,8")])
4505
4506(define_split
4507 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4508 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4509 (match_operand:SI 2 "reg_or_cint_operand" ""))
4510 (const_int 0)))
4511 (clobber (match_scratch:SI 3 ""))
4512 (clobber (match_scratch:SI 4 ""))]
4513 "TARGET_POWER && reload_completed"
4514 [(parallel [(set (match_dup 3)
4515 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4516 (clobber (match_dup 4))])
4517 (set (match_dup 0)
4518 (compare:CC (match_dup 3)
4519 (const_int 0)))]
4520 "")
ca7f5001
RK		 4521
4522(define_insn ""
44cd321e
PS		 4523 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4524 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4525 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
ca7f5001 4526 (const_int 0)))
44cd321e 4527 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4b8a63d6 4528 "! TARGET_POWER && TARGET_32BIT"
bdf423cb
MM		 4529 "@
4530 mr. %1,%1
44cd321e
PS		 4531 {sr.|srw.} %3,%1,%2
4532 {sri.|srwi.} %3,%1,%h2
4533 #
9ebbca7d
GK		 4534 #
4535 #"
44cd321e
PS		 4536 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4537 (set_attr "length" "4,4,4,8,8,8")])
1fd4e8c1 4538
9ebbca7d
GK		 4539(define_split
4540 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4541 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4542 (match_operand:SI 2 "reg_or_cint_operand" ""))
4543 (const_int 0)))
4544 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4545 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4546 [(set (match_dup 3)
4547 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4548 (set (match_dup 0)
4549 (compare:CC (match_dup 3)
4550 (const_int 0)))]
4551 "")
4552
4553(define_insn ""
4554 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4555 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4556 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4557 (const_int 0)))
9ebbca7d 4558 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 4559 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4560 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4561 "TARGET_POWER"
1fd4e8c1 4562 "@
29ae5b89
JL		 4563 sre. %0,%1,%2
4564 mr. %0,%1
9ebbca7d
GK		 4565 {s%A2i.|s%A2wi.} %0,%1,%h2
4566 #
4567 #
4568 #"
4569 [(set_attr "type" "delayed_compare")
4570 (set_attr "length" "4,4,4,8,8,8")])
4571
4572(define_split
4573 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4574 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4575 (match_operand:SI 2 "reg_or_cint_operand" ""))
4576 (const_int 0)))
4577 (set (match_operand:SI 0 "gpc_reg_operand" "")
4578 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4579 (clobber (match_scratch:SI 4 ""))]
4580 "TARGET_POWER && reload_completed"
4581 [(parallel [(set (match_dup 0)
4582 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4583 (clobber (match_dup 4))])
4584 (set (match_dup 3)
4585 (compare:CC (match_dup 0)
4586 (const_int 0)))]
4587 "")
ca7f5001
RK		 4588
4589(define_insn ""
44cd321e
PS		 4590 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4591 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4592 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
815cdc52 4593 (const_int 0)))
44cd321e 4594 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
29ae5b89 4595 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4596 "! TARGET_POWER && TARGET_32BIT"
29ae5b89
JL		 4597 "@
4598 mr. %0,%1
44cd321e
PS		 4599 {sr.|srw.} %0,%1,%2
4600 {sri.|srwi.} %0,%1,%h2
4601 #
9ebbca7d
GK		 4602 #
4603 #"
44cd321e
PS		 4604 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4605 (set_attr "length" "4,4,4,8,8,8")])
9ebbca7d
GK		 4606
4607(define_split
4608 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4609 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4610 (match_operand:SI 2 "reg_or_cint_operand" ""))
4611 (const_int 0)))
4612 (set (match_operand:SI 0 "gpc_reg_operand" "")
4613 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4614 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4615 [(set (match_dup 0)
4616 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4617 (set (match_dup 3)
4618 (compare:CC (match_dup 0)
4619 (const_int 0)))]
4620 "")
1fd4e8c1
RK		 4621
4622(define_insn ""
cd2b37d9
RK		 4623 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4624 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4625 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4626 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4627 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 4628 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 4629
4630(define_insn ""
9ebbca7d 4631 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4632 (compare:CC
9ebbca7d
GK		 4633 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4634 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4635 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4636 (const_int 0)))
9ebbca7d 4637 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4638 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4639 "@
4640 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4641 #"
4642 [(set_attr "type" "delayed_compare")
4643 (set_attr "length" "4,8")])
4644
4645(define_split
4646 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4647 (compare:CC
4648 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4649 (match_operand:SI 2 "const_int_operand" ""))
4650 (match_operand:SI 3 "mask_operand" ""))
4651 (const_int 0)))
4652 (clobber (match_scratch:SI 4 ""))]
ce71f754 4653 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4654 [(set (match_dup 4)
4655 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4656 (match_dup 3)))
4657 (set (match_dup 0)
4658 (compare:CC (match_dup 4)
4659 (const_int 0)))]
4660 "")
1fd4e8c1
RK		 4661
4662(define_insn ""
9ebbca7d 4663 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4664 (compare:CC
9ebbca7d
GK		 4665 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4666 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4667 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4668 (const_int 0)))
9ebbca7d 4669 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4670 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4671 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4672 "@
4673 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4674 #"
4675 [(set_attr "type" "delayed_compare")
4676 (set_attr "length" "4,8")])
4677
4678(define_split
4679 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4680 (compare:CC
4681 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4682 (match_operand:SI 2 "const_int_operand" ""))
4683 (match_operand:SI 3 "mask_operand" ""))
4684 (const_int 0)))
4685 (set (match_operand:SI 0 "gpc_reg_operand" "")
4686 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4687 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4688 [(set (match_dup 0)
4689 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4690 (set (match_dup 4)
4691 (compare:CC (match_dup 0)
4692 (const_int 0)))]
4693 "")
1fd4e8c1
RK		 4694
4695(define_insn ""
cd2b37d9 4696 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4697 (zero_extend:SI
4698 (subreg:QI
cd2b37d9 4699 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4700 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4701 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4702 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4703
4704(define_insn ""
9ebbca7d 4705 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4706 (compare:CC
4707 (zero_extend:SI
4708 (subreg:QI
9ebbca7d
GK		 4709 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4710 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4711 (const_int 0)))
9ebbca7d 4712 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4713 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4714 "@
4715 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4716 #"
4717 [(set_attr "type" "delayed_compare")
4718 (set_attr "length" "4,8")])
4719
4720(define_split
4721 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4722 (compare:CC
4723 (zero_extend:SI
4724 (subreg:QI
4725 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4726 (match_operand:SI 2 "const_int_operand" "")) 0))
4727 (const_int 0)))
4728 (clobber (match_scratch:SI 3 ""))]
4729 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4730 [(set (match_dup 3)
4731 (zero_extend:SI (subreg:QI
4732 (lshiftrt:SI (match_dup 1)
4733 (match_dup 2)) 0)))
4734 (set (match_dup 0)
4735 (compare:CC (match_dup 3)
4736 (const_int 0)))]
4737 "")
1fd4e8c1
RK		 4738
4739(define_insn ""
9ebbca7d 4740 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4741 (compare:CC
4742 (zero_extend:SI
4743 (subreg:QI
9ebbca7d
GK		 4744 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4745 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4746 (const_int 0)))
9ebbca7d 4747 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4748 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4749 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4750 "@
4751 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4752 #"
4753 [(set_attr "type" "delayed_compare")
4754 (set_attr "length" "4,8")])
4755
4756(define_split
4757 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4758 (compare:CC
4759 (zero_extend:SI
4760 (subreg:QI
4761 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4762 (match_operand:SI 2 "const_int_operand" "")) 0))
4763 (const_int 0)))
4764 (set (match_operand:SI 0 "gpc_reg_operand" "")
4765 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4766 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4767 [(set (match_dup 0)
4768 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4769 (set (match_dup 3)
4770 (compare:CC (match_dup 0)
4771 (const_int 0)))]
4772 "")
1fd4e8c1
RK		 4773
4774(define_insn ""
cd2b37d9 4775 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4776 (zero_extend:SI
4777 (subreg:HI
cd2b37d9 4778 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4779 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4780 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4781 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4782
4783(define_insn ""
9ebbca7d 4784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4785 (compare:CC
4786 (zero_extend:SI
4787 (subreg:HI
9ebbca7d
GK		 4788 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4789 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4790 (const_int 0)))
9ebbca7d 4791 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4792 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4793 "@
4794 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4795 #"
4796 [(set_attr "type" "delayed_compare")
4797 (set_attr "length" "4,8")])
4798
4799(define_split
4800 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4801 (compare:CC
4802 (zero_extend:SI
4803 (subreg:HI
4804 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4805 (match_operand:SI 2 "const_int_operand" "")) 0))
4806 (const_int 0)))
4807 (clobber (match_scratch:SI 3 ""))]
4808 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4809 [(set (match_dup 3)
4810 (zero_extend:SI (subreg:HI
4811 (lshiftrt:SI (match_dup 1)
4812 (match_dup 2)) 0)))
4813 (set (match_dup 0)
4814 (compare:CC (match_dup 3)
4815 (const_int 0)))]
4816 "")
1fd4e8c1
RK		 4817
4818(define_insn ""
9ebbca7d 4819 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4820 (compare:CC
4821 (zero_extend:SI
4822 (subreg:HI
9ebbca7d
GK		 4823 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4824 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4825 (const_int 0)))
9ebbca7d 4826 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4827 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4828 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4829 "@
4830 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4831 #"
4832 [(set_attr "type" "delayed_compare")
4833 (set_attr "length" "4,8")])
4834
4835(define_split
4836 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4837 (compare:CC
4838 (zero_extend:SI
4839 (subreg:HI
4840 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4841 (match_operand:SI 2 "const_int_operand" "")) 0))
4842 (const_int 0)))
4843 (set (match_operand:SI 0 "gpc_reg_operand" "")
4844 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4845 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4846 [(set (match_dup 0)
4847 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4848 (set (match_dup 3)
4849 (compare:CC (match_dup 0)
4850 (const_int 0)))]
4851 "")
1fd4e8c1
RK		 4852
4853(define_insn ""
cd2b37d9 4854 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4855 (const_int 1)
cd2b37d9
RK		 4856 (match_operand:SI 1 "gpc_reg_operand" "r"))
4857 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4858 (const_int 31)))]
ca7f5001 4859 "TARGET_POWER"
1fd4e8c1
RK		 4860 "rrib %0,%1,%2")
4861
4862(define_insn ""
cd2b37d9 4863 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4864 (const_int 1)
cd2b37d9
RK		 4865 (match_operand:SI 1 "gpc_reg_operand" "r"))
4866 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4867 (const_int 31)))]
ca7f5001 4868 "TARGET_POWER"
1fd4e8c1
RK		 4869 "rrib %0,%1,%2")
4870
4871(define_insn ""
cd2b37d9 4872 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4873 (const_int 1)
cd2b37d9
RK		 4874 (match_operand:SI 1 "gpc_reg_operand" "r"))
4875 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4876 (const_int 1)
4877 (const_int 0)))]
ca7f5001 4878 "TARGET_POWER"
1fd4e8c1
RK		 4879 "rrib %0,%1,%2")
4880
ca7f5001
RK		 4881(define_expand "ashrsi3"
4882 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4883 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4884 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4885 ""
4886 "
4887{
4888 if (TARGET_POWER)
4889 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4890 else
25c341fa 4891 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4892 DONE;
4893}")
4894
4895(define_insn "ashrsi3_power"
cd2b37d9
RK		 4896 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4897 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4898 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4899 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4900 "TARGET_POWER"
1fd4e8c1
RK		 4901 "@
4902 srea %0,%1,%2
44cd321e
PS		 4903 {srai|srawi} %0,%1,%h2"
4904 [(set_attr "type" "shift")])
ca7f5001 4905
25c341fa 4906(define_insn "ashrsi3_no_power"
44cd321e
PS		 4907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4908 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4909 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4910 "! TARGET_POWER"
44cd321e
PS		 4911 "@
4912 {sra|sraw} %0,%1,%2
4913 {srai|srawi} %0,%1,%h2"
4914 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4915
4916(define_insn ""
9ebbca7d
GK		 4917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4918 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4919 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4920 (const_int 0)))
9ebbca7d
GK		 4921 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4922 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4923 "TARGET_POWER"
1fd4e8c1
RK		 4924 "@
4925 srea. %3,%1,%2
9ebbca7d
GK		 4926 {srai.|srawi.} %3,%1,%h2
4927 #
4928 #"
4929 [(set_attr "type" "delayed_compare")
4930 (set_attr "length" "4,4,8,8")])
4931
4932(define_split
4933 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4934 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4935 (match_operand:SI 2 "reg_or_cint_operand" ""))
4936 (const_int 0)))
4937 (clobber (match_scratch:SI 3 ""))
4938 (clobber (match_scratch:SI 4 ""))]
4939 "TARGET_POWER && reload_completed"
4940 [(parallel [(set (match_dup 3)
4941 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4942 (clobber (match_dup 4))])
4943 (set (match_dup 0)
4944 (compare:CC (match_dup 3)
4945 (const_int 0)))]
4946 "")
ca7f5001
RK		 4947
4948(define_insn ""
44cd321e
PS		 4949 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4950 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4951 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4952 (const_int 0)))
44cd321e 4953 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
25c341fa 4954 "! TARGET_POWER"
9ebbca7d 4955 "@
44cd321e
PS		 4956 {sra.|sraw.} %3,%1,%2
4957 {srai.|srawi.} %3,%1,%h2
4958 #
9ebbca7d 4959 #"
44cd321e
PS		 4960 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4961 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4962
4963(define_split
4964 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4965 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4966 (match_operand:SI 2 "reg_or_cint_operand" ""))
4967 (const_int 0)))
4968 (clobber (match_scratch:SI 3 ""))]
4969 "! TARGET_POWER && reload_completed"
4970 [(set (match_dup 3)
4971 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4972 (set (match_dup 0)
4973 (compare:CC (match_dup 3)
4974 (const_int 0)))]
4975 "")
1fd4e8c1
RK		 4976
4977(define_insn ""
9ebbca7d
GK		 4978 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4979 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4980 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4981 (const_int 0)))
9ebbca7d 4982 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4983 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4984 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4985 "TARGET_POWER"
1fd4e8c1
RK		 4986 "@
4987 srea. %0,%1,%2
9ebbca7d
GK		 4988 {srai.|srawi.} %0,%1,%h2
4989 #
4990 #"
4991 [(set_attr "type" "delayed_compare")
4992 (set_attr "length" "4,4,8,8")])
4993
4994(define_split
4995 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4996 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4997 (match_operand:SI 2 "reg_or_cint_operand" ""))
4998 (const_int 0)))
4999 (set (match_operand:SI 0 "gpc_reg_operand" "")
5000 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5001 (clobber (match_scratch:SI 4 ""))]
5002 "TARGET_POWER && reload_completed"
5003 [(parallel [(set (match_dup 0)
5004 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5005 (clobber (match_dup 4))])
5006 (set (match_dup 3)
5007 (compare:CC (match_dup 0)
5008 (const_int 0)))]
5009 "")
1fd4e8c1 5010
ca7f5001 5011(define_insn ""
44cd321e
PS		 5012 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5013 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5014 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 5015 (const_int 0)))
44cd321e 5016 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 5017 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 5018 "! TARGET_POWER"
9ebbca7d 5019 "@
44cd321e
PS		 5020 {sra.|sraw.} %0,%1,%2
5021 {srai.|srawi.} %0,%1,%h2
5022 #
9ebbca7d 5023 #"
44cd321e
PS		 5024 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5025 (set_attr "length" "4,4,8,8")])
1fd4e8c1 5026\f
9ebbca7d
GK		 5027(define_split
5028 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5029 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5030 (match_operand:SI 2 "reg_or_cint_operand" ""))
5031 (const_int 0)))
5032 (set (match_operand:SI 0 "gpc_reg_operand" "")
5033 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5034 "! TARGET_POWER && reload_completed"
5035 [(set (match_dup 0)
5036 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5037 (set (match_dup 3)
5038 (compare:CC (match_dup 0)
5039 (const_int 0)))]
5040 "")
5041
1fd4e8c1
RK		 5042;; Floating-point insns, excluding normal data motion.
5043;;
ca7f5001
RK		 5044;; PowerPC has a full set of single-precision floating point instructions.
5045;;
5046;; For the POWER architecture, we pretend that we have both SFmode and
5047;; DFmode insns, while, in fact, all fp insns are actually done in double.
5048;; The only conversions we will do will be when storing to memory. In that
5049;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 5050;;
5051;; Note that when we store into a single-precision memory location, we need to
5052;; use the frsp insn first. If the register being stored isn't dead, we
5053;; need a scratch register for the frsp. But this is difficult when the store
5054;; is done by reload. It is not incorrect to do the frsp on the register in
5055;; this case, we just lose precision that we would have otherwise gotten but
5056;; is not guaranteed. Perhaps this should be tightened up at some point.
5057
99176a91
AH		 5058(define_expand "extendsfdf2"
5059 [(set (match_operand:DF 0 "gpc_reg_operand" "")
97c54d9a 5060 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
99176a91
AH		 5061 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5062 "")
5063
5064(define_insn_and_split "*extendsfdf2_fpr"
97c54d9a
DE		 5065 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5066 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
a3170dc6 5067 "TARGET_HARD_FLOAT && TARGET_FPRS"
11ac38b2
DE		 5068 "@
5069 #
97c54d9a
DE		 5070 fmr %0,%1
5071 lfs%U1%X1 %0,%1"
d7b1468b 5072 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
11ac38b2 5073 [(const_int 0)]
5c30aff8 5074{
11ac38b2
DE		 5075 emit_note (NOTE_INSN_DELETED);
5076 DONE;
5077}
97c54d9a 5078 [(set_attr "type" "fp,fp,fpload")])
1fd4e8c1 5079
7a2f7870
AH		 5080(define_expand "truncdfsf2"
5081 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5082 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5083 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5084 "")
5085
99176a91 5086(define_insn "*truncdfsf2_fpr"
cd2b37d9
RK		 5087 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5088 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5089 "TARGET_HARD_FLOAT && TARGET_FPRS"
dcac138d 5090 "frsp %0,%1"
1fd4e8c1
RK		 5091 [(set_attr "type" "fp")])
5092
455350f4
RK		 5093(define_insn "aux_truncdfsf2"
5094 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 5095 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
a3170dc6 5096 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 5097 "frsp %0,%1"
5098 [(set_attr "type" "fp")])
5099
a3170dc6
AH		 5100(define_expand "negsf2"
5101 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5102 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5103 "TARGET_HARD_FLOAT"
5104 "")
5105
5106(define_insn "*negsf2"
cd2b37d9
RK		 5107 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5108 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5109 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5110 "fneg %0,%1"
5111 [(set_attr "type" "fp")])
5112
a3170dc6
AH		 5113(define_expand "abssf2"
5114 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5115 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5116 "TARGET_HARD_FLOAT"
5117 "")
5118
5119(define_insn "*abssf2"
cd2b37d9
RK		 5120 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5121 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5122 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5123 "fabs %0,%1"
5124 [(set_attr "type" "fp")])
5125
5126(define_insn ""
cd2b37d9
RK		 5127 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5128 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
a3170dc6 5129 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5130 "fnabs %0,%1"
5131 [(set_attr "type" "fp")])
5132
ca7f5001
RK		 5133(define_expand "addsf3"
5134 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5135 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5136 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5137 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5138 "")
5139
5140(define_insn ""
cd2b37d9
RK		 5141 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5142 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5143 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5144 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5145 "fadds %0,%1,%2"
ca7f5001
RK		 5146 [(set_attr "type" "fp")])
5147
5148(define_insn ""
5149 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5150 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5151 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5152 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5153 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 5154 [(set_attr "type" "fp")])
5155
5156(define_expand "subsf3"
5157 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5158 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5159 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5160 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5161 "")
5162
5163(define_insn ""
5164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5165 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5166 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5167 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5168 "fsubs %0,%1,%2"
1fd4e8c1
RK		 5169 [(set_attr "type" "fp")])
5170
ca7f5001 5171(define_insn ""
cd2b37d9
RK		 5172 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5173 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5174 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5175 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5176 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 5177 [(set_attr "type" "fp")])
5178
5179(define_expand "mulsf3"
5180 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5181 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5182 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5183 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5184 "")
5185
5186(define_insn ""
5187 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5188 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5189 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5190 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5191 "fmuls %0,%1,%2"
1fd4e8c1
RK		 5192 [(set_attr "type" "fp")])
5193
ca7f5001 5194(define_insn ""
cd2b37d9
RK		 5195 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5196 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5197 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5198 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5199 "{fm|fmul} %0,%1,%2"
0780f386 5200 [(set_attr "type" "dmul")])
1fd4e8c1 5201
ca7f5001
RK		 5202(define_expand "divsf3"
5203 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5204 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5205 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5206 "TARGET_HARD_FLOAT"
9c78b944 5207 "")
ca7f5001
RK		 5208
5209(define_insn ""
cd2b37d9
RK		 5210 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5211 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5212 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5213 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5214 "fdivs %0,%1,%2"
ca7f5001
RK		 5215 [(set_attr "type" "sdiv")])
5216
5217(define_insn ""
5218 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5219 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5220 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5221 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5222 "{fd|fdiv} %0,%1,%2"
0780f386 5223 [(set_attr "type" "ddiv")])
1fd4e8c1 5224
9c78b944
DE		 5225(define_expand "recipsf3"
5226 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5227 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5228 (match_operand:SF 2 "gpc_reg_operand" "f")]
5229 UNSPEC_FRES))]
5230 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5231 && flag_finite_math_only && !flag_trapping_math"
5232{
5233 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5234 DONE;
5235})
5236
5237(define_insn "fres"
5238 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5239 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5240 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5241 "fres %0,%1"
5242 [(set_attr "type" "fp")])
5243
1fd4e8c1 5244(define_insn ""
cd2b37d9
RK		 5245 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5246 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5247 (match_operand:SF 2 "gpc_reg_operand" "f"))
5248 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5249 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5250 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 5251 [(set_attr "type" "fp")])
5252
5253(define_insn ""
5254 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5255 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5256 (match_operand:SF 2 "gpc_reg_operand" "f"))
5257 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5258 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5259 "{fma|fmadd} %0,%1,%2,%3"
cf27b467 5260 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5261
5262(define_insn ""
cd2b37d9
RK		 5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5265 (match_operand:SF 2 "gpc_reg_operand" "f"))
5266 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5267 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5268 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 5269 [(set_attr "type" "fp")])
5270
5271(define_insn ""
5272 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5273 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5274 (match_operand:SF 2 "gpc_reg_operand" "f"))
5275 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5276 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5277 "{fms|fmsub} %0,%1,%2,%3"
cf27b467 5278 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5279
5280(define_insn ""
cd2b37d9
RK		 5281 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5282 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5283 (match_operand:SF 2 "gpc_reg_operand" "f"))
5284 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5285 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5286 && HONOR_SIGNED_ZEROS (SFmode)"
5287 "fnmadds %0,%1,%2,%3"
5288 [(set_attr "type" "fp")])
5289
5290(define_insn ""
5291 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5292 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5293 (match_operand:SF 2 "gpc_reg_operand" "f"))
5294 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5295 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5296 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5297 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 5298 [(set_attr "type" "fp")])
5299
5300(define_insn ""
5301 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5302 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5303 (match_operand:SF 2 "gpc_reg_operand" "f"))
5304 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 5305 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5306 "{fnma|fnmadd} %0,%1,%2,%3"
cf27b467 5307 [(set_attr "type" "dmul")])
1fd4e8c1 5308
16823694
GK		 5309(define_insn ""
5310 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5311 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5312 (match_operand:SF 2 "gpc_reg_operand" "f"))
5313 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5314 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5315 && ! HONOR_SIGNED_ZEROS (SFmode)"
5316 "{fnma|fnmadd} %0,%1,%2,%3"
5317 [(set_attr "type" "dmul")])
5318
1fd4e8c1 5319(define_insn ""
cd2b37d9
RK		 5320 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5321 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5322 (match_operand:SF 2 "gpc_reg_operand" "f"))
5323 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5324 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5325 && HONOR_SIGNED_ZEROS (SFmode)"
5326 "fnmsubs %0,%1,%2,%3"
5327 [(set_attr "type" "fp")])
5328
5329(define_insn ""
5330 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5331 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5332 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5333 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5334 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5335 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5336 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 5337 [(set_attr "type" "fp")])
5338
5339(define_insn ""
5340 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5341 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5342 (match_operand:SF 2 "gpc_reg_operand" "f"))
5343 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 5344 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5345 "{fnms|fnmsub} %0,%1,%2,%3"
cf27b467 5346 [(set_attr "type" "dmul")])
1fd4e8c1 5347
16823694
GK		 5348(define_insn ""
5349 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5350 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5351 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5352 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5353 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5354 && ! HONOR_SIGNED_ZEROS (SFmode)"
5355 "{fnms|fnmsub} %0,%1,%2,%3"
9c6fdb46 5356 [(set_attr "type" "dmul")])
16823694 5357
ca7f5001
RK		 5358(define_expand "sqrtsf2"
5359 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5360 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
a3170dc6 5361 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5362 "")
5363
5364(define_insn ""
5365 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5366 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5367 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5368 "fsqrts %0,%1"
5369 [(set_attr "type" "ssqrt")])
5370
5371(define_insn ""
5372 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5373 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5374 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5375 "fsqrt %0,%1"
5376 [(set_attr "type" "dsqrt")])
5377
9c78b944
DE		 5378(define_expand "rsqrtsf2"
5379 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5380 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5381 UNSPEC_RSQRT))]
5382 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5383 && flag_finite_math_only && !flag_trapping_math"
5384{
5385 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5386 DONE;
5387})
5388
5389(define_insn "*rsqrt_internal1"
5390 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5391 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5392 UNSPEC_RSQRT))]
5393 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5394 "frsqrte %0,%1"
5395 [(set_attr "type" "fp")])
5396
0530bc70
AP		 5397(define_expand "copysignsf3"
5398 [(set (match_dup 3)
5399 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5400 (set (match_dup 4)
5401 (neg:SF (abs:SF (match_dup 1))))
5402 (set (match_operand:SF 0 "gpc_reg_operand" "")
5403 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5404 (match_dup 5))
5405 (match_dup 3)
5406 (match_dup 4)))]
5407 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
bb8df8a6 5408 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
0530bc70
AP		 5409 {
5410 operands[3] = gen_reg_rtx (SFmode);
5411 operands[4] = gen_reg_rtx (SFmode);
5412 operands[5] = CONST0_RTX (SFmode);
5413 })
5414
5415(define_expand "copysigndf3"
5416 [(set (match_dup 3)
5417 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5418 (set (match_dup 4)
5419 (neg:DF (abs:DF (match_dup 1))))
5420 (set (match_operand:DF 0 "gpc_reg_operand" "")
5421 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5422 (match_dup 5))
5423 (match_dup 3)
5424 (match_dup 4)))]
5425 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5426 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5427 {
5428 operands[3] = gen_reg_rtx (DFmode);
5429 operands[4] = gen_reg_rtx (DFmode);
5430 operands[5] = CONST0_RTX (DFmode);
5431 })
5432
94d7001a
RK		 5433;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5434;; fsel instruction and some auxiliary computations. Then we just have a
5435;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05 5436;; combine.
7ae4d8d4 5437(define_expand "smaxsf3"
8e871c05 5438 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5439 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5440 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5441 (match_dup 1)
5442 (match_dup 2)))]
89e73849 5443 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5444 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 5445
7ae4d8d4 5446(define_expand "sminsf3"
50a0b056
GK		 5447 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5448 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5449 (match_operand:SF 2 "gpc_reg_operand" ""))
5450 (match_dup 2)
5451 (match_dup 1)))]
89e73849 5452 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5453 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 5454
8e871c05
RK		 5455(define_split
5456 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5457 (match_operator:SF 3 "min_max_operator"
5458 [(match_operand:SF 1 "gpc_reg_operand" "")
5459 (match_operand:SF 2 "gpc_reg_operand" "")]))]
89e73849 5460 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5461 [(const_int 0)]
5462 "
6ae08853 5463{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5464 operands[1], operands[2]);
5465 DONE;
5466}")
2f607b94 5467
a3170dc6
AH		 5468(define_expand "movsicc"
5469 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5470 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5471 (match_operand:SI 2 "gpc_reg_operand" "")
5472 (match_operand:SI 3 "gpc_reg_operand" "")))]
5473 "TARGET_ISEL"
5474 "
5475{
5476 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5477 DONE;
5478 else
5479 FAIL;
5480}")
5481
5482;; We use the BASE_REGS for the isel input operands because, if rA is
5483;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5484;; because we may switch the operands and rB may end up being rA.
5485;;
5486;; We need 2 patterns: an unsigned and a signed pattern. We could
5487;; leave out the mode in operand 4 and use one pattern, but reload can
5488;; change the mode underneath our feet and then gets confused trying
5489;; to reload the value.
5490(define_insn "isel_signed"
5491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5492 (if_then_else:SI
5493 (match_operator 1 "comparison_operator"
5494 [(match_operand:CC 4 "cc_reg_operand" "y")
5495 (const_int 0)])
5496 (match_operand:SI 2 "gpc_reg_operand" "b")
5497 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5498 "TARGET_ISEL"
5499 "*
5500{ return output_isel (operands); }"
5501 [(set_attr "length" "4")])
5502
5503(define_insn "isel_unsigned"
5504 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5505 (if_then_else:SI
5506 (match_operator 1 "comparison_operator"
5507 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5508 (const_int 0)])
5509 (match_operand:SI 2 "gpc_reg_operand" "b")
5510 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5511 "TARGET_ISEL"
5512 "*
5513{ return output_isel (operands); }"
5514 [(set_attr "length" "4")])
5515
94d7001a 5516(define_expand "movsfcc"
0ad91047 5517 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 5518 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5519 (match_operand:SF 2 "gpc_reg_operand" "")
5520 (match_operand:SF 3 "gpc_reg_operand" "")))]
a3170dc6 5521 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5522 "
5523{
50a0b056
GK		 5524 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5525 DONE;
94d7001a 5526 else
50a0b056 5527 FAIL;
94d7001a 5528}")
d56d506a 5529
50a0b056 5530(define_insn "*fselsfsf4"
8e871c05
RK		 5531 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5532 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5533 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5534 (match_operand:SF 2 "gpc_reg_operand" "f")
5535 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5536 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5537 "fsel %0,%1,%2,%3"
5538 [(set_attr "type" "fp")])
2f607b94 5539
50a0b056 5540(define_insn "*fseldfsf4"
94d7001a
RK		 5541 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5542 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 5543 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5544 (match_operand:SF 2 "gpc_reg_operand" "f")
5545 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5546 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5547 "fsel %0,%1,%2,%3"
5548 [(set_attr "type" "fp")])
d56d506a 5549
7a2f7870
AH		 5550(define_expand "negdf2"
5551 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5552 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5553 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5554 "")
5555
99176a91 5556(define_insn "*negdf2_fpr"
cd2b37d9
RK		 5557 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5558 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5559 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5560 "fneg %0,%1"
5561 [(set_attr "type" "fp")])
5562
7a2f7870
AH		 5563(define_expand "absdf2"
5564 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5565 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5566 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5567 "")
5568
99176a91 5569(define_insn "*absdf2_fpr"
cd2b37d9
RK		 5570 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5571 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5572 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5573 "fabs %0,%1"
5574 [(set_attr "type" "fp")])
5575
99176a91 5576(define_insn "*nabsdf2_fpr"
cd2b37d9
RK		 5577 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5578 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
a3170dc6 5579 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5580 "fnabs %0,%1"
5581 [(set_attr "type" "fp")])
5582
7a2f7870
AH		 5583(define_expand "adddf3"
5584 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5585 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5586 (match_operand:DF 2 "gpc_reg_operand" "")))]
5587 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5588 "")
5589
99176a91 5590(define_insn "*adddf3_fpr"
cd2b37d9
RK		 5591 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5592 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5593 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5594 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5595 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 5596 [(set_attr "type" "fp")])
5597
7a2f7870
AH		 5598(define_expand "subdf3"
5599 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5600 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5601 (match_operand:DF 2 "gpc_reg_operand" "")))]
5602 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5603 "")
5604
99176a91 5605(define_insn "*subdf3_fpr"
cd2b37d9
RK		 5606 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5607 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5608 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5609 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5610 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 5611 [(set_attr "type" "fp")])
5612
7a2f7870
AH		 5613(define_expand "muldf3"
5614 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5615 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5616 (match_operand:DF 2 "gpc_reg_operand" "")))]
5617 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5618 "")
5619
99176a91 5620(define_insn "*muldf3_fpr"
cd2b37d9
RK		 5621 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5622 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5623 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5624 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5625 "{fm|fmul} %0,%1,%2"
cfb557c4 5626 [(set_attr "type" "dmul")])
1fd4e8c1 5627
7a2f7870
AH		 5628(define_expand "divdf3"
5629 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5630 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5631 (match_operand:DF 2 "gpc_reg_operand" "")))]
5632 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
9c78b944 5633 "")
7a2f7870 5634
99176a91 5635(define_insn "*divdf3_fpr"
cd2b37d9
RK		 5636 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5637 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5638 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5639 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5640 "{fd|fdiv} %0,%1,%2"
cfb557c4 5641 [(set_attr "type" "ddiv")])
1fd4e8c1 5642
9c78b944
DE		 5643(define_expand "recipdf3"
5644 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5645 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5646 (match_operand:DF 2 "gpc_reg_operand" "f")]
5647 UNSPEC_FRES))]
5648 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5649 && flag_finite_math_only && !flag_trapping_math"
5650{
5651 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5652 DONE;
5653})
5654
5655(define_insn "fred"
5656 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5657 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5658 "TARGET_POPCNTB && flag_finite_math_only"
5659 "fre %0,%1"
5660 [(set_attr "type" "fp")])
5661
1fd4e8c1 5662(define_insn ""
cd2b37d9
RK		 5663 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5664 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5665 (match_operand:DF 2 "gpc_reg_operand" "f"))
5666 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5667 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5668 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 5669 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5670
5671(define_insn ""
cd2b37d9
RK		 5672 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5673 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5674 (match_operand:DF 2 "gpc_reg_operand" "f"))
5675 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5676 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5677 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 5678 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5679
5680(define_insn ""
cd2b37d9
RK		 5681 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5682 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5683 (match_operand:DF 2 "gpc_reg_operand" "f"))
5684 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5685 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5686 && HONOR_SIGNED_ZEROS (DFmode)"
5687 "{fnma|fnmadd} %0,%1,%2,%3"
5688 [(set_attr "type" "dmul")])
5689
5690(define_insn ""
5691 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5692 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5693 (match_operand:DF 2 "gpc_reg_operand" "f"))
5694 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5695 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5696 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5697 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 5698 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5699
5700(define_insn ""
cd2b37d9
RK		 5701 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5702 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5703 (match_operand:DF 2 "gpc_reg_operand" "f"))
5704 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5705 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5706 && HONOR_SIGNED_ZEROS (DFmode)"
5707 "{fnms|fnmsub} %0,%1,%2,%3"
5708 [(set_attr "type" "dmul")])
5709
5710(define_insn ""
5711 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5712 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5713 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5714 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
6ae08853 5715 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5716 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5717 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 5718 [(set_attr "type" "dmul")])
ca7f5001
RK		 5719
5720(define_insn "sqrtdf2"
5721 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5722 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5723 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5724 "fsqrt %0,%1"
5725 [(set_attr "type" "dsqrt")])
b77dfefc 5726
50a0b056 5727;; The conditional move instructions allow us to perform max and min
6ae08853 5728;; operations even when
b77dfefc 5729
7ae4d8d4 5730(define_expand "smaxdf3"
8e871c05 5731 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5732 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5733 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5734 (match_dup 1)
5735 (match_dup 2)))]
89e73849 5736 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5737 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 5738
7ae4d8d4 5739(define_expand "smindf3"
50a0b056
GK		 5740 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5741 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5742 (match_operand:DF 2 "gpc_reg_operand" ""))
5743 (match_dup 2)
5744 (match_dup 1)))]
89e73849 5745 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5746 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 5747
8e871c05
RK		 5748(define_split
5749 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5750 (match_operator:DF 3 "min_max_operator"
5751 [(match_operand:DF 1 "gpc_reg_operand" "")
5752 (match_operand:DF 2 "gpc_reg_operand" "")]))]
89e73849 5753 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5754 [(const_int 0)]
5755 "
6ae08853 5756{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5757 operands[1], operands[2]);
5758 DONE;
5759}")
b77dfefc 5760
94d7001a 5761(define_expand "movdfcc"
0ad91047 5762 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 5763 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5764 (match_operand:DF 2 "gpc_reg_operand" "")
5765 (match_operand:DF 3 "gpc_reg_operand" "")))]
a3170dc6 5766 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5767 "
5768{
50a0b056
GK		 5769 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5770 DONE;
94d7001a 5771 else
50a0b056 5772 FAIL;
94d7001a 5773}")
d56d506a 5774
50a0b056 5775(define_insn "*fseldfdf4"
8e871c05
RK		 5776 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5777 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 5778 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5779 (match_operand:DF 2 "gpc_reg_operand" "f")
5780 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5781 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5782 "fsel %0,%1,%2,%3"
5783 [(set_attr "type" "fp")])
d56d506a 5784
50a0b056 5785(define_insn "*fselsfdf4"
94d7001a
RK		 5786 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5787 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5788 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5789 (match_operand:DF 2 "gpc_reg_operand" "f")
5790 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5791 "TARGET_PPC_GFXOPT"
5792 "fsel %0,%1,%2,%3"
5793 [(set_attr "type" "fp")])
1fd4e8c1 5794\f
d095928f
AH		 5795;; Conversions to and from floating-point.
5796
5797(define_expand "fixuns_truncsfsi2"
5798 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5799 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5800 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5801 "")
5802
5803(define_expand "fix_truncsfsi2"
5804 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5805 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5806 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5807 "")
5808
9ebbca7d
GK		 5809; For each of these conversions, there is a define_expand, a define_insn
5810; with a '#' template, and a define_split (with C code). The idea is
5811; to allow constant folding with the template of the define_insn,
5812; then to have the insns split later (between sched1 and final).
5813
1fd4e8c1 5814(define_expand "floatsidf2"
802a0058
MM		 5815 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5816 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5817 (use (match_dup 2))
5818 (use (match_dup 3))
208c89ce 5819 (clobber (match_dup 4))
a7df97e6 5820 (clobber (match_dup 5))
9ebbca7d 5821 (clobber (match_dup 6))])]
17caeff2 5822 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5823 "
5824{
99176a91
AH		 5825 if (TARGET_E500_DOUBLE)
5826 {
5827 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5828 DONE;
5829 }
44cd321e
PS		 5830 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5831 {
5832 rtx t1 = gen_reg_rtx (DImode);
5833 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5834 DONE;
5835 }
05d49501
AM		 5836 if (TARGET_POWERPC64)
5837 {
5838 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5839 rtx t1 = gen_reg_rtx (DImode);
5840 rtx t2 = gen_reg_rtx (DImode);
5841 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5842 DONE;
5843 }
5844
802a0058 5845 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5846 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5847 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5848 operands[5] = gen_reg_rtx (DFmode);
5849 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5850}")
5851
230215f5 5852(define_insn_and_split "*floatsidf2_internal"
802a0058
MM		 5853 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5854 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5855 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5856 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
b0d6c7d8 5857 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6f9c81f5
DJ		 5858 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5859 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
a3170dc6 5860 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5861 "#"
b3a13419 5862 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5863 [(pc)]
208c89ce
MM		 5864 "
5865{
9ebbca7d 5866 rtx lowword, highword;
230215f5
GK		 5867 gcc_assert (MEM_P (operands[4]));
5868 highword = adjust_address (operands[4], SImode, 0);
5869 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d
GK		 5870 if (! WORDS_BIG_ENDIAN)
5871 {
5872 rtx tmp;
5873 tmp = highword; highword = lowword; lowword = tmp;
5874 }
5875
6ae08853 5876 emit_insn (gen_xorsi3 (operands[6], operands[1],
9ebbca7d 5877 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
230215f5
GK		 5878 emit_move_insn (lowword, operands[6]);
5879 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5880 emit_move_insn (operands[5], operands[4]);
5881 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5882 DONE;
230215f5
GK		 5883}"
5884 [(set_attr "length" "24")])
802a0058 5885
a3170dc6
AH		 5886(define_expand "floatunssisf2"
5887 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5888 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5889 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5890 "")
5891
802a0058
MM		 5892(define_expand "floatunssidf2"
5893 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5894 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5895 (use (match_dup 2))
5896 (use (match_dup 3))
a7df97e6 5897 (clobber (match_dup 4))
9ebbca7d 5898 (clobber (match_dup 5))])]
99176a91 5899 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5900 "
5901{
99176a91
AH		 5902 if (TARGET_E500_DOUBLE)
5903 {
5904 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5905 DONE;
5906 }
05d49501
AM		 5907 if (TARGET_POWERPC64)
5908 {
5909 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5910 rtx t1 = gen_reg_rtx (DImode);
5911 rtx t2 = gen_reg_rtx (DImode);
5912 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5913 t1, t2));
5914 DONE;
5915 }
5916
802a0058 5917 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5918 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 5919 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5920 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 5921}")
5922
230215f5 5923(define_insn_and_split "*floatunssidf2_internal"
802a0058
MM		 5924 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5925 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5926 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5927 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
b0d6c7d8 5928 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6f9c81f5 5929 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
a3170dc6 5930 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5931 "#"
b3a13419 5932 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5933 [(pc)]
9ebbca7d 5934 "
802a0058 5935{
9ebbca7d 5936 rtx lowword, highword;
230215f5
GK		 5937 gcc_assert (MEM_P (operands[4]));
5938 highword = adjust_address (operands[4], SImode, 0);
5939 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d 5940 if (! WORDS_BIG_ENDIAN)
f6968f59 5941 {
9ebbca7d
GK		 5942 rtx tmp;
5943 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 5944 }
802a0058 5945
230215f5
GK		 5946 emit_move_insn (lowword, operands[1]);
5947 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5948 emit_move_insn (operands[5], operands[4]);
5949 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5950 DONE;
230215f5
GK		 5951}"
5952 [(set_attr "length" "20")])
1fd4e8c1 5953
1fd4e8c1 5954(define_expand "fix_truncdfsi2"
045a8eb3 5955 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
802a0058
MM		 5956 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5957 (clobber (match_dup 2))
9ebbca7d 5958 (clobber (match_dup 3))])]
99176a91
AH		 5959 "(TARGET_POWER2 || TARGET_POWERPC)
5960 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5961 "
5962{
99176a91
AH		 5963 if (TARGET_E500_DOUBLE)
5964 {
5965 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5966 DONE;
5967 }
802a0058 5968 operands[2] = gen_reg_rtx (DImode);
44cd321e
PS		 5969 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5970 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5971 {
5972 operands[3] = gen_reg_rtx (DImode);
5973 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5974 operands[2], operands[3]));
5975 DONE;
5976 }
da4c340c
GK		 5977 if (TARGET_PPC_GFXOPT)
5978 {
5979 rtx orig_dest = operands[0];
045a8eb3 5980 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
da4c340c
GK		 5981 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5982 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5983 operands[2]));
5984 if (operands[0] != orig_dest)
5985 emit_move_insn (orig_dest, operands[0]);
5986 DONE;
5987 }
9ebbca7d 5988 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 5989}")
5990
da4c340c 5991(define_insn_and_split "*fix_truncdfsi2_internal"
802a0058
MM		 5992 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5993 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 5994 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
b0d6c7d8 5995 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
a3170dc6 5996 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5997 "#"
b3a13419 5998 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
da4c340c 5999 [(pc)]
9ebbca7d 6000 "
802a0058 6001{
9ebbca7d 6002 rtx lowword;
230215f5
GK		 6003 gcc_assert (MEM_P (operands[3]));
6004 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
802a0058 6005
9ebbca7d
GK		 6006 emit_insn (gen_fctiwz (operands[2], operands[1]));
6007 emit_move_insn (operands[3], operands[2]);
230215f5 6008 emit_move_insn (operands[0], lowword);
9ebbca7d 6009 DONE;
da4c340c
GK		 6010}"
6011 [(set_attr "length" "16")])
6012
6013(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6014 [(set (match_operand:SI 0 "memory_operand" "=Z")
6015 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6016 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
6017 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6018 && TARGET_PPC_GFXOPT"
6019 "#"
6020 "&& 1"
6021 [(pc)]
6022 "
6023{
6024 emit_insn (gen_fctiwz (operands[2], operands[1]));
6025 emit_insn (gen_stfiwx (operands[0], operands[2]));
6026 DONE;
6027}"
6028 [(set_attr "length" "16")])
802a0058 6029
44cd321e
PS		 6030(define_insn_and_split "fix_truncdfsi2_mfpgpr"
6031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6032 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6033 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6034 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6035 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6036 "#"
6037 "&& 1"
6038 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6039 (set (match_dup 3) (match_dup 2))
6040 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6041 ""
6042 [(set_attr "length" "12")])
6043
615158e2 6044; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 6045; rather than (set (subreg:SI (reg)) (fix:SI ...))
6046; because the first makes it clear that operand 0 is not live
6047; before the instruction.
6048(define_insn "fctiwz"
da4c340c 6049 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
615158e2
JJ		 6050 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6051 UNSPEC_FCTIWZ))]
a3170dc6 6052 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
a260abc9
DE		 6053 "{fcirz|fctiwz} %0,%1"
6054 [(set_attr "type" "fp")])
6055
9719f3b7
DE		 6056(define_insn "btruncdf2"
6057 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6058 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6059 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6060 "friz %0,%1"
6061 [(set_attr "type" "fp")])
6062
6063(define_insn "btruncsf2"
6064 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6065 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6066 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6067 "friz %0,%1"
9719f3b7
DE		 6068 [(set_attr "type" "fp")])
6069
6070(define_insn "ceildf2"
6071 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6072 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6073 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6074 "frip %0,%1"
6075 [(set_attr "type" "fp")])
6076
6077(define_insn "ceilsf2"
833126ad 6078 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9719f3b7
DE		 6079 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6080 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6081 "frip %0,%1"
9719f3b7
DE		 6082 [(set_attr "type" "fp")])
6083
6084(define_insn "floordf2"
6085 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6086 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6087 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6088 "frim %0,%1"
6089 [(set_attr "type" "fp")])
6090
6091(define_insn "floorsf2"
6092 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6093 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6094 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6095 "frim %0,%1"
9719f3b7
DE		 6096 [(set_attr "type" "fp")])
6097
6098(define_insn "rounddf2"
6099 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6100 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6101 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6102 "frin %0,%1"
6103 [(set_attr "type" "fp")])
6104
6105(define_insn "roundsf2"
6106 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6107 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6108 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6109 "frin %0,%1"
9719f3b7
DE		 6110 [(set_attr "type" "fp")])
6111
da4c340c
GK		 6112; An UNSPEC is used so we don't have to support SImode in FP registers.
6113(define_insn "stfiwx"
6114 [(set (match_operand:SI 0 "memory_operand" "=Z")
6115 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6116 UNSPEC_STFIWX))]
6117 "TARGET_PPC_GFXOPT"
6118 "stfiwx %1,%y0"
6119 [(set_attr "type" "fpstore")])
6120
a3170dc6
AH		 6121(define_expand "floatsisf2"
6122 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6123 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6124 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6125 "")
6126
a473029f
RK		 6127(define_insn "floatdidf2"
6128 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
94e98316 6129 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
a3170dc6 6130 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6131 "fcfid %0,%1"
6132 [(set_attr "type" "fp")])
6133
44cd321e
PS		 6134(define_insn_and_split "floatsidf_ppc64_mfpgpr"
6135 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6136 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6137 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6138 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6139 "#"
6140 "&& 1"
6141 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6142 (set (match_dup 0) (float:DF (match_dup 2)))]
6143 "")
6144
05d49501
AM		 6145(define_insn_and_split "floatsidf_ppc64"
6146 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6147 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
b0d6c7d8 6148 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
05d49501
AM		 6149 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6150 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
44cd321e 6151 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 6152 "#"
ecb62ae7 6153 "&& 1"
05d49501
AM		 6154 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6155 (set (match_dup 2) (match_dup 3))
6156 (set (match_dup 4) (match_dup 2))
6157 (set (match_dup 0) (float:DF (match_dup 4)))]
6158 "")
6159
6160(define_insn_and_split "floatunssidf_ppc64"
6161 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6162 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
b0d6c7d8 6163 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
05d49501
AM		 6164 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6165 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 6166 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 6167 "#"
ecb62ae7 6168 "&& 1"
05d49501
AM		 6169 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6170 (set (match_dup 2) (match_dup 3))
6171 (set (match_dup 4) (match_dup 2))
6172 (set (match_dup 0) (float:DF (match_dup 4)))]
6173 "")
6174
a473029f 6175(define_insn "fix_truncdfdi2"
94e98316 6176 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
a473029f 6177 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 6178 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6179 "fctidz %0,%1"
6180 [(set_attr "type" "fp")])
ea112fc4 6181
678b7733
AM		 6182(define_expand "floatdisf2"
6183 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6184 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
994cf173 6185 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6186 "
6187{
994cf173 6188 rtx val = operands[1];
678b7733
AM		 6189 if (!flag_unsafe_math_optimizations)
6190 {
6191 rtx label = gen_label_rtx ();
994cf173
AM		 6192 val = gen_reg_rtx (DImode);
6193 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
678b7733
AM		 6194 emit_label (label);
6195 }
994cf173 6196 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
678b7733
AM		 6197 DONE;
6198}")
6199
6200;; This is not IEEE compliant if rounding mode is "round to nearest".
6201;; If the DI->DF conversion is inexact, then it's possible to suffer
6202;; from double rounding.
6203(define_insn_and_split "floatdisf2_internal1"
ea112fc4 6204 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
94e98316 6205 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
ea112fc4 6206 (clobber (match_scratch:DF 2 "=f"))]
678b7733 6207 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
ea112fc4
DE		 6208 "#"
6209 "&& reload_completed"
6210 [(set (match_dup 2)
6211 (float:DF (match_dup 1)))
6212 (set (match_dup 0)
6213 (float_truncate:SF (match_dup 2)))]
6214 "")
678b7733
AM		 6215
6216;; Twiddles bits to avoid double rounding.
b6d08ca1 6217;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 6218;; by a bit that won't be lost at that stage, but is below the SFmode
6219;; rounding position.
6220(define_expand "floatdisf2_internal2"
994cf173
AM		 6221 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6222 (const_int 53)))
6223 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6224 (const_int 2047)))
6225 (clobber (scratch:CC))])
6226 (set (match_dup 3) (plus:DI (match_dup 3)
6227 (const_int 1)))
6228 (set (match_dup 0) (plus:DI (match_dup 0)
6229 (const_int 2047)))
6230 (set (match_dup 4) (compare:CCUNS (match_dup 3)
c22e62a6 6231 (const_int 2)))
994cf173
AM		 6232 (set (match_dup 0) (ior:DI (match_dup 0)
6233 (match_dup 1)))
6234 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6235 (const_int -2048)))
6236 (clobber (scratch:CC))])
6237 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6238 (label_ref (match_operand:DI 2 "" ""))
678b7733 6239 (pc)))
994cf173
AM		 6240 (set (match_dup 0) (match_dup 1))]
6241 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6242 "
6243{
678b7733 6244 operands[3] = gen_reg_rtx (DImode);
994cf173 6245 operands[4] = gen_reg_rtx (CCUNSmode);
678b7733 6246}")
1fd4e8c1
RK		 6247\f
6248;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 6249;; of instructions. The & constraints are to prevent the register
6250;; allocator from allocating registers that overlap with the inputs
6251;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 6252;; also allow for the output being the same as one of the inputs.
a6ec530c 6253
266eb58a 6254(define_insn "*adddi3_noppc64"
a6ec530c
RK		 6255 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6256 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6257 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 6258 "! TARGET_POWERPC64"
0f645302
MM		 6259 "*
6260{
6261 if (WORDS_BIG_ENDIAN)
6262 return (GET_CODE (operands[2])) != CONST_INT
6263 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6264 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6265 else
6266 return (GET_CODE (operands[2])) != CONST_INT
6267 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6268 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6269}"
943c15ed
DE		 6270 [(set_attr "type" "two")
6271 (set_attr "length" "8")])
1fd4e8c1 6272
266eb58a 6273(define_insn "*subdi3_noppc64"
e7e5df70
RK		 6274 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6275 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6276 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 6277 "! TARGET_POWERPC64"
5502823b
RK		 6278 "*
6279{
0f645302
MM		 6280 if (WORDS_BIG_ENDIAN)
6281 return (GET_CODE (operands[1]) != CONST_INT)
6282 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6283 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6284 else
6285 return (GET_CODE (operands[1]) != CONST_INT)
6286 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6287 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 6288}"
943c15ed
DE		 6289 [(set_attr "type" "two")
6290 (set_attr "length" "8")])
ca7f5001 6291
266eb58a 6292(define_insn "*negdi2_noppc64"
a6ec530c
RK		 6293 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6294 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 6295 "! TARGET_POWERPC64"
5502823b
RK		 6296 "*
6297{
6298 return (WORDS_BIG_ENDIAN)
6299 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6300 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6301}"
943c15ed
DE		 6302 [(set_attr "type" "two")
6303 (set_attr "length" "8")])
ca7f5001 6304
8ffd9c51
RK		 6305(define_expand "mulsidi3"
6306 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6307 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6308 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 6309 "! TARGET_POWERPC64"
8ffd9c51
RK		 6310 "
6311{
6312 if (! TARGET_POWER && ! TARGET_POWERPC)
6313 {
39403d82
DE		 6314 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6315 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6316 emit_insn (gen_mull_call ());
cf27b467 6317 if (WORDS_BIG_ENDIAN)
39403d82 6318 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 6319 else
6320 {
6321 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 6322 gen_rtx_REG (SImode, 3));
cf27b467 6323 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 6324 gen_rtx_REG (SImode, 4));
cf27b467 6325 }
8ffd9c51
RK		 6326 DONE;
6327 }
6328 else if (TARGET_POWER)
6329 {
6330 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6331 DONE;
6332 }
6333}")
deb9225a 6334
8ffd9c51 6335(define_insn "mulsidi3_mq"
cd2b37d9 6336 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 6337 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 6338 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 6339 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 6340 "TARGET_POWER"
b19003d8 6341 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 6342 [(set_attr "type" "imul")
6343 (set_attr "length" "8")])
deb9225a 6344
f192bf8b 6345(define_insn "*mulsidi3_no_mq"
425c176f 6346 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 6347 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6348 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6349 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 6350 "*
6351{
6352 return (WORDS_BIG_ENDIAN)
6353 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6354 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6355}"
8ffd9c51
RK		 6356 [(set_attr "type" "imul")
6357 (set_attr "length" "8")])
deb9225a 6358
ebedb4dd
MM		 6359(define_split
6360 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6361 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6362 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6363 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6364 [(set (match_dup 3)
6365 (truncate:SI
6366 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6367 (sign_extend:DI (match_dup 2)))
6368 (const_int 32))))
6369 (set (match_dup 4)
6370 (mult:SI (match_dup 1)
6371 (match_dup 2)))]
6372 "
6373{
6374 int endian = (WORDS_BIG_ENDIAN == 0);
6375 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6376 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6377}")
6378
f192bf8b
DE		 6379(define_expand "umulsidi3"
6380 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6381 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6382 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6383 "TARGET_POWERPC && ! TARGET_POWERPC64"
6384 "
6385{
6386 if (TARGET_POWER)
6387 {
6388 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6389 DONE;
6390 }
6391}")
6392
6393(define_insn "umulsidi3_mq"
6394 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6395 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6396 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6397 (clobber (match_scratch:SI 3 "=q"))]
6398 "TARGET_POWERPC && TARGET_POWER"
6399 "*
6400{
6401 return (WORDS_BIG_ENDIAN)
6402 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6403 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6404}"
6405 [(set_attr "type" "imul")
6406 (set_attr "length" "8")])
6407
6408(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 6409 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6410 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6411 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6412 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 6413 "*
6414{
6415 return (WORDS_BIG_ENDIAN)
6416 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6417 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6418}"
6419 [(set_attr "type" "imul")
6420 (set_attr "length" "8")])
6421
ebedb4dd
MM		 6422(define_split
6423 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6424 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6425 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6426 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6427 [(set (match_dup 3)
6428 (truncate:SI
6429 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6430 (zero_extend:DI (match_dup 2)))
6431 (const_int 32))))
6432 (set (match_dup 4)
6433 (mult:SI (match_dup 1)
6434 (match_dup 2)))]
6435 "
6436{
6437 int endian = (WORDS_BIG_ENDIAN == 0);
6438 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6439 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6440}")
6441
8ffd9c51
RK		 6442(define_expand "smulsi3_highpart"
6443 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6444 (truncate:SI
6445 (lshiftrt:DI (mult:DI (sign_extend:DI
e42ac3de 6446 (match_operand:SI 1 "gpc_reg_operand" ""))
8ffd9c51 6447 (sign_extend:DI
e42ac3de 6448 (match_operand:SI 2 "gpc_reg_operand" "")))
8ffd9c51
RK		 6449 (const_int 32))))]
6450 ""
6451 "
6452{
6453 if (! TARGET_POWER && ! TARGET_POWERPC)
6454 {
39403d82
DE		 6455 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6456 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6457 emit_insn (gen_mulh_call ());
39403d82 6458 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 6459 DONE;
6460 }
6461 else if (TARGET_POWER)
6462 {
6463 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6464 DONE;
6465 }
6466}")
deb9225a 6467
8ffd9c51
RK		 6468(define_insn "smulsi3_highpart_mq"
6469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6470 (truncate:SI
fada905b
MM		 6471 (lshiftrt:DI (mult:DI (sign_extend:DI
6472 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6473 (sign_extend:DI
6474 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 6475 (const_int 32))))
6476 (clobber (match_scratch:SI 3 "=q"))]
6477 "TARGET_POWER"
6478 "mul %0,%1,%2"
6479 [(set_attr "type" "imul")])
deb9225a 6480
f192bf8b 6481(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 6482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6483 (truncate:SI
fada905b
MM		 6484 (lshiftrt:DI (mult:DI (sign_extend:DI
6485 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6486 (sign_extend:DI
6487 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 6488 (const_int 32))))]
f192bf8b 6489 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 6490 "mulhw %0,%1,%2"
6491 [(set_attr "type" "imul")])
deb9225a 6492
f192bf8b
DE		 6493(define_expand "umulsi3_highpart"
6494 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6495 (truncate:SI
6496 (lshiftrt:DI (mult:DI (zero_extend:DI
6497 (match_operand:SI 1 "gpc_reg_operand" ""))
6498 (zero_extend:DI
6499 (match_operand:SI 2 "gpc_reg_operand" "")))
6500 (const_int 32))))]
6501 "TARGET_POWERPC"
6502 "
6503{
6504 if (TARGET_POWER)
6505 {
6506 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6507 DONE;
6508 }
6509}")
6510
6511(define_insn "umulsi3_highpart_mq"
6512 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6513 (truncate:SI
6514 (lshiftrt:DI (mult:DI (zero_extend:DI
6515 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6516 (zero_extend:DI
6517 (match_operand:SI 2 "gpc_reg_operand" "r")))
6518 (const_int 32))))
6519 (clobber (match_scratch:SI 3 "=q"))]
6520 "TARGET_POWERPC && TARGET_POWER"
6521 "mulhwu %0,%1,%2"
6522 [(set_attr "type" "imul")])
6523
6524(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 6525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6526 (truncate:SI
6527 (lshiftrt:DI (mult:DI (zero_extend:DI
6528 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6529 (zero_extend:DI
6530 (match_operand:SI 2 "gpc_reg_operand" "r")))
6531 (const_int 32))))]
f192bf8b 6532 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 6533 "mulhwu %0,%1,%2"
6534 [(set_attr "type" "imul")])
6535
6536;; If operands 0 and 2 are in the same register, we have a problem. But
6537;; operands 0 and 1 (the usual case) can be in the same register. That's
6538;; why we have the strange constraints below.
6539(define_insn "ashldi3_power"
6540 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6541 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6542 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6543 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6544 "TARGET_POWER"
6545 "@
6546 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6547 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6548 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6549 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6550 [(set_attr "length" "8")])
6551
6552(define_insn "lshrdi3_power"
47ad8c61 6553 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 6554 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6555 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6556 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6557 "TARGET_POWER"
6558 "@
47ad8c61 6559 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 6560 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6561 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6562 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6563 [(set_attr "length" "8")])
6564
6565;; Shift by a variable amount is too complex to be worth open-coding. We
6566;; just handle shifts by constants.
6567(define_insn "ashrdi3_power"
7093ddee 6568 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 6569 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6570 (match_operand:SI 2 "const_int_operand" "M,i")))
6571 (clobber (match_scratch:SI 3 "=X,q"))]
6572 "TARGET_POWER"
6573 "@
6574 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6575 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
44cd321e
PS		 6576 [(set_attr "type" "shift")
6577 (set_attr "length" "8")])
4aa74a4f
FS		 6578
6579(define_insn "ashrdi3_no_power"
6580 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6581 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6582 (match_operand:SI 2 "const_int_operand" "M,i")))]
97727e85 6583 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
4aa74a4f
FS		 6584 "@
6585 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6586 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
943c15ed
DE		 6587 [(set_attr "type" "two,three")
6588 (set_attr "length" "8,12")])
683bdff7
FJ		 6589
6590(define_insn "*ashrdisi3_noppc64"
6591 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 6592 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
683bdff7
FJ		 6593 (const_int 32)) 4))]
6594 "TARGET_32BIT && !TARGET_POWERPC64"
6595 "*
6596{
6597 if (REGNO (operands[0]) == REGNO (operands[1]))
6598 return \"\";
6599 else
6600 return \"mr %0,%1\";
6601}"
6ae08853 6602 [(set_attr "length" "4")])
683bdff7 6603
266eb58a
DE		 6604\f
6605;; PowerPC64 DImode operations.
6606
ea112fc4 6607(define_insn_and_split "absdi2"
266eb58a 6608 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6609 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 6610 (clobber (match_scratch:DI 2 "=&r,&r"))]
6611 "TARGET_POWERPC64"
ea112fc4
DE		 6612 "#"
6613 "&& reload_completed"
a260abc9 6614 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6615 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 6616 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 6617 "")
6618
ea112fc4 6619(define_insn_and_split "*nabsdi2"
266eb58a 6620 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6621 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 6622 (clobber (match_scratch:DI 2 "=&r,&r"))]
6623 "TARGET_POWERPC64"
ea112fc4
DE		 6624 "#"
6625 "&& reload_completed"
a260abc9 6626 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6627 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 6628 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 6629 "")
6630
266eb58a 6631(define_insn "muldi3"
c9692532
DE		 6632 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6633 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6634 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
266eb58a 6635 "TARGET_POWERPC64"
c9692532
DE		 6636 "@
6637 mulld %0,%1,%2
6638 mulli %0,%1,%2"
6639 [(set (attr "type")
6640 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6641 (const_string "imul3")
6642 (match_operand:SI 2 "short_cint_operand" "")
6643 (const_string "imul2")]
6644 (const_string "lmul")))])
266eb58a 6645
9259f3b0
DE		 6646(define_insn "*muldi3_internal1"
6647 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6648 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6649 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6650 (const_int 0)))
6651 (clobber (match_scratch:DI 3 "=r,r"))]
6652 "TARGET_POWERPC64"
6653 "@
6654 mulld. %3,%1,%2
6655 #"
6656 [(set_attr "type" "lmul_compare")
6657 (set_attr "length" "4,8")])
6658
6659(define_split
6660 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6661 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6662 (match_operand:DI 2 "gpc_reg_operand" ""))
6663 (const_int 0)))
6664 (clobber (match_scratch:DI 3 ""))]
6665 "TARGET_POWERPC64 && reload_completed"
6666 [(set (match_dup 3)
6667 (mult:DI (match_dup 1) (match_dup 2)))
6668 (set (match_dup 0)
6669 (compare:CC (match_dup 3)
6670 (const_int 0)))]
6671 "")
6672
6673(define_insn "*muldi3_internal2"
6674 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6675 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6676 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6677 (const_int 0)))
6678 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6679 (mult:DI (match_dup 1) (match_dup 2)))]
6680 "TARGET_POWERPC64"
6681 "@
6682 mulld. %0,%1,%2
6683 #"
6684 [(set_attr "type" "lmul_compare")
6685 (set_attr "length" "4,8")])
6686
6687(define_split
6688 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6689 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6690 (match_operand:DI 2 "gpc_reg_operand" ""))
6691 (const_int 0)))
6692 (set (match_operand:DI 0 "gpc_reg_operand" "")
6693 (mult:DI (match_dup 1) (match_dup 2)))]
6694 "TARGET_POWERPC64 && reload_completed"
6695 [(set (match_dup 0)
6696 (mult:DI (match_dup 1) (match_dup 2)))
6697 (set (match_dup 3)
6698 (compare:CC (match_dup 0)
6699 (const_int 0)))]
6700 "")
6701
266eb58a
DE		 6702(define_insn "smuldi3_highpart"
6703 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6704 (truncate:DI
6705 (lshiftrt:TI (mult:TI (sign_extend:TI
6706 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6707 (sign_extend:TI
6708 (match_operand:DI 2 "gpc_reg_operand" "r")))
6709 (const_int 64))))]
6710 "TARGET_POWERPC64"
6711 "mulhd %0,%1,%2"
3cb999d8 6712 [(set_attr "type" "lmul")])
266eb58a
DE		 6713
6714(define_insn "umuldi3_highpart"
6715 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6716 (truncate:DI
6717 (lshiftrt:TI (mult:TI (zero_extend:TI
6718 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6719 (zero_extend:TI
6720 (match_operand:DI 2 "gpc_reg_operand" "r")))
6721 (const_int 64))))]
6722 "TARGET_POWERPC64"
6723 "mulhdu %0,%1,%2"
3cb999d8 6724 [(set_attr "type" "lmul")])
266eb58a 6725
266eb58a 6726(define_insn "rotldi3"
44cd321e
PS		 6727 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6728 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6729 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 6730 "TARGET_POWERPC64"
44cd321e
PS		 6731 "@
6732 rldcl %0,%1,%2,0
6733 rldicl %0,%1,%H2,0"
6734 [(set_attr "type" "var_shift_rotate,integer")])
266eb58a 6735
a260abc9 6736(define_insn "*rotldi3_internal2"
44cd321e
PS		 6737 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6738 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6739 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6740 (const_int 0)))
44cd321e 6741 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6742 "TARGET_64BIT"
9ebbca7d 6743 "@
44cd321e
PS		 6744 rldcl. %3,%1,%2,0
6745 rldicl. %3,%1,%H2,0
6746 #
9ebbca7d 6747 #"
44cd321e
PS		 6748 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6749 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6750
6751(define_split
6752 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6753 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6754 (match_operand:DI 2 "reg_or_cint_operand" ""))
6755 (const_int 0)))
6756 (clobber (match_scratch:DI 3 ""))]
6757 "TARGET_POWERPC64 && reload_completed"
6758 [(set (match_dup 3)
6759 (rotate:DI (match_dup 1) (match_dup 2)))
6760 (set (match_dup 0)
6761 (compare:CC (match_dup 3)
6762 (const_int 0)))]
6763 "")
266eb58a 6764
a260abc9 6765(define_insn "*rotldi3_internal3"
44cd321e
PS		 6766 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6767 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6768 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6769 (const_int 0)))
44cd321e 6770 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 6771 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 6772 "TARGET_64BIT"
9ebbca7d 6773 "@
44cd321e
PS		 6774 rldcl. %0,%1,%2,0
6775 rldicl. %0,%1,%H2,0
6776 #
9ebbca7d 6777 #"
44cd321e
PS		 6778 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6779 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6780
6781(define_split
6782 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6783 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6784 (match_operand:DI 2 "reg_or_cint_operand" ""))
6785 (const_int 0)))
6786 (set (match_operand:DI 0 "gpc_reg_operand" "")
6787 (rotate:DI (match_dup 1) (match_dup 2)))]
6788 "TARGET_POWERPC64 && reload_completed"
6789 [(set (match_dup 0)
6790 (rotate:DI (match_dup 1) (match_dup 2)))
6791 (set (match_dup 3)
6792 (compare:CC (match_dup 0)
6793 (const_int 0)))]
6794 "")
266eb58a 6795
a260abc9 6796(define_insn "*rotldi3_internal4"
44cd321e
PS		 6797 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6798 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6799 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6800 (match_operand:DI 3 "mask64_operand" "n,n")))]
a260abc9 6801 "TARGET_POWERPC64"
44cd321e
PS		 6802 "@
6803 rldc%B3 %0,%1,%2,%S3
6804 rldic%B3 %0,%1,%H2,%S3"
6805 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6806
6807(define_insn "*rotldi3_internal5"
44cd321e 6808 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6809 (compare:CC (and:DI
44cd321e
PS		 6810 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6811 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6812 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6813 (const_int 0)))
44cd321e 6814 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
683bdff7 6815 "TARGET_64BIT"
9ebbca7d 6816 "@
44cd321e
PS		 6817 rldc%B3. %4,%1,%2,%S3
6818 rldic%B3. %4,%1,%H2,%S3
6819 #
9ebbca7d 6820 #"
44cd321e
PS		 6821 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6822 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6823
6824(define_split
6825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6826 (compare:CC (and:DI
6827 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6828 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6829 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6830 (const_int 0)))
6831 (clobber (match_scratch:DI 4 ""))]
6832 "TARGET_POWERPC64 && reload_completed"
6833 [(set (match_dup 4)
6834 (and:DI (rotate:DI (match_dup 1)
6835 (match_dup 2))
6836 (match_dup 3)))
6837 (set (match_dup 0)
6838 (compare:CC (match_dup 4)
6839 (const_int 0)))]
6840 "")
a260abc9
DE		 6841
6842(define_insn "*rotldi3_internal6"
44cd321e 6843 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6844 (compare:CC (and:DI
44cd321e
PS		 6845 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6846 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6847 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6848 (const_int 0)))
44cd321e 6849 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6850 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6851 "TARGET_64BIT"
9ebbca7d 6852 "@
44cd321e
PS		 6853 rldc%B3. %0,%1,%2,%S3
6854 rldic%B3. %0,%1,%H2,%S3
6855 #
9ebbca7d 6856 #"
44cd321e
PS		 6857 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6858 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6859
6860(define_split
6861 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6862 (compare:CC (and:DI
6863 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6864 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6865 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6866 (const_int 0)))
6867 (set (match_operand:DI 0 "gpc_reg_operand" "")
6868 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6869 "TARGET_POWERPC64 && reload_completed"
6870 [(set (match_dup 0)
6871 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6872 (set (match_dup 4)
6873 (compare:CC (match_dup 0)
6874 (const_int 0)))]
6875 "")
a260abc9
DE		 6876
6877(define_insn "*rotldi3_internal7"
44cd321e 6878 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6879 (zero_extend:DI
6880 (subreg:QI
44cd321e
PS		 6881 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6882 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6883 "TARGET_POWERPC64"
44cd321e
PS		 6884 "@
6885 rldcl %0,%1,%2,56
6886 rldicl %0,%1,%H2,56"
6887 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6888
6889(define_insn "*rotldi3_internal8"
44cd321e 6890 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6891 (compare:CC (zero_extend:DI
6892 (subreg:QI
44cd321e
PS		 6893 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6894 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6895 (const_int 0)))
44cd321e 6896 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6897 "TARGET_64BIT"
9ebbca7d 6898 "@
44cd321e
PS		 6899 rldcl. %3,%1,%2,56
6900 rldicl. %3,%1,%H2,56
6901 #
9ebbca7d 6902 #"
44cd321e
PS		 6903 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6904 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6905
6906(define_split
6907 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6908 (compare:CC (zero_extend:DI
6909 (subreg:QI
6910 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6911 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6912 (const_int 0)))
6913 (clobber (match_scratch:DI 3 ""))]
6914 "TARGET_POWERPC64 && reload_completed"
6915 [(set (match_dup 3)
6916 (zero_extend:DI (subreg:QI
6917 (rotate:DI (match_dup 1)
6918 (match_dup 2)) 0)))
6919 (set (match_dup 0)
6920 (compare:CC (match_dup 3)
6921 (const_int 0)))]
6922 "")
a260abc9
DE		 6923
6924(define_insn "*rotldi3_internal9"
44cd321e 6925 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6926 (compare:CC (zero_extend:DI
6927 (subreg:QI
44cd321e
PS		 6928 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6929 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6930 (const_int 0)))
44cd321e 6931 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6932 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6933 "TARGET_64BIT"
9ebbca7d 6934 "@
44cd321e
PS		 6935 rldcl. %0,%1,%2,56
6936 rldicl. %0,%1,%H2,56
6937 #
9ebbca7d 6938 #"
44cd321e
PS		 6939 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6940 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6941
6942(define_split
6943 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6944 (compare:CC (zero_extend:DI
6945 (subreg:QI
6946 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6947 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6948 (const_int 0)))
6949 (set (match_operand:DI 0 "gpc_reg_operand" "")
6950 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6951 "TARGET_POWERPC64 && reload_completed"
6952 [(set (match_dup 0)
6953 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6954 (set (match_dup 3)
6955 (compare:CC (match_dup 0)
6956 (const_int 0)))]
6957 "")
a260abc9
DE		 6958
6959(define_insn "*rotldi3_internal10"
44cd321e 6960 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6961 (zero_extend:DI
6962 (subreg:HI
44cd321e
PS		 6963 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6964 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6965 "TARGET_POWERPC64"
44cd321e
PS		 6966 "@
6967 rldcl %0,%1,%2,48
6968 rldicl %0,%1,%H2,48"
6969 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6970
6971(define_insn "*rotldi3_internal11"
44cd321e 6972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6973 (compare:CC (zero_extend:DI
6974 (subreg:HI
44cd321e
PS		 6975 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6976 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6977 (const_int 0)))
44cd321e 6978 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6979 "TARGET_64BIT"
9ebbca7d 6980 "@
44cd321e
PS		 6981 rldcl. %3,%1,%2,48
6982 rldicl. %3,%1,%H2,48
6983 #
9ebbca7d 6984 #"
44cd321e
PS		 6985 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6986 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6987
6988(define_split
6989 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6990 (compare:CC (zero_extend:DI
6991 (subreg:HI
6992 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6993 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6994 (const_int 0)))
6995 (clobber (match_scratch:DI 3 ""))]
6996 "TARGET_POWERPC64 && reload_completed"
6997 [(set (match_dup 3)
6998 (zero_extend:DI (subreg:HI
6999 (rotate:DI (match_dup 1)
7000 (match_dup 2)) 0)))
7001 (set (match_dup 0)
7002 (compare:CC (match_dup 3)
7003 (const_int 0)))]
7004 "")
a260abc9
DE		 7005
7006(define_insn "*rotldi3_internal12"
44cd321e 7007 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7008 (compare:CC (zero_extend:DI
7009 (subreg:HI
44cd321e
PS		 7010 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7011 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7012 (const_int 0)))
44cd321e 7013 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7014 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7015 "TARGET_64BIT"
9ebbca7d 7016 "@
44cd321e
PS		 7017 rldcl. %0,%1,%2,48
7018 rldicl. %0,%1,%H2,48
7019 #
9ebbca7d 7020 #"
44cd321e
PS		 7021 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7022 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7023
7024(define_split
7025 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7026 (compare:CC (zero_extend:DI
7027 (subreg:HI
7028 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7029 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7030 (const_int 0)))
7031 (set (match_operand:DI 0 "gpc_reg_operand" "")
7032 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7033 "TARGET_POWERPC64 && reload_completed"
7034 [(set (match_dup 0)
7035 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7036 (set (match_dup 3)
7037 (compare:CC (match_dup 0)
7038 (const_int 0)))]
7039 "")
a260abc9
DE		 7040
7041(define_insn "*rotldi3_internal13"
44cd321e 7042 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 7043 (zero_extend:DI
7044 (subreg:SI
44cd321e
PS		 7045 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7046 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 7047 "TARGET_POWERPC64"
44cd321e
PS		 7048 "@
7049 rldcl %0,%1,%2,32
7050 rldicl %0,%1,%H2,32"
7051 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 7052
7053(define_insn "*rotldi3_internal14"
44cd321e 7054 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7055 (compare:CC (zero_extend:DI
7056 (subreg:SI
44cd321e
PS		 7057 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7058 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7059 (const_int 0)))
44cd321e 7060 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7061 "TARGET_64BIT"
9ebbca7d 7062 "@
44cd321e
PS		 7063 rldcl. %3,%1,%2,32
7064 rldicl. %3,%1,%H2,32
7065 #
9ebbca7d 7066 #"
44cd321e
PS		 7067 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7068 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7069
7070(define_split
7071 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7072 (compare:CC (zero_extend:DI
7073 (subreg:SI
7074 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7075 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7076 (const_int 0)))
7077 (clobber (match_scratch:DI 3 ""))]
7078 "TARGET_POWERPC64 && reload_completed"
7079 [(set (match_dup 3)
7080 (zero_extend:DI (subreg:SI
7081 (rotate:DI (match_dup 1)
7082 (match_dup 2)) 0)))
7083 (set (match_dup 0)
7084 (compare:CC (match_dup 3)
7085 (const_int 0)))]
7086 "")
a260abc9
DE		 7087
7088(define_insn "*rotldi3_internal15"
44cd321e 7089 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7090 (compare:CC (zero_extend:DI
7091 (subreg:SI
44cd321e
PS		 7092 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7093 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7094 (const_int 0)))
44cd321e 7095 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7096 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7097 "TARGET_64BIT"
9ebbca7d 7098 "@
44cd321e
PS		 7099 rldcl. %0,%1,%2,32
7100 rldicl. %0,%1,%H2,32
7101 #
9ebbca7d 7102 #"
44cd321e
PS		 7103 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7104 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7105
7106(define_split
7107 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7108 (compare:CC (zero_extend:DI
7109 (subreg:SI
7110 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7111 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7112 (const_int 0)))
7113 (set (match_operand:DI 0 "gpc_reg_operand" "")
7114 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7115 "TARGET_POWERPC64 && reload_completed"
7116 [(set (match_dup 0)
7117 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7118 (set (match_dup 3)
7119 (compare:CC (match_dup 0)
7120 (const_int 0)))]
7121 "")
a260abc9 7122
266eb58a
DE		 7123(define_expand "ashldi3"
7124 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7125 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7126 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7127 "TARGET_POWERPC64 || TARGET_POWER"
7128 "
7129{
7130 if (TARGET_POWERPC64)
7131 ;
7132 else if (TARGET_POWER)
7133 {
7134 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7135 DONE;
7136 }
7137 else
7138 FAIL;
7139}")
7140
e2c953b6 7141(define_insn "*ashldi3_internal1"
44cd321e
PS		 7142 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7143 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7144 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7145 "TARGET_POWERPC64"
44cd321e
PS		 7146 "@
7147 sld %0,%1,%2
7148 sldi %0,%1,%H2"
7149 [(set_attr "type" "var_shift_rotate,shift")])
6ae08853 7150
e2c953b6 7151(define_insn "*ashldi3_internal2"
44cd321e
PS		 7152 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7153 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7154 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7155 (const_int 0)))
44cd321e 7156 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7157 "TARGET_64BIT"
9ebbca7d 7158 "@
44cd321e
PS		 7159 sld. %3,%1,%2
7160 sldi. %3,%1,%H2
7161 #
9ebbca7d 7162 #"
44cd321e
PS		 7163 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7164 (set_attr "length" "4,4,8,8")])
6ae08853 7165
9ebbca7d
GK		 7166(define_split
7167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7168 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7169 (match_operand:SI 2 "reg_or_cint_operand" ""))
7170 (const_int 0)))
7171 (clobber (match_scratch:DI 3 ""))]
7172 "TARGET_POWERPC64 && reload_completed"
7173 [(set (match_dup 3)
7174 (ashift:DI (match_dup 1) (match_dup 2)))
7175 (set (match_dup 0)
7176 (compare:CC (match_dup 3)
7177 (const_int 0)))]
7178 "")
7179
e2c953b6 7180(define_insn "*ashldi3_internal3"
44cd321e
PS		 7181 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7182 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7183 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7184 (const_int 0)))
44cd321e 7185 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7186 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 7187 "TARGET_64BIT"
9ebbca7d 7188 "@
44cd321e
PS		 7189 sld. %0,%1,%2
7190 sldi. %0,%1,%H2
7191 #
9ebbca7d 7192 #"
44cd321e
PS		 7193 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7194 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7195
7196(define_split
7197 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7198 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7199 (match_operand:SI 2 "reg_or_cint_operand" ""))
7200 (const_int 0)))
7201 (set (match_operand:DI 0 "gpc_reg_operand" "")
7202 (ashift:DI (match_dup 1) (match_dup 2)))]
7203 "TARGET_POWERPC64 && reload_completed"
7204 [(set (match_dup 0)
7205 (ashift:DI (match_dup 1) (match_dup 2)))
7206 (set (match_dup 3)
7207 (compare:CC (match_dup 0)
7208 (const_int 0)))]
7209 "")
266eb58a 7210
e2c953b6 7211(define_insn "*ashldi3_internal4"
3cb999d8
DE		 7212 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7213 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7214 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 7215 (match_operand:DI 3 "const_int_operand" "n")))]
7216 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 7217 "rldic %0,%1,%H2,%W3")
3cb999d8 7218
e2c953b6 7219(define_insn "ashldi3_internal5"
9ebbca7d 7220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 7221 (compare:CC
9ebbca7d
GK		 7222 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7223 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7224 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7225 (const_int 0)))
9ebbca7d 7226 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7227 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7228 "@
e2c953b6 7229 rldic. %4,%1,%H2,%W3
9ebbca7d 7230 #"
9c6fdb46 7231 [(set_attr "type" "compare")
9ebbca7d
GK		 7232 (set_attr "length" "4,8")])
7233
7234(define_split
7235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7236 (compare:CC
7237 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7238 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7239 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7240 (const_int 0)))
7241 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 7242 "TARGET_POWERPC64 && reload_completed
7243 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 7244 [(set (match_dup 4)
7245 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 7246 (match_dup 3)))
9ebbca7d
GK		 7247 (set (match_dup 0)
7248 (compare:CC (match_dup 4)
7249 (const_int 0)))]
7250 "")
3cb999d8 7251
e2c953b6 7252(define_insn "*ashldi3_internal6"
9ebbca7d 7253 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 7254 (compare:CC
9ebbca7d
GK		 7255 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7256 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7257 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7258 (const_int 0)))
9ebbca7d 7259 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 7260 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7261 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7262 "@
e2c953b6 7263 rldic. %0,%1,%H2,%W3
9ebbca7d 7264 #"
9c6fdb46 7265 [(set_attr "type" "compare")
9ebbca7d
GK		 7266 (set_attr "length" "4,8")])
7267
7268(define_split
7269 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7270 (compare:CC
7271 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7272 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7273 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7274 (const_int 0)))
7275 (set (match_operand:DI 0 "gpc_reg_operand" "")
7276 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 7277 "TARGET_POWERPC64 && reload_completed
7278 && includes_rldic_lshift_p (operands[2], operands[3])"
7279 [(set (match_dup 0)
7280 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7281 (match_dup 3)))
7282 (set (match_dup 4)
7283 (compare:CC (match_dup 0)
7284 (const_int 0)))]
7285 "")
7286
7287(define_insn "*ashldi3_internal7"
7288 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7289 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7290 (match_operand:SI 2 "const_int_operand" "i"))
1990cd79 7291 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 7292 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7293 "rldicr %0,%1,%H2,%S3")
7294
7295(define_insn "ashldi3_internal8"
7296 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7297 (compare:CC
7298 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7299 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7300 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7301 (const_int 0)))
7302 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7303 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7304 "@
7305 rldicr. %4,%1,%H2,%S3
7306 #"
9c6fdb46 7307 [(set_attr "type" "compare")
c5059423
AM		 7308 (set_attr "length" "4,8")])
7309
7310(define_split
7311 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7312 (compare:CC
7313 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7314 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7315 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7316 (const_int 0)))
7317 (clobber (match_scratch:DI 4 ""))]
7318 "TARGET_POWERPC64 && reload_completed
7319 && includes_rldicr_lshift_p (operands[2], operands[3])"
7320 [(set (match_dup 4)
7321 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7322 (match_dup 3)))
7323 (set (match_dup 0)
7324 (compare:CC (match_dup 4)
7325 (const_int 0)))]
7326 "")
7327
7328(define_insn "*ashldi3_internal9"
7329 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7330 (compare:CC
7331 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7332 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7333 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7334 (const_int 0)))
7335 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7336 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7337 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7338 "@
7339 rldicr. %0,%1,%H2,%S3
7340 #"
9c6fdb46 7341 [(set_attr "type" "compare")
c5059423
AM		 7342 (set_attr "length" "4,8")])
7343
7344(define_split
7345 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7346 (compare:CC
7347 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7348 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7349 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7350 (const_int 0)))
7351 (set (match_operand:DI 0 "gpc_reg_operand" "")
7352 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7353 "TARGET_POWERPC64 && reload_completed
7354 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 7355 [(set (match_dup 0)
e2c953b6
DE		 7356 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7357 (match_dup 3)))
9ebbca7d
GK		 7358 (set (match_dup 4)
7359 (compare:CC (match_dup 0)
7360 (const_int 0)))]
7361 "")
7362
7363(define_expand "lshrdi3"
266eb58a
DE		 7364 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7365 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7366 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7367 "TARGET_POWERPC64 || TARGET_POWER"
7368 "
7369{
7370 if (TARGET_POWERPC64)
7371 ;
7372 else if (TARGET_POWER)
7373 {
7374 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7375 DONE;
7376 }
7377 else
7378 FAIL;
7379}")
7380
e2c953b6 7381(define_insn "*lshrdi3_internal1"
44cd321e
PS		 7382 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7383 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7384 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7385 "TARGET_POWERPC64"
44cd321e
PS		 7386 "@
7387 srd %0,%1,%2
7388 srdi %0,%1,%H2"
7389 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7390
e2c953b6 7391(define_insn "*lshrdi3_internal2"
44cd321e
PS		 7392 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7393 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7394 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
29ae5b89 7395 (const_int 0)))
44cd321e 7396 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7397 "TARGET_64BIT "
9ebbca7d 7398 "@
44cd321e
PS		 7399 srd. %3,%1,%2
7400 srdi. %3,%1,%H2
7401 #
9ebbca7d 7402 #"
44cd321e
PS		 7403 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7404 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7405
7406(define_split
7407 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7408 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7409 (match_operand:SI 2 "reg_or_cint_operand" ""))
7410 (const_int 0)))
7411 (clobber (match_scratch:DI 3 ""))]
7412 "TARGET_POWERPC64 && reload_completed"
7413 [(set (match_dup 3)
7414 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7415 (set (match_dup 0)
7416 (compare:CC (match_dup 3)
7417 (const_int 0)))]
7418 "")
266eb58a 7419
e2c953b6 7420(define_insn "*lshrdi3_internal3"
44cd321e
PS		 7421 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7422 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7423 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7424 (const_int 0)))
44cd321e 7425 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 7426 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7427 "TARGET_64BIT"
9ebbca7d 7428 "@
44cd321e
PS		 7429 srd. %0,%1,%2
7430 srdi. %0,%1,%H2
7431 #
9ebbca7d 7432 #"
44cd321e
PS		 7433 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7434 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7435
7436(define_split
7437 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7438 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7439 (match_operand:SI 2 "reg_or_cint_operand" ""))
7440 (const_int 0)))
7441 (set (match_operand:DI 0 "gpc_reg_operand" "")
7442 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7443 "TARGET_POWERPC64 && reload_completed"
7444 [(set (match_dup 0)
7445 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7446 (set (match_dup 3)
7447 (compare:CC (match_dup 0)
7448 (const_int 0)))]
7449 "")
266eb58a
DE		 7450
7451(define_expand "ashrdi3"
7452 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7453 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7454 (match_operand:SI 2 "reg_or_cint_operand" "")))]
97727e85 7455 "WORDS_BIG_ENDIAN"
266eb58a
DE		 7456 "
7457{
7458 if (TARGET_POWERPC64)
7459 ;
7460 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7461 {
7462 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7463 DONE;
7464 }
97727e85
AH		 7465 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7466 && WORDS_BIG_ENDIAN)
4aa74a4f
FS		 7467 {
7468 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7469 DONE;
7470 }
266eb58a
DE		 7471 else
7472 FAIL;
7473}")
7474
e2c953b6 7475(define_insn "*ashrdi3_internal1"
44cd321e
PS		 7476 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7477 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7478 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7479 "TARGET_POWERPC64"
44cd321e
PS		 7480 "@
7481 srad %0,%1,%2
7482 sradi %0,%1,%H2"
7483 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7484
e2c953b6 7485(define_insn "*ashrdi3_internal2"
44cd321e
PS		 7486 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7487 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7488 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7489 (const_int 0)))
44cd321e 7490 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7491 "TARGET_64BIT"
9ebbca7d 7492 "@
44cd321e
PS		 7493 srad. %3,%1,%2
7494 sradi. %3,%1,%H2
7495 #
9ebbca7d 7496 #"
44cd321e
PS		 7497 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7498 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7499
7500(define_split
7501 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7502 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7503 (match_operand:SI 2 "reg_or_cint_operand" ""))
7504 (const_int 0)))
7505 (clobber (match_scratch:DI 3 ""))]
7506 "TARGET_POWERPC64 && reload_completed"
7507 [(set (match_dup 3)
7508 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7509 (set (match_dup 0)
7510 (compare:CC (match_dup 3)
7511 (const_int 0)))]
7512 "")
266eb58a 7513
e2c953b6 7514(define_insn "*ashrdi3_internal3"
44cd321e
PS		 7515 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7516 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7517 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7518 (const_int 0)))
44cd321e 7519 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7520 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7521 "TARGET_64BIT"
9ebbca7d 7522 "@
44cd321e
PS		 7523 srad. %0,%1,%2
7524 sradi. %0,%1,%H2
7525 #
9ebbca7d 7526 #"
44cd321e
PS		 7527 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7528 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7529
7530(define_split
7531 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7532 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7533 (match_operand:SI 2 "reg_or_cint_operand" ""))
7534 (const_int 0)))
7535 (set (match_operand:DI 0 "gpc_reg_operand" "")
7536 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7537 "TARGET_POWERPC64 && reload_completed"
7538 [(set (match_dup 0)
7539 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7540 (set (match_dup 3)
7541 (compare:CC (match_dup 0)
7542 (const_int 0)))]
7543 "")
815cdc52 7544
29ae5b89 7545(define_insn "anddi3"
e1e2e653
NS		 7546 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7547 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7548 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7549 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6ffc8580 7550 "TARGET_POWERPC64"
266eb58a
DE		 7551 "@
7552 and %0,%1,%2
29ae5b89 7553 rldic%B2 %0,%1,0,%S2
e1e2e653 7554 rlwinm %0,%1,0,%m2,%M2
29ae5b89 7555 andi. %0,%1,%b2
0ba1b2ff
AM		 7556 andis. %0,%1,%u2
7557 #"
e1e2e653
NS		 7558 [(set_attr "type" "*,*,*,compare,compare,*")
7559 (set_attr "length" "4,4,4,4,4,8")])
0ba1b2ff
AM		 7560
7561(define_split
7562 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7563 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7564 (match_operand:DI 2 "mask64_2_operand" "")))
7565 (clobber (match_scratch:CC 3 ""))]
7566 "TARGET_POWERPC64
7567 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7568 && !mask_operand (operands[2], DImode)
7569 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7570 [(set (match_dup 0)
7571 (and:DI (rotate:DI (match_dup 1)
7572 (match_dup 4))
7573 (match_dup 5)))
7574 (set (match_dup 0)
7575 (and:DI (rotate:DI (match_dup 0)
7576 (match_dup 6))
7577 (match_dup 7)))]
0ba1b2ff
AM		 7578{
7579 build_mask64_2_operands (operands[2], &operands[4]);
e1e2e653 7580})
266eb58a 7581
a260abc9 7582(define_insn "*anddi3_internal2"
1990cd79
AM		 7583 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7584 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7585 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7586 (const_int 0)))
1990cd79
AM		 7587 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7588 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7589 "TARGET_64BIT"
266eb58a
DE		 7590 "@
7591 and. %3,%1,%2
6c873122 7592 rldic%B2. %3,%1,0,%S2
1990cd79 7593 rlwinm. %3,%1,0,%m2,%M2
6ffc8580
MM		 7594 andi. %3,%1,%b2
7595 andis. %3,%1,%u2
9ebbca7d
GK		 7596 #
7597 #
7598 #
0ba1b2ff
AM		 7599 #
7600 #
1990cd79 7601 #
9ebbca7d 7602 #"
44cd321e 7603 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7604 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d 7605
0ba1b2ff
AM		 7606(define_split
7607 [(set (match_operand:CC 0 "cc_reg_operand" "")
7608 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7609 (match_operand:DI 2 "mask64_2_operand" ""))
7610 (const_int 0)))
7611 (clobber (match_scratch:DI 3 ""))
7612 (clobber (match_scratch:CC 4 ""))]
1990cd79 7613 "TARGET_64BIT && reload_completed
0ba1b2ff 7614 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7615 && !mask_operand (operands[2], DImode)
7616 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7617 [(set (match_dup 3)
7618 (and:DI (rotate:DI (match_dup 1)
7619 (match_dup 5))
7620 (match_dup 6)))
7621 (parallel [(set (match_dup 0)
7622 (compare:CC (and:DI (rotate:DI (match_dup 3)
7623 (match_dup 7))
7624 (match_dup 8))
7625 (const_int 0)))
7626 (clobber (match_dup 3))])]
7627 "
7628{
7629 build_mask64_2_operands (operands[2], &operands[5]);
7630}")
7631
a260abc9 7632(define_insn "*anddi3_internal3"
1990cd79
AM		 7633 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7634 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7635 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7636 (const_int 0)))
1990cd79 7637 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7638 (and:DI (match_dup 1) (match_dup 2)))
1990cd79 7639 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7640 "TARGET_64BIT"
266eb58a
DE		 7641 "@
7642 and. %0,%1,%2
6c873122 7643 rldic%B2. %0,%1,0,%S2
1990cd79 7644 rlwinm. %0,%1,0,%m2,%M2
6ffc8580
MM		 7645 andi. %0,%1,%b2
7646 andis. %0,%1,%u2
9ebbca7d
GK		 7647 #
7648 #
7649 #
0ba1b2ff
AM		 7650 #
7651 #
1990cd79 7652 #
9ebbca7d 7653 #"
44cd321e 7654 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7655 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d
GK		 7656
7657(define_split
7658 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7659 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
1990cd79 7660 (match_operand:DI 2 "and64_2_operand" ""))
9ebbca7d
GK		 7661 (const_int 0)))
7662 (set (match_operand:DI 0 "gpc_reg_operand" "")
7663 (and:DI (match_dup 1) (match_dup 2)))
7664 (clobber (match_scratch:CC 4 ""))]
1990cd79 7665 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 7666 [(parallel [(set (match_dup 0)
7667 (and:DI (match_dup 1) (match_dup 2)))
7668 (clobber (match_dup 4))])
7669 (set (match_dup 3)
7670 (compare:CC (match_dup 0)
7671 (const_int 0)))]
7672 "")
266eb58a 7673
0ba1b2ff
AM		 7674(define_split
7675 [(set (match_operand:CC 3 "cc_reg_operand" "")
7676 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7677 (match_operand:DI 2 "mask64_2_operand" ""))
7678 (const_int 0)))
7679 (set (match_operand:DI 0 "gpc_reg_operand" "")
7680 (and:DI (match_dup 1) (match_dup 2)))
7681 (clobber (match_scratch:CC 4 ""))]
1990cd79 7682 "TARGET_64BIT && reload_completed
0ba1b2ff 7683 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7684 && !mask_operand (operands[2], DImode)
7685 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7686 [(set (match_dup 0)
7687 (and:DI (rotate:DI (match_dup 1)
7688 (match_dup 5))
7689 (match_dup 6)))
7690 (parallel [(set (match_dup 3)
7691 (compare:CC (and:DI (rotate:DI (match_dup 0)
7692 (match_dup 7))
7693 (match_dup 8))
7694 (const_int 0)))
7695 (set (match_dup 0)
7696 (and:DI (rotate:DI (match_dup 0)
7697 (match_dup 7))
7698 (match_dup 8)))])]
7699 "
7700{
7701 build_mask64_2_operands (operands[2], &operands[5]);
7702}")
7703
a260abc9 7704(define_expand "iordi3"
266eb58a 7705 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7706 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7707 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7708 "TARGET_POWERPC64"
266eb58a
DE		 7709 "
7710{
dfbdccdb 7711 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7712 {
dfbdccdb 7713 HOST_WIDE_INT value;
b3a13419
ILT		 7714 rtx tmp = ((!can_create_pseudo_p ()
7715 || rtx_equal_p (operands[0], operands[1]))
a260abc9 7716 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7717
dfbdccdb
GK		 7718 if (GET_CODE (operands[2]) == CONST_INT)
7719 {
7720 value = INTVAL (operands[2]);
7721 emit_insn (gen_iordi3 (tmp, operands[1],
7722 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7723 }
e2c953b6 7724 else
dfbdccdb
GK		 7725 {
7726 value = CONST_DOUBLE_LOW (operands[2]);
7727 emit_insn (gen_iordi3 (tmp, operands[1],
7728 immed_double_const (value
7729 & (~ (HOST_WIDE_INT) 0xffff),
7730 0, DImode)));
7731 }
e2c953b6 7732
9ebbca7d
GK		 7733 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7734 DONE;
7735 }
266eb58a
DE		 7736}")
7737
a260abc9
DE		 7738(define_expand "xordi3"
7739 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7740 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7741 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7742 "TARGET_POWERPC64"
7743 "
7744{
dfbdccdb 7745 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7746 {
dfbdccdb 7747 HOST_WIDE_INT value;
b3a13419
ILT		 7748 rtx tmp = ((!can_create_pseudo_p ()
7749 || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7750 ? operands[0] : gen_reg_rtx (DImode));
7751
dfbdccdb
GK		 7752 if (GET_CODE (operands[2]) == CONST_INT)
7753 {
7754 value = INTVAL (operands[2]);
7755 emit_insn (gen_xordi3 (tmp, operands[1],
7756 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7757 }
e2c953b6 7758 else
dfbdccdb
GK		 7759 {
7760 value = CONST_DOUBLE_LOW (operands[2]);
7761 emit_insn (gen_xordi3 (tmp, operands[1],
7762 immed_double_const (value
7763 & (~ (HOST_WIDE_INT) 0xffff),
7764 0, DImode)));
7765 }
e2c953b6 7766
9ebbca7d
GK		 7767 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7768 DONE;
7769 }
a260abc9
DE		 7770}")
7771
dfbdccdb 7772(define_insn "*booldi3_internal1"
266eb58a 7773 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7774 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7775 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7776 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7777 "TARGET_POWERPC64"
1fd4e8c1 7778 "@
dfbdccdb
GK		 7779 %q3 %0,%1,%2
7780 %q3i %0,%1,%b2
7781 %q3is %0,%1,%u2")
1fd4e8c1 7782
dfbdccdb 7783(define_insn "*booldi3_internal2"
9ebbca7d 7784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7785 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7786 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7787 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7788 (const_int 0)))
9ebbca7d 7789 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7790 "TARGET_64BIT"
9ebbca7d 7791 "@
dfbdccdb 7792 %q4. %3,%1,%2
9ebbca7d
GK		 7793 #"
7794 [(set_attr "type" "compare")
7795 (set_attr "length" "4,8")])
7796
7797(define_split
7798 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7799 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7800 [(match_operand:DI 1 "gpc_reg_operand" "")
7801 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7802 (const_int 0)))
9ebbca7d
GK		 7803 (clobber (match_scratch:DI 3 ""))]
7804 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7805 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7806 (set (match_dup 0)
7807 (compare:CC (match_dup 3)
7808 (const_int 0)))]
7809 "")
1fd4e8c1 7810
dfbdccdb 7811(define_insn "*booldi3_internal3"
9ebbca7d 7812 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7813 (compare:CC (match_operator:DI 4 "boolean_operator"
7814 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7815 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7816 (const_int 0)))
9ebbca7d 7817 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7818 (match_dup 4))]
683bdff7 7819 "TARGET_64BIT"
9ebbca7d 7820 "@
dfbdccdb 7821 %q4. %0,%1,%2
9ebbca7d
GK		 7822 #"
7823 [(set_attr "type" "compare")
7824 (set_attr "length" "4,8")])
7825
7826(define_split
e72247f4 7827 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7828 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7829 [(match_operand:DI 1 "gpc_reg_operand" "")
7830 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7831 (const_int 0)))
75540af0 7832 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7833 (match_dup 4))]
9ebbca7d 7834 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7835 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7836 (set (match_dup 3)
7837 (compare:CC (match_dup 0)
7838 (const_int 0)))]
7839 "")
1fd4e8c1 7840
6ae08853 7841;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7842;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7843
7844(define_split
7845 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7846 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7847 [(match_operand:DI 1 "gpc_reg_operand" "")
7848 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7849 "TARGET_POWERPC64"
dfbdccdb
GK		 7850 [(set (match_dup 0) (match_dup 4))
7851 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7852"
7853{
dfbdccdb 7854 rtx i3,i4;
6ae08853 7855
9ebbca7d
GK		 7856 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7857 {
7858 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7859 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7860 0, DImode);
dfbdccdb 7861 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7862 }
7863 else
7864 {
dfbdccdb 7865 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7866 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7867 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7868 }
1c563bed 7869 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7870 operands[1], i3);
1c563bed 7871 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7872 operands[0], i4);
1fd4e8c1
RK		 7873}")
7874
dfbdccdb 7875(define_insn "*boolcdi3_internal1"
9ebbca7d 7876 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7877 (match_operator:DI 3 "boolean_operator"
7878 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7879 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7880 "TARGET_POWERPC64"
1d328b19 7881 "%q3 %0,%2,%1")
a473029f 7882
dfbdccdb 7883(define_insn "*boolcdi3_internal2"
9ebbca7d 7884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7885 (compare:CC (match_operator:DI 4 "boolean_operator"
7886 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7887 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7888 (const_int 0)))
9ebbca7d 7889 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7890 "TARGET_64BIT"
9ebbca7d 7891 "@
1d328b19 7892 %q4. %3,%2,%1
9ebbca7d
GK		 7893 #"
7894 [(set_attr "type" "compare")
7895 (set_attr "length" "4,8")])
7896
7897(define_split
7898 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7899 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7900 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7901 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7902 (const_int 0)))
9ebbca7d
GK		 7903 (clobber (match_scratch:DI 3 ""))]
7904 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7905 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7906 (set (match_dup 0)
7907 (compare:CC (match_dup 3)
7908 (const_int 0)))]
7909 "")
a473029f 7910
dfbdccdb 7911(define_insn "*boolcdi3_internal3"
9ebbca7d 7912 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7913 (compare:CC (match_operator:DI 4 "boolean_operator"
7914 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7915 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7916 (const_int 0)))
9ebbca7d 7917 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7918 (match_dup 4))]
683bdff7 7919 "TARGET_64BIT"
9ebbca7d 7920 "@
1d328b19 7921 %q4. %0,%2,%1
9ebbca7d
GK		 7922 #"
7923 [(set_attr "type" "compare")
7924 (set_attr "length" "4,8")])
7925
7926(define_split
e72247f4 7927 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7928 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7929 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7930 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7931 (const_int 0)))
75540af0 7932 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7933 (match_dup 4))]
9ebbca7d 7934 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7935 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7936 (set (match_dup 3)
7937 (compare:CC (match_dup 0)
7938 (const_int 0)))]
7939 "")
266eb58a 7940
dfbdccdb 7941(define_insn "*boolccdi3_internal1"
a473029f 7942 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7943 (match_operator:DI 3 "boolean_operator"
7944 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7945 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 7946 "TARGET_POWERPC64"
dfbdccdb 7947 "%q3 %0,%1,%2")
a473029f 7948
dfbdccdb 7949(define_insn "*boolccdi3_internal2"
9ebbca7d 7950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7951 (compare:CC (match_operator:DI 4 "boolean_operator"
7952 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7953 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7954 (const_int 0)))
9ebbca7d 7955 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7956 "TARGET_64BIT"
9ebbca7d 7957 "@
dfbdccdb 7958 %q4. %3,%1,%2
9ebbca7d
GK		 7959 #"
7960 [(set_attr "type" "compare")
7961 (set_attr "length" "4,8")])
7962
7963(define_split
7964 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7965 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7966 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7967 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7968 (const_int 0)))
9ebbca7d
GK		 7969 (clobber (match_scratch:DI 3 ""))]
7970 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7971 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7972 (set (match_dup 0)
7973 (compare:CC (match_dup 3)
7974 (const_int 0)))]
7975 "")
266eb58a 7976
dfbdccdb 7977(define_insn "*boolccdi3_internal3"
9ebbca7d 7978 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7979 (compare:CC (match_operator:DI 4 "boolean_operator"
7980 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7981 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7982 (const_int 0)))
9ebbca7d 7983 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7984 (match_dup 4))]
683bdff7 7985 "TARGET_64BIT"
9ebbca7d 7986 "@
dfbdccdb 7987 %q4. %0,%1,%2
9ebbca7d
GK		 7988 #"
7989 [(set_attr "type" "compare")
7990 (set_attr "length" "4,8")])
7991
7992(define_split
e72247f4 7993 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7994 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7995 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7996 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7997 (const_int 0)))
75540af0 7998 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7999 (match_dup 4))]
9ebbca7d 8000 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 8001 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 8002 (set (match_dup 3)
8003 (compare:CC (match_dup 0)
8004 (const_int 0)))]
8005 "")
dfbdccdb 8006\f
1fd4e8c1 8007;; Now define ways of moving data around.
4697a36c 8008
766a866c
MM		 8009;; Set up a register with a value from the GOT table
8010
8011(define_expand "movsi_got"
52d3af72 8012 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8013 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 8014 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 8015 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 8016 "
8017{
38c1f2d7
MM		 8018 if (GET_CODE (operands[1]) == CONST)
8019 {
8020 rtx offset = const0_rtx;
8021 HOST_WIDE_INT value;
8022
8023 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8024 value = INTVAL (offset);
8025 if (value != 0)
8026 {
b3a13419
ILT		 8027 rtx tmp = (!can_create_pseudo_p ()
8028 ? operands[0]
8029 : gen_reg_rtx (Pmode));
38c1f2d7
MM		 8030 emit_insn (gen_movsi_got (tmp, operands[1]));
8031 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8032 DONE;
8033 }
8034 }
8035
c4c40373 8036 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 8037}")
8038
84f414bc 8039(define_insn "*movsi_got_internal"
52d3af72 8040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 8041 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8042 (match_operand:SI 2 "gpc_reg_operand" "b")]
8043 UNSPEC_MOVSI_GOT))]
f607bc57 8044 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 8045 "{l|lwz} %0,%a1@got(%2)"
8046 [(set_attr "type" "load")])
8047
b22b9b3e
JL		 8048;; Used by sched, shorten_branches and final when the GOT pseudo reg
8049;; didn't get allocated to a hard register.
6ae08853 8050(define_split
75540af0 8051 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8052 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8053 (match_operand:SI 2 "memory_operand" "")]
8054 UNSPEC_MOVSI_GOT))]
f607bc57 8055 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 8056 && flag_pic == 1
8057 && (reload_in_progress || reload_completed)"
8058 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 8059 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8060 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 8061 "")
8062
1fd4e8c1
RK		 8063;; For SI, we special-case integers that can't be loaded in one insn. We
8064;; do the load 16-bits at a time. We could do this by loading from memory,
8065;; and this is even supposed to be faster, but it is simpler not to get
8066;; integers in the TOC.
ee890fe2
SS		 8067(define_insn "movsi_low"
8068 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 8069 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 8070 (match_operand 2 "" ""))))]
8071 "TARGET_MACHO && ! TARGET_64BIT"
8072 "{l|lwz} %0,lo16(%2)(%1)"
8073 [(set_attr "type" "load")
8074 (set_attr "length" "4")])
8075
acad7ed3 8076(define_insn "*movsi_internal1"
165a5bad 8077 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
a004eb82 8078 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
19d5775a
RK		 8079 "gpc_reg_operand (operands[0], SImode)
8080 || gpc_reg_operand (operands[1], SImode)"
1fd4e8c1 8081 "@
deb9225a 8082 mr %0,%1
b9442c72 8083 {cal|la} %0,%a1
ca7f5001
RK		 8084 {l%U1%X1|lwz%U1%X1} %0,%1
8085 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 8086 {lil|li} %0,%1
802a0058 8087 {liu|lis} %0,%v1
beaec479 8088 #
aee86b38 8089 {cal|la} %0,%a1
1fd4e8c1 8090 mf%1 %0
5c23c401 8091 mt%0 %1
e76e75bb 8092 mt%0 %1
a004eb82 8093 mt%0 %1
e34eaae5 8094 {cror 0,0,0|nop}"
02ca7595 8095 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 8096 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 8097
77fa0940
RK		 8098;; Split a load of a large constant into the appropriate two-insn
8099;; sequence.
8100
8101(define_split
8102 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8103 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 8104 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 8105 && (INTVAL (operands[1]) & 0xffff) != 0"
8106 [(set (match_dup 0)
8107 (match_dup 2))
8108 (set (match_dup 0)
8109 (ior:SI (match_dup 0)
8110 (match_dup 3)))]
8111 "
af8cb5c5
DE		 8112{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8113
8114 if (tem == operands[0])
8115 DONE;
8116 else
8117 FAIL;
77fa0940
RK		 8118}")
8119
4ae234b0 8120(define_insn "*mov<mode>_internal2"
bb84cb12 8121 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
4ae234b0 8122 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 8123 (const_int 0)))
4ae234b0
GK		 8124 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8125 ""
9ebbca7d 8126 "@
4ae234b0 8127 {cmpi|cmp<wd>i} %2,%0,0
9ebbca7d
GK		 8128 mr. %0,%1
8129 #"
bb84cb12
DE		 8130 [(set_attr "type" "cmp,compare,cmp")
8131 (set_attr "length" "4,4,8")])
8132
9ebbca7d
GK		 8133(define_split
8134 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
4ae234b0 8135 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9ebbca7d 8136 (const_int 0)))
4ae234b0
GK		 8137 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8138 "reload_completed"
9ebbca7d
GK		 8139 [(set (match_dup 0) (match_dup 1))
8140 (set (match_dup 2)
8141 (compare:CC (match_dup 0)
8142 (const_int 0)))]
8143 "")
bb84cb12 8144\f
e34eaae5 8145(define_insn "*movhi_internal"
fb81d7ce
RK		 8146 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8147 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8148 "gpc_reg_operand (operands[0], HImode)
8149 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 8150 "@
deb9225a 8151 mr %0,%1
1fd4e8c1
RK		 8152 lhz%U1%X1 %0,%1
8153 sth%U0%X0 %1,%0
19d5775a 8154 {lil|li} %0,%w1
1fd4e8c1 8155 mf%1 %0
e76e75bb 8156 mt%0 %1
fb81d7ce 8157 mt%0 %1
e34eaae5 8158 {cror 0,0,0|nop}"
02ca7595 8159 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1 8160
4ae234b0
GK		 8161(define_expand "mov<mode>"
8162 [(set (match_operand:INT 0 "general_operand" "")
8163 (match_operand:INT 1 "any_operand" ""))]
1fd4e8c1 8164 ""
4ae234b0 8165 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
1fd4e8c1 8166
e34eaae5 8167(define_insn "*movqi_internal"
fb81d7ce
RK		 8168 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8169 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8170 "gpc_reg_operand (operands[0], QImode)
8171 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 8172 "@
deb9225a 8173 mr %0,%1
1fd4e8c1
RK		 8174 lbz%U1%X1 %0,%1
8175 stb%U0%X0 %1,%0
19d5775a 8176 {lil|li} %0,%1
1fd4e8c1 8177 mf%1 %0
e76e75bb 8178 mt%0 %1
fb81d7ce 8179 mt%0 %1
e34eaae5 8180 {cror 0,0,0|nop}"
02ca7595 8181 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 8182\f
8183;; Here is how to move condition codes around. When we store CC data in
8184;; an integer register or memory, we store just the high-order 4 bits.
8185;; This lets us not shift in the most common case of CR0.
8186(define_expand "movcc"
8187 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8188 (match_operand:CC 1 "nonimmediate_operand" ""))]
8189 ""
8190 "")
8191
a65c591c 8192(define_insn "*movcc_internal1"
4eb585a4
DE		 8193 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8194 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
1fd4e8c1
RK		 8195 "register_operand (operands[0], CCmode)
8196 || register_operand (operands[1], CCmode)"
8197 "@
8198 mcrf %0,%1
8199 mtcrf 128,%1
ca7f5001 8200 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
4eb585a4 8201 crxor %0,%0,%0
2c4a9cff
DE		 8202 mfcr %0%Q1
8203 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 8204 mr %0,%1
4eb585a4 8205 {lil|li} %0,%1
b54cf83a 8206 mf%1 %0
b991a865
GK		 8207 mt%0 %1
8208 mt%0 %1
ca7f5001
RK		 8209 {l%U1%X1|lwz%U1%X1} %0,%1
8210 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff 8211 [(set (attr "type")
4eb585a4 8212 (cond [(eq_attr "alternative" "0,3")
2c4a9cff
DE		 8213 (const_string "cr_logical")
8214 (eq_attr "alternative" "1,2")
8215 (const_string "mtcr")
4eb585a4 8216 (eq_attr "alternative" "6,7,9")
2c4a9cff 8217 (const_string "integer")
2c4a9cff 8218 (eq_attr "alternative" "8")
4eb585a4
DE		 8219 (const_string "mfjmpr")
8220 (eq_attr "alternative" "10")
2c4a9cff 8221 (const_string "mtjmpr")
4eb585a4 8222 (eq_attr "alternative" "11")
2c4a9cff 8223 (const_string "load")
4eb585a4 8224 (eq_attr "alternative" "12")
2c4a9cff
DE		 8225 (const_string "store")
8226 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8227 (const_string "mfcrf")
8228 ]
8229 (const_string "mfcr")))
4eb585a4 8230 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
1fd4e8c1 8231\f
e52e05ca
MM		 8232;; For floating-point, we normally deal with the floating-point registers
8233;; unless -msoft-float is used. The sole exception is that parameter passing
8234;; can produce floating-point values in fixed-point registers. Unless the
8235;; value is a simple constant or already in memory, we deal with this by
8236;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 8237(define_expand "movsf"
8238 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8239 (match_operand:SF 1 "any_operand" ""))]
8240 ""
fb4d4348 8241 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 8242
1fd4e8c1 8243(define_split
cd2b37d9 8244 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 8245 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 8246 "reload_completed
5ae4759c
MM		 8247 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8248 || (GET_CODE (operands[0]) == SUBREG
8249 && GET_CODE (SUBREG_REG (operands[0])) == REG
8250 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 8251 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 8252 "
8253{
8254 long l;
8255 REAL_VALUE_TYPE rv;
8256
8257 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8258 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 8259
f99f88e0
DE		 8260 if (! TARGET_POWERPC64)
8261 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8262 else
8263 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 8264
2496c7bd 8265 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 8266}")
8267
c4c40373 8268(define_insn "*movsf_hardfloat"
fb3249ef 8269 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
ae6669e7 8270 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
d14a6d05 8271 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8272 || gpc_reg_operand (operands[1], SFmode))
8273 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
1fd4e8c1 8274 "@
f99f88e0
DE		 8275 mr %0,%1
8276 {l%U1%X1|lwz%U1%X1} %0,%1
8277 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 8278 fmr %0,%1
8279 lfs%U1%X1 %0,%1
c4c40373 8280 stfs%U0%X0 %1,%0
b991a865
GK		 8281 mt%0 %1
8282 mt%0 %1
8283 mf%1 %0
e0740893 8284 {cror 0,0,0|nop}
c4c40373
MM		 8285 #
8286 #"
9c6fdb46 8287 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
ae6669e7 8288 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 8289
c4c40373 8290(define_insn "*movsf_softfloat"
dd0fbae2
MK		 8291 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8292 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 8293 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8294 || gpc_reg_operand (operands[1], SFmode))
8295 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 8296 "@
8297 mr %0,%1
b991a865
GK		 8298 mt%0 %1
8299 mt%0 %1
8300 mf%1 %0
d14a6d05
MM		 8301 {l%U1%X1|lwz%U1%X1} %0,%1
8302 {st%U0%X0|stw%U0%X0} %1,%0
8303 {lil|li} %0,%1
802a0058 8304 {liu|lis} %0,%v1
aee86b38 8305 {cal|la} %0,%a1
c4c40373 8306 #
dd0fbae2
MK		 8307 #
8308 {cror 0,0,0|nop}"
9c6fdb46 8309 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
dd0fbae2 8310 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 8311
1fd4e8c1
RK		 8312\f
8313(define_expand "movdf"
8314 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8315 (match_operand:DF 1 "any_operand" ""))]
8316 ""
fb4d4348 8317 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 8318
8319(define_split
cd2b37d9 8320 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 8321 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 8322 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8323 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8324 || (GET_CODE (operands[0]) == SUBREG
8325 && GET_CODE (SUBREG_REG (operands[0])) == REG
8326 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8327 [(set (match_dup 2) (match_dup 4))
8328 (set (match_dup 3) (match_dup 1))]
8329 "
8330{
5ae4759c 8331 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 8332 HOST_WIDE_INT value = INTVAL (operands[1]);
8333
5ae4759c
MM		 8334 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8335 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 8336#if HOST_BITS_PER_WIDE_INT == 32
8337 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8338#else
8339 operands[4] = GEN_INT (value >> 32);
a65c591c 8340 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 8341#endif
c4c40373
MM		 8342}")
8343
c4c40373
MM		 8344(define_split
8345 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8346 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8347 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8348 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8349 || (GET_CODE (operands[0]) == SUBREG
8350 && GET_CODE (SUBREG_REG (operands[0])) == REG
8351 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8352 [(set (match_dup 2) (match_dup 4))
8353 (set (match_dup 3) (match_dup 5))]
8354 "
8355{
5ae4759c 8356 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 8357 long l[2];
8358 REAL_VALUE_TYPE rv;
8359
8360 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8361 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8362
5ae4759c
MM		 8363 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8364 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 8365 operands[4] = gen_int_mode (l[endian], SImode);
8366 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 8367}")
8368
efc08378
DE		 8369(define_split
8370 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8308679f 8371 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8372 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8373 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8374 || (GET_CODE (operands[0]) == SUBREG
8375 && GET_CODE (SUBREG_REG (operands[0])) == REG
8376 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 8377 [(set (match_dup 2) (match_dup 3))]
5ae4759c 8378 "
a260abc9
DE		 8379{
8380 int endian = (WORDS_BIG_ENDIAN == 0);
8381 long l[2];
8382 REAL_VALUE_TYPE rv;
4977bab6 8383#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 8384 HOST_WIDE_INT val;
4977bab6 8385#endif
a260abc9
DE		 8386
8387 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8388 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8389
8390 operands[2] = gen_lowpart (DImode, operands[0]);
8391 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 8392#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8393 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8394 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 8395
f5264b52 8396 operands[3] = gen_int_mode (val, DImode);
5b029315 8397#else
a260abc9 8398 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 8399#endif
a260abc9 8400}")
efc08378 8401
4eae5fe1 8402;; Don't have reload use general registers to load a constant. First,
1427100a 8403;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 8404;; a non-offsettable memref, but also it is less efficient than loading
8405;; the constant into an FP register, since it will probably be used there.
8406;; The "??" is a kludge until we can figure out a more reasonable way
8407;; of handling these non-offsettable values.
c4c40373 8408(define_insn "*movdf_hardfloat32"
914a7297
DE		 8409 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8410 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
a3170dc6 8411 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8412 && (gpc_reg_operand (operands[0], DFmode)
8413 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 8414 "*
8415{
8416 switch (which_alternative)
8417 {
a260abc9 8418 default:
37409796 8419 gcc_unreachable ();
e7113111
RK		 8420 case 0:
8421 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 8422 the first register operand 0 is the same as the second register
8423 of operand 1, we must copy in the opposite order. */
e7113111 8424 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8425 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 8426 else
deb9225a 8427 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 8428 case 1:
d04b6e6e
EB		 8429 if (rs6000_offsettable_memref_p (operands[1])
8430 || (GET_CODE (operands[1]) == MEM
8431 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8432 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
6fb5fa3c
DB		 8433 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8434 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
000034eb
DE		 8435 {
8436 /* If the low-address word is used in the address, we must load
8437 it last. Otherwise, load it first. Note that we cannot have
8438 auto-increment in that case since the address register is
8439 known to be dead. */
8440 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8441 operands[1], 0))
8442 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8443 else
6fb5fa3c 8444 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
000034eb 8445 }
e7113111 8446 else
000034eb
DE		 8447 {
8448 rtx addreg;
8449
000034eb
DE		 8450 addreg = find_addr_reg (XEXP (operands[1], 0));
8451 if (refers_to_regno_p (REGNO (operands[0]),
8452 REGNO (operands[0]) + 1,
8453 operands[1], 0))
8454 {
8455 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8456 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb 8457 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2284bd2b 8458 return \"{l%X1|lwz%X1} %0,%1\";
000034eb
DE		 8459 }
8460 else
8461 {
2284bd2b 8462 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
000034eb 8463 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8464 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb
DE		 8465 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8466 return \"\";
8467 }
8468 }
e7113111 8469 case 2:
d04b6e6e
EB		 8470 if (rs6000_offsettable_memref_p (operands[0])
8471 || (GET_CODE (operands[0]) == MEM
8472 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8473 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
6fb5fa3c
DB		 8474 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8475 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8476 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
000034eb
DE		 8477 else
8478 {
8479 rtx addreg;
8480
000034eb 8481 addreg = find_addr_reg (XEXP (operands[0], 0));
2284bd2b 8482 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
000034eb 8483 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8484 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
000034eb
DE		 8485 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8486 return \"\";
8487 }
e7113111 8488 case 3:
914a7297 8489 return \"fmr %0,%1\";
e7113111 8490 case 4:
914a7297 8491 return \"lfd%U1%X1 %0,%1\";
e7113111 8492 case 5:
914a7297 8493 return \"stfd%U0%X0 %1,%0\";
e7113111 8494 case 6:
c4c40373 8495 case 7:
c4c40373 8496 case 8:
914a7297 8497 return \"#\";
e7113111
RK		 8498 }
8499}"
943c15ed 8500 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
914a7297 8501 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 8502
c4c40373 8503(define_insn "*movdf_softfloat32"
1427100a
DE		 8504 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8505 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7a2f7870 8506 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
52d3af72
DE		 8507 && (gpc_reg_operand (operands[0], DFmode)
8508 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8509 "*
8510{
8511 switch (which_alternative)
8512 {
a260abc9 8513 default:
37409796 8514 gcc_unreachable ();
dc4f83ca
MM		 8515 case 0:
8516 /* We normally copy the low-numbered register first. However, if
8517 the first register operand 0 is the same as the second register of
8518 operand 1, we must copy in the opposite order. */
8519 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8520 return \"mr %L0,%L1\;mr %0,%1\";
8521 else
8522 return \"mr %0,%1\;mr %L0,%L1\";
8523 case 1:
3cb999d8
DE		 8524 /* If the low-address word is used in the address, we must load
8525 it last. Otherwise, load it first. Note that we cannot have
8526 auto-increment in that case since the address register is
8527 known to be dead. */
dc4f83ca 8528 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8529 operands[1], 0))
dc4f83ca
MM		 8530 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8531 else
6fb5fa3c 8532 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
dc4f83ca 8533 case 2:
6fb5fa3c 8534 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
dc4f83ca 8535 case 3:
c4c40373
MM		 8536 case 4:
8537 case 5:
dc4f83ca
MM		 8538 return \"#\";
8539 }
8540}"
943c15ed 8541 [(set_attr "type" "two,load,store,*,*,*")
c4c40373 8542 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8543
44cd321e
PS		 8544; ld/std require word-aligned displacements -> 'Y' constraint.
8545; List Y->r and r->Y before r->r for reload.
8546(define_insn "*movdf_hardfloat64_mfpgpr"
8547 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8548 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8549 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8550 && (gpc_reg_operand (operands[0], DFmode)
8551 || gpc_reg_operand (operands[1], DFmode))"
8552 "@
8553 std%U0%X0 %1,%0
8554 ld%U1%X1 %0,%1
8555 mr %0,%1
8556 fmr %0,%1
8557 lfd%U1%X1 %0,%1
8558 stfd%U0%X0 %1,%0
8559 mt%0 %1
8560 mf%1 %0
8561 {cror 0,0,0|nop}
8562 #
8563 #
8564 #
8565 mftgpr %0,%1
8566 mffgpr %0,%1"
8567 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8568 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8569
d2288d5d
HP		 8570; ld/std require word-aligned displacements -> 'Y' constraint.
8571; List Y->r and r->Y before r->r for reload.
c4c40373 8572(define_insn "*movdf_hardfloat64"
fb3249ef 8573 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
ae6669e7 8574 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
44cd321e 8575 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8576 && (gpc_reg_operand (operands[0], DFmode)
8577 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8578 "@
96bb8ed3 8579 std%U0%X0 %1,%0
3364872d
FJ		 8580 ld%U1%X1 %0,%1
8581 mr %0,%1
3d5570cb 8582 fmr %0,%1
f63184ac 8583 lfd%U1%X1 %0,%1
914a7297
DE		 8584 stfd%U0%X0 %1,%0
8585 mt%0 %1
8586 mf%1 %0
e0740893 8587 {cror 0,0,0|nop}
914a7297
DE		 8588 #
8589 #
8590 #"
9c6fdb46 8591 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
ae6669e7 8592 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8593
c4c40373 8594(define_insn "*movdf_softfloat64"
d2288d5d
HP		 8595 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8596 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
a3170dc6 8597 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8598 && (gpc_reg_operand (operands[0], DFmode)
8599 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca 8600 "@
d2288d5d
HP		 8601 ld%U1%X1 %0,%1
8602 std%U0%X0 %1,%0
dc4f83ca 8603 mr %0,%1
914a7297
DE		 8604 mt%0 %1
8605 mf%1 %0
c4c40373
MM		 8606 #
8607 #
e2d0915c 8608 #
e0740893 8609 {cror 0,0,0|nop}"
9c6fdb46 8610 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
e2d0915c 8611 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 8612\f
06f4e019
DE		 8613(define_expand "movtf"
8614 [(set (match_operand:TF 0 "general_operand" "")
8615 (match_operand:TF 1 "any_operand" ""))]
8521c414 8616 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8617 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8618
a9baceb1
GK		 8619; It's important to list the o->f and f->o moves before f->f because
8620; otherwise reload, given m->f, will try to pick f->f and reload it,
409f61cd 8621; which doesn't make progress. Likewise r->Y must be before r->r.
a9baceb1 8622(define_insn_and_split "*movtf_internal"
409f61cd
AM		 8623 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8624 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
602ea4d3 8625 "!TARGET_IEEEQUAD
39e63627 8626 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8627 && (gpc_reg_operand (operands[0], TFmode)
8628 || gpc_reg_operand (operands[1], TFmode))"
a9baceb1 8629 "#"
ecb62ae7 8630 "&& reload_completed"
a9baceb1
GK		 8631 [(pc)]
8632{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
112ccb83 8633 [(set_attr "length" "8,8,8,20,20,16")])
06f4e019 8634
8521c414 8635(define_insn_and_split "*movtf_softfloat"
17caeff2 8636 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8521c414
JM		 8637 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8638 "!TARGET_IEEEQUAD
8639 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8640 && (gpc_reg_operand (operands[0], TFmode)
8641 || gpc_reg_operand (operands[1], TFmode))"
8642 "#"
8643 "&& reload_completed"
8644 [(pc)]
8645{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8646 [(set_attr "length" "20,20,16")])
8647
ecb62ae7 8648(define_expand "extenddftf2"
17caeff2
JM		 8649 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8650 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8651 "!TARGET_IEEEQUAD
8652 && TARGET_HARD_FLOAT
8653 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8654 && TARGET_LONG_DOUBLE_128"
8655{
8656 if (TARGET_E500_DOUBLE)
8657 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8658 else
8659 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8660 DONE;
8661})
8662
8663(define_expand "extenddftf2_fprs"
ecb62ae7
GK		 8664 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8665 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8666 (use (match_dup 2))])]
602ea4d3 8667 "!TARGET_IEEEQUAD
39e63627 8668 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8669{
ecb62ae7 8670 operands[2] = CONST0_RTX (DFmode);
aa9cf005
DE		 8671 /* Generate GOT reference early for SVR4 PIC. */
8672 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8673 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
ecb62ae7 8674})
06f4e019 8675
ecb62ae7
GK		 8676(define_insn_and_split "*extenddftf2_internal"
8677 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8678 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
97c54d9a 8679 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
602ea4d3 8680 "!TARGET_IEEEQUAD
39e63627 8681 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8682 "#"
8683 "&& reload_completed"
8684 [(pc)]
06f4e019 8685{
ecb62ae7
GK		 8686 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8687 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8688 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8689 operands[1]);
8690 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8691 operands[2]);
8692 DONE;
6ae08853 8693})
ecb62ae7
GK		 8694
8695(define_expand "extendsftf2"
8696 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8697 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
602ea4d3 8698 "!TARGET_IEEEQUAD
17caeff2
JM		 8699 && TARGET_HARD_FLOAT
8700 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8701 && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8702{
8703 rtx tmp = gen_reg_rtx (DFmode);
8704 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8705 emit_insn (gen_extenddftf2 (operands[0], tmp));
8706 DONE;
8707})
06f4e019 8708
8cb320b8 8709(define_expand "trunctfdf2"
589b3fda
DE		 8710 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8711 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8712 "!TARGET_IEEEQUAD
17caeff2
JM		 8713 && TARGET_HARD_FLOAT
8714 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8715 && TARGET_LONG_DOUBLE_128"
589b3fda 8716 "")
8cb320b8
DE		 8717
8718(define_insn_and_split "trunctfdf2_internal1"
8719 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8720 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
602ea4d3 8721 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8cb320b8
DE		 8722 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8723 "@
8724 #
8725 fmr %0,%1"
8726 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8727 [(const_int 0)]
8728{
8729 emit_note (NOTE_INSN_DELETED);
8730 DONE;
8731}
8732 [(set_attr "type" "fp")])
8733
8734(define_insn "trunctfdf2_internal2"
8735 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8736 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8737 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8cb320b8 8738 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8739 "fadd %0,%1,%L1"
8cb320b8 8740 [(set_attr "type" "fp")])
06f4e019 8741
17caeff2
JM		 8742(define_expand "trunctfsf2"
8743 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8744 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8745 "!TARGET_IEEEQUAD
8746 && TARGET_HARD_FLOAT
8747 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8748 && TARGET_LONG_DOUBLE_128"
8749{
8750 if (TARGET_E500_DOUBLE)
8751 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8752 else
8753 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8754 DONE;
8755})
8756
8757(define_insn_and_split "trunctfsf2_fprs"
06f4e019 8758 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 8759 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8760 (clobber (match_scratch:DF 2 "=f"))]
602ea4d3 8761 "!TARGET_IEEEQUAD
39e63627 8762 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8763 "#"
ea112fc4 8764 "&& reload_completed"
06f4e019
DE		 8765 [(set (match_dup 2)
8766 (float_truncate:DF (match_dup 1)))
8767 (set (match_dup 0)
8768 (float_truncate:SF (match_dup 2)))]
ea112fc4 8769 "")
06f4e019 8770
0c90aa3c 8771(define_expand "floatsitf2"
d29b7f64
DE		 8772 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8773 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
602ea4d3 8774 "!TARGET_IEEEQUAD
17caeff2
JM		 8775 && TARGET_HARD_FLOAT
8776 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8777 && TARGET_LONG_DOUBLE_128"
0c90aa3c
GK		 8778{
8779 rtx tmp = gen_reg_rtx (DFmode);
8780 expand_float (tmp, operands[1], false);
8781 emit_insn (gen_extenddftf2 (operands[0], tmp));
8782 DONE;
8783})
06f4e019 8784
ecb62ae7
GK		 8785; fadd, but rounding towards zero.
8786; This is probably not the optimal code sequence.
8787(define_insn "fix_trunc_helper"
8788 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8789 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8790 UNSPEC_FIX_TRUNC_TF))
8791 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8792 "TARGET_HARD_FLOAT && TARGET_FPRS"
8793 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8794 [(set_attr "type" "fp")
8795 (set_attr "length" "20")])
8796
0c90aa3c 8797(define_expand "fix_trunctfsi2"
17caeff2
JM		 8798 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8799 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8800 "!TARGET_IEEEQUAD
8801 && (TARGET_POWER2 || TARGET_POWERPC)
8802 && TARGET_HARD_FLOAT
8803 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8804 && TARGET_LONG_DOUBLE_128"
8805{
8806 if (TARGET_E500_DOUBLE)
8807 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8808 else
8809 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8810 DONE;
8811})
8812
8813(define_expand "fix_trunctfsi2_fprs"
ecb62ae7
GK		 8814 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8815 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8816 (clobber (match_dup 2))
8817 (clobber (match_dup 3))
8818 (clobber (match_dup 4))
8819 (clobber (match_dup 5))])]
602ea4d3 8820 "!TARGET_IEEEQUAD
ecb62ae7
GK		 8821 && (TARGET_POWER2 || TARGET_POWERPC)
8822 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8823{
8824 operands[2] = gen_reg_rtx (DFmode);
8825 operands[3] = gen_reg_rtx (DFmode);
8826 operands[4] = gen_reg_rtx (DImode);
8827 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8828})
8829
8830(define_insn_and_split "*fix_trunctfsi2_internal"
61c07d3c 8831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
ecb62ae7
GK		 8832 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8833 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8834 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8835 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
b0d6c7d8 8836 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
602ea4d3 8837 "!TARGET_IEEEQUAD
39e63627 8838 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 8839 "#"
b3a13419 8840 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
ecb62ae7 8841 [(pc)]
0c90aa3c 8842{
ecb62ae7
GK		 8843 rtx lowword;
8844 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8845
230215f5
GK		 8846 gcc_assert (MEM_P (operands[5]));
8847 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
ecb62ae7
GK		 8848
8849 emit_insn (gen_fctiwz (operands[4], operands[2]));
8850 emit_move_insn (operands[5], operands[4]);
230215f5 8851 emit_move_insn (operands[0], lowword);
0c90aa3c
GK		 8852 DONE;
8853})
06f4e019 8854
17caeff2
JM		 8855(define_expand "negtf2"
8856 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8857 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8858 "!TARGET_IEEEQUAD
8859 && TARGET_HARD_FLOAT
8860 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8861 && TARGET_LONG_DOUBLE_128"
8862 "")
8863
8864(define_insn "negtf2_internal"
06f4e019
DE		 8865 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8866 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8867 "!TARGET_IEEEQUAD
39e63627 8868 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8869 "*
8870{
8871 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8872 return \"fneg %L0,%L1\;fneg %0,%1\";
8873 else
8874 return \"fneg %0,%1\;fneg %L0,%L1\";
8875}"
8876 [(set_attr "type" "fp")
8877 (set_attr "length" "8")])
8878
1a402dc1 8879(define_expand "abstf2"
17caeff2
JM		 8880 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8881 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8882 "!TARGET_IEEEQUAD
17caeff2
JM		 8883 && TARGET_HARD_FLOAT
8884 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8885 && TARGET_LONG_DOUBLE_128"
1a402dc1 8886 "
06f4e019 8887{
1a402dc1 8888 rtx label = gen_label_rtx ();
17caeff2
JM		 8889 if (TARGET_E500_DOUBLE)
8890 {
8891 if (flag_unsafe_math_optimizations)
8892 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8893 else
8894 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8895 }
8896 else
8897 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
1a402dc1
AM		 8898 emit_label (label);
8899 DONE;
8900}")
06f4e019 8901
1a402dc1 8902(define_expand "abstf2_internal"
e42ac3de
RS		 8903 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8904 (match_operand:TF 1 "gpc_reg_operand" ""))
1a402dc1
AM		 8905 (set (match_dup 3) (match_dup 5))
8906 (set (match_dup 5) (abs:DF (match_dup 5)))
8907 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8908 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8909 (label_ref (match_operand 2 "" ""))
8910 (pc)))
8911 (set (match_dup 6) (neg:DF (match_dup 6)))]
602ea4d3 8912 "!TARGET_IEEEQUAD
39e63627 8913 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
1a402dc1 8914 "
06f4e019 8915{
1a402dc1
AM		 8916 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8917 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8918 operands[3] = gen_reg_rtx (DFmode);
8919 operands[4] = gen_reg_rtx (CCFPmode);
8920 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8921 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8922}")
06f4e019 8923\f
1fd4e8c1
RK		 8924;; Next come the multi-word integer load and store and the load and store
8925;; multiple insns.
1fd4e8c1 8926
112ccb83
GK		 8927; List r->r after r->"o<>", otherwise reload will try to reload a
8928; non-offsettable address by using r->r which won't make progress.
acad7ed3 8929(define_insn "*movdi_internal32"
17caeff2 8930 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
112ccb83 8931 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
a260abc9 8932 "! TARGET_POWERPC64
4e74d8ec
MM		 8933 && (gpc_reg_operand (operands[0], DImode)
8934 || gpc_reg_operand (operands[1], DImode))"
112ccb83
GK		 8935 "@
8936 #
8937 #
8938 #
8939 fmr %0,%1
8940 lfd%U1%X1 %0,%1
8941 stfd%U0%X0 %1,%0
8942 #"
8943 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
4e74d8ec
MM		 8944
8945(define_split
8946 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8947 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 8948 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8949 [(set (match_dup 2) (match_dup 4))
8950 (set (match_dup 3) (match_dup 1))]
8951 "
8952{
5f59ecb7 8953 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 8954 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8955 DImode);
8956 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8957 DImode);
75d39459 8958#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 8959 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 8960#else
5f59ecb7 8961 operands[4] = GEN_INT (value >> 32);
a65c591c 8962 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 8963#endif
4e74d8ec
MM		 8964}")
8965
3a1f863f 8966(define_split
17caeff2 8967 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
3a1f863f 8968 (match_operand:DI 1 "input_operand" ""))]
6ae08853 8969 "reload_completed && !TARGET_POWERPC64
3a1f863f 8970 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 8971 [(pc)]
8972{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
3a1f863f 8973
44cd321e
PS		 8974(define_insn "*movdi_mfpgpr"
8975 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8976 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8977 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8978 && (gpc_reg_operand (operands[0], DImode)
8979 || gpc_reg_operand (operands[1], DImode))"
8980 "@
8981 mr %0,%1
8982 ld%U1%X1 %0,%1
8983 std%U0%X0 %1,%0
8984 li %0,%1
8985 lis %0,%v1
8986 #
8987 {cal|la} %0,%a1
8988 fmr %0,%1
8989 lfd%U1%X1 %0,%1
8990 stfd%U0%X0 %1,%0
8991 mf%1 %0
8992 mt%0 %1
8993 {cror 0,0,0|nop}
8994 mftgpr %0,%1
8995 mffgpr %0,%1"
8996 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8997 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8998
acad7ed3 8999(define_insn "*movdi_internal64"
343f6bbf 9000 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9615f239 9001 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
44cd321e 9002 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
4e74d8ec
MM		 9003 && (gpc_reg_operand (operands[0], DImode)
9004 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 9005 "@
3d5570cb
RK		 9006 mr %0,%1
9007 ld%U1%X1 %0,%1
96bb8ed3 9008 std%U0%X0 %1,%0
3d5570cb 9009 li %0,%1
802a0058 9010 lis %0,%v1
e6ca2c17 9011 #
aee86b38 9012 {cal|la} %0,%a1
3d5570cb
RK		 9013 fmr %0,%1
9014 lfd%U1%X1 %0,%1
9015 stfd%U0%X0 %1,%0
9016 mf%1 %0
08075ead 9017 mt%0 %1
e34eaae5 9018 {cror 0,0,0|nop}"
02ca7595 9019 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 9020 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9021
5f59ecb7 9022;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 9023(define_insn ""
9024 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9025 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 9026 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9027 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 9028 && num_insns_constant (operands[1], DImode) == 1"
9029 "*
9030{
9031 return ((unsigned HOST_WIDE_INT)
9032 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9033 ? \"li %0,%1\" : \"lis %0,%v1\";
9034}")
9035
a260abc9
DE		 9036;; Generate all one-bits and clear left or right.
9037;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9038(define_split
9039 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1990cd79 9040 (match_operand:DI 1 "mask64_operand" ""))]
a260abc9
DE		 9041 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9042 [(set (match_dup 0) (const_int -1))
e6ca2c17 9043 (set (match_dup 0)
a260abc9
DE		 9044 (and:DI (rotate:DI (match_dup 0)
9045 (const_int 0))
9046 (match_dup 1)))]
9047 "")
9048
9049;; Split a load of a large constant into the appropriate five-instruction
9050;; sequence. Handle anything in a constant number of insns.
9051;; When non-easy constants can go in the TOC, this should use
9052;; easy_fp_constant predicate.
9053(define_split
9054 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9055 (match_operand:DI 1 "const_int_operand" ""))]
9056 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9057 [(set (match_dup 0) (match_dup 2))
9058 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 9059 "
2bfcf297
DB		 9060{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9061
9062 if (tem == operands[0])
9063 DONE;
e8d791dd 9064 else
2bfcf297 9065 FAIL;
5f59ecb7 9066}")
e6ca2c17 9067
5f59ecb7
DE		 9068(define_split
9069 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9070 (match_operand:DI 1 "const_double_operand" ""))]
9071 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9072 [(set (match_dup 0) (match_dup 2))
9073 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 9074 "
2bfcf297
DB		 9075{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9076
9077 if (tem == operands[0])
9078 DONE;
9079 else
9080 FAIL;
e6ca2c17 9081}")
acad7ed3 9082\f
1fd4e8c1
RK		 9083;; TImode is similar, except that we usually want to compute the address into
9084;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 9085;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 9086
9087;; We say that MQ is clobbered in the last alternative because the first
9088;; alternative would never get used otherwise since it would need a reload
9089;; while the 2nd alternative would not. We put memory cases first so they
9090;; are preferred. Otherwise, we'd try to reload the output instead of
9091;; giving the SCRATCH mq.
3a1f863f 9092
a260abc9 9093(define_insn "*movti_power"
7f514158
AM		 9094 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9095 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9096 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
6ae08853 9097 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 9098 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 9099 "*
9100{
9101 switch (which_alternative)
9102 {
dc4f83ca 9103 default:
37409796 9104 gcc_unreachable ();
dc4f83ca 9105
1fd4e8c1 9106 case 0:
3a1f863f
DE		 9107 if (TARGET_STRING)
9108 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 9109 case 1:
1fd4e8c1 9110 case 2:
3a1f863f 9111 return \"#\";
1fd4e8c1
RK		 9112 case 3:
9113 /* If the address is not used in the output, we can use lsi. Otherwise,
9114 fall through to generating four loads. */
e876481c
DE		 9115 if (TARGET_STRING
9116 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 9117 return \"{lsi|lswi} %0,%P1,16\";
82e41834 9118 /* ... fall through ... */
1fd4e8c1 9119 case 4:
7f514158 9120 case 5:
3a1f863f 9121 return \"#\";
1fd4e8c1
RK		 9122 }
9123}"
7f514158 9124 [(set_attr "type" "store,store,*,load,load,*")])
51b8fc2c 9125
a260abc9 9126(define_insn "*movti_string"
7f514158
AM		 9127 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9128 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
3a1f863f 9129 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 9130 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9131 "*
9132{
9133 switch (which_alternative)
9134 {
9135 default:
37409796 9136 gcc_unreachable ();
dc4f83ca 9137 case 0:
3a1f863f
DE		 9138 if (TARGET_STRING)
9139 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 9140 case 1:
cd1d3445 9141 case 2:
3a1f863f 9142 return \"#\";
cd1d3445
DE		 9143 case 3:
9144 /* If the address is not used in the output, we can use lsi. Otherwise,
9145 fall through to generating four loads. */
6ae08853 9146 if (TARGET_STRING
3a1f863f 9147 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 9148 return \"{lsi|lswi} %0,%P1,16\";
9149 /* ... fall through ... */
9150 case 4:
7f514158 9151 case 5:
3a1f863f 9152 return \"#\";
dc4f83ca
MM		 9153 }
9154}"
9c6fdb46 9155 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
dc4f83ca 9156
a260abc9 9157(define_insn "*movti_ppc64"
112ccb83
GK		 9158 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9159 (match_operand:TI 1 "input_operand" "r,r,m"))]
51b8fc2c
RK		 9160 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9161 || gpc_reg_operand (operands[1], TImode))"
112ccb83 9162 "#"
3a1f863f
DE		 9163 [(set_attr "type" "*,load,store")])
9164
7f514158
AM		 9165(define_split
9166 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9167 (match_operand:TI 1 "const_double_operand" ""))]
9168 "TARGET_POWERPC64"
9169 [(set (match_dup 2) (match_dup 4))
9170 (set (match_dup 3) (match_dup 5))]
9171 "
9172{
9173 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9174 TImode);
9175 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9176 TImode);
9177 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9178 {
9179 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9180 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9181 }
9182 else if (GET_CODE (operands[1]) == CONST_INT)
9183 {
9184 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9185 operands[5] = operands[1];
9186 }
9187 else
9188 FAIL;
9189}")
9190
3a1f863f
DE		 9191(define_split
9192 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9193 (match_operand:TI 1 "input_operand" ""))]
a9baceb1 9194 "reload_completed
3a1f863f 9195 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 9196 [(pc)]
9197{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
1fd4e8c1
RK		 9198\f
9199(define_expand "load_multiple"
2f622005
RK		 9200 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9201 (match_operand:SI 1 "" ""))
9202 (use (match_operand:SI 2 "" ""))])]
09a625f7 9203 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9204 "
9205{
9206 int regno;
9207 int count;
792760b9 9208 rtx op1;
1fd4e8c1
RK		 9209 int i;
9210
9211 /* Support only loading a constant number of fixed-point registers from
9212 memory and only bother with this if more than two; the machine
9213 doesn't support more than eight. */
9214 if (GET_CODE (operands[2]) != CONST_INT
9215 || INTVAL (operands[2]) <= 2
9216 || INTVAL (operands[2]) > 8
9217 || GET_CODE (operands[1]) != MEM
9218 || GET_CODE (operands[0]) != REG
9219 || REGNO (operands[0]) >= 32)
9220 FAIL;
9221
9222 count = INTVAL (operands[2]);
9223 regno = REGNO (operands[0]);
9224
39403d82 9225 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 9226 op1 = replace_equiv_address (operands[1],
9227 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 9228
9229 for (i = 0; i < count; i++)
9230 XVECEXP (operands[3], 0, i)
39403d82 9231 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 9232 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 9233}")
9234
9caa3eb2 9235(define_insn "*ldmsi8"
1fd4e8c1 9236 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 9237 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9238 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9239 (set (match_operand:SI 3 "gpc_reg_operand" "")
9240 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9241 (set (match_operand:SI 4 "gpc_reg_operand" "")
9242 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9243 (set (match_operand:SI 5 "gpc_reg_operand" "")
9244 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9245 (set (match_operand:SI 6 "gpc_reg_operand" "")
9246 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9247 (set (match_operand:SI 7 "gpc_reg_operand" "")
9248 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9249 (set (match_operand:SI 8 "gpc_reg_operand" "")
9250 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9251 (set (match_operand:SI 9 "gpc_reg_operand" "")
9252 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9253 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 9254 "*
9caa3eb2 9255{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9256 [(set_attr "type" "load_ux")
9caa3eb2 9257 (set_attr "length" "32")])
1fd4e8c1 9258
9caa3eb2
DE		 9259(define_insn "*ldmsi7"
9260 [(match_parallel 0 "load_multiple_operation"
9261 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9262 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9263 (set (match_operand:SI 3 "gpc_reg_operand" "")
9264 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9265 (set (match_operand:SI 4 "gpc_reg_operand" "")
9266 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9267 (set (match_operand:SI 5 "gpc_reg_operand" "")
9268 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9269 (set (match_operand:SI 6 "gpc_reg_operand" "")
9270 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9271 (set (match_operand:SI 7 "gpc_reg_operand" "")
9272 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9273 (set (match_operand:SI 8 "gpc_reg_operand" "")
9274 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9275 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9276 "*
9277{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9278 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9279 (set_attr "length" "32")])
9280
9281(define_insn "*ldmsi6"
9282 [(match_parallel 0 "load_multiple_operation"
9283 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9284 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9285 (set (match_operand:SI 3 "gpc_reg_operand" "")
9286 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9287 (set (match_operand:SI 4 "gpc_reg_operand" "")
9288 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9289 (set (match_operand:SI 5 "gpc_reg_operand" "")
9290 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9291 (set (match_operand:SI 6 "gpc_reg_operand" "")
9292 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9293 (set (match_operand:SI 7 "gpc_reg_operand" "")
9294 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9295 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9296 "*
9297{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9298 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9299 (set_attr "length" "32")])
9300
9301(define_insn "*ldmsi5"
9302 [(match_parallel 0 "load_multiple_operation"
9303 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9304 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9305 (set (match_operand:SI 3 "gpc_reg_operand" "")
9306 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9307 (set (match_operand:SI 4 "gpc_reg_operand" "")
9308 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9309 (set (match_operand:SI 5 "gpc_reg_operand" "")
9310 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9311 (set (match_operand:SI 6 "gpc_reg_operand" "")
9312 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9313 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9314 "*
9315{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9316 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9317 (set_attr "length" "32")])
9318
9319(define_insn "*ldmsi4"
9320 [(match_parallel 0 "load_multiple_operation"
9321 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9322 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9323 (set (match_operand:SI 3 "gpc_reg_operand" "")
9324 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9325 (set (match_operand:SI 4 "gpc_reg_operand" "")
9326 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9327 (set (match_operand:SI 5 "gpc_reg_operand" "")
9328 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9329 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9330 "*
9331{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9332 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9333 (set_attr "length" "32")])
9334
9335(define_insn "*ldmsi3"
9336 [(match_parallel 0 "load_multiple_operation"
9337 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9338 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9339 (set (match_operand:SI 3 "gpc_reg_operand" "")
9340 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9341 (set (match_operand:SI 4 "gpc_reg_operand" "")
9342 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9343 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9344 "*
9345{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9346 [(set_attr "type" "load_ux")
e82ee4cc 9347 (set_attr "length" "32")])
b19003d8 9348
1fd4e8c1 9349(define_expand "store_multiple"
2f622005
RK		 9350 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9351 (match_operand:SI 1 "" ""))
9352 (clobber (scratch:SI))
9353 (use (match_operand:SI 2 "" ""))])]
09a625f7 9354 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9355 "
9356{
9357 int regno;
9358 int count;
9359 rtx to;
792760b9 9360 rtx op0;
1fd4e8c1
RK		 9361 int i;
9362
9363 /* Support only storing a constant number of fixed-point registers to
9364 memory and only bother with this if more than two; the machine
9365 doesn't support more than eight. */
9366 if (GET_CODE (operands[2]) != CONST_INT
9367 || INTVAL (operands[2]) <= 2
9368 || INTVAL (operands[2]) > 8
9369 || GET_CODE (operands[0]) != MEM
9370 || GET_CODE (operands[1]) != REG
9371 || REGNO (operands[1]) >= 32)
9372 FAIL;
9373
9374 count = INTVAL (operands[2]);
9375 regno = REGNO (operands[1]);
9376
39403d82 9377 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 9378 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 9379 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 9380
9381 XVECEXP (operands[3], 0, 0)
7ef788f0 9382 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 9383 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 9384 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 9385
9386 for (i = 1; i < count; i++)
9387 XVECEXP (operands[3], 0, i + 1)
39403d82 9388 = gen_rtx_SET (VOIDmode,
7ef788f0 9389 adjust_address_nv (op0, SImode, i * 4),
c5c76735 9390 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 9391}")
9392
e46e3130 9393(define_insn "*stmsi8"
d14a6d05 9394 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 9395 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9396 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9397 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9398 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9399 (match_operand:SI 4 "gpc_reg_operand" "r"))
9400 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9401 (match_operand:SI 5 "gpc_reg_operand" "r"))
9402 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9403 (match_operand:SI 6 "gpc_reg_operand" "r"))
9404 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9405 (match_operand:SI 7 "gpc_reg_operand" "r"))
9406 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9407 (match_operand:SI 8 "gpc_reg_operand" "r"))
9408 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9409 (match_operand:SI 9 "gpc_reg_operand" "r"))
9410 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9411 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9412 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9413 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9414 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9415
9416(define_insn "*stmsi7"
9417 [(match_parallel 0 "store_multiple_operation"
9418 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9419 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9420 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9421 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9422 (match_operand:SI 4 "gpc_reg_operand" "r"))
9423 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9424 (match_operand:SI 5 "gpc_reg_operand" "r"))
9425 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9426 (match_operand:SI 6 "gpc_reg_operand" "r"))
9427 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9428 (match_operand:SI 7 "gpc_reg_operand" "r"))
9429 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9430 (match_operand:SI 8 "gpc_reg_operand" "r"))
9431 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9432 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9433 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9434 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9435 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9436
9437(define_insn "*stmsi6"
9438 [(match_parallel 0 "store_multiple_operation"
9439 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9440 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9441 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9442 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9443 (match_operand:SI 4 "gpc_reg_operand" "r"))
9444 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9445 (match_operand:SI 5 "gpc_reg_operand" "r"))
9446 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9447 (match_operand:SI 6 "gpc_reg_operand" "r"))
9448 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9449 (match_operand:SI 7 "gpc_reg_operand" "r"))
9450 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9451 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9452 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9453 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9454 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9455
9456(define_insn "*stmsi5"
9457 [(match_parallel 0 "store_multiple_operation"
9458 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9459 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9460 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9461 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9462 (match_operand:SI 4 "gpc_reg_operand" "r"))
9463 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9464 (match_operand:SI 5 "gpc_reg_operand" "r"))
9465 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9466 (match_operand:SI 6 "gpc_reg_operand" "r"))
9467 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9468 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9469 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9470 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9471 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9472
9473(define_insn "*stmsi4"
9474 [(match_parallel 0 "store_multiple_operation"
9475 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9476 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9477 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9478 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9479 (match_operand:SI 4 "gpc_reg_operand" "r"))
9480 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9481 (match_operand:SI 5 "gpc_reg_operand" "r"))
9482 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9483 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9484 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82 9485 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9486 [(set_attr "type" "store_ux")])
7e69e155 9487
e46e3130
DJ		 9488(define_insn "*stmsi3"
9489 [(match_parallel 0 "store_multiple_operation"
9490 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9491 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9492 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9493 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9494 (match_operand:SI 4 "gpc_reg_operand" "r"))
9495 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9496 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9497 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9498 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9499 [(set_attr "type" "store_ux")])
d2894ab5
DE		 9500
9501(define_insn "*stmsi8_power"
9502 [(match_parallel 0 "store_multiple_operation"
9503 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9504 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9505 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9506 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9507 (match_operand:SI 4 "gpc_reg_operand" "r"))
9508 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9509 (match_operand:SI 5 "gpc_reg_operand" "r"))
9510 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9511 (match_operand:SI 6 "gpc_reg_operand" "r"))
9512 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9513 (match_operand:SI 7 "gpc_reg_operand" "r"))
9514 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9515 (match_operand:SI 8 "gpc_reg_operand" "r"))
9516 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9517 (match_operand:SI 9 "gpc_reg_operand" "r"))
9518 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9519 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9520 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9521 "{stsi|stswi} %2,%1,%O0"
9522 [(set_attr "type" "store_ux")])
9523
9524(define_insn "*stmsi7_power"
9525 [(match_parallel 0 "store_multiple_operation"
9526 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9527 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9528 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9529 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9530 (match_operand:SI 4 "gpc_reg_operand" "r"))
9531 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9532 (match_operand:SI 5 "gpc_reg_operand" "r"))
9533 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9534 (match_operand:SI 6 "gpc_reg_operand" "r"))
9535 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9536 (match_operand:SI 7 "gpc_reg_operand" "r"))
9537 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9538 (match_operand:SI 8 "gpc_reg_operand" "r"))
9539 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9540 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9541 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9542 "{stsi|stswi} %2,%1,%O0"
9543 [(set_attr "type" "store_ux")])
9544
9545(define_insn "*stmsi6_power"
9546 [(match_parallel 0 "store_multiple_operation"
9547 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9548 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9549 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9550 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9551 (match_operand:SI 4 "gpc_reg_operand" "r"))
9552 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9553 (match_operand:SI 5 "gpc_reg_operand" "r"))
9554 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9555 (match_operand:SI 6 "gpc_reg_operand" "r"))
9556 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9557 (match_operand:SI 7 "gpc_reg_operand" "r"))
9558 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9559 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9560 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9561 "{stsi|stswi} %2,%1,%O0"
9562 [(set_attr "type" "store_ux")])
9563
9564(define_insn "*stmsi5_power"
9565 [(match_parallel 0 "store_multiple_operation"
9566 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9567 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9568 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9569 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9570 (match_operand:SI 4 "gpc_reg_operand" "r"))
9571 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9572 (match_operand:SI 5 "gpc_reg_operand" "r"))
9573 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9574 (match_operand:SI 6 "gpc_reg_operand" "r"))
9575 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9576 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9577 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9578 "{stsi|stswi} %2,%1,%O0"
9579 [(set_attr "type" "store_ux")])
9580
9581(define_insn "*stmsi4_power"
9582 [(match_parallel 0 "store_multiple_operation"
9583 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9584 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9585 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9586 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9587 (match_operand:SI 4 "gpc_reg_operand" "r"))
9588 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9589 (match_operand:SI 5 "gpc_reg_operand" "r"))
9590 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9591 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9592 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9593 "{stsi|stswi} %2,%1,%O0"
9594 [(set_attr "type" "store_ux")])
9595
9596(define_insn "*stmsi3_power"
9597 [(match_parallel 0 "store_multiple_operation"
9598 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9599 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9600 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9601 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9602 (match_operand:SI 4 "gpc_reg_operand" "r"))
9603 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9604 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9605 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9606 "{stsi|stswi} %2,%1,%O0"
9607 [(set_attr "type" "store_ux")])
7e69e155 9608\f
57e84f18 9609(define_expand "setmemsi"
fba73eb1 9610 [(parallel [(set (match_operand:BLK 0 "" "")
98843c92 9611 (match_operand 2 "const_int_operand" ""))
fba73eb1 9612 (use (match_operand:SI 1 "" ""))
57e84f18 9613 (use (match_operand:SI 3 "" ""))])]
fba73eb1
DE		 9614 ""
9615 "
9616{
57e84f18 9617 /* If value to set is not zero, use the library routine. */
a05be2e0 9618 if (operands[2] != const0_rtx)
57e84f18
AS		 9619 FAIL;
9620
fba73eb1
DE		 9621 if (expand_block_clear (operands))
9622 DONE;
9623 else
9624 FAIL;
9625}")
9626
7e69e155
MM		 9627;; String/block move insn.
9628;; Argument 0 is the destination
9629;; Argument 1 is the source
9630;; Argument 2 is the length
9631;; Argument 3 is the alignment
9632
70128ad9 9633(define_expand "movmemsi"
b6c9286a
MM		 9634 [(parallel [(set (match_operand:BLK 0 "" "")
9635 (match_operand:BLK 1 "" ""))
9636 (use (match_operand:SI 2 "" ""))
9637 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9638 ""
9639 "
9640{
9641 if (expand_block_move (operands))
9642 DONE;
9643 else
9644 FAIL;
9645}")
9646
9647;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9648;; register allocator doesn't have a clue about allocating 8 word registers.
9649;; rD/rS = r5 is preferred, efficient form.
70128ad9 9650(define_expand "movmemsi_8reg"
b6c9286a
MM		 9651 [(parallel [(set (match_operand 0 "" "")
9652 (match_operand 1 "" ""))
9653 (use (match_operand 2 "" ""))
9654 (use (match_operand 3 "" ""))
7e69e155
MM		 9655 (clobber (reg:SI 5))
9656 (clobber (reg:SI 6))
9657 (clobber (reg:SI 7))
9658 (clobber (reg:SI 8))
9659 (clobber (reg:SI 9))
9660 (clobber (reg:SI 10))
9661 (clobber (reg:SI 11))
9662 (clobber (reg:SI 12))
3c67b673 9663 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9664 "TARGET_STRING"
9665 "")
9666
9667(define_insn ""
52d3af72
DE		 9668 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9669 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9670 (use (match_operand:SI 2 "immediate_operand" "i"))
9671 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9672 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9673 (clobber (reg:SI 6))
9674 (clobber (reg:SI 7))
9675 (clobber (reg:SI 8))
9676 (clobber (reg:SI 9))
9677 (clobber (reg:SI 10))
9678 (clobber (reg:SI 11))
9679 (clobber (reg:SI 12))
3c67b673 9680 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9681 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9682 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9683 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9684 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9685 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9686 && REGNO (operands[4]) == 5"
9687 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9688 [(set_attr "type" "store_ux")
b7ff3d82 9689 (set_attr "length" "8")])
7e69e155
MM		 9690
9691(define_insn ""
4ae234b0
GK		 9692 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9693 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9694 (use (match_operand:SI 2 "immediate_operand" "i"))
9695 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9696 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9697 (clobber (reg:SI 6))
9698 (clobber (reg:SI 7))
9699 (clobber (reg:SI 8))
9700 (clobber (reg:SI 9))
9701 (clobber (reg:SI 10))
9702 (clobber (reg:SI 11))
9703 (clobber (reg:SI 12))
edd54d25 9704 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9705 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9706 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9707 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9708 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9709 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9710 && REGNO (operands[4]) == 5"
9711 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9712 [(set_attr "type" "store_ux")
b7ff3d82 9713 (set_attr "length" "8")])
7e69e155
MM		 9714
9715;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9716;; register allocator doesn't have a clue about allocating 6 word registers.
9717;; rD/rS = r5 is preferred, efficient form.
70128ad9 9718(define_expand "movmemsi_6reg"
b6c9286a
MM		 9719 [(parallel [(set (match_operand 0 "" "")
9720 (match_operand 1 "" ""))
9721 (use (match_operand 2 "" ""))
9722 (use (match_operand 3 "" ""))
f9562f27
DE		 9723 (clobber (reg:SI 5))
9724 (clobber (reg:SI 6))
7e69e155
MM		 9725 (clobber (reg:SI 7))
9726 (clobber (reg:SI 8))
9727 (clobber (reg:SI 9))
9728 (clobber (reg:SI 10))
3c67b673 9729 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9730 "TARGET_STRING"
9731 "")
9732
9733(define_insn ""
52d3af72
DE		 9734 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9735 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9736 (use (match_operand:SI 2 "immediate_operand" "i"))
9737 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9738 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9739 (clobber (reg:SI 6))
9740 (clobber (reg:SI 7))
7e69e155
MM		 9741 (clobber (reg:SI 8))
9742 (clobber (reg:SI 9))
9743 (clobber (reg:SI 10))
3c67b673 9744 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9745 "TARGET_STRING && TARGET_POWER
9746 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9747 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9748 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9749 && REGNO (operands[4]) == 5"
3c67b673 9750 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9751 [(set_attr "type" "store_ux")
b7ff3d82 9752 (set_attr "length" "8")])
7e69e155
MM		 9753
9754(define_insn ""
4ae234b0
GK		 9755 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9756 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9757 (use (match_operand:SI 2 "immediate_operand" "i"))
9758 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9759 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9760 (clobber (reg:SI 6))
9761 (clobber (reg:SI 7))
7e69e155
MM		 9762 (clobber (reg:SI 8))
9763 (clobber (reg:SI 9))
9764 (clobber (reg:SI 10))
edd54d25 9765 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9766 "TARGET_STRING && ! TARGET_POWER
7e69e155 9767 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9768 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9769 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9770 && REGNO (operands[4]) == 5"
3c67b673 9771 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9772 [(set_attr "type" "store_ux")
b7ff3d82 9773 (set_attr "length" "8")])
7e69e155 9774
f9562f27
DE		 9775;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9776;; problems with TImode.
9777;; rD/rS = r5 is preferred, efficient form.
70128ad9 9778(define_expand "movmemsi_4reg"
b6c9286a
MM		 9779 [(parallel [(set (match_operand 0 "" "")
9780 (match_operand 1 "" ""))
9781 (use (match_operand 2 "" ""))
9782 (use (match_operand 3 "" ""))
f9562f27
DE		 9783 (clobber (reg:SI 5))
9784 (clobber (reg:SI 6))
9785 (clobber (reg:SI 7))
9786 (clobber (reg:SI 8))
3c67b673 9787 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9788 "TARGET_STRING"
9789 "")
9790
9791(define_insn ""
52d3af72
DE		 9792 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9793 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9794 (use (match_operand:SI 2 "immediate_operand" "i"))
9795 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9796 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9797 (clobber (reg:SI 6))
9798 (clobber (reg:SI 7))
9799 (clobber (reg:SI 8))
3c67b673 9800 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9801 "TARGET_STRING && TARGET_POWER
9802 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9803 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9804 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9805 && REGNO (operands[4]) == 5"
3c67b673 9806 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9807 [(set_attr "type" "store_ux")
b7ff3d82 9808 (set_attr "length" "8")])
7e69e155
MM		 9809
9810(define_insn ""
4ae234b0
GK		 9811 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9812 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9813 (use (match_operand:SI 2 "immediate_operand" "i"))
9814 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9815 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9816 (clobber (reg:SI 6))
9817 (clobber (reg:SI 7))
9818 (clobber (reg:SI 8))
edd54d25 9819 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9820 "TARGET_STRING && ! TARGET_POWER
7e69e155 9821 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9822 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9823 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9824 && REGNO (operands[4]) == 5"
3c67b673 9825 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9826 [(set_attr "type" "store_ux")
b7ff3d82 9827 (set_attr "length" "8")])
7e69e155
MM		 9828
9829;; Move up to 8 bytes at a time.
70128ad9 9830(define_expand "movmemsi_2reg"
b6c9286a
MM		 9831 [(parallel [(set (match_operand 0 "" "")
9832 (match_operand 1 "" ""))
9833 (use (match_operand 2 "" ""))
9834 (use (match_operand 3 "" ""))
3c67b673
RK		 9835 (clobber (match_scratch:DI 4 ""))
9836 (clobber (match_scratch:SI 5 ""))])]
f9562f27 9837 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 9838 "")
9839
9840(define_insn ""
52d3af72
DE		 9841 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9842 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9843 (use (match_operand:SI 2 "immediate_operand" "i"))
9844 (use (match_operand:SI 3 "immediate_operand" "i"))
9845 (clobber (match_scratch:DI 4 "=&r"))
9846 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 9847 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 9848 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9849 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9850 [(set_attr "type" "store_ux")
b7ff3d82 9851 (set_attr "length" "8")])
7e69e155
MM		 9852
9853(define_insn ""
52d3af72
DE		 9854 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9855 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9856 (use (match_operand:SI 2 "immediate_operand" "i"))
9857 (use (match_operand:SI 3 "immediate_operand" "i"))
9858 (clobber (match_scratch:DI 4 "=&r"))
edd54d25 9859 (clobber (match_scratch:SI 5 "=X"))]
f9562f27 9860 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 9861 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 9862 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9863 [(set_attr "type" "store_ux")
b7ff3d82 9864 (set_attr "length" "8")])
7e69e155
MM		 9865
9866;; Move up to 4 bytes at a time.
70128ad9 9867(define_expand "movmemsi_1reg"
b6c9286a
MM		 9868 [(parallel [(set (match_operand 0 "" "")
9869 (match_operand 1 "" ""))
9870 (use (match_operand 2 "" ""))
9871 (use (match_operand 3 "" ""))
3c67b673
RK		 9872 (clobber (match_scratch:SI 4 ""))
9873 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 9874 "TARGET_STRING"
9875 "")
9876
9877(define_insn ""
52d3af72
DE		 9878 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9879 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9880 (use (match_operand:SI 2 "immediate_operand" "i"))
9881 (use (match_operand:SI 3 "immediate_operand" "i"))
9882 (clobber (match_scratch:SI 4 "=&r"))
9883 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9884 "TARGET_STRING && TARGET_POWER
9885 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9886 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9887 [(set_attr "type" "store_ux")
b7ff3d82 9888 (set_attr "length" "8")])
7e69e155
MM		 9889
9890(define_insn ""
4ae234b0
GK		 9891 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9892 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9893 (use (match_operand:SI 2 "immediate_operand" "i"))
9894 (use (match_operand:SI 3 "immediate_operand" "i"))
9895 (clobber (match_scratch:SI 4 "=&r"))
edd54d25 9896 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9897 "TARGET_STRING && ! TARGET_POWER
7e69e155 9898 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7 9899 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9900 [(set_attr "type" "store_ux")
09a625f7 9901 (set_attr "length" "8")])
1fd4e8c1 9902\f
7e69e155 9903;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 9904;; get by using pre-decrement or pre-increment, but the hardware can also
9905;; do cases where the increment is not the size of the object.
9906;;
9907;; In all these cases, we use operands 0 and 1 for the register being
9908;; incremented because those are the operands that local-alloc will
9909;; tie and these are the pair most likely to be tieable (and the ones
9910;; that will benefit the most).
9911
38c1f2d7 9912(define_insn "*movdi_update1"
51b8fc2c 9913 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 9914 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9915 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 9916 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9917 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9918 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9919 "@
9920 ldux %3,%0,%2
9921 ldu %3,%2(%0)"
b54cf83a 9922 [(set_attr "type" "load_ux,load_u")])
287f13ff 9923
2e6c9641
FJ		 9924(define_insn "movdi_<mode>_update"
9925 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9926 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c 9927 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
2e6c9641
FJ		 9928 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9929 (plus:P (match_dup 1) (match_dup 2)))]
38c1f2d7 9930 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9931 "@
9932 stdux %3,%0,%2
b7ff3d82 9933 stdu %3,%2(%0)"
b54cf83a 9934 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 9935
38c1f2d7 9936(define_insn "*movsi_update1"
cd2b37d9
RK		 9937 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9938 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9939 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9940 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9941 (plus:SI (match_dup 1) (match_dup 2)))]
f7b3ab8a 9942 "TARGET_UPDATE"
1fd4e8c1 9943 "@
ca7f5001
RK		 9944 {lux|lwzux} %3,%0,%2
9945 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 9946 [(set_attr "type" "load_ux,load_u")])
9947
9948(define_insn "*movsi_update2"
9949 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9950 (sign_extend:DI
9951 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9952 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9953 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9954 (plus:DI (match_dup 1) (match_dup 2)))]
9955 "TARGET_POWERPC64"
9956 "lwaux %3,%0,%2"
9957 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 9958
4697a36c 9959(define_insn "movsi_update"
cd2b37d9 9960 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9961 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9962 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9963 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9964 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9965 "TARGET_UPDATE"
1fd4e8c1 9966 "@
ca7f5001 9967 {stux|stwux} %3,%0,%2
b7ff3d82 9968 {stu|stwu} %3,%2(%0)"
b54cf83a 9969 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9970
b54cf83a 9971(define_insn "*movhi_update1"
cd2b37d9
RK		 9972 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9973 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9974 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9975 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9976 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9977 "TARGET_UPDATE"
1fd4e8c1 9978 "@
5f243543
RK		 9979 lhzux %3,%0,%2
9980 lhzu %3,%2(%0)"
b54cf83a 9981 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9982
38c1f2d7 9983(define_insn "*movhi_update2"
cd2b37d9 9984 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9985 (zero_extend:SI
cd2b37d9 9986 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9987 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9988 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9989 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9990 "TARGET_UPDATE"
1fd4e8c1 9991 "@
5f243543
RK		 9992 lhzux %3,%0,%2
9993 lhzu %3,%2(%0)"
b54cf83a 9994 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9995
38c1f2d7 9996(define_insn "*movhi_update3"
cd2b37d9 9997 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9998 (sign_extend:SI
cd2b37d9 9999 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10000 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10001 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10002 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10003 "TARGET_UPDATE"
1fd4e8c1 10004 "@
5f243543
RK		 10005 lhaux %3,%0,%2
10006 lhau %3,%2(%0)"
b54cf83a 10007 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 10008
38c1f2d7 10009(define_insn "*movhi_update4"
cd2b37d9 10010 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10011 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10012 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10013 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10014 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10015 "TARGET_UPDATE"
1fd4e8c1 10016 "@
5f243543 10017 sthux %3,%0,%2
b7ff3d82 10018 sthu %3,%2(%0)"
b54cf83a 10019 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10020
38c1f2d7 10021(define_insn "*movqi_update1"
cd2b37d9
RK		 10022 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10023 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10024 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10025 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10026 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10027 "TARGET_UPDATE"
1fd4e8c1 10028 "@
5f243543
RK		 10029 lbzux %3,%0,%2
10030 lbzu %3,%2(%0)"
b54cf83a 10031 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10032
38c1f2d7 10033(define_insn "*movqi_update2"
cd2b37d9 10034 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10035 (zero_extend:SI
cd2b37d9 10036 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10037 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10038 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10039 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10040 "TARGET_UPDATE"
1fd4e8c1 10041 "@
5f243543
RK		 10042 lbzux %3,%0,%2
10043 lbzu %3,%2(%0)"
b54cf83a 10044 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10045
38c1f2d7 10046(define_insn "*movqi_update3"
cd2b37d9 10047 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10048 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10049 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10050 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10051 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10052 "TARGET_UPDATE"
1fd4e8c1 10053 "@
5f243543 10054 stbux %3,%0,%2
b7ff3d82 10055 stbu %3,%2(%0)"
b54cf83a 10056 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10057
38c1f2d7 10058(define_insn "*movsf_update1"
cd2b37d9 10059 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 10060 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10061 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10062 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10063 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10064 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10065 "@
5f243543
RK		 10066 lfsux %3,%0,%2
10067 lfsu %3,%2(%0)"
b54cf83a 10068 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10069
38c1f2d7 10070(define_insn "*movsf_update2"
cd2b37d9 10071 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10072 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10073 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10074 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10075 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10076 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10077 "@
85fff2f3 10078 stfsux %3,%0,%2
b7ff3d82 10079 stfsu %3,%2(%0)"
b54cf83a 10080 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 10081
38c1f2d7
MM		 10082(define_insn "*movsf_update3"
10083 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10084 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10085 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10086 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10087 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10088 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10089 "@
10090 {lux|lwzux} %3,%0,%2
10091 {lu|lwzu} %3,%2(%0)"
b54cf83a 10092 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 10093
10094(define_insn "*movsf_update4"
10095 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10096 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10097 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10098 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10099 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10100 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10101 "@
10102 {stux|stwux} %3,%0,%2
10103 {stu|stwu} %3,%2(%0)"
b54cf83a 10104 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 10105
10106(define_insn "*movdf_update1"
cd2b37d9
RK		 10107 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10108 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10109 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10110 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10111 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10112 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10113 "@
5f243543
RK		 10114 lfdux %3,%0,%2
10115 lfdu %3,%2(%0)"
b54cf83a 10116 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10117
38c1f2d7 10118(define_insn "*movdf_update2"
cd2b37d9 10119 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10120 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10121 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10122 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10123 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10124 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10125 "@
5f243543 10126 stfdux %3,%0,%2
b7ff3d82 10127 stfdu %3,%2(%0)"
b54cf83a 10128 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 10129
10130;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10131
90f81f99 10132(define_insn "*lfq_power2"
bb8df8a6
EC		 10133 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10134 (match_operand:V2DF 1 "memory_operand" ""))]
90f81f99
AP		 10135 "TARGET_POWER2
10136 && TARGET_HARD_FLOAT && TARGET_FPRS"
bb8df8a6 10137 "lfq%U1%X1 %0,%1")
90f81f99
AP		 10138
10139(define_peephole2
10140 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4c70a4f3 10141 (match_operand:DF 1 "memory_operand" ""))
90f81f99 10142 (set (match_operand:DF 2 "gpc_reg_operand" "")
4c70a4f3
RK		 10143 (match_operand:DF 3 "memory_operand" ""))]
10144 "TARGET_POWER2
a3170dc6 10145 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10146 && registers_ok_for_quad_peep (operands[0], operands[2])
90f81f99
AP		 10147 && mems_ok_for_quad_peep (operands[1], operands[3])"
10148 [(set (match_dup 0)
bb8df8a6
EC		 10149 (match_dup 1))]
10150 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10151 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
4c70a4f3 10152
90f81f99 10153(define_insn "*stfq_power2"
bb8df8a6
EC		 10154 [(set (match_operand:V2DF 0 "memory_operand" "")
10155 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
90f81f99
AP		 10156 "TARGET_POWER2
10157 && TARGET_HARD_FLOAT && TARGET_FPRS"
10158 "stfq%U0%X0 %1,%0")
10159
10160
10161(define_peephole2
4c70a4f3 10162 [(set (match_operand:DF 0 "memory_operand" "")
90f81f99 10163 (match_operand:DF 1 "gpc_reg_operand" ""))
4c70a4f3 10164 (set (match_operand:DF 2 "memory_operand" "")
90f81f99 10165 (match_operand:DF 3 "gpc_reg_operand" ""))]
4c70a4f3 10166 "TARGET_POWER2
a3170dc6 10167 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10168 && registers_ok_for_quad_peep (operands[1], operands[3])
90f81f99
AP		 10169 && mems_ok_for_quad_peep (operands[0], operands[2])"
10170 [(set (match_dup 0)
10171 (match_dup 1))]
bb8df8a6
EC		 10172 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10173 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
2f4d9502 10174
036aadfc 10175;; After inserting conditional returns we can sometimes have
2f4d9502
NS		 10176;; unnecessary register moves. Unfortunately we cannot have a
10177;; modeless peephole here, because some single SImode sets have early
10178;; clobber outputs. Although those sets expand to multi-ppc-insn
10179;; sequences, using get_attr_length here will smash the operands
10180;; array. Neither is there an early_cobbler_p predicate.
036aadfc 10181;; Disallow subregs for E500 so we don't munge frob_di_df_2.
2f4d9502
NS		 10182(define_peephole2
10183 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10184 (match_operand:DF 1 "any_operand" ""))
10185 (set (match_operand:DF 2 "gpc_reg_operand" "")
10186 (match_dup 0))]
036aadfc
AM		 10187 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10188 && peep2_reg_dead_p (2, operands[0])"
2f4d9502
NS		 10189 [(set (match_dup 2) (match_dup 1))])
10190
10191(define_peephole2
10192 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10193 (match_operand:SF 1 "any_operand" ""))
10194 (set (match_operand:SF 2 "gpc_reg_operand" "")
10195 (match_dup 0))]
10196 "peep2_reg_dead_p (2, operands[0])"
10197 [(set (match_dup 2) (match_dup 1))])
10198
1fd4e8c1 10199\f
c4501e62
JJ		 10200;; TLS support.
10201
10202;; "b" output constraint here and on tls_ld to support tls linker optimization.
10203(define_insn "tls_gd_32"
b150f4f3
DE		 10204 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10205 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10206 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10207 UNSPEC_TLSGD))]
10208 "HAVE_AS_TLS && !TARGET_64BIT"
10209 "addi %0,%1,%2@got@tlsgd")
10210
10211(define_insn "tls_gd_64"
b150f4f3
DE		 10212 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10213 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10214 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10215 UNSPEC_TLSGD))]
10216 "HAVE_AS_TLS && TARGET_64BIT"
10217 "addi %0,%1,%2@got@tlsgd")
10218
10219(define_insn "tls_ld_32"
b150f4f3
DE		 10220 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10221 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 10222 UNSPEC_TLSLD))]
10223 "HAVE_AS_TLS && !TARGET_64BIT"
10224 "addi %0,%1,%&@got@tlsld")
10225
10226(define_insn "tls_ld_64"
b150f4f3
DE		 10227 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10228 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 10229 UNSPEC_TLSLD))]
10230 "HAVE_AS_TLS && TARGET_64BIT"
10231 "addi %0,%1,%&@got@tlsld")
10232
10233(define_insn "tls_dtprel_32"
b150f4f3
DE		 10234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10235 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10236 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10237 UNSPEC_TLSDTPREL))]
10238 "HAVE_AS_TLS && !TARGET_64BIT"
10239 "addi %0,%1,%2@dtprel")
10240
10241(define_insn "tls_dtprel_64"
b150f4f3
DE		 10242 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10243 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10244 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10245 UNSPEC_TLSDTPREL))]
10246 "HAVE_AS_TLS && TARGET_64BIT"
10247 "addi %0,%1,%2@dtprel")
10248
10249(define_insn "tls_dtprel_ha_32"
b150f4f3
DE		 10250 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10251 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10252 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10253 UNSPEC_TLSDTPRELHA))]
10254 "HAVE_AS_TLS && !TARGET_64BIT"
10255 "addis %0,%1,%2@dtprel@ha")
10256
10257(define_insn "tls_dtprel_ha_64"
b150f4f3
DE		 10258 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10259 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10260 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10261 UNSPEC_TLSDTPRELHA))]
10262 "HAVE_AS_TLS && TARGET_64BIT"
10263 "addis %0,%1,%2@dtprel@ha")
10264
10265(define_insn "tls_dtprel_lo_32"
b150f4f3
DE		 10266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10267 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10268 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10269 UNSPEC_TLSDTPRELLO))]
10270 "HAVE_AS_TLS && !TARGET_64BIT"
10271 "addi %0,%1,%2@dtprel@l")
10272
10273(define_insn "tls_dtprel_lo_64"
b150f4f3
DE		 10274 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10275 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10276 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10277 UNSPEC_TLSDTPRELLO))]
10278 "HAVE_AS_TLS && TARGET_64BIT"
10279 "addi %0,%1,%2@dtprel@l")
10280
10281(define_insn "tls_got_dtprel_32"
b150f4f3
DE		 10282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10283 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10284 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10285 UNSPEC_TLSGOTDTPREL))]
10286 "HAVE_AS_TLS && !TARGET_64BIT"
10287 "lwz %0,%2@got@dtprel(%1)")
10288
10289(define_insn "tls_got_dtprel_64"
b150f4f3
DE		 10290 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10291 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10292 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10293 UNSPEC_TLSGOTDTPREL))]
10294 "HAVE_AS_TLS && TARGET_64BIT"
10295 "ld %0,%2@got@dtprel(%1)")
10296
10297(define_insn "tls_tprel_32"
b150f4f3
DE		 10298 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10299 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10300 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10301 UNSPEC_TLSTPREL))]
10302 "HAVE_AS_TLS && !TARGET_64BIT"
10303 "addi %0,%1,%2@tprel")
10304
10305(define_insn "tls_tprel_64"
b150f4f3
DE		 10306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10307 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10308 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10309 UNSPEC_TLSTPREL))]
10310 "HAVE_AS_TLS && TARGET_64BIT"
10311 "addi %0,%1,%2@tprel")
10312
10313(define_insn "tls_tprel_ha_32"
b150f4f3
DE		 10314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10315 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10316 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10317 UNSPEC_TLSTPRELHA))]
10318 "HAVE_AS_TLS && !TARGET_64BIT"
10319 "addis %0,%1,%2@tprel@ha")
10320
10321(define_insn "tls_tprel_ha_64"
b150f4f3
DE		 10322 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10323 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10324 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10325 UNSPEC_TLSTPRELHA))]
10326 "HAVE_AS_TLS && TARGET_64BIT"
10327 "addis %0,%1,%2@tprel@ha")
10328
10329(define_insn "tls_tprel_lo_32"
b150f4f3
DE		 10330 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10331 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10332 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10333 UNSPEC_TLSTPRELLO))]
10334 "HAVE_AS_TLS && !TARGET_64BIT"
10335 "addi %0,%1,%2@tprel@l")
10336
10337(define_insn "tls_tprel_lo_64"
b150f4f3
DE		 10338 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10339 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10340 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10341 UNSPEC_TLSTPRELLO))]
10342 "HAVE_AS_TLS && TARGET_64BIT"
10343 "addi %0,%1,%2@tprel@l")
10344
c1207243 10345;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 10346;; optimization. The linker may edit the instructions emitted by a
10347;; tls_got_tprel/tls_tls pair to addis,addi.
10348(define_insn "tls_got_tprel_32"
b150f4f3
DE		 10349 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10350 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10351 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10352 UNSPEC_TLSGOTTPREL))]
10353 "HAVE_AS_TLS && !TARGET_64BIT"
10354 "lwz %0,%2@got@tprel(%1)")
10355
10356(define_insn "tls_got_tprel_64"
b150f4f3
DE		 10357 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10358 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10359 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10360 UNSPEC_TLSGOTTPREL))]
10361 "HAVE_AS_TLS && TARGET_64BIT"
10362 "ld %0,%2@got@tprel(%1)")
10363
10364(define_insn "tls_tls_32"
b150f4f3
DE		 10365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10366 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10367 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10368 UNSPEC_TLSTLS))]
10369 "HAVE_AS_TLS && !TARGET_64BIT"
10370 "add %0,%1,%2@tls")
10371
10372(define_insn "tls_tls_64"
b150f4f3
DE		 10373 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10374 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10375 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10376 UNSPEC_TLSTLS))]
10377 "HAVE_AS_TLS && TARGET_64BIT"
10378 "add %0,%1,%2@tls")
10379\f
1fd4e8c1
RK		 10380;; Next come insns related to the calling sequence.
10381;;
10382;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 10383;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 10384
10385(define_expand "allocate_stack"
e42ac3de 10386 [(set (match_operand 0 "gpc_reg_operand" "")
a260abc9
DE		 10387 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10388 (set (reg 1)
10389 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 10390 ""
10391 "
4697a36c 10392{ rtx chain = gen_reg_rtx (Pmode);
39403d82 10393 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 10394 rtx neg_op0;
1fd4e8c1
RK		 10395
10396 emit_move_insn (chain, stack_bot);
4697a36c 10397
a157febd 10398 /* Check stack bounds if necessary. */
e3b5732b 10399 if (crtl->limit_stack)
a157febd
GK		 10400 {
10401 rtx available;
6ae08853 10402 available = expand_binop (Pmode, sub_optab,
a157febd
GK		 10403 stack_pointer_rtx, stack_limit_rtx,
10404 NULL_RTX, 1, OPTAB_WIDEN);
10405 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10406 }
10407
e9a25f70
JL		 10408 if (GET_CODE (operands[1]) != CONST_INT
10409 || INTVAL (operands[1]) < -32767
10410 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 10411 {
10412 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 10413 if (TARGET_32BIT)
e9a25f70 10414 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 10415 else
e9a25f70 10416 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 10417 }
10418 else
e9a25f70 10419 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 10420
38c1f2d7 10421 if (TARGET_UPDATE)
2e6c9641 10422 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
38c1f2d7 10423 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
4697a36c 10424
38c1f2d7
MM		 10425 else
10426 {
10427 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10428 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
39403d82 10429 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
38c1f2d7 10430 }
e9a25f70
JL		 10431
10432 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 10433 DONE;
10434}")
59257ff7
RK		 10435
10436;; These patterns say how to save and restore the stack pointer. We need not
10437;; save the stack pointer at function level since we are careful to
10438;; preserve the backchain. At block level, we have to restore the backchain
10439;; when we restore the stack pointer.
10440;;
10441;; For nonlocal gotos, we must save both the stack pointer and its
10442;; backchain and restore both. Note that in the nonlocal case, the
10443;; save area is a memory location.
10444
10445(define_expand "save_stack_function"
ff381587
MM		 10446 [(match_operand 0 "any_operand" "")
10447 (match_operand 1 "any_operand" "")]
59257ff7 10448 ""
ff381587 10449 "DONE;")
59257ff7
RK		 10450
10451(define_expand "restore_stack_function"
ff381587
MM		 10452 [(match_operand 0 "any_operand" "")
10453 (match_operand 1 "any_operand" "")]
59257ff7 10454 ""
ff381587 10455 "DONE;")
59257ff7 10456
2eef28ec
AM		 10457;; Adjust stack pointer (op0) to a new value (op1).
10458;; First copy old stack backchain to new location, and ensure that the
10459;; scheduler won't reorder the sp assignment before the backchain write.
59257ff7 10460(define_expand "restore_stack_block"
2eef28ec
AM		 10461 [(set (match_dup 2) (match_dup 3))
10462 (set (match_dup 4) (match_dup 2))
10463 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10464 (set (match_operand 0 "register_operand" "")
10465 (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10466 ""
10467 "
dfdfa60f 10468{
583da60a 10469 operands[1] = force_reg (Pmode, operands[1]);
dfdfa60f 10470 operands[2] = gen_reg_rtx (Pmode);
2eef28ec
AM		 10471 operands[3] = gen_frame_mem (Pmode, operands[0]);
10472 operands[4] = gen_frame_mem (Pmode, operands[1]);
10473 operands[5] = gen_frame_mem (BLKmode, operands[0]);
dfdfa60f 10474}")
59257ff7
RK		 10475
10476(define_expand "save_stack_nonlocal"
2eef28ec
AM		 10477 [(set (match_dup 3) (match_dup 4))
10478 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10479 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10480 ""
10481 "
10482{
11b25716 10483 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10484
10485 /* Copy the backchain to the first word, sp to the second. */
2eef28ec
AM		 10486 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10487 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10488 operands[3] = gen_reg_rtx (Pmode);
10489 operands[4] = gen_frame_mem (Pmode, operands[1]);
59257ff7 10490}")
7e69e155 10491
59257ff7 10492(define_expand "restore_stack_nonlocal"
2eef28ec
AM		 10493 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10494 (set (match_dup 3) (match_dup 4))
10495 (set (match_dup 5) (match_dup 2))
10496 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10497 (set (match_operand 0 "register_operand" "") (match_dup 3))]
59257ff7
RK		 10498 ""
10499 "
10500{
11b25716 10501 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10502
10503 /* Restore the backchain from the first word, sp from the second. */
2eef28ec
AM		 10504 operands[2] = gen_reg_rtx (Pmode);
10505 operands[3] = gen_reg_rtx (Pmode);
10506 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10507 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10508 operands[5] = gen_frame_mem (Pmode, operands[3]);
10509 operands[6] = gen_frame_mem (BLKmode, operands[0]);
59257ff7 10510}")
9ebbca7d
GK		 10511\f
10512;; TOC register handling.
b6c9286a 10513
9ebbca7d 10514;; Code to initialize the TOC register...
f0f6a223 10515
9ebbca7d 10516(define_insn "load_toc_aix_si"
e72247f4 10517 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 10518 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10519 (use (reg:SI 2))])]
2bfcf297 10520 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 10521 "*
10522{
9ebbca7d
GK		 10523 char buf[30];
10524 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 10525 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10526 operands[2] = gen_rtx_REG (Pmode, 2);
10527 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 10528}"
10529 [(set_attr "type" "load")])
9ebbca7d
GK		 10530
10531(define_insn "load_toc_aix_di"
e72247f4 10532 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 10533 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10534 (use (reg:DI 2))])]
2bfcf297 10535 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 10536 "*
10537{
10538 char buf[30];
f585a356
DE		 10539#ifdef TARGET_RELOCATABLE
10540 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10541 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10542#else
9ebbca7d 10543 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 10544#endif
2bfcf297
DB		 10545 if (TARGET_ELF)
10546 strcat (buf, \"@toc\");
a8a05998 10547 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10548 operands[2] = gen_rtx_REG (Pmode, 2);
10549 return \"ld %0,%1(%2)\";
10550}"
10551 [(set_attr "type" "load")])
10552
10553(define_insn "load_toc_v4_pic_si"
1de43f85 10554 [(set (reg:SI LR_REGNO)
615158e2 10555 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 10556 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 10557 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10558 [(set_attr "type" "branch")
10559 (set_attr "length" "4")])
10560
9ebbca7d 10561(define_insn "load_toc_v4_PIC_1"
1de43f85 10562 [(set (reg:SI LR_REGNO)
e65a3857
DE		 10563 (match_operand:SI 0 "immediate_operand" "s"))
10564 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
7f970b70
AM		 10565 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10566 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
e65a3857 10567 "bcl 20,31,%0\\n%0:"
9ebbca7d
GK		 10568 [(set_attr "type" "branch")
10569 (set_attr "length" "4")])
10570
10571(define_insn "load_toc_v4_PIC_1b"
1de43f85 10572 [(set (reg:SI LR_REGNO)
e65a3857 10573 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
c4501e62 10574 UNSPEC_TOCPTR))]
20b71b17 10575 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
e65a3857 10576 "bcl 20,31,$+8\\n\\t.long %0-$"
9ebbca7d
GK		 10577 [(set_attr "type" "branch")
10578 (set_attr "length" "8")])
10579
10580(define_insn "load_toc_v4_PIC_2"
f585a356 10581 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 10582 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 10583 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10584 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 10585 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 10586 "{l|lwz} %0,%2-%3(%1)"
10587 [(set_attr "type" "load")])
10588
7f970b70
AM		 10589(define_insn "load_toc_v4_PIC_3b"
10590 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10591 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10592 (high:SI
10593 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10594 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10595 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10596 "{cau|addis} %0,%1,%2-%3@ha")
10597
10598(define_insn "load_toc_v4_PIC_3c"
10599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10600 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10601 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10602 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10603 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10604 "{cal|addi} %0,%1,%2-%3@l")
f51eee6a 10605
9ebbca7d
GK		 10606;; If the TOC is shared over a translation unit, as happens with all
10607;; the kinds of PIC that we support, we need to restore the TOC
10608;; pointer only when jumping over units of translation.
f51eee6a 10609;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 10610
10611(define_expand "builtin_setjmp_receiver"
10612 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 10613 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 10614 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10615 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 10616 "
10617{
84d7dd4a 10618#if TARGET_MACHO
f51eee6a
GK		 10619 if (DEFAULT_ABI == ABI_DARWIN)
10620 {
d24652ee 10621 const char *picbase = machopic_function_base_name ();
485bad26 10622 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
f51eee6a
GK		 10623 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10624 rtx tmplabrtx;
10625 char tmplab[20];
10626
10627 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10628 CODE_LABEL_NUMBER (operands[0]));
485bad26 10629 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a 10630
316fbf19 10631 emit_insn (gen_load_macho_picbase (tmplabrtx));
1de43f85 10632 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
b8a55285 10633 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
f51eee6a
GK		 10634 }
10635 else
84d7dd4a 10636#endif
f51eee6a 10637 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 10638 DONE;
10639}")
7f970b70
AM		 10640
10641;; Elf specific ways of loading addresses for non-PIC code.
10642;; The output of this could be r0, but we make a very strong
10643;; preference for a base register because it will usually
10644;; be needed there.
10645(define_insn "elf_high"
10646 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10647 (high:SI (match_operand 1 "" "")))]
10648 "TARGET_ELF && ! TARGET_64BIT"
10649 "{liu|lis} %0,%1@ha")
10650
10651(define_insn "elf_low"
10652 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10653 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10654 (match_operand 2 "" "")))]
10655 "TARGET_ELF && ! TARGET_64BIT"
10656 "@
10657 {cal|la} %0,%2@l(%1)
10658 {ai|addic} %0,%1,%K2")
9ebbca7d
GK		 10659\f
10660;; A function pointer under AIX is a pointer to a data area whose first word
10661;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 10662;; pointer to its TOC, and whose third word contains a value to place in the
10663;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 10664;; "trampoline" need not have any executable code.
b6c9286a 10665
cccf3bdc
DE		 10666(define_expand "call_indirect_aix32"
10667 [(set (match_dup 2)
10668 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10669 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10670 (reg:SI 2))
10671 (set (reg:SI 2)
10672 (mem:SI (plus:SI (match_dup 0)
10673 (const_int 4))))
10674 (set (reg:SI 11)
10675 (mem:SI (plus:SI (match_dup 0)
10676 (const_int 8))))
10677 (parallel [(call (mem:SI (match_dup 2))
10678 (match_operand 1 "" ""))
10679 (use (reg:SI 2))
10680 (use (reg:SI 11))
10681 (set (reg:SI 2)
10682 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10683 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10684 "TARGET_32BIT"
10685 "
10686{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 10687
cccf3bdc
DE		 10688(define_expand "call_indirect_aix64"
10689 [(set (match_dup 2)
10690 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10691 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10692 (reg:DI 2))
10693 (set (reg:DI 2)
10694 (mem:DI (plus:DI (match_dup 0)
10695 (const_int 8))))
10696 (set (reg:DI 11)
10697 (mem:DI (plus:DI (match_dup 0)
10698 (const_int 16))))
10699 (parallel [(call (mem:SI (match_dup 2))
10700 (match_operand 1 "" ""))
10701 (use (reg:DI 2))
10702 (use (reg:DI 11))
10703 (set (reg:DI 2)
10704 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10705 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10706 "TARGET_64BIT"
10707 "
10708{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 10709
cccf3bdc
DE		 10710(define_expand "call_value_indirect_aix32"
10711 [(set (match_dup 3)
10712 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10713 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10714 (reg:SI 2))
10715 (set (reg:SI 2)
10716 (mem:SI (plus:SI (match_dup 1)
10717 (const_int 4))))
10718 (set (reg:SI 11)
10719 (mem:SI (plus:SI (match_dup 1)
10720 (const_int 8))))
10721 (parallel [(set (match_operand 0 "" "")
10722 (call (mem:SI (match_dup 3))
10723 (match_operand 2 "" "")))
10724 (use (reg:SI 2))
10725 (use (reg:SI 11))
10726 (set (reg:SI 2)
10727 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10728 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10729 "TARGET_32BIT"
10730 "
10731{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 10732
cccf3bdc
DE		 10733(define_expand "call_value_indirect_aix64"
10734 [(set (match_dup 3)
10735 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10736 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10737 (reg:DI 2))
10738 (set (reg:DI 2)
10739 (mem:DI (plus:DI (match_dup 1)
10740 (const_int 8))))
10741 (set (reg:DI 11)
10742 (mem:DI (plus:DI (match_dup 1)
10743 (const_int 16))))
10744 (parallel [(set (match_operand 0 "" "")
10745 (call (mem:SI (match_dup 3))
10746 (match_operand 2 "" "")))
10747 (use (reg:DI 2))
10748 (use (reg:DI 11))
10749 (set (reg:DI 2)
10750 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10751 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10752 "TARGET_64BIT"
10753 "
10754{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 10755
b6c9286a 10756;; Now the definitions for the call and call_value insns
1fd4e8c1 10757(define_expand "call"
a260abc9 10758 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 10759 (match_operand 1 "" ""))
4697a36c 10760 (use (match_operand 2 "" ""))
1de43f85 10761 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 10762 ""
10763 "
10764{
ee890fe2 10765#if TARGET_MACHO
ab82a49f 10766 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10767 operands[0] = machopic_indirect_call_target (operands[0]);
10768#endif
10769
37409796
NS		 10770 gcc_assert (GET_CODE (operands[0]) == MEM);
10771 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
1fd4e8c1
RK		 10772
10773 operands[0] = XEXP (operands[0], 0);
7509c759 10774
7f970b70
AM		 10775 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10776 && flag_pic
10777 && GET_CODE (operands[0]) == SYMBOL_REF
10778 && !SYMBOL_REF_LOCAL_P (operands[0]))
10779 {
10780 rtx call;
10781 rtvec tmp;
10782
10783 tmp = gen_rtvec (3,
10784 gen_rtx_CALL (VOIDmode,
10785 gen_rtx_MEM (SImode, operands[0]),
10786 operands[1]),
10787 gen_rtx_USE (VOIDmode, operands[2]),
ee05ef56 10788 gen_rtx_CLOBBER (VOIDmode,
1de43f85 10789 gen_rtx_REG (Pmode, LR_REGNO)));
7f970b70
AM		 10790 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10791 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10792 DONE;
10793 }
10794
6a4cee5f 10795 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 10796 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
efdba735 10797 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
1fd4e8c1 10798 {
6a4cee5f
MM		 10799 if (INTVAL (operands[2]) & CALL_LONG)
10800 operands[0] = rs6000_longcall_ref (operands[0]);
10801
37409796
NS		 10802 switch (DEFAULT_ABI)
10803 {
10804 case ABI_V4:
10805 case ABI_DARWIN:
10806 operands[0] = force_reg (Pmode, operands[0]);
10807 break;
1fd4e8c1 10808
37409796 10809 case ABI_AIX:
cccf3bdc
DE		 10810 /* AIX function pointers are really pointers to a three word
10811 area. */
10812 emit_call_insn (TARGET_32BIT
10813 ? gen_call_indirect_aix32 (force_reg (SImode,
10814 operands[0]),
10815 operands[1])
10816 : gen_call_indirect_aix64 (force_reg (DImode,
10817 operands[0]),
10818 operands[1]));
10819 DONE;
37409796
NS		 10820
10821 default:
10822 gcc_unreachable ();
b6c9286a 10823 }
1fd4e8c1
RK		 10824 }
10825}")
10826
10827(define_expand "call_value"
10828 [(parallel [(set (match_operand 0 "" "")
a260abc9 10829 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 10830 (match_operand 2 "" "")))
4697a36c 10831 (use (match_operand 3 "" ""))
1de43f85 10832 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 10833 ""
10834 "
10835{
ee890fe2 10836#if TARGET_MACHO
ab82a49f 10837 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10838 operands[1] = machopic_indirect_call_target (operands[1]);
10839#endif
10840
37409796
NS		 10841 gcc_assert (GET_CODE (operands[1]) == MEM);
10842 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
1fd4e8c1
RK		 10843
10844 operands[1] = XEXP (operands[1], 0);
7509c759 10845
7f970b70
AM		 10846 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10847 && flag_pic
10848 && GET_CODE (operands[1]) == SYMBOL_REF
10849 && !SYMBOL_REF_LOCAL_P (operands[1]))
10850 {
10851 rtx call;
10852 rtvec tmp;
10853
10854 tmp = gen_rtvec (3,
10855 gen_rtx_SET (VOIDmode,
10856 operands[0],
10857 gen_rtx_CALL (VOIDmode,
10858 gen_rtx_MEM (SImode,
10859 operands[1]),
10860 operands[2])),
10861 gen_rtx_USE (VOIDmode, operands[3]),
ee05ef56 10862 gen_rtx_CLOBBER (VOIDmode,
1de43f85 10863 gen_rtx_REG (Pmode, LR_REGNO)));
7f970b70
AM		 10864 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10865 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10866 DONE;
10867 }
10868
6a4cee5f 10869 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 10870 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
efdba735 10871 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
1fd4e8c1 10872 {
6756293c 10873 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 10874 operands[1] = rs6000_longcall_ref (operands[1]);
10875
37409796
NS		 10876 switch (DEFAULT_ABI)
10877 {
10878 case ABI_V4:
10879 case ABI_DARWIN:
10880 operands[1] = force_reg (Pmode, operands[1]);
10881 break;
1fd4e8c1 10882
37409796 10883 case ABI_AIX:
cccf3bdc
DE		 10884 /* AIX function pointers are really pointers to a three word
10885 area. */
10886 emit_call_insn (TARGET_32BIT
10887 ? gen_call_value_indirect_aix32 (operands[0],
10888 force_reg (SImode,
10889 operands[1]),
10890 operands[2])
10891 : gen_call_value_indirect_aix64 (operands[0],
10892 force_reg (DImode,
10893 operands[1]),
10894 operands[2]));
10895 DONE;
37409796
NS		 10896
10897 default:
10898 gcc_unreachable ();
b6c9286a 10899 }
1fd4e8c1
RK		 10900 }
10901}")
10902
04780ee7 10903;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 10904;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10905;; either the function was not prototyped, or it was prototyped as a
10906;; variable argument function. It is > 0 if FP registers were passed
10907;; and < 0 if they were not.
04780ee7 10908
a260abc9 10909(define_insn "*call_local32"
4697a36c
MM		 10910 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10911 (match_operand 1 "" "g,g"))
10912 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 10913 (clobber (reg:SI LR_REGNO))]
5a19791c 10914 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 10915 "*
10916{
6a4cee5f
MM		 10917 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10918 output_asm_insn (\"crxor 6,6,6\", operands);
10919
10920 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10921 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 10922
a226df46 10923 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 10924}"
b7ff3d82
DE		 10925 [(set_attr "type" "branch")
10926 (set_attr "length" "4,8")])
04780ee7 10927
a260abc9
DE		 10928(define_insn "*call_local64"
10929 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10930 (match_operand 1 "" "g,g"))
10931 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 10932 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10933 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10934 "*
10935{
10936 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10937 output_asm_insn (\"crxor 6,6,6\", operands);
10938
10939 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10940 output_asm_insn (\"creqv 6,6,6\", operands);
10941
10942 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10943}"
10944 [(set_attr "type" "branch")
10945 (set_attr "length" "4,8")])
10946
cccf3bdc 10947(define_insn "*call_value_local32"
d18dba68 10948 [(set (match_operand 0 "" "")
a260abc9
DE		 10949 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10950 (match_operand 2 "" "g,g")))
10951 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 10952 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10953 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10954 "*
10955{
10956 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10957 output_asm_insn (\"crxor 6,6,6\", operands);
10958
10959 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10960 output_asm_insn (\"creqv 6,6,6\", operands);
10961
10962 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10963}"
10964 [(set_attr "type" "branch")
10965 (set_attr "length" "4,8")])
10966
10967
cccf3bdc 10968(define_insn "*call_value_local64"
d18dba68 10969 [(set (match_operand 0 "" "")
a260abc9
DE		 10970 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10971 (match_operand 2 "" "g,g")))
10972 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 10973 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10974 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10975 "*
10976{
10977 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10978 output_asm_insn (\"crxor 6,6,6\", operands);
10979
10980 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10981 output_asm_insn (\"creqv 6,6,6\", operands);
10982
10983 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10984}"
10985 [(set_attr "type" "branch")
10986 (set_attr "length" "4,8")])
10987
04780ee7 10988;; Call to function which may be in another module. Restore the TOC
911f679c 10989;; pointer (r2) after the call unless this is System V.
a0ab749a 10990;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10991;; either the function was not prototyped, or it was prototyped as a
10992;; variable argument function. It is > 0 if FP registers were passed
10993;; and < 0 if they were not.
04780ee7 10994
cccf3bdc 10995(define_insn "*call_indirect_nonlocal_aix32"
70ae0191
DE		 10996 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10997 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 10998 (use (reg:SI 2))
10999 (use (reg:SI 11))
11000 (set (reg:SI 2)
11001 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11002 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11003 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11004 "b%T0l\;{l|lwz} 2,20(1)"
11005 [(set_attr "type" "jmpreg")
11006 (set_attr "length" "8")])
11007
a260abc9 11008(define_insn "*call_nonlocal_aix32"
cc4d5fec 11009 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11010 (match_operand 1 "" "g"))
11011 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11012 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11013 "TARGET_32BIT
11014 && DEFAULT_ABI == ABI_AIX
5a19791c 11015 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 11016 "bl %z0\;%."
b7ff3d82 11017 [(set_attr "type" "branch")
cccf3bdc
DE		 11018 (set_attr "length" "8")])
11019
11020(define_insn "*call_indirect_nonlocal_aix64"
70ae0191
DE		 11021 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11022 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 11023 (use (reg:DI 2))
11024 (use (reg:DI 11))
11025 (set (reg:DI 2)
11026 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11027 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11028 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11029 "b%T0l\;ld 2,40(1)"
11030 [(set_attr "type" "jmpreg")
11031 (set_attr "length" "8")])
59313e4e 11032
a260abc9 11033(define_insn "*call_nonlocal_aix64"
cc4d5fec 11034 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11035 (match_operand 1 "" "g"))
11036 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11037 (clobber (reg:SI LR_REGNO))]
6ae08853 11038 "TARGET_64BIT
9ebbca7d 11039 && DEFAULT_ABI == ABI_AIX
a260abc9 11040 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 11041 "bl %z0\;%."
a260abc9 11042 [(set_attr "type" "branch")
cccf3bdc 11043 (set_attr "length" "8")])
7509c759 11044
cccf3bdc 11045(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 11046 [(set (match_operand 0 "" "")
70ae0191
DE		 11047 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11048 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11049 (use (reg:SI 2))
11050 (use (reg:SI 11))
11051 (set (reg:SI 2)
11052 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11053 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11054 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11055 "b%T1l\;{l|lwz} 2,20(1)"
11056 [(set_attr "type" "jmpreg")
11057 (set_attr "length" "8")])
1fd4e8c1 11058
cccf3bdc 11059(define_insn "*call_value_nonlocal_aix32"
d18dba68 11060 [(set (match_operand 0 "" "")
cc4d5fec 11061 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11062 (match_operand 2 "" "g")))
11063 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11064 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11065 "TARGET_32BIT
11066 && DEFAULT_ABI == ABI_AIX
a260abc9 11067 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 11068 "bl %z1\;%."
b7ff3d82 11069 [(set_attr "type" "branch")
cccf3bdc 11070 (set_attr "length" "8")])
04780ee7 11071
cccf3bdc 11072(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 11073 [(set (match_operand 0 "" "")
70ae0191
DE		 11074 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11075 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11076 (use (reg:DI 2))
11077 (use (reg:DI 11))
11078 (set (reg:DI 2)
11079 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11080 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11081 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11082 "b%T1l\;ld 2,40(1)"
11083 [(set_attr "type" "jmpreg")
11084 (set_attr "length" "8")])
11085
11086(define_insn "*call_value_nonlocal_aix64"
d18dba68 11087 [(set (match_operand 0 "" "")
cc4d5fec 11088 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11089 (match_operand 2 "" "g")))
11090 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11091 (clobber (reg:SI LR_REGNO))]
6ae08853 11092 "TARGET_64BIT
9ebbca7d 11093 && DEFAULT_ABI == ABI_AIX
5a19791c 11094 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 11095 "bl %z1\;%."
11096 [(set_attr "type" "branch")
11097 (set_attr "length" "8")])
11098
11099;; A function pointer under System V is just a normal pointer
11100;; operands[0] is the function pointer
11101;; operands[1] is the stack size to clean up
11102;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11103;; which indicates how to set cr1
11104
9613eaff
SH		 11105(define_insn "*call_indirect_nonlocal_sysv<mode>"
11106 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11107 (match_operand 1 "" "g,g,g,g"))
11108 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
1de43f85 11109 (clobber (reg:SI LR_REGNO))]
50d440bc 11110 "DEFAULT_ABI == ABI_V4
f607bc57 11111 || DEFAULT_ABI == ABI_DARWIN"
911f679c 11112{
cccf3bdc 11113 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11114 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 11115
cccf3bdc 11116 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11117 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11118
a5c76ee6
ZW		 11119 return "b%T0l";
11120}
6d0a8091
DJ		 11121 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11122 (set_attr "length" "4,4,8,8")])
cccf3bdc 11123
9613eaff
SH		 11124(define_insn "*call_nonlocal_sysv<mode>"
11125 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11126 (match_operand 1 "" "g,g"))
11127 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11128 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11129 "(DEFAULT_ABI == ABI_DARWIN
11130 || (DEFAULT_ABI == ABI_V4
11131 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11132{
11133 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11134 output_asm_insn ("crxor 6,6,6", operands);
11135
11136 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11137 output_asm_insn ("creqv 6,6,6", operands);
11138
c989f2f7 11139#if TARGET_MACHO
efdba735
SH		 11140 return output_call(insn, operands, 0, 2);
11141#else
7f970b70
AM		 11142 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11143 {
11144 if (TARGET_SECURE_PLT && flag_pic == 2)
11145 /* The magic 32768 offset here and in the other sysv call insns
11146 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11147 See sysv4.h:toc_section. */
11148 return "bl %z0+32768@plt";
11149 else
11150 return "bl %z0@plt";
11151 }
11152 else
11153 return "bl %z0";
6ae08853 11154#endif
a5c76ee6
ZW		 11155}
11156 [(set_attr "type" "branch,branch")
11157 (set_attr "length" "4,8")])
11158
9613eaff 11159(define_insn "*call_value_indirect_nonlocal_sysv<mode>"
d18dba68 11160 [(set (match_operand 0 "" "")
9613eaff 11161 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11162 (match_operand 2 "" "g,g,g,g")))
11163 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
1de43f85 11164 (clobber (reg:SI LR_REGNO))]
50d440bc 11165 "DEFAULT_ABI == ABI_V4
f607bc57 11166 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 11167{
6a4cee5f 11168 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11169 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 11170
11171 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11172 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11173
a5c76ee6
ZW		 11174 return "b%T1l";
11175}
6d0a8091
DJ		 11176 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11177 (set_attr "length" "4,4,8,8")])
a5c76ee6 11178
9613eaff 11179(define_insn "*call_value_nonlocal_sysv<mode>"
a5c76ee6 11180 [(set (match_operand 0 "" "")
9613eaff 11181 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11182 (match_operand 2 "" "g,g")))
11183 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11184 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11185 "(DEFAULT_ABI == ABI_DARWIN
11186 || (DEFAULT_ABI == ABI_V4
11187 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11188{
11189 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11190 output_asm_insn ("crxor 6,6,6", operands);
11191
11192 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11193 output_asm_insn ("creqv 6,6,6", operands);
11194
c989f2f7 11195#if TARGET_MACHO
efdba735
SH		 11196 return output_call(insn, operands, 1, 3);
11197#else
7f970b70
AM		 11198 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11199 {
11200 if (TARGET_SECURE_PLT && flag_pic == 2)
11201 return "bl %z1+32768@plt";
11202 else
11203 return "bl %z1@plt";
11204 }
11205 else
11206 return "bl %z1";
6ae08853 11207#endif
a5c76ee6
ZW		 11208}
11209 [(set_attr "type" "branch,branch")
11210 (set_attr "length" "4,8")])
e6f948e3
RK		 11211
11212;; Call subroutine returning any type.
e6f948e3
RK		 11213(define_expand "untyped_call"
11214 [(parallel [(call (match_operand 0 "" "")
11215 (const_int 0))
11216 (match_operand 1 "" "")
11217 (match_operand 2 "" "")])]
11218 ""
11219 "
11220{
11221 int i;
11222
7d70b8b2 11223 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 11224
11225 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11226 {
11227 rtx set = XVECEXP (operands[2], 0, i);
11228 emit_move_insn (SET_DEST (set), SET_SRC (set));
11229 }
11230
11231 /* The optimizer does not know that the call sets the function value
11232 registers we stored in the result block. We avoid problems by
11233 claiming that all hard registers are used and clobbered at this
11234 point. */
11235 emit_insn (gen_blockage ());
11236
11237 DONE;
11238}")
11239
5e1bf043
DJ		 11240;; sibling call patterns
11241(define_expand "sibcall"
11242 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11243 (match_operand 1 "" ""))
11244 (use (match_operand 2 "" ""))
1de43f85 11245 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11246 (return)])]
11247 ""
11248 "
11249{
11250#if TARGET_MACHO
ab82a49f 11251 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11252 operands[0] = machopic_indirect_call_target (operands[0]);
11253#endif
11254
37409796
NS		 11255 gcc_assert (GET_CODE (operands[0]) == MEM);
11256 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5e1bf043
DJ		 11257
11258 operands[0] = XEXP (operands[0], 0);
5e1bf043
DJ		 11259}")
11260
11261;; this and similar patterns must be marked as using LR, otherwise
11262;; dataflow will try to delete the store into it. This is true
11263;; even when the actual reg to jump to is in CTR, when LR was
11264;; saved and restored around the PIC-setting BCL.
11265(define_insn "*sibcall_local32"
11266 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11267 (match_operand 1 "" "g,g"))
11268 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11269 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11270 (return)]
11271 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11272 "*
11273{
11274 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11275 output_asm_insn (\"crxor 6,6,6\", operands);
11276
11277 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11278 output_asm_insn (\"creqv 6,6,6\", operands);
11279
11280 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11281}"
11282 [(set_attr "type" "branch")
11283 (set_attr "length" "4,8")])
11284
11285(define_insn "*sibcall_local64"
11286 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11287 (match_operand 1 "" "g,g"))
11288 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11289 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11290 (return)]
11291 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11292 "*
11293{
11294 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11295 output_asm_insn (\"crxor 6,6,6\", operands);
11296
11297 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11298 output_asm_insn (\"creqv 6,6,6\", operands);
11299
11300 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11301}"
11302 [(set_attr "type" "branch")
11303 (set_attr "length" "4,8")])
11304
11305(define_insn "*sibcall_value_local32"
11306 [(set (match_operand 0 "" "")
11307 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11308 (match_operand 2 "" "g,g")))
11309 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11310 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11311 (return)]
11312 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11313 "*
11314{
11315 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11316 output_asm_insn (\"crxor 6,6,6\", operands);
11317
11318 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11319 output_asm_insn (\"creqv 6,6,6\", operands);
11320
11321 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11322}"
11323 [(set_attr "type" "branch")
11324 (set_attr "length" "4,8")])
11325
11326
11327(define_insn "*sibcall_value_local64"
11328 [(set (match_operand 0 "" "")
11329 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11330 (match_operand 2 "" "g,g")))
11331 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11332 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11333 (return)]
11334 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11335 "*
11336{
11337 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11338 output_asm_insn (\"crxor 6,6,6\", operands);
11339
11340 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11341 output_asm_insn (\"creqv 6,6,6\", operands);
11342
11343 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11344}"
11345 [(set_attr "type" "branch")
11346 (set_attr "length" "4,8")])
11347
11348(define_insn "*sibcall_nonlocal_aix32"
11349 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11350 (match_operand 1 "" "g"))
11351 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11352 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11353 (return)]
11354 "TARGET_32BIT
11355 && DEFAULT_ABI == ABI_AIX
11356 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11357 "b %z0"
11358 [(set_attr "type" "branch")
11359 (set_attr "length" "4")])
11360
11361(define_insn "*sibcall_nonlocal_aix64"
11362 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11363 (match_operand 1 "" "g"))
11364 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11365 (use (reg:SI LR_REGNO))
5e1bf043 11366 (return)]
6ae08853 11367 "TARGET_64BIT
5e1bf043
DJ		 11368 && DEFAULT_ABI == ABI_AIX
11369 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11370 "b %z0"
11371 [(set_attr "type" "branch")
11372 (set_attr "length" "4")])
11373
11374(define_insn "*sibcall_value_nonlocal_aix32"
11375 [(set (match_operand 0 "" "")
11376 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11377 (match_operand 2 "" "g")))
11378 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11379 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11380 (return)]
11381 "TARGET_32BIT
11382 && DEFAULT_ABI == ABI_AIX
11383 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11384 "b %z1"
11385 [(set_attr "type" "branch")
11386 (set_attr "length" "4")])
11387
11388(define_insn "*sibcall_value_nonlocal_aix64"
11389 [(set (match_operand 0 "" "")
11390 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11391 (match_operand 2 "" "g")))
11392 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11393 (use (reg:SI LR_REGNO))
5e1bf043 11394 (return)]
6ae08853 11395 "TARGET_64BIT
5e1bf043
DJ		 11396 && DEFAULT_ABI == ABI_AIX
11397 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11398 "b %z1"
11399 [(set_attr "type" "branch")
11400 (set_attr "length" "4")])
11401
9613eaff
SH		 11402(define_insn "*sibcall_nonlocal_sysv<mode>"
11403 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11404 (match_operand 1 "" ""))
11405 (use (match_operand 2 "immediate_operand" "O,n"))
1de43f85 11406 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11407 (return)]
11408 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11409 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11410 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11411 "*
11412{
11413 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11414 output_asm_insn (\"crxor 6,6,6\", operands);
11415
11416 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11417 output_asm_insn (\"creqv 6,6,6\", operands);
11418
7f970b70
AM		 11419 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11420 {
11421 if (TARGET_SECURE_PLT && flag_pic == 2)
11422 return \"b %z0+32768@plt\";
11423 else
11424 return \"b %z0@plt\";
11425 }
11426 else
11427 return \"b %z0\";
5e1bf043
DJ		 11428}"
11429 [(set_attr "type" "branch,branch")
11430 (set_attr "length" "4,8")])
11431
11432(define_expand "sibcall_value"
11433 [(parallel [(set (match_operand 0 "register_operand" "")
11434 (call (mem:SI (match_operand 1 "address_operand" ""))
11435 (match_operand 2 "" "")))
11436 (use (match_operand 3 "" ""))
1de43f85 11437 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11438 (return)])]
11439 ""
11440 "
11441{
11442#if TARGET_MACHO
ab82a49f 11443 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11444 operands[1] = machopic_indirect_call_target (operands[1]);
11445#endif
11446
37409796
NS		 11447 gcc_assert (GET_CODE (operands[1]) == MEM);
11448 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5e1bf043
DJ		 11449
11450 operands[1] = XEXP (operands[1], 0);
5e1bf043
DJ		 11451}")
11452
9613eaff 11453(define_insn "*sibcall_value_nonlocal_sysv<mode>"
5e1bf043 11454 [(set (match_operand 0 "" "")
9613eaff 11455 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11456 (match_operand 2 "" "")))
11457 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11458 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11459 (return)]
11460 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11461 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11462 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11463 "*
11464{
11465 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11466 output_asm_insn (\"crxor 6,6,6\", operands);
11467
11468 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11469 output_asm_insn (\"creqv 6,6,6\", operands);
11470
7f970b70
AM		 11471 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11472 {
11473 if (TARGET_SECURE_PLT && flag_pic == 2)
11474 return \"b %z1+32768@plt\";
11475 else
11476 return \"b %z1@plt\";
11477 }
11478 else
11479 return \"b %z1\";
5e1bf043
DJ		 11480}"
11481 [(set_attr "type" "branch,branch")
11482 (set_attr "length" "4,8")])
11483
11484(define_expand "sibcall_epilogue"
11485 [(use (const_int 0))]
11486 "TARGET_SCHED_PROLOG"
11487 "
11488{
11489 rs6000_emit_epilogue (TRUE);
11490 DONE;
11491}")
11492
e6f948e3
RK		 11493;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11494;; all of memory. This blocks insns from being moved across this point.
11495
11496(define_insn "blockage"
615158e2 11497 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 11498 ""
11499 "")
1fd4e8c1
RK		 11500\f
11501;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 11502;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 11503;;
11504;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11505;; insns, and branches. We store the operands of compares until we see
11506;; how it is used.
4ae234b0 11507(define_expand "cmp<mode>"
1fd4e8c1 11508 [(set (cc0)
4ae234b0
GK		 11509 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11510 (match_operand:GPR 1 "reg_or_short_operand" "")))]
1fd4e8c1
RK		 11511 ""
11512 "
11513{
11514 /* Take care of the possibility that operands[1] might be negative but
11515 this might be a logical operation. That insn doesn't exist. */
11516 if (GET_CODE (operands[1]) == CONST_INT
11517 && INTVAL (operands[1]) < 0)
4ae234b0 11518 operands[1] = force_reg (<MODE>mode, operands[1]);
1fd4e8c1
RK		 11519
11520 rs6000_compare_op0 = operands[0];
11521 rs6000_compare_op1 = operands[1];
11522 rs6000_compare_fp_p = 0;
11523 DONE;
11524}")
11525
4ae234b0
GK		 11526(define_expand "cmp<mode>"
11527 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11528 (match_operand:FP 1 "gpc_reg_operand" "")))]
11529 ""
d6f99ca4
DE		 11530 "
11531{
11532 rs6000_compare_op0 = operands[0];
11533 rs6000_compare_op1 = operands[1];
11534 rs6000_compare_fp_p = 1;
11535 DONE;
11536}")
11537
1fd4e8c1 11538(define_expand "beq"
39a10a29 11539 [(use (match_operand 0 "" ""))]
1fd4e8c1 11540 ""
39a10a29 11541 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11542
11543(define_expand "bne"
39a10a29 11544 [(use (match_operand 0 "" ""))]
1fd4e8c1 11545 ""
39a10a29 11546 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
1fd4e8c1 11547
39a10a29
GK		 11548(define_expand "bge"
11549 [(use (match_operand 0 "" ""))]
1fd4e8c1 11550 ""
39a10a29 11551 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
1fd4e8c1
RK		 11552
11553(define_expand "bgt"
39a10a29 11554 [(use (match_operand 0 "" ""))]
1fd4e8c1 11555 ""
39a10a29 11556 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
1fd4e8c1
RK		 11557
11558(define_expand "ble"
39a10a29 11559 [(use (match_operand 0 "" ""))]
1fd4e8c1 11560 ""
39a10a29 11561 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
1fd4e8c1 11562
39a10a29
GK		 11563(define_expand "blt"
11564 [(use (match_operand 0 "" ""))]
1fd4e8c1 11565 ""
39a10a29 11566 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
1fd4e8c1 11567
39a10a29
GK		 11568(define_expand "bgeu"
11569 [(use (match_operand 0 "" ""))]
1fd4e8c1 11570 ""
39a10a29 11571 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
1fd4e8c1 11572
39a10a29
GK		 11573(define_expand "bgtu"
11574 [(use (match_operand 0 "" ""))]
1fd4e8c1 11575 ""
39a10a29 11576 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
1fd4e8c1 11577
39a10a29
GK		 11578(define_expand "bleu"
11579 [(use (match_operand 0 "" ""))]
1fd4e8c1 11580 ""
39a10a29 11581 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
1fd4e8c1 11582
39a10a29
GK		 11583(define_expand "bltu"
11584 [(use (match_operand 0 "" ""))]
1fd4e8c1 11585 ""
39a10a29 11586 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
1fd4e8c1 11587
1c882ea4 11588(define_expand "bunordered"
39a10a29 11589 [(use (match_operand 0 "" ""))]
8ef65e3d 11590 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11591 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11592
11593(define_expand "bordered"
39a10a29 11594 [(use (match_operand 0 "" ""))]
8ef65e3d 11595 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11596 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11597
11598(define_expand "buneq"
39a10a29 11599 [(use (match_operand 0 "" ""))]
b26941b4 11600 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11601 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
1c882ea4
GK		 11602
11603(define_expand "bunge"
39a10a29 11604 [(use (match_operand 0 "" ""))]
b26941b4 11605 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11606 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
1c882ea4
GK		 11607
11608(define_expand "bungt"
39a10a29 11609 [(use (match_operand 0 "" ""))]
b26941b4 11610 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11611 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
1c882ea4
GK		 11612
11613(define_expand "bunle"
39a10a29 11614 [(use (match_operand 0 "" ""))]
b26941b4 11615 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11616 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
1c882ea4
GK		 11617
11618(define_expand "bunlt"
39a10a29 11619 [(use (match_operand 0 "" ""))]
b26941b4 11620 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11621 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
1c882ea4
GK		 11622
11623(define_expand "bltgt"
39a10a29 11624 [(use (match_operand 0 "" ""))]
1c882ea4 11625 ""
39a10a29 11626 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
1c882ea4 11627
1fd4e8c1
RK		 11628;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11629;; For SEQ, likewise, except that comparisons with zero should be done
11630;; with an scc insns. However, due to the order that combine see the
11631;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11632;; the cases we don't want to handle.
11633(define_expand "seq"
39a10a29 11634 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11635 ""
39a10a29 11636 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11637
11638(define_expand "sne"
39a10a29 11639 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11640 ""
11641 "
6ae08853 11642{
39a10a29 11643 if (! rs6000_compare_fp_p)
1fd4e8c1
RK		 11644 FAIL;
11645
6ae08853 11646 rs6000_emit_sCOND (NE, operands[0]);
39a10a29 11647 DONE;
1fd4e8c1
RK		 11648}")
11649
b7053a3f
GK		 11650;; A >= 0 is best done the portable way for A an integer.
11651(define_expand "sge"
39a10a29 11652 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11653 ""
11654 "
5638268e 11655{
e56d7409 11656 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11657 FAIL;
11658
b7053a3f 11659 rs6000_emit_sCOND (GE, operands[0]);
39a10a29 11660 DONE;
1fd4e8c1
RK		 11661}")
11662
b7053a3f
GK		 11663;; A > 0 is best done using the portable sequence, so fail in that case.
11664(define_expand "sgt"
39a10a29 11665 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11666 ""
11667 "
5638268e 11668{
e56d7409 11669 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11670 FAIL;
11671
6ae08853 11672 rs6000_emit_sCOND (GT, operands[0]);
39a10a29 11673 DONE;
1fd4e8c1
RK		 11674}")
11675
b7053a3f
GK		 11676;; A <= 0 is best done the portable way for A an integer.
11677(define_expand "sle"
39a10a29 11678 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11679 ""
5638268e
DE		 11680 "
11681{
e56d7409 11682 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5638268e
DE		 11683 FAIL;
11684
6ae08853 11685 rs6000_emit_sCOND (LE, operands[0]);
5638268e
DE		 11686 DONE;
11687}")
1fd4e8c1 11688
b7053a3f
GK		 11689;; A < 0 is best done in the portable way for A an integer.
11690(define_expand "slt"
39a10a29 11691 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11692 ""
11693 "
5638268e 11694{
e56d7409 11695 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11696 FAIL;
11697
6ae08853 11698 rs6000_emit_sCOND (LT, operands[0]);
39a10a29 11699 DONE;
1fd4e8c1
RK		 11700}")
11701
b7053a3f
GK		 11702(define_expand "sgeu"
11703 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11704 ""
11705 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11706
1fd4e8c1 11707(define_expand "sgtu"
39a10a29 11708 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11709 ""
39a10a29 11710 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
1fd4e8c1 11711
b7053a3f
GK		 11712(define_expand "sleu"
11713 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11714 ""
11715 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11716
1fd4e8c1 11717(define_expand "sltu"
39a10a29 11718 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11719 ""
39a10a29 11720 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
1fd4e8c1 11721
b7053a3f 11722(define_expand "sunordered"
39a10a29 11723 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11724 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f 11725 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
1fd4e8c1 11726
b7053a3f 11727(define_expand "sordered"
39a10a29 11728 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11729 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11730 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11731
11732(define_expand "suneq"
11733 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11734 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11735 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11736
11737(define_expand "sunge"
11738 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11739 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11740 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11741
11742(define_expand "sungt"
11743 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11744 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11745 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11746
11747(define_expand "sunle"
11748 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11749 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11750 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11751
11752(define_expand "sunlt"
11753 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11754 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11755 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11756
11757(define_expand "sltgt"
11758 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11759 ""
11760 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11761
3aebbe5f
JJ		 11762(define_expand "stack_protect_set"
11763 [(match_operand 0 "memory_operand" "")
11764 (match_operand 1 "memory_operand" "")]
11765 ""
11766{
77008252
JJ		 11767#ifdef TARGET_THREAD_SSP_OFFSET
11768 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11769 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11770 operands[1] = gen_rtx_MEM (Pmode, addr);
11771#endif
3aebbe5f
JJ		 11772 if (TARGET_64BIT)
11773 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11774 else
11775 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11776 DONE;
11777})
11778
11779(define_insn "stack_protect_setsi"
11780 [(set (match_operand:SI 0 "memory_operand" "=m")
11781 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11782 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11783 "TARGET_32BIT"
11784 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11785 [(set_attr "type" "three")
11786 (set_attr "length" "12")])
11787
11788(define_insn "stack_protect_setdi"
11789 [(set (match_operand:DI 0 "memory_operand" "=m")
11790 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11791 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11792 "TARGET_64BIT"
11793 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11794 [(set_attr "type" "three")
11795 (set_attr "length" "12")])
11796
11797(define_expand "stack_protect_test"
11798 [(match_operand 0 "memory_operand" "")
11799 (match_operand 1 "memory_operand" "")
11800 (match_operand 2 "" "")]
11801 ""
11802{
77008252
JJ		 11803#ifdef TARGET_THREAD_SSP_OFFSET
11804 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11805 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11806 operands[1] = gen_rtx_MEM (Pmode, addr);
11807#endif
3aebbe5f
JJ		 11808 rs6000_compare_op0 = operands[0];
11809 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11810 UNSPEC_SP_TEST);
11811 rs6000_compare_fp_p = 0;
11812 emit_jump_insn (gen_beq (operands[2]));
11813 DONE;
11814})
11815
11816(define_insn "stack_protect_testsi"
11817 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11818 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11819 (match_operand:SI 2 "memory_operand" "m,m")]
11820 UNSPEC_SP_TEST))
41f12ed0
JJ		 11821 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11822 (clobber (match_scratch:SI 3 "=&r,&r"))]
3aebbe5f
JJ		 11823 "TARGET_32BIT"
11824 "@
11825 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11826 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11827 [(set_attr "length" "16,20")])
11828
11829(define_insn "stack_protect_testdi"
11830 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11831 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11832 (match_operand:DI 2 "memory_operand" "m,m")]
11833 UNSPEC_SP_TEST))
41f12ed0
JJ		 11834 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11835 (clobber (match_scratch:DI 3 "=&r,&r"))]
3aebbe5f
JJ		 11836 "TARGET_64BIT"
11837 "@
11838 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11839 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11840 [(set_attr "length" "16,20")])
11841
1fd4e8c1
RK		 11842\f
11843;; Here are the actual compare insns.
4ae234b0 11844(define_insn "*cmp<mode>_internal1"
1fd4e8c1 11845 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
4ae234b0
GK		 11846 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11847 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
1fd4e8c1 11848 ""
4ae234b0 11849 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
b54cf83a 11850 [(set_attr "type" "cmp")])
266eb58a 11851
f357808b 11852;; If we are comparing a register for equality with a large constant,
28d0e143
PB		 11853;; we can do this with an XOR followed by a compare. But this is profitable
11854;; only if the large constant is only used for the comparison (and in this
11855;; case we already have a register to reuse as scratch).
130869aa
PB		 11856;;
11857;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11858;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
f357808b 11859
28d0e143 11860(define_peephole2
130869aa 11861 [(set (match_operand:SI 0 "register_operand")
410c459d 11862 (match_operand:SI 1 "logical_const_operand" ""))
130869aa 11863 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
28d0e143 11864 [(match_dup 0)
410c459d 11865 (match_operand:SI 2 "logical_const_operand" "")]))
28d0e143 11866 (set (match_operand:CC 4 "cc_reg_operand" "")
130869aa 11867 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
28d0e143
PB		 11868 (match_dup 0)))
11869 (set (pc)
11870 (if_then_else (match_operator 6 "equality_operator"
11871 [(match_dup 4) (const_int 0)])
11872 (match_operand 7 "" "")
11873 (match_operand 8 "" "")))]
130869aa
PB		 11874 "peep2_reg_dead_p (3, operands[0])
11875 && peep2_reg_dead_p (4, operands[4])"
11876 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
28d0e143
PB		 11877 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11878 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11879
11880{
11881 /* Get the constant we are comparing against, and see what it looks like
11882 when sign-extended from 16 to 32 bits. Then see what constant we could
11883 XOR with SEXTC to get the sign-extended value. */
11884 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
130869aa 11885 SImode,
28d0e143
PB		 11886 operands[1], operands[2]);
11887 HOST_WIDE_INT c = INTVAL (cnst);
a65c591c 11888 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 11889 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 11890
28d0e143
PB		 11891 operands[9] = GEN_INT (xorv);
11892 operands[10] = GEN_INT (sextc);
11893})
f357808b 11894
acad7ed3 11895(define_insn "*cmpsi_internal2"
1fd4e8c1 11896 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 11897 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 11898 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 11899 ""
e2c953b6 11900 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 11901 [(set_attr "type" "cmp")])
1fd4e8c1 11902
acad7ed3 11903(define_insn "*cmpdi_internal2"
266eb58a
DE		 11904 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11905 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 11906 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 11907 ""
e2c953b6 11908 "cmpld%I2 %0,%1,%b2"
b54cf83a 11909 [(set_attr "type" "cmp")])
266eb58a 11910
1fd4e8c1
RK		 11911;; The following two insns don't exist as single insns, but if we provide
11912;; them, we can swap an add and compare, which will enable us to overlap more
11913;; of the required delay between a compare and branch. We generate code for
11914;; them by splitting.
11915
11916(define_insn ""
11917 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 11918 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11919 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 11920 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11921 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11922 ""
baf97f86
RK		 11923 "#"
11924 [(set_attr "length" "8")])
7e69e155 11925
1fd4e8c1
RK		 11926(define_insn ""
11927 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 11928 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11929 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 11930 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11931 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11932 ""
baf97f86
RK		 11933 "#"
11934 [(set_attr "length" "8")])
7e69e155 11935
1fd4e8c1
RK		 11936(define_split
11937 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 11938 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11939 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 11940 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11941 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11942 ""
11943 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11944 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11945
11946(define_split
11947 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 11948 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11949 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 11950 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11951 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11952 ""
11953 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11954 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11955
acad7ed3 11956(define_insn "*cmpsf_internal1"
1fd4e8c1 11957 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11958 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11959 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 11960 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11961 "fcmpu %0,%1,%2"
11962 [(set_attr "type" "fpcompare")])
11963
acad7ed3 11964(define_insn "*cmpdf_internal1"
1fd4e8c1 11965 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11966 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11967 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 11968 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11969 "fcmpu %0,%1,%2"
11970 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 11971
11972;; Only need to compare second words if first words equal
11973(define_insn "*cmptf_internal1"
11974 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11975 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11976 (match_operand:TF 2 "gpc_reg_operand" "f")))]
602ea4d3 11977 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
39e63627 11978 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 11979 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 11980 [(set_attr "type" "fpcompare")
11981 (set_attr "length" "12")])
de17c25f
DE		 11982
11983(define_insn_and_split "*cmptf_internal2"
11984 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11985 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11986 (match_operand:TF 2 "gpc_reg_operand" "f")))
11987 (clobber (match_scratch:DF 3 "=f"))
11988 (clobber (match_scratch:DF 4 "=f"))
11989 (clobber (match_scratch:DF 5 "=f"))
11990 (clobber (match_scratch:DF 6 "=f"))
11991 (clobber (match_scratch:DF 7 "=f"))
11992 (clobber (match_scratch:DF 8 "=f"))
11993 (clobber (match_scratch:DF 9 "=f"))
11994 (clobber (match_scratch:DF 10 "=f"))]
602ea4d3 11995 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
de17c25f
DE		 11996 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11997 "#"
11998 "&& reload_completed"
11999 [(set (match_dup 3) (match_dup 13))
12000 (set (match_dup 4) (match_dup 14))
12001 (set (match_dup 9) (abs:DF (match_dup 5)))
12002 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12003 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12004 (label_ref (match_dup 11))
12005 (pc)))
12006 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12007 (set (pc) (label_ref (match_dup 12)))
12008 (match_dup 11)
12009 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12010 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12011 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12012 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12013 (match_dup 12)]
12014{
12015 REAL_VALUE_TYPE rv;
12016 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12017 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12018
12019 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12020 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12021 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12022 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12023 operands[11] = gen_label_rtx ();
12024 operands[12] = gen_label_rtx ();
12025 real_inf (&rv);
12026 operands[13] = force_const_mem (DFmode,
12027 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12028 operands[14] = force_const_mem (DFmode,
12029 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12030 DFmode));
12031 if (TARGET_TOC)
12032 {
12033 operands[13] = gen_const_mem (DFmode,
12034 create_TOC_reference (XEXP (operands[13], 0)));
12035 operands[14] = gen_const_mem (DFmode,
12036 create_TOC_reference (XEXP (operands[14], 0)));
12037 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12038 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12039 }
12040})
1fd4e8c1
RK		 12041\f
12042;; Now we have the scc insns. We can do some combinations because of the
12043;; way the machine works.
12044;;
12045;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 12046;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12047;; cases the insns below which don't use an intermediate CR field will
12048;; be used instead.
1fd4e8c1 12049(define_insn ""
cd2b37d9 12050 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12051 (match_operator:SI 1 "scc_comparison_operator"
12052 [(match_operand 2 "cc_reg_operand" "y")
12053 (const_int 0)]))]
12054 ""
2c4a9cff
DE		 12055 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12056 [(set (attr "type")
12057 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12058 (const_string "mfcrf")
12059 ]
12060 (const_string "mfcr")))
c1618c0c 12061 (set_attr "length" "8")])
1fd4e8c1 12062
423c1189 12063;; Same as above, but get the GT bit.
64022b5d 12064(define_insn "move_from_CR_gt_bit"
423c1189 12065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
64022b5d 12066 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
423c1189 12067 "TARGET_E500"
64022b5d 12068 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
423c1189 12069 [(set_attr "type" "mfcr")
c1618c0c 12070 (set_attr "length" "8")])
423c1189 12071
a3170dc6
AH		 12072;; Same as above, but get the OV/ORDERED bit.
12073(define_insn "move_from_CR_ov_bit"
12074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 12075 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 12076 "TARGET_ISEL"
b7053a3f 12077 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a 12078 [(set_attr "type" "mfcr")
c1618c0c 12079 (set_attr "length" "8")])
a3170dc6 12080
1fd4e8c1 12081(define_insn ""
9ebbca7d
GK		 12082 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12083 (match_operator:DI 1 "scc_comparison_operator"
12084 [(match_operand 2 "cc_reg_operand" "y")
12085 (const_int 0)]))]
12086 "TARGET_POWERPC64"
2c4a9cff
DE		 12087 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12088 [(set (attr "type")
12089 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12090 (const_string "mfcrf")
12091 ]
12092 (const_string "mfcr")))
c1618c0c 12093 (set_attr "length" "8")])
9ebbca7d
GK		 12094
12095(define_insn ""
12096 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12097 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12098 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 12099 (const_int 0)])
12100 (const_int 0)))
9ebbca7d 12101 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 12102 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12103 "TARGET_32BIT"
9ebbca7d 12104 "@
2c4a9cff 12105 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 12106 #"
b19003d8 12107 [(set_attr "type" "delayed_compare")
c1618c0c 12108 (set_attr "length" "8,16")])
9ebbca7d
GK		 12109
12110(define_split
12111 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12112 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12113 [(match_operand 2 "cc_reg_operand" "")
12114 (const_int 0)])
12115 (const_int 0)))
12116 (set (match_operand:SI 3 "gpc_reg_operand" "")
12117 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12118 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12119 [(set (match_dup 3)
12120 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12121 (set (match_dup 0)
12122 (compare:CC (match_dup 3)
12123 (const_int 0)))]
12124 "")
1fd4e8c1
RK		 12125
12126(define_insn ""
cd2b37d9 12127 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12128 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12129 [(match_operand 2 "cc_reg_operand" "y")
12130 (const_int 0)])
12131 (match_operand:SI 3 "const_int_operand" "n")))]
12132 ""
12133 "*
12134{
12135 int is_bit = ccr_bit (operands[1], 1);
12136 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12137 int count;
12138
12139 if (is_bit >= put_bit)
12140 count = is_bit - put_bit;
12141 else
12142 count = 32 - (put_bit - is_bit);
12143
89e9f3a8
MM		 12144 operands[4] = GEN_INT (count);
12145 operands[5] = GEN_INT (put_bit);
1fd4e8c1 12146
2c4a9cff 12147 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 12148}"
2c4a9cff
DE		 12149 [(set (attr "type")
12150 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12151 (const_string "mfcrf")
12152 ]
12153 (const_string "mfcr")))
c1618c0c 12154 (set_attr "length" "8")])
1fd4e8c1
RK		 12155
12156(define_insn ""
9ebbca7d 12157 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12158 (compare:CC
12159 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12160 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 12161 (const_int 0)])
9ebbca7d 12162 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 12163 (const_int 0)))
9ebbca7d 12164 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12165 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12166 (match_dup 3)))]
ce71f754 12167 ""
1fd4e8c1
RK		 12168 "*
12169{
12170 int is_bit = ccr_bit (operands[1], 1);
12171 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12172 int count;
12173
9ebbca7d
GK		 12174 /* Force split for non-cc0 compare. */
12175 if (which_alternative == 1)
12176 return \"#\";
12177
1fd4e8c1
RK		 12178 if (is_bit >= put_bit)
12179 count = is_bit - put_bit;
12180 else
12181 count = 32 - (put_bit - is_bit);
12182
89e9f3a8
MM		 12183 operands[5] = GEN_INT (count);
12184 operands[6] = GEN_INT (put_bit);
1fd4e8c1 12185
2c4a9cff 12186 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 12187}"
b19003d8 12188 [(set_attr "type" "delayed_compare")
c1618c0c 12189 (set_attr "length" "8,16")])
9ebbca7d
GK		 12190
12191(define_split
12192 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12193 (compare:CC
12194 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12195 [(match_operand 2 "cc_reg_operand" "")
12196 (const_int 0)])
12197 (match_operand:SI 3 "const_int_operand" ""))
12198 (const_int 0)))
12199 (set (match_operand:SI 4 "gpc_reg_operand" "")
12200 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12201 (match_dup 3)))]
ce71f754 12202 "reload_completed"
9ebbca7d
GK		 12203 [(set (match_dup 4)
12204 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12205 (match_dup 3)))
12206 (set (match_dup 0)
12207 (compare:CC (match_dup 4)
12208 (const_int 0)))]
12209 "")
1fd4e8c1 12210
c5defebb
RK		 12211;; There is a 3 cycle delay between consecutive mfcr instructions
12212;; so it is useful to combine 2 scc instructions to use only one mfcr.
12213
12214(define_peephole
cd2b37d9 12215 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 12216 (match_operator:SI 1 "scc_comparison_operator"
12217 [(match_operand 2 "cc_reg_operand" "y")
12218 (const_int 0)]))
cd2b37d9 12219 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 12220 (match_operator:SI 4 "scc_comparison_operator"
12221 [(match_operand 5 "cc_reg_operand" "y")
12222 (const_int 0)]))]
309323c2 12223 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12224 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12225 [(set_attr "type" "mfcr")
c1618c0c 12226 (set_attr "length" "12")])
c5defebb 12227
9ebbca7d
GK		 12228(define_peephole
12229 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12230 (match_operator:DI 1 "scc_comparison_operator"
12231 [(match_operand 2 "cc_reg_operand" "y")
12232 (const_int 0)]))
12233 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12234 (match_operator:DI 4 "scc_comparison_operator"
12235 [(match_operand 5 "cc_reg_operand" "y")
12236 (const_int 0)]))]
309323c2 12237 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12238 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12239 [(set_attr "type" "mfcr")
c1618c0c 12240 (set_attr "length" "12")])
9ebbca7d 12241
1fd4e8c1
RK		 12242;; There are some scc insns that can be done directly, without a compare.
12243;; These are faster because they don't involve the communications between
12244;; the FXU and branch units. In fact, we will be replacing all of the
12245;; integer scc insns here or in the portable methods in emit_store_flag.
12246;;
12247;; Also support (neg (scc ..)) since that construct is used to replace
12248;; branches, (plus (scc ..) ..) since that construct is common and
12249;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12250;; cases where it is no more expensive than (neg (scc ..)).
12251
12252;; Have reload force a constant into a register for the simple insns that
12253;; otherwise won't accept constants. We do this because it is faster than
12254;; the cmp/mfcr sequence we would otherwise generate.
12255
e9441276
DE		 12256(define_mode_attr scc_eq_op2 [(SI "rKLI")
12257 (DI "rKJI")])
a260abc9 12258
e9441276
DE		 12259(define_insn_and_split "*eq<mode>"
12260 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12261 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
d0515b39 12262 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
27f0fe7f 12263 "!TARGET_POWER"
e9441276 12264 "#"
27f0fe7f 12265 "!TARGET_POWER"
d0515b39
DE		 12266 [(set (match_dup 0)
12267 (clz:GPR (match_dup 3)))
70ae0191 12268 (set (match_dup 0)
d0515b39 12269 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
70ae0191 12270 {
e9441276
DE		 12271 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12272 {
d0515b39
DE		 12273 /* Use output operand as intermediate. */
12274 operands[3] = operands[0];
12275
e9441276 12276 if (logical_operand (operands[2], <MODE>mode))
d0515b39 12277 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12278 gen_rtx_XOR (<MODE>mode,
12279 operands[1], operands[2])));
12280 else
d0515b39 12281 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12282 gen_rtx_PLUS (<MODE>mode, operands[1],
12283 negate_rtx (<MODE>mode,
12284 operands[2]))));
12285 }
12286 else
d0515b39 12287 operands[3] = operands[1];
9ebbca7d 12288
d0515b39 12289 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
e9441276 12290 })
a260abc9 12291
e9441276 12292(define_insn_and_split "*eq<mode>_compare"
d0515b39 12293 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
70ae0191 12294 (compare:CC
1fa5c709
DE		 12295 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12296 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
70ae0191 12297 (const_int 0)))
1fa5c709 12298 (set (match_operand:P 0 "gpc_reg_operand" "=r")
d0515b39 12299 (eq:P (match_dup 1) (match_dup 2)))]
27f0fe7f 12300 "!TARGET_POWER && optimize_size"
e9441276 12301 "#"
27f0fe7f 12302 "!TARGET_POWER && optimize_size"
d0515b39 12303 [(set (match_dup 0)
1fa5c709 12304 (clz:P (match_dup 4)))
d0515b39
DE		 12305 (parallel [(set (match_dup 3)
12306 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
70ae0191
DE		 12307 (const_int 0)))
12308 (set (match_dup 0)
d0515b39 12309 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
70ae0191 12310 {
e9441276
DE		 12311 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12312 {
d0515b39
DE		 12313 /* Use output operand as intermediate. */
12314 operands[4] = operands[0];
12315
e9441276
DE		 12316 if (logical_operand (operands[2], <MODE>mode))
12317 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12318 gen_rtx_XOR (<MODE>mode,
12319 operands[1], operands[2])));
12320 else
12321 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12322 gen_rtx_PLUS (<MODE>mode, operands[1],
12323 negate_rtx (<MODE>mode,
12324 operands[2]))));
12325 }
12326 else
12327 operands[4] = operands[1];
12328
d0515b39 12329 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
70ae0191
DE		 12330 })
12331
05f68097
DE		 12332(define_insn "*eqsi_power"
12333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12334 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12335 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12336 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12337 "TARGET_POWER"
12338 "@
12339 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12340 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12341 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12342 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12343 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12344 [(set_attr "type" "three,two,three,three,three")
12345 (set_attr "length" "12,8,12,12,12")])
12346
b19003d8
RK		 12347;; We have insns of the form shown by the first define_insn below. If
12348;; there is something inside the comparison operation, we must split it.
12349(define_split
12350 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12351 (plus:SI (match_operator 1 "comparison_operator"
12352 [(match_operand:SI 2 "" "")
12353 (match_operand:SI 3
12354 "reg_or_cint_operand" "")])
12355 (match_operand:SI 4 "gpc_reg_operand" "")))
12356 (clobber (match_operand:SI 5 "register_operand" ""))]
12357 "! gpc_reg_operand (operands[2], SImode)"
12358 [(set (match_dup 5) (match_dup 2))
12359 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12360 (match_dup 4)))])
1fd4e8c1 12361
297abd0d 12362(define_insn "*plus_eqsi"
5276df18 12363 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 12364 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
56fc483e 12365 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
5276df18 12366 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
59d6560b 12367 "TARGET_32BIT"
1fd4e8c1 12368 "@
5276df18
DE		 12369 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12370 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12371 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12372 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12373 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
943c15ed
DE		 12374 [(set_attr "type" "three,two,three,three,three")
12375 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1 12376
297abd0d 12377(define_insn "*compare_plus_eqsi"
9ebbca7d 12378 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12379 (compare:CC
1fd4e8c1 12380 (plus:SI
9ebbca7d 12381 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12382 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12383 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12384 (const_int 0)))
9ebbca7d 12385 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
297abd0d 12386 "TARGET_32BIT && optimize_size"
1fd4e8c1 12387 "@
ca7f5001 12388 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 12389 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 12390 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12391 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12392 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12393 #
12394 #
12395 #
12396 #
12397 #"
b19003d8 12398 [(set_attr "type" "compare")
9ebbca7d
GK		 12399 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12400
12401(define_split
12402 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12403 (compare:CC
12404 (plus:SI
12405 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12406 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12407 (match_operand:SI 3 "gpc_reg_operand" ""))
12408 (const_int 0)))
12409 (clobber (match_scratch:SI 4 ""))]
297abd0d 12410 "TARGET_32BIT && optimize_size && reload_completed"
9ebbca7d
GK		 12411 [(set (match_dup 4)
12412 (plus:SI (eq:SI (match_dup 1)
12413 (match_dup 2))
12414 (match_dup 3)))
12415 (set (match_dup 0)
12416 (compare:CC (match_dup 4)
12417 (const_int 0)))]
12418 "")
1fd4e8c1 12419
297abd0d 12420(define_insn "*plus_eqsi_compare"
0387639b 12421 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12422 (compare:CC
1fd4e8c1 12423 (plus:SI
9ebbca7d 12424 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12425 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12426 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12427 (const_int 0)))
0387639b
DE		 12428 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12429 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12430 "TARGET_32BIT && optimize_size"
1fd4e8c1 12431 "@
0387639b
DE		 12432 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12433 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12434 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12435 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12436 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12437 #
12438 #
12439 #
12440 #
12441 #"
12442 [(set_attr "type" "compare")
12443 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12444
12445(define_split
0387639b 12446 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12447 (compare:CC
12448 (plus:SI
12449 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12450 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12451 (match_operand:SI 3 "gpc_reg_operand" ""))
12452 (const_int 0)))
12453 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 12454 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12455 "TARGET_32BIT && optimize_size && reload_completed"
0387639b 12456 [(set (match_dup 0)
9ebbca7d 12457 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 12458 (set (match_dup 4)
9ebbca7d
GK		 12459 (compare:CC (match_dup 0)
12460 (const_int 0)))]
12461 "")
12462
d0515b39
DE		 12463(define_insn "*neg_eq0<mode>"
12464 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12465 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12466 (const_int 0))))]
59d6560b 12467 ""
d0515b39
DE		 12468 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12469 [(set_attr "type" "two")
12470 (set_attr "length" "8")])
12471
12472(define_insn_and_split "*neg_eq<mode>"
12473 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12474 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12475 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
59d6560b 12476 ""
d0515b39 12477 "#"
59d6560b 12478 ""
d0515b39
DE		 12479 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12480 {
12481 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12482 {
12483 /* Use output operand as intermediate. */
12484 operands[3] = operands[0];
12485
12486 if (logical_operand (operands[2], <MODE>mode))
12487 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12488 gen_rtx_XOR (<MODE>mode,
12489 operands[1], operands[2])));
12490 else
12491 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12492 gen_rtx_PLUS (<MODE>mode, operands[1],
12493 negate_rtx (<MODE>mode,
12494 operands[2]))));
12495 }
12496 else
12497 operands[3] = operands[1];
12498 })
1fd4e8c1 12499
ea9be077
MM		 12500;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12501;; since it nabs/sr is just as fast.
ce45ef46 12502(define_insn "*ne0si"
b4e95693 12503 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 12504 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12505 (const_int 31)))
12506 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 12507 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077 12508 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
943c15ed
DE		 12509 [(set_attr "type" "two")
12510 (set_attr "length" "8")])
ea9be077 12511
ce45ef46 12512(define_insn "*ne0di"
a260abc9
DE		 12513 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12514 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12515 (const_int 63)))
12516 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 12517 "TARGET_64BIT"
a260abc9 12518 "addic %2,%1,-1\;subfe %0,%2,%1"
943c15ed
DE		 12519 [(set_attr "type" "two")
12520 (set_attr "length" "8")])
a260abc9 12521
1fd4e8c1 12522;; This is what (plus (ne X (const_int 0)) Y) looks like.
297abd0d 12523(define_insn "*plus_ne0si"
cd2b37d9 12524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 12525 (plus:SI (lshiftrt:SI
cd2b37d9 12526 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 12527 (const_int 31))
cd2b37d9 12528 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 12529 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 12530 "TARGET_32BIT"
ca7f5001 12531 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
943c15ed
DE		 12532 [(set_attr "type" "two")
12533 (set_attr "length" "8")])
1fd4e8c1 12534
297abd0d 12535(define_insn "*plus_ne0di"
a260abc9
DE		 12536 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12537 (plus:DI (lshiftrt:DI
12538 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12539 (const_int 63))
12540 (match_operand:DI 2 "gpc_reg_operand" "r")))
12541 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 12542 "TARGET_64BIT"
a260abc9 12543 "addic %3,%1,-1\;addze %0,%2"
943c15ed
DE		 12544 [(set_attr "type" "two")
12545 (set_attr "length" "8")])
a260abc9 12546
297abd0d 12547(define_insn "*compare_plus_ne0si"
9ebbca7d 12548 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12549 (compare:CC
12550 (plus:SI (lshiftrt:SI
9ebbca7d 12551 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12552 (const_int 31))
9ebbca7d 12553 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12554 (const_int 0)))
889b90a1
GK		 12555 (clobber (match_scratch:SI 3 "=&r,&r"))
12556 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 12557 "TARGET_32BIT"
9ebbca7d
GK		 12558 "@
12559 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12560 #"
b19003d8 12561 [(set_attr "type" "compare")
9ebbca7d
GK		 12562 (set_attr "length" "8,12")])
12563
12564(define_split
12565 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12566 (compare:CC
12567 (plus:SI (lshiftrt:SI
12568 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12569 (const_int 31))
12570 (match_operand:SI 2 "gpc_reg_operand" ""))
12571 (const_int 0)))
889b90a1
GK		 12572 (clobber (match_scratch:SI 3 ""))
12573 (clobber (match_scratch:SI 4 ""))]
683bdff7 12574 "TARGET_32BIT && reload_completed"
889b90a1 12575 [(parallel [(set (match_dup 3)
ce71f754
AM		 12576 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12577 (const_int 31))
12578 (match_dup 2)))
889b90a1 12579 (clobber (match_dup 4))])
9ebbca7d
GK		 12580 (set (match_dup 0)
12581 (compare:CC (match_dup 3)
12582 (const_int 0)))]
12583 "")
1fd4e8c1 12584
297abd0d 12585(define_insn "*compare_plus_ne0di"
9ebbca7d 12586 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12587 (compare:CC
12588 (plus:DI (lshiftrt:DI
9ebbca7d 12589 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12590 (const_int 63))
9ebbca7d 12591 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12592 (const_int 0)))
9ebbca7d 12593 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12594 "TARGET_64BIT"
9ebbca7d
GK		 12595 "@
12596 addic %3,%1,-1\;addze. %3,%2
12597 #"
a260abc9 12598 [(set_attr "type" "compare")
9ebbca7d
GK		 12599 (set_attr "length" "8,12")])
12600
12601(define_split
12602 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12603 (compare:CC
12604 (plus:DI (lshiftrt:DI
12605 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12606 (const_int 63))
12607 (match_operand:DI 2 "gpc_reg_operand" ""))
12608 (const_int 0)))
12609 (clobber (match_scratch:DI 3 ""))]
683bdff7 12610 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12611 [(set (match_dup 3)
12612 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12613 (const_int 63))
12614 (match_dup 2)))
12615 (set (match_dup 0)
12616 (compare:CC (match_dup 3)
12617 (const_int 0)))]
12618 "")
a260abc9 12619
297abd0d 12620(define_insn "*plus_ne0si_compare"
9ebbca7d 12621 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12622 (compare:CC
12623 (plus:SI (lshiftrt:SI
9ebbca7d 12624 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12625 (const_int 31))
9ebbca7d 12626 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12627 (const_int 0)))
9ebbca7d 12628 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12629 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12630 (match_dup 2)))
9ebbca7d 12631 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 12632 "TARGET_32BIT"
9ebbca7d
GK		 12633 "@
12634 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12635 #"
b19003d8 12636 [(set_attr "type" "compare")
9ebbca7d
GK		 12637 (set_attr "length" "8,12")])
12638
12639(define_split
12640 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12641 (compare:CC
12642 (plus:SI (lshiftrt:SI
12643 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12644 (const_int 31))
12645 (match_operand:SI 2 "gpc_reg_operand" ""))
12646 (const_int 0)))
12647 (set (match_operand:SI 0 "gpc_reg_operand" "")
12648 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12649 (match_dup 2)))
12650 (clobber (match_scratch:SI 3 ""))]
683bdff7 12651 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12652 [(parallel [(set (match_dup 0)
12653 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12654 (match_dup 2)))
12655 (clobber (match_dup 3))])
12656 (set (match_dup 4)
12657 (compare:CC (match_dup 0)
12658 (const_int 0)))]
12659 "")
1fd4e8c1 12660
297abd0d 12661(define_insn "*plus_ne0di_compare"
9ebbca7d 12662 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12663 (compare:CC
12664 (plus:DI (lshiftrt:DI
9ebbca7d 12665 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12666 (const_int 63))
9ebbca7d 12667 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12668 (const_int 0)))
9ebbca7d 12669 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 12670 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12671 (match_dup 2)))
9ebbca7d 12672 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12673 "TARGET_64BIT"
9ebbca7d
GK		 12674 "@
12675 addic %3,%1,-1\;addze. %0,%2
12676 #"
a260abc9 12677 [(set_attr "type" "compare")
9ebbca7d
GK		 12678 (set_attr "length" "8,12")])
12679
12680(define_split
12681 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12682 (compare:CC
12683 (plus:DI (lshiftrt:DI
12684 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12685 (const_int 63))
12686 (match_operand:DI 2 "gpc_reg_operand" ""))
12687 (const_int 0)))
12688 (set (match_operand:DI 0 "gpc_reg_operand" "")
12689 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12690 (match_dup 2)))
12691 (clobber (match_scratch:DI 3 ""))]
683bdff7 12692 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12693 [(parallel [(set (match_dup 0)
12694 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12695 (match_dup 2)))
12696 (clobber (match_dup 3))])
12697 (set (match_dup 4)
12698 (compare:CC (match_dup 0)
12699 (const_int 0)))]
12700 "")
a260abc9 12701
1fd4e8c1 12702(define_insn ""
cd2b37d9
RK		 12703 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12704 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 12705 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12706 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 12707 "TARGET_POWER"
1fd4e8c1 12708 "@
ca7f5001 12709 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 12710 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12711 [(set_attr "length" "12")])
1fd4e8c1
RK		 12712
12713(define_insn ""
9ebbca7d 12714 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12715 (compare:CC
9ebbca7d
GK		 12716 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12717 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 12718 (const_int 0)))
9ebbca7d 12719 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12720 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12721 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 12722 "TARGET_POWER"
1fd4e8c1 12723 "@
ca7f5001 12724 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 12725 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12726 #
12727 #"
12728 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12729 (set_attr "length" "12,12,16,16")])
12730
12731(define_split
12732 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12733 (compare:CC
12734 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12735 (match_operand:SI 2 "reg_or_short_operand" ""))
12736 (const_int 0)))
12737 (set (match_operand:SI 0 "gpc_reg_operand" "")
12738 (le:SI (match_dup 1) (match_dup 2)))
12739 (clobber (match_scratch:SI 3 ""))]
12740 "TARGET_POWER && reload_completed"
12741 [(parallel [(set (match_dup 0)
12742 (le:SI (match_dup 1) (match_dup 2)))
12743 (clobber (match_dup 3))])
12744 (set (match_dup 4)
12745 (compare:CC (match_dup 0)
12746 (const_int 0)))]
12747 "")
1fd4e8c1
RK		 12748
12749(define_insn ""
097657c3 12750 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12751 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12752 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 12753 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 12754 "TARGET_POWER"
1fd4e8c1 12755 "@
097657c3
AM		 12756 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12757 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 12758 [(set_attr "length" "12")])
1fd4e8c1
RK		 12759
12760(define_insn ""
9ebbca7d 12761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12762 (compare:CC
9ebbca7d
GK		 12763 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12764 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12765 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12766 (const_int 0)))
9ebbca7d 12767 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 12768 "TARGET_POWER"
1fd4e8c1 12769 "@
ca7f5001 12770 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12771 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12772 #
12773 #"
b19003d8 12774 [(set_attr "type" "compare")
9ebbca7d
GK		 12775 (set_attr "length" "12,12,16,16")])
12776
12777(define_split
12778 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12779 (compare:CC
12780 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12781 (match_operand:SI 2 "reg_or_short_operand" ""))
12782 (match_operand:SI 3 "gpc_reg_operand" ""))
12783 (const_int 0)))
12784 (clobber (match_scratch:SI 4 ""))]
12785 "TARGET_POWER && reload_completed"
12786 [(set (match_dup 4)
12787 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 12788 (match_dup 3)))
9ebbca7d
GK		 12789 (set (match_dup 0)
12790 (compare:CC (match_dup 4)
12791 (const_int 0)))]
12792 "")
1fd4e8c1
RK		 12793
12794(define_insn ""
097657c3 12795 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12796 (compare:CC
9ebbca7d
GK		 12797 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12798 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12799 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12800 (const_int 0)))
097657c3
AM		 12801 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12802 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12803 "TARGET_POWER"
1fd4e8c1 12804 "@
097657c3
AM		 12805 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12806 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12807 #
12808 #"
b19003d8 12809 [(set_attr "type" "compare")
9ebbca7d
GK		 12810 (set_attr "length" "12,12,16,16")])
12811
12812(define_split
097657c3 12813 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12814 (compare:CC
12815 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12816 (match_operand:SI 2 "reg_or_short_operand" ""))
12817 (match_operand:SI 3 "gpc_reg_operand" ""))
12818 (const_int 0)))
12819 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12820 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12821 "TARGET_POWER && reload_completed"
097657c3 12822 [(set (match_dup 0)
9ebbca7d 12823 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12824 (set (match_dup 4)
9ebbca7d
GK		 12825 (compare:CC (match_dup 0)
12826 (const_int 0)))]
12827 "")
1fd4e8c1
RK		 12828
12829(define_insn ""
cd2b37d9
RK		 12830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12831 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12832 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 12833 "TARGET_POWER"
1fd4e8c1 12834 "@
ca7f5001
RK		 12835 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12836 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12837 [(set_attr "length" "12")])
1fd4e8c1 12838
a2dba291
DE		 12839(define_insn "*leu<mode>"
12840 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12841 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12842 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12843 ""
ca7f5001 12844 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 12845 [(set_attr "type" "three")
12846 (set_attr "length" "12")])
1fd4e8c1 12847
a2dba291 12848(define_insn "*leu<mode>_compare"
9ebbca7d 12849 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12850 (compare:CC
a2dba291
DE		 12851 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12852 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12853 (const_int 0)))
a2dba291
DE		 12854 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12855 (leu:P (match_dup 1) (match_dup 2)))]
12856 ""
9ebbca7d
GK		 12857 "@
12858 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12859 #"
b19003d8 12860 [(set_attr "type" "compare")
9ebbca7d
GK		 12861 (set_attr "length" "12,16")])
12862
12863(define_split
12864 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12865 (compare:CC
a2dba291
DE		 12866 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12867 (match_operand:P 2 "reg_or_short_operand" ""))
9ebbca7d 12868 (const_int 0)))
a2dba291
DE		 12869 (set (match_operand:P 0 "gpc_reg_operand" "")
12870 (leu:P (match_dup 1) (match_dup 2)))]
12871 "reload_completed"
9ebbca7d 12872 [(set (match_dup 0)
a2dba291 12873 (leu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 12874 (set (match_dup 3)
12875 (compare:CC (match_dup 0)
12876 (const_int 0)))]
12877 "")
1fd4e8c1 12878
a2dba291
DE		 12879(define_insn "*plus_leu<mode>"
12880 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12881 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12882 (match_operand:P 2 "reg_or_short_operand" "rI"))
12883 (match_operand:P 3 "gpc_reg_operand" "r")))]
12884 ""
80103f96 12885 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
943c15ed
DE		 12886 [(set_attr "type" "two")
12887 (set_attr "length" "8")])
1fd4e8c1
RK		 12888
12889(define_insn ""
9ebbca7d 12890 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12891 (compare:CC
9ebbca7d
GK		 12892 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12893 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12894 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12895 (const_int 0)))
9ebbca7d 12896 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12897 "TARGET_32BIT"
9ebbca7d
GK		 12898 "@
12899 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12900 #"
b19003d8 12901 [(set_attr "type" "compare")
9ebbca7d
GK		 12902 (set_attr "length" "8,12")])
12903
12904(define_split
12905 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12906 (compare:CC
12907 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12908 (match_operand:SI 2 "reg_or_short_operand" ""))
12909 (match_operand:SI 3 "gpc_reg_operand" ""))
12910 (const_int 0)))
12911 (clobber (match_scratch:SI 4 ""))]
683bdff7 12912 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12913 [(set (match_dup 4)
12914 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12915 (match_dup 3)))
12916 (set (match_dup 0)
12917 (compare:CC (match_dup 4)
12918 (const_int 0)))]
12919 "")
1fd4e8c1
RK		 12920
12921(define_insn ""
097657c3 12922 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12923 (compare:CC
9ebbca7d
GK		 12924 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12925 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12926 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12927 (const_int 0)))
097657c3
AM		 12928 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12929 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12930 "TARGET_32BIT"
9ebbca7d 12931 "@
097657c3 12932 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 12933 #"
b19003d8 12934 [(set_attr "type" "compare")
9ebbca7d
GK		 12935 (set_attr "length" "8,12")])
12936
12937(define_split
097657c3 12938 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12939 (compare:CC
12940 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12941 (match_operand:SI 2 "reg_or_short_operand" ""))
12942 (match_operand:SI 3 "gpc_reg_operand" ""))
12943 (const_int 0)))
12944 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12945 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12946 "TARGET_32BIT && reload_completed"
097657c3 12947 [(set (match_dup 0)
9ebbca7d 12948 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12949 (set (match_dup 4)
9ebbca7d
GK		 12950 (compare:CC (match_dup 0)
12951 (const_int 0)))]
12952 "")
1fd4e8c1 12953
a2dba291
DE		 12954(define_insn "*neg_leu<mode>"
12955 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12956 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12957 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12958 ""
ca7f5001 12959 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
943c15ed
DE		 12960 [(set_attr "type" "three")
12961 (set_attr "length" "12")])
1fd4e8c1 12962
a2dba291
DE		 12963(define_insn "*and_neg_leu<mode>"
12964 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12965 (and:P (neg:P
12966 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12967 (match_operand:P 2 "reg_or_short_operand" "rI")))
12968 (match_operand:P 3 "gpc_reg_operand" "r")))]
12969 ""
097657c3 12970 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 12971 [(set_attr "type" "three")
12972 (set_attr "length" "12")])
1fd4e8c1
RK		 12973
12974(define_insn ""
9ebbca7d 12975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12976 (compare:CC
12977 (and:SI (neg:SI
9ebbca7d
GK		 12978 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12979 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12980 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12981 (const_int 0)))
9ebbca7d 12982 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12983 "TARGET_32BIT"
9ebbca7d
GK		 12984 "@
12985 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12986 #"
12987 [(set_attr "type" "compare")
12988 (set_attr "length" "12,16")])
12989
12990(define_split
12991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12992 (compare:CC
12993 (and:SI (neg:SI
12994 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12995 (match_operand:SI 2 "reg_or_short_operand" "")))
12996 (match_operand:SI 3 "gpc_reg_operand" ""))
12997 (const_int 0)))
12998 (clobber (match_scratch:SI 4 ""))]
683bdff7 12999 "TARGET_32BIT && reload_completed"
9ebbca7d 13000 [(set (match_dup 4)
097657c3
AM		 13001 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13002 (match_dup 3)))
9ebbca7d
GK		 13003 (set (match_dup 0)
13004 (compare:CC (match_dup 4)
13005 (const_int 0)))]
13006 "")
1fd4e8c1
RK		 13007
13008(define_insn ""
097657c3 13009 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 13010 (compare:CC
13011 (and:SI (neg:SI
9ebbca7d
GK		 13012 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13013 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13014 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13015 (const_int 0)))
097657c3
AM		 13016 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13017 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13018 "TARGET_32BIT"
9ebbca7d 13019 "@
097657c3 13020 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 13021 #"
b19003d8 13022 [(set_attr "type" "compare")
9ebbca7d
GK		 13023 (set_attr "length" "12,16")])
13024
13025(define_split
097657c3 13026 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13027 (compare:CC
13028 (and:SI (neg:SI
13029 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13030 (match_operand:SI 2 "reg_or_short_operand" "")))
13031 (match_operand:SI 3 "gpc_reg_operand" ""))
13032 (const_int 0)))
13033 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13034 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13035 "TARGET_32BIT && reload_completed"
097657c3
AM		 13036 [(set (match_dup 0)
13037 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13038 (match_dup 3)))
13039 (set (match_dup 4)
9ebbca7d
GK		 13040 (compare:CC (match_dup 0)
13041 (const_int 0)))]
13042 "")
1fd4e8c1
RK		 13043
13044(define_insn ""
cd2b37d9
RK		 13045 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13046 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13047 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 13048 "TARGET_POWER"
7f340546 13049 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13050 [(set_attr "length" "12")])
1fd4e8c1
RK		 13051
13052(define_insn ""
9ebbca7d 13053 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13054 (compare:CC
9ebbca7d
GK		 13055 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13056 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13057 (const_int 0)))
9ebbca7d 13058 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13059 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13060 "TARGET_POWER"
9ebbca7d
GK		 13061 "@
13062 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13063 #"
29ae5b89 13064 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13065 (set_attr "length" "12,16")])
13066
13067(define_split
13068 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13069 (compare:CC
13070 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13071 (match_operand:SI 2 "reg_or_short_operand" ""))
13072 (const_int 0)))
13073 (set (match_operand:SI 0 "gpc_reg_operand" "")
13074 (lt:SI (match_dup 1) (match_dup 2)))]
13075 "TARGET_POWER && reload_completed"
13076 [(set (match_dup 0)
13077 (lt:SI (match_dup 1) (match_dup 2)))
13078 (set (match_dup 3)
13079 (compare:CC (match_dup 0)
13080 (const_int 0)))]
13081 "")
1fd4e8c1
RK		 13082
13083(define_insn ""
097657c3 13084 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13085 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13086 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13087 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13088 "TARGET_POWER"
097657c3 13089 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13090 [(set_attr "length" "12")])
1fd4e8c1
RK		 13091
13092(define_insn ""
9ebbca7d 13093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13094 (compare:CC
9ebbca7d
GK		 13095 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13096 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13097 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13098 (const_int 0)))
9ebbca7d 13099 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13100 "TARGET_POWER"
9ebbca7d
GK		 13101 "@
13102 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13103 #"
b19003d8 13104 [(set_attr "type" "compare")
9ebbca7d
GK		 13105 (set_attr "length" "12,16")])
13106
13107(define_split
13108 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13109 (compare:CC
13110 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13111 (match_operand:SI 2 "reg_or_short_operand" ""))
13112 (match_operand:SI 3 "gpc_reg_operand" ""))
13113 (const_int 0)))
13114 (clobber (match_scratch:SI 4 ""))]
13115 "TARGET_POWER && reload_completed"
13116 [(set (match_dup 4)
13117 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 13118 (match_dup 3)))
9ebbca7d
GK		 13119 (set (match_dup 0)
13120 (compare:CC (match_dup 4)
13121 (const_int 0)))]
13122 "")
1fd4e8c1
RK		 13123
13124(define_insn ""
097657c3 13125 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13126 (compare:CC
9ebbca7d
GK		 13127 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13128 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13129 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13130 (const_int 0)))
097657c3
AM		 13131 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13132 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13133 "TARGET_POWER"
9ebbca7d 13134 "@
097657c3 13135 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13136 #"
b19003d8 13137 [(set_attr "type" "compare")
9ebbca7d
GK		 13138 (set_attr "length" "12,16")])
13139
13140(define_split
097657c3 13141 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13142 (compare:CC
13143 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13144 (match_operand:SI 2 "reg_or_short_operand" ""))
13145 (match_operand:SI 3 "gpc_reg_operand" ""))
13146 (const_int 0)))
13147 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13148 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13149 "TARGET_POWER && reload_completed"
097657c3 13150 [(set (match_dup 0)
9ebbca7d 13151 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13152 (set (match_dup 4)
9ebbca7d
GK		 13153 (compare:CC (match_dup 0)
13154 (const_int 0)))]
13155 "")
1fd4e8c1
RK		 13156
13157(define_insn ""
cd2b37d9
RK		 13158 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13159 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13160 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13161 "TARGET_POWER"
13162 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13163 [(set_attr "length" "12")])
1fd4e8c1 13164
ce45ef46
DE		 13165(define_insn_and_split "*ltu<mode>"
13166 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13167 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13168 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13169 ""
c0600ecd 13170 "#"
ce45ef46
DE		 13171 ""
13172 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13173 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13174 "")
1fd4e8c1 13175
1e24ce83 13176(define_insn_and_split "*ltu<mode>_compare"
9ebbca7d 13177 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13178 (compare:CC
a2dba291
DE		 13179 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13180 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13181 (const_int 0)))
a2dba291
DE		 13182 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13183 (ltu:P (match_dup 1) (match_dup 2)))]
13184 ""
1e24ce83
DE		 13185 "#"
13186 ""
13187 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13188 (parallel [(set (match_dup 3)
13189 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13190 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13191 "")
1fd4e8c1 13192
a2dba291
DE		 13193(define_insn_and_split "*plus_ltu<mode>"
13194 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13195 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13196 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
1e24ce83 13197 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
a2dba291 13198 ""
c0600ecd 13199 "#"
04fa46cf 13200 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13201 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13202 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13203 "")
1fd4e8c1 13204
1e24ce83 13205(define_insn_and_split "*plus_ltu<mode>_compare"
097657c3 13206 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13207 (compare:CC
1e24ce83
DE		 13208 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13209 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13210 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13211 (const_int 0)))
1e24ce83
DE		 13212 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13213 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13214 ""
13215 "#"
13216 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13217 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13218 (parallel [(set (match_dup 4)
13219 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13220 (const_int 0)))
13221 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13222 "")
1fd4e8c1 13223
ce45ef46
DE		 13224(define_insn "*neg_ltu<mode>"
13225 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13226 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13227 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13228 ""
c0600ecd
DE		 13229 "@
13230 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13231 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
943c15ed 13232 [(set_attr "type" "two")
c0600ecd 13233 (set_attr "length" "8")])
1fd4e8c1
RK		 13234
13235(define_insn ""
cd2b37d9
RK		 13236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13237 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 13238 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13239 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 13240 "TARGET_POWER"
13241 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 13242 [(set_attr "length" "12")])
1fd4e8c1 13243
9ebbca7d
GK		 13244(define_insn ""
13245 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13246 (compare:CC
9ebbca7d
GK		 13247 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13248 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13249 (const_int 0)))
9ebbca7d 13250 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13251 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 13252 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 13253 "TARGET_POWER"
9ebbca7d
GK		 13254 "@
13255 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13256 #"
13257 [(set_attr "type" "compare")
13258 (set_attr "length" "12,16")])
13259
13260(define_split
13261 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13262 (compare:CC
13263 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13264 (match_operand:SI 2 "reg_or_short_operand" ""))
13265 (const_int 0)))
13266 (set (match_operand:SI 0 "gpc_reg_operand" "")
13267 (ge:SI (match_dup 1) (match_dup 2)))
13268 (clobber (match_scratch:SI 3 ""))]
13269 "TARGET_POWER && reload_completed"
13270 [(parallel [(set (match_dup 0)
097657c3
AM		 13271 (ge:SI (match_dup 1) (match_dup 2)))
13272 (clobber (match_dup 3))])
9ebbca7d
GK		 13273 (set (match_dup 4)
13274 (compare:CC (match_dup 0)
13275 (const_int 0)))]
13276 "")
13277
1fd4e8c1 13278(define_insn ""
097657c3 13279 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13280 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13281 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13282 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13283 "TARGET_POWER"
097657c3 13284 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 13285 [(set_attr "length" "12")])
1fd4e8c1
RK		 13286
13287(define_insn ""
9ebbca7d 13288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13289 (compare:CC
9ebbca7d
GK		 13290 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13291 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13292 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13293 (const_int 0)))
9ebbca7d 13294 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13295 "TARGET_POWER"
9ebbca7d
GK		 13296 "@
13297 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13298 #"
b19003d8 13299 [(set_attr "type" "compare")
9ebbca7d
GK		 13300 (set_attr "length" "12,16")])
13301
13302(define_split
13303 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13304 (compare:CC
13305 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13306 (match_operand:SI 2 "reg_or_short_operand" ""))
13307 (match_operand:SI 3 "gpc_reg_operand" ""))
13308 (const_int 0)))
13309 (clobber (match_scratch:SI 4 ""))]
13310 "TARGET_POWER && reload_completed"
13311 [(set (match_dup 4)
13312 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 13313 (match_dup 3)))
9ebbca7d
GK		 13314 (set (match_dup 0)
13315 (compare:CC (match_dup 4)
13316 (const_int 0)))]
13317 "")
1fd4e8c1
RK		 13318
13319(define_insn ""
097657c3 13320 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13321 (compare:CC
9ebbca7d
GK		 13322 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13323 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13324 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13325 (const_int 0)))
097657c3
AM		 13326 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13327 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13328 "TARGET_POWER"
9ebbca7d 13329 "@
097657c3 13330 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 13331 #"
b19003d8 13332 [(set_attr "type" "compare")
9ebbca7d
GK		 13333 (set_attr "length" "12,16")])
13334
13335(define_split
097657c3 13336 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13337 (compare:CC
13338 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13339 (match_operand:SI 2 "reg_or_short_operand" ""))
13340 (match_operand:SI 3 "gpc_reg_operand" ""))
13341 (const_int 0)))
13342 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13343 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13344 "TARGET_POWER && reload_completed"
097657c3 13345 [(set (match_dup 0)
9ebbca7d 13346 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13347 (set (match_dup 4)
9ebbca7d
GK		 13348 (compare:CC (match_dup 0)
13349 (const_int 0)))]
13350 "")
1fd4e8c1
RK		 13351
13352(define_insn ""
cd2b37d9
RK		 13353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13354 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13355 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13356 "TARGET_POWER"
13357 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 13358 [(set_attr "length" "12")])
1fd4e8c1 13359
a2dba291
DE		 13360(define_insn "*geu<mode>"
13361 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13362 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13363 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13364 ""
1fd4e8c1 13365 "@
ca7f5001
RK		 13366 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13367 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 13368 [(set_attr "type" "three")
13369 (set_attr "length" "12")])
1fd4e8c1 13370
a2dba291 13371(define_insn "*geu<mode>_compare"
9ebbca7d 13372 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13373 (compare:CC
a2dba291
DE		 13374 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13375 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13376 (const_int 0)))
a2dba291
DE		 13377 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13378 (geu:P (match_dup 1) (match_dup 2)))]
13379 ""
1fd4e8c1 13380 "@
ca7f5001 13381 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 13382 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13383 #
13384 #"
b19003d8 13385 [(set_attr "type" "compare")
9ebbca7d
GK		 13386 (set_attr "length" "12,12,16,16")])
13387
13388(define_split
13389 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13390 (compare:CC
a2dba291
DE		 13391 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13392 (match_operand:P 2 "reg_or_neg_short_operand" ""))
9ebbca7d 13393 (const_int 0)))
a2dba291
DE		 13394 (set (match_operand:P 0 "gpc_reg_operand" "")
13395 (geu:P (match_dup 1) (match_dup 2)))]
13396 "reload_completed"
9ebbca7d 13397 [(set (match_dup 0)
a2dba291 13398 (geu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 13399 (set (match_dup 3)
13400 (compare:CC (match_dup 0)
13401 (const_int 0)))]
13402 "")
f9562f27 13403
a2dba291
DE		 13404(define_insn "*plus_geu<mode>"
13405 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13406 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13407 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13408 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13409 ""
1fd4e8c1 13410 "@
80103f96
FS		 13411 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13412 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
943c15ed
DE		 13413 [(set_attr "type" "two")
13414 (set_attr "length" "8")])
1fd4e8c1
RK		 13415
13416(define_insn ""
9ebbca7d 13417 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13418 (compare:CC
9ebbca7d
GK		 13419 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13420 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13421 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13422 (const_int 0)))
9ebbca7d 13423 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13424 "TARGET_32BIT"
1fd4e8c1 13425 "@
ca7f5001 13426 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13427 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13428 #
13429 #"
b19003d8 13430 [(set_attr "type" "compare")
9ebbca7d
GK		 13431 (set_attr "length" "8,8,12,12")])
13432
13433(define_split
13434 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13435 (compare:CC
13436 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13437 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13438 (match_operand:SI 3 "gpc_reg_operand" ""))
13439 (const_int 0)))
13440 (clobber (match_scratch:SI 4 ""))]
683bdff7 13441 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13442 [(set (match_dup 4)
13443 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13444 (match_dup 3)))
13445 (set (match_dup 0)
13446 (compare:CC (match_dup 4)
13447 (const_int 0)))]
13448 "")
1fd4e8c1
RK		 13449
13450(define_insn ""
097657c3 13451 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13452 (compare:CC
9ebbca7d
GK		 13453 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13454 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13455 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13456 (const_int 0)))
097657c3
AM		 13457 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13458 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13459 "TARGET_32BIT"
1fd4e8c1 13460 "@
097657c3
AM		 13461 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13462 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 13463 #
13464 #"
b19003d8 13465 [(set_attr "type" "compare")
9ebbca7d
GK		 13466 (set_attr "length" "8,8,12,12")])
13467
13468(define_split
097657c3 13469 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13470 (compare:CC
13471 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13472 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13473 (match_operand:SI 3 "gpc_reg_operand" ""))
13474 (const_int 0)))
13475 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13476 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13477 "TARGET_32BIT && reload_completed"
097657c3 13478 [(set (match_dup 0)
9ebbca7d 13479 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13480 (set (match_dup 4)
9ebbca7d
GK		 13481 (compare:CC (match_dup 0)
13482 (const_int 0)))]
13483 "")
1fd4e8c1 13484
a2dba291
DE		 13485(define_insn "*neg_geu<mode>"
13486 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13487 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13488 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13489 ""
1fd4e8c1 13490 "@
ca7f5001 13491 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 13492 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
943c15ed
DE		 13493 [(set_attr "type" "three")
13494 (set_attr "length" "12")])
1fd4e8c1 13495
a2dba291
DE		 13496(define_insn "*and_neg_geu<mode>"
13497 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13498 (and:P (neg:P
13499 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13500 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13501 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13502 ""
1fd4e8c1 13503 "@
097657c3
AM		 13504 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13505 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 13506 [(set_attr "type" "three")
13507 (set_attr "length" "12")])
1fd4e8c1
RK		 13508
13509(define_insn ""
9ebbca7d 13510 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13511 (compare:CC
13512 (and:SI (neg:SI
9ebbca7d
GK		 13513 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13514 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13515 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13516 (const_int 0)))
9ebbca7d 13517 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13518 "TARGET_32BIT"
1fd4e8c1 13519 "@
ca7f5001 13520 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 13521 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13522 #
13523 #"
b19003d8 13524 [(set_attr "type" "compare")
9ebbca7d
GK		 13525 (set_attr "length" "12,12,16,16")])
13526
13527(define_split
13528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13529 (compare:CC
13530 (and:SI (neg:SI
13531 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13532 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13533 (match_operand:SI 3 "gpc_reg_operand" ""))
13534 (const_int 0)))
13535 (clobber (match_scratch:SI 4 ""))]
683bdff7 13536 "TARGET_32BIT && reload_completed"
9ebbca7d 13537 [(set (match_dup 4)
097657c3
AM		 13538 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13539 (match_dup 3)))
9ebbca7d
GK		 13540 (set (match_dup 0)
13541 (compare:CC (match_dup 4)
13542 (const_int 0)))]
13543 "")
1fd4e8c1
RK		 13544
13545(define_insn ""
097657c3 13546 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13547 (compare:CC
13548 (and:SI (neg:SI
9ebbca7d
GK		 13549 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13550 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13551 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13552 (const_int 0)))
097657c3
AM		 13553 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13554 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13555 "TARGET_32BIT"
1fd4e8c1 13556 "@
097657c3
AM		 13557 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13558 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 13559 #
13560 #"
b19003d8 13561 [(set_attr "type" "compare")
9ebbca7d
GK		 13562 (set_attr "length" "12,12,16,16")])
13563
13564(define_split
097657c3 13565 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13566 (compare:CC
13567 (and:SI (neg:SI
13568 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13569 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13570 (match_operand:SI 3 "gpc_reg_operand" ""))
13571 (const_int 0)))
13572 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13573 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13574 "TARGET_32BIT && reload_completed"
097657c3 13575 [(set (match_dup 0)
9ebbca7d 13576 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 13577 (set (match_dup 4)
9ebbca7d
GK		 13578 (compare:CC (match_dup 0)
13579 (const_int 0)))]
13580 "")
1fd4e8c1 13581
1fd4e8c1 13582(define_insn ""
cd2b37d9
RK		 13583 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13584 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13585 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 13586 "TARGET_POWER"
13587 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13588 [(set_attr "length" "12")])
1fd4e8c1
RK		 13589
13590(define_insn ""
9ebbca7d 13591 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13592 (compare:CC
9ebbca7d
GK		 13593 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13594 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 13595 (const_int 0)))
9ebbca7d 13596 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13597 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13598 "TARGET_POWER"
9ebbca7d
GK		 13599 "@
13600 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13601 #"
29ae5b89 13602 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13603 (set_attr "length" "12,16")])
13604
13605(define_split
13606 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13607 (compare:CC
13608 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13609 (match_operand:SI 2 "reg_or_short_operand" ""))
13610 (const_int 0)))
13611 (set (match_operand:SI 0 "gpc_reg_operand" "")
13612 (gt:SI (match_dup 1) (match_dup 2)))]
13613 "TARGET_POWER && reload_completed"
13614 [(set (match_dup 0)
13615 (gt:SI (match_dup 1) (match_dup 2)))
13616 (set (match_dup 3)
13617 (compare:CC (match_dup 0)
13618 (const_int 0)))]
13619 "")
1fd4e8c1 13620
d0515b39 13621(define_insn "*plus_gt0<mode>"
a2dba291
DE		 13622 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13623 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13624 (const_int 0))
13625 (match_operand:P 2 "gpc_reg_operand" "r")))]
13626 ""
80103f96 13627 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
943c15ed
DE		 13628 [(set_attr "type" "three")
13629 (set_attr "length" "12")])
1fd4e8c1
RK		 13630
13631(define_insn ""
9ebbca7d 13632 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13633 (compare:CC
9ebbca7d 13634 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13635 (const_int 0))
9ebbca7d 13636 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 13637 (const_int 0)))
9ebbca7d 13638 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 13639 "TARGET_32BIT"
9ebbca7d
GK		 13640 "@
13641 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13642 #"
b19003d8 13643 [(set_attr "type" "compare")
9ebbca7d
GK		 13644 (set_attr "length" "12,16")])
13645
13646(define_split
13647 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13648 (compare:CC
13649 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13650 (const_int 0))
13651 (match_operand:SI 2 "gpc_reg_operand" ""))
13652 (const_int 0)))
13653 (clobber (match_scratch:SI 3 ""))]
683bdff7 13654 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13655 [(set (match_dup 3)
13656 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13657 (match_dup 2)))
13658 (set (match_dup 0)
13659 (compare:CC (match_dup 3)
13660 (const_int 0)))]
13661 "")
1fd4e8c1 13662
f9562f27 13663(define_insn ""
9ebbca7d 13664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 13665 (compare:CC
9ebbca7d 13666 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13667 (const_int 0))
9ebbca7d 13668 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13669 (const_int 0)))
9ebbca7d 13670 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 13671 "TARGET_64BIT"
9ebbca7d
GK		 13672 "@
13673 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13674 #"
f9562f27 13675 [(set_attr "type" "compare")
9ebbca7d
GK		 13676 (set_attr "length" "12,16")])
13677
13678(define_split
13679 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13680 (compare:CC
13681 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13682 (const_int 0))
13683 (match_operand:DI 2 "gpc_reg_operand" ""))
13684 (const_int 0)))
13685 (clobber (match_scratch:DI 3 ""))]
683bdff7 13686 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13687 [(set (match_dup 3)
13688 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 13689 (match_dup 2)))
9ebbca7d
GK		 13690 (set (match_dup 0)
13691 (compare:CC (match_dup 3)
13692 (const_int 0)))]
13693 "")
f9562f27 13694
1fd4e8c1 13695(define_insn ""
097657c3 13696 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 13697 (compare:CC
13698 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13699 (const_int 0))
13700 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13701 (const_int 0)))
097657c3
AM		 13702 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13703 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13704 "TARGET_32BIT"
9ebbca7d 13705 "@
097657c3 13706 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 13707 #"
13708 [(set_attr "type" "compare")
13709 (set_attr "length" "12,16")])
13710
13711(define_split
097657c3 13712 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 13713 (compare:CC
9ebbca7d 13714 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 13715 (const_int 0))
9ebbca7d 13716 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 13717 (const_int 0)))
9ebbca7d 13718 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13719 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13720 "TARGET_32BIT && reload_completed"
097657c3 13721 [(set (match_dup 0)
9ebbca7d 13722 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13723 (set (match_dup 3)
9ebbca7d
GK		 13724 (compare:CC (match_dup 0)
13725 (const_int 0)))]
13726 "")
1fd4e8c1 13727
f9562f27 13728(define_insn ""
097657c3 13729 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13730 (compare:CC
9ebbca7d 13731 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13732 (const_int 0))
9ebbca7d 13733 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13734 (const_int 0)))
097657c3
AM		 13735 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13736 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13737 "TARGET_64BIT"
9ebbca7d 13738 "@
097657c3 13739 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 13740 #"
f9562f27 13741 [(set_attr "type" "compare")
9ebbca7d
GK		 13742 (set_attr "length" "12,16")])
13743
13744(define_split
097657c3 13745 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13746 (compare:CC
13747 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13748 (const_int 0))
13749 (match_operand:DI 2 "gpc_reg_operand" ""))
13750 (const_int 0)))
13751 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13752 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13753 "TARGET_64BIT && reload_completed"
097657c3 13754 [(set (match_dup 0)
9ebbca7d 13755 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13756 (set (match_dup 3)
9ebbca7d
GK		 13757 (compare:CC (match_dup 0)
13758 (const_int 0)))]
13759 "")
f9562f27 13760
1fd4e8c1 13761(define_insn ""
097657c3 13762 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13763 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13764 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 13765 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13766 "TARGET_POWER"
097657c3 13767 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13768 [(set_attr "length" "12")])
1fd4e8c1
RK		 13769
13770(define_insn ""
9ebbca7d 13771 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13772 (compare:CC
9ebbca7d
GK		 13773 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13774 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13775 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13776 (const_int 0)))
9ebbca7d 13777 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13778 "TARGET_POWER"
9ebbca7d
GK		 13779 "@
13780 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13781 #"
b19003d8 13782 [(set_attr "type" "compare")
9ebbca7d
GK		 13783 (set_attr "length" "12,16")])
13784
13785(define_split
13786 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13787 (compare:CC
13788 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13789 (match_operand:SI 2 "reg_or_short_operand" ""))
13790 (match_operand:SI 3 "gpc_reg_operand" ""))
13791 (const_int 0)))
13792 (clobber (match_scratch:SI 4 ""))]
13793 "TARGET_POWER && reload_completed"
13794 [(set (match_dup 4)
097657c3 13795 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 13796 (set (match_dup 0)
13797 (compare:CC (match_dup 4)
13798 (const_int 0)))]
13799 "")
1fd4e8c1
RK		 13800
13801(define_insn ""
097657c3 13802 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13803 (compare:CC
9ebbca7d
GK		 13804 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13805 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13806 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13807 (const_int 0)))
097657c3
AM		 13808 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13809 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13810 "TARGET_POWER"
9ebbca7d 13811 "@
097657c3 13812 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13813 #"
b19003d8 13814 [(set_attr "type" "compare")
9ebbca7d
GK		 13815 (set_attr "length" "12,16")])
13816
13817(define_split
097657c3 13818 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13819 (compare:CC
13820 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13821 (match_operand:SI 2 "reg_or_short_operand" ""))
13822 (match_operand:SI 3 "gpc_reg_operand" ""))
13823 (const_int 0)))
13824 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13825 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13826 "TARGET_POWER && reload_completed"
097657c3 13827 [(set (match_dup 0)
9ebbca7d 13828 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13829 (set (match_dup 4)
9ebbca7d
GK		 13830 (compare:CC (match_dup 0)
13831 (const_int 0)))]
13832 "")
1fd4e8c1 13833
1fd4e8c1 13834(define_insn ""
cd2b37d9
RK		 13835 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13836 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13837 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 13838 "TARGET_POWER"
13839 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13840 [(set_attr "length" "12")])
1fd4e8c1 13841
ce45ef46
DE		 13842(define_insn_and_split "*gtu<mode>"
13843 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13844 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13845 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13846 ""
c0600ecd 13847 "#"
ce45ef46
DE		 13848 ""
13849 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13850 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13851 "")
f9562f27 13852
1e24ce83 13853(define_insn_and_split "*gtu<mode>_compare"
9ebbca7d 13854 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13855 (compare:CC
a2dba291
DE		 13856 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13857 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13858 (const_int 0)))
a2dba291
DE		 13859 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13860 (gtu:P (match_dup 1) (match_dup 2)))]
13861 ""
1e24ce83
DE		 13862 "#"
13863 ""
13864 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13865 (parallel [(set (match_dup 3)
13866 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13867 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13868 "")
f9562f27 13869
1e24ce83 13870(define_insn_and_split "*plus_gtu<mode>"
a2dba291
DE		 13871 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13872 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13873 (match_operand:P 2 "reg_or_short_operand" "rI"))
13874 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13875 ""
c0600ecd 13876 "#"
04fa46cf 13877 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13878 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13879 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13880 "")
f9562f27 13881
1e24ce83 13882(define_insn_and_split "*plus_gtu<mode>_compare"
097657c3 13883 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13884 (compare:CC
1e24ce83
DE		 13885 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13886 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13887 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13888 (const_int 0)))
1e24ce83
DE		 13889 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13890 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13891 ""
13892 "#"
13893 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13894 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13895 (parallel [(set (match_dup 4)
13896 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13897 (const_int 0)))
13898 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13899 "")
f9562f27 13900
ce45ef46
DE		 13901(define_insn "*neg_gtu<mode>"
13902 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13903 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13904 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13905 ""
ca7f5001 13906 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
943c15ed 13907 [(set_attr "type" "two")
c0600ecd 13908 (set_attr "length" "8")])
f9562f27 13909
1fd4e8c1
RK		 13910\f
13911;; Define both directions of branch and return. If we need a reload
13912;; register, we'd rather use CR0 since it is much easier to copy a
13913;; register CC value to there.
13914
13915(define_insn ""
13916 [(set (pc)
13917 (if_then_else (match_operator 1 "branch_comparison_operator"
13918 [(match_operand 2
b54cf83a 13919 "cc_reg_operand" "y")
1fd4e8c1
RK		 13920 (const_int 0)])
13921 (label_ref (match_operand 0 "" ""))
13922 (pc)))]
13923 ""
b19003d8
RK		 13924 "*
13925{
12a4e8c5 13926 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 13927}"
13928 [(set_attr "type" "branch")])
13929
1fd4e8c1
RK		 13930(define_insn ""
13931 [(set (pc)
13932 (if_then_else (match_operator 0 "branch_comparison_operator"
13933 [(match_operand 1
b54cf83a 13934 "cc_reg_operand" "y")
1fd4e8c1
RK		 13935 (const_int 0)])
13936 (return)
13937 (pc)))]
13938 "direct_return ()"
12a4e8c5
GK		 13939 "*
13940{
13941 return output_cbranch (operands[0], NULL, 0, insn);
13942}"
9c6fdb46 13943 [(set_attr "type" "jmpreg")
39a10a29 13944 (set_attr "length" "4")])
1fd4e8c1
RK		 13945
13946(define_insn ""
13947 [(set (pc)
13948 (if_then_else (match_operator 1 "branch_comparison_operator"
13949 [(match_operand 2
b54cf83a 13950 "cc_reg_operand" "y")
1fd4e8c1
RK		 13951 (const_int 0)])
13952 (pc)
13953 (label_ref (match_operand 0 "" ""))))]
13954 ""
b19003d8
RK		 13955 "*
13956{
12a4e8c5 13957 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 13958}"
13959 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13960
13961(define_insn ""
13962 [(set (pc)
13963 (if_then_else (match_operator 0 "branch_comparison_operator"
13964 [(match_operand 1
b54cf83a 13965 "cc_reg_operand" "y")
1fd4e8c1
RK		 13966 (const_int 0)])
13967 (pc)
13968 (return)))]
13969 "direct_return ()"
12a4e8c5
GK		 13970 "*
13971{
13972 return output_cbranch (operands[0], NULL, 1, insn);
13973}"
9c6fdb46 13974 [(set_attr "type" "jmpreg")
39a10a29
GK		 13975 (set_attr "length" "4")])
13976
13977;; Logic on condition register values.
13978
13979; This pattern matches things like
13980; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13981; (eq:SI (reg:CCFP 68) (const_int 0)))
13982; (const_int 1)))
13983; which are generated by the branch logic.
b54cf83a 13984; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29 13985
423c1189 13986(define_insn "*cceq_ior_compare"
b54cf83a 13987 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13988 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 13989 [(match_operator:SI 2
39a10a29
GK		 13990 "branch_positive_comparison_operator"
13991 [(match_operand 3
b54cf83a 13992 "cc_reg_operand" "y,y")
39a10a29 13993 (const_int 0)])
b54cf83a 13994 (match_operator:SI 4
39a10a29
GK		 13995 "branch_positive_comparison_operator"
13996 [(match_operand 5
b54cf83a 13997 "cc_reg_operand" "0,y")
39a10a29
GK		 13998 (const_int 0)])])
13999 (const_int 1)))]
24fab1d3 14000 ""
39a10a29 14001 "cr%q1 %E0,%j2,%j4"
b54cf83a 14002 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 14003
14004; Why is the constant -1 here, but 1 in the previous pattern?
14005; Because ~1 has all but the low bit set.
14006(define_insn ""
b54cf83a 14007 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 14008 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 14009 [(not:SI (match_operator:SI 2
39a10a29
GK		 14010 "branch_positive_comparison_operator"
14011 [(match_operand 3
b54cf83a 14012 "cc_reg_operand" "y,y")
39a10a29
GK		 14013 (const_int 0)]))
14014 (match_operator:SI 4
14015 "branch_positive_comparison_operator"
14016 [(match_operand 5
b54cf83a 14017 "cc_reg_operand" "0,y")
39a10a29
GK		 14018 (const_int 0)])])
14019 (const_int -1)))]
14020 ""
14021 "cr%q1 %E0,%j2,%j4"
b54cf83a 14022 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29 14023
423c1189 14024(define_insn "*cceq_rev_compare"
b54cf83a 14025 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 14026 (compare:CCEQ (match_operator:SI 1
39a10a29 14027 "branch_positive_comparison_operator"
6c873122 14028 [(match_operand 2
b54cf83a 14029 "cc_reg_operand" "0,y")
39a10a29
GK		 14030 (const_int 0)])
14031 (const_int 0)))]
423c1189 14032 ""
251b3667 14033 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 14034 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 14035
14036;; If we are comparing the result of two comparisons, this can be done
14037;; using creqv or crxor.
14038
14039(define_insn_and_split ""
14040 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14041 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14042 [(match_operand 2 "cc_reg_operand" "y")
14043 (const_int 0)])
14044 (match_operator 3 "branch_comparison_operator"
14045 [(match_operand 4 "cc_reg_operand" "y")
14046 (const_int 0)])))]
14047 ""
14048 "#"
14049 ""
14050 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14051 (match_dup 5)))]
14052 "
14053{
14054 int positive_1, positive_2;
14055
364849ee
DE		 14056 positive_1 = branch_positive_comparison_operator (operands[1],
14057 GET_MODE (operands[1]));
14058 positive_2 = branch_positive_comparison_operator (operands[3],
14059 GET_MODE (operands[3]));
39a10a29
GK		 14060
14061 if (! positive_1)
1c563bed 14062 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
0f4c242b
KH		 14063 GET_CODE (operands[1])),
14064 SImode,
14065 operands[2], const0_rtx);
39a10a29 14066 else if (GET_MODE (operands[1]) != SImode)
0f4c242b
KH		 14067 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14068 operands[2], const0_rtx);
39a10a29
GK		 14069
14070 if (! positive_2)
1c563bed 14071 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
0f4c242b
KH		 14072 GET_CODE (operands[3])),
14073 SImode,
14074 operands[4], const0_rtx);
39a10a29 14075 else if (GET_MODE (operands[3]) != SImode)
0f4c242b
KH		 14076 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14077 operands[4], const0_rtx);
39a10a29
GK		 14078
14079 if (positive_1 == positive_2)
251b3667
DE		 14080 {
14081 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14082 operands[5] = constm1_rtx;
14083 }
14084 else
14085 {
14086 operands[5] = const1_rtx;
14087 }
39a10a29 14088}")
1fd4e8c1
RK		 14089
14090;; Unconditional branch and return.
14091
14092(define_insn "jump"
14093 [(set (pc)
14094 (label_ref (match_operand 0 "" "")))]
14095 ""
b7ff3d82
DE		 14096 "b %l0"
14097 [(set_attr "type" "branch")])
1fd4e8c1
RK		 14098
14099(define_insn "return"
14100 [(return)]
14101 "direct_return ()"
324e52cc
TG		 14102 "{br|blr}"
14103 [(set_attr "type" "jmpreg")])
1fd4e8c1 14104
0ad91047 14105(define_expand "indirect_jump"
4ae234b0 14106 [(set (pc) (match_operand 0 "register_operand" ""))])
0ad91047 14107
4ae234b0
GK		 14108(define_insn "*indirect_jump<mode>"
14109 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14110 ""
b92b324d
DE		 14111 "@
14112 bctr
14113 {br|blr}"
324e52cc 14114 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14115
14116;; Table jump for switch statements:
14117(define_expand "tablejump"
e6ca2c17
DE		 14118 [(use (match_operand 0 "" ""))
14119 (use (label_ref (match_operand 1 "" "")))]
14120 ""
14121 "
14122{
14123 if (TARGET_32BIT)
14124 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14125 else
14126 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14127 DONE;
14128}")
14129
14130(define_expand "tablejumpsi"
1fd4e8c1
RK		 14131 [(set (match_dup 3)
14132 (plus:SI (match_operand:SI 0 "" "")
14133 (match_dup 2)))
14134 (parallel [(set (pc) (match_dup 3))
14135 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14136 "TARGET_32BIT"
1fd4e8c1
RK		 14137 "
14138{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 14139 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 14140 operands[3] = gen_reg_rtx (SImode);
14141}")
14142
e6ca2c17 14143(define_expand "tablejumpdi"
6ae08853 14144 [(set (match_dup 4)
e42ac3de 14145 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
9ebbca7d
GK		 14146 (set (match_dup 3)
14147 (plus:DI (match_dup 4)
e6ca2c17
DE		 14148 (match_dup 2)))
14149 (parallel [(set (pc) (match_dup 3))
14150 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14151 "TARGET_64BIT"
e6ca2c17 14152 "
9ebbca7d 14153{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 14154 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 14155 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 14156}")
14157
ce45ef46 14158(define_insn "*tablejump<mode>_internal1"
1fd4e8c1 14159 [(set (pc)
4ae234b0 14160 (match_operand:P 0 "register_operand" "c,*l"))
1fd4e8c1 14161 (use (label_ref (match_operand 1 "" "")))]
4ae234b0 14162 ""
c859cda6
DJ		 14163 "@
14164 bctr
14165 {br|blr}"
a6845123 14166 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14167
14168(define_insn "nop"
14169 [(const_int 0)]
14170 ""
ca7f5001 14171 "{cror 0,0,0|nop}")
1fd4e8c1 14172\f
7e69e155 14173;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 14174;; so loop.c knows what to generate.
14175
5527bf14
RH		 14176(define_expand "doloop_end"
14177 [(use (match_operand 0 "" "")) ; loop pseudo
14178 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14179 (use (match_operand 2 "" "")) ; max iterations
14180 (use (match_operand 3 "" "")) ; loop level
14181 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 14182 ""
14183 "
14184{
5527bf14
RH		 14185 /* Only use this on innermost loops. */
14186 if (INTVAL (operands[3]) > 1)
14187 FAIL;
683bdff7 14188 if (TARGET_64BIT)
5527bf14
RH		 14189 {
14190 if (GET_MODE (operands[0]) != DImode)
14191 FAIL;
14192 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14193 }
0ad91047 14194 else
5527bf14
RH		 14195 {
14196 if (GET_MODE (operands[0]) != SImode)
14197 FAIL;
14198 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14199 }
0ad91047
DE		 14200 DONE;
14201}")
14202
4ae234b0 14203(define_expand "ctr<mode>"
3cb999d8 14204 [(parallel [(set (pc)
4ae234b0 14205 (if_then_else (ne (match_operand:P 0 "register_operand" "")
3cb999d8
DE		 14206 (const_int 1))
14207 (label_ref (match_operand 1 "" ""))
14208 (pc)))
b6c9286a 14209 (set (match_dup 0)
4ae234b0 14210 (plus:P (match_dup 0)
b6c9286a 14211 (const_int -1)))
5f81043f 14212 (clobber (match_scratch:CC 2 ""))
4ae234b0
GK		 14213 (clobber (match_scratch:P 3 ""))])]
14214 ""
61c07d3c 14215 "")
c225ba7b 14216
1fd4e8c1
RK		 14217;; We need to be able to do this for any operand, including MEM, or we
14218;; will cause reload to blow up since we don't allow output reloads on
7e69e155 14219;; JUMP_INSNs.
0ad91047 14220;; For the length attribute to be calculated correctly, the
5f81043f
RK		 14221;; label MUST be operand 0.
14222
4ae234b0 14223(define_insn "*ctr<mode>_internal1"
0ad91047 14224 [(set (pc)
4ae234b0 14225 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14226 (const_int 1))
14227 (label_ref (match_operand 0 "" ""))
14228 (pc)))
4ae234b0
GK		 14229 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14230 (plus:P (match_dup 1)
0ad91047 14231 (const_int -1)))
43b68ce5 14232 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14233 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14234 ""
0ad91047
DE		 14235 "*
14236{
14237 if (which_alternative != 0)
14238 return \"#\";
856a6884 14239 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14240 return \"{bdn|bdnz} %l0\";
14241 else
f607bc57 14242 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14243}"
14244 [(set_attr "type" "branch")
5a195cb5 14245 (set_attr "length" "*,12,16,16")])
0ad91047 14246
4ae234b0 14247(define_insn "*ctr<mode>_internal2"
0ad91047 14248 [(set (pc)
4ae234b0 14249 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14250 (const_int 1))
14251 (pc)
14252 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14253 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14254 (plus:P (match_dup 1)
0ad91047 14255 (const_int -1)))
43b68ce5 14256 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14257 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14258 ""
5f81043f
RK		 14259 "*
14260{
14261 if (which_alternative != 0)
14262 return \"#\";
856a6884 14263 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14264 return \"bdz %l0\";
14265 else
f607bc57 14266 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14267}"
14268 [(set_attr "type" "branch")
5a195cb5 14269 (set_attr "length" "*,12,16,16")])
5f81043f 14270
0ad91047
DE		 14271;; Similar but use EQ
14272
4ae234b0 14273(define_insn "*ctr<mode>_internal5"
5f81043f 14274 [(set (pc)
4ae234b0 14275 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14276 (const_int 1))
a6845123 14277 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14278 (pc)))
4ae234b0
GK		 14279 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14280 (plus:P (match_dup 1)
0ad91047 14281 (const_int -1)))
43b68ce5 14282 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14283 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14284 ""
0ad91047
DE		 14285 "*
14286{
14287 if (which_alternative != 0)
14288 return \"#\";
856a6884 14289 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14290 return \"bdz %l0\";
14291 else
f607bc57 14292 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14293}"
14294 [(set_attr "type" "branch")
5a195cb5 14295 (set_attr "length" "*,12,16,16")])
0ad91047 14296
4ae234b0 14297(define_insn "*ctr<mode>_internal6"
0ad91047 14298 [(set (pc)
4ae234b0 14299 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14300 (const_int 1))
14301 (pc)
14302 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14303 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14304 (plus:P (match_dup 1)
0ad91047 14305 (const_int -1)))
43b68ce5 14306 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14307 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14308 ""
5f81043f
RK		 14309 "*
14310{
14311 if (which_alternative != 0)
14312 return \"#\";
856a6884 14313 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14314 return \"{bdn|bdnz} %l0\";
14315 else
f607bc57 14316 return \"bdz $+8\;b %l0\";
5f81043f
RK		 14317}"
14318 [(set_attr "type" "branch")
5a195cb5 14319 (set_attr "length" "*,12,16,16")])
5f81043f 14320
0ad91047
DE		 14321;; Now the splitters if we could not allocate the CTR register
14322
1fd4e8c1
RK		 14323(define_split
14324 [(set (pc)
14325 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14326 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14327 (const_int 1)])
61c07d3c
DE		 14328 (match_operand 5 "" "")
14329 (match_operand 6 "" "")))
4ae234b0
GK		 14330 (set (match_operand:P 0 "gpc_reg_operand" "")
14331 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14332 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14333 (clobber (match_scratch:P 4 ""))]
14334 "reload_completed"
0ad91047 14335 [(parallel [(set (match_dup 3)
4ae234b0 14336 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14337 (const_int -1))
14338 (const_int 0)))
14339 (set (match_dup 0)
4ae234b0 14340 (plus:P (match_dup 1)
0ad91047 14341 (const_int -1)))])
61c07d3c
DE		 14342 (set (pc) (if_then_else (match_dup 7)
14343 (match_dup 5)
14344 (match_dup 6)))]
0ad91047 14345 "
0f4c242b
KH		 14346{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14347 operands[3], const0_rtx); }")
0ad91047
DE		 14348
14349(define_split
14350 [(set (pc)
14351 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14352 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14353 (const_int 1)])
61c07d3c
DE		 14354 (match_operand 5 "" "")
14355 (match_operand 6 "" "")))
4ae234b0
GK		 14356 (set (match_operand:P 0 "nonimmediate_operand" "")
14357 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14358 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14359 (clobber (match_scratch:P 4 ""))]
14360 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
0ad91047 14361 [(parallel [(set (match_dup 3)
4ae234b0 14362 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14363 (const_int -1))
14364 (const_int 0)))
14365 (set (match_dup 4)
4ae234b0 14366 (plus:P (match_dup 1)
0ad91047
DE		 14367 (const_int -1)))])
14368 (set (match_dup 0)
14369 (match_dup 4))
61c07d3c
DE		 14370 (set (pc) (if_then_else (match_dup 7)
14371 (match_dup 5)
14372 (match_dup 6)))]
0ad91047 14373 "
0f4c242b
KH		 14374{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14375 operands[3], const0_rtx); }")
e0cd0770
JC		 14376\f
14377(define_insn "trap"
14378 [(trap_if (const_int 1) (const_int 0))]
14379 ""
44cd321e
PS		 14380 "{t 31,0,0|trap}"
14381 [(set_attr "type" "trap")])
e0cd0770
JC		 14382
14383(define_expand "conditional_trap"
14384 [(trap_if (match_operator 0 "trap_comparison_operator"
14385 [(match_dup 2) (match_dup 3)])
14386 (match_operand 1 "const_int_operand" ""))]
14387 ""
14388 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14389 operands[2] = rs6000_compare_op0;
14390 operands[3] = rs6000_compare_op1;")
14391
14392(define_insn ""
14393 [(trap_if (match_operator 0 "trap_comparison_operator"
4ae234b0
GK		 14394 [(match_operand:GPR 1 "register_operand" "r")
14395 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
e0cd0770
JC		 14396 (const_int 0))]
14397 ""
44cd321e
PS		 14398 "{t|t<wd>}%V0%I2 %1,%2"
14399 [(set_attr "type" "trap")])
9ebbca7d
GK		 14400\f
14401;; Insns related to generating the function prologue and epilogue.
14402
14403(define_expand "prologue"
14404 [(use (const_int 0))]
14405 "TARGET_SCHED_PROLOG"
14406 "
14407{
14408 rs6000_emit_prologue ();
14409 DONE;
14410}")
14411
2c4a9cff
DE		 14412(define_insn "*movesi_from_cr_one"
14413 [(match_parallel 0 "mfcr_operation"
14414 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14415 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14416 (match_operand 3 "immediate_operand" "n")]
14417 UNSPEC_MOVESI_FROM_CR))])]
14418 "TARGET_MFCRF"
14419 "*
14420{
14421 int mask = 0;
14422 int i;
14423 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14424 {
14425 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14426 operands[4] = GEN_INT (mask);
14427 output_asm_insn (\"mfcr %1,%4\", operands);
14428 }
14429 return \"\";
14430}"
14431 [(set_attr "type" "mfcrf")])
14432
9ebbca7d
GK		 14433(define_insn "movesi_from_cr"
14434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1de43f85
DE		 14435 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14436 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14437 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14438 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
615158e2 14439 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 14440 ""
309323c2 14441 "mfcr %0"
b54cf83a 14442 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14443
14444(define_insn "*stmw"
e033a023
DE		 14445 [(match_parallel 0 "stmw_operation"
14446 [(set (match_operand:SI 1 "memory_operand" "=m")
14447 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14448 "TARGET_MULTIPLE"
9c6fdb46
DE		 14449 "{stm|stmw} %2,%1"
14450 [(set_attr "type" "store_ux")])
6ae08853 14451
4ae234b0 14452(define_insn "*save_fpregs_<mode>"
85d346f1 14453 [(match_parallel 0 "any_parallel_operand"
e65a3857
DE		 14454 [(clobber (reg:P 65))
14455 (use (match_operand:P 1 "call_operand" "s"))
14456 (set (match_operand:DF 2 "memory_operand" "=m")
14457 (match_operand:DF 3 "gpc_reg_operand" "f"))])]
4ae234b0 14458 ""
e65a3857 14459 "bl %z1"
e033a023
DE		 14460 [(set_attr "type" "branch")
14461 (set_attr "length" "4")])
9ebbca7d
GK		 14462
14463; These are to explain that changes to the stack pointer should
14464; not be moved over stores to stack memory.
14465(define_insn "stack_tie"
14466 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 14467 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 14468 ""
14469 ""
14470 [(set_attr "length" "0")])
14471
14472
14473(define_expand "epilogue"
14474 [(use (const_int 0))]
14475 "TARGET_SCHED_PROLOG"
14476 "
14477{
14478 rs6000_emit_epilogue (FALSE);
14479 DONE;
14480}")
14481
14482; On some processors, doing the mtcrf one CC register at a time is
14483; faster (like on the 604e). On others, doing them all at once is
14484; faster; for instance, on the 601 and 750.
14485
14486(define_expand "movsi_to_cr_one"
e42ac3de
RS		 14487 [(set (match_operand:CC 0 "cc_reg_operand" "")
14488 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
615158e2 14489 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 14490 ""
14491 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14492
14493(define_insn "*movsi_to_cr"
35aba846
DE		 14494 [(match_parallel 0 "mtcrf_operation"
14495 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14496 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14497 (match_operand 3 "immediate_operand" "n")]
615158e2 14498 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 14499 ""
e35b9579
GK		 14500 "*
14501{
14502 int mask = 0;
14503 int i;
14504 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14505 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14506 operands[4] = GEN_INT (mask);
14507 return \"mtcrf %4,%2\";
309323c2 14508}"
b54cf83a 14509 [(set_attr "type" "mtcr")])
9ebbca7d 14510
b54cf83a 14511(define_insn "*mtcrfsi"
309323c2
DE		 14512 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14513 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 14514 (match_operand 2 "immediate_operand" "n")]
14515 UNSPEC_MOVESI_TO_CR))]
6ae08853 14516 "GET_CODE (operands[0]) == REG
309323c2
DE		 14517 && CR_REGNO_P (REGNO (operands[0]))
14518 && GET_CODE (operands[2]) == CONST_INT
14519 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14520 "mtcrf %R0,%1"
b54cf83a 14521 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14522
14523; The load-multiple instructions have similar properties.
14524; Note that "load_multiple" is a name known to the machine-independent
9c6fdb46 14525; code that actually corresponds to the PowerPC load-string.
9ebbca7d
GK		 14526
14527(define_insn "*lmw"
35aba846
DE		 14528 [(match_parallel 0 "lmw_operation"
14529 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14530 (match_operand:SI 2 "memory_operand" "m"))])]
14531 "TARGET_MULTIPLE"
9c6fdb46
DE		 14532 "{lm|lmw} %1,%2"
14533 [(set_attr "type" "load_ux")])
6ae08853 14534
4ae234b0 14535(define_insn "*return_internal_<mode>"
e35b9579 14536 [(return)
4ae234b0
GK		 14537 (use (match_operand:P 0 "register_operand" "lc"))]
14538 ""
cccf3bdc 14539 "b%T0"
9ebbca7d
GK		 14540 [(set_attr "type" "jmpreg")])
14541
14542; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
85d346f1 14543; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
9ebbca7d 14544
4ae234b0 14545(define_insn "*return_and_restore_fpregs_<mode>"
85d346f1 14546 [(match_parallel 0 "any_parallel_operand"
e35b9579 14547 [(return)
e65a3857
DE		 14548 (use (reg:P 65))
14549 (use (match_operand:P 1 "call_operand" "s"))
14550 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
14551 (match_operand:DF 3 "memory_operand" "m"))])]
4ae234b0 14552 ""
e65a3857 14553 "b %z1")
9ebbca7d 14554
83720594
RH		 14555; This is used in compiling the unwind routines.
14556(define_expand "eh_return"
34dc173c 14557 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 14558 ""
14559 "
14560{
83720594 14561 if (TARGET_32BIT)
34dc173c 14562 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 14563 else
34dc173c 14564 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 14565 DONE;
14566}")
14567
83720594 14568; We can't expand this before we know where the link register is stored.
4ae234b0
GK		 14569(define_insn "eh_set_lr_<mode>"
14570 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
615158e2 14571 UNSPECV_EH_RR)
4ae234b0
GK		 14572 (clobber (match_scratch:P 1 "=&b"))]
14573 ""
83720594 14574 "#")
9ebbca7d
GK		 14575
14576(define_split
615158e2 14577 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 14578 (clobber (match_scratch 1 ""))]
14579 "reload_completed"
14580 [(const_int 0)]
9ebbca7d
GK		 14581 "
14582{
d1d0c603 14583 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 14584 DONE;
14585}")
0ac081f6 14586
01a2ccd0 14587(define_insn "prefetch"
3256a76e 14588 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
6041bf2f
DE		 14589 (match_operand:SI 1 "const_int_operand" "n")
14590 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14591 "TARGET_POWERPC"
6041bf2f
DE		 14592 "*
14593{
01a2ccd0
DE		 14594 if (GET_CODE (operands[0]) == REG)
14595 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14596 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14597}"
14598 [(set_attr "type" "load")])
915167f5 14599\f
a3170dc6 14600
f565b0a1 14601(include "sync.md")
10ed84db 14602(include "altivec.md")
a3170dc6 14603(include "spe.md")
7393f7f8 14604(include "dfp.md")
96038623 14605(include "paired.md")
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