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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
9ebbca7d | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
792760b9 | 3 | ;; 1999, 2000, 2001 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
5 | |
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d GK |
24 | |
25 | ;; `unspec' values used in rs6000.md: | |
26 | ;; Number Use | |
27 | ;; 0 frsp for POWER machines | |
28 | ;; 0/v blockage | |
29 | ;; 5 used to tie the stack contents and the stack pointer | |
30 | ;; 6 address of a word pointing to the TOC | |
31 | ;; 7 address of the TOC (more-or-less) | |
32 | ;; 8 movsi_got | |
33 | ;; 9/v eh_reg_restore | |
34 | ;; 10 fctiwz | |
35 | ;; 19 movesi_from_cr | |
36 | ;; 20 movesi_to_cr | |
1fd4e8c1 RK |
37 | \f |
38 | ;; Define an insn type attribute. This is used in function unit delay | |
39 | ;; computations. | |
39a10a29 | 40 | (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" |
1fd4e8c1 RK |
41 | (const_string "integer")) |
42 | ||
b19003d8 | 43 | ;; Length (in bytes). |
6cbadf36 GK |
44 | ; '(pc)' in the following doesn't include the instruction itself; it is |
45 | ; calculated as if the instruction had zero size. | |
b19003d8 RK |
46 | (define_attr "length" "" |
47 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 48 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 49 | (const_int -32768)) |
6cbadf36 GK |
50 | (lt (minus (match_dup 0) (pc)) |
51 | (const_int 32764))) | |
39a10a29 GK |
52 | (const_int 4) |
53 | (const_int 8)) | |
b19003d8 RK |
54 | (const_int 4))) |
55 | ||
cfb557c4 RK |
56 | ;; Processor type -- this attribute must exactly match the processor_type |
57 | ;; enumeration in rs6000.h. | |
58 | ||
3cb999d8 | 59 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750" |
cfb557c4 RK |
60 | (const (symbol_ref "rs6000_cpu_attr"))) |
61 | ||
62 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
63 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
64 | ||
b7ff3d82 | 65 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 66 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
67 | (define_function_unit "lsu" 1 0 |
68 | (and (eq_attr "type" "load") | |
3cb999d8 | 69 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 70 | 2 1) |
cfb557c4 RK |
71 | |
72 | (define_function_unit "lsu" 1 0 | |
b7ff3d82 | 73 | (and (eq_attr "type" "store,fpstore") |
3cb999d8 | 74 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 75 | 1 1) |
b6c9286a MM |
76 | |
77 | (define_function_unit "lsu" 1 0 | |
78 | (and (eq_attr "type" "fpload") | |
bef84347 | 79 | (eq_attr "cpu" "mpccore,ppc603,ppc750")) |
b6c9286a | 80 | 2 1) |
cfb557c4 | 81 | |
b7ff3d82 DE |
82 | (define_function_unit "lsu" 1 0 |
83 | (and (eq_attr "type" "fpload") | |
3cb999d8 | 84 | (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 DE |
85 | 3 1) |
86 | ||
cfb557c4 RK |
87 | (define_function_unit "iu" 1 0 |
88 | (and (eq_attr "type" "load") | |
b7ff3d82 | 89 | (eq_attr "cpu" "rios1,ppc403,ppc601")) |
b6c9286a | 90 | 2 1) |
cfb557c4 RK |
91 | |
92 | (define_function_unit "iu" 1 0 | |
b7ff3d82 DE |
93 | (and (eq_attr "type" "store,fpstore") |
94 | (eq_attr "cpu" "rios1,ppc403,ppc601")) | |
95 | 1 1) | |
96 | ||
97 | (define_function_unit "fpu" 1 0 | |
98 | (and (eq_attr "type" "fpstore") | |
3624a679 | 99 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 100 | 0 1) |
cfb557c4 | 101 | |
49a0b204 | 102 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 103 | (and (eq_attr "type" "fpload") |
b6c9286a | 104 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
105 | 2 1) |
106 | ||
107 | (define_function_unit "iu" 1 0 | |
108 | (and (eq_attr "type" "fpload") | |
109 | (eq_attr "cpu" "ppc601")) | |
110 | 3 1) | |
111 | ||
112 | (define_function_unit "iu2" 2 0 | |
113 | (and (eq_attr "type" "load,fpload") | |
114 | (eq_attr "cpu" "rios2")) | |
115 | 2 1) | |
116 | ||
117 | (define_function_unit "iu2" 2 0 | |
118 | (and (eq_attr "type" "store,fpstore") | |
119 | (eq_attr "cpu" "rios2")) | |
120 | 1 1) | |
121 | ||
3cb999d8 | 122 | ; Integer Unit (RIOS1, PPC601, PPC603, RS64a) |
b7ff3d82 DE |
123 | (define_function_unit "iu" 1 0 |
124 | (and (eq_attr "type" "integer") | |
3cb999d8 | 125 | (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603")) |
b7ff3d82 | 126 | 1 1) |
49a0b204 | 127 | |
39a10a29 GK |
128 | (define_function_unit "iu" 1 0 |
129 | (and (eq_attr "type" "cr_logical") | |
5638268e | 130 | (eq_attr "cpu" "mpccore,ppc403,ppc601")) |
39a10a29 GK |
131 | 1 1) |
132 | ||
da0ae67f MM |
133 | (define_function_unit "iu" 1 0 |
134 | (and (eq_attr "type" "imul") | |
135 | (eq_attr "cpu" "ppc403")) | |
136 | 4 4) | |
137 | ||
cfb557c4 RK |
138 | (define_function_unit "iu" 1 0 |
139 | (and (eq_attr "type" "imul") | |
b7ff3d82 | 140 | (eq_attr "cpu" "rios1,ppc601,ppc603")) |
51b8fc2c | 141 | 5 5) |
cfb557c4 | 142 | |
3cb999d8 DE |
143 | (define_function_unit "iu" 1 0 |
144 | (and (eq_attr "type" "imul") | |
145 | (eq_attr "cpu" "rs64a")) | |
146 | 20 14) | |
147 | ||
148 | (define_function_unit "iu" 1 0 | |
149 | (and (eq_attr "type" "lmul") | |
150 | (eq_attr "cpu" "rs64a")) | |
151 | 34 34) | |
152 | ||
cfb557c4 RK |
153 | (define_function_unit "iu" 1 0 |
154 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 155 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 156 | 19 19) |
cfb557c4 | 157 | |
3cb999d8 DE |
158 | (define_function_unit "iu" 1 0 |
159 | (and (eq_attr "type" "idiv") | |
160 | (eq_attr "cpu" "rs64a")) | |
161 | 66 66) | |
162 | ||
163 | (define_function_unit "iu" 1 0 | |
164 | (and (eq_attr "type" "ldiv") | |
165 | (eq_attr "cpu" "rs64a")) | |
166 | 66 66) | |
167 | ||
cfb557c4 RK |
168 | (define_function_unit "iu" 1 0 |
169 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
170 | (eq_attr "cpu" "ppc403")) |
171 | 33 33) | |
51b8fc2c | 172 | |
da0ae67f MM |
173 | (define_function_unit "iu" 1 0 |
174 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
175 | (eq_attr "cpu" "ppc601")) |
176 | 36 36) | |
da0ae67f | 177 | |
51b8fc2c RK |
178 | (define_function_unit "iu" 1 0 |
179 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 180 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
181 | 37 36) |
182 | ||
183 | ; RIOS2 has two integer units: a primary one which can perform all | |
184 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
185 | ; and can perform "simple" integer operations. |
186 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
187 | ; for the complex insns. | |
51b8fc2c RK |
188 | (define_function_unit "iu2" 2 0 |
189 | (and (eq_attr "type" "integer") | |
190 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 191 | 1 1) |
b6c9286a MM |
192 | |
193 | (define_function_unit "iu2" 2 0 | |
194 | (and (eq_attr "type" "imul") | |
195 | (eq_attr "cpu" "rios2")) | |
196 | 2 2) | |
197 | ||
198 | (define_function_unit "iu2" 2 0 | |
199 | (and (eq_attr "type" "idiv") | |
200 | (eq_attr "cpu" "rios2")) | |
201 | 13 13) | |
51b8fc2c RK |
202 | |
203 | (define_function_unit "imuldiv" 1 0 | |
204 | (and (eq_attr "type" "imul") | |
205 | (eq_attr "cpu" "rios2")) | |
b6c9286a MM |
206 | 2 2) |
207 | ||
51b8fc2c RK |
208 | (define_function_unit "imuldiv" 1 0 |
209 | (and (eq_attr "type" "idiv") | |
210 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 211 | 13 13) |
51b8fc2c | 212 | |
cf27b467 MM |
213 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
214 | ; Divide latency varies greatly from 2-11, use 6 as average | |
215 | (define_function_unit "imuldiv" 1 0 | |
216 | (and (eq_attr "type" "imul") | |
217 | (eq_attr "cpu" "mpccore")) | |
218 | 2 1) | |
219 | ||
220 | (define_function_unit "imuldiv" 1 0 | |
221 | (and (eq_attr "type" "idiv") | |
222 | (eq_attr "cpu" "mpccore")) | |
223 | 6 6) | |
224 | ||
cac8ce95 | 225 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
226 | ; and one unit for divide/multiply operations (and move |
227 | ; from/to spr). | |
228 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 229 | (and (eq_attr "type" "integer") |
3cb999d8 | 230 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 231 | 1 1) |
51b8fc2c RK |
232 | |
233 | (define_function_unit "imuldiv" 1 0 | |
234 | (and (eq_attr "type" "imul") | |
3cb999d8 | 235 | (eq_attr "cpu" "ppc604")) |
b7ff3d82 | 236 | 4 2) |
51b8fc2c | 237 | |
3cb999d8 DE |
238 | (define_function_unit "imuldiv" 1 0 |
239 | (and (eq_attr "type" "imul") | |
240 | (eq_attr "cpu" "ppc620,ppc630")) | |
241 | 5 3) | |
242 | ||
243 | (define_function_unit "imuldiv" 1 0 | |
244 | (and (eq_attr "type" "lmul") | |
245 | (eq_attr "cpu" "ppc620,ppc630")) | |
246 | 5 3) | |
247 | ||
cac8ce95 DE |
248 | (define_function_unit "imuldiv" 1 0 |
249 | (and (eq_attr "type" "imul") | |
250 | (eq_attr "cpu" "ppc604e")) | |
251 | 2 1) | |
252 | ||
51b8fc2c RK |
253 | (define_function_unit "imuldiv" 1 0 |
254 | (and (eq_attr "type" "idiv") | |
3cb999d8 | 255 | (eq_attr "cpu" "ppc604,ppc604e")) |
b7ff3d82 | 256 | 20 19) |
cfb557c4 | 257 | |
3cb999d8 DE |
258 | (define_function_unit "imuldiv" 1 0 |
259 | (and (eq_attr "type" "idiv") | |
260 | (eq_attr "cpu" "ppc620")) | |
261 | 37 36) | |
262 | ||
263 | (define_function_unit "imuldiv" 1 0 | |
264 | (and (eq_attr "type" "idiv") | |
265 | (eq_attr "cpu" "ppc630")) | |
266 | 21 20) | |
267 | ||
268 | (define_function_unit "imuldiv" 1 0 | |
269 | (and (eq_attr "type" "ldiv") | |
270 | (eq_attr "cpu" "ppc620,ppc630")) | |
271 | 37 36) | |
272 | ||
bef84347 VM |
273 | ; PPC750 has two integer units: a primary one which can perform all |
274 | ; operations and a secondary one which is fed in lock step with the first | |
275 | ; and can perform "simple" integer operations. | |
276 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
277 | ; for the complex insns. | |
278 | (define_function_unit "iu2" 2 0 | |
279 | (and (eq_attr "type" "integer") | |
280 | (eq_attr "cpu" "ppc750")) | |
281 | 1 1) | |
282 | ||
283 | (define_function_unit "iu2" 2 0 | |
284 | (and (eq_attr "type" "imul") | |
285 | (eq_attr "cpu" "ppc750")) | |
286 | 4 2) | |
287 | ||
288 | (define_function_unit "imuldiv" 1 0 | |
289 | (and (eq_attr "type" "imul") | |
290 | (eq_attr "cpu" "ppc750")) | |
291 | 4 2) | |
292 | ||
293 | (define_function_unit "imuldiv" 1 0 | |
294 | (and (eq_attr "type" "idiv") | |
295 | (eq_attr "cpu" "ppc750")) | |
296 | 19 19) | |
297 | ||
39a10a29 GK |
298 | ; CR-logical operations are execute-serialized, that is they don't |
299 | ; start (and block the function unit) until all preceding operations | |
300 | ; have finished. They don't block dispatch of other insns, though. | |
301 | ; I've imitated this by giving them longer latency. | |
302 | (define_function_unit "sru" 1 0 | |
303 | (and (eq_attr "type" "cr_logical") | |
304 | (eq_attr "cpu" "ppc603,ppc750")) | |
305 | 3 2) | |
306 | ||
b6c9286a | 307 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 308 | ; execute on the branch unit. |
b6c9286a MM |
309 | (define_function_unit "iu" 1 0 |
310 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
311 | (eq_attr "cpu" "rios1")) |
312 | 4 1) | |
313 | ||
314 | (define_function_unit "iu" 1 0 | |
315 | (and (eq_attr "type" "delayed_compare") | |
316 | (eq_attr "cpu" "rios1")) | |
317 | 5 1) | |
318 | ||
319 | (define_function_unit "iu" 1 0 | |
320 | (and (eq_attr "type" "compare,delayed_compare") | |
3cb999d8 | 321 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 322 | 3 1) |
b6c9286a MM |
323 | |
324 | (define_function_unit "iu2" 2 0 | |
b7ff3d82 | 325 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 326 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 327 | 3 1) |
b6c9286a | 328 | |
b6c9286a | 329 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 330 | (and (eq_attr "type" "compare,delayed_compare") |
3cb999d8 | 331 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 332 | 1 1) |
cfb557c4 | 333 | |
b6c9286a MM |
334 | ; fp compare uses fp unit |
335 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 336 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 337 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 338 | 9 1) |
cfb557c4 | 339 | |
b6c9286a MM |
340 | ; rios1 and rios2 have different fpcompare delays |
341 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 342 | (and (eq_attr "type" "fpcompare") |
3cb999d8 | 343 | (eq_attr "cpu" "rios2,ppc630")) |
b6c9286a MM |
344 | 5 1) |
345 | ||
346 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
347 | ; the integer unit | |
348 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 349 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
350 | (define_function_unit "iu" 1 0 |
351 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 352 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
353 | 0 2) |
354 | ||
355 | ; fp compare uses fp unit | |
356 | (define_function_unit "fpu" 1 0 | |
357 | (and (eq_attr "type" "fpcompare") | |
5638268e | 358 | (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 359 | 5 1) |
cfb557c4 | 360 | |
cf27b467 MM |
361 | (define_function_unit "fpu" 1 0 |
362 | (and (eq_attr "type" "fpcompare") | |
363 | (eq_attr "cpu" "mpccore")) | |
364 | 1 1) | |
365 | ||
cfb557c4 | 366 | (define_function_unit "bpu" 1 0 |
324e52cc | 367 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 368 | (eq_attr "cpu" "rios1,rios2,rs64a")) |
b7ff3d82 | 369 | 5 1) |
cfb557c4 RK |
370 | |
371 | (define_function_unit "bpu" 1 0 | |
324e52cc | 372 | (and (eq_attr "type" "mtjmpr") |
5638268e | 373 | (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 374 | 4 1) |
cfb557c4 | 375 | |
39a10a29 GK |
376 | (define_function_unit "bpu" 1 0 |
377 | (and (eq_attr "type" "cr_logical") | |
5638268e | 378 | (eq_attr "cpu" "rios1,rios2,ppc604")) |
39a10a29 GK |
379 | 4 1) |
380 | ||
381 | (define_function_unit "cru" 1 0 | |
382 | (and (eq_attr "type" "cr_logical") | |
5638268e DE |
383 | (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a")) |
384 | 1 1) | |
39a10a29 | 385 | |
b6c9286a MM |
386 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
387 | (define_function_unit "bpu" 1 0 | |
388 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 389 | 1 1) |
b6c9286a MM |
390 | |
391 | (define_function_unit "bpu" 1 0 | |
392 | (eq_attr "type" "branch") | |
b7ff3d82 | 393 | 1 1) |
b6c9286a | 394 | |
cf27b467 | 395 | ; Floating Point Unit |
cfb557c4 | 396 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 397 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 398 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 399 | 2 1) |
cfb557c4 | 400 | |
cf27b467 MM |
401 | (define_function_unit "fpu" 1 0 |
402 | (and (eq_attr "type" "fp") | |
3cb999d8 DE |
403 | (eq_attr "cpu" "rs64a,mpccore")) |
404 | 4 2) | |
cf27b467 | 405 | |
cfb557c4 RK |
406 | (define_function_unit "fpu" 1 0 |
407 | (and (eq_attr "type" "fp") | |
51b8fc2c | 408 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 409 | 4 1) |
cfb557c4 | 410 | |
51b8fc2c RK |
411 | (define_function_unit "fpu" 1 0 |
412 | (and (eq_attr "type" "fp") | |
3cb999d8 | 413 | (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620")) |
b6c9286a | 414 | 3 1) |
51b8fc2c | 415 | |
3cb999d8 DE |
416 | (define_function_unit "fpu" 1 0 |
417 | (and (eq_attr "type" "dmul") | |
418 | (eq_attr "cpu" "rs64a")) | |
419 | 7 2) | |
420 | ||
cf27b467 MM |
421 | (define_function_unit "fpu" 1 0 |
422 | (and (eq_attr "type" "dmul") | |
423 | (eq_attr "cpu" "mpccore")) | |
424 | 5 5) | |
425 | ||
cfb557c4 RK |
426 | (define_function_unit "fpu" 1 0 |
427 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 428 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 429 | 5 2) |
cfb557c4 | 430 | |
b6c9286a | 431 | ; is this true? |
cfb557c4 RK |
432 | (define_function_unit "fpu" 1 0 |
433 | (and (eq_attr "type" "dmul") | |
bef84347 | 434 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 435 | 4 2) |
cfb557c4 RK |
436 | |
437 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 438 | (and (eq_attr "type" "dmul") |
cac8ce95 | 439 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b6c9286a | 440 | 3 1) |
51b8fc2c RK |
441 | |
442 | (define_function_unit "fpu" 1 0 | |
443 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 444 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 445 | 19 19) |
cfb557c4 | 446 | |
3cb999d8 DE |
447 | (define_function_unit "fpu" 1 0 |
448 | (and (eq_attr "type" "sdiv") | |
449 | (eq_attr "cpu" "rs64a")) | |
450 | 31 31) | |
451 | ||
cfb557c4 RK |
452 | (define_function_unit "fpu" 1 0 |
453 | (and (eq_attr "type" "sdiv") | |
51b8fc2c RK |
454 | (eq_attr "cpu" "ppc601")) |
455 | 17 17) | |
456 | ||
cf27b467 MM |
457 | (define_function_unit "fpu" 1 0 |
458 | (and (eq_attr "type" "sdiv") | |
459 | (eq_attr "cpu" "mpccore")) | |
460 | 10 10) | |
461 | ||
51b8fc2c RK |
462 | (define_function_unit "fpu" 1 0 |
463 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 464 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 465 | 18 18) |
cfb557c4 | 466 | |
cf27b467 MM |
467 | (define_function_unit "fpu" 1 0 |
468 | (and (eq_attr "type" "ddiv") | |
469 | (eq_attr "cpu" "mpccore")) | |
470 | 17 17) | |
471 | ||
cfb557c4 RK |
472 | (define_function_unit "fpu" 1 0 |
473 | (and (eq_attr "type" "ddiv") | |
3cb999d8 | 474 | (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620")) |
51b8fc2c | 475 | 31 31) |
cfb557c4 RK |
476 | |
477 | (define_function_unit "fpu" 1 0 | |
478 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 479 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 480 | 33 33) |
cfb557c4 RK |
481 | |
482 | (define_function_unit "fpu" 1 0 | |
483 | (and (eq_attr "type" "ssqrt") | |
a473029f | 484 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 485 | 31 31) |
cfb557c4 RK |
486 | |
487 | (define_function_unit "fpu" 1 0 | |
488 | (and (eq_attr "type" "dsqrt") | |
a473029f | 489 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 490 | 31 31) |
b73d04f2 | 491 | |
51b8fc2c | 492 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 RK |
493 | (define_function_unit "fpu2" 2 0 |
494 | (and (eq_attr "type" "fp") | |
4652f1d4 | 495 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 496 | 2 1) |
cfb557c4 | 497 | |
3cb999d8 DE |
498 | (define_function_unit "fpu2" 2 0 |
499 | (and (eq_attr "type" "fp") | |
500 | (eq_attr "cpu" "ppc630")) | |
501 | 3 1) | |
502 | ||
cfb557c4 RK |
503 | (define_function_unit "fpu2" 2 0 |
504 | (and (eq_attr "type" "dmul") | |
505 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 506 | 2 1) |
cfb557c4 | 507 | |
3cb999d8 DE |
508 | (define_function_unit "fpu2" 2 0 |
509 | (and (eq_attr "type" "dmul") | |
510 | (eq_attr "cpu" "ppc630")) | |
511 | 3 1) | |
512 | ||
cfb557c4 | 513 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 514 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 515 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 516 | 17 17) |
ca7f5001 | 517 | |
3cb999d8 DE |
518 | (define_function_unit "fpu2" 2 0 |
519 | (and (eq_attr "type" "sdiv") | |
520 | (eq_attr "cpu" "ppc630")) | |
521 | 17 17) | |
522 | ||
523 | (define_function_unit "fpu2" 2 0 | |
524 | (and (eq_attr "type" "ddiv") | |
525 | (eq_attr "cpu" "ppc630")) | |
526 | 21 21) | |
527 | ||
ca7f5001 | 528 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 529 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 530 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 531 | 26 26) |
b6c9286a | 532 | |
3cb999d8 DE |
533 | (define_function_unit "fpu2" 2 0 |
534 | (and (eq_attr "type" "ssqrt") | |
535 | (eq_attr "cpu" "ppc630")) | |
536 | 18 18) | |
537 | ||
538 | (define_function_unit "fpu2" 2 0 | |
539 | (and (eq_attr "type" "dsqrt") | |
540 | (eq_attr "cpu" "ppc630")) | |
541 | 26 26) | |
542 | ||
1fd4e8c1 RK |
543 | \f |
544 | ;; Start with fixed-point load and store insns. Here we put only the more | |
545 | ;; complex forms. Basic data transfer is done later. | |
546 | ||
51b8fc2c RK |
547 | (define_expand "zero_extendqidi2" |
548 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
549 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
550 | "TARGET_POWERPC64" | |
551 | "") | |
552 | ||
553 | (define_insn "" | |
554 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
555 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
556 | "TARGET_POWERPC64" | |
557 | "@ | |
558 | lbz%U1%X1 %0,%1 | |
4371f8af | 559 | rldicl %0,%1,0,56" |
51b8fc2c RK |
560 | [(set_attr "type" "load,*")]) |
561 | ||
562 | (define_insn "" | |
9ebbca7d GK |
563 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
564 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 565 | (const_int 0))) |
9ebbca7d | 566 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 567 | "TARGET_POWERPC64" |
9ebbca7d GK |
568 | "@ |
569 | rldicl. %2,%1,0,56 | |
570 | #" | |
571 | [(set_attr "type" "compare") | |
572 | (set_attr "length" "4,8")]) | |
573 | ||
574 | (define_split | |
575 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
576 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
577 | (const_int 0))) | |
578 | (clobber (match_scratch:DI 2 ""))] | |
579 | "TARGET_POWERPC64 && reload_completed" | |
580 | [(set (match_dup 2) | |
581 | (zero_extend:DI (match_dup 1))) | |
582 | (set (match_dup 0) | |
583 | (compare:CC (match_dup 2) | |
584 | (const_int 0)))] | |
585 | "") | |
51b8fc2c RK |
586 | |
587 | (define_insn "" | |
9ebbca7d GK |
588 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
589 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 590 | (const_int 0))) |
9ebbca7d | 591 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 592 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 593 | "TARGET_POWERPC64" |
9ebbca7d GK |
594 | "@ |
595 | rldicl. %0,%1,0,56 | |
596 | #" | |
597 | [(set_attr "type" "compare") | |
598 | (set_attr "length" "4,8")]) | |
599 | ||
600 | (define_split | |
601 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
602 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
603 | (const_int 0))) | |
604 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
605 | (zero_extend:DI (match_dup 1)))] | |
606 | "TARGET_POWERPC64 && reload_completed" | |
607 | [(set (match_dup 0) | |
608 | (zero_extend:DI (match_dup 1))) | |
609 | (set (match_dup 2) | |
610 | (compare:CC (match_dup 0) | |
611 | (const_int 0)))] | |
612 | "") | |
51b8fc2c | 613 | |
2bee0449 RK |
614 | (define_insn "extendqidi2" |
615 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
616 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 617 | "TARGET_POWERPC64" |
2bee0449 | 618 | "extsb %0,%1") |
51b8fc2c RK |
619 | |
620 | (define_insn "" | |
9ebbca7d GK |
621 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
622 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 623 | (const_int 0))) |
9ebbca7d | 624 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 625 | "TARGET_POWERPC64" |
9ebbca7d GK |
626 | "@ |
627 | extsb. %2,%1 | |
628 | #" | |
629 | [(set_attr "type" "compare") | |
630 | (set_attr "length" "4,8")]) | |
631 | ||
632 | (define_split | |
633 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
634 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
635 | (const_int 0))) | |
636 | (clobber (match_scratch:DI 2 ""))] | |
637 | "TARGET_POWERPC64 && reload_completed" | |
638 | [(set (match_dup 2) | |
639 | (sign_extend:DI (match_dup 1))) | |
640 | (set (match_dup 0) | |
641 | (compare:CC (match_dup 2) | |
642 | (const_int 0)))] | |
643 | "") | |
51b8fc2c RK |
644 | |
645 | (define_insn "" | |
9ebbca7d GK |
646 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
647 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 648 | (const_int 0))) |
9ebbca7d | 649 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
650 | (sign_extend:DI (match_dup 1)))] |
651 | "TARGET_POWERPC64" | |
9ebbca7d GK |
652 | "@ |
653 | extsb. %0,%1 | |
654 | #" | |
655 | [(set_attr "type" "compare") | |
656 | (set_attr "length" "4,8")]) | |
657 | ||
658 | (define_split | |
659 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
660 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
661 | (const_int 0))) | |
662 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
663 | (sign_extend:DI (match_dup 1)))] | |
664 | "TARGET_POWERPC64 && reload_completed" | |
665 | [(set (match_dup 0) | |
666 | (sign_extend:DI (match_dup 1))) | |
667 | (set (match_dup 2) | |
668 | (compare:CC (match_dup 0) | |
669 | (const_int 0)))] | |
670 | "") | |
51b8fc2c RK |
671 | |
672 | (define_expand "zero_extendhidi2" | |
673 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
674 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
675 | "TARGET_POWERPC64" | |
676 | "") | |
677 | ||
678 | (define_insn "" | |
679 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
680 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
681 | "TARGET_POWERPC64" | |
682 | "@ | |
683 | lhz%U1%X1 %0,%1 | |
4371f8af | 684 | rldicl %0,%1,0,48" |
51b8fc2c RK |
685 | [(set_attr "type" "load,*")]) |
686 | ||
687 | (define_insn "" | |
9ebbca7d GK |
688 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
689 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 690 | (const_int 0))) |
9ebbca7d | 691 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 692 | "TARGET_POWERPC64" |
9ebbca7d GK |
693 | "@ |
694 | rldicl. %2,%1,0,48 | |
695 | #" | |
696 | [(set_attr "type" "compare") | |
697 | (set_attr "length" "4,8")]) | |
698 | ||
699 | (define_split | |
700 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
701 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
702 | (const_int 0))) | |
703 | (clobber (match_scratch:DI 2 ""))] | |
704 | "TARGET_POWERPC64 && reload_completed" | |
705 | [(set (match_dup 2) | |
706 | (zero_extend:DI (match_dup 1))) | |
707 | (set (match_dup 0) | |
708 | (compare:CC (match_dup 2) | |
709 | (const_int 0)))] | |
710 | "") | |
51b8fc2c RK |
711 | |
712 | (define_insn "" | |
9ebbca7d GK |
713 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
714 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 715 | (const_int 0))) |
9ebbca7d | 716 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
717 | (zero_extend:DI (match_dup 1)))] |
718 | "TARGET_POWERPC64" | |
9ebbca7d GK |
719 | "@ |
720 | rldicl. %0,%1,0,48 | |
721 | #" | |
722 | [(set_attr "type" "compare") | |
723 | (set_attr "length" "4,8")]) | |
724 | ||
725 | (define_split | |
726 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
727 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
728 | (const_int 0))) | |
729 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
730 | (zero_extend:DI (match_dup 1)))] | |
731 | "TARGET_POWERPC64 && reload_completed" | |
732 | [(set (match_dup 0) | |
733 | (zero_extend:DI (match_dup 1))) | |
734 | (set (match_dup 2) | |
735 | (compare:CC (match_dup 0) | |
736 | (const_int 0)))] | |
737 | "") | |
51b8fc2c RK |
738 | |
739 | (define_expand "extendhidi2" | |
740 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
741 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
742 | "TARGET_POWERPC64" | |
743 | "") | |
744 | ||
745 | (define_insn "" | |
746 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
747 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
748 | "TARGET_POWERPC64" | |
749 | "@ | |
750 | lha%U1%X1 %0,%1 | |
751 | extsh %0,%1" | |
752 | [(set_attr "type" "load,*")]) | |
753 | ||
754 | (define_insn "" | |
9ebbca7d GK |
755 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
756 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 757 | (const_int 0))) |
9ebbca7d | 758 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 759 | "TARGET_POWERPC64" |
9ebbca7d GK |
760 | "@ |
761 | extsh. %2,%1 | |
762 | #" | |
763 | [(set_attr "type" "compare") | |
764 | (set_attr "length" "4,8")]) | |
765 | ||
766 | (define_split | |
767 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
768 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
769 | (const_int 0))) | |
770 | (clobber (match_scratch:DI 2 ""))] | |
771 | "TARGET_POWERPC64 && reload_completed" | |
772 | [(set (match_dup 2) | |
773 | (sign_extend:DI (match_dup 1))) | |
774 | (set (match_dup 0) | |
775 | (compare:CC (match_dup 2) | |
776 | (const_int 0)))] | |
777 | "") | |
51b8fc2c RK |
778 | |
779 | (define_insn "" | |
9ebbca7d GK |
780 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
781 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 782 | (const_int 0))) |
9ebbca7d | 783 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
784 | (sign_extend:DI (match_dup 1)))] |
785 | "TARGET_POWERPC64" | |
9ebbca7d GK |
786 | "@ |
787 | extsh. %0,%1 | |
788 | #" | |
789 | [(set_attr "type" "compare") | |
790 | (set_attr "length" "4,8")]) | |
791 | ||
792 | (define_split | |
793 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
794 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
795 | (const_int 0))) | |
796 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
797 | (sign_extend:DI (match_dup 1)))] | |
798 | "TARGET_POWERPC64 && reload_completed" | |
799 | [(set (match_dup 0) | |
800 | (sign_extend:DI (match_dup 1))) | |
801 | (set (match_dup 2) | |
802 | (compare:CC (match_dup 0) | |
803 | (const_int 0)))] | |
804 | "") | |
51b8fc2c RK |
805 | |
806 | (define_expand "zero_extendsidi2" | |
807 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
808 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
809 | "TARGET_POWERPC64" | |
810 | "") | |
811 | ||
812 | (define_insn "" | |
813 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
814 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
815 | "TARGET_POWERPC64" | |
816 | "@ | |
817 | lwz%U1%X1 %0,%1 | |
818 | rldicl %0,%1,0,32" | |
819 | [(set_attr "type" "load,*")]) | |
820 | ||
821 | (define_insn "" | |
9ebbca7d GK |
822 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
823 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 824 | (const_int 0))) |
9ebbca7d | 825 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 826 | "TARGET_POWERPC64" |
9ebbca7d GK |
827 | "@ |
828 | rldicl. %2,%1,0,32 | |
829 | #" | |
830 | [(set_attr "type" "compare") | |
831 | (set_attr "length" "4,8")]) | |
832 | ||
833 | (define_split | |
834 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
835 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
836 | (const_int 0))) | |
837 | (clobber (match_scratch:DI 2 ""))] | |
838 | "TARGET_POWERPC64 && reload_completed" | |
839 | [(set (match_dup 2) | |
840 | (zero_extend:DI (match_dup 1))) | |
841 | (set (match_dup 0) | |
842 | (compare:CC (match_dup 2) | |
843 | (const_int 0)))] | |
844 | "") | |
51b8fc2c RK |
845 | |
846 | (define_insn "" | |
9ebbca7d GK |
847 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
848 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 849 | (const_int 0))) |
9ebbca7d | 850 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
851 | (zero_extend:DI (match_dup 1)))] |
852 | "TARGET_POWERPC64" | |
9ebbca7d GK |
853 | "@ |
854 | rldicl. %0,%1,0,32 | |
855 | #" | |
856 | [(set_attr "type" "compare") | |
857 | (set_attr "length" "4,8")]) | |
858 | ||
859 | (define_split | |
860 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
861 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
862 | (const_int 0))) | |
863 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
864 | (zero_extend:DI (match_dup 1)))] | |
865 | "TARGET_POWERPC64 && reload_completed" | |
866 | [(set (match_dup 0) | |
867 | (zero_extend:DI (match_dup 1))) | |
868 | (set (match_dup 2) | |
869 | (compare:CC (match_dup 0) | |
870 | (const_int 0)))] | |
871 | "") | |
51b8fc2c RK |
872 | |
873 | (define_expand "extendsidi2" | |
874 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
875 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
876 | "TARGET_POWERPC64" | |
877 | "") | |
878 | ||
879 | (define_insn "" | |
880 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 881 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
882 | "TARGET_POWERPC64" |
883 | "@ | |
884 | lwa%U1%X1 %0,%1 | |
885 | extsw %0,%1" | |
886 | [(set_attr "type" "load,*")]) | |
887 | ||
888 | (define_insn "" | |
9ebbca7d GK |
889 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
890 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 891 | (const_int 0))) |
9ebbca7d | 892 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 893 | "TARGET_POWERPC64" |
9ebbca7d GK |
894 | "@ |
895 | extsw. %2,%1 | |
896 | #" | |
897 | [(set_attr "type" "compare") | |
898 | (set_attr "length" "4,8")]) | |
899 | ||
900 | (define_split | |
901 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
902 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
903 | (const_int 0))) | |
904 | (clobber (match_scratch:DI 2 ""))] | |
905 | "TARGET_POWERPC64 && reload_completed" | |
906 | [(set (match_dup 2) | |
907 | (sign_extend:DI (match_dup 1))) | |
908 | (set (match_dup 0) | |
909 | (compare:CC (match_dup 2) | |
910 | (const_int 0)))] | |
911 | "") | |
51b8fc2c RK |
912 | |
913 | (define_insn "" | |
9ebbca7d GK |
914 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
915 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 916 | (const_int 0))) |
9ebbca7d | 917 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
918 | (sign_extend:DI (match_dup 1)))] |
919 | "TARGET_POWERPC64" | |
9ebbca7d GK |
920 | "@ |
921 | extsw. %0,%1 | |
922 | #" | |
923 | [(set_attr "type" "compare") | |
924 | (set_attr "length" "4,8")]) | |
925 | ||
926 | (define_split | |
927 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
928 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
929 | (const_int 0))) | |
930 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
931 | (sign_extend:DI (match_dup 1)))] | |
932 | "TARGET_POWERPC64 && reload_completed" | |
933 | [(set (match_dup 0) | |
934 | (sign_extend:DI (match_dup 1))) | |
935 | (set (match_dup 2) | |
936 | (compare:CC (match_dup 0) | |
937 | (const_int 0)))] | |
938 | "") | |
51b8fc2c | 939 | |
1fd4e8c1 | 940 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
941 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
942 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
943 | "" |
944 | "") | |
945 | ||
946 | (define_insn "" | |
cd2b37d9 | 947 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
948 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
949 | "" | |
950 | "@ | |
951 | lbz%U1%X1 %0,%1 | |
005a35b9 | 952 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
953 | [(set_attr "type" "load,*")]) |
954 | ||
955 | (define_insn "" | |
9ebbca7d GK |
956 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
957 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 958 | (const_int 0))) |
9ebbca7d | 959 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 960 | "" |
9ebbca7d GK |
961 | "@ |
962 | {andil.|andi.} %2,%1,0xff | |
963 | #" | |
964 | [(set_attr "type" "compare") | |
965 | (set_attr "length" "4,8")]) | |
966 | ||
967 | (define_split | |
968 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
969 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
970 | (const_int 0))) | |
971 | (clobber (match_scratch:SI 2 ""))] | |
972 | "reload_completed" | |
973 | [(set (match_dup 2) | |
974 | (zero_extend:SI (match_dup 1))) | |
975 | (set (match_dup 0) | |
976 | (compare:CC (match_dup 2) | |
977 | (const_int 0)))] | |
978 | "") | |
1fd4e8c1 RK |
979 | |
980 | (define_insn "" | |
9ebbca7d GK |
981 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
982 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 983 | (const_int 0))) |
9ebbca7d | 984 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
985 | (zero_extend:SI (match_dup 1)))] |
986 | "" | |
9ebbca7d GK |
987 | "@ |
988 | {andil.|andi.} %0,%1,0xff | |
989 | #" | |
990 | [(set_attr "type" "compare") | |
991 | (set_attr "length" "4,8")]) | |
992 | ||
993 | (define_split | |
994 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
995 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
996 | (const_int 0))) | |
997 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
998 | (zero_extend:SI (match_dup 1)))] | |
999 | "reload_completed" | |
1000 | [(set (match_dup 0) | |
1001 | (zero_extend:SI (match_dup 1))) | |
1002 | (set (match_dup 2) | |
1003 | (compare:CC (match_dup 0) | |
1004 | (const_int 0)))] | |
1005 | "") | |
1fd4e8c1 | 1006 | |
51b8fc2c RK |
1007 | (define_expand "extendqisi2" |
1008 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1009 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1010 | "" | |
1011 | " | |
1012 | { | |
1013 | if (TARGET_POWERPC) | |
1014 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
1015 | else if (TARGET_POWER) | |
1016 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
1017 | else | |
1018 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
1019 | DONE; | |
1020 | }") | |
1021 | ||
1022 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
1023 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1024 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 1025 | "TARGET_POWERPC" |
2bee0449 | 1026 | "extsb %0,%1") |
51b8fc2c RK |
1027 | |
1028 | (define_insn "" | |
9ebbca7d GK |
1029 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1030 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1031 | (const_int 0))) |
9ebbca7d | 1032 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 1033 | "TARGET_POWERPC" |
9ebbca7d GK |
1034 | "@ |
1035 | extsb. %2,%1 | |
1036 | #" | |
1037 | [(set_attr "type" "compare") | |
1038 | (set_attr "length" "4,8")]) | |
1039 | ||
1040 | (define_split | |
1041 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1042 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1043 | (const_int 0))) | |
1044 | (clobber (match_scratch:SI 2 ""))] | |
1045 | "TARGET_POWERPC && reload_completed" | |
1046 | [(set (match_dup 2) | |
1047 | (sign_extend:SI (match_dup 1))) | |
1048 | (set (match_dup 0) | |
1049 | (compare:CC (match_dup 2) | |
1050 | (const_int 0)))] | |
1051 | "") | |
51b8fc2c RK |
1052 | |
1053 | (define_insn "" | |
9ebbca7d GK |
1054 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1055 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1056 | (const_int 0))) |
9ebbca7d | 1057 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1058 | (sign_extend:SI (match_dup 1)))] |
1059 | "TARGET_POWERPC" | |
9ebbca7d GK |
1060 | "@ |
1061 | extsb. %0,%1 | |
1062 | #" | |
1063 | [(set_attr "type" "compare") | |
1064 | (set_attr "length" "4,8")]) | |
1065 | ||
1066 | (define_split | |
1067 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1068 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1069 | (const_int 0))) | |
1070 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1071 | (sign_extend:SI (match_dup 1)))] | |
1072 | "TARGET_POWERPC && reload_completed" | |
1073 | [(set (match_dup 0) | |
1074 | (sign_extend:SI (match_dup 1))) | |
1075 | (set (match_dup 2) | |
1076 | (compare:CC (match_dup 0) | |
1077 | (const_int 0)))] | |
1078 | "") | |
51b8fc2c RK |
1079 | |
1080 | (define_expand "extendqisi2_power" | |
1081 | [(parallel [(set (match_dup 2) | |
1082 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1083 | (const_int 24))) | |
1084 | (clobber (scratch:SI))]) | |
1085 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1086 | (ashiftrt:SI (match_dup 2) | |
1087 | (const_int 24))) | |
1088 | (clobber (scratch:SI))])] | |
1089 | "TARGET_POWER" | |
1090 | " | |
1091 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1092 | operands[2] = gen_reg_rtx (SImode); }") | |
1093 | ||
1094 | (define_expand "extendqisi2_no_power" | |
1095 | [(set (match_dup 2) | |
1096 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1097 | (const_int 24))) | |
1098 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1099 | (ashiftrt:SI (match_dup 2) | |
1100 | (const_int 24)))] | |
1101 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1102 | " | |
1103 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1104 | operands[2] = gen_reg_rtx (SImode); }") | |
1105 | ||
1fd4e8c1 | 1106 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
1107 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
1108 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1109 | "" |
1110 | "") | |
1111 | ||
1112 | (define_insn "" | |
cd2b37d9 | 1113 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1114 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1115 | "" | |
1116 | "@ | |
1117 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1118 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
1119 | [(set_attr "type" "load,*")]) |
1120 | ||
1121 | (define_insn "" | |
9ebbca7d GK |
1122 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1123 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1124 | (const_int 0))) |
9ebbca7d | 1125 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 1126 | "" |
9ebbca7d GK |
1127 | "@ |
1128 | {andil.|andi.} %2,%1,0xff | |
1129 | #" | |
1130 | [(set_attr "type" "compare") | |
1131 | (set_attr "length" "4,8")]) | |
1132 | ||
1133 | (define_split | |
1134 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1135 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1136 | (const_int 0))) | |
1137 | (clobber (match_scratch:HI 2 ""))] | |
1138 | "reload_completed" | |
1139 | [(set (match_dup 2) | |
1140 | (zero_extend:HI (match_dup 1))) | |
1141 | (set (match_dup 0) | |
1142 | (compare:CC (match_dup 2) | |
1143 | (const_int 0)))] | |
1144 | "") | |
1fd4e8c1 | 1145 | |
51b8fc2c | 1146 | (define_insn "" |
9ebbca7d GK |
1147 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1148 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1149 | (const_int 0))) |
9ebbca7d | 1150 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
1151 | (zero_extend:HI (match_dup 1)))] |
1152 | "" | |
9ebbca7d GK |
1153 | "@ |
1154 | {andil.|andi.} %0,%1,0xff | |
1155 | #" | |
1156 | [(set_attr "type" "compare") | |
1157 | (set_attr "length" "4,8")]) | |
1158 | ||
1159 | (define_split | |
1160 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1161 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1162 | (const_int 0))) | |
1163 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1164 | (zero_extend:HI (match_dup 1)))] | |
1165 | "reload_completed" | |
1166 | [(set (match_dup 0) | |
1167 | (zero_extend:HI (match_dup 1))) | |
1168 | (set (match_dup 2) | |
1169 | (compare:CC (match_dup 0) | |
1170 | (const_int 0)))] | |
1171 | "") | |
815cdc52 MM |
1172 | |
1173 | (define_expand "extendqihi2" | |
1174 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
1175 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1176 | "" | |
1177 | " | |
1178 | { | |
1179 | if (TARGET_POWERPC) | |
1180 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
1181 | else if (TARGET_POWER) | |
1182 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
1183 | else | |
1184 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
1185 | DONE; | |
1186 | }") | |
1187 | ||
1188 | (define_insn "extendqihi2_ppc" | |
1189 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
1190 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
1191 | "TARGET_POWERPC" | |
1192 | "extsb %0,%1") | |
1193 | ||
1194 | (define_insn "" | |
9ebbca7d GK |
1195 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1196 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1197 | (const_int 0))) |
9ebbca7d | 1198 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 1199 | "TARGET_POWERPC" |
9ebbca7d GK |
1200 | "@ |
1201 | extsb. %2,%1 | |
1202 | #" | |
1203 | [(set_attr "type" "compare") | |
1204 | (set_attr "length" "4,8")]) | |
1205 | ||
1206 | (define_split | |
1207 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1208 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1209 | (const_int 0))) | |
1210 | (clobber (match_scratch:HI 2 ""))] | |
1211 | "TARGET_POWERPC && reload_completed" | |
1212 | [(set (match_dup 2) | |
1213 | (sign_extend:HI (match_dup 1))) | |
1214 | (set (match_dup 0) | |
1215 | (compare:CC (match_dup 2) | |
1216 | (const_int 0)))] | |
1217 | "") | |
815cdc52 MM |
1218 | |
1219 | (define_insn "" | |
9ebbca7d GK |
1220 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1221 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1222 | (const_int 0))) |
9ebbca7d | 1223 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1224 | (sign_extend:HI (match_dup 1)))] |
1225 | "TARGET_POWERPC" | |
9ebbca7d GK |
1226 | "@ |
1227 | extsb. %0,%1 | |
1228 | #" | |
1229 | [(set_attr "type" "compare") | |
1230 | (set_attr "length" "4,8")]) | |
1231 | ||
1232 | (define_split | |
1233 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1234 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1235 | (const_int 0))) | |
1236 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1237 | (sign_extend:HI (match_dup 1)))] | |
1238 | "TARGET_POWERPC && reload_completed" | |
1239 | [(set (match_dup 0) | |
1240 | (sign_extend:HI (match_dup 1))) | |
1241 | (set (match_dup 2) | |
1242 | (compare:CC (match_dup 0) | |
1243 | (const_int 0)))] | |
1244 | "") | |
51b8fc2c RK |
1245 | |
1246 | (define_expand "extendqihi2_power" | |
1247 | [(parallel [(set (match_dup 2) | |
1248 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1249 | (const_int 24))) | |
1250 | (clobber (scratch:SI))]) | |
1251 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
1252 | (ashiftrt:SI (match_dup 2) | |
1253 | (const_int 24))) | |
1254 | (clobber (scratch:SI))])] | |
1255 | "TARGET_POWER" | |
1256 | " | |
1257 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1258 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1259 | operands[2] = gen_reg_rtx (SImode); }") | |
1260 | ||
1261 | (define_expand "extendqihi2_no_power" | |
1262 | [(set (match_dup 2) | |
1263 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1264 | (const_int 24))) | |
1265 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1266 | (ashiftrt:SI (match_dup 2) | |
1267 | (const_int 24)))] | |
1268 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1269 | " | |
1270 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1271 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1272 | operands[2] = gen_reg_rtx (SImode); }") | |
1273 | ||
1fd4e8c1 | 1274 | (define_expand "zero_extendhisi2" |
5f243543 | 1275 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 1276 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
1277 | "" |
1278 | "") | |
1279 | ||
1280 | (define_insn "" | |
cd2b37d9 | 1281 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1282 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1283 | "" | |
1284 | "@ | |
1285 | lhz%U1%X1 %0,%1 | |
005a35b9 | 1286 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
1287 | [(set_attr "type" "load,*")]) |
1288 | ||
1289 | (define_insn "" | |
9ebbca7d GK |
1290 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1291 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1292 | (const_int 0))) |
9ebbca7d | 1293 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1294 | "" |
9ebbca7d GK |
1295 | "@ |
1296 | {andil.|andi.} %2,%1,0xffff | |
1297 | #" | |
1298 | [(set_attr "type" "compare") | |
1299 | (set_attr "length" "4,8")]) | |
1300 | ||
1301 | (define_split | |
1302 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1303 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1304 | (const_int 0))) | |
1305 | (clobber (match_scratch:SI 2 ""))] | |
1306 | "reload_completed" | |
1307 | [(set (match_dup 2) | |
1308 | (zero_extend:SI (match_dup 1))) | |
1309 | (set (match_dup 0) | |
1310 | (compare:CC (match_dup 2) | |
1311 | (const_int 0)))] | |
1312 | "") | |
1fd4e8c1 RK |
1313 | |
1314 | (define_insn "" | |
9ebbca7d GK |
1315 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1316 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1317 | (const_int 0))) |
9ebbca7d | 1318 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1319 | (zero_extend:SI (match_dup 1)))] |
1320 | "" | |
9ebbca7d GK |
1321 | "@ |
1322 | {andil.|andi.} %0,%1,0xffff | |
1323 | #" | |
1324 | [(set_attr "type" "compare") | |
1325 | (set_attr "length" "4,8")]) | |
1326 | ||
1327 | (define_split | |
1328 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1329 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1330 | (const_int 0))) | |
1331 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1332 | (zero_extend:SI (match_dup 1)))] | |
1333 | "reload_completed" | |
1334 | [(set (match_dup 0) | |
1335 | (zero_extend:SI (match_dup 1))) | |
1336 | (set (match_dup 2) | |
1337 | (compare:CC (match_dup 0) | |
1338 | (const_int 0)))] | |
1339 | "") | |
1fd4e8c1 RK |
1340 | |
1341 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
1342 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1343 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1344 | "" |
1345 | "") | |
1346 | ||
1347 | (define_insn "" | |
cd2b37d9 | 1348 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1349 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1350 | "" | |
1351 | "@ | |
1352 | lha%U1%X1 %0,%1 | |
ca7f5001 | 1353 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
1354 | [(set_attr "type" "load,*")]) |
1355 | ||
1356 | (define_insn "" | |
9ebbca7d GK |
1357 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1358 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1359 | (const_int 0))) |
9ebbca7d | 1360 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1361 | "" |
9ebbca7d GK |
1362 | "@ |
1363 | {exts.|extsh.} %2,%1 | |
1364 | #" | |
1365 | [(set_attr "type" "compare") | |
1366 | (set_attr "length" "4,8")]) | |
1367 | ||
1368 | (define_split | |
1369 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1370 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1371 | (const_int 0))) | |
1372 | (clobber (match_scratch:SI 2 ""))] | |
1373 | "reload_completed" | |
1374 | [(set (match_dup 2) | |
1375 | (sign_extend:SI (match_dup 1))) | |
1376 | (set (match_dup 0) | |
1377 | (compare:CC (match_dup 2) | |
1378 | (const_int 0)))] | |
1379 | "") | |
1fd4e8c1 RK |
1380 | |
1381 | (define_insn "" | |
9ebbca7d GK |
1382 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1383 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1384 | (const_int 0))) |
9ebbca7d | 1385 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1386 | (sign_extend:SI (match_dup 1)))] |
1387 | "" | |
9ebbca7d GK |
1388 | "@ |
1389 | {exts.|extsh.} %0,%1 | |
1390 | #" | |
1391 | [(set_attr "type" "compare") | |
1392 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1393 | \f |
9ebbca7d GK |
1394 | (define_split |
1395 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1396 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1397 | (const_int 0))) | |
1398 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1399 | (sign_extend:SI (match_dup 1)))] | |
1400 | "reload_completed" | |
1401 | [(set (match_dup 0) | |
1402 | (sign_extend:SI (match_dup 1))) | |
1403 | (set (match_dup 2) | |
1404 | (compare:CC (match_dup 0) | |
1405 | (const_int 0)))] | |
1406 | "") | |
1407 | ||
1fd4e8c1 | 1408 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
1409 | |
1410 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
1411 | ;; allowing register zero as source. | |
7cd5235b MM |
1412 | (define_expand "addsi3" |
1413 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1414 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 1415 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
1416 | "" |
1417 | " | |
1418 | { | |
677a9668 DE |
1419 | if (GET_CODE (operands[2]) == CONST_INT |
1420 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 1421 | { |
677a9668 | 1422 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
1423 | ? operands[0] : gen_reg_rtx (SImode)); |
1424 | ||
2bfcf297 DB |
1425 | HOST_WIDE_INT val = INTVAL (operands[2]); |
1426 | HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); | |
1427 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); | |
7cd5235b | 1428 | |
9ebbca7d GK |
1429 | /* The ordering here is important for the prolog expander. |
1430 | When space is allocated from the stack, adding 'low' first may | |
1431 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 1432 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
1433 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
1434 | DONE; | |
1435 | } | |
1436 | }") | |
1437 | ||
1438 | (define_insn "*addsi3_internal1" | |
1439 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1440 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1441 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1442 | "" |
1443 | "@ | |
deb9225a RK |
1444 | {cax|add} %0,%1,%2 |
1445 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1446 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1447 | {cau|addis} %0,%1,%v2" |
1448 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1449 | |
ee890fe2 SS |
1450 | (define_insn "addsi3_high" |
1451 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1452 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1453 | (high:SI (match_operand 2 "" ""))))] | |
1454 | "TARGET_MACHO && !TARGET_64BIT" | |
1455 | "{cau|addis} %0,%1,ha16(%2)" | |
1456 | [(set_attr "length" "4")]) | |
1457 | ||
7cd5235b | 1458 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1459 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1460 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1461 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1462 | (const_int 0))) |
cb8cc086 | 1463 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1464 | "! TARGET_POWERPC64" |
deb9225a RK |
1465 | "@ |
1466 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1467 | {ai.|addic.} %3,%1,%2 |
1468 | # | |
1469 | #" | |
1470 | [(set_attr "type" "compare") | |
1471 | (set_attr "length" "4,4,8,8")]) | |
1472 | ||
1473 | (define_split | |
1474 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1475 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1476 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1477 | (const_int 0))) | |
1478 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1479 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1480 | [(set (match_dup 3) |
1481 | (plus:SI (match_dup 1) | |
1482 | (match_dup 2))) | |
1483 | (set (match_dup 0) | |
1484 | (compare:CC (match_dup 3) | |
1485 | (const_int 0)))] | |
1486 | "") | |
7e69e155 | 1487 | |
7cd5235b | 1488 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1489 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1490 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1491 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1492 | (const_int 0))) |
cb8cc086 MM |
1493 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1494 | (plus:SI (match_dup 1) | |
1495 | (match_dup 2)))] | |
0ad91047 | 1496 | "! TARGET_POWERPC64" |
deb9225a RK |
1497 | "@ |
1498 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1499 | {ai.|addic.} %0,%1,%2 |
1500 | # | |
1501 | #" | |
1502 | [(set_attr "type" "compare") | |
1503 | (set_attr "length" "4,4,8,8")]) | |
1504 | ||
1505 | (define_split | |
1506 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1507 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1508 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1509 | (const_int 0))) | |
1510 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1511 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1512 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1513 | [(set (match_dup 0) |
1514 | (plus:SI (match_dup 1) | |
1515 | (match_dup 2))) | |
1516 | (set (match_dup 3) | |
1517 | (compare:CC (match_dup 0) | |
1518 | (const_int 0)))] | |
1519 | "") | |
7e69e155 | 1520 | |
f357808b RK |
1521 | ;; Split an add that we can't do in one insn into two insns, each of which |
1522 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1523 | ;; add should be last in case the result gets used in an address. | |
1524 | ||
1525 | (define_split | |
cd2b37d9 RK |
1526 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1527 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1528 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1529 | "" |
f357808b RK |
1530 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1531 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1532 | " | |
1fd4e8c1 | 1533 | { |
2bfcf297 DB |
1534 | HOST_WIDE_INT val = INTVAL (operands[2]); |
1535 | HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); | |
1536 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); | |
1fd4e8c1 | 1537 | |
2bfcf297 | 1538 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1539 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1540 | }") |
1541 | ||
8de2a197 | 1542 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1543 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1544 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1545 | "" |
ca7f5001 RK |
1546 | "nor %0,%1,%1") |
1547 | ||
1548 | (define_insn "" | |
52d3af72 DE |
1549 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1550 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1551 | (const_int 0))) |
52d3af72 | 1552 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1553 | "! TARGET_POWERPC64" |
52d3af72 DE |
1554 | "@ |
1555 | nor. %2,%1,%1 | |
1556 | #" | |
1557 | [(set_attr "type" "compare") | |
1558 | (set_attr "length" "4,8")]) | |
1559 | ||
1560 | (define_split | |
1561 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1562 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1563 | (const_int 0))) | |
1564 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1565 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1566 | [(set (match_dup 2) |
1567 | (not:SI (match_dup 1))) | |
1568 | (set (match_dup 0) | |
1569 | (compare:CC (match_dup 2) | |
1570 | (const_int 0)))] | |
1571 | "") | |
ca7f5001 RK |
1572 | |
1573 | (define_insn "" | |
52d3af72 DE |
1574 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1575 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1576 | (const_int 0))) |
52d3af72 | 1577 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1578 | (not:SI (match_dup 1)))] |
0ad91047 | 1579 | "! TARGET_POWERPC64" |
52d3af72 DE |
1580 | "@ |
1581 | nor. %0,%1,%1 | |
1582 | #" | |
1583 | [(set_attr "type" "compare") | |
1584 | (set_attr "length" "4,8")]) | |
1585 | ||
1586 | (define_split | |
1587 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1588 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1589 | (const_int 0))) | |
1590 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1591 | (not:SI (match_dup 1)))] | |
0ad91047 | 1592 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1593 | [(set (match_dup 0) |
1594 | (not:SI (match_dup 1))) | |
1595 | (set (match_dup 2) | |
1596 | (compare:CC (match_dup 0) | |
1597 | (const_int 0)))] | |
1598 | "") | |
1fd4e8c1 RK |
1599 | |
1600 | (define_insn "" | |
3d91674b RK |
1601 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1602 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1603 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1604 | "! TARGET_POWERPC" |
ca7f5001 | 1605 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1606 | |
deb9225a RK |
1607 | (define_insn "" |
1608 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1609 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1610 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1611 | "TARGET_POWERPC" | |
1612 | "@ | |
1613 | subf %0,%2,%1 | |
1614 | subfic %0,%2,%1") | |
1615 | ||
1fd4e8c1 | 1616 | (define_insn "" |
cb8cc086 MM |
1617 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1618 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1619 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1620 | (const_int 0))) |
cb8cc086 | 1621 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1622 | "! TARGET_POWERPC" |
cb8cc086 MM |
1623 | "@ |
1624 | {sf.|subfc.} %3,%2,%1 | |
1625 | #" | |
1626 | [(set_attr "type" "compare") | |
1627 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1628 | |
deb9225a | 1629 | (define_insn "" |
cb8cc086 MM |
1630 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1631 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1632 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1633 | (const_int 0))) |
cb8cc086 | 1634 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1635 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1636 | "@ |
1637 | subf. %3,%2,%1 | |
1638 | #" | |
1639 | [(set_attr "type" "compare") | |
1640 | (set_attr "length" "4,8")]) | |
1641 | ||
1642 | (define_split | |
1643 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1644 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1645 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1646 | (const_int 0))) | |
1647 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1648 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1649 | [(set (match_dup 3) |
1650 | (minus:SI (match_dup 1) | |
1651 | (match_dup 2))) | |
1652 | (set (match_dup 0) | |
1653 | (compare:CC (match_dup 3) | |
1654 | (const_int 0)))] | |
1655 | "") | |
deb9225a | 1656 | |
1fd4e8c1 | 1657 | (define_insn "" |
cb8cc086 MM |
1658 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1659 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1660 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1661 | (const_int 0))) |
cb8cc086 | 1662 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1663 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1664 | "! TARGET_POWERPC" |
cb8cc086 MM |
1665 | "@ |
1666 | {sf.|subfc.} %0,%2,%1 | |
1667 | #" | |
1668 | [(set_attr "type" "compare") | |
1669 | (set_attr "length" "4,8")]) | |
815cdc52 | 1670 | |
29ae5b89 | 1671 | (define_insn "" |
cb8cc086 MM |
1672 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1673 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1674 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1675 | (const_int 0))) |
cb8cc086 MM |
1676 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1677 | (minus:SI (match_dup 1) | |
1678 | (match_dup 2)))] | |
0ad91047 | 1679 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1680 | "@ |
1681 | subf. %0,%2,%1 | |
1682 | #" | |
cb8cc086 MM |
1683 | [(set_attr "type" "compare") |
1684 | (set_attr "length" "4,8")]) | |
1685 | ||
1686 | (define_split | |
1687 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1688 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1689 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1690 | (const_int 0))) | |
1691 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1692 | (minus:SI (match_dup 1) | |
1693 | (match_dup 2)))] | |
0ad91047 | 1694 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1695 | [(set (match_dup 0) |
1696 | (minus:SI (match_dup 1) | |
1697 | (match_dup 2))) | |
1698 | (set (match_dup 3) | |
1699 | (compare:CC (match_dup 0) | |
1700 | (const_int 0)))] | |
1701 | "") | |
deb9225a | 1702 | |
1fd4e8c1 | 1703 | (define_expand "subsi3" |
cd2b37d9 | 1704 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1705 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1706 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1707 | "" |
a0044fb1 RK |
1708 | " |
1709 | { | |
1710 | if (GET_CODE (operands[2]) == CONST_INT) | |
1711 | { | |
1712 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1713 | negate_rtx (SImode, operands[2]))); | |
1714 | DONE; | |
1715 | } | |
1716 | }") | |
1fd4e8c1 RK |
1717 | |
1718 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1719 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1720 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1721 | ;; combine. | |
1fd4e8c1 RK |
1722 | |
1723 | (define_expand "sminsi3" | |
1724 | [(set (match_dup 3) | |
cd2b37d9 | 1725 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1726 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1727 | (const_int 0) | |
1728 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1729 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1730 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1731 | "TARGET_POWER" |
1fd4e8c1 RK |
1732 | " |
1733 | { operands[3] = gen_reg_rtx (SImode); }") | |
1734 | ||
95ac8e67 RK |
1735 | (define_split |
1736 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1737 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1738 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1739 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1740 | "TARGET_POWER" |
95ac8e67 RK |
1741 | [(set (match_dup 3) |
1742 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1743 | (const_int 0) | |
1744 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1745 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1746 | "") | |
1747 | ||
1fd4e8c1 RK |
1748 | (define_expand "smaxsi3" |
1749 | [(set (match_dup 3) | |
cd2b37d9 | 1750 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1751 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1752 | (const_int 0) | |
1753 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1754 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1755 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1756 | "TARGET_POWER" |
1fd4e8c1 RK |
1757 | " |
1758 | { operands[3] = gen_reg_rtx (SImode); }") | |
1759 | ||
95ac8e67 RK |
1760 | (define_split |
1761 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1762 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1763 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1764 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1765 | "TARGET_POWER" |
95ac8e67 RK |
1766 | [(set (match_dup 3) |
1767 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1768 | (const_int 0) | |
1769 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1770 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1771 | "") | |
1772 | ||
1fd4e8c1 | 1773 | (define_expand "uminsi3" |
cd2b37d9 | 1774 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1775 | (match_dup 5))) |
cd2b37d9 | 1776 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1777 | (match_dup 5))) |
1fd4e8c1 RK |
1778 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1779 | (const_int 0) | |
1780 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1781 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1782 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1783 | "TARGET_POWER" |
1fd4e8c1 | 1784 | " |
bb68ff55 MM |
1785 | { |
1786 | operands[3] = gen_reg_rtx (SImode); | |
1787 | operands[4] = gen_reg_rtx (SImode); | |
1788 | operands[5] = GEN_INT (-2147483647 - 1); | |
1789 | }") | |
1fd4e8c1 RK |
1790 | |
1791 | (define_expand "umaxsi3" | |
cd2b37d9 | 1792 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1793 | (match_dup 5))) |
cd2b37d9 | 1794 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1795 | (match_dup 5))) |
1fd4e8c1 RK |
1796 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1797 | (const_int 0) | |
1798 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1799 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1800 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1801 | "TARGET_POWER" |
1fd4e8c1 | 1802 | " |
bb68ff55 MM |
1803 | { |
1804 | operands[3] = gen_reg_rtx (SImode); | |
1805 | operands[4] = gen_reg_rtx (SImode); | |
1806 | operands[5] = GEN_INT (-2147483647 - 1); | |
1807 | }") | |
1fd4e8c1 RK |
1808 | |
1809 | (define_insn "" | |
cd2b37d9 RK |
1810 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1811 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1812 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1813 | (const_int 0) |
1814 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1815 | "TARGET_POWER" |
1fd4e8c1 RK |
1816 | "doz%I2 %0,%1,%2") |
1817 | ||
1818 | (define_insn "" | |
9ebbca7d | 1819 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1820 | (compare:CC |
9ebbca7d GK |
1821 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1822 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1823 | (const_int 0) |
1824 | (minus:SI (match_dup 2) (match_dup 1))) | |
1825 | (const_int 0))) | |
9ebbca7d | 1826 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1827 | "TARGET_POWER" |
9ebbca7d GK |
1828 | "@ |
1829 | doz%I2. %3,%1,%2 | |
1830 | #" | |
1831 | [(set_attr "type" "delayed_compare") | |
1832 | (set_attr "length" "4,8")]) | |
1833 | ||
1834 | (define_split | |
1835 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1836 | (compare:CC | |
1837 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1838 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1839 | (const_int 0) | |
1840 | (minus:SI (match_dup 2) (match_dup 1))) | |
1841 | (const_int 0))) | |
1842 | (clobber (match_scratch:SI 3 ""))] | |
1843 | "TARGET_POWER && reload_completed" | |
1844 | [(set (match_dup 3) | |
1845 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1846 | (const_int 0) | |
1847 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1848 | (set (match_dup 0) | |
1849 | (compare:CC (match_dup 3) | |
1850 | (const_int 0)))] | |
1851 | "") | |
1fd4e8c1 RK |
1852 | |
1853 | (define_insn "" | |
9ebbca7d | 1854 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1855 | (compare:CC |
9ebbca7d GK |
1856 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1857 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1858 | (const_int 0) |
1859 | (minus:SI (match_dup 2) (match_dup 1))) | |
1860 | (const_int 0))) | |
9ebbca7d | 1861 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1862 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1863 | (const_int 0) | |
1864 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1865 | "TARGET_POWER" |
9ebbca7d GK |
1866 | "@ |
1867 | doz%I2. %0,%1,%2 | |
1868 | #" | |
1869 | [(set_attr "type" "delayed_compare") | |
1870 | (set_attr "length" "4,8")]) | |
1871 | ||
1872 | (define_split | |
1873 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1874 | (compare:CC | |
1875 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1876 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1877 | (const_int 0) | |
1878 | (minus:SI (match_dup 2) (match_dup 1))) | |
1879 | (const_int 0))) | |
1880 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1881 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1882 | (const_int 0) | |
1883 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1884 | "TARGET_POWER && reload_completed" | |
1885 | [(set (match_dup 0) | |
1886 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1887 | (const_int 0) | |
1888 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1889 | (set (match_dup 3) | |
1890 | (compare:CC (match_dup 0) | |
1891 | (const_int 0)))] | |
1892 | "") | |
1fd4e8c1 RK |
1893 | |
1894 | ;; We don't need abs with condition code because such comparisons should | |
1895 | ;; never be done. | |
ea9be077 MM |
1896 | (define_expand "abssi2" |
1897 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1898 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1899 | "" | |
1900 | " | |
1901 | { | |
0ad91047 | 1902 | if (! TARGET_POWER) |
ea9be077 MM |
1903 | { |
1904 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1905 | DONE; | |
1906 | } | |
1907 | }") | |
1908 | ||
1909 | (define_insn "abssi2_power" | |
cd2b37d9 RK |
1910 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1911 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1912 | "TARGET_POWER" |
1fd4e8c1 RK |
1913 | "abs %0,%1") |
1914 | ||
ea9be077 MM |
1915 | (define_insn "abssi2_nopower" |
1916 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1917 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1918 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1919 | "! TARGET_POWER" |
3595d104 MM |
1920 | "* |
1921 | { | |
1922 | return (TARGET_POWERPC) | |
1923 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" | |
1924 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; | |
1925 | }" | |
ea9be077 MM |
1926 | [(set_attr "length" "12")]) |
1927 | ||
1928 | (define_split | |
1929 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1930 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1931 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1932 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
1933 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1934 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1935 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1936 | "") |
1937 | ||
463b558b | 1938 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1939 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1940 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1941 | "TARGET_POWER" |
1fd4e8c1 RK |
1942 | "nabs %0,%1") |
1943 | ||
463b558b | 1944 | (define_insn "*nabs_no_power" |
ea9be077 MM |
1945 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
1946 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1947 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1948 | "! TARGET_POWER" |
3595d104 MM |
1949 | "* |
1950 | { | |
1951 | return (TARGET_POWERPC) | |
1952 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" | |
1953 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; | |
1954 | }" | |
ea9be077 MM |
1955 | [(set_attr "length" "12")]) |
1956 | ||
1957 | (define_split | |
1958 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1959 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1960 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1961 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
1962 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1963 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1964 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1965 | "") |
1966 | ||
1fd4e8c1 | 1967 | (define_insn "negsi2" |
cd2b37d9 RK |
1968 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1969 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1970 | "" |
1971 | "neg %0,%1") | |
1972 | ||
1973 | (define_insn "" | |
9ebbca7d GK |
1974 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1975 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1976 | (const_int 0))) |
9ebbca7d | 1977 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1978 | "! TARGET_POWERPC64" |
9ebbca7d GK |
1979 | "@ |
1980 | neg. %2,%1 | |
1981 | #" | |
1982 | [(set_attr "type" "compare") | |
1983 | (set_attr "length" "4,8")]) | |
1984 | ||
1985 | (define_split | |
1986 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1987 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1988 | (const_int 0))) | |
1989 | (clobber (match_scratch:SI 2 ""))] | |
1990 | "! TARGET_POWERPC64 && reload_completed" | |
1991 | [(set (match_dup 2) | |
1992 | (neg:SI (match_dup 1))) | |
1993 | (set (match_dup 0) | |
1994 | (compare:CC (match_dup 2) | |
1995 | (const_int 0)))] | |
1996 | "") | |
1fd4e8c1 RK |
1997 | |
1998 | (define_insn "" | |
9ebbca7d GK |
1999 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
2000 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2001 | (const_int 0))) |
9ebbca7d | 2002 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 2003 | (neg:SI (match_dup 1)))] |
0ad91047 | 2004 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2005 | "@ |
2006 | neg. %0,%1 | |
2007 | #" | |
2008 | [(set_attr "type" "compare") | |
2009 | (set_attr "length" "4,8")]) | |
2010 | ||
2011 | (define_split | |
2012 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
2013 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2014 | (const_int 0))) | |
2015 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2016 | (neg:SI (match_dup 1)))] | |
2017 | "! TARGET_POWERPC64 && reload_completed" | |
2018 | [(set (match_dup 0) | |
2019 | (neg:SI (match_dup 1))) | |
2020 | (set (match_dup 2) | |
2021 | (compare:CC (match_dup 0) | |
2022 | (const_int 0)))] | |
2023 | "") | |
1fd4e8c1 RK |
2024 | |
2025 | (define_insn "ffssi2" | |
242e8072 RK |
2026 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
2027 | (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 2028 | "" |
7f340546 | 2029 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 2030 | [(set_attr "length" "16")]) |
1fd4e8c1 | 2031 | |
ca7f5001 RK |
2032 | (define_expand "mulsi3" |
2033 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2034 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2035 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
2036 | "" | |
2037 | " | |
2038 | { | |
2039 | if (TARGET_POWER) | |
68b40e7e | 2040 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 2041 | else |
68b40e7e | 2042 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2043 | DONE; |
2044 | }") | |
2045 | ||
68b40e7e | 2046 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
2047 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2048 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
2049 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
2050 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
2051 | "TARGET_POWER" |
2052 | "@ | |
2053 | {muls|mullw} %0,%1,%2 | |
2054 | {muli|mulli} %0,%1,%2" | |
2055 | [(set_attr "type" "imul")]) | |
2056 | ||
68b40e7e | 2057 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
2058 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2059 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2060 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 2061 | "! TARGET_POWER" |
1fd4e8c1 | 2062 | "@ |
d904e9ed RK |
2063 | {muls|mullw} %0,%1,%2 |
2064 | {muli|mulli} %0,%1,%2" | |
cfb557c4 | 2065 | [(set_attr "type" "imul")]) |
1fd4e8c1 RK |
2066 | |
2067 | (define_insn "" | |
9ebbca7d GK |
2068 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2069 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2070 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2071 | (const_int 0))) |
9ebbca7d GK |
2072 | (clobber (match_scratch:SI 3 "=r,r")) |
2073 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 2074 | "TARGET_POWER" |
9ebbca7d GK |
2075 | "@ |
2076 | {muls.|mullw.} %3,%1,%2 | |
2077 | #" | |
2078 | [(set_attr "type" "delayed_compare") | |
2079 | (set_attr "length" "4,8")]) | |
2080 | ||
2081 | (define_split | |
2082 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2083 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2084 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2085 | (const_int 0))) | |
2086 | (clobber (match_scratch:SI 3 "")) | |
2087 | (clobber (match_scratch:SI 4 ""))] | |
2088 | "TARGET_POWER && reload_completed" | |
2089 | [(parallel [(set (match_dup 3) | |
2090 | (mult:SI (match_dup 1) (match_dup 2))) | |
2091 | (clobber (match_dup 4))]) | |
2092 | (set (match_dup 0) | |
2093 | (compare:CC (match_dup 3) | |
2094 | (const_int 0)))] | |
2095 | "") | |
ca7f5001 RK |
2096 | |
2097 | (define_insn "" | |
9ebbca7d GK |
2098 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2099 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2100 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2101 | (const_int 0))) |
9ebbca7d | 2102 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 2103 | "! TARGET_POWER" |
9ebbca7d GK |
2104 | "@ |
2105 | {muls.|mullw.} %3,%1,%2 | |
2106 | #" | |
2107 | [(set_attr "type" "delayed_compare") | |
2108 | (set_attr "length" "4,8")]) | |
2109 | ||
2110 | (define_split | |
2111 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2112 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2113 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2114 | (const_int 0))) | |
2115 | (clobber (match_scratch:SI 3 ""))] | |
2116 | "! TARGET_POWER && reload_completed" | |
2117 | [(set (match_dup 3) | |
2118 | (mult:SI (match_dup 1) (match_dup 2))) | |
2119 | (set (match_dup 0) | |
2120 | (compare:CC (match_dup 3) | |
2121 | (const_int 0)))] | |
2122 | "") | |
1fd4e8c1 RK |
2123 | |
2124 | (define_insn "" | |
9ebbca7d GK |
2125 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2126 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2127 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2128 | (const_int 0))) |
9ebbca7d | 2129 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2130 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 2131 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 2132 | "TARGET_POWER" |
9ebbca7d GK |
2133 | "@ |
2134 | {muls.|mullw.} %0,%1,%2 | |
2135 | #" | |
2136 | [(set_attr "type" "delayed_compare") | |
2137 | (set_attr "length" "4,8")]) | |
2138 | ||
2139 | (define_split | |
2140 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2141 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2142 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2143 | (const_int 0))) | |
2144 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2145 | (mult:SI (match_dup 1) (match_dup 2))) | |
2146 | (clobber (match_scratch:SI 4 ""))] | |
2147 | "TARGET_POWER && reload_completed" | |
2148 | [(parallel [(set (match_dup 0) | |
2149 | (mult:SI (match_dup 1) (match_dup 2))) | |
2150 | (clobber (match_dup 4))]) | |
2151 | (set (match_dup 3) | |
2152 | (compare:CC (match_dup 0) | |
2153 | (const_int 0)))] | |
2154 | "") | |
ca7f5001 RK |
2155 | |
2156 | (define_insn "" | |
9ebbca7d GK |
2157 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2158 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2159 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2160 | (const_int 0))) |
9ebbca7d | 2161 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 2162 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 2163 | "! TARGET_POWER" |
9ebbca7d GK |
2164 | "@ |
2165 | {muls.|mullw.} %0,%1,%2 | |
2166 | #" | |
2167 | [(set_attr "type" "delayed_compare") | |
2168 | (set_attr "length" "4,8")]) | |
2169 | ||
2170 | (define_split | |
2171 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2172 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2173 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2174 | (const_int 0))) | |
2175 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2176 | (mult:SI (match_dup 1) (match_dup 2)))] | |
2177 | "! TARGET_POWER && reload_completed" | |
2178 | [(set (match_dup 0) | |
2179 | (mult:SI (match_dup 1) (match_dup 2))) | |
2180 | (set (match_dup 3) | |
2181 | (compare:CC (match_dup 0) | |
2182 | (const_int 0)))] | |
2183 | "") | |
1fd4e8c1 RK |
2184 | |
2185 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
2186 | ;; 0 and remainder to operand 3. | |
2187 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
2188 | ||
8ffd9c51 RK |
2189 | (define_expand "divmodsi4" |
2190 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2191 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2192 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2193 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
2194 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
2195 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2196 | " | |
2197 | { | |
2198 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2199 | { | |
39403d82 DE |
2200 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2201 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2202 | emit_insn (gen_divss_call ()); |
39403d82 DE |
2203 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2204 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
2205 | DONE; |
2206 | } | |
2207 | }") | |
deb9225a | 2208 | |
fada905b | 2209 | (define_insn "" |
cd2b37d9 RK |
2210 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2211 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2212 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2213 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 2214 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 2215 | "TARGET_POWER" |
cfb557c4 RK |
2216 | "divs %0,%1,%2" |
2217 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 2218 | |
8ffd9c51 RK |
2219 | (define_expand "udivsi3" |
2220 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2221 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2222 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
2223 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2224 | " | |
2225 | { | |
2226 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2227 | { | |
39403d82 DE |
2228 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2229 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2230 | emit_insn (gen_quous_call ()); |
39403d82 | 2231 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2232 | DONE; |
2233 | } | |
f192bf8b DE |
2234 | else if (TARGET_POWER) |
2235 | { | |
2236 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
2237 | DONE; | |
2238 | } | |
8ffd9c51 | 2239 | }") |
deb9225a | 2240 | |
f192bf8b DE |
2241 | (define_insn "udivsi3_mq" |
2242 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2243 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2244 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2245 | (clobber (match_scratch:SI 3 "=q"))] | |
2246 | "TARGET_POWERPC && TARGET_POWER" | |
2247 | "divwu %0,%1,%2" | |
2248 | [(set_attr "type" "idiv")]) | |
2249 | ||
2250 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
2251 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2252 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2253 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 2254 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 2255 | "divwu %0,%1,%2" |
ca7f5001 RK |
2256 | [(set_attr "type" "idiv")]) |
2257 | ||
1fd4e8c1 | 2258 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 2259 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
2260 | ;; used; for PowerPC, force operands into register and do a normal divide; |
2261 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 2262 | (define_expand "divsi3" |
cd2b37d9 RK |
2263 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2264 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
2265 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
2266 | "" | |
2267 | " | |
2268 | { | |
ca7f5001 | 2269 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 2270 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
2271 | && exact_log2 (INTVAL (operands[2])) >= 0) |
2272 | ; | |
b6c9286a | 2273 | else if (TARGET_POWERPC) |
f192bf8b DE |
2274 | { |
2275 | operands[2] = force_reg (SImode, operands[2]); | |
2276 | if (TARGET_POWER) | |
2277 | { | |
2278 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
2279 | DONE; | |
2280 | } | |
2281 | } | |
b6c9286a | 2282 | else if (TARGET_POWER) |
1fd4e8c1 | 2283 | FAIL; |
405c5495 | 2284 | else |
8ffd9c51 | 2285 | { |
39403d82 DE |
2286 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2287 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2288 | emit_insn (gen_quoss_call ()); |
39403d82 | 2289 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2290 | DONE; |
2291 | } | |
1fd4e8c1 RK |
2292 | }") |
2293 | ||
f192bf8b DE |
2294 | (define_insn "divsi3_mq" |
2295 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2296 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2297 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2298 | (clobber (match_scratch:SI 3 "=q"))] | |
2299 | "TARGET_POWERPC && TARGET_POWER" | |
2300 | "divw %0,%1,%2" | |
2301 | [(set_attr "type" "idiv")]) | |
2302 | ||
2303 | (define_insn "*divsi3_no_mq" | |
2304 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2305 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2306 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
2307 | "TARGET_POWERPC && ! TARGET_POWER" | |
2308 | "divw %0,%1,%2" | |
2309 | [(set_attr "type" "idiv")]) | |
2310 | ||
1fd4e8c1 | 2311 | (define_expand "modsi3" |
85644414 RK |
2312 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
2313 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 2314 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 2315 | "" |
1fd4e8c1 RK |
2316 | " |
2317 | { | |
481c7efa | 2318 | int i; |
39b52ba2 RK |
2319 | rtx temp1; |
2320 | rtx temp2; | |
2321 | ||
2bfcf297 DB |
2322 | if (GET_CODE (operands[2]) != CONST_INT |
2323 | || INTVAL (operands[2]) < 0 | |
2324 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
39b52ba2 RK |
2325 | FAIL; |
2326 | ||
2327 | temp1 = gen_reg_rtx (SImode); | |
2328 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 2329 | |
85644414 | 2330 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 2331 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
2332 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
2333 | DONE; | |
1fd4e8c1 RK |
2334 | }") |
2335 | ||
2336 | (define_insn "" | |
cd2b37d9 RK |
2337 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2338 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
2339 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
2340 | "" | |
ca7f5001 | 2341 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 2342 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
2343 | |
2344 | (define_insn "" | |
9ebbca7d GK |
2345 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2346 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2347 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2348 | (const_int 0))) |
9ebbca7d | 2349 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 2350 | "" |
9ebbca7d GK |
2351 | "@ |
2352 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
2353 | #" | |
b19003d8 | 2354 | [(set_attr "type" "compare") |
9ebbca7d GK |
2355 | (set_attr "length" "8,12")]) |
2356 | ||
2357 | (define_split | |
2358 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2359 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2360 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2361 | (const_int 0))) |
2362 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 2363 | "reload_completed" |
9ebbca7d GK |
2364 | [(set (match_dup 3) |
2365 | (div:SI (match_dup 1) (match_dup 2))) | |
2366 | (set (match_dup 0) | |
2367 | (compare:CC (match_dup 3) | |
2368 | (const_int 0)))] | |
2369 | "") | |
1fd4e8c1 RK |
2370 | |
2371 | (define_insn "" | |
9ebbca7d GK |
2372 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2373 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2374 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2375 | (const_int 0))) |
9ebbca7d | 2376 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2377 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2378 | "" |
9ebbca7d GK |
2379 | "@ |
2380 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2381 | #" | |
b19003d8 | 2382 | [(set_attr "type" "compare") |
9ebbca7d GK |
2383 | (set_attr "length" "8,12")]) |
2384 | ||
2385 | (define_split | |
2386 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2387 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2388 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2389 | (const_int 0))) |
2390 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2391 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2392 | "reload_completed" |
9ebbca7d GK |
2393 | [(set (match_dup 0) |
2394 | (div:SI (match_dup 1) (match_dup 2))) | |
2395 | (set (match_dup 3) | |
2396 | (compare:CC (match_dup 0) | |
2397 | (const_int 0)))] | |
2398 | "") | |
1fd4e8c1 RK |
2399 | |
2400 | (define_insn "" | |
cd2b37d9 | 2401 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2402 | (udiv:SI |
996a5f59 | 2403 | (plus:DI (ashift:DI |
cd2b37d9 | 2404 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2405 | (const_int 32)) |
23a900dc | 2406 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2407 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2408 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2409 | (umod:SI |
996a5f59 | 2410 | (plus:DI (ashift:DI |
1fd4e8c1 | 2411 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2412 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2413 | (match_dup 3)))] |
ca7f5001 | 2414 | "TARGET_POWER" |
cfb557c4 RK |
2415 | "div %0,%1,%3" |
2416 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2417 | |
2418 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2419 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2420 | ;; have to worry about the branches. So make a few subroutines here. | |
2421 | ;; | |
2422 | ;; First comes the normal case. | |
2423 | (define_expand "udivmodsi4_normal" | |
2424 | [(set (match_dup 4) (const_int 0)) | |
2425 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2426 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2427 | (const_int 32)) |
2428 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2429 | (match_operand:SI 2 "" ""))) | |
2430 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2431 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2432 | (const_int 32)) |
2433 | (zero_extend:DI (match_dup 1))) | |
2434 | (match_dup 2)))])] | |
ca7f5001 | 2435 | "TARGET_POWER" |
1fd4e8c1 RK |
2436 | " |
2437 | { operands[4] = gen_reg_rtx (SImode); }") | |
2438 | ||
2439 | ;; This handles the branches. | |
2440 | (define_expand "udivmodsi4_tests" | |
2441 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2442 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2443 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2444 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2445 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2446 | (set (match_dup 0) (const_int 1)) | |
2447 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2448 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2449 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2450 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2451 | "TARGET_POWER" |
1fd4e8c1 RK |
2452 | " |
2453 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2454 | operands[6] = gen_reg_rtx (CCmode); | |
2455 | }") | |
2456 | ||
2457 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2458 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2459 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2460 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2461 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2462 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2463 | "" |
1fd4e8c1 RK |
2464 | " |
2465 | { | |
2466 | rtx label = 0; | |
2467 | ||
8ffd9c51 | 2468 | if (! TARGET_POWER) |
c4d38ccb MM |
2469 | { |
2470 | if (! TARGET_POWERPC) | |
2471 | { | |
39403d82 DE |
2472 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2473 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2474 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2475 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2476 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2477 | DONE; |
2478 | } | |
2479 | else | |
2480 | FAIL; | |
2481 | } | |
0081a354 | 2482 | |
1fd4e8c1 RK |
2483 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2484 | { | |
2485 | operands[2] = force_reg (SImode, operands[2]); | |
2486 | label = gen_label_rtx (); | |
2487 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2488 | operands[3], label)); | |
2489 | } | |
2490 | else | |
2491 | operands[2] = force_reg (SImode, operands[2]); | |
2492 | ||
2493 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2494 | operands[3])); | |
2495 | if (label) | |
2496 | emit_label (label); | |
2497 | ||
2498 | DONE; | |
2499 | }") | |
0081a354 | 2500 | |
fada905b MM |
2501 | ;; AIX architecture-independent common-mode multiply (DImode), |
2502 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2503 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2504 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2505 | ;; assumed unused if generating common-mode, so ignore. | |
2506 | (define_insn "mulh_call" | |
2507 | [(set (reg:SI 3) | |
2508 | (truncate:SI | |
2509 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2510 | (sign_extend:DI (reg:SI 4))) | |
2511 | (const_int 32)))) | |
cf27b467 | 2512 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2513 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2514 | "bla __mulh" |
2515 | [(set_attr "type" "imul")]) | |
fada905b MM |
2516 | |
2517 | (define_insn "mull_call" | |
2518 | [(set (reg:DI 3) | |
2519 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2520 | (sign_extend:DI (reg:SI 4)))) | |
2521 | (clobber (match_scratch:SI 0 "=l")) | |
2522 | (clobber (reg:SI 0))] | |
2523 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2524 | "bla __mull" |
2525 | [(set_attr "type" "imul")]) | |
fada905b MM |
2526 | |
2527 | (define_insn "divss_call" | |
2528 | [(set (reg:SI 3) | |
2529 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2530 | (set (reg:SI 4) | |
2531 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2532 | (clobber (match_scratch:SI 0 "=l")) | |
2533 | (clobber (reg:SI 0))] | |
2534 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2535 | "bla __divss" |
2536 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2537 | |
2538 | (define_insn "divus_call" | |
8ffd9c51 RK |
2539 | [(set (reg:SI 3) |
2540 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2541 | (set (reg:SI 4) | |
2542 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2543 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2544 | (clobber (reg:SI 0)) |
2545 | (clobber (match_scratch:CC 1 "=x")) | |
2546 | (clobber (reg:CC 69))] | |
2547 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2548 | "bla __divus" |
2549 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2550 | |
2551 | (define_insn "quoss_call" | |
2552 | [(set (reg:SI 3) | |
2553 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2554 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2555 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2556 | "bla __quoss" |
2557 | [(set_attr "type" "idiv")]) | |
0081a354 | 2558 | |
fada905b MM |
2559 | (define_insn "quous_call" |
2560 | [(set (reg:SI 3) | |
2561 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2562 | (clobber (match_scratch:SI 0 "=l")) | |
2563 | (clobber (reg:SI 0)) | |
2564 | (clobber (match_scratch:CC 1 "=x")) | |
2565 | (clobber (reg:CC 69))] | |
2566 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2567 | "bla __quous" |
2568 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2569 | \f |
bb21487f | 2570 | ;; Logical instructions |
dfbdccdb GK |
2571 | ;; The logical instructions are mostly combined by using match_operator, |
2572 | ;; but the plain AND insns are somewhat different because there is no | |
2573 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2574 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2575 | ||
29ae5b89 JL |
2576 | (define_insn "andsi3" |
2577 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2578 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2579 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2580 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2581 | "" |
2582 | "@ | |
2583 | and %0,%1,%2 | |
ca7f5001 RK |
2584 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2585 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2586 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2587 | |
2588 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
2589 | ;; the test again -- this avoids a mcrf which on the higher end | |
2590 | ;; machines causes an execution serialization | |
1fd4e8c1 | 2591 | |
7cd5235b | 2592 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2593 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2594 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2595 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2596 | (const_int 0))) |
52d3af72 DE |
2597 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2598 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2599 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2600 | "@ |
2601 | and. %3,%1,%2 | |
ca7f5001 RK |
2602 | {andil.|andi.} %3,%1,%b2 |
2603 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2604 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2605 | # | |
2606 | # | |
2607 | # | |
2608 | #" | |
2609 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2610 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2611 | |
52d3af72 DE |
2612 | (define_split |
2613 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2614 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2615 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2616 | (const_int 0))) |
52d3af72 DE |
2617 | (clobber (match_scratch:SI 3 "")) |
2618 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2619 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2620 | [(parallel [(set (match_dup 3) |
2621 | (and:SI (match_dup 1) | |
2622 | (match_dup 2))) | |
2623 | (clobber (match_dup 4))]) | |
2624 | (set (match_dup 0) | |
2625 | (compare:CC (match_dup 3) | |
2626 | (const_int 0)))] | |
2627 | "") | |
2628 | ||
2629 | (define_insn "*andsi3_internal3" | |
2630 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2631 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2632 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2633 | (const_int 0))) |
2634 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2635 | (and:SI (match_dup 1) | |
2636 | (match_dup 2))) | |
2637 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2638 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2639 | "@ |
2640 | and. %0,%1,%2 | |
ca7f5001 RK |
2641 | {andil.|andi.} %0,%1,%b2 |
2642 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2643 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2644 | # | |
2645 | # | |
2646 | # | |
2647 | #" | |
2648 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2649 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2650 | ||
2651 | (define_split | |
2652 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2653 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2654 | (match_operand:SI 2 "and_operand" "")) | |
2655 | (const_int 0))) | |
2656 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2657 | (and:SI (match_dup 1) | |
2658 | (match_dup 2))) | |
2659 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2660 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2661 | [(parallel [(set (match_dup 0) |
2662 | (and:SI (match_dup 1) | |
2663 | (match_dup 2))) | |
2664 | (clobber (match_dup 4))]) | |
2665 | (set (match_dup 3) | |
2666 | (compare:CC (match_dup 0) | |
2667 | (const_int 0)))] | |
2668 | "") | |
1fd4e8c1 | 2669 | |
7cd5235b | 2670 | (define_expand "iorsi3" |
cd2b37d9 | 2671 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2672 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2673 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2674 | "" |
f357808b RK |
2675 | " |
2676 | { | |
7cd5235b | 2677 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2678 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2679 | { |
2680 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2681 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2682 | ? operands[0] : gen_reg_rtx (SImode)); |
2683 | ||
a260abc9 DE |
2684 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2685 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2686 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2687 | DONE; |
2688 | } | |
f357808b RK |
2689 | }") |
2690 | ||
7cd5235b | 2691 | (define_expand "xorsi3" |
cd2b37d9 | 2692 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2693 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2694 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2695 | "" |
7cd5235b | 2696 | " |
1fd4e8c1 | 2697 | { |
7cd5235b | 2698 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2699 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2700 | { |
2701 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2702 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2703 | ? operands[0] : gen_reg_rtx (SImode)); |
2704 | ||
a260abc9 DE |
2705 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2706 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2707 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2708 | DONE; |
2709 | } | |
1fd4e8c1 RK |
2710 | }") |
2711 | ||
dfbdccdb | 2712 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2713 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2714 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2715 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2716 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2717 | "" |
2718 | "@ | |
dfbdccdb GK |
2719 | %q3 %0,%1,%2 |
2720 | {%q3il|%q3i} %0,%1,%b2 | |
2721 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2722 | |
dfbdccdb | 2723 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2724 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2725 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2726 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2727 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2728 | (const_int 0))) | |
52d3af72 | 2729 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2730 | "! TARGET_POWERPC64" |
52d3af72 | 2731 | "@ |
dfbdccdb | 2732 | %q4. %3,%1,%2 |
52d3af72 DE |
2733 | #" |
2734 | [(set_attr "type" "compare") | |
2735 | (set_attr "length" "4,8")]) | |
2736 | ||
2737 | (define_split | |
2738 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2739 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2740 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2741 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2742 | (const_int 0))) | |
52d3af72 | 2743 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2744 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2745 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2746 | (set (match_dup 0) |
2747 | (compare:CC (match_dup 3) | |
2748 | (const_int 0)))] | |
2749 | "") | |
815cdc52 | 2750 | |
dfbdccdb | 2751 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2752 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2753 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2754 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2755 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2756 | (const_int 0))) | |
52d3af72 | 2757 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2758 | (match_dup 4))] |
0ad91047 | 2759 | "! TARGET_POWERPC64" |
52d3af72 | 2760 | "@ |
dfbdccdb | 2761 | %q4. %0,%1,%2 |
52d3af72 DE |
2762 | #" |
2763 | [(set_attr "type" "compare") | |
2764 | (set_attr "length" "4,8")]) | |
2765 | ||
2766 | (define_split | |
dfbdccdb GK |
2767 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2768 | (compare:CC (match_operator:SI 4 "boolean_operator" | |
2769 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2770 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2771 | (const_int 0))) | |
2772 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
2773 | (match_dup 4))] | |
0ad91047 | 2774 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2775 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2776 | (set (match_dup 3) |
2777 | (compare:CC (match_dup 0) | |
2778 | (const_int 0)))] | |
2779 | "") | |
1fd4e8c1 | 2780 | |
dfbdccdb GK |
2781 | ;; Split an logical operation that we can't do in one insn into two insns, |
2782 | ;; each of which does one 16-bit part. This is used by combine. | |
a260abc9 DE |
2783 | |
2784 | (define_split | |
2785 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2786 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2787 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2788 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2789 | "" |
dfbdccdb GK |
2790 | [(set (match_dup 0) (match_dup 4)) |
2791 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2792 | " |
2793 | { | |
dfbdccdb GK |
2794 | rtx i; |
2795 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2796 | operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2797 | operands[1], i); | |
2798 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2799 | operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2800 | operands[0], i); | |
a260abc9 DE |
2801 | }") |
2802 | ||
dfbdccdb | 2803 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2804 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2805 | (match_operator:SI 3 "boolean_operator" |
2806 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2807 | (match_operand:SI 2 "logical_operand" "r")]))] | |
1fd4e8c1 | 2808 | "" |
dfbdccdb | 2809 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2810 | |
dfbdccdb | 2811 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2812 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2813 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2814 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2815 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2816 | (const_int 0))) | |
52d3af72 | 2817 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2818 | "! TARGET_POWERPC64" |
52d3af72 | 2819 | "@ |
dfbdccdb | 2820 | %q4. %3,%2,%1 |
52d3af72 DE |
2821 | #" |
2822 | [(set_attr "type" "compare") | |
2823 | (set_attr "length" "4,8")]) | |
2824 | ||
2825 | (define_split | |
2826 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2827 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2828 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2829 | (match_operand:SI 2 "gpc_reg_operand" "r")]) | |
2830 | (const_int 0))) | |
52d3af72 | 2831 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2832 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2833 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2834 | (set (match_dup 0) |
2835 | (compare:CC (match_dup 3) | |
2836 | (const_int 0)))] | |
2837 | "") | |
1fd4e8c1 | 2838 | |
dfbdccdb | 2839 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2840 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2841 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2842 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2843 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2844 | (const_int 0))) | |
52d3af72 | 2845 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2846 | (match_dup 4))] |
0ad91047 | 2847 | "! TARGET_POWERPC64" |
52d3af72 | 2848 | "@ |
dfbdccdb | 2849 | %q4. %0,%2,%1 |
52d3af72 DE |
2850 | #" |
2851 | [(set_attr "type" "compare") | |
2852 | (set_attr "length" "4,8")]) | |
2853 | ||
2854 | (define_split | |
52d3af72 | 2855 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2856 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2857 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2858 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2859 | (const_int 0))) | |
52d3af72 | 2860 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2861 | (match_dup 4))] |
0ad91047 | 2862 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2863 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2864 | (set (match_dup 3) |
2865 | (compare:CC (match_dup 0) | |
2866 | (const_int 0)))] | |
2867 | "") | |
2868 | ||
dfbdccdb | 2869 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2870 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2871 | (match_operator:SI 3 "boolean_operator" |
2872 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2873 | (not:SI (match_operand:SI 2 "logical_operand" "r"))]))] | |
1fd4e8c1 | 2874 | "" |
dfbdccdb | 2875 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2876 | |
dfbdccdb | 2877 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2878 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2879 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2880 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2881 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2882 | (const_int 0))) | |
52d3af72 | 2883 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2884 | "! TARGET_POWERPC64" |
52d3af72 | 2885 | "@ |
dfbdccdb | 2886 | %q4. %3,%1,%2 |
52d3af72 DE |
2887 | #" |
2888 | [(set_attr "type" "compare") | |
2889 | (set_attr "length" "4,8")]) | |
2890 | ||
2891 | (define_split | |
2892 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2893 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2894 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2895 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]) | |
2896 | (const_int 0))) | |
52d3af72 | 2897 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2898 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2899 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2900 | (set (match_dup 0) |
2901 | (compare:CC (match_dup 3) | |
2902 | (const_int 0)))] | |
2903 | "") | |
1fd4e8c1 | 2904 | |
dfbdccdb | 2905 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2906 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2907 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2908 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2909 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2910 | (const_int 0))) | |
52d3af72 | 2911 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2912 | (match_dup 4))] |
0ad91047 | 2913 | "! TARGET_POWERPC64" |
52d3af72 | 2914 | "@ |
dfbdccdb | 2915 | %q4. %0,%1,%2 |
52d3af72 DE |
2916 | #" |
2917 | [(set_attr "type" "compare") | |
2918 | (set_attr "length" "4,8")]) | |
2919 | ||
2920 | (define_split | |
52d3af72 | 2921 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2922 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2923 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2924 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2925 | (const_int 0))) | |
52d3af72 | 2926 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2927 | (match_dup 4))] |
0ad91047 | 2928 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2929 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2930 | (set (match_dup 3) |
2931 | (compare:CC (match_dup 0) | |
2932 | (const_int 0)))] | |
2933 | "") | |
1fd4e8c1 RK |
2934 | |
2935 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2936 | ;; orders. Don't define forms that only set CR fields because these | |
2937 | ;; would modify an input register. | |
2938 | ||
7cd5235b | 2939 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2940 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2941 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2942 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2943 | (and:SI (match_dup 2) | |
cd2b37d9 | 2944 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2945 | "TARGET_POWER" |
01def764 | 2946 | "maskir %0,%3,%2") |
1fd4e8c1 | 2947 | |
7cd5235b | 2948 | (define_insn "*maskir_internal2" |
242e8072 | 2949 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2950 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2951 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2952 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2953 | (match_dup 2))))] |
ca7f5001 | 2954 | "TARGET_POWER" |
01def764 | 2955 | "maskir %0,%3,%2") |
1fd4e8c1 | 2956 | |
7cd5235b | 2957 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2958 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2959 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2960 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2961 | (and:SI (not:SI (match_dup 2)) |
2962 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2963 | "TARGET_POWER" |
01def764 | 2964 | "maskir %0,%3,%2") |
1fd4e8c1 | 2965 | |
7cd5235b | 2966 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2967 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2968 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2969 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2970 | (and:SI (not:SI (match_dup 2)) | |
2971 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2972 | "TARGET_POWER" |
01def764 | 2973 | "maskir %0,%3,%2") |
1fd4e8c1 | 2974 | |
7cd5235b | 2975 | (define_insn "*maskir_internal5" |
9ebbca7d | 2976 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2977 | (compare:CC |
9ebbca7d GK |
2978 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2979 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2980 | (and:SI (match_dup 2) |
9ebbca7d | 2981 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2982 | (const_int 0))) |
9ebbca7d | 2983 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2984 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2985 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2986 | "TARGET_POWER" |
9ebbca7d GK |
2987 | "@ |
2988 | maskir. %0,%3,%2 | |
2989 | #" | |
2990 | [(set_attr "type" "compare") | |
2991 | (set_attr "length" "4,8")]) | |
2992 | ||
2993 | (define_split | |
2994 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2995 | (compare:CC | |
2996 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2997 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2998 | (and:SI (match_dup 2) | |
2999 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
3000 | (const_int 0))) | |
3001 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3002 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3003 | (and:SI (match_dup 2) (match_dup 3))))] | |
3004 | "TARGET_POWER && reload_completed" | |
3005 | [(set (match_dup 0) | |
3006 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3007 | (and:SI (match_dup 2) (match_dup 3)))) | |
3008 | (set (match_dup 4) | |
3009 | (compare:CC (match_dup 0) | |
3010 | (const_int 0)))] | |
3011 | "") | |
1fd4e8c1 | 3012 | |
7cd5235b | 3013 | (define_insn "*maskir_internal6" |
9ebbca7d | 3014 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3015 | (compare:CC |
9ebbca7d GK |
3016 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3017 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
3018 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 3019 | (match_dup 2))) |
1fd4e8c1 | 3020 | (const_int 0))) |
9ebbca7d | 3021 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3022 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3023 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 3024 | "TARGET_POWER" |
9ebbca7d GK |
3025 | "@ |
3026 | maskir. %0,%3,%2 | |
3027 | #" | |
3028 | [(set_attr "type" "compare") | |
3029 | (set_attr "length" "4,8")]) | |
3030 | ||
3031 | (define_split | |
3032 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3033 | (compare:CC | |
3034 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3035 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3036 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3037 | (match_dup 2))) | |
3038 | (const_int 0))) | |
3039 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3040 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3041 | (and:SI (match_dup 3) (match_dup 2))))] | |
3042 | "TARGET_POWER && reload_completed" | |
3043 | [(set (match_dup 0) | |
3044 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3045 | (and:SI (match_dup 3) (match_dup 2)))) | |
3046 | (set (match_dup 4) | |
3047 | (compare:CC (match_dup 0) | |
3048 | (const_int 0)))] | |
3049 | "") | |
1fd4e8c1 | 3050 | |
7cd5235b | 3051 | (define_insn "*maskir_internal7" |
9ebbca7d | 3052 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 3053 | (compare:CC |
9ebbca7d GK |
3054 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
3055 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 3056 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3057 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 3058 | (const_int 0))) |
9ebbca7d | 3059 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
3060 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
3061 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3062 | "TARGET_POWER" | |
9ebbca7d GK |
3063 | "@ |
3064 | maskir. %0,%3,%2 | |
3065 | #" | |
3066 | [(set_attr "type" "compare") | |
3067 | (set_attr "length" "4,8")]) | |
3068 | ||
3069 | (define_split | |
3070 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3071 | (compare:CC | |
3072 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
3073 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
3074 | (and:SI (not:SI (match_dup 2)) | |
3075 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3076 | (const_int 0))) | |
3077 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3078 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3079 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3080 | "TARGET_POWER && reload_completed" | |
3081 | [(set (match_dup 0) | |
3082 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3083 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3084 | (set (match_dup 4) | |
3085 | (compare:CC (match_dup 0) | |
3086 | (const_int 0)))] | |
3087 | "") | |
1fd4e8c1 | 3088 | |
7cd5235b | 3089 | (define_insn "*maskir_internal8" |
9ebbca7d | 3090 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3091 | (compare:CC |
9ebbca7d GK |
3092 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
3093 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 3094 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3095 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 3096 | (const_int 0))) |
9ebbca7d | 3097 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3098 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
3099 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 3100 | "TARGET_POWER" |
9ebbca7d GK |
3101 | "@ |
3102 | maskir. %0,%3,%2 | |
3103 | #" | |
3104 | [(set_attr "type" "compare") | |
3105 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 3106 | \f |
9ebbca7d GK |
3107 | (define_split |
3108 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3109 | (compare:CC | |
3110 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3111 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3112 | (and:SI (not:SI (match_dup 2)) | |
3113 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3114 | (const_int 0))) | |
3115 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3116 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3117 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3118 | "TARGET_POWER && reload_completed" | |
3119 | [(set (match_dup 0) | |
3120 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3121 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3122 | (set (match_dup 4) | |
3123 | (compare:CC (match_dup 0) | |
3124 | (const_int 0)))] | |
3125 | "") | |
3126 | ||
1fd4e8c1 RK |
3127 | ;; Rotate and shift insns, in all their variants. These support shifts, |
3128 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 3129 | (define_expand "insv" |
0ad91047 DE |
3130 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
3131 | (match_operand:SI 1 "const_int_operand" "") | |
3132 | (match_operand:SI 2 "const_int_operand" "")) | |
3133 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
3134 | "" |
3135 | " | |
3136 | { | |
3137 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3138 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3139 | compiler if the address of the structure is taken later. */ | |
3140 | if (GET_CODE (operands[0]) == SUBREG | |
3141 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3142 | FAIL; | |
a78e33fc DE |
3143 | |
3144 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
3145 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
3146 | else | |
3147 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
3148 | DONE; | |
034c1be0 MM |
3149 | }") |
3150 | ||
a78e33fc | 3151 | (define_insn "insvsi" |
cd2b37d9 | 3152 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
3153 | (match_operand:SI 1 "const_int_operand" "i") |
3154 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 3155 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
3156 | "" |
3157 | "* | |
3158 | { | |
3159 | int start = INTVAL (operands[2]) & 31; | |
3160 | int size = INTVAL (operands[1]) & 31; | |
3161 | ||
89e9f3a8 MM |
3162 | operands[4] = GEN_INT (32 - start - size); |
3163 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3164 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
3165 | }") |
3166 | ||
a78e33fc | 3167 | (define_insn "*insvsi_internal1" |
d56d506a RK |
3168 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3169 | (match_operand:SI 1 "const_int_operand" "i") | |
3170 | (match_operand:SI 2 "const_int_operand" "i")) | |
3171 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3172 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3173 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3174 | "* |
3175 | { | |
3176 | int shift = INTVAL (operands[4]) & 31; | |
3177 | int start = INTVAL (operands[2]) & 31; | |
3178 | int size = INTVAL (operands[1]) & 31; | |
3179 | ||
89e9f3a8 MM |
3180 | operands[4] = GEN_INT (shift - start - size); |
3181 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3182 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3183 | }") |
3184 | ||
a78e33fc | 3185 | (define_insn "*insvsi_internal2" |
d56d506a RK |
3186 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3187 | (match_operand:SI 1 "const_int_operand" "i") | |
3188 | (match_operand:SI 2 "const_int_operand" "i")) | |
3189 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3190 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3191 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3192 | "* |
3193 | { | |
3194 | int shift = INTVAL (operands[4]) & 31; | |
3195 | int start = INTVAL (operands[2]) & 31; | |
3196 | int size = INTVAL (operands[1]) & 31; | |
3197 | ||
89e9f3a8 MM |
3198 | operands[4] = GEN_INT (32 - shift - start - size); |
3199 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3200 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3201 | }") |
3202 | ||
a78e33fc | 3203 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3204 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3205 | (match_operand:SI 1 "const_int_operand" "i") | |
3206 | (match_operand:SI 2 "const_int_operand" "i")) | |
3207 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3208 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3209 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3210 | "* |
3211 | { | |
3212 | int shift = INTVAL (operands[4]) & 31; | |
3213 | int start = INTVAL (operands[2]) & 31; | |
3214 | int size = INTVAL (operands[1]) & 31; | |
3215 | ||
89e9f3a8 MM |
3216 | operands[4] = GEN_INT (32 - shift - start - size); |
3217 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3218 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3219 | }") |
3220 | ||
a78e33fc | 3221 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3222 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3223 | (match_operand:SI 1 "const_int_operand" "i") | |
3224 | (match_operand:SI 2 "const_int_operand" "i")) | |
3225 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3226 | (match_operand:SI 4 "const_int_operand" "i") | |
3227 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3228 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3229 | "* | |
3230 | { | |
3231 | int extract_start = INTVAL (operands[5]) & 31; | |
3232 | int extract_size = INTVAL (operands[4]) & 31; | |
3233 | int insert_start = INTVAL (operands[2]) & 31; | |
3234 | int insert_size = INTVAL (operands[1]) & 31; | |
3235 | ||
3236 | /* Align extract field with insert field */ | |
3a598fbe | 3237 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3238 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3239 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
3240 | }") |
3241 | ||
a78e33fc | 3242 | (define_insn "insvdi" |
685f3906 | 3243 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3244 | (match_operand:SI 1 "const_int_operand" "i") |
3245 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3246 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3247 | "TARGET_POWERPC64" | |
3248 | "* | |
3249 | { | |
3250 | int start = INTVAL (operands[2]) & 63; | |
3251 | int size = INTVAL (operands[1]) & 63; | |
3252 | ||
a78e33fc DE |
3253 | operands[1] = GEN_INT (64 - start - size); |
3254 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3255 | }") |
3256 | ||
034c1be0 | 3257 | (define_expand "extzv" |
0ad91047 DE |
3258 | [(set (match_operand 0 "gpc_reg_operand" "") |
3259 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3260 | (match_operand:SI 2 "const_int_operand" "") | |
3261 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3262 | "" |
3263 | " | |
3264 | { | |
3265 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3266 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3267 | compiler if the address of the structure is taken later. */ | |
3268 | if (GET_CODE (operands[0]) == SUBREG | |
3269 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3270 | FAIL; | |
a78e33fc DE |
3271 | |
3272 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3273 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3274 | else | |
3275 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3276 | DONE; | |
034c1be0 MM |
3277 | }") |
3278 | ||
a78e33fc | 3279 | (define_insn "extzvsi" |
cd2b37d9 RK |
3280 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3281 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3282 | (match_operand:SI 2 "const_int_operand" "i") |
3283 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3284 | "" | |
3285 | "* | |
3286 | { | |
3287 | int start = INTVAL (operands[3]) & 31; | |
3288 | int size = INTVAL (operands[2]) & 31; | |
3289 | ||
3290 | if (start + size >= 32) | |
3291 | operands[3] = const0_rtx; | |
3292 | else | |
89e9f3a8 | 3293 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3294 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3295 | }") |
3296 | ||
a78e33fc | 3297 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3298 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3299 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3300 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3301 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3302 | (const_int 0))) |
9ebbca7d | 3303 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3304 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3305 | "* |
3306 | { | |
3307 | int start = INTVAL (operands[3]) & 31; | |
3308 | int size = INTVAL (operands[2]) & 31; | |
3309 | ||
9ebbca7d GK |
3310 | /* Force split for non-cc0 compare. */ |
3311 | if (which_alternative == 1) | |
3312 | return \"#\"; | |
3313 | ||
a7a975e1 RK |
3314 | /* If the bitfield being tested fits in the upper or lower half of a |
3315 | word, it is possible to use andiu. or andil. to test it. This is | |
3316 | useful because the condition register set-use delay is smaller for | |
3317 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3318 | position is 0 because the LT and GT bits may be set wrong. */ | |
3319 | ||
3320 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3321 | { |
3a598fbe | 3322 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3323 | - (1 << (16 - (start & 15) - size)))); |
3324 | if (start < 16) | |
ca7f5001 | 3325 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3326 | else |
ca7f5001 | 3327 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3328 | } |
7e69e155 | 3329 | |
1fd4e8c1 RK |
3330 | if (start + size >= 32) |
3331 | operands[3] = const0_rtx; | |
3332 | else | |
89e9f3a8 | 3333 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3334 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3335 | }" |
9ebbca7d GK |
3336 | [(set_attr "type" "compare") |
3337 | (set_attr "length" "4,8")]) | |
3338 | ||
3339 | (define_split | |
3340 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3341 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3342 | (match_operand:SI 2 "const_int_operand" "") | |
3343 | (match_operand:SI 3 "const_int_operand" "")) | |
3344 | (const_int 0))) | |
3345 | (clobber (match_scratch:SI 4 ""))] | |
3346 | "! TARGET_POWERPC64 && reload_completed" | |
3347 | [(set (match_dup 4) | |
3348 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3349 | (match_dup 3))) | |
3350 | (set (match_dup 0) | |
3351 | (compare:CC (match_dup 4) | |
3352 | (const_int 0)))] | |
3353 | "") | |
1fd4e8c1 | 3354 | |
a78e33fc | 3355 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3356 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3357 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3358 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3359 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3360 | (const_int 0))) |
9ebbca7d | 3361 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3362 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
0ad91047 | 3363 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3364 | "* |
3365 | { | |
3366 | int start = INTVAL (operands[3]) & 31; | |
3367 | int size = INTVAL (operands[2]) & 31; | |
3368 | ||
9ebbca7d GK |
3369 | /* Force split for non-cc0 compare. */ |
3370 | if (which_alternative == 1) | |
3371 | return \"#\"; | |
3372 | ||
a7a975e1 | 3373 | if (start >= 16 && start + size == 32) |
df031c43 | 3374 | { |
89e9f3a8 | 3375 | operands[3] = GEN_INT ((1 << (32 - start)) - 1); |
ca7f5001 | 3376 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 | 3377 | } |
7e69e155 | 3378 | |
1fd4e8c1 RK |
3379 | if (start + size >= 32) |
3380 | operands[3] = const0_rtx; | |
3381 | else | |
89e9f3a8 | 3382 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3383 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3384 | }" |
9ebbca7d GK |
3385 | [(set_attr "type" "delayed_compare") |
3386 | (set_attr "length" "4,8")]) | |
3387 | ||
3388 | (define_split | |
3389 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3390 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3391 | (match_operand:SI 2 "const_int_operand" "") | |
3392 | (match_operand:SI 3 "const_int_operand" "")) | |
3393 | (const_int 0))) | |
3394 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3395 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
3396 | "! TARGET_POWERPC64 && reload_completed" | |
3397 | [(set (match_dup 0) | |
3398 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3399 | (set (match_dup 4) | |
3400 | (compare:CC (match_dup 0) | |
3401 | (const_int 0)))] | |
3402 | "") | |
1fd4e8c1 | 3403 | |
a78e33fc | 3404 | (define_insn "extzvdi" |
685f3906 DE |
3405 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3406 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3407 | (match_operand:SI 2 "const_int_operand" "i") |
3408 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3409 | "TARGET_POWERPC64" |
3410 | "* | |
3411 | { | |
3412 | int start = INTVAL (operands[3]) & 63; | |
3413 | int size = INTVAL (operands[2]) & 63; | |
3414 | ||
3415 | if (start + size >= 64) | |
3416 | operands[3] = const0_rtx; | |
3417 | else | |
89e9f3a8 MM |
3418 | operands[3] = GEN_INT (start + size); |
3419 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3420 | return \"rldicl %0,%1,%3,%2\"; |
3421 | }") | |
3422 | ||
a78e33fc | 3423 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3424 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3425 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3426 | (match_operand:SI 2 "const_int_operand" "i") |
3427 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3428 | (const_int 0))) |
29ae5b89 | 3429 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
3430 | "TARGET_POWERPC64" |
3431 | "* | |
3432 | { | |
3433 | int start = INTVAL (operands[3]) & 63; | |
3434 | int size = INTVAL (operands[2]) & 63; | |
3435 | ||
3436 | if (start + size >= 64) | |
3437 | operands[3] = const0_rtx; | |
3438 | else | |
89e9f3a8 MM |
3439 | operands[3] = GEN_INT (start + size); |
3440 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3441 | return \"rldicl. %4,%1,%3,%2\"; |
3442 | }") | |
3443 | ||
a78e33fc | 3444 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3445 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3446 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3447 | (match_operand:SI 2 "const_int_operand" "i") |
3448 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3449 | (const_int 0))) |
29ae5b89 | 3450 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
3451 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
3452 | "TARGET_POWERPC64" | |
3453 | "* | |
3454 | { | |
3455 | int start = INTVAL (operands[3]) & 63; | |
3456 | int size = INTVAL (operands[2]) & 63; | |
3457 | ||
3458 | if (start + size >= 64) | |
3459 | operands[3] = const0_rtx; | |
3460 | else | |
89e9f3a8 MM |
3461 | operands[3] = GEN_INT (start + size); |
3462 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3463 | return \"rldicl. %0,%1,%3,%2\"; |
3464 | }") | |
3465 | ||
1fd4e8c1 | 3466 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3467 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3468 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3469 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3470 | "" | |
ca7f5001 | 3471 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3472 | |
a260abc9 | 3473 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3474 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3475 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3476 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3477 | (const_int 0))) |
9ebbca7d | 3478 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3479 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3480 | "@ |
3481 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3482 | #" | |
3483 | [(set_attr "type" "delayed_compare") | |
3484 | (set_attr "length" "4,8")]) | |
3485 | ||
3486 | (define_split | |
3487 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3488 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3489 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3490 | (const_int 0))) | |
3491 | (clobber (match_scratch:SI 3 ""))] | |
3492 | "! TARGET_POWERPC64 && reload_completed" | |
3493 | [(set (match_dup 3) | |
3494 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3495 | (set (match_dup 0) | |
3496 | (compare:CC (match_dup 3) | |
3497 | (const_int 0)))] | |
3498 | "") | |
1fd4e8c1 | 3499 | |
a260abc9 | 3500 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3501 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3502 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3503 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3504 | (const_int 0))) |
9ebbca7d | 3505 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3506 | (rotate:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3507 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3508 | "@ |
3509 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3510 | #" | |
3511 | [(set_attr "type" "delayed_compare") | |
3512 | (set_attr "length" "4,8")]) | |
3513 | ||
3514 | (define_split | |
3515 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3516 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3517 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3518 | (const_int 0))) | |
3519 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3520 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
3521 | "! TARGET_POWERPC64 && reload_completed" | |
3522 | [(set (match_dup 0) | |
3523 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3524 | (set (match_dup 3) | |
3525 | (compare:CC (match_dup 0) | |
3526 | (const_int 0)))] | |
3527 | "") | |
1fd4e8c1 | 3528 | |
a260abc9 | 3529 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3530 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3531 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3532 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
9615f239 | 3533 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3534 | "" |
ca7f5001 | 3535 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3536 | |
a260abc9 | 3537 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3538 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3539 | (compare:CC (and:SI |
9ebbca7d GK |
3540 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3541 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3542 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3543 | (const_int 0))) |
9ebbca7d | 3544 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3545 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3546 | "@ |
3547 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3548 | #" | |
3549 | [(set_attr "type" "delayed_compare") | |
3550 | (set_attr "length" "4,8")]) | |
3551 | ||
3552 | (define_split | |
3553 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3554 | (compare:CC (and:SI | |
3555 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3556 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3557 | (match_operand:SI 3 "mask_operand" "")) | |
3558 | (const_int 0))) | |
3559 | (clobber (match_scratch:SI 4 ""))] | |
3560 | "! TARGET_POWERPC64 && reload_completed" | |
3561 | [(set (match_dup 4) | |
3562 | (and:SI (rotate:SI (match_dup 1) | |
3563 | (match_dup 2)) | |
3564 | (match_dup 3))) | |
3565 | (set (match_dup 0) | |
3566 | (compare:CC (match_dup 4) | |
3567 | (const_int 0)))] | |
3568 | "") | |
1fd4e8c1 | 3569 | |
a260abc9 | 3570 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3571 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3572 | (compare:CC (and:SI |
9ebbca7d GK |
3573 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3574 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3575 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3576 | (const_int 0))) |
9ebbca7d | 3577 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3578 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3579 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3580 | "@ |
3581 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3582 | #" | |
3583 | [(set_attr "type" "delayed_compare") | |
3584 | (set_attr "length" "4,8")]) | |
3585 | ||
3586 | (define_split | |
3587 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3588 | (compare:CC (and:SI | |
3589 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3590 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3591 | (match_operand:SI 3 "mask_operand" "")) | |
3592 | (const_int 0))) | |
3593 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3594 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
3595 | "! TARGET_POWERPC64 && reload_completed" | |
3596 | [(set (match_dup 0) | |
3597 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3598 | (set (match_dup 4) | |
3599 | (compare:CC (match_dup 0) | |
3600 | (const_int 0)))] | |
3601 | "") | |
1fd4e8c1 | 3602 | |
a260abc9 | 3603 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3604 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3605 | (zero_extend:SI |
3606 | (subreg:QI | |
cd2b37d9 | 3607 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3608 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3609 | "" | |
ca7f5001 | 3610 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3611 | |
a260abc9 | 3612 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3613 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3614 | (compare:CC (zero_extend:SI |
3615 | (subreg:QI | |
9ebbca7d GK |
3616 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3617 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3618 | (const_int 0))) |
9ebbca7d | 3619 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3620 | "" |
9ebbca7d GK |
3621 | "@ |
3622 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3623 | #" | |
3624 | [(set_attr "type" "delayed_compare") | |
3625 | (set_attr "length" "4,8")]) | |
3626 | ||
3627 | (define_split | |
3628 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3629 | (compare:CC (zero_extend:SI | |
3630 | (subreg:QI | |
3631 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3632 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3633 | (const_int 0))) | |
3634 | (clobber (match_scratch:SI 3 ""))] | |
3635 | "reload_completed" | |
3636 | [(set (match_dup 3) | |
3637 | (zero_extend:SI (subreg:QI | |
3638 | (rotate:SI (match_dup 1) | |
3639 | (match_dup 2)) 0))) | |
3640 | (set (match_dup 0) | |
3641 | (compare:CC (match_dup 3) | |
3642 | (const_int 0)))] | |
3643 | "") | |
1fd4e8c1 | 3644 | |
a260abc9 | 3645 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3646 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3647 | (compare:CC (zero_extend:SI |
3648 | (subreg:QI | |
9ebbca7d GK |
3649 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3650 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3651 | (const_int 0))) |
9ebbca7d | 3652 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3653 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3654 | "" | |
9ebbca7d GK |
3655 | "@ |
3656 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3657 | #" | |
3658 | [(set_attr "type" "delayed_compare") | |
3659 | (set_attr "length" "4,8")]) | |
3660 | ||
3661 | (define_split | |
3662 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3663 | (compare:CC (zero_extend:SI | |
3664 | (subreg:QI | |
3665 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3666 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3667 | (const_int 0))) | |
3668 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3669 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3670 | "reload_completed" | |
3671 | [(set (match_dup 0) | |
3672 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3673 | (set (match_dup 3) | |
3674 | (compare:CC (match_dup 0) | |
3675 | (const_int 0)))] | |
3676 | "") | |
1fd4e8c1 | 3677 | |
a260abc9 | 3678 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3679 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3680 | (zero_extend:SI |
3681 | (subreg:HI | |
cd2b37d9 | 3682 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3683 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3684 | "" | |
ca7f5001 | 3685 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3686 | |
a260abc9 | 3687 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3688 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3689 | (compare:CC (zero_extend:SI |
3690 | (subreg:HI | |
9ebbca7d GK |
3691 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3692 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3693 | (const_int 0))) |
9ebbca7d | 3694 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3695 | "" |
9ebbca7d GK |
3696 | "@ |
3697 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3698 | #" | |
3699 | [(set_attr "type" "delayed_compare") | |
3700 | (set_attr "length" "4,8")]) | |
3701 | ||
3702 | (define_split | |
3703 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3704 | (compare:CC (zero_extend:SI | |
3705 | (subreg:HI | |
3706 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3707 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3708 | (const_int 0))) | |
3709 | (clobber (match_scratch:SI 3 ""))] | |
3710 | "reload_completed" | |
3711 | [(set (match_dup 3) | |
3712 | (zero_extend:SI (subreg:HI | |
3713 | (rotate:SI (match_dup 1) | |
3714 | (match_dup 2)) 0))) | |
3715 | (set (match_dup 0) | |
3716 | (compare:CC (match_dup 3) | |
3717 | (const_int 0)))] | |
3718 | "") | |
1fd4e8c1 | 3719 | |
a260abc9 | 3720 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3721 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3722 | (compare:CC (zero_extend:SI |
3723 | (subreg:HI | |
9ebbca7d GK |
3724 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3725 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3726 | (const_int 0))) |
9ebbca7d | 3727 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3728 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3729 | "" | |
9ebbca7d GK |
3730 | "@ |
3731 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3732 | #" | |
3733 | [(set_attr "type" "delayed_compare") | |
3734 | (set_attr "length" "4,8")]) | |
3735 | ||
3736 | (define_split | |
3737 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3738 | (compare:CC (zero_extend:SI | |
3739 | (subreg:HI | |
3740 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3741 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3742 | (const_int 0))) | |
3743 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3744 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3745 | "reload_completed" | |
3746 | [(set (match_dup 0) | |
3747 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3748 | (set (match_dup 3) | |
3749 | (compare:CC (match_dup 0) | |
3750 | (const_int 0)))] | |
3751 | "") | |
1fd4e8c1 RK |
3752 | |
3753 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3754 | ;; SHIFT_COUNT_TRUNCATED. | |
3755 | ||
ca7f5001 RK |
3756 | (define_expand "ashlsi3" |
3757 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3758 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3759 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3760 | "" | |
3761 | " | |
3762 | { | |
3763 | if (TARGET_POWER) | |
3764 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3765 | else | |
25c341fa | 3766 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3767 | DONE; |
3768 | }") | |
3769 | ||
3770 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3771 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3772 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3773 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3774 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3775 | "TARGET_POWER" |
1fd4e8c1 RK |
3776 | "@ |
3777 | sle %0,%1,%2 | |
9ebbca7d | 3778 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3779 | |
25c341fa | 3780 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3781 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3782 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3783 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3784 | "! TARGET_POWER" |
9ebbca7d | 3785 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3786 | |
3787 | (define_insn "" | |
9ebbca7d GK |
3788 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3789 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3790 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3791 | (const_int 0))) |
9ebbca7d GK |
3792 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3793 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3794 | "TARGET_POWER" |
1fd4e8c1 RK |
3795 | "@ |
3796 | sle. %3,%1,%2 | |
9ebbca7d GK |
3797 | {sli.|slwi.} %3,%1,%h2 |
3798 | # | |
3799 | #" | |
3800 | [(set_attr "type" "delayed_compare") | |
3801 | (set_attr "length" "4,4,8,8")]) | |
3802 | ||
3803 | (define_split | |
3804 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3805 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3806 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3807 | (const_int 0))) | |
3808 | (clobber (match_scratch:SI 3 "")) | |
3809 | (clobber (match_scratch:SI 4 ""))] | |
3810 | "TARGET_POWER && reload_completed" | |
3811 | [(parallel [(set (match_dup 3) | |
3812 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3813 | (clobber (match_dup 4))]) | |
3814 | (set (match_dup 0) | |
3815 | (compare:CC (match_dup 3) | |
3816 | (const_int 0)))] | |
3817 | "") | |
25c341fa | 3818 | |
ca7f5001 | 3819 | (define_insn "" |
9ebbca7d GK |
3820 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3821 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3822 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3823 | (const_int 0))) |
9ebbca7d | 3824 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3825 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3826 | "@ |
3827 | {sl|slw}%I2. %3,%1,%h2 | |
3828 | #" | |
3829 | [(set_attr "type" "delayed_compare") | |
3830 | (set_attr "length" "4,8")]) | |
3831 | ||
3832 | (define_split | |
3833 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3834 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3835 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3836 | (const_int 0))) | |
3837 | (clobber (match_scratch:SI 3 ""))] | |
3838 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3839 | [(set (match_dup 3) | |
3840 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3841 | (set (match_dup 0) | |
3842 | (compare:CC (match_dup 3) | |
3843 | (const_int 0)))] | |
3844 | "") | |
1fd4e8c1 RK |
3845 | |
3846 | (define_insn "" | |
9ebbca7d GK |
3847 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3848 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3849 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3850 | (const_int 0))) |
9ebbca7d | 3851 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3852 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3853 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3854 | "TARGET_POWER" |
1fd4e8c1 RK |
3855 | "@ |
3856 | sle. %0,%1,%2 | |
9ebbca7d GK |
3857 | {sli.|slwi.} %0,%1,%h2 |
3858 | # | |
3859 | #" | |
3860 | [(set_attr "type" "delayed_compare") | |
3861 | (set_attr "length" "4,4,8,8")]) | |
3862 | ||
3863 | (define_split | |
3864 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3865 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3866 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3867 | (const_int 0))) | |
3868 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3869 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3870 | (clobber (match_scratch:SI 4 ""))] | |
3871 | "TARGET_POWER && reload_completed" | |
3872 | [(parallel [(set (match_dup 0) | |
3873 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3874 | (clobber (match_dup 4))]) | |
3875 | (set (match_dup 3) | |
3876 | (compare:CC (match_dup 0) | |
3877 | (const_int 0)))] | |
3878 | "") | |
25c341fa | 3879 | |
ca7f5001 | 3880 | (define_insn "" |
9ebbca7d GK |
3881 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3882 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3883 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3884 | (const_int 0))) |
9ebbca7d | 3885 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3886 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3887 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3888 | "@ |
3889 | {sl|slw}%I2. %0,%1,%h2 | |
3890 | #" | |
3891 | [(set_attr "type" "delayed_compare") | |
3892 | (set_attr "length" "4,8")]) | |
3893 | ||
3894 | (define_split | |
3895 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3896 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3897 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3898 | (const_int 0))) | |
3899 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3900 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
3901 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3902 | [(set (match_dup 0) | |
3903 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3904 | (set (match_dup 3) | |
3905 | (compare:CC (match_dup 0) | |
3906 | (const_int 0)))] | |
3907 | "") | |
1fd4e8c1 RK |
3908 | |
3909 | (define_insn "" | |
cd2b37d9 RK |
3910 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3911 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3912 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 3913 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3914 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3915 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3916 | |
3917 | (define_insn "" | |
9ebbca7d | 3918 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3919 | (compare:CC |
9ebbca7d GK |
3920 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3921 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
3922 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3923 | (const_int 0))) |
9ebbca7d | 3924 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3925 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3926 | "@ |
3927 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3928 | #" | |
3929 | [(set_attr "type" "delayed_compare") | |
3930 | (set_attr "length" "4,8")]) | |
3931 | ||
3932 | (define_split | |
3933 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3934 | (compare:CC | |
3935 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3936 | (match_operand:SI 2 "const_int_operand" "")) | |
3937 | (match_operand:SI 3 "mask_operand" "")) | |
3938 | (const_int 0))) | |
3939 | (clobber (match_scratch:SI 4 ""))] | |
3940 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
3941 | [(set (match_dup 4) | |
3942 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3943 | (match_dup 3))) | |
3944 | (set (match_dup 0) | |
3945 | (compare:CC (match_dup 4) | |
3946 | (const_int 0)))] | |
3947 | "") | |
1fd4e8c1 RK |
3948 | |
3949 | (define_insn "" | |
9ebbca7d | 3950 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3951 | (compare:CC |
9ebbca7d GK |
3952 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3953 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
3954 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3955 | (const_int 0))) |
9ebbca7d | 3956 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3957 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3958 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3959 | "@ |
3960 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3961 | #" | |
3962 | [(set_attr "type" "delayed_compare") | |
3963 | (set_attr "length" "4,8")]) | |
3964 | ||
3965 | (define_split | |
3966 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3967 | (compare:CC | |
3968 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3969 | (match_operand:SI 2 "const_int_operand" "")) | |
3970 | (match_operand:SI 3 "mask_operand" "")) | |
3971 | (const_int 0))) | |
3972 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3973 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
3974 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
3975 | [(set (match_dup 0) | |
3976 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3977 | (set (match_dup 4) | |
3978 | (compare:CC (match_dup 0) | |
3979 | (const_int 0)))] | |
3980 | "") | |
1fd4e8c1 | 3981 | |
ca7f5001 | 3982 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3983 | ;; "sli x,x,0". |
ca7f5001 RK |
3984 | (define_expand "lshrsi3" |
3985 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3986 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3987 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3988 | "" | |
3989 | " | |
3990 | { | |
3991 | if (TARGET_POWER) | |
3992 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3993 | else | |
25c341fa | 3994 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3995 | DONE; |
3996 | }") | |
3997 | ||
3998 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3999 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
4000 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
4001 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
4002 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 4003 | "TARGET_POWER" |
1fd4e8c1 RK |
4004 | "@ |
4005 | sre %0,%1,%2 | |
bdf423cb | 4006 | mr %0,%1 |
ca7f5001 RK |
4007 | {s%A2i|s%A2wi} %0,%1,%h2") |
4008 | ||
25c341fa | 4009 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
4010 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4011 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4012 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 4013 | "! TARGET_POWER" |
bdf423cb MM |
4014 | "@ |
4015 | mr %0,%1 | |
4016 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
4017 | |
4018 | (define_insn "" | |
9ebbca7d GK |
4019 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
4020 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4021 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4022 | (const_int 0))) |
9ebbca7d GK |
4023 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
4024 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 4025 | "TARGET_POWER" |
1fd4e8c1 | 4026 | "@ |
29ae5b89 JL |
4027 | sre. %3,%1,%2 |
4028 | mr. %1,%1 | |
9ebbca7d GK |
4029 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
4030 | # | |
4031 | # | |
4032 | #" | |
4033 | [(set_attr "type" "delayed_compare") | |
4034 | (set_attr "length" "4,4,4,8,8,8")]) | |
4035 | ||
4036 | (define_split | |
4037 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4038 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4039 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4040 | (const_int 0))) | |
4041 | (clobber (match_scratch:SI 3 "")) | |
4042 | (clobber (match_scratch:SI 4 ""))] | |
4043 | "TARGET_POWER && reload_completed" | |
4044 | [(parallel [(set (match_dup 3) | |
4045 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4046 | (clobber (match_dup 4))]) | |
4047 | (set (match_dup 0) | |
4048 | (compare:CC (match_dup 3) | |
4049 | (const_int 0)))] | |
4050 | "") | |
ca7f5001 RK |
4051 | |
4052 | (define_insn "" | |
9ebbca7d GK |
4053 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4054 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4055 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 4056 | (const_int 0))) |
9ebbca7d | 4057 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
0ad91047 | 4058 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
4059 | "@ |
4060 | mr. %1,%1 | |
9ebbca7d GK |
4061 | {sr|srw}%I2. %3,%1,%h2 |
4062 | # | |
4063 | #" | |
4064 | [(set_attr "type" "delayed_compare") | |
4065 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 4066 | |
9ebbca7d GK |
4067 | (define_split |
4068 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4069 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4070 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4071 | (const_int 0))) | |
4072 | (clobber (match_scratch:SI 3 ""))] | |
4073 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4074 | [(set (match_dup 3) | |
4075 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4076 | (set (match_dup 0) | |
4077 | (compare:CC (match_dup 3) | |
4078 | (const_int 0)))] | |
4079 | "") | |
4080 | ||
4081 | (define_insn "" | |
4082 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
4083 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4084 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4085 | (const_int 0))) |
9ebbca7d | 4086 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 4087 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4088 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 4089 | "TARGET_POWER" |
1fd4e8c1 | 4090 | "@ |
29ae5b89 JL |
4091 | sre. %0,%1,%2 |
4092 | mr. %0,%1 | |
9ebbca7d GK |
4093 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
4094 | # | |
4095 | # | |
4096 | #" | |
4097 | [(set_attr "type" "delayed_compare") | |
4098 | (set_attr "length" "4,4,4,8,8,8")]) | |
4099 | ||
4100 | (define_split | |
4101 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4102 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4103 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4104 | (const_int 0))) | |
4105 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4106 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4107 | (clobber (match_scratch:SI 4 ""))] | |
4108 | "TARGET_POWER && reload_completed" | |
4109 | [(parallel [(set (match_dup 0) | |
4110 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4111 | (clobber (match_dup 4))]) | |
4112 | (set (match_dup 3) | |
4113 | (compare:CC (match_dup 0) | |
4114 | (const_int 0)))] | |
4115 | "") | |
ca7f5001 RK |
4116 | |
4117 | (define_insn "" | |
9ebbca7d GK |
4118 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4119 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4120 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4121 | (const_int 0))) |
9ebbca7d | 4122 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4123 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4124 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
4125 | "@ |
4126 | mr. %0,%1 | |
9ebbca7d GK |
4127 | {sr|srw}%I2. %0,%1,%h2 |
4128 | # | |
4129 | #" | |
4130 | [(set_attr "type" "delayed_compare") | |
4131 | (set_attr "length" "4,4,8,8")]) | |
4132 | ||
4133 | (define_split | |
4134 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4135 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4136 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4137 | (const_int 0))) | |
4138 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4139 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4140 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4141 | [(set (match_dup 0) | |
4142 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4143 | (set (match_dup 3) | |
4144 | (compare:CC (match_dup 0) | |
4145 | (const_int 0)))] | |
4146 | "") | |
1fd4e8c1 RK |
4147 | |
4148 | (define_insn "" | |
cd2b37d9 RK |
4149 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4150 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4151 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 4152 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 4153 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4154 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4155 | |
4156 | (define_insn "" | |
9ebbca7d | 4157 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4158 | (compare:CC |
9ebbca7d GK |
4159 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4160 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4161 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4162 | (const_int 0))) |
9ebbca7d | 4163 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4164 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4165 | "@ |
4166 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4167 | #" | |
4168 | [(set_attr "type" "delayed_compare") | |
4169 | (set_attr "length" "4,8")]) | |
4170 | ||
4171 | (define_split | |
4172 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4173 | (compare:CC | |
4174 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4175 | (match_operand:SI 2 "const_int_operand" "")) | |
4176 | (match_operand:SI 3 "mask_operand" "")) | |
4177 | (const_int 0))) | |
4178 | (clobber (match_scratch:SI 4 ""))] | |
4179 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4180 | [(set (match_dup 4) | |
4181 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4182 | (match_dup 3))) | |
4183 | (set (match_dup 0) | |
4184 | (compare:CC (match_dup 4) | |
4185 | (const_int 0)))] | |
4186 | "") | |
1fd4e8c1 RK |
4187 | |
4188 | (define_insn "" | |
9ebbca7d | 4189 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4190 | (compare:CC |
9ebbca7d GK |
4191 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4192 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4193 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4194 | (const_int 0))) |
9ebbca7d | 4195 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4196 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4197 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4198 | "@ |
4199 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4200 | #" | |
4201 | [(set_attr "type" "delayed_compare") | |
4202 | (set_attr "length" "4,8")]) | |
4203 | ||
4204 | (define_split | |
4205 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4206 | (compare:CC | |
4207 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4208 | (match_operand:SI 2 "const_int_operand" "")) | |
4209 | (match_operand:SI 3 "mask_operand" "")) | |
4210 | (const_int 0))) | |
4211 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4212 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4213 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4214 | [(set (match_dup 0) | |
4215 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4216 | (set (match_dup 4) | |
4217 | (compare:CC (match_dup 0) | |
4218 | (const_int 0)))] | |
4219 | "") | |
1fd4e8c1 RK |
4220 | |
4221 | (define_insn "" | |
cd2b37d9 | 4222 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4223 | (zero_extend:SI |
4224 | (subreg:QI | |
cd2b37d9 | 4225 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4226 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4227 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4228 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4229 | |
4230 | (define_insn "" | |
9ebbca7d | 4231 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4232 | (compare:CC |
4233 | (zero_extend:SI | |
4234 | (subreg:QI | |
9ebbca7d GK |
4235 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4236 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4237 | (const_int 0))) |
9ebbca7d | 4238 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4239 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4240 | "@ |
4241 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4242 | #" | |
4243 | [(set_attr "type" "delayed_compare") | |
4244 | (set_attr "length" "4,8")]) | |
4245 | ||
4246 | (define_split | |
4247 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4248 | (compare:CC | |
4249 | (zero_extend:SI | |
4250 | (subreg:QI | |
4251 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4252 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4253 | (const_int 0))) | |
4254 | (clobber (match_scratch:SI 3 ""))] | |
4255 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4256 | [(set (match_dup 3) | |
4257 | (zero_extend:SI (subreg:QI | |
4258 | (lshiftrt:SI (match_dup 1) | |
4259 | (match_dup 2)) 0))) | |
4260 | (set (match_dup 0) | |
4261 | (compare:CC (match_dup 3) | |
4262 | (const_int 0)))] | |
4263 | "") | |
1fd4e8c1 RK |
4264 | |
4265 | (define_insn "" | |
9ebbca7d | 4266 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4267 | (compare:CC |
4268 | (zero_extend:SI | |
4269 | (subreg:QI | |
9ebbca7d GK |
4270 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4271 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4272 | (const_int 0))) |
9ebbca7d | 4273 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4274 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4275 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4276 | "@ |
4277 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4278 | #" | |
4279 | [(set_attr "type" "delayed_compare") | |
4280 | (set_attr "length" "4,8")]) | |
4281 | ||
4282 | (define_split | |
4283 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4284 | (compare:CC | |
4285 | (zero_extend:SI | |
4286 | (subreg:QI | |
4287 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4288 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4289 | (const_int 0))) | |
4290 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4291 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4292 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4293 | [(set (match_dup 0) | |
4294 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4295 | (set (match_dup 3) | |
4296 | (compare:CC (match_dup 0) | |
4297 | (const_int 0)))] | |
4298 | "") | |
1fd4e8c1 RK |
4299 | |
4300 | (define_insn "" | |
cd2b37d9 | 4301 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4302 | (zero_extend:SI |
4303 | (subreg:HI | |
cd2b37d9 | 4304 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4305 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4306 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4307 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4308 | |
4309 | (define_insn "" | |
9ebbca7d | 4310 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4311 | (compare:CC |
4312 | (zero_extend:SI | |
4313 | (subreg:HI | |
9ebbca7d GK |
4314 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4315 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4316 | (const_int 0))) |
9ebbca7d | 4317 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4318 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4319 | "@ |
4320 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4321 | #" | |
4322 | [(set_attr "type" "delayed_compare") | |
4323 | (set_attr "length" "4,8")]) | |
4324 | ||
4325 | (define_split | |
4326 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4327 | (compare:CC | |
4328 | (zero_extend:SI | |
4329 | (subreg:HI | |
4330 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4331 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4332 | (const_int 0))) | |
4333 | (clobber (match_scratch:SI 3 ""))] | |
4334 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4335 | [(set (match_dup 3) | |
4336 | (zero_extend:SI (subreg:HI | |
4337 | (lshiftrt:SI (match_dup 1) | |
4338 | (match_dup 2)) 0))) | |
4339 | (set (match_dup 0) | |
4340 | (compare:CC (match_dup 3) | |
4341 | (const_int 0)))] | |
4342 | "") | |
1fd4e8c1 RK |
4343 | |
4344 | (define_insn "" | |
9ebbca7d | 4345 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4346 | (compare:CC |
4347 | (zero_extend:SI | |
4348 | (subreg:HI | |
9ebbca7d GK |
4349 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4350 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4351 | (const_int 0))) |
9ebbca7d | 4352 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4353 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4354 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4355 | "@ |
4356 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4357 | #" | |
4358 | [(set_attr "type" "delayed_compare") | |
4359 | (set_attr "length" "4,8")]) | |
4360 | ||
4361 | (define_split | |
4362 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4363 | (compare:CC | |
4364 | (zero_extend:SI | |
4365 | (subreg:HI | |
4366 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4367 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4368 | (const_int 0))) | |
4369 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4370 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4371 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4372 | [(set (match_dup 0) | |
4373 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4374 | (set (match_dup 3) | |
4375 | (compare:CC (match_dup 0) | |
4376 | (const_int 0)))] | |
4377 | "") | |
1fd4e8c1 RK |
4378 | |
4379 | (define_insn "" | |
cd2b37d9 | 4380 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4381 | (const_int 1) |
cd2b37d9 RK |
4382 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4383 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4384 | (const_int 31)))] |
ca7f5001 | 4385 | "TARGET_POWER" |
1fd4e8c1 RK |
4386 | "rrib %0,%1,%2") |
4387 | ||
4388 | (define_insn "" | |
cd2b37d9 | 4389 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4390 | (const_int 1) |
cd2b37d9 RK |
4391 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4392 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4393 | (const_int 31)))] |
ca7f5001 | 4394 | "TARGET_POWER" |
1fd4e8c1 RK |
4395 | "rrib %0,%1,%2") |
4396 | ||
4397 | (define_insn "" | |
cd2b37d9 | 4398 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4399 | (const_int 1) |
cd2b37d9 RK |
4400 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4401 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4402 | (const_int 1) |
4403 | (const_int 0)))] | |
ca7f5001 | 4404 | "TARGET_POWER" |
1fd4e8c1 RK |
4405 | "rrib %0,%1,%2") |
4406 | ||
ca7f5001 RK |
4407 | (define_expand "ashrsi3" |
4408 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4409 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4410 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4411 | "" | |
4412 | " | |
4413 | { | |
4414 | if (TARGET_POWER) | |
4415 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4416 | else | |
25c341fa | 4417 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4418 | DONE; |
4419 | }") | |
4420 | ||
4421 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4422 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4423 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4424 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4425 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4426 | "TARGET_POWER" |
1fd4e8c1 RK |
4427 | "@ |
4428 | srea %0,%1,%2 | |
ca7f5001 RK |
4429 | {srai|srawi} %0,%1,%h2") |
4430 | ||
25c341fa | 4431 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4432 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4433 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4434 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4435 | "! TARGET_POWER" |
d904e9ed | 4436 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4437 | |
4438 | (define_insn "" | |
9ebbca7d GK |
4439 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4440 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4441 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4442 | (const_int 0))) |
9ebbca7d GK |
4443 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4444 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4445 | "TARGET_POWER" |
1fd4e8c1 RK |
4446 | "@ |
4447 | srea. %3,%1,%2 | |
9ebbca7d GK |
4448 | {srai.|srawi.} %3,%1,%h2 |
4449 | # | |
4450 | #" | |
4451 | [(set_attr "type" "delayed_compare") | |
4452 | (set_attr "length" "4,4,8,8")]) | |
4453 | ||
4454 | (define_split | |
4455 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4456 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4457 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4458 | (const_int 0))) | |
4459 | (clobber (match_scratch:SI 3 "")) | |
4460 | (clobber (match_scratch:SI 4 ""))] | |
4461 | "TARGET_POWER && reload_completed" | |
4462 | [(parallel [(set (match_dup 3) | |
4463 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4464 | (clobber (match_dup 4))]) | |
4465 | (set (match_dup 0) | |
4466 | (compare:CC (match_dup 3) | |
4467 | (const_int 0)))] | |
4468 | "") | |
ca7f5001 RK |
4469 | |
4470 | (define_insn "" | |
9ebbca7d GK |
4471 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4472 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4473 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4474 | (const_int 0))) |
9ebbca7d | 4475 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4476 | "! TARGET_POWER" |
9ebbca7d GK |
4477 | "@ |
4478 | {sra|sraw}%I2. %3,%1,%h2 | |
4479 | #" | |
4480 | [(set_attr "type" "delayed_compare") | |
4481 | (set_attr "length" "4,8")]) | |
4482 | ||
4483 | (define_split | |
4484 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4485 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4486 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4487 | (const_int 0))) | |
4488 | (clobber (match_scratch:SI 3 ""))] | |
4489 | "! TARGET_POWER && reload_completed" | |
4490 | [(set (match_dup 3) | |
4491 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4492 | (set (match_dup 0) | |
4493 | (compare:CC (match_dup 3) | |
4494 | (const_int 0)))] | |
4495 | "") | |
1fd4e8c1 RK |
4496 | |
4497 | (define_insn "" | |
9ebbca7d GK |
4498 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4499 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4500 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4501 | (const_int 0))) |
9ebbca7d | 4502 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4503 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4504 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4505 | "TARGET_POWER" |
1fd4e8c1 RK |
4506 | "@ |
4507 | srea. %0,%1,%2 | |
9ebbca7d GK |
4508 | {srai.|srawi.} %0,%1,%h2 |
4509 | # | |
4510 | #" | |
4511 | [(set_attr "type" "delayed_compare") | |
4512 | (set_attr "length" "4,4,8,8")]) | |
4513 | ||
4514 | (define_split | |
4515 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4516 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4517 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4518 | (const_int 0))) | |
4519 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4520 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4521 | (clobber (match_scratch:SI 4 ""))] | |
4522 | "TARGET_POWER && reload_completed" | |
4523 | [(parallel [(set (match_dup 0) | |
4524 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4525 | (clobber (match_dup 4))]) | |
4526 | (set (match_dup 3) | |
4527 | (compare:CC (match_dup 0) | |
4528 | (const_int 0)))] | |
4529 | "") | |
1fd4e8c1 | 4530 | |
ca7f5001 | 4531 | (define_insn "" |
9ebbca7d GK |
4532 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4533 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4534 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4535 | (const_int 0))) |
9ebbca7d | 4536 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4537 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4538 | "! TARGET_POWER" |
9ebbca7d GK |
4539 | "@ |
4540 | {sra|sraw}%I2. %0,%1,%h2 | |
4541 | #" | |
4542 | [(set_attr "type" "delayed_compare") | |
4543 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4544 | \f |
9ebbca7d GK |
4545 | (define_split |
4546 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4547 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4548 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4549 | (const_int 0))) | |
4550 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4551 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4552 | "! TARGET_POWER && reload_completed" | |
4553 | [(set (match_dup 0) | |
4554 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4555 | (set (match_dup 3) | |
4556 | (compare:CC (match_dup 0) | |
4557 | (const_int 0)))] | |
4558 | "") | |
4559 | ||
1fd4e8c1 RK |
4560 | ;; Floating-point insns, excluding normal data motion. |
4561 | ;; | |
ca7f5001 RK |
4562 | ;; PowerPC has a full set of single-precision floating point instructions. |
4563 | ;; | |
4564 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4565 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4566 | ;; The only conversions we will do will be when storing to memory. In that | |
4567 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4568 | ;; |
4569 | ;; Note that when we store into a single-precision memory location, we need to | |
4570 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4571 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4572 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4573 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4574 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4575 | ||
e8112008 | 4576 | (define_insn "extendsfdf2" |
cd2b37d9 | 4577 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 4578 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 4579 | "TARGET_HARD_FLOAT" |
e8112008 | 4580 | "* |
5c30aff8 | 4581 | { |
e8112008 RK |
4582 | if (REGNO (operands[0]) == REGNO (operands[1])) |
4583 | return \"\"; | |
4584 | else | |
4585 | return \"fmr %0,%1\"; | |
4586 | }" | |
4587 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4588 | |
4589 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
4590 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4591 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4592 | "TARGET_HARD_FLOAT" |
dcac138d | 4593 | "frsp %0,%1" |
1fd4e8c1 RK |
4594 | [(set_attr "type" "fp")]) |
4595 | ||
455350f4 RK |
4596 | (define_insn "aux_truncdfsf2" |
4597 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4598 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
4599 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" | |
4600 | "frsp %0,%1" | |
4601 | [(set_attr "type" "fp")]) | |
4602 | ||
1fd4e8c1 | 4603 | (define_insn "negsf2" |
cd2b37d9 RK |
4604 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4605 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4606 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4607 | "fneg %0,%1" |
4608 | [(set_attr "type" "fp")]) | |
4609 | ||
4610 | (define_insn "abssf2" | |
cd2b37d9 RK |
4611 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4612 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4613 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4614 | "fabs %0,%1" |
4615 | [(set_attr "type" "fp")]) | |
4616 | ||
4617 | (define_insn "" | |
cd2b37d9 RK |
4618 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4619 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4620 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4621 | "fnabs %0,%1" |
4622 | [(set_attr "type" "fp")]) | |
4623 | ||
ca7f5001 RK |
4624 | (define_expand "addsf3" |
4625 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4626 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4627 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4628 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4629 | "") |
4630 | ||
4631 | (define_insn "" | |
cd2b37d9 RK |
4632 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4633 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4634 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4635 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4636 | "fadds %0,%1,%2" |
ca7f5001 RK |
4637 | [(set_attr "type" "fp")]) |
4638 | ||
4639 | (define_insn "" | |
4640 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4641 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4642 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4643 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4644 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4645 | [(set_attr "type" "fp")]) |
4646 | ||
4647 | (define_expand "subsf3" | |
4648 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4649 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4650 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4651 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4652 | "") |
4653 | ||
4654 | (define_insn "" | |
4655 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4656 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4657 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4658 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4659 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4660 | [(set_attr "type" "fp")]) |
4661 | ||
ca7f5001 | 4662 | (define_insn "" |
cd2b37d9 RK |
4663 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4664 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4665 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4666 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4667 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4668 | [(set_attr "type" "fp")]) |
4669 | ||
4670 | (define_expand "mulsf3" | |
4671 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4672 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4673 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4674 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4675 | "") |
4676 | ||
4677 | (define_insn "" | |
4678 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4679 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4680 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4681 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4682 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4683 | [(set_attr "type" "fp")]) |
4684 | ||
ca7f5001 | 4685 | (define_insn "" |
cd2b37d9 RK |
4686 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4687 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4688 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4689 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4690 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4691 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4692 | |
ca7f5001 RK |
4693 | (define_expand "divsf3" |
4694 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4695 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4696 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4697 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4698 | "") |
4699 | ||
4700 | (define_insn "" | |
cd2b37d9 RK |
4701 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4702 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4703 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4704 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4705 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4706 | [(set_attr "type" "sdiv")]) |
4707 | ||
4708 | (define_insn "" | |
4709 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4710 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4711 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4712 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4713 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4714 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4715 | |
4716 | (define_insn "" | |
cd2b37d9 RK |
4717 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4718 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4719 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4720 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4721 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4722 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4723 | [(set_attr "type" "fp")]) |
4724 | ||
4725 | (define_insn "" | |
4726 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4727 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4728 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4729 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4730 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4731 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4732 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4733 | |
4734 | (define_insn "" | |
cd2b37d9 RK |
4735 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4736 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4737 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4738 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4739 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4740 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4741 | [(set_attr "type" "fp")]) |
4742 | ||
4743 | (define_insn "" | |
4744 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4745 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4746 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4747 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4748 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4749 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4750 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4751 | |
4752 | (define_insn "" | |
cd2b37d9 RK |
4753 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4754 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4755 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4756 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4757 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4758 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4759 | [(set_attr "type" "fp")]) |
4760 | ||
4761 | (define_insn "" | |
4762 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4763 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4764 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4765 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4766 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4767 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4768 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4769 | |
4770 | (define_insn "" | |
cd2b37d9 RK |
4771 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4772 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4773 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4774 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4775 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4776 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4777 | [(set_attr "type" "fp")]) |
4778 | ||
4779 | (define_insn "" | |
4780 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4781 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4782 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4783 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4784 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4785 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4786 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4787 | |
ca7f5001 RK |
4788 | (define_expand "sqrtsf2" |
4789 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4790 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 4791 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4792 | "") |
4793 | ||
4794 | (define_insn "" | |
4795 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4796 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4797 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4798 | "fsqrts %0,%1" |
4799 | [(set_attr "type" "ssqrt")]) | |
4800 | ||
4801 | (define_insn "" | |
4802 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4803 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4804 | "TARGET_POWER2 && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4805 | "fsqrt %0,%1" |
4806 | [(set_attr "type" "dsqrt")]) | |
4807 | ||
94d7001a RK |
4808 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4809 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4810 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4811 | ;; combine. |
4812 | (define_expand "maxsf3" | |
8e871c05 | 4813 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4814 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4815 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4816 | (match_dup 1) |
4817 | (match_dup 2)))] | |
50a0b056 GK |
4818 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
4819 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") | |
2f607b94 | 4820 | |
8e871c05 | 4821 | (define_expand "minsf3" |
50a0b056 GK |
4822 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4823 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4824 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4825 | (match_dup 2) | |
4826 | (match_dup 1)))] | |
d14a6d05 | 4827 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 | 4828 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4829 | |
8e871c05 RK |
4830 | (define_split |
4831 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4832 | (match_operator:SF 3 "min_max_operator" |
4833 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4834 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
d14a6d05 | 4835 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 GK |
4836 | [(const_int 0)] |
4837 | " | |
4838 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
4839 | operands[1], operands[2]); | |
4840 | DONE; | |
4841 | }") | |
2f607b94 | 4842 | |
94d7001a | 4843 | (define_expand "movsfcc" |
0ad91047 | 4844 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4845 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4846 | (match_operand:SF 2 "gpc_reg_operand" "") |
4847 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 4848 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4849 | " |
4850 | { | |
50a0b056 GK |
4851 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4852 | DONE; | |
94d7001a | 4853 | else |
50a0b056 | 4854 | FAIL; |
94d7001a | 4855 | }") |
d56d506a | 4856 | |
50a0b056 | 4857 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4858 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4859 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4860 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4861 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4862 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4863 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4864 | "fsel %0,%1,%2,%3" |
4865 | [(set_attr "type" "fp")]) | |
2f607b94 | 4866 | |
50a0b056 | 4867 | (define_insn "*fseldfsf4" |
94d7001a RK |
4868 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4869 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4870 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4871 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4872 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4873 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4874 | "fsel %0,%1,%2,%3" |
4875 | [(set_attr "type" "fp")]) | |
d56d506a | 4876 | |
1fd4e8c1 | 4877 | (define_insn "negdf2" |
cd2b37d9 RK |
4878 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4879 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4880 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4881 | "fneg %0,%1" |
4882 | [(set_attr "type" "fp")]) | |
4883 | ||
4884 | (define_insn "absdf2" | |
cd2b37d9 RK |
4885 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4886 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4887 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4888 | "fabs %0,%1" |
4889 | [(set_attr "type" "fp")]) | |
4890 | ||
4891 | (define_insn "" | |
cd2b37d9 RK |
4892 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4893 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4894 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4895 | "fnabs %0,%1" |
4896 | [(set_attr "type" "fp")]) | |
4897 | ||
4898 | (define_insn "adddf3" | |
cd2b37d9 RK |
4899 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4900 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4901 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4902 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4903 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4904 | [(set_attr "type" "fp")]) |
4905 | ||
4906 | (define_insn "subdf3" | |
cd2b37d9 RK |
4907 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4908 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4909 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4910 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4911 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4912 | [(set_attr "type" "fp")]) |
4913 | ||
4914 | (define_insn "muldf3" | |
cd2b37d9 RK |
4915 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4916 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4917 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4918 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4919 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4920 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4921 | |
4922 | (define_insn "divdf3" | |
cd2b37d9 RK |
4923 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4924 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4925 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4926 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4927 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4928 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4929 | |
4930 | (define_insn "" | |
cd2b37d9 RK |
4931 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4932 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4933 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4934 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 4935 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4936 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4937 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4938 | |
4939 | (define_insn "" | |
cd2b37d9 RK |
4940 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4941 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4942 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4943 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 4944 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4945 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4946 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4947 | |
4948 | (define_insn "" | |
cd2b37d9 RK |
4949 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4950 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4951 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4952 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 4953 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4954 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 4955 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4956 | |
4957 | (define_insn "" | |
cd2b37d9 RK |
4958 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4959 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4960 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4961 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 4962 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4963 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 4964 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
4965 | |
4966 | (define_insn "sqrtdf2" | |
4967 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4968 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4969 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4970 | "fsqrt %0,%1" |
4971 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 4972 | |
50a0b056 GK |
4973 | ;; The conditional move instructions allow us to perform max and min |
4974 | ;; operations even when | |
b77dfefc | 4975 | |
8e871c05 | 4976 | (define_expand "maxdf3" |
8e871c05 | 4977 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4978 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
4979 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4980 | (match_dup 1) |
4981 | (match_dup 2)))] | |
50a0b056 GK |
4982 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
4983 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") | |
b77dfefc | 4984 | |
8e871c05 | 4985 | (define_expand "mindf3" |
50a0b056 GK |
4986 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4987 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
4988 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
4989 | (match_dup 2) | |
4990 | (match_dup 1)))] | |
d14a6d05 | 4991 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 | 4992 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 4993 | |
8e871c05 RK |
4994 | (define_split |
4995 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4996 | (match_operator:DF 3 "min_max_operator" |
4997 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
4998 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
d14a6d05 | 4999 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 GK |
5000 | [(const_int 0)] |
5001 | " | |
5002 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
5003 | operands[1], operands[2]); | |
5004 | DONE; | |
5005 | }") | |
b77dfefc | 5006 | |
94d7001a | 5007 | (define_expand "movdfcc" |
0ad91047 | 5008 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5009 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5010 | (match_operand:DF 2 "gpc_reg_operand" "") |
5011 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 5012 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5013 | " |
5014 | { | |
50a0b056 GK |
5015 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5016 | DONE; | |
94d7001a | 5017 | else |
50a0b056 | 5018 | FAIL; |
94d7001a | 5019 | }") |
d56d506a | 5020 | |
50a0b056 | 5021 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5022 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5023 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5024 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5025 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5026 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5027 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5028 | "fsel %0,%1,%2,%3" |
5029 | [(set_attr "type" "fp")]) | |
d56d506a | 5030 | |
50a0b056 | 5031 | (define_insn "*fselsfdf4" |
94d7001a RK |
5032 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5033 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5034 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5035 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5036 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5037 | "TARGET_PPC_GFXOPT" | |
5038 | "fsel %0,%1,%2,%3" | |
5039 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5040 | \f |
5041 | ;; Conversions to and from floating-point. | |
802a0058 | 5042 | |
9ebbca7d GK |
5043 | ; For each of these conversions, there is a define_expand, a define_insn |
5044 | ; with a '#' template, and a define_split (with C code). The idea is | |
5045 | ; to allow constant folding with the template of the define_insn, | |
5046 | ; then to have the insns split later (between sched1 and final). | |
5047 | ||
1fd4e8c1 | 5048 | (define_expand "floatsidf2" |
802a0058 MM |
5049 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5050 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5051 | (use (match_dup 2)) | |
5052 | (use (match_dup 3)) | |
208c89ce | 5053 | (clobber (match_dup 4)) |
a7df97e6 | 5054 | (clobber (match_dup 5)) |
9ebbca7d | 5055 | (clobber (match_dup 6))])] |
31bfaa0b | 5056 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5057 | " |
5058 | { | |
802a0058 MM |
5059 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5060 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); | |
9ebbca7d GK |
5061 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5062 | operands[5] = gen_reg_rtx (DFmode); | |
5063 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5064 | }") |
5065 | ||
802a0058 MM |
5066 | (define_insn "*floatsidf2_internal" |
5067 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5068 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5069 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5070 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5071 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5072 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f")) | |
5073 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))] | |
31bfaa0b | 5074 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5075 | "#" |
a7df97e6 | 5076 | [(set_attr "length" "24")]) |
802a0058 MM |
5077 | |
5078 | (define_split | |
dbe3df29 | 5079 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5080 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5081 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5082 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5083 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5084 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5085 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
31bfaa0b | 5086 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5087 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5088 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5089 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5090 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5091 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5092 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5093 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5094 | " |
5095 | { | |
9ebbca7d GK |
5096 | rtx lowword, highword; |
5097 | if (GET_CODE (operands[4]) != MEM) | |
5098 | abort(); | |
5099 | highword = XEXP (operands[4], 0); | |
5100 | lowword = plus_constant (highword, 4); | |
5101 | if (! WORDS_BIG_ENDIAN) | |
5102 | { | |
5103 | rtx tmp; | |
5104 | tmp = highword; highword = lowword; lowword = tmp; | |
5105 | } | |
5106 | ||
5107 | emit_insn (gen_xorsi3 (operands[6], operands[1], | |
5108 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); | |
5109 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5110 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5111 | emit_move_insn (operands[5], operands[4]); | |
5112 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5113 | DONE; | |
208c89ce | 5114 | }") |
802a0058 MM |
5115 | |
5116 | (define_expand "floatunssidf2" | |
5117 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5118 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5119 | (use (match_dup 2)) | |
5120 | (use (match_dup 3)) | |
a7df97e6 | 5121 | (clobber (match_dup 4)) |
9ebbca7d | 5122 | (clobber (match_dup 5))])] |
31bfaa0b | 5123 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5124 | " |
5125 | { | |
802a0058 MM |
5126 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5127 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); | |
9ebbca7d GK |
5128 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5129 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5130 | }") |
5131 | ||
802a0058 MM |
5132 | (define_insn "*floatunssidf2_internal" |
5133 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5134 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5135 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5136 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5137 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5138 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))] | |
31bfaa0b | 5139 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5140 | "#" |
a7df97e6 | 5141 | [(set_attr "length" "20")]) |
802a0058 MM |
5142 | |
5143 | (define_split | |
5144 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5145 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5146 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5147 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5148 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5149 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
31bfaa0b | 5150 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5151 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5152 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5153 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5154 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5155 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5156 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5157 | " | |
802a0058 | 5158 | { |
9ebbca7d GK |
5159 | rtx lowword, highword; |
5160 | if (GET_CODE (operands[4]) != MEM) | |
5161 | abort(); | |
5162 | highword = XEXP (operands[4], 0); | |
5163 | lowword = plus_constant (highword, 4); | |
5164 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5165 | { |
9ebbca7d GK |
5166 | rtx tmp; |
5167 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5168 | } |
802a0058 | 5169 | |
9ebbca7d GK |
5170 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5171 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5172 | emit_move_insn (operands[5], operands[4]); | |
5173 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5174 | DONE; | |
5175 | }") | |
1fd4e8c1 | 5176 | |
1fd4e8c1 | 5177 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5178 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5179 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5180 | (clobber (match_dup 2)) | |
9ebbca7d | 5181 | (clobber (match_dup 3))])] |
9cb8fcaf | 5182 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5183 | " |
5184 | { | |
802a0058 | 5185 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5186 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5187 | }") |
5188 | ||
802a0058 MM |
5189 | (define_insn "*fix_truncdfsi2_internal" |
5190 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5191 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5192 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) | |
9ebbca7d | 5193 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
9cb8fcaf | 5194 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
802a0058 | 5195 | "#" |
9ebbca7d | 5196 | [(set_attr "length" "16")]) |
802a0058 MM |
5197 | |
5198 | (define_split | |
5199 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5200 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5201 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
9ebbca7d | 5202 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
9cb8fcaf | 5203 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5204 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5205 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5206 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
5207 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5208 | " | |
802a0058 | 5209 | { |
9ebbca7d GK |
5210 | rtx lowword; |
5211 | if (GET_CODE (operands[3]) != MEM) | |
5212 | abort(); | |
5213 | lowword = XEXP (operands[3], 0); | |
5214 | if (WORDS_BIG_ENDIAN) | |
5215 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5216 | |
9ebbca7d GK |
5217 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5218 | emit_move_insn (operands[3], operands[2]); | |
5219 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5220 | DONE; | |
5221 | }") | |
802a0058 | 5222 | |
9ebbca7d GK |
5223 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10)) |
5224 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) | |
5225 | ; because the first makes it clear that operand 0 is not live | |
5226 | ; before the instruction. | |
5227 | (define_insn "fctiwz" | |
5228 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5229 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] | |
a260abc9 DE |
5230 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
5231 | "{fcirz|fctiwz} %0,%1" | |
5232 | [(set_attr "type" "fp")]) | |
5233 | ||
a473029f RK |
5234 | (define_insn "floatdidf2" |
5235 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5236 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5237 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5238 | "fcfid %0,%1" |
5239 | [(set_attr "type" "fp")]) | |
5240 | ||
5241 | (define_insn "fix_truncdfdi2" | |
5242 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5243 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5244 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5245 | "fctidz %0,%1" |
5246 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5247 | \f |
5248 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5249 | ;; of instructions. The & constraints are to prevent the register |
5250 | ;; allocator from allocating registers that overlap with the inputs | |
5251 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5252 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5253 | |
266eb58a | 5254 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5255 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5256 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5257 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5258 | "! TARGET_POWERPC64" |
0f645302 MM |
5259 | "* |
5260 | { | |
5261 | if (WORDS_BIG_ENDIAN) | |
5262 | return (GET_CODE (operands[2])) != CONST_INT | |
5263 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5264 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5265 | else | |
5266 | return (GET_CODE (operands[2])) != CONST_INT | |
5267 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5268 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5269 | }" | |
b19003d8 | 5270 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5271 | |
266eb58a | 5272 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5273 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5274 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5275 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5276 | "! TARGET_POWERPC64" |
5502823b RK |
5277 | "* |
5278 | { | |
0f645302 MM |
5279 | if (WORDS_BIG_ENDIAN) |
5280 | return (GET_CODE (operands[1]) != CONST_INT) | |
5281 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5282 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5283 | else | |
5284 | return (GET_CODE (operands[1]) != CONST_INT) | |
5285 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5286 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5287 | }" |
ca7f5001 RK |
5288 | [(set_attr "length" "8")]) |
5289 | ||
266eb58a | 5290 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5291 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5292 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5293 | "! TARGET_POWERPC64" |
5502823b RK |
5294 | "* |
5295 | { | |
5296 | return (WORDS_BIG_ENDIAN) | |
5297 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5298 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5299 | }" | |
ca7f5001 RK |
5300 | [(set_attr "length" "8")]) |
5301 | ||
8ffd9c51 RK |
5302 | (define_expand "mulsidi3" |
5303 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5304 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5305 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5306 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5307 | " |
5308 | { | |
5309 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5310 | { | |
39403d82 DE |
5311 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5312 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5313 | emit_insn (gen_mull_call ()); |
cf27b467 | 5314 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5315 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5316 | else |
5317 | { | |
5318 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5319 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5320 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5321 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5322 | } |
8ffd9c51 RK |
5323 | DONE; |
5324 | } | |
5325 | else if (TARGET_POWER) | |
5326 | { | |
5327 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5328 | DONE; | |
5329 | } | |
5330 | }") | |
deb9225a | 5331 | |
8ffd9c51 | 5332 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5333 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5334 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5335 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5336 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5337 | "TARGET_POWER" |
b19003d8 | 5338 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5339 | [(set_attr "type" "imul") |
5340 | (set_attr "length" "8")]) | |
deb9225a | 5341 | |
f192bf8b | 5342 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5343 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5344 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5345 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5346 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5347 | "* |
5348 | { | |
5349 | return (WORDS_BIG_ENDIAN) | |
5350 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5351 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5352 | }" | |
8ffd9c51 RK |
5353 | [(set_attr "type" "imul") |
5354 | (set_attr "length" "8")]) | |
deb9225a | 5355 | |
ebedb4dd MM |
5356 | (define_split |
5357 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5358 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5359 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5360 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5361 | [(set (match_dup 3) |
5362 | (truncate:SI | |
5363 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5364 | (sign_extend:DI (match_dup 2))) | |
5365 | (const_int 32)))) | |
5366 | (set (match_dup 4) | |
5367 | (mult:SI (match_dup 1) | |
5368 | (match_dup 2)))] | |
5369 | " | |
5370 | { | |
5371 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5372 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5373 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5374 | }") | |
5375 | ||
f192bf8b DE |
5376 | (define_expand "umulsidi3" |
5377 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5378 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5379 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5380 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5381 | " | |
5382 | { | |
5383 | if (TARGET_POWER) | |
5384 | { | |
5385 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5386 | DONE; | |
5387 | } | |
5388 | }") | |
5389 | ||
5390 | (define_insn "umulsidi3_mq" | |
5391 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5392 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5393 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5394 | (clobber (match_scratch:SI 3 "=q"))] | |
5395 | "TARGET_POWERPC && TARGET_POWER" | |
5396 | "* | |
5397 | { | |
5398 | return (WORDS_BIG_ENDIAN) | |
5399 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5400 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5401 | }" | |
5402 | [(set_attr "type" "imul") | |
5403 | (set_attr "length" "8")]) | |
5404 | ||
5405 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5406 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5407 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5408 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5409 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5410 | "* |
5411 | { | |
5412 | return (WORDS_BIG_ENDIAN) | |
5413 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5414 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5415 | }" | |
5416 | [(set_attr "type" "imul") | |
5417 | (set_attr "length" "8")]) | |
5418 | ||
ebedb4dd MM |
5419 | (define_split |
5420 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5421 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5422 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5423 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5424 | [(set (match_dup 3) |
5425 | (truncate:SI | |
5426 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5427 | (zero_extend:DI (match_dup 2))) | |
5428 | (const_int 32)))) | |
5429 | (set (match_dup 4) | |
5430 | (mult:SI (match_dup 1) | |
5431 | (match_dup 2)))] | |
5432 | " | |
5433 | { | |
5434 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5435 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5436 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5437 | }") | |
5438 | ||
8ffd9c51 RK |
5439 | (define_expand "smulsi3_highpart" |
5440 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5441 | (truncate:SI | |
5442 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5443 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5444 | (sign_extend:DI | |
5445 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5446 | (const_int 32))))] | |
5447 | "" | |
5448 | " | |
5449 | { | |
5450 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5451 | { | |
39403d82 DE |
5452 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5453 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5454 | emit_insn (gen_mulh_call ()); |
39403d82 | 5455 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5456 | DONE; |
5457 | } | |
5458 | else if (TARGET_POWER) | |
5459 | { | |
5460 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5461 | DONE; | |
5462 | } | |
5463 | }") | |
deb9225a | 5464 | |
8ffd9c51 RK |
5465 | (define_insn "smulsi3_highpart_mq" |
5466 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5467 | (truncate:SI | |
fada905b MM |
5468 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5469 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5470 | (sign_extend:DI | |
5471 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5472 | (const_int 32)))) |
5473 | (clobber (match_scratch:SI 3 "=q"))] | |
5474 | "TARGET_POWER" | |
5475 | "mul %0,%1,%2" | |
5476 | [(set_attr "type" "imul")]) | |
deb9225a | 5477 | |
f192bf8b | 5478 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5479 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5480 | (truncate:SI | |
fada905b MM |
5481 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5482 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5483 | (sign_extend:DI | |
5484 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5485 | (const_int 32))))] |
f192bf8b | 5486 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5487 | "mulhw %0,%1,%2" |
5488 | [(set_attr "type" "imul")]) | |
deb9225a | 5489 | |
f192bf8b DE |
5490 | (define_expand "umulsi3_highpart" |
5491 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5492 | (truncate:SI | |
5493 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5494 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5495 | (zero_extend:DI | |
5496 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5497 | (const_int 32))))] | |
5498 | "TARGET_POWERPC" | |
5499 | " | |
5500 | { | |
5501 | if (TARGET_POWER) | |
5502 | { | |
5503 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5504 | DONE; | |
5505 | } | |
5506 | }") | |
5507 | ||
5508 | (define_insn "umulsi3_highpart_mq" | |
5509 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5510 | (truncate:SI | |
5511 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5512 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5513 | (zero_extend:DI | |
5514 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5515 | (const_int 32)))) | |
5516 | (clobber (match_scratch:SI 3 "=q"))] | |
5517 | "TARGET_POWERPC && TARGET_POWER" | |
5518 | "mulhwu %0,%1,%2" | |
5519 | [(set_attr "type" "imul")]) | |
5520 | ||
5521 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5522 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5523 | (truncate:SI | |
5524 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5525 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5526 | (zero_extend:DI | |
5527 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5528 | (const_int 32))))] | |
f192bf8b | 5529 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5530 | "mulhwu %0,%1,%2" |
5531 | [(set_attr "type" "imul")]) | |
5532 | ||
5533 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5534 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5535 | ;; why we have the strange constraints below. | |
5536 | (define_insn "ashldi3_power" | |
5537 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5538 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5539 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5540 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5541 | "TARGET_POWER" | |
5542 | "@ | |
5543 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5544 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5545 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5546 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5547 | [(set_attr "length" "8")]) | |
5548 | ||
5549 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5550 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5551 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5552 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5553 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5554 | "TARGET_POWER" | |
5555 | "@ | |
47ad8c61 | 5556 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5557 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5558 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5559 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5560 | [(set_attr "length" "8")]) | |
5561 | ||
5562 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5563 | ;; just handle shifts by constants. | |
5564 | (define_insn "ashrdi3_power" | |
7093ddee | 5565 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5566 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5567 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5568 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5569 | "TARGET_POWER" | |
5570 | "@ | |
5571 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5572 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5573 | [(set_attr "length" "8")]) | |
5574 | \f | |
5575 | ;; PowerPC64 DImode operations. | |
5576 | ||
5577 | (define_expand "adddi3" | |
5578 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5579 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 5580 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
5581 | "" |
5582 | " | |
5583 | { | |
a260abc9 DE |
5584 | if (! TARGET_POWERPC64) |
5585 | { | |
5586 | if (non_short_cint_operand (operands[2], DImode)) | |
5587 | FAIL; | |
5588 | } | |
5589 | else | |
5590 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5591 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5592 | { |
677a9668 | 5593 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5594 | ? operands[0] : gen_reg_rtx (DImode)); |
5595 | ||
2bfcf297 DB |
5596 | HOST_WIDE_INT val = INTVAL (operands[2]); |
5597 | HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); | |
5598 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); | |
a260abc9 | 5599 | |
2bfcf297 DB |
5600 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
5601 | FAIL; | |
a260abc9 | 5602 | |
2bfcf297 DB |
5603 | /* The ordering here is important for the prolog expander. |
5604 | When space is allocated from the stack, adding 'low' first may | |
5605 | produce a temporary deallocation (which would be bad). */ | |
5606 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
5607 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
5608 | DONE; | |
5609 | } | |
266eb58a DE |
5610 | }") |
5611 | ||
5612 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5613 | ;; allowing register zero as source. | |
5614 | ||
a260abc9 | 5615 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5616 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5617 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5618 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5619 | "TARGET_POWERPC64" |
5620 | "@ | |
5621 | add %0,%1,%2 | |
5622 | addi %0,%1,%2 | |
5623 | addic %0,%1,%2 | |
802a0058 | 5624 | addis %0,%1,%v2") |
266eb58a | 5625 | |
a260abc9 | 5626 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5627 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5628 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5629 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5630 | (const_int 0))) |
9ebbca7d | 5631 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
266eb58a DE |
5632 | "TARGET_POWERPC64" |
5633 | "@ | |
5634 | add. %3,%1,%2 | |
9ebbca7d GK |
5635 | addic. %3,%1,%2 |
5636 | # | |
5637 | #" | |
5638 | [(set_attr "type" "compare") | |
5639 | (set_attr "length" "4,4,8,8")]) | |
5640 | ||
5641 | (define_split | |
5642 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5643 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5644 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5645 | (const_int 0))) | |
5646 | (clobber (match_scratch:DI 3 ""))] | |
5647 | "TARGET_POWERPC64 && reload_completed" | |
5648 | [(set (match_dup 3) | |
5649 | (plus:DI (match_dup 1) (match_dup 2))) | |
5650 | (set (match_dup 0) | |
5651 | (compare:CC (match_dup 3) | |
5652 | (const_int 0)))] | |
5653 | "") | |
266eb58a | 5654 | |
a260abc9 | 5655 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5656 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5657 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5658 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5659 | (const_int 0))) |
9ebbca7d | 5660 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a DE |
5661 | (plus:DI (match_dup 1) (match_dup 2)))] |
5662 | "TARGET_POWERPC64" | |
5663 | "@ | |
5664 | add. %0,%1,%2 | |
9ebbca7d GK |
5665 | addic. %0,%1,%2 |
5666 | # | |
5667 | #" | |
5668 | [(set_attr "type" "compare") | |
5669 | (set_attr "length" "4,4,8,8")]) | |
5670 | ||
5671 | (define_split | |
5672 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5673 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5674 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5675 | (const_int 0))) | |
5676 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5677 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5678 | "TARGET_POWERPC64 && reload_completed" | |
5679 | [(set (match_dup 0) | |
5680 | (plus:DI (match_dup 1) (match_dup 2))) | |
5681 | (set (match_dup 3) | |
5682 | (compare:CC (match_dup 0) | |
5683 | (const_int 0)))] | |
5684 | "") | |
266eb58a DE |
5685 | |
5686 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5687 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5688 | ;; add should be last in case the result gets used in an address. | |
5689 | ||
5690 | (define_split | |
5691 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5692 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5693 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5694 | "TARGET_POWERPC64" | |
5695 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5696 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5697 | " | |
5698 | { | |
2bfcf297 DB |
5699 | HOST_WIDE_INT val = INTVAL (operands[2]); |
5700 | HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); | |
5701 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); | |
266eb58a | 5702 | |
2bfcf297 DB |
5703 | operands[4] = GEN_INT (low); |
5704 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
5705 | operands[3] = GEN_INT (rest); | |
5706 | else if (! no_new_pseudos) | |
38886f37 | 5707 | { |
2bfcf297 DB |
5708 | operands[3] = gen_reg_rtx (DImode); |
5709 | emit_move_insn (operands[3], operands[2]); | |
5710 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
5711 | DONE; | |
38886f37 | 5712 | } |
2bfcf297 DB |
5713 | else |
5714 | FAIL; | |
266eb58a DE |
5715 | }") |
5716 | ||
5717 | (define_insn "one_cmpldi2" | |
5718 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5719 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5720 | "TARGET_POWERPC64" | |
5721 | "nor %0,%1,%1") | |
5722 | ||
5723 | (define_insn "" | |
9ebbca7d GK |
5724 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5725 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5726 | (const_int 0))) |
9ebbca7d | 5727 | (clobber (match_scratch:DI 2 "=r,r"))] |
266eb58a | 5728 | "TARGET_POWERPC64" |
9ebbca7d GK |
5729 | "@ |
5730 | nor. %2,%1,%1 | |
5731 | #" | |
5732 | [(set_attr "type" "compare") | |
5733 | (set_attr "length" "4,8")]) | |
5734 | ||
5735 | (define_split | |
5736 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5737 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5738 | (const_int 0))) | |
5739 | (clobber (match_scratch:DI 2 ""))] | |
5740 | "TARGET_POWERPC64 && reload_completed" | |
5741 | [(set (match_dup 2) | |
5742 | (not:DI (match_dup 1))) | |
5743 | (set (match_dup 0) | |
5744 | (compare:CC (match_dup 2) | |
5745 | (const_int 0)))] | |
5746 | "") | |
266eb58a DE |
5747 | |
5748 | (define_insn "" | |
9ebbca7d GK |
5749 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5750 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5751 | (const_int 0))) |
9ebbca7d | 5752 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5753 | (not:DI (match_dup 1)))] |
5754 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5755 | "@ |
5756 | nor. %0,%1,%1 | |
5757 | #" | |
5758 | [(set_attr "type" "compare") | |
5759 | (set_attr "length" "4,8")]) | |
5760 | ||
5761 | (define_split | |
5762 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5763 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5764 | (const_int 0))) | |
5765 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5766 | (not:DI (match_dup 1)))] | |
5767 | "TARGET_POWERPC64 && reload_completed" | |
5768 | [(set (match_dup 0) | |
5769 | (not:DI (match_dup 1))) | |
5770 | (set (match_dup 2) | |
5771 | (compare:CC (match_dup 0) | |
5772 | (const_int 0)))] | |
5773 | "") | |
266eb58a DE |
5774 | |
5775 | (define_insn "" | |
5776 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5777 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5778 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5779 | "TARGET_POWERPC64" | |
5780 | "@ | |
5781 | subf %0,%2,%1 | |
5782 | subfic %0,%2,%1") | |
5783 | ||
5784 | (define_insn "" | |
9ebbca7d GK |
5785 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5786 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5787 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5788 | (const_int 0))) |
9ebbca7d | 5789 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 5790 | "TARGET_POWERPC64" |
9ebbca7d GK |
5791 | "@ |
5792 | subf. %3,%2,%1 | |
5793 | #" | |
5794 | [(set_attr "type" "compare") | |
5795 | (set_attr "length" "4,8")]) | |
5796 | ||
5797 | (define_split | |
5798 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5799 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5800 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5801 | (const_int 0))) | |
5802 | (clobber (match_scratch:DI 3 ""))] | |
5803 | "TARGET_POWERPC64 && reload_completed" | |
5804 | [(set (match_dup 3) | |
5805 | (minus:DI (match_dup 1) (match_dup 2))) | |
5806 | (set (match_dup 0) | |
5807 | (compare:CC (match_dup 3) | |
5808 | (const_int 0)))] | |
5809 | "") | |
266eb58a DE |
5810 | |
5811 | (define_insn "" | |
9ebbca7d GK |
5812 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5813 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5814 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5815 | (const_int 0))) |
9ebbca7d | 5816 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5817 | (minus:DI (match_dup 1) (match_dup 2)))] |
5818 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5819 | "@ |
5820 | subf. %0,%2,%1 | |
5821 | #" | |
5822 | [(set_attr "type" "compare") | |
5823 | (set_attr "length" "4,8")]) | |
5824 | ||
5825 | (define_split | |
5826 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5827 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5828 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5829 | (const_int 0))) | |
5830 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5831 | (minus:DI (match_dup 1) (match_dup 2)))] | |
5832 | "TARGET_POWERPC64 && reload_completed" | |
5833 | [(set (match_dup 0) | |
5834 | (minus:DI (match_dup 1) (match_dup 2))) | |
5835 | (set (match_dup 3) | |
5836 | (compare:CC (match_dup 0) | |
5837 | (const_int 0)))] | |
5838 | "") | |
266eb58a DE |
5839 | |
5840 | (define_expand "subdi3" | |
5841 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5842 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 5843 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
5844 | "" |
5845 | " | |
5846 | { | |
5847 | if (GET_CODE (operands[2]) == CONST_INT) | |
5848 | { | |
5849 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
5850 | negate_rtx (DImode, operands[2]))); | |
5851 | DONE; | |
5852 | } | |
5853 | }") | |
5854 | ||
5855 | (define_insn "absdi2" | |
5856 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
5857 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
5858 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5859 | "TARGET_POWERPC64" | |
a260abc9 | 5860 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" |
266eb58a DE |
5861 | [(set_attr "length" "12")]) |
5862 | ||
5863 | (define_split | |
5864 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
5865 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
5866 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5867 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 5868 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5869 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 5870 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
5871 | "") |
5872 | ||
19ba8161 | 5873 | (define_insn "*nabsdi2" |
266eb58a DE |
5874 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5875 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
5876 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5877 | "TARGET_POWERPC64" | |
a260abc9 | 5878 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" |
266eb58a DE |
5879 | [(set_attr "length" "12")]) |
5880 | ||
5881 | (define_split | |
5882 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
5883 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
5884 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5885 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 5886 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5887 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 5888 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
5889 | "") |
5890 | ||
5891 | (define_expand "negdi2" | |
5892 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5893 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
5894 | "" | |
5895 | "") | |
5896 | ||
5897 | (define_insn "" | |
5898 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5899 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5900 | "TARGET_POWERPC64" | |
5901 | "neg %0,%1") | |
5902 | ||
5903 | (define_insn "" | |
9ebbca7d GK |
5904 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5905 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5906 | (const_int 0))) |
9ebbca7d | 5907 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 5908 | "TARGET_POWERPC64" |
9ebbca7d GK |
5909 | "@ |
5910 | neg. %2,%1 | |
5911 | #" | |
5912 | [(set_attr "type" "compare") | |
5913 | (set_attr "length" "4,8")]) | |
5914 | ||
5915 | (define_split | |
5916 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5917 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5918 | (const_int 0))) | |
5919 | (clobber (match_scratch:DI 2 ""))] | |
5920 | "TARGET_POWERPC64 && reload_completed" | |
5921 | [(set (match_dup 2) | |
5922 | (neg:DI (match_dup 1))) | |
5923 | (set (match_dup 0) | |
5924 | (compare:CC (match_dup 2) | |
5925 | (const_int 0)))] | |
5926 | "") | |
815cdc52 | 5927 | |
29ae5b89 | 5928 | (define_insn "" |
9ebbca7d GK |
5929 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5930 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 5931 | (const_int 0))) |
9ebbca7d | 5932 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 5933 | (neg:DI (match_dup 1)))] |
29ae5b89 | 5934 | "TARGET_POWERPC64" |
9ebbca7d GK |
5935 | "@ |
5936 | neg. %0,%1 | |
5937 | #" | |
5938 | [(set_attr "type" "compare") | |
5939 | (set_attr "length" "4,8")]) | |
5940 | ||
5941 | (define_split | |
5942 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5943 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5944 | (const_int 0))) | |
5945 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5946 | (neg:DI (match_dup 1)))] | |
5947 | "TARGET_POWERPC64 && reload_completed" | |
5948 | [(set (match_dup 0) | |
5949 | (neg:DI (match_dup 1))) | |
5950 | (set (match_dup 2) | |
5951 | (compare:CC (match_dup 0) | |
5952 | (const_int 0)))] | |
5953 | "") | |
266eb58a DE |
5954 | |
5955 | (define_insn "ffsdi2" | |
5956 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5957 | (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5958 | "TARGET_POWERPC64" | |
5959 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
5960 | [(set_attr "length" "16")]) | |
5961 | ||
5962 | (define_insn "muldi3" | |
5963 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5964 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5965 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
5966 | "TARGET_POWERPC64" | |
5967 | "mulld %0,%1,%2" | |
3cb999d8 | 5968 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5969 | |
5970 | (define_insn "smuldi3_highpart" | |
5971 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5972 | (truncate:DI | |
5973 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
5974 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5975 | (sign_extend:TI | |
5976 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5977 | (const_int 64))))] | |
5978 | "TARGET_POWERPC64" | |
5979 | "mulhd %0,%1,%2" | |
3cb999d8 | 5980 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5981 | |
5982 | (define_insn "umuldi3_highpart" | |
5983 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5984 | (truncate:DI | |
5985 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
5986 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5987 | (zero_extend:TI | |
5988 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5989 | (const_int 64))))] | |
5990 | "TARGET_POWERPC64" | |
5991 | "mulhdu %0,%1,%2" | |
3cb999d8 | 5992 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5993 | |
5994 | (define_expand "divdi3" | |
5995 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5996 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5997 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
5998 | "TARGET_POWERPC64" | |
5999 | " | |
6000 | { | |
6001 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6002 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6003 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6004 | ; | |
6005 | else | |
6006 | operands[2] = force_reg (DImode, operands[2]); | |
6007 | }") | |
6008 | ||
6009 | (define_expand "moddi3" | |
6010 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6011 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6012 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6013 | "TARGET_POWERPC64" | |
6014 | " | |
6015 | { | |
2bfcf297 | 6016 | int i; |
266eb58a DE |
6017 | rtx temp1; |
6018 | rtx temp2; | |
6019 | ||
2bfcf297 DB |
6020 | if (GET_CODE (operands[2]) != CONST_INT |
6021 | || INTVAL (operands[2]) <= 0 | |
6022 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6023 | FAIL; |
6024 | ||
6025 | temp1 = gen_reg_rtx (DImode); | |
6026 | temp2 = gen_reg_rtx (DImode); | |
6027 | ||
6028 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6029 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6030 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6031 | DONE; | |
6032 | }") | |
6033 | ||
6034 | (define_insn "" | |
6035 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6036 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6037 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6038 | "TARGET_POWERPC64" | |
266eb58a DE |
6039 | "sradi %0,%1,%p2\;addze %0,%0" |
6040 | [(set_attr "length" "8")]) | |
6041 | ||
6042 | (define_insn "" | |
9ebbca7d GK |
6043 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6044 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6045 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6046 | (const_int 0))) |
9ebbca7d | 6047 | (clobber (match_scratch:DI 3 "=r,r"))] |
2bfcf297 | 6048 | "TARGET_POWERPC64" |
9ebbca7d GK |
6049 | "@ |
6050 | sradi %3,%1,%p2\;addze. %3,%3 | |
6051 | #" | |
266eb58a | 6052 | [(set_attr "type" "compare") |
9ebbca7d GK |
6053 | (set_attr "length" "8,12")]) |
6054 | ||
6055 | (define_split | |
6056 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6057 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6058 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6059 | (const_int 0))) |
6060 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6061 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6062 | [(set (match_dup 3) |
6063 | (div:DI (match_dup 1) (match_dup 2))) | |
6064 | (set (match_dup 0) | |
6065 | (compare:CC (match_dup 3) | |
6066 | (const_int 0)))] | |
6067 | "") | |
266eb58a DE |
6068 | |
6069 | (define_insn "" | |
9ebbca7d GK |
6070 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6071 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6072 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6073 | (const_int 0))) |
9ebbca7d | 6074 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6075 | (div:DI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 6076 | "TARGET_POWERPC64" |
9ebbca7d GK |
6077 | "@ |
6078 | sradi %0,%1,%p2\;addze. %0,%0 | |
6079 | #" | |
266eb58a | 6080 | [(set_attr "type" "compare") |
9ebbca7d | 6081 | (set_attr "length" "8,12")]) |
266eb58a | 6082 | |
9ebbca7d GK |
6083 | (define_split |
6084 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6085 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6086 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6087 | (const_int 0))) |
6088 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6089 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6090 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6091 | [(set (match_dup 0) |
6092 | (div:DI (match_dup 1) (match_dup 2))) | |
6093 | (set (match_dup 3) | |
6094 | (compare:CC (match_dup 0) | |
6095 | (const_int 0)))] | |
6096 | "") | |
6097 | ||
6098 | (define_insn "" | |
6099 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6100 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6101 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6102 | "TARGET_POWERPC64" |
6103 | "divd %0,%1,%2" | |
3cb999d8 | 6104 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6105 | |
6106 | (define_insn "udivdi3" | |
6107 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6108 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6109 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6110 | "TARGET_POWERPC64" | |
6111 | "divdu %0,%1,%2" | |
3cb999d8 | 6112 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6113 | |
6114 | (define_insn "rotldi3" | |
6115 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6116 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6117 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6118 | "TARGET_POWERPC64" | |
a66078ee | 6119 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6120 | |
a260abc9 | 6121 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6122 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6123 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6124 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6125 | (const_int 0))) |
9ebbca7d | 6126 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6127 | "TARGET_POWERPC64" |
9ebbca7d GK |
6128 | "@ |
6129 | rld%I2cl. %3,%1,%H2,0 | |
6130 | #" | |
6131 | [(set_attr "type" "delayed_compare") | |
6132 | (set_attr "length" "4,8")]) | |
6133 | ||
6134 | (define_split | |
6135 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6136 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6137 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6138 | (const_int 0))) | |
6139 | (clobber (match_scratch:DI 3 ""))] | |
6140 | "TARGET_POWERPC64 && reload_completed" | |
6141 | [(set (match_dup 3) | |
6142 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6143 | (set (match_dup 0) | |
6144 | (compare:CC (match_dup 3) | |
6145 | (const_int 0)))] | |
6146 | "") | |
266eb58a | 6147 | |
a260abc9 | 6148 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6149 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6150 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6151 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6152 | (const_int 0))) |
9ebbca7d | 6153 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6154 | (rotate:DI (match_dup 1) (match_dup 2)))] |
6155 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6156 | "@ |
6157 | rld%I2cl. %0,%1,%H2,0 | |
6158 | #" | |
6159 | [(set_attr "type" "delayed_compare") | |
6160 | (set_attr "length" "4,8")]) | |
6161 | ||
6162 | (define_split | |
6163 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6164 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6165 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6166 | (const_int 0))) | |
6167 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6168 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6169 | "TARGET_POWERPC64 && reload_completed" | |
6170 | [(set (match_dup 0) | |
6171 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6172 | (set (match_dup 3) | |
6173 | (compare:CC (match_dup 0) | |
6174 | (const_int 0)))] | |
6175 | "") | |
266eb58a | 6176 | |
a260abc9 DE |
6177 | (define_insn "*rotldi3_internal4" |
6178 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6179 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6180 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
6181 | (match_operand:DI 3 "mask64_operand" "S")))] | |
6182 | "TARGET_POWERPC64" | |
6183 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6184 | ||
6185 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6186 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6187 | (compare:CC (and:DI |
9ebbca7d GK |
6188 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6189 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6190 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6191 | (const_int 0))) |
9ebbca7d | 6192 | (clobber (match_scratch:DI 4 "=r,r"))] |
a260abc9 | 6193 | "TARGET_POWERPC64" |
9ebbca7d GK |
6194 | "@ |
6195 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6196 | #" | |
6197 | [(set_attr "type" "delayed_compare") | |
6198 | (set_attr "length" "4,8")]) | |
6199 | ||
6200 | (define_split | |
6201 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6202 | (compare:CC (and:DI | |
6203 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6204 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6205 | (match_operand:DI 3 "mask64_operand" "")) | |
6206 | (const_int 0))) | |
6207 | (clobber (match_scratch:DI 4 ""))] | |
6208 | "TARGET_POWERPC64 && reload_completed" | |
6209 | [(set (match_dup 4) | |
6210 | (and:DI (rotate:DI (match_dup 1) | |
6211 | (match_dup 2)) | |
6212 | (match_dup 3))) | |
6213 | (set (match_dup 0) | |
6214 | (compare:CC (match_dup 4) | |
6215 | (const_int 0)))] | |
6216 | "") | |
a260abc9 DE |
6217 | |
6218 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6219 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6220 | (compare:CC (and:DI |
9ebbca7d GK |
6221 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6222 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6223 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6224 | (const_int 0))) |
9ebbca7d | 6225 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6226 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
6227 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6228 | "@ |
6229 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6230 | #" | |
6231 | [(set_attr "type" "delayed_compare") | |
6232 | (set_attr "length" "4,8")]) | |
6233 | ||
6234 | (define_split | |
6235 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6236 | (compare:CC (and:DI | |
6237 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6238 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6239 | (match_operand:DI 3 "mask64_operand" "")) | |
6240 | (const_int 0))) | |
6241 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6242 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6243 | "TARGET_POWERPC64 && reload_completed" | |
6244 | [(set (match_dup 0) | |
6245 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6246 | (set (match_dup 4) | |
6247 | (compare:CC (match_dup 0) | |
6248 | (const_int 0)))] | |
6249 | "") | |
a260abc9 DE |
6250 | |
6251 | (define_insn "*rotldi3_internal7" | |
6252 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6253 | (zero_extend:DI | |
6254 | (subreg:QI | |
6255 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6256 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6257 | "TARGET_POWERPC64" | |
6258 | "rld%I2cl %0,%1,%H2,56") | |
6259 | ||
6260 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6261 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6262 | (compare:CC (zero_extend:DI |
6263 | (subreg:QI | |
9ebbca7d GK |
6264 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6265 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6266 | (const_int 0))) |
9ebbca7d | 6267 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6268 | "TARGET_POWERPC64" |
9ebbca7d GK |
6269 | "@ |
6270 | rld%I2cl. %3,%1,%H2,56 | |
6271 | #" | |
6272 | [(set_attr "type" "delayed_compare") | |
6273 | (set_attr "length" "4,8")]) | |
6274 | ||
6275 | (define_split | |
6276 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6277 | (compare:CC (zero_extend:DI | |
6278 | (subreg:QI | |
6279 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6280 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6281 | (const_int 0))) | |
6282 | (clobber (match_scratch:DI 3 ""))] | |
6283 | "TARGET_POWERPC64 && reload_completed" | |
6284 | [(set (match_dup 3) | |
6285 | (zero_extend:DI (subreg:QI | |
6286 | (rotate:DI (match_dup 1) | |
6287 | (match_dup 2)) 0))) | |
6288 | (set (match_dup 0) | |
6289 | (compare:CC (match_dup 3) | |
6290 | (const_int 0)))] | |
6291 | "") | |
a260abc9 DE |
6292 | |
6293 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6294 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6295 | (compare:CC (zero_extend:DI |
6296 | (subreg:QI | |
9ebbca7d GK |
6297 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6298 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6299 | (const_int 0))) |
9ebbca7d | 6300 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6301 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6302 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6303 | "@ |
6304 | rld%I2cl. %0,%1,%H2,56 | |
6305 | #" | |
6306 | [(set_attr "type" "delayed_compare") | |
6307 | (set_attr "length" "4,8")]) | |
6308 | ||
6309 | (define_split | |
6310 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6311 | (compare:CC (zero_extend:DI | |
6312 | (subreg:QI | |
6313 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6314 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6315 | (const_int 0))) | |
6316 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6317 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6318 | "TARGET_POWERPC64 && reload_completed" | |
6319 | [(set (match_dup 0) | |
6320 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6321 | (set (match_dup 3) | |
6322 | (compare:CC (match_dup 0) | |
6323 | (const_int 0)))] | |
6324 | "") | |
a260abc9 DE |
6325 | |
6326 | (define_insn "*rotldi3_internal10" | |
6327 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6328 | (zero_extend:DI | |
6329 | (subreg:HI | |
6330 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6331 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6332 | "TARGET_POWERPC64" | |
6333 | "rld%I2cl %0,%1,%H2,48") | |
6334 | ||
6335 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6336 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6337 | (compare:CC (zero_extend:DI |
6338 | (subreg:HI | |
9ebbca7d GK |
6339 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6340 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6341 | (const_int 0))) |
9ebbca7d | 6342 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6343 | "TARGET_POWERPC64" |
9ebbca7d GK |
6344 | "@ |
6345 | rld%I2cl. %3,%1,%H2,48 | |
6346 | #" | |
6347 | [(set_attr "type" "delayed_compare") | |
6348 | (set_attr "length" "4,8")]) | |
6349 | ||
6350 | (define_split | |
6351 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6352 | (compare:CC (zero_extend:DI | |
6353 | (subreg:HI | |
6354 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6355 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6356 | (const_int 0))) | |
6357 | (clobber (match_scratch:DI 3 ""))] | |
6358 | "TARGET_POWERPC64 && reload_completed" | |
6359 | [(set (match_dup 3) | |
6360 | (zero_extend:DI (subreg:HI | |
6361 | (rotate:DI (match_dup 1) | |
6362 | (match_dup 2)) 0))) | |
6363 | (set (match_dup 0) | |
6364 | (compare:CC (match_dup 3) | |
6365 | (const_int 0)))] | |
6366 | "") | |
a260abc9 DE |
6367 | |
6368 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6369 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6370 | (compare:CC (zero_extend:DI |
6371 | (subreg:HI | |
9ebbca7d GK |
6372 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6373 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6374 | (const_int 0))) |
9ebbca7d | 6375 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6376 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6377 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6378 | "@ |
6379 | rld%I2cl. %0,%1,%H2,48 | |
6380 | #" | |
6381 | [(set_attr "type" "delayed_compare") | |
6382 | (set_attr "length" "4,8")]) | |
6383 | ||
6384 | (define_split | |
6385 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6386 | (compare:CC (zero_extend:DI | |
6387 | (subreg:HI | |
6388 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6389 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6390 | (const_int 0))) | |
6391 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6392 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6393 | "TARGET_POWERPC64 && reload_completed" | |
6394 | [(set (match_dup 0) | |
6395 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6396 | (set (match_dup 3) | |
6397 | (compare:CC (match_dup 0) | |
6398 | (const_int 0)))] | |
6399 | "") | |
a260abc9 DE |
6400 | |
6401 | (define_insn "*rotldi3_internal13" | |
6402 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6403 | (zero_extend:DI | |
6404 | (subreg:SI | |
6405 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6406 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6407 | "TARGET_POWERPC64" | |
6408 | "rld%I2cl %0,%1,%H2,32") | |
6409 | ||
6410 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6411 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6412 | (compare:CC (zero_extend:DI |
6413 | (subreg:SI | |
9ebbca7d GK |
6414 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6415 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6416 | (const_int 0))) |
9ebbca7d | 6417 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6418 | "TARGET_POWERPC64" |
9ebbca7d GK |
6419 | "@ |
6420 | rld%I2cl. %3,%1,%H2,32 | |
6421 | #" | |
6422 | [(set_attr "type" "delayed_compare") | |
6423 | (set_attr "length" "4,8")]) | |
6424 | ||
6425 | (define_split | |
6426 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6427 | (compare:CC (zero_extend:DI | |
6428 | (subreg:SI | |
6429 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6430 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6431 | (const_int 0))) | |
6432 | (clobber (match_scratch:DI 3 ""))] | |
6433 | "TARGET_POWERPC64 && reload_completed" | |
6434 | [(set (match_dup 3) | |
6435 | (zero_extend:DI (subreg:SI | |
6436 | (rotate:DI (match_dup 1) | |
6437 | (match_dup 2)) 0))) | |
6438 | (set (match_dup 0) | |
6439 | (compare:CC (match_dup 3) | |
6440 | (const_int 0)))] | |
6441 | "") | |
a260abc9 DE |
6442 | |
6443 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6444 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6445 | (compare:CC (zero_extend:DI |
6446 | (subreg:SI | |
9ebbca7d GK |
6447 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6448 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6449 | (const_int 0))) |
9ebbca7d | 6450 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6451 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6452 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6453 | "@ |
6454 | rld%I2cl. %0,%1,%H2,32 | |
6455 | #" | |
6456 | [(set_attr "type" "delayed_compare") | |
6457 | (set_attr "length" "4,8")]) | |
6458 | ||
6459 | (define_split | |
6460 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6461 | (compare:CC (zero_extend:DI | |
6462 | (subreg:SI | |
6463 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6464 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6465 | (const_int 0))) | |
6466 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6467 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6468 | "TARGET_POWERPC64 && reload_completed" | |
6469 | [(set (match_dup 0) | |
6470 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6471 | (set (match_dup 3) | |
6472 | (compare:CC (match_dup 0) | |
6473 | (const_int 0)))] | |
6474 | "") | |
a260abc9 | 6475 | |
266eb58a DE |
6476 | (define_expand "ashldi3" |
6477 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6478 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6479 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6480 | "TARGET_POWERPC64 || TARGET_POWER" | |
6481 | " | |
6482 | { | |
6483 | if (TARGET_POWERPC64) | |
6484 | ; | |
6485 | else if (TARGET_POWER) | |
6486 | { | |
6487 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6488 | DONE; | |
6489 | } | |
6490 | else | |
6491 | FAIL; | |
6492 | }") | |
6493 | ||
e2c953b6 | 6494 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6495 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6496 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6497 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6498 | "TARGET_POWERPC64" | |
a66078ee | 6499 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
6500 | [(set_attr "length" "8")]) |
6501 | ||
e2c953b6 | 6502 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6503 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6504 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6505 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6506 | (const_int 0))) |
9ebbca7d | 6507 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6508 | "TARGET_POWERPC64" |
9ebbca7d GK |
6509 | "@ |
6510 | sld%I2. %3,%1,%H2 | |
6511 | #" | |
6512 | [(set_attr "type" "delayed_compare") | |
6513 | (set_attr "length" "4,8")]) | |
29ae5b89 | 6514 | |
9ebbca7d GK |
6515 | (define_split |
6516 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6517 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6518 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6519 | (const_int 0))) | |
6520 | (clobber (match_scratch:DI 3 ""))] | |
6521 | "TARGET_POWERPC64 && reload_completed" | |
6522 | [(set (match_dup 3) | |
6523 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6524 | (set (match_dup 0) | |
6525 | (compare:CC (match_dup 3) | |
6526 | (const_int 0)))] | |
6527 | "") | |
6528 | ||
e2c953b6 | 6529 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6530 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6531 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6532 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6533 | (const_int 0))) |
9ebbca7d | 6534 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6535 | (ashift:DI (match_dup 1) (match_dup 2)))] |
6536 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6537 | "@ |
6538 | sld%I2. %0,%1,%H2 | |
6539 | #" | |
6540 | [(set_attr "type" "delayed_compare") | |
6541 | (set_attr "length" "4,8")]) | |
6542 | ||
6543 | (define_split | |
6544 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6545 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6546 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6547 | (const_int 0))) | |
6548 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6549 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6550 | "TARGET_POWERPC64 && reload_completed" | |
6551 | [(set (match_dup 0) | |
6552 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6553 | (set (match_dup 3) | |
6554 | (compare:CC (match_dup 0) | |
6555 | (const_int 0)))] | |
6556 | "") | |
266eb58a | 6557 | |
e2c953b6 | 6558 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6559 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6560 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6561 | (match_operand:SI 2 "const_int_operand" "i")) | |
e2c953b6 | 6562 | (match_operand:DI 3 "rldic_operand" "n")))] |
4264cf59 | 6563 | "TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3])" |
e2c953b6 | 6564 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6565 | |
e2c953b6 | 6566 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6567 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6568 | (compare:CC |
9ebbca7d GK |
6569 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6570 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
e2c953b6 | 6571 | (match_operand:DI 3 "rldic_operand" "n,n")) |
3cb999d8 | 6572 | (const_int 0))) |
9ebbca7d | 6573 | (clobber (match_scratch:DI 4 "=r,r"))] |
4264cf59 | 6574 | "TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3])" |
9ebbca7d | 6575 | "@ |
e2c953b6 | 6576 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6577 | #" |
6578 | [(set_attr "type" "delayed_compare") | |
6579 | (set_attr "length" "4,8")]) | |
6580 | ||
6581 | (define_split | |
6582 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6583 | (compare:CC | |
6584 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6585 | (match_operand:SI 2 "const_int_operand" "")) | |
e2c953b6 | 6586 | (match_operand:DI 3 "rldic_operand" "")) |
9ebbca7d GK |
6587 | (const_int 0))) |
6588 | (clobber (match_scratch:DI 4 ""))] | |
4264cf59 | 6589 | "TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
6590 | [(set (match_dup 4) |
6591 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6592 | (match_dup 3))) |
9ebbca7d GK |
6593 | (set (match_dup 0) |
6594 | (compare:CC (match_dup 4) | |
6595 | (const_int 0)))] | |
6596 | "") | |
3cb999d8 | 6597 | |
e2c953b6 | 6598 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6599 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6600 | (compare:CC |
9ebbca7d GK |
6601 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6602 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
e2c953b6 | 6603 | (match_operand:DI 3 "rldic_operand" "n,n")) |
3cb999d8 | 6604 | (const_int 0))) |
9ebbca7d | 6605 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6606 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
4264cf59 | 6607 | "TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3])" |
9ebbca7d | 6608 | "@ |
e2c953b6 | 6609 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6610 | #" |
6611 | [(set_attr "type" "delayed_compare") | |
6612 | (set_attr "length" "4,8")]) | |
6613 | ||
6614 | (define_split | |
6615 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6616 | (compare:CC | |
6617 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6618 | (match_operand:SI 2 "const_int_operand" "")) | |
e2c953b6 | 6619 | (match_operand:DI 3 "rldic_operand" "")) |
9ebbca7d GK |
6620 | (const_int 0))) |
6621 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6622 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4264cf59 | 6623 | "TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d | 6624 | [(set (match_dup 0) |
e2c953b6 DE |
6625 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6626 | (match_dup 3))) | |
9ebbca7d GK |
6627 | (set (match_dup 4) |
6628 | (compare:CC (match_dup 0) | |
6629 | (const_int 0)))] | |
6630 | "") | |
6631 | ||
6632 | (define_expand "lshrdi3" | |
266eb58a DE |
6633 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6634 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6635 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6636 | "TARGET_POWERPC64 || TARGET_POWER" | |
6637 | " | |
6638 | { | |
6639 | if (TARGET_POWERPC64) | |
6640 | ; | |
6641 | else if (TARGET_POWER) | |
6642 | { | |
6643 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6644 | DONE; | |
6645 | } | |
6646 | else | |
6647 | FAIL; | |
6648 | }") | |
6649 | ||
e2c953b6 | 6650 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6651 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6652 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6653 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6654 | "TARGET_POWERPC64" | |
a66078ee | 6655 | "srd%I2 %0,%1,%H2") |
266eb58a | 6656 | |
e2c953b6 | 6657 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6658 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6659 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6660 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6661 | (const_int 0))) |
9ebbca7d | 6662 | (clobber (match_scratch:DI 3 "=r,r"))] |
29ae5b89 | 6663 | "TARGET_POWERPC64" |
9ebbca7d GK |
6664 | "@ |
6665 | srd%I2. %3,%1,%H2 | |
6666 | #" | |
6667 | [(set_attr "type" "delayed_compare") | |
6668 | (set_attr "length" "4,8")]) | |
6669 | ||
6670 | (define_split | |
6671 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6672 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6673 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6674 | (const_int 0))) | |
6675 | (clobber (match_scratch:DI 3 ""))] | |
6676 | "TARGET_POWERPC64 && reload_completed" | |
6677 | [(set (match_dup 3) | |
6678 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6679 | (set (match_dup 0) | |
6680 | (compare:CC (match_dup 3) | |
6681 | (const_int 0)))] | |
6682 | "") | |
266eb58a | 6683 | |
e2c953b6 | 6684 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6685 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6686 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6687 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6688 | (const_int 0))) |
9ebbca7d | 6689 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 JL |
6690 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
6691 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6692 | "@ |
6693 | srd%I2. %0,%1,%H2 | |
6694 | #" | |
6695 | [(set_attr "type" "delayed_compare") | |
6696 | (set_attr "length" "4,8")]) | |
6697 | ||
6698 | (define_split | |
6699 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6700 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6701 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6702 | (const_int 0))) | |
6703 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6704 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6705 | "TARGET_POWERPC64 && reload_completed" | |
6706 | [(set (match_dup 0) | |
6707 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6708 | (set (match_dup 3) | |
6709 | (compare:CC (match_dup 0) | |
6710 | (const_int 0)))] | |
6711 | "") | |
266eb58a DE |
6712 | |
6713 | (define_expand "ashrdi3" | |
6714 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6715 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6716 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6717 | "TARGET_POWERPC64 || TARGET_POWER" | |
6718 | " | |
6719 | { | |
6720 | if (TARGET_POWERPC64) | |
6721 | ; | |
6722 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6723 | { | |
6724 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6725 | DONE; | |
6726 | } | |
6727 | else | |
6728 | FAIL; | |
6729 | }") | |
6730 | ||
e2c953b6 | 6731 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
6732 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6733 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6734 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6735 | "TARGET_POWERPC64" | |
375490e0 | 6736 | "srad%I2 %0,%1,%H2") |
266eb58a | 6737 | |
e2c953b6 | 6738 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
6739 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6740 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6741 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6742 | (const_int 0))) |
9ebbca7d | 6743 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6744 | "TARGET_POWERPC64" |
9ebbca7d GK |
6745 | "@ |
6746 | srad%I2. %3,%1,%H2 | |
6747 | #" | |
6748 | [(set_attr "type" "delayed_compare") | |
6749 | (set_attr "length" "4,8")]) | |
6750 | ||
6751 | (define_split | |
6752 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6753 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6754 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6755 | (const_int 0))) | |
6756 | (clobber (match_scratch:DI 3 ""))] | |
6757 | "TARGET_POWERPC64 && reload_completed" | |
6758 | [(set (match_dup 3) | |
6759 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6760 | (set (match_dup 0) | |
6761 | (compare:CC (match_dup 3) | |
6762 | (const_int 0)))] | |
6763 | "") | |
266eb58a | 6764 | |
e2c953b6 | 6765 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
6766 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6767 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6768 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6769 | (const_int 0))) |
9ebbca7d | 6770 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6771 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6772 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6773 | "@ |
6774 | srad%I2. %0,%1,%H2 | |
6775 | #" | |
6776 | [(set_attr "type" "delayed_compare") | |
6777 | (set_attr "length" "4,8")]) | |
6778 | ||
6779 | (define_split | |
6780 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6781 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6782 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6783 | (const_int 0))) | |
6784 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6785 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
6786 | "TARGET_POWERPC64 && reload_completed" | |
6787 | [(set (match_dup 0) | |
6788 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6789 | (set (match_dup 3) | |
6790 | (compare:CC (match_dup 0) | |
6791 | (const_int 0)))] | |
6792 | "") | |
815cdc52 | 6793 | |
29ae5b89 JL |
6794 | (define_insn "anddi3" |
6795 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") | |
6796 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
6797 | (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) | |
6798 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
6ffc8580 | 6799 | "TARGET_POWERPC64" |
266eb58a DE |
6800 | "@ |
6801 | and %0,%1,%2 | |
29ae5b89 JL |
6802 | rldic%B2 %0,%1,0,%S2 |
6803 | andi. %0,%1,%b2 | |
6804 | andis. %0,%1,%u2") | |
266eb58a | 6805 | |
a260abc9 | 6806 | (define_insn "*anddi3_internal2" |
6c873122 | 6807 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") |
9ebbca7d | 6808 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,") |
6c873122 | 6809 | (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) |
266eb58a | 6810 | (const_int 0))) |
9ebbca7d | 6811 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r")) |
6c873122 | 6812 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] |
6ffc8580 | 6813 | "TARGET_POWERPC64" |
266eb58a DE |
6814 | "@ |
6815 | and. %3,%1,%2 | |
6c873122 | 6816 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
6817 | andi. %3,%1,%b2 |
6818 | andis. %3,%1,%u2 | |
9ebbca7d GK |
6819 | # |
6820 | # | |
6821 | # | |
6822 | #" | |
6c873122 | 6823 | [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") |
9ebbca7d GK |
6824 | (set_attr "length" "4,4,4,4,8,8,8,8")]) |
6825 | ||
6826 | (define_split | |
6827 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6828 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6829 | (match_operand:DI 2 "and64_operand" "")) | |
6830 | (const_int 0))) | |
6831 | (clobber (match_scratch:DI 3 "")) | |
6832 | (clobber (match_scratch:CC 4 ""))] | |
6833 | "TARGET_POWERPC64 && reload_completed" | |
6834 | [(parallel [(set (match_dup 3) | |
6835 | (and:DI (match_dup 1) | |
6836 | (match_dup 2))) | |
6837 | (clobber (match_dup 4))]) | |
6838 | (set (match_dup 0) | |
6839 | (compare:CC (match_dup 3) | |
6840 | (const_int 0)))] | |
6841 | "") | |
266eb58a | 6842 | |
a260abc9 | 6843 | (define_insn "*anddi3_internal3" |
6c873122 | 6844 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") |
9ebbca7d | 6845 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") |
6c873122 | 6846 | (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) |
266eb58a | 6847 | (const_int 0))) |
9ebbca7d GK |
6848 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") |
6849 | (and:DI (match_dup 1) (match_dup 2))) | |
6c873122 | 6850 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] |
6ffc8580 | 6851 | "TARGET_POWERPC64" |
266eb58a DE |
6852 | "@ |
6853 | and. %0,%1,%2 | |
6c873122 | 6854 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
6855 | andi. %0,%1,%b2 |
6856 | andis. %0,%1,%u2 | |
9ebbca7d GK |
6857 | # |
6858 | # | |
6859 | # | |
6860 | #" | |
6c873122 | 6861 | [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") |
9ebbca7d GK |
6862 | (set_attr "length" "4,4,4,4,8,8,8,8")]) |
6863 | ||
6864 | (define_split | |
6865 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6866 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6867 | (match_operand:DI 2 "and64_operand" "")) | |
6868 | (const_int 0))) | |
6869 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6870 | (and:DI (match_dup 1) (match_dup 2))) | |
6871 | (clobber (match_scratch:CC 4 ""))] | |
6872 | "TARGET_POWERPC64 && reload_completed" | |
6873 | [(parallel [(set (match_dup 0) | |
6874 | (and:DI (match_dup 1) (match_dup 2))) | |
6875 | (clobber (match_dup 4))]) | |
6876 | (set (match_dup 3) | |
6877 | (compare:CC (match_dup 0) | |
6878 | (const_int 0)))] | |
6879 | "") | |
266eb58a | 6880 | |
a260abc9 | 6881 | (define_expand "iordi3" |
266eb58a | 6882 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 6883 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 6884 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 6885 | "TARGET_POWERPC64" |
266eb58a DE |
6886 | " |
6887 | { | |
dfbdccdb | 6888 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 6889 | { |
dfbdccdb | 6890 | HOST_WIDE_INT value; |
677a9668 | 6891 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 6892 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 6893 | |
dfbdccdb GK |
6894 | if (GET_CODE (operands[2]) == CONST_INT) |
6895 | { | |
6896 | value = INTVAL (operands[2]); | |
6897 | emit_insn (gen_iordi3 (tmp, operands[1], | |
6898 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
6899 | } | |
e2c953b6 | 6900 | else |
dfbdccdb GK |
6901 | { |
6902 | value = CONST_DOUBLE_LOW (operands[2]); | |
6903 | emit_insn (gen_iordi3 (tmp, operands[1], | |
6904 | immed_double_const (value | |
6905 | & (~ (HOST_WIDE_INT) 0xffff), | |
6906 | 0, DImode))); | |
6907 | } | |
e2c953b6 | 6908 | |
9ebbca7d GK |
6909 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
6910 | DONE; | |
6911 | } | |
266eb58a DE |
6912 | }") |
6913 | ||
a260abc9 DE |
6914 | (define_expand "xordi3" |
6915 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6916 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 6917 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
6918 | "TARGET_POWERPC64" |
6919 | " | |
6920 | { | |
dfbdccdb | 6921 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 6922 | { |
dfbdccdb | 6923 | HOST_WIDE_INT value; |
677a9668 | 6924 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
6925 | ? operands[0] : gen_reg_rtx (DImode)); |
6926 | ||
dfbdccdb GK |
6927 | if (GET_CODE (operands[2]) == CONST_INT) |
6928 | { | |
6929 | value = INTVAL (operands[2]); | |
6930 | emit_insn (gen_xordi3 (tmp, operands[1], | |
6931 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
6932 | } | |
e2c953b6 | 6933 | else |
dfbdccdb GK |
6934 | { |
6935 | value = CONST_DOUBLE_LOW (operands[2]); | |
6936 | emit_insn (gen_xordi3 (tmp, operands[1], | |
6937 | immed_double_const (value | |
6938 | & (~ (HOST_WIDE_INT) 0xffff), | |
6939 | 0, DImode))); | |
6940 | } | |
e2c953b6 | 6941 | |
9ebbca7d GK |
6942 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
6943 | DONE; | |
6944 | } | |
a260abc9 DE |
6945 | }") |
6946 | ||
dfbdccdb | 6947 | (define_insn "*booldi3_internal1" |
266eb58a | 6948 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 6949 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
6950 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
6951 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 6952 | "TARGET_POWERPC64" |
1fd4e8c1 | 6953 | "@ |
dfbdccdb GK |
6954 | %q3 %0,%1,%2 |
6955 | %q3i %0,%1,%b2 | |
6956 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 6957 | |
dfbdccdb | 6958 | (define_insn "*booldi3_internal2" |
9ebbca7d | 6959 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 6960 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
6961 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
6962 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
6963 | (const_int 0))) | |
9ebbca7d | 6964 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6965 | "TARGET_POWERPC64" |
9ebbca7d | 6966 | "@ |
dfbdccdb | 6967 | %q4. %3,%1,%2 |
9ebbca7d GK |
6968 | #" |
6969 | [(set_attr "type" "compare") | |
6970 | (set_attr "length" "4,8")]) | |
6971 | ||
6972 | (define_split | |
6973 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
6974 | (compare:CC (match_operator:DI 4 "boolean_operator" |
6975 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6976 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
6977 | (const_int 0))) | |
9ebbca7d GK |
6978 | (clobber (match_scratch:DI 3 ""))] |
6979 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 6980 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
6981 | (set (match_dup 0) |
6982 | (compare:CC (match_dup 3) | |
6983 | (const_int 0)))] | |
6984 | "") | |
1fd4e8c1 | 6985 | |
dfbdccdb | 6986 | (define_insn "*booldi3_internal3" |
9ebbca7d | 6987 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
6988 | (compare:CC (match_operator:DI 4 "boolean_operator" |
6989 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6990 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
6991 | (const_int 0))) | |
9ebbca7d | 6992 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 6993 | (match_dup 4))] |
266eb58a | 6994 | "TARGET_POWERPC64" |
9ebbca7d | 6995 | "@ |
dfbdccdb | 6996 | %q4. %0,%1,%2 |
9ebbca7d GK |
6997 | #" |
6998 | [(set_attr "type" "compare") | |
6999 | (set_attr "length" "4,8")]) | |
7000 | ||
7001 | (define_split | |
dfbdccdb GK |
7002 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7003 | (compare:CC (match_operator:DI 4 "boolean_operator" | |
7004 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7005 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7006 | (const_int 0))) | |
7007 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
7008 | (match_dup 4))] | |
9ebbca7d | 7009 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7010 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7011 | (set (match_dup 3) |
7012 | (compare:CC (match_dup 0) | |
7013 | (const_int 0)))] | |
7014 | "") | |
1fd4e8c1 | 7015 | |
dfbdccdb GK |
7016 | ;; Split an logical operation that we can't do in one insn into two insns, |
7017 | ;; each of which does one 16-bit part. This is used by combine. | |
266eb58a DE |
7018 | |
7019 | (define_split | |
7020 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7021 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7022 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7023 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7024 | "TARGET_POWERPC64" |
dfbdccdb GK |
7025 | [(set (match_dup 0) (match_dup 4)) |
7026 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7027 | " |
7028 | { | |
dfbdccdb GK |
7029 | rtx i3,i4; |
7030 | ||
9ebbca7d GK |
7031 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7032 | { | |
7033 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7034 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7035 | 0, DImode); |
dfbdccdb | 7036 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7037 | } |
7038 | else | |
7039 | { | |
dfbdccdb | 7040 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7041 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7042 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7043 | } |
dfbdccdb GK |
7044 | operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, |
7045 | operands[1], i3); | |
7046 | operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, | |
7047 | operands[0], i4); | |
1fd4e8c1 RK |
7048 | }") |
7049 | ||
dfbdccdb | 7050 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7051 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7052 | (match_operator:DI 3 "boolean_operator" |
7053 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7054 | (match_operand:DI 2 "logical_operand" "r")]))] | |
a473029f | 7055 | "TARGET_POWERPC64" |
1d328b19 | 7056 | "%q3 %0,%2,%1") |
a473029f | 7057 | |
dfbdccdb | 7058 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7059 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7060 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7061 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7062 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7063 | (const_int 0))) | |
9ebbca7d | 7064 | (clobber (match_scratch:DI 3 "=r,r"))] |
a473029f | 7065 | "TARGET_POWERPC64" |
9ebbca7d | 7066 | "@ |
1d328b19 | 7067 | %q4. %3,%2,%1 |
9ebbca7d GK |
7068 | #" |
7069 | [(set_attr "type" "compare") | |
7070 | (set_attr "length" "4,8")]) | |
7071 | ||
7072 | (define_split | |
7073 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
7074 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7075 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7076 | (match_operand:DI 2 "gpc_reg_operand" "r")]) | |
7077 | (const_int 0))) | |
9ebbca7d GK |
7078 | (clobber (match_scratch:DI 3 ""))] |
7079 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7080 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7081 | (set (match_dup 0) |
7082 | (compare:CC (match_dup 3) | |
7083 | (const_int 0)))] | |
7084 | "") | |
a473029f | 7085 | |
dfbdccdb | 7086 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7087 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7088 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7089 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7090 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7091 | (const_int 0))) | |
9ebbca7d | 7092 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7093 | (match_dup 4))] |
a473029f | 7094 | "TARGET_POWERPC64" |
9ebbca7d | 7095 | "@ |
1d328b19 | 7096 | %q4. %0,%2,%1 |
9ebbca7d GK |
7097 | #" |
7098 | [(set_attr "type" "compare") | |
7099 | (set_attr "length" "4,8")]) | |
7100 | ||
7101 | (define_split | |
9ebbca7d | 7102 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7103 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7104 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7105 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7106 | (const_int 0))) | |
9ebbca7d | 7107 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7108 | (match_dup 4))] |
9ebbca7d | 7109 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7110 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7111 | (set (match_dup 3) |
7112 | (compare:CC (match_dup 0) | |
7113 | (const_int 0)))] | |
7114 | "") | |
266eb58a | 7115 | |
dfbdccdb | 7116 | (define_insn "*boolccdi3_internal1" |
a473029f | 7117 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7118 | (match_operator:DI 3 "boolean_operator" |
7119 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7120 | (not:DI (match_operand:DI 2 "logical_operand" "r"))]))] | |
a473029f | 7121 | "TARGET_POWERPC64" |
dfbdccdb | 7122 | "%q3 %0,%1,%2") |
a473029f | 7123 | |
dfbdccdb | 7124 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7125 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7126 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7127 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7128 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7129 | (const_int 0))) | |
9ebbca7d | 7130 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7131 | "TARGET_POWERPC64" |
9ebbca7d | 7132 | "@ |
dfbdccdb | 7133 | %q4. %3,%1,%2 |
9ebbca7d GK |
7134 | #" |
7135 | [(set_attr "type" "compare") | |
7136 | (set_attr "length" "4,8")]) | |
7137 | ||
7138 | (define_split | |
7139 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
7140 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7141 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7142 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]) | |
7143 | (const_int 0))) | |
9ebbca7d GK |
7144 | (clobber (match_scratch:DI 3 ""))] |
7145 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7146 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7147 | (set (match_dup 0) |
7148 | (compare:CC (match_dup 3) | |
7149 | (const_int 0)))] | |
7150 | "") | |
266eb58a | 7151 | |
dfbdccdb | 7152 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7153 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7154 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7155 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7156 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7157 | (const_int 0))) | |
9ebbca7d | 7158 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7159 | (match_dup 4))] |
29ae5b89 | 7160 | "TARGET_POWERPC64" |
9ebbca7d | 7161 | "@ |
dfbdccdb | 7162 | %q4. %0,%1,%2 |
9ebbca7d GK |
7163 | #" |
7164 | [(set_attr "type" "compare") | |
7165 | (set_attr "length" "4,8")]) | |
7166 | ||
7167 | (define_split | |
9ebbca7d | 7168 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7169 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7170 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7171 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7172 | (const_int 0))) | |
9ebbca7d | 7173 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7174 | (match_dup 4))] |
9ebbca7d | 7175 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7176 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7177 | (set (match_dup 3) |
7178 | (compare:CC (match_dup 0) | |
7179 | (const_int 0)))] | |
7180 | "") | |
dfbdccdb | 7181 | \f |
1fd4e8c1 | 7182 | ;; Now define ways of moving data around. |
4697a36c MM |
7183 | |
7184 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7185 | ;; The output of this could be r0, but we make a very strong |
7186 | ;; preference for a base register because it will usually | |
7187 | ;; be needed there. | |
4697a36c | 7188 | (define_insn "elf_high" |
9ebbca7d | 7189 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7190 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7191 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7192 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7193 | |
7194 | (define_insn "elf_low" | |
9ebbca7d GK |
7195 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7196 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7197 | (match_operand 2 "" "")))] |
0ad91047 | 7198 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7199 | "@ |
7200 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7201 | {ai|addic} %0,%1,%K2") |
4697a36c | 7202 | |
ee890fe2 SS |
7203 | ;; Mach-O PIC trickery. |
7204 | (define_insn "macho_high" | |
7205 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
7206 | (high:SI (match_operand 1 "" "")))] | |
7207 | "TARGET_MACHO && ! TARGET_64BIT" | |
7208 | "{liu|lis} %0,ha16(%1)") | |
7209 | ||
7210 | (define_insn "macho_low" | |
7211 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
7212 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
7213 | (match_operand 2 "" "")))] | |
7214 | "TARGET_MACHO && ! TARGET_64BIT" | |
7215 | "@ | |
7216 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
7217 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
7218 | ||
766a866c MM |
7219 | ;; Set up a register with a value from the GOT table |
7220 | ||
7221 | (define_expand "movsi_got" | |
52d3af72 | 7222 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d GK |
7223 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
7224 | (match_dup 2)] 8))] | |
58307bcd | 7225 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
7226 | " |
7227 | { | |
38c1f2d7 MM |
7228 | if (GET_CODE (operands[1]) == CONST) |
7229 | { | |
7230 | rtx offset = const0_rtx; | |
7231 | HOST_WIDE_INT value; | |
7232 | ||
7233 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7234 | value = INTVAL (offset); | |
7235 | if (value != 0) | |
7236 | { | |
677a9668 | 7237 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7238 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7239 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7240 | DONE; | |
7241 | } | |
7242 | } | |
7243 | ||
c4c40373 | 7244 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7245 | }") |
7246 | ||
84f414bc | 7247 | (define_insn "*movsi_got_internal" |
52d3af72 | 7248 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7249 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7250 | (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] | |
c81bebd7 | 7251 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
7252 | "{l|lwz} %0,%a1@got(%2)" |
7253 | [(set_attr "type" "load")]) | |
7254 | ||
b22b9b3e JL |
7255 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7256 | ;; didn't get allocated to a hard register. | |
7257 | (define_split | |
52d3af72 | 7258 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7259 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7260 | (match_operand:SI 2 "memory_operand" "m")] 8))] | |
b22b9b3e JL |
7261 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
7262 | && flag_pic == 1 | |
7263 | && (reload_in_progress || reload_completed)" | |
7264 | [(set (match_dup 0) (match_dup 2)) | |
9ebbca7d | 7265 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))] |
b22b9b3e JL |
7266 | "") |
7267 | ||
1fd4e8c1 RK |
7268 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7269 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7270 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7271 | ;; integers in the TOC. | |
7272 | (define_expand "movsi" | |
7273 | [(set (match_operand:SI 0 "general_operand" "") | |
7274 | (match_operand:SI 1 "any_operand" ""))] | |
7275 | "" | |
fb4d4348 | 7276 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7277 | |
ee890fe2 SS |
7278 | (define_insn "movsi_low" |
7279 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
7280 | (mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "b") | |
7281 | (match_operand 2 "" ""))))] | |
7282 | "TARGET_MACHO && ! TARGET_64BIT" | |
7283 | "{l|lwz} %0,lo16(%2)(%1)" | |
7284 | [(set_attr "type" "load") | |
7285 | (set_attr "length" "4")]) | |
7286 | ||
acad7ed3 | 7287 | (define_insn "*movsi_internal1" |
a260abc9 | 7288 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h") |
9615f239 | 7289 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))] |
19d5775a RK |
7290 | "gpc_reg_operand (operands[0], SImode) |
7291 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7292 | "@ |
deb9225a | 7293 | mr %0,%1 |
b9442c72 | 7294 | {cal|la} %0,%a1 |
ca7f5001 RK |
7295 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7296 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7297 | {lil|li} %0,%1 |
802a0058 | 7298 | {liu|lis} %0,%v1 |
beaec479 | 7299 | # |
aee86b38 | 7300 | {cal|la} %0,%a1 |
1fd4e8c1 | 7301 | mf%1 %0 |
5c23c401 | 7302 | mt%0 %1 |
e76e75bb RK |
7303 | mt%0 %1 |
7304 | cror 0,0,0" | |
a260abc9 DE |
7305 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*") |
7306 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")]) | |
1fd4e8c1 | 7307 | |
77fa0940 RK |
7308 | ;; Split a load of a large constant into the appropriate two-insn |
7309 | ;; sequence. | |
7310 | ||
7311 | (define_split | |
7312 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7313 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7314 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7315 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7316 | [(set (match_dup 0) | |
7317 | (match_dup 2)) | |
7318 | (set (match_dup 0) | |
7319 | (ior:SI (match_dup 0) | |
7320 | (match_dup 3)))] | |
7321 | " | |
7322 | { | |
5f59ecb7 | 7323 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 7324 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
77fa0940 RK |
7325 | }") |
7326 | ||
acad7ed3 | 7327 | (define_insn "*movsi_internal2" |
9ebbca7d GK |
7328 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
7329 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 7330 | (const_int 0))) |
9ebbca7d | 7331 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
0ad91047 | 7332 | "! TARGET_POWERPC64" |
9ebbca7d GK |
7333 | "@ |
7334 | mr. %0,%1 | |
7335 | #" | |
7336 | [(set_attr "type" "compare") | |
7337 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 7338 | \f |
9ebbca7d GK |
7339 | (define_split |
7340 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7341 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7342 | (const_int 0))) | |
7343 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
7344 | "! TARGET_POWERPC64 && reload_completed" | |
7345 | [(set (match_dup 0) (match_dup 1)) | |
7346 | (set (match_dup 2) | |
7347 | (compare:CC (match_dup 0) | |
7348 | (const_int 0)))] | |
7349 | "") | |
7350 | ||
1fd4e8c1 RK |
7351 | (define_expand "movhi" |
7352 | [(set (match_operand:HI 0 "general_operand" "") | |
7353 | (match_operand:HI 1 "any_operand" ""))] | |
7354 | "" | |
fb4d4348 | 7355 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 RK |
7356 | |
7357 | (define_insn "" | |
fb81d7ce RK |
7358 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7359 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7360 | "gpc_reg_operand (operands[0], HImode) |
7361 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7362 | "@ |
deb9225a | 7363 | mr %0,%1 |
1fd4e8c1 RK |
7364 | lhz%U1%X1 %0,%1 |
7365 | sth%U0%X0 %1,%0 | |
19d5775a | 7366 | {lil|li} %0,%w1 |
1fd4e8c1 | 7367 | mf%1 %0 |
e76e75bb | 7368 | mt%0 %1 |
fb81d7ce | 7369 | mt%0 %1 |
e76e75bb | 7370 | cror 0,0,0" |
b7ff3d82 | 7371 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7372 | |
7373 | (define_expand "movqi" | |
7374 | [(set (match_operand:QI 0 "general_operand" "") | |
7375 | (match_operand:QI 1 "any_operand" ""))] | |
7376 | "" | |
fb4d4348 | 7377 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 RK |
7378 | |
7379 | (define_insn "" | |
fb81d7ce RK |
7380 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7381 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7382 | "gpc_reg_operand (operands[0], QImode) |
7383 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7384 | "@ |
deb9225a | 7385 | mr %0,%1 |
1fd4e8c1 RK |
7386 | lbz%U1%X1 %0,%1 |
7387 | stb%U0%X0 %1,%0 | |
19d5775a | 7388 | {lil|li} %0,%1 |
1fd4e8c1 | 7389 | mf%1 %0 |
e76e75bb | 7390 | mt%0 %1 |
fb81d7ce | 7391 | mt%0 %1 |
e76e75bb | 7392 | cror 0,0,0" |
b7ff3d82 | 7393 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7394 | \f |
7395 | ;; Here is how to move condition codes around. When we store CC data in | |
7396 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7397 | ;; This lets us not shift in the most common case of CR0. | |
7398 | (define_expand "movcc" | |
7399 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7400 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7401 | "" | |
7402 | "") | |
7403 | ||
7404 | (define_insn "" | |
7405 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") | |
7406 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
7407 | "register_operand (operands[0], CCmode) | |
7408 | || register_operand (operands[1], CCmode)" | |
7409 | "@ | |
7410 | mcrf %0,%1 | |
7411 | mtcrf 128,%1 | |
ca7f5001 | 7412 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 7413 | mfcr %0 |
ca7f5001 | 7414 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 7415 | mr %0,%1 |
ca7f5001 RK |
7416 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7417 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b7ff3d82 | 7418 | [(set_attr "type" "*,*,*,compare,*,*,load,store") |
b19003d8 | 7419 | (set_attr "length" "*,*,12,*,8,*,*,*")]) |
1fd4e8c1 | 7420 | \f |
e52e05ca MM |
7421 | ;; For floating-point, we normally deal with the floating-point registers |
7422 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7423 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7424 | ;; value is a simple constant or already in memory, we deal with this by | |
7425 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7426 | (define_expand "movsf" |
7427 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7428 | (match_operand:SF 1 "any_operand" ""))] | |
7429 | "" | |
fb4d4348 | 7430 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7431 | |
1fd4e8c1 | 7432 | (define_split |
cd2b37d9 | 7433 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7434 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7435 | "reload_completed |
5ae4759c MM |
7436 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7437 | || (GET_CODE (operands[0]) == SUBREG | |
7438 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7439 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7440 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7441 | " |
7442 | { | |
7443 | long l; | |
7444 | REAL_VALUE_TYPE rv; | |
7445 | ||
7446 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7447 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7448 | |
f99f88e0 DE |
7449 | if (! TARGET_POWERPC64) |
7450 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7451 | else | |
7452 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7453 | |
38886f37 | 7454 | operands[3] = GEN_INT (trunc_int_for_mode (l, SImode)); |
a260abc9 DE |
7455 | }") |
7456 | ||
c4c40373 | 7457 | (define_insn "*movsf_hardfloat" |
f99f88e0 DE |
7458 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") |
7459 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] | |
d14a6d05 MM |
7460 | "(gpc_reg_operand (operands[0], SFmode) |
7461 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" | |
1fd4e8c1 | 7462 | "@ |
f99f88e0 DE |
7463 | mr %0,%1 |
7464 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7465 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7466 | fmr %0,%1 |
7467 | lfs%U1%X1 %0,%1 | |
c4c40373 MM |
7468 | stfs%U0%X0 %1,%0 |
7469 | # | |
7470 | #" | |
f99f88e0 DE |
7471 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") |
7472 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7473 | |
c4c40373 MM |
7474 | (define_insn "*movsf_softfloat" |
7475 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") | |
9615f239 | 7476 | (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))] |
d14a6d05 MM |
7477 | "(gpc_reg_operand (operands[0], SFmode) |
7478 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" | |
7479 | "@ | |
7480 | mr %0,%1 | |
7481 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7482 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7483 | {lil|li} %0,%1 | |
802a0058 | 7484 | {liu|lis} %0,%v1 |
aee86b38 | 7485 | {cal|la} %0,%a1 |
c4c40373 MM |
7486 | # |
7487 | #" | |
7488 | [(set_attr "type" "*,load,store,*,*,*,*,*") | |
7489 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7490 | |
1fd4e8c1 RK |
7491 | \f |
7492 | (define_expand "movdf" | |
7493 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7494 | (match_operand:DF 1 "any_operand" ""))] | |
7495 | "" | |
fb4d4348 | 7496 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7497 | |
7498 | (define_split | |
cd2b37d9 | 7499 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7500 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7501 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7502 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7503 | || (GET_CODE (operands[0]) == SUBREG | |
7504 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7505 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7506 | [(set (match_dup 2) (match_dup 4)) |
7507 | (set (match_dup 3) (match_dup 1))] | |
7508 | " | |
7509 | { | |
5ae4759c | 7510 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7511 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7512 | ||
5ae4759c MM |
7513 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7514 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7515 | #if HOST_BITS_PER_WIDE_INT == 32 |
7516 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7517 | #else | |
7518 | operands[4] = GEN_INT (value >> 32); | |
7519 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
7520 | #endif | |
c4c40373 MM |
7521 | }") |
7522 | ||
c4c40373 MM |
7523 | (define_split |
7524 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7525 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7526 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7527 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7528 | || (GET_CODE (operands[0]) == SUBREG | |
7529 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7530 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7531 | [(set (match_dup 2) (match_dup 4)) |
7532 | (set (match_dup 3) (match_dup 5))] | |
7533 | " | |
7534 | { | |
5ae4759c | 7535 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7536 | long l[2]; |
7537 | REAL_VALUE_TYPE rv; | |
7538 | ||
7539 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7540 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7541 | ||
5ae4759c MM |
7542 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7543 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
38886f37 AO |
7544 | operands[4] = GEN_INT (trunc_int_for_mode (l[endian], SImode)); |
7545 | operands[5] = GEN_INT (trunc_int_for_mode (l[1 - endian], SImode)); | |
c4c40373 MM |
7546 | }") |
7547 | ||
efc08378 DE |
7548 | (define_split |
7549 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7550 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7551 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7552 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7553 | || (GET_CODE (operands[0]) == SUBREG | |
7554 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7555 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7556 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7557 | " |
a260abc9 DE |
7558 | { |
7559 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7560 | long l[2]; | |
7561 | REAL_VALUE_TYPE rv; | |
7562 | ||
7563 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7564 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7565 | ||
7566 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7567 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
7568 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); | |
7569 | }") | |
efc08378 | 7570 | |
4eae5fe1 | 7571 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7572 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7573 | ;; a non-offsettable memref, but also it is less efficient than loading |
7574 | ;; the constant into an FP register, since it will probably be used there. | |
7575 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7576 | ;; of handling these non-offsettable values. | |
c4c40373 | 7577 | (define_insn "*movdf_hardfloat32" |
000034eb DE |
7578 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
7579 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 7580 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
7581 | && (gpc_reg_operand (operands[0], DFmode) |
7582 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7583 | "* |
7584 | { | |
7585 | switch (which_alternative) | |
7586 | { | |
a260abc9 | 7587 | default: |
a6c2a102 | 7588 | abort (); |
e7113111 RK |
7589 | case 0: |
7590 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
7591 | the first register operand 0 is the same as the second register |
7592 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 7593 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 7594 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 7595 | else |
deb9225a | 7596 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 7597 | case 1: |
2b97222d DE |
7598 | if (offsettable_memref_p (operands[1]) |
7599 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
7600 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
7601 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
7602 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
7603 | { |
7604 | /* If the low-address word is used in the address, we must load | |
7605 | it last. Otherwise, load it first. Note that we cannot have | |
7606 | auto-increment in that case since the address register is | |
7607 | known to be dead. */ | |
7608 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7609 | operands[1], 0)) | |
7610 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
7611 | else | |
7612 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7613 | } | |
e7113111 | 7614 | else |
000034eb DE |
7615 | { |
7616 | rtx addreg; | |
7617 | ||
000034eb DE |
7618 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
7619 | if (refers_to_regno_p (REGNO (operands[0]), | |
7620 | REGNO (operands[0]) + 1, | |
7621 | operands[1], 0)) | |
7622 | { | |
7623 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 7624 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 7625 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 7626 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
7627 | } |
7628 | else | |
7629 | { | |
2b97222d | 7630 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 7631 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7632 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
7633 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7634 | return \"\"; | |
7635 | } | |
7636 | } | |
e7113111 | 7637 | case 2: |
2b97222d DE |
7638 | if (offsettable_memref_p (operands[0]) |
7639 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
7640 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
7641 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
7642 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
7643 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
7644 | else | |
7645 | { | |
7646 | rtx addreg; | |
7647 | ||
000034eb | 7648 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 7649 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 7650 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7651 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
7652 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7653 | return \"\"; | |
7654 | } | |
e7113111 | 7655 | case 3: |
e7113111 | 7656 | case 4: |
e7113111 | 7657 | case 5: |
c4c40373 | 7658 | return \"#\"; |
e7113111 | 7659 | case 6: |
c4c40373 MM |
7660 | return \"fmr %0,%1\"; |
7661 | case 7: | |
7662 | return \"lfd%U1%X1 %0,%1\"; | |
7663 | case 8: | |
e7113111 RK |
7664 | return \"stfd%U0%X0 %1,%0\"; |
7665 | } | |
7666 | }" | |
c4c40373 | 7667 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
2f76d42c | 7668 | (set_attr "length" "8,16,16,8,12,16,*,*,*")]) |
51b8fc2c | 7669 | |
c4c40373 | 7670 | (define_insn "*movdf_softfloat32" |
1427100a DE |
7671 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7672 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 7673 | "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
7674 | && (gpc_reg_operand (operands[0], DFmode) |
7675 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7676 | "* |
7677 | { | |
7678 | switch (which_alternative) | |
7679 | { | |
a260abc9 | 7680 | default: |
a6c2a102 | 7681 | abort (); |
dc4f83ca MM |
7682 | case 0: |
7683 | /* We normally copy the low-numbered register first. However, if | |
7684 | the first register operand 0 is the same as the second register of | |
7685 | operand 1, we must copy in the opposite order. */ | |
7686 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
7687 | return \"mr %L0,%L1\;mr %0,%1\"; | |
7688 | else | |
7689 | return \"mr %0,%1\;mr %L0,%L1\"; | |
7690 | case 1: | |
3cb999d8 DE |
7691 | /* If the low-address word is used in the address, we must load |
7692 | it last. Otherwise, load it first. Note that we cannot have | |
7693 | auto-increment in that case since the address register is | |
7694 | known to be dead. */ | |
dc4f83ca | 7695 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 7696 | operands[1], 0)) |
dc4f83ca MM |
7697 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
7698 | else | |
7699 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7700 | case 2: | |
7701 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
7702 | case 3: | |
c4c40373 MM |
7703 | case 4: |
7704 | case 5: | |
dc4f83ca MM |
7705 | return \"#\"; |
7706 | } | |
7707 | }" | |
c4c40373 MM |
7708 | [(set_attr "type" "*,load,store,*,*,*") |
7709 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 7710 | |
c4c40373 | 7711 | (define_insn "*movdf_hardfloat64" |
1427100a DE |
7712 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
7713 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 7714 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
7715 | && (gpc_reg_operand (operands[0], DFmode) |
7716 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 7717 | "@ |
3d5570cb RK |
7718 | mr %0,%1 |
7719 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 7720 | std%U0%X0 %1,%0 |
3d5570cb | 7721 | # |
c4c40373 MM |
7722 | # |
7723 | # | |
3d5570cb | 7724 | fmr %0,%1 |
f63184ac | 7725 | lfd%U1%X1 %0,%1 |
3d5570cb | 7726 | stfd%U0%X0 %1,%0" |
c4c40373 MM |
7727 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
7728 | (set_attr "length" "4,4,4,8,12,16,4,4,4")]) | |
dc4f83ca | 7729 | |
c4c40373 | 7730 | (define_insn "*movdf_softfloat64" |
1427100a DE |
7731 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7732 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 7733 | "TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
7734 | && (gpc_reg_operand (operands[0], DFmode) |
7735 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7736 | "@ |
7737 | mr %0,%1 | |
7738 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 7739 | std%U0%X0 %1,%0 |
c4c40373 MM |
7740 | # |
7741 | # | |
dc4f83ca | 7742 | #" |
c4c40373 MM |
7743 | [(set_attr "type" "*,load,store,*,*,*") |
7744 | (set_attr "length" "*,*,*,8,12,16")]) | |
1fd4e8c1 RK |
7745 | \f |
7746 | ;; Next come the multi-word integer load and store and the load and store | |
7747 | ;; multiple insns. | |
7748 | (define_expand "movdi" | |
7749 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 7750 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 7751 | "" |
fb4d4348 | 7752 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 7753 | |
acad7ed3 | 7754 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
7755 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
7756 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 7757 | "! TARGET_POWERPC64 |
4e74d8ec MM |
7758 | && (gpc_reg_operand (operands[0], DImode) |
7759 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
7760 | "* |
7761 | { | |
7762 | switch (which_alternative) | |
7763 | { | |
a260abc9 | 7764 | default: |
a6c2a102 | 7765 | abort (); |
1fd4e8c1 RK |
7766 | case 0: |
7767 | /* We normally copy the low-numbered register first. However, if | |
7768 | the first register operand 0 is the same as the second register of | |
7769 | operand 1, we must copy in the opposite order. */ | |
7770 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 7771 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 7772 | else |
deb9225a | 7773 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
7774 | case 1: |
7775 | /* If the low-address word is used in the address, we must load it | |
7776 | last. Otherwise, load it first. Note that we cannot have | |
7777 | auto-increment in that case since the address register is known to be | |
7778 | dead. */ | |
7779 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 7780 | operands[1], 0)) |
ca7f5001 | 7781 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 7782 | else |
ca7f5001 | 7783 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 7784 | case 2: |
ca7f5001 | 7785 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
7786 | case 3: |
7787 | return \"fmr %0,%1\"; | |
7788 | case 4: | |
7789 | return \"lfd%U1%X1 %0,%1\"; | |
7790 | case 5: | |
7791 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
7792 | case 6: |
7793 | case 7: | |
7794 | case 8: | |
7795 | case 9: | |
7796 | case 10: | |
7797 | return \"#\"; | |
1fd4e8c1 RK |
7798 | } |
7799 | }" | |
4e74d8ec MM |
7800 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
7801 | (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) | |
7802 | ||
7803 | (define_split | |
7804 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7805 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 7806 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
7807 | [(set (match_dup 2) (match_dup 4)) |
7808 | (set (match_dup 3) (match_dup 1))] | |
7809 | " | |
7810 | { | |
5f59ecb7 | 7811 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
7812 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
7813 | DImode); | |
7814 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
7815 | DImode); | |
75d39459 | 7816 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 7817 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 7818 | #else |
5f59ecb7 DE |
7819 | operands[4] = GEN_INT (value >> 32); |
7820 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
75d39459 | 7821 | #endif |
4e74d8ec MM |
7822 | }") |
7823 | ||
4e74d8ec MM |
7824 | (define_split |
7825 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7826 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 7827 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
7828 | [(set (match_dup 2) (match_dup 4)) |
7829 | (set (match_dup 3) (match_dup 5))] | |
7830 | " | |
7831 | { | |
bdaa0181 GK |
7832 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
7833 | DImode); | |
7834 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
7835 | DImode); | |
f6968f59 MM |
7836 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
7837 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
7838 | }") |
7839 | ||
acad7ed3 | 7840 | (define_insn "*movdi_internal64" |
e6ca2c17 | 7841 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") |
9615f239 | 7842 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 7843 | "TARGET_POWERPC64 |
4e74d8ec MM |
7844 | && (gpc_reg_operand (operands[0], DImode) |
7845 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 7846 | "@ |
3d5570cb RK |
7847 | mr %0,%1 |
7848 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 7849 | std%U0%X0 %1,%0 |
3d5570cb | 7850 | li %0,%1 |
802a0058 | 7851 | lis %0,%v1 |
e6ca2c17 | 7852 | # |
aee86b38 | 7853 | {cal|la} %0,%a1 |
3d5570cb RK |
7854 | fmr %0,%1 |
7855 | lfd%U1%X1 %0,%1 | |
7856 | stfd%U0%X0 %1,%0 | |
7857 | mf%1 %0 | |
08075ead DE |
7858 | mt%0 %1 |
7859 | cror 0,0,0" | |
b7ff3d82 | 7860 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
7861 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
7862 | ||
5f59ecb7 | 7863 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
7864 | (define_insn "" |
7865 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
7866 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
7867 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
7868 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
7869 | && num_insns_constant (operands[1], DImode) == 1" |
7870 | "* | |
7871 | { | |
7872 | return ((unsigned HOST_WIDE_INT) | |
7873 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
7874 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
7875 | }") | |
7876 | ||
a260abc9 DE |
7877 | ;; Generate all one-bits and clear left or right. |
7878 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
7879 | (define_split | |
7880 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7881 | (match_operand:DI 1 "mask64_operand" ""))] | |
7882 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
7883 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 7884 | (set (match_dup 0) |
a260abc9 DE |
7885 | (and:DI (rotate:DI (match_dup 0) |
7886 | (const_int 0)) | |
7887 | (match_dup 1)))] | |
7888 | "") | |
7889 | ||
7890 | ;; Split a load of a large constant into the appropriate five-instruction | |
7891 | ;; sequence. Handle anything in a constant number of insns. | |
7892 | ;; When non-easy constants can go in the TOC, this should use | |
7893 | ;; easy_fp_constant predicate. | |
7894 | (define_split | |
7895 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
7896 | (match_operand:DI 1 "const_int_operand" ""))] |
7897 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
7898 | [(set (match_dup 0) (match_dup 2)) | |
7899 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 7900 | " |
2bfcf297 DB |
7901 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
7902 | ||
7903 | if (tem == operands[0]) | |
7904 | DONE; | |
e8d791dd | 7905 | else |
2bfcf297 | 7906 | FAIL; |
5f59ecb7 | 7907 | }") |
e6ca2c17 | 7908 | |
5f59ecb7 DE |
7909 | (define_split |
7910 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
7911 | (match_operand:DI 1 "const_double_operand" ""))] |
7912 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
7913 | [(set (match_dup 0) (match_dup 2)) | |
7914 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 7915 | " |
2bfcf297 DB |
7916 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
7917 | ||
7918 | if (tem == operands[0]) | |
7919 | DONE; | |
7920 | else | |
7921 | FAIL; | |
e6ca2c17 | 7922 | }") |
08075ead | 7923 | |
2bfcf297 | 7924 | ;; Split a load of a large constant into the appropriate five-instruction |
acad7ed3 | 7925 | (define_insn "*movdi_internal2" |
9ebbca7d GK |
7926 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
7927 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
08075ead | 7928 | (const_int 0))) |
9ebbca7d | 7929 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
08075ead | 7930 | "TARGET_POWERPC64" |
9ebbca7d GK |
7931 | "@ |
7932 | mr. %0,%1 | |
7933 | #" | |
7934 | [(set_attr "type" "compare") | |
7935 | (set_attr "length" "4,8")]) | |
acad7ed3 | 7936 | |
9ebbca7d GK |
7937 | (define_split |
7938 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7939 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
7940 | (const_int 0))) | |
7941 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
7942 | "TARGET_POWERPC64 && reload_completed" | |
7943 | [(set (match_dup 0) (match_dup 1)) | |
7944 | (set (match_dup 2) | |
7945 | (compare:CC (match_dup 0) | |
7946 | (const_int 0)))] | |
7947 | "") | |
acad7ed3 | 7948 | \f |
1fd4e8c1 RK |
7949 | ;; TImode is similar, except that we usually want to compute the address into |
7950 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 7951 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
7952 | (define_expand "movti" |
7953 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
7954 | (match_operand:TI 1 "general_operand" "")) | |
7955 | (clobber (scratch:SI))])] | |
7e69e155 | 7956 | "TARGET_STRING || TARGET_POWERPC64" |
fb4d4348 | 7957 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
7958 | |
7959 | ;; We say that MQ is clobbered in the last alternative because the first | |
7960 | ;; alternative would never get used otherwise since it would need a reload | |
7961 | ;; while the 2nd alternative would not. We put memory cases first so they | |
7962 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
7963 | ;; giving the SCRATCH mq. | |
a260abc9 | 7964 | (define_insn "*movti_power" |
e1469d0d | 7965 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
7966 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
7967 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 7968 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 7969 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
7970 | "* |
7971 | { | |
7972 | switch (which_alternative) | |
7973 | { | |
dc4f83ca MM |
7974 | default: |
7975 | abort (); | |
7976 | ||
1fd4e8c1 | 7977 | case 0: |
ca7f5001 | 7978 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
7979 | |
7980 | case 1: | |
ca7f5001 | 7981 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
7982 | |
7983 | case 2: | |
7984 | /* Normally copy registers with lowest numbered register copied first. | |
7985 | But copy in the other order if the first register of the output | |
7986 | is the second, third, or fourth register in the input. */ | |
7987 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
7988 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 7989 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 7990 | else |
deb9225a | 7991 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
7992 | case 3: |
7993 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
7994 | fall through to generating four loads. */ | |
7995 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 7996 | return \"{lsi|lswi} %0,%P1,16\"; |
1fd4e8c1 RK |
7997 | /* ... fall through ... */ |
7998 | case 4: | |
7999 | /* If the address register is the same as the register for the lowest- | |
8000 | addressed word, load it last. Similarly for the next two words. | |
8001 | Otherwise load lowest address to highest. */ | |
8002 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8003 | operands[1], 0)) | |
ca7f5001 | 8004 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
8005 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
8006 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 8007 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
8008 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
8009 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 8010 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 8011 | else |
ca7f5001 | 8012 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
8013 | } |
8014 | }" | |
b7ff3d82 | 8015 | [(set_attr "type" "store,store,*,load,load") |
b19003d8 | 8016 | (set_attr "length" "*,16,16,*,16")]) |
51b8fc2c | 8017 | |
a260abc9 | 8018 | (define_insn "*movti_string" |
dc4f83ca MM |
8019 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") |
8020 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) | |
8021 | (clobber (match_scratch:SI 2 "=X,X,X"))] | |
0ad91047 | 8022 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8023 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8024 | "* | |
8025 | { | |
8026 | switch (which_alternative) | |
8027 | { | |
8028 | default: | |
8029 | abort (); | |
8030 | ||
8031 | case 0: | |
8032 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; | |
8033 | ||
8034 | case 1: | |
8035 | /* Normally copy registers with lowest numbered register copied first. | |
8036 | But copy in the other order if the first register of the output | |
8037 | is the second, third, or fourth register in the input. */ | |
8038 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8039 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
8040 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
8041 | else | |
8042 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
8043 | case 2: | |
8044 | /* If the address register is the same as the register for the lowest- | |
8045 | addressed word, load it last. Similarly for the next two words. | |
8046 | Otherwise load lowest address to highest. */ | |
8047 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8048 | operands[1], 0)) | |
8049 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
8050 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
8051 | REGNO (operands[0]) + 2, operands[1], 0)) | |
8052 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
8053 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
8054 | REGNO (operands[0]) + 3, operands[1], 0)) | |
8055 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
8056 | else | |
8057 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
8058 | } | |
8059 | }" | |
b7ff3d82 | 8060 | [(set_attr "type" "store,*,load") |
dc4f83ca MM |
8061 | (set_attr "length" "16,16,16")]) |
8062 | ||
a260abc9 | 8063 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
8064 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
8065 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
8066 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
8067 | || gpc_reg_operand (operands[1], TImode))" | |
8068 | "* | |
8069 | { | |
8070 | switch (which_alternative) | |
8071 | { | |
a260abc9 | 8072 | default: |
a6c2a102 | 8073 | abort (); |
51b8fc2c RK |
8074 | case 0: |
8075 | /* We normally copy the low-numbered register first. However, if | |
8076 | the first register operand 0 is the same as the second register of | |
8077 | operand 1, we must copy in the opposite order. */ | |
8078 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8079 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8080 | else | |
8081 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8082 | case 1: | |
8083 | /* If the low-address word is used in the address, we must load it | |
8084 | last. Otherwise, load it first. Note that we cannot have | |
8085 | auto-increment in that case since the address register is known to be | |
8086 | dead. */ | |
8087 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8088 | operands[1], 0)) |
51b8fc2c RK |
8089 | return \"ld %L0,%L1\;ld %0,%1\"; |
8090 | else | |
8091 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
8092 | case 2: | |
8093 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
8094 | } | |
8095 | }" | |
b7ff3d82 | 8096 | [(set_attr "type" "*,load,store") |
51b8fc2c | 8097 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
8098 | \f |
8099 | (define_expand "load_multiple" | |
2f622005 RK |
8100 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8101 | (match_operand:SI 1 "" "")) | |
8102 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 8103 | "TARGET_STRING" |
1fd4e8c1 RK |
8104 | " |
8105 | { | |
8106 | int regno; | |
8107 | int count; | |
792760b9 | 8108 | rtx op1; |
1fd4e8c1 RK |
8109 | int i; |
8110 | ||
8111 | /* Support only loading a constant number of fixed-point registers from | |
8112 | memory and only bother with this if more than two; the machine | |
8113 | doesn't support more than eight. */ | |
8114 | if (GET_CODE (operands[2]) != CONST_INT | |
8115 | || INTVAL (operands[2]) <= 2 | |
8116 | || INTVAL (operands[2]) > 8 | |
8117 | || GET_CODE (operands[1]) != MEM | |
8118 | || GET_CODE (operands[0]) != REG | |
8119 | || REGNO (operands[0]) >= 32) | |
8120 | FAIL; | |
8121 | ||
8122 | count = INTVAL (operands[2]); | |
8123 | regno = REGNO (operands[0]); | |
8124 | ||
39403d82 | 8125 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8126 | op1 = replace_equiv_address (operands[1], |
8127 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8128 | |
8129 | for (i = 0; i < count; i++) | |
8130 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8131 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
792760b9 | 8132 | adjust_address (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8133 | }") |
8134 | ||
8135 | (define_insn "" | |
8136 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 8137 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
52d3af72 | 8138 | (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] |
7e69e155 | 8139 | "TARGET_STRING" |
1fd4e8c1 RK |
8140 | "* |
8141 | { | |
8142 | /* We have to handle the case where the pseudo used to contain the address | |
e82ee4cc RK |
8143 | is assigned to one of the output registers. */ |
8144 | int i, j; | |
8145 | int words = XVECLEN (operands[0], 0); | |
8146 | rtx xop[10]; | |
8147 | ||
8148 | if (XVECLEN (operands[0], 0) == 1) | |
8149 | return \"{l|lwz} %1,0(%2)\"; | |
1fd4e8c1 | 8150 | |
e82ee4cc | 8151 | for (i = 0; i < words; i++) |
1fd4e8c1 RK |
8152 | if (refers_to_regno_p (REGNO (operands[1]) + i, |
8153 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
8154 | { | |
e82ee4cc RK |
8155 | if (i == words-1) |
8156 | { | |
8157 | xop[0] = operands[1]; | |
8158 | xop[1] = operands[2]; | |
8159 | xop[2] = GEN_INT (4 * (words-1)); | |
d89ddcfd | 8160 | output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); |
e82ee4cc RK |
8161 | return \"\"; |
8162 | } | |
8163 | else if (i == 0) | |
8164 | { | |
8165 | xop[0] = operands[1]; | |
39403d82 | 8166 | xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
e82ee4cc RK |
8167 | xop[2] = GEN_INT (4 * (words-1)); |
8168 | output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); | |
8169 | return \"\"; | |
8170 | } | |
8171 | else | |
8172 | { | |
8173 | for (j = 0; j < words; j++) | |
8174 | if (j != i) | |
8175 | { | |
39403d82 | 8176 | xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); |
e82ee4cc RK |
8177 | xop[1] = operands[2]; |
8178 | xop[2] = GEN_INT (j * 4); | |
8179 | output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); | |
8180 | } | |
8181 | xop[0] = operands[2]; | |
8182 | xop[1] = GEN_INT (i * 4); | |
8183 | output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); | |
8184 | return \"\"; | |
8185 | } | |
1fd4e8c1 RK |
8186 | } |
8187 | ||
e82ee4cc | 8188 | return \"{lsi|lswi} %1,%2,%N0\"; |
1fd4e8c1 | 8189 | }" |
b19003d8 | 8190 | [(set_attr "type" "load") |
e82ee4cc | 8191 | (set_attr "length" "32")]) |
b19003d8 | 8192 | |
b7ff3d82 | 8193 | \f |
1fd4e8c1 | 8194 | (define_expand "store_multiple" |
2f622005 RK |
8195 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8196 | (match_operand:SI 1 "" "")) | |
8197 | (clobber (scratch:SI)) | |
8198 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 8199 | "TARGET_STRING" |
1fd4e8c1 RK |
8200 | " |
8201 | { | |
8202 | int regno; | |
8203 | int count; | |
8204 | rtx to; | |
792760b9 | 8205 | rtx op0; |
1fd4e8c1 RK |
8206 | int i; |
8207 | ||
8208 | /* Support only storing a constant number of fixed-point registers to | |
8209 | memory and only bother with this if more than two; the machine | |
8210 | doesn't support more than eight. */ | |
8211 | if (GET_CODE (operands[2]) != CONST_INT | |
8212 | || INTVAL (operands[2]) <= 2 | |
8213 | || INTVAL (operands[2]) > 8 | |
8214 | || GET_CODE (operands[0]) != MEM | |
8215 | || GET_CODE (operands[1]) != REG | |
8216 | || REGNO (operands[1]) >= 32) | |
8217 | FAIL; | |
8218 | ||
8219 | count = INTVAL (operands[2]); | |
8220 | regno = REGNO (operands[1]); | |
8221 | ||
39403d82 | 8222 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8223 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8224 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8225 | |
8226 | XVECEXP (operands[3], 0, 0) | |
792760b9 | 8227 | = gen_rtx_SET (VOIDmode, op0, operands[1]); |
39403d82 | 8228 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8229 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8230 | |
8231 | for (i = 1; i < count; i++) | |
8232 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8233 | = gen_rtx_SET (VOIDmode, |
792760b9 | 8234 | adjust_address (op0, SImode, i * 4), |
c5c76735 | 8235 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8236 | }") |
8237 | ||
8238 | (define_insn "" | |
8239 | [(match_parallel 0 "store_multiple_operation" | |
8240 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8241 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8242 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8243 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8244 | "{stsi|stswi} %2,%P1,%O0" |
8245 | [(set_attr "type" "store")]) | |
d14a6d05 MM |
8246 | |
8247 | (define_insn "" | |
8248 | [(match_parallel 0 "store_multiple_operation" | |
52d3af72 | 8249 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
d14a6d05 MM |
8250 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
8251 | (clobber (match_scratch:SI 3 "X"))])] | |
0ad91047 | 8252 | "TARGET_STRING && ! TARGET_POWER" |
b7ff3d82 DE |
8253 | "{stsi|stswi} %2,%1,%O0" |
8254 | [(set_attr "type" "store")]) | |
7e69e155 MM |
8255 | |
8256 | \f | |
8257 | ;; String/block move insn. | |
8258 | ;; Argument 0 is the destination | |
8259 | ;; Argument 1 is the source | |
8260 | ;; Argument 2 is the length | |
8261 | ;; Argument 3 is the alignment | |
8262 | ||
8263 | (define_expand "movstrsi" | |
b6c9286a MM |
8264 | [(parallel [(set (match_operand:BLK 0 "" "") |
8265 | (match_operand:BLK 1 "" "")) | |
8266 | (use (match_operand:SI 2 "" "")) | |
8267 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
8268 | "" |
8269 | " | |
8270 | { | |
8271 | if (expand_block_move (operands)) | |
8272 | DONE; | |
8273 | else | |
8274 | FAIL; | |
8275 | }") | |
8276 | ||
8277 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8278 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
8279 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8280 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
8281 | [(parallel [(set (match_operand 0 "" "") |
8282 | (match_operand 1 "" "")) | |
8283 | (use (match_operand 2 "" "")) | |
8284 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
8285 | (clobber (reg:SI 5)) |
8286 | (clobber (reg:SI 6)) | |
8287 | (clobber (reg:SI 7)) | |
8288 | (clobber (reg:SI 8)) | |
8289 | (clobber (reg:SI 9)) | |
8290 | (clobber (reg:SI 10)) | |
8291 | (clobber (reg:SI 11)) | |
8292 | (clobber (reg:SI 12)) | |
3c67b673 | 8293 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8294 | "TARGET_STRING" |
8295 | "") | |
8296 | ||
8297 | (define_insn "" | |
52d3af72 DE |
8298 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8299 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8300 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8301 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8302 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8303 | (clobber (reg:SI 6)) |
8304 | (clobber (reg:SI 7)) | |
8305 | (clobber (reg:SI 8)) | |
8306 | (clobber (reg:SI 9)) | |
8307 | (clobber (reg:SI 10)) | |
8308 | (clobber (reg:SI 11)) | |
8309 | (clobber (reg:SI 12)) | |
3c67b673 | 8310 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 8311 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
8312 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8313 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8314 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8315 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8316 | && REGNO (operands[4]) == 5" |
8317 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8318 | [(set_attr "type" "load") |
8319 | (set_attr "length" "8")]) | |
7e69e155 MM |
8320 | |
8321 | (define_insn "" | |
52d3af72 DE |
8322 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8323 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8324 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8325 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8326 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8327 | (clobber (reg:SI 6)) |
8328 | (clobber (reg:SI 7)) | |
8329 | (clobber (reg:SI 8)) | |
8330 | (clobber (reg:SI 9)) | |
8331 | (clobber (reg:SI 10)) | |
8332 | (clobber (reg:SI 11)) | |
8333 | (clobber (reg:SI 12)) | |
3c67b673 | 8334 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8335 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
8336 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8337 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8338 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8339 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8340 | && REGNO (operands[4]) == 5" |
8341 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8342 | [(set_attr "type" "load") |
8343 | (set_attr "length" "8")]) | |
7e69e155 MM |
8344 | |
8345 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8346 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
8347 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8348 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
8349 | [(parallel [(set (match_operand 0 "" "") |
8350 | (match_operand 1 "" "")) | |
8351 | (use (match_operand 2 "" "")) | |
8352 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8353 | (clobber (reg:SI 5)) |
8354 | (clobber (reg:SI 6)) | |
7e69e155 MM |
8355 | (clobber (reg:SI 7)) |
8356 | (clobber (reg:SI 8)) | |
8357 | (clobber (reg:SI 9)) | |
8358 | (clobber (reg:SI 10)) | |
3c67b673 | 8359 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8360 | "TARGET_STRING" |
8361 | "") | |
8362 | ||
8363 | (define_insn "" | |
52d3af72 DE |
8364 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8365 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8366 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8367 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8368 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8369 | (clobber (reg:SI 6)) |
8370 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8371 | (clobber (reg:SI 8)) |
8372 | (clobber (reg:SI 9)) | |
8373 | (clobber (reg:SI 10)) | |
3c67b673 | 8374 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8375 | "TARGET_STRING && TARGET_POWER |
8376 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
8377 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8378 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8379 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8380 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8381 | [(set_attr "type" "load") |
8382 | (set_attr "length" "8")]) | |
7e69e155 MM |
8383 | |
8384 | (define_insn "" | |
52d3af72 DE |
8385 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8386 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8387 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8388 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8389 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8390 | (clobber (reg:SI 6)) |
8391 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8392 | (clobber (reg:SI 8)) |
8393 | (clobber (reg:SI 9)) | |
8394 | (clobber (reg:SI 10)) | |
3c67b673 | 8395 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8396 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8397 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
8398 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8399 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8400 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8401 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8402 | [(set_attr "type" "load") |
8403 | (set_attr "length" "8")]) | |
7e69e155 | 8404 | |
f9562f27 DE |
8405 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
8406 | ;; problems with TImode. | |
8407 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8408 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
8409 | [(parallel [(set (match_operand 0 "" "") |
8410 | (match_operand 1 "" "")) | |
8411 | (use (match_operand 2 "" "")) | |
8412 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8413 | (clobber (reg:SI 5)) |
8414 | (clobber (reg:SI 6)) | |
8415 | (clobber (reg:SI 7)) | |
8416 | (clobber (reg:SI 8)) | |
3c67b673 | 8417 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8418 | "TARGET_STRING" |
8419 | "") | |
8420 | ||
8421 | (define_insn "" | |
52d3af72 DE |
8422 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8423 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8424 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8425 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8426 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8427 | (clobber (reg:SI 6)) |
8428 | (clobber (reg:SI 7)) | |
8429 | (clobber (reg:SI 8)) | |
3c67b673 | 8430 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8431 | "TARGET_STRING && TARGET_POWER |
8432 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
8433 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8434 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8435 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8436 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8437 | [(set_attr "type" "load") |
8438 | (set_attr "length" "8")]) | |
7e69e155 MM |
8439 | |
8440 | (define_insn "" | |
52d3af72 DE |
8441 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8442 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8443 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8444 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8445 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8446 | (clobber (reg:SI 6)) |
8447 | (clobber (reg:SI 7)) | |
8448 | (clobber (reg:SI 8)) | |
3c67b673 | 8449 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8450 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8451 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
8452 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8453 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8454 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8455 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8456 | [(set_attr "type" "load") |
8457 | (set_attr "length" "8")]) | |
7e69e155 MM |
8458 | |
8459 | ;; Move up to 8 bytes at a time. | |
8460 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
8461 | [(parallel [(set (match_operand 0 "" "") |
8462 | (match_operand 1 "" "")) | |
8463 | (use (match_operand 2 "" "")) | |
8464 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8465 | (clobber (match_scratch:DI 4 "")) |
8466 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 8467 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
8468 | "") |
8469 | ||
8470 | (define_insn "" | |
52d3af72 DE |
8471 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8472 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8473 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8474 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8475 | (clobber (match_scratch:DI 4 "=&r")) | |
8476 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 8477 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
8478 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
8479 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8480 | [(set_attr "type" "load") |
8481 | (set_attr "length" "8")]) | |
7e69e155 MM |
8482 | |
8483 | (define_insn "" | |
52d3af72 DE |
8484 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8485 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8486 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8487 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8488 | (clobber (match_scratch:DI 4 "=&r")) | |
8489 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 8490 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 8491 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 8492 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8493 | [(set_attr "type" "load") |
8494 | (set_attr "length" "8")]) | |
7e69e155 MM |
8495 | |
8496 | ;; Move up to 4 bytes at a time. | |
8497 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
8498 | [(parallel [(set (match_operand 0 "" "") |
8499 | (match_operand 1 "" "")) | |
8500 | (use (match_operand 2 "" "")) | |
8501 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8502 | (clobber (match_scratch:SI 4 "")) |
8503 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
8504 | "TARGET_STRING" |
8505 | "") | |
8506 | ||
8507 | (define_insn "" | |
52d3af72 DE |
8508 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8509 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8510 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8511 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8512 | (clobber (match_scratch:SI 4 "=&r")) | |
8513 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
8514 | "TARGET_STRING && TARGET_POWER |
8515 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 8516 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8517 | [(set_attr "type" "load") |
8518 | (set_attr "length" "8")]) | |
7e69e155 MM |
8519 | |
8520 | (define_insn "" | |
52d3af72 DE |
8521 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8522 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8523 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8524 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8525 | (clobber (match_scratch:SI 4 "=&r")) | |
8526 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 8527 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8528 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
3c67b673 | 8529 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8530 | [(set_attr "type" "load") |
8531 | (set_attr "length" "8")]) | |
7e69e155 | 8532 | |
1fd4e8c1 | 8533 | \f |
7e69e155 | 8534 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
8535 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
8536 | ;; do cases where the increment is not the size of the object. | |
8537 | ;; | |
8538 | ;; In all these cases, we use operands 0 and 1 for the register being | |
8539 | ;; incremented because those are the operands that local-alloc will | |
8540 | ;; tie and these are the pair most likely to be tieable (and the ones | |
8541 | ;; that will benefit the most). | |
8542 | ||
38c1f2d7 | 8543 | (define_insn "*movdi_update1" |
51b8fc2c | 8544 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 8545 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
51b8fc2c RK |
8546 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))) |
8547 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
8548 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8549 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8550 | "@ |
8551 | ldux %3,%0,%2 | |
8552 | ldu %3,%2(%0)" | |
8553 | [(set_attr "type" "load")]) | |
8554 | ||
38c1f2d7 | 8555 | (define_insn "*movdi_update2" |
287f13ff RK |
8556 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
8557 | (sign_extend:DI | |
8558 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
8559 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
8560 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
8561 | (plus:DI (match_dup 1) (match_dup 2)))] | |
8562 | "TARGET_POWERPC64" | |
8563 | "lwaux %3,%0,%2" | |
8564 | [(set_attr "type" "load")]) | |
8565 | ||
4697a36c | 8566 | (define_insn "movdi_update" |
51b8fc2c RK |
8567 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
8568 | (match_operand:DI 2 "reg_or_short_operand" "r,I"))) | |
8569 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) | |
8570 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
8571 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8572 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8573 | "@ |
8574 | stdux %3,%0,%2 | |
b7ff3d82 DE |
8575 | stdu %3,%2(%0)" |
8576 | [(set_attr "type" "store")]) | |
51b8fc2c | 8577 | |
38c1f2d7 | 8578 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
8579 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
8580 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8581 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8582 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
8583 | (plus:SI (match_dup 1) (match_dup 2)))] |
8584 | "" | |
8585 | "@ | |
ca7f5001 RK |
8586 | {lux|lwzux} %3,%0,%2 |
8587 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 8588 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8589 | |
4697a36c | 8590 | (define_insn "movsi_update" |
cd2b37d9 | 8591 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8592 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8593 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
8594 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8595 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8596 | "TARGET_UPDATE" |
1fd4e8c1 | 8597 | "@ |
ca7f5001 | 8598 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
8599 | {stu|stwu} %3,%2(%0)" |
8600 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8601 | |
38c1f2d7 | 8602 | (define_insn "*movhi_update" |
cd2b37d9 RK |
8603 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
8604 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8605 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8606 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8607 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8608 | "TARGET_UPDATE" |
1fd4e8c1 | 8609 | "@ |
5f243543 RK |
8610 | lhzux %3,%0,%2 |
8611 | lhzu %3,%2(%0)" | |
cfb557c4 | 8612 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8613 | |
38c1f2d7 | 8614 | (define_insn "*movhi_update2" |
cd2b37d9 | 8615 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8616 | (zero_extend:SI |
cd2b37d9 | 8617 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8618 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8619 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8620 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8621 | "TARGET_UPDATE" |
1fd4e8c1 | 8622 | "@ |
5f243543 RK |
8623 | lhzux %3,%0,%2 |
8624 | lhzu %3,%2(%0)" | |
cfb557c4 | 8625 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8626 | |
38c1f2d7 | 8627 | (define_insn "*movhi_update3" |
cd2b37d9 | 8628 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8629 | (sign_extend:SI |
cd2b37d9 | 8630 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8631 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8632 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8633 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8634 | "TARGET_UPDATE" |
1fd4e8c1 | 8635 | "@ |
5f243543 RK |
8636 | lhaux %3,%0,%2 |
8637 | lhau %3,%2(%0)" | |
cfb557c4 | 8638 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8639 | |
38c1f2d7 | 8640 | (define_insn "*movhi_update4" |
cd2b37d9 | 8641 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8642 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8643 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
8644 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8645 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8646 | "TARGET_UPDATE" |
1fd4e8c1 | 8647 | "@ |
5f243543 | 8648 | sthux %3,%0,%2 |
b7ff3d82 DE |
8649 | sthu %3,%2(%0)" |
8650 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8651 | |
38c1f2d7 | 8652 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
8653 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
8654 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8655 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8656 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8657 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8658 | "TARGET_UPDATE" |
1fd4e8c1 | 8659 | "@ |
5f243543 RK |
8660 | lbzux %3,%0,%2 |
8661 | lbzu %3,%2(%0)" | |
cfb557c4 | 8662 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8663 | |
38c1f2d7 | 8664 | (define_insn "*movqi_update2" |
cd2b37d9 | 8665 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8666 | (zero_extend:SI |
cd2b37d9 | 8667 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8668 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8669 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8670 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8671 | "TARGET_UPDATE" |
1fd4e8c1 | 8672 | "@ |
5f243543 RK |
8673 | lbzux %3,%0,%2 |
8674 | lbzu %3,%2(%0)" | |
cfb557c4 | 8675 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8676 | |
38c1f2d7 | 8677 | (define_insn "*movqi_update3" |
cd2b37d9 | 8678 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8679 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8680 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
8681 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8682 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8683 | "TARGET_UPDATE" |
1fd4e8c1 | 8684 | "@ |
5f243543 | 8685 | stbux %3,%0,%2 |
b7ff3d82 DE |
8686 | stbu %3,%2(%0)" |
8687 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8688 | |
38c1f2d7 | 8689 | (define_insn "*movsf_update1" |
cd2b37d9 | 8690 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 8691 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8692 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8693 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8694 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8695 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8696 | "@ |
5f243543 RK |
8697 | lfsux %3,%0,%2 |
8698 | lfsu %3,%2(%0)" | |
cfb557c4 | 8699 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 8700 | |
38c1f2d7 | 8701 | (define_insn "*movsf_update2" |
cd2b37d9 | 8702 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8703 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8704 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
8705 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8706 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8707 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8708 | "@ |
85fff2f3 | 8709 | stfsux %3,%0,%2 |
b7ff3d82 DE |
8710 | stfsu %3,%2(%0)" |
8711 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 8712 | |
38c1f2d7 MM |
8713 | (define_insn "*movsf_update3" |
8714 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
8715 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
8716 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
8717 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
8718 | (plus:SI (match_dup 1) (match_dup 2)))] | |
8719 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
8720 | "@ | |
8721 | {lux|lwzux} %3,%0,%2 | |
8722 | {lu|lwzu} %3,%2(%0)" | |
8723 | [(set_attr "type" "load")]) | |
8724 | ||
8725 | (define_insn "*movsf_update4" | |
8726 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
8727 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
8728 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
8729 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
8730 | (plus:SI (match_dup 1) (match_dup 2)))] | |
8731 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
8732 | "@ | |
8733 | {stux|stwux} %3,%0,%2 | |
8734 | {stu|stwu} %3,%2(%0)" | |
8735 | [(set_attr "type" "store")]) | |
8736 | ||
8737 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
8738 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
8739 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8740 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8741 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8742 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8743 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8744 | "@ |
5f243543 RK |
8745 | lfdux %3,%0,%2 |
8746 | lfdu %3,%2(%0)" | |
cfb557c4 | 8747 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 8748 | |
38c1f2d7 | 8749 | (define_insn "*movdf_update2" |
cd2b37d9 | 8750 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8751 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8752 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
8753 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8754 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8755 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8756 | "@ |
5f243543 | 8757 | stfdux %3,%0,%2 |
b7ff3d82 DE |
8758 | stfdu %3,%2(%0)" |
8759 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
8760 | |
8761 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
8762 | ||
8763 | (define_peephole | |
8764 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8765 | (match_operand:DF 1 "memory_operand" "")) | |
8766 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
8767 | (match_operand:DF 3 "memory_operand" ""))] | |
8768 | "TARGET_POWER2 | |
d14a6d05 | 8769 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
8770 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
8771 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
8772 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
8773 | "lfq%U1%X1 %0,%1") | |
8774 | ||
8775 | (define_peephole | |
8776 | [(set (match_operand:DF 0 "memory_operand" "") | |
8777 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
8778 | (set (match_operand:DF 2 "memory_operand" "") | |
8779 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
8780 | "TARGET_POWER2 | |
d14a6d05 | 8781 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
8782 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
8783 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
8784 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
8785 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
8786 | \f |
8787 | ;; Next come insns related to the calling sequence. | |
8788 | ;; | |
8789 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 8790 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
8791 | |
8792 | (define_expand "allocate_stack" | |
52d3af72 | 8793 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
8794 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
8795 | (set (reg 1) | |
8796 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
8797 | "" |
8798 | " | |
4697a36c | 8799 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 8800 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 8801 | rtx neg_op0; |
1fd4e8c1 RK |
8802 | |
8803 | emit_move_insn (chain, stack_bot); | |
4697a36c | 8804 | |
a157febd GK |
8805 | /* Check stack bounds if necessary. */ |
8806 | if (current_function_limit_stack) | |
8807 | { | |
8808 | rtx available; | |
8809 | available = expand_binop (Pmode, sub_optab, | |
8810 | stack_pointer_rtx, stack_limit_rtx, | |
8811 | NULL_RTX, 1, OPTAB_WIDEN); | |
8812 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
8813 | } | |
8814 | ||
e9a25f70 JL |
8815 | if (GET_CODE (operands[1]) != CONST_INT |
8816 | || INTVAL (operands[1]) < -32767 | |
8817 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
8818 | { |
8819 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 8820 | if (TARGET_32BIT) |
e9a25f70 | 8821 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 8822 | else |
e9a25f70 | 8823 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
8824 | } |
8825 | else | |
e9a25f70 | 8826 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 8827 | |
38c1f2d7 MM |
8828 | if (TARGET_UPDATE) |
8829 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
8830 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 8831 | |
38c1f2d7 MM |
8832 | else |
8833 | { | |
8834 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
8835 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 8836 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 8837 | } |
e9a25f70 JL |
8838 | |
8839 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
8840 | DONE; |
8841 | }") | |
59257ff7 RK |
8842 | |
8843 | ;; These patterns say how to save and restore the stack pointer. We need not | |
8844 | ;; save the stack pointer at function level since we are careful to | |
8845 | ;; preserve the backchain. At block level, we have to restore the backchain | |
8846 | ;; when we restore the stack pointer. | |
8847 | ;; | |
8848 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
8849 | ;; backchain and restore both. Note that in the nonlocal case, the | |
8850 | ;; save area is a memory location. | |
8851 | ||
8852 | (define_expand "save_stack_function" | |
ff381587 MM |
8853 | [(match_operand 0 "any_operand" "") |
8854 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 8855 | "" |
ff381587 | 8856 | "DONE;") |
59257ff7 RK |
8857 | |
8858 | (define_expand "restore_stack_function" | |
ff381587 MM |
8859 | [(match_operand 0 "any_operand" "") |
8860 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 8861 | "" |
ff381587 | 8862 | "DONE;") |
59257ff7 RK |
8863 | |
8864 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
8865 | [(use (match_operand 0 "register_operand" "")) |
8866 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 8867 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 8868 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
8869 | "" |
8870 | " | |
dfdfa60f DE |
8871 | { |
8872 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 8873 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 8874 | }") |
59257ff7 RK |
8875 | |
8876 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
8877 | [(match_operand 0 "memory_operand" "") |
8878 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
8879 | "" |
8880 | " | |
8881 | { | |
a260abc9 | 8882 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
8883 | |
8884 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 8885 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
8886 | emit_move_insn (operand_subword (operands[0], 0, 0, |
8887 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
8888 | temp); |
8889 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
8890 | operands[1]); | |
59257ff7 RK |
8891 | DONE; |
8892 | }") | |
7e69e155 | 8893 | |
59257ff7 | 8894 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
8895 | [(match_operand 0 "register_operand" "") |
8896 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
8897 | "" |
8898 | " | |
8899 | { | |
a260abc9 | 8900 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
8901 | |
8902 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
8903 | emit_move_insn (temp, |
8904 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
8905 | emit_move_insn (operands[0], | |
c5c76735 JL |
8906 | operand_subword (operands[1], 1, 0, |
8907 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 8908 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
8909 | DONE; |
8910 | }") | |
9ebbca7d GK |
8911 | \f |
8912 | ;; TOC register handling. | |
b6c9286a | 8913 | |
9ebbca7d | 8914 | ;; Code to initialize the TOC register... |
f0f6a223 | 8915 | |
9ebbca7d GK |
8916 | (define_insn "load_toc_aix_si" |
8917 | [(set (match_operand:SI 0 "register_operand" "=r") | |
8918 | (unspec:SI [(const_int 0)] 7))] | |
2bfcf297 | 8919 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
8920 | "* |
8921 | { | |
9ebbca7d GK |
8922 | char buf[30]; |
8923 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 8924 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
8925 | operands[2] = gen_rtx_REG (Pmode, 2); |
8926 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
8927 | }" |
8928 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
8929 | |
8930 | (define_insn "load_toc_aix_di" | |
8931 | [(set (match_operand:DI 0 "register_operand" "=r") | |
8932 | (unspec:DI [(const_int 0)] 7))] | |
2bfcf297 | 8933 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
8934 | "* |
8935 | { | |
8936 | char buf[30]; | |
8937 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
2bfcf297 DB |
8938 | if (TARGET_ELF) |
8939 | strcat (buf, \"@toc\"); | |
a8a05998 | 8940 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
8941 | operands[2] = gen_rtx_REG (Pmode, 2); |
8942 | return \"ld %0,%1(%2)\"; | |
8943 | }" | |
8944 | [(set_attr "type" "load")]) | |
8945 | ||
8946 | (define_insn "load_toc_v4_pic_si" | |
8947 | [(set (match_operand:SI 0 "register_operand" "=l") | |
8948 | (unspec:SI [(const_int 0)] 7))] | |
8949 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1 | |
8950 | && TARGET_32BIT" | |
8951 | "bl _GLOBAL_OFFSET_TABLE_@local-4" | |
8952 | [(set_attr "type" "branch") | |
8953 | (set_attr "length" "4")]) | |
8954 | ||
9ebbca7d GK |
8955 | (define_insn "load_toc_v4_PIC_1" |
8956 | [(set (match_operand:SI 0 "register_operand" "=l") | |
8957 | (match_operand:SI 1 "immediate_operand" "s")) | |
8958 | (unspec [(match_dup 1)] 7)] | |
8959 | "TARGET_ELF && flag_pic == 2" | |
8960 | "bl %1\\n%1:" | |
8961 | [(set_attr "type" "branch") | |
8962 | (set_attr "length" "4")]) | |
8963 | ||
8964 | (define_insn "load_toc_v4_PIC_1b" | |
8965 | [(set (match_operand:SI 0 "register_operand" "=l") | |
8966 | (match_operand:SI 1 "immediate_operand" "s")) | |
8967 | (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] | |
8968 | "TARGET_ELF && flag_pic == 2" | |
8969 | "bl %1\\n\\t.long %2-%1+4\\n%1:" | |
8970 | [(set_attr "type" "branch") | |
8971 | (set_attr "length" "8")]) | |
8972 | ||
8973 | (define_insn "load_toc_v4_PIC_2" | |
8974 | [(set (match_operand:SI 0 "register_operand" "=r") | |
8975 | (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") | |
8976 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") | |
8977 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
8978 | "TARGET_ELF && flag_pic == 2" | |
8979 | "{l|lwz} %0,%2-%3(%1)" | |
8980 | [(set_attr "type" "load")]) | |
8981 | ||
ee890fe2 SS |
8982 | (define_insn "load_macho_picbase" |
8983 | [(set (match_operand:SI 0 "register_operand" "=l") | |
8984 | (unspec:SI [(const_int 0)] 15))] | |
8985 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" | |
8986 | "* | |
8987 | { | |
8988 | #if TARGET_MACHO | |
8989 | char *picbase = machopic_function_base_name (); | |
8990 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); | |
8991 | #endif | |
8992 | return \"bcl 20,31,%1\\n%1:\"; | |
8993 | }" | |
8994 | [(set_attr "type" "branch") | |
8995 | (set_attr "length" "4")]) | |
8996 | ||
9ebbca7d GK |
8997 | ;; If the TOC is shared over a translation unit, as happens with all |
8998 | ;; the kinds of PIC that we support, we need to restore the TOC | |
8999 | ;; pointer only when jumping over units of translation. | |
9000 | ||
9001 | (define_expand "builtin_setjmp_receiver" | |
9002 | [(use (label_ref (match_operand 0 "" "")))] | |
9003 | "((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1) | |
9004 | || (TARGET_TOC && TARGET_MINIMAL_TOC)" | |
9005 | " | |
9006 | { | |
9007 | rs6000_emit_load_toc_table (FALSE); | |
9008 | DONE; | |
9009 | }") | |
9010 | \f | |
9011 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
9012 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
9013 | ;; pointer to its TOC, and whose third word contains a value to place in the |
9014 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 9015 | ;; "trampoline" need not have any executable code. |
b6c9286a | 9016 | |
cccf3bdc DE |
9017 | (define_expand "call_indirect_aix32" |
9018 | [(set (match_dup 2) | |
9019 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
9020 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9021 | (reg:SI 2)) | |
9022 | (set (reg:SI 2) | |
9023 | (mem:SI (plus:SI (match_dup 0) | |
9024 | (const_int 4)))) | |
9025 | (set (reg:SI 11) | |
9026 | (mem:SI (plus:SI (match_dup 0) | |
9027 | (const_int 8)))) | |
9028 | (parallel [(call (mem:SI (match_dup 2)) | |
9029 | (match_operand 1 "" "")) | |
9030 | (use (reg:SI 2)) | |
9031 | (use (reg:SI 11)) | |
9032 | (set (reg:SI 2) | |
9033 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9034 | (clobber (scratch:SI))])] | |
9035 | "TARGET_32BIT" | |
9036 | " | |
9037 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9038 | |
cccf3bdc DE |
9039 | (define_expand "call_indirect_aix64" |
9040 | [(set (match_dup 2) | |
9041 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
9042 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9043 | (reg:DI 2)) | |
9044 | (set (reg:DI 2) | |
9045 | (mem:DI (plus:DI (match_dup 0) | |
9046 | (const_int 8)))) | |
9047 | (set (reg:DI 11) | |
9048 | (mem:DI (plus:DI (match_dup 0) | |
9049 | (const_int 16)))) | |
9050 | (parallel [(call (mem:SI (match_dup 2)) | |
9051 | (match_operand 1 "" "")) | |
9052 | (use (reg:DI 2)) | |
9053 | (use (reg:DI 11)) | |
9054 | (set (reg:DI 2) | |
9055 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9056 | (clobber (scratch:SI))])] | |
9057 | "TARGET_64BIT" | |
9058 | " | |
9059 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 9060 | |
cccf3bdc DE |
9061 | (define_expand "call_value_indirect_aix32" |
9062 | [(set (match_dup 3) | |
9063 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
9064 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9065 | (reg:SI 2)) | |
9066 | (set (reg:SI 2) | |
9067 | (mem:SI (plus:SI (match_dup 1) | |
9068 | (const_int 4)))) | |
9069 | (set (reg:SI 11) | |
9070 | (mem:SI (plus:SI (match_dup 1) | |
9071 | (const_int 8)))) | |
9072 | (parallel [(set (match_operand 0 "" "") | |
9073 | (call (mem:SI (match_dup 3)) | |
9074 | (match_operand 2 "" ""))) | |
9075 | (use (reg:SI 2)) | |
9076 | (use (reg:SI 11)) | |
9077 | (set (reg:SI 2) | |
9078 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9079 | (clobber (scratch:SI))])] | |
9080 | "TARGET_32BIT" | |
9081 | " | |
9082 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9083 | |
cccf3bdc DE |
9084 | (define_expand "call_value_indirect_aix64" |
9085 | [(set (match_dup 3) | |
9086 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
9087 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9088 | (reg:DI 2)) | |
9089 | (set (reg:DI 2) | |
9090 | (mem:DI (plus:DI (match_dup 1) | |
9091 | (const_int 8)))) | |
9092 | (set (reg:DI 11) | |
9093 | (mem:DI (plus:DI (match_dup 1) | |
9094 | (const_int 16)))) | |
9095 | (parallel [(set (match_operand 0 "" "") | |
9096 | (call (mem:SI (match_dup 3)) | |
9097 | (match_operand 2 "" ""))) | |
9098 | (use (reg:DI 2)) | |
9099 | (use (reg:DI 11)) | |
9100 | (set (reg:DI 2) | |
9101 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9102 | (clobber (scratch:SI))])] | |
9103 | "TARGET_64BIT" | |
9104 | " | |
9105 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 9106 | |
b6c9286a | 9107 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 9108 | (define_expand "call" |
a260abc9 | 9109 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 9110 | (match_operand 1 "" "")) |
4697a36c | 9111 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
9112 | (clobber (scratch:SI))])] |
9113 | "" | |
9114 | " | |
9115 | { | |
ee890fe2 SS |
9116 | #if TARGET_MACHO |
9117 | if (flag_pic) | |
9118 | operands[0] = machopic_indirect_call_target (operands[0]); | |
9119 | #endif | |
9120 | ||
1fd4e8c1 RK |
9121 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
9122 | abort (); | |
9123 | ||
9124 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 9125 | |
6a4cee5f MM |
9126 | if (GET_CODE (operands[0]) != SYMBOL_REF |
9127 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9128 | { |
6a4cee5f MM |
9129 | if (INTVAL (operands[2]) & CALL_LONG) |
9130 | operands[0] = rs6000_longcall_ref (operands[0]); | |
9131 | ||
cccf3bdc DE |
9132 | if (DEFAULT_ABI == ABI_V4 |
9133 | || DEFAULT_ABI == ABI_AIX_NODESC | |
ee890fe2 | 9134 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc DE |
9135 | || DEFAULT_ABI == ABI_SOLARIS) |
9136 | operands[0] = force_reg (Pmode, operands[0]); | |
1fd4e8c1 | 9137 | |
cccf3bdc DE |
9138 | else if (DEFAULT_ABI == ABI_AIX) |
9139 | { | |
9140 | /* AIX function pointers are really pointers to a three word | |
9141 | area. */ | |
9142 | emit_call_insn (TARGET_32BIT | |
9143 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
9144 | operands[0]), | |
9145 | operands[1]) | |
9146 | : gen_call_indirect_aix64 (force_reg (DImode, | |
9147 | operands[0]), | |
9148 | operands[1])); | |
9149 | DONE; | |
b6c9286a | 9150 | } |
cccf3bdc DE |
9151 | else |
9152 | abort (); | |
1fd4e8c1 RK |
9153 | } |
9154 | }") | |
9155 | ||
9156 | (define_expand "call_value" | |
9157 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 9158 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 9159 | (match_operand 2 "" ""))) |
4697a36c | 9160 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
9161 | (clobber (scratch:SI))])] |
9162 | "" | |
9163 | " | |
9164 | { | |
ee890fe2 SS |
9165 | #if TARGET_MACHO |
9166 | if (flag_pic) | |
9167 | operands[1] = machopic_indirect_call_target (operands[1]); | |
9168 | #endif | |
9169 | ||
1fd4e8c1 RK |
9170 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
9171 | abort (); | |
9172 | ||
9173 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 9174 | |
6a4cee5f MM |
9175 | if (GET_CODE (operands[1]) != SYMBOL_REF |
9176 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9177 | { |
6756293c | 9178 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
9179 | operands[1] = rs6000_longcall_ref (operands[1]); |
9180 | ||
cccf3bdc DE |
9181 | if (DEFAULT_ABI == ABI_V4 |
9182 | || DEFAULT_ABI == ABI_AIX_NODESC | |
ee890fe2 | 9183 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc DE |
9184 | || DEFAULT_ABI == ABI_SOLARIS) |
9185 | operands[0] = force_reg (Pmode, operands[0]); | |
1fd4e8c1 | 9186 | |
cccf3bdc DE |
9187 | else if (DEFAULT_ABI == ABI_AIX) |
9188 | { | |
9189 | /* AIX function pointers are really pointers to a three word | |
9190 | area. */ | |
9191 | emit_call_insn (TARGET_32BIT | |
9192 | ? gen_call_value_indirect_aix32 (operands[0], | |
9193 | force_reg (SImode, | |
9194 | operands[1]), | |
9195 | operands[2]) | |
9196 | : gen_call_value_indirect_aix64 (operands[0], | |
9197 | force_reg (DImode, | |
9198 | operands[1]), | |
9199 | operands[2])); | |
9200 | DONE; | |
b6c9286a | 9201 | } |
cccf3bdc DE |
9202 | else |
9203 | abort (); | |
1fd4e8c1 RK |
9204 | } |
9205 | }") | |
9206 | ||
04780ee7 | 9207 | ;; Call to function in current module. No TOC pointer reload needed. |
4697a36c MM |
9208 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9209 | ;; either the function was not prototyped, or it was prototyped as a | |
9210 | ;; variable argument function. It is > 0 if FP registers were passed | |
9211 | ;; and < 0 if they were not. | |
04780ee7 | 9212 | |
a260abc9 | 9213 | (define_insn "*call_local32" |
4697a36c MM |
9214 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
9215 | (match_operand 1 "" "g,g")) | |
9216 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9217 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 9218 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
9219 | "* |
9220 | { | |
6a4cee5f MM |
9221 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9222 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9223 | ||
9224 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9225 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 9226 | |
a226df46 | 9227 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 9228 | }" |
b7ff3d82 DE |
9229 | [(set_attr "type" "branch") |
9230 | (set_attr "length" "4,8")]) | |
04780ee7 | 9231 | |
a260abc9 DE |
9232 | (define_insn "*call_local64" |
9233 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
9234 | (match_operand 1 "" "g,g")) | |
9235 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9236 | (clobber (match_scratch:SI 3 "=l,l"))] | |
9237 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
9238 | "* | |
9239 | { | |
9240 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
9241 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9242 | ||
9243 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9244 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9245 | ||
9246 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
9247 | }" | |
9248 | [(set_attr "type" "branch") | |
9249 | (set_attr "length" "4,8")]) | |
9250 | ||
cccf3bdc | 9251 | (define_insn "*call_value_local32" |
a260abc9 DE |
9252 | [(set (match_operand 0 "" "=fg,fg") |
9253 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
9254 | (match_operand 2 "" "g,g"))) | |
9255 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9256 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9257 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
9258 | "* | |
9259 | { | |
9260 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9261 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9262 | ||
9263 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9264 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9265 | ||
9266 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9267 | }" | |
9268 | [(set_attr "type" "branch") | |
9269 | (set_attr "length" "4,8")]) | |
9270 | ||
9271 | ||
cccf3bdc | 9272 | (define_insn "*call_value_local64" |
a260abc9 DE |
9273 | [(set (match_operand 0 "" "=fg,fg") |
9274 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
9275 | (match_operand 2 "" "g,g"))) | |
9276 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9277 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9278 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
9279 | "* | |
9280 | { | |
9281 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9282 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9283 | ||
9284 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9285 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9286 | ||
9287 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9288 | }" | |
9289 | [(set_attr "type" "branch") | |
9290 | (set_attr "length" "4,8")]) | |
9291 | ||
04780ee7 | 9292 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 9293 | ;; pointer (r2) after the call unless this is System V. |
4697a36c MM |
9294 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9295 | ;; either the function was not prototyped, or it was prototyped as a | |
9296 | ;; variable argument function. It is > 0 if FP registers were passed | |
9297 | ;; and < 0 if they were not. | |
04780ee7 | 9298 | |
cccf3bdc DE |
9299 | (define_insn "*call_indirect_nonlocal_aix32" |
9300 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
9301 | (match_operand 1 "" "g")) | |
9302 | (use (reg:SI 2)) | |
9303 | (use (reg:SI 11)) | |
9304 | (set (reg:SI 2) | |
9305 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 9306 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
9307 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
9308 | "b%T0l\;{l|lwz} 2,20(1)" | |
9309 | [(set_attr "type" "jmpreg") | |
9310 | (set_attr "length" "8")]) | |
9311 | ||
a260abc9 | 9312 | (define_insn "*call_nonlocal_aix32" |
cccf3bdc DE |
9313 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s")) |
9314 | (match_operand 1 "" "g")) | |
9315 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9316 | (clobber (match_scratch:SI 3 "=l"))] | |
9317 | "TARGET_32BIT | |
9318 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 9319 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9320 | "bl %z0\;%." |
b7ff3d82 | 9321 | [(set_attr "type" "branch") |
cccf3bdc DE |
9322 | (set_attr "length" "8")]) |
9323 | ||
9324 | (define_insn "*call_indirect_nonlocal_aix64" | |
9325 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
9326 | (match_operand 1 "" "g")) | |
9327 | (use (reg:DI 2)) | |
9328 | (use (reg:DI 11)) | |
9329 | (set (reg:DI 2) | |
9330 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 9331 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
9332 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
9333 | "b%T0l\;ld 2,40(1)" | |
9334 | [(set_attr "type" "jmpreg") | |
9335 | (set_attr "length" "8")]) | |
59313e4e | 9336 | |
a260abc9 | 9337 | (define_insn "*call_nonlocal_aix64" |
cccf3bdc DE |
9338 | [(call (mem:SI (match_operand:DI 0 "call_operand" "s")) |
9339 | (match_operand 1 "" "g")) | |
9340 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9341 | (clobber (match_scratch:SI 3 "=l"))] | |
9ebbca7d GK |
9342 | "TARGET_64BIT |
9343 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 9344 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9345 | "bl %z0\;%." |
a260abc9 | 9346 | [(set_attr "type" "branch") |
cccf3bdc | 9347 | (set_attr "length" "8")]) |
7509c759 | 9348 | |
cccf3bdc DE |
9349 | (define_insn "*call_value_indirect_nonlocal_aix32" |
9350 | [(set (match_operand 0 "" "=fg") | |
9351 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) | |
9352 | (match_operand 2 "" "g"))) | |
9353 | (use (reg:SI 2)) | |
9354 | (use (reg:SI 11)) | |
9355 | (set (reg:SI 2) | |
9356 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9357 | (clobber (match_scratch:SI 3 "=l"))] | |
9358 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
9359 | "b%T1l\;{l|lwz} 2,20(1)" | |
9360 | [(set_attr "type" "jmpreg") | |
9361 | (set_attr "length" "8")]) | |
1fd4e8c1 | 9362 | |
cccf3bdc DE |
9363 | (define_insn "*call_value_nonlocal_aix32" |
9364 | [(set (match_operand 0 "" "=fg") | |
9365 | (call (mem:SI (match_operand:SI 1 "call_operand" "s")) | |
9366 | (match_operand 2 "" "g"))) | |
9367 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
9368 | (clobber (match_scratch:SI 4 "=l"))] | |
9369 | "TARGET_32BIT | |
9370 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 9371 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 9372 | "bl %z1\;%." |
b7ff3d82 | 9373 | [(set_attr "type" "branch") |
cccf3bdc | 9374 | (set_attr "length" "8")]) |
04780ee7 | 9375 | |
cccf3bdc DE |
9376 | (define_insn "*call_value_indirect_nonlocal_aix64" |
9377 | [(set (match_operand 0 "" "=fg") | |
9378 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) | |
9379 | (match_operand 2 "" "g"))) | |
9380 | (use (reg:DI 2)) | |
9381 | (use (reg:DI 11)) | |
9382 | (set (reg:DI 2) | |
9383 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9384 | (clobber (match_scratch:SI 3 "=l"))] | |
9385 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
9386 | "b%T1l\;ld 2,40(1)" | |
9387 | [(set_attr "type" "jmpreg") | |
9388 | (set_attr "length" "8")]) | |
9389 | ||
9390 | (define_insn "*call_value_nonlocal_aix64" | |
9391 | [(set (match_operand 0 "" "=fg") | |
9392 | (call (mem:SI (match_operand:DI 1 "call_operand" "s")) | |
9393 | (match_operand 2 "" "g"))) | |
9394 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
9395 | (clobber (match_scratch:SI 4 "=l"))] | |
9ebbca7d GK |
9396 | "TARGET_64BIT |
9397 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 9398 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
9399 | "bl %z1\;%." |
9400 | [(set_attr "type" "branch") | |
9401 | (set_attr "length" "8")]) | |
9402 | ||
9403 | ;; A function pointer under System V is just a normal pointer | |
9404 | ;; operands[0] is the function pointer | |
9405 | ;; operands[1] is the stack size to clean up | |
9406 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
9407 | ;; which indicates how to set cr1 | |
9408 | ||
9409 | (define_insn "*call_nonlocal_sysv" | |
9410 | [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s")) | |
9411 | (match_operand 1 "" "g,g,g,g")) | |
9412 | (use (match_operand:SI 2 "immediate_operand" "O,n,O,n")) | |
9413 | (clobber (match_scratch:SI 3 "=l,l,l,l"))] | |
9414 | "DEFAULT_ABI == ABI_AIX_NODESC | |
9415 | || DEFAULT_ABI == ABI_V4 | |
ee890fe2 | 9416 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc | 9417 | || DEFAULT_ABI == ABI_SOLARIS" |
911f679c MM |
9418 | "* |
9419 | { | |
cccf3bdc | 9420 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
6a4cee5f MM |
9421 | output_asm_insn (\"crxor 6,6,6\", operands); |
9422 | ||
cccf3bdc | 9423 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
6a4cee5f | 9424 | output_asm_insn (\"creqv 6,6,6\", operands); |
7509c759 | 9425 | |
cccf3bdc DE |
9426 | switch (which_alternative) |
9427 | { | |
9428 | default: | |
9429 | abort (); | |
9430 | case 0: | |
9431 | case 1: | |
9432 | return \"b%T0l\"; | |
9433 | case 2: | |
9434 | case 3: | |
9435 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; | |
9436 | } | |
b6c9286a | 9437 | }" |
cccf3bdc DE |
9438 | [(set_attr "type" "jmpreg,jmpreg,branch,branch") |
9439 | (set_attr "length" "4,8,4,8")]) | |
9440 | ||
9441 | (define_insn "*call_value_nonlocal_sysv" | |
9442 | [(set (match_operand 0 "" "=fg,fg,fg,fg") | |
9443 | (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s")) | |
9444 | (match_operand 2 "" "g,g,g,g"))) | |
9445 | (use (match_operand:SI 3 "immediate_operand" "O,n,O,n")) | |
9446 | (clobber (match_scratch:SI 4 "=l,l,l,l"))] | |
9447 | "DEFAULT_ABI == ABI_AIX_NODESC | |
9448 | || DEFAULT_ABI == ABI_V4 | |
ee890fe2 | 9449 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc | 9450 | || DEFAULT_ABI == ABI_SOLARIS" |
b6c9286a MM |
9451 | "* |
9452 | { | |
6a4cee5f MM |
9453 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
9454 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9455 | ||
9456 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9457 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 9458 | |
cccf3bdc DE |
9459 | switch (which_alternative) |
9460 | { | |
9461 | default: | |
9462 | abort (); | |
9463 | case 0: | |
9464 | case 1: | |
9465 | return \"b%T1l\"; | |
9466 | case 2: | |
9467 | case 3: | |
9468 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; | |
9469 | } | |
911f679c | 9470 | }" |
cccf3bdc DE |
9471 | [(set_attr "type" "jmpreg,jmpreg,branch,branch") |
9472 | (set_attr "length" "4,8,4,8")]) | |
e6f948e3 RK |
9473 | |
9474 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
9475 | (define_expand "untyped_call" |
9476 | [(parallel [(call (match_operand 0 "" "") | |
9477 | (const_int 0)) | |
9478 | (match_operand 1 "" "") | |
9479 | (match_operand 2 "" "")])] | |
9480 | "" | |
9481 | " | |
9482 | { | |
9483 | int i; | |
9484 | ||
7d70b8b2 | 9485 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
9486 | |
9487 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9488 | { | |
9489 | rtx set = XVECEXP (operands[2], 0, i); | |
9490 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9491 | } | |
9492 | ||
9493 | /* The optimizer does not know that the call sets the function value | |
9494 | registers we stored in the result block. We avoid problems by | |
9495 | claiming that all hard registers are used and clobbered at this | |
9496 | point. */ | |
9497 | emit_insn (gen_blockage ()); | |
9498 | ||
9499 | DONE; | |
9500 | }") | |
9501 | ||
9502 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9503 | ;; all of memory. This blocks insns from being moved across this point. | |
9504 | ||
9505 | (define_insn "blockage" | |
9506 | [(unspec_volatile [(const_int 0)] 0)] | |
9507 | "" | |
9508 | "") | |
1fd4e8c1 RK |
9509 | \f |
9510 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 9511 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
9512 | ;; |
9513 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
9514 | ;; insns, and branches. We store the operands of compares until we see | |
9515 | ;; how it is used. | |
9516 | (define_expand "cmpsi" | |
9517 | [(set (cc0) | |
cd2b37d9 | 9518 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
9519 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
9520 | "" | |
9521 | " | |
9522 | { | |
9523 | /* Take care of the possibility that operands[1] might be negative but | |
9524 | this might be a logical operation. That insn doesn't exist. */ | |
9525 | if (GET_CODE (operands[1]) == CONST_INT | |
9526 | && INTVAL (operands[1]) < 0) | |
9527 | operands[1] = force_reg (SImode, operands[1]); | |
9528 | ||
9529 | rs6000_compare_op0 = operands[0]; | |
9530 | rs6000_compare_op1 = operands[1]; | |
9531 | rs6000_compare_fp_p = 0; | |
9532 | DONE; | |
9533 | }") | |
9534 | ||
266eb58a DE |
9535 | (define_expand "cmpdi" |
9536 | [(set (cc0) | |
9537 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
9538 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
9539 | "TARGET_POWERPC64" | |
9540 | " | |
9541 | { | |
9542 | /* Take care of the possibility that operands[1] might be negative but | |
9543 | this might be a logical operation. That insn doesn't exist. */ | |
9544 | if (GET_CODE (operands[1]) == CONST_INT | |
9545 | && INTVAL (operands[1]) < 0) | |
9546 | operands[1] = force_reg (DImode, operands[1]); | |
9547 | ||
9548 | rs6000_compare_op0 = operands[0]; | |
9549 | rs6000_compare_op1 = operands[1]; | |
9550 | rs6000_compare_fp_p = 0; | |
9551 | DONE; | |
9552 | }") | |
9553 | ||
1fd4e8c1 | 9554 | (define_expand "cmpsf" |
cd2b37d9 RK |
9555 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
9556 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 9557 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9558 | " |
9559 | { | |
9560 | rs6000_compare_op0 = operands[0]; | |
9561 | rs6000_compare_op1 = operands[1]; | |
9562 | rs6000_compare_fp_p = 1; | |
9563 | DONE; | |
9564 | }") | |
9565 | ||
9566 | (define_expand "cmpdf" | |
cd2b37d9 RK |
9567 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
9568 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 9569 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9570 | " |
9571 | { | |
9572 | rs6000_compare_op0 = operands[0]; | |
9573 | rs6000_compare_op1 = operands[1]; | |
9574 | rs6000_compare_fp_p = 1; | |
9575 | DONE; | |
9576 | }") | |
9577 | ||
9578 | (define_expand "beq" | |
39a10a29 | 9579 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9580 | "" |
39a10a29 | 9581 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
9582 | |
9583 | (define_expand "bne" | |
39a10a29 | 9584 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9585 | "" |
39a10a29 | 9586 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 9587 | |
39a10a29 GK |
9588 | (define_expand "bge" |
9589 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9590 | "" |
39a10a29 | 9591 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
9592 | |
9593 | (define_expand "bgt" | |
39a10a29 | 9594 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9595 | "" |
39a10a29 | 9596 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
9597 | |
9598 | (define_expand "ble" | |
39a10a29 | 9599 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9600 | "" |
39a10a29 | 9601 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 9602 | |
39a10a29 GK |
9603 | (define_expand "blt" |
9604 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9605 | "" |
39a10a29 | 9606 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 9607 | |
39a10a29 GK |
9608 | (define_expand "bgeu" |
9609 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9610 | "" |
39a10a29 | 9611 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 9612 | |
39a10a29 GK |
9613 | (define_expand "bgtu" |
9614 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9615 | "" |
39a10a29 | 9616 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 9617 | |
39a10a29 GK |
9618 | (define_expand "bleu" |
9619 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9620 | "" |
39a10a29 | 9621 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 9622 | |
39a10a29 GK |
9623 | (define_expand "bltu" |
9624 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9625 | "" |
39a10a29 | 9626 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 9627 | |
1c882ea4 | 9628 | (define_expand "bunordered" |
39a10a29 | 9629 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9630 | "" |
39a10a29 | 9631 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
9632 | |
9633 | (define_expand "bordered" | |
39a10a29 | 9634 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9635 | "" |
39a10a29 | 9636 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
9637 | |
9638 | (define_expand "buneq" | |
39a10a29 | 9639 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9640 | "" |
39a10a29 | 9641 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
9642 | |
9643 | (define_expand "bunge" | |
39a10a29 | 9644 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9645 | "" |
39a10a29 | 9646 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
9647 | |
9648 | (define_expand "bungt" | |
39a10a29 | 9649 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9650 | "" |
39a10a29 | 9651 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
9652 | |
9653 | (define_expand "bunle" | |
39a10a29 | 9654 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9655 | "" |
39a10a29 | 9656 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
9657 | |
9658 | (define_expand "bunlt" | |
39a10a29 | 9659 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9660 | "" |
39a10a29 | 9661 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
9662 | |
9663 | (define_expand "bltgt" | |
39a10a29 | 9664 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9665 | "" |
39a10a29 | 9666 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 9667 | |
1fd4e8c1 RK |
9668 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
9669 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
9670 | ;; with an scc insns. However, due to the order that combine see the | |
9671 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
9672 | ;; the cases we don't want to handle. | |
9673 | (define_expand "seq" | |
39a10a29 | 9674 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9675 | "" |
39a10a29 | 9676 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
9677 | |
9678 | (define_expand "sne" | |
39a10a29 | 9679 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9680 | "" |
9681 | " | |
39a10a29 GK |
9682 | { |
9683 | if (! rs6000_compare_fp_p) | |
1fd4e8c1 RK |
9684 | FAIL; |
9685 | ||
39a10a29 GK |
9686 | rs6000_emit_sCOND (NE, operands[0]); |
9687 | DONE; | |
1fd4e8c1 RK |
9688 | }") |
9689 | ||
9690 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
9691 | (define_expand "sgt" | |
39a10a29 | 9692 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9693 | "" |
9694 | " | |
5638268e DE |
9695 | { |
9696 | if (! rs6000_compare_fp_p | |
9697 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
9698 | FAIL; |
9699 | ||
39a10a29 GK |
9700 | rs6000_emit_sCOND (GT, operands[0]); |
9701 | DONE; | |
1fd4e8c1 RK |
9702 | }") |
9703 | ||
9704 | ;; A < 0 is best done in the portable way for A an integer. | |
9705 | (define_expand "slt" | |
39a10a29 | 9706 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9707 | "" |
9708 | " | |
5638268e DE |
9709 | { |
9710 | if (! rs6000_compare_fp_p | |
9711 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
9712 | FAIL; |
9713 | ||
39a10a29 GK |
9714 | rs6000_emit_sCOND (LT, operands[0]); |
9715 | DONE; | |
1fd4e8c1 RK |
9716 | }") |
9717 | ||
5638268e | 9718 | ;; A >= 0 is best done the portable way for A an integer. |
1fd4e8c1 | 9719 | (define_expand "sge" |
39a10a29 | 9720 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9721 | "" |
5638268e DE |
9722 | " |
9723 | { | |
9724 | if (! rs6000_compare_fp_p | |
9725 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
9726 | FAIL; | |
9727 | ||
9728 | rs6000_emit_sCOND (GE, operands[0]); | |
9729 | DONE; | |
9730 | }") | |
1fd4e8c1 RK |
9731 | |
9732 | ;; A <= 0 is best done the portable way for A an integer. | |
9733 | (define_expand "sle" | |
39a10a29 | 9734 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9735 | "" |
9736 | " | |
5638268e DE |
9737 | { |
9738 | if (! rs6000_compare_fp_p | |
9739 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
9740 | FAIL; |
9741 | ||
39a10a29 GK |
9742 | rs6000_emit_sCOND (LE, operands[0]); |
9743 | DONE; | |
1fd4e8c1 RK |
9744 | }") |
9745 | ||
9746 | (define_expand "sgtu" | |
39a10a29 | 9747 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9748 | "" |
39a10a29 | 9749 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9750 | |
9751 | (define_expand "sltu" | |
39a10a29 | 9752 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9753 | "" |
39a10a29 | 9754 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9755 | |
9756 | (define_expand "sgeu" | |
39a10a29 | 9757 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9758 | "" |
39a10a29 | 9759 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9760 | |
9761 | (define_expand "sleu" | |
39a10a29 | 9762 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9763 | "" |
39a10a29 | 9764 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9765 | \f |
9766 | ;; Here are the actual compare insns. | |
acad7ed3 | 9767 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 9768 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 9769 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
9770 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
9771 | "" | |
7f340546 | 9772 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
9773 | [(set_attr "type" "compare")]) |
9774 | ||
acad7ed3 | 9775 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
9776 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
9777 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
9778 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
9779 | "TARGET_POWERPC64" | |
9780 | "cmpd%I2 %0,%1,%2" | |
9781 | [(set_attr "type" "compare")]) | |
9782 | ||
f357808b RK |
9783 | ;; If we are comparing a register for equality with a large constant, |
9784 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
9785 | ;; register for the result of the XOR. | |
9786 | ||
9787 | (define_split | |
9788 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 9789 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 9790 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 9791 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
9792 | "find_single_use (operands[0], insn, 0) |
9793 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
9794 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
9795 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
9796 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
9797 | " | |
9798 | { | |
9799 | /* Get the constant we are comparing against, C, and see what it looks like | |
9800 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
9801 | with C to get the sign-extended value. */ | |
9802 | ||
5f59ecb7 DE |
9803 | HOST_WIDE_INT c = INTVAL (operands[2]); |
9804 | HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000); | |
9805 | HOST_WIDE_INT xorv = c ^ sextc; | |
f357808b | 9806 | |
89e9f3a8 MM |
9807 | operands[4] = GEN_INT (xorv); |
9808 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
9809 | }") |
9810 | ||
acad7ed3 | 9811 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 9812 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 9813 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 9814 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 9815 | "" |
e2c953b6 | 9816 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
1fd4e8c1 RK |
9817 | [(set_attr "type" "compare")]) |
9818 | ||
acad7ed3 | 9819 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
9820 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
9821 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 9822 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 9823 | "" |
e2c953b6 | 9824 | "cmpld%I2 %0,%1,%b2" |
266eb58a DE |
9825 | [(set_attr "type" "compare")]) |
9826 | ||
1fd4e8c1 RK |
9827 | ;; The following two insns don't exist as single insns, but if we provide |
9828 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
9829 | ;; of the required delay between a compare and branch. We generate code for | |
9830 | ;; them by splitting. | |
9831 | ||
9832 | (define_insn "" | |
9833 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 9834 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9835 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 9836 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9837 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
9838 | "" | |
baf97f86 RK |
9839 | "#" |
9840 | [(set_attr "length" "8")]) | |
7e69e155 | 9841 | |
1fd4e8c1 RK |
9842 | (define_insn "" |
9843 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 9844 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9845 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 9846 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9847 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
9848 | "" | |
baf97f86 RK |
9849 | "#" |
9850 | [(set_attr "length" "8")]) | |
7e69e155 | 9851 | |
1fd4e8c1 RK |
9852 | (define_split |
9853 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 9854 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 9855 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 9856 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
9857 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
9858 | "" | |
9859 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
9860 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
9861 | ||
9862 | (define_split | |
9863 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 9864 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 9865 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 9866 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
9867 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
9868 | "" | |
9869 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
9870 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
9871 | ||
acad7ed3 | 9872 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 9873 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
9874 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
9875 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 9876 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9877 | "fcmpu %0,%1,%2" |
9878 | [(set_attr "type" "fpcompare")]) | |
9879 | ||
acad7ed3 | 9880 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 9881 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
9882 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
9883 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 9884 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9885 | "fcmpu %0,%1,%2" |
9886 | [(set_attr "type" "fpcompare")]) | |
9887 | \f | |
9888 | ;; Now we have the scc insns. We can do some combinations because of the | |
9889 | ;; way the machine works. | |
9890 | ;; | |
9891 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
9892 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
9893 | ;; cases the insns below which don't use an intermediate CR field will | |
9894 | ;; be used instead. | |
1fd4e8c1 | 9895 | (define_insn "" |
cd2b37d9 | 9896 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9897 | (match_operator:SI 1 "scc_comparison_operator" |
9898 | [(match_operand 2 "cc_reg_operand" "y") | |
9899 | (const_int 0)]))] | |
9900 | "" | |
ca7f5001 | 9901 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b19003d8 | 9902 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9903 | |
9904 | (define_insn "" | |
9ebbca7d GK |
9905 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9906 | (match_operator:DI 1 "scc_comparison_operator" | |
9907 | [(match_operand 2 "cc_reg_operand" "y") | |
9908 | (const_int 0)]))] | |
9909 | "TARGET_POWERPC64" | |
9910 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" | |
9911 | [(set_attr "length" "12")]) | |
9912 | ||
9913 | (define_insn "" | |
9914 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 9915 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 9916 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
9917 | (const_int 0)]) |
9918 | (const_int 0))) | |
9ebbca7d | 9919 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9920 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 9921 | "! TARGET_POWERPC64" |
9ebbca7d GK |
9922 | "@ |
9923 | %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 | |
9924 | #" | |
b19003d8 | 9925 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
9926 | (set_attr "length" "12,16")]) |
9927 | ||
9928 | (define_split | |
9929 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
9930 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
9931 | [(match_operand 2 "cc_reg_operand" "") | |
9932 | (const_int 0)]) | |
9933 | (const_int 0))) | |
9934 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
9935 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
9936 | "! TARGET_POWERPC64 && reload_completed" | |
9937 | [(set (match_dup 3) | |
9938 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
9939 | (set (match_dup 0) | |
9940 | (compare:CC (match_dup 3) | |
9941 | (const_int 0)))] | |
9942 | "") | |
1fd4e8c1 RK |
9943 | |
9944 | (define_insn "" | |
cd2b37d9 | 9945 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9946 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
9947 | [(match_operand 2 "cc_reg_operand" "y") | |
9948 | (const_int 0)]) | |
9949 | (match_operand:SI 3 "const_int_operand" "n")))] | |
9950 | "" | |
9951 | "* | |
9952 | { | |
9953 | int is_bit = ccr_bit (operands[1], 1); | |
9954 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
9955 | int count; | |
9956 | ||
9957 | if (is_bit >= put_bit) | |
9958 | count = is_bit - put_bit; | |
9959 | else | |
9960 | count = 32 - (put_bit - is_bit); | |
9961 | ||
89e9f3a8 MM |
9962 | operands[4] = GEN_INT (count); |
9963 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 9964 | |
ca7f5001 | 9965 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 RK |
9966 | }" |
9967 | [(set_attr "length" "12")]) | |
1fd4e8c1 RK |
9968 | |
9969 | (define_insn "" | |
9ebbca7d | 9970 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
9971 | (compare:CC |
9972 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 9973 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 9974 | (const_int 0)]) |
9ebbca7d | 9975 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 9976 | (const_int 0))) |
9ebbca7d | 9977 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
9978 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
9979 | (match_dup 3)))] | |
9ebbca7d | 9980 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
9981 | "* |
9982 | { | |
9983 | int is_bit = ccr_bit (operands[1], 1); | |
9984 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
9985 | int count; | |
9986 | ||
9ebbca7d GK |
9987 | /* Force split for non-cc0 compare. */ |
9988 | if (which_alternative == 1) | |
9989 | return \"#\"; | |
9990 | ||
1fd4e8c1 RK |
9991 | if (is_bit >= put_bit) |
9992 | count = is_bit - put_bit; | |
9993 | else | |
9994 | count = 32 - (put_bit - is_bit); | |
9995 | ||
89e9f3a8 MM |
9996 | operands[5] = GEN_INT (count); |
9997 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 9998 | |
ca7f5001 | 9999 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 10000 | }" |
b19003d8 | 10001 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10002 | (set_attr "length" "12,16")]) |
10003 | ||
10004 | (define_split | |
10005 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10006 | (compare:CC | |
10007 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
10008 | [(match_operand 2 "cc_reg_operand" "") | |
10009 | (const_int 0)]) | |
10010 | (match_operand:SI 3 "const_int_operand" "")) | |
10011 | (const_int 0))) | |
10012 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
10013 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10014 | (match_dup 3)))] | |
10015 | "! TARGET_POWERPC64 && reload_completed" | |
10016 | [(set (match_dup 4) | |
10017 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10018 | (match_dup 3))) | |
10019 | (set (match_dup 0) | |
10020 | (compare:CC (match_dup 4) | |
10021 | (const_int 0)))] | |
10022 | "") | |
1fd4e8c1 | 10023 | |
c5defebb RK |
10024 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
10025 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
10026 | ||
10027 | (define_peephole | |
cd2b37d9 | 10028 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
10029 | (match_operator:SI 1 "scc_comparison_operator" |
10030 | [(match_operand 2 "cc_reg_operand" "y") | |
10031 | (const_int 0)])) | |
cd2b37d9 | 10032 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
10033 | (match_operator:SI 4 "scc_comparison_operator" |
10034 | [(match_operand 5 "cc_reg_operand" "y") | |
10035 | (const_int 0)]))] | |
10036 | "REGNO (operands[2]) != REGNO (operands[5])" | |
ca7f5001 | 10037 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b19003d8 | 10038 | [(set_attr "length" "20")]) |
c5defebb | 10039 | |
9ebbca7d GK |
10040 | (define_peephole |
10041 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10042 | (match_operator:DI 1 "scc_comparison_operator" | |
10043 | [(match_operand 2 "cc_reg_operand" "y") | |
10044 | (const_int 0)])) | |
10045 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
10046 | (match_operator:DI 4 "scc_comparison_operator" | |
10047 | [(match_operand 5 "cc_reg_operand" "y") | |
10048 | (const_int 0)]))] | |
10049 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" | |
10050 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
10051 | [(set_attr "length" "20")]) | |
10052 | ||
1fd4e8c1 RK |
10053 | ;; There are some scc insns that can be done directly, without a compare. |
10054 | ;; These are faster because they don't involve the communications between | |
10055 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
10056 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
10057 | ;; | |
10058 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
10059 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
10060 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
10061 | ;; cases where it is no more expensive than (neg (scc ..)). | |
10062 | ||
10063 | ;; Have reload force a constant into a register for the simple insns that | |
10064 | ;; otherwise won't accept constants. We do this because it is faster than | |
10065 | ;; the cmp/mfcr sequence we would otherwise generate. | |
10066 | ||
10067 | (define_insn "" | |
cd2b37d9 RK |
10068 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
10069 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 10070 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 10071 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
f9562f27 | 10072 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10073 | "@ |
ca7f5001 | 10074 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 10075 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
10076 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
10077 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
10078 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 10079 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 10080 | |
a260abc9 DE |
10081 | (define_insn "" |
10082 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
10083 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
10084 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
10085 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
10086 | "TARGET_POWERPC64" | |
10087 | "@ | |
10088 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10089 | subfic %3,%1,0\;adde %0,%3,%1 | |
10090 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10091 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10092 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
10093 | [(set_attr "length" "12,8,12,12,12")]) | |
10094 | ||
1fd4e8c1 | 10095 | (define_insn "" |
9ebbca7d | 10096 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10097 | (compare:CC |
9ebbca7d GK |
10098 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10099 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 10100 | (const_int 0))) |
9ebbca7d | 10101 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 10102 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10103 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
f9562f27 | 10104 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10105 | "@ |
ca7f5001 RK |
10106 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
10107 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
10108 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
10109 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
10110 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
10111 | # | |
10112 | # | |
10113 | # | |
10114 | # | |
10115 | #" | |
b19003d8 | 10116 | [(set_attr "type" "compare") |
9ebbca7d GK |
10117 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10118 | ||
10119 | (define_split | |
10120 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10121 | (compare:CC | |
10122 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10123 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10124 | (const_int 0))) | |
10125 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10126 | (eq:SI (match_dup 1) (match_dup 2))) | |
10127 | (clobber (match_scratch:SI 3 ""))] | |
10128 | "! TARGET_POWERPC64 && reload_completed" | |
10129 | [(parallel [(set (match_dup 0) | |
10130 | (eq:SI (match_dup 1) (match_dup 2))) | |
10131 | (clobber (match_dup 3))]) | |
10132 | (set (match_dup 4) | |
10133 | (compare:CC (match_dup 0) | |
10134 | (const_int 0)))] | |
10135 | "") | |
b19003d8 | 10136 | |
a260abc9 | 10137 | (define_insn "" |
9ebbca7d | 10138 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 10139 | (compare:CC |
9ebbca7d GK |
10140 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10141 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 10142 | (const_int 0))) |
9ebbca7d | 10143 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 10144 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10145 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
a260abc9 DE |
10146 | "TARGET_POWERPC64" |
10147 | "@ | |
10148 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
10149 | subfic %3,%1,0\;adde. %0,%3,%1 | |
10150 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
10151 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
10152 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
10153 | # | |
10154 | # | |
10155 | # | |
10156 | # | |
10157 | #" | |
a260abc9 | 10158 | [(set_attr "type" "compare") |
9ebbca7d GK |
10159 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10160 | ||
10161 | (define_split | |
10162 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10163 | (compare:CC | |
10164 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
10165 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
10166 | (const_int 0))) | |
10167 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10168 | (eq:DI (match_dup 1) (match_dup 2))) | |
10169 | (clobber (match_scratch:DI 3 ""))] | |
10170 | "TARGET_POWERPC64 && reload_completed" | |
10171 | [(parallel [(set (match_dup 0) | |
10172 | (eq:DI (match_dup 1) (match_dup 2))) | |
10173 | (clobber (match_dup 3))]) | |
10174 | (set (match_dup 4) | |
10175 | (compare:CC (match_dup 0) | |
10176 | (const_int 0)))] | |
10177 | "") | |
a260abc9 | 10178 | |
b19003d8 RK |
10179 | ;; We have insns of the form shown by the first define_insn below. If |
10180 | ;; there is something inside the comparison operation, we must split it. | |
10181 | (define_split | |
10182 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
10183 | (plus:SI (match_operator 1 "comparison_operator" | |
10184 | [(match_operand:SI 2 "" "") | |
10185 | (match_operand:SI 3 | |
10186 | "reg_or_cint_operand" "")]) | |
10187 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
10188 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
10189 | "! gpc_reg_operand (operands[2], SImode)" | |
10190 | [(set (match_dup 5) (match_dup 2)) | |
10191 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
10192 | (match_dup 4)))]) | |
1fd4e8c1 RK |
10193 | |
10194 | (define_insn "" | |
cd2b37d9 RK |
10195 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
10196 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 10197 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
cd2b37d9 | 10198 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) |
1fd4e8c1 | 10199 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
f9562f27 | 10200 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10201 | "@ |
ca7f5001 RK |
10202 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
10203 | {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 | |
10204 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
10205 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
d9d934ef | 10206 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" |
b19003d8 | 10207 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
10208 | |
10209 | (define_insn "" | |
9ebbca7d | 10210 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10211 | (compare:CC |
1fd4e8c1 | 10212 | (plus:SI |
9ebbca7d GK |
10213 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10214 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
10215 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 10216 | (const_int 0))) |
9ebbca7d | 10217 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 10218 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10219 | "@ |
ca7f5001 | 10220 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 10221 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
10222 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
10223 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
10224 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
10225 | # | |
10226 | # | |
10227 | # | |
10228 | # | |
10229 | #" | |
b19003d8 | 10230 | [(set_attr "type" "compare") |
9ebbca7d GK |
10231 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10232 | ||
10233 | (define_split | |
10234 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10235 | (compare:CC | |
10236 | (plus:SI | |
10237 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10238 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10239 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10240 | (const_int 0))) | |
10241 | (clobber (match_scratch:SI 4 ""))] | |
10242 | "! TARGET_POWERPC64 && reload_completed" | |
10243 | [(set (match_dup 4) | |
10244 | (plus:SI (eq:SI (match_dup 1) | |
10245 | (match_dup 2)) | |
10246 | (match_dup 3))) | |
10247 | (set (match_dup 0) | |
10248 | (compare:CC (match_dup 4) | |
10249 | (const_int 0)))] | |
10250 | "") | |
1fd4e8c1 RK |
10251 | |
10252 | (define_insn "" | |
9ebbca7d | 10253 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10254 | (compare:CC |
1fd4e8c1 | 10255 | (plus:SI |
9ebbca7d GK |
10256 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10257 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
10258 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 10259 | (const_int 0))) |
9ebbca7d | 10260 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 10261 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10262 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 10263 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10264 | "@ |
ca7f5001 | 10265 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
19378cf8 | 10266 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 |
ca7f5001 RK |
10267 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
10268 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
10269 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
10270 | # | |
10271 | # | |
10272 | # | |
10273 | # | |
10274 | #" | |
10275 | [(set_attr "type" "compare") | |
10276 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
10277 | ||
10278 | (define_split | |
10279 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10280 | (compare:CC | |
10281 | (plus:SI | |
10282 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10283 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10284 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10285 | (const_int 0))) | |
10286 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10287 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10288 | (clobber (match_scratch:SI 4 ""))] | |
10289 | "! TARGET_POWERPC64 && reload_completed" | |
10290 | [(parallel [(set (match_dup 0) | |
10291 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10292 | (clobber (match_dup 4))]) | |
10293 | (set (match_dup 5) | |
10294 | (compare:CC (match_dup 0) | |
10295 | (const_int 0)))] | |
10296 | "") | |
10297 | ||
1fd4e8c1 | 10298 | (define_insn "" |
cd2b37d9 | 10299 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 10300 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 10301 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
f9562f27 | 10302 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10303 | "@ |
ca7f5001 RK |
10304 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
10305 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
10306 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
10307 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
10308 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 10309 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 10310 | |
ea9be077 MM |
10311 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
10312 | ;; since it nabs/sr is just as fast. | |
463b558b | 10313 | (define_insn "*ne0" |
b4e95693 | 10314 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
10315 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
10316 | (const_int 31))) | |
10317 | (clobber (match_scratch:SI 2 "=&r"))] | |
9ebbca7d | 10318 | "! TARGET_POWER && ! TARGET_POWERPC64" |
ea9be077 MM |
10319 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
10320 | [(set_attr "length" "8")]) | |
10321 | ||
a260abc9 DE |
10322 | (define_insn "" |
10323 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10324 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
10325 | (const_int 63))) | |
10326 | (clobber (match_scratch:DI 2 "=&r"))] | |
10327 | "TARGET_POWERPC64" | |
10328 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
10329 | [(set_attr "length" "8")]) | |
10330 | ||
1fd4e8c1 RK |
10331 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
10332 | (define_insn "" | |
cd2b37d9 | 10333 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10334 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 10335 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10336 | (const_int 31)) |
cd2b37d9 | 10337 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10338 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 10339 | "! TARGET_POWERPC64" |
ca7f5001 | 10340 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 10341 | [(set_attr "length" "8")]) |
1fd4e8c1 | 10342 | |
a260abc9 DE |
10343 | (define_insn "" |
10344 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10345 | (plus:DI (lshiftrt:DI | |
10346 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
10347 | (const_int 63)) | |
10348 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
10349 | (clobber (match_scratch:DI 3 "=&r"))] | |
10350 | "TARGET_POWERPC64" | |
10351 | "addic %3,%1,-1\;addze %0,%2" | |
10352 | [(set_attr "length" "8")]) | |
10353 | ||
1fd4e8c1 | 10354 | (define_insn "" |
9ebbca7d | 10355 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10356 | (compare:CC |
10357 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 10358 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10359 | (const_int 31)) |
9ebbca7d | 10360 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 10361 | (const_int 0))) |
9ebbca7d | 10362 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 10363 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10364 | "@ |
10365 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
10366 | #" | |
b19003d8 | 10367 | [(set_attr "type" "compare") |
9ebbca7d GK |
10368 | (set_attr "length" "8,12")]) |
10369 | ||
10370 | (define_split | |
10371 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10372 | (compare:CC | |
10373 | (plus:SI (lshiftrt:SI | |
10374 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10375 | (const_int 31)) | |
10376 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
10377 | (const_int 0))) | |
10378 | (clobber (match_scratch:SI 3 ""))] | |
10379 | "! TARGET_POWERPC64 && reload_completed" | |
10380 | [(set (match_dup 3) | |
10381 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) | |
10382 | (const_int 31)) | |
10383 | (match_dup 2))) | |
10384 | (set (match_dup 0) | |
10385 | (compare:CC (match_dup 3) | |
10386 | (const_int 0)))] | |
10387 | "") | |
1fd4e8c1 | 10388 | |
a260abc9 | 10389 | (define_insn "" |
9ebbca7d | 10390 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
10391 | (compare:CC |
10392 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 10393 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 10394 | (const_int 63)) |
9ebbca7d | 10395 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 10396 | (const_int 0))) |
9ebbca7d | 10397 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 10398 | "TARGET_POWERPC64" |
9ebbca7d GK |
10399 | "@ |
10400 | addic %3,%1,-1\;addze. %3,%2 | |
10401 | #" | |
a260abc9 | 10402 | [(set_attr "type" "compare") |
9ebbca7d GK |
10403 | (set_attr "length" "8,12")]) |
10404 | ||
10405 | (define_split | |
10406 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10407 | (compare:CC | |
10408 | (plus:DI (lshiftrt:DI | |
10409 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10410 | (const_int 63)) | |
10411 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
10412 | (const_int 0))) | |
10413 | (clobber (match_scratch:DI 3 ""))] | |
10414 | "TARGET_POWERPC64 && reload_completed" | |
10415 | [(set (match_dup 3) | |
10416 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
10417 | (const_int 63)) | |
10418 | (match_dup 2))) | |
10419 | (set (match_dup 0) | |
10420 | (compare:CC (match_dup 3) | |
10421 | (const_int 0)))] | |
10422 | "") | |
a260abc9 | 10423 | |
1fd4e8c1 | 10424 | (define_insn "" |
9ebbca7d | 10425 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10426 | (compare:CC |
10427 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 10428 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10429 | (const_int 31)) |
9ebbca7d | 10430 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 10431 | (const_int 0))) |
9ebbca7d | 10432 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
10433 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
10434 | (match_dup 2))) | |
9ebbca7d | 10435 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 10436 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10437 | "@ |
10438 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
10439 | #" | |
b19003d8 | 10440 | [(set_attr "type" "compare") |
9ebbca7d GK |
10441 | (set_attr "length" "8,12")]) |
10442 | ||
10443 | (define_split | |
10444 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10445 | (compare:CC | |
10446 | (plus:SI (lshiftrt:SI | |
10447 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10448 | (const_int 31)) | |
10449 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
10450 | (const_int 0))) | |
10451 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10452 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
10453 | (match_dup 2))) | |
10454 | (clobber (match_scratch:SI 3 ""))] | |
10455 | "! TARGET_POWERPC64 && reload_completed" | |
10456 | [(parallel [(set (match_dup 0) | |
10457 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
10458 | (match_dup 2))) | |
10459 | (clobber (match_dup 3))]) | |
10460 | (set (match_dup 4) | |
10461 | (compare:CC (match_dup 0) | |
10462 | (const_int 0)))] | |
10463 | "") | |
1fd4e8c1 | 10464 | |
a260abc9 | 10465 | (define_insn "" |
9ebbca7d | 10466 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
10467 | (compare:CC |
10468 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 10469 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 10470 | (const_int 63)) |
9ebbca7d | 10471 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 10472 | (const_int 0))) |
9ebbca7d | 10473 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
10474 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
10475 | (match_dup 2))) | |
9ebbca7d | 10476 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 10477 | "TARGET_POWERPC64" |
9ebbca7d GK |
10478 | "@ |
10479 | addic %3,%1,-1\;addze. %0,%2 | |
10480 | #" | |
a260abc9 | 10481 | [(set_attr "type" "compare") |
9ebbca7d GK |
10482 | (set_attr "length" "8,12")]) |
10483 | ||
10484 | (define_split | |
10485 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10486 | (compare:CC | |
10487 | (plus:DI (lshiftrt:DI | |
10488 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10489 | (const_int 63)) | |
10490 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
10491 | (const_int 0))) | |
10492 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10493 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
10494 | (match_dup 2))) | |
10495 | (clobber (match_scratch:DI 3 ""))] | |
10496 | "TARGET_POWERPC64 && reload_completed" | |
10497 | [(parallel [(set (match_dup 0) | |
10498 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
10499 | (match_dup 2))) | |
10500 | (clobber (match_dup 3))]) | |
10501 | (set (match_dup 4) | |
10502 | (compare:CC (match_dup 0) | |
10503 | (const_int 0)))] | |
10504 | "") | |
a260abc9 | 10505 | |
1fd4e8c1 | 10506 | (define_insn "" |
cd2b37d9 RK |
10507 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10508 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
10509 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
10510 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 10511 | "TARGET_POWER" |
1fd4e8c1 | 10512 | "@ |
ca7f5001 | 10513 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 10514 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 10515 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10516 | |
10517 | (define_insn "" | |
9ebbca7d | 10518 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10519 | (compare:CC |
9ebbca7d GK |
10520 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10521 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 10522 | (const_int 0))) |
9ebbca7d | 10523 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 10524 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10525 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 10526 | "TARGET_POWER" |
1fd4e8c1 | 10527 | "@ |
ca7f5001 | 10528 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
10529 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
10530 | # | |
10531 | #" | |
10532 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
10533 | (set_attr "length" "12,12,16,16")]) | |
10534 | ||
10535 | (define_split | |
10536 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10537 | (compare:CC | |
10538 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10539 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10540 | (const_int 0))) | |
10541 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10542 | (le:SI (match_dup 1) (match_dup 2))) | |
10543 | (clobber (match_scratch:SI 3 ""))] | |
10544 | "TARGET_POWER && reload_completed" | |
10545 | [(parallel [(set (match_dup 0) | |
10546 | (le:SI (match_dup 1) (match_dup 2))) | |
10547 | (clobber (match_dup 3))]) | |
10548 | (set (match_dup 4) | |
10549 | (compare:CC (match_dup 0) | |
10550 | (const_int 0)))] | |
10551 | "") | |
1fd4e8c1 RK |
10552 | |
10553 | (define_insn "" | |
cd2b37d9 RK |
10554 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10555 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 10556 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 10557 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10558 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 10559 | "TARGET_POWER" |
1fd4e8c1 | 10560 | "@ |
ca7f5001 RK |
10561 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
10562 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" | |
b19003d8 | 10563 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10564 | |
10565 | (define_insn "" | |
9ebbca7d | 10566 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10567 | (compare:CC |
9ebbca7d GK |
10568 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10569 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
10570 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 10571 | (const_int 0))) |
9ebbca7d | 10572 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 10573 | "TARGET_POWER" |
1fd4e8c1 | 10574 | "@ |
ca7f5001 | 10575 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
10576 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
10577 | # | |
10578 | #" | |
b19003d8 | 10579 | [(set_attr "type" "compare") |
9ebbca7d GK |
10580 | (set_attr "length" "12,12,16,16")]) |
10581 | ||
10582 | (define_split | |
10583 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10584 | (compare:CC | |
10585 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10586 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10587 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10588 | (const_int 0))) | |
10589 | (clobber (match_scratch:SI 4 ""))] | |
10590 | "TARGET_POWER && reload_completed" | |
10591 | [(set (match_dup 4) | |
10592 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
10593 | (match_dup 3))) | |
10594 | (set (match_dup 0) | |
10595 | (compare:CC (match_dup 4) | |
10596 | (const_int 0)))] | |
10597 | "") | |
1fd4e8c1 RK |
10598 | |
10599 | (define_insn "" | |
9ebbca7d | 10600 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10601 | (compare:CC |
9ebbca7d GK |
10602 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10603 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
10604 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 10605 | (const_int 0))) |
9ebbca7d | 10606 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 10607 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10608 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 10609 | "TARGET_POWER" |
1fd4e8c1 | 10610 | "@ |
ca7f5001 | 10611 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
10612 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3 |
10613 | # | |
10614 | #" | |
b19003d8 | 10615 | [(set_attr "type" "compare") |
9ebbca7d GK |
10616 | (set_attr "length" "12,12,16,16")]) |
10617 | ||
10618 | (define_split | |
10619 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10620 | (compare:CC | |
10621 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10622 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10623 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10624 | (const_int 0))) | |
10625 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10626 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10627 | (clobber (match_scratch:SI 4 ""))] | |
10628 | "TARGET_POWER && reload_completed" | |
10629 | [(parallel [(set (match_dup 0) | |
10630 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10631 | (clobber (match_dup 4))]) | |
10632 | (set (match_dup 5) | |
10633 | (compare:CC (match_dup 0) | |
10634 | (const_int 0)))] | |
10635 | "") | |
1fd4e8c1 RK |
10636 | |
10637 | (define_insn "" | |
cd2b37d9 RK |
10638 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10639 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 10640 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 10641 | "TARGET_POWER" |
1fd4e8c1 | 10642 | "@ |
ca7f5001 RK |
10643 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
10644 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 10645 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10646 | |
10647 | (define_insn "" | |
cd2b37d9 RK |
10648 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10649 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10650 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 10651 | "! TARGET_POWERPC64" |
ca7f5001 | 10652 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 10653 | [(set_attr "length" "12")]) |
1fd4e8c1 | 10654 | |
f9562f27 DE |
10655 | (define_insn "" |
10656 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10657 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
10658 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
10659 | "TARGET_POWERPC64" | |
10660 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" | |
10661 | [(set_attr "length" "12")]) | |
10662 | ||
10663 | (define_insn "" | |
9ebbca7d | 10664 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 10665 | (compare:CC |
9ebbca7d GK |
10666 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
10667 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 10668 | (const_int 0))) |
9ebbca7d | 10669 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
10670 | (leu:DI (match_dup 1) (match_dup 2)))] |
10671 | "TARGET_POWERPC64" | |
9ebbca7d GK |
10672 | "@ |
10673 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
10674 | #" | |
f9562f27 | 10675 | [(set_attr "type" "compare") |
9ebbca7d GK |
10676 | (set_attr "length" "12,16")]) |
10677 | ||
10678 | (define_split | |
10679 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
10680 | (compare:CC | |
10681 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
10682 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
10683 | (const_int 0))) | |
10684 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10685 | (leu:DI (match_dup 1) (match_dup 2)))] | |
10686 | "TARGET_POWERPC64 && reload_completed" | |
10687 | [(set (match_dup 0) | |
10688 | (leu:DI (match_dup 1) (match_dup 2))) | |
10689 | (set (match_dup 3) | |
10690 | (compare:CC (match_dup 0) | |
10691 | (const_int 0)))] | |
10692 | "") | |
f9562f27 | 10693 | |
1fd4e8c1 | 10694 | (define_insn "" |
9ebbca7d | 10695 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10696 | (compare:CC |
9ebbca7d GK |
10697 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10698 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 10699 | (const_int 0))) |
9ebbca7d | 10700 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10701 | (leu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 10702 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10703 | "@ |
10704 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
10705 | #" | |
b19003d8 | 10706 | [(set_attr "type" "compare") |
9ebbca7d GK |
10707 | (set_attr "length" "12,16")]) |
10708 | ||
10709 | (define_split | |
10710 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
10711 | (compare:CC | |
10712 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10713 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10714 | (const_int 0))) | |
10715 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10716 | (leu:SI (match_dup 1) (match_dup 2)))] | |
10717 | "! TARGET_POWERPC64 && reload_completed" | |
10718 | [(set (match_dup 0) | |
10719 | (leu:SI (match_dup 1) (match_dup 2))) | |
10720 | (set (match_dup 3) | |
10721 | (compare:CC (match_dup 0) | |
10722 | (const_int 0)))] | |
10723 | "") | |
1fd4e8c1 | 10724 | |
f9562f27 | 10725 | (define_insn "" |
9ebbca7d | 10726 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 10727 | (compare:CC |
9ebbca7d GK |
10728 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
10729 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 10730 | (const_int 0))) |
9ebbca7d | 10731 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
10732 | (leu:DI (match_dup 1) (match_dup 2)))] |
10733 | "TARGET_POWERPC64" | |
9ebbca7d GK |
10734 | "@ |
10735 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
10736 | #" | |
f9562f27 | 10737 | [(set_attr "type" "compare") |
9ebbca7d | 10738 | (set_attr "length" "12,16")]) |
f9562f27 | 10739 | |
1fd4e8c1 | 10740 | (define_insn "" |
cd2b37d9 RK |
10741 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10742 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10743 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 10744 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10745 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 10746 | "! TARGET_POWERPC64" |
ca7f5001 | 10747 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 10748 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
10749 | |
10750 | (define_insn "" | |
9ebbca7d | 10751 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10752 | (compare:CC |
9ebbca7d GK |
10753 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10754 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
10755 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10756 | (const_int 0))) |
9ebbca7d | 10757 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 10758 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10759 | "@ |
10760 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
10761 | #" | |
b19003d8 | 10762 | [(set_attr "type" "compare") |
9ebbca7d GK |
10763 | (set_attr "length" "8,12")]) |
10764 | ||
10765 | (define_split | |
10766 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10767 | (compare:CC | |
10768 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10769 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10770 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10771 | (const_int 0))) | |
10772 | (clobber (match_scratch:SI 4 ""))] | |
10773 | "! TARGET_POWERPC64 && reload_completed" | |
10774 | [(set (match_dup 4) | |
10775 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
10776 | (match_dup 3))) | |
10777 | (set (match_dup 0) | |
10778 | (compare:CC (match_dup 4) | |
10779 | (const_int 0)))] | |
10780 | "") | |
1fd4e8c1 RK |
10781 | |
10782 | (define_insn "" | |
9ebbca7d | 10783 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10784 | (compare:CC |
9ebbca7d GK |
10785 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10786 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
10787 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10788 | (const_int 0))) |
9ebbca7d | 10789 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10790 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10791 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 10792 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10793 | "@ |
10794 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3 | |
10795 | #" | |
b19003d8 | 10796 | [(set_attr "type" "compare") |
9ebbca7d GK |
10797 | (set_attr "length" "8,12")]) |
10798 | ||
10799 | (define_split | |
10800 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10801 | (compare:CC | |
10802 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10803 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10804 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10805 | (const_int 0))) | |
10806 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10807 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10808 | (clobber (match_scratch:SI 4 ""))] | |
10809 | "! TARGET_POWERPC64 && reload_completed" | |
10810 | [(parallel [(set (match_dup 0) | |
10811 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10812 | (clobber (match_dup 4))]) | |
10813 | (set (match_dup 5) | |
10814 | (compare:CC (match_dup 0) | |
10815 | (const_int 0)))] | |
10816 | "") | |
1fd4e8c1 RK |
10817 | |
10818 | (define_insn "" | |
cd2b37d9 RK |
10819 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10820 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10821 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 10822 | "! TARGET_POWERPC64" |
ca7f5001 | 10823 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 10824 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10825 | |
10826 | (define_insn "" | |
cd2b37d9 | 10827 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10828 | (and:SI (neg:SI |
cd2b37d9 | 10829 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10830 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 10831 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10832 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 10833 | "! TARGET_POWERPC64" |
ca7f5001 | 10834 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" |
b19003d8 | 10835 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10836 | |
10837 | (define_insn "" | |
9ebbca7d | 10838 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10839 | (compare:CC |
10840 | (and:SI (neg:SI | |
9ebbca7d GK |
10841 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10842 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
10843 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10844 | (const_int 0))) |
9ebbca7d | 10845 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 10846 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10847 | "@ |
10848 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
10849 | #" | |
10850 | [(set_attr "type" "compare") | |
10851 | (set_attr "length" "12,16")]) | |
10852 | ||
10853 | (define_split | |
10854 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10855 | (compare:CC | |
10856 | (and:SI (neg:SI | |
10857 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10858 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
10859 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10860 | (const_int 0))) | |
10861 | (clobber (match_scratch:SI 4 ""))] | |
10862 | "! TARGET_POWERPC64 && reload_completed" | |
10863 | [(set (match_dup 4) | |
10864 | (and:SI (neg:SI (leu:SI (match_dup 1) | |
10865 | (match_dup 2))) | |
10866 | (match_dup 3))) | |
10867 | (set (match_dup 0) | |
10868 | (compare:CC (match_dup 4) | |
10869 | (const_int 0)))] | |
10870 | "") | |
1fd4e8c1 RK |
10871 | |
10872 | (define_insn "" | |
9ebbca7d | 10873 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10874 | (compare:CC |
10875 | (and:SI (neg:SI | |
9ebbca7d GK |
10876 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10877 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
10878 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10879 | (const_int 0))) |
9ebbca7d | 10880 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10881 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 10882 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 10883 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10884 | "@ |
10885 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 | |
10886 | #" | |
b19003d8 | 10887 | [(set_attr "type" "compare") |
9ebbca7d GK |
10888 | (set_attr "length" "12,16")]) |
10889 | ||
10890 | (define_split | |
10891 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10892 | (compare:CC | |
10893 | (and:SI (neg:SI | |
10894 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10895 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
10896 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10897 | (const_int 0))) | |
10898 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10899 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
10900 | (clobber (match_scratch:SI 4 ""))] | |
10901 | "! TARGET_POWERPC64 && reload_completed" | |
10902 | [(parallel [(set (match_dup 0) | |
10903 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
10904 | (clobber (match_dup 4))]) | |
10905 | (set (match_dup 5) | |
10906 | (compare:CC (match_dup 0) | |
10907 | (const_int 0)))] | |
10908 | "") | |
1fd4e8c1 RK |
10909 | |
10910 | (define_insn "" | |
cd2b37d9 RK |
10911 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10912 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10913 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 10914 | "TARGET_POWER" |
7f340546 | 10915 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 10916 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10917 | |
10918 | (define_insn "" | |
9ebbca7d | 10919 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10920 | (compare:CC |
9ebbca7d GK |
10921 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10922 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 10923 | (const_int 0))) |
9ebbca7d | 10924 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10925 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 10926 | "TARGET_POWER" |
9ebbca7d GK |
10927 | "@ |
10928 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
10929 | #" | |
29ae5b89 | 10930 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10931 | (set_attr "length" "12,16")]) |
10932 | ||
10933 | (define_split | |
10934 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
10935 | (compare:CC | |
10936 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10937 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10938 | (const_int 0))) | |
10939 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10940 | (lt:SI (match_dup 1) (match_dup 2)))] | |
10941 | "TARGET_POWER && reload_completed" | |
10942 | [(set (match_dup 0) | |
10943 | (lt:SI (match_dup 1) (match_dup 2))) | |
10944 | (set (match_dup 3) | |
10945 | (compare:CC (match_dup 0) | |
10946 | (const_int 0)))] | |
10947 | "") | |
1fd4e8c1 RK |
10948 | |
10949 | (define_insn "" | |
cd2b37d9 RK |
10950 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10951 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10952 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 10953 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10954 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
10955 | "TARGET_POWER" |
10956 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 10957 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10958 | |
10959 | (define_insn "" | |
9ebbca7d | 10960 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10961 | (compare:CC |
9ebbca7d GK |
10962 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10963 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
10964 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10965 | (const_int 0))) |
9ebbca7d | 10966 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 10967 | "TARGET_POWER" |
9ebbca7d GK |
10968 | "@ |
10969 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
10970 | #" | |
b19003d8 | 10971 | [(set_attr "type" "compare") |
9ebbca7d GK |
10972 | (set_attr "length" "12,16")]) |
10973 | ||
10974 | (define_split | |
10975 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10976 | (compare:CC | |
10977 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10978 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10979 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10980 | (const_int 0))) | |
10981 | (clobber (match_scratch:SI 4 ""))] | |
10982 | "TARGET_POWER && reload_completed" | |
10983 | [(set (match_dup 4) | |
10984 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
10985 | (match_dup 3))) | |
10986 | (set (match_dup 0) | |
10987 | (compare:CC (match_dup 4) | |
10988 | (const_int 0)))] | |
10989 | "") | |
1fd4e8c1 RK |
10990 | |
10991 | (define_insn "" | |
9ebbca7d | 10992 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10993 | (compare:CC |
9ebbca7d GK |
10994 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10995 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
10996 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10997 | (const_int 0))) |
9ebbca7d | 10998 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10999 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11000 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11001 | "TARGET_POWER" |
9ebbca7d GK |
11002 | "@ |
11003 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
11004 | #" | |
b19003d8 | 11005 | [(set_attr "type" "compare") |
9ebbca7d GK |
11006 | (set_attr "length" "12,16")]) |
11007 | ||
11008 | (define_split | |
11009 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11010 | (compare:CC | |
11011 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11012 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11013 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11014 | (const_int 0))) | |
11015 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11016 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11017 | (clobber (match_scratch:SI 4 ""))] | |
11018 | "TARGET_POWER && reload_completed" | |
11019 | [(parallel [(set (match_dup 0) | |
11020 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11021 | (clobber (match_dup 4))]) | |
11022 | (set (match_dup 5) | |
11023 | (compare:CC (match_dup 0) | |
11024 | (const_int 0)))] | |
11025 | "") | |
1fd4e8c1 RK |
11026 | |
11027 | (define_insn "" | |
cd2b37d9 RK |
11028 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11029 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11030 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11031 | "TARGET_POWER" |
11032 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11033 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11034 | |
11035 | (define_insn "" | |
cd2b37d9 RK |
11036 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11037 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11038 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11039 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11040 | "@ |
ca7f5001 RK |
11041 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
11042 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 11043 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11044 | |
11045 | (define_insn "" | |
9ebbca7d | 11046 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11047 | (compare:CC |
9ebbca7d GK |
11048 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11049 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 11050 | (const_int 0))) |
9ebbca7d | 11051 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11052 | (ltu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11053 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11054 | "@ |
ca7f5001 | 11055 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
11056 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
11057 | # | |
11058 | #" | |
b19003d8 | 11059 | [(set_attr "type" "compare") |
9ebbca7d GK |
11060 | (set_attr "length" "12,12,16,16")]) |
11061 | ||
11062 | (define_split | |
11063 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11064 | (compare:CC | |
11065 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11066 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11067 | (const_int 0))) | |
11068 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11069 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
11070 | "! TARGET_POWERPC64 && reload_completed" | |
11071 | [(set (match_dup 0) | |
11072 | (ltu:SI (match_dup 1) (match_dup 2))) | |
11073 | (set (match_dup 3) | |
11074 | (compare:CC (match_dup 0) | |
11075 | (const_int 0)))] | |
11076 | "") | |
1fd4e8c1 RK |
11077 | |
11078 | (define_insn "" | |
19378cf8 MM |
11079 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11080 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
11081 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
11082 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI"))) | |
11083 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 11084 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11085 | "@ |
ca7f5001 | 11086 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 |
04be6346 | 11087 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
b19003d8 | 11088 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11089 | |
11090 | (define_insn "" | |
9ebbca7d | 11091 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11092 | (compare:CC |
9ebbca7d GK |
11093 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11094 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11095 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11096 | (const_int 0))) |
9ebbca7d | 11097 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11098 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11099 | "@ |
ca7f5001 | 11100 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
11101 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
11102 | # | |
11103 | #" | |
b19003d8 | 11104 | [(set_attr "type" "compare") |
9ebbca7d GK |
11105 | (set_attr "length" "12,12,16,16")]) |
11106 | ||
11107 | (define_split | |
11108 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11109 | (compare:CC | |
11110 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11111 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11112 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11113 | (const_int 0))) | |
11114 | (clobber (match_scratch:SI 4 ""))] | |
11115 | "! TARGET_POWERPC64 && reload_completed" | |
11116 | [(set (match_dup 4) | |
11117 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
11118 | (match_dup 3))) | |
11119 | (set (match_dup 0) | |
11120 | (compare:CC (match_dup 4) | |
11121 | (const_int 0)))] | |
11122 | "") | |
1fd4e8c1 RK |
11123 | |
11124 | (define_insn "" | |
9ebbca7d | 11125 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11126 | (compare:CC |
9ebbca7d GK |
11127 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11128 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11129 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11130 | (const_int 0))) |
9ebbca7d | 11131 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11132 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11133 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11134 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11135 | "@ |
ca7f5001 | 11136 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
9ebbca7d GK |
11137 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
11138 | # | |
11139 | #" | |
b19003d8 | 11140 | [(set_attr "type" "compare") |
9ebbca7d GK |
11141 | (set_attr "length" "12,12,16,16")]) |
11142 | ||
11143 | (define_split | |
11144 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11145 | (compare:CC | |
11146 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11147 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11148 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11149 | (const_int 0))) | |
11150 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11151 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11152 | (clobber (match_scratch:SI 4 ""))] | |
11153 | "! TARGET_POWERPC64 && reload_completed" | |
11154 | [(parallel [(set (match_dup 0) | |
11155 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11156 | (clobber (match_dup 4))]) | |
11157 | (set (match_dup 5) | |
11158 | (compare:CC (match_dup 0) | |
11159 | (const_int 0)))] | |
11160 | "") | |
1fd4e8c1 RK |
11161 | |
11162 | (define_insn "" | |
cd2b37d9 RK |
11163 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11164 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11165 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
f9562f27 | 11166 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11167 | "@ |
ca7f5001 RK |
11168 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
11169 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11170 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11171 | |
11172 | (define_insn "" | |
cd2b37d9 RK |
11173 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11174 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
11175 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
11176 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
11177 | "TARGET_POWER" |
11178 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 11179 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11180 | |
9ebbca7d GK |
11181 | (define_insn "" |
11182 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11183 | (compare:CC |
9ebbca7d GK |
11184 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11185 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11186 | (const_int 0))) |
9ebbca7d | 11187 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11188 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11189 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 11190 | "TARGET_POWER" |
9ebbca7d GK |
11191 | "@ |
11192 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
11193 | #" | |
11194 | [(set_attr "type" "compare") | |
11195 | (set_attr "length" "12,16")]) | |
11196 | ||
11197 | (define_split | |
11198 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11199 | (compare:CC | |
11200 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11201 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11202 | (const_int 0))) | |
11203 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11204 | (ge:SI (match_dup 1) (match_dup 2))) | |
11205 | (clobber (match_scratch:SI 3 ""))] | |
11206 | "TARGET_POWER && reload_completed" | |
11207 | [(parallel [(set (match_dup 0) | |
11208 | (ge:SI (match_dup 1) (match_dup 2))) | |
11209 | (clobber (match_dup 3))]) | |
11210 | (set (match_dup 4) | |
11211 | (compare:CC (match_dup 0) | |
11212 | (const_int 0)))] | |
11213 | "") | |
11214 | ||
1fd4e8c1 | 11215 | (define_insn "" |
cd2b37d9 RK |
11216 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11217 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11218 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11219 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11220 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11221 | "TARGET_POWER" |
11222 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" | |
b19003d8 | 11223 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11224 | |
11225 | (define_insn "" | |
9ebbca7d | 11226 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11227 | (compare:CC |
9ebbca7d GK |
11228 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11229 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11230 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11231 | (const_int 0))) |
9ebbca7d | 11232 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11233 | "TARGET_POWER" |
9ebbca7d GK |
11234 | "@ |
11235 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
11236 | #" | |
b19003d8 | 11237 | [(set_attr "type" "compare") |
9ebbca7d GK |
11238 | (set_attr "length" "12,16")]) |
11239 | ||
11240 | (define_split | |
11241 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11242 | (compare:CC | |
11243 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11244 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11245 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11246 | (const_int 0))) | |
11247 | (clobber (match_scratch:SI 4 ""))] | |
11248 | "TARGET_POWER && reload_completed" | |
11249 | [(set (match_dup 4) | |
11250 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
11251 | (match_dup 3))) | |
11252 | (set (match_dup 0) | |
11253 | (compare:CC (match_dup 4) | |
11254 | (const_int 0)))] | |
11255 | "") | |
1fd4e8c1 RK |
11256 | |
11257 | (define_insn "" | |
9ebbca7d | 11258 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11259 | (compare:CC |
9ebbca7d GK |
11260 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11261 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11262 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11263 | (const_int 0))) |
9ebbca7d | 11264 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11265 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11266 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11267 | "TARGET_POWER" |
9ebbca7d GK |
11268 | "@ |
11269 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
11270 | #" | |
b19003d8 | 11271 | [(set_attr "type" "compare") |
9ebbca7d GK |
11272 | (set_attr "length" "12,16")]) |
11273 | ||
11274 | (define_split | |
11275 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11276 | (compare:CC | |
11277 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11278 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11279 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11280 | (const_int 0))) | |
11281 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11282 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11283 | (clobber (match_scratch:SI 4 ""))] | |
11284 | "TARGET_POWER && reload_completed" | |
11285 | [(parallel [(set (match_dup 0) | |
11286 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11287 | (clobber (match_dup 4))]) | |
11288 | (set (match_dup 5) | |
11289 | (compare:CC (match_dup 0) | |
11290 | (const_int 0)))] | |
11291 | "") | |
1fd4e8c1 RK |
11292 | |
11293 | (define_insn "" | |
cd2b37d9 RK |
11294 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11295 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11296 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11297 | "TARGET_POWER" |
11298 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11299 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11300 | |
1fd4e8c1 | 11301 | (define_insn "" |
cd2b37d9 RK |
11302 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11303 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11304 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11305 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11306 | "@ |
ca7f5001 RK |
11307 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
11308 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 11309 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11310 | |
f9562f27 DE |
11311 | (define_insn "" |
11312 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
11313 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
11314 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
11315 | "TARGET_POWERPC64" | |
11316 | "@ | |
11317 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
11318 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
11319 | [(set_attr "length" "12")]) | |
11320 | ||
1fd4e8c1 | 11321 | (define_insn "" |
9ebbca7d | 11322 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11323 | (compare:CC |
9ebbca7d GK |
11324 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11325 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 11326 | (const_int 0))) |
9ebbca7d | 11327 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11328 | (geu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11329 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11330 | "@ |
ca7f5001 | 11331 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
11332 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
11333 | # | |
11334 | #" | |
b19003d8 | 11335 | [(set_attr "type" "compare") |
9ebbca7d GK |
11336 | (set_attr "length" "12,12,16,16")]) |
11337 | ||
11338 | (define_split | |
11339 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11340 | (compare:CC | |
11341 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11342 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11343 | (const_int 0))) | |
11344 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11345 | (geu:SI (match_dup 1) (match_dup 2)))] | |
11346 | "! TARGET_POWERPC64 && reload_completed" | |
11347 | [(set (match_dup 0) | |
11348 | (geu:SI (match_dup 1) (match_dup 2))) | |
11349 | (set (match_dup 3) | |
11350 | (compare:CC (match_dup 0) | |
11351 | (const_int 0)))] | |
11352 | "") | |
1fd4e8c1 | 11353 | |
f9562f27 | 11354 | (define_insn "" |
9ebbca7d | 11355 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 11356 | (compare:CC |
9ebbca7d GK |
11357 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
11358 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 11359 | (const_int 0))) |
9ebbca7d | 11360 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 DE |
11361 | (geu:DI (match_dup 1) (match_dup 2)))] |
11362 | "TARGET_POWERPC64" | |
11363 | "@ | |
11364 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
11365 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
11366 | # | |
11367 | #" | |
f9562f27 | 11368 | [(set_attr "type" "compare") |
9ebbca7d GK |
11369 | (set_attr "length" "12,12,16,16")]) |
11370 | ||
11371 | (define_split | |
11372 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11373 | (compare:CC | |
11374 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11375 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
11376 | (const_int 0))) | |
11377 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11378 | (geu:DI (match_dup 1) (match_dup 2)))] | |
11379 | "TARGET_POWERPC64 && reload_completed" | |
11380 | [(set (match_dup 0) | |
11381 | (geu:DI (match_dup 1) (match_dup 2))) | |
11382 | (set (match_dup 3) | |
11383 | (compare:CC (match_dup 0) | |
11384 | (const_int 0)))] | |
11385 | "") | |
f9562f27 | 11386 | |
1fd4e8c1 | 11387 | (define_insn "" |
cd2b37d9 RK |
11388 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11389 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11390 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 11391 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11392 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11393 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11394 | "@ |
ca7f5001 RK |
11395 | {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 |
11396 | {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 11397 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11398 | |
11399 | (define_insn "" | |
9ebbca7d | 11400 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11401 | (compare:CC |
9ebbca7d GK |
11402 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11403 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11404 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11405 | (const_int 0))) |
9ebbca7d | 11406 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11407 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11408 | "@ |
ca7f5001 | 11409 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11410 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
11411 | # | |
11412 | #" | |
b19003d8 | 11413 | [(set_attr "type" "compare") |
9ebbca7d GK |
11414 | (set_attr "length" "8,8,12,12")]) |
11415 | ||
11416 | (define_split | |
11417 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11418 | (compare:CC | |
11419 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11420 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11421 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11422 | (const_int 0))) | |
11423 | (clobber (match_scratch:SI 4 ""))] | |
11424 | "! TARGET_POWERPC64 && reload_completed" | |
11425 | [(set (match_dup 4) | |
11426 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
11427 | (match_dup 3))) | |
11428 | (set (match_dup 0) | |
11429 | (compare:CC (match_dup 4) | |
11430 | (const_int 0)))] | |
11431 | "") | |
1fd4e8c1 RK |
11432 | |
11433 | (define_insn "" | |
9ebbca7d | 11434 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11435 | (compare:CC |
9ebbca7d GK |
11436 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11437 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11438 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11439 | (const_int 0))) |
9ebbca7d | 11440 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11441 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11442 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11443 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11444 | "@ |
ca7f5001 | 11445 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
11446 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3 |
11447 | # | |
11448 | #" | |
b19003d8 | 11449 | [(set_attr "type" "compare") |
9ebbca7d GK |
11450 | (set_attr "length" "8,8,12,12")]) |
11451 | ||
11452 | (define_split | |
11453 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11454 | (compare:CC | |
11455 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11456 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11457 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11458 | (const_int 0))) | |
11459 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11460 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11461 | (clobber (match_scratch:SI 4 ""))] | |
11462 | "! TARGET_POWERPC64 && reload_completed" | |
11463 | [(parallel [(set (match_dup 0) | |
11464 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11465 | (clobber (match_dup 4))]) | |
11466 | (set (match_dup 5) | |
11467 | (compare:CC (match_dup 0) | |
11468 | (const_int 0)))] | |
11469 | "") | |
1fd4e8c1 RK |
11470 | |
11471 | (define_insn "" | |
cd2b37d9 RK |
11472 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11473 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11474 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
f9562f27 | 11475 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11476 | "@ |
ca7f5001 | 11477 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 11478 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 11479 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11480 | |
11481 | (define_insn "" | |
cd2b37d9 | 11482 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11483 | (and:SI (neg:SI |
cd2b37d9 | 11484 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11485 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 11486 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11487 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11488 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11489 | "@ |
ca7f5001 RK |
11490 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 |
11491 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" | |
b19003d8 | 11492 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11493 | |
11494 | (define_insn "" | |
9ebbca7d | 11495 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
11496 | (compare:CC |
11497 | (and:SI (neg:SI | |
9ebbca7d GK |
11498 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11499 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
11500 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11501 | (const_int 0))) |
9ebbca7d | 11502 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11503 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11504 | "@ |
ca7f5001 | 11505 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
11506 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
11507 | # | |
11508 | #" | |
b19003d8 | 11509 | [(set_attr "type" "compare") |
9ebbca7d GK |
11510 | (set_attr "length" "12,12,16,16")]) |
11511 | ||
11512 | (define_split | |
11513 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11514 | (compare:CC | |
11515 | (and:SI (neg:SI | |
11516 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11517 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
11518 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11519 | (const_int 0))) | |
11520 | (clobber (match_scratch:SI 4 ""))] | |
11521 | "! TARGET_POWERPC64 && reload_completed" | |
11522 | [(set (match_dup 4) | |
11523 | (and:SI (neg:SI (geu:SI (match_dup 1) | |
11524 | (match_dup 2))) | |
11525 | (match_dup 3))) | |
11526 | (set (match_dup 0) | |
11527 | (compare:CC (match_dup 4) | |
11528 | (const_int 0)))] | |
11529 | "") | |
1fd4e8c1 RK |
11530 | |
11531 | (define_insn "" | |
9ebbca7d | 11532 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
11533 | (compare:CC |
11534 | (and:SI (neg:SI | |
9ebbca7d GK |
11535 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11536 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
11537 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11538 | (const_int 0))) |
9ebbca7d | 11539 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11540 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 11541 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11542 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11543 | "@ |
ca7f5001 | 11544 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
9ebbca7d GK |
11545 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
11546 | # | |
11547 | #" | |
b19003d8 | 11548 | [(set_attr "type" "compare") |
9ebbca7d GK |
11549 | (set_attr "length" "12,12,16,16")]) |
11550 | ||
11551 | (define_split | |
11552 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11553 | (compare:CC | |
11554 | (and:SI (neg:SI | |
11555 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11556 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
11557 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11558 | (const_int 0))) | |
11559 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11560 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11561 | (clobber (match_scratch:SI 4 ""))] | |
11562 | "! TARGET_POWERPC64 && reload_completed" | |
11563 | [(parallel [(set (match_dup 0) | |
11564 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11565 | (clobber (match_dup 4))]) | |
11566 | (set (match_dup 5) | |
11567 | (compare:CC (match_dup 0) | |
11568 | (const_int 0)))] | |
11569 | "") | |
1fd4e8c1 RK |
11570 | |
11571 | (define_insn "" | |
cd2b37d9 RK |
11572 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11573 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11574 | (const_int 0)))] |
f9562f27 | 11575 | "! TARGET_POWERPC64" |
ca7f5001 | 11576 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11577 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11578 | |
f9562f27 DE |
11579 | (define_insn "" |
11580 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11581 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11582 | (const_int 0)))] | |
11583 | "TARGET_POWERPC64" | |
11584 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" | |
11585 | [(set_attr "length" "12")]) | |
11586 | ||
1fd4e8c1 | 11587 | (define_insn "" |
9ebbca7d | 11588 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11589 | (compare:CC |
9ebbca7d | 11590 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
11591 | (const_int 0)) |
11592 | (const_int 0))) | |
9ebbca7d | 11593 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11594 | (gt:SI (match_dup 1) (const_int 0)))] |
f9562f27 | 11595 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11596 | "@ |
11597 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
11598 | #" | |
29ae5b89 | 11599 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11600 | (set_attr "length" "12,16")]) |
11601 | ||
11602 | (define_split | |
11603 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
11604 | (compare:CC | |
11605 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11606 | (const_int 0)) | |
11607 | (const_int 0))) | |
11608 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11609 | (gt:SI (match_dup 1) (const_int 0)))] | |
11610 | "! TARGET_POWERPC64 && reload_completed" | |
11611 | [(set (match_dup 0) | |
11612 | (gt:SI (match_dup 1) (const_int 0))) | |
11613 | (set (match_dup 2) | |
11614 | (compare:CC (match_dup 0) | |
11615 | (const_int 0)))] | |
11616 | "") | |
1fd4e8c1 | 11617 | |
f9562f27 | 11618 | (define_insn "" |
9ebbca7d | 11619 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 11620 | (compare:CC |
9ebbca7d | 11621 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
11622 | (const_int 0)) |
11623 | (const_int 0))) | |
9ebbca7d | 11624 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11625 | (gt:DI (match_dup 1) (const_int 0)))] |
11626 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11627 | "@ |
11628 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
11629 | #" | |
f9562f27 | 11630 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11631 | (set_attr "length" "12,16")]) |
11632 | ||
11633 | (define_split | |
11634 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
11635 | (compare:CC | |
11636 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11637 | (const_int 0)) | |
11638 | (const_int 0))) | |
11639 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11640 | (gt:DI (match_dup 1) (const_int 0)))] | |
11641 | "TARGET_POWERPC64 && reload_completed" | |
11642 | [(set (match_dup 0) | |
11643 | (gt:DI (match_dup 1) (const_int 0))) | |
11644 | (set (match_dup 2) | |
11645 | (compare:CC (match_dup 0) | |
11646 | (const_int 0)))] | |
11647 | "") | |
f9562f27 | 11648 | |
1fd4e8c1 | 11649 | (define_insn "" |
cd2b37d9 RK |
11650 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11651 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11652 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
11653 | "TARGET_POWER" |
11654 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 11655 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11656 | |
11657 | (define_insn "" | |
9ebbca7d | 11658 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11659 | (compare:CC |
9ebbca7d GK |
11660 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11661 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 11662 | (const_int 0))) |
9ebbca7d | 11663 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11664 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11665 | "TARGET_POWER" |
9ebbca7d GK |
11666 | "@ |
11667 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11668 | #" | |
29ae5b89 | 11669 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11670 | (set_attr "length" "12,16")]) |
11671 | ||
11672 | (define_split | |
11673 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11674 | (compare:CC | |
11675 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11676 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11677 | (const_int 0))) | |
11678 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11679 | (gt:SI (match_dup 1) (match_dup 2)))] | |
11680 | "TARGET_POWER && reload_completed" | |
11681 | [(set (match_dup 0) | |
11682 | (gt:SI (match_dup 1) (match_dup 2))) | |
11683 | (set (match_dup 3) | |
11684 | (compare:CC (match_dup 0) | |
11685 | (const_int 0)))] | |
11686 | "") | |
1fd4e8c1 RK |
11687 | |
11688 | (define_insn "" | |
cd2b37d9 RK |
11689 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11690 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11691 | (const_int 0)) |
cd2b37d9 | 11692 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11693 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 11694 | "! TARGET_POWERPC64" |
ca7f5001 | 11695 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" |
b19003d8 | 11696 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11697 | |
f9562f27 DE |
11698 | (define_insn "" |
11699 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11700 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11701 | (const_int 0)) | |
11702 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11703 | (clobber (match_scratch:DI 3 "=&r"))] | |
11704 | "TARGET_POWERPC64" | |
11705 | "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2" | |
11706 | [(set_attr "length" "12")]) | |
11707 | ||
1fd4e8c1 | 11708 | (define_insn "" |
9ebbca7d | 11709 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11710 | (compare:CC |
9ebbca7d | 11711 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11712 | (const_int 0)) |
9ebbca7d | 11713 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11714 | (const_int 0))) |
9ebbca7d | 11715 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 11716 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11717 | "@ |
11718 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
11719 | #" | |
b19003d8 | 11720 | [(set_attr "type" "compare") |
9ebbca7d GK |
11721 | (set_attr "length" "12,16")]) |
11722 | ||
11723 | (define_split | |
11724 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11725 | (compare:CC | |
11726 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11727 | (const_int 0)) | |
11728 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11729 | (const_int 0))) | |
11730 | (clobber (match_scratch:SI 3 ""))] | |
11731 | "! TARGET_POWERPC64 && reload_completed" | |
11732 | [(set (match_dup 3) | |
11733 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
11734 | (match_dup 2))) | |
11735 | (set (match_dup 0) | |
11736 | (compare:CC (match_dup 3) | |
11737 | (const_int 0)))] | |
11738 | "") | |
1fd4e8c1 | 11739 | |
f9562f27 | 11740 | (define_insn "" |
9ebbca7d | 11741 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 11742 | (compare:CC |
9ebbca7d | 11743 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 11744 | (const_int 0)) |
9ebbca7d | 11745 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 11746 | (const_int 0))) |
9ebbca7d | 11747 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 11748 | "TARGET_POWERPC64" |
9ebbca7d GK |
11749 | "@ |
11750 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
11751 | #" | |
f9562f27 | 11752 | [(set_attr "type" "compare") |
9ebbca7d GK |
11753 | (set_attr "length" "12,16")]) |
11754 | ||
11755 | (define_split | |
11756 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11757 | (compare:CC | |
11758 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11759 | (const_int 0)) | |
11760 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11761 | (const_int 0))) | |
11762 | (clobber (match_scratch:DI 3 ""))] | |
11763 | "TARGET_POWERPC64 && reload_completed" | |
11764 | [(set (match_dup 3) | |
11765 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
11766 | (match_dup 2))) | |
11767 | (set (match_dup 0) | |
11768 | (compare:CC (match_dup 3) | |
11769 | (const_int 0)))] | |
11770 | "") | |
f9562f27 | 11771 | |
1fd4e8c1 | 11772 | (define_insn "" |
9ebbca7d GK |
11773 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
11774 | (compare:CC | |
11775 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
11776 | (const_int 0)) | |
11777 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
11778 | (const_int 0))) | |
11779 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
11780 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11781 | (clobber (match_scratch:SI 3 "=&r,&r"))] | |
11782 | "! TARGET_POWERPC64" | |
11783 | "@ | |
11784 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2 | |
11785 | #" | |
11786 | [(set_attr "type" "compare") | |
11787 | (set_attr "length" "12,16")]) | |
11788 | ||
11789 | (define_split | |
11790 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
1fd4e8c1 | 11791 | (compare:CC |
9ebbca7d | 11792 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11793 | (const_int 0)) |
9ebbca7d | 11794 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 11795 | (const_int 0))) |
9ebbca7d | 11796 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 11797 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d GK |
11798 | (clobber (match_scratch:SI 3 ""))] |
11799 | "! TARGET_POWERPC64 && reload_completed" | |
11800 | [(parallel [(set (match_dup 0) | |
11801 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11802 | (clobber (match_dup 3))]) | |
11803 | (set (match_dup 4) | |
11804 | (compare:CC (match_dup 0) | |
11805 | (const_int 0)))] | |
11806 | "") | |
1fd4e8c1 | 11807 | |
f9562f27 | 11808 | (define_insn "" |
9ebbca7d | 11809 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
f9562f27 | 11810 | (compare:CC |
9ebbca7d | 11811 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 11812 | (const_int 0)) |
9ebbca7d | 11813 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 11814 | (const_int 0))) |
9ebbca7d | 11815 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 11816 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d | 11817 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 11818 | "TARGET_POWERPC64" |
9ebbca7d GK |
11819 | "@ |
11820 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2 | |
11821 | #" | |
f9562f27 | 11822 | [(set_attr "type" "compare") |
9ebbca7d GK |
11823 | (set_attr "length" "12,16")]) |
11824 | ||
11825 | (define_split | |
11826 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11827 | (compare:CC | |
11828 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11829 | (const_int 0)) | |
11830 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11831 | (const_int 0))) | |
11832 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11833 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11834 | (clobber (match_scratch:DI 3 ""))] | |
11835 | "TARGET_POWERPC64 && reload_completed" | |
11836 | [(parallel [(set (match_dup 0) | |
11837 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11838 | (clobber (match_dup 3))]) | |
11839 | (set (match_dup 4) | |
11840 | (compare:CC (match_dup 0) | |
11841 | (const_int 0)))] | |
11842 | "") | |
f9562f27 | 11843 | |
1fd4e8c1 | 11844 | (define_insn "" |
cd2b37d9 RK |
11845 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11846 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11847 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 11848 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11849 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11850 | "TARGET_POWER" |
11851 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 11852 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11853 | |
11854 | (define_insn "" | |
9ebbca7d | 11855 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11856 | (compare:CC |
9ebbca7d GK |
11857 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11858 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
11859 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11860 | (const_int 0))) |
9ebbca7d | 11861 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11862 | "TARGET_POWER" |
9ebbca7d GK |
11863 | "@ |
11864 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
11865 | #" | |
b19003d8 | 11866 | [(set_attr "type" "compare") |
9ebbca7d GK |
11867 | (set_attr "length" "12,16")]) |
11868 | ||
11869 | (define_split | |
11870 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11871 | (compare:CC | |
11872 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11873 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11874 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11875 | (const_int 0))) | |
11876 | (clobber (match_scratch:SI 4 ""))] | |
11877 | "TARGET_POWER && reload_completed" | |
11878 | [(set (match_dup 4) | |
11879 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) | |
11880 | (match_dup 3))) | |
11881 | (set (match_dup 0) | |
11882 | (compare:CC (match_dup 4) | |
11883 | (const_int 0)))] | |
11884 | "") | |
1fd4e8c1 RK |
11885 | |
11886 | (define_insn "" | |
9ebbca7d | 11887 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11888 | (compare:CC |
9ebbca7d GK |
11889 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11890 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
11891 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11892 | (const_int 0))) |
9ebbca7d | 11893 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11894 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11895 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11896 | "TARGET_POWER" |
9ebbca7d GK |
11897 | "@ |
11898 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
11899 | #" | |
b19003d8 | 11900 | [(set_attr "type" "compare") |
9ebbca7d GK |
11901 | (set_attr "length" "12,16")]) |
11902 | ||
11903 | (define_split | |
11904 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11905 | (compare:CC | |
11906 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11907 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11908 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11909 | (const_int 0))) | |
11910 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11911 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11912 | (clobber (match_scratch:SI 4 ""))] | |
11913 | "TARGET_POWER && reload_completed" | |
11914 | [(parallel [(set (match_dup 0) | |
11915 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11916 | (clobber (match_dup 4))]) | |
11917 | (set (match_dup 5) | |
11918 | (compare:CC (match_dup 0) | |
11919 | (const_int 0)))] | |
11920 | "") | |
1fd4e8c1 RK |
11921 | |
11922 | (define_insn "" | |
cd2b37d9 RK |
11923 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11924 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11925 | (const_int 0))))] |
f9562f27 | 11926 | "! TARGET_POWERPC64" |
ca7f5001 | 11927 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 11928 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11929 | |
f9562f27 DE |
11930 | (define_insn "" |
11931 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11932 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11933 | (const_int 0))))] | |
11934 | "TARGET_POWERPC64" | |
11935 | "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63" | |
11936 | [(set_attr "length" "12")]) | |
11937 | ||
1fd4e8c1 | 11938 | (define_insn "" |
cd2b37d9 RK |
11939 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11940 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11941 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
11942 | "TARGET_POWER" |
11943 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11944 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11945 | |
11946 | (define_insn "" | |
cd2b37d9 RK |
11947 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11948 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11949 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 11950 | "! TARGET_POWERPC64" |
ca7f5001 | 11951 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 11952 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11953 | |
f9562f27 DE |
11954 | (define_insn "" |
11955 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11956 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11957 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11958 | "TARGET_POWERPC64" | |
11959 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" | |
11960 | [(set_attr "length" "12")]) | |
11961 | ||
1fd4e8c1 | 11962 | (define_insn "" |
9ebbca7d | 11963 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11964 | (compare:CC |
9ebbca7d GK |
11965 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11966 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11967 | (const_int 0))) |
9ebbca7d | 11968 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11969 | (gtu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11970 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11971 | "@ |
11972 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
11973 | #" | |
b19003d8 | 11974 | [(set_attr "type" "compare") |
9ebbca7d GK |
11975 | (set_attr "length" "12,16")]) |
11976 | ||
11977 | (define_split | |
11978 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11979 | (compare:CC | |
11980 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11981 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11982 | (const_int 0))) | |
11983 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11984 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
11985 | "! TARGET_POWERPC64 && reload_completed" | |
11986 | [(set (match_dup 0) | |
11987 | (gtu:SI (match_dup 1) (match_dup 2))) | |
11988 | (set (match_dup 3) | |
11989 | (compare:CC (match_dup 0) | |
11990 | (const_int 0)))] | |
11991 | "") | |
1fd4e8c1 | 11992 | |
f9562f27 | 11993 | (define_insn "" |
9ebbca7d | 11994 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11995 | (compare:CC |
9ebbca7d GK |
11996 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11997 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11998 | (const_int 0))) |
9ebbca7d | 11999 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12000 | (gtu:DI (match_dup 1) (match_dup 2)))] |
12001 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12002 | "@ |
12003 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
12004 | #" | |
f9562f27 | 12005 | [(set_attr "type" "compare") |
9ebbca7d GK |
12006 | (set_attr "length" "12,16")]) |
12007 | ||
12008 | (define_split | |
12009 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12010 | (compare:CC | |
12011 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12012 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12013 | (const_int 0))) | |
12014 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12015 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
12016 | "TARGET_POWERPC64 && reload_completed" | |
12017 | [(set (match_dup 0) | |
12018 | (gtu:DI (match_dup 1) (match_dup 2))) | |
12019 | (set (match_dup 3) | |
12020 | (compare:CC (match_dup 0) | |
12021 | (const_int 0)))] | |
12022 | "") | |
f9562f27 | 12023 | |
1fd4e8c1 | 12024 | (define_insn "" |
19378cf8 MM |
12025 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12026 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12027 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
12028 | (match_operand:SI 3 "reg_or_short_operand" "r,rI"))) | |
12029 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 12030 | "! TARGET_POWERPC64" |
00751805 | 12031 | "@ |
ca7f5001 | 12032 | {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 |
ca7f5001 | 12033 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
19378cf8 | 12034 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 12035 | |
f9562f27 DE |
12036 | (define_insn "" |
12037 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12038 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12039 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
12040 | (match_operand:DI 3 "reg_or_short_operand" "r,rI"))) | |
12041 | (clobber (match_scratch:DI 4 "=&r,&r"))] | |
12042 | "TARGET_POWERPC64" | |
12043 | "@ | |
12044 | addic %4,%1,%k2\;addze %0,%3 | |
12045 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3" | |
12046 | [(set_attr "length" "8,12")]) | |
12047 | ||
1fd4e8c1 | 12048 | (define_insn "" |
9ebbca7d | 12049 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12050 | (compare:CC |
9ebbca7d GK |
12051 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12052 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
12053 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12054 | (const_int 0))) |
9ebbca7d | 12055 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12056 | "! TARGET_POWERPC64" |
00751805 | 12057 | "@ |
19378cf8 | 12058 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12059 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12060 | # | |
12061 | #" | |
b19003d8 | 12062 | [(set_attr "type" "compare") |
9ebbca7d GK |
12063 | (set_attr "length" "8,12,12,16")]) |
12064 | ||
12065 | (define_split | |
12066 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12067 | (compare:CC | |
12068 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12069 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12070 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12071 | (const_int 0))) | |
12072 | (clobber (match_scratch:SI 4 ""))] | |
12073 | "! TARGET_POWERPC64 && reload_completed" | |
12074 | [(set (match_dup 4) | |
12075 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
12076 | (match_dup 3))) | |
12077 | (set (match_dup 0) | |
12078 | (compare:CC (match_dup 4) | |
12079 | (const_int 0)))] | |
12080 | "") | |
1fd4e8c1 | 12081 | |
f9562f27 | 12082 | (define_insn "" |
9ebbca7d | 12083 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12084 | (compare:CC |
9ebbca7d GK |
12085 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12086 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
12087 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12088 | (const_int 0))) |
9ebbca7d | 12089 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
12090 | "TARGET_POWERPC64" |
12091 | "@ | |
12092 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
12093 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
12094 | # | |
12095 | #" | |
f9562f27 | 12096 | [(set_attr "type" "compare") |
9ebbca7d GK |
12097 | (set_attr "length" "8,12,12,16")]) |
12098 | ||
12099 | (define_split | |
12100 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12101 | (compare:CC | |
12102 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12103 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12104 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
12105 | (const_int 0))) | |
12106 | (clobber (match_scratch:DI 4 ""))] | |
12107 | "TARGET_POWERPC64 && reload_completed" | |
12108 | [(set (match_dup 4) | |
12109 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
12110 | (match_dup 3))) | |
12111 | (set (match_dup 0) | |
12112 | (compare:CC (match_dup 4) | |
12113 | (const_int 0)))] | |
12114 | "") | |
f9562f27 | 12115 | |
1fd4e8c1 | 12116 | (define_insn "" |
9ebbca7d | 12117 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12118 | (compare:CC |
9ebbca7d GK |
12119 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12120 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
12121 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12122 | (const_int 0))) |
9ebbca7d | 12123 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12124 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12125 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12126 | "! TARGET_POWERPC64" |
00751805 | 12127 | "@ |
ca7f5001 | 12128 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
12129 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
12130 | # | |
12131 | #" | |
b19003d8 | 12132 | [(set_attr "type" "compare") |
9ebbca7d GK |
12133 | (set_attr "length" "8,12,12,16")]) |
12134 | ||
12135 | (define_split | |
12136 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12137 | (compare:CC | |
12138 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12139 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12140 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12141 | (const_int 0))) | |
12142 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12143 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12144 | (clobber (match_scratch:SI 4 ""))] | |
12145 | "! TARGET_POWERPC64 && reload_completed" | |
12146 | [(parallel [(set (match_dup 0) | |
12147 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12148 | (clobber (match_dup 4))]) | |
12149 | (set (match_dup 5) | |
12150 | (compare:CC (match_dup 0) | |
12151 | (const_int 0)))] | |
12152 | "") | |
1fd4e8c1 | 12153 | |
f9562f27 | 12154 | (define_insn "" |
9ebbca7d | 12155 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12156 | (compare:CC |
9ebbca7d GK |
12157 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12158 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
12159 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12160 | (const_int 0))) |
9ebbca7d | 12161 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12162 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12163 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
12164 | "TARGET_POWERPC64" |
12165 | "@ | |
12166 | addic %4,%1,%k2\;addze. %0,%3 | |
9ebbca7d GK |
12167 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3 |
12168 | # | |
12169 | #" | |
f9562f27 | 12170 | [(set_attr "type" "compare") |
9ebbca7d GK |
12171 | (set_attr "length" "8,12,12,16")]) |
12172 | ||
12173 | (define_split | |
12174 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12175 | (compare:CC | |
12176 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12177 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12178 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
12179 | (const_int 0))) | |
12180 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12181 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12182 | (clobber (match_scratch:DI 4 ""))] | |
12183 | "TARGET_POWERPC64 && reload_completed" | |
12184 | [(parallel [(set (match_dup 0) | |
12185 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12186 | (clobber (match_dup 4))]) | |
12187 | (set (match_dup 5) | |
12188 | (compare:CC (match_dup 0) | |
12189 | (const_int 0)))] | |
12190 | "") | |
f9562f27 | 12191 | |
1fd4e8c1 | 12192 | (define_insn "" |
cd2b37d9 RK |
12193 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12194 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12195 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 12196 | "! TARGET_POWERPC64" |
ca7f5001 | 12197 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12198 | [(set_attr "length" "8")]) |
f9562f27 DE |
12199 | |
12200 | (define_insn "" | |
12201 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12202 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12203 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
12204 | "TARGET_POWERPC64" | |
12205 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" | |
12206 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
12207 | \f |
12208 | ;; Define both directions of branch and return. If we need a reload | |
12209 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
12210 | ;; register CC value to there. | |
12211 | ||
12212 | (define_insn "" | |
12213 | [(set (pc) | |
12214 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12215 | [(match_operand 2 | |
12216 | "cc_reg_operand" "x,?y") | |
12217 | (const_int 0)]) | |
12218 | (label_ref (match_operand 0 "" "")) | |
12219 | (pc)))] | |
12220 | "" | |
b19003d8 RK |
12221 | "* |
12222 | { | |
12a4e8c5 | 12223 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
12224 | }" |
12225 | [(set_attr "type" "branch")]) | |
12226 | ||
1fd4e8c1 RK |
12227 | (define_insn "" |
12228 | [(set (pc) | |
12229 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12230 | [(match_operand 1 | |
12231 | "cc_reg_operand" "x,?y") | |
12232 | (const_int 0)]) | |
12233 | (return) | |
12234 | (pc)))] | |
12235 | "direct_return ()" | |
12a4e8c5 GK |
12236 | "* |
12237 | { | |
12238 | return output_cbranch (operands[0], NULL, 0, insn); | |
12239 | }" | |
b7ff3d82 | 12240 | [(set_attr "type" "branch") |
39a10a29 | 12241 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
12242 | |
12243 | (define_insn "" | |
12244 | [(set (pc) | |
12245 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12246 | [(match_operand 2 | |
12247 | "cc_reg_operand" "x,?y") | |
12248 | (const_int 0)]) | |
12249 | (pc) | |
12250 | (label_ref (match_operand 0 "" ""))))] | |
12251 | "" | |
b19003d8 RK |
12252 | "* |
12253 | { | |
12a4e8c5 | 12254 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
12255 | }" |
12256 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12257 | |
12258 | (define_insn "" | |
12259 | [(set (pc) | |
12260 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12261 | [(match_operand 1 | |
12262 | "cc_reg_operand" "x,?y") | |
12263 | (const_int 0)]) | |
12264 | (pc) | |
12265 | (return)))] | |
12266 | "direct_return ()" | |
12a4e8c5 GK |
12267 | "* |
12268 | { | |
12269 | return output_cbranch (operands[0], NULL, 1, insn); | |
12270 | }" | |
b7ff3d82 | 12271 | [(set_attr "type" "branch") |
39a10a29 GK |
12272 | (set_attr "length" "4")]) |
12273 | ||
12274 | ;; Logic on condition register values. | |
12275 | ||
12276 | ; This pattern matches things like | |
12277 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
12278 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
12279 | ; (const_int 1))) | |
12280 | ; which are generated by the branch logic. | |
12281 | ||
12282 | (define_insn "" | |
12283 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12284 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" | |
12285 | [(match_operator:SI 2 | |
12286 | "branch_positive_comparison_operator" | |
12287 | [(match_operand 3 | |
12288 | "cc_reg_operand" "y") | |
12289 | (const_int 0)]) | |
12290 | (match_operator:SI 4 | |
12291 | "branch_positive_comparison_operator" | |
12292 | [(match_operand 5 | |
12293 | "cc_reg_operand" "y") | |
12294 | (const_int 0)])]) | |
12295 | (const_int 1)))] | |
12296 | "" | |
12297 | "cr%q1 %E0,%j2,%j4" | |
12298 | [(set_attr "type" "cr_logical")]) | |
12299 | ||
12300 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
12301 | ; Because ~1 has all but the low bit set. | |
12302 | (define_insn "" | |
12303 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12304 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" | |
12305 | [(not:SI (match_operator:SI 2 | |
12306 | "branch_positive_comparison_operator" | |
12307 | [(match_operand 3 | |
12308 | "cc_reg_operand" "y") | |
12309 | (const_int 0)])) | |
12310 | (match_operator:SI 4 | |
12311 | "branch_positive_comparison_operator" | |
12312 | [(match_operand 5 | |
12313 | "cc_reg_operand" "y") | |
12314 | (const_int 0)])]) | |
12315 | (const_int -1)))] | |
12316 | "" | |
12317 | "cr%q1 %E0,%j2,%j4" | |
12318 | [(set_attr "type" "cr_logical")]) | |
12319 | ||
12320 | (define_insn "" | |
12321 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
6c873122 | 12322 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 12323 | "branch_positive_comparison_operator" |
6c873122 | 12324 | [(match_operand 2 |
39a10a29 GK |
12325 | "cc_reg_operand" "y") |
12326 | (const_int 0)]) | |
12327 | (const_int 0)))] | |
12328 | "" | |
251b3667 | 12329 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
39a10a29 GK |
12330 | [(set_attr "type" "cr_logical")]) |
12331 | ||
12332 | ;; If we are comparing the result of two comparisons, this can be done | |
12333 | ;; using creqv or crxor. | |
12334 | ||
12335 | (define_insn_and_split "" | |
12336 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12337 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
12338 | [(match_operand 2 "cc_reg_operand" "y") | |
12339 | (const_int 0)]) | |
12340 | (match_operator 3 "branch_comparison_operator" | |
12341 | [(match_operand 4 "cc_reg_operand" "y") | |
12342 | (const_int 0)])))] | |
12343 | "" | |
12344 | "#" | |
12345 | "" | |
12346 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
12347 | (match_dup 5)))] | |
12348 | " | |
12349 | { | |
12350 | int positive_1, positive_2; | |
12351 | ||
12352 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
12353 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
12354 | ||
12355 | if (! positive_1) | |
12356 | operands[1] = gen_rtx (SImode, | |
12357 | rs6000_reverse_condition (GET_MODE (operands[2]), | |
12358 | GET_CODE (operands[1])), | |
12359 | operands[2]); | |
12360 | else if (GET_MODE (operands[1]) != SImode) | |
12361 | operands[1] = gen_rtx (SImode, | |
12362 | GET_CODE (operands[1]), | |
12363 | operands[2]); | |
12364 | ||
12365 | if (! positive_2) | |
12366 | operands[3] = gen_rtx (SImode, | |
12367 | rs6000_reverse_condition (GET_MODE (operands[4]), | |
12368 | GET_CODE (operands[3])), | |
12369 | operands[4]); | |
12370 | else if (GET_MODE (operands[3]) != SImode) | |
12371 | operands[3] = gen_rtx (SImode, | |
12372 | GET_CODE (operands[3]), | |
12373 | operands[4]); | |
12374 | ||
12375 | if (positive_1 == positive_2) | |
251b3667 DE |
12376 | { |
12377 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
12378 | operands[5] = constm1_rtx; | |
12379 | } | |
12380 | else | |
12381 | { | |
12382 | operands[5] = const1_rtx; | |
12383 | } | |
39a10a29 | 12384 | }") |
1fd4e8c1 RK |
12385 | |
12386 | ;; Unconditional branch and return. | |
12387 | ||
12388 | (define_insn "jump" | |
12389 | [(set (pc) | |
12390 | (label_ref (match_operand 0 "" "")))] | |
12391 | "" | |
b7ff3d82 DE |
12392 | "b %l0" |
12393 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12394 | |
12395 | (define_insn "return" | |
12396 | [(return)] | |
12397 | "direct_return ()" | |
324e52cc TG |
12398 | "{br|blr}" |
12399 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 12400 | |
0ad91047 DE |
12401 | (define_expand "indirect_jump" |
12402 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 12403 | "" |
0ad91047 DE |
12404 | " |
12405 | { | |
12406 | if (TARGET_32BIT) | |
12407 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
12408 | else | |
12409 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
12410 | DONE; | |
12411 | }") | |
12412 | ||
12413 | (define_insn "indirect_jumpsi" | |
cccf3bdc | 12414 | [(set (pc) (match_operand:SI 0 "register_operand" "cl"))] |
0ad91047 | 12415 | "TARGET_32BIT" |
cccf3bdc | 12416 | "b%T0" |
324e52cc | 12417 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 12418 | |
0ad91047 | 12419 | (define_insn "indirect_jumpdi" |
cccf3bdc | 12420 | [(set (pc) (match_operand:DI 0 "register_operand" "cl"))] |
0ad91047 | 12421 | "TARGET_64BIT" |
cccf3bdc | 12422 | "b%T0" |
266eb58a DE |
12423 | [(set_attr "type" "jmpreg")]) |
12424 | ||
1fd4e8c1 RK |
12425 | ;; Table jump for switch statements: |
12426 | (define_expand "tablejump" | |
e6ca2c17 DE |
12427 | [(use (match_operand 0 "" "")) |
12428 | (use (label_ref (match_operand 1 "" "")))] | |
12429 | "" | |
12430 | " | |
12431 | { | |
12432 | if (TARGET_32BIT) | |
12433 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
12434 | else | |
12435 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
12436 | DONE; | |
12437 | }") | |
12438 | ||
12439 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
12440 | [(set (match_dup 3) |
12441 | (plus:SI (match_operand:SI 0 "" "") | |
12442 | (match_dup 2))) | |
12443 | (parallel [(set (pc) (match_dup 3)) | |
12444 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 12445 | "TARGET_32BIT" |
1fd4e8c1 RK |
12446 | " |
12447 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 12448 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
12449 | operands[3] = gen_reg_rtx (SImode); |
12450 | }") | |
12451 | ||
e6ca2c17 | 12452 | (define_expand "tablejumpdi" |
9ebbca7d GK |
12453 | [(set (match_dup 4) |
12454 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) | |
12455 | (set (match_dup 3) | |
12456 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
12457 | (match_dup 2))) |
12458 | (parallel [(set (pc) (match_dup 3)) | |
12459 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 12460 | "TARGET_64BIT" |
e6ca2c17 | 12461 | " |
9ebbca7d | 12462 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 12463 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 12464 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
12465 | }") |
12466 | ||
1fd4e8c1 RK |
12467 | (define_insn "" |
12468 | [(set (pc) | |
cccf3bdc | 12469 | (match_operand:SI 0 "register_operand" "cl")) |
1fd4e8c1 | 12470 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 12471 | "TARGET_32BIT" |
cccf3bdc | 12472 | "b%T0" |
a6845123 | 12473 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 12474 | |
266eb58a DE |
12475 | (define_insn "" |
12476 | [(set (pc) | |
cccf3bdc | 12477 | (match_operand:DI 0 "register_operand" "cl")) |
266eb58a | 12478 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 12479 | "TARGET_64BIT" |
cccf3bdc | 12480 | "b%T0" |
266eb58a DE |
12481 | [(set_attr "type" "jmpreg")]) |
12482 | ||
1fd4e8c1 RK |
12483 | (define_insn "nop" |
12484 | [(const_int 0)] | |
12485 | "" | |
ca7f5001 | 12486 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 12487 | \f |
7e69e155 | 12488 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
12489 | ;; so loop.c knows what to generate. |
12490 | ||
5527bf14 RH |
12491 | (define_expand "doloop_end" |
12492 | [(use (match_operand 0 "" "")) ; loop pseudo | |
12493 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
12494 | (use (match_operand 2 "" "")) ; max iterations | |
12495 | (use (match_operand 3 "" "")) ; loop level | |
12496 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
12497 | "" |
12498 | " | |
12499 | { | |
5527bf14 RH |
12500 | /* Only use this on innermost loops. */ |
12501 | if (INTVAL (operands[3]) > 1) | |
12502 | FAIL; | |
0ad91047 | 12503 | if (TARGET_POWERPC64) |
5527bf14 RH |
12504 | { |
12505 | if (GET_MODE (operands[0]) != DImode) | |
12506 | FAIL; | |
12507 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
12508 | } | |
0ad91047 | 12509 | else |
5527bf14 RH |
12510 | { |
12511 | if (GET_MODE (operands[0]) != SImode) | |
12512 | FAIL; | |
12513 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
12514 | } | |
0ad91047 DE |
12515 | DONE; |
12516 | }") | |
12517 | ||
12518 | (define_expand "ctrsi" | |
3cb999d8 DE |
12519 | [(parallel [(set (pc) |
12520 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
12521 | (const_int 1)) | |
12522 | (label_ref (match_operand 1 "" "")) | |
12523 | (pc))) | |
b6c9286a MM |
12524 | (set (match_dup 0) |
12525 | (plus:SI (match_dup 0) | |
12526 | (const_int -1))) | |
5f81043f RK |
12527 | (clobber (match_scratch:CC 2 "")) |
12528 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
12529 | "! TARGET_POWERPC64" |
12530 | "") | |
12531 | ||
12532 | (define_expand "ctrdi" | |
3cb999d8 DE |
12533 | [(parallel [(set (pc) |
12534 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
12535 | (const_int 1)) | |
12536 | (label_ref (match_operand 1 "" "")) | |
12537 | (pc))) | |
0ad91047 DE |
12538 | (set (match_dup 0) |
12539 | (plus:DI (match_dup 0) | |
12540 | (const_int -1))) | |
12541 | (clobber (match_scratch:CC 2 "")) | |
12542 | (clobber (match_scratch:DI 3 ""))])] | |
12543 | "TARGET_POWERPC64" | |
c225ba7b RK |
12544 | "") |
12545 | ||
1fd4e8c1 RK |
12546 | ;; We need to be able to do this for any operand, including MEM, or we |
12547 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 12548 | ;; JUMP_INSNs. |
0ad91047 | 12549 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
12550 | ;; label MUST be operand 0. |
12551 | ||
0ad91047 | 12552 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 12553 | [(set (pc) |
5f81043f | 12554 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 12555 | (const_int 1)) |
a6845123 | 12556 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12557 | (pc))) |
5f81043f RK |
12558 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12559 | (plus:SI (match_dup 1) | |
12560 | (const_int -1))) | |
1fd4e8c1 RK |
12561 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
12562 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12563 | "! TARGET_POWERPC64" |
b19003d8 RK |
12564 | "* |
12565 | { | |
af87a13e | 12566 | if (which_alternative != 0) |
b19003d8 | 12567 | return \"#\"; |
856a6884 | 12568 | else if (get_attr_length (insn) == 4) |
a6845123 | 12569 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 12570 | else |
c81bebd7 | 12571 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 12572 | }" |
baf97f86 RK |
12573 | [(set_attr "type" "branch") |
12574 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 12575 | |
0ad91047 | 12576 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
12577 | [(set (pc) |
12578 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
12579 | (const_int 1)) | |
12580 | (pc) | |
12581 | (label_ref (match_operand 0 "" "")))) | |
12582 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
12583 | (plus:SI (match_dup 1) | |
12584 | (const_int -1))) | |
12585 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12586 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
12587 | "! TARGET_POWERPC64" |
12588 | "* | |
12589 | { | |
12590 | if (which_alternative != 0) | |
12591 | return \"#\"; | |
856a6884 | 12592 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12593 | return \"bdz %l0\"; |
12594 | else | |
12595 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
12596 | }" | |
12597 | [(set_attr "type" "branch") | |
12598 | (set_attr "length" "*,12,16")]) | |
12599 | ||
12600 | (define_insn "*ctrdi_internal1" | |
12601 | [(set (pc) | |
12602 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12603 | (const_int 1)) | |
12604 | (label_ref (match_operand 0 "" "")) | |
12605 | (pc))) | |
12606 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12607 | (plus:DI (match_dup 1) | |
12608 | (const_int -1))) | |
12609 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12610 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12611 | "TARGET_POWERPC64" | |
12612 | "* | |
12613 | { | |
12614 | if (which_alternative != 0) | |
12615 | return \"#\"; | |
856a6884 | 12616 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12617 | return \"{bdn|bdnz} %l0\"; |
12618 | else | |
12619 | return \"bdz %$+8\;b %l0\"; | |
12620 | }" | |
12621 | [(set_attr "type" "branch") | |
12622 | (set_attr "length" "*,12,16")]) | |
12623 | ||
12624 | (define_insn "*ctrdi_internal2" | |
12625 | [(set (pc) | |
12626 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12627 | (const_int 1)) | |
12628 | (pc) | |
12629 | (label_ref (match_operand 0 "" "")))) | |
12630 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12631 | (plus:DI (match_dup 1) | |
12632 | (const_int -1))) | |
12633 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12634 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12635 | "TARGET_POWERPC64" | |
5f81043f RK |
12636 | "* |
12637 | { | |
12638 | if (which_alternative != 0) | |
12639 | return \"#\"; | |
856a6884 | 12640 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
12641 | return \"bdz %l0\"; |
12642 | else | |
c81bebd7 | 12643 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
12644 | }" |
12645 | [(set_attr "type" "branch") | |
12646 | (set_attr "length" "*,12,16")]) | |
12647 | ||
c225ba7b | 12648 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
12649 | |
12650 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 12651 | [(set (pc) |
5f81043f | 12652 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 12653 | (const_int 0)) |
a6845123 | 12654 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12655 | (pc))) |
5f81043f RK |
12656 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12657 | (plus:SI (match_dup 1) | |
12658 | (const_int -1))) | |
1fd4e8c1 RK |
12659 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
12660 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12661 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
12662 | "* |
12663 | { | |
af87a13e | 12664 | if (which_alternative != 0) |
b19003d8 | 12665 | return \"#\"; |
856a6884 | 12666 | else if (get_attr_length (insn) == 4) |
a6845123 | 12667 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 12668 | else |
c81bebd7 | 12669 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 12670 | }" |
baf97f86 RK |
12671 | [(set_attr "type" "branch") |
12672 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 12673 | |
0ad91047 | 12674 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 12675 | [(set (pc) |
5f81043f RK |
12676 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
12677 | (const_int 0)) | |
12678 | (pc) | |
12679 | (label_ref (match_operand 0 "" "")))) | |
12680 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
12681 | (plus:SI (match_dup 1) | |
12682 | (const_int -1))) | |
12683 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
12684 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12685 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
12686 | "* |
12687 | { | |
12688 | if (which_alternative != 0) | |
12689 | return \"#\"; | |
856a6884 | 12690 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
12691 | return \"bdz %l0\"; |
12692 | else | |
c81bebd7 | 12693 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
12694 | }" |
12695 | [(set_attr "type" "branch") | |
12696 | (set_attr "length" "*,12,16")]) | |
12697 | ||
0ad91047 DE |
12698 | (define_insn "*ctrdi_internal3" |
12699 | [(set (pc) | |
12700 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12701 | (const_int 0)) | |
12702 | (label_ref (match_operand 0 "" "")) | |
12703 | (pc))) | |
12704 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12705 | (plus:DI (match_dup 1) | |
12706 | (const_int -1))) | |
12707 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
12708 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12709 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
12710 | "* | |
12711 | { | |
12712 | if (which_alternative != 0) | |
12713 | return \"#\"; | |
856a6884 | 12714 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12715 | return \"{bdn|bdnz} %l0\"; |
12716 | else | |
12717 | return \"bdz %$+8\;b %l0\"; | |
12718 | }" | |
12719 | [(set_attr "type" "branch") | |
12720 | (set_attr "length" "*,12,16")]) | |
12721 | ||
12722 | (define_insn "*ctrdi_internal4" | |
12723 | [(set (pc) | |
12724 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12725 | (const_int 0)) | |
12726 | (pc) | |
12727 | (label_ref (match_operand 0 "" "")))) | |
12728 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12729 | (plus:DI (match_dup 1) | |
12730 | (const_int -1))) | |
12731 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
12732 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12733 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
12734 | "* | |
12735 | { | |
12736 | if (which_alternative != 0) | |
12737 | return \"#\"; | |
856a6884 | 12738 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12739 | return \"bdz %l0\"; |
12740 | else | |
12741 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
12742 | }" | |
12743 | [(set_attr "type" "branch") | |
12744 | (set_attr "length" "*,12,16")]) | |
12745 | ||
12746 | ;; Similar but use EQ | |
12747 | ||
12748 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
12749 | [(set (pc) |
12750 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 12751 | (const_int 1)) |
a6845123 | 12752 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12753 | (pc))) |
5f81043f RK |
12754 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12755 | (plus:SI (match_dup 1) | |
12756 | (const_int -1))) | |
1fd4e8c1 RK |
12757 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
12758 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12759 | "! TARGET_POWERPC64" |
b19003d8 RK |
12760 | "* |
12761 | { | |
af87a13e | 12762 | if (which_alternative != 0) |
b19003d8 | 12763 | return \"#\"; |
856a6884 | 12764 | else if (get_attr_length (insn) == 4) |
a6845123 | 12765 | return \"bdz %l0\"; |
b19003d8 | 12766 | else |
c81bebd7 | 12767 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
b19003d8 | 12768 | }" |
baf97f86 RK |
12769 | [(set_attr "type" "branch") |
12770 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 12771 | |
0ad91047 | 12772 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
12773 | [(set (pc) |
12774 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
12775 | (const_int 1)) | |
12776 | (pc) | |
12777 | (label_ref (match_operand 0 "" "")))) | |
12778 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
12779 | (plus:SI (match_dup 1) | |
12780 | (const_int -1))) | |
12781 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12782 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
12783 | "! TARGET_POWERPC64" |
12784 | "* | |
12785 | { | |
12786 | if (which_alternative != 0) | |
12787 | return \"#\"; | |
856a6884 | 12788 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12789 | return \"{bdn|bdnz} %l0\"; |
12790 | else | |
12791 | return \"bdz %$+8\;b %l0\"; | |
12792 | }" | |
12793 | [(set_attr "type" "branch") | |
12794 | (set_attr "length" "*,12,16")]) | |
12795 | ||
12796 | (define_insn "*ctrdi_internal5" | |
12797 | [(set (pc) | |
12798 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12799 | (const_int 1)) | |
12800 | (label_ref (match_operand 0 "" "")) | |
12801 | (pc))) | |
12802 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12803 | (plus:DI (match_dup 1) | |
12804 | (const_int -1))) | |
12805 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12806 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12807 | "TARGET_POWERPC64" | |
12808 | "* | |
12809 | { | |
12810 | if (which_alternative != 0) | |
12811 | return \"#\"; | |
856a6884 | 12812 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12813 | return \"bdz %l0\"; |
12814 | else | |
12815 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
12816 | }" | |
12817 | [(set_attr "type" "branch") | |
12818 | (set_attr "length" "*,12,16")]) | |
12819 | ||
12820 | (define_insn "*ctrdi_internal6" | |
12821 | [(set (pc) | |
12822 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12823 | (const_int 1)) | |
12824 | (pc) | |
12825 | (label_ref (match_operand 0 "" "")))) | |
12826 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12827 | (plus:DI (match_dup 1) | |
12828 | (const_int -1))) | |
12829 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12830 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12831 | "TARGET_POWERPC64" | |
5f81043f RK |
12832 | "* |
12833 | { | |
12834 | if (which_alternative != 0) | |
12835 | return \"#\"; | |
856a6884 | 12836 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
12837 | return \"{bdn|bdnz} %l0\"; |
12838 | else | |
c81bebd7 | 12839 | return \"bdz %$+8\;b %l0\"; |
5f81043f RK |
12840 | }" |
12841 | [(set_attr "type" "branch") | |
12842 | (set_attr "length" "*,12,16")]) | |
12843 | ||
0ad91047 DE |
12844 | ;; Now the splitters if we could not allocate the CTR register |
12845 | ||
1fd4e8c1 RK |
12846 | (define_split |
12847 | [(set (pc) | |
12848 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 12849 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
12850 | (const_int 1)]) |
12851 | (match_operand 5 "" "") | |
12852 | (match_operand 6 "" ""))) | |
cd2b37d9 | 12853 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
12854 | (plus:SI (match_dup 1) |
12855 | (const_int -1))) | |
1fd4e8c1 RK |
12856 | (clobber (match_scratch:CC 3 "")) |
12857 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 12858 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 12859 | [(parallel [(set (match_dup 3) |
5f81043f RK |
12860 | (compare:CC (plus:SI (match_dup 1) |
12861 | (const_int -1)) | |
1fd4e8c1 | 12862 | (const_int 0))) |
5f81043f RK |
12863 | (set (match_dup 0) |
12864 | (plus:SI (match_dup 1) | |
12865 | (const_int -1)))]) | |
12866 | (set (pc) (if_then_else (match_dup 7) | |
12867 | (match_dup 5) | |
12868 | (match_dup 6)))] | |
1fd4e8c1 RK |
12869 | " |
12870 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
12871 | const0_rtx); }") | |
12872 | ||
12873 | (define_split | |
12874 | [(set (pc) | |
12875 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 12876 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
12877 | (const_int 1)]) |
12878 | (match_operand 5 "" "") | |
12879 | (match_operand 6 "" ""))) | |
9ebbca7d | 12880 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
12881 | (plus:SI (match_dup 1) (const_int -1))) |
12882 | (clobber (match_scratch:CC 3 "")) | |
12883 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
12884 | "! TARGET_POWERPC64 && reload_completed |
12885 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 12886 | [(parallel [(set (match_dup 3) |
5f81043f RK |
12887 | (compare:CC (plus:SI (match_dup 1) |
12888 | (const_int -1)) | |
1fd4e8c1 | 12889 | (const_int 0))) |
5f81043f RK |
12890 | (set (match_dup 4) |
12891 | (plus:SI (match_dup 1) | |
12892 | (const_int -1)))]) | |
12893 | (set (match_dup 0) | |
12894 | (match_dup 4)) | |
12895 | (set (pc) (if_then_else (match_dup 7) | |
12896 | (match_dup 5) | |
12897 | (match_dup 6)))] | |
1fd4e8c1 RK |
12898 | " |
12899 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
12900 | const0_rtx); }") | |
0ad91047 DE |
12901 | (define_split |
12902 | [(set (pc) | |
12903 | (if_then_else (match_operator 2 "comparison_operator" | |
12904 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
12905 | (const_int 1)]) | |
12906 | (match_operand 5 "" "") | |
12907 | (match_operand 6 "" ""))) | |
12908 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12909 | (plus:DI (match_dup 1) | |
12910 | (const_int -1))) | |
12911 | (clobber (match_scratch:CC 3 "")) | |
12912 | (clobber (match_scratch:DI 4 ""))] | |
12913 | "TARGET_POWERPC64 && reload_completed" | |
12914 | [(parallel [(set (match_dup 3) | |
12915 | (compare:CC (plus:DI (match_dup 1) | |
12916 | (const_int -1)) | |
12917 | (const_int 0))) | |
12918 | (set (match_dup 0) | |
12919 | (plus:DI (match_dup 1) | |
12920 | (const_int -1)))]) | |
12921 | (set (pc) (if_then_else (match_dup 7) | |
12922 | (match_dup 5) | |
12923 | (match_dup 6)))] | |
12924 | " | |
12925 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
12926 | const0_rtx); }") | |
12927 | ||
12928 | (define_split | |
12929 | [(set (pc) | |
12930 | (if_then_else (match_operator 2 "comparison_operator" | |
12931 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
12932 | (const_int 1)]) | |
12933 | (match_operand 5 "" "") | |
12934 | (match_operand 6 "" ""))) | |
9ebbca7d | 12935 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
12936 | (plus:DI (match_dup 1) (const_int -1))) |
12937 | (clobber (match_scratch:CC 3 "")) | |
12938 | (clobber (match_scratch:DI 4 ""))] | |
12939 | "TARGET_POWERPC64 && reload_completed | |
12940 | && ! gpc_reg_operand (operands[0], DImode)" | |
12941 | [(parallel [(set (match_dup 3) | |
12942 | (compare:CC (plus:DI (match_dup 1) | |
12943 | (const_int -1)) | |
12944 | (const_int 0))) | |
12945 | (set (match_dup 4) | |
12946 | (plus:DI (match_dup 1) | |
12947 | (const_int -1)))]) | |
12948 | (set (match_dup 0) | |
12949 | (match_dup 4)) | |
12950 | (set (pc) (if_then_else (match_dup 7) | |
12951 | (match_dup 5) | |
12952 | (match_dup 6)))] | |
12953 | " | |
12954 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
12955 | const0_rtx); }") | |
e0cd0770 JC |
12956 | \f |
12957 | (define_insn "trap" | |
12958 | [(trap_if (const_int 1) (const_int 0))] | |
12959 | "" | |
12960 | "{t 31,0,0|trap}") | |
12961 | ||
12962 | (define_expand "conditional_trap" | |
12963 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
12964 | [(match_dup 2) (match_dup 3)]) | |
12965 | (match_operand 1 "const_int_operand" ""))] | |
12966 | "" | |
12967 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
12968 | operands[2] = rs6000_compare_op0; | |
12969 | operands[3] = rs6000_compare_op1;") | |
12970 | ||
12971 | (define_insn "" | |
12972 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
12973 | [(match_operand:SI 1 "register_operand" "r") | |
12974 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
12975 | (const_int 0))] | |
12976 | "" | |
a157febd GK |
12977 | "{t|tw}%V0%I2 %1,%2") |
12978 | ||
12979 | (define_insn "" | |
12980 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
12981 | [(match_operand:DI 1 "register_operand" "r") | |
12982 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
12983 | (const_int 0))] | |
12984 | "TARGET_POWERPC64" | |
12985 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
12986 | \f |
12987 | ;; Insns related to generating the function prologue and epilogue. | |
12988 | ||
12989 | (define_expand "prologue" | |
12990 | [(use (const_int 0))] | |
12991 | "TARGET_SCHED_PROLOG" | |
12992 | " | |
12993 | { | |
12994 | rs6000_emit_prologue (); | |
12995 | DONE; | |
12996 | }") | |
12997 | ||
12998 | (define_insn "movesi_from_cr" | |
12999 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
13000 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) | |
13001 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))] | |
13002 | "" | |
13003 | "mfcr %0") | |
13004 | ||
13005 | (define_insn "*stmw" | |
13006 | [(match_parallel 0 "stmw_operation" | |
13007 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
13008 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
13009 | "TARGET_MULTIPLE" | |
13010 | "{stm|stmw} %2,%1") | |
13011 | ||
13012 | (define_insn "*save_fpregs_si" | |
13013 | [(match_parallel 0 "any_operand" | |
13014 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
13015 | (use (match_operand:SI 2 "call_operand" "s")) | |
13016 | (set (match_operand:DF 3 "memory_operand" "=m") | |
13017 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
13018 | "TARGET_32BIT" | |
13019 | "bl %z2") | |
13020 | ||
13021 | (define_insn "*save_fpregs_di" | |
13022 | [(match_parallel 0 "any_operand" | |
13023 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
13024 | (use (match_operand:DI 2 "call_operand" "s")) | |
13025 | (set (match_operand:DF 3 "memory_operand" "=m") | |
13026 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
13027 | "TARGET_64BIT" | |
13028 | "bl %z2") | |
13029 | ||
13030 | ; These are to explain that changes to the stack pointer should | |
13031 | ; not be moved over stores to stack memory. | |
13032 | (define_insn "stack_tie" | |
13033 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
13034 | (unspec:BLK [(match_dup 0)] 5))] | |
13035 | "" | |
13036 | "" | |
13037 | [(set_attr "length" "0")]) | |
13038 | ||
13039 | ||
13040 | (define_expand "epilogue" | |
13041 | [(use (const_int 0))] | |
13042 | "TARGET_SCHED_PROLOG" | |
13043 | " | |
13044 | { | |
13045 | rs6000_emit_epilogue (FALSE); | |
13046 | DONE; | |
13047 | }") | |
13048 | ||
13049 | ; On some processors, doing the mtcrf one CC register at a time is | |
13050 | ; faster (like on the 604e). On others, doing them all at once is | |
13051 | ; faster; for instance, on the 601 and 750. | |
13052 | ||
13053 | (define_expand "movsi_to_cr_one" | |
13054 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
13055 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
13056 | (match_dup 2)] 20))] | |
13057 | "" | |
13058 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
13059 | ||
13060 | (define_insn "*movsi_to_cr" | |
13061 | [(match_parallel 0 "mtcrf_operation" | |
e35b9579 GK |
13062 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") |
13063 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
13064 | (match_operand 3 "immediate_operand" "n")] | |
9ebbca7d GK |
13065 | 20))])] |
13066 | "" | |
e35b9579 GK |
13067 | "* |
13068 | { | |
13069 | int mask = 0; | |
13070 | int i; | |
13071 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
13072 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
13073 | operands[4] = GEN_INT (mask); | |
13074 | return \"mtcrf %4,%2\"; | |
13075 | }") | |
9ebbca7d GK |
13076 | |
13077 | (define_insn "" | |
13078 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
13079 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
13080 | (match_operand 2 "immediate_operand" "n")] 20))] | |
13081 | "GET_CODE (operands[0]) == REG | |
13082 | && CR_REGNO_P (REGNO (operands[0])) | |
13083 | && GET_CODE (operands[2]) == CONST_INT | |
13084 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
13085 | "mtcrf %R0,%1") | |
13086 | ||
13087 | ; The load-multiple instructions have similar properties. | |
13088 | ; Note that "load_multiple" is a name known to the machine-independent | |
13089 | ; code that actually corresponds to the powerpc load-string. | |
13090 | ||
13091 | (define_insn "*lmw" | |
13092 | [(match_parallel 0 "lmw_operation" | |
13093 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
13094 | (match_operand:SI 2 "memory_operand" "m"))])] | |
13095 | "TARGET_MULTIPLE" | |
13096 | "{lm|lmw} %1,%2") | |
13097 | ||
13098 | (define_insn "*return_internal_si" | |
e35b9579 GK |
13099 | [(return) |
13100 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 13101 | "TARGET_32BIT" |
cccf3bdc | 13102 | "b%T0" |
9ebbca7d GK |
13103 | [(set_attr "type" "jmpreg")]) |
13104 | ||
13105 | (define_insn "*return_internal_di" | |
e35b9579 GK |
13106 | [(return) |
13107 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 13108 | "TARGET_64BIT" |
cccf3bdc | 13109 | "b%T0" |
9ebbca7d GK |
13110 | [(set_attr "type" "jmpreg")]) |
13111 | ||
13112 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
13113 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
13114 | ||
13115 | (define_insn "*return_and_restore_fpregs_si" | |
13116 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
13117 | [(return) |
13118 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
13119 | (use (match_operand:SI 2 "call_operand" "s")) |
13120 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
13121 | (match_operand:DF 4 "memory_operand" "m"))])] | |
13122 | "TARGET_32BIT" | |
13123 | "b %z2") | |
13124 | ||
13125 | (define_insn "*return_and_restore_fpregs_di" | |
13126 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
13127 | [(return) |
13128 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
13129 | (use (match_operand:DI 2 "call_operand" "s")) |
13130 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
13131 | (match_operand:DF 4 "memory_operand" "m"))])] | |
13132 | "TARGET_64BIT" | |
13133 | "b %z2") | |
13134 | ||
83720594 RH |
13135 | ; This is used in compiling the unwind routines. |
13136 | (define_expand "eh_return" | |
13137 | [(use (match_operand 0 "general_operand" "")) | |
13138 | (use (match_operand 1 "general_operand" ""))] | |
9ebbca7d GK |
13139 | "" |
13140 | " | |
13141 | { | |
3553b09d | 13142 | #if TARGET_AIX |
83720594 | 13143 | rs6000_emit_eh_toc_restore (operands[0]); |
3553b09d | 13144 | #endif |
83720594 RH |
13145 | if (TARGET_32BIT) |
13146 | emit_insn (gen_eh_set_lr_si (operands[1])); | |
9ebbca7d | 13147 | else |
83720594 RH |
13148 | emit_insn (gen_eh_set_lr_di (operands[1])); |
13149 | emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]); | |
9ebbca7d GK |
13150 | DONE; |
13151 | }") | |
13152 | ||
83720594 RH |
13153 | ; We can't expand this before we know where the link register is stored. |
13154 | (define_insn "eh_set_lr_si" | |
13155 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9) | |
13156 | (clobber (match_scratch:SI 1 "=&r"))] | |
13157 | "TARGET_32BIT" | |
13158 | "#") | |
13159 | ||
13160 | (define_insn "eh_set_lr_di" | |
13161 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9) | |
13162 | (clobber (match_scratch:DI 1 "=&r"))] | |
13163 | "TARGET_64BIT" | |
13164 | "#") | |
9ebbca7d GK |
13165 | |
13166 | (define_split | |
83720594 RH |
13167 | [(unspec_volatile [(match_operand 0 "register_operand" "")] 9) |
13168 | (clobber (match_scratch 1 ""))] | |
13169 | "reload_completed" | |
13170 | [(const_int 0)] | |
9ebbca7d GK |
13171 | " |
13172 | { | |
83720594 | 13173 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d | 13174 | |
83720594 RH |
13175 | if (info->lr_save_p) |
13176 | { | |
13177 | rtx frame_rtx = stack_pointer_rtx; | |
13178 | int sp_offset = 0; | |
13179 | rtx tmp; | |
9ebbca7d | 13180 | |
83720594 RH |
13181 | if (frame_pointer_needed |
13182 | || current_function_calls_alloca | |
13183 | || info->total_size > 32767) | |
13184 | { | |
13185 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
13186 | frame_rtx = operands[1]; | |
13187 | } | |
13188 | else if (info->push_p) | |
13189 | sp_offset = info->total_size; | |
9ebbca7d | 13190 | |
83720594 RH |
13191 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); |
13192 | tmp = gen_rtx_MEM (Pmode, tmp); | |
13193 | emit_move_insn (tmp, operands[0]); | |
13194 | } | |
13195 | else | |
13196 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
13197 | DONE; | |
13198 | }") |