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re PR c++/33506 (TYPE_RAISES_EXCEPTIONS dumped with attributes)
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
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996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
8ef65e3d 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
602ea4d3 4;; Free Software Foundation, Inc.
996a5f59 5;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 6
5de601cf 7;; This file is part of GCC.
1fd4e8c1 8
5de601cf
NC		 9;; GCC is free software; you can redistribute it and/or modify it
10;; under the terms of the GNU General Public License as published
2f83c7d6 11;; by the Free Software Foundation; either version 3, or (at your
5de601cf 12;; option) any later version.
1fd4e8c1 13
5de601cf
NC		 14;; GCC is distributed in the hope that it will be useful, but WITHOUT
15;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17;; License for more details.
1fd4e8c1
RK		 18
19;; You should have received a copy of the GNU General Public License
2f83c7d6
NC		 20;; along with GCC; see the file COPYING3. If not see
21;; <http://www.gnu.org/licenses/>.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 24
1de43f85
DE		 25;;
26;; REGNOS
27;;
28
29(define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
615158e2
JJ		 52;;
53;; UNSPEC usage
54;;
55
56(define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
9719f3b7
DE		 64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
615158e2
JJ		 68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
ecb62ae7 83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
cef6b86c 84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
da4c340c 85 (UNSPEC_STFIWX 32)
9f0076e5
DE		 86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
716019c0
JM		 98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
615158e2
JJ		 101 ])
102
103;;
104;; UNSPEC_VOLATILE usage
105;;
106
107(define_constants
108 [(UNSPECV_BLOCK 0)
b52110d4
DE		 109 (UNSPECV_LL 1) ; load-locked
110 (UNSPECV_SC 2) ; store-conditional
615158e2
JJ		 111 (UNSPECV_EH_RR 9) ; eh_reg_restore
112 ])
1fd4e8c1
RK		 113\f
114;; Define an insn type attribute. This is used in function unit delay
115;; computations.
44cd321e 116(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
1fd4e8c1
RK		 117 (const_string "integer"))
118
b19003d8 119;; Length (in bytes).
6ae08853 120; '(pc)' in the following doesn't include the instruction itself; it is
6cbadf36 121; calculated as if the instruction had zero size.
b19003d8
RK		 122(define_attr "length" ""
123 (if_then_else (eq_attr "type" "branch")
6cbadf36 124 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 125 (const_int -32768))
6cbadf36
GK		 126 (lt (minus (match_dup 0) (pc))
127 (const_int 32764)))
39a10a29
GK		 128 (const_int 4)
129 (const_int 8))
b19003d8
RK		 130 (const_int 4)))
131
cfb557c4
RK		 132;; Processor type -- this attribute must exactly match the processor_type
133;; enumeration in rs6000.h.
134
d296e02e 135(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
cfb557c4
RK		 136 (const (symbol_ref "rs6000_cpu_attr")))
137
d296e02e
AP		 138
139;; If this instruction is microcoded on the CELL processor
140; The default for load and stores is conditional
141; The default for load extended and the recorded instructions is always microcoded
142(define_attr "cell_micro" "not,conditional,always"
143 (if_then_else (ior (ior (eq_attr "type" "load")
144 (eq_attr "type" "store"))
145 (ior (eq_attr "type" "fpload")
146 (eq_attr "type" "fpstore")))
147 (const_string "conditional")
148 (if_then_else (ior (eq_attr "type" "load_ext")
149 (ior (eq_attr "type" "compare")
150 (eq_attr "type" "delayed_compare")))
151 (const_string "always")
152 (const_string "not"))))
153
154
b54cf83a
DE		 155(automata_option "ndfa")
156
157(include "rios1.md")
158(include "rios2.md")
159(include "rs64.md")
160(include "mpc.md")
161(include "40x.md")
02ca7595 162(include "440.md")
b54cf83a
DE		 163(include "603.md")
164(include "6xx.md")
165(include "7xx.md")
166(include "7450.md")
5e8006fa 167(include "8540.md")
b54cf83a 168(include "power4.md")
ec507f2d 169(include "power5.md")
44cd321e 170(include "power6.md")
d296e02e 171(include "cell.md")
48d72335
DE		 172
173(include "predicates.md")
279bb624 174(include "constraints.md")
48d72335 175
ac9e2cff 176(include "darwin.md")
309323c2 177
1fd4e8c1 178\f
3abcb3a7 179;; Mode iterators
915167f5 180
3abcb3a7 181; This mode iterator allows :GPR to be used to indicate the allowable size
915167f5 182; of whole values in GPRs.
3abcb3a7 183(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
915167f5 184
0354e5d8 185; Any supported integer mode.
3abcb3a7 186(define_mode_iterator INT [QI HI SI DI TI])
915167f5 187
0354e5d8 188; Any supported integer mode that fits in one register.
3abcb3a7 189(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
915167f5 190
b5568f07 191; extend modes for DImode
3abcb3a7 192(define_mode_iterator QHSI [QI HI SI])
b5568f07 193
0354e5d8 194; SImode or DImode, even if DImode doesn't fit in GPRs.
3abcb3a7 195(define_mode_iterator SDI [SI DI])
0354e5d8
GK		 196
197; The size of a pointer. Also, the size of the value that a record-condition
198; (one with a '.') will compare.
3abcb3a7 199(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
2e6c9641 200
4ae234b0 201; Any hardware-supported floating-point mode
3abcb3a7 202(define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
4ae234b0 203 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
602ea4d3 204 (TF "!TARGET_IEEEQUAD
17caeff2
JM		 205 && TARGET_HARD_FLOAT
206 && (TARGET_FPRS || TARGET_E500_DOUBLE)
6ef9a246
JJ		 207 && TARGET_LONG_DOUBLE_128")
208 (DD "TARGET_DFP")
209 (TD "TARGET_DFP")])
4ae234b0 210
915167f5 211; Various instructions that come in SI and DI forms.
0354e5d8 212; A generic w/d attribute, for things like cmpw/cmpd.
b5568f07
DE		 213(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
214
215; DImode bits
216(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
915167f5
GK		 217
218\f
1fd4e8c1
RK		 219;; Start with fixed-point load and store insns. Here we put only the more
220;; complex forms. Basic data transfer is done later.
221
b5568f07 222(define_expand "zero_extend<mode>di2"
51b8fc2c 223 [(set (match_operand:DI 0 "gpc_reg_operand" "")
b5568f07 224 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
51b8fc2c
RK		 225 "TARGET_POWERPC64"
226 "")
227
b5568f07 228(define_insn "*zero_extend<mode>di2_internal1"
51b8fc2c 229 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
b5568f07 230 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
51b8fc2c
RK		 231 "TARGET_POWERPC64"
232 "@
b5568f07
DE		 233 l<wd>z%U1%X1 %0,%1
234 rldicl %0,%1,0,<dbits>"
51b8fc2c
RK		 235 [(set_attr "type" "load,*")])
236
b5568f07 237(define_insn "*zero_extend<mode>di2_internal2"
9ebbca7d 238 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
b5568f07 239 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
815cdc52 240 (const_int 0)))
9ebbca7d 241 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 242 "TARGET_64BIT"
9ebbca7d 243 "@
b5568f07 244 rldicl. %2,%1,0,<dbits>
9ebbca7d
GK		 245 #"
246 [(set_attr "type" "compare")
247 (set_attr "length" "4,8")])
248
249(define_split
250 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
b5568f07 251 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 252 (const_int 0)))
253 (clobber (match_scratch:DI 2 ""))]
254 "TARGET_POWERPC64 && reload_completed"
255 [(set (match_dup 2)
256 (zero_extend:DI (match_dup 1)))
257 (set (match_dup 0)
258 (compare:CC (match_dup 2)
259 (const_int 0)))]
260 "")
51b8fc2c 261
b5568f07 262(define_insn "*zero_extend<mode>di2_internal3"
9ebbca7d 263 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
b5568f07 264 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 265 (const_int 0)))
9ebbca7d 266 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 267 (zero_extend:DI (match_dup 1)))]
683bdff7 268 "TARGET_64BIT"
9ebbca7d 269 "@
b5568f07 270 rldicl. %0,%1,0,<dbits>
9ebbca7d
GK		 271 #"
272 [(set_attr "type" "compare")
273 (set_attr "length" "4,8")])
274
275(define_split
276 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
b5568f07 277 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 278 (const_int 0)))
279 (set (match_operand:DI 0 "gpc_reg_operand" "")
280 (zero_extend:DI (match_dup 1)))]
281 "TARGET_POWERPC64 && reload_completed"
282 [(set (match_dup 0)
283 (zero_extend:DI (match_dup 1)))
284 (set (match_dup 2)
285 (compare:CC (match_dup 0)
286 (const_int 0)))]
287 "")
51b8fc2c 288
2bee0449
RK		 289(define_insn "extendqidi2"
290 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
291 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 292 "TARGET_POWERPC64"
44cd321e
PS		 293 "extsb %0,%1"
294 [(set_attr "type" "exts")])
51b8fc2c
RK		 295
296(define_insn ""
9ebbca7d
GK		 297 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
298 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 299 (const_int 0)))
9ebbca7d 300 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 301 "TARGET_64BIT"
9ebbca7d
GK		 302 "@
303 extsb. %2,%1
304 #"
305 [(set_attr "type" "compare")
306 (set_attr "length" "4,8")])
307
308(define_split
309 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
310 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
311 (const_int 0)))
312 (clobber (match_scratch:DI 2 ""))]
313 "TARGET_POWERPC64 && reload_completed"
314 [(set (match_dup 2)
315 (sign_extend:DI (match_dup 1)))
316 (set (match_dup 0)
317 (compare:CC (match_dup 2)
318 (const_int 0)))]
319 "")
51b8fc2c
RK		 320
321(define_insn ""
9ebbca7d
GK		 322 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
323 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 324 (const_int 0)))
9ebbca7d 325 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 326 (sign_extend:DI (match_dup 1)))]
683bdff7 327 "TARGET_64BIT"
9ebbca7d
GK		 328 "@
329 extsb. %0,%1
330 #"
331 [(set_attr "type" "compare")
332 (set_attr "length" "4,8")])
333
334(define_split
335 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
336 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
337 (const_int 0)))
338 (set (match_operand:DI 0 "gpc_reg_operand" "")
339 (sign_extend:DI (match_dup 1)))]
340 "TARGET_POWERPC64 && reload_completed"
341 [(set (match_dup 0)
342 (sign_extend:DI (match_dup 1)))
343 (set (match_dup 2)
344 (compare:CC (match_dup 0)
345 (const_int 0)))]
346 "")
51b8fc2c 347
51b8fc2c
RK		 348(define_expand "extendhidi2"
349 [(set (match_operand:DI 0 "gpc_reg_operand" "")
350 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
351 "TARGET_POWERPC64"
352 "")
353
354(define_insn ""
355 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
356 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
357 "TARGET_POWERPC64"
358 "@
359 lha%U1%X1 %0,%1
360 extsh %0,%1"
44cd321e 361 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 362
363(define_insn ""
9ebbca7d
GK		 364 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
365 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 366 (const_int 0)))
9ebbca7d 367 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 368 "TARGET_64BIT"
9ebbca7d
GK		 369 "@
370 extsh. %2,%1
371 #"
372 [(set_attr "type" "compare")
373 (set_attr "length" "4,8")])
374
375(define_split
376 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
377 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
378 (const_int 0)))
379 (clobber (match_scratch:DI 2 ""))]
380 "TARGET_POWERPC64 && reload_completed"
381 [(set (match_dup 2)
382 (sign_extend:DI (match_dup 1)))
383 (set (match_dup 0)
384 (compare:CC (match_dup 2)
385 (const_int 0)))]
386 "")
51b8fc2c
RK		 387
388(define_insn ""
9ebbca7d
GK		 389 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
390 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 391 (const_int 0)))
9ebbca7d 392 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 393 (sign_extend:DI (match_dup 1)))]
683bdff7 394 "TARGET_64BIT"
9ebbca7d
GK		 395 "@
396 extsh. %0,%1
397 #"
398 [(set_attr "type" "compare")
399 (set_attr "length" "4,8")])
400
401(define_split
402 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
403 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
404 (const_int 0)))
405 (set (match_operand:DI 0 "gpc_reg_operand" "")
406 (sign_extend:DI (match_dup 1)))]
407 "TARGET_POWERPC64 && reload_completed"
408 [(set (match_dup 0)
409 (sign_extend:DI (match_dup 1)))
410 (set (match_dup 2)
411 (compare:CC (match_dup 0)
412 (const_int 0)))]
413 "")
51b8fc2c 414
51b8fc2c
RK		 415(define_expand "extendsidi2"
416 [(set (match_operand:DI 0 "gpc_reg_operand" "")
417 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
418 "TARGET_POWERPC64"
419 "")
420
421(define_insn ""
422 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 423 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
51b8fc2c
RK		 424 "TARGET_POWERPC64"
425 "@
426 lwa%U1%X1 %0,%1
427 extsw %0,%1"
44cd321e 428 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 429
430(define_insn ""
9ebbca7d
GK		 431 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
432 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 433 (const_int 0)))
9ebbca7d 434 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 435 "TARGET_64BIT"
9ebbca7d
GK		 436 "@
437 extsw. %2,%1
438 #"
439 [(set_attr "type" "compare")
440 (set_attr "length" "4,8")])
441
442(define_split
443 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
444 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
445 (const_int 0)))
446 (clobber (match_scratch:DI 2 ""))]
447 "TARGET_POWERPC64 && reload_completed"
448 [(set (match_dup 2)
449 (sign_extend:DI (match_dup 1)))
450 (set (match_dup 0)
451 (compare:CC (match_dup 2)
452 (const_int 0)))]
453 "")
51b8fc2c
RK		 454
455(define_insn ""
9ebbca7d
GK		 456 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
457 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 458 (const_int 0)))
9ebbca7d 459 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 460 (sign_extend:DI (match_dup 1)))]
683bdff7 461 "TARGET_64BIT"
9ebbca7d
GK		 462 "@
463 extsw. %0,%1
464 #"
465 [(set_attr "type" "compare")
466 (set_attr "length" "4,8")])
467
468(define_split
469 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
470 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
471 (const_int 0)))
472 (set (match_operand:DI 0 "gpc_reg_operand" "")
473 (sign_extend:DI (match_dup 1)))]
474 "TARGET_POWERPC64 && reload_completed"
475 [(set (match_dup 0)
476 (sign_extend:DI (match_dup 1)))
477 (set (match_dup 2)
478 (compare:CC (match_dup 0)
479 (const_int 0)))]
480 "")
51b8fc2c 481
1fd4e8c1 482(define_expand "zero_extendqisi2"
cd2b37d9
RK		 483 [(set (match_operand:SI 0 "gpc_reg_operand" "")
484 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 485 ""
486 "")
487
488(define_insn ""
cd2b37d9 489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 490 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
491 ""
492 "@
493 lbz%U1%X1 %0,%1
005a35b9 494 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 495 [(set_attr "type" "load,*")])
496
497(define_insn ""
9ebbca7d
GK		 498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
499 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 500 (const_int 0)))
9ebbca7d 501 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 502 ""
9ebbca7d
GK		 503 "@
504 {andil.|andi.} %2,%1,0xff
505 #"
506 [(set_attr "type" "compare")
507 (set_attr "length" "4,8")])
508
509(define_split
510 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
511 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
512 (const_int 0)))
513 (clobber (match_scratch:SI 2 ""))]
514 "reload_completed"
515 [(set (match_dup 2)
516 (zero_extend:SI (match_dup 1)))
517 (set (match_dup 0)
518 (compare:CC (match_dup 2)
519 (const_int 0)))]
520 "")
1fd4e8c1
RK		 521
522(define_insn ""
9ebbca7d
GK		 523 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
524 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 525 (const_int 0)))
9ebbca7d 526 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 527 (zero_extend:SI (match_dup 1)))]
528 ""
9ebbca7d
GK		 529 "@
530 {andil.|andi.} %0,%1,0xff
531 #"
532 [(set_attr "type" "compare")
533 (set_attr "length" "4,8")])
534
535(define_split
536 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
537 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
538 (const_int 0)))
539 (set (match_operand:SI 0 "gpc_reg_operand" "")
540 (zero_extend:SI (match_dup 1)))]
541 "reload_completed"
542 [(set (match_dup 0)
543 (zero_extend:SI (match_dup 1)))
544 (set (match_dup 2)
545 (compare:CC (match_dup 0)
546 (const_int 0)))]
547 "")
1fd4e8c1 548
51b8fc2c
RK		 549(define_expand "extendqisi2"
550 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
551 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
552 ""
553 "
554{
555 if (TARGET_POWERPC)
556 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
557 else if (TARGET_POWER)
558 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
559 else
560 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
561 DONE;
562}")
563
564(define_insn "extendqisi2_ppc"
2bee0449
RK		 565 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
566 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 567 "TARGET_POWERPC"
44cd321e
PS		 568 "extsb %0,%1"
569 [(set_attr "type" "exts")])
51b8fc2c
RK		 570
571(define_insn ""
9ebbca7d
GK		 572 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
573 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 574 (const_int 0)))
9ebbca7d 575 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 576 "TARGET_POWERPC"
9ebbca7d
GK		 577 "@
578 extsb. %2,%1
579 #"
580 [(set_attr "type" "compare")
581 (set_attr "length" "4,8")])
582
583(define_split
584 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
585 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
586 (const_int 0)))
587 (clobber (match_scratch:SI 2 ""))]
588 "TARGET_POWERPC && reload_completed"
589 [(set (match_dup 2)
590 (sign_extend:SI (match_dup 1)))
591 (set (match_dup 0)
592 (compare:CC (match_dup 2)
593 (const_int 0)))]
594 "")
51b8fc2c
RK		 595
596(define_insn ""
9ebbca7d
GK		 597 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
598 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 599 (const_int 0)))
9ebbca7d 600 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 601 (sign_extend:SI (match_dup 1)))]
602 "TARGET_POWERPC"
9ebbca7d
GK		 603 "@
604 extsb. %0,%1
605 #"
606 [(set_attr "type" "compare")
607 (set_attr "length" "4,8")])
608
609(define_split
610 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
611 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
612 (const_int 0)))
613 (set (match_operand:SI 0 "gpc_reg_operand" "")
614 (sign_extend:SI (match_dup 1)))]
615 "TARGET_POWERPC && reload_completed"
616 [(set (match_dup 0)
617 (sign_extend:SI (match_dup 1)))
618 (set (match_dup 2)
619 (compare:CC (match_dup 0)
620 (const_int 0)))]
621 "")
51b8fc2c
RK		 622
623(define_expand "extendqisi2_power"
624 [(parallel [(set (match_dup 2)
625 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
626 (const_int 24)))
627 (clobber (scratch:SI))])
628 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
629 (ashiftrt:SI (match_dup 2)
630 (const_int 24)))
631 (clobber (scratch:SI))])]
632 "TARGET_POWER"
633 "
634{ operands[1] = gen_lowpart (SImode, operands[1]);
635 operands[2] = gen_reg_rtx (SImode); }")
636
637(define_expand "extendqisi2_no_power"
638 [(set (match_dup 2)
639 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
640 (const_int 24)))
641 (set (match_operand:SI 0 "gpc_reg_operand" "")
642 (ashiftrt:SI (match_dup 2)
643 (const_int 24)))]
644 "! TARGET_POWER && ! TARGET_POWERPC"
645 "
646{ operands[1] = gen_lowpart (SImode, operands[1]);
647 operands[2] = gen_reg_rtx (SImode); }")
648
1fd4e8c1 649(define_expand "zero_extendqihi2"
cd2b37d9
RK		 650 [(set (match_operand:HI 0 "gpc_reg_operand" "")
651 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 652 ""
653 "")
654
655(define_insn ""
cd2b37d9 656 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 657 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
658 ""
659 "@
660 lbz%U1%X1 %0,%1
005a35b9 661 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 662 [(set_attr "type" "load,*")])
663
664(define_insn ""
9ebbca7d
GK		 665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
666 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 667 (const_int 0)))
9ebbca7d 668 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 669 ""
9ebbca7d
GK		 670 "@
671 {andil.|andi.} %2,%1,0xff
672 #"
673 [(set_attr "type" "compare")
674 (set_attr "length" "4,8")])
675
676(define_split
677 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
678 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
679 (const_int 0)))
680 (clobber (match_scratch:HI 2 ""))]
681 "reload_completed"
682 [(set (match_dup 2)
683 (zero_extend:HI (match_dup 1)))
684 (set (match_dup 0)
685 (compare:CC (match_dup 2)
686 (const_int 0)))]
687 "")
1fd4e8c1 688
51b8fc2c 689(define_insn ""
9ebbca7d
GK		 690 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
691 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 692 (const_int 0)))
9ebbca7d 693 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 694 (zero_extend:HI (match_dup 1)))]
695 ""
9ebbca7d
GK		 696 "@
697 {andil.|andi.} %0,%1,0xff
698 #"
699 [(set_attr "type" "compare")
700 (set_attr "length" "4,8")])
701
702(define_split
703 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
704 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
705 (const_int 0)))
706 (set (match_operand:HI 0 "gpc_reg_operand" "")
707 (zero_extend:HI (match_dup 1)))]
708 "reload_completed"
709 [(set (match_dup 0)
710 (zero_extend:HI (match_dup 1)))
711 (set (match_dup 2)
712 (compare:CC (match_dup 0)
713 (const_int 0)))]
714 "")
815cdc52
MM		 715
716(define_expand "extendqihi2"
717 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
718 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
719 ""
720 "
721{
722 if (TARGET_POWERPC)
723 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
724 else if (TARGET_POWER)
725 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
726 else
727 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
728 DONE;
729}")
730
731(define_insn "extendqihi2_ppc"
732 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
733 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
734 "TARGET_POWERPC"
44cd321e
PS		 735 "extsb %0,%1"
736 [(set_attr "type" "exts")])
815cdc52
MM		 737
738(define_insn ""
9ebbca7d
GK		 739 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
740 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 741 (const_int 0)))
9ebbca7d 742 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 743 "TARGET_POWERPC"
9ebbca7d
GK		 744 "@
745 extsb. %2,%1
746 #"
747 [(set_attr "type" "compare")
748 (set_attr "length" "4,8")])
749
750(define_split
751 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
752 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
753 (const_int 0)))
754 (clobber (match_scratch:HI 2 ""))]
755 "TARGET_POWERPC && reload_completed"
756 [(set (match_dup 2)
757 (sign_extend:HI (match_dup 1)))
758 (set (match_dup 0)
759 (compare:CC (match_dup 2)
760 (const_int 0)))]
761 "")
815cdc52
MM		 762
763(define_insn ""
9ebbca7d
GK		 764 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
765 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 766 (const_int 0)))
9ebbca7d 767 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 768 (sign_extend:HI (match_dup 1)))]
769 "TARGET_POWERPC"
9ebbca7d
GK		 770 "@
771 extsb. %0,%1
772 #"
773 [(set_attr "type" "compare")
774 (set_attr "length" "4,8")])
775
776(define_split
777 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
778 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
779 (const_int 0)))
780 (set (match_operand:HI 0 "gpc_reg_operand" "")
781 (sign_extend:HI (match_dup 1)))]
782 "TARGET_POWERPC && reload_completed"
783 [(set (match_dup 0)
784 (sign_extend:HI (match_dup 1)))
785 (set (match_dup 2)
786 (compare:CC (match_dup 0)
787 (const_int 0)))]
788 "")
51b8fc2c
RK		 789
790(define_expand "extendqihi2_power"
791 [(parallel [(set (match_dup 2)
792 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
793 (const_int 24)))
794 (clobber (scratch:SI))])
795 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
796 (ashiftrt:SI (match_dup 2)
797 (const_int 24)))
798 (clobber (scratch:SI))])]
799 "TARGET_POWER"
800 "
801{ operands[0] = gen_lowpart (SImode, operands[0]);
802 operands[1] = gen_lowpart (SImode, operands[1]);
803 operands[2] = gen_reg_rtx (SImode); }")
804
805(define_expand "extendqihi2_no_power"
806 [(set (match_dup 2)
807 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
808 (const_int 24)))
809 (set (match_operand:HI 0 "gpc_reg_operand" "")
810 (ashiftrt:SI (match_dup 2)
811 (const_int 24)))]
812 "! TARGET_POWER && ! TARGET_POWERPC"
813 "
814{ operands[0] = gen_lowpart (SImode, operands[0]);
815 operands[1] = gen_lowpart (SImode, operands[1]);
816 operands[2] = gen_reg_rtx (SImode); }")
817
1fd4e8c1 818(define_expand "zero_extendhisi2"
5f243543 819 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 820 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 821 ""
822 "")
823
824(define_insn ""
cd2b37d9 825 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 826 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
827 ""
828 "@
829 lhz%U1%X1 %0,%1
005a35b9 830 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 831 [(set_attr "type" "load,*")])
832
833(define_insn ""
9ebbca7d
GK		 834 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
835 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 836 (const_int 0)))
9ebbca7d 837 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 838 ""
9ebbca7d
GK		 839 "@
840 {andil.|andi.} %2,%1,0xffff
841 #"
842 [(set_attr "type" "compare")
843 (set_attr "length" "4,8")])
844
845(define_split
846 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
847 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
848 (const_int 0)))
849 (clobber (match_scratch:SI 2 ""))]
850 "reload_completed"
851 [(set (match_dup 2)
852 (zero_extend:SI (match_dup 1)))
853 (set (match_dup 0)
854 (compare:CC (match_dup 2)
855 (const_int 0)))]
856 "")
1fd4e8c1
RK		 857
858(define_insn ""
9ebbca7d
GK		 859 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
860 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 861 (const_int 0)))
9ebbca7d 862 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 863 (zero_extend:SI (match_dup 1)))]
864 ""
9ebbca7d
GK		 865 "@
866 {andil.|andi.} %0,%1,0xffff
867 #"
868 [(set_attr "type" "compare")
869 (set_attr "length" "4,8")])
870
871(define_split
872 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
873 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
874 (const_int 0)))
875 (set (match_operand:SI 0 "gpc_reg_operand" "")
876 (zero_extend:SI (match_dup 1)))]
877 "reload_completed"
878 [(set (match_dup 0)
879 (zero_extend:SI (match_dup 1)))
880 (set (match_dup 2)
881 (compare:CC (match_dup 0)
882 (const_int 0)))]
883 "")
1fd4e8c1
RK		 884
885(define_expand "extendhisi2"
cd2b37d9
RK		 886 [(set (match_operand:SI 0 "gpc_reg_operand" "")
887 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 888 ""
889 "")
890
891(define_insn ""
cd2b37d9 892 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 893 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
894 ""
895 "@
896 lha%U1%X1 %0,%1
ca7f5001 897 {exts|extsh} %0,%1"
44cd321e 898 [(set_attr "type" "load_ext,exts")])
1fd4e8c1
RK		 899
900(define_insn ""
9ebbca7d
GK		 901 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
902 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 903 (const_int 0)))
9ebbca7d 904 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 905 ""
9ebbca7d
GK		 906 "@
907 {exts.|extsh.} %2,%1
908 #"
909 [(set_attr "type" "compare")
910 (set_attr "length" "4,8")])
911
912(define_split
913 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
914 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
915 (const_int 0)))
916 (clobber (match_scratch:SI 2 ""))]
917 "reload_completed"
918 [(set (match_dup 2)
919 (sign_extend:SI (match_dup 1)))
920 (set (match_dup 0)
921 (compare:CC (match_dup 2)
922 (const_int 0)))]
923 "")
1fd4e8c1
RK		 924
925(define_insn ""
9ebbca7d
GK		 926 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
927 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 928 (const_int 0)))
9ebbca7d 929 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 930 (sign_extend:SI (match_dup 1)))]
931 ""
9ebbca7d
GK		 932 "@
933 {exts.|extsh.} %0,%1
934 #"
935 [(set_attr "type" "compare")
936 (set_attr "length" "4,8")])
1fd4e8c1 937\f
131aeb82
JM		 938;; IBM 405 and 440 half-word multiplication operations.
939
940(define_insn "*macchwc"
941 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
942 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
943 (match_operand:SI 2 "gpc_reg_operand" "r")
944 (const_int 16))
945 (sign_extend:SI
946 (match_operand:HI 1 "gpc_reg_operand" "r")))
947 (match_operand:SI 4 "gpc_reg_operand" "0"))
948 (const_int 0)))
949 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
950 (plus:SI (mult:SI (ashiftrt:SI
951 (match_dup 2)
952 (const_int 16))
953 (sign_extend:SI
954 (match_dup 1)))
955 (match_dup 4)))]
956 "TARGET_MULHW"
957 "macchw. %0, %1, %2"
958 [(set_attr "type" "imul3")])
959
960(define_insn "*macchw"
961 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
962 (plus:SI (mult:SI (ashiftrt:SI
963 (match_operand:SI 2 "gpc_reg_operand" "r")
964 (const_int 16))
965 (sign_extend:SI
966 (match_operand:HI 1 "gpc_reg_operand" "r")))
967 (match_operand:SI 3 "gpc_reg_operand" "0")))]
968 "TARGET_MULHW"
969 "macchw %0, %1, %2"
970 [(set_attr "type" "imul3")])
971
972(define_insn "*macchwuc"
973 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
974 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
975 (match_operand:SI 2 "gpc_reg_operand" "r")
976 (const_int 16))
977 (zero_extend:SI
978 (match_operand:HI 1 "gpc_reg_operand" "r")))
979 (match_operand:SI 4 "gpc_reg_operand" "0"))
980 (const_int 0)))
981 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
982 (plus:SI (mult:SI (lshiftrt:SI
983 (match_dup 2)
984 (const_int 16))
985 (zero_extend:SI
986 (match_dup 1)))
987 (match_dup 4)))]
988 "TARGET_MULHW"
989 "macchwu. %0, %1, %2"
990 [(set_attr "type" "imul3")])
991
992(define_insn "*macchwu"
993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
994 (plus:SI (mult:SI (lshiftrt:SI
995 (match_operand:SI 2 "gpc_reg_operand" "r")
996 (const_int 16))
997 (zero_extend:SI
998 (match_operand:HI 1 "gpc_reg_operand" "r")))
999 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1000 "TARGET_MULHW"
1001 "macchwu %0, %1, %2"
1002 [(set_attr "type" "imul3")])
1003
1004(define_insn "*machhwc"
1005 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1006 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1007 (match_operand:SI 1 "gpc_reg_operand" "%r")
1008 (const_int 16))
1009 (ashiftrt:SI
1010 (match_operand:SI 2 "gpc_reg_operand" "r")
1011 (const_int 16)))
1012 (match_operand:SI 4 "gpc_reg_operand" "0"))
1013 (const_int 0)))
1014 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1015 (plus:SI (mult:SI (ashiftrt:SI
1016 (match_dup 1)
1017 (const_int 16))
1018 (ashiftrt:SI
1019 (match_dup 2)
1020 (const_int 16)))
1021 (match_dup 4)))]
1022 "TARGET_MULHW"
1023 "machhw. %0, %1, %2"
1024 [(set_attr "type" "imul3")])
1025
1026(define_insn "*machhw"
1027 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1028 (plus:SI (mult:SI (ashiftrt:SI
1029 (match_operand:SI 1 "gpc_reg_operand" "%r")
1030 (const_int 16))
1031 (ashiftrt:SI
1032 (match_operand:SI 2 "gpc_reg_operand" "r")
1033 (const_int 16)))
1034 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1035 "TARGET_MULHW"
1036 "machhw %0, %1, %2"
1037 [(set_attr "type" "imul3")])
1038
1039(define_insn "*machhwuc"
1040 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1041 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1042 (match_operand:SI 1 "gpc_reg_operand" "%r")
1043 (const_int 16))
1044 (lshiftrt:SI
1045 (match_operand:SI 2 "gpc_reg_operand" "r")
1046 (const_int 16)))
1047 (match_operand:SI 4 "gpc_reg_operand" "0"))
1048 (const_int 0)))
1049 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1050 (plus:SI (mult:SI (lshiftrt:SI
1051 (match_dup 1)
1052 (const_int 16))
1053 (lshiftrt:SI
1054 (match_dup 2)
1055 (const_int 16)))
1056 (match_dup 4)))]
1057 "TARGET_MULHW"
1058 "machhwu. %0, %1, %2"
1059 [(set_attr "type" "imul3")])
1060
1061(define_insn "*machhwu"
1062 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1063 (plus:SI (mult:SI (lshiftrt:SI
1064 (match_operand:SI 1 "gpc_reg_operand" "%r")
1065 (const_int 16))
1066 (lshiftrt:SI
1067 (match_operand:SI 2 "gpc_reg_operand" "r")
1068 (const_int 16)))
1069 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1070 "TARGET_MULHW"
1071 "machhwu %0, %1, %2"
1072 [(set_attr "type" "imul3")])
1073
1074(define_insn "*maclhwc"
1075 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1076 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1077 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1078 (sign_extend:SI
1079 (match_operand:HI 2 "gpc_reg_operand" "r")))
1080 (match_operand:SI 4 "gpc_reg_operand" "0"))
1081 (const_int 0)))
1082 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1083 (plus:SI (mult:SI (sign_extend:SI
1084 (match_dup 1))
1085 (sign_extend:SI
1086 (match_dup 2)))
1087 (match_dup 4)))]
1088 "TARGET_MULHW"
1089 "maclhw. %0, %1, %2"
1090 [(set_attr "type" "imul3")])
1091
1092(define_insn "*maclhw"
1093 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1094 (plus:SI (mult:SI (sign_extend:SI
1095 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1096 (sign_extend:SI
1097 (match_operand:HI 2 "gpc_reg_operand" "r")))
1098 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1099 "TARGET_MULHW"
1100 "maclhw %0, %1, %2"
1101 [(set_attr "type" "imul3")])
1102
1103(define_insn "*maclhwuc"
1104 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1105 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1106 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1107 (zero_extend:SI
1108 (match_operand:HI 2 "gpc_reg_operand" "r")))
1109 (match_operand:SI 4 "gpc_reg_operand" "0"))
1110 (const_int 0)))
1111 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1112 (plus:SI (mult:SI (zero_extend:SI
1113 (match_dup 1))
1114 (zero_extend:SI
1115 (match_dup 2)))
1116 (match_dup 4)))]
1117 "TARGET_MULHW"
1118 "maclhwu. %0, %1, %2"
1119 [(set_attr "type" "imul3")])
1120
1121(define_insn "*maclhwu"
1122 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1123 (plus:SI (mult:SI (zero_extend:SI
1124 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1125 (zero_extend:SI
1126 (match_operand:HI 2 "gpc_reg_operand" "r")))
1127 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1128 "TARGET_MULHW"
1129 "maclhwu %0, %1, %2"
1130 [(set_attr "type" "imul3")])
1131
1132(define_insn "*nmacchwc"
1133 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1134 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1135 (mult:SI (ashiftrt:SI
1136 (match_operand:SI 2 "gpc_reg_operand" "r")
1137 (const_int 16))
1138 (sign_extend:SI
1139 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1140 (const_int 0)))
1141 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1142 (minus:SI (match_dup 4)
1143 (mult:SI (ashiftrt:SI
1144 (match_dup 2)
1145 (const_int 16))
1146 (sign_extend:SI
1147 (match_dup 1)))))]
1148 "TARGET_MULHW"
1149 "nmacchw. %0, %1, %2"
1150 [(set_attr "type" "imul3")])
1151
1152(define_insn "*nmacchw"
1153 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1154 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1155 (mult:SI (ashiftrt:SI
1156 (match_operand:SI 2 "gpc_reg_operand" "r")
1157 (const_int 16))
1158 (sign_extend:SI
1159 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1160 "TARGET_MULHW"
1161 "nmacchw %0, %1, %2"
1162 [(set_attr "type" "imul3")])
1163
1164(define_insn "*nmachhwc"
1165 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1166 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1167 (mult:SI (ashiftrt:SI
1168 (match_operand:SI 1 "gpc_reg_operand" "%r")
1169 (const_int 16))
1170 (ashiftrt:SI
1171 (match_operand:SI 2 "gpc_reg_operand" "r")
1172 (const_int 16))))
1173 (const_int 0)))
1174 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1175 (minus:SI (match_dup 4)
1176 (mult:SI (ashiftrt:SI
1177 (match_dup 1)
1178 (const_int 16))
1179 (ashiftrt:SI
1180 (match_dup 2)
1181 (const_int 16)))))]
1182 "TARGET_MULHW"
1183 "nmachhw. %0, %1, %2"
1184 [(set_attr "type" "imul3")])
1185
1186(define_insn "*nmachhw"
1187 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1188 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1189 (mult:SI (ashiftrt:SI
1190 (match_operand:SI 1 "gpc_reg_operand" "%r")
1191 (const_int 16))
1192 (ashiftrt:SI
1193 (match_operand:SI 2 "gpc_reg_operand" "r")
1194 (const_int 16)))))]
1195 "TARGET_MULHW"
1196 "nmachhw %0, %1, %2"
1197 [(set_attr "type" "imul3")])
1198
1199(define_insn "*nmaclhwc"
1200 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1201 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1202 (mult:SI (sign_extend:SI
1203 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1204 (sign_extend:SI
1205 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1206 (const_int 0)))
1207 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1208 (minus:SI (match_dup 4)
1209 (mult:SI (sign_extend:SI
1210 (match_dup 1))
1211 (sign_extend:SI
1212 (match_dup 2)))))]
1213 "TARGET_MULHW"
1214 "nmaclhw. %0, %1, %2"
1215 [(set_attr "type" "imul3")])
1216
1217(define_insn "*nmaclhw"
1218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1219 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1220 (mult:SI (sign_extend:SI
1221 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1222 (sign_extend:SI
1223 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1224 "TARGET_MULHW"
1225 "nmaclhw %0, %1, %2"
1226 [(set_attr "type" "imul3")])
1227
1228(define_insn "*mulchwc"
1229 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1230 (compare:CC (mult:SI (ashiftrt:SI
1231 (match_operand:SI 2 "gpc_reg_operand" "r")
1232 (const_int 16))
1233 (sign_extend:SI
1234 (match_operand:HI 1 "gpc_reg_operand" "r")))
1235 (const_int 0)))
1236 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1237 (mult:SI (ashiftrt:SI
1238 (match_dup 2)
1239 (const_int 16))
1240 (sign_extend:SI
1241 (match_dup 1))))]
1242 "TARGET_MULHW"
1243 "mulchw. %0, %1, %2"
1244 [(set_attr "type" "imul3")])
1245
1246(define_insn "*mulchw"
1247 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1248 (mult:SI (ashiftrt:SI
1249 (match_operand:SI 2 "gpc_reg_operand" "r")
1250 (const_int 16))
1251 (sign_extend:SI
1252 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1253 "TARGET_MULHW"
1254 "mulchw %0, %1, %2"
1255 [(set_attr "type" "imul3")])
1256
1257(define_insn "*mulchwuc"
1258 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1259 (compare:CC (mult:SI (lshiftrt:SI
1260 (match_operand:SI 2 "gpc_reg_operand" "r")
1261 (const_int 16))
1262 (zero_extend:SI
1263 (match_operand:HI 1 "gpc_reg_operand" "r")))
1264 (const_int 0)))
1265 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1266 (mult:SI (lshiftrt:SI
1267 (match_dup 2)
1268 (const_int 16))
1269 (zero_extend:SI
1270 (match_dup 1))))]
1271 "TARGET_MULHW"
1272 "mulchwu. %0, %1, %2"
1273 [(set_attr "type" "imul3")])
1274
1275(define_insn "*mulchwu"
1276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1277 (mult:SI (lshiftrt:SI
1278 (match_operand:SI 2 "gpc_reg_operand" "r")
1279 (const_int 16))
1280 (zero_extend:SI
1281 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1282 "TARGET_MULHW"
1283 "mulchwu %0, %1, %2"
1284 [(set_attr "type" "imul3")])
1285
1286(define_insn "*mulhhwc"
1287 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1288 (compare:CC (mult:SI (ashiftrt:SI
1289 (match_operand:SI 1 "gpc_reg_operand" "%r")
1290 (const_int 16))
1291 (ashiftrt:SI
1292 (match_operand:SI 2 "gpc_reg_operand" "r")
1293 (const_int 16)))
1294 (const_int 0)))
1295 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1296 (mult:SI (ashiftrt:SI
1297 (match_dup 1)
1298 (const_int 16))
1299 (ashiftrt:SI
1300 (match_dup 2)
1301 (const_int 16))))]
1302 "TARGET_MULHW"
1303 "mulhhw. %0, %1, %2"
1304 [(set_attr "type" "imul3")])
1305
1306(define_insn "*mulhhw"
1307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1308 (mult:SI (ashiftrt:SI
1309 (match_operand:SI 1 "gpc_reg_operand" "%r")
1310 (const_int 16))
1311 (ashiftrt:SI
1312 (match_operand:SI 2 "gpc_reg_operand" "r")
1313 (const_int 16))))]
1314 "TARGET_MULHW"
1315 "mulhhw %0, %1, %2"
1316 [(set_attr "type" "imul3")])
1317
1318(define_insn "*mulhhwuc"
1319 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1320 (compare:CC (mult:SI (lshiftrt:SI
1321 (match_operand:SI 1 "gpc_reg_operand" "%r")
1322 (const_int 16))
1323 (lshiftrt:SI
1324 (match_operand:SI 2 "gpc_reg_operand" "r")
1325 (const_int 16)))
1326 (const_int 0)))
1327 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1328 (mult:SI (lshiftrt:SI
1329 (match_dup 1)
1330 (const_int 16))
1331 (lshiftrt:SI
1332 (match_dup 2)
1333 (const_int 16))))]
1334 "TARGET_MULHW"
1335 "mulhhwu. %0, %1, %2"
1336 [(set_attr "type" "imul3")])
1337
1338(define_insn "*mulhhwu"
1339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1340 (mult:SI (lshiftrt:SI
1341 (match_operand:SI 1 "gpc_reg_operand" "%r")
1342 (const_int 16))
1343 (lshiftrt:SI
1344 (match_operand:SI 2 "gpc_reg_operand" "r")
1345 (const_int 16))))]
1346 "TARGET_MULHW"
1347 "mulhhwu %0, %1, %2"
1348 [(set_attr "type" "imul3")])
1349
1350(define_insn "*mullhwc"
1351 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1352 (compare:CC (mult:SI (sign_extend:SI
1353 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1354 (sign_extend:SI
1355 (match_operand:HI 2 "gpc_reg_operand" "r")))
1356 (const_int 0)))
1357 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1358 (mult:SI (sign_extend:SI
1359 (match_dup 1))
1360 (sign_extend:SI
1361 (match_dup 2))))]
1362 "TARGET_MULHW"
1363 "mullhw. %0, %1, %2"
1364 [(set_attr "type" "imul3")])
1365
1366(define_insn "*mullhw"
1367 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1368 (mult:SI (sign_extend:SI
1369 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1370 (sign_extend:SI
1371 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1372 "TARGET_MULHW"
1373 "mullhw %0, %1, %2"
1374 [(set_attr "type" "imul3")])
1375
1376(define_insn "*mullhwuc"
1377 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1378 (compare:CC (mult:SI (zero_extend:SI
1379 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1380 (zero_extend:SI
1381 (match_operand:HI 2 "gpc_reg_operand" "r")))
1382 (const_int 0)))
1383 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1384 (mult:SI (zero_extend:SI
1385 (match_dup 1))
1386 (zero_extend:SI
1387 (match_dup 2))))]
1388 "TARGET_MULHW"
1389 "mullhwu. %0, %1, %2"
1390 [(set_attr "type" "imul3")])
1391
1392(define_insn "*mullhwu"
1393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1394 (mult:SI (zero_extend:SI
1395 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1396 (zero_extend:SI
1397 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1398 "TARGET_MULHW"
1399 "mullhwu %0, %1, %2"
1400 [(set_attr "type" "imul3")])
1401\f
716019c0
JM		 1402;; IBM 405 and 440 string-search dlmzb instruction support.
1403(define_insn "dlmzb"
1404 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1405 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1406 (match_operand:SI 2 "gpc_reg_operand" "r")]
1407 UNSPEC_DLMZB_CR))
1408 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1409 (unspec:SI [(match_dup 1)
1410 (match_dup 2)]
1411 UNSPEC_DLMZB))]
1412 "TARGET_DLMZB"
1413 "dlmzb. %0, %1, %2")
1414
1415(define_expand "strlensi"
1416 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1417 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1418 (match_operand:QI 2 "const_int_operand" "")
1419 (match_operand 3 "const_int_operand" "")]
1420 UNSPEC_DLMZB_STRLEN))
1421 (clobber (match_scratch:CC 4 "=x"))]
1422 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1423{
1424 rtx result = operands[0];
1425 rtx src = operands[1];
1426 rtx search_char = operands[2];
1427 rtx align = operands[3];
1428 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1429 rtx loop_label, end_label, mem, cr0, cond;
1430 if (search_char != const0_rtx
1431 || GET_CODE (align) != CONST_INT
1432 || INTVAL (align) < 8)
1433 FAIL;
1434 word1 = gen_reg_rtx (SImode);
1435 word2 = gen_reg_rtx (SImode);
1436 scratch_dlmzb = gen_reg_rtx (SImode);
1437 scratch_string = gen_reg_rtx (Pmode);
1438 loop_label = gen_label_rtx ();
1439 end_label = gen_label_rtx ();
1440 addr = force_reg (Pmode, XEXP (src, 0));
1441 emit_move_insn (scratch_string, addr);
1442 emit_label (loop_label);
1443 mem = change_address (src, SImode, scratch_string);
1444 emit_move_insn (word1, mem);
1445 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1446 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1447 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1448 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1449 emit_jump_insn (gen_rtx_SET (VOIDmode,
1450 pc_rtx,
1451 gen_rtx_IF_THEN_ELSE (VOIDmode,
1452 cond,
1453 gen_rtx_LABEL_REF
1454 (VOIDmode,
1455 end_label),
1456 pc_rtx)));
1457 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1458 emit_jump_insn (gen_rtx_SET (VOIDmode,
1459 pc_rtx,
1460 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
ea5bd0d8 1461 emit_barrier ();
716019c0
JM		 1462 emit_label (end_label);
1463 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1464 emit_insn (gen_subsi3 (result, scratch_string, addr));
1465 emit_insn (gen_subsi3 (result, result, const1_rtx));
1466 DONE;
1467})
1468\f
9ebbca7d
GK		 1469(define_split
1470 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1471 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1472 (const_int 0)))
1473 (set (match_operand:SI 0 "gpc_reg_operand" "")
1474 (sign_extend:SI (match_dup 1)))]
1475 "reload_completed"
1476 [(set (match_dup 0)
1477 (sign_extend:SI (match_dup 1)))
1478 (set (match_dup 2)
1479 (compare:CC (match_dup 0)
1480 (const_int 0)))]
1481 "")
1482
1fd4e8c1 1483;; Fixed-point arithmetic insns.
deb9225a 1484
0354e5d8
GK		 1485(define_expand "add<mode>3"
1486 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1487 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
4ae234b0 1488 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
7cd5235b 1489 ""
7cd5235b 1490{
0354e5d8
GK		 1491 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1492 {
1493 if (non_short_cint_operand (operands[2], DImode))
1494 FAIL;
1495 }
1496 else if (GET_CODE (operands[2]) == CONST_INT
1497 && ! add_operand (operands[2], <MODE>mode))
7cd5235b 1498 {
b3a13419
ILT		 1499 rtx tmp = ((!can_create_pseudo_p ()
1500 || rtx_equal_p (operands[0], operands[1]))
0354e5d8 1501 ? operands[0] : gen_reg_rtx (<MODE>mode));
7cd5235b 1502
2bfcf297 1503 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1504 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8
GK		 1505 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1506
279bb624 1507 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1508 FAIL;
7cd5235b 1509
9ebbca7d
GK		 1510 /* The ordering here is important for the prolog expander.
1511 When space is allocated from the stack, adding 'low' first may
1512 produce a temporary deallocation (which would be bad). */
0354e5d8
GK		 1513 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1514 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
7cd5235b
MM		 1515 DONE;
1516 }
279bb624 1517})
7cd5235b 1518
0354e5d8
GK		 1519;; Discourage ai/addic because of carry but provide it in an alternative
1520;; allowing register zero as source.
1521(define_insn "*add<mode>3_internal1"
1522 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1523 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1524 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
7393f7f8 1525 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1fd4e8c1 1526 "@
deb9225a
RK		 1527 {cax|add} %0,%1,%2
1528 {cal %0,%2(%1)|addi %0,%1,%2}
1529 {ai|addic} %0,%1,%2
7cd5235b
MM		 1530 {cau|addis} %0,%1,%v2"
1531 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 1532
ee890fe2
SS		 1533(define_insn "addsi3_high"
1534 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1535 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1536 (high:SI (match_operand 2 "" ""))))]
1537 "TARGET_MACHO && !TARGET_64BIT"
1538 "{cau|addis} %0,%1,ha16(%2)"
1539 [(set_attr "length" "4")])
1540
0354e5d8 1541(define_insn "*add<mode>3_internal2"
cb8cc086 1542 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1543 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1544 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1545 (const_int 0)))
0354e5d8
GK		 1546 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1547 ""
deb9225a
RK		 1548 "@
1549 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1550 {ai.|addic.} %3,%1,%2
1551 #
1552 #"
a62bfff2 1553 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1554 (set_attr "length" "4,4,8,8")])
1555
1556(define_split
1557 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1558 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1559 (match_operand:GPR 2 "reg_or_short_operand" ""))
cb8cc086 1560 (const_int 0)))
0354e5d8
GK		 1561 (clobber (match_scratch:GPR 3 ""))]
1562 "reload_completed"
cb8cc086 1563 [(set (match_dup 3)
0354e5d8 1564 (plus:GPR (match_dup 1)
cb8cc086
MM		 1565 (match_dup 2)))
1566 (set (match_dup 0)
1567 (compare:CC (match_dup 3)
1568 (const_int 0)))]
1569 "")
7e69e155 1570
0354e5d8 1571(define_insn "*add<mode>3_internal3"
cb8cc086 1572 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1573 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1574 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1575 (const_int 0)))
0354e5d8
GK		 1576 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1577 (plus:P (match_dup 1)
1578 (match_dup 2)))]
1579 ""
deb9225a
RK		 1580 "@
1581 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1582 {ai.|addic.} %0,%1,%2
1583 #
1584 #"
a62bfff2 1585 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1586 (set_attr "length" "4,4,8,8")])
1587
1588(define_split
1589 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1590 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1591 (match_operand:P 2 "reg_or_short_operand" ""))
cb8cc086 1592 (const_int 0)))
0354e5d8
GK		 1593 (set (match_operand:P 0 "gpc_reg_operand" "")
1594 (plus:P (match_dup 1) (match_dup 2)))]
1595 "reload_completed"
cb8cc086 1596 [(set (match_dup 0)
0354e5d8
GK		 1597 (plus:P (match_dup 1)
1598 (match_dup 2)))
cb8cc086
MM		 1599 (set (match_dup 3)
1600 (compare:CC (match_dup 0)
1601 (const_int 0)))]
1602 "")
7e69e155 1603
f357808b
RK		 1604;; Split an add that we can't do in one insn into two insns, each of which
1605;; does one 16-bit part. This is used by combine. Note that the low-order
1606;; add should be last in case the result gets used in an address.
1607
1608(define_split
0354e5d8
GK		 1609 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1610 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1611 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1fd4e8c1 1612 ""
0354e5d8
GK		 1613 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1614 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1fd4e8c1 1615{
2bfcf297 1616 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1617 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8 1618 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1fd4e8c1 1619
e6ca2c17 1620 operands[4] = GEN_INT (low);
279bb624 1621 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1622 operands[3] = GEN_INT (rest);
b3a13419 1623 else if (can_create_pseudo_p ())
0354e5d8
GK		 1624 {
1625 operands[3] = gen_reg_rtx (DImode);
1626 emit_move_insn (operands[3], operands[2]);
1627 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1628 DONE;
1629 }
1630 else
1631 FAIL;
279bb624 1632})
1fd4e8c1 1633
0354e5d8
GK		 1634(define_insn "one_cmpl<mode>2"
1635 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1636 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1637 ""
ca7f5001
RK		 1638 "nor %0,%1,%1")
1639
1640(define_insn ""
52d3af72 1641 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 1642 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
ca7f5001 1643 (const_int 0)))
0354e5d8
GK		 1644 (clobber (match_scratch:P 2 "=r,r"))]
1645 ""
52d3af72
DE		 1646 "@
1647 nor. %2,%1,%1
1648 #"
1649 [(set_attr "type" "compare")
1650 (set_attr "length" "4,8")])
1651
1652(define_split
1653 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 1654 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1655 (const_int 0)))
0354e5d8
GK		 1656 (clobber (match_scratch:P 2 ""))]
1657 "reload_completed"
52d3af72 1658 [(set (match_dup 2)
0354e5d8 1659 (not:P (match_dup 1)))
52d3af72
DE		 1660 (set (match_dup 0)
1661 (compare:CC (match_dup 2)
1662 (const_int 0)))]
1663 "")
ca7f5001
RK		 1664
1665(define_insn ""
52d3af72 1666 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 1667 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 1668 (const_int 0)))
0354e5d8
GK		 1669 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1670 (not:P (match_dup 1)))]
1671 ""
52d3af72
DE		 1672 "@
1673 nor. %0,%1,%1
1674 #"
1675 [(set_attr "type" "compare")
1676 (set_attr "length" "4,8")])
1677
1678(define_split
1679 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 1680 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1681 (const_int 0)))
0354e5d8
GK		 1682 (set (match_operand:P 0 "gpc_reg_operand" "")
1683 (not:P (match_dup 1)))]
1684 "reload_completed"
52d3af72 1685 [(set (match_dup 0)
0354e5d8 1686 (not:P (match_dup 1)))
52d3af72
DE		 1687 (set (match_dup 2)
1688 (compare:CC (match_dup 0)
1689 (const_int 0)))]
1690 "")
1fd4e8c1
RK		 1691
1692(define_insn ""
3d91674b
RK		 1693 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1694 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1695 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1696 "! TARGET_POWERPC"
ca7f5001 1697 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1698
deb9225a 1699(define_insn ""
0354e5d8
GK		 1700 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1701 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1702 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
deb9225a
RK		 1703 "TARGET_POWERPC"
1704 "@
1705 subf %0,%2,%1
1706 subfic %0,%2,%1")
1707
1fd4e8c1 1708(define_insn ""
cb8cc086
MM		 1709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1710 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1711 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1712 (const_int 0)))
cb8cc086 1713 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1714 "! TARGET_POWERPC"
cb8cc086
MM		 1715 "@
1716 {sf.|subfc.} %3,%2,%1
1717 #"
1718 [(set_attr "type" "compare")
1719 (set_attr "length" "4,8")])
1fd4e8c1 1720
deb9225a 1721(define_insn ""
cb8cc086 1722 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1723 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1724 (match_operand:P 2 "gpc_reg_operand" "r,r"))
deb9225a 1725 (const_int 0)))
0354e5d8
GK		 1726 (clobber (match_scratch:P 3 "=r,r"))]
1727 "TARGET_POWERPC"
cb8cc086
MM		 1728 "@
1729 subf. %3,%2,%1
1730 #"
a62bfff2 1731 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1732 (set_attr "length" "4,8")])
1733
1734(define_split
1735 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1736 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1737 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1738 (const_int 0)))
0354e5d8
GK		 1739 (clobber (match_scratch:P 3 ""))]
1740 "reload_completed"
cb8cc086 1741 [(set (match_dup 3)
0354e5d8 1742 (minus:P (match_dup 1)
cb8cc086
MM		 1743 (match_dup 2)))
1744 (set (match_dup 0)
1745 (compare:CC (match_dup 3)
1746 (const_int 0)))]
1747 "")
deb9225a 1748
1fd4e8c1 1749(define_insn ""
cb8cc086
MM		 1750 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1751 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1752 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1753 (const_int 0)))
cb8cc086 1754 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1755 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1756 "! TARGET_POWERPC"
cb8cc086
MM		 1757 "@
1758 {sf.|subfc.} %0,%2,%1
1759 #"
1760 [(set_attr "type" "compare")
1761 (set_attr "length" "4,8")])
815cdc52 1762
29ae5b89 1763(define_insn ""
cb8cc086 1764 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1765 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1766 (match_operand:P 2 "gpc_reg_operand" "r,r"))
815cdc52 1767 (const_int 0)))
0354e5d8
GK		 1768 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1769 (minus:P (match_dup 1)
cb8cc086 1770 (match_dup 2)))]
0354e5d8 1771 "TARGET_POWERPC"
90612787
DE		 1772 "@
1773 subf. %0,%2,%1
1774 #"
a62bfff2 1775 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1776 (set_attr "length" "4,8")])
1777
1778(define_split
1779 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1780 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1781 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1782 (const_int 0)))
0354e5d8
GK		 1783 (set (match_operand:P 0 "gpc_reg_operand" "")
1784 (minus:P (match_dup 1)
cb8cc086 1785 (match_dup 2)))]
0354e5d8 1786 "reload_completed"
cb8cc086 1787 [(set (match_dup 0)
0354e5d8 1788 (minus:P (match_dup 1)
cb8cc086
MM		 1789 (match_dup 2)))
1790 (set (match_dup 3)
1791 (compare:CC (match_dup 0)
1792 (const_int 0)))]
1793 "")
deb9225a 1794
0354e5d8
GK		 1795(define_expand "sub<mode>3"
1796 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1797 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
4ae234b0 1798 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1fd4e8c1 1799 ""
a0044fb1
RK		 1800 "
1801{
1802 if (GET_CODE (operands[2]) == CONST_INT)
1803 {
0354e5d8
GK		 1804 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1805 negate_rtx (<MODE>mode, operands[2])));
a0044fb1
RK		 1806 DONE;
1807 }
1808}")
1fd4e8c1
RK		 1809
1810;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1811;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1812;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1813;; combine.
1fd4e8c1
RK		 1814
1815(define_expand "sminsi3"
1816 [(set (match_dup 3)
cd2b37d9 1817 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1818 (match_operand:SI 2 "reg_or_short_operand" ""))
1819 (const_int 0)
1820 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1821 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1822 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1823 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1824 "
a3170dc6
AH		 1825{
1826 if (TARGET_ISEL)
1827 {
1828 operands[2] = force_reg (SImode, operands[2]);
1829 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1830 DONE;
1831 }
1832
1833 operands[3] = gen_reg_rtx (SImode);
1834}")
1fd4e8c1 1835
95ac8e67
RK		 1836(define_split
1837 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1838 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1839 (match_operand:SI 2 "reg_or_short_operand" "")))
1840 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1841 "TARGET_POWER"
95ac8e67
RK		 1842 [(set (match_dup 3)
1843 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1844 (const_int 0)
1845 (minus:SI (match_dup 2) (match_dup 1))))
1846 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1847 "")
1848
1fd4e8c1
RK		 1849(define_expand "smaxsi3"
1850 [(set (match_dup 3)
cd2b37d9 1851 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1852 (match_operand:SI 2 "reg_or_short_operand" ""))
1853 (const_int 0)
1854 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1855 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1856 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1857 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1858 "
a3170dc6
AH		 1859{
1860 if (TARGET_ISEL)
1861 {
1862 operands[2] = force_reg (SImode, operands[2]);
1863 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1864 DONE;
1865 }
1866 operands[3] = gen_reg_rtx (SImode);
1867}")
1fd4e8c1 1868
95ac8e67
RK		 1869(define_split
1870 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1871 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1872 (match_operand:SI 2 "reg_or_short_operand" "")))
1873 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1874 "TARGET_POWER"
95ac8e67
RK		 1875 [(set (match_dup 3)
1876 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1877 (const_int 0)
1878 (minus:SI (match_dup 2) (match_dup 1))))
1879 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1880 "")
1881
1fd4e8c1 1882(define_expand "uminsi3"
cd2b37d9 1883 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1884 (match_dup 5)))
cd2b37d9 1885 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1886 (match_dup 5)))
1fd4e8c1
RK		 1887 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1888 (const_int 0)
1889 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1890 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1891 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1892 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1893 "
bb68ff55 1894{
a3170dc6
AH		 1895 if (TARGET_ISEL)
1896 {
1897 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1898 DONE;
1899 }
bb68ff55
MM		 1900 operands[3] = gen_reg_rtx (SImode);
1901 operands[4] = gen_reg_rtx (SImode);
1902 operands[5] = GEN_INT (-2147483647 - 1);
1903}")
1fd4e8c1
RK		 1904
1905(define_expand "umaxsi3"
cd2b37d9 1906 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1907 (match_dup 5)))
cd2b37d9 1908 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1909 (match_dup 5)))
1fd4e8c1
RK		 1910 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1911 (const_int 0)
1912 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1913 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1914 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1915 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1916 "
bb68ff55 1917{
a3170dc6
AH		 1918 if (TARGET_ISEL)
1919 {
1920 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1921 DONE;
1922 }
bb68ff55
MM		 1923 operands[3] = gen_reg_rtx (SImode);
1924 operands[4] = gen_reg_rtx (SImode);
1925 operands[5] = GEN_INT (-2147483647 - 1);
1926}")
1fd4e8c1
RK		 1927
1928(define_insn ""
cd2b37d9
RK		 1929 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1930 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1931 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1932 (const_int 0)
1933 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1934 "TARGET_POWER"
1fd4e8c1
RK		 1935 "doz%I2 %0,%1,%2")
1936
1937(define_insn ""
9ebbca7d 1938 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1939 (compare:CC
9ebbca7d
GK		 1940 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1941 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1942 (const_int 0)
1943 (minus:SI (match_dup 2) (match_dup 1)))
1944 (const_int 0)))
9ebbca7d 1945 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1946 "TARGET_POWER"
9ebbca7d
GK		 1947 "@
1948 doz%I2. %3,%1,%2
1949 #"
1950 [(set_attr "type" "delayed_compare")
1951 (set_attr "length" "4,8")])
1952
1953(define_split
1954 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1955 (compare:CC
1956 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1957 (match_operand:SI 2 "reg_or_short_operand" ""))
1958 (const_int 0)
1959 (minus:SI (match_dup 2) (match_dup 1)))
1960 (const_int 0)))
1961 (clobber (match_scratch:SI 3 ""))]
1962 "TARGET_POWER && reload_completed"
1963 [(set (match_dup 3)
1964 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1965 (const_int 0)
1966 (minus:SI (match_dup 2) (match_dup 1))))
1967 (set (match_dup 0)
1968 (compare:CC (match_dup 3)
1969 (const_int 0)))]
1970 "")
1fd4e8c1
RK		 1971
1972(define_insn ""
9ebbca7d 1973 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1974 (compare:CC
9ebbca7d
GK		 1975 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1976 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1977 (const_int 0)
1978 (minus:SI (match_dup 2) (match_dup 1)))
1979 (const_int 0)))
9ebbca7d 1980 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1981 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1982 (const_int 0)
1983 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1984 "TARGET_POWER"
9ebbca7d
GK		 1985 "@
1986 doz%I2. %0,%1,%2
1987 #"
1988 [(set_attr "type" "delayed_compare")
1989 (set_attr "length" "4,8")])
1990
1991(define_split
1992 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1993 (compare:CC
1994 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1995 (match_operand:SI 2 "reg_or_short_operand" ""))
1996 (const_int 0)
1997 (minus:SI (match_dup 2) (match_dup 1)))
1998 (const_int 0)))
1999 (set (match_operand:SI 0 "gpc_reg_operand" "")
2000 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2001 (const_int 0)
2002 (minus:SI (match_dup 2) (match_dup 1))))]
2003 "TARGET_POWER && reload_completed"
2004 [(set (match_dup 0)
2005 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2006 (const_int 0)
2007 (minus:SI (match_dup 2) (match_dup 1))))
2008 (set (match_dup 3)
2009 (compare:CC (match_dup 0)
2010 (const_int 0)))]
2011 "")
1fd4e8c1
RK		 2012
2013;; We don't need abs with condition code because such comparisons should
2014;; never be done.
ea9be077
MM		 2015(define_expand "abssi2"
2016 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2017 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2018 ""
2019 "
2020{
a3170dc6
AH		 2021 if (TARGET_ISEL)
2022 {
2023 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2024 DONE;
2025 }
2026 else if (! TARGET_POWER)
ea9be077
MM		 2027 {
2028 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2029 DONE;
2030 }
2031}")
2032
ea112fc4 2033(define_insn "*abssi2_power"
cd2b37d9
RK		 2034 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2035 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 2036 "TARGET_POWER"
1fd4e8c1
RK		 2037 "abs %0,%1")
2038
a3170dc6
AH		 2039(define_insn_and_split "abssi2_isel"
2040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2041 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 2042 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 2043 (clobber (match_scratch:CC 3 "=y"))]
2044 "TARGET_ISEL"
2045 "#"
2046 "&& reload_completed"
2047 [(set (match_dup 2) (neg:SI (match_dup 1)))
2048 (set (match_dup 3)
2049 (compare:CC (match_dup 1)
2050 (const_int 0)))
2051 (set (match_dup 0)
2052 (if_then_else:SI (ge (match_dup 3)
2053 (const_int 0))
2054 (match_dup 1)
2055 (match_dup 2)))]
2056 "")
2057
ea112fc4 2058(define_insn_and_split "abssi2_nopower"
ea9be077 2059 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2060 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 2061 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 2062 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 2063 "#"
2064 "&& reload_completed"
ea9be077
MM		 2065 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2066 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2067 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 2068 "")
2069
463b558b 2070(define_insn "*nabs_power"
cd2b37d9
RK		 2071 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2072 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 2073 "TARGET_POWER"
1fd4e8c1
RK		 2074 "nabs %0,%1")
2075
ea112fc4 2076(define_insn_and_split "*nabs_nopower"
ea9be077 2077 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2078 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 2079 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 2080 "! TARGET_POWER"
ea112fc4
DE		 2081 "#"
2082 "&& reload_completed"
ea9be077
MM		 2083 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2084 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2085 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 2086 "")
2087
0354e5d8
GK		 2088(define_expand "neg<mode>2"
2089 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2090 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2091 ""
2092 "")
2093
2094(define_insn "*neg<mode>2_internal"
2095 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2096 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 2097 ""
2098 "neg %0,%1")
2099
2100(define_insn ""
9ebbca7d 2101 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 2102 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 2103 (const_int 0)))
0354e5d8
GK		 2104 (clobber (match_scratch:P 2 "=r,r"))]
2105 ""
9ebbca7d
GK		 2106 "@
2107 neg. %2,%1
2108 #"
a62bfff2 2109 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2110 (set_attr "length" "4,8")])
2111
2112(define_split
2113 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 2114 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2115 (const_int 0)))
0354e5d8
GK		 2116 (clobber (match_scratch:P 2 ""))]
2117 "reload_completed"
9ebbca7d 2118 [(set (match_dup 2)
0354e5d8 2119 (neg:P (match_dup 1)))
9ebbca7d
GK		 2120 (set (match_dup 0)
2121 (compare:CC (match_dup 2)
2122 (const_int 0)))]
2123 "")
1fd4e8c1
RK		 2124
2125(define_insn ""
9ebbca7d 2126 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 2127 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 2128 (const_int 0)))
0354e5d8
GK		 2129 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2130 (neg:P (match_dup 1)))]
2131 ""
9ebbca7d
GK		 2132 "@
2133 neg. %0,%1
2134 #"
a62bfff2 2135 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2136 (set_attr "length" "4,8")])
2137
2138(define_split
2139 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 2140 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2141 (const_int 0)))
0354e5d8
GK		 2142 (set (match_operand:P 0 "gpc_reg_operand" "")
2143 (neg:P (match_dup 1)))]
66859ace 2144 "reload_completed"
9ebbca7d 2145 [(set (match_dup 0)
0354e5d8 2146 (neg:P (match_dup 1)))
9ebbca7d
GK		 2147 (set (match_dup 2)
2148 (compare:CC (match_dup 0)
2149 (const_int 0)))]
2150 "")
1fd4e8c1 2151
0354e5d8
GK		 2152(define_insn "clz<mode>2"
2153 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2154 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1b1edcfa 2155 ""
44cd321e
PS		 2156 "{cntlz|cntlz<wd>} %0,%1"
2157 [(set_attr "type" "cntlz")])
1b1edcfa 2158
0354e5d8 2159(define_expand "ctz<mode>2"
4977bab6 2160 [(set (match_dup 2)
e42ac3de 2161 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2162 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2163 (match_dup 2)))
1b1edcfa 2164 (clobber (scratch:CC))])
0354e5d8 2165 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2166 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2167 (minus:GPR (match_dup 5) (match_dup 4)))]
1fd4e8c1 2168 ""
4977bab6 2169 {
0354e5d8
GK		 2170 operands[2] = gen_reg_rtx (<MODE>mode);
2171 operands[3] = gen_reg_rtx (<MODE>mode);
2172 operands[4] = gen_reg_rtx (<MODE>mode);
2173 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
4977bab6 2174 })
6ae08853 2175
0354e5d8 2176(define_expand "ffs<mode>2"
1b1edcfa 2177 [(set (match_dup 2)
e42ac3de 2178 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2179 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2180 (match_dup 2)))
1b1edcfa 2181 (clobber (scratch:CC))])
0354e5d8 2182 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2183 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2184 (minus:GPR (match_dup 5) (match_dup 4)))]
4977bab6 2185 ""
1b1edcfa 2186 {
0354e5d8
GK		 2187 operands[2] = gen_reg_rtx (<MODE>mode);
2188 operands[3] = gen_reg_rtx (<MODE>mode);
2189 operands[4] = gen_reg_rtx (<MODE>mode);
2190 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1b1edcfa 2191 })
6ae08853 2192
432218ba
DE		 2193(define_insn "popcntb<mode>2"
2194 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2195 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2196 UNSPEC_POPCNTB))]
2197 "TARGET_POPCNTB"
2198 "popcntb %0,%1")
2199
565ef4ba 2200(define_expand "popcount<mode>2"
e42ac3de
RS		 2201 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2202 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2203 "TARGET_POPCNTB"
2204 {
2205 rs6000_emit_popcount (operands[0], operands[1]);
2206 DONE;
2207 })
2208
2209(define_expand "parity<mode>2"
e42ac3de
RS		 2210 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2211 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2212 "TARGET_POPCNTB"
2213 {
2214 rs6000_emit_parity (operands[0], operands[1]);
2215 DONE;
2216 })
2217
03f79051
DE		 2218(define_insn "bswapsi2"
2219 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2220 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2221 ""
2222 "@
2223 {lbrx|lwbrx} %0,%y1
2224 {stbrx|stwbrx} %1,%y0
2225 #"
2226 [(set_attr "length" "4,4,12")])
2227
2228(define_split
2229 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2230 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2231 "reload_completed"
2232 [(set (match_dup 0)
2233 (rotate:SI (match_dup 1) (const_int 8)))
2234 (set (zero_extract:SI (match_dup 0)
2235 (const_int 8)
2236 (const_int 0))
2237 (match_dup 1))
2238 (set (zero_extract:SI (match_dup 0)
2239 (const_int 8)
2240 (const_int 16))
2241 (rotate:SI (match_dup 1)
2242 (const_int 16)))]
2243 "")
2244
ca7f5001
RK		 2245(define_expand "mulsi3"
2246 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2247 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2248 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2249 ""
2250 "
2251{
2252 if (TARGET_POWER)
68b40e7e 2253 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 2254 else
68b40e7e 2255 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 2256 DONE;
2257}")
2258
68b40e7e 2259(define_insn "mulsi3_mq"
cd2b37d9
RK		 2260 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2261 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 2262 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2263 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 2264 "TARGET_POWER"
2265 "@
2266 {muls|mullw} %0,%1,%2
2267 {muli|mulli} %0,%1,%2"
6ae08853 2268 [(set (attr "type")
c859cda6
DJ		 2269 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2270 (const_string "imul3")
6ae08853 2271 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2272 (const_string "imul2")]
2273 (const_string "imul")))])
ca7f5001 2274
68b40e7e 2275(define_insn "mulsi3_no_mq"
ca7f5001
RK		 2276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2277 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2278 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 2279 "! TARGET_POWER"
1fd4e8c1 2280 "@
d904e9ed
RK		 2281 {muls|mullw} %0,%1,%2
2282 {muli|mulli} %0,%1,%2"
6ae08853 2283 [(set (attr "type")
c859cda6
DJ		 2284 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2285 (const_string "imul3")
6ae08853 2286 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2287 (const_string "imul2")]
2288 (const_string "imul")))])
1fd4e8c1 2289
9259f3b0 2290(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 2291 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2292 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2293 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2294 (const_int 0)))
9ebbca7d
GK		 2295 (clobber (match_scratch:SI 3 "=r,r"))
2296 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2297 "TARGET_POWER"
9ebbca7d
GK		 2298 "@
2299 {muls.|mullw.} %3,%1,%2
2300 #"
9259f3b0 2301 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2302 (set_attr "length" "4,8")])
2303
2304(define_split
2305 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2306 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2307 (match_operand:SI 2 "gpc_reg_operand" ""))
2308 (const_int 0)))
2309 (clobber (match_scratch:SI 3 ""))
2310 (clobber (match_scratch:SI 4 ""))]
2311 "TARGET_POWER && reload_completed"
2312 [(parallel [(set (match_dup 3)
2313 (mult:SI (match_dup 1) (match_dup 2)))
2314 (clobber (match_dup 4))])
2315 (set (match_dup 0)
2316 (compare:CC (match_dup 3)
2317 (const_int 0)))]
2318 "")
ca7f5001 2319
9259f3b0 2320(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 2321 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2322 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2323 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2324 (const_int 0)))
9ebbca7d 2325 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 2326 "! TARGET_POWER"
9ebbca7d
GK		 2327 "@
2328 {muls.|mullw.} %3,%1,%2
2329 #"
9259f3b0 2330 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2331 (set_attr "length" "4,8")])
2332
2333(define_split
2334 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2335 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2336 (match_operand:SI 2 "gpc_reg_operand" ""))
2337 (const_int 0)))
2338 (clobber (match_scratch:SI 3 ""))]
2339 "! TARGET_POWER && reload_completed"
2340 [(set (match_dup 3)
2341 (mult:SI (match_dup 1) (match_dup 2)))
2342 (set (match_dup 0)
2343 (compare:CC (match_dup 3)
2344 (const_int 0)))]
2345 "")
1fd4e8c1 2346
9259f3b0 2347(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 2348 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2349 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2350 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2351 (const_int 0)))
9ebbca7d 2352 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 2353 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 2354 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2355 "TARGET_POWER"
9ebbca7d
GK		 2356 "@
2357 {muls.|mullw.} %0,%1,%2
2358 #"
9259f3b0 2359 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2360 (set_attr "length" "4,8")])
2361
2362(define_split
2363 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2364 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2365 (match_operand:SI 2 "gpc_reg_operand" ""))
2366 (const_int 0)))
2367 (set (match_operand:SI 0 "gpc_reg_operand" "")
2368 (mult:SI (match_dup 1) (match_dup 2)))
2369 (clobber (match_scratch:SI 4 ""))]
2370 "TARGET_POWER && reload_completed"
2371 [(parallel [(set (match_dup 0)
2372 (mult:SI (match_dup 1) (match_dup 2)))
2373 (clobber (match_dup 4))])
2374 (set (match_dup 3)
2375 (compare:CC (match_dup 0)
2376 (const_int 0)))]
2377 "")
ca7f5001 2378
9259f3b0 2379(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 2380 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2381 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2382 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2383 (const_int 0)))
9ebbca7d 2384 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 2385 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 2386 "! TARGET_POWER"
9ebbca7d
GK		 2387 "@
2388 {muls.|mullw.} %0,%1,%2
2389 #"
9259f3b0 2390 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2391 (set_attr "length" "4,8")])
2392
2393(define_split
2394 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2395 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2396 (match_operand:SI 2 "gpc_reg_operand" ""))
2397 (const_int 0)))
2398 (set (match_operand:SI 0 "gpc_reg_operand" "")
2399 (mult:SI (match_dup 1) (match_dup 2)))]
2400 "! TARGET_POWER && reload_completed"
2401 [(set (match_dup 0)
2402 (mult:SI (match_dup 1) (match_dup 2)))
2403 (set (match_dup 3)
2404 (compare:CC (match_dup 0)
2405 (const_int 0)))]
2406 "")
1fd4e8c1
RK		 2407
2408;; Operand 1 is divided by operand 2; quotient goes to operand
2409;; 0 and remainder to operand 3.
2410;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2411
8ffd9c51
RK		 2412(define_expand "divmodsi4"
2413 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2414 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2415 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 2416 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 2417 (mod:SI (match_dup 1) (match_dup 2)))])]
2418 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2419 "
2420{
2421 if (! TARGET_POWER && ! TARGET_POWERPC)
2422 {
39403d82
DE		 2423 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2424 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2425 emit_insn (gen_divss_call ());
39403d82
DE		 2426 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2427 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 2428 DONE;
2429 }
2430}")
deb9225a 2431
bb157ff4 2432(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 2433 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2434 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2435 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 2436 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 2437 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 2438 "TARGET_POWER"
cfb557c4
RK		 2439 "divs %0,%1,%2"
2440 [(set_attr "type" "idiv")])
1fd4e8c1 2441
4ae234b0
GK		 2442(define_expand "udiv<mode>3"
2443 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2444 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2445 (match_operand:GPR 2 "gpc_reg_operand" "")))]
8ffd9c51
RK		 2446 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2447 "
2448{
2449 if (! TARGET_POWER && ! TARGET_POWERPC)
2450 {
39403d82
DE		 2451 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2452 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2453 emit_insn (gen_quous_call ());
39403d82 2454 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2455 DONE;
2456 }
f192bf8b
DE		 2457 else if (TARGET_POWER)
2458 {
2459 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2460 DONE;
2461 }
8ffd9c51 2462}")
deb9225a 2463
f192bf8b
DE		 2464(define_insn "udivsi3_mq"
2465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2466 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2467 (match_operand:SI 2 "gpc_reg_operand" "r")))
2468 (clobber (match_scratch:SI 3 "=q"))]
2469 "TARGET_POWERPC && TARGET_POWER"
2470 "divwu %0,%1,%2"
2471 [(set_attr "type" "idiv")])
2472
2473(define_insn "*udivsi3_no_mq"
4ae234b0
GK		 2474 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2475 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2476 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2477 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2478 "div<wd>u %0,%1,%2"
44cd321e
PS		 2479 [(set (attr "type")
2480 (cond [(match_operand:SI 0 "" "")
2481 (const_string "idiv")]
2482 (const_string "ldiv")))])
2483
ca7f5001 2484
1fd4e8c1 2485;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 2486;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 2487;; used; for PowerPC, force operands into register and do a normal divide;
2488;; for AIX common-mode, use quoss call on register operands.
4ae234b0
GK		 2489(define_expand "div<mode>3"
2490 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2491 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2492 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1fd4e8c1
RK		 2493 ""
2494 "
2495{
ca7f5001 2496 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 2497 && INTVAL (operands[2]) > 0
ca7f5001
RK		 2498 && exact_log2 (INTVAL (operands[2])) >= 0)
2499 ;
b6c9286a 2500 else if (TARGET_POWERPC)
f192bf8b 2501 {
99e8e649 2502 operands[2] = force_reg (<MODE>mode, operands[2]);
f192bf8b
DE		 2503 if (TARGET_POWER)
2504 {
2505 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2506 DONE;
2507 }
2508 }
b6c9286a 2509 else if (TARGET_POWER)
1fd4e8c1 2510 FAIL;
405c5495 2511 else
8ffd9c51 2512 {
39403d82
DE		 2513 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2514 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2515 emit_insn (gen_quoss_call ());
39403d82 2516 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2517 DONE;
2518 }
1fd4e8c1
RK		 2519}")
2520
f192bf8b
DE		 2521(define_insn "divsi3_mq"
2522 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2523 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2524 (match_operand:SI 2 "gpc_reg_operand" "r")))
2525 (clobber (match_scratch:SI 3 "=q"))]
2526 "TARGET_POWERPC && TARGET_POWER"
2527 "divw %0,%1,%2"
2528 [(set_attr "type" "idiv")])
2529
4ae234b0
GK		 2530(define_insn "*div<mode>3_no_mq"
2531 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2532 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2533 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2534 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2535 "div<wd> %0,%1,%2"
44cd321e
PS		 2536 [(set (attr "type")
2537 (cond [(match_operand:SI 0 "" "")
2538 (const_string "idiv")]
2539 (const_string "ldiv")))])
f192bf8b 2540
4ae234b0
GK		 2541(define_expand "mod<mode>3"
2542 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2543 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2544 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
39b52ba2 2545 ""
1fd4e8c1
RK		 2546 "
2547{
481c7efa 2548 int i;
39b52ba2
RK		 2549 rtx temp1;
2550 rtx temp2;
2551
2bfcf297 2552 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 2553 || INTVAL (operands[2]) <= 0
2bfcf297 2554 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 2555 FAIL;
2556
4ae234b0
GK		 2557 temp1 = gen_reg_rtx (<MODE>mode);
2558 temp2 = gen_reg_rtx (<MODE>mode);
1fd4e8c1 2559
4ae234b0
GK		 2560 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2561 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2562 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
85644414 2563 DONE;
1fd4e8c1
RK		 2564}")
2565
2566(define_insn ""
4ae234b0
GK		 2567 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2568 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2569 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2bfcf297 2570 ""
4ae234b0 2571 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
943c15ed
DE		 2572 [(set_attr "type" "two")
2573 (set_attr "length" "8")])
1fd4e8c1
RK		 2574
2575(define_insn ""
9ebbca7d 2576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2577 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2578 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2579 (const_int 0)))
4ae234b0 2580 (clobber (match_scratch:P 3 "=r,r"))]
2bfcf297 2581 ""
9ebbca7d 2582 "@
4ae234b0 2583 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
9ebbca7d 2584 #"
b19003d8 2585 [(set_attr "type" "compare")
9ebbca7d
GK		 2586 (set_attr "length" "8,12")])
2587
2588(define_split
2589 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2590 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2591 (match_operand:GPR 2 "exact_log2_cint_operand"
2592 ""))
9ebbca7d 2593 (const_int 0)))
4ae234b0 2594 (clobber (match_scratch:GPR 3 ""))]
2bfcf297 2595 "reload_completed"
9ebbca7d 2596 [(set (match_dup 3)
4ae234b0 2597 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2598 (set (match_dup 0)
2599 (compare:CC (match_dup 3)
2600 (const_int 0)))]
2601 "")
1fd4e8c1
RK		 2602
2603(define_insn ""
9ebbca7d 2604 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2605 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2606 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2607 (const_int 0)))
4ae234b0
GK		 2608 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2609 (div:P (match_dup 1) (match_dup 2)))]
2bfcf297 2610 ""
9ebbca7d 2611 "@
4ae234b0 2612 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
9ebbca7d 2613 #"
b19003d8 2614 [(set_attr "type" "compare")
9ebbca7d
GK		 2615 (set_attr "length" "8,12")])
2616
2617(define_split
2618 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2619 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2620 (match_operand:GPR 2 "exact_log2_cint_operand"
2621 ""))
9ebbca7d 2622 (const_int 0)))
4ae234b0
GK		 2623 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2624 (div:GPR (match_dup 1) (match_dup 2)))]
2bfcf297 2625 "reload_completed"
9ebbca7d 2626 [(set (match_dup 0)
4ae234b0 2627 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2628 (set (match_dup 3)
2629 (compare:CC (match_dup 0)
2630 (const_int 0)))]
2631 "")
1fd4e8c1
RK		 2632
2633(define_insn ""
cd2b37d9 2634 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2635 (udiv:SI
996a5f59 2636 (plus:DI (ashift:DI
cd2b37d9 2637 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2638 (const_int 32))
23a900dc 2639 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2640 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2641 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2642 (umod:SI
996a5f59 2643 (plus:DI (ashift:DI
1fd4e8c1 2644 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2645 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2646 (match_dup 3)))]
ca7f5001 2647 "TARGET_POWER"
cfb557c4
RK		 2648 "div %0,%1,%3"
2649 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2650
2651;; To do unsigned divide we handle the cases of the divisor looking like a
2652;; negative number. If it is a constant that is less than 2**31, we don't
2653;; have to worry about the branches. So make a few subroutines here.
2654;;
2655;; First comes the normal case.
2656(define_expand "udivmodsi4_normal"
2657 [(set (match_dup 4) (const_int 0))
2658 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2659 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2660 (const_int 32))
2661 (zero_extend:DI (match_operand:SI 1 "" "")))
2662 (match_operand:SI 2 "" "")))
2663 (set (match_operand:SI 3 "" "")
996a5f59 2664 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2665 (const_int 32))
2666 (zero_extend:DI (match_dup 1)))
2667 (match_dup 2)))])]
ca7f5001 2668 "TARGET_POWER"
1fd4e8c1
RK		 2669 "
2670{ operands[4] = gen_reg_rtx (SImode); }")
2671
2672;; This handles the branches.
2673(define_expand "udivmodsi4_tests"
2674 [(set (match_operand:SI 0 "" "") (const_int 0))
2675 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2676 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2677 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2678 (label_ref (match_operand:SI 4 "" "")) (pc)))
2679 (set (match_dup 0) (const_int 1))
2680 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2681 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2682 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2683 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2684 "TARGET_POWER"
1fd4e8c1
RK		 2685 "
2686{ operands[5] = gen_reg_rtx (CCUNSmode);
2687 operands[6] = gen_reg_rtx (CCmode);
2688}")
2689
2690(define_expand "udivmodsi4"
cd2b37d9
RK		 2691 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2692 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2693 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2694 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2695 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2696 ""
1fd4e8c1
RK		 2697 "
2698{
2699 rtx label = 0;
2700
8ffd9c51 2701 if (! TARGET_POWER)
c4d38ccb
MM		 2702 {
2703 if (! TARGET_POWERPC)
2704 {
39403d82
DE		 2705 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2706 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2707 emit_insn (gen_divus_call ());
39403d82
DE		 2708 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2709 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2710 DONE;
2711 }
2712 else
2713 FAIL;
2714 }
0081a354 2715
1fd4e8c1
RK		 2716 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2717 {
2718 operands[2] = force_reg (SImode, operands[2]);
2719 label = gen_label_rtx ();
2720 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2721 operands[3], label));
2722 }
2723 else
2724 operands[2] = force_reg (SImode, operands[2]);
2725
2726 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2727 operands[3]));
2728 if (label)
2729 emit_label (label);
2730
2731 DONE;
2732}")
0081a354 2733
fada905b
MM		 2734;; AIX architecture-independent common-mode multiply (DImode),
2735;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2736;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2737;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2738;; assumed unused if generating common-mode, so ignore.
2739(define_insn "mulh_call"
2740 [(set (reg:SI 3)
2741 (truncate:SI
2742 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2743 (sign_extend:DI (reg:SI 4)))
2744 (const_int 32))))
1de43f85 2745 (clobber (reg:SI LR_REGNO))]
fada905b 2746 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2747 "bla __mulh"
2748 [(set_attr "type" "imul")])
fada905b
MM		 2749
2750(define_insn "mull_call"
2751 [(set (reg:DI 3)
2752 (mult:DI (sign_extend:DI (reg:SI 3))
2753 (sign_extend:DI (reg:SI 4))))
1de43f85 2754 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2755 (clobber (reg:SI 0))]
2756 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2757 "bla __mull"
2758 [(set_attr "type" "imul")])
fada905b
MM		 2759
2760(define_insn "divss_call"
2761 [(set (reg:SI 3)
2762 (div:SI (reg:SI 3) (reg:SI 4)))
2763 (set (reg:SI 4)
2764 (mod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2765 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2766 (clobber (reg:SI 0))]
2767 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2768 "bla __divss"
2769 [(set_attr "type" "idiv")])
fada905b
MM		 2770
2771(define_insn "divus_call"
8ffd9c51
RK		 2772 [(set (reg:SI 3)
2773 (udiv:SI (reg:SI 3) (reg:SI 4)))
2774 (set (reg:SI 4)
2775 (umod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2776 (clobber (reg:SI LR_REGNO))
fada905b 2777 (clobber (reg:SI 0))
e65a3857 2778 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2779 (clobber (reg:CC CR1_REGNO))]
fada905b 2780 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2781 "bla __divus"
2782 [(set_attr "type" "idiv")])
fada905b
MM		 2783
2784(define_insn "quoss_call"
2785 [(set (reg:SI 3)
2786 (div:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2787 (clobber (reg:SI LR_REGNO))]
8ffd9c51 2788 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2789 "bla __quoss"
2790 [(set_attr "type" "idiv")])
0081a354 2791
fada905b
MM		 2792(define_insn "quous_call"
2793 [(set (reg:SI 3)
2794 (udiv:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2795 (clobber (reg:SI LR_REGNO))
fada905b 2796 (clobber (reg:SI 0))
e65a3857 2797 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2798 (clobber (reg:CC CR1_REGNO))]
fada905b 2799 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2800 "bla __quous"
2801 [(set_attr "type" "idiv")])
8ffd9c51 2802\f
bb21487f 2803;; Logical instructions
dfbdccdb
GK		 2804;; The logical instructions are mostly combined by using match_operator,
2805;; but the plain AND insns are somewhat different because there is no
2806;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2807;; those rotate-and-mask operations. Thus, the AND insns come first.
2808
29ae5b89
JL		 2809(define_insn "andsi3"
2810 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2811 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2812 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2813 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1fd4e8c1
RK		 2814 ""
2815 "@
2816 and %0,%1,%2
ca7f5001
RK		 2817 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2818 {andil.|andi.} %0,%1,%b2
520308bc
DE		 2819 {andiu.|andis.} %0,%1,%u2"
2820 [(set_attr "type" "*,*,compare,compare")])
52d3af72
DE		 2821
2822;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2823;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2824;; machines causes an execution serialization
1fd4e8c1 2825
7cd5235b 2826(define_insn "*andsi3_internal2"
52d3af72
DE		 2827 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2828 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2829 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2830 (const_int 0)))
52d3af72
DE		 2831 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2832 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2833 "TARGET_32BIT"
1fd4e8c1
RK		 2834 "@
2835 and. %3,%1,%2
ca7f5001
RK		 2836 {andil.|andi.} %3,%1,%b2
2837 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2838 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2839 #
2840 #
2841 #
2842 #"
2843 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2844 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2845
0ba1b2ff
AM		 2846(define_insn "*andsi3_internal3"
2847 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2848 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2849 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2850 (const_int 0)))
2851 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2852 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2853 "TARGET_64BIT"
0ba1b2ff
AM		 2854 "@
2855 #
2856 {andil.|andi.} %3,%1,%b2
2857 {andiu.|andis.} %3,%1,%u2
2858 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2859 #
2860 #
2861 #
2862 #"
2863 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2864 (set_attr "length" "8,4,4,4,8,8,8,8")])
2865
52d3af72
DE		 2866(define_split
2867 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2868 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2869 (match_operand:GPR 2 "and_operand" ""))
1fd4e8c1 2870 (const_int 0)))
4ae234b0 2871 (clobber (match_scratch:GPR 3 ""))
52d3af72 2872 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2873 "reload_completed"
52d3af72 2874 [(parallel [(set (match_dup 3)
4ae234b0
GK		 2875 (and:<MODE> (match_dup 1)
2876 (match_dup 2)))
52d3af72
DE		 2877 (clobber (match_dup 4))])
2878 (set (match_dup 0)
2879 (compare:CC (match_dup 3)
2880 (const_int 0)))]
2881 "")
2882
0ba1b2ff
AM		 2883;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2884;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2885
2886(define_split
2887 [(set (match_operand:CC 0 "cc_reg_operand" "")
2888 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2889 (match_operand:SI 2 "gpc_reg_operand" ""))
2890 (const_int 0)))
2891 (clobber (match_scratch:SI 3 ""))
2892 (clobber (match_scratch:CC 4 ""))]
2893 "TARGET_POWERPC64 && reload_completed"
2894 [(parallel [(set (match_dup 3)
2895 (and:SI (match_dup 1)
2896 (match_dup 2)))
2897 (clobber (match_dup 4))])
2898 (set (match_dup 0)
2899 (compare:CC (match_dup 3)
2900 (const_int 0)))]
2901 "")
2902
2903(define_insn "*andsi3_internal4"
52d3af72
DE		 2904 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2905 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2906 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2907 (const_int 0)))
2908 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2909 (and:SI (match_dup 1)
2910 (match_dup 2)))
2911 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2912 "TARGET_32BIT"
1fd4e8c1
RK		 2913 "@
2914 and. %0,%1,%2
ca7f5001
RK		 2915 {andil.|andi.} %0,%1,%b2
2916 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2917 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2918 #
2919 #
2920 #
2921 #"
2922 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2923 (set_attr "length" "4,4,4,4,8,8,8,8")])
2924
0ba1b2ff
AM		 2925(define_insn "*andsi3_internal5"
2926 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2927 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2928 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2929 (const_int 0)))
2930 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2931 (and:SI (match_dup 1)
2932 (match_dup 2)))
2933 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2934 "TARGET_64BIT"
0ba1b2ff
AM		 2935 "@
2936 #
2937 {andil.|andi.} %0,%1,%b2
2938 {andiu.|andis.} %0,%1,%u2
2939 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2940 #
2941 #
2942 #
2943 #"
2944 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2945 (set_attr "length" "8,4,4,4,8,8,8,8")])
2946
52d3af72
DE		 2947(define_split
2948 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2949 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2950 (match_operand:SI 2 "and_operand" ""))
2951 (const_int 0)))
2952 (set (match_operand:SI 0 "gpc_reg_operand" "")
2953 (and:SI (match_dup 1)
2954 (match_dup 2)))
2955 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2956 "reload_completed"
52d3af72
DE		 2957 [(parallel [(set (match_dup 0)
2958 (and:SI (match_dup 1)
2959 (match_dup 2)))
2960 (clobber (match_dup 4))])
2961 (set (match_dup 3)
2962 (compare:CC (match_dup 0)
2963 (const_int 0)))]
2964 "")
1fd4e8c1 2965
0ba1b2ff
AM		 2966(define_split
2967 [(set (match_operand:CC 3 "cc_reg_operand" "")
2968 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2969 (match_operand:SI 2 "gpc_reg_operand" ""))
2970 (const_int 0)))
2971 (set (match_operand:SI 0 "gpc_reg_operand" "")
2972 (and:SI (match_dup 1)
2973 (match_dup 2)))
2974 (clobber (match_scratch:CC 4 ""))]
2975 "TARGET_POWERPC64 && reload_completed"
2976 [(parallel [(set (match_dup 0)
2977 (and:SI (match_dup 1)
2978 (match_dup 2)))
2979 (clobber (match_dup 4))])
2980 (set (match_dup 3)
2981 (compare:CC (match_dup 0)
2982 (const_int 0)))]
2983 "")
2984
2985;; Handle the PowerPC64 rlwinm corner case
2986
2987(define_insn_and_split "*andsi3_internal6"
2988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2989 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2990 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2991 "TARGET_POWERPC64"
2992 "#"
2993 "TARGET_POWERPC64"
2994 [(set (match_dup 0)
2995 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2996 (match_dup 4)))
2997 (set (match_dup 0)
2998 (rotate:SI (match_dup 0) (match_dup 5)))]
2999 "
3000{
3001 int mb = extract_MB (operands[2]);
3002 int me = extract_ME (operands[2]);
3003 operands[3] = GEN_INT (me + 1);
3004 operands[5] = GEN_INT (32 - (me + 1));
3005 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3006}"
3007 [(set_attr "length" "8")])
3008
7cd5235b 3009(define_expand "iorsi3"
cd2b37d9 3010 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3011 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3012 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 3013 ""
f357808b
RK		 3014 "
3015{
7cd5235b 3016 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3017 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3018 {
3019 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3020 rtx tmp = ((!can_create_pseudo_p ()
3021 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3022 ? operands[0] : gen_reg_rtx (SImode));
3023
a260abc9
DE		 3024 emit_insn (gen_iorsi3 (tmp, operands[1],
3025 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3026 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3027 DONE;
3028 }
f357808b
RK		 3029}")
3030
7cd5235b 3031(define_expand "xorsi3"
cd2b37d9 3032 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3033 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3034 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 3035 ""
7cd5235b 3036 "
1fd4e8c1 3037{
7cd5235b 3038 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3039 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3040 {
3041 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3042 rtx tmp = ((!can_create_pseudo_p ()
3043 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3044 ? operands[0] : gen_reg_rtx (SImode));
3045
a260abc9
DE		 3046 emit_insn (gen_xorsi3 (tmp, operands[1],
3047 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3048 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3049 DONE;
3050 }
1fd4e8c1
RK		 3051}")
3052
dfbdccdb 3053(define_insn "*boolsi3_internal1"
7cd5235b 3054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 3055 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3056 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3057 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 3058 ""
3059 "@
dfbdccdb
GK		 3060 %q3 %0,%1,%2
3061 {%q3il|%q3i} %0,%1,%b2
3062 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 3063
dfbdccdb 3064(define_insn "*boolsi3_internal2"
52d3af72 3065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 3066 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 3067 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3068 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3069 (const_int 0)))
52d3af72 3070 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3071 "TARGET_32BIT"
52d3af72 3072 "@
dfbdccdb 3073 %q4. %3,%1,%2
52d3af72
DE		 3074 #"
3075 [(set_attr "type" "compare")
3076 (set_attr "length" "4,8")])
3077
3078(define_split
3079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3080 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3081 [(match_operand:SI 1 "gpc_reg_operand" "")
3082 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3083 (const_int 0)))
52d3af72 3084 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3085 "TARGET_32BIT && reload_completed"
dfbdccdb 3086 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3087 (set (match_dup 0)
3088 (compare:CC (match_dup 3)
3089 (const_int 0)))]
3090 "")
815cdc52 3091
dfbdccdb 3092(define_insn "*boolsi3_internal3"
52d3af72 3093 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3094 (compare:CC (match_operator:SI 4 "boolean_operator"
3095 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3096 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3097 (const_int 0)))
52d3af72 3098 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3099 (match_dup 4))]
4b8a63d6 3100 "TARGET_32BIT"
52d3af72 3101 "@
dfbdccdb 3102 %q4. %0,%1,%2
52d3af72
DE		 3103 #"
3104 [(set_attr "type" "compare")
3105 (set_attr "length" "4,8")])
3106
3107(define_split
e72247f4 3108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3109 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3110 [(match_operand:SI 1 "gpc_reg_operand" "")
3111 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3112 (const_int 0)))
75540af0 3113 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3114 (match_dup 4))]
4b8a63d6 3115 "TARGET_32BIT && reload_completed"
dfbdccdb 3116 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3117 (set (match_dup 3)
3118 (compare:CC (match_dup 0)
3119 (const_int 0)))]
3120 "")
1fd4e8c1 3121
6ae08853 3122;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 3123;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 3124
3125(define_split
3126 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 3127 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3128 [(match_operand:SI 1 "gpc_reg_operand" "")
3129 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 3130 ""
dfbdccdb
GK		 3131 [(set (match_dup 0) (match_dup 4))
3132 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 3133"
3134{
dfbdccdb
GK		 3135 rtx i;
3136 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1c563bed 3137 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3138 operands[1], i);
dfbdccdb 3139 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
1c563bed 3140 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3141 operands[0], i);
a260abc9
DE		 3142}")
3143
dfbdccdb 3144(define_insn "*boolcsi3_internal1"
cd2b37d9 3145 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3146 (match_operator:SI 3 "boolean_operator"
3147 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3148 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 3149 ""
dfbdccdb 3150 "%q3 %0,%2,%1")
1fd4e8c1 3151
dfbdccdb 3152(define_insn "*boolcsi3_internal2"
52d3af72 3153 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3154 (compare:CC (match_operator:SI 4 "boolean_operator"
3155 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3156 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3157 (const_int 0)))
52d3af72 3158 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3159 "TARGET_32BIT"
52d3af72 3160 "@
dfbdccdb 3161 %q4. %3,%2,%1
52d3af72
DE		 3162 #"
3163 [(set_attr "type" "compare")
3164 (set_attr "length" "4,8")])
3165
3166(define_split
3167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3168 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3169 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3170 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3171 (const_int 0)))
52d3af72 3172 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3173 "TARGET_32BIT && reload_completed"
dfbdccdb 3174 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3175 (set (match_dup 0)
3176 (compare:CC (match_dup 3)
3177 (const_int 0)))]
3178 "")
1fd4e8c1 3179
dfbdccdb 3180(define_insn "*boolcsi3_internal3"
52d3af72 3181 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3182 (compare:CC (match_operator:SI 4 "boolean_operator"
3183 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3184 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3185 (const_int 0)))
52d3af72 3186 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3187 (match_dup 4))]
4b8a63d6 3188 "TARGET_32BIT"
52d3af72 3189 "@
dfbdccdb 3190 %q4. %0,%2,%1
52d3af72
DE		 3191 #"
3192 [(set_attr "type" "compare")
3193 (set_attr "length" "4,8")])
3194
3195(define_split
e72247f4 3196 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3197 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3198 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3199 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3200 (const_int 0)))
75540af0 3201 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3202 (match_dup 4))]
4b8a63d6 3203 "TARGET_32BIT && reload_completed"
dfbdccdb 3204 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3205 (set (match_dup 3)
3206 (compare:CC (match_dup 0)
3207 (const_int 0)))]
3208 "")
3209
dfbdccdb 3210(define_insn "*boolccsi3_internal1"
cd2b37d9 3211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3212 (match_operator:SI 3 "boolean_operator"
3213 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3214 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 3215 ""
dfbdccdb 3216 "%q3 %0,%1,%2")
1fd4e8c1 3217
dfbdccdb 3218(define_insn "*boolccsi3_internal2"
52d3af72 3219 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3220 (compare:CC (match_operator:SI 4 "boolean_operator"
3221 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3222 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3223 (const_int 0)))
52d3af72 3224 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3225 "TARGET_32BIT"
52d3af72 3226 "@
dfbdccdb 3227 %q4. %3,%1,%2
52d3af72
DE		 3228 #"
3229 [(set_attr "type" "compare")
3230 (set_attr "length" "4,8")])
3231
3232(define_split
3233 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3234 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3235 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3236 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3237 (const_int 0)))
52d3af72 3238 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3239 "TARGET_32BIT && reload_completed"
dfbdccdb 3240 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3241 (set (match_dup 0)
3242 (compare:CC (match_dup 3)
3243 (const_int 0)))]
3244 "")
1fd4e8c1 3245
dfbdccdb 3246(define_insn "*boolccsi3_internal3"
52d3af72 3247 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3248 (compare:CC (match_operator:SI 4 "boolean_operator"
3249 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3250 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3251 (const_int 0)))
52d3af72 3252 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3253 (match_dup 4))]
4b8a63d6 3254 "TARGET_32BIT"
52d3af72 3255 "@
dfbdccdb 3256 %q4. %0,%1,%2
52d3af72
DE		 3257 #"
3258 [(set_attr "type" "compare")
3259 (set_attr "length" "4,8")])
3260
3261(define_split
e72247f4 3262 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3263 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3264 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3265 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3266 (const_int 0)))
75540af0 3267 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3268 (match_dup 4))]
4b8a63d6 3269 "TARGET_32BIT && reload_completed"
dfbdccdb 3270 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3271 (set (match_dup 3)
3272 (compare:CC (match_dup 0)
3273 (const_int 0)))]
3274 "")
1fd4e8c1
RK		 3275
3276;; maskir insn. We need four forms because things might be in arbitrary
3277;; orders. Don't define forms that only set CR fields because these
3278;; would modify an input register.
3279
7cd5235b 3280(define_insn "*maskir_internal1"
cd2b37d9 3281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3282 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3283 (match_operand:SI 1 "gpc_reg_operand" "0"))
3284 (and:SI (match_dup 2)
cd2b37d9 3285 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 3286 "TARGET_POWER"
01def764 3287 "maskir %0,%3,%2")
1fd4e8c1 3288
7cd5235b 3289(define_insn "*maskir_internal2"
242e8072 3290 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3291 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3292 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 3293 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 3294 (match_dup 2))))]
ca7f5001 3295 "TARGET_POWER"
01def764 3296 "maskir %0,%3,%2")
1fd4e8c1 3297
7cd5235b 3298(define_insn "*maskir_internal3"
cd2b37d9 3299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 3300 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 3301 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 3302 (and:SI (not:SI (match_dup 2))
3303 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3304 "TARGET_POWER"
01def764 3305 "maskir %0,%3,%2")
1fd4e8c1 3306
7cd5235b 3307(define_insn "*maskir_internal4"
cd2b37d9
RK		 3308 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3309 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 3310 (match_operand:SI 2 "gpc_reg_operand" "r"))
3311 (and:SI (not:SI (match_dup 2))
3312 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3313 "TARGET_POWER"
01def764 3314 "maskir %0,%3,%2")
1fd4e8c1 3315
7cd5235b 3316(define_insn "*maskir_internal5"
9ebbca7d 3317 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3318 (compare:CC
9ebbca7d
GK		 3319 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3320 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 3321 (and:SI (match_dup 2)
9ebbca7d 3322 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 3323 (const_int 0)))
9ebbca7d 3324 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3325 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3326 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 3327 "TARGET_POWER"
9ebbca7d
GK		 3328 "@
3329 maskir. %0,%3,%2
3330 #"
3331 [(set_attr "type" "compare")
3332 (set_attr "length" "4,8")])
3333
3334(define_split
3335 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3336 (compare:CC
3337 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3338 (match_operand:SI 1 "gpc_reg_operand" ""))
3339 (and:SI (match_dup 2)
3340 (match_operand:SI 3 "gpc_reg_operand" "")))
3341 (const_int 0)))
3342 (set (match_operand:SI 0 "gpc_reg_operand" "")
3343 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3344 (and:SI (match_dup 2) (match_dup 3))))]
3345 "TARGET_POWER && reload_completed"
3346 [(set (match_dup 0)
3347 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3348 (and:SI (match_dup 2) (match_dup 3))))
3349 (set (match_dup 4)
3350 (compare:CC (match_dup 0)
3351 (const_int 0)))]
3352 "")
1fd4e8c1 3353
7cd5235b 3354(define_insn "*maskir_internal6"
9ebbca7d 3355 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3356 (compare:CC
9ebbca7d
GK		 3357 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3358 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3359 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 3360 (match_dup 2)))
1fd4e8c1 3361 (const_int 0)))
9ebbca7d 3362 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3363 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3364 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 3365 "TARGET_POWER"
9ebbca7d
GK		 3366 "@
3367 maskir. %0,%3,%2
3368 #"
3369 [(set_attr "type" "compare")
3370 (set_attr "length" "4,8")])
3371
3372(define_split
3373 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3374 (compare:CC
3375 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3376 (match_operand:SI 1 "gpc_reg_operand" ""))
3377 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3378 (match_dup 2)))
3379 (const_int 0)))
3380 (set (match_operand:SI 0 "gpc_reg_operand" "")
3381 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3382 (and:SI (match_dup 3) (match_dup 2))))]
3383 "TARGET_POWER && reload_completed"
3384 [(set (match_dup 0)
3385 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3386 (and:SI (match_dup 3) (match_dup 2))))
3387 (set (match_dup 4)
3388 (compare:CC (match_dup 0)
3389 (const_int 0)))]
3390 "")
1fd4e8c1 3391
7cd5235b 3392(define_insn "*maskir_internal7"
9ebbca7d 3393 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 3394 (compare:CC
9ebbca7d
GK		 3395 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3396 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 3397 (and:SI (not:SI (match_dup 2))
9ebbca7d 3398 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 3399 (const_int 0)))
9ebbca7d 3400 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 3401 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3402 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3403 "TARGET_POWER"
9ebbca7d
GK		 3404 "@
3405 maskir. %0,%3,%2
3406 #"
3407 [(set_attr "type" "compare")
3408 (set_attr "length" "4,8")])
3409
3410(define_split
3411 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3412 (compare:CC
3413 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3414 (match_operand:SI 3 "gpc_reg_operand" ""))
3415 (and:SI (not:SI (match_dup 2))
3416 (match_operand:SI 1 "gpc_reg_operand" "")))
3417 (const_int 0)))
3418 (set (match_operand:SI 0 "gpc_reg_operand" "")
3419 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3420 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3421 "TARGET_POWER && reload_completed"
3422 [(set (match_dup 0)
3423 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3424 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3425 (set (match_dup 4)
3426 (compare:CC (match_dup 0)
3427 (const_int 0)))]
3428 "")
1fd4e8c1 3429
7cd5235b 3430(define_insn "*maskir_internal8"
9ebbca7d 3431 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3432 (compare:CC
9ebbca7d
GK		 3433 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3434 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 3435 (and:SI (not:SI (match_dup 2))
9ebbca7d 3436 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 3437 (const_int 0)))
9ebbca7d 3438 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3439 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3440 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 3441 "TARGET_POWER"
9ebbca7d
GK		 3442 "@
3443 maskir. %0,%3,%2
3444 #"
3445 [(set_attr "type" "compare")
3446 (set_attr "length" "4,8")])
fcce224d 3447
9ebbca7d
GK		 3448(define_split
3449 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3450 (compare:CC
3451 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3452 (match_operand:SI 2 "gpc_reg_operand" ""))
3453 (and:SI (not:SI (match_dup 2))
3454 (match_operand:SI 1 "gpc_reg_operand" "")))
3455 (const_int 0)))
3456 (set (match_operand:SI 0 "gpc_reg_operand" "")
3457 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3458 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3459 "TARGET_POWER && reload_completed"
3460 [(set (match_dup 0)
3461 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3462 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3463 (set (match_dup 4)
3464 (compare:CC (match_dup 0)
3465 (const_int 0)))]
3466 "")
fcce224d 3467\f
1fd4e8c1
RK		 3468;; Rotate and shift insns, in all their variants. These support shifts,
3469;; field inserts and extracts, and various combinations thereof.
034c1be0 3470(define_expand "insv"
0ad91047
DE		 3471 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3472 (match_operand:SI 1 "const_int_operand" "")
3473 (match_operand:SI 2 "const_int_operand" ""))
3474 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 3475 ""
3476 "
3477{
3478 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3479 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
14502dad
JM		 3480 compiler if the address of the structure is taken later. Likewise, do
3481 not handle invalid E500 subregs. */
034c1be0 3482 if (GET_CODE (operands[0]) == SUBREG
14502dad
JM		 3483 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3484 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3485 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
034c1be0 3486 FAIL;
a78e33fc
DE		 3487
3488 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3489 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3490 else
3491 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3492 DONE;
034c1be0
MM		 3493}")
3494
a78e33fc 3495(define_insn "insvsi"
cd2b37d9 3496 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 3497 (match_operand:SI 1 "const_int_operand" "i")
3498 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 3499 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 3500 ""
3501 "*
3502{
3503 int start = INTVAL (operands[2]) & 31;
3504 int size = INTVAL (operands[1]) & 31;
3505
89e9f3a8
MM		 3506 operands[4] = GEN_INT (32 - start - size);
3507 operands[1] = GEN_INT (start + size - 1);
a66078ee 3508 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3509}"
3510 [(set_attr "type" "insert_word")])
1fd4e8c1 3511
a78e33fc 3512(define_insn "*insvsi_internal1"
d56d506a
RK		 3513 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3514 (match_operand:SI 1 "const_int_operand" "i")
3515 (match_operand:SI 2 "const_int_operand" "i"))
6d0a8091 3516 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
d56d506a 3517 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3518 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3519 "*
3520{
3521 int shift = INTVAL (operands[4]) & 31;
3522 int start = INTVAL (operands[2]) & 31;
3523 int size = INTVAL (operands[1]) & 31;
3524
89e9f3a8 3525 operands[4] = GEN_INT (shift - start - size);
6d0a8091 3526 operands[1] = GEN_INT (start + size - 1);
a66078ee 3527 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3528}"
3529 [(set_attr "type" "insert_word")])
d56d506a 3530
a78e33fc 3531(define_insn "*insvsi_internal2"
d56d506a
RK		 3532 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3533 (match_operand:SI 1 "const_int_operand" "i")
3534 (match_operand:SI 2 "const_int_operand" "i"))
3535 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3536 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3537 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3538 "*
3539{
3540 int shift = INTVAL (operands[4]) & 31;
3541 int start = INTVAL (operands[2]) & 31;
3542 int size = INTVAL (operands[1]) & 31;
3543
89e9f3a8
MM		 3544 operands[4] = GEN_INT (32 - shift - start - size);
3545 operands[1] = GEN_INT (start + size - 1);
a66078ee 3546 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3547}"
3548 [(set_attr "type" "insert_word")])
d56d506a 3549
a78e33fc 3550(define_insn "*insvsi_internal3"
d56d506a
RK		 3551 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3552 (match_operand:SI 1 "const_int_operand" "i")
3553 (match_operand:SI 2 "const_int_operand" "i"))
3554 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3555 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 3556 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3557 "*
3558{
3559 int shift = INTVAL (operands[4]) & 31;
3560 int start = INTVAL (operands[2]) & 31;
3561 int size = INTVAL (operands[1]) & 31;
3562
89e9f3a8
MM		 3563 operands[4] = GEN_INT (32 - shift - start - size);
3564 operands[1] = GEN_INT (start + size - 1);
a66078ee 3565 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3566}"
3567 [(set_attr "type" "insert_word")])
d56d506a 3568
a78e33fc 3569(define_insn "*insvsi_internal4"
d56d506a
RK		 3570 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3571 (match_operand:SI 1 "const_int_operand" "i")
3572 (match_operand:SI 2 "const_int_operand" "i"))
3573 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3574 (match_operand:SI 4 "const_int_operand" "i")
3575 (match_operand:SI 5 "const_int_operand" "i")))]
3576 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3577 "*
3578{
3579 int extract_start = INTVAL (operands[5]) & 31;
3580 int extract_size = INTVAL (operands[4]) & 31;
3581 int insert_start = INTVAL (operands[2]) & 31;
3582 int insert_size = INTVAL (operands[1]) & 31;
3583
3584/* Align extract field with insert field */
3a598fbe 3585 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3586 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3587 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 3588}"
3589 [(set_attr "type" "insert_word")])
d56d506a 3590
f241bf89
EC		 3591;; combine patterns for rlwimi
3592(define_insn "*insvsi_internal5"
3593 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3594 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3595 (match_operand:SI 1 "mask_operand" "i"))
3596 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3597 (match_operand:SI 2 "const_int_operand" "i"))
3598 (match_operand:SI 5 "mask_operand" "i"))))]
3599 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3600 "*
3601{
3602 int me = extract_ME(operands[5]);
3603 int mb = extract_MB(operands[5]);
3604 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3605 operands[2] = GEN_INT(mb);
3606 operands[1] = GEN_INT(me);
3607 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3608}"
3609 [(set_attr "type" "insert_word")])
3610
3611(define_insn "*insvsi_internal6"
3612 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3613 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3614 (match_operand:SI 2 "const_int_operand" "i"))
3615 (match_operand:SI 5 "mask_operand" "i"))
3616 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3617 (match_operand:SI 1 "mask_operand" "i"))))]
3618 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3619 "*
3620{
3621 int me = extract_ME(operands[5]);
3622 int mb = extract_MB(operands[5]);
3623 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3624 operands[2] = GEN_INT(mb);
3625 operands[1] = GEN_INT(me);
3626 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3627}"
3628 [(set_attr "type" "insert_word")])
3629
a78e33fc 3630(define_insn "insvdi"
685f3906 3631 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3632 (match_operand:SI 1 "const_int_operand" "i")
3633 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3634 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3635 "TARGET_POWERPC64"
3636 "*
3637{
3638 int start = INTVAL (operands[2]) & 63;
3639 int size = INTVAL (operands[1]) & 63;
3640
a78e33fc
DE		 3641 operands[1] = GEN_INT (64 - start - size);
3642 return \"rldimi %0,%3,%H1,%H2\";
44cd321e
PS		 3643}"
3644 [(set_attr "type" "insert_dword")])
685f3906 3645
11ac38b2
DE		 3646(define_insn "*insvdi_internal2"
3647 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3648 (match_operand:SI 1 "const_int_operand" "i")
3649 (match_operand:SI 2 "const_int_operand" "i"))
3650 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3651 (match_operand:SI 4 "const_int_operand" "i")))]
3652 "TARGET_POWERPC64
3653 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3654 "*
3655{
3656 int shift = INTVAL (operands[4]) & 63;
3657 int start = (INTVAL (operands[2]) & 63) - 32;
3658 int size = INTVAL (operands[1]) & 63;
3659
3660 operands[4] = GEN_INT (64 - shift - start - size);
3661 operands[2] = GEN_INT (start);
3662 operands[1] = GEN_INT (start + size - 1);
3663 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3664}")
3665
3666(define_insn "*insvdi_internal3"
3667 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3668 (match_operand:SI 1 "const_int_operand" "i")
3669 (match_operand:SI 2 "const_int_operand" "i"))
3670 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3671 (match_operand:SI 4 "const_int_operand" "i")))]
3672 "TARGET_POWERPC64
3673 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3674 "*
3675{
3676 int shift = INTVAL (operands[4]) & 63;
3677 int start = (INTVAL (operands[2]) & 63) - 32;
3678 int size = INTVAL (operands[1]) & 63;
3679
3680 operands[4] = GEN_INT (64 - shift - start - size);
3681 operands[2] = GEN_INT (start);
3682 operands[1] = GEN_INT (start + size - 1);
3683 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3684}")
3685
034c1be0 3686(define_expand "extzv"
0ad91047
DE		 3687 [(set (match_operand 0 "gpc_reg_operand" "")
3688 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3689 (match_operand:SI 2 "const_int_operand" "")
3690 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3691 ""
3692 "
3693{
3694 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3695 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3696 compiler if the address of the structure is taken later. */
3697 if (GET_CODE (operands[0]) == SUBREG
3698 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3699 FAIL;
a78e33fc
DE		 3700
3701 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3702 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3703 else
3704 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3705 DONE;
034c1be0
MM		 3706}")
3707
a78e33fc 3708(define_insn "extzvsi"
cd2b37d9
RK		 3709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3710 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3711 (match_operand:SI 2 "const_int_operand" "i")
3712 (match_operand:SI 3 "const_int_operand" "i")))]
3713 ""
3714 "*
3715{
3716 int start = INTVAL (operands[3]) & 31;
3717 int size = INTVAL (operands[2]) & 31;
3718
3719 if (start + size >= 32)
3720 operands[3] = const0_rtx;
3721 else
89e9f3a8 3722 operands[3] = GEN_INT (start + size);
ca7f5001 3723 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3724}")
3725
a78e33fc 3726(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3728 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3729 (match_operand:SI 2 "const_int_operand" "i,i")
3730 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3731 (const_int 0)))
9ebbca7d 3732 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3733 ""
1fd4e8c1
RK		 3734 "*
3735{
3736 int start = INTVAL (operands[3]) & 31;
3737 int size = INTVAL (operands[2]) & 31;
3738
9ebbca7d
GK		 3739 /* Force split for non-cc0 compare. */
3740 if (which_alternative == 1)
3741 return \"#\";
3742
43a88a8c 3743 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3744 word, it is possible to use andiu. or andil. to test it. This is
3745 useful because the condition register set-use delay is smaller for
3746 andi[ul]. than for rlinm. This doesn't work when the starting bit
3747 position is 0 because the LT and GT bits may be set wrong. */
3748
3749 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3750 {
3a598fbe 3751 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3752 - (1 << (16 - (start & 15) - size))));
3753 if (start < 16)
ca7f5001 3754 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3755 else
ca7f5001 3756 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3757 }
7e69e155 3758
1fd4e8c1
RK		 3759 if (start + size >= 32)
3760 operands[3] = const0_rtx;
3761 else
89e9f3a8 3762 operands[3] = GEN_INT (start + size);
ca7f5001 3763 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3764}"
44cd321e 3765 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3766 (set_attr "length" "4,8")])
3767
3768(define_split
3769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3770 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3771 (match_operand:SI 2 "const_int_operand" "")
3772 (match_operand:SI 3 "const_int_operand" ""))
3773 (const_int 0)))
3774 (clobber (match_scratch:SI 4 ""))]
ce71f754 3775 "reload_completed"
9ebbca7d
GK		 3776 [(set (match_dup 4)
3777 (zero_extract:SI (match_dup 1) (match_dup 2)
3778 (match_dup 3)))
3779 (set (match_dup 0)
3780 (compare:CC (match_dup 4)
3781 (const_int 0)))]
3782 "")
1fd4e8c1 3783
a78e33fc 3784(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3785 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3786 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3787 (match_operand:SI 2 "const_int_operand" "i,i")
3788 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3789 (const_int 0)))
9ebbca7d 3790 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3791 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3792 ""
1fd4e8c1
RK		 3793 "*
3794{
3795 int start = INTVAL (operands[3]) & 31;
3796 int size = INTVAL (operands[2]) & 31;
3797
9ebbca7d
GK		 3798 /* Force split for non-cc0 compare. */
3799 if (which_alternative == 1)
3800 return \"#\";
3801
bc401279 3802 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3803 a shift. The bit-field must end at the LSB. */
bc401279 3804 if (start >= 16 && start + size == 32)
df031c43 3805 {
bc401279
AM		 3806 operands[3] = GEN_INT ((1 << size) - 1);
3807 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3808 }
7e69e155 3809
1fd4e8c1
RK		 3810 if (start + size >= 32)
3811 operands[3] = const0_rtx;
3812 else
89e9f3a8 3813 operands[3] = GEN_INT (start + size);
ca7f5001 3814 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3815}"
44cd321e 3816 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3817 (set_attr "length" "4,8")])
3818
3819(define_split
3820 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3821 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3822 (match_operand:SI 2 "const_int_operand" "")
3823 (match_operand:SI 3 "const_int_operand" ""))
3824 (const_int 0)))
3825 (set (match_operand:SI 0 "gpc_reg_operand" "")
3826 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3827 "reload_completed"
9ebbca7d
GK		 3828 [(set (match_dup 0)
3829 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3830 (set (match_dup 4)
3831 (compare:CC (match_dup 0)
3832 (const_int 0)))]
3833 "")
1fd4e8c1 3834
a78e33fc 3835(define_insn "extzvdi"
685f3906
DE		 3836 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3837 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3838 (match_operand:SI 2 "const_int_operand" "i")
3839 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3840 "TARGET_POWERPC64"
3841 "*
3842{
3843 int start = INTVAL (operands[3]) & 63;
3844 int size = INTVAL (operands[2]) & 63;
3845
3846 if (start + size >= 64)
3847 operands[3] = const0_rtx;
3848 else
89e9f3a8
MM		 3849 operands[3] = GEN_INT (start + size);
3850 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3851 return \"rldicl %0,%1,%3,%2\";
3852}")
3853
a78e33fc 3854(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3855 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3856 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3857 (match_operand:SI 2 "const_int_operand" "i")
3858 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3859 (const_int 0)))
29ae5b89 3860 (clobber (match_scratch:DI 4 "=r"))]
683bdff7 3861 "TARGET_64BIT"
685f3906
DE		 3862 "*
3863{
3864 int start = INTVAL (operands[3]) & 63;
3865 int size = INTVAL (operands[2]) & 63;
3866
3867 if (start + size >= 64)
3868 operands[3] = const0_rtx;
3869 else
89e9f3a8
MM		 3870 operands[3] = GEN_INT (start + size);
3871 operands[2] = GEN_INT (64 - size);
685f3906 3872 return \"rldicl. %4,%1,%3,%2\";
9a3c428b
DE		 3873}"
3874 [(set_attr "type" "compare")])
685f3906 3875
a78e33fc 3876(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3877 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3878 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3879 (match_operand:SI 2 "const_int_operand" "i")
3880 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3881 (const_int 0)))
29ae5b89 3882 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3883 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
683bdff7 3884 "TARGET_64BIT"
685f3906
DE		 3885 "*
3886{
3887 int start = INTVAL (operands[3]) & 63;
3888 int size = INTVAL (operands[2]) & 63;
3889
3890 if (start + size >= 64)
3891 operands[3] = const0_rtx;
3892 else
89e9f3a8
MM		 3893 operands[3] = GEN_INT (start + size);
3894 operands[2] = GEN_INT (64 - size);
685f3906 3895 return \"rldicl. %0,%1,%3,%2\";
9a3c428b
DE		 3896}"
3897 [(set_attr "type" "compare")])
685f3906 3898
1fd4e8c1 3899(define_insn "rotlsi3"
44cd321e
PS		 3900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3901 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3902 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
1fd4e8c1 3903 ""
44cd321e
PS		 3904 "@
3905 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3906 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3907 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3908
a260abc9 3909(define_insn "*rotlsi3_internal2"
44cd321e
PS		 3910 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3911 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3912 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3913 (const_int 0)))
44cd321e 3914 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
ce71f754 3915 ""
9ebbca7d 3916 "@
44cd321e
PS		 3917 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3918 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3919 #
9ebbca7d 3920 #"
44cd321e
PS		 3921 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3922 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3923
3924(define_split
3925 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3926 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3927 (match_operand:SI 2 "reg_or_cint_operand" ""))
3928 (const_int 0)))
3929 (clobber (match_scratch:SI 3 ""))]
ce71f754 3930 "reload_completed"
9ebbca7d
GK		 3931 [(set (match_dup 3)
3932 (rotate:SI (match_dup 1) (match_dup 2)))
3933 (set (match_dup 0)
3934 (compare:CC (match_dup 3)
3935 (const_int 0)))]
3936 "")
1fd4e8c1 3937
a260abc9 3938(define_insn "*rotlsi3_internal3"
44cd321e
PS		 3939 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3940 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3941 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3942 (const_int 0)))
44cd321e 3943 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3944 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3945 ""
9ebbca7d 3946 "@
44cd321e
PS		 3947 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3948 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3949 #
9ebbca7d 3950 #"
44cd321e
PS		 3951 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3952 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3953
3954(define_split
3955 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3956 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3957 (match_operand:SI 2 "reg_or_cint_operand" ""))
3958 (const_int 0)))
3959 (set (match_operand:SI 0 "gpc_reg_operand" "")
3960 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3961 "reload_completed"
9ebbca7d
GK		 3962 [(set (match_dup 0)
3963 (rotate:SI (match_dup 1) (match_dup 2)))
3964 (set (match_dup 3)
3965 (compare:CC (match_dup 0)
3966 (const_int 0)))]
3967 "")
1fd4e8c1 3968
a260abc9 3969(define_insn "*rotlsi3_internal4"
44cd321e
PS		 3970 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3971 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3972 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3973 (match_operand:SI 3 "mask_operand" "n,n")))]
1fd4e8c1 3974 ""
44cd321e
PS		 3975 "@
3976 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3977 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3978 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3979
a260abc9 3980(define_insn "*rotlsi3_internal5"
44cd321e 3981 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 3982 (compare:CC (and:SI
44cd321e
PS		 3983 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3984 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3985 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 3986 (const_int 0)))
44cd321e 3987 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
ce71f754 3988 ""
9ebbca7d 3989 "@
44cd321e
PS		 3990 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3991 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3992 #
9ebbca7d 3993 #"
44cd321e
PS		 3994 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3995 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3996
3997(define_split
3998 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3999 (compare:CC (and:SI
4000 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4001 (match_operand:SI 2 "reg_or_cint_operand" ""))
4002 (match_operand:SI 3 "mask_operand" ""))
4003 (const_int 0)))
4004 (clobber (match_scratch:SI 4 ""))]
ce71f754 4005 "reload_completed"
9ebbca7d
GK		 4006 [(set (match_dup 4)
4007 (and:SI (rotate:SI (match_dup 1)
4008 (match_dup 2))
4009 (match_dup 3)))
4010 (set (match_dup 0)
4011 (compare:CC (match_dup 4)
4012 (const_int 0)))]
4013 "")
1fd4e8c1 4014
a260abc9 4015(define_insn "*rotlsi3_internal6"
44cd321e 4016 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 4017 (compare:CC (and:SI
44cd321e
PS		 4018 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4019 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4020 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 4021 (const_int 0)))
44cd321e 4022 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4023 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4024 ""
9ebbca7d 4025 "@
44cd321e
PS		 4026 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4027 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4028 #
9ebbca7d 4029 #"
44cd321e
PS		 4030 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4031 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4032
4033(define_split
4034 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4035 (compare:CC (and:SI
4036 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4037 (match_operand:SI 2 "reg_or_cint_operand" ""))
4038 (match_operand:SI 3 "mask_operand" ""))
4039 (const_int 0)))
4040 (set (match_operand:SI 0 "gpc_reg_operand" "")
4041 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4042 "reload_completed"
9ebbca7d
GK		 4043 [(set (match_dup 0)
4044 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4045 (set (match_dup 4)
4046 (compare:CC (match_dup 0)
4047 (const_int 0)))]
4048 "")
1fd4e8c1 4049
a260abc9 4050(define_insn "*rotlsi3_internal7"
cd2b37d9 4051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4052 (zero_extend:SI
4053 (subreg:QI
cd2b37d9 4054 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4055 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4056 ""
ca7f5001 4057 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1 4058
a260abc9 4059(define_insn "*rotlsi3_internal8"
44cd321e 4060 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4061 (compare:CC (zero_extend:SI
4062 (subreg:QI
44cd321e
PS		 4063 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4064 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4065 (const_int 0)))
44cd321e 4066 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4067 ""
9ebbca7d 4068 "@
44cd321e
PS		 4069 {rlnm.|rlwnm.} %3,%1,%2,0xff
4070 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4071 #
9ebbca7d 4072 #"
44cd321e
PS		 4073 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4074 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4075
4076(define_split
4077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4078 (compare:CC (zero_extend:SI
4079 (subreg:QI
4080 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4081 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4082 (const_int 0)))
4083 (clobber (match_scratch:SI 3 ""))]
4084 "reload_completed"
4085 [(set (match_dup 3)
4086 (zero_extend:SI (subreg:QI
4087 (rotate:SI (match_dup 1)
4088 (match_dup 2)) 0)))
4089 (set (match_dup 0)
4090 (compare:CC (match_dup 3)
4091 (const_int 0)))]
4092 "")
1fd4e8c1 4093
a260abc9 4094(define_insn "*rotlsi3_internal9"
44cd321e 4095 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4096 (compare:CC (zero_extend:SI
4097 (subreg:QI
44cd321e
PS		 4098 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4099 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4100 (const_int 0)))
44cd321e 4101 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4102 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4103 ""
9ebbca7d 4104 "@
44cd321e
PS		 4105 {rlnm.|rlwnm.} %0,%1,%2,0xff
4106 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4107 #
9ebbca7d 4108 #"
44cd321e
PS		 4109 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4110 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4111
4112(define_split
4113 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4114 (compare:CC (zero_extend:SI
4115 (subreg:QI
4116 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4117 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4118 (const_int 0)))
4119 (set (match_operand:SI 0 "gpc_reg_operand" "")
4120 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4121 "reload_completed"
4122 [(set (match_dup 0)
4123 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4124 (set (match_dup 3)
4125 (compare:CC (match_dup 0)
4126 (const_int 0)))]
4127 "")
1fd4e8c1 4128
a260abc9 4129(define_insn "*rotlsi3_internal10"
44cd321e 4130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4131 (zero_extend:SI
4132 (subreg:HI
44cd321e
PS		 4133 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4134 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
1fd4e8c1 4135 ""
44cd321e
PS		 4136 "@
4137 {rlnm|rlwnm} %0,%1,%2,0xffff
4138 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4139 [(set_attr "type" "var_shift_rotate,integer")])
4140
1fd4e8c1 4141
a260abc9 4142(define_insn "*rotlsi3_internal11"
44cd321e 4143 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4144 (compare:CC (zero_extend:SI
4145 (subreg:HI
44cd321e
PS		 4146 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4147 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4148 (const_int 0)))
44cd321e 4149 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4150 ""
9ebbca7d 4151 "@
44cd321e
PS		 4152 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4153 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4154 #
9ebbca7d 4155 #"
44cd321e
PS		 4156 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4157 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4158
4159(define_split
4160 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4161 (compare:CC (zero_extend:SI
4162 (subreg:HI
4163 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4164 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4165 (const_int 0)))
4166 (clobber (match_scratch:SI 3 ""))]
4167 "reload_completed"
4168 [(set (match_dup 3)
4169 (zero_extend:SI (subreg:HI
4170 (rotate:SI (match_dup 1)
4171 (match_dup 2)) 0)))
4172 (set (match_dup 0)
4173 (compare:CC (match_dup 3)
4174 (const_int 0)))]
4175 "")
1fd4e8c1 4176
a260abc9 4177(define_insn "*rotlsi3_internal12"
44cd321e 4178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4179 (compare:CC (zero_extend:SI
4180 (subreg:HI
44cd321e
PS		 4181 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4182 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4183 (const_int 0)))
44cd321e 4184 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4185 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4186 ""
9ebbca7d 4187 "@
44cd321e
PS		 4188 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4189 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4190 #
9ebbca7d 4191 #"
44cd321e
PS		 4192 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4193 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4194
4195(define_split
4196 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4197 (compare:CC (zero_extend:SI
4198 (subreg:HI
4199 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4200 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4201 (const_int 0)))
4202 (set (match_operand:SI 0 "gpc_reg_operand" "")
4203 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4204 "reload_completed"
4205 [(set (match_dup 0)
4206 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4207 (set (match_dup 3)
4208 (compare:CC (match_dup 0)
4209 (const_int 0)))]
4210 "")
1fd4e8c1
RK		 4211
4212;; Note that we use "sle." instead of "sl." so that we can set
4213;; SHIFT_COUNT_TRUNCATED.
4214
ca7f5001
RK		 4215(define_expand "ashlsi3"
4216 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4217 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4218 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4219 ""
4220 "
4221{
4222 if (TARGET_POWER)
4223 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4224 else
25c341fa 4225 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4226 DONE;
4227}")
4228
4229(define_insn "ashlsi3_power"
cd2b37d9
RK		 4230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4231 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4232 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4233 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4234 "TARGET_POWER"
1fd4e8c1
RK		 4235 "@
4236 sle %0,%1,%2
9ebbca7d 4237 {sli|slwi} %0,%1,%h2")
ca7f5001 4238
25c341fa 4239(define_insn "ashlsi3_no_power"
44cd321e
PS		 4240 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4241 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4242 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4243 "! TARGET_POWER"
44cd321e
PS		 4244 "@
4245 {sl|slw} %0,%1,%2
4246 {sli|slwi} %0,%1,%h2"
4247 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4248
4249(define_insn ""
9ebbca7d
GK		 4250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4251 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4252 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4253 (const_int 0)))
9ebbca7d
GK		 4254 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4255 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4256 "TARGET_POWER"
1fd4e8c1
RK		 4257 "@
4258 sle. %3,%1,%2
9ebbca7d
GK		 4259 {sli.|slwi.} %3,%1,%h2
4260 #
4261 #"
4262 [(set_attr "type" "delayed_compare")
4263 (set_attr "length" "4,4,8,8")])
4264
4265(define_split
4266 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4267 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4268 (match_operand:SI 2 "reg_or_cint_operand" ""))
4269 (const_int 0)))
4270 (clobber (match_scratch:SI 3 ""))
4271 (clobber (match_scratch:SI 4 ""))]
4272 "TARGET_POWER && reload_completed"
4273 [(parallel [(set (match_dup 3)
4274 (ashift:SI (match_dup 1) (match_dup 2)))
4275 (clobber (match_dup 4))])
4276 (set (match_dup 0)
4277 (compare:CC (match_dup 3)
4278 (const_int 0)))]
4279 "")
25c341fa 4280
ca7f5001 4281(define_insn ""
44cd321e
PS		 4282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4283 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4284 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4285 (const_int 0)))
44cd321e 4286 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4b8a63d6 4287 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4288 "@
44cd321e
PS		 4289 {sl.|slw.} %3,%1,%2
4290 {sli.|slwi.} %3,%1,%h2
4291 #
9ebbca7d 4292 #"
44cd321e
PS		 4293 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4294 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4295
4296(define_split
4297 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4298 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4299 (match_operand:SI 2 "reg_or_cint_operand" ""))
4300 (const_int 0)))
4301 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4302 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4303 [(set (match_dup 3)
4304 (ashift:SI (match_dup 1) (match_dup 2)))
4305 (set (match_dup 0)
4306 (compare:CC (match_dup 3)
4307 (const_int 0)))]
4308 "")
1fd4e8c1
RK		 4309
4310(define_insn ""
9ebbca7d
GK		 4311 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4312 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4313 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4314 (const_int 0)))
9ebbca7d 4315 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4316 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4317 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4318 "TARGET_POWER"
1fd4e8c1
RK		 4319 "@
4320 sle. %0,%1,%2
9ebbca7d
GK		 4321 {sli.|slwi.} %0,%1,%h2
4322 #
4323 #"
4324 [(set_attr "type" "delayed_compare")
4325 (set_attr "length" "4,4,8,8")])
4326
4327(define_split
4328 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4329 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4330 (match_operand:SI 2 "reg_or_cint_operand" ""))
4331 (const_int 0)))
4332 (set (match_operand:SI 0 "gpc_reg_operand" "")
4333 (ashift:SI (match_dup 1) (match_dup 2)))
4334 (clobber (match_scratch:SI 4 ""))]
4335 "TARGET_POWER && reload_completed"
4336 [(parallel [(set (match_dup 0)
4337 (ashift:SI (match_dup 1) (match_dup 2)))
4338 (clobber (match_dup 4))])
4339 (set (match_dup 3)
4340 (compare:CC (match_dup 0)
4341 (const_int 0)))]
4342 "")
25c341fa 4343
ca7f5001 4344(define_insn ""
44cd321e
PS		 4345 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4346 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4347 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4348 (const_int 0)))
44cd321e 4349 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 4350 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4351 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4352 "@
44cd321e
PS		 4353 {sl.|slw.} %0,%1,%2
4354 {sli.|slwi.} %0,%1,%h2
4355 #
9ebbca7d 4356 #"
44cd321e
PS		 4357 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4358 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4359
4360(define_split
4361 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4362 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4363 (match_operand:SI 2 "reg_or_cint_operand" ""))
4364 (const_int 0)))
4365 (set (match_operand:SI 0 "gpc_reg_operand" "")
4366 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4367 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4368 [(set (match_dup 0)
4369 (ashift:SI (match_dup 1) (match_dup 2)))
4370 (set (match_dup 3)
4371 (compare:CC (match_dup 0)
4372 (const_int 0)))]
4373 "")
1fd4e8c1 4374
915167f5 4375(define_insn "rlwinm"
cd2b37d9
RK		 4376 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4377 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4378 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4379 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4380 "includes_lshift_p (operands[2], operands[3])"
d56d506a 4381 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 4382
4383(define_insn ""
9ebbca7d 4384 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4385 (compare:CC
9ebbca7d
GK		 4386 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4387 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4388 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4389 (const_int 0)))
9ebbca7d 4390 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4391 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4392 "@
4393 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4394 #"
4395 [(set_attr "type" "delayed_compare")
4396 (set_attr "length" "4,8")])
4397
4398(define_split
4399 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4400 (compare:CC
4401 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4402 (match_operand:SI 2 "const_int_operand" ""))
4403 (match_operand:SI 3 "mask_operand" ""))
4404 (const_int 0)))
4405 (clobber (match_scratch:SI 4 ""))]
ce71f754 4406 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4407 [(set (match_dup 4)
4408 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4409 (match_dup 3)))
4410 (set (match_dup 0)
4411 (compare:CC (match_dup 4)
4412 (const_int 0)))]
4413 "")
1fd4e8c1
RK		 4414
4415(define_insn ""
9ebbca7d 4416 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4417 (compare:CC
9ebbca7d
GK		 4418 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4419 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4420 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4421 (const_int 0)))
9ebbca7d 4422 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4423 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4424 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4425 "@
4426 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4427 #"
4428 [(set_attr "type" "delayed_compare")
4429 (set_attr "length" "4,8")])
4430
4431(define_split
4432 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4433 (compare:CC
4434 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4435 (match_operand:SI 2 "const_int_operand" ""))
4436 (match_operand:SI 3 "mask_operand" ""))
4437 (const_int 0)))
4438 (set (match_operand:SI 0 "gpc_reg_operand" "")
4439 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4440 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4441 [(set (match_dup 0)
4442 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4443 (set (match_dup 4)
4444 (compare:CC (match_dup 0)
4445 (const_int 0)))]
4446 "")
1fd4e8c1 4447
ca7f5001 4448;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 4449;; "sli x,x,0".
ca7f5001
RK		 4450(define_expand "lshrsi3"
4451 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4452 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4453 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4454 ""
4455 "
4456{
4457 if (TARGET_POWER)
4458 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4459 else
25c341fa 4460 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4461 DONE;
4462}")
4463
4464(define_insn "lshrsi3_power"
bdf423cb
MM		 4465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4466 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4467 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4468 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 4469 "TARGET_POWER"
1fd4e8c1
RK		 4470 "@
4471 sre %0,%1,%2
bdf423cb 4472 mr %0,%1
ca7f5001
RK		 4473 {s%A2i|s%A2wi} %0,%1,%h2")
4474
25c341fa 4475(define_insn "lshrsi3_no_power"
44cd321e
PS		 4476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4477 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4478 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
25c341fa 4479 "! TARGET_POWER"
bdf423cb
MM		 4480 "@
4481 mr %0,%1
44cd321e
PS		 4482 {sr|srw} %0,%1,%2
4483 {sri|srwi} %0,%1,%h2"
4484 [(set_attr "type" "integer,var_shift_rotate,shift")])
1fd4e8c1
RK		 4485
4486(define_insn ""
9ebbca7d
GK		 4487 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4488 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4489 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4490 (const_int 0)))
9ebbca7d
GK		 4491 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4492 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4493 "TARGET_POWER"
1fd4e8c1 4494 "@
29ae5b89
JL		 4495 sre. %3,%1,%2
4496 mr. %1,%1
9ebbca7d
GK		 4497 {s%A2i.|s%A2wi.} %3,%1,%h2
4498 #
4499 #
4500 #"
4501 [(set_attr "type" "delayed_compare")
4502 (set_attr "length" "4,4,4,8,8,8")])
4503
4504(define_split
4505 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4506 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4507 (match_operand:SI 2 "reg_or_cint_operand" ""))
4508 (const_int 0)))
4509 (clobber (match_scratch:SI 3 ""))
4510 (clobber (match_scratch:SI 4 ""))]
4511 "TARGET_POWER && reload_completed"
4512 [(parallel [(set (match_dup 3)
4513 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4514 (clobber (match_dup 4))])
4515 (set (match_dup 0)
4516 (compare:CC (match_dup 3)
4517 (const_int 0)))]
4518 "")
ca7f5001
RK		 4519
4520(define_insn ""
44cd321e
PS		 4521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4522 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4523 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
ca7f5001 4524 (const_int 0)))
44cd321e 4525 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4b8a63d6 4526 "! TARGET_POWER && TARGET_32BIT"
bdf423cb
MM		 4527 "@
4528 mr. %1,%1
44cd321e
PS		 4529 {sr.|srw.} %3,%1,%2
4530 {sri.|srwi.} %3,%1,%h2
4531 #
9ebbca7d
GK		 4532 #
4533 #"
44cd321e
PS		 4534 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4535 (set_attr "length" "4,4,4,8,8,8")])
1fd4e8c1 4536
9ebbca7d
GK		 4537(define_split
4538 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4539 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4540 (match_operand:SI 2 "reg_or_cint_operand" ""))
4541 (const_int 0)))
4542 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4543 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4544 [(set (match_dup 3)
4545 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4546 (set (match_dup 0)
4547 (compare:CC (match_dup 3)
4548 (const_int 0)))]
4549 "")
4550
4551(define_insn ""
4552 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4553 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4554 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4555 (const_int 0)))
9ebbca7d 4556 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 4557 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4558 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4559 "TARGET_POWER"
1fd4e8c1 4560 "@
29ae5b89
JL		 4561 sre. %0,%1,%2
4562 mr. %0,%1
9ebbca7d
GK		 4563 {s%A2i.|s%A2wi.} %0,%1,%h2
4564 #
4565 #
4566 #"
4567 [(set_attr "type" "delayed_compare")
4568 (set_attr "length" "4,4,4,8,8,8")])
4569
4570(define_split
4571 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4572 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4573 (match_operand:SI 2 "reg_or_cint_operand" ""))
4574 (const_int 0)))
4575 (set (match_operand:SI 0 "gpc_reg_operand" "")
4576 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4577 (clobber (match_scratch:SI 4 ""))]
4578 "TARGET_POWER && reload_completed"
4579 [(parallel [(set (match_dup 0)
4580 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4581 (clobber (match_dup 4))])
4582 (set (match_dup 3)
4583 (compare:CC (match_dup 0)
4584 (const_int 0)))]
4585 "")
ca7f5001
RK		 4586
4587(define_insn ""
44cd321e
PS		 4588 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4589 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4590 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
815cdc52 4591 (const_int 0)))
44cd321e 4592 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
29ae5b89 4593 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4594 "! TARGET_POWER && TARGET_32BIT"
29ae5b89
JL		 4595 "@
4596 mr. %0,%1
44cd321e
PS		 4597 {sr.|srw.} %0,%1,%2
4598 {sri.|srwi.} %0,%1,%h2
4599 #
9ebbca7d
GK		 4600 #
4601 #"
44cd321e
PS		 4602 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4603 (set_attr "length" "4,4,4,8,8,8")])
9ebbca7d
GK		 4604
4605(define_split
4606 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4607 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4608 (match_operand:SI 2 "reg_or_cint_operand" ""))
4609 (const_int 0)))
4610 (set (match_operand:SI 0 "gpc_reg_operand" "")
4611 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4612 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4613 [(set (match_dup 0)
4614 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4615 (set (match_dup 3)
4616 (compare:CC (match_dup 0)
4617 (const_int 0)))]
4618 "")
1fd4e8c1
RK		 4619
4620(define_insn ""
cd2b37d9
RK		 4621 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4622 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4623 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4624 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4625 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 4626 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 4627
4628(define_insn ""
9ebbca7d 4629 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4630 (compare:CC
9ebbca7d
GK		 4631 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4632 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4633 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4634 (const_int 0)))
9ebbca7d 4635 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4636 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4637 "@
4638 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4639 #"
4640 [(set_attr "type" "delayed_compare")
4641 (set_attr "length" "4,8")])
4642
4643(define_split
4644 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4645 (compare:CC
4646 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4647 (match_operand:SI 2 "const_int_operand" ""))
4648 (match_operand:SI 3 "mask_operand" ""))
4649 (const_int 0)))
4650 (clobber (match_scratch:SI 4 ""))]
ce71f754 4651 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4652 [(set (match_dup 4)
4653 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4654 (match_dup 3)))
4655 (set (match_dup 0)
4656 (compare:CC (match_dup 4)
4657 (const_int 0)))]
4658 "")
1fd4e8c1
RK		 4659
4660(define_insn ""
9ebbca7d 4661 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4662 (compare:CC
9ebbca7d
GK		 4663 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4664 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4665 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4666 (const_int 0)))
9ebbca7d 4667 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4668 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4669 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4670 "@
4671 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4672 #"
4673 [(set_attr "type" "delayed_compare")
4674 (set_attr "length" "4,8")])
4675
4676(define_split
4677 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4678 (compare:CC
4679 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4680 (match_operand:SI 2 "const_int_operand" ""))
4681 (match_operand:SI 3 "mask_operand" ""))
4682 (const_int 0)))
4683 (set (match_operand:SI 0 "gpc_reg_operand" "")
4684 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4685 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4686 [(set (match_dup 0)
4687 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4688 (set (match_dup 4)
4689 (compare:CC (match_dup 0)
4690 (const_int 0)))]
4691 "")
1fd4e8c1
RK		 4692
4693(define_insn ""
cd2b37d9 4694 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4695 (zero_extend:SI
4696 (subreg:QI
cd2b37d9 4697 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4698 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4699 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4700 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4701
4702(define_insn ""
9ebbca7d 4703 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4704 (compare:CC
4705 (zero_extend:SI
4706 (subreg:QI
9ebbca7d
GK		 4707 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4708 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4709 (const_int 0)))
9ebbca7d 4710 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4711 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4712 "@
4713 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4714 #"
4715 [(set_attr "type" "delayed_compare")
4716 (set_attr "length" "4,8")])
4717
4718(define_split
4719 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4720 (compare:CC
4721 (zero_extend:SI
4722 (subreg:QI
4723 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4724 (match_operand:SI 2 "const_int_operand" "")) 0))
4725 (const_int 0)))
4726 (clobber (match_scratch:SI 3 ""))]
4727 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4728 [(set (match_dup 3)
4729 (zero_extend:SI (subreg:QI
4730 (lshiftrt:SI (match_dup 1)
4731 (match_dup 2)) 0)))
4732 (set (match_dup 0)
4733 (compare:CC (match_dup 3)
4734 (const_int 0)))]
4735 "")
1fd4e8c1
RK		 4736
4737(define_insn ""
9ebbca7d 4738 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4739 (compare:CC
4740 (zero_extend:SI
4741 (subreg:QI
9ebbca7d
GK		 4742 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4743 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4744 (const_int 0)))
9ebbca7d 4745 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4746 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4747 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4748 "@
4749 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4750 #"
4751 [(set_attr "type" "delayed_compare")
4752 (set_attr "length" "4,8")])
4753
4754(define_split
4755 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4756 (compare:CC
4757 (zero_extend:SI
4758 (subreg:QI
4759 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4760 (match_operand:SI 2 "const_int_operand" "")) 0))
4761 (const_int 0)))
4762 (set (match_operand:SI 0 "gpc_reg_operand" "")
4763 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4764 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4765 [(set (match_dup 0)
4766 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4767 (set (match_dup 3)
4768 (compare:CC (match_dup 0)
4769 (const_int 0)))]
4770 "")
1fd4e8c1
RK		 4771
4772(define_insn ""
cd2b37d9 4773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4774 (zero_extend:SI
4775 (subreg:HI
cd2b37d9 4776 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4777 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4778 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4779 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4780
4781(define_insn ""
9ebbca7d 4782 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4783 (compare:CC
4784 (zero_extend:SI
4785 (subreg:HI
9ebbca7d
GK		 4786 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4787 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4788 (const_int 0)))
9ebbca7d 4789 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4790 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4791 "@
4792 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4793 #"
4794 [(set_attr "type" "delayed_compare")
4795 (set_attr "length" "4,8")])
4796
4797(define_split
4798 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4799 (compare:CC
4800 (zero_extend:SI
4801 (subreg:HI
4802 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4803 (match_operand:SI 2 "const_int_operand" "")) 0))
4804 (const_int 0)))
4805 (clobber (match_scratch:SI 3 ""))]
4806 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4807 [(set (match_dup 3)
4808 (zero_extend:SI (subreg:HI
4809 (lshiftrt:SI (match_dup 1)
4810 (match_dup 2)) 0)))
4811 (set (match_dup 0)
4812 (compare:CC (match_dup 3)
4813 (const_int 0)))]
4814 "")
1fd4e8c1
RK		 4815
4816(define_insn ""
9ebbca7d 4817 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4818 (compare:CC
4819 (zero_extend:SI
4820 (subreg:HI
9ebbca7d
GK		 4821 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4822 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4823 (const_int 0)))
9ebbca7d 4824 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4825 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4826 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4827 "@
4828 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4829 #"
4830 [(set_attr "type" "delayed_compare")
4831 (set_attr "length" "4,8")])
4832
4833(define_split
4834 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4835 (compare:CC
4836 (zero_extend:SI
4837 (subreg:HI
4838 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4839 (match_operand:SI 2 "const_int_operand" "")) 0))
4840 (const_int 0)))
4841 (set (match_operand:SI 0 "gpc_reg_operand" "")
4842 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4843 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4844 [(set (match_dup 0)
4845 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4846 (set (match_dup 3)
4847 (compare:CC (match_dup 0)
4848 (const_int 0)))]
4849 "")
1fd4e8c1
RK		 4850
4851(define_insn ""
cd2b37d9 4852 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4853 (const_int 1)
cd2b37d9
RK		 4854 (match_operand:SI 1 "gpc_reg_operand" "r"))
4855 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4856 (const_int 31)))]
ca7f5001 4857 "TARGET_POWER"
1fd4e8c1
RK		 4858 "rrib %0,%1,%2")
4859
4860(define_insn ""
cd2b37d9 4861 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4862 (const_int 1)
cd2b37d9
RK		 4863 (match_operand:SI 1 "gpc_reg_operand" "r"))
4864 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4865 (const_int 31)))]
ca7f5001 4866 "TARGET_POWER"
1fd4e8c1
RK		 4867 "rrib %0,%1,%2")
4868
4869(define_insn ""
cd2b37d9 4870 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4871 (const_int 1)
cd2b37d9
RK		 4872 (match_operand:SI 1 "gpc_reg_operand" "r"))
4873 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4874 (const_int 1)
4875 (const_int 0)))]
ca7f5001 4876 "TARGET_POWER"
1fd4e8c1
RK		 4877 "rrib %0,%1,%2")
4878
ca7f5001
RK		 4879(define_expand "ashrsi3"
4880 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4881 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4882 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4883 ""
4884 "
4885{
4886 if (TARGET_POWER)
4887 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4888 else
25c341fa 4889 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4890 DONE;
4891}")
4892
4893(define_insn "ashrsi3_power"
cd2b37d9
RK		 4894 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4895 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4896 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4897 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4898 "TARGET_POWER"
1fd4e8c1
RK		 4899 "@
4900 srea %0,%1,%2
44cd321e
PS		 4901 {srai|srawi} %0,%1,%h2"
4902 [(set_attr "type" "shift")])
ca7f5001 4903
25c341fa 4904(define_insn "ashrsi3_no_power"
44cd321e
PS		 4905 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4906 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4907 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4908 "! TARGET_POWER"
44cd321e
PS		 4909 "@
4910 {sra|sraw} %0,%1,%2
4911 {srai|srawi} %0,%1,%h2"
4912 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4913
4914(define_insn ""
9ebbca7d
GK		 4915 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4916 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4917 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4918 (const_int 0)))
9ebbca7d
GK		 4919 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4920 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4921 "TARGET_POWER"
1fd4e8c1
RK		 4922 "@
4923 srea. %3,%1,%2
9ebbca7d
GK		 4924 {srai.|srawi.} %3,%1,%h2
4925 #
4926 #"
4927 [(set_attr "type" "delayed_compare")
4928 (set_attr "length" "4,4,8,8")])
4929
4930(define_split
4931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4932 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4933 (match_operand:SI 2 "reg_or_cint_operand" ""))
4934 (const_int 0)))
4935 (clobber (match_scratch:SI 3 ""))
4936 (clobber (match_scratch:SI 4 ""))]
4937 "TARGET_POWER && reload_completed"
4938 [(parallel [(set (match_dup 3)
4939 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4940 (clobber (match_dup 4))])
4941 (set (match_dup 0)
4942 (compare:CC (match_dup 3)
4943 (const_int 0)))]
4944 "")
ca7f5001
RK		 4945
4946(define_insn ""
44cd321e
PS		 4947 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4948 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4949 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4950 (const_int 0)))
44cd321e 4951 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
25c341fa 4952 "! TARGET_POWER"
9ebbca7d 4953 "@
44cd321e
PS		 4954 {sra.|sraw.} %3,%1,%2
4955 {srai.|srawi.} %3,%1,%h2
4956 #
9ebbca7d 4957 #"
44cd321e
PS		 4958 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4959 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4960
4961(define_split
4962 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4963 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4964 (match_operand:SI 2 "reg_or_cint_operand" ""))
4965 (const_int 0)))
4966 (clobber (match_scratch:SI 3 ""))]
4967 "! TARGET_POWER && reload_completed"
4968 [(set (match_dup 3)
4969 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4970 (set (match_dup 0)
4971 (compare:CC (match_dup 3)
4972 (const_int 0)))]
4973 "")
1fd4e8c1
RK		 4974
4975(define_insn ""
9ebbca7d
GK		 4976 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4977 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4978 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4979 (const_int 0)))
9ebbca7d 4980 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4981 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4982 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4983 "TARGET_POWER"
1fd4e8c1
RK		 4984 "@
4985 srea. %0,%1,%2
9ebbca7d
GK		 4986 {srai.|srawi.} %0,%1,%h2
4987 #
4988 #"
4989 [(set_attr "type" "delayed_compare")
4990 (set_attr "length" "4,4,8,8")])
4991
4992(define_split
4993 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4994 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4995 (match_operand:SI 2 "reg_or_cint_operand" ""))
4996 (const_int 0)))
4997 (set (match_operand:SI 0 "gpc_reg_operand" "")
4998 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4999 (clobber (match_scratch:SI 4 ""))]
5000 "TARGET_POWER && reload_completed"
5001 [(parallel [(set (match_dup 0)
5002 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5003 (clobber (match_dup 4))])
5004 (set (match_dup 3)
5005 (compare:CC (match_dup 0)
5006 (const_int 0)))]
5007 "")
1fd4e8c1 5008
ca7f5001 5009(define_insn ""
44cd321e
PS		 5010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5011 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5012 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 5013 (const_int 0)))
44cd321e 5014 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 5015 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 5016 "! TARGET_POWER"
9ebbca7d 5017 "@
44cd321e
PS		 5018 {sra.|sraw.} %0,%1,%2
5019 {srai.|srawi.} %0,%1,%h2
5020 #
9ebbca7d 5021 #"
44cd321e
PS		 5022 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5023 (set_attr "length" "4,4,8,8")])
1fd4e8c1 5024\f
9ebbca7d
GK		 5025(define_split
5026 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5027 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5028 (match_operand:SI 2 "reg_or_cint_operand" ""))
5029 (const_int 0)))
5030 (set (match_operand:SI 0 "gpc_reg_operand" "")
5031 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5032 "! TARGET_POWER && reload_completed"
5033 [(set (match_dup 0)
5034 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5035 (set (match_dup 3)
5036 (compare:CC (match_dup 0)
5037 (const_int 0)))]
5038 "")
5039
1fd4e8c1
RK		 5040;; Floating-point insns, excluding normal data motion.
5041;;
ca7f5001
RK		 5042;; PowerPC has a full set of single-precision floating point instructions.
5043;;
5044;; For the POWER architecture, we pretend that we have both SFmode and
5045;; DFmode insns, while, in fact, all fp insns are actually done in double.
5046;; The only conversions we will do will be when storing to memory. In that
5047;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 5048;;
5049;; Note that when we store into a single-precision memory location, we need to
5050;; use the frsp insn first. If the register being stored isn't dead, we
5051;; need a scratch register for the frsp. But this is difficult when the store
5052;; is done by reload. It is not incorrect to do the frsp on the register in
5053;; this case, we just lose precision that we would have otherwise gotten but
5054;; is not guaranteed. Perhaps this should be tightened up at some point.
5055
99176a91
AH		 5056(define_expand "extendsfdf2"
5057 [(set (match_operand:DF 0 "gpc_reg_operand" "")
97c54d9a 5058 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
99176a91
AH		 5059 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5060 "")
5061
5062(define_insn_and_split "*extendsfdf2_fpr"
97c54d9a
DE		 5063 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5064 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
a3170dc6 5065 "TARGET_HARD_FLOAT && TARGET_FPRS"
11ac38b2
DE		 5066 "@
5067 #
97c54d9a
DE		 5068 fmr %0,%1
5069 lfs%U1%X1 %0,%1"
d7b1468b 5070 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
11ac38b2 5071 [(const_int 0)]
5c30aff8 5072{
11ac38b2
DE		 5073 emit_note (NOTE_INSN_DELETED);
5074 DONE;
5075}
97c54d9a 5076 [(set_attr "type" "fp,fp,fpload")])
1fd4e8c1 5077
7a2f7870
AH		 5078(define_expand "truncdfsf2"
5079 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5080 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5081 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5082 "")
5083
99176a91 5084(define_insn "*truncdfsf2_fpr"
cd2b37d9
RK		 5085 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5086 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5087 "TARGET_HARD_FLOAT && TARGET_FPRS"
dcac138d 5088 "frsp %0,%1"
1fd4e8c1
RK		 5089 [(set_attr "type" "fp")])
5090
455350f4
RK		 5091(define_insn "aux_truncdfsf2"
5092 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 5093 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
a3170dc6 5094 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 5095 "frsp %0,%1"
5096 [(set_attr "type" "fp")])
5097
a3170dc6
AH		 5098(define_expand "negsf2"
5099 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5100 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5101 "TARGET_HARD_FLOAT"
5102 "")
5103
5104(define_insn "*negsf2"
cd2b37d9
RK		 5105 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5106 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5107 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5108 "fneg %0,%1"
5109 [(set_attr "type" "fp")])
5110
a3170dc6
AH		 5111(define_expand "abssf2"
5112 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5113 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5114 "TARGET_HARD_FLOAT"
5115 "")
5116
5117(define_insn "*abssf2"
cd2b37d9
RK		 5118 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5119 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5120 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5121 "fabs %0,%1"
5122 [(set_attr "type" "fp")])
5123
5124(define_insn ""
cd2b37d9
RK		 5125 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5126 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
a3170dc6 5127 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5128 "fnabs %0,%1"
5129 [(set_attr "type" "fp")])
5130
ca7f5001
RK		 5131(define_expand "addsf3"
5132 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5133 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5134 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5135 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5136 "")
5137
5138(define_insn ""
cd2b37d9
RK		 5139 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5140 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5141 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5142 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5143 "fadds %0,%1,%2"
ca7f5001
RK		 5144 [(set_attr "type" "fp")])
5145
5146(define_insn ""
5147 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5148 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5149 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5150 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5151 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 5152 [(set_attr "type" "fp")])
5153
5154(define_expand "subsf3"
5155 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5156 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5157 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5158 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5159 "")
5160
5161(define_insn ""
5162 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5163 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5164 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5165 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5166 "fsubs %0,%1,%2"
1fd4e8c1
RK		 5167 [(set_attr "type" "fp")])
5168
ca7f5001 5169(define_insn ""
cd2b37d9
RK		 5170 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5171 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5172 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5173 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5174 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 5175 [(set_attr "type" "fp")])
5176
5177(define_expand "mulsf3"
5178 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5179 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5180 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5181 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5182 "")
5183
5184(define_insn ""
5185 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5186 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5187 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5188 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5189 "fmuls %0,%1,%2"
1fd4e8c1
RK		 5190 [(set_attr "type" "fp")])
5191
ca7f5001 5192(define_insn ""
cd2b37d9
RK		 5193 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5194 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5195 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5196 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5197 "{fm|fmul} %0,%1,%2"
0780f386 5198 [(set_attr "type" "dmul")])
1fd4e8c1 5199
ef765ea9
DE		 5200(define_insn "fres"
5201 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5202 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5203 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5204 "fres %0,%1"
5205 [(set_attr "type" "fp")])
5206
ca7f5001
RK		 5207(define_expand "divsf3"
5208 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5209 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5210 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5211 "TARGET_HARD_FLOAT"
ef765ea9
DE		 5212{
5213 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5214 && flag_finite_math_only && !flag_trapping_math)
5215 {
5216 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5217 DONE;
5218 }
5219})
ca7f5001
RK		 5220
5221(define_insn ""
cd2b37d9
RK		 5222 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5223 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5224 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5225 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5226 "fdivs %0,%1,%2"
ca7f5001
RK		 5227 [(set_attr "type" "sdiv")])
5228
5229(define_insn ""
5230 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5231 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5232 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5233 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5234 "{fd|fdiv} %0,%1,%2"
0780f386 5235 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 5236
5237(define_insn ""
cd2b37d9
RK		 5238 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5239 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5240 (match_operand:SF 2 "gpc_reg_operand" "f"))
5241 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5242 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5243 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 5244 [(set_attr "type" "fp")])
5245
5246(define_insn ""
5247 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5248 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5249 (match_operand:SF 2 "gpc_reg_operand" "f"))
5250 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5251 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5252 "{fma|fmadd} %0,%1,%2,%3"
cf27b467 5253 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5254
5255(define_insn ""
cd2b37d9
RK		 5256 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5257 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5258 (match_operand:SF 2 "gpc_reg_operand" "f"))
5259 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5260 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5261 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 5262 [(set_attr "type" "fp")])
5263
5264(define_insn ""
5265 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5266 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5267 (match_operand:SF 2 "gpc_reg_operand" "f"))
5268 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5269 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5270 "{fms|fmsub} %0,%1,%2,%3"
cf27b467 5271 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5272
5273(define_insn ""
cd2b37d9
RK		 5274 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5275 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5276 (match_operand:SF 2 "gpc_reg_operand" "f"))
5277 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5278 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5279 && HONOR_SIGNED_ZEROS (SFmode)"
5280 "fnmadds %0,%1,%2,%3"
5281 [(set_attr "type" "fp")])
5282
5283(define_insn ""
5284 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5285 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5286 (match_operand:SF 2 "gpc_reg_operand" "f"))
5287 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5288 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5289 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5290 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 5291 [(set_attr "type" "fp")])
5292
5293(define_insn ""
5294 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5295 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5296 (match_operand:SF 2 "gpc_reg_operand" "f"))
5297 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 5298 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5299 "{fnma|fnmadd} %0,%1,%2,%3"
cf27b467 5300 [(set_attr "type" "dmul")])
1fd4e8c1 5301
16823694
GK		 5302(define_insn ""
5303 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5304 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5305 (match_operand:SF 2 "gpc_reg_operand" "f"))
5306 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5307 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5308 && ! HONOR_SIGNED_ZEROS (SFmode)"
5309 "{fnma|fnmadd} %0,%1,%2,%3"
5310 [(set_attr "type" "dmul")])
5311
1fd4e8c1 5312(define_insn ""
cd2b37d9
RK		 5313 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5314 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5315 (match_operand:SF 2 "gpc_reg_operand" "f"))
5316 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5317 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5318 && HONOR_SIGNED_ZEROS (SFmode)"
5319 "fnmsubs %0,%1,%2,%3"
5320 [(set_attr "type" "fp")])
5321
5322(define_insn ""
5323 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5324 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5325 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5326 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5327 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5328 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5329 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 5330 [(set_attr "type" "fp")])
5331
5332(define_insn ""
5333 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5334 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5335 (match_operand:SF 2 "gpc_reg_operand" "f"))
5336 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 5337 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5338 "{fnms|fnmsub} %0,%1,%2,%3"
cf27b467 5339 [(set_attr "type" "dmul")])
1fd4e8c1 5340
16823694
GK		 5341(define_insn ""
5342 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5343 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5344 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5345 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5346 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5347 && ! HONOR_SIGNED_ZEROS (SFmode)"
5348 "{fnms|fnmsub} %0,%1,%2,%3"
9c6fdb46 5349 [(set_attr "type" "dmul")])
16823694 5350
ca7f5001
RK		 5351(define_expand "sqrtsf2"
5352 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5353 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
a3170dc6 5354 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5355 "")
5356
5357(define_insn ""
5358 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5359 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5360 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5361 "fsqrts %0,%1"
5362 [(set_attr "type" "ssqrt")])
5363
5364(define_insn ""
5365 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5366 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5367 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5368 "fsqrt %0,%1"
5369 [(set_attr "type" "dsqrt")])
5370
0530bc70
AP		 5371(define_expand "copysignsf3"
5372 [(set (match_dup 3)
5373 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5374 (set (match_dup 4)
5375 (neg:SF (abs:SF (match_dup 1))))
5376 (set (match_operand:SF 0 "gpc_reg_operand" "")
5377 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5378 (match_dup 5))
5379 (match_dup 3)
5380 (match_dup 4)))]
5381 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
bb8df8a6 5382 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
0530bc70
AP		 5383 {
5384 operands[3] = gen_reg_rtx (SFmode);
5385 operands[4] = gen_reg_rtx (SFmode);
5386 operands[5] = CONST0_RTX (SFmode);
5387 })
5388
5389(define_expand "copysigndf3"
5390 [(set (match_dup 3)
5391 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5392 (set (match_dup 4)
5393 (neg:DF (abs:DF (match_dup 1))))
5394 (set (match_operand:DF 0 "gpc_reg_operand" "")
5395 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5396 (match_dup 5))
5397 (match_dup 3)
5398 (match_dup 4)))]
5399 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5400 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5401 {
5402 operands[3] = gen_reg_rtx (DFmode);
5403 operands[4] = gen_reg_rtx (DFmode);
5404 operands[5] = CONST0_RTX (DFmode);
5405 })
5406
94d7001a
RK		 5407;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5408;; fsel instruction and some auxiliary computations. Then we just have a
5409;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05 5410;; combine.
7ae4d8d4 5411(define_expand "smaxsf3"
8e871c05 5412 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5413 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5414 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5415 (match_dup 1)
5416 (match_dup 2)))]
89e73849 5417 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5418 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 5419
7ae4d8d4 5420(define_expand "sminsf3"
50a0b056
GK		 5421 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5422 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5423 (match_operand:SF 2 "gpc_reg_operand" ""))
5424 (match_dup 2)
5425 (match_dup 1)))]
89e73849 5426 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5427 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 5428
8e871c05
RK		 5429(define_split
5430 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5431 (match_operator:SF 3 "min_max_operator"
5432 [(match_operand:SF 1 "gpc_reg_operand" "")
5433 (match_operand:SF 2 "gpc_reg_operand" "")]))]
89e73849 5434 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5435 [(const_int 0)]
5436 "
6ae08853 5437{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5438 operands[1], operands[2]);
5439 DONE;
5440}")
2f607b94 5441
a3170dc6
AH		 5442(define_expand "movsicc"
5443 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5444 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5445 (match_operand:SI 2 "gpc_reg_operand" "")
5446 (match_operand:SI 3 "gpc_reg_operand" "")))]
5447 "TARGET_ISEL"
5448 "
5449{
5450 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5451 DONE;
5452 else
5453 FAIL;
5454}")
5455
5456;; We use the BASE_REGS for the isel input operands because, if rA is
5457;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5458;; because we may switch the operands and rB may end up being rA.
5459;;
5460;; We need 2 patterns: an unsigned and a signed pattern. We could
5461;; leave out the mode in operand 4 and use one pattern, but reload can
5462;; change the mode underneath our feet and then gets confused trying
5463;; to reload the value.
5464(define_insn "isel_signed"
5465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5466 (if_then_else:SI
5467 (match_operator 1 "comparison_operator"
5468 [(match_operand:CC 4 "cc_reg_operand" "y")
5469 (const_int 0)])
5470 (match_operand:SI 2 "gpc_reg_operand" "b")
5471 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5472 "TARGET_ISEL"
5473 "*
5474{ return output_isel (operands); }"
5475 [(set_attr "length" "4")])
5476
5477(define_insn "isel_unsigned"
5478 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5479 (if_then_else:SI
5480 (match_operator 1 "comparison_operator"
5481 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5482 (const_int 0)])
5483 (match_operand:SI 2 "gpc_reg_operand" "b")
5484 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5485 "TARGET_ISEL"
5486 "*
5487{ return output_isel (operands); }"
5488 [(set_attr "length" "4")])
5489
94d7001a 5490(define_expand "movsfcc"
0ad91047 5491 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 5492 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5493 (match_operand:SF 2 "gpc_reg_operand" "")
5494 (match_operand:SF 3 "gpc_reg_operand" "")))]
a3170dc6 5495 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5496 "
5497{
50a0b056
GK		 5498 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5499 DONE;
94d7001a 5500 else
50a0b056 5501 FAIL;
94d7001a 5502}")
d56d506a 5503
50a0b056 5504(define_insn "*fselsfsf4"
8e871c05
RK		 5505 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5506 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5507 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5508 (match_operand:SF 2 "gpc_reg_operand" "f")
5509 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5510 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5511 "fsel %0,%1,%2,%3"
5512 [(set_attr "type" "fp")])
2f607b94 5513
50a0b056 5514(define_insn "*fseldfsf4"
94d7001a
RK		 5515 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5516 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 5517 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5518 (match_operand:SF 2 "gpc_reg_operand" "f")
5519 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5520 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5521 "fsel %0,%1,%2,%3"
5522 [(set_attr "type" "fp")])
d56d506a 5523
7a2f7870
AH		 5524(define_expand "negdf2"
5525 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5526 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5527 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5528 "")
5529
99176a91 5530(define_insn "*negdf2_fpr"
cd2b37d9
RK		 5531 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5532 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5533 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5534 "fneg %0,%1"
5535 [(set_attr "type" "fp")])
5536
7a2f7870
AH		 5537(define_expand "absdf2"
5538 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5539 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5540 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5541 "")
5542
99176a91 5543(define_insn "*absdf2_fpr"
cd2b37d9
RK		 5544 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5545 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5546 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5547 "fabs %0,%1"
5548 [(set_attr "type" "fp")])
5549
99176a91 5550(define_insn "*nabsdf2_fpr"
cd2b37d9
RK		 5551 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5552 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
a3170dc6 5553 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5554 "fnabs %0,%1"
5555 [(set_attr "type" "fp")])
5556
7a2f7870
AH		 5557(define_expand "adddf3"
5558 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5559 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5560 (match_operand:DF 2 "gpc_reg_operand" "")))]
5561 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5562 "")
5563
99176a91 5564(define_insn "*adddf3_fpr"
cd2b37d9
RK		 5565 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5566 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5567 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5568 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5569 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 5570 [(set_attr "type" "fp")])
5571
7a2f7870
AH		 5572(define_expand "subdf3"
5573 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5574 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5575 (match_operand:DF 2 "gpc_reg_operand" "")))]
5576 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5577 "")
5578
99176a91 5579(define_insn "*subdf3_fpr"
cd2b37d9
RK		 5580 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5581 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5582 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5583 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5584 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 5585 [(set_attr "type" "fp")])
5586
7a2f7870
AH		 5587(define_expand "muldf3"
5588 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5589 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5590 (match_operand:DF 2 "gpc_reg_operand" "")))]
5591 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5592 "")
5593
99176a91 5594(define_insn "*muldf3_fpr"
cd2b37d9
RK		 5595 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5596 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5597 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5598 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5599 "{fm|fmul} %0,%1,%2"
cfb557c4 5600 [(set_attr "type" "dmul")])
1fd4e8c1 5601
ef765ea9
DE		 5602(define_insn "fred"
5603 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5604 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5605 "TARGET_POPCNTB && flag_finite_math_only"
5606 "fre %0,%1"
5607 [(set_attr "type" "fp")])
5608
7a2f7870
AH		 5609(define_expand "divdf3"
5610 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5611 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5612 (match_operand:DF 2 "gpc_reg_operand" "")))]
5613 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
ef765ea9
DE		 5614{
5615 if (swdiv && !optimize_size && TARGET_POPCNTB
5616 && flag_finite_math_only && !flag_trapping_math)
5617 {
5618 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5619 DONE;
5620 }
5621})
7a2f7870 5622
99176a91 5623(define_insn "*divdf3_fpr"
cd2b37d9
RK		 5624 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5625 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5626 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5627 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5628 "{fd|fdiv} %0,%1,%2"
cfb557c4 5629 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 5630
5631(define_insn ""
cd2b37d9
RK		 5632 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5633 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5634 (match_operand:DF 2 "gpc_reg_operand" "f"))
5635 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5636 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5637 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 5638 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5639
5640(define_insn ""
cd2b37d9
RK		 5641 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5642 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5643 (match_operand:DF 2 "gpc_reg_operand" "f"))
5644 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5645 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5646 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 5647 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5648
5649(define_insn ""
cd2b37d9
RK		 5650 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5651 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5652 (match_operand:DF 2 "gpc_reg_operand" "f"))
5653 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5654 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5655 && HONOR_SIGNED_ZEROS (DFmode)"
5656 "{fnma|fnmadd} %0,%1,%2,%3"
5657 [(set_attr "type" "dmul")])
5658
5659(define_insn ""
5660 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5661 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5662 (match_operand:DF 2 "gpc_reg_operand" "f"))
5663 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5664 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5665 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5666 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 5667 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5668
5669(define_insn ""
cd2b37d9
RK		 5670 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5671 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5672 (match_operand:DF 2 "gpc_reg_operand" "f"))
5673 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5674 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5675 && HONOR_SIGNED_ZEROS (DFmode)"
5676 "{fnms|fnmsub} %0,%1,%2,%3"
5677 [(set_attr "type" "dmul")])
5678
5679(define_insn ""
5680 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5681 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5682 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5683 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
6ae08853 5684 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5685 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5686 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 5687 [(set_attr "type" "dmul")])
ca7f5001
RK		 5688
5689(define_insn "sqrtdf2"
5690 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5691 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5692 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5693 "fsqrt %0,%1"
5694 [(set_attr "type" "dsqrt")])
b77dfefc 5695
50a0b056 5696;; The conditional move instructions allow us to perform max and min
6ae08853 5697;; operations even when
b77dfefc 5698
7ae4d8d4 5699(define_expand "smaxdf3"
8e871c05 5700 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5701 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5702 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5703 (match_dup 1)
5704 (match_dup 2)))]
89e73849 5705 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5706 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 5707
7ae4d8d4 5708(define_expand "smindf3"
50a0b056
GK		 5709 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5710 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5711 (match_operand:DF 2 "gpc_reg_operand" ""))
5712 (match_dup 2)
5713 (match_dup 1)))]
89e73849 5714 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5715 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 5716
8e871c05
RK		 5717(define_split
5718 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5719 (match_operator:DF 3 "min_max_operator"
5720 [(match_operand:DF 1 "gpc_reg_operand" "")
5721 (match_operand:DF 2 "gpc_reg_operand" "")]))]
89e73849 5722 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5723 [(const_int 0)]
5724 "
6ae08853 5725{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5726 operands[1], operands[2]);
5727 DONE;
5728}")
b77dfefc 5729
94d7001a 5730(define_expand "movdfcc"
0ad91047 5731 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 5732 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5733 (match_operand:DF 2 "gpc_reg_operand" "")
5734 (match_operand:DF 3 "gpc_reg_operand" "")))]
a3170dc6 5735 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5736 "
5737{
50a0b056
GK		 5738 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5739 DONE;
94d7001a 5740 else
50a0b056 5741 FAIL;
94d7001a 5742}")
d56d506a 5743
50a0b056 5744(define_insn "*fseldfdf4"
8e871c05
RK		 5745 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5746 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 5747 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5748 (match_operand:DF 2 "gpc_reg_operand" "f")
5749 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5750 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5751 "fsel %0,%1,%2,%3"
5752 [(set_attr "type" "fp")])
d56d506a 5753
50a0b056 5754(define_insn "*fselsfdf4"
94d7001a
RK		 5755 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5756 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5757 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5758 (match_operand:DF 2 "gpc_reg_operand" "f")
5759 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5760 "TARGET_PPC_GFXOPT"
5761 "fsel %0,%1,%2,%3"
5762 [(set_attr "type" "fp")])
1fd4e8c1 5763\f
d095928f
AH		 5764;; Conversions to and from floating-point.
5765
5766(define_expand "fixuns_truncsfsi2"
5767 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5768 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5769 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5770 "")
5771
5772(define_expand "fix_truncsfsi2"
5773 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5774 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5775 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5776 "")
5777
9ebbca7d
GK		 5778; For each of these conversions, there is a define_expand, a define_insn
5779; with a '#' template, and a define_split (with C code). The idea is
5780; to allow constant folding with the template of the define_insn,
5781; then to have the insns split later (between sched1 and final).
5782
1fd4e8c1 5783(define_expand "floatsidf2"
802a0058
MM		 5784 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5785 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5786 (use (match_dup 2))
5787 (use (match_dup 3))
208c89ce 5788 (clobber (match_dup 4))
a7df97e6 5789 (clobber (match_dup 5))
9ebbca7d 5790 (clobber (match_dup 6))])]
17caeff2 5791 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5792 "
5793{
99176a91
AH		 5794 if (TARGET_E500_DOUBLE)
5795 {
5796 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5797 DONE;
5798 }
44cd321e
PS		 5799 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5800 {
5801 rtx t1 = gen_reg_rtx (DImode);
5802 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5803 DONE;
5804 }
05d49501
AM		 5805 if (TARGET_POWERPC64)
5806 {
5807 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5808 rtx t1 = gen_reg_rtx (DImode);
5809 rtx t2 = gen_reg_rtx (DImode);
5810 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5811 DONE;
5812 }
5813
802a0058 5814 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5815 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5816 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5817 operands[5] = gen_reg_rtx (DFmode);
5818 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5819}")
5820
230215f5 5821(define_insn_and_split "*floatsidf2_internal"
802a0058
MM		 5822 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5823 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5824 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5825 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
b0d6c7d8 5826 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6f9c81f5
DJ		 5827 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5828 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
a3170dc6 5829 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5830 "#"
b3a13419 5831 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5832 [(pc)]
208c89ce
MM		 5833 "
5834{
9ebbca7d 5835 rtx lowword, highword;
230215f5
GK		 5836 gcc_assert (MEM_P (operands[4]));
5837 highword = adjust_address (operands[4], SImode, 0);
5838 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d
GK		 5839 if (! WORDS_BIG_ENDIAN)
5840 {
5841 rtx tmp;
5842 tmp = highword; highword = lowword; lowword = tmp;
5843 }
5844
6ae08853 5845 emit_insn (gen_xorsi3 (operands[6], operands[1],
9ebbca7d 5846 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
230215f5
GK		 5847 emit_move_insn (lowword, operands[6]);
5848 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5849 emit_move_insn (operands[5], operands[4]);
5850 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5851 DONE;
230215f5
GK		 5852}"
5853 [(set_attr "length" "24")])
802a0058 5854
a3170dc6
AH		 5855(define_expand "floatunssisf2"
5856 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5857 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5858 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5859 "")
5860
802a0058
MM		 5861(define_expand "floatunssidf2"
5862 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5863 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5864 (use (match_dup 2))
5865 (use (match_dup 3))
a7df97e6 5866 (clobber (match_dup 4))
9ebbca7d 5867 (clobber (match_dup 5))])]
99176a91 5868 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5869 "
5870{
99176a91
AH		 5871 if (TARGET_E500_DOUBLE)
5872 {
5873 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5874 DONE;
5875 }
05d49501
AM		 5876 if (TARGET_POWERPC64)
5877 {
5878 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5879 rtx t1 = gen_reg_rtx (DImode);
5880 rtx t2 = gen_reg_rtx (DImode);
5881 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5882 t1, t2));
5883 DONE;
5884 }
5885
802a0058 5886 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5887 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 5888 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5889 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 5890}")
5891
230215f5 5892(define_insn_and_split "*floatunssidf2_internal"
802a0058
MM		 5893 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5894 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5895 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5896 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
b0d6c7d8 5897 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6f9c81f5 5898 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
a3170dc6 5899 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5900 "#"
b3a13419 5901 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5902 [(pc)]
9ebbca7d 5903 "
802a0058 5904{
9ebbca7d 5905 rtx lowword, highword;
230215f5
GK		 5906 gcc_assert (MEM_P (operands[4]));
5907 highword = adjust_address (operands[4], SImode, 0);
5908 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d 5909 if (! WORDS_BIG_ENDIAN)
f6968f59 5910 {
9ebbca7d
GK		 5911 rtx tmp;
5912 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 5913 }
802a0058 5914
230215f5
GK		 5915 emit_move_insn (lowword, operands[1]);
5916 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5917 emit_move_insn (operands[5], operands[4]);
5918 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5919 DONE;
230215f5
GK		 5920}"
5921 [(set_attr "length" "20")])
1fd4e8c1 5922
1fd4e8c1 5923(define_expand "fix_truncdfsi2"
045a8eb3 5924 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
802a0058
MM		 5925 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5926 (clobber (match_dup 2))
9ebbca7d 5927 (clobber (match_dup 3))])]
99176a91
AH		 5928 "(TARGET_POWER2 || TARGET_POWERPC)
5929 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5930 "
5931{
99176a91
AH		 5932 if (TARGET_E500_DOUBLE)
5933 {
5934 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5935 DONE;
5936 }
802a0058 5937 operands[2] = gen_reg_rtx (DImode);
44cd321e
PS		 5938 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5939 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5940 {
5941 operands[3] = gen_reg_rtx (DImode);
5942 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5943 operands[2], operands[3]));
5944 DONE;
5945 }
da4c340c
GK		 5946 if (TARGET_PPC_GFXOPT)
5947 {
5948 rtx orig_dest = operands[0];
045a8eb3 5949 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
da4c340c
GK		 5950 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5951 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5952 operands[2]));
5953 if (operands[0] != orig_dest)
5954 emit_move_insn (orig_dest, operands[0]);
5955 DONE;
5956 }
9ebbca7d 5957 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 5958}")
5959
da4c340c 5960(define_insn_and_split "*fix_truncdfsi2_internal"
802a0058
MM		 5961 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5962 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 5963 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
b0d6c7d8 5964 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
a3170dc6 5965 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5966 "#"
b3a13419 5967 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
da4c340c 5968 [(pc)]
9ebbca7d 5969 "
802a0058 5970{
9ebbca7d 5971 rtx lowword;
230215f5
GK		 5972 gcc_assert (MEM_P (operands[3]));
5973 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
802a0058 5974
9ebbca7d
GK		 5975 emit_insn (gen_fctiwz (operands[2], operands[1]));
5976 emit_move_insn (operands[3], operands[2]);
230215f5 5977 emit_move_insn (operands[0], lowword);
9ebbca7d 5978 DONE;
da4c340c
GK		 5979}"
5980 [(set_attr "length" "16")])
5981
5982(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5983 [(set (match_operand:SI 0 "memory_operand" "=Z")
5984 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5985 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5986 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5987 && TARGET_PPC_GFXOPT"
5988 "#"
5989 "&& 1"
5990 [(pc)]
5991 "
5992{
5993 emit_insn (gen_fctiwz (operands[2], operands[1]));
5994 emit_insn (gen_stfiwx (operands[0], operands[2]));
5995 DONE;
5996}"
5997 [(set_attr "length" "16")])
802a0058 5998
44cd321e
PS		 5999(define_insn_and_split "fix_truncdfsi2_mfpgpr"
6000 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6001 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6002 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6003 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6004 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6005 "#"
6006 "&& 1"
6007 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6008 (set (match_dup 3) (match_dup 2))
6009 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6010 ""
6011 [(set_attr "length" "12")])
6012
615158e2 6013; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 6014; rather than (set (subreg:SI (reg)) (fix:SI ...))
6015; because the first makes it clear that operand 0 is not live
6016; before the instruction.
6017(define_insn "fctiwz"
da4c340c 6018 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
615158e2
JJ		 6019 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6020 UNSPEC_FCTIWZ))]
a3170dc6 6021 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
a260abc9
DE		 6022 "{fcirz|fctiwz} %0,%1"
6023 [(set_attr "type" "fp")])
6024
9719f3b7
DE		 6025(define_insn "btruncdf2"
6026 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6027 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6028 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6029 "friz %0,%1"
6030 [(set_attr "type" "fp")])
6031
6032(define_insn "btruncsf2"
6033 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6034 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6035 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6036 "friz %0,%1"
9719f3b7
DE		 6037 [(set_attr "type" "fp")])
6038
6039(define_insn "ceildf2"
6040 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6041 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6042 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6043 "frip %0,%1"
6044 [(set_attr "type" "fp")])
6045
6046(define_insn "ceilsf2"
833126ad 6047 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9719f3b7
DE		 6048 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6049 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6050 "frip %0,%1"
9719f3b7
DE		 6051 [(set_attr "type" "fp")])
6052
6053(define_insn "floordf2"
6054 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6055 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6056 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6057 "frim %0,%1"
6058 [(set_attr "type" "fp")])
6059
6060(define_insn "floorsf2"
6061 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6062 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6063 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6064 "frim %0,%1"
9719f3b7
DE		 6065 [(set_attr "type" "fp")])
6066
6067(define_insn "rounddf2"
6068 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6069 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6070 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6071 "frin %0,%1"
6072 [(set_attr "type" "fp")])
6073
6074(define_insn "roundsf2"
6075 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6076 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6077 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6078 "frin %0,%1"
9719f3b7
DE		 6079 [(set_attr "type" "fp")])
6080
da4c340c
GK		 6081; An UNSPEC is used so we don't have to support SImode in FP registers.
6082(define_insn "stfiwx"
6083 [(set (match_operand:SI 0 "memory_operand" "=Z")
6084 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6085 UNSPEC_STFIWX))]
6086 "TARGET_PPC_GFXOPT"
6087 "stfiwx %1,%y0"
6088 [(set_attr "type" "fpstore")])
6089
a3170dc6
AH		 6090(define_expand "floatsisf2"
6091 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6092 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6093 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6094 "")
6095
a473029f
RK		 6096(define_insn "floatdidf2"
6097 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
61c07d3c 6098 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
a3170dc6 6099 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6100 "fcfid %0,%1"
6101 [(set_attr "type" "fp")])
6102
44cd321e
PS		 6103(define_insn_and_split "floatsidf_ppc64_mfpgpr"
6104 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6105 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6106 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6107 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6108 "#"
6109 "&& 1"
6110 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6111 (set (match_dup 0) (float:DF (match_dup 2)))]
6112 "")
6113
05d49501
AM		 6114(define_insn_and_split "floatsidf_ppc64"
6115 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6116 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
b0d6c7d8 6117 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
05d49501
AM		 6118 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6119 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
44cd321e 6120 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 6121 "#"
ecb62ae7 6122 "&& 1"
05d49501
AM		 6123 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6124 (set (match_dup 2) (match_dup 3))
6125 (set (match_dup 4) (match_dup 2))
6126 (set (match_dup 0) (float:DF (match_dup 4)))]
6127 "")
6128
6129(define_insn_and_split "floatunssidf_ppc64"
6130 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6131 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
b0d6c7d8 6132 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
05d49501
AM		 6133 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6134 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 6135 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 6136 "#"
ecb62ae7 6137 "&& 1"
05d49501
AM		 6138 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6139 (set (match_dup 2) (match_dup 3))
6140 (set (match_dup 4) (match_dup 2))
6141 (set (match_dup 0) (float:DF (match_dup 4)))]
6142 "")
6143
a473029f 6144(define_insn "fix_truncdfdi2"
61c07d3c 6145 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
a473029f 6146 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 6147 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6148 "fctidz %0,%1"
6149 [(set_attr "type" "fp")])
ea112fc4 6150
678b7733
AM		 6151(define_expand "floatdisf2"
6152 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6153 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
994cf173 6154 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6155 "
6156{
994cf173 6157 rtx val = operands[1];
678b7733
AM		 6158 if (!flag_unsafe_math_optimizations)
6159 {
6160 rtx label = gen_label_rtx ();
994cf173
AM		 6161 val = gen_reg_rtx (DImode);
6162 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
678b7733
AM		 6163 emit_label (label);
6164 }
994cf173 6165 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
678b7733
AM		 6166 DONE;
6167}")
6168
6169;; This is not IEEE compliant if rounding mode is "round to nearest".
6170;; If the DI->DF conversion is inexact, then it's possible to suffer
6171;; from double rounding.
6172(define_insn_and_split "floatdisf2_internal1"
ea112fc4 6173 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
61c07d3c 6174 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
ea112fc4 6175 (clobber (match_scratch:DF 2 "=f"))]
678b7733 6176 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
ea112fc4
DE		 6177 "#"
6178 "&& reload_completed"
6179 [(set (match_dup 2)
6180 (float:DF (match_dup 1)))
6181 (set (match_dup 0)
6182 (float_truncate:SF (match_dup 2)))]
6183 "")
678b7733
AM		 6184
6185;; Twiddles bits to avoid double rounding.
b6d08ca1 6186;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 6187;; by a bit that won't be lost at that stage, but is below the SFmode
6188;; rounding position.
6189(define_expand "floatdisf2_internal2"
994cf173
AM		 6190 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6191 (const_int 53)))
6192 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6193 (const_int 2047)))
6194 (clobber (scratch:CC))])
6195 (set (match_dup 3) (plus:DI (match_dup 3)
6196 (const_int 1)))
6197 (set (match_dup 0) (plus:DI (match_dup 0)
6198 (const_int 2047)))
6199 (set (match_dup 4) (compare:CCUNS (match_dup 3)
c22e62a6 6200 (const_int 2)))
994cf173
AM		 6201 (set (match_dup 0) (ior:DI (match_dup 0)
6202 (match_dup 1)))
6203 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6204 (const_int -2048)))
6205 (clobber (scratch:CC))])
6206 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6207 (label_ref (match_operand:DI 2 "" ""))
678b7733 6208 (pc)))
994cf173
AM		 6209 (set (match_dup 0) (match_dup 1))]
6210 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6211 "
6212{
678b7733 6213 operands[3] = gen_reg_rtx (DImode);
994cf173 6214 operands[4] = gen_reg_rtx (CCUNSmode);
678b7733 6215}")
1fd4e8c1
RK		 6216\f
6217;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 6218;; of instructions. The & constraints are to prevent the register
6219;; allocator from allocating registers that overlap with the inputs
6220;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 6221;; also allow for the output being the same as one of the inputs.
a6ec530c 6222
266eb58a 6223(define_insn "*adddi3_noppc64"
a6ec530c
RK		 6224 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6225 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6226 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 6227 "! TARGET_POWERPC64"
0f645302
MM		 6228 "*
6229{
6230 if (WORDS_BIG_ENDIAN)
6231 return (GET_CODE (operands[2])) != CONST_INT
6232 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6233 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6234 else
6235 return (GET_CODE (operands[2])) != CONST_INT
6236 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6237 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6238}"
943c15ed
DE		 6239 [(set_attr "type" "two")
6240 (set_attr "length" "8")])
1fd4e8c1 6241
266eb58a 6242(define_insn "*subdi3_noppc64"
e7e5df70
RK		 6243 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6244 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6245 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 6246 "! TARGET_POWERPC64"
5502823b
RK		 6247 "*
6248{
0f645302
MM		 6249 if (WORDS_BIG_ENDIAN)
6250 return (GET_CODE (operands[1]) != CONST_INT)
6251 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6252 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6253 else
6254 return (GET_CODE (operands[1]) != CONST_INT)
6255 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6256 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 6257}"
943c15ed
DE		 6258 [(set_attr "type" "two")
6259 (set_attr "length" "8")])
ca7f5001 6260
266eb58a 6261(define_insn "*negdi2_noppc64"
a6ec530c
RK		 6262 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6263 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 6264 "! TARGET_POWERPC64"
5502823b
RK		 6265 "*
6266{
6267 return (WORDS_BIG_ENDIAN)
6268 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6269 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6270}"
943c15ed
DE		 6271 [(set_attr "type" "two")
6272 (set_attr "length" "8")])
ca7f5001 6273
8ffd9c51
RK		 6274(define_expand "mulsidi3"
6275 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6276 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6277 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 6278 "! TARGET_POWERPC64"
8ffd9c51
RK		 6279 "
6280{
6281 if (! TARGET_POWER && ! TARGET_POWERPC)
6282 {
39403d82
DE		 6283 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6284 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6285 emit_insn (gen_mull_call ());
cf27b467 6286 if (WORDS_BIG_ENDIAN)
39403d82 6287 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 6288 else
6289 {
6290 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 6291 gen_rtx_REG (SImode, 3));
cf27b467 6292 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 6293 gen_rtx_REG (SImode, 4));
cf27b467 6294 }
8ffd9c51
RK		 6295 DONE;
6296 }
6297 else if (TARGET_POWER)
6298 {
6299 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6300 DONE;
6301 }
6302}")
deb9225a 6303
8ffd9c51 6304(define_insn "mulsidi3_mq"
cd2b37d9 6305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 6306 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 6307 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 6308 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 6309 "TARGET_POWER"
b19003d8 6310 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 6311 [(set_attr "type" "imul")
6312 (set_attr "length" "8")])
deb9225a 6313
f192bf8b 6314(define_insn "*mulsidi3_no_mq"
425c176f 6315 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 6316 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6317 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6318 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 6319 "*
6320{
6321 return (WORDS_BIG_ENDIAN)
6322 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6323 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6324}"
8ffd9c51
RK		 6325 [(set_attr "type" "imul")
6326 (set_attr "length" "8")])
deb9225a 6327
ebedb4dd
MM		 6328(define_split
6329 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6330 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6331 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6332 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6333 [(set (match_dup 3)
6334 (truncate:SI
6335 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6336 (sign_extend:DI (match_dup 2)))
6337 (const_int 32))))
6338 (set (match_dup 4)
6339 (mult:SI (match_dup 1)
6340 (match_dup 2)))]
6341 "
6342{
6343 int endian = (WORDS_BIG_ENDIAN == 0);
6344 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6345 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6346}")
6347
f192bf8b
DE		 6348(define_expand "umulsidi3"
6349 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6350 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6351 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6352 "TARGET_POWERPC && ! TARGET_POWERPC64"
6353 "
6354{
6355 if (TARGET_POWER)
6356 {
6357 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6358 DONE;
6359 }
6360}")
6361
6362(define_insn "umulsidi3_mq"
6363 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6364 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6365 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6366 (clobber (match_scratch:SI 3 "=q"))]
6367 "TARGET_POWERPC && TARGET_POWER"
6368 "*
6369{
6370 return (WORDS_BIG_ENDIAN)
6371 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6372 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6373}"
6374 [(set_attr "type" "imul")
6375 (set_attr "length" "8")])
6376
6377(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 6378 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6379 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6380 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6381 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 6382 "*
6383{
6384 return (WORDS_BIG_ENDIAN)
6385 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6386 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6387}"
6388 [(set_attr "type" "imul")
6389 (set_attr "length" "8")])
6390
ebedb4dd
MM		 6391(define_split
6392 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6393 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6394 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6395 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6396 [(set (match_dup 3)
6397 (truncate:SI
6398 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6399 (zero_extend:DI (match_dup 2)))
6400 (const_int 32))))
6401 (set (match_dup 4)
6402 (mult:SI (match_dup 1)
6403 (match_dup 2)))]
6404 "
6405{
6406 int endian = (WORDS_BIG_ENDIAN == 0);
6407 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6408 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6409}")
6410
8ffd9c51
RK		 6411(define_expand "smulsi3_highpart"
6412 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6413 (truncate:SI
6414 (lshiftrt:DI (mult:DI (sign_extend:DI
e42ac3de 6415 (match_operand:SI 1 "gpc_reg_operand" ""))
8ffd9c51 6416 (sign_extend:DI
e42ac3de 6417 (match_operand:SI 2 "gpc_reg_operand" "")))
8ffd9c51
RK		 6418 (const_int 32))))]
6419 ""
6420 "
6421{
6422 if (! TARGET_POWER && ! TARGET_POWERPC)
6423 {
39403d82
DE		 6424 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6425 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6426 emit_insn (gen_mulh_call ());
39403d82 6427 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 6428 DONE;
6429 }
6430 else if (TARGET_POWER)
6431 {
6432 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6433 DONE;
6434 }
6435}")
deb9225a 6436
8ffd9c51
RK		 6437(define_insn "smulsi3_highpart_mq"
6438 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6439 (truncate:SI
fada905b
MM		 6440 (lshiftrt:DI (mult:DI (sign_extend:DI
6441 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6442 (sign_extend:DI
6443 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 6444 (const_int 32))))
6445 (clobber (match_scratch:SI 3 "=q"))]
6446 "TARGET_POWER"
6447 "mul %0,%1,%2"
6448 [(set_attr "type" "imul")])
deb9225a 6449
f192bf8b 6450(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 6451 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6452 (truncate:SI
fada905b
MM		 6453 (lshiftrt:DI (mult:DI (sign_extend:DI
6454 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6455 (sign_extend:DI
6456 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 6457 (const_int 32))))]
f192bf8b 6458 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 6459 "mulhw %0,%1,%2"
6460 [(set_attr "type" "imul")])
deb9225a 6461
f192bf8b
DE		 6462(define_expand "umulsi3_highpart"
6463 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6464 (truncate:SI
6465 (lshiftrt:DI (mult:DI (zero_extend:DI
6466 (match_operand:SI 1 "gpc_reg_operand" ""))
6467 (zero_extend:DI
6468 (match_operand:SI 2 "gpc_reg_operand" "")))
6469 (const_int 32))))]
6470 "TARGET_POWERPC"
6471 "
6472{
6473 if (TARGET_POWER)
6474 {
6475 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6476 DONE;
6477 }
6478}")
6479
6480(define_insn "umulsi3_highpart_mq"
6481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6482 (truncate:SI
6483 (lshiftrt:DI (mult:DI (zero_extend:DI
6484 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6485 (zero_extend:DI
6486 (match_operand:SI 2 "gpc_reg_operand" "r")))
6487 (const_int 32))))
6488 (clobber (match_scratch:SI 3 "=q"))]
6489 "TARGET_POWERPC && TARGET_POWER"
6490 "mulhwu %0,%1,%2"
6491 [(set_attr "type" "imul")])
6492
6493(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 6494 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6495 (truncate:SI
6496 (lshiftrt:DI (mult:DI (zero_extend:DI
6497 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6498 (zero_extend:DI
6499 (match_operand:SI 2 "gpc_reg_operand" "r")))
6500 (const_int 32))))]
f192bf8b 6501 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 6502 "mulhwu %0,%1,%2"
6503 [(set_attr "type" "imul")])
6504
6505;; If operands 0 and 2 are in the same register, we have a problem. But
6506;; operands 0 and 1 (the usual case) can be in the same register. That's
6507;; why we have the strange constraints below.
6508(define_insn "ashldi3_power"
6509 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6510 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6511 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6512 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6513 "TARGET_POWER"
6514 "@
6515 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6516 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6517 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6518 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6519 [(set_attr "length" "8")])
6520
6521(define_insn "lshrdi3_power"
47ad8c61 6522 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 6523 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6524 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6525 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6526 "TARGET_POWER"
6527 "@
47ad8c61 6528 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 6529 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6530 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6531 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6532 [(set_attr "length" "8")])
6533
6534;; Shift by a variable amount is too complex to be worth open-coding. We
6535;; just handle shifts by constants.
6536(define_insn "ashrdi3_power"
7093ddee 6537 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 6538 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6539 (match_operand:SI 2 "const_int_operand" "M,i")))
6540 (clobber (match_scratch:SI 3 "=X,q"))]
6541 "TARGET_POWER"
6542 "@
6543 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6544 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
44cd321e
PS		 6545 [(set_attr "type" "shift")
6546 (set_attr "length" "8")])
4aa74a4f
FS		 6547
6548(define_insn "ashrdi3_no_power"
6549 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6550 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6551 (match_operand:SI 2 "const_int_operand" "M,i")))]
97727e85 6552 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
4aa74a4f
FS		 6553 "@
6554 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6555 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
943c15ed
DE		 6556 [(set_attr "type" "two,three")
6557 (set_attr "length" "8,12")])
683bdff7
FJ		 6558
6559(define_insn "*ashrdisi3_noppc64"
6560 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 6561 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
683bdff7
FJ		 6562 (const_int 32)) 4))]
6563 "TARGET_32BIT && !TARGET_POWERPC64"
6564 "*
6565{
6566 if (REGNO (operands[0]) == REGNO (operands[1]))
6567 return \"\";
6568 else
6569 return \"mr %0,%1\";
6570}"
6ae08853 6571 [(set_attr "length" "4")])
683bdff7 6572
266eb58a
DE		 6573\f
6574;; PowerPC64 DImode operations.
6575
ea112fc4 6576(define_insn_and_split "absdi2"
266eb58a 6577 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6578 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 6579 (clobber (match_scratch:DI 2 "=&r,&r"))]
6580 "TARGET_POWERPC64"
ea112fc4
DE		 6581 "#"
6582 "&& reload_completed"
a260abc9 6583 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6584 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 6585 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 6586 "")
6587
ea112fc4 6588(define_insn_and_split "*nabsdi2"
266eb58a 6589 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6590 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 6591 (clobber (match_scratch:DI 2 "=&r,&r"))]
6592 "TARGET_POWERPC64"
ea112fc4
DE		 6593 "#"
6594 "&& reload_completed"
a260abc9 6595 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6596 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 6597 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 6598 "")
6599
266eb58a 6600(define_insn "muldi3"
c9692532
DE		 6601 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6602 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6603 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
266eb58a 6604 "TARGET_POWERPC64"
c9692532
DE		 6605 "@
6606 mulld %0,%1,%2
6607 mulli %0,%1,%2"
6608 [(set (attr "type")
6609 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6610 (const_string "imul3")
6611 (match_operand:SI 2 "short_cint_operand" "")
6612 (const_string "imul2")]
6613 (const_string "lmul")))])
266eb58a 6614
9259f3b0
DE		 6615(define_insn "*muldi3_internal1"
6616 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6617 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6618 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6619 (const_int 0)))
6620 (clobber (match_scratch:DI 3 "=r,r"))]
6621 "TARGET_POWERPC64"
6622 "@
6623 mulld. %3,%1,%2
6624 #"
6625 [(set_attr "type" "lmul_compare")
6626 (set_attr "length" "4,8")])
6627
6628(define_split
6629 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6630 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6631 (match_operand:DI 2 "gpc_reg_operand" ""))
6632 (const_int 0)))
6633 (clobber (match_scratch:DI 3 ""))]
6634 "TARGET_POWERPC64 && reload_completed"
6635 [(set (match_dup 3)
6636 (mult:DI (match_dup 1) (match_dup 2)))
6637 (set (match_dup 0)
6638 (compare:CC (match_dup 3)
6639 (const_int 0)))]
6640 "")
6641
6642(define_insn "*muldi3_internal2"
6643 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6644 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6645 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6646 (const_int 0)))
6647 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6648 (mult:DI (match_dup 1) (match_dup 2)))]
6649 "TARGET_POWERPC64"
6650 "@
6651 mulld. %0,%1,%2
6652 #"
6653 [(set_attr "type" "lmul_compare")
6654 (set_attr "length" "4,8")])
6655
6656(define_split
6657 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6658 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6659 (match_operand:DI 2 "gpc_reg_operand" ""))
6660 (const_int 0)))
6661 (set (match_operand:DI 0 "gpc_reg_operand" "")
6662 (mult:DI (match_dup 1) (match_dup 2)))]
6663 "TARGET_POWERPC64 && reload_completed"
6664 [(set (match_dup 0)
6665 (mult:DI (match_dup 1) (match_dup 2)))
6666 (set (match_dup 3)
6667 (compare:CC (match_dup 0)
6668 (const_int 0)))]
6669 "")
6670
266eb58a
DE		 6671(define_insn "smuldi3_highpart"
6672 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6673 (truncate:DI
6674 (lshiftrt:TI (mult:TI (sign_extend:TI
6675 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6676 (sign_extend:TI
6677 (match_operand:DI 2 "gpc_reg_operand" "r")))
6678 (const_int 64))))]
6679 "TARGET_POWERPC64"
6680 "mulhd %0,%1,%2"
3cb999d8 6681 [(set_attr "type" "lmul")])
266eb58a
DE		 6682
6683(define_insn "umuldi3_highpart"
6684 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6685 (truncate:DI
6686 (lshiftrt:TI (mult:TI (zero_extend:TI
6687 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6688 (zero_extend:TI
6689 (match_operand:DI 2 "gpc_reg_operand" "r")))
6690 (const_int 64))))]
6691 "TARGET_POWERPC64"
6692 "mulhdu %0,%1,%2"
3cb999d8 6693 [(set_attr "type" "lmul")])
266eb58a 6694
266eb58a 6695(define_insn "rotldi3"
44cd321e
PS		 6696 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6697 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6698 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 6699 "TARGET_POWERPC64"
44cd321e
PS		 6700 "@
6701 rldcl %0,%1,%2,0
6702 rldicl %0,%1,%H2,0"
6703 [(set_attr "type" "var_shift_rotate,integer")])
266eb58a 6704
a260abc9 6705(define_insn "*rotldi3_internal2"
44cd321e
PS		 6706 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6707 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6708 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6709 (const_int 0)))
44cd321e 6710 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6711 "TARGET_64BIT"
9ebbca7d 6712 "@
44cd321e
PS		 6713 rldcl. %3,%1,%2,0
6714 rldicl. %3,%1,%H2,0
6715 #
9ebbca7d 6716 #"
44cd321e
PS		 6717 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6718 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6719
6720(define_split
6721 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6722 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6723 (match_operand:DI 2 "reg_or_cint_operand" ""))
6724 (const_int 0)))
6725 (clobber (match_scratch:DI 3 ""))]
6726 "TARGET_POWERPC64 && reload_completed"
6727 [(set (match_dup 3)
6728 (rotate:DI (match_dup 1) (match_dup 2)))
6729 (set (match_dup 0)
6730 (compare:CC (match_dup 3)
6731 (const_int 0)))]
6732 "")
266eb58a 6733
a260abc9 6734(define_insn "*rotldi3_internal3"
44cd321e
PS		 6735 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6736 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6737 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6738 (const_int 0)))
44cd321e 6739 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 6740 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 6741 "TARGET_64BIT"
9ebbca7d 6742 "@
44cd321e
PS		 6743 rldcl. %0,%1,%2,0
6744 rldicl. %0,%1,%H2,0
6745 #
9ebbca7d 6746 #"
44cd321e
PS		 6747 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6748 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6749
6750(define_split
6751 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6752 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6753 (match_operand:DI 2 "reg_or_cint_operand" ""))
6754 (const_int 0)))
6755 (set (match_operand:DI 0 "gpc_reg_operand" "")
6756 (rotate:DI (match_dup 1) (match_dup 2)))]
6757 "TARGET_POWERPC64 && reload_completed"
6758 [(set (match_dup 0)
6759 (rotate:DI (match_dup 1) (match_dup 2)))
6760 (set (match_dup 3)
6761 (compare:CC (match_dup 0)
6762 (const_int 0)))]
6763 "")
266eb58a 6764
a260abc9 6765(define_insn "*rotldi3_internal4"
44cd321e
PS		 6766 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6767 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6768 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6769 (match_operand:DI 3 "mask64_operand" "n,n")))]
a260abc9 6770 "TARGET_POWERPC64"
44cd321e
PS		 6771 "@
6772 rldc%B3 %0,%1,%2,%S3
6773 rldic%B3 %0,%1,%H2,%S3"
6774 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6775
6776(define_insn "*rotldi3_internal5"
44cd321e 6777 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6778 (compare:CC (and:DI
44cd321e
PS		 6779 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6780 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6781 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6782 (const_int 0)))
44cd321e 6783 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
683bdff7 6784 "TARGET_64BIT"
9ebbca7d 6785 "@
44cd321e
PS		 6786 rldc%B3. %4,%1,%2,%S3
6787 rldic%B3. %4,%1,%H2,%S3
6788 #
9ebbca7d 6789 #"
44cd321e
PS		 6790 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6791 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6792
6793(define_split
6794 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6795 (compare:CC (and:DI
6796 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6797 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6798 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6799 (const_int 0)))
6800 (clobber (match_scratch:DI 4 ""))]
6801 "TARGET_POWERPC64 && reload_completed"
6802 [(set (match_dup 4)
6803 (and:DI (rotate:DI (match_dup 1)
6804 (match_dup 2))
6805 (match_dup 3)))
6806 (set (match_dup 0)
6807 (compare:CC (match_dup 4)
6808 (const_int 0)))]
6809 "")
a260abc9
DE		 6810
6811(define_insn "*rotldi3_internal6"
44cd321e 6812 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6813 (compare:CC (and:DI
44cd321e
PS		 6814 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6815 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6816 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6817 (const_int 0)))
44cd321e 6818 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6819 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6820 "TARGET_64BIT"
9ebbca7d 6821 "@
44cd321e
PS		 6822 rldc%B3. %0,%1,%2,%S3
6823 rldic%B3. %0,%1,%H2,%S3
6824 #
9ebbca7d 6825 #"
44cd321e
PS		 6826 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6827 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6828
6829(define_split
6830 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6831 (compare:CC (and:DI
6832 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6833 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6834 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6835 (const_int 0)))
6836 (set (match_operand:DI 0 "gpc_reg_operand" "")
6837 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6838 "TARGET_POWERPC64 && reload_completed"
6839 [(set (match_dup 0)
6840 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6841 (set (match_dup 4)
6842 (compare:CC (match_dup 0)
6843 (const_int 0)))]
6844 "")
a260abc9
DE		 6845
6846(define_insn "*rotldi3_internal7"
44cd321e 6847 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6848 (zero_extend:DI
6849 (subreg:QI
44cd321e
PS		 6850 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6851 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6852 "TARGET_POWERPC64"
44cd321e
PS		 6853 "@
6854 rldcl %0,%1,%2,56
6855 rldicl %0,%1,%H2,56"
6856 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6857
6858(define_insn "*rotldi3_internal8"
44cd321e 6859 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6860 (compare:CC (zero_extend:DI
6861 (subreg:QI
44cd321e
PS		 6862 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6863 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6864 (const_int 0)))
44cd321e 6865 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6866 "TARGET_64BIT"
9ebbca7d 6867 "@
44cd321e
PS		 6868 rldcl. %3,%1,%2,56
6869 rldicl. %3,%1,%H2,56
6870 #
9ebbca7d 6871 #"
44cd321e
PS		 6872 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6873 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6874
6875(define_split
6876 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6877 (compare:CC (zero_extend:DI
6878 (subreg:QI
6879 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6880 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6881 (const_int 0)))
6882 (clobber (match_scratch:DI 3 ""))]
6883 "TARGET_POWERPC64 && reload_completed"
6884 [(set (match_dup 3)
6885 (zero_extend:DI (subreg:QI
6886 (rotate:DI (match_dup 1)
6887 (match_dup 2)) 0)))
6888 (set (match_dup 0)
6889 (compare:CC (match_dup 3)
6890 (const_int 0)))]
6891 "")
a260abc9
DE		 6892
6893(define_insn "*rotldi3_internal9"
44cd321e 6894 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6895 (compare:CC (zero_extend:DI
6896 (subreg:QI
44cd321e
PS		 6897 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6898 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6899 (const_int 0)))
44cd321e 6900 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6901 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6902 "TARGET_64BIT"
9ebbca7d 6903 "@
44cd321e
PS		 6904 rldcl. %0,%1,%2,56
6905 rldicl. %0,%1,%H2,56
6906 #
9ebbca7d 6907 #"
44cd321e
PS		 6908 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6909 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6910
6911(define_split
6912 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6913 (compare:CC (zero_extend:DI
6914 (subreg:QI
6915 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6916 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6917 (const_int 0)))
6918 (set (match_operand:DI 0 "gpc_reg_operand" "")
6919 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6920 "TARGET_POWERPC64 && reload_completed"
6921 [(set (match_dup 0)
6922 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6923 (set (match_dup 3)
6924 (compare:CC (match_dup 0)
6925 (const_int 0)))]
6926 "")
a260abc9
DE		 6927
6928(define_insn "*rotldi3_internal10"
44cd321e 6929 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6930 (zero_extend:DI
6931 (subreg:HI
44cd321e
PS		 6932 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6933 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6934 "TARGET_POWERPC64"
44cd321e
PS		 6935 "@
6936 rldcl %0,%1,%2,48
6937 rldicl %0,%1,%H2,48"
6938 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6939
6940(define_insn "*rotldi3_internal11"
44cd321e 6941 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6942 (compare:CC (zero_extend:DI
6943 (subreg:HI
44cd321e
PS		 6944 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6945 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6946 (const_int 0)))
44cd321e 6947 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6948 "TARGET_64BIT"
9ebbca7d 6949 "@
44cd321e
PS		 6950 rldcl. %3,%1,%2,48
6951 rldicl. %3,%1,%H2,48
6952 #
9ebbca7d 6953 #"
44cd321e
PS		 6954 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6955 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6956
6957(define_split
6958 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6959 (compare:CC (zero_extend:DI
6960 (subreg:HI
6961 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6962 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6963 (const_int 0)))
6964 (clobber (match_scratch:DI 3 ""))]
6965 "TARGET_POWERPC64 && reload_completed"
6966 [(set (match_dup 3)
6967 (zero_extend:DI (subreg:HI
6968 (rotate:DI (match_dup 1)
6969 (match_dup 2)) 0)))
6970 (set (match_dup 0)
6971 (compare:CC (match_dup 3)
6972 (const_int 0)))]
6973 "")
a260abc9
DE		 6974
6975(define_insn "*rotldi3_internal12"
44cd321e 6976 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6977 (compare:CC (zero_extend:DI
6978 (subreg:HI
44cd321e
PS		 6979 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6980 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6981 (const_int 0)))
44cd321e 6982 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6983 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6984 "TARGET_64BIT"
9ebbca7d 6985 "@
44cd321e
PS		 6986 rldcl. %0,%1,%2,48
6987 rldicl. %0,%1,%H2,48
6988 #
9ebbca7d 6989 #"
44cd321e
PS		 6990 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6991 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6992
6993(define_split
6994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6995 (compare:CC (zero_extend:DI
6996 (subreg:HI
6997 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6998 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6999 (const_int 0)))
7000 (set (match_operand:DI 0 "gpc_reg_operand" "")
7001 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7002 "TARGET_POWERPC64 && reload_completed"
7003 [(set (match_dup 0)
7004 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7005 (set (match_dup 3)
7006 (compare:CC (match_dup 0)
7007 (const_int 0)))]
7008 "")
a260abc9
DE		 7009
7010(define_insn "*rotldi3_internal13"
44cd321e 7011 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 7012 (zero_extend:DI
7013 (subreg:SI
44cd321e
PS		 7014 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7015 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 7016 "TARGET_POWERPC64"
44cd321e
PS		 7017 "@
7018 rldcl %0,%1,%2,32
7019 rldicl %0,%1,%H2,32"
7020 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 7021
7022(define_insn "*rotldi3_internal14"
44cd321e 7023 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7024 (compare:CC (zero_extend:DI
7025 (subreg:SI
44cd321e
PS		 7026 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7027 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7028 (const_int 0)))
44cd321e 7029 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7030 "TARGET_64BIT"
9ebbca7d 7031 "@
44cd321e
PS		 7032 rldcl. %3,%1,%2,32
7033 rldicl. %3,%1,%H2,32
7034 #
9ebbca7d 7035 #"
44cd321e
PS		 7036 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7037 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7038
7039(define_split
7040 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7041 (compare:CC (zero_extend:DI
7042 (subreg:SI
7043 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7044 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7045 (const_int 0)))
7046 (clobber (match_scratch:DI 3 ""))]
7047 "TARGET_POWERPC64 && reload_completed"
7048 [(set (match_dup 3)
7049 (zero_extend:DI (subreg:SI
7050 (rotate:DI (match_dup 1)
7051 (match_dup 2)) 0)))
7052 (set (match_dup 0)
7053 (compare:CC (match_dup 3)
7054 (const_int 0)))]
7055 "")
a260abc9
DE		 7056
7057(define_insn "*rotldi3_internal15"
44cd321e 7058 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7059 (compare:CC (zero_extend:DI
7060 (subreg:SI
44cd321e
PS		 7061 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7062 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7063 (const_int 0)))
44cd321e 7064 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7065 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7066 "TARGET_64BIT"
9ebbca7d 7067 "@
44cd321e
PS		 7068 rldcl. %0,%1,%2,32
7069 rldicl. %0,%1,%H2,32
7070 #
9ebbca7d 7071 #"
44cd321e
PS		 7072 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7073 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7074
7075(define_split
7076 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7077 (compare:CC (zero_extend:DI
7078 (subreg:SI
7079 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7080 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7081 (const_int 0)))
7082 (set (match_operand:DI 0 "gpc_reg_operand" "")
7083 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7084 "TARGET_POWERPC64 && reload_completed"
7085 [(set (match_dup 0)
7086 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7087 (set (match_dup 3)
7088 (compare:CC (match_dup 0)
7089 (const_int 0)))]
7090 "")
a260abc9 7091
266eb58a
DE		 7092(define_expand "ashldi3"
7093 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7094 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7095 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7096 "TARGET_POWERPC64 || TARGET_POWER"
7097 "
7098{
7099 if (TARGET_POWERPC64)
7100 ;
7101 else if (TARGET_POWER)
7102 {
7103 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7104 DONE;
7105 }
7106 else
7107 FAIL;
7108}")
7109
e2c953b6 7110(define_insn "*ashldi3_internal1"
44cd321e
PS		 7111 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7112 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7113 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7114 "TARGET_POWERPC64"
44cd321e
PS		 7115 "@
7116 sld %0,%1,%2
7117 sldi %0,%1,%H2"
7118 [(set_attr "type" "var_shift_rotate,shift")])
6ae08853 7119
e2c953b6 7120(define_insn "*ashldi3_internal2"
44cd321e
PS		 7121 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7122 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7123 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7124 (const_int 0)))
44cd321e 7125 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7126 "TARGET_64BIT"
9ebbca7d 7127 "@
44cd321e
PS		 7128 sld. %3,%1,%2
7129 sldi. %3,%1,%H2
7130 #
9ebbca7d 7131 #"
44cd321e
PS		 7132 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7133 (set_attr "length" "4,4,8,8")])
6ae08853 7134
9ebbca7d
GK		 7135(define_split
7136 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7137 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7138 (match_operand:SI 2 "reg_or_cint_operand" ""))
7139 (const_int 0)))
7140 (clobber (match_scratch:DI 3 ""))]
7141 "TARGET_POWERPC64 && reload_completed"
7142 [(set (match_dup 3)
7143 (ashift:DI (match_dup 1) (match_dup 2)))
7144 (set (match_dup 0)
7145 (compare:CC (match_dup 3)
7146 (const_int 0)))]
7147 "")
7148
e2c953b6 7149(define_insn "*ashldi3_internal3"
44cd321e
PS		 7150 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7151 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7152 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7153 (const_int 0)))
44cd321e 7154 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7155 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 7156 "TARGET_64BIT"
9ebbca7d 7157 "@
44cd321e
PS		 7158 sld. %0,%1,%2
7159 sldi. %0,%1,%H2
7160 #
9ebbca7d 7161 #"
44cd321e
PS		 7162 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7163 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7164
7165(define_split
7166 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7167 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7168 (match_operand:SI 2 "reg_or_cint_operand" ""))
7169 (const_int 0)))
7170 (set (match_operand:DI 0 "gpc_reg_operand" "")
7171 (ashift:DI (match_dup 1) (match_dup 2)))]
7172 "TARGET_POWERPC64 && reload_completed"
7173 [(set (match_dup 0)
7174 (ashift:DI (match_dup 1) (match_dup 2)))
7175 (set (match_dup 3)
7176 (compare:CC (match_dup 0)
7177 (const_int 0)))]
7178 "")
266eb58a 7179
e2c953b6 7180(define_insn "*ashldi3_internal4"
3cb999d8
DE		 7181 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7182 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7183 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 7184 (match_operand:DI 3 "const_int_operand" "n")))]
7185 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 7186 "rldic %0,%1,%H2,%W3")
3cb999d8 7187
e2c953b6 7188(define_insn "ashldi3_internal5"
9ebbca7d 7189 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 7190 (compare:CC
9ebbca7d
GK		 7191 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7192 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7193 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7194 (const_int 0)))
9ebbca7d 7195 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7196 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7197 "@
e2c953b6 7198 rldic. %4,%1,%H2,%W3
9ebbca7d 7199 #"
9c6fdb46 7200 [(set_attr "type" "compare")
9ebbca7d
GK		 7201 (set_attr "length" "4,8")])
7202
7203(define_split
7204 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7205 (compare:CC
7206 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7207 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7208 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7209 (const_int 0)))
7210 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 7211 "TARGET_POWERPC64 && reload_completed
7212 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 7213 [(set (match_dup 4)
7214 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 7215 (match_dup 3)))
9ebbca7d
GK		 7216 (set (match_dup 0)
7217 (compare:CC (match_dup 4)
7218 (const_int 0)))]
7219 "")
3cb999d8 7220
e2c953b6 7221(define_insn "*ashldi3_internal6"
9ebbca7d 7222 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 7223 (compare:CC
9ebbca7d
GK		 7224 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7225 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7226 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7227 (const_int 0)))
9ebbca7d 7228 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 7229 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7230 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7231 "@
e2c953b6 7232 rldic. %0,%1,%H2,%W3
9ebbca7d 7233 #"
9c6fdb46 7234 [(set_attr "type" "compare")
9ebbca7d
GK		 7235 (set_attr "length" "4,8")])
7236
7237(define_split
7238 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7239 (compare:CC
7240 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7241 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7242 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7243 (const_int 0)))
7244 (set (match_operand:DI 0 "gpc_reg_operand" "")
7245 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 7246 "TARGET_POWERPC64 && reload_completed
7247 && includes_rldic_lshift_p (operands[2], operands[3])"
7248 [(set (match_dup 0)
7249 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7250 (match_dup 3)))
7251 (set (match_dup 4)
7252 (compare:CC (match_dup 0)
7253 (const_int 0)))]
7254 "")
7255
7256(define_insn "*ashldi3_internal7"
7257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7258 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7259 (match_operand:SI 2 "const_int_operand" "i"))
1990cd79 7260 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 7261 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7262 "rldicr %0,%1,%H2,%S3")
7263
7264(define_insn "ashldi3_internal8"
7265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7266 (compare:CC
7267 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7268 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7269 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7270 (const_int 0)))
7271 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7272 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7273 "@
7274 rldicr. %4,%1,%H2,%S3
7275 #"
9c6fdb46 7276 [(set_attr "type" "compare")
c5059423
AM		 7277 (set_attr "length" "4,8")])
7278
7279(define_split
7280 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7281 (compare:CC
7282 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7283 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7284 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7285 (const_int 0)))
7286 (clobber (match_scratch:DI 4 ""))]
7287 "TARGET_POWERPC64 && reload_completed
7288 && includes_rldicr_lshift_p (operands[2], operands[3])"
7289 [(set (match_dup 4)
7290 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7291 (match_dup 3)))
7292 (set (match_dup 0)
7293 (compare:CC (match_dup 4)
7294 (const_int 0)))]
7295 "")
7296
7297(define_insn "*ashldi3_internal9"
7298 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7299 (compare:CC
7300 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7301 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7302 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7303 (const_int 0)))
7304 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7305 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7306 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7307 "@
7308 rldicr. %0,%1,%H2,%S3
7309 #"
9c6fdb46 7310 [(set_attr "type" "compare")
c5059423
AM		 7311 (set_attr "length" "4,8")])
7312
7313(define_split
7314 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7315 (compare:CC
7316 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7317 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7318 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7319 (const_int 0)))
7320 (set (match_operand:DI 0 "gpc_reg_operand" "")
7321 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7322 "TARGET_POWERPC64 && reload_completed
7323 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 7324 [(set (match_dup 0)
e2c953b6
DE		 7325 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7326 (match_dup 3)))
9ebbca7d
GK		 7327 (set (match_dup 4)
7328 (compare:CC (match_dup 0)
7329 (const_int 0)))]
7330 "")
7331
7332(define_expand "lshrdi3"
266eb58a
DE		 7333 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7334 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7335 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7336 "TARGET_POWERPC64 || TARGET_POWER"
7337 "
7338{
7339 if (TARGET_POWERPC64)
7340 ;
7341 else if (TARGET_POWER)
7342 {
7343 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7344 DONE;
7345 }
7346 else
7347 FAIL;
7348}")
7349
e2c953b6 7350(define_insn "*lshrdi3_internal1"
44cd321e
PS		 7351 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7352 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7353 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7354 "TARGET_POWERPC64"
44cd321e
PS		 7355 "@
7356 srd %0,%1,%2
7357 srdi %0,%1,%H2"
7358 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7359
e2c953b6 7360(define_insn "*lshrdi3_internal2"
44cd321e
PS		 7361 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7362 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7363 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
29ae5b89 7364 (const_int 0)))
44cd321e 7365 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7366 "TARGET_64BIT "
9ebbca7d 7367 "@
44cd321e
PS		 7368 srd. %3,%1,%2
7369 srdi. %3,%1,%H2
7370 #
9ebbca7d 7371 #"
44cd321e
PS		 7372 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7373 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7374
7375(define_split
7376 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7377 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7378 (match_operand:SI 2 "reg_or_cint_operand" ""))
7379 (const_int 0)))
7380 (clobber (match_scratch:DI 3 ""))]
7381 "TARGET_POWERPC64 && reload_completed"
7382 [(set (match_dup 3)
7383 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7384 (set (match_dup 0)
7385 (compare:CC (match_dup 3)
7386 (const_int 0)))]
7387 "")
266eb58a 7388
e2c953b6 7389(define_insn "*lshrdi3_internal3"
44cd321e
PS		 7390 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7391 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7392 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7393 (const_int 0)))
44cd321e 7394 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 7395 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7396 "TARGET_64BIT"
9ebbca7d 7397 "@
44cd321e
PS		 7398 srd. %0,%1,%2
7399 srdi. %0,%1,%H2
7400 #
9ebbca7d 7401 #"
44cd321e
PS		 7402 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7403 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7404
7405(define_split
7406 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7407 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7408 (match_operand:SI 2 "reg_or_cint_operand" ""))
7409 (const_int 0)))
7410 (set (match_operand:DI 0 "gpc_reg_operand" "")
7411 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7412 "TARGET_POWERPC64 && reload_completed"
7413 [(set (match_dup 0)
7414 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7415 (set (match_dup 3)
7416 (compare:CC (match_dup 0)
7417 (const_int 0)))]
7418 "")
266eb58a
DE		 7419
7420(define_expand "ashrdi3"
7421 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7422 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7423 (match_operand:SI 2 "reg_or_cint_operand" "")))]
97727e85 7424 "WORDS_BIG_ENDIAN"
266eb58a
DE		 7425 "
7426{
7427 if (TARGET_POWERPC64)
7428 ;
7429 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7430 {
7431 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7432 DONE;
7433 }
97727e85
AH		 7434 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7435 && WORDS_BIG_ENDIAN)
4aa74a4f
FS		 7436 {
7437 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7438 DONE;
7439 }
266eb58a
DE		 7440 else
7441 FAIL;
7442}")
7443
e2c953b6 7444(define_insn "*ashrdi3_internal1"
44cd321e
PS		 7445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7446 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7447 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7448 "TARGET_POWERPC64"
44cd321e
PS		 7449 "@
7450 srad %0,%1,%2
7451 sradi %0,%1,%H2"
7452 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7453
e2c953b6 7454(define_insn "*ashrdi3_internal2"
44cd321e
PS		 7455 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7456 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7457 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7458 (const_int 0)))
44cd321e 7459 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7460 "TARGET_64BIT"
9ebbca7d 7461 "@
44cd321e
PS		 7462 srad. %3,%1,%2
7463 sradi. %3,%1,%H2
7464 #
9ebbca7d 7465 #"
44cd321e
PS		 7466 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7467 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7468
7469(define_split
7470 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7471 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7472 (match_operand:SI 2 "reg_or_cint_operand" ""))
7473 (const_int 0)))
7474 (clobber (match_scratch:DI 3 ""))]
7475 "TARGET_POWERPC64 && reload_completed"
7476 [(set (match_dup 3)
7477 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7478 (set (match_dup 0)
7479 (compare:CC (match_dup 3)
7480 (const_int 0)))]
7481 "")
266eb58a 7482
e2c953b6 7483(define_insn "*ashrdi3_internal3"
44cd321e
PS		 7484 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7485 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7486 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7487 (const_int 0)))
44cd321e 7488 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7489 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7490 "TARGET_64BIT"
9ebbca7d 7491 "@
44cd321e
PS		 7492 srad. %0,%1,%2
7493 sradi. %0,%1,%H2
7494 #
9ebbca7d 7495 #"
44cd321e
PS		 7496 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7497 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7498
7499(define_split
7500 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7501 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7502 (match_operand:SI 2 "reg_or_cint_operand" ""))
7503 (const_int 0)))
7504 (set (match_operand:DI 0 "gpc_reg_operand" "")
7505 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7506 "TARGET_POWERPC64 && reload_completed"
7507 [(set (match_dup 0)
7508 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7509 (set (match_dup 3)
7510 (compare:CC (match_dup 0)
7511 (const_int 0)))]
7512 "")
815cdc52 7513
29ae5b89 7514(define_insn "anddi3"
e1e2e653
NS		 7515 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7516 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7517 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7518 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6ffc8580 7519 "TARGET_POWERPC64"
266eb58a
DE		 7520 "@
7521 and %0,%1,%2
29ae5b89 7522 rldic%B2 %0,%1,0,%S2
e1e2e653 7523 rlwinm %0,%1,0,%m2,%M2
29ae5b89 7524 andi. %0,%1,%b2
0ba1b2ff
AM		 7525 andis. %0,%1,%u2
7526 #"
e1e2e653
NS		 7527 [(set_attr "type" "*,*,*,compare,compare,*")
7528 (set_attr "length" "4,4,4,4,4,8")])
0ba1b2ff
AM		 7529
7530(define_split
7531 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7532 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7533 (match_operand:DI 2 "mask64_2_operand" "")))
7534 (clobber (match_scratch:CC 3 ""))]
7535 "TARGET_POWERPC64
7536 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7537 && !mask_operand (operands[2], DImode)
7538 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7539 [(set (match_dup 0)
7540 (and:DI (rotate:DI (match_dup 1)
7541 (match_dup 4))
7542 (match_dup 5)))
7543 (set (match_dup 0)
7544 (and:DI (rotate:DI (match_dup 0)
7545 (match_dup 6))
7546 (match_dup 7)))]
0ba1b2ff
AM		 7547{
7548 build_mask64_2_operands (operands[2], &operands[4]);
e1e2e653 7549})
266eb58a 7550
a260abc9 7551(define_insn "*anddi3_internal2"
1990cd79
AM		 7552 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7553 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7554 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7555 (const_int 0)))
1990cd79
AM		 7556 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7557 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7558 "TARGET_64BIT"
266eb58a
DE		 7559 "@
7560 and. %3,%1,%2
6c873122 7561 rldic%B2. %3,%1,0,%S2
1990cd79 7562 rlwinm. %3,%1,0,%m2,%M2
6ffc8580
MM		 7563 andi. %3,%1,%b2
7564 andis. %3,%1,%u2
9ebbca7d
GK		 7565 #
7566 #
7567 #
0ba1b2ff
AM		 7568 #
7569 #
1990cd79 7570 #
9ebbca7d 7571 #"
44cd321e 7572 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7573 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d 7574
0ba1b2ff
AM		 7575(define_split
7576 [(set (match_operand:CC 0 "cc_reg_operand" "")
7577 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7578 (match_operand:DI 2 "mask64_2_operand" ""))
7579 (const_int 0)))
7580 (clobber (match_scratch:DI 3 ""))
7581 (clobber (match_scratch:CC 4 ""))]
1990cd79 7582 "TARGET_64BIT && reload_completed
0ba1b2ff 7583 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7584 && !mask_operand (operands[2], DImode)
7585 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7586 [(set (match_dup 3)
7587 (and:DI (rotate:DI (match_dup 1)
7588 (match_dup 5))
7589 (match_dup 6)))
7590 (parallel [(set (match_dup 0)
7591 (compare:CC (and:DI (rotate:DI (match_dup 3)
7592 (match_dup 7))
7593 (match_dup 8))
7594 (const_int 0)))
7595 (clobber (match_dup 3))])]
7596 "
7597{
7598 build_mask64_2_operands (operands[2], &operands[5]);
7599}")
7600
a260abc9 7601(define_insn "*anddi3_internal3"
1990cd79
AM		 7602 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7603 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7604 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7605 (const_int 0)))
1990cd79 7606 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7607 (and:DI (match_dup 1) (match_dup 2)))
1990cd79 7608 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7609 "TARGET_64BIT"
266eb58a
DE		 7610 "@
7611 and. %0,%1,%2
6c873122 7612 rldic%B2. %0,%1,0,%S2
1990cd79 7613 rlwinm. %0,%1,0,%m2,%M2
6ffc8580
MM		 7614 andi. %0,%1,%b2
7615 andis. %0,%1,%u2
9ebbca7d
GK		 7616 #
7617 #
7618 #
0ba1b2ff
AM		 7619 #
7620 #
1990cd79 7621 #
9ebbca7d 7622 #"
44cd321e 7623 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7624 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d
GK		 7625
7626(define_split
7627 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7628 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
1990cd79 7629 (match_operand:DI 2 "and64_2_operand" ""))
9ebbca7d
GK		 7630 (const_int 0)))
7631 (set (match_operand:DI 0 "gpc_reg_operand" "")
7632 (and:DI (match_dup 1) (match_dup 2)))
7633 (clobber (match_scratch:CC 4 ""))]
1990cd79 7634 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 7635 [(parallel [(set (match_dup 0)
7636 (and:DI (match_dup 1) (match_dup 2)))
7637 (clobber (match_dup 4))])
7638 (set (match_dup 3)
7639 (compare:CC (match_dup 0)
7640 (const_int 0)))]
7641 "")
266eb58a 7642
0ba1b2ff
AM		 7643(define_split
7644 [(set (match_operand:CC 3 "cc_reg_operand" "")
7645 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7646 (match_operand:DI 2 "mask64_2_operand" ""))
7647 (const_int 0)))
7648 (set (match_operand:DI 0 "gpc_reg_operand" "")
7649 (and:DI (match_dup 1) (match_dup 2)))
7650 (clobber (match_scratch:CC 4 ""))]
1990cd79 7651 "TARGET_64BIT && reload_completed
0ba1b2ff 7652 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7653 && !mask_operand (operands[2], DImode)
7654 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7655 [(set (match_dup 0)
7656 (and:DI (rotate:DI (match_dup 1)
7657 (match_dup 5))
7658 (match_dup 6)))
7659 (parallel [(set (match_dup 3)
7660 (compare:CC (and:DI (rotate:DI (match_dup 0)
7661 (match_dup 7))
7662 (match_dup 8))
7663 (const_int 0)))
7664 (set (match_dup 0)
7665 (and:DI (rotate:DI (match_dup 0)
7666 (match_dup 7))
7667 (match_dup 8)))])]
7668 "
7669{
7670 build_mask64_2_operands (operands[2], &operands[5]);
7671}")
7672
a260abc9 7673(define_expand "iordi3"
266eb58a 7674 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7675 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7676 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7677 "TARGET_POWERPC64"
266eb58a
DE		 7678 "
7679{
dfbdccdb 7680 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7681 {
dfbdccdb 7682 HOST_WIDE_INT value;
b3a13419
ILT		 7683 rtx tmp = ((!can_create_pseudo_p ()
7684 || rtx_equal_p (operands[0], operands[1]))
a260abc9 7685 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7686
dfbdccdb
GK		 7687 if (GET_CODE (operands[2]) == CONST_INT)
7688 {
7689 value = INTVAL (operands[2]);
7690 emit_insn (gen_iordi3 (tmp, operands[1],
7691 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7692 }
e2c953b6 7693 else
dfbdccdb
GK		 7694 {
7695 value = CONST_DOUBLE_LOW (operands[2]);
7696 emit_insn (gen_iordi3 (tmp, operands[1],
7697 immed_double_const (value
7698 & (~ (HOST_WIDE_INT) 0xffff),
7699 0, DImode)));
7700 }
e2c953b6 7701
9ebbca7d
GK		 7702 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7703 DONE;
7704 }
266eb58a
DE		 7705}")
7706
a260abc9
DE		 7707(define_expand "xordi3"
7708 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7709 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7710 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7711 "TARGET_POWERPC64"
7712 "
7713{
dfbdccdb 7714 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7715 {
dfbdccdb 7716 HOST_WIDE_INT value;
b3a13419
ILT		 7717 rtx tmp = ((!can_create_pseudo_p ()
7718 || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7719 ? operands[0] : gen_reg_rtx (DImode));
7720
dfbdccdb
GK		 7721 if (GET_CODE (operands[2]) == CONST_INT)
7722 {
7723 value = INTVAL (operands[2]);
7724 emit_insn (gen_xordi3 (tmp, operands[1],
7725 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7726 }
e2c953b6 7727 else
dfbdccdb
GK		 7728 {
7729 value = CONST_DOUBLE_LOW (operands[2]);
7730 emit_insn (gen_xordi3 (tmp, operands[1],
7731 immed_double_const (value
7732 & (~ (HOST_WIDE_INT) 0xffff),
7733 0, DImode)));
7734 }
e2c953b6 7735
9ebbca7d
GK		 7736 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7737 DONE;
7738 }
a260abc9
DE		 7739}")
7740
dfbdccdb 7741(define_insn "*booldi3_internal1"
266eb58a 7742 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7743 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7744 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7745 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7746 "TARGET_POWERPC64"
1fd4e8c1 7747 "@
dfbdccdb
GK		 7748 %q3 %0,%1,%2
7749 %q3i %0,%1,%b2
7750 %q3is %0,%1,%u2")
1fd4e8c1 7751
dfbdccdb 7752(define_insn "*booldi3_internal2"
9ebbca7d 7753 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7754 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7755 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7756 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7757 (const_int 0)))
9ebbca7d 7758 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7759 "TARGET_64BIT"
9ebbca7d 7760 "@
dfbdccdb 7761 %q4. %3,%1,%2
9ebbca7d
GK		 7762 #"
7763 [(set_attr "type" "compare")
7764 (set_attr "length" "4,8")])
7765
7766(define_split
7767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7768 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7769 [(match_operand:DI 1 "gpc_reg_operand" "")
7770 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7771 (const_int 0)))
9ebbca7d
GK		 7772 (clobber (match_scratch:DI 3 ""))]
7773 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7774 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7775 (set (match_dup 0)
7776 (compare:CC (match_dup 3)
7777 (const_int 0)))]
7778 "")
1fd4e8c1 7779
dfbdccdb 7780(define_insn "*booldi3_internal3"
9ebbca7d 7781 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7782 (compare:CC (match_operator:DI 4 "boolean_operator"
7783 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7784 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7785 (const_int 0)))
9ebbca7d 7786 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7787 (match_dup 4))]
683bdff7 7788 "TARGET_64BIT"
9ebbca7d 7789 "@
dfbdccdb 7790 %q4. %0,%1,%2
9ebbca7d
GK		 7791 #"
7792 [(set_attr "type" "compare")
7793 (set_attr "length" "4,8")])
7794
7795(define_split
e72247f4 7796 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7797 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7798 [(match_operand:DI 1 "gpc_reg_operand" "")
7799 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7800 (const_int 0)))
75540af0 7801 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7802 (match_dup 4))]
9ebbca7d 7803 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7804 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7805 (set (match_dup 3)
7806 (compare:CC (match_dup 0)
7807 (const_int 0)))]
7808 "")
1fd4e8c1 7809
6ae08853 7810;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7811;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7812
7813(define_split
7814 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7815 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7816 [(match_operand:DI 1 "gpc_reg_operand" "")
7817 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7818 "TARGET_POWERPC64"
dfbdccdb
GK		 7819 [(set (match_dup 0) (match_dup 4))
7820 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7821"
7822{
dfbdccdb 7823 rtx i3,i4;
6ae08853 7824
9ebbca7d
GK		 7825 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7826 {
7827 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7828 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7829 0, DImode);
dfbdccdb 7830 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7831 }
7832 else
7833 {
dfbdccdb 7834 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7835 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7836 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7837 }
1c563bed 7838 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7839 operands[1], i3);
1c563bed 7840 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7841 operands[0], i4);
1fd4e8c1
RK		 7842}")
7843
dfbdccdb 7844(define_insn "*boolcdi3_internal1"
9ebbca7d 7845 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7846 (match_operator:DI 3 "boolean_operator"
7847 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7848 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7849 "TARGET_POWERPC64"
1d328b19 7850 "%q3 %0,%2,%1")
a473029f 7851
dfbdccdb 7852(define_insn "*boolcdi3_internal2"
9ebbca7d 7853 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7854 (compare:CC (match_operator:DI 4 "boolean_operator"
7855 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7856 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7857 (const_int 0)))
9ebbca7d 7858 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7859 "TARGET_64BIT"
9ebbca7d 7860 "@
1d328b19 7861 %q4. %3,%2,%1
9ebbca7d
GK		 7862 #"
7863 [(set_attr "type" "compare")
7864 (set_attr "length" "4,8")])
7865
7866(define_split
7867 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7868 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7869 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7870 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7871 (const_int 0)))
9ebbca7d
GK		 7872 (clobber (match_scratch:DI 3 ""))]
7873 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7874 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7875 (set (match_dup 0)
7876 (compare:CC (match_dup 3)
7877 (const_int 0)))]
7878 "")
a473029f 7879
dfbdccdb 7880(define_insn "*boolcdi3_internal3"
9ebbca7d 7881 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7882 (compare:CC (match_operator:DI 4 "boolean_operator"
7883 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7884 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7885 (const_int 0)))
9ebbca7d 7886 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7887 (match_dup 4))]
683bdff7 7888 "TARGET_64BIT"
9ebbca7d 7889 "@
1d328b19 7890 %q4. %0,%2,%1
9ebbca7d
GK		 7891 #"
7892 [(set_attr "type" "compare")
7893 (set_attr "length" "4,8")])
7894
7895(define_split
e72247f4 7896 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7897 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7898 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7899 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7900 (const_int 0)))
75540af0 7901 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7902 (match_dup 4))]
9ebbca7d 7903 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7904 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7905 (set (match_dup 3)
7906 (compare:CC (match_dup 0)
7907 (const_int 0)))]
7908 "")
266eb58a 7909
dfbdccdb 7910(define_insn "*boolccdi3_internal1"
a473029f 7911 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7912 (match_operator:DI 3 "boolean_operator"
7913 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7914 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 7915 "TARGET_POWERPC64"
dfbdccdb 7916 "%q3 %0,%1,%2")
a473029f 7917
dfbdccdb 7918(define_insn "*boolccdi3_internal2"
9ebbca7d 7919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7920 (compare:CC (match_operator:DI 4 "boolean_operator"
7921 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7922 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7923 (const_int 0)))
9ebbca7d 7924 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7925 "TARGET_64BIT"
9ebbca7d 7926 "@
dfbdccdb 7927 %q4. %3,%1,%2
9ebbca7d
GK		 7928 #"
7929 [(set_attr "type" "compare")
7930 (set_attr "length" "4,8")])
7931
7932(define_split
7933 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7934 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7935 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7936 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7937 (const_int 0)))
9ebbca7d
GK		 7938 (clobber (match_scratch:DI 3 ""))]
7939 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7940 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7941 (set (match_dup 0)
7942 (compare:CC (match_dup 3)
7943 (const_int 0)))]
7944 "")
266eb58a 7945
dfbdccdb 7946(define_insn "*boolccdi3_internal3"
9ebbca7d 7947 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7948 (compare:CC (match_operator:DI 4 "boolean_operator"
7949 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7950 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7951 (const_int 0)))
9ebbca7d 7952 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7953 (match_dup 4))]
683bdff7 7954 "TARGET_64BIT"
9ebbca7d 7955 "@
dfbdccdb 7956 %q4. %0,%1,%2
9ebbca7d
GK		 7957 #"
7958 [(set_attr "type" "compare")
7959 (set_attr "length" "4,8")])
7960
7961(define_split
e72247f4 7962 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7963 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7964 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7965 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7966 (const_int 0)))
75540af0 7967 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7968 (match_dup 4))]
9ebbca7d 7969 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7970 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7971 (set (match_dup 3)
7972 (compare:CC (match_dup 0)
7973 (const_int 0)))]
7974 "")
dfbdccdb 7975\f
1fd4e8c1 7976;; Now define ways of moving data around.
4697a36c 7977
766a866c
MM		 7978;; Set up a register with a value from the GOT table
7979
7980(define_expand "movsi_got"
52d3af72 7981 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7982 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 7983 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 7984 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7985 "
7986{
38c1f2d7
MM		 7987 if (GET_CODE (operands[1]) == CONST)
7988 {
7989 rtx offset = const0_rtx;
7990 HOST_WIDE_INT value;
7991
7992 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7993 value = INTVAL (offset);
7994 if (value != 0)
7995 {
b3a13419
ILT		 7996 rtx tmp = (!can_create_pseudo_p ()
7997 ? operands[0]
7998 : gen_reg_rtx (Pmode));
38c1f2d7
MM		 7999 emit_insn (gen_movsi_got (tmp, operands[1]));
8000 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8001 DONE;
8002 }
8003 }
8004
c4c40373 8005 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 8006}")
8007
84f414bc 8008(define_insn "*movsi_got_internal"
52d3af72 8009 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 8010 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8011 (match_operand:SI 2 "gpc_reg_operand" "b")]
8012 UNSPEC_MOVSI_GOT))]
f607bc57 8013 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 8014 "{l|lwz} %0,%a1@got(%2)"
8015 [(set_attr "type" "load")])
8016
b22b9b3e
JL		 8017;; Used by sched, shorten_branches and final when the GOT pseudo reg
8018;; didn't get allocated to a hard register.
6ae08853 8019(define_split
75540af0 8020 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8021 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8022 (match_operand:SI 2 "memory_operand" "")]
8023 UNSPEC_MOVSI_GOT))]
f607bc57 8024 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 8025 && flag_pic == 1
8026 && (reload_in_progress || reload_completed)"
8027 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 8028 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8029 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 8030 "")
8031
1fd4e8c1
RK		 8032;; For SI, we special-case integers that can't be loaded in one insn. We
8033;; do the load 16-bits at a time. We could do this by loading from memory,
8034;; and this is even supposed to be faster, but it is simpler not to get
8035;; integers in the TOC.
ee890fe2
SS		 8036(define_insn "movsi_low"
8037 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 8038 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 8039 (match_operand 2 "" ""))))]
8040 "TARGET_MACHO && ! TARGET_64BIT"
8041 "{l|lwz} %0,lo16(%2)(%1)"
8042 [(set_attr "type" "load")
8043 (set_attr "length" "4")])
8044
acad7ed3 8045(define_insn "*movsi_internal1"
165a5bad 8046 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
a004eb82 8047 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
19d5775a
RK		 8048 "gpc_reg_operand (operands[0], SImode)
8049 || gpc_reg_operand (operands[1], SImode)"
1fd4e8c1 8050 "@
deb9225a 8051 mr %0,%1
b9442c72 8052 {cal|la} %0,%a1
ca7f5001
RK		 8053 {l%U1%X1|lwz%U1%X1} %0,%1
8054 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 8055 {lil|li} %0,%1
802a0058 8056 {liu|lis} %0,%v1
beaec479 8057 #
aee86b38 8058 {cal|la} %0,%a1
1fd4e8c1 8059 mf%1 %0
5c23c401 8060 mt%0 %1
e76e75bb 8061 mt%0 %1
a004eb82 8062 mt%0 %1
e34eaae5 8063 {cror 0,0,0|nop}"
02ca7595 8064 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 8065 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 8066
77fa0940
RK		 8067;; Split a load of a large constant into the appropriate two-insn
8068;; sequence.
8069
8070(define_split
8071 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8072 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 8073 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 8074 && (INTVAL (operands[1]) & 0xffff) != 0"
8075 [(set (match_dup 0)
8076 (match_dup 2))
8077 (set (match_dup 0)
8078 (ior:SI (match_dup 0)
8079 (match_dup 3)))]
8080 "
af8cb5c5
DE		 8081{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8082
8083 if (tem == operands[0])
8084 DONE;
8085 else
8086 FAIL;
77fa0940
RK		 8087}")
8088
4ae234b0 8089(define_insn "*mov<mode>_internal2"
bb84cb12 8090 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
4ae234b0 8091 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 8092 (const_int 0)))
4ae234b0
GK		 8093 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8094 ""
9ebbca7d 8095 "@
4ae234b0 8096 {cmpi|cmp<wd>i} %2,%0,0
9ebbca7d
GK		 8097 mr. %0,%1
8098 #"
bb84cb12
DE		 8099 [(set_attr "type" "cmp,compare,cmp")
8100 (set_attr "length" "4,4,8")])
8101
9ebbca7d
GK		 8102(define_split
8103 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
4ae234b0 8104 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9ebbca7d 8105 (const_int 0)))
4ae234b0
GK		 8106 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8107 "reload_completed"
9ebbca7d
GK		 8108 [(set (match_dup 0) (match_dup 1))
8109 (set (match_dup 2)
8110 (compare:CC (match_dup 0)
8111 (const_int 0)))]
8112 "")
bb84cb12 8113\f
e34eaae5 8114(define_insn "*movhi_internal"
fb81d7ce
RK		 8115 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8116 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8117 "gpc_reg_operand (operands[0], HImode)
8118 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 8119 "@
deb9225a 8120 mr %0,%1
1fd4e8c1
RK		 8121 lhz%U1%X1 %0,%1
8122 sth%U0%X0 %1,%0
19d5775a 8123 {lil|li} %0,%w1
1fd4e8c1 8124 mf%1 %0
e76e75bb 8125 mt%0 %1
fb81d7ce 8126 mt%0 %1
e34eaae5 8127 {cror 0,0,0|nop}"
02ca7595 8128 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1 8129
4ae234b0
GK		 8130(define_expand "mov<mode>"
8131 [(set (match_operand:INT 0 "general_operand" "")
8132 (match_operand:INT 1 "any_operand" ""))]
1fd4e8c1 8133 ""
4ae234b0 8134 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
1fd4e8c1 8135
e34eaae5 8136(define_insn "*movqi_internal"
fb81d7ce
RK		 8137 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8138 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8139 "gpc_reg_operand (operands[0], QImode)
8140 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 8141 "@
deb9225a 8142 mr %0,%1
1fd4e8c1
RK		 8143 lbz%U1%X1 %0,%1
8144 stb%U0%X0 %1,%0
19d5775a 8145 {lil|li} %0,%1
1fd4e8c1 8146 mf%1 %0
e76e75bb 8147 mt%0 %1
fb81d7ce 8148 mt%0 %1
e34eaae5 8149 {cror 0,0,0|nop}"
02ca7595 8150 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 8151\f
8152;; Here is how to move condition codes around. When we store CC data in
8153;; an integer register or memory, we store just the high-order 4 bits.
8154;; This lets us not shift in the most common case of CR0.
8155(define_expand "movcc"
8156 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8157 (match_operand:CC 1 "nonimmediate_operand" ""))]
8158 ""
8159 "")
8160
a65c591c 8161(define_insn "*movcc_internal1"
4eb585a4
DE		 8162 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8163 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
1fd4e8c1
RK		 8164 "register_operand (operands[0], CCmode)
8165 || register_operand (operands[1], CCmode)"
8166 "@
8167 mcrf %0,%1
8168 mtcrf 128,%1
ca7f5001 8169 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
4eb585a4 8170 crxor %0,%0,%0
2c4a9cff
DE		 8171 mfcr %0%Q1
8172 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 8173 mr %0,%1
4eb585a4 8174 {lil|li} %0,%1
b54cf83a 8175 mf%1 %0
b991a865
GK		 8176 mt%0 %1
8177 mt%0 %1
ca7f5001
RK		 8178 {l%U1%X1|lwz%U1%X1} %0,%1
8179 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff 8180 [(set (attr "type")
4eb585a4 8181 (cond [(eq_attr "alternative" "0,3")
2c4a9cff
DE		 8182 (const_string "cr_logical")
8183 (eq_attr "alternative" "1,2")
8184 (const_string "mtcr")
4eb585a4 8185 (eq_attr "alternative" "6,7,9")
2c4a9cff 8186 (const_string "integer")
2c4a9cff 8187 (eq_attr "alternative" "8")
4eb585a4
DE		 8188 (const_string "mfjmpr")
8189 (eq_attr "alternative" "10")
2c4a9cff 8190 (const_string "mtjmpr")
4eb585a4 8191 (eq_attr "alternative" "11")
2c4a9cff 8192 (const_string "load")
4eb585a4 8193 (eq_attr "alternative" "12")
2c4a9cff
DE		 8194 (const_string "store")
8195 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8196 (const_string "mfcrf")
8197 ]
8198 (const_string "mfcr")))
4eb585a4 8199 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
1fd4e8c1 8200\f
e52e05ca
MM		 8201;; For floating-point, we normally deal with the floating-point registers
8202;; unless -msoft-float is used. The sole exception is that parameter passing
8203;; can produce floating-point values in fixed-point registers. Unless the
8204;; value is a simple constant or already in memory, we deal with this by
8205;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 8206(define_expand "movsf"
8207 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8208 (match_operand:SF 1 "any_operand" ""))]
8209 ""
fb4d4348 8210 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 8211
1fd4e8c1 8212(define_split
cd2b37d9 8213 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 8214 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 8215 "reload_completed
5ae4759c
MM		 8216 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8217 || (GET_CODE (operands[0]) == SUBREG
8218 && GET_CODE (SUBREG_REG (operands[0])) == REG
8219 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 8220 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 8221 "
8222{
8223 long l;
8224 REAL_VALUE_TYPE rv;
8225
8226 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8227 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 8228
f99f88e0
DE		 8229 if (! TARGET_POWERPC64)
8230 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8231 else
8232 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 8233
2496c7bd 8234 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 8235}")
8236
c4c40373 8237(define_insn "*movsf_hardfloat"
fb3249ef 8238 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
ae6669e7 8239 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
d14a6d05 8240 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8241 || gpc_reg_operand (operands[1], SFmode))
8242 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
1fd4e8c1 8243 "@
f99f88e0
DE		 8244 mr %0,%1
8245 {l%U1%X1|lwz%U1%X1} %0,%1
8246 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 8247 fmr %0,%1
8248 lfs%U1%X1 %0,%1
c4c40373 8249 stfs%U0%X0 %1,%0
b991a865
GK		 8250 mt%0 %1
8251 mt%0 %1
8252 mf%1 %0
e0740893 8253 {cror 0,0,0|nop}
c4c40373
MM		 8254 #
8255 #"
9c6fdb46 8256 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
ae6669e7 8257 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 8258
c4c40373 8259(define_insn "*movsf_softfloat"
dd0fbae2
MK		 8260 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8261 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 8262 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8263 || gpc_reg_operand (operands[1], SFmode))
8264 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 8265 "@
8266 mr %0,%1
b991a865
GK		 8267 mt%0 %1
8268 mt%0 %1
8269 mf%1 %0
d14a6d05
MM		 8270 {l%U1%X1|lwz%U1%X1} %0,%1
8271 {st%U0%X0|stw%U0%X0} %1,%0
8272 {lil|li} %0,%1
802a0058 8273 {liu|lis} %0,%v1
aee86b38 8274 {cal|la} %0,%a1
c4c40373 8275 #
dd0fbae2
MK		 8276 #
8277 {cror 0,0,0|nop}"
9c6fdb46 8278 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
dd0fbae2 8279 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 8280
1fd4e8c1
RK		 8281\f
8282(define_expand "movdf"
8283 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8284 (match_operand:DF 1 "any_operand" ""))]
8285 ""
fb4d4348 8286 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 8287
8288(define_split
cd2b37d9 8289 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 8290 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 8291 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8292 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8293 || (GET_CODE (operands[0]) == SUBREG
8294 && GET_CODE (SUBREG_REG (operands[0])) == REG
8295 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8296 [(set (match_dup 2) (match_dup 4))
8297 (set (match_dup 3) (match_dup 1))]
8298 "
8299{
5ae4759c 8300 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 8301 HOST_WIDE_INT value = INTVAL (operands[1]);
8302
5ae4759c
MM		 8303 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8304 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 8305#if HOST_BITS_PER_WIDE_INT == 32
8306 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8307#else
8308 operands[4] = GEN_INT (value >> 32);
a65c591c 8309 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 8310#endif
c4c40373
MM		 8311}")
8312
c4c40373
MM		 8313(define_split
8314 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8315 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8316 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8317 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8318 || (GET_CODE (operands[0]) == SUBREG
8319 && GET_CODE (SUBREG_REG (operands[0])) == REG
8320 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8321 [(set (match_dup 2) (match_dup 4))
8322 (set (match_dup 3) (match_dup 5))]
8323 "
8324{
5ae4759c 8325 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 8326 long l[2];
8327 REAL_VALUE_TYPE rv;
8328
8329 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8330 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8331
5ae4759c
MM		 8332 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8333 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 8334 operands[4] = gen_int_mode (l[endian], SImode);
8335 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 8336}")
8337
efc08378
DE		 8338(define_split
8339 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8308679f 8340 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8341 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8342 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8343 || (GET_CODE (operands[0]) == SUBREG
8344 && GET_CODE (SUBREG_REG (operands[0])) == REG
8345 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 8346 [(set (match_dup 2) (match_dup 3))]
5ae4759c 8347 "
a260abc9
DE		 8348{
8349 int endian = (WORDS_BIG_ENDIAN == 0);
8350 long l[2];
8351 REAL_VALUE_TYPE rv;
4977bab6 8352#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 8353 HOST_WIDE_INT val;
4977bab6 8354#endif
a260abc9
DE		 8355
8356 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8357 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8358
8359 operands[2] = gen_lowpart (DImode, operands[0]);
8360 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 8361#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8362 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8363 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 8364
f5264b52 8365 operands[3] = gen_int_mode (val, DImode);
5b029315 8366#else
a260abc9 8367 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 8368#endif
a260abc9 8369}")
efc08378 8370
4eae5fe1 8371;; Don't have reload use general registers to load a constant. First,
1427100a 8372;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 8373;; a non-offsettable memref, but also it is less efficient than loading
8374;; the constant into an FP register, since it will probably be used there.
8375;; The "??" is a kludge until we can figure out a more reasonable way
8376;; of handling these non-offsettable values.
c4c40373 8377(define_insn "*movdf_hardfloat32"
914a7297
DE		 8378 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8379 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
a3170dc6 8380 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8381 && (gpc_reg_operand (operands[0], DFmode)
8382 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 8383 "*
8384{
8385 switch (which_alternative)
8386 {
a260abc9 8387 default:
37409796 8388 gcc_unreachable ();
e7113111
RK		 8389 case 0:
8390 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 8391 the first register operand 0 is the same as the second register
8392 of operand 1, we must copy in the opposite order. */
e7113111 8393 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8394 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 8395 else
deb9225a 8396 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 8397 case 1:
d04b6e6e
EB		 8398 if (rs6000_offsettable_memref_p (operands[1])
8399 || (GET_CODE (operands[1]) == MEM
8400 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8401 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
6fb5fa3c
DB		 8402 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8403 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
000034eb
DE		 8404 {
8405 /* If the low-address word is used in the address, we must load
8406 it last. Otherwise, load it first. Note that we cannot have
8407 auto-increment in that case since the address register is
8408 known to be dead. */
8409 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8410 operands[1], 0))
8411 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8412 else
6fb5fa3c 8413 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
000034eb 8414 }
e7113111 8415 else
000034eb
DE		 8416 {
8417 rtx addreg;
8418
000034eb
DE		 8419 addreg = find_addr_reg (XEXP (operands[1], 0));
8420 if (refers_to_regno_p (REGNO (operands[0]),
8421 REGNO (operands[0]) + 1,
8422 operands[1], 0))
8423 {
8424 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8425 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb 8426 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2284bd2b 8427 return \"{l%X1|lwz%X1} %0,%1\";
000034eb
DE		 8428 }
8429 else
8430 {
2284bd2b 8431 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
000034eb 8432 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8433 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb
DE		 8434 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8435 return \"\";
8436 }
8437 }
e7113111 8438 case 2:
d04b6e6e
EB		 8439 if (rs6000_offsettable_memref_p (operands[0])
8440 || (GET_CODE (operands[0]) == MEM
8441 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8442 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
6fb5fa3c
DB		 8443 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8444 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8445 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
000034eb
DE		 8446 else
8447 {
8448 rtx addreg;
8449
000034eb 8450 addreg = find_addr_reg (XEXP (operands[0], 0));
2284bd2b 8451 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
000034eb 8452 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8453 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
000034eb
DE		 8454 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8455 return \"\";
8456 }
e7113111 8457 case 3:
914a7297 8458 return \"fmr %0,%1\";
e7113111 8459 case 4:
914a7297 8460 return \"lfd%U1%X1 %0,%1\";
e7113111 8461 case 5:
914a7297 8462 return \"stfd%U0%X0 %1,%0\";
e7113111 8463 case 6:
c4c40373 8464 case 7:
c4c40373 8465 case 8:
914a7297 8466 return \"#\";
e7113111
RK		 8467 }
8468}"
943c15ed 8469 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
914a7297 8470 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 8471
c4c40373 8472(define_insn "*movdf_softfloat32"
1427100a
DE		 8473 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8474 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7a2f7870 8475 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
52d3af72
DE		 8476 && (gpc_reg_operand (operands[0], DFmode)
8477 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8478 "*
8479{
8480 switch (which_alternative)
8481 {
a260abc9 8482 default:
37409796 8483 gcc_unreachable ();
dc4f83ca
MM		 8484 case 0:
8485 /* We normally copy the low-numbered register first. However, if
8486 the first register operand 0 is the same as the second register of
8487 operand 1, we must copy in the opposite order. */
8488 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8489 return \"mr %L0,%L1\;mr %0,%1\";
8490 else
8491 return \"mr %0,%1\;mr %L0,%L1\";
8492 case 1:
3cb999d8
DE		 8493 /* If the low-address word is used in the address, we must load
8494 it last. Otherwise, load it first. Note that we cannot have
8495 auto-increment in that case since the address register is
8496 known to be dead. */
dc4f83ca 8497 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8498 operands[1], 0))
dc4f83ca
MM		 8499 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8500 else
6fb5fa3c 8501 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
dc4f83ca 8502 case 2:
6fb5fa3c 8503 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
dc4f83ca 8504 case 3:
c4c40373
MM		 8505 case 4:
8506 case 5:
dc4f83ca
MM		 8507 return \"#\";
8508 }
8509}"
943c15ed 8510 [(set_attr "type" "two,load,store,*,*,*")
c4c40373 8511 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8512
44cd321e
PS		 8513; ld/std require word-aligned displacements -> 'Y' constraint.
8514; List Y->r and r->Y before r->r for reload.
8515(define_insn "*movdf_hardfloat64_mfpgpr"
8516 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8517 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8518 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8519 && (gpc_reg_operand (operands[0], DFmode)
8520 || gpc_reg_operand (operands[1], DFmode))"
8521 "@
8522 std%U0%X0 %1,%0
8523 ld%U1%X1 %0,%1
8524 mr %0,%1
8525 fmr %0,%1
8526 lfd%U1%X1 %0,%1
8527 stfd%U0%X0 %1,%0
8528 mt%0 %1
8529 mf%1 %0
8530 {cror 0,0,0|nop}
8531 #
8532 #
8533 #
8534 mftgpr %0,%1
8535 mffgpr %0,%1"
8536 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8537 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8538
d2288d5d
HP		 8539; ld/std require word-aligned displacements -> 'Y' constraint.
8540; List Y->r and r->Y before r->r for reload.
c4c40373 8541(define_insn "*movdf_hardfloat64"
fb3249ef 8542 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
ae6669e7 8543 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
44cd321e 8544 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8545 && (gpc_reg_operand (operands[0], DFmode)
8546 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8547 "@
96bb8ed3 8548 std%U0%X0 %1,%0
3364872d
FJ		 8549 ld%U1%X1 %0,%1
8550 mr %0,%1
3d5570cb 8551 fmr %0,%1
f63184ac 8552 lfd%U1%X1 %0,%1
914a7297
DE		 8553 stfd%U0%X0 %1,%0
8554 mt%0 %1
8555 mf%1 %0
e0740893 8556 {cror 0,0,0|nop}
914a7297
DE		 8557 #
8558 #
8559 #"
9c6fdb46 8560 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
ae6669e7 8561 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8562
c4c40373 8563(define_insn "*movdf_softfloat64"
d2288d5d
HP		 8564 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8565 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
a3170dc6 8566 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8567 && (gpc_reg_operand (operands[0], DFmode)
8568 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca 8569 "@
d2288d5d
HP		 8570 ld%U1%X1 %0,%1
8571 std%U0%X0 %1,%0
dc4f83ca 8572 mr %0,%1
914a7297
DE		 8573 mt%0 %1
8574 mf%1 %0
c4c40373
MM		 8575 #
8576 #
e2d0915c 8577 #
e0740893 8578 {cror 0,0,0|nop}"
9c6fdb46 8579 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
e2d0915c 8580 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 8581\f
06f4e019
DE		 8582(define_expand "movtf"
8583 [(set (match_operand:TF 0 "general_operand" "")
8584 (match_operand:TF 1 "any_operand" ""))]
8521c414 8585 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8586 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8587
a9baceb1
GK		 8588; It's important to list the o->f and f->o moves before f->f because
8589; otherwise reload, given m->f, will try to pick f->f and reload it,
409f61cd 8590; which doesn't make progress. Likewise r->Y must be before r->r.
a9baceb1 8591(define_insn_and_split "*movtf_internal"
409f61cd
AM		 8592 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8593 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
602ea4d3 8594 "!TARGET_IEEEQUAD
39e63627 8595 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8596 && (gpc_reg_operand (operands[0], TFmode)
8597 || gpc_reg_operand (operands[1], TFmode))"
a9baceb1 8598 "#"
ecb62ae7 8599 "&& reload_completed"
a9baceb1
GK		 8600 [(pc)]
8601{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
112ccb83 8602 [(set_attr "length" "8,8,8,20,20,16")])
06f4e019 8603
8521c414 8604(define_insn_and_split "*movtf_softfloat"
17caeff2 8605 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8521c414
JM		 8606 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8607 "!TARGET_IEEEQUAD
8608 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8609 && (gpc_reg_operand (operands[0], TFmode)
8610 || gpc_reg_operand (operands[1], TFmode))"
8611 "#"
8612 "&& reload_completed"
8613 [(pc)]
8614{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8615 [(set_attr "length" "20,20,16")])
8616
ecb62ae7 8617(define_expand "extenddftf2"
17caeff2
JM		 8618 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8619 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8620 "!TARGET_IEEEQUAD
8621 && TARGET_HARD_FLOAT
8622 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8623 && TARGET_LONG_DOUBLE_128"
8624{
8625 if (TARGET_E500_DOUBLE)
8626 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8627 else
8628 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8629 DONE;
8630})
8631
8632(define_expand "extenddftf2_fprs"
ecb62ae7
GK		 8633 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8634 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8635 (use (match_dup 2))])]
602ea4d3 8636 "!TARGET_IEEEQUAD
39e63627 8637 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8638{
ecb62ae7 8639 operands[2] = CONST0_RTX (DFmode);
aa9cf005
DE		 8640 /* Generate GOT reference early for SVR4 PIC. */
8641 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8642 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
ecb62ae7 8643})
06f4e019 8644
ecb62ae7
GK		 8645(define_insn_and_split "*extenddftf2_internal"
8646 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8647 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
97c54d9a 8648 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
602ea4d3 8649 "!TARGET_IEEEQUAD
39e63627 8650 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8651 "#"
8652 "&& reload_completed"
8653 [(pc)]
06f4e019 8654{
ecb62ae7
GK		 8655 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8656 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8657 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8658 operands[1]);
8659 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8660 operands[2]);
8661 DONE;
6ae08853 8662})
ecb62ae7
GK		 8663
8664(define_expand "extendsftf2"
8665 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8666 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
602ea4d3 8667 "!TARGET_IEEEQUAD
17caeff2
JM		 8668 && TARGET_HARD_FLOAT
8669 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8670 && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8671{
8672 rtx tmp = gen_reg_rtx (DFmode);
8673 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8674 emit_insn (gen_extenddftf2 (operands[0], tmp));
8675 DONE;
8676})
06f4e019 8677
8cb320b8 8678(define_expand "trunctfdf2"
589b3fda
DE		 8679 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8680 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8681 "!TARGET_IEEEQUAD
17caeff2
JM		 8682 && TARGET_HARD_FLOAT
8683 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8684 && TARGET_LONG_DOUBLE_128"
589b3fda 8685 "")
8cb320b8
DE		 8686
8687(define_insn_and_split "trunctfdf2_internal1"
8688 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8689 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
602ea4d3 8690 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8cb320b8
DE		 8691 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8692 "@
8693 #
8694 fmr %0,%1"
8695 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8696 [(const_int 0)]
8697{
8698 emit_note (NOTE_INSN_DELETED);
8699 DONE;
8700}
8701 [(set_attr "type" "fp")])
8702
8703(define_insn "trunctfdf2_internal2"
8704 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8705 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8706 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8cb320b8 8707 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8708 "fadd %0,%1,%L1"
8cb320b8 8709 [(set_attr "type" "fp")])
06f4e019 8710
17caeff2
JM		 8711(define_expand "trunctfsf2"
8712 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8713 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8714 "!TARGET_IEEEQUAD
8715 && TARGET_HARD_FLOAT
8716 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8717 && TARGET_LONG_DOUBLE_128"
8718{
8719 if (TARGET_E500_DOUBLE)
8720 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8721 else
8722 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8723 DONE;
8724})
8725
8726(define_insn_and_split "trunctfsf2_fprs"
06f4e019 8727 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 8728 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8729 (clobber (match_scratch:DF 2 "=f"))]
602ea4d3 8730 "!TARGET_IEEEQUAD
39e63627 8731 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8732 "#"
ea112fc4 8733 "&& reload_completed"
06f4e019
DE		 8734 [(set (match_dup 2)
8735 (float_truncate:DF (match_dup 1)))
8736 (set (match_dup 0)
8737 (float_truncate:SF (match_dup 2)))]
ea112fc4 8738 "")
06f4e019 8739
0c90aa3c 8740(define_expand "floatsitf2"
d29b7f64
DE		 8741 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8742 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
602ea4d3 8743 "!TARGET_IEEEQUAD
17caeff2
JM		 8744 && TARGET_HARD_FLOAT
8745 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8746 && TARGET_LONG_DOUBLE_128"
0c90aa3c
GK		 8747{
8748 rtx tmp = gen_reg_rtx (DFmode);
8749 expand_float (tmp, operands[1], false);
8750 emit_insn (gen_extenddftf2 (operands[0], tmp));
8751 DONE;
8752})
06f4e019 8753
ecb62ae7
GK		 8754; fadd, but rounding towards zero.
8755; This is probably not the optimal code sequence.
8756(define_insn "fix_trunc_helper"
8757 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8758 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8759 UNSPEC_FIX_TRUNC_TF))
8760 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8761 "TARGET_HARD_FLOAT && TARGET_FPRS"
8762 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8763 [(set_attr "type" "fp")
8764 (set_attr "length" "20")])
8765
0c90aa3c 8766(define_expand "fix_trunctfsi2"
17caeff2
JM		 8767 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8768 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8769 "!TARGET_IEEEQUAD
8770 && (TARGET_POWER2 || TARGET_POWERPC)
8771 && TARGET_HARD_FLOAT
8772 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8773 && TARGET_LONG_DOUBLE_128"
8774{
8775 if (TARGET_E500_DOUBLE)
8776 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8777 else
8778 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8779 DONE;
8780})
8781
8782(define_expand "fix_trunctfsi2_fprs"
ecb62ae7
GK		 8783 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8784 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8785 (clobber (match_dup 2))
8786 (clobber (match_dup 3))
8787 (clobber (match_dup 4))
8788 (clobber (match_dup 5))])]
602ea4d3 8789 "!TARGET_IEEEQUAD
ecb62ae7
GK		 8790 && (TARGET_POWER2 || TARGET_POWERPC)
8791 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8792{
8793 operands[2] = gen_reg_rtx (DFmode);
8794 operands[3] = gen_reg_rtx (DFmode);
8795 operands[4] = gen_reg_rtx (DImode);
8796 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8797})
8798
8799(define_insn_and_split "*fix_trunctfsi2_internal"
61c07d3c 8800 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
ecb62ae7
GK		 8801 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8802 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8803 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8804 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
b0d6c7d8 8805 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
602ea4d3 8806 "!TARGET_IEEEQUAD
39e63627 8807 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 8808 "#"
b3a13419 8809 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
ecb62ae7 8810 [(pc)]
0c90aa3c 8811{
ecb62ae7
GK		 8812 rtx lowword;
8813 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8814
230215f5
GK		 8815 gcc_assert (MEM_P (operands[5]));
8816 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
ecb62ae7
GK		 8817
8818 emit_insn (gen_fctiwz (operands[4], operands[2]));
8819 emit_move_insn (operands[5], operands[4]);
230215f5 8820 emit_move_insn (operands[0], lowword);
0c90aa3c
GK		 8821 DONE;
8822})
06f4e019 8823
17caeff2
JM		 8824(define_expand "negtf2"
8825 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8826 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8827 "!TARGET_IEEEQUAD
8828 && TARGET_HARD_FLOAT
8829 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8830 && TARGET_LONG_DOUBLE_128"
8831 "")
8832
8833(define_insn "negtf2_internal"
06f4e019
DE		 8834 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8835 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8836 "!TARGET_IEEEQUAD
39e63627 8837 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8838 "*
8839{
8840 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8841 return \"fneg %L0,%L1\;fneg %0,%1\";
8842 else
8843 return \"fneg %0,%1\;fneg %L0,%L1\";
8844}"
8845 [(set_attr "type" "fp")
8846 (set_attr "length" "8")])
8847
1a402dc1 8848(define_expand "abstf2"
17caeff2
JM		 8849 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8850 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8851 "!TARGET_IEEEQUAD
17caeff2
JM		 8852 && TARGET_HARD_FLOAT
8853 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8854 && TARGET_LONG_DOUBLE_128"
1a402dc1 8855 "
06f4e019 8856{
1a402dc1 8857 rtx label = gen_label_rtx ();
17caeff2
JM		 8858 if (TARGET_E500_DOUBLE)
8859 {
8860 if (flag_unsafe_math_optimizations)
8861 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8862 else
8863 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8864 }
8865 else
8866 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
1a402dc1
AM		 8867 emit_label (label);
8868 DONE;
8869}")
06f4e019 8870
1a402dc1 8871(define_expand "abstf2_internal"
e42ac3de
RS		 8872 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8873 (match_operand:TF 1 "gpc_reg_operand" ""))
1a402dc1
AM		 8874 (set (match_dup 3) (match_dup 5))
8875 (set (match_dup 5) (abs:DF (match_dup 5)))
8876 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8877 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8878 (label_ref (match_operand 2 "" ""))
8879 (pc)))
8880 (set (match_dup 6) (neg:DF (match_dup 6)))]
602ea4d3 8881 "!TARGET_IEEEQUAD
39e63627 8882 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
1a402dc1 8883 "
06f4e019 8884{
1a402dc1
AM		 8885 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8886 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8887 operands[3] = gen_reg_rtx (DFmode);
8888 operands[4] = gen_reg_rtx (CCFPmode);
8889 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8890 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8891}")
06f4e019 8892\f
1fd4e8c1
RK		 8893;; Next come the multi-word integer load and store and the load and store
8894;; multiple insns.
1fd4e8c1 8895
112ccb83
GK		 8896; List r->r after r->"o<>", otherwise reload will try to reload a
8897; non-offsettable address by using r->r which won't make progress.
acad7ed3 8898(define_insn "*movdi_internal32"
17caeff2 8899 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
112ccb83 8900 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
a260abc9 8901 "! TARGET_POWERPC64
4e74d8ec
MM		 8902 && (gpc_reg_operand (operands[0], DImode)
8903 || gpc_reg_operand (operands[1], DImode))"
112ccb83
GK		 8904 "@
8905 #
8906 #
8907 #
8908 fmr %0,%1
8909 lfd%U1%X1 %0,%1
8910 stfd%U0%X0 %1,%0
8911 #"
8912 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
4e74d8ec
MM		 8913
8914(define_split
8915 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8916 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 8917 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8918 [(set (match_dup 2) (match_dup 4))
8919 (set (match_dup 3) (match_dup 1))]
8920 "
8921{
5f59ecb7 8922 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 8923 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8924 DImode);
8925 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8926 DImode);
75d39459 8927#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 8928 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 8929#else
5f59ecb7 8930 operands[4] = GEN_INT (value >> 32);
a65c591c 8931 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 8932#endif
4e74d8ec
MM		 8933}")
8934
3a1f863f 8935(define_split
17caeff2 8936 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
3a1f863f 8937 (match_operand:DI 1 "input_operand" ""))]
6ae08853 8938 "reload_completed && !TARGET_POWERPC64
3a1f863f 8939 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 8940 [(pc)]
8941{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
3a1f863f 8942
44cd321e
PS		 8943(define_insn "*movdi_mfpgpr"
8944 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8945 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8946 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8947 && (gpc_reg_operand (operands[0], DImode)
8948 || gpc_reg_operand (operands[1], DImode))"
8949 "@
8950 mr %0,%1
8951 ld%U1%X1 %0,%1
8952 std%U0%X0 %1,%0
8953 li %0,%1
8954 lis %0,%v1
8955 #
8956 {cal|la} %0,%a1
8957 fmr %0,%1
8958 lfd%U1%X1 %0,%1
8959 stfd%U0%X0 %1,%0
8960 mf%1 %0
8961 mt%0 %1
8962 {cror 0,0,0|nop}
8963 mftgpr %0,%1
8964 mffgpr %0,%1"
8965 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8966 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8967
acad7ed3 8968(define_insn "*movdi_internal64"
343f6bbf 8969 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9615f239 8970 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
44cd321e 8971 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
4e74d8ec
MM		 8972 && (gpc_reg_operand (operands[0], DImode)
8973 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 8974 "@
3d5570cb
RK		 8975 mr %0,%1
8976 ld%U1%X1 %0,%1
96bb8ed3 8977 std%U0%X0 %1,%0
3d5570cb 8978 li %0,%1
802a0058 8979 lis %0,%v1
e6ca2c17 8980 #
aee86b38 8981 {cal|la} %0,%a1
3d5570cb
RK		 8982 fmr %0,%1
8983 lfd%U1%X1 %0,%1
8984 stfd%U0%X0 %1,%0
8985 mf%1 %0
08075ead 8986 mt%0 %1
e34eaae5 8987 {cror 0,0,0|nop}"
02ca7595 8988 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 8989 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8990
5f59ecb7 8991;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 8992(define_insn ""
8993 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8994 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 8995 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8996 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 8997 && num_insns_constant (operands[1], DImode) == 1"
8998 "*
8999{
9000 return ((unsigned HOST_WIDE_INT)
9001 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9002 ? \"li %0,%1\" : \"lis %0,%v1\";
9003}")
9004
a260abc9
DE		 9005;; Generate all one-bits and clear left or right.
9006;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9007(define_split
9008 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1990cd79 9009 (match_operand:DI 1 "mask64_operand" ""))]
a260abc9
DE		 9010 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9011 [(set (match_dup 0) (const_int -1))
e6ca2c17 9012 (set (match_dup 0)
a260abc9
DE		 9013 (and:DI (rotate:DI (match_dup 0)
9014 (const_int 0))
9015 (match_dup 1)))]
9016 "")
9017
9018;; Split a load of a large constant into the appropriate five-instruction
9019;; sequence. Handle anything in a constant number of insns.
9020;; When non-easy constants can go in the TOC, this should use
9021;; easy_fp_constant predicate.
9022(define_split
9023 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9024 (match_operand:DI 1 "const_int_operand" ""))]
9025 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9026 [(set (match_dup 0) (match_dup 2))
9027 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 9028 "
2bfcf297
DB		 9029{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9030
9031 if (tem == operands[0])
9032 DONE;
e8d791dd 9033 else
2bfcf297 9034 FAIL;
5f59ecb7 9035}")
e6ca2c17 9036
5f59ecb7
DE		 9037(define_split
9038 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9039 (match_operand:DI 1 "const_double_operand" ""))]
9040 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9041 [(set (match_dup 0) (match_dup 2))
9042 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 9043 "
2bfcf297
DB		 9044{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9045
9046 if (tem == operands[0])
9047 DONE;
9048 else
9049 FAIL;
e6ca2c17 9050}")
acad7ed3 9051\f
1fd4e8c1
RK		 9052;; TImode is similar, except that we usually want to compute the address into
9053;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 9054;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 9055
9056;; We say that MQ is clobbered in the last alternative because the first
9057;; alternative would never get used otherwise since it would need a reload
9058;; while the 2nd alternative would not. We put memory cases first so they
9059;; are preferred. Otherwise, we'd try to reload the output instead of
9060;; giving the SCRATCH mq.
3a1f863f 9061
a260abc9 9062(define_insn "*movti_power"
7f514158
AM		 9063 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9064 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9065 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
6ae08853 9066 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 9067 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 9068 "*
9069{
9070 switch (which_alternative)
9071 {
dc4f83ca 9072 default:
37409796 9073 gcc_unreachable ();
dc4f83ca 9074
1fd4e8c1 9075 case 0:
3a1f863f
DE		 9076 if (TARGET_STRING)
9077 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 9078 case 1:
1fd4e8c1 9079 case 2:
3a1f863f 9080 return \"#\";
1fd4e8c1
RK		 9081 case 3:
9082 /* If the address is not used in the output, we can use lsi. Otherwise,
9083 fall through to generating four loads. */
e876481c
DE		 9084 if (TARGET_STRING
9085 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 9086 return \"{lsi|lswi} %0,%P1,16\";
82e41834 9087 /* ... fall through ... */
1fd4e8c1 9088 case 4:
7f514158 9089 case 5:
3a1f863f 9090 return \"#\";
1fd4e8c1
RK		 9091 }
9092}"
7f514158 9093 [(set_attr "type" "store,store,*,load,load,*")])
51b8fc2c 9094
a260abc9 9095(define_insn "*movti_string"
7f514158
AM		 9096 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9097 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
3a1f863f 9098 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 9099 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9100 "*
9101{
9102 switch (which_alternative)
9103 {
9104 default:
37409796 9105 gcc_unreachable ();
dc4f83ca 9106 case 0:
3a1f863f
DE		 9107 if (TARGET_STRING)
9108 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 9109 case 1:
cd1d3445 9110 case 2:
3a1f863f 9111 return \"#\";
cd1d3445
DE		 9112 case 3:
9113 /* If the address is not used in the output, we can use lsi. Otherwise,
9114 fall through to generating four loads. */
6ae08853 9115 if (TARGET_STRING
3a1f863f 9116 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 9117 return \"{lsi|lswi} %0,%P1,16\";
9118 /* ... fall through ... */
9119 case 4:
7f514158 9120 case 5:
3a1f863f 9121 return \"#\";
dc4f83ca
MM		 9122 }
9123}"
9c6fdb46 9124 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
dc4f83ca 9125
a260abc9 9126(define_insn "*movti_ppc64"
112ccb83
GK		 9127 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9128 (match_operand:TI 1 "input_operand" "r,r,m"))]
51b8fc2c
RK		 9129 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9130 || gpc_reg_operand (operands[1], TImode))"
112ccb83 9131 "#"
3a1f863f
DE		 9132 [(set_attr "type" "*,load,store")])
9133
7f514158
AM		 9134(define_split
9135 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9136 (match_operand:TI 1 "const_double_operand" ""))]
9137 "TARGET_POWERPC64"
9138 [(set (match_dup 2) (match_dup 4))
9139 (set (match_dup 3) (match_dup 5))]
9140 "
9141{
9142 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9143 TImode);
9144 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9145 TImode);
9146 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9147 {
9148 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9149 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9150 }
9151 else if (GET_CODE (operands[1]) == CONST_INT)
9152 {
9153 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9154 operands[5] = operands[1];
9155 }
9156 else
9157 FAIL;
9158}")
9159
3a1f863f
DE		 9160(define_split
9161 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9162 (match_operand:TI 1 "input_operand" ""))]
a9baceb1 9163 "reload_completed
3a1f863f 9164 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 9165 [(pc)]
9166{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
1fd4e8c1
RK		 9167\f
9168(define_expand "load_multiple"
2f622005
RK		 9169 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9170 (match_operand:SI 1 "" ""))
9171 (use (match_operand:SI 2 "" ""))])]
09a625f7 9172 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9173 "
9174{
9175 int regno;
9176 int count;
792760b9 9177 rtx op1;
1fd4e8c1
RK		 9178 int i;
9179
9180 /* Support only loading a constant number of fixed-point registers from
9181 memory and only bother with this if more than two; the machine
9182 doesn't support more than eight. */
9183 if (GET_CODE (operands[2]) != CONST_INT
9184 || INTVAL (operands[2]) <= 2
9185 || INTVAL (operands[2]) > 8
9186 || GET_CODE (operands[1]) != MEM
9187 || GET_CODE (operands[0]) != REG
9188 || REGNO (operands[0]) >= 32)
9189 FAIL;
9190
9191 count = INTVAL (operands[2]);
9192 regno = REGNO (operands[0]);
9193
39403d82 9194 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 9195 op1 = replace_equiv_address (operands[1],
9196 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 9197
9198 for (i = 0; i < count; i++)
9199 XVECEXP (operands[3], 0, i)
39403d82 9200 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 9201 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 9202}")
9203
9caa3eb2 9204(define_insn "*ldmsi8"
1fd4e8c1 9205 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 9206 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9207 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9208 (set (match_operand:SI 3 "gpc_reg_operand" "")
9209 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9210 (set (match_operand:SI 4 "gpc_reg_operand" "")
9211 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9212 (set (match_operand:SI 5 "gpc_reg_operand" "")
9213 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9214 (set (match_operand:SI 6 "gpc_reg_operand" "")
9215 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9216 (set (match_operand:SI 7 "gpc_reg_operand" "")
9217 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9218 (set (match_operand:SI 8 "gpc_reg_operand" "")
9219 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9220 (set (match_operand:SI 9 "gpc_reg_operand" "")
9221 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9222 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 9223 "*
9caa3eb2 9224{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9225 [(set_attr "type" "load_ux")
9caa3eb2 9226 (set_attr "length" "32")])
1fd4e8c1 9227
9caa3eb2
DE		 9228(define_insn "*ldmsi7"
9229 [(match_parallel 0 "load_multiple_operation"
9230 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9231 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9232 (set (match_operand:SI 3 "gpc_reg_operand" "")
9233 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9234 (set (match_operand:SI 4 "gpc_reg_operand" "")
9235 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9236 (set (match_operand:SI 5 "gpc_reg_operand" "")
9237 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9238 (set (match_operand:SI 6 "gpc_reg_operand" "")
9239 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9240 (set (match_operand:SI 7 "gpc_reg_operand" "")
9241 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9242 (set (match_operand:SI 8 "gpc_reg_operand" "")
9243 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9244 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9245 "*
9246{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9247 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9248 (set_attr "length" "32")])
9249
9250(define_insn "*ldmsi6"
9251 [(match_parallel 0 "load_multiple_operation"
9252 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9253 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9254 (set (match_operand:SI 3 "gpc_reg_operand" "")
9255 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9256 (set (match_operand:SI 4 "gpc_reg_operand" "")
9257 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9258 (set (match_operand:SI 5 "gpc_reg_operand" "")
9259 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9260 (set (match_operand:SI 6 "gpc_reg_operand" "")
9261 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9262 (set (match_operand:SI 7 "gpc_reg_operand" "")
9263 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9264 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9265 "*
9266{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9267 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9268 (set_attr "length" "32")])
9269
9270(define_insn "*ldmsi5"
9271 [(match_parallel 0 "load_multiple_operation"
9272 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9273 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9274 (set (match_operand:SI 3 "gpc_reg_operand" "")
9275 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9276 (set (match_operand:SI 4 "gpc_reg_operand" "")
9277 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9278 (set (match_operand:SI 5 "gpc_reg_operand" "")
9279 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9280 (set (match_operand:SI 6 "gpc_reg_operand" "")
9281 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9282 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9283 "*
9284{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9285 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9286 (set_attr "length" "32")])
9287
9288(define_insn "*ldmsi4"
9289 [(match_parallel 0 "load_multiple_operation"
9290 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9291 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9292 (set (match_operand:SI 3 "gpc_reg_operand" "")
9293 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9294 (set (match_operand:SI 4 "gpc_reg_operand" "")
9295 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9296 (set (match_operand:SI 5 "gpc_reg_operand" "")
9297 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9298 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9299 "*
9300{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9301 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9302 (set_attr "length" "32")])
9303
9304(define_insn "*ldmsi3"
9305 [(match_parallel 0 "load_multiple_operation"
9306 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9307 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9308 (set (match_operand:SI 3 "gpc_reg_operand" "")
9309 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9310 (set (match_operand:SI 4 "gpc_reg_operand" "")
9311 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9312 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9313 "*
9314{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9315 [(set_attr "type" "load_ux")
e82ee4cc 9316 (set_attr "length" "32")])
b19003d8 9317
1fd4e8c1 9318(define_expand "store_multiple"
2f622005
RK		 9319 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9320 (match_operand:SI 1 "" ""))
9321 (clobber (scratch:SI))
9322 (use (match_operand:SI 2 "" ""))])]
09a625f7 9323 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9324 "
9325{
9326 int regno;
9327 int count;
9328 rtx to;
792760b9 9329 rtx op0;
1fd4e8c1
RK		 9330 int i;
9331
9332 /* Support only storing a constant number of fixed-point registers to
9333 memory and only bother with this if more than two; the machine
9334 doesn't support more than eight. */
9335 if (GET_CODE (operands[2]) != CONST_INT
9336 || INTVAL (operands[2]) <= 2
9337 || INTVAL (operands[2]) > 8
9338 || GET_CODE (operands[0]) != MEM
9339 || GET_CODE (operands[1]) != REG
9340 || REGNO (operands[1]) >= 32)
9341 FAIL;
9342
9343 count = INTVAL (operands[2]);
9344 regno = REGNO (operands[1]);
9345
39403d82 9346 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 9347 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 9348 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 9349
9350 XVECEXP (operands[3], 0, 0)
7ef788f0 9351 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 9352 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 9353 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 9354
9355 for (i = 1; i < count; i++)
9356 XVECEXP (operands[3], 0, i + 1)
39403d82 9357 = gen_rtx_SET (VOIDmode,
7ef788f0 9358 adjust_address_nv (op0, SImode, i * 4),
c5c76735 9359 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 9360}")
9361
e46e3130 9362(define_insn "*stmsi8"
d14a6d05 9363 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 9364 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9365 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9366 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9367 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9368 (match_operand:SI 4 "gpc_reg_operand" "r"))
9369 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9370 (match_operand:SI 5 "gpc_reg_operand" "r"))
9371 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9372 (match_operand:SI 6 "gpc_reg_operand" "r"))
9373 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9374 (match_operand:SI 7 "gpc_reg_operand" "r"))
9375 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9376 (match_operand:SI 8 "gpc_reg_operand" "r"))
9377 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9378 (match_operand:SI 9 "gpc_reg_operand" "r"))
9379 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9380 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9381 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9382 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9383 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9384
9385(define_insn "*stmsi7"
9386 [(match_parallel 0 "store_multiple_operation"
9387 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9388 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9389 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9390 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9391 (match_operand:SI 4 "gpc_reg_operand" "r"))
9392 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9393 (match_operand:SI 5 "gpc_reg_operand" "r"))
9394 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9395 (match_operand:SI 6 "gpc_reg_operand" "r"))
9396 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9397 (match_operand:SI 7 "gpc_reg_operand" "r"))
9398 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9399 (match_operand:SI 8 "gpc_reg_operand" "r"))
9400 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9401 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9402 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9403 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9404 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9405
9406(define_insn "*stmsi6"
9407 [(match_parallel 0 "store_multiple_operation"
9408 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9409 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9410 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9411 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9412 (match_operand:SI 4 "gpc_reg_operand" "r"))
9413 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9414 (match_operand:SI 5 "gpc_reg_operand" "r"))
9415 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9416 (match_operand:SI 6 "gpc_reg_operand" "r"))
9417 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9418 (match_operand:SI 7 "gpc_reg_operand" "r"))
9419 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9420 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9421 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9422 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9423 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9424
9425(define_insn "*stmsi5"
9426 [(match_parallel 0 "store_multiple_operation"
9427 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9428 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9429 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9430 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9431 (match_operand:SI 4 "gpc_reg_operand" "r"))
9432 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9433 (match_operand:SI 5 "gpc_reg_operand" "r"))
9434 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9435 (match_operand:SI 6 "gpc_reg_operand" "r"))
9436 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9437 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9438 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9439 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9440 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9441
9442(define_insn "*stmsi4"
9443 [(match_parallel 0 "store_multiple_operation"
9444 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9445 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9446 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9447 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9448 (match_operand:SI 4 "gpc_reg_operand" "r"))
9449 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9450 (match_operand:SI 5 "gpc_reg_operand" "r"))
9451 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9452 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9453 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82 9454 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9455 [(set_attr "type" "store_ux")])
7e69e155 9456
e46e3130
DJ		 9457(define_insn "*stmsi3"
9458 [(match_parallel 0 "store_multiple_operation"
9459 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9460 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9461 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9462 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9463 (match_operand:SI 4 "gpc_reg_operand" "r"))
9464 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9465 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9466 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9467 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9468 [(set_attr "type" "store_ux")])
d2894ab5
DE		 9469
9470(define_insn "*stmsi8_power"
9471 [(match_parallel 0 "store_multiple_operation"
9472 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9473 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9474 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9475 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9476 (match_operand:SI 4 "gpc_reg_operand" "r"))
9477 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9478 (match_operand:SI 5 "gpc_reg_operand" "r"))
9479 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9480 (match_operand:SI 6 "gpc_reg_operand" "r"))
9481 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9482 (match_operand:SI 7 "gpc_reg_operand" "r"))
9483 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9484 (match_operand:SI 8 "gpc_reg_operand" "r"))
9485 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9486 (match_operand:SI 9 "gpc_reg_operand" "r"))
9487 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9488 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9489 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9490 "{stsi|stswi} %2,%1,%O0"
9491 [(set_attr "type" "store_ux")])
9492
9493(define_insn "*stmsi7_power"
9494 [(match_parallel 0 "store_multiple_operation"
9495 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9496 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9497 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9498 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9499 (match_operand:SI 4 "gpc_reg_operand" "r"))
9500 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9501 (match_operand:SI 5 "gpc_reg_operand" "r"))
9502 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9503 (match_operand:SI 6 "gpc_reg_operand" "r"))
9504 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9505 (match_operand:SI 7 "gpc_reg_operand" "r"))
9506 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9507 (match_operand:SI 8 "gpc_reg_operand" "r"))
9508 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9509 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9510 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9511 "{stsi|stswi} %2,%1,%O0"
9512 [(set_attr "type" "store_ux")])
9513
9514(define_insn "*stmsi6_power"
9515 [(match_parallel 0 "store_multiple_operation"
9516 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9517 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9518 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9519 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9520 (match_operand:SI 4 "gpc_reg_operand" "r"))
9521 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9522 (match_operand:SI 5 "gpc_reg_operand" "r"))
9523 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9524 (match_operand:SI 6 "gpc_reg_operand" "r"))
9525 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9526 (match_operand:SI 7 "gpc_reg_operand" "r"))
9527 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9528 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9529 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9530 "{stsi|stswi} %2,%1,%O0"
9531 [(set_attr "type" "store_ux")])
9532
9533(define_insn "*stmsi5_power"
9534 [(match_parallel 0 "store_multiple_operation"
9535 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9536 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9537 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9538 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9539 (match_operand:SI 4 "gpc_reg_operand" "r"))
9540 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9541 (match_operand:SI 5 "gpc_reg_operand" "r"))
9542 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9543 (match_operand:SI 6 "gpc_reg_operand" "r"))
9544 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9545 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9546 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9547 "{stsi|stswi} %2,%1,%O0"
9548 [(set_attr "type" "store_ux")])
9549
9550(define_insn "*stmsi4_power"
9551 [(match_parallel 0 "store_multiple_operation"
9552 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9553 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9554 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9555 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9556 (match_operand:SI 4 "gpc_reg_operand" "r"))
9557 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9558 (match_operand:SI 5 "gpc_reg_operand" "r"))
9559 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9560 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9561 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9562 "{stsi|stswi} %2,%1,%O0"
9563 [(set_attr "type" "store_ux")])
9564
9565(define_insn "*stmsi3_power"
9566 [(match_parallel 0 "store_multiple_operation"
9567 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9568 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9569 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9570 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9571 (match_operand:SI 4 "gpc_reg_operand" "r"))
9572 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9573 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9574 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9575 "{stsi|stswi} %2,%1,%O0"
9576 [(set_attr "type" "store_ux")])
7e69e155 9577\f
57e84f18 9578(define_expand "setmemsi"
fba73eb1 9579 [(parallel [(set (match_operand:BLK 0 "" "")
98843c92 9580 (match_operand 2 "const_int_operand" ""))
fba73eb1 9581 (use (match_operand:SI 1 "" ""))
57e84f18 9582 (use (match_operand:SI 3 "" ""))])]
fba73eb1
DE		 9583 ""
9584 "
9585{
57e84f18 9586 /* If value to set is not zero, use the library routine. */
a05be2e0 9587 if (operands[2] != const0_rtx)
57e84f18
AS		 9588 FAIL;
9589
fba73eb1
DE		 9590 if (expand_block_clear (operands))
9591 DONE;
9592 else
9593 FAIL;
9594}")
9595
7e69e155
MM		 9596;; String/block move insn.
9597;; Argument 0 is the destination
9598;; Argument 1 is the source
9599;; Argument 2 is the length
9600;; Argument 3 is the alignment
9601
70128ad9 9602(define_expand "movmemsi"
b6c9286a
MM		 9603 [(parallel [(set (match_operand:BLK 0 "" "")
9604 (match_operand:BLK 1 "" ""))
9605 (use (match_operand:SI 2 "" ""))
9606 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9607 ""
9608 "
9609{
9610 if (expand_block_move (operands))
9611 DONE;
9612 else
9613 FAIL;
9614}")
9615
9616;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9617;; register allocator doesn't have a clue about allocating 8 word registers.
9618;; rD/rS = r5 is preferred, efficient form.
70128ad9 9619(define_expand "movmemsi_8reg"
b6c9286a
MM		 9620 [(parallel [(set (match_operand 0 "" "")
9621 (match_operand 1 "" ""))
9622 (use (match_operand 2 "" ""))
9623 (use (match_operand 3 "" ""))
7e69e155
MM		 9624 (clobber (reg:SI 5))
9625 (clobber (reg:SI 6))
9626 (clobber (reg:SI 7))
9627 (clobber (reg:SI 8))
9628 (clobber (reg:SI 9))
9629 (clobber (reg:SI 10))
9630 (clobber (reg:SI 11))
9631 (clobber (reg:SI 12))
3c67b673 9632 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9633 "TARGET_STRING"
9634 "")
9635
9636(define_insn ""
52d3af72
DE		 9637 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9638 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9639 (use (match_operand:SI 2 "immediate_operand" "i"))
9640 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9641 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9642 (clobber (reg:SI 6))
9643 (clobber (reg:SI 7))
9644 (clobber (reg:SI 8))
9645 (clobber (reg:SI 9))
9646 (clobber (reg:SI 10))
9647 (clobber (reg:SI 11))
9648 (clobber (reg:SI 12))
3c67b673 9649 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9650 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9651 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9652 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9653 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9654 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9655 && REGNO (operands[4]) == 5"
9656 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9657 [(set_attr "type" "store_ux")
b7ff3d82 9658 (set_attr "length" "8")])
7e69e155
MM		 9659
9660(define_insn ""
4ae234b0
GK		 9661 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9662 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9663 (use (match_operand:SI 2 "immediate_operand" "i"))
9664 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9665 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9666 (clobber (reg:SI 6))
9667 (clobber (reg:SI 7))
9668 (clobber (reg:SI 8))
9669 (clobber (reg:SI 9))
9670 (clobber (reg:SI 10))
9671 (clobber (reg:SI 11))
9672 (clobber (reg:SI 12))
edd54d25 9673 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9674 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9675 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9676 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9677 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9678 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9679 && REGNO (operands[4]) == 5"
9680 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9681 [(set_attr "type" "store_ux")
b7ff3d82 9682 (set_attr "length" "8")])
7e69e155
MM		 9683
9684;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9685;; register allocator doesn't have a clue about allocating 6 word registers.
9686;; rD/rS = r5 is preferred, efficient form.
70128ad9 9687(define_expand "movmemsi_6reg"
b6c9286a
MM		 9688 [(parallel [(set (match_operand 0 "" "")
9689 (match_operand 1 "" ""))
9690 (use (match_operand 2 "" ""))
9691 (use (match_operand 3 "" ""))
f9562f27
DE		 9692 (clobber (reg:SI 5))
9693 (clobber (reg:SI 6))
7e69e155
MM		 9694 (clobber (reg:SI 7))
9695 (clobber (reg:SI 8))
9696 (clobber (reg:SI 9))
9697 (clobber (reg:SI 10))
3c67b673 9698 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9699 "TARGET_STRING"
9700 "")
9701
9702(define_insn ""
52d3af72
DE		 9703 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9704 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9705 (use (match_operand:SI 2 "immediate_operand" "i"))
9706 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9707 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9708 (clobber (reg:SI 6))
9709 (clobber (reg:SI 7))
7e69e155
MM		 9710 (clobber (reg:SI 8))
9711 (clobber (reg:SI 9))
9712 (clobber (reg:SI 10))
3c67b673 9713 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9714 "TARGET_STRING && TARGET_POWER
9715 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9716 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9717 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9718 && REGNO (operands[4]) == 5"
3c67b673 9719 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9720 [(set_attr "type" "store_ux")
b7ff3d82 9721 (set_attr "length" "8")])
7e69e155
MM		 9722
9723(define_insn ""
4ae234b0
GK		 9724 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9725 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9726 (use (match_operand:SI 2 "immediate_operand" "i"))
9727 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9728 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9729 (clobber (reg:SI 6))
9730 (clobber (reg:SI 7))
7e69e155
MM		 9731 (clobber (reg:SI 8))
9732 (clobber (reg:SI 9))
9733 (clobber (reg:SI 10))
edd54d25 9734 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9735 "TARGET_STRING && ! TARGET_POWER
7e69e155 9736 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9737 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9738 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9739 && REGNO (operands[4]) == 5"
3c67b673 9740 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9741 [(set_attr "type" "store_ux")
b7ff3d82 9742 (set_attr "length" "8")])
7e69e155 9743
f9562f27
DE		 9744;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9745;; problems with TImode.
9746;; rD/rS = r5 is preferred, efficient form.
70128ad9 9747(define_expand "movmemsi_4reg"
b6c9286a
MM		 9748 [(parallel [(set (match_operand 0 "" "")
9749 (match_operand 1 "" ""))
9750 (use (match_operand 2 "" ""))
9751 (use (match_operand 3 "" ""))
f9562f27
DE		 9752 (clobber (reg:SI 5))
9753 (clobber (reg:SI 6))
9754 (clobber (reg:SI 7))
9755 (clobber (reg:SI 8))
3c67b673 9756 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9757 "TARGET_STRING"
9758 "")
9759
9760(define_insn ""
52d3af72
DE		 9761 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9762 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9763 (use (match_operand:SI 2 "immediate_operand" "i"))
9764 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9765 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9766 (clobber (reg:SI 6))
9767 (clobber (reg:SI 7))
9768 (clobber (reg:SI 8))
3c67b673 9769 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9770 "TARGET_STRING && TARGET_POWER
9771 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9772 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9773 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9774 && REGNO (operands[4]) == 5"
3c67b673 9775 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9776 [(set_attr "type" "store_ux")
b7ff3d82 9777 (set_attr "length" "8")])
7e69e155
MM		 9778
9779(define_insn ""
4ae234b0
GK		 9780 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9781 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9782 (use (match_operand:SI 2 "immediate_operand" "i"))
9783 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9784 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9785 (clobber (reg:SI 6))
9786 (clobber (reg:SI 7))
9787 (clobber (reg:SI 8))
edd54d25 9788 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9789 "TARGET_STRING && ! TARGET_POWER
7e69e155 9790 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9791 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9792 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9793 && REGNO (operands[4]) == 5"
3c67b673 9794 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9795 [(set_attr "type" "store_ux")
b7ff3d82 9796 (set_attr "length" "8")])
7e69e155
MM		 9797
9798;; Move up to 8 bytes at a time.
70128ad9 9799(define_expand "movmemsi_2reg"
b6c9286a
MM		 9800 [(parallel [(set (match_operand 0 "" "")
9801 (match_operand 1 "" ""))
9802 (use (match_operand 2 "" ""))
9803 (use (match_operand 3 "" ""))
3c67b673
RK		 9804 (clobber (match_scratch:DI 4 ""))
9805 (clobber (match_scratch:SI 5 ""))])]
f9562f27 9806 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 9807 "")
9808
9809(define_insn ""
52d3af72
DE		 9810 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9811 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9812 (use (match_operand:SI 2 "immediate_operand" "i"))
9813 (use (match_operand:SI 3 "immediate_operand" "i"))
9814 (clobber (match_scratch:DI 4 "=&r"))
9815 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 9816 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 9817 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9818 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9819 [(set_attr "type" "store_ux")
b7ff3d82 9820 (set_attr "length" "8")])
7e69e155
MM		 9821
9822(define_insn ""
52d3af72
DE		 9823 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9824 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9825 (use (match_operand:SI 2 "immediate_operand" "i"))
9826 (use (match_operand:SI 3 "immediate_operand" "i"))
9827 (clobber (match_scratch:DI 4 "=&r"))
edd54d25 9828 (clobber (match_scratch:SI 5 "=X"))]
f9562f27 9829 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 9830 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 9831 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9832 [(set_attr "type" "store_ux")
b7ff3d82 9833 (set_attr "length" "8")])
7e69e155
MM		 9834
9835;; Move up to 4 bytes at a time.
70128ad9 9836(define_expand "movmemsi_1reg"
b6c9286a
MM		 9837 [(parallel [(set (match_operand 0 "" "")
9838 (match_operand 1 "" ""))
9839 (use (match_operand 2 "" ""))
9840 (use (match_operand 3 "" ""))
3c67b673
RK		 9841 (clobber (match_scratch:SI 4 ""))
9842 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 9843 "TARGET_STRING"
9844 "")
9845
9846(define_insn ""
52d3af72
DE		 9847 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9848 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9849 (use (match_operand:SI 2 "immediate_operand" "i"))
9850 (use (match_operand:SI 3 "immediate_operand" "i"))
9851 (clobber (match_scratch:SI 4 "=&r"))
9852 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9853 "TARGET_STRING && TARGET_POWER
9854 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9855 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9856 [(set_attr "type" "store_ux")
b7ff3d82 9857 (set_attr "length" "8")])
7e69e155
MM		 9858
9859(define_insn ""
4ae234b0
GK		 9860 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9861 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9862 (use (match_operand:SI 2 "immediate_operand" "i"))
9863 (use (match_operand:SI 3 "immediate_operand" "i"))
9864 (clobber (match_scratch:SI 4 "=&r"))
edd54d25 9865 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9866 "TARGET_STRING && ! TARGET_POWER
7e69e155 9867 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7 9868 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9869 [(set_attr "type" "store_ux")
09a625f7 9870 (set_attr "length" "8")])
1fd4e8c1 9871\f
7e69e155 9872;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 9873;; get by using pre-decrement or pre-increment, but the hardware can also
9874;; do cases where the increment is not the size of the object.
9875;;
9876;; In all these cases, we use operands 0 and 1 for the register being
9877;; incremented because those are the operands that local-alloc will
9878;; tie and these are the pair most likely to be tieable (and the ones
9879;; that will benefit the most).
9880
38c1f2d7 9881(define_insn "*movdi_update1"
51b8fc2c 9882 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 9883 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9884 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 9885 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9886 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9887 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9888 "@
9889 ldux %3,%0,%2
9890 ldu %3,%2(%0)"
b54cf83a 9891 [(set_attr "type" "load_ux,load_u")])
287f13ff 9892
2e6c9641
FJ		 9893(define_insn "movdi_<mode>_update"
9894 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9895 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c 9896 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
2e6c9641
FJ		 9897 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9898 (plus:P (match_dup 1) (match_dup 2)))]
38c1f2d7 9899 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9900 "@
9901 stdux %3,%0,%2
b7ff3d82 9902 stdu %3,%2(%0)"
b54cf83a 9903 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 9904
38c1f2d7 9905(define_insn "*movsi_update1"
cd2b37d9
RK		 9906 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9907 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9908 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9909 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9910 (plus:SI (match_dup 1) (match_dup 2)))]
f7b3ab8a 9911 "TARGET_UPDATE"
1fd4e8c1 9912 "@
ca7f5001
RK		 9913 {lux|lwzux} %3,%0,%2
9914 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 9915 [(set_attr "type" "load_ux,load_u")])
9916
9917(define_insn "*movsi_update2"
9918 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9919 (sign_extend:DI
9920 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9921 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9922 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9923 (plus:DI (match_dup 1) (match_dup 2)))]
9924 "TARGET_POWERPC64"
9925 "lwaux %3,%0,%2"
9926 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 9927
4697a36c 9928(define_insn "movsi_update"
cd2b37d9 9929 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9930 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9931 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9932 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9933 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9934 "TARGET_UPDATE"
1fd4e8c1 9935 "@
ca7f5001 9936 {stux|stwux} %3,%0,%2
b7ff3d82 9937 {stu|stwu} %3,%2(%0)"
b54cf83a 9938 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9939
b54cf83a 9940(define_insn "*movhi_update1"
cd2b37d9
RK		 9941 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9942 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9943 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9944 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9945 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9946 "TARGET_UPDATE"
1fd4e8c1 9947 "@
5f243543
RK		 9948 lhzux %3,%0,%2
9949 lhzu %3,%2(%0)"
b54cf83a 9950 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9951
38c1f2d7 9952(define_insn "*movhi_update2"
cd2b37d9 9953 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9954 (zero_extend:SI
cd2b37d9 9955 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9956 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9957 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9958 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9959 "TARGET_UPDATE"
1fd4e8c1 9960 "@
5f243543
RK		 9961 lhzux %3,%0,%2
9962 lhzu %3,%2(%0)"
b54cf83a 9963 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9964
38c1f2d7 9965(define_insn "*movhi_update3"
cd2b37d9 9966 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9967 (sign_extend:SI
cd2b37d9 9968 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9969 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9970 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9971 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9972 "TARGET_UPDATE"
1fd4e8c1 9973 "@
5f243543
RK		 9974 lhaux %3,%0,%2
9975 lhau %3,%2(%0)"
b54cf83a 9976 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 9977
38c1f2d7 9978(define_insn "*movhi_update4"
cd2b37d9 9979 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9980 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9981 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9982 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9983 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9984 "TARGET_UPDATE"
1fd4e8c1 9985 "@
5f243543 9986 sthux %3,%0,%2
b7ff3d82 9987 sthu %3,%2(%0)"
b54cf83a 9988 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9989
38c1f2d7 9990(define_insn "*movqi_update1"
cd2b37d9
RK		 9991 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9992 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9993 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9994 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9995 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9996 "TARGET_UPDATE"
1fd4e8c1 9997 "@
5f243543
RK		 9998 lbzux %3,%0,%2
9999 lbzu %3,%2(%0)"
b54cf83a 10000 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10001
38c1f2d7 10002(define_insn "*movqi_update2"
cd2b37d9 10003 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10004 (zero_extend:SI
cd2b37d9 10005 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10006 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10007 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10008 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10009 "TARGET_UPDATE"
1fd4e8c1 10010 "@
5f243543
RK		 10011 lbzux %3,%0,%2
10012 lbzu %3,%2(%0)"
b54cf83a 10013 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10014
38c1f2d7 10015(define_insn "*movqi_update3"
cd2b37d9 10016 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10017 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10018 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10019 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10020 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10021 "TARGET_UPDATE"
1fd4e8c1 10022 "@
5f243543 10023 stbux %3,%0,%2
b7ff3d82 10024 stbu %3,%2(%0)"
b54cf83a 10025 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10026
38c1f2d7 10027(define_insn "*movsf_update1"
cd2b37d9 10028 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 10029 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10030 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10031 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10032 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10033 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10034 "@
5f243543
RK		 10035 lfsux %3,%0,%2
10036 lfsu %3,%2(%0)"
b54cf83a 10037 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10038
38c1f2d7 10039(define_insn "*movsf_update2"
cd2b37d9 10040 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10041 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10042 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10043 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10044 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10045 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10046 "@
85fff2f3 10047 stfsux %3,%0,%2
b7ff3d82 10048 stfsu %3,%2(%0)"
b54cf83a 10049 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 10050
38c1f2d7
MM		 10051(define_insn "*movsf_update3"
10052 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10053 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10054 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10055 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10056 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10057 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10058 "@
10059 {lux|lwzux} %3,%0,%2
10060 {lu|lwzu} %3,%2(%0)"
b54cf83a 10061 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 10062
10063(define_insn "*movsf_update4"
10064 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10065 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10066 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10067 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10068 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10069 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10070 "@
10071 {stux|stwux} %3,%0,%2
10072 {stu|stwu} %3,%2(%0)"
b54cf83a 10073 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 10074
10075(define_insn "*movdf_update1"
cd2b37d9
RK		 10076 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10077 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10078 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10079 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10080 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10081 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10082 "@
5f243543
RK		 10083 lfdux %3,%0,%2
10084 lfdu %3,%2(%0)"
b54cf83a 10085 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10086
38c1f2d7 10087(define_insn "*movdf_update2"
cd2b37d9 10088 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10089 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10090 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10091 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10092 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10093 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10094 "@
5f243543 10095 stfdux %3,%0,%2
b7ff3d82 10096 stfdu %3,%2(%0)"
b54cf83a 10097 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 10098
10099;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10100
90f81f99 10101(define_insn "*lfq_power2"
bb8df8a6
EC		 10102 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10103 (match_operand:V2DF 1 "memory_operand" ""))]
90f81f99
AP		 10104 "TARGET_POWER2
10105 && TARGET_HARD_FLOAT && TARGET_FPRS"
bb8df8a6 10106 "lfq%U1%X1 %0,%1")
90f81f99
AP		 10107
10108(define_peephole2
10109 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4c70a4f3 10110 (match_operand:DF 1 "memory_operand" ""))
90f81f99 10111 (set (match_operand:DF 2 "gpc_reg_operand" "")
4c70a4f3
RK		 10112 (match_operand:DF 3 "memory_operand" ""))]
10113 "TARGET_POWER2
a3170dc6 10114 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10115 && registers_ok_for_quad_peep (operands[0], operands[2])
90f81f99
AP		 10116 && mems_ok_for_quad_peep (operands[1], operands[3])"
10117 [(set (match_dup 0)
bb8df8a6
EC		 10118 (match_dup 1))]
10119 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10120 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
4c70a4f3 10121
90f81f99 10122(define_insn "*stfq_power2"
bb8df8a6
EC		 10123 [(set (match_operand:V2DF 0 "memory_operand" "")
10124 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
90f81f99
AP		 10125 "TARGET_POWER2
10126 && TARGET_HARD_FLOAT && TARGET_FPRS"
10127 "stfq%U0%X0 %1,%0")
10128
10129
10130(define_peephole2
4c70a4f3 10131 [(set (match_operand:DF 0 "memory_operand" "")
90f81f99 10132 (match_operand:DF 1 "gpc_reg_operand" ""))
4c70a4f3 10133 (set (match_operand:DF 2 "memory_operand" "")
90f81f99 10134 (match_operand:DF 3 "gpc_reg_operand" ""))]
4c70a4f3 10135 "TARGET_POWER2
a3170dc6 10136 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10137 && registers_ok_for_quad_peep (operands[1], operands[3])
90f81f99
AP		 10138 && mems_ok_for_quad_peep (operands[0], operands[2])"
10139 [(set (match_dup 0)
10140 (match_dup 1))]
bb8df8a6
EC		 10141 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10142 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
2f4d9502 10143
036aadfc 10144;; After inserting conditional returns we can sometimes have
2f4d9502
NS		 10145;; unnecessary register moves. Unfortunately we cannot have a
10146;; modeless peephole here, because some single SImode sets have early
10147;; clobber outputs. Although those sets expand to multi-ppc-insn
10148;; sequences, using get_attr_length here will smash the operands
10149;; array. Neither is there an early_cobbler_p predicate.
036aadfc 10150;; Disallow subregs for E500 so we don't munge frob_di_df_2.
2f4d9502
NS		 10151(define_peephole2
10152 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10153 (match_operand:DF 1 "any_operand" ""))
10154 (set (match_operand:DF 2 "gpc_reg_operand" "")
10155 (match_dup 0))]
036aadfc
AM		 10156 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10157 && peep2_reg_dead_p (2, operands[0])"
2f4d9502
NS		 10158 [(set (match_dup 2) (match_dup 1))])
10159
10160(define_peephole2
10161 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10162 (match_operand:SF 1 "any_operand" ""))
10163 (set (match_operand:SF 2 "gpc_reg_operand" "")
10164 (match_dup 0))]
10165 "peep2_reg_dead_p (2, operands[0])"
10166 [(set (match_dup 2) (match_dup 1))])
10167
1fd4e8c1 10168\f
c4501e62
JJ		 10169;; TLS support.
10170
10171;; "b" output constraint here and on tls_ld to support tls linker optimization.
10172(define_insn "tls_gd_32"
b150f4f3
DE		 10173 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10174 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10175 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10176 UNSPEC_TLSGD))]
10177 "HAVE_AS_TLS && !TARGET_64BIT"
10178 "addi %0,%1,%2@got@tlsgd")
10179
10180(define_insn "tls_gd_64"
b150f4f3
DE		 10181 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10182 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10183 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10184 UNSPEC_TLSGD))]
10185 "HAVE_AS_TLS && TARGET_64BIT"
10186 "addi %0,%1,%2@got@tlsgd")
10187
10188(define_insn "tls_ld_32"
b150f4f3
DE		 10189 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10190 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 10191 UNSPEC_TLSLD))]
10192 "HAVE_AS_TLS && !TARGET_64BIT"
10193 "addi %0,%1,%&@got@tlsld")
10194
10195(define_insn "tls_ld_64"
b150f4f3
DE		 10196 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10197 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 10198 UNSPEC_TLSLD))]
10199 "HAVE_AS_TLS && TARGET_64BIT"
10200 "addi %0,%1,%&@got@tlsld")
10201
10202(define_insn "tls_dtprel_32"
b150f4f3
DE		 10203 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10204 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10205 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10206 UNSPEC_TLSDTPREL))]
10207 "HAVE_AS_TLS && !TARGET_64BIT"
10208 "addi %0,%1,%2@dtprel")
10209
10210(define_insn "tls_dtprel_64"
b150f4f3
DE		 10211 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10212 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10213 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10214 UNSPEC_TLSDTPREL))]
10215 "HAVE_AS_TLS && TARGET_64BIT"
10216 "addi %0,%1,%2@dtprel")
10217
10218(define_insn "tls_dtprel_ha_32"
b150f4f3
DE		 10219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10220 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10221 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10222 UNSPEC_TLSDTPRELHA))]
10223 "HAVE_AS_TLS && !TARGET_64BIT"
10224 "addis %0,%1,%2@dtprel@ha")
10225
10226(define_insn "tls_dtprel_ha_64"
b150f4f3
DE		 10227 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10228 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10229 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10230 UNSPEC_TLSDTPRELHA))]
10231 "HAVE_AS_TLS && TARGET_64BIT"
10232 "addis %0,%1,%2@dtprel@ha")
10233
10234(define_insn "tls_dtprel_lo_32"
b150f4f3
DE		 10235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10236 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10237 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10238 UNSPEC_TLSDTPRELLO))]
10239 "HAVE_AS_TLS && !TARGET_64BIT"
10240 "addi %0,%1,%2@dtprel@l")
10241
10242(define_insn "tls_dtprel_lo_64"
b150f4f3
DE		 10243 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10244 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10245 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10246 UNSPEC_TLSDTPRELLO))]
10247 "HAVE_AS_TLS && TARGET_64BIT"
10248 "addi %0,%1,%2@dtprel@l")
10249
10250(define_insn "tls_got_dtprel_32"
b150f4f3
DE		 10251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10252 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10253 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10254 UNSPEC_TLSGOTDTPREL))]
10255 "HAVE_AS_TLS && !TARGET_64BIT"
10256 "lwz %0,%2@got@dtprel(%1)")
10257
10258(define_insn "tls_got_dtprel_64"
b150f4f3
DE		 10259 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10260 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10261 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10262 UNSPEC_TLSGOTDTPREL))]
10263 "HAVE_AS_TLS && TARGET_64BIT"
10264 "ld %0,%2@got@dtprel(%1)")
10265
10266(define_insn "tls_tprel_32"
b150f4f3
DE		 10267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10268 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10269 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10270 UNSPEC_TLSTPREL))]
10271 "HAVE_AS_TLS && !TARGET_64BIT"
10272 "addi %0,%1,%2@tprel")
10273
10274(define_insn "tls_tprel_64"
b150f4f3
DE		 10275 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10276 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10277 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10278 UNSPEC_TLSTPREL))]
10279 "HAVE_AS_TLS && TARGET_64BIT"
10280 "addi %0,%1,%2@tprel")
10281
10282(define_insn "tls_tprel_ha_32"
b150f4f3
DE		 10283 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10284 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10285 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10286 UNSPEC_TLSTPRELHA))]
10287 "HAVE_AS_TLS && !TARGET_64BIT"
10288 "addis %0,%1,%2@tprel@ha")
10289
10290(define_insn "tls_tprel_ha_64"
b150f4f3
DE		 10291 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10292 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10293 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10294 UNSPEC_TLSTPRELHA))]
10295 "HAVE_AS_TLS && TARGET_64BIT"
10296 "addis %0,%1,%2@tprel@ha")
10297
10298(define_insn "tls_tprel_lo_32"
b150f4f3
DE		 10299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10300 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10301 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10302 UNSPEC_TLSTPRELLO))]
10303 "HAVE_AS_TLS && !TARGET_64BIT"
10304 "addi %0,%1,%2@tprel@l")
10305
10306(define_insn "tls_tprel_lo_64"
b150f4f3
DE		 10307 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10308 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10309 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10310 UNSPEC_TLSTPRELLO))]
10311 "HAVE_AS_TLS && TARGET_64BIT"
10312 "addi %0,%1,%2@tprel@l")
10313
c1207243 10314;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 10315;; optimization. The linker may edit the instructions emitted by a
10316;; tls_got_tprel/tls_tls pair to addis,addi.
10317(define_insn "tls_got_tprel_32"
b150f4f3
DE		 10318 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10319 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10320 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10321 UNSPEC_TLSGOTTPREL))]
10322 "HAVE_AS_TLS && !TARGET_64BIT"
10323 "lwz %0,%2@got@tprel(%1)")
10324
10325(define_insn "tls_got_tprel_64"
b150f4f3
DE		 10326 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10327 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10328 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10329 UNSPEC_TLSGOTTPREL))]
10330 "HAVE_AS_TLS && TARGET_64BIT"
10331 "ld %0,%2@got@tprel(%1)")
10332
10333(define_insn "tls_tls_32"
b150f4f3
DE		 10334 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10335 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10336 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10337 UNSPEC_TLSTLS))]
10338 "HAVE_AS_TLS && !TARGET_64BIT"
10339 "add %0,%1,%2@tls")
10340
10341(define_insn "tls_tls_64"
b150f4f3
DE		 10342 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10343 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10344 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10345 UNSPEC_TLSTLS))]
10346 "HAVE_AS_TLS && TARGET_64BIT"
10347 "add %0,%1,%2@tls")
10348\f
1fd4e8c1
RK		 10349;; Next come insns related to the calling sequence.
10350;;
10351;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 10352;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 10353
10354(define_expand "allocate_stack"
e42ac3de 10355 [(set (match_operand 0 "gpc_reg_operand" "")
a260abc9
DE		 10356 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10357 (set (reg 1)
10358 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 10359 ""
10360 "
4697a36c 10361{ rtx chain = gen_reg_rtx (Pmode);
39403d82 10362 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 10363 rtx neg_op0;
1fd4e8c1
RK		 10364
10365 emit_move_insn (chain, stack_bot);
4697a36c 10366
a157febd
GK		 10367 /* Check stack bounds if necessary. */
10368 if (current_function_limit_stack)
10369 {
10370 rtx available;
6ae08853 10371 available = expand_binop (Pmode, sub_optab,
a157febd
GK		 10372 stack_pointer_rtx, stack_limit_rtx,
10373 NULL_RTX, 1, OPTAB_WIDEN);
10374 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10375 }
10376
e9a25f70
JL		 10377 if (GET_CODE (operands[1]) != CONST_INT
10378 || INTVAL (operands[1]) < -32767
10379 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 10380 {
10381 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 10382 if (TARGET_32BIT)
e9a25f70 10383 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 10384 else
e9a25f70 10385 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 10386 }
10387 else
e9a25f70 10388 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 10389
38c1f2d7 10390 if (TARGET_UPDATE)
2e6c9641 10391 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
38c1f2d7 10392 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
4697a36c 10393
38c1f2d7
MM		 10394 else
10395 {
10396 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10397 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
39403d82 10398 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
38c1f2d7 10399 }
e9a25f70
JL		 10400
10401 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 10402 DONE;
10403}")
59257ff7
RK		 10404
10405;; These patterns say how to save and restore the stack pointer. We need not
10406;; save the stack pointer at function level since we are careful to
10407;; preserve the backchain. At block level, we have to restore the backchain
10408;; when we restore the stack pointer.
10409;;
10410;; For nonlocal gotos, we must save both the stack pointer and its
10411;; backchain and restore both. Note that in the nonlocal case, the
10412;; save area is a memory location.
10413
10414(define_expand "save_stack_function"
ff381587
MM		 10415 [(match_operand 0 "any_operand" "")
10416 (match_operand 1 "any_operand" "")]
59257ff7 10417 ""
ff381587 10418 "DONE;")
59257ff7
RK		 10419
10420(define_expand "restore_stack_function"
ff381587
MM		 10421 [(match_operand 0 "any_operand" "")
10422 (match_operand 1 "any_operand" "")]
59257ff7 10423 ""
ff381587 10424 "DONE;")
59257ff7 10425
2eef28ec
AM		 10426;; Adjust stack pointer (op0) to a new value (op1).
10427;; First copy old stack backchain to new location, and ensure that the
10428;; scheduler won't reorder the sp assignment before the backchain write.
59257ff7 10429(define_expand "restore_stack_block"
2eef28ec
AM		 10430 [(set (match_dup 2) (match_dup 3))
10431 (set (match_dup 4) (match_dup 2))
10432 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10433 (set (match_operand 0 "register_operand" "")
10434 (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10435 ""
10436 "
dfdfa60f
DE		 10437{
10438 operands[2] = gen_reg_rtx (Pmode);
2eef28ec
AM		 10439 operands[3] = gen_frame_mem (Pmode, operands[0]);
10440 operands[4] = gen_frame_mem (Pmode, operands[1]);
10441 operands[5] = gen_frame_mem (BLKmode, operands[0]);
dfdfa60f 10442}")
59257ff7
RK		 10443
10444(define_expand "save_stack_nonlocal"
2eef28ec
AM		 10445 [(set (match_dup 3) (match_dup 4))
10446 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10447 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10448 ""
10449 "
10450{
11b25716 10451 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10452
10453 /* Copy the backchain to the first word, sp to the second. */
2eef28ec
AM		 10454 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10455 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10456 operands[3] = gen_reg_rtx (Pmode);
10457 operands[4] = gen_frame_mem (Pmode, operands[1]);
59257ff7 10458}")
7e69e155 10459
59257ff7 10460(define_expand "restore_stack_nonlocal"
2eef28ec
AM		 10461 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10462 (set (match_dup 3) (match_dup 4))
10463 (set (match_dup 5) (match_dup 2))
10464 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10465 (set (match_operand 0 "register_operand" "") (match_dup 3))]
59257ff7
RK		 10466 ""
10467 "
10468{
11b25716 10469 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10470
10471 /* Restore the backchain from the first word, sp from the second. */
2eef28ec
AM		 10472 operands[2] = gen_reg_rtx (Pmode);
10473 operands[3] = gen_reg_rtx (Pmode);
10474 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10475 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10476 operands[5] = gen_frame_mem (Pmode, operands[3]);
10477 operands[6] = gen_frame_mem (BLKmode, operands[0]);
59257ff7 10478}")
9ebbca7d
GK		 10479\f
10480;; TOC register handling.
b6c9286a 10481
9ebbca7d 10482;; Code to initialize the TOC register...
f0f6a223 10483
9ebbca7d 10484(define_insn "load_toc_aix_si"
e72247f4 10485 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 10486 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10487 (use (reg:SI 2))])]
2bfcf297 10488 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 10489 "*
10490{
9ebbca7d
GK		 10491 char buf[30];
10492 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 10493 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10494 operands[2] = gen_rtx_REG (Pmode, 2);
10495 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 10496}"
10497 [(set_attr "type" "load")])
9ebbca7d
GK		 10498
10499(define_insn "load_toc_aix_di"
e72247f4 10500 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 10501 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10502 (use (reg:DI 2))])]
2bfcf297 10503 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 10504 "*
10505{
10506 char buf[30];
f585a356
DE		 10507#ifdef TARGET_RELOCATABLE
10508 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10509 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10510#else
9ebbca7d 10511 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 10512#endif
2bfcf297
DB		 10513 if (TARGET_ELF)
10514 strcat (buf, \"@toc\");
a8a05998 10515 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10516 operands[2] = gen_rtx_REG (Pmode, 2);
10517 return \"ld %0,%1(%2)\";
10518}"
10519 [(set_attr "type" "load")])
10520
10521(define_insn "load_toc_v4_pic_si"
1de43f85 10522 [(set (reg:SI LR_REGNO)
615158e2 10523 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 10524 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 10525 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10526 [(set_attr "type" "branch")
10527 (set_attr "length" "4")])
10528
9ebbca7d 10529(define_insn "load_toc_v4_PIC_1"
1de43f85 10530 [(set (reg:SI LR_REGNO)
e65a3857
DE		 10531 (match_operand:SI 0 "immediate_operand" "s"))
10532 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
7f970b70
AM		 10533 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10534 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
e65a3857 10535 "bcl 20,31,%0\\n%0:"
9ebbca7d
GK		 10536 [(set_attr "type" "branch")
10537 (set_attr "length" "4")])
10538
10539(define_insn "load_toc_v4_PIC_1b"
1de43f85 10540 [(set (reg:SI LR_REGNO)
e65a3857 10541 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
c4501e62 10542 UNSPEC_TOCPTR))]
20b71b17 10543 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
e65a3857 10544 "bcl 20,31,$+8\\n\\t.long %0-$"
9ebbca7d
GK		 10545 [(set_attr "type" "branch")
10546 (set_attr "length" "8")])
10547
10548(define_insn "load_toc_v4_PIC_2"
f585a356 10549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 10550 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 10551 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10552 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 10553 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 10554 "{l|lwz} %0,%2-%3(%1)"
10555 [(set_attr "type" "load")])
10556
7f970b70
AM		 10557(define_insn "load_toc_v4_PIC_3b"
10558 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10559 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10560 (high:SI
10561 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10562 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10563 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10564 "{cau|addis} %0,%1,%2-%3@ha")
10565
10566(define_insn "load_toc_v4_PIC_3c"
10567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10568 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10569 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10570 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10571 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10572 "{cal|addi} %0,%1,%2-%3@l")
f51eee6a 10573
9ebbca7d
GK		 10574;; If the TOC is shared over a translation unit, as happens with all
10575;; the kinds of PIC that we support, we need to restore the TOC
10576;; pointer only when jumping over units of translation.
f51eee6a 10577;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 10578
10579(define_expand "builtin_setjmp_receiver"
10580 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 10581 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 10582 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10583 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 10584 "
10585{
84d7dd4a 10586#if TARGET_MACHO
f51eee6a
GK		 10587 if (DEFAULT_ABI == ABI_DARWIN)
10588 {
d24652ee 10589 const char *picbase = machopic_function_base_name ();
485bad26 10590 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
f51eee6a
GK		 10591 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10592 rtx tmplabrtx;
10593 char tmplab[20];
10594
10595 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10596 CODE_LABEL_NUMBER (operands[0]));
485bad26 10597 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a 10598
316fbf19 10599 emit_insn (gen_load_macho_picbase (tmplabrtx));
1de43f85 10600 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
b8a55285 10601 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
f51eee6a
GK		 10602 }
10603 else
84d7dd4a 10604#endif
f51eee6a 10605 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 10606 DONE;
10607}")
7f970b70
AM		 10608
10609;; Elf specific ways of loading addresses for non-PIC code.
10610;; The output of this could be r0, but we make a very strong
10611;; preference for a base register because it will usually
10612;; be needed there.
10613(define_insn "elf_high"
10614 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10615 (high:SI (match_operand 1 "" "")))]
10616 "TARGET_ELF && ! TARGET_64BIT"
10617 "{liu|lis} %0,%1@ha")
10618
10619(define_insn "elf_low"
10620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10621 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10622 (match_operand 2 "" "")))]
10623 "TARGET_ELF && ! TARGET_64BIT"
10624 "@
10625 {cal|la} %0,%2@l(%1)
10626 {ai|addic} %0,%1,%K2")
9ebbca7d
GK		 10627\f
10628;; A function pointer under AIX is a pointer to a data area whose first word
10629;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 10630;; pointer to its TOC, and whose third word contains a value to place in the
10631;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 10632;; "trampoline" need not have any executable code.
b6c9286a 10633
cccf3bdc
DE		 10634(define_expand "call_indirect_aix32"
10635 [(set (match_dup 2)
10636 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10637 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10638 (reg:SI 2))
10639 (set (reg:SI 2)
10640 (mem:SI (plus:SI (match_dup 0)
10641 (const_int 4))))
10642 (set (reg:SI 11)
10643 (mem:SI (plus:SI (match_dup 0)
10644 (const_int 8))))
10645 (parallel [(call (mem:SI (match_dup 2))
10646 (match_operand 1 "" ""))
10647 (use (reg:SI 2))
10648 (use (reg:SI 11))
10649 (set (reg:SI 2)
10650 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10651 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10652 "TARGET_32BIT"
10653 "
10654{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 10655
cccf3bdc
DE		 10656(define_expand "call_indirect_aix64"
10657 [(set (match_dup 2)
10658 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10659 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10660 (reg:DI 2))
10661 (set (reg:DI 2)
10662 (mem:DI (plus:DI (match_dup 0)
10663 (const_int 8))))
10664 (set (reg:DI 11)
10665 (mem:DI (plus:DI (match_dup 0)
10666 (const_int 16))))
10667 (parallel [(call (mem:SI (match_dup 2))
10668 (match_operand 1 "" ""))
10669 (use (reg:DI 2))
10670 (use (reg:DI 11))
10671 (set (reg:DI 2)
10672 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10673 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10674 "TARGET_64BIT"
10675 "
10676{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 10677
cccf3bdc
DE		 10678(define_expand "call_value_indirect_aix32"
10679 [(set (match_dup 3)
10680 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10681 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10682 (reg:SI 2))
10683 (set (reg:SI 2)
10684 (mem:SI (plus:SI (match_dup 1)
10685 (const_int 4))))
10686 (set (reg:SI 11)
10687 (mem:SI (plus:SI (match_dup 1)
10688 (const_int 8))))
10689 (parallel [(set (match_operand 0 "" "")
10690 (call (mem:SI (match_dup 3))
10691 (match_operand 2 "" "")))
10692 (use (reg:SI 2))
10693 (use (reg:SI 11))
10694 (set (reg:SI 2)
10695 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10696 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10697 "TARGET_32BIT"
10698 "
10699{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 10700
cccf3bdc
DE		 10701(define_expand "call_value_indirect_aix64"
10702 [(set (match_dup 3)
10703 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10704 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10705 (reg:DI 2))
10706 (set (reg:DI 2)
10707 (mem:DI (plus:DI (match_dup 1)
10708 (const_int 8))))
10709 (set (reg:DI 11)
10710 (mem:DI (plus:DI (match_dup 1)
10711 (const_int 16))))
10712 (parallel [(set (match_operand 0 "" "")
10713 (call (mem:SI (match_dup 3))
10714 (match_operand 2 "" "")))
10715 (use (reg:DI 2))
10716 (use (reg:DI 11))
10717 (set (reg:DI 2)
10718 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10719 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10720 "TARGET_64BIT"
10721 "
10722{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 10723
b6c9286a 10724;; Now the definitions for the call and call_value insns
1fd4e8c1 10725(define_expand "call"
a260abc9 10726 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 10727 (match_operand 1 "" ""))
4697a36c 10728 (use (match_operand 2 "" ""))
1de43f85 10729 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 10730 ""
10731 "
10732{
ee890fe2 10733#if TARGET_MACHO
ab82a49f 10734 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10735 operands[0] = machopic_indirect_call_target (operands[0]);
10736#endif
10737
37409796
NS		 10738 gcc_assert (GET_CODE (operands[0]) == MEM);
10739 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
1fd4e8c1
RK		 10740
10741 operands[0] = XEXP (operands[0], 0);
7509c759 10742
7f970b70
AM		 10743 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10744 && flag_pic
10745 && GET_CODE (operands[0]) == SYMBOL_REF
10746 && !SYMBOL_REF_LOCAL_P (operands[0]))
10747 {
10748 rtx call;
10749 rtvec tmp;
10750
10751 tmp = gen_rtvec (3,
10752 gen_rtx_CALL (VOIDmode,
10753 gen_rtx_MEM (SImode, operands[0]),
10754 operands[1]),
10755 gen_rtx_USE (VOIDmode, operands[2]),
ee05ef56 10756 gen_rtx_CLOBBER (VOIDmode,
1de43f85 10757 gen_rtx_REG (Pmode, LR_REGNO)));
7f970b70
AM		 10758 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10759 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10760 DONE;
10761 }
10762
6a4cee5f 10763 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 10764 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
efdba735 10765 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
1fd4e8c1 10766 {
6a4cee5f
MM		 10767 if (INTVAL (operands[2]) & CALL_LONG)
10768 operands[0] = rs6000_longcall_ref (operands[0]);
10769
37409796
NS		 10770 switch (DEFAULT_ABI)
10771 {
10772 case ABI_V4:
10773 case ABI_DARWIN:
10774 operands[0] = force_reg (Pmode, operands[0]);
10775 break;
1fd4e8c1 10776
37409796 10777 case ABI_AIX:
cccf3bdc
DE		 10778 /* AIX function pointers are really pointers to a three word
10779 area. */
10780 emit_call_insn (TARGET_32BIT
10781 ? gen_call_indirect_aix32 (force_reg (SImode,
10782 operands[0]),
10783 operands[1])
10784 : gen_call_indirect_aix64 (force_reg (DImode,
10785 operands[0]),
10786 operands[1]));
10787 DONE;
37409796
NS		 10788
10789 default:
10790 gcc_unreachable ();
b6c9286a 10791 }
1fd4e8c1
RK		 10792 }
10793}")
10794
10795(define_expand "call_value"
10796 [(parallel [(set (match_operand 0 "" "")
a260abc9 10797 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 10798 (match_operand 2 "" "")))
4697a36c 10799 (use (match_operand 3 "" ""))
1de43f85 10800 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 10801 ""
10802 "
10803{
ee890fe2 10804#if TARGET_MACHO
ab82a49f 10805 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10806 operands[1] = machopic_indirect_call_target (operands[1]);
10807#endif
10808
37409796
NS		 10809 gcc_assert (GET_CODE (operands[1]) == MEM);
10810 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
1fd4e8c1
RK		 10811
10812 operands[1] = XEXP (operands[1], 0);
7509c759 10813
7f970b70
AM		 10814 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10815 && flag_pic
10816 && GET_CODE (operands[1]) == SYMBOL_REF
10817 && !SYMBOL_REF_LOCAL_P (operands[1]))
10818 {
10819 rtx call;
10820 rtvec tmp;
10821
10822 tmp = gen_rtvec (3,
10823 gen_rtx_SET (VOIDmode,
10824 operands[0],
10825 gen_rtx_CALL (VOIDmode,
10826 gen_rtx_MEM (SImode,
10827 operands[1]),
10828 operands[2])),
10829 gen_rtx_USE (VOIDmode, operands[3]),
ee05ef56 10830 gen_rtx_CLOBBER (VOIDmode,
1de43f85 10831 gen_rtx_REG (Pmode, LR_REGNO)));
7f970b70
AM		 10832 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10833 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10834 DONE;
10835 }
10836
6a4cee5f 10837 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 10838 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
efdba735 10839 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
1fd4e8c1 10840 {
6756293c 10841 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 10842 operands[1] = rs6000_longcall_ref (operands[1]);
10843
37409796
NS		 10844 switch (DEFAULT_ABI)
10845 {
10846 case ABI_V4:
10847 case ABI_DARWIN:
10848 operands[1] = force_reg (Pmode, operands[1]);
10849 break;
1fd4e8c1 10850
37409796 10851 case ABI_AIX:
cccf3bdc
DE		 10852 /* AIX function pointers are really pointers to a three word
10853 area. */
10854 emit_call_insn (TARGET_32BIT
10855 ? gen_call_value_indirect_aix32 (operands[0],
10856 force_reg (SImode,
10857 operands[1]),
10858 operands[2])
10859 : gen_call_value_indirect_aix64 (operands[0],
10860 force_reg (DImode,
10861 operands[1]),
10862 operands[2]));
10863 DONE;
37409796
NS		 10864
10865 default:
10866 gcc_unreachable ();
b6c9286a 10867 }
1fd4e8c1
RK		 10868 }
10869}")
10870
04780ee7 10871;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 10872;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10873;; either the function was not prototyped, or it was prototyped as a
10874;; variable argument function. It is > 0 if FP registers were passed
10875;; and < 0 if they were not.
04780ee7 10876
a260abc9 10877(define_insn "*call_local32"
4697a36c
MM		 10878 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10879 (match_operand 1 "" "g,g"))
10880 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 10881 (clobber (reg:SI LR_REGNO))]
5a19791c 10882 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 10883 "*
10884{
6a4cee5f
MM		 10885 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10886 output_asm_insn (\"crxor 6,6,6\", operands);
10887
10888 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10889 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 10890
a226df46 10891 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 10892}"
b7ff3d82
DE		 10893 [(set_attr "type" "branch")
10894 (set_attr "length" "4,8")])
04780ee7 10895
a260abc9
DE		 10896(define_insn "*call_local64"
10897 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10898 (match_operand 1 "" "g,g"))
10899 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 10900 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10901 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10902 "*
10903{
10904 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10905 output_asm_insn (\"crxor 6,6,6\", operands);
10906
10907 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10908 output_asm_insn (\"creqv 6,6,6\", operands);
10909
10910 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10911}"
10912 [(set_attr "type" "branch")
10913 (set_attr "length" "4,8")])
10914
cccf3bdc 10915(define_insn "*call_value_local32"
d18dba68 10916 [(set (match_operand 0 "" "")
a260abc9
DE		 10917 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10918 (match_operand 2 "" "g,g")))
10919 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 10920 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10921 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10922 "*
10923{
10924 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10925 output_asm_insn (\"crxor 6,6,6\", operands);
10926
10927 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10928 output_asm_insn (\"creqv 6,6,6\", operands);
10929
10930 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10931}"
10932 [(set_attr "type" "branch")
10933 (set_attr "length" "4,8")])
10934
10935
cccf3bdc 10936(define_insn "*call_value_local64"
d18dba68 10937 [(set (match_operand 0 "" "")
a260abc9
DE		 10938 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10939 (match_operand 2 "" "g,g")))
10940 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 10941 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10942 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10943 "*
10944{
10945 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10946 output_asm_insn (\"crxor 6,6,6\", operands);
10947
10948 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10949 output_asm_insn (\"creqv 6,6,6\", operands);
10950
10951 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10952}"
10953 [(set_attr "type" "branch")
10954 (set_attr "length" "4,8")])
10955
04780ee7 10956;; Call to function which may be in another module. Restore the TOC
911f679c 10957;; pointer (r2) after the call unless this is System V.
a0ab749a 10958;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10959;; either the function was not prototyped, or it was prototyped as a
10960;; variable argument function. It is > 0 if FP registers were passed
10961;; and < 0 if they were not.
04780ee7 10962
cccf3bdc 10963(define_insn "*call_indirect_nonlocal_aix32"
70ae0191
DE		 10964 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10965 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 10966 (use (reg:SI 2))
10967 (use (reg:SI 11))
10968 (set (reg:SI 2)
10969 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10970 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10971 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10972 "b%T0l\;{l|lwz} 2,20(1)"
10973 [(set_attr "type" "jmpreg")
10974 (set_attr "length" "8")])
10975
a260abc9 10976(define_insn "*call_nonlocal_aix32"
cc4d5fec 10977 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10978 (match_operand 1 "" "g"))
10979 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 10980 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10981 "TARGET_32BIT
10982 && DEFAULT_ABI == ABI_AIX
5a19791c 10983 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10984 "bl %z0\;%."
b7ff3d82 10985 [(set_attr "type" "branch")
cccf3bdc
DE		 10986 (set_attr "length" "8")])
10987
10988(define_insn "*call_indirect_nonlocal_aix64"
70ae0191
DE		 10989 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10990 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 10991 (use (reg:DI 2))
10992 (use (reg:DI 11))
10993 (set (reg:DI 2)
10994 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10995 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10996 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10997 "b%T0l\;ld 2,40(1)"
10998 [(set_attr "type" "jmpreg")
10999 (set_attr "length" "8")])
59313e4e 11000
a260abc9 11001(define_insn "*call_nonlocal_aix64"
cc4d5fec 11002 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11003 (match_operand 1 "" "g"))
11004 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11005 (clobber (reg:SI LR_REGNO))]
6ae08853 11006 "TARGET_64BIT
9ebbca7d 11007 && DEFAULT_ABI == ABI_AIX
a260abc9 11008 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 11009 "bl %z0\;%."
a260abc9 11010 [(set_attr "type" "branch")
cccf3bdc 11011 (set_attr "length" "8")])
7509c759 11012
cccf3bdc 11013(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 11014 [(set (match_operand 0 "" "")
70ae0191
DE		 11015 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11016 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11017 (use (reg:SI 2))
11018 (use (reg:SI 11))
11019 (set (reg:SI 2)
11020 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11021 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11022 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11023 "b%T1l\;{l|lwz} 2,20(1)"
11024 [(set_attr "type" "jmpreg")
11025 (set_attr "length" "8")])
1fd4e8c1 11026
cccf3bdc 11027(define_insn "*call_value_nonlocal_aix32"
d18dba68 11028 [(set (match_operand 0 "" "")
cc4d5fec 11029 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11030 (match_operand 2 "" "g")))
11031 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11032 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11033 "TARGET_32BIT
11034 && DEFAULT_ABI == ABI_AIX
a260abc9 11035 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 11036 "bl %z1\;%."
b7ff3d82 11037 [(set_attr "type" "branch")
cccf3bdc 11038 (set_attr "length" "8")])
04780ee7 11039
cccf3bdc 11040(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 11041 [(set (match_operand 0 "" "")
70ae0191
DE		 11042 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11043 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11044 (use (reg:DI 2))
11045 (use (reg:DI 11))
11046 (set (reg:DI 2)
11047 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11048 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11049 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11050 "b%T1l\;ld 2,40(1)"
11051 [(set_attr "type" "jmpreg")
11052 (set_attr "length" "8")])
11053
11054(define_insn "*call_value_nonlocal_aix64"
d18dba68 11055 [(set (match_operand 0 "" "")
cc4d5fec 11056 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11057 (match_operand 2 "" "g")))
11058 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11059 (clobber (reg:SI LR_REGNO))]
6ae08853 11060 "TARGET_64BIT
9ebbca7d 11061 && DEFAULT_ABI == ABI_AIX
5a19791c 11062 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 11063 "bl %z1\;%."
11064 [(set_attr "type" "branch")
11065 (set_attr "length" "8")])
11066
11067;; A function pointer under System V is just a normal pointer
11068;; operands[0] is the function pointer
11069;; operands[1] is the stack size to clean up
11070;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11071;; which indicates how to set cr1
11072
9613eaff
SH		 11073(define_insn "*call_indirect_nonlocal_sysv<mode>"
11074 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11075 (match_operand 1 "" "g,g,g,g"))
11076 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
1de43f85 11077 (clobber (reg:SI LR_REGNO))]
50d440bc 11078 "DEFAULT_ABI == ABI_V4
f607bc57 11079 || DEFAULT_ABI == ABI_DARWIN"
911f679c 11080{
cccf3bdc 11081 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11082 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 11083
cccf3bdc 11084 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11085 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11086
a5c76ee6
ZW		 11087 return "b%T0l";
11088}
6d0a8091
DJ		 11089 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11090 (set_attr "length" "4,4,8,8")])
cccf3bdc 11091
9613eaff
SH		 11092(define_insn "*call_nonlocal_sysv<mode>"
11093 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11094 (match_operand 1 "" "g,g"))
11095 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11096 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11097 "(DEFAULT_ABI == ABI_DARWIN
11098 || (DEFAULT_ABI == ABI_V4
11099 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11100{
11101 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11102 output_asm_insn ("crxor 6,6,6", operands);
11103
11104 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11105 output_asm_insn ("creqv 6,6,6", operands);
11106
c989f2f7 11107#if TARGET_MACHO
efdba735
SH		 11108 return output_call(insn, operands, 0, 2);
11109#else
7f970b70
AM		 11110 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11111 {
11112 if (TARGET_SECURE_PLT && flag_pic == 2)
11113 /* The magic 32768 offset here and in the other sysv call insns
11114 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11115 See sysv4.h:toc_section. */
11116 return "bl %z0+32768@plt";
11117 else
11118 return "bl %z0@plt";
11119 }
11120 else
11121 return "bl %z0";
6ae08853 11122#endif
a5c76ee6
ZW		 11123}
11124 [(set_attr "type" "branch,branch")
11125 (set_attr "length" "4,8")])
11126
9613eaff 11127(define_insn "*call_value_indirect_nonlocal_sysv<mode>"
d18dba68 11128 [(set (match_operand 0 "" "")
9613eaff 11129 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11130 (match_operand 2 "" "g,g,g,g")))
11131 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
1de43f85 11132 (clobber (reg:SI LR_REGNO))]
50d440bc 11133 "DEFAULT_ABI == ABI_V4
f607bc57 11134 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 11135{
6a4cee5f 11136 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11137 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 11138
11139 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11140 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11141
a5c76ee6
ZW		 11142 return "b%T1l";
11143}
6d0a8091
DJ		 11144 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11145 (set_attr "length" "4,4,8,8")])
a5c76ee6 11146
9613eaff 11147(define_insn "*call_value_nonlocal_sysv<mode>"
a5c76ee6 11148 [(set (match_operand 0 "" "")
9613eaff 11149 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11150 (match_operand 2 "" "g,g")))
11151 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11152 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11153 "(DEFAULT_ABI == ABI_DARWIN
11154 || (DEFAULT_ABI == ABI_V4
11155 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11156{
11157 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11158 output_asm_insn ("crxor 6,6,6", operands);
11159
11160 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11161 output_asm_insn ("creqv 6,6,6", operands);
11162
c989f2f7 11163#if TARGET_MACHO
efdba735
SH		 11164 return output_call(insn, operands, 1, 3);
11165#else
7f970b70
AM		 11166 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11167 {
11168 if (TARGET_SECURE_PLT && flag_pic == 2)
11169 return "bl %z1+32768@plt";
11170 else
11171 return "bl %z1@plt";
11172 }
11173 else
11174 return "bl %z1";
6ae08853 11175#endif
a5c76ee6
ZW		 11176}
11177 [(set_attr "type" "branch,branch")
11178 (set_attr "length" "4,8")])
e6f948e3
RK		 11179
11180;; Call subroutine returning any type.
e6f948e3
RK		 11181(define_expand "untyped_call"
11182 [(parallel [(call (match_operand 0 "" "")
11183 (const_int 0))
11184 (match_operand 1 "" "")
11185 (match_operand 2 "" "")])]
11186 ""
11187 "
11188{
11189 int i;
11190
7d70b8b2 11191 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 11192
11193 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11194 {
11195 rtx set = XVECEXP (operands[2], 0, i);
11196 emit_move_insn (SET_DEST (set), SET_SRC (set));
11197 }
11198
11199 /* The optimizer does not know that the call sets the function value
11200 registers we stored in the result block. We avoid problems by
11201 claiming that all hard registers are used and clobbered at this
11202 point. */
11203 emit_insn (gen_blockage ());
11204
11205 DONE;
11206}")
11207
5e1bf043
DJ		 11208;; sibling call patterns
11209(define_expand "sibcall"
11210 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11211 (match_operand 1 "" ""))
11212 (use (match_operand 2 "" ""))
1de43f85 11213 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11214 (return)])]
11215 ""
11216 "
11217{
11218#if TARGET_MACHO
ab82a49f 11219 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11220 operands[0] = machopic_indirect_call_target (operands[0]);
11221#endif
11222
37409796
NS		 11223 gcc_assert (GET_CODE (operands[0]) == MEM);
11224 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5e1bf043
DJ		 11225
11226 operands[0] = XEXP (operands[0], 0);
5e1bf043
DJ		 11227}")
11228
11229;; this and similar patterns must be marked as using LR, otherwise
11230;; dataflow will try to delete the store into it. This is true
11231;; even when the actual reg to jump to is in CTR, when LR was
11232;; saved and restored around the PIC-setting BCL.
11233(define_insn "*sibcall_local32"
11234 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11235 (match_operand 1 "" "g,g"))
11236 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11237 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11238 (return)]
11239 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11240 "*
11241{
11242 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11243 output_asm_insn (\"crxor 6,6,6\", operands);
11244
11245 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11246 output_asm_insn (\"creqv 6,6,6\", operands);
11247
11248 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11249}"
11250 [(set_attr "type" "branch")
11251 (set_attr "length" "4,8")])
11252
11253(define_insn "*sibcall_local64"
11254 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11255 (match_operand 1 "" "g,g"))
11256 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11257 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11258 (return)]
11259 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11260 "*
11261{
11262 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11263 output_asm_insn (\"crxor 6,6,6\", operands);
11264
11265 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11266 output_asm_insn (\"creqv 6,6,6\", operands);
11267
11268 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11269}"
11270 [(set_attr "type" "branch")
11271 (set_attr "length" "4,8")])
11272
11273(define_insn "*sibcall_value_local32"
11274 [(set (match_operand 0 "" "")
11275 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11276 (match_operand 2 "" "g,g")))
11277 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11278 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11279 (return)]
11280 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11281 "*
11282{
11283 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11284 output_asm_insn (\"crxor 6,6,6\", operands);
11285
11286 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11287 output_asm_insn (\"creqv 6,6,6\", operands);
11288
11289 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11290}"
11291 [(set_attr "type" "branch")
11292 (set_attr "length" "4,8")])
11293
11294
11295(define_insn "*sibcall_value_local64"
11296 [(set (match_operand 0 "" "")
11297 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11298 (match_operand 2 "" "g,g")))
11299 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11300 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11301 (return)]
11302 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11303 "*
11304{
11305 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11306 output_asm_insn (\"crxor 6,6,6\", operands);
11307
11308 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11309 output_asm_insn (\"creqv 6,6,6\", operands);
11310
11311 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11312}"
11313 [(set_attr "type" "branch")
11314 (set_attr "length" "4,8")])
11315
11316(define_insn "*sibcall_nonlocal_aix32"
11317 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11318 (match_operand 1 "" "g"))
11319 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11320 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11321 (return)]
11322 "TARGET_32BIT
11323 && DEFAULT_ABI == ABI_AIX
11324 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11325 "b %z0"
11326 [(set_attr "type" "branch")
11327 (set_attr "length" "4")])
11328
11329(define_insn "*sibcall_nonlocal_aix64"
11330 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11331 (match_operand 1 "" "g"))
11332 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11333 (use (reg:SI LR_REGNO))
5e1bf043 11334 (return)]
6ae08853 11335 "TARGET_64BIT
5e1bf043
DJ		 11336 && DEFAULT_ABI == ABI_AIX
11337 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11338 "b %z0"
11339 [(set_attr "type" "branch")
11340 (set_attr "length" "4")])
11341
11342(define_insn "*sibcall_value_nonlocal_aix32"
11343 [(set (match_operand 0 "" "")
11344 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11345 (match_operand 2 "" "g")))
11346 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11347 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11348 (return)]
11349 "TARGET_32BIT
11350 && DEFAULT_ABI == ABI_AIX
11351 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11352 "b %z1"
11353 [(set_attr "type" "branch")
11354 (set_attr "length" "4")])
11355
11356(define_insn "*sibcall_value_nonlocal_aix64"
11357 [(set (match_operand 0 "" "")
11358 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11359 (match_operand 2 "" "g")))
11360 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11361 (use (reg:SI LR_REGNO))
5e1bf043 11362 (return)]
6ae08853 11363 "TARGET_64BIT
5e1bf043
DJ		 11364 && DEFAULT_ABI == ABI_AIX
11365 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11366 "b %z1"
11367 [(set_attr "type" "branch")
11368 (set_attr "length" "4")])
11369
9613eaff
SH		 11370(define_insn "*sibcall_nonlocal_sysv<mode>"
11371 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11372 (match_operand 1 "" ""))
11373 (use (match_operand 2 "immediate_operand" "O,n"))
1de43f85 11374 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11375 (return)]
11376 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11377 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11378 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11379 "*
11380{
11381 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11382 output_asm_insn (\"crxor 6,6,6\", operands);
11383
11384 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11385 output_asm_insn (\"creqv 6,6,6\", operands);
11386
7f970b70
AM		 11387 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11388 {
11389 if (TARGET_SECURE_PLT && flag_pic == 2)
11390 return \"b %z0+32768@plt\";
11391 else
11392 return \"b %z0@plt\";
11393 }
11394 else
11395 return \"b %z0\";
5e1bf043
DJ		 11396}"
11397 [(set_attr "type" "branch,branch")
11398 (set_attr "length" "4,8")])
11399
11400(define_expand "sibcall_value"
11401 [(parallel [(set (match_operand 0 "register_operand" "")
11402 (call (mem:SI (match_operand 1 "address_operand" ""))
11403 (match_operand 2 "" "")))
11404 (use (match_operand 3 "" ""))
1de43f85 11405 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11406 (return)])]
11407 ""
11408 "
11409{
11410#if TARGET_MACHO
ab82a49f 11411 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11412 operands[1] = machopic_indirect_call_target (operands[1]);
11413#endif
11414
37409796
NS		 11415 gcc_assert (GET_CODE (operands[1]) == MEM);
11416 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5e1bf043
DJ		 11417
11418 operands[1] = XEXP (operands[1], 0);
5e1bf043
DJ		 11419}")
11420
9613eaff 11421(define_insn "*sibcall_value_nonlocal_sysv<mode>"
5e1bf043 11422 [(set (match_operand 0 "" "")
9613eaff 11423 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11424 (match_operand 2 "" "")))
11425 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11426 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11427 (return)]
11428 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11429 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11430 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11431 "*
11432{
11433 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11434 output_asm_insn (\"crxor 6,6,6\", operands);
11435
11436 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11437 output_asm_insn (\"creqv 6,6,6\", operands);
11438
7f970b70
AM		 11439 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11440 {
11441 if (TARGET_SECURE_PLT && flag_pic == 2)
11442 return \"b %z1+32768@plt\";
11443 else
11444 return \"b %z1@plt\";
11445 }
11446 else
11447 return \"b %z1\";
5e1bf043
DJ		 11448}"
11449 [(set_attr "type" "branch,branch")
11450 (set_attr "length" "4,8")])
11451
11452(define_expand "sibcall_epilogue"
11453 [(use (const_int 0))]
11454 "TARGET_SCHED_PROLOG"
11455 "
11456{
11457 rs6000_emit_epilogue (TRUE);
11458 DONE;
11459}")
11460
e6f948e3
RK		 11461;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11462;; all of memory. This blocks insns from being moved across this point.
11463
11464(define_insn "blockage"
615158e2 11465 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 11466 ""
11467 "")
1fd4e8c1
RK		 11468\f
11469;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 11470;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 11471;;
11472;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11473;; insns, and branches. We store the operands of compares until we see
11474;; how it is used.
4ae234b0 11475(define_expand "cmp<mode>"
1fd4e8c1 11476 [(set (cc0)
4ae234b0
GK		 11477 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11478 (match_operand:GPR 1 "reg_or_short_operand" "")))]
1fd4e8c1
RK		 11479 ""
11480 "
11481{
11482 /* Take care of the possibility that operands[1] might be negative but
11483 this might be a logical operation. That insn doesn't exist. */
11484 if (GET_CODE (operands[1]) == CONST_INT
11485 && INTVAL (operands[1]) < 0)
4ae234b0 11486 operands[1] = force_reg (<MODE>mode, operands[1]);
1fd4e8c1
RK		 11487
11488 rs6000_compare_op0 = operands[0];
11489 rs6000_compare_op1 = operands[1];
11490 rs6000_compare_fp_p = 0;
11491 DONE;
11492}")
11493
4ae234b0
GK		 11494(define_expand "cmp<mode>"
11495 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11496 (match_operand:FP 1 "gpc_reg_operand" "")))]
11497 ""
d6f99ca4
DE		 11498 "
11499{
11500 rs6000_compare_op0 = operands[0];
11501 rs6000_compare_op1 = operands[1];
11502 rs6000_compare_fp_p = 1;
11503 DONE;
11504}")
11505
1fd4e8c1 11506(define_expand "beq"
39a10a29 11507 [(use (match_operand 0 "" ""))]
1fd4e8c1 11508 ""
39a10a29 11509 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11510
11511(define_expand "bne"
39a10a29 11512 [(use (match_operand 0 "" ""))]
1fd4e8c1 11513 ""
39a10a29 11514 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
1fd4e8c1 11515
39a10a29
GK		 11516(define_expand "bge"
11517 [(use (match_operand 0 "" ""))]
1fd4e8c1 11518 ""
39a10a29 11519 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
1fd4e8c1
RK		 11520
11521(define_expand "bgt"
39a10a29 11522 [(use (match_operand 0 "" ""))]
1fd4e8c1 11523 ""
39a10a29 11524 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
1fd4e8c1
RK		 11525
11526(define_expand "ble"
39a10a29 11527 [(use (match_operand 0 "" ""))]
1fd4e8c1 11528 ""
39a10a29 11529 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
1fd4e8c1 11530
39a10a29
GK		 11531(define_expand "blt"
11532 [(use (match_operand 0 "" ""))]
1fd4e8c1 11533 ""
39a10a29 11534 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
1fd4e8c1 11535
39a10a29
GK		 11536(define_expand "bgeu"
11537 [(use (match_operand 0 "" ""))]
1fd4e8c1 11538 ""
39a10a29 11539 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
1fd4e8c1 11540
39a10a29
GK		 11541(define_expand "bgtu"
11542 [(use (match_operand 0 "" ""))]
1fd4e8c1 11543 ""
39a10a29 11544 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
1fd4e8c1 11545
39a10a29
GK		 11546(define_expand "bleu"
11547 [(use (match_operand 0 "" ""))]
1fd4e8c1 11548 ""
39a10a29 11549 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
1fd4e8c1 11550
39a10a29
GK		 11551(define_expand "bltu"
11552 [(use (match_operand 0 "" ""))]
1fd4e8c1 11553 ""
39a10a29 11554 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
1fd4e8c1 11555
1c882ea4 11556(define_expand "bunordered"
39a10a29 11557 [(use (match_operand 0 "" ""))]
8ef65e3d 11558 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11559 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11560
11561(define_expand "bordered"
39a10a29 11562 [(use (match_operand 0 "" ""))]
8ef65e3d 11563 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11564 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11565
11566(define_expand "buneq"
39a10a29 11567 [(use (match_operand 0 "" ""))]
b26941b4 11568 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11569 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
1c882ea4
GK		 11570
11571(define_expand "bunge"
39a10a29 11572 [(use (match_operand 0 "" ""))]
b26941b4 11573 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11574 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
1c882ea4
GK		 11575
11576(define_expand "bungt"
39a10a29 11577 [(use (match_operand 0 "" ""))]
b26941b4 11578 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11579 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
1c882ea4
GK		 11580
11581(define_expand "bunle"
39a10a29 11582 [(use (match_operand 0 "" ""))]
b26941b4 11583 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11584 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
1c882ea4
GK		 11585
11586(define_expand "bunlt"
39a10a29 11587 [(use (match_operand 0 "" ""))]
b26941b4 11588 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11589 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
1c882ea4
GK		 11590
11591(define_expand "bltgt"
39a10a29 11592 [(use (match_operand 0 "" ""))]
1c882ea4 11593 ""
39a10a29 11594 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
1c882ea4 11595
1fd4e8c1
RK		 11596;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11597;; For SEQ, likewise, except that comparisons with zero should be done
11598;; with an scc insns. However, due to the order that combine see the
11599;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11600;; the cases we don't want to handle.
11601(define_expand "seq"
39a10a29 11602 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11603 ""
39a10a29 11604 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11605
11606(define_expand "sne"
39a10a29 11607 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11608 ""
11609 "
6ae08853 11610{
39a10a29 11611 if (! rs6000_compare_fp_p)
1fd4e8c1
RK		 11612 FAIL;
11613
6ae08853 11614 rs6000_emit_sCOND (NE, operands[0]);
39a10a29 11615 DONE;
1fd4e8c1
RK		 11616}")
11617
b7053a3f
GK		 11618;; A >= 0 is best done the portable way for A an integer.
11619(define_expand "sge"
39a10a29 11620 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11621 ""
11622 "
5638268e 11623{
e56d7409 11624 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11625 FAIL;
11626
b7053a3f 11627 rs6000_emit_sCOND (GE, operands[0]);
39a10a29 11628 DONE;
1fd4e8c1
RK		 11629}")
11630
b7053a3f
GK		 11631;; A > 0 is best done using the portable sequence, so fail in that case.
11632(define_expand "sgt"
39a10a29 11633 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11634 ""
11635 "
5638268e 11636{
e56d7409 11637 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11638 FAIL;
11639
6ae08853 11640 rs6000_emit_sCOND (GT, operands[0]);
39a10a29 11641 DONE;
1fd4e8c1
RK		 11642}")
11643
b7053a3f
GK		 11644;; A <= 0 is best done the portable way for A an integer.
11645(define_expand "sle"
39a10a29 11646 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11647 ""
5638268e
DE		 11648 "
11649{
e56d7409 11650 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5638268e
DE		 11651 FAIL;
11652
6ae08853 11653 rs6000_emit_sCOND (LE, operands[0]);
5638268e
DE		 11654 DONE;
11655}")
1fd4e8c1 11656
b7053a3f
GK		 11657;; A < 0 is best done in the portable way for A an integer.
11658(define_expand "slt"
39a10a29 11659 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11660 ""
11661 "
5638268e 11662{
e56d7409 11663 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11664 FAIL;
11665
6ae08853 11666 rs6000_emit_sCOND (LT, operands[0]);
39a10a29 11667 DONE;
1fd4e8c1
RK		 11668}")
11669
b7053a3f
GK		 11670(define_expand "sgeu"
11671 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11672 ""
11673 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11674
1fd4e8c1 11675(define_expand "sgtu"
39a10a29 11676 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11677 ""
39a10a29 11678 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
1fd4e8c1 11679
b7053a3f
GK		 11680(define_expand "sleu"
11681 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11682 ""
11683 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11684
1fd4e8c1 11685(define_expand "sltu"
39a10a29 11686 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11687 ""
39a10a29 11688 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
1fd4e8c1 11689
b7053a3f 11690(define_expand "sunordered"
39a10a29 11691 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11692 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f 11693 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
1fd4e8c1 11694
b7053a3f 11695(define_expand "sordered"
39a10a29 11696 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11697 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11698 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11699
11700(define_expand "suneq"
11701 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11702 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11703 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11704
11705(define_expand "sunge"
11706 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11707 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11708 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11709
11710(define_expand "sungt"
11711 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11712 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11713 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11714
11715(define_expand "sunle"
11716 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11717 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11718 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11719
11720(define_expand "sunlt"
11721 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11722 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11723 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11724
11725(define_expand "sltgt"
11726 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11727 ""
11728 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11729
3aebbe5f
JJ		 11730(define_expand "stack_protect_set"
11731 [(match_operand 0 "memory_operand" "")
11732 (match_operand 1 "memory_operand" "")]
11733 ""
11734{
77008252
JJ		 11735#ifdef TARGET_THREAD_SSP_OFFSET
11736 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11737 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11738 operands[1] = gen_rtx_MEM (Pmode, addr);
11739#endif
3aebbe5f
JJ		 11740 if (TARGET_64BIT)
11741 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11742 else
11743 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11744 DONE;
11745})
11746
11747(define_insn "stack_protect_setsi"
11748 [(set (match_operand:SI 0 "memory_operand" "=m")
11749 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11750 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11751 "TARGET_32BIT"
11752 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11753 [(set_attr "type" "three")
11754 (set_attr "length" "12")])
11755
11756(define_insn "stack_protect_setdi"
11757 [(set (match_operand:DI 0 "memory_operand" "=m")
11758 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11759 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11760 "TARGET_64BIT"
11761 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11762 [(set_attr "type" "three")
11763 (set_attr "length" "12")])
11764
11765(define_expand "stack_protect_test"
11766 [(match_operand 0 "memory_operand" "")
11767 (match_operand 1 "memory_operand" "")
11768 (match_operand 2 "" "")]
11769 ""
11770{
77008252
JJ		 11771#ifdef TARGET_THREAD_SSP_OFFSET
11772 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11773 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11774 operands[1] = gen_rtx_MEM (Pmode, addr);
11775#endif
3aebbe5f
JJ		 11776 rs6000_compare_op0 = operands[0];
11777 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11778 UNSPEC_SP_TEST);
11779 rs6000_compare_fp_p = 0;
11780 emit_jump_insn (gen_beq (operands[2]));
11781 DONE;
11782})
11783
11784(define_insn "stack_protect_testsi"
11785 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11786 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11787 (match_operand:SI 2 "memory_operand" "m,m")]
11788 UNSPEC_SP_TEST))
41f12ed0
JJ		 11789 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11790 (clobber (match_scratch:SI 3 "=&r,&r"))]
3aebbe5f
JJ		 11791 "TARGET_32BIT"
11792 "@
11793 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11794 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11795 [(set_attr "length" "16,20")])
11796
11797(define_insn "stack_protect_testdi"
11798 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11799 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11800 (match_operand:DI 2 "memory_operand" "m,m")]
11801 UNSPEC_SP_TEST))
41f12ed0
JJ		 11802 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11803 (clobber (match_scratch:DI 3 "=&r,&r"))]
3aebbe5f
JJ		 11804 "TARGET_64BIT"
11805 "@
11806 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11807 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11808 [(set_attr "length" "16,20")])
11809
1fd4e8c1
RK		 11810\f
11811;; Here are the actual compare insns.
4ae234b0 11812(define_insn "*cmp<mode>_internal1"
1fd4e8c1 11813 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
4ae234b0
GK		 11814 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11815 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
1fd4e8c1 11816 ""
4ae234b0 11817 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
b54cf83a 11818 [(set_attr "type" "cmp")])
266eb58a 11819
f357808b 11820;; If we are comparing a register for equality with a large constant,
28d0e143
PB		 11821;; we can do this with an XOR followed by a compare. But this is profitable
11822;; only if the large constant is only used for the comparison (and in this
11823;; case we already have a register to reuse as scratch).
130869aa
PB		 11824;;
11825;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11826;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
f357808b 11827
28d0e143 11828(define_peephole2
130869aa 11829 [(set (match_operand:SI 0 "register_operand")
410c459d 11830 (match_operand:SI 1 "logical_const_operand" ""))
130869aa 11831 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
28d0e143 11832 [(match_dup 0)
410c459d 11833 (match_operand:SI 2 "logical_const_operand" "")]))
28d0e143 11834 (set (match_operand:CC 4 "cc_reg_operand" "")
130869aa 11835 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
28d0e143
PB		 11836 (match_dup 0)))
11837 (set (pc)
11838 (if_then_else (match_operator 6 "equality_operator"
11839 [(match_dup 4) (const_int 0)])
11840 (match_operand 7 "" "")
11841 (match_operand 8 "" "")))]
130869aa
PB		 11842 "peep2_reg_dead_p (3, operands[0])
11843 && peep2_reg_dead_p (4, operands[4])"
11844 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
28d0e143
PB		 11845 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11846 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11847
11848{
11849 /* Get the constant we are comparing against, and see what it looks like
11850 when sign-extended from 16 to 32 bits. Then see what constant we could
11851 XOR with SEXTC to get the sign-extended value. */
11852 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
130869aa 11853 SImode,
28d0e143
PB		 11854 operands[1], operands[2]);
11855 HOST_WIDE_INT c = INTVAL (cnst);
a65c591c 11856 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 11857 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 11858
28d0e143
PB		 11859 operands[9] = GEN_INT (xorv);
11860 operands[10] = GEN_INT (sextc);
11861})
f357808b 11862
acad7ed3 11863(define_insn "*cmpsi_internal2"
1fd4e8c1 11864 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 11865 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 11866 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 11867 ""
e2c953b6 11868 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 11869 [(set_attr "type" "cmp")])
1fd4e8c1 11870
acad7ed3 11871(define_insn "*cmpdi_internal2"
266eb58a
DE		 11872 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11873 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 11874 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 11875 ""
e2c953b6 11876 "cmpld%I2 %0,%1,%b2"
b54cf83a 11877 [(set_attr "type" "cmp")])
266eb58a 11878
1fd4e8c1
RK		 11879;; The following two insns don't exist as single insns, but if we provide
11880;; them, we can swap an add and compare, which will enable us to overlap more
11881;; of the required delay between a compare and branch. We generate code for
11882;; them by splitting.
11883
11884(define_insn ""
11885 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 11886 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11887 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 11888 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11889 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11890 ""
baf97f86
RK		 11891 "#"
11892 [(set_attr "length" "8")])
7e69e155 11893
1fd4e8c1
RK		 11894(define_insn ""
11895 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 11896 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11897 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 11898 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11899 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11900 ""
baf97f86
RK		 11901 "#"
11902 [(set_attr "length" "8")])
7e69e155 11903
1fd4e8c1
RK		 11904(define_split
11905 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 11906 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11907 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 11908 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11909 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11910 ""
11911 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11912 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11913
11914(define_split
11915 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 11916 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11917 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 11918 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11919 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11920 ""
11921 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11922 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11923
acad7ed3 11924(define_insn "*cmpsf_internal1"
1fd4e8c1 11925 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11926 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11927 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 11928 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11929 "fcmpu %0,%1,%2"
11930 [(set_attr "type" "fpcompare")])
11931
acad7ed3 11932(define_insn "*cmpdf_internal1"
1fd4e8c1 11933 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11934 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11935 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 11936 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11937 "fcmpu %0,%1,%2"
11938 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 11939
11940;; Only need to compare second words if first words equal
11941(define_insn "*cmptf_internal1"
11942 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11943 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11944 (match_operand:TF 2 "gpc_reg_operand" "f")))]
602ea4d3 11945 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
39e63627 11946 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 11947 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 11948 [(set_attr "type" "fpcompare")
11949 (set_attr "length" "12")])
de17c25f
DE		 11950
11951(define_insn_and_split "*cmptf_internal2"
11952 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11953 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11954 (match_operand:TF 2 "gpc_reg_operand" "f")))
11955 (clobber (match_scratch:DF 3 "=f"))
11956 (clobber (match_scratch:DF 4 "=f"))
11957 (clobber (match_scratch:DF 5 "=f"))
11958 (clobber (match_scratch:DF 6 "=f"))
11959 (clobber (match_scratch:DF 7 "=f"))
11960 (clobber (match_scratch:DF 8 "=f"))
11961 (clobber (match_scratch:DF 9 "=f"))
11962 (clobber (match_scratch:DF 10 "=f"))]
602ea4d3 11963 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
de17c25f
DE		 11964 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11965 "#"
11966 "&& reload_completed"
11967 [(set (match_dup 3) (match_dup 13))
11968 (set (match_dup 4) (match_dup 14))
11969 (set (match_dup 9) (abs:DF (match_dup 5)))
11970 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11971 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11972 (label_ref (match_dup 11))
11973 (pc)))
11974 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11975 (set (pc) (label_ref (match_dup 12)))
11976 (match_dup 11)
11977 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11978 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11979 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11980 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11981 (match_dup 12)]
11982{
11983 REAL_VALUE_TYPE rv;
11984 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11985 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11986
11987 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11988 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11989 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11990 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11991 operands[11] = gen_label_rtx ();
11992 operands[12] = gen_label_rtx ();
11993 real_inf (&rv);
11994 operands[13] = force_const_mem (DFmode,
11995 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11996 operands[14] = force_const_mem (DFmode,
11997 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11998 DFmode));
11999 if (TARGET_TOC)
12000 {
12001 operands[13] = gen_const_mem (DFmode,
12002 create_TOC_reference (XEXP (operands[13], 0)));
12003 operands[14] = gen_const_mem (DFmode,
12004 create_TOC_reference (XEXP (operands[14], 0)));
12005 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12006 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12007 }
12008})
1fd4e8c1
RK		 12009\f
12010;; Now we have the scc insns. We can do some combinations because of the
12011;; way the machine works.
12012;;
12013;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 12014;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12015;; cases the insns below which don't use an intermediate CR field will
12016;; be used instead.
1fd4e8c1 12017(define_insn ""
cd2b37d9 12018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12019 (match_operator:SI 1 "scc_comparison_operator"
12020 [(match_operand 2 "cc_reg_operand" "y")
12021 (const_int 0)]))]
12022 ""
2c4a9cff
DE		 12023 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12024 [(set (attr "type")
12025 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12026 (const_string "mfcrf")
12027 ]
12028 (const_string "mfcr")))
c1618c0c 12029 (set_attr "length" "8")])
1fd4e8c1 12030
423c1189 12031;; Same as above, but get the GT bit.
64022b5d 12032(define_insn "move_from_CR_gt_bit"
423c1189 12033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
64022b5d 12034 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
423c1189 12035 "TARGET_E500"
64022b5d 12036 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
423c1189 12037 [(set_attr "type" "mfcr")
c1618c0c 12038 (set_attr "length" "8")])
423c1189 12039
a3170dc6
AH		 12040;; Same as above, but get the OV/ORDERED bit.
12041(define_insn "move_from_CR_ov_bit"
12042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 12043 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 12044 "TARGET_ISEL"
b7053a3f 12045 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a 12046 [(set_attr "type" "mfcr")
c1618c0c 12047 (set_attr "length" "8")])
a3170dc6 12048
1fd4e8c1 12049(define_insn ""
9ebbca7d
GK		 12050 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12051 (match_operator:DI 1 "scc_comparison_operator"
12052 [(match_operand 2 "cc_reg_operand" "y")
12053 (const_int 0)]))]
12054 "TARGET_POWERPC64"
2c4a9cff
DE		 12055 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12056 [(set (attr "type")
12057 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12058 (const_string "mfcrf")
12059 ]
12060 (const_string "mfcr")))
c1618c0c 12061 (set_attr "length" "8")])
9ebbca7d
GK		 12062
12063(define_insn ""
12064 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12065 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12066 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 12067 (const_int 0)])
12068 (const_int 0)))
9ebbca7d 12069 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 12070 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12071 "TARGET_32BIT"
9ebbca7d 12072 "@
2c4a9cff 12073 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 12074 #"
b19003d8 12075 [(set_attr "type" "delayed_compare")
c1618c0c 12076 (set_attr "length" "8,16")])
9ebbca7d
GK		 12077
12078(define_split
12079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12080 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12081 [(match_operand 2 "cc_reg_operand" "")
12082 (const_int 0)])
12083 (const_int 0)))
12084 (set (match_operand:SI 3 "gpc_reg_operand" "")
12085 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12086 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12087 [(set (match_dup 3)
12088 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12089 (set (match_dup 0)
12090 (compare:CC (match_dup 3)
12091 (const_int 0)))]
12092 "")
1fd4e8c1
RK		 12093
12094(define_insn ""
cd2b37d9 12095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12096 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12097 [(match_operand 2 "cc_reg_operand" "y")
12098 (const_int 0)])
12099 (match_operand:SI 3 "const_int_operand" "n")))]
12100 ""
12101 "*
12102{
12103 int is_bit = ccr_bit (operands[1], 1);
12104 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12105 int count;
12106
12107 if (is_bit >= put_bit)
12108 count = is_bit - put_bit;
12109 else
12110 count = 32 - (put_bit - is_bit);
12111
89e9f3a8
MM		 12112 operands[4] = GEN_INT (count);
12113 operands[5] = GEN_INT (put_bit);
1fd4e8c1 12114
2c4a9cff 12115 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 12116}"
2c4a9cff
DE		 12117 [(set (attr "type")
12118 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12119 (const_string "mfcrf")
12120 ]
12121 (const_string "mfcr")))
c1618c0c 12122 (set_attr "length" "8")])
1fd4e8c1
RK		 12123
12124(define_insn ""
9ebbca7d 12125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12126 (compare:CC
12127 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12128 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 12129 (const_int 0)])
9ebbca7d 12130 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 12131 (const_int 0)))
9ebbca7d 12132 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12133 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12134 (match_dup 3)))]
ce71f754 12135 ""
1fd4e8c1
RK		 12136 "*
12137{
12138 int is_bit = ccr_bit (operands[1], 1);
12139 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12140 int count;
12141
9ebbca7d
GK		 12142 /* Force split for non-cc0 compare. */
12143 if (which_alternative == 1)
12144 return \"#\";
12145
1fd4e8c1
RK		 12146 if (is_bit >= put_bit)
12147 count = is_bit - put_bit;
12148 else
12149 count = 32 - (put_bit - is_bit);
12150
89e9f3a8
MM		 12151 operands[5] = GEN_INT (count);
12152 operands[6] = GEN_INT (put_bit);
1fd4e8c1 12153
2c4a9cff 12154 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 12155}"
b19003d8 12156 [(set_attr "type" "delayed_compare")
c1618c0c 12157 (set_attr "length" "8,16")])
9ebbca7d
GK		 12158
12159(define_split
12160 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12161 (compare:CC
12162 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12163 [(match_operand 2 "cc_reg_operand" "")
12164 (const_int 0)])
12165 (match_operand:SI 3 "const_int_operand" ""))
12166 (const_int 0)))
12167 (set (match_operand:SI 4 "gpc_reg_operand" "")
12168 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12169 (match_dup 3)))]
ce71f754 12170 "reload_completed"
9ebbca7d
GK		 12171 [(set (match_dup 4)
12172 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12173 (match_dup 3)))
12174 (set (match_dup 0)
12175 (compare:CC (match_dup 4)
12176 (const_int 0)))]
12177 "")
1fd4e8c1 12178
c5defebb
RK		 12179;; There is a 3 cycle delay between consecutive mfcr instructions
12180;; so it is useful to combine 2 scc instructions to use only one mfcr.
12181
12182(define_peephole
cd2b37d9 12183 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 12184 (match_operator:SI 1 "scc_comparison_operator"
12185 [(match_operand 2 "cc_reg_operand" "y")
12186 (const_int 0)]))
cd2b37d9 12187 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 12188 (match_operator:SI 4 "scc_comparison_operator"
12189 [(match_operand 5 "cc_reg_operand" "y")
12190 (const_int 0)]))]
309323c2 12191 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12192 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12193 [(set_attr "type" "mfcr")
c1618c0c 12194 (set_attr "length" "12")])
c5defebb 12195
9ebbca7d
GK		 12196(define_peephole
12197 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12198 (match_operator:DI 1 "scc_comparison_operator"
12199 [(match_operand 2 "cc_reg_operand" "y")
12200 (const_int 0)]))
12201 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12202 (match_operator:DI 4 "scc_comparison_operator"
12203 [(match_operand 5 "cc_reg_operand" "y")
12204 (const_int 0)]))]
309323c2 12205 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12206 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12207 [(set_attr "type" "mfcr")
c1618c0c 12208 (set_attr "length" "12")])
9ebbca7d 12209
1fd4e8c1
RK		 12210;; There are some scc insns that can be done directly, without a compare.
12211;; These are faster because they don't involve the communications between
12212;; the FXU and branch units. In fact, we will be replacing all of the
12213;; integer scc insns here or in the portable methods in emit_store_flag.
12214;;
12215;; Also support (neg (scc ..)) since that construct is used to replace
12216;; branches, (plus (scc ..) ..) since that construct is common and
12217;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12218;; cases where it is no more expensive than (neg (scc ..)).
12219
12220;; Have reload force a constant into a register for the simple insns that
12221;; otherwise won't accept constants. We do this because it is faster than
12222;; the cmp/mfcr sequence we would otherwise generate.
12223
e9441276
DE		 12224(define_mode_attr scc_eq_op2 [(SI "rKLI")
12225 (DI "rKJI")])
a260abc9 12226
e9441276
DE		 12227(define_insn_and_split "*eq<mode>"
12228 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12229 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
d0515b39 12230 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
27f0fe7f 12231 "!TARGET_POWER"
e9441276 12232 "#"
27f0fe7f 12233 "!TARGET_POWER"
d0515b39
DE		 12234 [(set (match_dup 0)
12235 (clz:GPR (match_dup 3)))
70ae0191 12236 (set (match_dup 0)
d0515b39 12237 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
70ae0191 12238 {
e9441276
DE		 12239 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12240 {
d0515b39
DE		 12241 /* Use output operand as intermediate. */
12242 operands[3] = operands[0];
12243
e9441276 12244 if (logical_operand (operands[2], <MODE>mode))
d0515b39 12245 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12246 gen_rtx_XOR (<MODE>mode,
12247 operands[1], operands[2])));
12248 else
d0515b39 12249 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12250 gen_rtx_PLUS (<MODE>mode, operands[1],
12251 negate_rtx (<MODE>mode,
12252 operands[2]))));
12253 }
12254 else
d0515b39 12255 operands[3] = operands[1];
9ebbca7d 12256
d0515b39 12257 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
e9441276 12258 })
a260abc9 12259
e9441276 12260(define_insn_and_split "*eq<mode>_compare"
d0515b39 12261 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
70ae0191 12262 (compare:CC
1fa5c709
DE		 12263 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12264 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
70ae0191 12265 (const_int 0)))
1fa5c709 12266 (set (match_operand:P 0 "gpc_reg_operand" "=r")
d0515b39 12267 (eq:P (match_dup 1) (match_dup 2)))]
27f0fe7f 12268 "!TARGET_POWER && optimize_size"
e9441276 12269 "#"
27f0fe7f 12270 "!TARGET_POWER && optimize_size"
d0515b39 12271 [(set (match_dup 0)
1fa5c709 12272 (clz:P (match_dup 4)))
d0515b39
DE		 12273 (parallel [(set (match_dup 3)
12274 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
70ae0191
DE		 12275 (const_int 0)))
12276 (set (match_dup 0)
d0515b39 12277 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
70ae0191 12278 {
e9441276
DE		 12279 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12280 {
d0515b39
DE		 12281 /* Use output operand as intermediate. */
12282 operands[4] = operands[0];
12283
e9441276
DE		 12284 if (logical_operand (operands[2], <MODE>mode))
12285 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12286 gen_rtx_XOR (<MODE>mode,
12287 operands[1], operands[2])));
12288 else
12289 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12290 gen_rtx_PLUS (<MODE>mode, operands[1],
12291 negate_rtx (<MODE>mode,
12292 operands[2]))));
12293 }
12294 else
12295 operands[4] = operands[1];
12296
d0515b39 12297 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
70ae0191
DE		 12298 })
12299
05f68097
DE		 12300(define_insn "*eqsi_power"
12301 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12302 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12303 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12304 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12305 "TARGET_POWER"
12306 "@
12307 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12308 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12309 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12310 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12311 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12312 [(set_attr "type" "three,two,three,three,three")
12313 (set_attr "length" "12,8,12,12,12")])
12314
b19003d8
RK		 12315;; We have insns of the form shown by the first define_insn below. If
12316;; there is something inside the comparison operation, we must split it.
12317(define_split
12318 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12319 (plus:SI (match_operator 1 "comparison_operator"
12320 [(match_operand:SI 2 "" "")
12321 (match_operand:SI 3
12322 "reg_or_cint_operand" "")])
12323 (match_operand:SI 4 "gpc_reg_operand" "")))
12324 (clobber (match_operand:SI 5 "register_operand" ""))]
12325 "! gpc_reg_operand (operands[2], SImode)"
12326 [(set (match_dup 5) (match_dup 2))
12327 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12328 (match_dup 4)))])
1fd4e8c1 12329
297abd0d 12330(define_insn "*plus_eqsi"
5276df18 12331 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 12332 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
56fc483e 12333 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
5276df18 12334 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
59d6560b 12335 "TARGET_32BIT"
1fd4e8c1 12336 "@
5276df18
DE		 12337 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12338 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12339 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12340 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12341 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
943c15ed
DE		 12342 [(set_attr "type" "three,two,three,three,three")
12343 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1 12344
297abd0d 12345(define_insn "*compare_plus_eqsi"
9ebbca7d 12346 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12347 (compare:CC
1fd4e8c1 12348 (plus:SI
9ebbca7d 12349 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12350 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12351 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12352 (const_int 0)))
9ebbca7d 12353 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
297abd0d 12354 "TARGET_32BIT && optimize_size"
1fd4e8c1 12355 "@
ca7f5001 12356 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 12357 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 12358 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12359 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12360 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12361 #
12362 #
12363 #
12364 #
12365 #"
b19003d8 12366 [(set_attr "type" "compare")
9ebbca7d
GK		 12367 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12368
12369(define_split
12370 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12371 (compare:CC
12372 (plus:SI
12373 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12374 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12375 (match_operand:SI 3 "gpc_reg_operand" ""))
12376 (const_int 0)))
12377 (clobber (match_scratch:SI 4 ""))]
297abd0d 12378 "TARGET_32BIT && optimize_size && reload_completed"
9ebbca7d
GK		 12379 [(set (match_dup 4)
12380 (plus:SI (eq:SI (match_dup 1)
12381 (match_dup 2))
12382 (match_dup 3)))
12383 (set (match_dup 0)
12384 (compare:CC (match_dup 4)
12385 (const_int 0)))]
12386 "")
1fd4e8c1 12387
297abd0d 12388(define_insn "*plus_eqsi_compare"
0387639b 12389 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12390 (compare:CC
1fd4e8c1 12391 (plus:SI
9ebbca7d 12392 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12393 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12394 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12395 (const_int 0)))
0387639b
DE		 12396 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12397 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12398 "TARGET_32BIT && optimize_size"
1fd4e8c1 12399 "@
0387639b
DE		 12400 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12401 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12402 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12403 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12404 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12405 #
12406 #
12407 #
12408 #
12409 #"
12410 [(set_attr "type" "compare")
12411 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12412
12413(define_split
0387639b 12414 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12415 (compare:CC
12416 (plus:SI
12417 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12418 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12419 (match_operand:SI 3 "gpc_reg_operand" ""))
12420 (const_int 0)))
12421 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 12422 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12423 "TARGET_32BIT && optimize_size && reload_completed"
0387639b 12424 [(set (match_dup 0)
9ebbca7d 12425 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 12426 (set (match_dup 4)
9ebbca7d
GK		 12427 (compare:CC (match_dup 0)
12428 (const_int 0)))]
12429 "")
12430
d0515b39
DE		 12431(define_insn "*neg_eq0<mode>"
12432 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12433 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12434 (const_int 0))))]
59d6560b 12435 ""
d0515b39
DE		 12436 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12437 [(set_attr "type" "two")
12438 (set_attr "length" "8")])
12439
12440(define_insn_and_split "*neg_eq<mode>"
12441 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12442 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12443 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
59d6560b 12444 ""
d0515b39 12445 "#"
59d6560b 12446 ""
d0515b39
DE		 12447 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12448 {
12449 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12450 {
12451 /* Use output operand as intermediate. */
12452 operands[3] = operands[0];
12453
12454 if (logical_operand (operands[2], <MODE>mode))
12455 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12456 gen_rtx_XOR (<MODE>mode,
12457 operands[1], operands[2])));
12458 else
12459 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12460 gen_rtx_PLUS (<MODE>mode, operands[1],
12461 negate_rtx (<MODE>mode,
12462 operands[2]))));
12463 }
12464 else
12465 operands[3] = operands[1];
12466 })
1fd4e8c1 12467
ea9be077
MM		 12468;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12469;; since it nabs/sr is just as fast.
ce45ef46 12470(define_insn "*ne0si"
b4e95693 12471 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 12472 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12473 (const_int 31)))
12474 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 12475 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077 12476 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
943c15ed
DE		 12477 [(set_attr "type" "two")
12478 (set_attr "length" "8")])
ea9be077 12479
ce45ef46 12480(define_insn "*ne0di"
a260abc9
DE		 12481 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12482 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12483 (const_int 63)))
12484 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 12485 "TARGET_64BIT"
a260abc9 12486 "addic %2,%1,-1\;subfe %0,%2,%1"
943c15ed
DE		 12487 [(set_attr "type" "two")
12488 (set_attr "length" "8")])
a260abc9 12489
1fd4e8c1 12490;; This is what (plus (ne X (const_int 0)) Y) looks like.
297abd0d 12491(define_insn "*plus_ne0si"
cd2b37d9 12492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 12493 (plus:SI (lshiftrt:SI
cd2b37d9 12494 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 12495 (const_int 31))
cd2b37d9 12496 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 12497 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 12498 "TARGET_32BIT"
ca7f5001 12499 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
943c15ed
DE		 12500 [(set_attr "type" "two")
12501 (set_attr "length" "8")])
1fd4e8c1 12502
297abd0d 12503(define_insn "*plus_ne0di"
a260abc9
DE		 12504 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12505 (plus:DI (lshiftrt:DI
12506 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12507 (const_int 63))
12508 (match_operand:DI 2 "gpc_reg_operand" "r")))
12509 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 12510 "TARGET_64BIT"
a260abc9 12511 "addic %3,%1,-1\;addze %0,%2"
943c15ed
DE		 12512 [(set_attr "type" "two")
12513 (set_attr "length" "8")])
a260abc9 12514
297abd0d 12515(define_insn "*compare_plus_ne0si"
9ebbca7d 12516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12517 (compare:CC
12518 (plus:SI (lshiftrt:SI
9ebbca7d 12519 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12520 (const_int 31))
9ebbca7d 12521 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12522 (const_int 0)))
889b90a1
GK		 12523 (clobber (match_scratch:SI 3 "=&r,&r"))
12524 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 12525 "TARGET_32BIT"
9ebbca7d
GK		 12526 "@
12527 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12528 #"
b19003d8 12529 [(set_attr "type" "compare")
9ebbca7d
GK		 12530 (set_attr "length" "8,12")])
12531
12532(define_split
12533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12534 (compare:CC
12535 (plus:SI (lshiftrt:SI
12536 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12537 (const_int 31))
12538 (match_operand:SI 2 "gpc_reg_operand" ""))
12539 (const_int 0)))
889b90a1
GK		 12540 (clobber (match_scratch:SI 3 ""))
12541 (clobber (match_scratch:SI 4 ""))]
683bdff7 12542 "TARGET_32BIT && reload_completed"
889b90a1 12543 [(parallel [(set (match_dup 3)
ce71f754
AM		 12544 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12545 (const_int 31))
12546 (match_dup 2)))
889b90a1 12547 (clobber (match_dup 4))])
9ebbca7d
GK		 12548 (set (match_dup 0)
12549 (compare:CC (match_dup 3)
12550 (const_int 0)))]
12551 "")
1fd4e8c1 12552
297abd0d 12553(define_insn "*compare_plus_ne0di"
9ebbca7d 12554 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12555 (compare:CC
12556 (plus:DI (lshiftrt:DI
9ebbca7d 12557 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12558 (const_int 63))
9ebbca7d 12559 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12560 (const_int 0)))
9ebbca7d 12561 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12562 "TARGET_64BIT"
9ebbca7d
GK		 12563 "@
12564 addic %3,%1,-1\;addze. %3,%2
12565 #"
a260abc9 12566 [(set_attr "type" "compare")
9ebbca7d
GK		 12567 (set_attr "length" "8,12")])
12568
12569(define_split
12570 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12571 (compare:CC
12572 (plus:DI (lshiftrt:DI
12573 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12574 (const_int 63))
12575 (match_operand:DI 2 "gpc_reg_operand" ""))
12576 (const_int 0)))
12577 (clobber (match_scratch:DI 3 ""))]
683bdff7 12578 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12579 [(set (match_dup 3)
12580 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12581 (const_int 63))
12582 (match_dup 2)))
12583 (set (match_dup 0)
12584 (compare:CC (match_dup 3)
12585 (const_int 0)))]
12586 "")
a260abc9 12587
297abd0d 12588(define_insn "*plus_ne0si_compare"
9ebbca7d 12589 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12590 (compare:CC
12591 (plus:SI (lshiftrt:SI
9ebbca7d 12592 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12593 (const_int 31))
9ebbca7d 12594 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12595 (const_int 0)))
9ebbca7d 12596 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12597 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12598 (match_dup 2)))
9ebbca7d 12599 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 12600 "TARGET_32BIT"
9ebbca7d
GK		 12601 "@
12602 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12603 #"
b19003d8 12604 [(set_attr "type" "compare")
9ebbca7d
GK		 12605 (set_attr "length" "8,12")])
12606
12607(define_split
12608 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12609 (compare:CC
12610 (plus:SI (lshiftrt:SI
12611 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12612 (const_int 31))
12613 (match_operand:SI 2 "gpc_reg_operand" ""))
12614 (const_int 0)))
12615 (set (match_operand:SI 0 "gpc_reg_operand" "")
12616 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12617 (match_dup 2)))
12618 (clobber (match_scratch:SI 3 ""))]
683bdff7 12619 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12620 [(parallel [(set (match_dup 0)
12621 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12622 (match_dup 2)))
12623 (clobber (match_dup 3))])
12624 (set (match_dup 4)
12625 (compare:CC (match_dup 0)
12626 (const_int 0)))]
12627 "")
1fd4e8c1 12628
297abd0d 12629(define_insn "*plus_ne0di_compare"
9ebbca7d 12630 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12631 (compare:CC
12632 (plus:DI (lshiftrt:DI
9ebbca7d 12633 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12634 (const_int 63))
9ebbca7d 12635 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12636 (const_int 0)))
9ebbca7d 12637 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 12638 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12639 (match_dup 2)))
9ebbca7d 12640 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12641 "TARGET_64BIT"
9ebbca7d
GK		 12642 "@
12643 addic %3,%1,-1\;addze. %0,%2
12644 #"
a260abc9 12645 [(set_attr "type" "compare")
9ebbca7d
GK		 12646 (set_attr "length" "8,12")])
12647
12648(define_split
12649 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12650 (compare:CC
12651 (plus:DI (lshiftrt:DI
12652 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12653 (const_int 63))
12654 (match_operand:DI 2 "gpc_reg_operand" ""))
12655 (const_int 0)))
12656 (set (match_operand:DI 0 "gpc_reg_operand" "")
12657 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12658 (match_dup 2)))
12659 (clobber (match_scratch:DI 3 ""))]
683bdff7 12660 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12661 [(parallel [(set (match_dup 0)
12662 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12663 (match_dup 2)))
12664 (clobber (match_dup 3))])
12665 (set (match_dup 4)
12666 (compare:CC (match_dup 0)
12667 (const_int 0)))]
12668 "")
a260abc9 12669
1fd4e8c1 12670(define_insn ""
cd2b37d9
RK		 12671 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12672 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 12673 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12674 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 12675 "TARGET_POWER"
1fd4e8c1 12676 "@
ca7f5001 12677 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 12678 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12679 [(set_attr "length" "12")])
1fd4e8c1
RK		 12680
12681(define_insn ""
9ebbca7d 12682 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12683 (compare:CC
9ebbca7d
GK		 12684 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12685 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 12686 (const_int 0)))
9ebbca7d 12687 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12688 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12689 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 12690 "TARGET_POWER"
1fd4e8c1 12691 "@
ca7f5001 12692 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 12693 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12694 #
12695 #"
12696 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12697 (set_attr "length" "12,12,16,16")])
12698
12699(define_split
12700 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12701 (compare:CC
12702 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12703 (match_operand:SI 2 "reg_or_short_operand" ""))
12704 (const_int 0)))
12705 (set (match_operand:SI 0 "gpc_reg_operand" "")
12706 (le:SI (match_dup 1) (match_dup 2)))
12707 (clobber (match_scratch:SI 3 ""))]
12708 "TARGET_POWER && reload_completed"
12709 [(parallel [(set (match_dup 0)
12710 (le:SI (match_dup 1) (match_dup 2)))
12711 (clobber (match_dup 3))])
12712 (set (match_dup 4)
12713 (compare:CC (match_dup 0)
12714 (const_int 0)))]
12715 "")
1fd4e8c1
RK		 12716
12717(define_insn ""
097657c3 12718 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12719 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12720 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 12721 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 12722 "TARGET_POWER"
1fd4e8c1 12723 "@
097657c3
AM		 12724 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12725 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 12726 [(set_attr "length" "12")])
1fd4e8c1
RK		 12727
12728(define_insn ""
9ebbca7d 12729 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12730 (compare:CC
9ebbca7d
GK		 12731 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12732 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12733 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12734 (const_int 0)))
9ebbca7d 12735 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 12736 "TARGET_POWER"
1fd4e8c1 12737 "@
ca7f5001 12738 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12739 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12740 #
12741 #"
b19003d8 12742 [(set_attr "type" "compare")
9ebbca7d
GK		 12743 (set_attr "length" "12,12,16,16")])
12744
12745(define_split
12746 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12747 (compare:CC
12748 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12749 (match_operand:SI 2 "reg_or_short_operand" ""))
12750 (match_operand:SI 3 "gpc_reg_operand" ""))
12751 (const_int 0)))
12752 (clobber (match_scratch:SI 4 ""))]
12753 "TARGET_POWER && reload_completed"
12754 [(set (match_dup 4)
12755 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 12756 (match_dup 3)))
9ebbca7d
GK		 12757 (set (match_dup 0)
12758 (compare:CC (match_dup 4)
12759 (const_int 0)))]
12760 "")
1fd4e8c1
RK		 12761
12762(define_insn ""
097657c3 12763 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12764 (compare:CC
9ebbca7d
GK		 12765 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12766 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12767 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12768 (const_int 0)))
097657c3
AM		 12769 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12770 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12771 "TARGET_POWER"
1fd4e8c1 12772 "@
097657c3
AM		 12773 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12774 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12775 #
12776 #"
b19003d8 12777 [(set_attr "type" "compare")
9ebbca7d
GK		 12778 (set_attr "length" "12,12,16,16")])
12779
12780(define_split
097657c3 12781 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12782 (compare:CC
12783 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12784 (match_operand:SI 2 "reg_or_short_operand" ""))
12785 (match_operand:SI 3 "gpc_reg_operand" ""))
12786 (const_int 0)))
12787 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12788 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12789 "TARGET_POWER && reload_completed"
097657c3 12790 [(set (match_dup 0)
9ebbca7d 12791 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12792 (set (match_dup 4)
9ebbca7d
GK		 12793 (compare:CC (match_dup 0)
12794 (const_int 0)))]
12795 "")
1fd4e8c1
RK		 12796
12797(define_insn ""
cd2b37d9
RK		 12798 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12799 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12800 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 12801 "TARGET_POWER"
1fd4e8c1 12802 "@
ca7f5001
RK		 12803 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12804 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12805 [(set_attr "length" "12")])
1fd4e8c1 12806
a2dba291
DE		 12807(define_insn "*leu<mode>"
12808 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12809 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12810 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12811 ""
ca7f5001 12812 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 12813 [(set_attr "type" "three")
12814 (set_attr "length" "12")])
1fd4e8c1 12815
a2dba291 12816(define_insn "*leu<mode>_compare"
9ebbca7d 12817 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12818 (compare:CC
a2dba291
DE		 12819 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12820 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12821 (const_int 0)))
a2dba291
DE		 12822 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12823 (leu:P (match_dup 1) (match_dup 2)))]
12824 ""
9ebbca7d
GK		 12825 "@
12826 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12827 #"
b19003d8 12828 [(set_attr "type" "compare")
9ebbca7d
GK		 12829 (set_attr "length" "12,16")])
12830
12831(define_split
12832 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12833 (compare:CC
a2dba291
DE		 12834 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12835 (match_operand:P 2 "reg_or_short_operand" ""))
9ebbca7d 12836 (const_int 0)))
a2dba291
DE		 12837 (set (match_operand:P 0 "gpc_reg_operand" "")
12838 (leu:P (match_dup 1) (match_dup 2)))]
12839 "reload_completed"
9ebbca7d 12840 [(set (match_dup 0)
a2dba291 12841 (leu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 12842 (set (match_dup 3)
12843 (compare:CC (match_dup 0)
12844 (const_int 0)))]
12845 "")
1fd4e8c1 12846
a2dba291
DE		 12847(define_insn "*plus_leu<mode>"
12848 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12849 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12850 (match_operand:P 2 "reg_or_short_operand" "rI"))
12851 (match_operand:P 3 "gpc_reg_operand" "r")))]
12852 ""
80103f96 12853 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
943c15ed
DE		 12854 [(set_attr "type" "two")
12855 (set_attr "length" "8")])
1fd4e8c1
RK		 12856
12857(define_insn ""
9ebbca7d 12858 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12859 (compare:CC
9ebbca7d
GK		 12860 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12861 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12862 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12863 (const_int 0)))
9ebbca7d 12864 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12865 "TARGET_32BIT"
9ebbca7d
GK		 12866 "@
12867 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12868 #"
b19003d8 12869 [(set_attr "type" "compare")
9ebbca7d
GK		 12870 (set_attr "length" "8,12")])
12871
12872(define_split
12873 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12874 (compare:CC
12875 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12876 (match_operand:SI 2 "reg_or_short_operand" ""))
12877 (match_operand:SI 3 "gpc_reg_operand" ""))
12878 (const_int 0)))
12879 (clobber (match_scratch:SI 4 ""))]
683bdff7 12880 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12881 [(set (match_dup 4)
12882 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12883 (match_dup 3)))
12884 (set (match_dup 0)
12885 (compare:CC (match_dup 4)
12886 (const_int 0)))]
12887 "")
1fd4e8c1
RK		 12888
12889(define_insn ""
097657c3 12890 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12891 (compare:CC
9ebbca7d
GK		 12892 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12893 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12894 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12895 (const_int 0)))
097657c3
AM		 12896 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12897 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12898 "TARGET_32BIT"
9ebbca7d 12899 "@
097657c3 12900 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 12901 #"
b19003d8 12902 [(set_attr "type" "compare")
9ebbca7d
GK		 12903 (set_attr "length" "8,12")])
12904
12905(define_split
097657c3 12906 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12907 (compare:CC
12908 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12909 (match_operand:SI 2 "reg_or_short_operand" ""))
12910 (match_operand:SI 3 "gpc_reg_operand" ""))
12911 (const_int 0)))
12912 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12913 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12914 "TARGET_32BIT && reload_completed"
097657c3 12915 [(set (match_dup 0)
9ebbca7d 12916 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12917 (set (match_dup 4)
9ebbca7d
GK		 12918 (compare:CC (match_dup 0)
12919 (const_int 0)))]
12920 "")
1fd4e8c1 12921
a2dba291
DE		 12922(define_insn "*neg_leu<mode>"
12923 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12924 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12925 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12926 ""
ca7f5001 12927 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
943c15ed
DE		 12928 [(set_attr "type" "three")
12929 (set_attr "length" "12")])
1fd4e8c1 12930
a2dba291
DE		 12931(define_insn "*and_neg_leu<mode>"
12932 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12933 (and:P (neg:P
12934 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12935 (match_operand:P 2 "reg_or_short_operand" "rI")))
12936 (match_operand:P 3 "gpc_reg_operand" "r")))]
12937 ""
097657c3 12938 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 12939 [(set_attr "type" "three")
12940 (set_attr "length" "12")])
1fd4e8c1
RK		 12941
12942(define_insn ""
9ebbca7d 12943 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12944 (compare:CC
12945 (and:SI (neg:SI
9ebbca7d
GK		 12946 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12947 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12948 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12949 (const_int 0)))
9ebbca7d 12950 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12951 "TARGET_32BIT"
9ebbca7d
GK		 12952 "@
12953 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12954 #"
12955 [(set_attr "type" "compare")
12956 (set_attr "length" "12,16")])
12957
12958(define_split
12959 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12960 (compare:CC
12961 (and:SI (neg:SI
12962 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12963 (match_operand:SI 2 "reg_or_short_operand" "")))
12964 (match_operand:SI 3 "gpc_reg_operand" ""))
12965 (const_int 0)))
12966 (clobber (match_scratch:SI 4 ""))]
683bdff7 12967 "TARGET_32BIT && reload_completed"
9ebbca7d 12968 [(set (match_dup 4)
097657c3
AM		 12969 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12970 (match_dup 3)))
9ebbca7d
GK		 12971 (set (match_dup 0)
12972 (compare:CC (match_dup 4)
12973 (const_int 0)))]
12974 "")
1fd4e8c1
RK		 12975
12976(define_insn ""
097657c3 12977 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12978 (compare:CC
12979 (and:SI (neg:SI
9ebbca7d
GK		 12980 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12981 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12982 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12983 (const_int 0)))
097657c3
AM		 12984 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12985 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12986 "TARGET_32BIT"
9ebbca7d 12987 "@
097657c3 12988 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 12989 #"
b19003d8 12990 [(set_attr "type" "compare")
9ebbca7d
GK		 12991 (set_attr "length" "12,16")])
12992
12993(define_split
097657c3 12994 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12995 (compare:CC
12996 (and:SI (neg:SI
12997 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12998 (match_operand:SI 2 "reg_or_short_operand" "")))
12999 (match_operand:SI 3 "gpc_reg_operand" ""))
13000 (const_int 0)))
13001 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13002 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13003 "TARGET_32BIT && reload_completed"
097657c3
AM		 13004 [(set (match_dup 0)
13005 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13006 (match_dup 3)))
13007 (set (match_dup 4)
9ebbca7d
GK		 13008 (compare:CC (match_dup 0)
13009 (const_int 0)))]
13010 "")
1fd4e8c1
RK		 13011
13012(define_insn ""
cd2b37d9
RK		 13013 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13014 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13015 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 13016 "TARGET_POWER"
7f340546 13017 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13018 [(set_attr "length" "12")])
1fd4e8c1
RK		 13019
13020(define_insn ""
9ebbca7d 13021 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13022 (compare:CC
9ebbca7d
GK		 13023 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13024 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13025 (const_int 0)))
9ebbca7d 13026 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13027 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13028 "TARGET_POWER"
9ebbca7d
GK		 13029 "@
13030 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13031 #"
29ae5b89 13032 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13033 (set_attr "length" "12,16")])
13034
13035(define_split
13036 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13037 (compare:CC
13038 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13039 (match_operand:SI 2 "reg_or_short_operand" ""))
13040 (const_int 0)))
13041 (set (match_operand:SI 0 "gpc_reg_operand" "")
13042 (lt:SI (match_dup 1) (match_dup 2)))]
13043 "TARGET_POWER && reload_completed"
13044 [(set (match_dup 0)
13045 (lt:SI (match_dup 1) (match_dup 2)))
13046 (set (match_dup 3)
13047 (compare:CC (match_dup 0)
13048 (const_int 0)))]
13049 "")
1fd4e8c1
RK		 13050
13051(define_insn ""
097657c3 13052 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13053 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13054 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13055 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13056 "TARGET_POWER"
097657c3 13057 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13058 [(set_attr "length" "12")])
1fd4e8c1
RK		 13059
13060(define_insn ""
9ebbca7d 13061 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13062 (compare:CC
9ebbca7d
GK		 13063 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13064 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13065 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13066 (const_int 0)))
9ebbca7d 13067 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13068 "TARGET_POWER"
9ebbca7d
GK		 13069 "@
13070 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13071 #"
b19003d8 13072 [(set_attr "type" "compare")
9ebbca7d
GK		 13073 (set_attr "length" "12,16")])
13074
13075(define_split
13076 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13077 (compare:CC
13078 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13079 (match_operand:SI 2 "reg_or_short_operand" ""))
13080 (match_operand:SI 3 "gpc_reg_operand" ""))
13081 (const_int 0)))
13082 (clobber (match_scratch:SI 4 ""))]
13083 "TARGET_POWER && reload_completed"
13084 [(set (match_dup 4)
13085 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 13086 (match_dup 3)))
9ebbca7d
GK		 13087 (set (match_dup 0)
13088 (compare:CC (match_dup 4)
13089 (const_int 0)))]
13090 "")
1fd4e8c1
RK		 13091
13092(define_insn ""
097657c3 13093 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13094 (compare:CC
9ebbca7d
GK		 13095 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13096 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13097 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13098 (const_int 0)))
097657c3
AM		 13099 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13100 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13101 "TARGET_POWER"
9ebbca7d 13102 "@
097657c3 13103 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13104 #"
b19003d8 13105 [(set_attr "type" "compare")
9ebbca7d
GK		 13106 (set_attr "length" "12,16")])
13107
13108(define_split
097657c3 13109 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13110 (compare:CC
13111 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13112 (match_operand:SI 2 "reg_or_short_operand" ""))
13113 (match_operand:SI 3 "gpc_reg_operand" ""))
13114 (const_int 0)))
13115 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13116 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13117 "TARGET_POWER && reload_completed"
097657c3 13118 [(set (match_dup 0)
9ebbca7d 13119 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13120 (set (match_dup 4)
9ebbca7d
GK		 13121 (compare:CC (match_dup 0)
13122 (const_int 0)))]
13123 "")
1fd4e8c1
RK		 13124
13125(define_insn ""
cd2b37d9
RK		 13126 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13127 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13128 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13129 "TARGET_POWER"
13130 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13131 [(set_attr "length" "12")])
1fd4e8c1 13132
ce45ef46
DE		 13133(define_insn_and_split "*ltu<mode>"
13134 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13135 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13136 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13137 ""
c0600ecd 13138 "#"
ce45ef46
DE		 13139 ""
13140 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13141 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13142 "")
1fd4e8c1 13143
1e24ce83 13144(define_insn_and_split "*ltu<mode>_compare"
9ebbca7d 13145 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13146 (compare:CC
a2dba291
DE		 13147 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13148 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13149 (const_int 0)))
a2dba291
DE		 13150 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13151 (ltu:P (match_dup 1) (match_dup 2)))]
13152 ""
1e24ce83
DE		 13153 "#"
13154 ""
13155 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13156 (parallel [(set (match_dup 3)
13157 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13158 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13159 "")
1fd4e8c1 13160
a2dba291
DE		 13161(define_insn_and_split "*plus_ltu<mode>"
13162 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13163 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13164 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
1e24ce83 13165 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
a2dba291 13166 ""
c0600ecd 13167 "#"
04fa46cf 13168 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13169 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13170 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13171 "")
1fd4e8c1 13172
1e24ce83 13173(define_insn_and_split "*plus_ltu<mode>_compare"
097657c3 13174 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13175 (compare:CC
1e24ce83
DE		 13176 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13177 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13178 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13179 (const_int 0)))
1e24ce83
DE		 13180 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13181 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13182 ""
13183 "#"
13184 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13185 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13186 (parallel [(set (match_dup 4)
13187 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13188 (const_int 0)))
13189 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13190 "")
1fd4e8c1 13191
ce45ef46
DE		 13192(define_insn "*neg_ltu<mode>"
13193 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13194 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13195 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13196 ""
c0600ecd
DE		 13197 "@
13198 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13199 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
943c15ed 13200 [(set_attr "type" "two")
c0600ecd 13201 (set_attr "length" "8")])
1fd4e8c1
RK		 13202
13203(define_insn ""
cd2b37d9
RK		 13204 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13205 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 13206 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13207 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 13208 "TARGET_POWER"
13209 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 13210 [(set_attr "length" "12")])
1fd4e8c1 13211
9ebbca7d
GK		 13212(define_insn ""
13213 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13214 (compare:CC
9ebbca7d
GK		 13215 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13216 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13217 (const_int 0)))
9ebbca7d 13218 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13219 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 13220 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 13221 "TARGET_POWER"
9ebbca7d
GK		 13222 "@
13223 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13224 #"
13225 [(set_attr "type" "compare")
13226 (set_attr "length" "12,16")])
13227
13228(define_split
13229 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13230 (compare:CC
13231 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13232 (match_operand:SI 2 "reg_or_short_operand" ""))
13233 (const_int 0)))
13234 (set (match_operand:SI 0 "gpc_reg_operand" "")
13235 (ge:SI (match_dup 1) (match_dup 2)))
13236 (clobber (match_scratch:SI 3 ""))]
13237 "TARGET_POWER && reload_completed"
13238 [(parallel [(set (match_dup 0)
097657c3
AM		 13239 (ge:SI (match_dup 1) (match_dup 2)))
13240 (clobber (match_dup 3))])
9ebbca7d
GK		 13241 (set (match_dup 4)
13242 (compare:CC (match_dup 0)
13243 (const_int 0)))]
13244 "")
13245
1fd4e8c1 13246(define_insn ""
097657c3 13247 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13248 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13249 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13250 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13251 "TARGET_POWER"
097657c3 13252 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 13253 [(set_attr "length" "12")])
1fd4e8c1
RK		 13254
13255(define_insn ""
9ebbca7d 13256 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13257 (compare:CC
9ebbca7d
GK		 13258 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13259 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13260 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13261 (const_int 0)))
9ebbca7d 13262 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13263 "TARGET_POWER"
9ebbca7d
GK		 13264 "@
13265 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13266 #"
b19003d8 13267 [(set_attr "type" "compare")
9ebbca7d
GK		 13268 (set_attr "length" "12,16")])
13269
13270(define_split
13271 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13272 (compare:CC
13273 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13274 (match_operand:SI 2 "reg_or_short_operand" ""))
13275 (match_operand:SI 3 "gpc_reg_operand" ""))
13276 (const_int 0)))
13277 (clobber (match_scratch:SI 4 ""))]
13278 "TARGET_POWER && reload_completed"
13279 [(set (match_dup 4)
13280 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 13281 (match_dup 3)))
9ebbca7d
GK		 13282 (set (match_dup 0)
13283 (compare:CC (match_dup 4)
13284 (const_int 0)))]
13285 "")
1fd4e8c1
RK		 13286
13287(define_insn ""
097657c3 13288 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13289 (compare:CC
9ebbca7d
GK		 13290 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13291 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13292 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13293 (const_int 0)))
097657c3
AM		 13294 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13295 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13296 "TARGET_POWER"
9ebbca7d 13297 "@
097657c3 13298 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 13299 #"
b19003d8 13300 [(set_attr "type" "compare")
9ebbca7d
GK		 13301 (set_attr "length" "12,16")])
13302
13303(define_split
097657c3 13304 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13305 (compare:CC
13306 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13307 (match_operand:SI 2 "reg_or_short_operand" ""))
13308 (match_operand:SI 3 "gpc_reg_operand" ""))
13309 (const_int 0)))
13310 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13311 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13312 "TARGET_POWER && reload_completed"
097657c3 13313 [(set (match_dup 0)
9ebbca7d 13314 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13315 (set (match_dup 4)
9ebbca7d
GK		 13316 (compare:CC (match_dup 0)
13317 (const_int 0)))]
13318 "")
1fd4e8c1
RK		 13319
13320(define_insn ""
cd2b37d9
RK		 13321 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13322 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13323 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13324 "TARGET_POWER"
13325 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 13326 [(set_attr "length" "12")])
1fd4e8c1 13327
a2dba291
DE		 13328(define_insn "*geu<mode>"
13329 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13330 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13331 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13332 ""
1fd4e8c1 13333 "@
ca7f5001
RK		 13334 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13335 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 13336 [(set_attr "type" "three")
13337 (set_attr "length" "12")])
1fd4e8c1 13338
a2dba291 13339(define_insn "*geu<mode>_compare"
9ebbca7d 13340 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13341 (compare:CC
a2dba291
DE		 13342 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13343 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13344 (const_int 0)))
a2dba291
DE		 13345 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13346 (geu:P (match_dup 1) (match_dup 2)))]
13347 ""
1fd4e8c1 13348 "@
ca7f5001 13349 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 13350 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13351 #
13352 #"
b19003d8 13353 [(set_attr "type" "compare")
9ebbca7d
GK		 13354 (set_attr "length" "12,12,16,16")])
13355
13356(define_split
13357 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13358 (compare:CC
a2dba291
DE		 13359 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13360 (match_operand:P 2 "reg_or_neg_short_operand" ""))
9ebbca7d 13361 (const_int 0)))
a2dba291
DE		 13362 (set (match_operand:P 0 "gpc_reg_operand" "")
13363 (geu:P (match_dup 1) (match_dup 2)))]
13364 "reload_completed"
9ebbca7d 13365 [(set (match_dup 0)
a2dba291 13366 (geu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 13367 (set (match_dup 3)
13368 (compare:CC (match_dup 0)
13369 (const_int 0)))]
13370 "")
f9562f27 13371
a2dba291
DE		 13372(define_insn "*plus_geu<mode>"
13373 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13374 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13375 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13376 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13377 ""
1fd4e8c1 13378 "@
80103f96
FS		 13379 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13380 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
943c15ed
DE		 13381 [(set_attr "type" "two")
13382 (set_attr "length" "8")])
1fd4e8c1
RK		 13383
13384(define_insn ""
9ebbca7d 13385 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13386 (compare:CC
9ebbca7d
GK		 13387 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13388 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13389 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13390 (const_int 0)))
9ebbca7d 13391 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13392 "TARGET_32BIT"
1fd4e8c1 13393 "@
ca7f5001 13394 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13395 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13396 #
13397 #"
b19003d8 13398 [(set_attr "type" "compare")
9ebbca7d
GK		 13399 (set_attr "length" "8,8,12,12")])
13400
13401(define_split
13402 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13403 (compare:CC
13404 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13405 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13406 (match_operand:SI 3 "gpc_reg_operand" ""))
13407 (const_int 0)))
13408 (clobber (match_scratch:SI 4 ""))]
683bdff7 13409 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13410 [(set (match_dup 4)
13411 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13412 (match_dup 3)))
13413 (set (match_dup 0)
13414 (compare:CC (match_dup 4)
13415 (const_int 0)))]
13416 "")
1fd4e8c1
RK		 13417
13418(define_insn ""
097657c3 13419 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13420 (compare:CC
9ebbca7d
GK		 13421 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13422 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13423 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13424 (const_int 0)))
097657c3
AM		 13425 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13426 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13427 "TARGET_32BIT"
1fd4e8c1 13428 "@
097657c3
AM		 13429 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13430 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 13431 #
13432 #"
b19003d8 13433 [(set_attr "type" "compare")
9ebbca7d
GK		 13434 (set_attr "length" "8,8,12,12")])
13435
13436(define_split
097657c3 13437 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13438 (compare:CC
13439 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13440 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13441 (match_operand:SI 3 "gpc_reg_operand" ""))
13442 (const_int 0)))
13443 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13444 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13445 "TARGET_32BIT && reload_completed"
097657c3 13446 [(set (match_dup 0)
9ebbca7d 13447 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13448 (set (match_dup 4)
9ebbca7d
GK		 13449 (compare:CC (match_dup 0)
13450 (const_int 0)))]
13451 "")
1fd4e8c1 13452
a2dba291
DE		 13453(define_insn "*neg_geu<mode>"
13454 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13455 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13456 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13457 ""
1fd4e8c1 13458 "@
ca7f5001 13459 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 13460 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
943c15ed
DE		 13461 [(set_attr "type" "three")
13462 (set_attr "length" "12")])
1fd4e8c1 13463
a2dba291
DE		 13464(define_insn "*and_neg_geu<mode>"
13465 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13466 (and:P (neg:P
13467 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13468 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13469 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13470 ""
1fd4e8c1 13471 "@
097657c3
AM		 13472 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13473 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 13474 [(set_attr "type" "three")
13475 (set_attr "length" "12")])
1fd4e8c1
RK		 13476
13477(define_insn ""
9ebbca7d 13478 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13479 (compare:CC
13480 (and:SI (neg:SI
9ebbca7d
GK		 13481 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13482 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13483 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13484 (const_int 0)))
9ebbca7d 13485 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13486 "TARGET_32BIT"
1fd4e8c1 13487 "@
ca7f5001 13488 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 13489 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13490 #
13491 #"
b19003d8 13492 [(set_attr "type" "compare")
9ebbca7d
GK		 13493 (set_attr "length" "12,12,16,16")])
13494
13495(define_split
13496 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13497 (compare:CC
13498 (and:SI (neg:SI
13499 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13500 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13501 (match_operand:SI 3 "gpc_reg_operand" ""))
13502 (const_int 0)))
13503 (clobber (match_scratch:SI 4 ""))]
683bdff7 13504 "TARGET_32BIT && reload_completed"
9ebbca7d 13505 [(set (match_dup 4)
097657c3
AM		 13506 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13507 (match_dup 3)))
9ebbca7d
GK		 13508 (set (match_dup 0)
13509 (compare:CC (match_dup 4)
13510 (const_int 0)))]
13511 "")
1fd4e8c1
RK		 13512
13513(define_insn ""
097657c3 13514 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13515 (compare:CC
13516 (and:SI (neg:SI
9ebbca7d
GK		 13517 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13518 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13519 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13520 (const_int 0)))
097657c3
AM		 13521 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13522 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13523 "TARGET_32BIT"
1fd4e8c1 13524 "@
097657c3
AM		 13525 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13526 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 13527 #
13528 #"
b19003d8 13529 [(set_attr "type" "compare")
9ebbca7d
GK		 13530 (set_attr "length" "12,12,16,16")])
13531
13532(define_split
097657c3 13533 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13534 (compare:CC
13535 (and:SI (neg:SI
13536 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13537 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13538 (match_operand:SI 3 "gpc_reg_operand" ""))
13539 (const_int 0)))
13540 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13541 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13542 "TARGET_32BIT && reload_completed"
097657c3 13543 [(set (match_dup 0)
9ebbca7d 13544 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 13545 (set (match_dup 4)
9ebbca7d
GK		 13546 (compare:CC (match_dup 0)
13547 (const_int 0)))]
13548 "")
1fd4e8c1 13549
1fd4e8c1 13550(define_insn ""
cd2b37d9
RK		 13551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13552 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13553 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 13554 "TARGET_POWER"
13555 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13556 [(set_attr "length" "12")])
1fd4e8c1
RK		 13557
13558(define_insn ""
9ebbca7d 13559 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13560 (compare:CC
9ebbca7d
GK		 13561 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13562 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 13563 (const_int 0)))
9ebbca7d 13564 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13565 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13566 "TARGET_POWER"
9ebbca7d
GK		 13567 "@
13568 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13569 #"
29ae5b89 13570 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13571 (set_attr "length" "12,16")])
13572
13573(define_split
13574 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13575 (compare:CC
13576 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13577 (match_operand:SI 2 "reg_or_short_operand" ""))
13578 (const_int 0)))
13579 (set (match_operand:SI 0 "gpc_reg_operand" "")
13580 (gt:SI (match_dup 1) (match_dup 2)))]
13581 "TARGET_POWER && reload_completed"
13582 [(set (match_dup 0)
13583 (gt:SI (match_dup 1) (match_dup 2)))
13584 (set (match_dup 3)
13585 (compare:CC (match_dup 0)
13586 (const_int 0)))]
13587 "")
1fd4e8c1 13588
d0515b39 13589(define_insn "*plus_gt0<mode>"
a2dba291
DE		 13590 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13591 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13592 (const_int 0))
13593 (match_operand:P 2 "gpc_reg_operand" "r")))]
13594 ""
80103f96 13595 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
943c15ed
DE		 13596 [(set_attr "type" "three")
13597 (set_attr "length" "12")])
1fd4e8c1
RK		 13598
13599(define_insn ""
9ebbca7d 13600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13601 (compare:CC
9ebbca7d 13602 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13603 (const_int 0))
9ebbca7d 13604 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 13605 (const_int 0)))
9ebbca7d 13606 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 13607 "TARGET_32BIT"
9ebbca7d
GK		 13608 "@
13609 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13610 #"
b19003d8 13611 [(set_attr "type" "compare")
9ebbca7d
GK		 13612 (set_attr "length" "12,16")])
13613
13614(define_split
13615 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13616 (compare:CC
13617 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13618 (const_int 0))
13619 (match_operand:SI 2 "gpc_reg_operand" ""))
13620 (const_int 0)))
13621 (clobber (match_scratch:SI 3 ""))]
683bdff7 13622 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13623 [(set (match_dup 3)
13624 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13625 (match_dup 2)))
13626 (set (match_dup 0)
13627 (compare:CC (match_dup 3)
13628 (const_int 0)))]
13629 "")
1fd4e8c1 13630
f9562f27 13631(define_insn ""
9ebbca7d 13632 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 13633 (compare:CC
9ebbca7d 13634 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13635 (const_int 0))
9ebbca7d 13636 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13637 (const_int 0)))
9ebbca7d 13638 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 13639 "TARGET_64BIT"
9ebbca7d
GK		 13640 "@
13641 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13642 #"
f9562f27 13643 [(set_attr "type" "compare")
9ebbca7d
GK		 13644 (set_attr "length" "12,16")])
13645
13646(define_split
13647 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13648 (compare:CC
13649 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13650 (const_int 0))
13651 (match_operand:DI 2 "gpc_reg_operand" ""))
13652 (const_int 0)))
13653 (clobber (match_scratch:DI 3 ""))]
683bdff7 13654 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13655 [(set (match_dup 3)
13656 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 13657 (match_dup 2)))
9ebbca7d
GK		 13658 (set (match_dup 0)
13659 (compare:CC (match_dup 3)
13660 (const_int 0)))]
13661 "")
f9562f27 13662
1fd4e8c1 13663(define_insn ""
097657c3 13664 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 13665 (compare:CC
13666 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13667 (const_int 0))
13668 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13669 (const_int 0)))
097657c3
AM		 13670 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13671 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13672 "TARGET_32BIT"
9ebbca7d 13673 "@
097657c3 13674 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 13675 #"
13676 [(set_attr "type" "compare")
13677 (set_attr "length" "12,16")])
13678
13679(define_split
097657c3 13680 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 13681 (compare:CC
9ebbca7d 13682 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 13683 (const_int 0))
9ebbca7d 13684 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 13685 (const_int 0)))
9ebbca7d 13686 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13687 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13688 "TARGET_32BIT && reload_completed"
097657c3 13689 [(set (match_dup 0)
9ebbca7d 13690 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13691 (set (match_dup 3)
9ebbca7d
GK		 13692 (compare:CC (match_dup 0)
13693 (const_int 0)))]
13694 "")
1fd4e8c1 13695
f9562f27 13696(define_insn ""
097657c3 13697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13698 (compare:CC
9ebbca7d 13699 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13700 (const_int 0))
9ebbca7d 13701 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13702 (const_int 0)))
097657c3
AM		 13703 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13704 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13705 "TARGET_64BIT"
9ebbca7d 13706 "@
097657c3 13707 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 13708 #"
f9562f27 13709 [(set_attr "type" "compare")
9ebbca7d
GK		 13710 (set_attr "length" "12,16")])
13711
13712(define_split
097657c3 13713 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13714 (compare:CC
13715 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13716 (const_int 0))
13717 (match_operand:DI 2 "gpc_reg_operand" ""))
13718 (const_int 0)))
13719 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13720 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13721 "TARGET_64BIT && reload_completed"
097657c3 13722 [(set (match_dup 0)
9ebbca7d 13723 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13724 (set (match_dup 3)
9ebbca7d
GK		 13725 (compare:CC (match_dup 0)
13726 (const_int 0)))]
13727 "")
f9562f27 13728
1fd4e8c1 13729(define_insn ""
097657c3 13730 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13731 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13732 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 13733 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13734 "TARGET_POWER"
097657c3 13735 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13736 [(set_attr "length" "12")])
1fd4e8c1
RK		 13737
13738(define_insn ""
9ebbca7d 13739 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13740 (compare:CC
9ebbca7d
GK		 13741 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13742 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13743 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13744 (const_int 0)))
9ebbca7d 13745 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13746 "TARGET_POWER"
9ebbca7d
GK		 13747 "@
13748 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13749 #"
b19003d8 13750 [(set_attr "type" "compare")
9ebbca7d
GK		 13751 (set_attr "length" "12,16")])
13752
13753(define_split
13754 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13755 (compare:CC
13756 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13757 (match_operand:SI 2 "reg_or_short_operand" ""))
13758 (match_operand:SI 3 "gpc_reg_operand" ""))
13759 (const_int 0)))
13760 (clobber (match_scratch:SI 4 ""))]
13761 "TARGET_POWER && reload_completed"
13762 [(set (match_dup 4)
097657c3 13763 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 13764 (set (match_dup 0)
13765 (compare:CC (match_dup 4)
13766 (const_int 0)))]
13767 "")
1fd4e8c1
RK		 13768
13769(define_insn ""
097657c3 13770 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13771 (compare:CC
9ebbca7d
GK		 13772 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13773 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13774 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13775 (const_int 0)))
097657c3
AM		 13776 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13777 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13778 "TARGET_POWER"
9ebbca7d 13779 "@
097657c3 13780 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13781 #"
b19003d8 13782 [(set_attr "type" "compare")
9ebbca7d
GK		 13783 (set_attr "length" "12,16")])
13784
13785(define_split
097657c3 13786 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13787 (compare:CC
13788 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13789 (match_operand:SI 2 "reg_or_short_operand" ""))
13790 (match_operand:SI 3 "gpc_reg_operand" ""))
13791 (const_int 0)))
13792 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13793 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13794 "TARGET_POWER && reload_completed"
097657c3 13795 [(set (match_dup 0)
9ebbca7d 13796 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13797 (set (match_dup 4)
9ebbca7d
GK		 13798 (compare:CC (match_dup 0)
13799 (const_int 0)))]
13800 "")
1fd4e8c1 13801
1fd4e8c1 13802(define_insn ""
cd2b37d9
RK		 13803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13804 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13805 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 13806 "TARGET_POWER"
13807 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13808 [(set_attr "length" "12")])
1fd4e8c1 13809
ce45ef46
DE		 13810(define_insn_and_split "*gtu<mode>"
13811 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13812 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13813 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13814 ""
c0600ecd 13815 "#"
ce45ef46
DE		 13816 ""
13817 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13818 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13819 "")
f9562f27 13820
1e24ce83 13821(define_insn_and_split "*gtu<mode>_compare"
9ebbca7d 13822 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13823 (compare:CC
a2dba291
DE		 13824 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13825 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13826 (const_int 0)))
a2dba291
DE		 13827 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13828 (gtu:P (match_dup 1) (match_dup 2)))]
13829 ""
1e24ce83
DE		 13830 "#"
13831 ""
13832 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13833 (parallel [(set (match_dup 3)
13834 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13835 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13836 "")
f9562f27 13837
1e24ce83 13838(define_insn_and_split "*plus_gtu<mode>"
a2dba291
DE		 13839 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13840 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13841 (match_operand:P 2 "reg_or_short_operand" "rI"))
13842 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13843 ""
c0600ecd 13844 "#"
04fa46cf 13845 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13846 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13847 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13848 "")
f9562f27 13849
1e24ce83 13850(define_insn_and_split "*plus_gtu<mode>_compare"
097657c3 13851 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13852 (compare:CC
1e24ce83
DE		 13853 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13854 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13855 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13856 (const_int 0)))
1e24ce83
DE		 13857 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13858 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13859 ""
13860 "#"
13861 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13862 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13863 (parallel [(set (match_dup 4)
13864 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13865 (const_int 0)))
13866 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13867 "")
f9562f27 13868
ce45ef46
DE		 13869(define_insn "*neg_gtu<mode>"
13870 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13871 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13872 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13873 ""
ca7f5001 13874 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
943c15ed 13875 [(set_attr "type" "two")
c0600ecd 13876 (set_attr "length" "8")])
f9562f27 13877
1fd4e8c1
RK		 13878\f
13879;; Define both directions of branch and return. If we need a reload
13880;; register, we'd rather use CR0 since it is much easier to copy a
13881;; register CC value to there.
13882
13883(define_insn ""
13884 [(set (pc)
13885 (if_then_else (match_operator 1 "branch_comparison_operator"
13886 [(match_operand 2
b54cf83a 13887 "cc_reg_operand" "y")
1fd4e8c1
RK		 13888 (const_int 0)])
13889 (label_ref (match_operand 0 "" ""))
13890 (pc)))]
13891 ""
b19003d8
RK		 13892 "*
13893{
12a4e8c5 13894 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 13895}"
13896 [(set_attr "type" "branch")])
13897
1fd4e8c1
RK		 13898(define_insn ""
13899 [(set (pc)
13900 (if_then_else (match_operator 0 "branch_comparison_operator"
13901 [(match_operand 1
b54cf83a 13902 "cc_reg_operand" "y")
1fd4e8c1
RK		 13903 (const_int 0)])
13904 (return)
13905 (pc)))]
13906 "direct_return ()"
12a4e8c5
GK		 13907 "*
13908{
13909 return output_cbranch (operands[0], NULL, 0, insn);
13910}"
9c6fdb46 13911 [(set_attr "type" "jmpreg")
39a10a29 13912 (set_attr "length" "4")])
1fd4e8c1
RK		 13913
13914(define_insn ""
13915 [(set (pc)
13916 (if_then_else (match_operator 1 "branch_comparison_operator"
13917 [(match_operand 2
b54cf83a 13918 "cc_reg_operand" "y")
1fd4e8c1
RK		 13919 (const_int 0)])
13920 (pc)
13921 (label_ref (match_operand 0 "" ""))))]
13922 ""
b19003d8
RK		 13923 "*
13924{
12a4e8c5 13925 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 13926}"
13927 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13928
13929(define_insn ""
13930 [(set (pc)
13931 (if_then_else (match_operator 0 "branch_comparison_operator"
13932 [(match_operand 1
b54cf83a 13933 "cc_reg_operand" "y")
1fd4e8c1
RK		 13934 (const_int 0)])
13935 (pc)
13936 (return)))]
13937 "direct_return ()"
12a4e8c5
GK		 13938 "*
13939{
13940 return output_cbranch (operands[0], NULL, 1, insn);
13941}"
9c6fdb46 13942 [(set_attr "type" "jmpreg")
39a10a29
GK		 13943 (set_attr "length" "4")])
13944
13945;; Logic on condition register values.
13946
13947; This pattern matches things like
13948; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13949; (eq:SI (reg:CCFP 68) (const_int 0)))
13950; (const_int 1)))
13951; which are generated by the branch logic.
b54cf83a 13952; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29 13953
423c1189 13954(define_insn "*cceq_ior_compare"
b54cf83a 13955 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13956 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 13957 [(match_operator:SI 2
39a10a29
GK		 13958 "branch_positive_comparison_operator"
13959 [(match_operand 3
b54cf83a 13960 "cc_reg_operand" "y,y")
39a10a29 13961 (const_int 0)])
b54cf83a 13962 (match_operator:SI 4
39a10a29
GK		 13963 "branch_positive_comparison_operator"
13964 [(match_operand 5
b54cf83a 13965 "cc_reg_operand" "0,y")
39a10a29
GK		 13966 (const_int 0)])])
13967 (const_int 1)))]
24fab1d3 13968 ""
39a10a29 13969 "cr%q1 %E0,%j2,%j4"
b54cf83a 13970 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13971
13972; Why is the constant -1 here, but 1 in the previous pattern?
13973; Because ~1 has all but the low bit set.
13974(define_insn ""
b54cf83a 13975 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13976 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 13977 [(not:SI (match_operator:SI 2
39a10a29
GK		 13978 "branch_positive_comparison_operator"
13979 [(match_operand 3
b54cf83a 13980 "cc_reg_operand" "y,y")
39a10a29
GK		 13981 (const_int 0)]))
13982 (match_operator:SI 4
13983 "branch_positive_comparison_operator"
13984 [(match_operand 5
b54cf83a 13985 "cc_reg_operand" "0,y")
39a10a29
GK		 13986 (const_int 0)])])
13987 (const_int -1)))]
13988 ""
13989 "cr%q1 %E0,%j2,%j4"
b54cf83a 13990 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29 13991
423c1189 13992(define_insn "*cceq_rev_compare"
b54cf83a 13993 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 13994 (compare:CCEQ (match_operator:SI 1
39a10a29 13995 "branch_positive_comparison_operator"
6c873122 13996 [(match_operand 2
b54cf83a 13997 "cc_reg_operand" "0,y")
39a10a29
GK		 13998 (const_int 0)])
13999 (const_int 0)))]
423c1189 14000 ""
251b3667 14001 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 14002 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 14003
14004;; If we are comparing the result of two comparisons, this can be done
14005;; using creqv or crxor.
14006
14007(define_insn_and_split ""
14008 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14009 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14010 [(match_operand 2 "cc_reg_operand" "y")
14011 (const_int 0)])
14012 (match_operator 3 "branch_comparison_operator"
14013 [(match_operand 4 "cc_reg_operand" "y")
14014 (const_int 0)])))]
14015 ""
14016 "#"
14017 ""
14018 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14019 (match_dup 5)))]
14020 "
14021{
14022 int positive_1, positive_2;
14023
364849ee
DE		 14024 positive_1 = branch_positive_comparison_operator (operands[1],
14025 GET_MODE (operands[1]));
14026 positive_2 = branch_positive_comparison_operator (operands[3],
14027 GET_MODE (operands[3]));
39a10a29
GK		 14028
14029 if (! positive_1)
1c563bed 14030 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
0f4c242b
KH		 14031 GET_CODE (operands[1])),
14032 SImode,
14033 operands[2], const0_rtx);
39a10a29 14034 else if (GET_MODE (operands[1]) != SImode)
0f4c242b
KH		 14035 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14036 operands[2], const0_rtx);
39a10a29
GK		 14037
14038 if (! positive_2)
1c563bed 14039 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
0f4c242b
KH		 14040 GET_CODE (operands[3])),
14041 SImode,
14042 operands[4], const0_rtx);
39a10a29 14043 else if (GET_MODE (operands[3]) != SImode)
0f4c242b
KH		 14044 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14045 operands[4], const0_rtx);
39a10a29
GK		 14046
14047 if (positive_1 == positive_2)
251b3667
DE		 14048 {
14049 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14050 operands[5] = constm1_rtx;
14051 }
14052 else
14053 {
14054 operands[5] = const1_rtx;
14055 }
39a10a29 14056}")
1fd4e8c1
RK		 14057
14058;; Unconditional branch and return.
14059
14060(define_insn "jump"
14061 [(set (pc)
14062 (label_ref (match_operand 0 "" "")))]
14063 ""
b7ff3d82
DE		 14064 "b %l0"
14065 [(set_attr "type" "branch")])
1fd4e8c1
RK		 14066
14067(define_insn "return"
14068 [(return)]
14069 "direct_return ()"
324e52cc
TG		 14070 "{br|blr}"
14071 [(set_attr "type" "jmpreg")])
1fd4e8c1 14072
0ad91047 14073(define_expand "indirect_jump"
4ae234b0 14074 [(set (pc) (match_operand 0 "register_operand" ""))])
0ad91047 14075
4ae234b0
GK		 14076(define_insn "*indirect_jump<mode>"
14077 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14078 ""
b92b324d
DE		 14079 "@
14080 bctr
14081 {br|blr}"
324e52cc 14082 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14083
14084;; Table jump for switch statements:
14085(define_expand "tablejump"
e6ca2c17
DE		 14086 [(use (match_operand 0 "" ""))
14087 (use (label_ref (match_operand 1 "" "")))]
14088 ""
14089 "
14090{
14091 if (TARGET_32BIT)
14092 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14093 else
14094 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14095 DONE;
14096}")
14097
14098(define_expand "tablejumpsi"
1fd4e8c1
RK		 14099 [(set (match_dup 3)
14100 (plus:SI (match_operand:SI 0 "" "")
14101 (match_dup 2)))
14102 (parallel [(set (pc) (match_dup 3))
14103 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14104 "TARGET_32BIT"
1fd4e8c1
RK		 14105 "
14106{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 14107 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 14108 operands[3] = gen_reg_rtx (SImode);
14109}")
14110
e6ca2c17 14111(define_expand "tablejumpdi"
6ae08853 14112 [(set (match_dup 4)
e42ac3de 14113 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
9ebbca7d
GK		 14114 (set (match_dup 3)
14115 (plus:DI (match_dup 4)
e6ca2c17
DE		 14116 (match_dup 2)))
14117 (parallel [(set (pc) (match_dup 3))
14118 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14119 "TARGET_64BIT"
e6ca2c17 14120 "
9ebbca7d 14121{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 14122 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 14123 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 14124}")
14125
ce45ef46 14126(define_insn "*tablejump<mode>_internal1"
1fd4e8c1 14127 [(set (pc)
4ae234b0 14128 (match_operand:P 0 "register_operand" "c,*l"))
1fd4e8c1 14129 (use (label_ref (match_operand 1 "" "")))]
4ae234b0 14130 ""
c859cda6
DJ		 14131 "@
14132 bctr
14133 {br|blr}"
a6845123 14134 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14135
14136(define_insn "nop"
14137 [(const_int 0)]
14138 ""
ca7f5001 14139 "{cror 0,0,0|nop}")
1fd4e8c1 14140\f
7e69e155 14141;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 14142;; so loop.c knows what to generate.
14143
5527bf14
RH		 14144(define_expand "doloop_end"
14145 [(use (match_operand 0 "" "")) ; loop pseudo
14146 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14147 (use (match_operand 2 "" "")) ; max iterations
14148 (use (match_operand 3 "" "")) ; loop level
14149 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 14150 ""
14151 "
14152{
5527bf14
RH		 14153 /* Only use this on innermost loops. */
14154 if (INTVAL (operands[3]) > 1)
14155 FAIL;
683bdff7 14156 if (TARGET_64BIT)
5527bf14
RH		 14157 {
14158 if (GET_MODE (operands[0]) != DImode)
14159 FAIL;
14160 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14161 }
0ad91047 14162 else
5527bf14
RH		 14163 {
14164 if (GET_MODE (operands[0]) != SImode)
14165 FAIL;
14166 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14167 }
0ad91047
DE		 14168 DONE;
14169}")
14170
4ae234b0 14171(define_expand "ctr<mode>"
3cb999d8 14172 [(parallel [(set (pc)
4ae234b0 14173 (if_then_else (ne (match_operand:P 0 "register_operand" "")
3cb999d8
DE		 14174 (const_int 1))
14175 (label_ref (match_operand 1 "" ""))
14176 (pc)))
b6c9286a 14177 (set (match_dup 0)
4ae234b0 14178 (plus:P (match_dup 0)
b6c9286a 14179 (const_int -1)))
5f81043f 14180 (clobber (match_scratch:CC 2 ""))
4ae234b0
GK		 14181 (clobber (match_scratch:P 3 ""))])]
14182 ""
61c07d3c 14183 "")
c225ba7b 14184
1fd4e8c1
RK		 14185;; We need to be able to do this for any operand, including MEM, or we
14186;; will cause reload to blow up since we don't allow output reloads on
7e69e155 14187;; JUMP_INSNs.
0ad91047 14188;; For the length attribute to be calculated correctly, the
5f81043f
RK		 14189;; label MUST be operand 0.
14190
4ae234b0 14191(define_insn "*ctr<mode>_internal1"
0ad91047 14192 [(set (pc)
4ae234b0 14193 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14194 (const_int 1))
14195 (label_ref (match_operand 0 "" ""))
14196 (pc)))
4ae234b0
GK		 14197 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14198 (plus:P (match_dup 1)
0ad91047 14199 (const_int -1)))
43b68ce5 14200 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14201 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14202 ""
0ad91047
DE		 14203 "*
14204{
14205 if (which_alternative != 0)
14206 return \"#\";
856a6884 14207 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14208 return \"{bdn|bdnz} %l0\";
14209 else
f607bc57 14210 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14211}"
14212 [(set_attr "type" "branch")
5a195cb5 14213 (set_attr "length" "*,12,16,16")])
0ad91047 14214
4ae234b0 14215(define_insn "*ctr<mode>_internal2"
0ad91047 14216 [(set (pc)
4ae234b0 14217 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14218 (const_int 1))
14219 (pc)
14220 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14221 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14222 (plus:P (match_dup 1)
0ad91047 14223 (const_int -1)))
43b68ce5 14224 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14225 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14226 ""
5f81043f
RK		 14227 "*
14228{
14229 if (which_alternative != 0)
14230 return \"#\";
856a6884 14231 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14232 return \"bdz %l0\";
14233 else
f607bc57 14234 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14235}"
14236 [(set_attr "type" "branch")
5a195cb5 14237 (set_attr "length" "*,12,16,16")])
5f81043f 14238
0ad91047
DE		 14239;; Similar but use EQ
14240
4ae234b0 14241(define_insn "*ctr<mode>_internal5"
5f81043f 14242 [(set (pc)
4ae234b0 14243 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14244 (const_int 1))
a6845123 14245 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14246 (pc)))
4ae234b0
GK		 14247 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14248 (plus:P (match_dup 1)
0ad91047 14249 (const_int -1)))
43b68ce5 14250 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14251 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14252 ""
0ad91047
DE		 14253 "*
14254{
14255 if (which_alternative != 0)
14256 return \"#\";
856a6884 14257 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14258 return \"bdz %l0\";
14259 else
f607bc57 14260 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14261}"
14262 [(set_attr "type" "branch")
5a195cb5 14263 (set_attr "length" "*,12,16,16")])
0ad91047 14264
4ae234b0 14265(define_insn "*ctr<mode>_internal6"
0ad91047 14266 [(set (pc)
4ae234b0 14267 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14268 (const_int 1))
14269 (pc)
14270 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14271 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14272 (plus:P (match_dup 1)
0ad91047 14273 (const_int -1)))
43b68ce5 14274 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14275 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14276 ""
5f81043f
RK		 14277 "*
14278{
14279 if (which_alternative != 0)
14280 return \"#\";
856a6884 14281 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14282 return \"{bdn|bdnz} %l0\";
14283 else
f607bc57 14284 return \"bdz $+8\;b %l0\";
5f81043f
RK		 14285}"
14286 [(set_attr "type" "branch")
5a195cb5 14287 (set_attr "length" "*,12,16,16")])
5f81043f 14288
0ad91047
DE		 14289;; Now the splitters if we could not allocate the CTR register
14290
1fd4e8c1
RK		 14291(define_split
14292 [(set (pc)
14293 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14294 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14295 (const_int 1)])
61c07d3c
DE		 14296 (match_operand 5 "" "")
14297 (match_operand 6 "" "")))
4ae234b0
GK		 14298 (set (match_operand:P 0 "gpc_reg_operand" "")
14299 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14300 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14301 (clobber (match_scratch:P 4 ""))]
14302 "reload_completed"
0ad91047 14303 [(parallel [(set (match_dup 3)
4ae234b0 14304 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14305 (const_int -1))
14306 (const_int 0)))
14307 (set (match_dup 0)
4ae234b0 14308 (plus:P (match_dup 1)
0ad91047 14309 (const_int -1)))])
61c07d3c
DE		 14310 (set (pc) (if_then_else (match_dup 7)
14311 (match_dup 5)
14312 (match_dup 6)))]
0ad91047 14313 "
0f4c242b
KH		 14314{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14315 operands[3], const0_rtx); }")
0ad91047
DE		 14316
14317(define_split
14318 [(set (pc)
14319 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14320 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14321 (const_int 1)])
61c07d3c
DE		 14322 (match_operand 5 "" "")
14323 (match_operand 6 "" "")))
4ae234b0
GK		 14324 (set (match_operand:P 0 "nonimmediate_operand" "")
14325 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14326 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14327 (clobber (match_scratch:P 4 ""))]
14328 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
0ad91047 14329 [(parallel [(set (match_dup 3)
4ae234b0 14330 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14331 (const_int -1))
14332 (const_int 0)))
14333 (set (match_dup 4)
4ae234b0 14334 (plus:P (match_dup 1)
0ad91047
DE		 14335 (const_int -1)))])
14336 (set (match_dup 0)
14337 (match_dup 4))
61c07d3c
DE		 14338 (set (pc) (if_then_else (match_dup 7)
14339 (match_dup 5)
14340 (match_dup 6)))]
0ad91047 14341 "
0f4c242b
KH		 14342{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14343 operands[3], const0_rtx); }")
e0cd0770
JC		 14344\f
14345(define_insn "trap"
14346 [(trap_if (const_int 1) (const_int 0))]
14347 ""
44cd321e
PS		 14348 "{t 31,0,0|trap}"
14349 [(set_attr "type" "trap")])
e0cd0770
JC		 14350
14351(define_expand "conditional_trap"
14352 [(trap_if (match_operator 0 "trap_comparison_operator"
14353 [(match_dup 2) (match_dup 3)])
14354 (match_operand 1 "const_int_operand" ""))]
14355 ""
14356 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14357 operands[2] = rs6000_compare_op0;
14358 operands[3] = rs6000_compare_op1;")
14359
14360(define_insn ""
14361 [(trap_if (match_operator 0 "trap_comparison_operator"
4ae234b0
GK		 14362 [(match_operand:GPR 1 "register_operand" "r")
14363 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
e0cd0770
JC		 14364 (const_int 0))]
14365 ""
44cd321e
PS		 14366 "{t|t<wd>}%V0%I2 %1,%2"
14367 [(set_attr "type" "trap")])
9ebbca7d
GK		 14368\f
14369;; Insns related to generating the function prologue and epilogue.
14370
14371(define_expand "prologue"
14372 [(use (const_int 0))]
14373 "TARGET_SCHED_PROLOG"
14374 "
14375{
14376 rs6000_emit_prologue ();
14377 DONE;
14378}")
14379
2c4a9cff
DE		 14380(define_insn "*movesi_from_cr_one"
14381 [(match_parallel 0 "mfcr_operation"
14382 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14383 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14384 (match_operand 3 "immediate_operand" "n")]
14385 UNSPEC_MOVESI_FROM_CR))])]
14386 "TARGET_MFCRF"
14387 "*
14388{
14389 int mask = 0;
14390 int i;
14391 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14392 {
14393 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14394 operands[4] = GEN_INT (mask);
14395 output_asm_insn (\"mfcr %1,%4\", operands);
14396 }
14397 return \"\";
14398}"
14399 [(set_attr "type" "mfcrf")])
14400
9ebbca7d
GK		 14401(define_insn "movesi_from_cr"
14402 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1de43f85
DE		 14403 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14404 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14405 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14406 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
615158e2 14407 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 14408 ""
309323c2 14409 "mfcr %0"
b54cf83a 14410 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14411
14412(define_insn "*stmw"
e033a023
DE		 14413 [(match_parallel 0 "stmw_operation"
14414 [(set (match_operand:SI 1 "memory_operand" "=m")
14415 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14416 "TARGET_MULTIPLE"
9c6fdb46
DE		 14417 "{stm|stmw} %2,%1"
14418 [(set_attr "type" "store_ux")])
6ae08853 14419
4ae234b0 14420(define_insn "*save_fpregs_<mode>"
85d346f1 14421 [(match_parallel 0 "any_parallel_operand"
e65a3857
DE		 14422 [(clobber (reg:P 65))
14423 (use (match_operand:P 1 "call_operand" "s"))
14424 (set (match_operand:DF 2 "memory_operand" "=m")
14425 (match_operand:DF 3 "gpc_reg_operand" "f"))])]
4ae234b0 14426 ""
e65a3857 14427 "bl %z1"
e033a023
DE		 14428 [(set_attr "type" "branch")
14429 (set_attr "length" "4")])
9ebbca7d
GK		 14430
14431; These are to explain that changes to the stack pointer should
14432; not be moved over stores to stack memory.
14433(define_insn "stack_tie"
14434 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 14435 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 14436 ""
14437 ""
14438 [(set_attr "length" "0")])
14439
14440
14441(define_expand "epilogue"
14442 [(use (const_int 0))]
14443 "TARGET_SCHED_PROLOG"
14444 "
14445{
14446 rs6000_emit_epilogue (FALSE);
14447 DONE;
14448}")
14449
14450; On some processors, doing the mtcrf one CC register at a time is
14451; faster (like on the 604e). On others, doing them all at once is
14452; faster; for instance, on the 601 and 750.
14453
14454(define_expand "movsi_to_cr_one"
e42ac3de
RS		 14455 [(set (match_operand:CC 0 "cc_reg_operand" "")
14456 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
615158e2 14457 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 14458 ""
14459 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14460
14461(define_insn "*movsi_to_cr"
35aba846
DE		 14462 [(match_parallel 0 "mtcrf_operation"
14463 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14464 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14465 (match_operand 3 "immediate_operand" "n")]
615158e2 14466 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 14467 ""
e35b9579
GK		 14468 "*
14469{
14470 int mask = 0;
14471 int i;
14472 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14473 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14474 operands[4] = GEN_INT (mask);
14475 return \"mtcrf %4,%2\";
309323c2 14476}"
b54cf83a 14477 [(set_attr "type" "mtcr")])
9ebbca7d 14478
b54cf83a 14479(define_insn "*mtcrfsi"
309323c2
DE		 14480 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14481 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 14482 (match_operand 2 "immediate_operand" "n")]
14483 UNSPEC_MOVESI_TO_CR))]
6ae08853 14484 "GET_CODE (operands[0]) == REG
309323c2
DE		 14485 && CR_REGNO_P (REGNO (operands[0]))
14486 && GET_CODE (operands[2]) == CONST_INT
14487 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14488 "mtcrf %R0,%1"
b54cf83a 14489 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14490
14491; The load-multiple instructions have similar properties.
14492; Note that "load_multiple" is a name known to the machine-independent
9c6fdb46 14493; code that actually corresponds to the PowerPC load-string.
9ebbca7d
GK		 14494
14495(define_insn "*lmw"
35aba846
DE		 14496 [(match_parallel 0 "lmw_operation"
14497 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14498 (match_operand:SI 2 "memory_operand" "m"))])]
14499 "TARGET_MULTIPLE"
9c6fdb46
DE		 14500 "{lm|lmw} %1,%2"
14501 [(set_attr "type" "load_ux")])
6ae08853 14502
4ae234b0 14503(define_insn "*return_internal_<mode>"
e35b9579 14504 [(return)
4ae234b0
GK		 14505 (use (match_operand:P 0 "register_operand" "lc"))]
14506 ""
cccf3bdc 14507 "b%T0"
9ebbca7d
GK		 14508 [(set_attr "type" "jmpreg")])
14509
14510; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
85d346f1 14511; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
9ebbca7d 14512
4ae234b0 14513(define_insn "*return_and_restore_fpregs_<mode>"
85d346f1 14514 [(match_parallel 0 "any_parallel_operand"
e35b9579 14515 [(return)
e65a3857
DE		 14516 (use (reg:P 65))
14517 (use (match_operand:P 1 "call_operand" "s"))
14518 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
14519 (match_operand:DF 3 "memory_operand" "m"))])]
4ae234b0 14520 ""
e65a3857 14521 "b %z1")
9ebbca7d 14522
83720594
RH		 14523; This is used in compiling the unwind routines.
14524(define_expand "eh_return"
34dc173c 14525 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 14526 ""
14527 "
14528{
83720594 14529 if (TARGET_32BIT)
34dc173c 14530 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 14531 else
34dc173c 14532 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 14533 DONE;
14534}")
14535
83720594 14536; We can't expand this before we know where the link register is stored.
4ae234b0
GK		 14537(define_insn "eh_set_lr_<mode>"
14538 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
615158e2 14539 UNSPECV_EH_RR)
4ae234b0
GK		 14540 (clobber (match_scratch:P 1 "=&b"))]
14541 ""
83720594 14542 "#")
9ebbca7d
GK		 14543
14544(define_split
615158e2 14545 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 14546 (clobber (match_scratch 1 ""))]
14547 "reload_completed"
14548 [(const_int 0)]
9ebbca7d
GK		 14549 "
14550{
d1d0c603 14551 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 14552 DONE;
14553}")
0ac081f6 14554
01a2ccd0 14555(define_insn "prefetch"
3256a76e 14556 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
6041bf2f
DE		 14557 (match_operand:SI 1 "const_int_operand" "n")
14558 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14559 "TARGET_POWERPC"
6041bf2f
DE		 14560 "*
14561{
01a2ccd0
DE		 14562 if (GET_CODE (operands[0]) == REG)
14563 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14564 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14565}"
14566 [(set_attr "type" "load")])
915167f5 14567\f
a3170dc6 14568
f565b0a1 14569(include "sync.md")
10ed84db 14570(include "altivec.md")
a3170dc6 14571(include "spe.md")
7393f7f8 14572(include "dfp.md")
96038623 14573(include "paired.md")
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