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v850.c (ep_memory_operand): Return FALSE if TARGET_EP is not defined.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
CommitLineData
996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
409f61cd 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
996a5f59 4;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 5
5de601cf 6;; This file is part of GCC.
1fd4e8c1 7
5de601cf
NC		 8;; GCC is free software; you can redistribute it and/or modify it
9;; under the terms of the GNU General Public License as published
10;; by the Free Software Foundation; either version 2, or (at your
11;; option) any later version.
1fd4e8c1 12
5de601cf
NC		 13;; GCC is distributed in the hope that it will be useful, but WITHOUT
14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16;; License for more details.
1fd4e8c1
RK		 17
18;; You should have received a copy of the GNU General Public License
5de601cf 19;; along with GCC; see the file COPYING. If not, write to the
39d14dda
KC		 20;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21;; MA 02110-1301, USA.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 24
615158e2
JJ		 25;;
26;; UNSPEC usage
27;;
28
29(define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
ecb62ae7 52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
64022b5d 53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
da4c340c 54 (UNSPEC_STFIWX 32)
9f0076e5
DE		 55 (UNSPEC_POPCNTB 33)
56 (UNSPEC_FRES 34)
57 (UNSPEC_SP_SET 35)
58 (UNSPEC_SP_TEST 36)
59 (UNSPEC_SYNC 37)
60 (UNSPEC_LWSYNC 38)
61 (UNSPEC_ISYNC 39)
62 (UNSPEC_SYNC_OP 40)
63 (UNSPEC_ATOMIC 41)
64 (UNSPEC_CMPXCHG 42)
65 (UNSPEC_XCHG 43)
66 (UNSPEC_AND 44)
615158e2
JJ		 67 ])
68
69;;
70;; UNSPEC_VOLATILE usage
71;;
72
73(define_constants
74 [(UNSPECV_BLOCK 0)
b52110d4
DE		 75 (UNSPECV_LL 1) ; load-locked
76 (UNSPECV_SC 2) ; store-conditional
615158e2
JJ		 77 (UNSPECV_EH_RR 9) ; eh_reg_restore
78 ])
1fd4e8c1
RK		 79\f
80;; Define an insn type attribute. This is used in function unit delay
81;; computations.
b52110d4 82(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
1fd4e8c1
RK		 83 (const_string "integer"))
84
b19003d8 85;; Length (in bytes).
6ae08853 86; '(pc)' in the following doesn't include the instruction itself; it is
6cbadf36 87; calculated as if the instruction had zero size.
b19003d8
RK		 88(define_attr "length" ""
89 (if_then_else (eq_attr "type" "branch")
6cbadf36 90 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 91 (const_int -32768))
6cbadf36
GK		 92 (lt (minus (match_dup 0) (pc))
93 (const_int 32764)))
39a10a29
GK		 94 (const_int 4)
95 (const_int 8))
b19003d8
RK		 96 (const_int 4)))
97
cfb557c4
RK		 98;; Processor type -- this attribute must exactly match the processor_type
99;; enumeration in rs6000.h.
100
ec507f2d 101(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
cfb557c4
RK		 102 (const (symbol_ref "rs6000_cpu_attr")))
103
b54cf83a
DE		 104(automata_option "ndfa")
105
106(include "rios1.md")
107(include "rios2.md")
108(include "rs64.md")
109(include "mpc.md")
110(include "40x.md")
02ca7595 111(include "440.md")
b54cf83a
DE		 112(include "603.md")
113(include "6xx.md")
114(include "7xx.md")
115(include "7450.md")
5e8006fa 116(include "8540.md")
b54cf83a 117(include "power4.md")
ec507f2d 118(include "power5.md")
48d72335
DE		 119
120(include "predicates.md")
121
ac9e2cff 122(include "darwin.md")
309323c2 123
1fd4e8c1 124\f
915167f5
GK		 125;; Mode macros
126
127; This mode macro allows :GPR to be used to indicate the allowable size
128; of whole values in GPRs.
129(define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
130
0354e5d8 131; Any supported integer mode.
915167f5
GK		 132(define_mode_macro INT [QI HI SI DI TI])
133
0354e5d8 134; Any supported integer mode that fits in one register.
915167f5
GK		 135(define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
136
b5568f07
DE		 137; extend modes for DImode
138(define_mode_macro QHSI [QI HI SI])
139
0354e5d8
GK		 140; SImode or DImode, even if DImode doesn't fit in GPRs.
141(define_mode_macro SDI [SI DI])
142
143; The size of a pointer. Also, the size of the value that a record-condition
144; (one with a '.') will compare.
145(define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
2e6c9641 146
4ae234b0
GK		 147; Any hardware-supported floating-point mode
148(define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
149 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
150 (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
151 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
152
915167f5 153; Various instructions that come in SI and DI forms.
0354e5d8 154; A generic w/d attribute, for things like cmpw/cmpd.
b5568f07
DE		 155(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
156
157; DImode bits
158(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
915167f5
GK		 159
160\f
1fd4e8c1
RK		 161;; Start with fixed-point load and store insns. Here we put only the more
162;; complex forms. Basic data transfer is done later.
163
b5568f07 164(define_expand "zero_extend<mode>di2"
51b8fc2c 165 [(set (match_operand:DI 0 "gpc_reg_operand" "")
b5568f07 166 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
51b8fc2c
RK		 167 "TARGET_POWERPC64"
168 "")
169
b5568f07 170(define_insn "*zero_extend<mode>di2_internal1"
51b8fc2c 171 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
b5568f07 172 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
51b8fc2c
RK		 173 "TARGET_POWERPC64"
174 "@
b5568f07
DE		 175 l<wd>z%U1%X1 %0,%1
176 rldicl %0,%1,0,<dbits>"
51b8fc2c
RK		 177 [(set_attr "type" "load,*")])
178
b5568f07 179(define_insn "*zero_extend<mode>di2_internal2"
9ebbca7d 180 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
b5568f07 181 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
815cdc52 182 (const_int 0)))
9ebbca7d 183 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 184 "TARGET_64BIT"
9ebbca7d 185 "@
b5568f07 186 rldicl. %2,%1,0,<dbits>
9ebbca7d
GK		 187 #"
188 [(set_attr "type" "compare")
189 (set_attr "length" "4,8")])
190
191(define_split
192 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
b5568f07 193 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 194 (const_int 0)))
195 (clobber (match_scratch:DI 2 ""))]
196 "TARGET_POWERPC64 && reload_completed"
197 [(set (match_dup 2)
198 (zero_extend:DI (match_dup 1)))
199 (set (match_dup 0)
200 (compare:CC (match_dup 2)
201 (const_int 0)))]
202 "")
51b8fc2c 203
b5568f07 204(define_insn "*zero_extend<mode>di2_internal3"
9ebbca7d 205 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
b5568f07 206 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 207 (const_int 0)))
9ebbca7d 208 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 209 (zero_extend:DI (match_dup 1)))]
683bdff7 210 "TARGET_64BIT"
9ebbca7d 211 "@
b5568f07 212 rldicl. %0,%1,0,<dbits>
9ebbca7d
GK		 213 #"
214 [(set_attr "type" "compare")
215 (set_attr "length" "4,8")])
216
217(define_split
218 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
b5568f07 219 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 220 (const_int 0)))
221 (set (match_operand:DI 0 "gpc_reg_operand" "")
222 (zero_extend:DI (match_dup 1)))]
223 "TARGET_POWERPC64 && reload_completed"
224 [(set (match_dup 0)
225 (zero_extend:DI (match_dup 1)))
226 (set (match_dup 2)
227 (compare:CC (match_dup 0)
228 (const_int 0)))]
229 "")
51b8fc2c 230
2bee0449
RK		 231(define_insn "extendqidi2"
232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
233 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 234 "TARGET_POWERPC64"
2bee0449 235 "extsb %0,%1")
51b8fc2c
RK		 236
237(define_insn ""
9ebbca7d
GK		 238 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
239 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 240 (const_int 0)))
9ebbca7d 241 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 242 "TARGET_64BIT"
9ebbca7d
GK		 243 "@
244 extsb. %2,%1
245 #"
246 [(set_attr "type" "compare")
247 (set_attr "length" "4,8")])
248
249(define_split
250 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
251 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
252 (const_int 0)))
253 (clobber (match_scratch:DI 2 ""))]
254 "TARGET_POWERPC64 && reload_completed"
255 [(set (match_dup 2)
256 (sign_extend:DI (match_dup 1)))
257 (set (match_dup 0)
258 (compare:CC (match_dup 2)
259 (const_int 0)))]
260 "")
51b8fc2c
RK		 261
262(define_insn ""
9ebbca7d
GK		 263 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
264 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 265 (const_int 0)))
9ebbca7d 266 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 267 (sign_extend:DI (match_dup 1)))]
683bdff7 268 "TARGET_64BIT"
9ebbca7d
GK		 269 "@
270 extsb. %0,%1
271 #"
272 [(set_attr "type" "compare")
273 (set_attr "length" "4,8")])
274
275(define_split
276 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
277 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
278 (const_int 0)))
279 (set (match_operand:DI 0 "gpc_reg_operand" "")
280 (sign_extend:DI (match_dup 1)))]
281 "TARGET_POWERPC64 && reload_completed"
282 [(set (match_dup 0)
283 (sign_extend:DI (match_dup 1)))
284 (set (match_dup 2)
285 (compare:CC (match_dup 0)
286 (const_int 0)))]
287 "")
51b8fc2c 288
51b8fc2c
RK		 289(define_expand "extendhidi2"
290 [(set (match_operand:DI 0 "gpc_reg_operand" "")
291 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
292 "TARGET_POWERPC64"
293 "")
294
295(define_insn ""
296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
297 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
298 "TARGET_POWERPC64"
299 "@
300 lha%U1%X1 %0,%1
301 extsh %0,%1"
b54cf83a 302 [(set_attr "type" "load_ext,*")])
51b8fc2c
RK		 303
304(define_insn ""
9ebbca7d
GK		 305 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
306 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 307 (const_int 0)))
9ebbca7d 308 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 309 "TARGET_64BIT"
9ebbca7d
GK		 310 "@
311 extsh. %2,%1
312 #"
313 [(set_attr "type" "compare")
314 (set_attr "length" "4,8")])
315
316(define_split
317 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
318 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
319 (const_int 0)))
320 (clobber (match_scratch:DI 2 ""))]
321 "TARGET_POWERPC64 && reload_completed"
322 [(set (match_dup 2)
323 (sign_extend:DI (match_dup 1)))
324 (set (match_dup 0)
325 (compare:CC (match_dup 2)
326 (const_int 0)))]
327 "")
51b8fc2c
RK		 328
329(define_insn ""
9ebbca7d
GK		 330 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
331 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 332 (const_int 0)))
9ebbca7d 333 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 334 (sign_extend:DI (match_dup 1)))]
683bdff7 335 "TARGET_64BIT"
9ebbca7d
GK		 336 "@
337 extsh. %0,%1
338 #"
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
341
342(define_split
343 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
344 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
345 (const_int 0)))
346 (set (match_operand:DI 0 "gpc_reg_operand" "")
347 (sign_extend:DI (match_dup 1)))]
348 "TARGET_POWERPC64 && reload_completed"
349 [(set (match_dup 0)
350 (sign_extend:DI (match_dup 1)))
351 (set (match_dup 2)
352 (compare:CC (match_dup 0)
353 (const_int 0)))]
354 "")
51b8fc2c 355
51b8fc2c
RK		 356(define_expand "extendsidi2"
357 [(set (match_operand:DI 0 "gpc_reg_operand" "")
358 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
359 "TARGET_POWERPC64"
360 "")
361
362(define_insn ""
363 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 364 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
51b8fc2c
RK		 365 "TARGET_POWERPC64"
366 "@
367 lwa%U1%X1 %0,%1
368 extsw %0,%1"
b54cf83a 369 [(set_attr "type" "load_ext,*")])
51b8fc2c
RK		 370
371(define_insn ""
9ebbca7d
GK		 372 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
373 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 374 (const_int 0)))
9ebbca7d 375 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 376 "TARGET_64BIT"
9ebbca7d
GK		 377 "@
378 extsw. %2,%1
379 #"
380 [(set_attr "type" "compare")
381 (set_attr "length" "4,8")])
382
383(define_split
384 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
385 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
386 (const_int 0)))
387 (clobber (match_scratch:DI 2 ""))]
388 "TARGET_POWERPC64 && reload_completed"
389 [(set (match_dup 2)
390 (sign_extend:DI (match_dup 1)))
391 (set (match_dup 0)
392 (compare:CC (match_dup 2)
393 (const_int 0)))]
394 "")
51b8fc2c
RK		 395
396(define_insn ""
9ebbca7d
GK		 397 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
398 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 399 (const_int 0)))
9ebbca7d 400 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 401 (sign_extend:DI (match_dup 1)))]
683bdff7 402 "TARGET_64BIT"
9ebbca7d
GK		 403 "@
404 extsw. %0,%1
405 #"
406 [(set_attr "type" "compare")
407 (set_attr "length" "4,8")])
408
409(define_split
410 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
411 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
412 (const_int 0)))
413 (set (match_operand:DI 0 "gpc_reg_operand" "")
414 (sign_extend:DI (match_dup 1)))]
415 "TARGET_POWERPC64 && reload_completed"
416 [(set (match_dup 0)
417 (sign_extend:DI (match_dup 1)))
418 (set (match_dup 2)
419 (compare:CC (match_dup 0)
420 (const_int 0)))]
421 "")
51b8fc2c 422
1fd4e8c1 423(define_expand "zero_extendqisi2"
cd2b37d9
RK		 424 [(set (match_operand:SI 0 "gpc_reg_operand" "")
425 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 426 ""
427 "")
428
429(define_insn ""
cd2b37d9 430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 431 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
432 ""
433 "@
434 lbz%U1%X1 %0,%1
005a35b9 435 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 436 [(set_attr "type" "load,*")])
437
438(define_insn ""
9ebbca7d
GK		 439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
440 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 441 (const_int 0)))
9ebbca7d 442 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 443 ""
9ebbca7d
GK		 444 "@
445 {andil.|andi.} %2,%1,0xff
446 #"
447 [(set_attr "type" "compare")
448 (set_attr "length" "4,8")])
449
450(define_split
451 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
452 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
453 (const_int 0)))
454 (clobber (match_scratch:SI 2 ""))]
455 "reload_completed"
456 [(set (match_dup 2)
457 (zero_extend:SI (match_dup 1)))
458 (set (match_dup 0)
459 (compare:CC (match_dup 2)
460 (const_int 0)))]
461 "")
1fd4e8c1
RK		 462
463(define_insn ""
9ebbca7d
GK		 464 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
465 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 466 (const_int 0)))
9ebbca7d 467 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 468 (zero_extend:SI (match_dup 1)))]
469 ""
9ebbca7d
GK		 470 "@
471 {andil.|andi.} %0,%1,0xff
472 #"
473 [(set_attr "type" "compare")
474 (set_attr "length" "4,8")])
475
476(define_split
477 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
478 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
479 (const_int 0)))
480 (set (match_operand:SI 0 "gpc_reg_operand" "")
481 (zero_extend:SI (match_dup 1)))]
482 "reload_completed"
483 [(set (match_dup 0)
484 (zero_extend:SI (match_dup 1)))
485 (set (match_dup 2)
486 (compare:CC (match_dup 0)
487 (const_int 0)))]
488 "")
1fd4e8c1 489
51b8fc2c
RK		 490(define_expand "extendqisi2"
491 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
492 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
493 ""
494 "
495{
496 if (TARGET_POWERPC)
497 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
498 else if (TARGET_POWER)
499 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
500 else
501 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
502 DONE;
503}")
504
505(define_insn "extendqisi2_ppc"
2bee0449
RK		 506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
507 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 508 "TARGET_POWERPC"
2bee0449 509 "extsb %0,%1")
51b8fc2c
RK		 510
511(define_insn ""
9ebbca7d
GK		 512 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
513 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 514 (const_int 0)))
9ebbca7d 515 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 516 "TARGET_POWERPC"
9ebbca7d
GK		 517 "@
518 extsb. %2,%1
519 #"
520 [(set_attr "type" "compare")
521 (set_attr "length" "4,8")])
522
523(define_split
524 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
525 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
526 (const_int 0)))
527 (clobber (match_scratch:SI 2 ""))]
528 "TARGET_POWERPC && reload_completed"
529 [(set (match_dup 2)
530 (sign_extend:SI (match_dup 1)))
531 (set (match_dup 0)
532 (compare:CC (match_dup 2)
533 (const_int 0)))]
534 "")
51b8fc2c
RK		 535
536(define_insn ""
9ebbca7d
GK		 537 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
538 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 539 (const_int 0)))
9ebbca7d 540 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 541 (sign_extend:SI (match_dup 1)))]
542 "TARGET_POWERPC"
9ebbca7d
GK		 543 "@
544 extsb. %0,%1
545 #"
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
548
549(define_split
550 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
551 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
552 (const_int 0)))
553 (set (match_operand:SI 0 "gpc_reg_operand" "")
554 (sign_extend:SI (match_dup 1)))]
555 "TARGET_POWERPC && reload_completed"
556 [(set (match_dup 0)
557 (sign_extend:SI (match_dup 1)))
558 (set (match_dup 2)
559 (compare:CC (match_dup 0)
560 (const_int 0)))]
561 "")
51b8fc2c
RK		 562
563(define_expand "extendqisi2_power"
564 [(parallel [(set (match_dup 2)
565 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
566 (const_int 24)))
567 (clobber (scratch:SI))])
568 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
569 (ashiftrt:SI (match_dup 2)
570 (const_int 24)))
571 (clobber (scratch:SI))])]
572 "TARGET_POWER"
573 "
574{ operands[1] = gen_lowpart (SImode, operands[1]);
575 operands[2] = gen_reg_rtx (SImode); }")
576
577(define_expand "extendqisi2_no_power"
578 [(set (match_dup 2)
579 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
580 (const_int 24)))
581 (set (match_operand:SI 0 "gpc_reg_operand" "")
582 (ashiftrt:SI (match_dup 2)
583 (const_int 24)))]
584 "! TARGET_POWER && ! TARGET_POWERPC"
585 "
586{ operands[1] = gen_lowpart (SImode, operands[1]);
587 operands[2] = gen_reg_rtx (SImode); }")
588
1fd4e8c1 589(define_expand "zero_extendqihi2"
cd2b37d9
RK		 590 [(set (match_operand:HI 0 "gpc_reg_operand" "")
591 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 592 ""
593 "")
594
595(define_insn ""
cd2b37d9 596 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 597 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
598 ""
599 "@
600 lbz%U1%X1 %0,%1
005a35b9 601 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 602 [(set_attr "type" "load,*")])
603
604(define_insn ""
9ebbca7d
GK		 605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 607 (const_int 0)))
9ebbca7d 608 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 609 ""
9ebbca7d
GK		 610 "@
611 {andil.|andi.} %2,%1,0xff
612 #"
613 [(set_attr "type" "compare")
614 (set_attr "length" "4,8")])
615
616(define_split
617 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
618 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (const_int 0)))
620 (clobber (match_scratch:HI 2 ""))]
621 "reload_completed"
622 [(set (match_dup 2)
623 (zero_extend:HI (match_dup 1)))
624 (set (match_dup 0)
625 (compare:CC (match_dup 2)
626 (const_int 0)))]
627 "")
1fd4e8c1 628
51b8fc2c 629(define_insn ""
9ebbca7d
GK		 630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
631 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 632 (const_int 0)))
9ebbca7d 633 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 634 (zero_extend:HI (match_dup 1)))]
635 ""
9ebbca7d
GK		 636 "@
637 {andil.|andi.} %0,%1,0xff
638 #"
639 [(set_attr "type" "compare")
640 (set_attr "length" "4,8")])
641
642(define_split
643 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
644 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
645 (const_int 0)))
646 (set (match_operand:HI 0 "gpc_reg_operand" "")
647 (zero_extend:HI (match_dup 1)))]
648 "reload_completed"
649 [(set (match_dup 0)
650 (zero_extend:HI (match_dup 1)))
651 (set (match_dup 2)
652 (compare:CC (match_dup 0)
653 (const_int 0)))]
654 "")
815cdc52
MM		 655
656(define_expand "extendqihi2"
657 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
658 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
659 ""
660 "
661{
662 if (TARGET_POWERPC)
663 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
664 else if (TARGET_POWER)
665 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
666 else
667 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
668 DONE;
669}")
670
671(define_insn "extendqihi2_ppc"
672 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
673 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
674 "TARGET_POWERPC"
675 "extsb %0,%1")
676
677(define_insn ""
9ebbca7d
GK		 678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
679 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 680 (const_int 0)))
9ebbca7d 681 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 682 "TARGET_POWERPC"
9ebbca7d
GK		 683 "@
684 extsb. %2,%1
685 #"
686 [(set_attr "type" "compare")
687 (set_attr "length" "4,8")])
688
689(define_split
690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
691 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
692 (const_int 0)))
693 (clobber (match_scratch:HI 2 ""))]
694 "TARGET_POWERPC && reload_completed"
695 [(set (match_dup 2)
696 (sign_extend:HI (match_dup 1)))
697 (set (match_dup 0)
698 (compare:CC (match_dup 2)
699 (const_int 0)))]
700 "")
815cdc52
MM		 701
702(define_insn ""
9ebbca7d
GK		 703 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
704 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 705 (const_int 0)))
9ebbca7d 706 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 707 (sign_extend:HI (match_dup 1)))]
708 "TARGET_POWERPC"
9ebbca7d
GK		 709 "@
710 extsb. %0,%1
711 #"
712 [(set_attr "type" "compare")
713 (set_attr "length" "4,8")])
714
715(define_split
716 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
717 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
718 (const_int 0)))
719 (set (match_operand:HI 0 "gpc_reg_operand" "")
720 (sign_extend:HI (match_dup 1)))]
721 "TARGET_POWERPC && reload_completed"
722 [(set (match_dup 0)
723 (sign_extend:HI (match_dup 1)))
724 (set (match_dup 2)
725 (compare:CC (match_dup 0)
726 (const_int 0)))]
727 "")
51b8fc2c
RK		 728
729(define_expand "extendqihi2_power"
730 [(parallel [(set (match_dup 2)
731 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
732 (const_int 24)))
733 (clobber (scratch:SI))])
734 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
735 (ashiftrt:SI (match_dup 2)
736 (const_int 24)))
737 (clobber (scratch:SI))])]
738 "TARGET_POWER"
739 "
740{ operands[0] = gen_lowpart (SImode, operands[0]);
741 operands[1] = gen_lowpart (SImode, operands[1]);
742 operands[2] = gen_reg_rtx (SImode); }")
743
744(define_expand "extendqihi2_no_power"
745 [(set (match_dup 2)
746 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
747 (const_int 24)))
748 (set (match_operand:HI 0 "gpc_reg_operand" "")
749 (ashiftrt:SI (match_dup 2)
750 (const_int 24)))]
751 "! TARGET_POWER && ! TARGET_POWERPC"
752 "
753{ operands[0] = gen_lowpart (SImode, operands[0]);
754 operands[1] = gen_lowpart (SImode, operands[1]);
755 operands[2] = gen_reg_rtx (SImode); }")
756
1fd4e8c1 757(define_expand "zero_extendhisi2"
5f243543 758 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 759 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 760 ""
761 "")
762
763(define_insn ""
cd2b37d9 764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 765 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
766 ""
767 "@
768 lhz%U1%X1 %0,%1
005a35b9 769 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 770 [(set_attr "type" "load,*")])
771
772(define_insn ""
9ebbca7d
GK		 773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
774 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 775 (const_int 0)))
9ebbca7d 776 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 777 ""
9ebbca7d
GK		 778 "@
779 {andil.|andi.} %2,%1,0xffff
780 #"
781 [(set_attr "type" "compare")
782 (set_attr "length" "4,8")])
783
784(define_split
785 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
786 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
787 (const_int 0)))
788 (clobber (match_scratch:SI 2 ""))]
789 "reload_completed"
790 [(set (match_dup 2)
791 (zero_extend:SI (match_dup 1)))
792 (set (match_dup 0)
793 (compare:CC (match_dup 2)
794 (const_int 0)))]
795 "")
1fd4e8c1
RK		 796
797(define_insn ""
9ebbca7d
GK		 798 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
799 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 800 (const_int 0)))
9ebbca7d 801 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 802 (zero_extend:SI (match_dup 1)))]
803 ""
9ebbca7d
GK		 804 "@
805 {andil.|andi.} %0,%1,0xffff
806 #"
807 [(set_attr "type" "compare")
808 (set_attr "length" "4,8")])
809
810(define_split
811 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
812 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
813 (const_int 0)))
814 (set (match_operand:SI 0 "gpc_reg_operand" "")
815 (zero_extend:SI (match_dup 1)))]
816 "reload_completed"
817 [(set (match_dup 0)
818 (zero_extend:SI (match_dup 1)))
819 (set (match_dup 2)
820 (compare:CC (match_dup 0)
821 (const_int 0)))]
822 "")
1fd4e8c1
RK		 823
824(define_expand "extendhisi2"
cd2b37d9
RK		 825 [(set (match_operand:SI 0 "gpc_reg_operand" "")
826 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 827 ""
828 "")
829
830(define_insn ""
cd2b37d9 831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 832 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
833 ""
834 "@
835 lha%U1%X1 %0,%1
ca7f5001 836 {exts|extsh} %0,%1"
b54cf83a 837 [(set_attr "type" "load_ext,*")])
1fd4e8c1
RK		 838
839(define_insn ""
9ebbca7d
GK		 840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
841 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 842 (const_int 0)))
9ebbca7d 843 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 844 ""
9ebbca7d
GK		 845 "@
846 {exts.|extsh.} %2,%1
847 #"
848 [(set_attr "type" "compare")
849 (set_attr "length" "4,8")])
850
851(define_split
852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
853 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
854 (const_int 0)))
855 (clobber (match_scratch:SI 2 ""))]
856 "reload_completed"
857 [(set (match_dup 2)
858 (sign_extend:SI (match_dup 1)))
859 (set (match_dup 0)
860 (compare:CC (match_dup 2)
861 (const_int 0)))]
862 "")
1fd4e8c1
RK		 863
864(define_insn ""
9ebbca7d
GK		 865 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
866 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 867 (const_int 0)))
9ebbca7d 868 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 869 (sign_extend:SI (match_dup 1)))]
870 ""
9ebbca7d
GK		 871 "@
872 {exts.|extsh.} %0,%1
873 #"
874 [(set_attr "type" "compare")
875 (set_attr "length" "4,8")])
1fd4e8c1 876\f
9ebbca7d
GK		 877(define_split
878 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
879 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
880 (const_int 0)))
881 (set (match_operand:SI 0 "gpc_reg_operand" "")
882 (sign_extend:SI (match_dup 1)))]
883 "reload_completed"
884 [(set (match_dup 0)
885 (sign_extend:SI (match_dup 1)))
886 (set (match_dup 2)
887 (compare:CC (match_dup 0)
888 (const_int 0)))]
889 "")
890
1fd4e8c1 891;; Fixed-point arithmetic insns.
deb9225a 892
0354e5d8
GK		 893(define_expand "add<mode>3"
894 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
895 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
4ae234b0 896 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
7cd5235b
MM		 897 ""
898 "
899{
0354e5d8
GK		 900 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
901 {
902 if (non_short_cint_operand (operands[2], DImode))
903 FAIL;
904 }
905 else if (GET_CODE (operands[2]) == CONST_INT
906 && ! add_operand (operands[2], <MODE>mode))
7cd5235b 907 {
677a9668 908 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
0354e5d8 909 ? operands[0] : gen_reg_rtx (<MODE>mode));
7cd5235b 910
2bfcf297 911 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 912 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8
GK		 913 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
914
915 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
916 FAIL;
7cd5235b 917
9ebbca7d
GK		 918 /* The ordering here is important for the prolog expander.
919 When space is allocated from the stack, adding 'low' first may
920 produce a temporary deallocation (which would be bad). */
0354e5d8
GK		 921 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
922 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
7cd5235b
MM		 923 DONE;
924 }
925}")
926
0354e5d8
GK		 927;; Discourage ai/addic because of carry but provide it in an alternative
928;; allowing register zero as source.
929(define_insn "*add<mode>3_internal1"
930 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
931 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
932 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1fd4e8c1
RK		 933 ""
934 "@
deb9225a
RK		 935 {cax|add} %0,%1,%2
936 {cal %0,%2(%1)|addi %0,%1,%2}
937 {ai|addic} %0,%1,%2
7cd5235b
MM		 938 {cau|addis} %0,%1,%v2"
939 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 940
ee890fe2
SS		 941(define_insn "addsi3_high"
942 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
943 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
944 (high:SI (match_operand 2 "" ""))))]
945 "TARGET_MACHO && !TARGET_64BIT"
946 "{cau|addis} %0,%1,ha16(%2)"
947 [(set_attr "length" "4")])
948
0354e5d8 949(define_insn "*add<mode>3_internal2"
cb8cc086 950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 951 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
952 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 953 (const_int 0)))
0354e5d8
GK		 954 (clobber (match_scratch:P 3 "=r,r,r,r"))]
955 ""
deb9225a
RK		 956 "@
957 {cax.|add.} %3,%1,%2
cb8cc086
MM		 958 {ai.|addic.} %3,%1,%2
959 #
960 #"
a62bfff2 961 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 962 (set_attr "length" "4,4,8,8")])
963
964(define_split
965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 966 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
967 (match_operand:GPR 2 "reg_or_short_operand" ""))
cb8cc086 968 (const_int 0)))
0354e5d8
GK		 969 (clobber (match_scratch:GPR 3 ""))]
970 "reload_completed"
cb8cc086 971 [(set (match_dup 3)
0354e5d8 972 (plus:GPR (match_dup 1)
cb8cc086
MM		 973 (match_dup 2)))
974 (set (match_dup 0)
975 (compare:CC (match_dup 3)
976 (const_int 0)))]
977 "")
7e69e155 978
0354e5d8 979(define_insn "*add<mode>3_internal3"
cb8cc086 980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 981 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
982 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 983 (const_int 0)))
0354e5d8
GK		 984 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
985 (plus:P (match_dup 1)
986 (match_dup 2)))]
987 ""
deb9225a
RK		 988 "@
989 {cax.|add.} %0,%1,%2
cb8cc086
MM		 990 {ai.|addic.} %0,%1,%2
991 #
992 #"
a62bfff2 993 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 994 (set_attr "length" "4,4,8,8")])
995
996(define_split
997 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 998 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
999 (match_operand:P 2 "reg_or_short_operand" ""))
cb8cc086 1000 (const_int 0)))
0354e5d8
GK		 1001 (set (match_operand:P 0 "gpc_reg_operand" "")
1002 (plus:P (match_dup 1) (match_dup 2)))]
1003 "reload_completed"
cb8cc086 1004 [(set (match_dup 0)
0354e5d8
GK		 1005 (plus:P (match_dup 1)
1006 (match_dup 2)))
cb8cc086
MM		 1007 (set (match_dup 3)
1008 (compare:CC (match_dup 0)
1009 (const_int 0)))]
1010 "")
7e69e155 1011
f357808b
RK		 1012;; Split an add that we can't do in one insn into two insns, each of which
1013;; does one 16-bit part. This is used by combine. Note that the low-order
1014;; add should be last in case the result gets used in an address.
1015
1016(define_split
0354e5d8
GK		 1017 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1018 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1019 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1fd4e8c1 1020 ""
0354e5d8
GK		 1021 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1022 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
f357808b 1023"
1fd4e8c1 1024{
2bfcf297 1025 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1026 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8 1027 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1fd4e8c1 1028
e6ca2c17 1029 operands[4] = GEN_INT (low);
0354e5d8
GK		 1030 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1031 operands[3] = GEN_INT (rest);
1032 else if (! no_new_pseudos)
1033 {
1034 operands[3] = gen_reg_rtx (DImode);
1035 emit_move_insn (operands[3], operands[2]);
1036 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1037 DONE;
1038 }
1039 else
1040 FAIL;
1fd4e8c1
RK		 1041}")
1042
0354e5d8
GK		 1043(define_insn "one_cmpl<mode>2"
1044 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1045 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1046 ""
ca7f5001
RK		 1047 "nor %0,%1,%1")
1048
1049(define_insn ""
52d3af72 1050 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 1051 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
ca7f5001 1052 (const_int 0)))
0354e5d8
GK		 1053 (clobber (match_scratch:P 2 "=r,r"))]
1054 ""
52d3af72
DE		 1055 "@
1056 nor. %2,%1,%1
1057 #"
1058 [(set_attr "type" "compare")
1059 (set_attr "length" "4,8")])
1060
1061(define_split
1062 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 1063 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1064 (const_int 0)))
0354e5d8
GK		 1065 (clobber (match_scratch:P 2 ""))]
1066 "reload_completed"
52d3af72 1067 [(set (match_dup 2)
0354e5d8 1068 (not:P (match_dup 1)))
52d3af72
DE		 1069 (set (match_dup 0)
1070 (compare:CC (match_dup 2)
1071 (const_int 0)))]
1072 "")
ca7f5001
RK		 1073
1074(define_insn ""
52d3af72 1075 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 1076 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 1077 (const_int 0)))
0354e5d8
GK		 1078 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1079 (not:P (match_dup 1)))]
1080 ""
52d3af72
DE		 1081 "@
1082 nor. %0,%1,%1
1083 #"
1084 [(set_attr "type" "compare")
1085 (set_attr "length" "4,8")])
1086
1087(define_split
1088 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 1089 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1090 (const_int 0)))
0354e5d8
GK		 1091 (set (match_operand:P 0 "gpc_reg_operand" "")
1092 (not:P (match_dup 1)))]
1093 "reload_completed"
52d3af72 1094 [(set (match_dup 0)
0354e5d8 1095 (not:P (match_dup 1)))
52d3af72
DE		 1096 (set (match_dup 2)
1097 (compare:CC (match_dup 0)
1098 (const_int 0)))]
1099 "")
1fd4e8c1
RK		 1100
1101(define_insn ""
3d91674b
RK		 1102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1103 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1104 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1105 "! TARGET_POWERPC"
ca7f5001 1106 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1107
deb9225a 1108(define_insn ""
0354e5d8
GK		 1109 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1110 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1111 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
deb9225a
RK		 1112 "TARGET_POWERPC"
1113 "@
1114 subf %0,%2,%1
1115 subfic %0,%2,%1")
1116
1fd4e8c1 1117(define_insn ""
cb8cc086
MM		 1118 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1119 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1120 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1121 (const_int 0)))
cb8cc086 1122 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1123 "! TARGET_POWERPC"
cb8cc086
MM		 1124 "@
1125 {sf.|subfc.} %3,%2,%1
1126 #"
1127 [(set_attr "type" "compare")
1128 (set_attr "length" "4,8")])
1fd4e8c1 1129
deb9225a 1130(define_insn ""
cb8cc086 1131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1132 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1133 (match_operand:P 2 "gpc_reg_operand" "r,r"))
deb9225a 1134 (const_int 0)))
0354e5d8
GK		 1135 (clobber (match_scratch:P 3 "=r,r"))]
1136 "TARGET_POWERPC"
cb8cc086
MM		 1137 "@
1138 subf. %3,%2,%1
1139 #"
a62bfff2 1140 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1141 (set_attr "length" "4,8")])
1142
1143(define_split
1144 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1145 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1146 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1147 (const_int 0)))
0354e5d8
GK		 1148 (clobber (match_scratch:P 3 ""))]
1149 "reload_completed"
cb8cc086 1150 [(set (match_dup 3)
0354e5d8 1151 (minus:P (match_dup 1)
cb8cc086
MM		 1152 (match_dup 2)))
1153 (set (match_dup 0)
1154 (compare:CC (match_dup 3)
1155 (const_int 0)))]
1156 "")
deb9225a 1157
1fd4e8c1 1158(define_insn ""
cb8cc086
MM		 1159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1160 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1161 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1162 (const_int 0)))
cb8cc086 1163 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1164 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1165 "! TARGET_POWERPC"
cb8cc086
MM		 1166 "@
1167 {sf.|subfc.} %0,%2,%1
1168 #"
1169 [(set_attr "type" "compare")
1170 (set_attr "length" "4,8")])
815cdc52 1171
29ae5b89 1172(define_insn ""
cb8cc086 1173 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1174 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1175 (match_operand:P 2 "gpc_reg_operand" "r,r"))
815cdc52 1176 (const_int 0)))
0354e5d8
GK		 1177 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1178 (minus:P (match_dup 1)
cb8cc086 1179 (match_dup 2)))]
0354e5d8 1180 "TARGET_POWERPC"
90612787
DE		 1181 "@
1182 subf. %0,%2,%1
1183 #"
a62bfff2 1184 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1185 (set_attr "length" "4,8")])
1186
1187(define_split
1188 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1189 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1190 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1191 (const_int 0)))
0354e5d8
GK		 1192 (set (match_operand:P 0 "gpc_reg_operand" "")
1193 (minus:P (match_dup 1)
cb8cc086 1194 (match_dup 2)))]
0354e5d8 1195 "reload_completed"
cb8cc086 1196 [(set (match_dup 0)
0354e5d8 1197 (minus:P (match_dup 1)
cb8cc086
MM		 1198 (match_dup 2)))
1199 (set (match_dup 3)
1200 (compare:CC (match_dup 0)
1201 (const_int 0)))]
1202 "")
deb9225a 1203
0354e5d8
GK		 1204(define_expand "sub<mode>3"
1205 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1206 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
4ae234b0 1207 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1fd4e8c1 1208 ""
a0044fb1
RK		 1209 "
1210{
1211 if (GET_CODE (operands[2]) == CONST_INT)
1212 {
0354e5d8
GK		 1213 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1214 negate_rtx (<MODE>mode, operands[2])));
a0044fb1
RK		 1215 DONE;
1216 }
1217}")
1fd4e8c1
RK		 1218
1219;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1220;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1221;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1222;; combine.
1fd4e8c1
RK		 1223
1224(define_expand "sminsi3"
1225 [(set (match_dup 3)
cd2b37d9 1226 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1227 (match_operand:SI 2 "reg_or_short_operand" ""))
1228 (const_int 0)
1229 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1230 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1231 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1232 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1233 "
a3170dc6
AH		 1234{
1235 if (TARGET_ISEL)
1236 {
1237 operands[2] = force_reg (SImode, operands[2]);
1238 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1239 DONE;
1240 }
1241
1242 operands[3] = gen_reg_rtx (SImode);
1243}")
1fd4e8c1 1244
95ac8e67
RK		 1245(define_split
1246 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1247 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1248 (match_operand:SI 2 "reg_or_short_operand" "")))
1249 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1250 "TARGET_POWER"
95ac8e67
RK		 1251 [(set (match_dup 3)
1252 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1253 (const_int 0)
1254 (minus:SI (match_dup 2) (match_dup 1))))
1255 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1256 "")
1257
1fd4e8c1
RK		 1258(define_expand "smaxsi3"
1259 [(set (match_dup 3)
cd2b37d9 1260 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1261 (match_operand:SI 2 "reg_or_short_operand" ""))
1262 (const_int 0)
1263 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1264 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1265 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1266 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1267 "
a3170dc6
AH		 1268{
1269 if (TARGET_ISEL)
1270 {
1271 operands[2] = force_reg (SImode, operands[2]);
1272 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1273 DONE;
1274 }
1275 operands[3] = gen_reg_rtx (SImode);
1276}")
1fd4e8c1 1277
95ac8e67
RK		 1278(define_split
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1280 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1281 (match_operand:SI 2 "reg_or_short_operand" "")))
1282 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1283 "TARGET_POWER"
95ac8e67
RK		 1284 [(set (match_dup 3)
1285 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1286 (const_int 0)
1287 (minus:SI (match_dup 2) (match_dup 1))))
1288 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1289 "")
1290
1fd4e8c1 1291(define_expand "uminsi3"
cd2b37d9 1292 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1293 (match_dup 5)))
cd2b37d9 1294 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1295 (match_dup 5)))
1fd4e8c1
RK		 1296 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1297 (const_int 0)
1298 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1299 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1300 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1301 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1302 "
bb68ff55 1303{
a3170dc6
AH		 1304 if (TARGET_ISEL)
1305 {
1306 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1307 DONE;
1308 }
bb68ff55
MM		 1309 operands[3] = gen_reg_rtx (SImode);
1310 operands[4] = gen_reg_rtx (SImode);
1311 operands[5] = GEN_INT (-2147483647 - 1);
1312}")
1fd4e8c1
RK		 1313
1314(define_expand "umaxsi3"
cd2b37d9 1315 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1316 (match_dup 5)))
cd2b37d9 1317 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1318 (match_dup 5)))
1fd4e8c1
RK		 1319 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1320 (const_int 0)
1321 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1322 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1323 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1324 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1325 "
bb68ff55 1326{
a3170dc6
AH		 1327 if (TARGET_ISEL)
1328 {
1329 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1330 DONE;
1331 }
bb68ff55
MM		 1332 operands[3] = gen_reg_rtx (SImode);
1333 operands[4] = gen_reg_rtx (SImode);
1334 operands[5] = GEN_INT (-2147483647 - 1);
1335}")
1fd4e8c1
RK		 1336
1337(define_insn ""
cd2b37d9
RK		 1338 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1339 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1340 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1341 (const_int 0)
1342 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1343 "TARGET_POWER"
1fd4e8c1
RK		 1344 "doz%I2 %0,%1,%2")
1345
1346(define_insn ""
9ebbca7d 1347 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1348 (compare:CC
9ebbca7d
GK		 1349 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1350 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1351 (const_int 0)
1352 (minus:SI (match_dup 2) (match_dup 1)))
1353 (const_int 0)))
9ebbca7d 1354 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1355 "TARGET_POWER"
9ebbca7d
GK		 1356 "@
1357 doz%I2. %3,%1,%2
1358 #"
1359 [(set_attr "type" "delayed_compare")
1360 (set_attr "length" "4,8")])
1361
1362(define_split
1363 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1364 (compare:CC
1365 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1366 (match_operand:SI 2 "reg_or_short_operand" ""))
1367 (const_int 0)
1368 (minus:SI (match_dup 2) (match_dup 1)))
1369 (const_int 0)))
1370 (clobber (match_scratch:SI 3 ""))]
1371 "TARGET_POWER && reload_completed"
1372 [(set (match_dup 3)
1373 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1374 (const_int 0)
1375 (minus:SI (match_dup 2) (match_dup 1))))
1376 (set (match_dup 0)
1377 (compare:CC (match_dup 3)
1378 (const_int 0)))]
1379 "")
1fd4e8c1
RK		 1380
1381(define_insn ""
9ebbca7d 1382 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1383 (compare:CC
9ebbca7d
GK		 1384 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1385 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1386 (const_int 0)
1387 (minus:SI (match_dup 2) (match_dup 1)))
1388 (const_int 0)))
9ebbca7d 1389 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1390 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1391 (const_int 0)
1392 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1393 "TARGET_POWER"
9ebbca7d
GK		 1394 "@
1395 doz%I2. %0,%1,%2
1396 #"
1397 [(set_attr "type" "delayed_compare")
1398 (set_attr "length" "4,8")])
1399
1400(define_split
1401 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1402 (compare:CC
1403 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1404 (match_operand:SI 2 "reg_or_short_operand" ""))
1405 (const_int 0)
1406 (minus:SI (match_dup 2) (match_dup 1)))
1407 (const_int 0)))
1408 (set (match_operand:SI 0 "gpc_reg_operand" "")
1409 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1410 (const_int 0)
1411 (minus:SI (match_dup 2) (match_dup 1))))]
1412 "TARGET_POWER && reload_completed"
1413 [(set (match_dup 0)
1414 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1415 (const_int 0)
1416 (minus:SI (match_dup 2) (match_dup 1))))
1417 (set (match_dup 3)
1418 (compare:CC (match_dup 0)
1419 (const_int 0)))]
1420 "")
1fd4e8c1
RK		 1421
1422;; We don't need abs with condition code because such comparisons should
1423;; never be done.
ea9be077
MM		 1424(define_expand "abssi2"
1425 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1426 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1427 ""
1428 "
1429{
a3170dc6
AH		 1430 if (TARGET_ISEL)
1431 {
1432 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1433 DONE;
1434 }
1435 else if (! TARGET_POWER)
ea9be077
MM		 1436 {
1437 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1438 DONE;
1439 }
1440}")
1441
ea112fc4 1442(define_insn "*abssi2_power"
cd2b37d9
RK		 1443 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1444 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 1445 "TARGET_POWER"
1fd4e8c1
RK		 1446 "abs %0,%1")
1447
a3170dc6
AH		 1448(define_insn_and_split "abssi2_isel"
1449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1450 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 1451 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 1452 (clobber (match_scratch:CC 3 "=y"))]
1453 "TARGET_ISEL"
1454 "#"
1455 "&& reload_completed"
1456 [(set (match_dup 2) (neg:SI (match_dup 1)))
1457 (set (match_dup 3)
1458 (compare:CC (match_dup 1)
1459 (const_int 0)))
1460 (set (match_dup 0)
1461 (if_then_else:SI (ge (match_dup 3)
1462 (const_int 0))
1463 (match_dup 1)
1464 (match_dup 2)))]
1465 "")
1466
ea112fc4 1467(define_insn_and_split "abssi2_nopower"
ea9be077 1468 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 1469 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 1470 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 1471 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 1472 "#"
1473 "&& reload_completed"
ea9be077
MM		 1474 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1475 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 1476 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 1477 "")
1478
463b558b 1479(define_insn "*nabs_power"
cd2b37d9
RK		 1480 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1481 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 1482 "TARGET_POWER"
1fd4e8c1
RK		 1483 "nabs %0,%1")
1484
ea112fc4 1485(define_insn_and_split "*nabs_nopower"
ea9be077 1486 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 1487 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 1488 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 1489 "! TARGET_POWER"
ea112fc4
DE		 1490 "#"
1491 "&& reload_completed"
ea9be077
MM		 1492 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1493 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 1494 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 1495 "")
1496
0354e5d8
GK		 1497(define_expand "neg<mode>2"
1498 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1499 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1500 ""
1501 "")
1502
1503(define_insn "*neg<mode>2_internal"
1504 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1505 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 1506 ""
1507 "neg %0,%1")
1508
1509(define_insn ""
9ebbca7d 1510 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 1511 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 1512 (const_int 0)))
0354e5d8
GK		 1513 (clobber (match_scratch:P 2 "=r,r"))]
1514 ""
9ebbca7d
GK		 1515 "@
1516 neg. %2,%1
1517 #"
a62bfff2 1518 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 1519 (set_attr "length" "4,8")])
1520
1521(define_split
1522 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 1523 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 1524 (const_int 0)))
0354e5d8
GK		 1525 (clobber (match_scratch:P 2 ""))]
1526 "reload_completed"
9ebbca7d 1527 [(set (match_dup 2)
0354e5d8 1528 (neg:P (match_dup 1)))
9ebbca7d
GK		 1529 (set (match_dup 0)
1530 (compare:CC (match_dup 2)
1531 (const_int 0)))]
1532 "")
1fd4e8c1
RK		 1533
1534(define_insn ""
9ebbca7d 1535 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 1536 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 1537 (const_int 0)))
0354e5d8
GK		 1538 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1539 (neg:P (match_dup 1)))]
1540 ""
9ebbca7d
GK		 1541 "@
1542 neg. %0,%1
1543 #"
a62bfff2 1544 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 1545 (set_attr "length" "4,8")])
1546
1547(define_split
1548 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 1549 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 1550 (const_int 0)))
0354e5d8
GK		 1551 (set (match_operand:P 0 "gpc_reg_operand" "")
1552 (neg:P (match_dup 1)))]
66859ace 1553 "reload_completed"
9ebbca7d 1554 [(set (match_dup 0)
0354e5d8 1555 (neg:P (match_dup 1)))
9ebbca7d
GK		 1556 (set (match_dup 2)
1557 (compare:CC (match_dup 0)
1558 (const_int 0)))]
1559 "")
1fd4e8c1 1560
0354e5d8
GK		 1561(define_insn "clz<mode>2"
1562 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1563 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1b1edcfa 1564 ""
0354e5d8 1565 "{cntlz|cntlz<wd>} %0,%1")
1b1edcfa 1566
0354e5d8 1567(define_expand "ctz<mode>2"
4977bab6 1568 [(set (match_dup 2)
0354e5d8
GK		 1569 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1570 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1571 (match_dup 2)))
1b1edcfa 1572 (clobber (scratch:CC))])
0354e5d8
GK		 1573 (set (match_dup 4) (clz:GPR (match_dup 3)))
1574 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1575 (minus:GPR (match_dup 5) (match_dup 4)))]
1fd4e8c1 1576 ""
4977bab6 1577 {
0354e5d8
GK		 1578 operands[2] = gen_reg_rtx (<MODE>mode);
1579 operands[3] = gen_reg_rtx (<MODE>mode);
1580 operands[4] = gen_reg_rtx (<MODE>mode);
1581 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
4977bab6 1582 })
6ae08853 1583
0354e5d8 1584(define_expand "ffs<mode>2"
1b1edcfa 1585 [(set (match_dup 2)
0354e5d8
GK		 1586 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1587 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1588 (match_dup 2)))
1b1edcfa 1589 (clobber (scratch:CC))])
0354e5d8
GK		 1590 (set (match_dup 4) (clz:GPR (match_dup 3)))
1591 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1592 (minus:GPR (match_dup 5) (match_dup 4)))]
4977bab6 1593 ""
1b1edcfa 1594 {
0354e5d8
GK		 1595 operands[2] = gen_reg_rtx (<MODE>mode);
1596 operands[3] = gen_reg_rtx (<MODE>mode);
1597 operands[4] = gen_reg_rtx (<MODE>mode);
1598 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1b1edcfa 1599 })
6ae08853 1600
432218ba
DE		 1601(define_expand "popcount<mode>2"
1602 [(set (match_dup 2)
1603 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1604 UNSPEC_POPCNTB))
1605 (set (match_dup 3)
1606 (mult:GPR (match_dup 2) (match_dup 4)))
1607 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1608 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1609 "TARGET_POPCNTB"
1610 {
1611 operands[2] = gen_reg_rtx (<MODE>mode);
1612 operands[3] = gen_reg_rtx (<MODE>mode);
1e0aa44a
DE		 1613 operands[4] = force_reg (<MODE>mode,
1614 <MODE>mode == SImode
1615 ? GEN_INT (0x01010101)
1616 : GEN_INT ((HOST_WIDE_INT)
1617 0x01010101 << 32 | 0x01010101));
432218ba
DE		 1618 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1619 })
1620
1621(define_insn "popcntb<mode>2"
1622 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1623 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1624 UNSPEC_POPCNTB))]
1625 "TARGET_POPCNTB"
1626 "popcntb %0,%1")
1627
ca7f5001
RK		 1628(define_expand "mulsi3"
1629 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1630 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1631 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1632 ""
1633 "
1634{
1635 if (TARGET_POWER)
68b40e7e 1636 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 1637 else
68b40e7e 1638 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 1639 DONE;
1640}")
1641
68b40e7e 1642(define_insn "mulsi3_mq"
cd2b37d9
RK		 1643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1644 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 1645 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1646 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 1647 "TARGET_POWER"
1648 "@
1649 {muls|mullw} %0,%1,%2
1650 {muli|mulli} %0,%1,%2"
6ae08853 1651 [(set (attr "type")
c859cda6
DJ		 1652 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1653 (const_string "imul3")
6ae08853 1654 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 1655 (const_string "imul2")]
1656 (const_string "imul")))])
ca7f5001 1657
68b40e7e 1658(define_insn "mulsi3_no_mq"
ca7f5001
RK		 1659 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1660 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1661 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 1662 "! TARGET_POWER"
1fd4e8c1 1663 "@
d904e9ed
RK		 1664 {muls|mullw} %0,%1,%2
1665 {muli|mulli} %0,%1,%2"
6ae08853 1666 [(set (attr "type")
c859cda6
DJ		 1667 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1668 (const_string "imul3")
6ae08853 1669 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 1670 (const_string "imul2")]
1671 (const_string "imul")))])
1fd4e8c1 1672
9259f3b0 1673(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 1674 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1675 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1676 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1677 (const_int 0)))
9ebbca7d
GK		 1678 (clobber (match_scratch:SI 3 "=r,r"))
1679 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 1680 "TARGET_POWER"
9ebbca7d
GK		 1681 "@
1682 {muls.|mullw.} %3,%1,%2
1683 #"
9259f3b0 1684 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1685 (set_attr "length" "4,8")])
1686
1687(define_split
1688 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1689 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1690 (match_operand:SI 2 "gpc_reg_operand" ""))
1691 (const_int 0)))
1692 (clobber (match_scratch:SI 3 ""))
1693 (clobber (match_scratch:SI 4 ""))]
1694 "TARGET_POWER && reload_completed"
1695 [(parallel [(set (match_dup 3)
1696 (mult:SI (match_dup 1) (match_dup 2)))
1697 (clobber (match_dup 4))])
1698 (set (match_dup 0)
1699 (compare:CC (match_dup 3)
1700 (const_int 0)))]
1701 "")
ca7f5001 1702
9259f3b0 1703(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 1704 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1705 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1706 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 1707 (const_int 0)))
9ebbca7d 1708 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 1709 "! TARGET_POWER"
9ebbca7d
GK		 1710 "@
1711 {muls.|mullw.} %3,%1,%2
1712 #"
9259f3b0 1713 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1714 (set_attr "length" "4,8")])
1715
1716(define_split
1717 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1718 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1719 (match_operand:SI 2 "gpc_reg_operand" ""))
1720 (const_int 0)))
1721 (clobber (match_scratch:SI 3 ""))]
1722 "! TARGET_POWER && reload_completed"
1723 [(set (match_dup 3)
1724 (mult:SI (match_dup 1) (match_dup 2)))
1725 (set (match_dup 0)
1726 (compare:CC (match_dup 3)
1727 (const_int 0)))]
1728 "")
1fd4e8c1 1729
9259f3b0 1730(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 1731 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1732 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1733 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1734 (const_int 0)))
9ebbca7d 1735 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 1736 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 1737 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 1738 "TARGET_POWER"
9ebbca7d
GK		 1739 "@
1740 {muls.|mullw.} %0,%1,%2
1741 #"
9259f3b0 1742 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1743 (set_attr "length" "4,8")])
1744
1745(define_split
1746 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1747 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1748 (match_operand:SI 2 "gpc_reg_operand" ""))
1749 (const_int 0)))
1750 (set (match_operand:SI 0 "gpc_reg_operand" "")
1751 (mult:SI (match_dup 1) (match_dup 2)))
1752 (clobber (match_scratch:SI 4 ""))]
1753 "TARGET_POWER && reload_completed"
1754 [(parallel [(set (match_dup 0)
1755 (mult:SI (match_dup 1) (match_dup 2)))
1756 (clobber (match_dup 4))])
1757 (set (match_dup 3)
1758 (compare:CC (match_dup 0)
1759 (const_int 0)))]
1760 "")
ca7f5001 1761
9259f3b0 1762(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 1763 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1764 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1765 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 1766 (const_int 0)))
9ebbca7d 1767 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 1768 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 1769 "! TARGET_POWER"
9ebbca7d
GK		 1770 "@
1771 {muls.|mullw.} %0,%1,%2
1772 #"
9259f3b0 1773 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1774 (set_attr "length" "4,8")])
1775
1776(define_split
1777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1778 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1779 (match_operand:SI 2 "gpc_reg_operand" ""))
1780 (const_int 0)))
1781 (set (match_operand:SI 0 "gpc_reg_operand" "")
1782 (mult:SI (match_dup 1) (match_dup 2)))]
1783 "! TARGET_POWER && reload_completed"
1784 [(set (match_dup 0)
1785 (mult:SI (match_dup 1) (match_dup 2)))
1786 (set (match_dup 3)
1787 (compare:CC (match_dup 0)
1788 (const_int 0)))]
1789 "")
1fd4e8c1
RK		 1790
1791;; Operand 1 is divided by operand 2; quotient goes to operand
1792;; 0 and remainder to operand 3.
1793;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1794
8ffd9c51
RK		 1795(define_expand "divmodsi4"
1796 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1797 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1798 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 1799 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 1800 (mod:SI (match_dup 1) (match_dup 2)))])]
1801 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1802 "
1803{
1804 if (! TARGET_POWER && ! TARGET_POWERPC)
1805 {
39403d82
DE		 1806 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1807 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1808 emit_insn (gen_divss_call ());
39403d82
DE		 1809 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1810 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 1811 DONE;
1812 }
1813}")
deb9225a 1814
bb157ff4 1815(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 1816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1817 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1818 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 1819 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 1820 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 1821 "TARGET_POWER"
cfb557c4
RK		 1822 "divs %0,%1,%2"
1823 [(set_attr "type" "idiv")])
1fd4e8c1 1824
4ae234b0
GK		 1825(define_expand "udiv<mode>3"
1826 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1827 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1828 (match_operand:GPR 2 "gpc_reg_operand" "")))]
8ffd9c51
RK		 1829 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1830 "
1831{
1832 if (! TARGET_POWER && ! TARGET_POWERPC)
1833 {
39403d82
DE		 1834 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1835 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1836 emit_insn (gen_quous_call ());
39403d82 1837 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 1838 DONE;
1839 }
f192bf8b
DE		 1840 else if (TARGET_POWER)
1841 {
1842 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1843 DONE;
1844 }
8ffd9c51 1845}")
deb9225a 1846
f192bf8b
DE		 1847(define_insn "udivsi3_mq"
1848 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1849 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1850 (match_operand:SI 2 "gpc_reg_operand" "r")))
1851 (clobber (match_scratch:SI 3 "=q"))]
1852 "TARGET_POWERPC && TARGET_POWER"
1853 "divwu %0,%1,%2"
1854 [(set_attr "type" "idiv")])
1855
1856(define_insn "*udivsi3_no_mq"
4ae234b0
GK		 1857 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1858 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1859 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 1860 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 1861 "div<wd>u %0,%1,%2"
ca7f5001
RK		 1862 [(set_attr "type" "idiv")])
1863
1fd4e8c1 1864;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 1865;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 1866;; used; for PowerPC, force operands into register and do a normal divide;
1867;; for AIX common-mode, use quoss call on register operands.
4ae234b0
GK		 1868(define_expand "div<mode>3"
1869 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1870 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1871 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1fd4e8c1
RK		 1872 ""
1873 "
1874{
ca7f5001 1875 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 1876 && INTVAL (operands[2]) > 0
ca7f5001
RK		 1877 && exact_log2 (INTVAL (operands[2])) >= 0)
1878 ;
b6c9286a 1879 else if (TARGET_POWERPC)
f192bf8b
DE		 1880 {
1881 operands[2] = force_reg (SImode, operands[2]);
1882 if (TARGET_POWER)
1883 {
1884 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1885 DONE;
1886 }
1887 }
b6c9286a 1888 else if (TARGET_POWER)
1fd4e8c1 1889 FAIL;
405c5495 1890 else
8ffd9c51 1891 {
39403d82
DE		 1892 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1893 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1894 emit_insn (gen_quoss_call ());
39403d82 1895 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 1896 DONE;
1897 }
1fd4e8c1
RK		 1898}")
1899
f192bf8b
DE		 1900(define_insn "divsi3_mq"
1901 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1902 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1903 (match_operand:SI 2 "gpc_reg_operand" "r")))
1904 (clobber (match_scratch:SI 3 "=q"))]
1905 "TARGET_POWERPC && TARGET_POWER"
1906 "divw %0,%1,%2"
1907 [(set_attr "type" "idiv")])
1908
4ae234b0
GK		 1909(define_insn "*div<mode>3_no_mq"
1910 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1911 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1912 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 1913 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 1914 "div<wd> %0,%1,%2"
f192bf8b
DE		 1915 [(set_attr "type" "idiv")])
1916
4ae234b0
GK		 1917(define_expand "mod<mode>3"
1918 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
1919 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
1920 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
39b52ba2 1921 ""
1fd4e8c1
RK		 1922 "
1923{
481c7efa 1924 int i;
39b52ba2
RK		 1925 rtx temp1;
1926 rtx temp2;
1927
2bfcf297 1928 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 1929 || INTVAL (operands[2]) <= 0
2bfcf297 1930 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 1931 FAIL;
1932
4ae234b0
GK		 1933 temp1 = gen_reg_rtx (<MODE>mode);
1934 temp2 = gen_reg_rtx (<MODE>mode);
1fd4e8c1 1935
4ae234b0
GK		 1936 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
1937 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
1938 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
85644414 1939 DONE;
1fd4e8c1
RK		 1940}")
1941
1942(define_insn ""
4ae234b0
GK		 1943 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1944 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1945 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2bfcf297 1946 ""
4ae234b0 1947 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
943c15ed
DE		 1948 [(set_attr "type" "two")
1949 (set_attr "length" "8")])
1fd4e8c1
RK		 1950
1951(define_insn ""
9ebbca7d 1952 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 1953 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1954 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 1955 (const_int 0)))
4ae234b0 1956 (clobber (match_scratch:P 3 "=r,r"))]
2bfcf297 1957 ""
9ebbca7d 1958 "@
4ae234b0 1959 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
9ebbca7d 1960 #"
b19003d8 1961 [(set_attr "type" "compare")
9ebbca7d
GK		 1962 (set_attr "length" "8,12")])
1963
1964(define_split
1965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 1966 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1967 (match_operand:GPR 2 "exact_log2_cint_operand"
1968 ""))
9ebbca7d 1969 (const_int 0)))
4ae234b0 1970 (clobber (match_scratch:GPR 3 ""))]
2bfcf297 1971 "reload_completed"
9ebbca7d 1972 [(set (match_dup 3)
4ae234b0 1973 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 1974 (set (match_dup 0)
1975 (compare:CC (match_dup 3)
1976 (const_int 0)))]
1977 "")
1fd4e8c1
RK		 1978
1979(define_insn ""
9ebbca7d 1980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 1981 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1982 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 1983 (const_int 0)))
4ae234b0
GK		 1984 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1985 (div:P (match_dup 1) (match_dup 2)))]
2bfcf297 1986 ""
9ebbca7d 1987 "@
4ae234b0 1988 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
9ebbca7d 1989 #"
b19003d8 1990 [(set_attr "type" "compare")
9ebbca7d
GK		 1991 (set_attr "length" "8,12")])
1992
1993(define_split
1994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 1995 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1996 (match_operand:GPR 2 "exact_log2_cint_operand"
1997 ""))
9ebbca7d 1998 (const_int 0)))
4ae234b0
GK		 1999 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2000 (div:GPR (match_dup 1) (match_dup 2)))]
2bfcf297 2001 "reload_completed"
9ebbca7d 2002 [(set (match_dup 0)
4ae234b0 2003 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2004 (set (match_dup 3)
2005 (compare:CC (match_dup 0)
2006 (const_int 0)))]
2007 "")
1fd4e8c1
RK		 2008
2009(define_insn ""
cd2b37d9 2010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2011 (udiv:SI
996a5f59 2012 (plus:DI (ashift:DI
cd2b37d9 2013 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2014 (const_int 32))
23a900dc 2015 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2016 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2017 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2018 (umod:SI
996a5f59 2019 (plus:DI (ashift:DI
1fd4e8c1 2020 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2021 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2022 (match_dup 3)))]
ca7f5001 2023 "TARGET_POWER"
cfb557c4
RK		 2024 "div %0,%1,%3"
2025 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2026
2027;; To do unsigned divide we handle the cases of the divisor looking like a
2028;; negative number. If it is a constant that is less than 2**31, we don't
2029;; have to worry about the branches. So make a few subroutines here.
2030;;
2031;; First comes the normal case.
2032(define_expand "udivmodsi4_normal"
2033 [(set (match_dup 4) (const_int 0))
2034 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2035 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2036 (const_int 32))
2037 (zero_extend:DI (match_operand:SI 1 "" "")))
2038 (match_operand:SI 2 "" "")))
2039 (set (match_operand:SI 3 "" "")
996a5f59 2040 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2041 (const_int 32))
2042 (zero_extend:DI (match_dup 1)))
2043 (match_dup 2)))])]
ca7f5001 2044 "TARGET_POWER"
1fd4e8c1
RK		 2045 "
2046{ operands[4] = gen_reg_rtx (SImode); }")
2047
2048;; This handles the branches.
2049(define_expand "udivmodsi4_tests"
2050 [(set (match_operand:SI 0 "" "") (const_int 0))
2051 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2052 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2053 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2054 (label_ref (match_operand:SI 4 "" "")) (pc)))
2055 (set (match_dup 0) (const_int 1))
2056 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2057 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2058 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2059 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2060 "TARGET_POWER"
1fd4e8c1
RK		 2061 "
2062{ operands[5] = gen_reg_rtx (CCUNSmode);
2063 operands[6] = gen_reg_rtx (CCmode);
2064}")
2065
2066(define_expand "udivmodsi4"
cd2b37d9
RK		 2067 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2068 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2069 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2070 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2071 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2072 ""
1fd4e8c1
RK		 2073 "
2074{
2075 rtx label = 0;
2076
8ffd9c51 2077 if (! TARGET_POWER)
c4d38ccb
MM		 2078 {
2079 if (! TARGET_POWERPC)
2080 {
39403d82
DE		 2081 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2082 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2083 emit_insn (gen_divus_call ());
39403d82
DE		 2084 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2085 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2086 DONE;
2087 }
2088 else
2089 FAIL;
2090 }
0081a354 2091
1fd4e8c1
RK		 2092 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2093 {
2094 operands[2] = force_reg (SImode, operands[2]);
2095 label = gen_label_rtx ();
2096 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2097 operands[3], label));
2098 }
2099 else
2100 operands[2] = force_reg (SImode, operands[2]);
2101
2102 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2103 operands[3]));
2104 if (label)
2105 emit_label (label);
2106
2107 DONE;
2108}")
0081a354 2109
fada905b
MM		 2110;; AIX architecture-independent common-mode multiply (DImode),
2111;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2112;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2113;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2114;; assumed unused if generating common-mode, so ignore.
2115(define_insn "mulh_call"
2116 [(set (reg:SI 3)
2117 (truncate:SI
2118 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2119 (sign_extend:DI (reg:SI 4)))
2120 (const_int 32))))
cf27b467 2121 (clobber (match_scratch:SI 0 "=l"))]
fada905b 2122 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2123 "bla __mulh"
2124 [(set_attr "type" "imul")])
fada905b
MM		 2125
2126(define_insn "mull_call"
2127 [(set (reg:DI 3)
2128 (mult:DI (sign_extend:DI (reg:SI 3))
2129 (sign_extend:DI (reg:SI 4))))
2130 (clobber (match_scratch:SI 0 "=l"))
2131 (clobber (reg:SI 0))]
2132 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2133 "bla __mull"
2134 [(set_attr "type" "imul")])
fada905b
MM		 2135
2136(define_insn "divss_call"
2137 [(set (reg:SI 3)
2138 (div:SI (reg:SI 3) (reg:SI 4)))
2139 (set (reg:SI 4)
2140 (mod:SI (reg:SI 3) (reg:SI 4)))
2141 (clobber (match_scratch:SI 0 "=l"))
2142 (clobber (reg:SI 0))]
2143 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2144 "bla __divss"
2145 [(set_attr "type" "idiv")])
fada905b
MM		 2146
2147(define_insn "divus_call"
8ffd9c51
RK		 2148 [(set (reg:SI 3)
2149 (udiv:SI (reg:SI 3) (reg:SI 4)))
2150 (set (reg:SI 4)
2151 (umod:SI (reg:SI 3) (reg:SI 4)))
2152 (clobber (match_scratch:SI 0 "=l"))
fada905b
MM		 2153 (clobber (reg:SI 0))
2154 (clobber (match_scratch:CC 1 "=x"))
2155 (clobber (reg:CC 69))]
2156 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2157 "bla __divus"
2158 [(set_attr "type" "idiv")])
fada905b
MM		 2159
2160(define_insn "quoss_call"
2161 [(set (reg:SI 3)
2162 (div:SI (reg:SI 3) (reg:SI 4)))
cf27b467 2163 (clobber (match_scratch:SI 0 "=l"))]
8ffd9c51 2164 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2165 "bla __quoss"
2166 [(set_attr "type" "idiv")])
0081a354 2167
fada905b
MM		 2168(define_insn "quous_call"
2169 [(set (reg:SI 3)
2170 (udiv:SI (reg:SI 3) (reg:SI 4)))
2171 (clobber (match_scratch:SI 0 "=l"))
2172 (clobber (reg:SI 0))
2173 (clobber (match_scratch:CC 1 "=x"))
2174 (clobber (reg:CC 69))]
2175 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2176 "bla __quous"
2177 [(set_attr "type" "idiv")])
8ffd9c51 2178\f
bb21487f 2179;; Logical instructions
dfbdccdb
GK		 2180;; The logical instructions are mostly combined by using match_operator,
2181;; but the plain AND insns are somewhat different because there is no
2182;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2183;; those rotate-and-mask operations. Thus, the AND insns come first.
2184
29ae5b89
JL		 2185(define_insn "andsi3"
2186 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2187 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2188 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2189 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1fd4e8c1
RK		 2190 ""
2191 "@
2192 and %0,%1,%2
ca7f5001
RK		 2193 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2194 {andil.|andi.} %0,%1,%b2
520308bc
DE		 2195 {andiu.|andis.} %0,%1,%u2"
2196 [(set_attr "type" "*,*,compare,compare")])
52d3af72
DE		 2197
2198;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2199;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2200;; machines causes an execution serialization
1fd4e8c1 2201
7cd5235b 2202(define_insn "*andsi3_internal2"
52d3af72
DE		 2203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2204 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2205 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2206 (const_int 0)))
52d3af72
DE		 2207 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2208 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2209 "TARGET_32BIT"
1fd4e8c1
RK		 2210 "@
2211 and. %3,%1,%2
ca7f5001
RK		 2212 {andil.|andi.} %3,%1,%b2
2213 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2214 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2215 #
2216 #
2217 #
2218 #"
2219 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2220 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2221
0ba1b2ff
AM		 2222(define_insn "*andsi3_internal3"
2223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2224 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2225 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2226 (const_int 0)))
2227 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2228 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2229 "TARGET_64BIT"
0ba1b2ff
AM		 2230 "@
2231 #
2232 {andil.|andi.} %3,%1,%b2
2233 {andiu.|andis.} %3,%1,%u2
2234 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2235 #
2236 #
2237 #
2238 #"
2239 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2240 (set_attr "length" "8,4,4,4,8,8,8,8")])
2241
52d3af72
DE		 2242(define_split
2243 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2244 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2245 (match_operand:GPR 2 "and_operand" ""))
1fd4e8c1 2246 (const_int 0)))
4ae234b0 2247 (clobber (match_scratch:GPR 3 ""))
52d3af72 2248 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2249 "reload_completed"
52d3af72 2250 [(parallel [(set (match_dup 3)
4ae234b0
GK		 2251 (and:<MODE> (match_dup 1)
2252 (match_dup 2)))
52d3af72
DE		 2253 (clobber (match_dup 4))])
2254 (set (match_dup 0)
2255 (compare:CC (match_dup 3)
2256 (const_int 0)))]
2257 "")
2258
0ba1b2ff
AM		 2259;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2260;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2261
2262(define_split
2263 [(set (match_operand:CC 0 "cc_reg_operand" "")
2264 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2265 (match_operand:SI 2 "gpc_reg_operand" ""))
2266 (const_int 0)))
2267 (clobber (match_scratch:SI 3 ""))
2268 (clobber (match_scratch:CC 4 ""))]
2269 "TARGET_POWERPC64 && reload_completed"
2270 [(parallel [(set (match_dup 3)
2271 (and:SI (match_dup 1)
2272 (match_dup 2)))
2273 (clobber (match_dup 4))])
2274 (set (match_dup 0)
2275 (compare:CC (match_dup 3)
2276 (const_int 0)))]
2277 "")
2278
2279(define_insn "*andsi3_internal4"
52d3af72
DE		 2280 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2281 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2282 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2283 (const_int 0)))
2284 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2285 (and:SI (match_dup 1)
2286 (match_dup 2)))
2287 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2288 "TARGET_32BIT"
1fd4e8c1
RK		 2289 "@
2290 and. %0,%1,%2
ca7f5001
RK		 2291 {andil.|andi.} %0,%1,%b2
2292 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2293 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2294 #
2295 #
2296 #
2297 #"
2298 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2299 (set_attr "length" "4,4,4,4,8,8,8,8")])
2300
0ba1b2ff
AM		 2301(define_insn "*andsi3_internal5"
2302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2303 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2304 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2305 (const_int 0)))
2306 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2307 (and:SI (match_dup 1)
2308 (match_dup 2)))
2309 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2310 "TARGET_64BIT"
0ba1b2ff
AM		 2311 "@
2312 #
2313 {andil.|andi.} %0,%1,%b2
2314 {andiu.|andis.} %0,%1,%u2
2315 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2316 #
2317 #
2318 #
2319 #"
2320 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2321 (set_attr "length" "8,4,4,4,8,8,8,8")])
2322
52d3af72
DE		 2323(define_split
2324 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2326 (match_operand:SI 2 "and_operand" ""))
2327 (const_int 0)))
2328 (set (match_operand:SI 0 "gpc_reg_operand" "")
2329 (and:SI (match_dup 1)
2330 (match_dup 2)))
2331 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2332 "reload_completed"
52d3af72
DE		 2333 [(parallel [(set (match_dup 0)
2334 (and:SI (match_dup 1)
2335 (match_dup 2)))
2336 (clobber (match_dup 4))])
2337 (set (match_dup 3)
2338 (compare:CC (match_dup 0)
2339 (const_int 0)))]
2340 "")
1fd4e8c1 2341
0ba1b2ff
AM		 2342(define_split
2343 [(set (match_operand:CC 3 "cc_reg_operand" "")
2344 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2345 (match_operand:SI 2 "gpc_reg_operand" ""))
2346 (const_int 0)))
2347 (set (match_operand:SI 0 "gpc_reg_operand" "")
2348 (and:SI (match_dup 1)
2349 (match_dup 2)))
2350 (clobber (match_scratch:CC 4 ""))]
2351 "TARGET_POWERPC64 && reload_completed"
2352 [(parallel [(set (match_dup 0)
2353 (and:SI (match_dup 1)
2354 (match_dup 2)))
2355 (clobber (match_dup 4))])
2356 (set (match_dup 3)
2357 (compare:CC (match_dup 0)
2358 (const_int 0)))]
2359 "")
2360
2361;; Handle the PowerPC64 rlwinm corner case
2362
2363(define_insn_and_split "*andsi3_internal6"
2364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2365 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2366 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2367 "TARGET_POWERPC64"
2368 "#"
2369 "TARGET_POWERPC64"
2370 [(set (match_dup 0)
2371 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2372 (match_dup 4)))
2373 (set (match_dup 0)
2374 (rotate:SI (match_dup 0) (match_dup 5)))]
2375 "
2376{
2377 int mb = extract_MB (operands[2]);
2378 int me = extract_ME (operands[2]);
2379 operands[3] = GEN_INT (me + 1);
2380 operands[5] = GEN_INT (32 - (me + 1));
2381 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2382}"
2383 [(set_attr "length" "8")])
2384
7cd5235b 2385(define_expand "iorsi3"
cd2b37d9 2386 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 2387 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 2388 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 2389 ""
f357808b
RK		 2390 "
2391{
7cd5235b 2392 if (GET_CODE (operands[2]) == CONST_INT
677a9668 2393 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 2394 {
2395 HOST_WIDE_INT value = INTVAL (operands[2]);
677a9668 2396 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 2397 ? operands[0] : gen_reg_rtx (SImode));
2398
a260abc9
DE		 2399 emit_insn (gen_iorsi3 (tmp, operands[1],
2400 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2401 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 2402 DONE;
2403 }
f357808b
RK		 2404}")
2405
7cd5235b 2406(define_expand "xorsi3"
cd2b37d9 2407 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 2408 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 2409 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 2410 ""
7cd5235b 2411 "
1fd4e8c1 2412{
7cd5235b 2413 if (GET_CODE (operands[2]) == CONST_INT
677a9668 2414 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 2415 {
2416 HOST_WIDE_INT value = INTVAL (operands[2]);
677a9668 2417 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 2418 ? operands[0] : gen_reg_rtx (SImode));
2419
a260abc9
DE		 2420 emit_insn (gen_xorsi3 (tmp, operands[1],
2421 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2422 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 2423 DONE;
2424 }
1fd4e8c1
RK		 2425}")
2426
dfbdccdb 2427(define_insn "*boolsi3_internal1"
7cd5235b 2428 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 2429 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 2430 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2431 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 2432 ""
2433 "@
dfbdccdb
GK		 2434 %q3 %0,%1,%2
2435 {%q3il|%q3i} %0,%1,%b2
2436 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 2437
dfbdccdb 2438(define_insn "*boolsi3_internal2"
52d3af72 2439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 2440 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 2441 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2442 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2443 (const_int 0)))
52d3af72 2444 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 2445 "TARGET_32BIT"
52d3af72 2446 "@
dfbdccdb 2447 %q4. %3,%1,%2
52d3af72
DE		 2448 #"
2449 [(set_attr "type" "compare")
2450 (set_attr "length" "4,8")])
2451
2452(define_split
2453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2454 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2455 [(match_operand:SI 1 "gpc_reg_operand" "")
2456 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2457 (const_int 0)))
52d3af72 2458 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 2459 "TARGET_32BIT && reload_completed"
dfbdccdb 2460 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2461 (set (match_dup 0)
2462 (compare:CC (match_dup 3)
2463 (const_int 0)))]
2464 "")
815cdc52 2465
dfbdccdb 2466(define_insn "*boolsi3_internal3"
52d3af72 2467 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2468 (compare:CC (match_operator:SI 4 "boolean_operator"
2469 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2470 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2471 (const_int 0)))
52d3af72 2472 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2473 (match_dup 4))]
4b8a63d6 2474 "TARGET_32BIT"
52d3af72 2475 "@
dfbdccdb 2476 %q4. %0,%1,%2
52d3af72
DE		 2477 #"
2478 [(set_attr "type" "compare")
2479 (set_attr "length" "4,8")])
2480
2481(define_split
e72247f4 2482 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2483 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2484 [(match_operand:SI 1 "gpc_reg_operand" "")
2485 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2486 (const_int 0)))
75540af0 2487 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2488 (match_dup 4))]
4b8a63d6 2489 "TARGET_32BIT && reload_completed"
dfbdccdb 2490 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2491 (set (match_dup 3)
2492 (compare:CC (match_dup 0)
2493 (const_int 0)))]
2494 "")
1fd4e8c1 2495
6ae08853 2496;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 2497;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 2498
2499(define_split
2500 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 2501 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 2502 [(match_operand:SI 1 "gpc_reg_operand" "")
2503 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 2504 ""
dfbdccdb
GK		 2505 [(set (match_dup 0) (match_dup 4))
2506 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 2507"
2508{
dfbdccdb
GK		 2509 rtx i;
2510 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1c563bed 2511 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 2512 operands[1], i);
dfbdccdb 2513 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
1c563bed 2514 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 2515 operands[0], i);
a260abc9
DE		 2516}")
2517
dfbdccdb 2518(define_insn "*boolcsi3_internal1"
cd2b37d9 2519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 2520 (match_operator:SI 3 "boolean_operator"
2521 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 2522 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 2523 ""
dfbdccdb 2524 "%q3 %0,%2,%1")
1fd4e8c1 2525
dfbdccdb 2526(define_insn "*boolcsi3_internal2"
52d3af72 2527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2528 (compare:CC (match_operator:SI 4 "boolean_operator"
2529 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2530 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2531 (const_int 0)))
52d3af72 2532 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 2533 "TARGET_32BIT"
52d3af72 2534 "@
dfbdccdb 2535 %q4. %3,%2,%1
52d3af72
DE		 2536 #"
2537 [(set_attr "type" "compare")
2538 (set_attr "length" "4,8")])
2539
2540(define_split
2541 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2542 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2543 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2544 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2545 (const_int 0)))
52d3af72 2546 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 2547 "TARGET_32BIT && reload_completed"
dfbdccdb 2548 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2549 (set (match_dup 0)
2550 (compare:CC (match_dup 3)
2551 (const_int 0)))]
2552 "")
1fd4e8c1 2553
dfbdccdb 2554(define_insn "*boolcsi3_internal3"
52d3af72 2555 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2556 (compare:CC (match_operator:SI 4 "boolean_operator"
2557 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2558 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2559 (const_int 0)))
52d3af72 2560 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2561 (match_dup 4))]
4b8a63d6 2562 "TARGET_32BIT"
52d3af72 2563 "@
dfbdccdb 2564 %q4. %0,%2,%1
52d3af72
DE		 2565 #"
2566 [(set_attr "type" "compare")
2567 (set_attr "length" "4,8")])
2568
2569(define_split
e72247f4 2570 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2571 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2572 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2573 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2574 (const_int 0)))
75540af0 2575 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2576 (match_dup 4))]
4b8a63d6 2577 "TARGET_32BIT && reload_completed"
dfbdccdb 2578 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2579 (set (match_dup 3)
2580 (compare:CC (match_dup 0)
2581 (const_int 0)))]
2582 "")
2583
dfbdccdb 2584(define_insn "*boolccsi3_internal1"
cd2b37d9 2585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 2586 (match_operator:SI 3 "boolean_operator"
2587 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 2588 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 2589 ""
dfbdccdb 2590 "%q3 %0,%1,%2")
1fd4e8c1 2591
dfbdccdb 2592(define_insn "*boolccsi3_internal2"
52d3af72 2593 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2594 (compare:CC (match_operator:SI 4 "boolean_operator"
2595 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2596 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2597 (const_int 0)))
52d3af72 2598 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 2599 "TARGET_32BIT"
52d3af72 2600 "@
dfbdccdb 2601 %q4. %3,%1,%2
52d3af72
DE		 2602 #"
2603 [(set_attr "type" "compare")
2604 (set_attr "length" "4,8")])
2605
2606(define_split
2607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2608 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2609 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2610 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 2611 (const_int 0)))
52d3af72 2612 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 2613 "TARGET_32BIT && reload_completed"
dfbdccdb 2614 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2615 (set (match_dup 0)
2616 (compare:CC (match_dup 3)
2617 (const_int 0)))]
2618 "")
1fd4e8c1 2619
dfbdccdb 2620(define_insn "*boolccsi3_internal3"
52d3af72 2621 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2622 (compare:CC (match_operator:SI 4 "boolean_operator"
2623 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2624 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2625 (const_int 0)))
52d3af72 2626 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2627 (match_dup 4))]
4b8a63d6 2628 "TARGET_32BIT"
52d3af72 2629 "@
dfbdccdb 2630 %q4. %0,%1,%2
52d3af72
DE		 2631 #"
2632 [(set_attr "type" "compare")
2633 (set_attr "length" "4,8")])
2634
2635(define_split
e72247f4 2636 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2637 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2638 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2639 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 2640 (const_int 0)))
75540af0 2641 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2642 (match_dup 4))]
4b8a63d6 2643 "TARGET_32BIT && reload_completed"
dfbdccdb 2644 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2645 (set (match_dup 3)
2646 (compare:CC (match_dup 0)
2647 (const_int 0)))]
2648 "")
1fd4e8c1
RK		 2649
2650;; maskir insn. We need four forms because things might be in arbitrary
2651;; orders. Don't define forms that only set CR fields because these
2652;; would modify an input register.
2653
7cd5235b 2654(define_insn "*maskir_internal1"
cd2b37d9 2655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 2656 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2657 (match_operand:SI 1 "gpc_reg_operand" "0"))
2658 (and:SI (match_dup 2)
cd2b37d9 2659 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 2660 "TARGET_POWER"
01def764 2661 "maskir %0,%3,%2")
1fd4e8c1 2662
7cd5235b 2663(define_insn "*maskir_internal2"
242e8072 2664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 2665 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2666 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 2667 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 2668 (match_dup 2))))]
ca7f5001 2669 "TARGET_POWER"
01def764 2670 "maskir %0,%3,%2")
1fd4e8c1 2671
7cd5235b 2672(define_insn "*maskir_internal3"
cd2b37d9 2673 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 2674 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 2675 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 2676 (and:SI (not:SI (match_dup 2))
2677 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 2678 "TARGET_POWER"
01def764 2679 "maskir %0,%3,%2")
1fd4e8c1 2680
7cd5235b 2681(define_insn "*maskir_internal4"
cd2b37d9
RK		 2682 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2683 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 2684 (match_operand:SI 2 "gpc_reg_operand" "r"))
2685 (and:SI (not:SI (match_dup 2))
2686 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 2687 "TARGET_POWER"
01def764 2688 "maskir %0,%3,%2")
1fd4e8c1 2689
7cd5235b 2690(define_insn "*maskir_internal5"
9ebbca7d 2691 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2692 (compare:CC
9ebbca7d
GK		 2693 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2694 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 2695 (and:SI (match_dup 2)
9ebbca7d 2696 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 2697 (const_int 0)))
9ebbca7d 2698 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2699 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2700 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 2701 "TARGET_POWER"
9ebbca7d
GK		 2702 "@
2703 maskir. %0,%3,%2
2704 #"
2705 [(set_attr "type" "compare")
2706 (set_attr "length" "4,8")])
2707
2708(define_split
2709 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2710 (compare:CC
2711 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2712 (match_operand:SI 1 "gpc_reg_operand" ""))
2713 (and:SI (match_dup 2)
2714 (match_operand:SI 3 "gpc_reg_operand" "")))
2715 (const_int 0)))
2716 (set (match_operand:SI 0 "gpc_reg_operand" "")
2717 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2718 (and:SI (match_dup 2) (match_dup 3))))]
2719 "TARGET_POWER && reload_completed"
2720 [(set (match_dup 0)
2721 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2722 (and:SI (match_dup 2) (match_dup 3))))
2723 (set (match_dup 4)
2724 (compare:CC (match_dup 0)
2725 (const_int 0)))]
2726 "")
1fd4e8c1 2727
7cd5235b 2728(define_insn "*maskir_internal6"
9ebbca7d 2729 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2730 (compare:CC
9ebbca7d
GK		 2731 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2732 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2733 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 2734 (match_dup 2)))
1fd4e8c1 2735 (const_int 0)))
9ebbca7d 2736 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2737 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2738 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 2739 "TARGET_POWER"
9ebbca7d
GK		 2740 "@
2741 maskir. %0,%3,%2
2742 #"
2743 [(set_attr "type" "compare")
2744 (set_attr "length" "4,8")])
2745
2746(define_split
2747 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2748 (compare:CC
2749 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2750 (match_operand:SI 1 "gpc_reg_operand" ""))
2751 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2752 (match_dup 2)))
2753 (const_int 0)))
2754 (set (match_operand:SI 0 "gpc_reg_operand" "")
2755 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2756 (and:SI (match_dup 3) (match_dup 2))))]
2757 "TARGET_POWER && reload_completed"
2758 [(set (match_dup 0)
2759 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2760 (and:SI (match_dup 3) (match_dup 2))))
2761 (set (match_dup 4)
2762 (compare:CC (match_dup 0)
2763 (const_int 0)))]
2764 "")
1fd4e8c1 2765
7cd5235b 2766(define_insn "*maskir_internal7"
9ebbca7d 2767 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 2768 (compare:CC
9ebbca7d
GK		 2769 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2770 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 2771 (and:SI (not:SI (match_dup 2))
9ebbca7d 2772 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 2773 (const_int 0)))
9ebbca7d 2774 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 2775 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2776 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2777 "TARGET_POWER"
9ebbca7d
GK		 2778 "@
2779 maskir. %0,%3,%2
2780 #"
2781 [(set_attr "type" "compare")
2782 (set_attr "length" "4,8")])
2783
2784(define_split
2785 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2786 (compare:CC
2787 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2788 (match_operand:SI 3 "gpc_reg_operand" ""))
2789 (and:SI (not:SI (match_dup 2))
2790 (match_operand:SI 1 "gpc_reg_operand" "")))
2791 (const_int 0)))
2792 (set (match_operand:SI 0 "gpc_reg_operand" "")
2793 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2794 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2795 "TARGET_POWER && reload_completed"
2796 [(set (match_dup 0)
2797 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2798 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2799 (set (match_dup 4)
2800 (compare:CC (match_dup 0)
2801 (const_int 0)))]
2802 "")
1fd4e8c1 2803
7cd5235b 2804(define_insn "*maskir_internal8"
9ebbca7d 2805 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2806 (compare:CC
9ebbca7d
GK		 2807 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2808 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 2809 (and:SI (not:SI (match_dup 2))
9ebbca7d 2810 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 2811 (const_int 0)))
9ebbca7d 2812 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2813 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2814 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 2815 "TARGET_POWER"
9ebbca7d
GK		 2816 "@
2817 maskir. %0,%3,%2
2818 #"
2819 [(set_attr "type" "compare")
2820 (set_attr "length" "4,8")])
fcce224d 2821
9ebbca7d
GK		 2822(define_split
2823 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2824 (compare:CC
2825 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2826 (match_operand:SI 2 "gpc_reg_operand" ""))
2827 (and:SI (not:SI (match_dup 2))
2828 (match_operand:SI 1 "gpc_reg_operand" "")))
2829 (const_int 0)))
2830 (set (match_operand:SI 0 "gpc_reg_operand" "")
2831 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2832 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2833 "TARGET_POWER && reload_completed"
2834 [(set (match_dup 0)
2835 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2836 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2837 (set (match_dup 4)
2838 (compare:CC (match_dup 0)
2839 (const_int 0)))]
2840 "")
fcce224d 2841\f
1fd4e8c1
RK		 2842;; Rotate and shift insns, in all their variants. These support shifts,
2843;; field inserts and extracts, and various combinations thereof.
034c1be0 2844(define_expand "insv"
0ad91047
DE		 2845 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2846 (match_operand:SI 1 "const_int_operand" "")
2847 (match_operand:SI 2 "const_int_operand" ""))
2848 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 2849 ""
2850 "
2851{
2852 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2853 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2854 compiler if the address of the structure is taken later. */
2855 if (GET_CODE (operands[0]) == SUBREG
2856 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2857 FAIL;
a78e33fc
DE		 2858
2859 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2860 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2861 else
2862 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2863 DONE;
034c1be0
MM		 2864}")
2865
a78e33fc 2866(define_insn "insvsi"
cd2b37d9 2867 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 2868 (match_operand:SI 1 "const_int_operand" "i")
2869 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 2870 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 2871 ""
2872 "*
2873{
2874 int start = INTVAL (operands[2]) & 31;
2875 int size = INTVAL (operands[1]) & 31;
2876
89e9f3a8
MM		 2877 operands[4] = GEN_INT (32 - start - size);
2878 operands[1] = GEN_INT (start + size - 1);
a66078ee 2879 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 2880}"
2881 [(set_attr "type" "insert_word")])
1fd4e8c1 2882
a78e33fc 2883(define_insn "*insvsi_internal1"
d56d506a
RK		 2884 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2885 (match_operand:SI 1 "const_int_operand" "i")
2886 (match_operand:SI 2 "const_int_operand" "i"))
6d0a8091 2887 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
d56d506a 2888 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 2889 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 2890 "*
2891{
2892 int shift = INTVAL (operands[4]) & 31;
2893 int start = INTVAL (operands[2]) & 31;
2894 int size = INTVAL (operands[1]) & 31;
2895
89e9f3a8 2896 operands[4] = GEN_INT (shift - start - size);
6d0a8091 2897 operands[1] = GEN_INT (start + size - 1);
a66078ee 2898 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 2899}"
2900 [(set_attr "type" "insert_word")])
d56d506a 2901
a78e33fc 2902(define_insn "*insvsi_internal2"
d56d506a
RK		 2903 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2904 (match_operand:SI 1 "const_int_operand" "i")
2905 (match_operand:SI 2 "const_int_operand" "i"))
2906 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2907 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 2908 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 2909 "*
2910{
2911 int shift = INTVAL (operands[4]) & 31;
2912 int start = INTVAL (operands[2]) & 31;
2913 int size = INTVAL (operands[1]) & 31;
2914
89e9f3a8
MM		 2915 operands[4] = GEN_INT (32 - shift - start - size);
2916 operands[1] = GEN_INT (start + size - 1);
a66078ee 2917 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 2918}"
2919 [(set_attr "type" "insert_word")])
d56d506a 2920
a78e33fc 2921(define_insn "*insvsi_internal3"
d56d506a
RK		 2922 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2923 (match_operand:SI 1 "const_int_operand" "i")
2924 (match_operand:SI 2 "const_int_operand" "i"))
2925 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2926 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 2927 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 2928 "*
2929{
2930 int shift = INTVAL (operands[4]) & 31;
2931 int start = INTVAL (operands[2]) & 31;
2932 int size = INTVAL (operands[1]) & 31;
2933
89e9f3a8
MM		 2934 operands[4] = GEN_INT (32 - shift - start - size);
2935 operands[1] = GEN_INT (start + size - 1);
a66078ee 2936 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 2937}"
2938 [(set_attr "type" "insert_word")])
d56d506a 2939
a78e33fc 2940(define_insn "*insvsi_internal4"
d56d506a
RK		 2941 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2942 (match_operand:SI 1 "const_int_operand" "i")
2943 (match_operand:SI 2 "const_int_operand" "i"))
2944 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2945 (match_operand:SI 4 "const_int_operand" "i")
2946 (match_operand:SI 5 "const_int_operand" "i")))]
2947 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2948 "*
2949{
2950 int extract_start = INTVAL (operands[5]) & 31;
2951 int extract_size = INTVAL (operands[4]) & 31;
2952 int insert_start = INTVAL (operands[2]) & 31;
2953 int insert_size = INTVAL (operands[1]) & 31;
2954
2955/* Align extract field with insert field */
3a598fbe 2956 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 2957 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 2958 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 2959}"
2960 [(set_attr "type" "insert_word")])
d56d506a 2961
f241bf89
EC		 2962;; combine patterns for rlwimi
2963(define_insn "*insvsi_internal5"
2964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2965 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2966 (match_operand:SI 1 "mask_operand" "i"))
2967 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2968 (match_operand:SI 2 "const_int_operand" "i"))
2969 (match_operand:SI 5 "mask_operand" "i"))))]
2970 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
2971 "*
2972{
2973 int me = extract_ME(operands[5]);
2974 int mb = extract_MB(operands[5]);
2975 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
2976 operands[2] = GEN_INT(mb);
2977 operands[1] = GEN_INT(me);
2978 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2979}"
2980 [(set_attr "type" "insert_word")])
2981
2982(define_insn "*insvsi_internal6"
2983 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2984 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2985 (match_operand:SI 2 "const_int_operand" "i"))
2986 (match_operand:SI 5 "mask_operand" "i"))
2987 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2988 (match_operand:SI 1 "mask_operand" "i"))))]
2989 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
2990 "*
2991{
2992 int me = extract_ME(operands[5]);
2993 int mb = extract_MB(operands[5]);
2994 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
2995 operands[2] = GEN_INT(mb);
2996 operands[1] = GEN_INT(me);
2997 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2998}"
2999 [(set_attr "type" "insert_word")])
3000
a78e33fc 3001(define_insn "insvdi"
685f3906 3002 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3003 (match_operand:SI 1 "const_int_operand" "i")
3004 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3005 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3006 "TARGET_POWERPC64"
3007 "*
3008{
3009 int start = INTVAL (operands[2]) & 63;
3010 int size = INTVAL (operands[1]) & 63;
3011
a78e33fc
DE		 3012 operands[1] = GEN_INT (64 - start - size);
3013 return \"rldimi %0,%3,%H1,%H2\";
685f3906
DE		 3014}")
3015
11ac38b2
DE		 3016(define_insn "*insvdi_internal2"
3017 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3018 (match_operand:SI 1 "const_int_operand" "i")
3019 (match_operand:SI 2 "const_int_operand" "i"))
3020 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3021 (match_operand:SI 4 "const_int_operand" "i")))]
3022 "TARGET_POWERPC64
3023 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3024 "*
3025{
3026 int shift = INTVAL (operands[4]) & 63;
3027 int start = (INTVAL (operands[2]) & 63) - 32;
3028 int size = INTVAL (operands[1]) & 63;
3029
3030 operands[4] = GEN_INT (64 - shift - start - size);
3031 operands[2] = GEN_INT (start);
3032 operands[1] = GEN_INT (start + size - 1);
3033 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3034}")
3035
3036(define_insn "*insvdi_internal3"
3037 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3038 (match_operand:SI 1 "const_int_operand" "i")
3039 (match_operand:SI 2 "const_int_operand" "i"))
3040 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3041 (match_operand:SI 4 "const_int_operand" "i")))]
3042 "TARGET_POWERPC64
3043 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3044 "*
3045{
3046 int shift = INTVAL (operands[4]) & 63;
3047 int start = (INTVAL (operands[2]) & 63) - 32;
3048 int size = INTVAL (operands[1]) & 63;
3049
3050 operands[4] = GEN_INT (64 - shift - start - size);
3051 operands[2] = GEN_INT (start);
3052 operands[1] = GEN_INT (start + size - 1);
3053 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3054}")
3055
034c1be0 3056(define_expand "extzv"
0ad91047
DE		 3057 [(set (match_operand 0 "gpc_reg_operand" "")
3058 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3059 (match_operand:SI 2 "const_int_operand" "")
3060 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3061 ""
3062 "
3063{
3064 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3065 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3066 compiler if the address of the structure is taken later. */
3067 if (GET_CODE (operands[0]) == SUBREG
3068 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3069 FAIL;
a78e33fc
DE		 3070
3071 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3072 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3073 else
3074 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3075 DONE;
034c1be0
MM		 3076}")
3077
a78e33fc 3078(define_insn "extzvsi"
cd2b37d9
RK		 3079 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3080 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3081 (match_operand:SI 2 "const_int_operand" "i")
3082 (match_operand:SI 3 "const_int_operand" "i")))]
3083 ""
3084 "*
3085{
3086 int start = INTVAL (operands[3]) & 31;
3087 int size = INTVAL (operands[2]) & 31;
3088
3089 if (start + size >= 32)
3090 operands[3] = const0_rtx;
3091 else
89e9f3a8 3092 operands[3] = GEN_INT (start + size);
ca7f5001 3093 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3094}")
3095
a78e33fc 3096(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3097 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3098 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3099 (match_operand:SI 2 "const_int_operand" "i,i")
3100 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3101 (const_int 0)))
9ebbca7d 3102 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3103 ""
1fd4e8c1
RK		 3104 "*
3105{
3106 int start = INTVAL (operands[3]) & 31;
3107 int size = INTVAL (operands[2]) & 31;
3108
9ebbca7d
GK		 3109 /* Force split for non-cc0 compare. */
3110 if (which_alternative == 1)
3111 return \"#\";
3112
43a88a8c 3113 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3114 word, it is possible to use andiu. or andil. to test it. This is
3115 useful because the condition register set-use delay is smaller for
3116 andi[ul]. than for rlinm. This doesn't work when the starting bit
3117 position is 0 because the LT and GT bits may be set wrong. */
3118
3119 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3120 {
3a598fbe 3121 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3122 - (1 << (16 - (start & 15) - size))));
3123 if (start < 16)
ca7f5001 3124 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3125 else
ca7f5001 3126 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3127 }
7e69e155 3128
1fd4e8c1
RK		 3129 if (start + size >= 32)
3130 operands[3] = const0_rtx;
3131 else
89e9f3a8 3132 operands[3] = GEN_INT (start + size);
ca7f5001 3133 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3134}"
9ebbca7d
GK		 3135 [(set_attr "type" "compare")
3136 (set_attr "length" "4,8")])
3137
3138(define_split
3139 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3140 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3141 (match_operand:SI 2 "const_int_operand" "")
3142 (match_operand:SI 3 "const_int_operand" ""))
3143 (const_int 0)))
3144 (clobber (match_scratch:SI 4 ""))]
ce71f754 3145 "reload_completed"
9ebbca7d
GK		 3146 [(set (match_dup 4)
3147 (zero_extract:SI (match_dup 1) (match_dup 2)
3148 (match_dup 3)))
3149 (set (match_dup 0)
3150 (compare:CC (match_dup 4)
3151 (const_int 0)))]
3152 "")
1fd4e8c1 3153
a78e33fc 3154(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3155 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3156 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3157 (match_operand:SI 2 "const_int_operand" "i,i")
3158 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3159 (const_int 0)))
9ebbca7d 3160 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3161 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3162 ""
1fd4e8c1
RK		 3163 "*
3164{
3165 int start = INTVAL (operands[3]) & 31;
3166 int size = INTVAL (operands[2]) & 31;
3167
9ebbca7d
GK		 3168 /* Force split for non-cc0 compare. */
3169 if (which_alternative == 1)
3170 return \"#\";
3171
bc401279 3172 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3173 a shift. The bit-field must end at the LSB. */
bc401279 3174 if (start >= 16 && start + size == 32)
df031c43 3175 {
bc401279
AM		 3176 operands[3] = GEN_INT ((1 << size) - 1);
3177 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3178 }
7e69e155 3179
1fd4e8c1
RK		 3180 if (start + size >= 32)
3181 operands[3] = const0_rtx;
3182 else
89e9f3a8 3183 operands[3] = GEN_INT (start + size);
ca7f5001 3184 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3185}"
ce71f754 3186 [(set_attr "type" "compare")
9ebbca7d
GK		 3187 (set_attr "length" "4,8")])
3188
3189(define_split
3190 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3191 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3192 (match_operand:SI 2 "const_int_operand" "")
3193 (match_operand:SI 3 "const_int_operand" ""))
3194 (const_int 0)))
3195 (set (match_operand:SI 0 "gpc_reg_operand" "")
3196 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3197 "reload_completed"
9ebbca7d
GK		 3198 [(set (match_dup 0)
3199 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3200 (set (match_dup 4)
3201 (compare:CC (match_dup 0)
3202 (const_int 0)))]
3203 "")
1fd4e8c1 3204
a78e33fc 3205(define_insn "extzvdi"
685f3906
DE		 3206 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3207 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3208 (match_operand:SI 2 "const_int_operand" "i")
3209 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3210 "TARGET_POWERPC64"
3211 "*
3212{
3213 int start = INTVAL (operands[3]) & 63;
3214 int size = INTVAL (operands[2]) & 63;
3215
3216 if (start + size >= 64)
3217 operands[3] = const0_rtx;
3218 else
89e9f3a8
MM		 3219 operands[3] = GEN_INT (start + size);
3220 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3221 return \"rldicl %0,%1,%3,%2\";
3222}")
3223
a78e33fc 3224(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3225 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3226 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3227 (match_operand:SI 2 "const_int_operand" "i")
3228 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3229 (const_int 0)))
29ae5b89 3230 (clobber (match_scratch:DI 4 "=r"))]
683bdff7 3231 "TARGET_64BIT"
685f3906
DE		 3232 "*
3233{
3234 int start = INTVAL (operands[3]) & 63;
3235 int size = INTVAL (operands[2]) & 63;
3236
3237 if (start + size >= 64)
3238 operands[3] = const0_rtx;
3239 else
89e9f3a8
MM		 3240 operands[3] = GEN_INT (start + size);
3241 operands[2] = GEN_INT (64 - size);
685f3906 3242 return \"rldicl. %4,%1,%3,%2\";
9a3c428b
DE		 3243}"
3244 [(set_attr "type" "compare")])
685f3906 3245
a78e33fc 3246(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3247 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3248 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3249 (match_operand:SI 2 "const_int_operand" "i")
3250 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3251 (const_int 0)))
29ae5b89 3252 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3253 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
683bdff7 3254 "TARGET_64BIT"
685f3906
DE		 3255 "*
3256{
3257 int start = INTVAL (operands[3]) & 63;
3258 int size = INTVAL (operands[2]) & 63;
3259
3260 if (start + size >= 64)
3261 operands[3] = const0_rtx;
3262 else
89e9f3a8
MM		 3263 operands[3] = GEN_INT (start + size);
3264 operands[2] = GEN_INT (64 - size);
685f3906 3265 return \"rldicl. %0,%1,%3,%2\";
9a3c428b
DE		 3266}"
3267 [(set_attr "type" "compare")])
685f3906 3268
1fd4e8c1 3269(define_insn "rotlsi3"
cd2b37d9
RK		 3270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3271 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3272 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3273 ""
ca7f5001 3274 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
1fd4e8c1 3275
a260abc9 3276(define_insn "*rotlsi3_internal2"
9ebbca7d
GK		 3277 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3278 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3279 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
1fd4e8c1 3280 (const_int 0)))
9ebbca7d 3281 (clobber (match_scratch:SI 3 "=r,r"))]
ce71f754 3282 ""
9ebbca7d
GK		 3283 "@
3284 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3285 #"
3286 [(set_attr "type" "delayed_compare")
3287 (set_attr "length" "4,8")])
3288
3289(define_split
3290 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3291 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3292 (match_operand:SI 2 "reg_or_cint_operand" ""))
3293 (const_int 0)))
3294 (clobber (match_scratch:SI 3 ""))]
ce71f754 3295 "reload_completed"
9ebbca7d
GK		 3296 [(set (match_dup 3)
3297 (rotate:SI (match_dup 1) (match_dup 2)))
3298 (set (match_dup 0)
3299 (compare:CC (match_dup 3)
3300 (const_int 0)))]
3301 "")
1fd4e8c1 3302
a260abc9 3303(define_insn "*rotlsi3_internal3"
9ebbca7d
GK		 3304 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3305 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3306 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
1fd4e8c1 3307 (const_int 0)))
9ebbca7d 3308 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3309 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3310 ""
9ebbca7d
GK		 3311 "@
3312 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3313 #"
3314 [(set_attr "type" "delayed_compare")
3315 (set_attr "length" "4,8")])
3316
3317(define_split
3318 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3319 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3320 (match_operand:SI 2 "reg_or_cint_operand" ""))
3321 (const_int 0)))
3322 (set (match_operand:SI 0 "gpc_reg_operand" "")
3323 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3324 "reload_completed"
9ebbca7d
GK		 3325 [(set (match_dup 0)
3326 (rotate:SI (match_dup 1) (match_dup 2)))
3327 (set (match_dup 3)
3328 (compare:CC (match_dup 0)
3329 (const_int 0)))]
3330 "")
1fd4e8c1 3331
a260abc9 3332(define_insn "*rotlsi3_internal4"
cd2b37d9
RK		 3333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3334 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3335 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
ce71f754 3336 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3337 ""
ca7f5001 3338 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
1fd4e8c1 3339
a260abc9 3340(define_insn "*rotlsi3_internal5"
9ebbca7d 3341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3342 (compare:CC (and:SI
9ebbca7d
GK		 3343 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3344 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 3345 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3346 (const_int 0)))
9ebbca7d 3347 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3348 ""
9ebbca7d
GK		 3349 "@
3350 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3351 #"
3352 [(set_attr "type" "delayed_compare")
3353 (set_attr "length" "4,8")])
3354
3355(define_split
3356 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3357 (compare:CC (and:SI
3358 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3359 (match_operand:SI 2 "reg_or_cint_operand" ""))
3360 (match_operand:SI 3 "mask_operand" ""))
3361 (const_int 0)))
3362 (clobber (match_scratch:SI 4 ""))]
ce71f754 3363 "reload_completed"
9ebbca7d
GK		 3364 [(set (match_dup 4)
3365 (and:SI (rotate:SI (match_dup 1)
3366 (match_dup 2))
3367 (match_dup 3)))
3368 (set (match_dup 0)
3369 (compare:CC (match_dup 4)
3370 (const_int 0)))]
3371 "")
1fd4e8c1 3372
a260abc9 3373(define_insn "*rotlsi3_internal6"
9ebbca7d 3374 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3375 (compare:CC (and:SI
9ebbca7d
GK		 3376 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3377 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 3378 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3379 (const_int 0)))
9ebbca7d 3380 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3381 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3382 ""
9ebbca7d
GK		 3383 "@
3384 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3385 #"
3386 [(set_attr "type" "delayed_compare")
3387 (set_attr "length" "4,8")])
3388
3389(define_split
3390 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3391 (compare:CC (and:SI
3392 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3393 (match_operand:SI 2 "reg_or_cint_operand" ""))
3394 (match_operand:SI 3 "mask_operand" ""))
3395 (const_int 0)))
3396 (set (match_operand:SI 0 "gpc_reg_operand" "")
3397 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3398 "reload_completed"
9ebbca7d
GK		 3399 [(set (match_dup 0)
3400 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3401 (set (match_dup 4)
3402 (compare:CC (match_dup 0)
3403 (const_int 0)))]
3404 "")
1fd4e8c1 3405
a260abc9 3406(define_insn "*rotlsi3_internal7"
cd2b37d9 3407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 3408 (zero_extend:SI
3409 (subreg:QI
cd2b37d9 3410 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3411 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3412 ""
ca7f5001 3413 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1 3414
a260abc9 3415(define_insn "*rotlsi3_internal8"
9ebbca7d 3416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3417 (compare:CC (zero_extend:SI
3418 (subreg:QI
9ebbca7d
GK		 3419 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3420 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3421 (const_int 0)))
9ebbca7d 3422 (clobber (match_scratch:SI 3 "=r,r"))]
1fd4e8c1 3423 ""
9ebbca7d
GK		 3424 "@
3425 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3426 #"
3427 [(set_attr "type" "delayed_compare")
3428 (set_attr "length" "4,8")])
3429
3430(define_split
3431 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3432 (compare:CC (zero_extend:SI
3433 (subreg:QI
3434 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3435 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3436 (const_int 0)))
3437 (clobber (match_scratch:SI 3 ""))]
3438 "reload_completed"
3439 [(set (match_dup 3)
3440 (zero_extend:SI (subreg:QI
3441 (rotate:SI (match_dup 1)
3442 (match_dup 2)) 0)))
3443 (set (match_dup 0)
3444 (compare:CC (match_dup 3)
3445 (const_int 0)))]
3446 "")
1fd4e8c1 3447
a260abc9 3448(define_insn "*rotlsi3_internal9"
9ebbca7d 3449 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3450 (compare:CC (zero_extend:SI
3451 (subreg:QI
9ebbca7d
GK		 3452 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3453 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3454 (const_int 0)))
9ebbca7d 3455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 3456 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3457 ""
9ebbca7d
GK		 3458 "@
3459 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3460 #"
3461 [(set_attr "type" "delayed_compare")
3462 (set_attr "length" "4,8")])
3463
3464(define_split
3465 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3466 (compare:CC (zero_extend:SI
3467 (subreg:QI
3468 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3469 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3470 (const_int 0)))
3471 (set (match_operand:SI 0 "gpc_reg_operand" "")
3472 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3473 "reload_completed"
3474 [(set (match_dup 0)
3475 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3476 (set (match_dup 3)
3477 (compare:CC (match_dup 0)
3478 (const_int 0)))]
3479 "")
1fd4e8c1 3480
a260abc9 3481(define_insn "*rotlsi3_internal10"
cd2b37d9 3482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 3483 (zero_extend:SI
3484 (subreg:HI
cd2b37d9 3485 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3486 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3487 ""
ca7f5001 3488 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
1fd4e8c1 3489
a260abc9 3490(define_insn "*rotlsi3_internal11"
9ebbca7d 3491 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3492 (compare:CC (zero_extend:SI
3493 (subreg:HI
9ebbca7d
GK		 3494 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3495 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3496 (const_int 0)))
9ebbca7d 3497 (clobber (match_scratch:SI 3 "=r,r"))]
1fd4e8c1 3498 ""
9ebbca7d
GK		 3499 "@
3500 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3501 #"
3502 [(set_attr "type" "delayed_compare")
3503 (set_attr "length" "4,8")])
3504
3505(define_split
3506 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3507 (compare:CC (zero_extend:SI
3508 (subreg:HI
3509 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3510 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3511 (const_int 0)))
3512 (clobber (match_scratch:SI 3 ""))]
3513 "reload_completed"
3514 [(set (match_dup 3)
3515 (zero_extend:SI (subreg:HI
3516 (rotate:SI (match_dup 1)
3517 (match_dup 2)) 0)))
3518 (set (match_dup 0)
3519 (compare:CC (match_dup 3)
3520 (const_int 0)))]
3521 "")
1fd4e8c1 3522
a260abc9 3523(define_insn "*rotlsi3_internal12"
9ebbca7d 3524 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3525 (compare:CC (zero_extend:SI
3526 (subreg:HI
9ebbca7d
GK		 3527 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3528 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3529 (const_int 0)))
9ebbca7d 3530 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 3531 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3532 ""
9ebbca7d
GK		 3533 "@
3534 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3535 #"
3536 [(set_attr "type" "delayed_compare")
3537 (set_attr "length" "4,8")])
3538
3539(define_split
3540 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3541 (compare:CC (zero_extend:SI
3542 (subreg:HI
3543 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3544 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3545 (const_int 0)))
3546 (set (match_operand:SI 0 "gpc_reg_operand" "")
3547 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3548 "reload_completed"
3549 [(set (match_dup 0)
3550 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3551 (set (match_dup 3)
3552 (compare:CC (match_dup 0)
3553 (const_int 0)))]
3554 "")
1fd4e8c1
RK		 3555
3556;; Note that we use "sle." instead of "sl." so that we can set
3557;; SHIFT_COUNT_TRUNCATED.
3558
ca7f5001
RK		 3559(define_expand "ashlsi3"
3560 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3561 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3562 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3563 ""
3564 "
3565{
3566 if (TARGET_POWER)
3567 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3568 else
25c341fa 3569 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 3570 DONE;
3571}")
3572
3573(define_insn "ashlsi3_power"
cd2b37d9
RK		 3574 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3575 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 3576 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3577 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 3578 "TARGET_POWER"
1fd4e8c1
RK		 3579 "@
3580 sle %0,%1,%2
9ebbca7d 3581 {sli|slwi} %0,%1,%h2")
ca7f5001 3582
25c341fa 3583(define_insn "ashlsi3_no_power"
ca7f5001
RK		 3584 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3585 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3586 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 3587 "! TARGET_POWER"
9ebbca7d 3588 "{sl|slw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 3589
3590(define_insn ""
9ebbca7d
GK		 3591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3592 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3593 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3594 (const_int 0)))
9ebbca7d
GK		 3595 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3596 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 3597 "TARGET_POWER"
1fd4e8c1
RK		 3598 "@
3599 sle. %3,%1,%2
9ebbca7d
GK		 3600 {sli.|slwi.} %3,%1,%h2
3601 #
3602 #"
3603 [(set_attr "type" "delayed_compare")
3604 (set_attr "length" "4,4,8,8")])
3605
3606(define_split
3607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3608 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3609 (match_operand:SI 2 "reg_or_cint_operand" ""))
3610 (const_int 0)))
3611 (clobber (match_scratch:SI 3 ""))
3612 (clobber (match_scratch:SI 4 ""))]
3613 "TARGET_POWER && reload_completed"
3614 [(parallel [(set (match_dup 3)
3615 (ashift:SI (match_dup 1) (match_dup 2)))
3616 (clobber (match_dup 4))])
3617 (set (match_dup 0)
3618 (compare:CC (match_dup 3)
3619 (const_int 0)))]
3620 "")
25c341fa 3621
ca7f5001 3622(define_insn ""
9ebbca7d
GK		 3623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3624 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3625 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 3626 (const_int 0)))
9ebbca7d 3627 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3628 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d
GK		 3629 "@
3630 {sl|slw}%I2. %3,%1,%h2
3631 #"
3632 [(set_attr "type" "delayed_compare")
3633 (set_attr "length" "4,8")])
3634
3635(define_split
3636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3637 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3638 (match_operand:SI 2 "reg_or_cint_operand" ""))
3639 (const_int 0)))
3640 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3641 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 3642 [(set (match_dup 3)
3643 (ashift:SI (match_dup 1) (match_dup 2)))
3644 (set (match_dup 0)
3645 (compare:CC (match_dup 3)
3646 (const_int 0)))]
3647 "")
1fd4e8c1
RK		 3648
3649(define_insn ""
9ebbca7d
GK		 3650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3651 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3652 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3653 (const_int 0)))
9ebbca7d 3654 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3655 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 3656 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 3657 "TARGET_POWER"
1fd4e8c1
RK		 3658 "@
3659 sle. %0,%1,%2
9ebbca7d
GK		 3660 {sli.|slwi.} %0,%1,%h2
3661 #
3662 #"
3663 [(set_attr "type" "delayed_compare")
3664 (set_attr "length" "4,4,8,8")])
3665
3666(define_split
3667 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3668 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3669 (match_operand:SI 2 "reg_or_cint_operand" ""))
3670 (const_int 0)))
3671 (set (match_operand:SI 0 "gpc_reg_operand" "")
3672 (ashift:SI (match_dup 1) (match_dup 2)))
3673 (clobber (match_scratch:SI 4 ""))]
3674 "TARGET_POWER && reload_completed"
3675 [(parallel [(set (match_dup 0)
3676 (ashift:SI (match_dup 1) (match_dup 2)))
3677 (clobber (match_dup 4))])
3678 (set (match_dup 3)
3679 (compare:CC (match_dup 0)
3680 (const_int 0)))]
3681 "")
25c341fa 3682
ca7f5001 3683(define_insn ""
9ebbca7d
GK		 3684 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3685 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3686 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 3687 (const_int 0)))
9ebbca7d 3688 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 3689 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 3690 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d
GK		 3691 "@
3692 {sl|slw}%I2. %0,%1,%h2
3693 #"
3694 [(set_attr "type" "delayed_compare")
3695 (set_attr "length" "4,8")])
3696
3697(define_split
3698 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3699 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3700 (match_operand:SI 2 "reg_or_cint_operand" ""))
3701 (const_int 0)))
3702 (set (match_operand:SI 0 "gpc_reg_operand" "")
3703 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 3704 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 3705 [(set (match_dup 0)
3706 (ashift:SI (match_dup 1) (match_dup 2)))
3707 (set (match_dup 3)
3708 (compare:CC (match_dup 0)
3709 (const_int 0)))]
3710 "")
1fd4e8c1 3711
915167f5 3712(define_insn "rlwinm"
cd2b37d9
RK		 3713 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3714 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3715 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 3716 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3717 "includes_lshift_p (operands[2], operands[3])"
d56d506a 3718 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 3719
3720(define_insn ""
9ebbca7d 3721 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3722 (compare:CC
9ebbca7d
GK		 3723 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3724 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3725 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3726 (const_int 0)))
9ebbca7d 3727 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3728 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3729 "@
3730 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3731 #"
3732 [(set_attr "type" "delayed_compare")
3733 (set_attr "length" "4,8")])
3734
3735(define_split
3736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3737 (compare:CC
3738 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3739 (match_operand:SI 2 "const_int_operand" ""))
3740 (match_operand:SI 3 "mask_operand" ""))
3741 (const_int 0)))
3742 (clobber (match_scratch:SI 4 ""))]
ce71f754 3743 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3744 [(set (match_dup 4)
3745 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3746 (match_dup 3)))
3747 (set (match_dup 0)
3748 (compare:CC (match_dup 4)
3749 (const_int 0)))]
3750 "")
1fd4e8c1
RK		 3751
3752(define_insn ""
9ebbca7d 3753 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3754 (compare:CC
9ebbca7d
GK		 3755 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3756 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3757 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3758 (const_int 0)))
9ebbca7d 3759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3760 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3761 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3762 "@
3763 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3764 #"
3765 [(set_attr "type" "delayed_compare")
3766 (set_attr "length" "4,8")])
3767
3768(define_split
3769 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3770 (compare:CC
3771 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3772 (match_operand:SI 2 "const_int_operand" ""))
3773 (match_operand:SI 3 "mask_operand" ""))
3774 (const_int 0)))
3775 (set (match_operand:SI 0 "gpc_reg_operand" "")
3776 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3777 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3778 [(set (match_dup 0)
3779 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3780 (set (match_dup 4)
3781 (compare:CC (match_dup 0)
3782 (const_int 0)))]
3783 "")
1fd4e8c1 3784
ca7f5001 3785;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 3786;; "sli x,x,0".
ca7f5001
RK		 3787(define_expand "lshrsi3"
3788 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3789 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3790 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3791 ""
3792 "
3793{
3794 if (TARGET_POWER)
3795 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3796 else
25c341fa 3797 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 3798 DONE;
3799}")
3800
3801(define_insn "lshrsi3_power"
bdf423cb
MM		 3802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3803 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3804 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3805 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 3806 "TARGET_POWER"
1fd4e8c1
RK		 3807 "@
3808 sre %0,%1,%2
bdf423cb 3809 mr %0,%1
ca7f5001
RK		 3810 {s%A2i|s%A2wi} %0,%1,%h2")
3811
25c341fa 3812(define_insn "lshrsi3_no_power"
bdf423cb
MM		 3813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3814 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3815 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
25c341fa 3816 "! TARGET_POWER"
bdf423cb
MM		 3817 "@
3818 mr %0,%1
3819 {sr|srw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 3820
3821(define_insn ""
9ebbca7d
GK		 3822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3823 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3824 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 3825 (const_int 0)))
9ebbca7d
GK		 3826 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3827 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 3828 "TARGET_POWER"
1fd4e8c1 3829 "@
29ae5b89
JL		 3830 sre. %3,%1,%2
3831 mr. %1,%1
9ebbca7d
GK		 3832 {s%A2i.|s%A2wi.} %3,%1,%h2
3833 #
3834 #
3835 #"
3836 [(set_attr "type" "delayed_compare")
3837 (set_attr "length" "4,4,4,8,8,8")])
3838
3839(define_split
3840 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3841 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3842 (match_operand:SI 2 "reg_or_cint_operand" ""))
3843 (const_int 0)))
3844 (clobber (match_scratch:SI 3 ""))
3845 (clobber (match_scratch:SI 4 ""))]
3846 "TARGET_POWER && reload_completed"
3847 [(parallel [(set (match_dup 3)
3848 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3849 (clobber (match_dup 4))])
3850 (set (match_dup 0)
3851 (compare:CC (match_dup 3)
3852 (const_int 0)))]
3853 "")
ca7f5001
RK		 3854
3855(define_insn ""
9ebbca7d
GK		 3856 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3857 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3858 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
ca7f5001 3859 (const_int 0)))
9ebbca7d 3860 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4b8a63d6 3861 "! TARGET_POWER && TARGET_32BIT"
bdf423cb
MM		 3862 "@
3863 mr. %1,%1
9ebbca7d
GK		 3864 {sr|srw}%I2. %3,%1,%h2
3865 #
3866 #"
3867 [(set_attr "type" "delayed_compare")
3868 (set_attr "length" "4,4,8,8")])
1fd4e8c1 3869
9ebbca7d
GK		 3870(define_split
3871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3872 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3873 (match_operand:SI 2 "reg_or_cint_operand" ""))
3874 (const_int 0)))
3875 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3876 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 3877 [(set (match_dup 3)
3878 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3879 (set (match_dup 0)
3880 (compare:CC (match_dup 3)
3881 (const_int 0)))]
3882 "")
3883
3884(define_insn ""
3885 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3886 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3887 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 3888 (const_int 0)))
9ebbca7d 3889 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 3890 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 3891 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 3892 "TARGET_POWER"
1fd4e8c1 3893 "@
29ae5b89
JL		 3894 sre. %0,%1,%2
3895 mr. %0,%1
9ebbca7d
GK		 3896 {s%A2i.|s%A2wi.} %0,%1,%h2
3897 #
3898 #
3899 #"
3900 [(set_attr "type" "delayed_compare")
3901 (set_attr "length" "4,4,4,8,8,8")])
3902
3903(define_split
3904 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3905 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3906 (match_operand:SI 2 "reg_or_cint_operand" ""))
3907 (const_int 0)))
3908 (set (match_operand:SI 0 "gpc_reg_operand" "")
3909 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3910 (clobber (match_scratch:SI 4 ""))]
3911 "TARGET_POWER && reload_completed"
3912 [(parallel [(set (match_dup 0)
3913 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3914 (clobber (match_dup 4))])
3915 (set (match_dup 3)
3916 (compare:CC (match_dup 0)
3917 (const_int 0)))]
3918 "")
ca7f5001
RK		 3919
3920(define_insn ""
9ebbca7d
GK		 3921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3922 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3923 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
815cdc52 3924 (const_int 0)))
9ebbca7d 3925 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 3926 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 3927 "! TARGET_POWER && TARGET_32BIT"
29ae5b89
JL		 3928 "@
3929 mr. %0,%1
9ebbca7d
GK		 3930 {sr|srw}%I2. %0,%1,%h2
3931 #
3932 #"
3933 [(set_attr "type" "delayed_compare")
3934 (set_attr "length" "4,4,8,8")])
3935
3936(define_split
3937 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3938 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3939 (match_operand:SI 2 "reg_or_cint_operand" ""))
3940 (const_int 0)))
3941 (set (match_operand:SI 0 "gpc_reg_operand" "")
3942 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 3943 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 3944 [(set (match_dup 0)
3945 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3946 (set (match_dup 3)
3947 (compare:CC (match_dup 0)
3948 (const_int 0)))]
3949 "")
1fd4e8c1
RK		 3950
3951(define_insn ""
cd2b37d9
RK		 3952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3953 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3954 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 3955 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3956 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 3957 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 3958
3959(define_insn ""
9ebbca7d 3960 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3961 (compare:CC
9ebbca7d
GK		 3962 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3963 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3964 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3965 (const_int 0)))
9ebbca7d 3966 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3967 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3968 "@
3969 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3970 #"
3971 [(set_attr "type" "delayed_compare")
3972 (set_attr "length" "4,8")])
3973
3974(define_split
3975 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3976 (compare:CC
3977 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3978 (match_operand:SI 2 "const_int_operand" ""))
3979 (match_operand:SI 3 "mask_operand" ""))
3980 (const_int 0)))
3981 (clobber (match_scratch:SI 4 ""))]
ce71f754 3982 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3983 [(set (match_dup 4)
3984 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3985 (match_dup 3)))
3986 (set (match_dup 0)
3987 (compare:CC (match_dup 4)
3988 (const_int 0)))]
3989 "")
1fd4e8c1
RK		 3990
3991(define_insn ""
9ebbca7d 3992 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3993 (compare:CC
9ebbca7d
GK		 3994 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3995 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3996 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3997 (const_int 0)))
9ebbca7d 3998 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3999 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4000 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4001 "@
4002 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4003 #"
4004 [(set_attr "type" "delayed_compare")
4005 (set_attr "length" "4,8")])
4006
4007(define_split
4008 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4009 (compare:CC
4010 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4011 (match_operand:SI 2 "const_int_operand" ""))
4012 (match_operand:SI 3 "mask_operand" ""))
4013 (const_int 0)))
4014 (set (match_operand:SI 0 "gpc_reg_operand" "")
4015 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4016 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4017 [(set (match_dup 0)
4018 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4019 (set (match_dup 4)
4020 (compare:CC (match_dup 0)
4021 (const_int 0)))]
4022 "")
1fd4e8c1
RK		 4023
4024(define_insn ""
cd2b37d9 4025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4026 (zero_extend:SI
4027 (subreg:QI
cd2b37d9 4028 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4029 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4030 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4031 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4032
4033(define_insn ""
9ebbca7d 4034 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4035 (compare:CC
4036 (zero_extend:SI
4037 (subreg:QI
9ebbca7d
GK		 4038 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4039 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4040 (const_int 0)))
9ebbca7d 4041 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4042 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4043 "@
4044 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4045 #"
4046 [(set_attr "type" "delayed_compare")
4047 (set_attr "length" "4,8")])
4048
4049(define_split
4050 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4051 (compare:CC
4052 (zero_extend:SI
4053 (subreg:QI
4054 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4055 (match_operand:SI 2 "const_int_operand" "")) 0))
4056 (const_int 0)))
4057 (clobber (match_scratch:SI 3 ""))]
4058 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4059 [(set (match_dup 3)
4060 (zero_extend:SI (subreg:QI
4061 (lshiftrt:SI (match_dup 1)
4062 (match_dup 2)) 0)))
4063 (set (match_dup 0)
4064 (compare:CC (match_dup 3)
4065 (const_int 0)))]
4066 "")
1fd4e8c1
RK		 4067
4068(define_insn ""
9ebbca7d 4069 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4070 (compare:CC
4071 (zero_extend:SI
4072 (subreg:QI
9ebbca7d
GK		 4073 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4074 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4075 (const_int 0)))
9ebbca7d 4076 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4077 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4078 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4079 "@
4080 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4081 #"
4082 [(set_attr "type" "delayed_compare")
4083 (set_attr "length" "4,8")])
4084
4085(define_split
4086 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4087 (compare:CC
4088 (zero_extend:SI
4089 (subreg:QI
4090 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4091 (match_operand:SI 2 "const_int_operand" "")) 0))
4092 (const_int 0)))
4093 (set (match_operand:SI 0 "gpc_reg_operand" "")
4094 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4095 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4096 [(set (match_dup 0)
4097 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4098 (set (match_dup 3)
4099 (compare:CC (match_dup 0)
4100 (const_int 0)))]
4101 "")
1fd4e8c1
RK		 4102
4103(define_insn ""
cd2b37d9 4104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4105 (zero_extend:SI
4106 (subreg:HI
cd2b37d9 4107 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4108 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4109 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4110 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4111
4112(define_insn ""
9ebbca7d 4113 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4114 (compare:CC
4115 (zero_extend:SI
4116 (subreg:HI
9ebbca7d
GK		 4117 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4118 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4119 (const_int 0)))
9ebbca7d 4120 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4121 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4122 "@
4123 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4124 #"
4125 [(set_attr "type" "delayed_compare")
4126 (set_attr "length" "4,8")])
4127
4128(define_split
4129 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4130 (compare:CC
4131 (zero_extend:SI
4132 (subreg:HI
4133 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4134 (match_operand:SI 2 "const_int_operand" "")) 0))
4135 (const_int 0)))
4136 (clobber (match_scratch:SI 3 ""))]
4137 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4138 [(set (match_dup 3)
4139 (zero_extend:SI (subreg:HI
4140 (lshiftrt:SI (match_dup 1)
4141 (match_dup 2)) 0)))
4142 (set (match_dup 0)
4143 (compare:CC (match_dup 3)
4144 (const_int 0)))]
4145 "")
1fd4e8c1
RK		 4146
4147(define_insn ""
9ebbca7d 4148 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4149 (compare:CC
4150 (zero_extend:SI
4151 (subreg:HI
9ebbca7d
GK		 4152 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4153 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4154 (const_int 0)))
9ebbca7d 4155 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4156 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4157 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4158 "@
4159 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4160 #"
4161 [(set_attr "type" "delayed_compare")
4162 (set_attr "length" "4,8")])
4163
4164(define_split
4165 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4166 (compare:CC
4167 (zero_extend:SI
4168 (subreg:HI
4169 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4170 (match_operand:SI 2 "const_int_operand" "")) 0))
4171 (const_int 0)))
4172 (set (match_operand:SI 0 "gpc_reg_operand" "")
4173 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4174 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4175 [(set (match_dup 0)
4176 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4177 (set (match_dup 3)
4178 (compare:CC (match_dup 0)
4179 (const_int 0)))]
4180 "")
1fd4e8c1
RK		 4181
4182(define_insn ""
cd2b37d9 4183 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4184 (const_int 1)
cd2b37d9
RK		 4185 (match_operand:SI 1 "gpc_reg_operand" "r"))
4186 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4187 (const_int 31)))]
ca7f5001 4188 "TARGET_POWER"
1fd4e8c1
RK		 4189 "rrib %0,%1,%2")
4190
4191(define_insn ""
cd2b37d9 4192 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4193 (const_int 1)
cd2b37d9
RK		 4194 (match_operand:SI 1 "gpc_reg_operand" "r"))
4195 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4196 (const_int 31)))]
ca7f5001 4197 "TARGET_POWER"
1fd4e8c1
RK		 4198 "rrib %0,%1,%2")
4199
4200(define_insn ""
cd2b37d9 4201 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4202 (const_int 1)
cd2b37d9
RK		 4203 (match_operand:SI 1 "gpc_reg_operand" "r"))
4204 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4205 (const_int 1)
4206 (const_int 0)))]
ca7f5001 4207 "TARGET_POWER"
1fd4e8c1
RK		 4208 "rrib %0,%1,%2")
4209
ca7f5001
RK		 4210(define_expand "ashrsi3"
4211 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4212 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4213 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4214 ""
4215 "
4216{
4217 if (TARGET_POWER)
4218 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4219 else
25c341fa 4220 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4221 DONE;
4222}")
4223
4224(define_insn "ashrsi3_power"
cd2b37d9
RK		 4225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4226 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4227 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4228 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4229 "TARGET_POWER"
1fd4e8c1
RK		 4230 "@
4231 srea %0,%1,%2
ca7f5001
RK		 4232 {srai|srawi} %0,%1,%h2")
4233
25c341fa 4234(define_insn "ashrsi3_no_power"
ca7f5001
RK		 4235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4236 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4237 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 4238 "! TARGET_POWER"
d904e9ed 4239 "{sra|sraw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 4240
4241(define_insn ""
9ebbca7d
GK		 4242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4243 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4244 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4245 (const_int 0)))
9ebbca7d
GK		 4246 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4247 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4248 "TARGET_POWER"
1fd4e8c1
RK		 4249 "@
4250 srea. %3,%1,%2
9ebbca7d
GK		 4251 {srai.|srawi.} %3,%1,%h2
4252 #
4253 #"
4254 [(set_attr "type" "delayed_compare")
4255 (set_attr "length" "4,4,8,8")])
4256
4257(define_split
4258 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4259 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4260 (match_operand:SI 2 "reg_or_cint_operand" ""))
4261 (const_int 0)))
4262 (clobber (match_scratch:SI 3 ""))
4263 (clobber (match_scratch:SI 4 ""))]
4264 "TARGET_POWER && reload_completed"
4265 [(parallel [(set (match_dup 3)
4266 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4267 (clobber (match_dup 4))])
4268 (set (match_dup 0)
4269 (compare:CC (match_dup 3)
4270 (const_int 0)))]
4271 "")
ca7f5001
RK		 4272
4273(define_insn ""
9ebbca7d
GK		 4274 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4275 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4276 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 4277 (const_int 0)))
9ebbca7d 4278 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 4279 "! TARGET_POWER"
9ebbca7d
GK		 4280 "@
4281 {sra|sraw}%I2. %3,%1,%h2
4282 #"
4283 [(set_attr "type" "delayed_compare")
4284 (set_attr "length" "4,8")])
4285
4286(define_split
4287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4288 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4289 (match_operand:SI 2 "reg_or_cint_operand" ""))
4290 (const_int 0)))
4291 (clobber (match_scratch:SI 3 ""))]
4292 "! TARGET_POWER && reload_completed"
4293 [(set (match_dup 3)
4294 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4295 (set (match_dup 0)
4296 (compare:CC (match_dup 3)
4297 (const_int 0)))]
4298 "")
1fd4e8c1
RK		 4299
4300(define_insn ""
9ebbca7d
GK		 4301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4302 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4303 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4304 (const_int 0)))
9ebbca7d 4305 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4306 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4307 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4308 "TARGET_POWER"
1fd4e8c1
RK		 4309 "@
4310 srea. %0,%1,%2
9ebbca7d
GK		 4311 {srai.|srawi.} %0,%1,%h2
4312 #
4313 #"
4314 [(set_attr "type" "delayed_compare")
4315 (set_attr "length" "4,4,8,8")])
4316
4317(define_split
4318 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4319 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4320 (match_operand:SI 2 "reg_or_cint_operand" ""))
4321 (const_int 0)))
4322 (set (match_operand:SI 0 "gpc_reg_operand" "")
4323 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4324 (clobber (match_scratch:SI 4 ""))]
4325 "TARGET_POWER && reload_completed"
4326 [(parallel [(set (match_dup 0)
4327 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4328 (clobber (match_dup 4))])
4329 (set (match_dup 3)
4330 (compare:CC (match_dup 0)
4331 (const_int 0)))]
4332 "")
1fd4e8c1 4333
ca7f5001 4334(define_insn ""
9ebbca7d
GK		 4335 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4336 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4337 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 4338 (const_int 0)))
9ebbca7d 4339 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 4340 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 4341 "! TARGET_POWER"
9ebbca7d
GK		 4342 "@
4343 {sra|sraw}%I2. %0,%1,%h2
4344 #"
4345 [(set_attr "type" "delayed_compare")
4346 (set_attr "length" "4,8")])
1fd4e8c1 4347\f
9ebbca7d
GK		 4348(define_split
4349 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4350 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4351 (match_operand:SI 2 "reg_or_cint_operand" ""))
4352 (const_int 0)))
4353 (set (match_operand:SI 0 "gpc_reg_operand" "")
4354 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4355 "! TARGET_POWER && reload_completed"
4356 [(set (match_dup 0)
4357 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4358 (set (match_dup 3)
4359 (compare:CC (match_dup 0)
4360 (const_int 0)))]
4361 "")
4362
1fd4e8c1
RK		 4363;; Floating-point insns, excluding normal data motion.
4364;;
ca7f5001
RK		 4365;; PowerPC has a full set of single-precision floating point instructions.
4366;;
4367;; For the POWER architecture, we pretend that we have both SFmode and
4368;; DFmode insns, while, in fact, all fp insns are actually done in double.
4369;; The only conversions we will do will be when storing to memory. In that
4370;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 4371;;
4372;; Note that when we store into a single-precision memory location, we need to
4373;; use the frsp insn first. If the register being stored isn't dead, we
4374;; need a scratch register for the frsp. But this is difficult when the store
4375;; is done by reload. It is not incorrect to do the frsp on the register in
4376;; this case, we just lose precision that we would have otherwise gotten but
4377;; is not guaranteed. Perhaps this should be tightened up at some point.
4378
99176a91
AH		 4379(define_expand "extendsfdf2"
4380 [(set (match_operand:DF 0 "gpc_reg_operand" "")
97c54d9a 4381 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
99176a91
AH		 4382 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4383 "")
4384
4385(define_insn_and_split "*extendsfdf2_fpr"
97c54d9a
DE		 4386 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4387 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
a3170dc6 4388 "TARGET_HARD_FLOAT && TARGET_FPRS"
11ac38b2
DE		 4389 "@
4390 #
97c54d9a
DE		 4391 fmr %0,%1
4392 lfs%U1%X1 %0,%1"
d7b1468b 4393 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
11ac38b2 4394 [(const_int 0)]
5c30aff8 4395{
11ac38b2
DE		 4396 emit_note (NOTE_INSN_DELETED);
4397 DONE;
4398}
97c54d9a 4399 [(set_attr "type" "fp,fp,fpload")])
1fd4e8c1 4400
7a2f7870
AH		 4401(define_expand "truncdfsf2"
4402 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4403 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4404 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4405 "")
4406
99176a91 4407(define_insn "*truncdfsf2_fpr"
cd2b37d9
RK		 4408 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4409 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4410 "TARGET_HARD_FLOAT && TARGET_FPRS"
dcac138d 4411 "frsp %0,%1"
1fd4e8c1
RK		 4412 [(set_attr "type" "fp")])
4413
455350f4
RK		 4414(define_insn "aux_truncdfsf2"
4415 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 4416 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
a3170dc6 4417 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 4418 "frsp %0,%1"
4419 [(set_attr "type" "fp")])
4420
a3170dc6
AH		 4421(define_expand "negsf2"
4422 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4423 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4424 "TARGET_HARD_FLOAT"
4425 "")
4426
4427(define_insn "*negsf2"
cd2b37d9
RK		 4428 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4429 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4430 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4431 "fneg %0,%1"
4432 [(set_attr "type" "fp")])
4433
a3170dc6
AH		 4434(define_expand "abssf2"
4435 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4436 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4437 "TARGET_HARD_FLOAT"
4438 "")
4439
4440(define_insn "*abssf2"
cd2b37d9
RK		 4441 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4442 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4443 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4444 "fabs %0,%1"
4445 [(set_attr "type" "fp")])
4446
4447(define_insn ""
cd2b37d9
RK		 4448 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4449 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
a3170dc6 4450 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4451 "fnabs %0,%1"
4452 [(set_attr "type" "fp")])
4453
ca7f5001
RK		 4454(define_expand "addsf3"
4455 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4456 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4457 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4458 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4459 "")
4460
4461(define_insn ""
cd2b37d9
RK		 4462 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4463 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4464 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4465 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4466 "fadds %0,%1,%2"
ca7f5001
RK		 4467 [(set_attr "type" "fp")])
4468
4469(define_insn ""
4470 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4471 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4472 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4473 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4474 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 4475 [(set_attr "type" "fp")])
4476
4477(define_expand "subsf3"
4478 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4479 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4480 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4481 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4482 "")
4483
4484(define_insn ""
4485 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4486 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4487 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4488 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4489 "fsubs %0,%1,%2"
1fd4e8c1
RK		 4490 [(set_attr "type" "fp")])
4491
ca7f5001 4492(define_insn ""
cd2b37d9
RK		 4493 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4494 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4495 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4496 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4497 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 4498 [(set_attr "type" "fp")])
4499
4500(define_expand "mulsf3"
4501 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4502 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4503 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4504 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4505 "")
4506
4507(define_insn ""
4508 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4509 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4510 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4511 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4512 "fmuls %0,%1,%2"
1fd4e8c1
RK		 4513 [(set_attr "type" "fp")])
4514
ca7f5001 4515(define_insn ""
cd2b37d9
RK		 4516 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4517 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4518 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4519 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4520 "{fm|fmul} %0,%1,%2"
0780f386 4521 [(set_attr "type" "dmul")])
1fd4e8c1 4522
ef765ea9
DE		 4523(define_insn "fres"
4524 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4525 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4526 "TARGET_PPC_GFXOPT && flag_finite_math_only"
4527 "fres %0,%1"
4528 [(set_attr "type" "fp")])
4529
ca7f5001
RK		 4530(define_expand "divsf3"
4531 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4532 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4533 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4534 "TARGET_HARD_FLOAT"
ef765ea9
DE		 4535{
4536 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
4537 && flag_finite_math_only && !flag_trapping_math)
4538 {
4539 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
4540 DONE;
4541 }
4542})
ca7f5001
RK		 4543
4544(define_insn ""
cd2b37d9
RK		 4545 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4546 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4547 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4548 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4549 "fdivs %0,%1,%2"
ca7f5001
RK		 4550 [(set_attr "type" "sdiv")])
4551
4552(define_insn ""
4553 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4554 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4555 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4556 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4557 "{fd|fdiv} %0,%1,%2"
0780f386 4558 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 4559
4560(define_insn ""
cd2b37d9
RK		 4561 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4562 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4563 (match_operand:SF 2 "gpc_reg_operand" "f"))
4564 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4565 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4566 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 4567 [(set_attr "type" "fp")])
4568
4569(define_insn ""
4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f"))
4573 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4574 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4575 "{fma|fmadd} %0,%1,%2,%3"
cf27b467 4576 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4577
4578(define_insn ""
cd2b37d9
RK		 4579 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4580 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4581 (match_operand:SF 2 "gpc_reg_operand" "f"))
4582 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4583 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4584 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 4585 [(set_attr "type" "fp")])
4586
4587(define_insn ""
4588 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4589 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4590 (match_operand:SF 2 "gpc_reg_operand" "f"))
4591 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4592 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4593 "{fms|fmsub} %0,%1,%2,%3"
cf27b467 4594 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4595
4596(define_insn ""
cd2b37d9
RK		 4597 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4598 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4599 (match_operand:SF 2 "gpc_reg_operand" "f"))
4600 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4601 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4602 && HONOR_SIGNED_ZEROS (SFmode)"
4603 "fnmadds %0,%1,%2,%3"
4604 [(set_attr "type" "fp")])
4605
4606(define_insn ""
4607 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4608 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4609 (match_operand:SF 2 "gpc_reg_operand" "f"))
4610 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4611 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4612 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 4613 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 4614 [(set_attr "type" "fp")])
4615
4616(define_insn ""
4617 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4618 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4619 (match_operand:SF 2 "gpc_reg_operand" "f"))
4620 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 4621 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4622 "{fnma|fnmadd} %0,%1,%2,%3"
cf27b467 4623 [(set_attr "type" "dmul")])
1fd4e8c1 4624
16823694
GK		 4625(define_insn ""
4626 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4627 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4628 (match_operand:SF 2 "gpc_reg_operand" "f"))
4629 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4630 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4631 && ! HONOR_SIGNED_ZEROS (SFmode)"
4632 "{fnma|fnmadd} %0,%1,%2,%3"
4633 [(set_attr "type" "dmul")])
4634
1fd4e8c1 4635(define_insn ""
cd2b37d9
RK		 4636 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4637 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4638 (match_operand:SF 2 "gpc_reg_operand" "f"))
4639 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4640 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4641 && HONOR_SIGNED_ZEROS (SFmode)"
4642 "fnmsubs %0,%1,%2,%3"
4643 [(set_attr "type" "fp")])
4644
4645(define_insn ""
4646 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4647 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4648 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4649 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4650 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4651 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 4652 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 4653 [(set_attr "type" "fp")])
4654
4655(define_insn ""
4656 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4657 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4658 (match_operand:SF 2 "gpc_reg_operand" "f"))
4659 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 4660 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4661 "{fnms|fnmsub} %0,%1,%2,%3"
cf27b467 4662 [(set_attr "type" "dmul")])
1fd4e8c1 4663
16823694
GK		 4664(define_insn ""
4665 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4666 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4667 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4668 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4669 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4670 && ! HONOR_SIGNED_ZEROS (SFmode)"
4671 "{fnms|fnmsub} %0,%1,%2,%3"
4672 [(set_attr "type" "fp")])
4673
ca7f5001
RK		 4674(define_expand "sqrtsf2"
4675 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4676 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
a3170dc6 4677 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4678 "")
4679
4680(define_insn ""
4681 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4682 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4683 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4684 "fsqrts %0,%1"
4685 [(set_attr "type" "ssqrt")])
4686
4687(define_insn ""
4688 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4689 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4690 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4691 "fsqrt %0,%1"
4692 [(set_attr "type" "dsqrt")])
4693
0530bc70
AP		 4694(define_expand "copysignsf3"
4695 [(set (match_dup 3)
4696 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4697 (set (match_dup 4)
4698 (neg:SF (abs:SF (match_dup 1))))
4699 (set (match_operand:SF 0 "gpc_reg_operand" "")
4700 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4701 (match_dup 5))
4702 (match_dup 3)
4703 (match_dup 4)))]
4704 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
bb8df8a6 4705 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
0530bc70
AP		 4706 {
4707 operands[3] = gen_reg_rtx (SFmode);
4708 operands[4] = gen_reg_rtx (SFmode);
4709 operands[5] = CONST0_RTX (SFmode);
4710 })
4711
4712(define_expand "copysigndf3"
4713 [(set (match_dup 3)
4714 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4715 (set (match_dup 4)
4716 (neg:DF (abs:DF (match_dup 1))))
4717 (set (match_operand:DF 0 "gpc_reg_operand" "")
4718 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4719 (match_dup 5))
4720 (match_dup 3)
4721 (match_dup 4)))]
4722 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4723 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4724 {
4725 operands[3] = gen_reg_rtx (DFmode);
4726 operands[4] = gen_reg_rtx (DFmode);
4727 operands[5] = CONST0_RTX (DFmode);
4728 })
4729
94d7001a
RK		 4730;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4731;; fsel instruction and some auxiliary computations. Then we just have a
4732;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05 4733;; combine.
7ae4d8d4 4734(define_expand "smaxsf3"
8e871c05 4735 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 4736 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4737 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 4738 (match_dup 1)
4739 (match_dup 2)))]
89e73849 4740 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 4741 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 4742
7ae4d8d4 4743(define_expand "sminsf3"
50a0b056
GK		 4744 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4745 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4746 (match_operand:SF 2 "gpc_reg_operand" ""))
4747 (match_dup 2)
4748 (match_dup 1)))]
89e73849 4749 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 4750 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 4751
8e871c05
RK		 4752(define_split
4753 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 4754 (match_operator:SF 3 "min_max_operator"
4755 [(match_operand:SF 1 "gpc_reg_operand" "")
4756 (match_operand:SF 2 "gpc_reg_operand" "")]))]
89e73849 4757 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 4758 [(const_int 0)]
4759 "
6ae08853 4760{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 4761 operands[1], operands[2]);
4762 DONE;
4763}")
2f607b94 4764
a3170dc6
AH		 4765(define_expand "movsicc"
4766 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4767 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4768 (match_operand:SI 2 "gpc_reg_operand" "")
4769 (match_operand:SI 3 "gpc_reg_operand" "")))]
4770 "TARGET_ISEL"
4771 "
4772{
4773 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4774 DONE;
4775 else
4776 FAIL;
4777}")
4778
4779;; We use the BASE_REGS for the isel input operands because, if rA is
4780;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4781;; because we may switch the operands and rB may end up being rA.
4782;;
4783;; We need 2 patterns: an unsigned and a signed pattern. We could
4784;; leave out the mode in operand 4 and use one pattern, but reload can
4785;; change the mode underneath our feet and then gets confused trying
4786;; to reload the value.
4787(define_insn "isel_signed"
4788 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4789 (if_then_else:SI
4790 (match_operator 1 "comparison_operator"
4791 [(match_operand:CC 4 "cc_reg_operand" "y")
4792 (const_int 0)])
4793 (match_operand:SI 2 "gpc_reg_operand" "b")
4794 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4795 "TARGET_ISEL"
4796 "*
4797{ return output_isel (operands); }"
4798 [(set_attr "length" "4")])
4799
4800(define_insn "isel_unsigned"
4801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4802 (if_then_else:SI
4803 (match_operator 1 "comparison_operator"
4804 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4805 (const_int 0)])
4806 (match_operand:SI 2 "gpc_reg_operand" "b")
4807 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4808 "TARGET_ISEL"
4809 "*
4810{ return output_isel (operands); }"
4811 [(set_attr "length" "4")])
4812
94d7001a 4813(define_expand "movsfcc"
0ad91047 4814 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 4815 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 4816 (match_operand:SF 2 "gpc_reg_operand" "")
4817 (match_operand:SF 3 "gpc_reg_operand" "")))]
a3170dc6 4818 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4819 "
4820{
50a0b056
GK		 4821 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4822 DONE;
94d7001a 4823 else
50a0b056 4824 FAIL;
94d7001a 4825}")
d56d506a 4826
50a0b056 4827(define_insn "*fselsfsf4"
8e871c05
RK		 4828 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4829 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 4830 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 4831 (match_operand:SF 2 "gpc_reg_operand" "f")
4832 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4833 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 4834 "fsel %0,%1,%2,%3"
4835 [(set_attr "type" "fp")])
2f607b94 4836
50a0b056 4837(define_insn "*fseldfsf4"
94d7001a
RK		 4838 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4839 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 4840 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 4841 (match_operand:SF 2 "gpc_reg_operand" "f")
4842 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4843 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4844 "fsel %0,%1,%2,%3"
4845 [(set_attr "type" "fp")])
d56d506a 4846
7a2f7870
AH		 4847(define_expand "negdf2"
4848 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4849 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4850 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4851 "")
4852
99176a91 4853(define_insn "*negdf2_fpr"
cd2b37d9
RK		 4854 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4855 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4856 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4857 "fneg %0,%1"
4858 [(set_attr "type" "fp")])
4859
7a2f7870
AH		 4860(define_expand "absdf2"
4861 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4862 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4863 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4864 "")
4865
99176a91 4866(define_insn "*absdf2_fpr"
cd2b37d9
RK		 4867 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4868 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4869 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4870 "fabs %0,%1"
4871 [(set_attr "type" "fp")])
4872
99176a91 4873(define_insn "*nabsdf2_fpr"
cd2b37d9
RK		 4874 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4875 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
a3170dc6 4876 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4877 "fnabs %0,%1"
4878 [(set_attr "type" "fp")])
4879
7a2f7870
AH		 4880(define_expand "adddf3"
4881 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4882 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4883 (match_operand:DF 2 "gpc_reg_operand" "")))]
4884 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4885 "")
4886
99176a91 4887(define_insn "*adddf3_fpr"
cd2b37d9
RK		 4888 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4889 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4890 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4891 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4892 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 4893 [(set_attr "type" "fp")])
4894
7a2f7870
AH		 4895(define_expand "subdf3"
4896 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4897 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4898 (match_operand:DF 2 "gpc_reg_operand" "")))]
4899 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4900 "")
4901
99176a91 4902(define_insn "*subdf3_fpr"
cd2b37d9
RK		 4903 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4904 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4905 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4906 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4907 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 4908 [(set_attr "type" "fp")])
4909
7a2f7870
AH		 4910(define_expand "muldf3"
4911 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4912 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4913 (match_operand:DF 2 "gpc_reg_operand" "")))]
4914 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4915 "")
4916
99176a91 4917(define_insn "*muldf3_fpr"
cd2b37d9
RK		 4918 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4919 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4920 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4921 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4922 "{fm|fmul} %0,%1,%2"
cfb557c4 4923 [(set_attr "type" "dmul")])
1fd4e8c1 4924
ef765ea9
DE		 4925(define_insn "fred"
4926 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4927 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4928 "TARGET_POPCNTB && flag_finite_math_only"
4929 "fre %0,%1"
4930 [(set_attr "type" "fp")])
4931
7a2f7870
AH		 4932(define_expand "divdf3"
4933 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4934 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4935 (match_operand:DF 2 "gpc_reg_operand" "")))]
4936 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
ef765ea9
DE		 4937{
4938 if (swdiv && !optimize_size && TARGET_POPCNTB
4939 && flag_finite_math_only && !flag_trapping_math)
4940 {
4941 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
4942 DONE;
4943 }
4944})
7a2f7870 4945
99176a91 4946(define_insn "*divdf3_fpr"
cd2b37d9
RK		 4947 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4948 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4949 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4950 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4951 "{fd|fdiv} %0,%1,%2"
cfb557c4 4952 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 4953
4954(define_insn ""
cd2b37d9
RK		 4955 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4956 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4957 (match_operand:DF 2 "gpc_reg_operand" "f"))
4958 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4959 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 4960 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 4961 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4962
4963(define_insn ""
cd2b37d9
RK		 4964 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4965 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4966 (match_operand:DF 2 "gpc_reg_operand" "f"))
4967 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4968 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 4969 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 4970 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4971
4972(define_insn ""
cd2b37d9
RK		 4973 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4974 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4975 (match_operand:DF 2 "gpc_reg_operand" "f"))
4976 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4977 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4978 && HONOR_SIGNED_ZEROS (DFmode)"
4979 "{fnma|fnmadd} %0,%1,%2,%3"
4980 [(set_attr "type" "dmul")])
4981
4982(define_insn ""
4983 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4984 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4985 (match_operand:DF 2 "gpc_reg_operand" "f"))
4986 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4987 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4988 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 4989 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 4990 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4991
4992(define_insn ""
cd2b37d9
RK		 4993 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4994 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4995 (match_operand:DF 2 "gpc_reg_operand" "f"))
4996 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4997 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4998 && HONOR_SIGNED_ZEROS (DFmode)"
4999 "{fnms|fnmsub} %0,%1,%2,%3"
5000 [(set_attr "type" "dmul")])
5001
5002(define_insn ""
5003 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5004 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5005 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5006 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
6ae08853 5007 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5008 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5009 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 5010 [(set_attr "type" "dmul")])
ca7f5001
RK		 5011
5012(define_insn "sqrtdf2"
5013 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5014 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5015 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5016 "fsqrt %0,%1"
5017 [(set_attr "type" "dsqrt")])
b77dfefc 5018
50a0b056 5019;; The conditional move instructions allow us to perform max and min
6ae08853 5020;; operations even when
b77dfefc 5021
7ae4d8d4 5022(define_expand "smaxdf3"
8e871c05 5023 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5024 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5025 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5026 (match_dup 1)
5027 (match_dup 2)))]
89e73849 5028 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5029 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 5030
7ae4d8d4 5031(define_expand "smindf3"
50a0b056
GK		 5032 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5033 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5034 (match_operand:DF 2 "gpc_reg_operand" ""))
5035 (match_dup 2)
5036 (match_dup 1)))]
89e73849 5037 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5038 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 5039
8e871c05
RK		 5040(define_split
5041 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5042 (match_operator:DF 3 "min_max_operator"
5043 [(match_operand:DF 1 "gpc_reg_operand" "")
5044 (match_operand:DF 2 "gpc_reg_operand" "")]))]
89e73849 5045 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5046 [(const_int 0)]
5047 "
6ae08853 5048{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5049 operands[1], operands[2]);
5050 DONE;
5051}")
b77dfefc 5052
94d7001a 5053(define_expand "movdfcc"
0ad91047 5054 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 5055 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5056 (match_operand:DF 2 "gpc_reg_operand" "")
5057 (match_operand:DF 3 "gpc_reg_operand" "")))]
a3170dc6 5058 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5059 "
5060{
50a0b056
GK		 5061 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5062 DONE;
94d7001a 5063 else
50a0b056 5064 FAIL;
94d7001a 5065}")
d56d506a 5066
50a0b056 5067(define_insn "*fseldfdf4"
8e871c05
RK		 5068 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5069 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 5070 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5071 (match_operand:DF 2 "gpc_reg_operand" "f")
5072 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5073 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5074 "fsel %0,%1,%2,%3"
5075 [(set_attr "type" "fp")])
d56d506a 5076
50a0b056 5077(define_insn "*fselsfdf4"
94d7001a
RK		 5078 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5079 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5080 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5081 (match_operand:DF 2 "gpc_reg_operand" "f")
5082 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5083 "TARGET_PPC_GFXOPT"
5084 "fsel %0,%1,%2,%3"
5085 [(set_attr "type" "fp")])
1fd4e8c1 5086\f
d095928f
AH		 5087;; Conversions to and from floating-point.
5088
5089(define_expand "fixuns_truncsfsi2"
5090 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5091 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5092 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5093 "")
5094
5095(define_expand "fix_truncsfsi2"
5096 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5097 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5098 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5099 "")
5100
9ebbca7d
GK		 5101; For each of these conversions, there is a define_expand, a define_insn
5102; with a '#' template, and a define_split (with C code). The idea is
5103; to allow constant folding with the template of the define_insn,
5104; then to have the insns split later (between sched1 and final).
5105
1fd4e8c1 5106(define_expand "floatsidf2"
802a0058
MM		 5107 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5108 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5109 (use (match_dup 2))
5110 (use (match_dup 3))
208c89ce 5111 (clobber (match_dup 4))
a7df97e6 5112 (clobber (match_dup 5))
9ebbca7d 5113 (clobber (match_dup 6))])]
a3170dc6 5114 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5115 "
5116{
99176a91
AH		 5117 if (TARGET_E500_DOUBLE)
5118 {
5119 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5120 DONE;
5121 }
05d49501
AM		 5122 if (TARGET_POWERPC64)
5123 {
5124 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5125 rtx t1 = gen_reg_rtx (DImode);
5126 rtx t2 = gen_reg_rtx (DImode);
5127 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5128 DONE;
5129 }
5130
802a0058 5131 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5132 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5133 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5134 operands[5] = gen_reg_rtx (DFmode);
5135 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5136}")
5137
230215f5 5138(define_insn_and_split "*floatsidf2_internal"
802a0058
MM		 5139 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5140 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5141 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5142 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5143 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5
DJ		 5144 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5145 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
a3170dc6 5146 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5147 "#"
230215f5
GK		 5148 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5149 [(pc)]
208c89ce
MM		 5150 "
5151{
9ebbca7d 5152 rtx lowword, highword;
230215f5
GK		 5153 gcc_assert (MEM_P (operands[4]));
5154 highword = adjust_address (operands[4], SImode, 0);
5155 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d
GK		 5156 if (! WORDS_BIG_ENDIAN)
5157 {
5158 rtx tmp;
5159 tmp = highword; highword = lowword; lowword = tmp;
5160 }
5161
6ae08853 5162 emit_insn (gen_xorsi3 (operands[6], operands[1],
9ebbca7d 5163 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
230215f5
GK		 5164 emit_move_insn (lowword, operands[6]);
5165 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5166 emit_move_insn (operands[5], operands[4]);
5167 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5168 DONE;
230215f5
GK		 5169}"
5170 [(set_attr "length" "24")])
802a0058 5171
a3170dc6
AH		 5172(define_expand "floatunssisf2"
5173 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5174 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5175 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5176 "")
5177
802a0058
MM		 5178(define_expand "floatunssidf2"
5179 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5180 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5181 (use (match_dup 2))
5182 (use (match_dup 3))
a7df97e6 5183 (clobber (match_dup 4))
9ebbca7d 5184 (clobber (match_dup 5))])]
99176a91 5185 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5186 "
5187{
99176a91
AH		 5188 if (TARGET_E500_DOUBLE)
5189 {
5190 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5191 DONE;
5192 }
05d49501
AM		 5193 if (TARGET_POWERPC64)
5194 {
5195 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5196 rtx t1 = gen_reg_rtx (DImode);
5197 rtx t2 = gen_reg_rtx (DImode);
5198 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5199 t1, t2));
5200 DONE;
5201 }
5202
802a0058 5203 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5204 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 5205 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5206 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 5207}")
5208
230215f5 5209(define_insn_and_split "*floatunssidf2_internal"
802a0058
MM		 5210 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5211 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5212 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5213 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5214 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5 5215 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
a3170dc6 5216 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5217 "#"
230215f5
GK		 5218 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5219 [(pc)]
9ebbca7d 5220 "
802a0058 5221{
9ebbca7d 5222 rtx lowword, highword;
230215f5
GK		 5223 gcc_assert (MEM_P (operands[4]));
5224 highword = adjust_address (operands[4], SImode, 0);
5225 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d 5226 if (! WORDS_BIG_ENDIAN)
f6968f59 5227 {
9ebbca7d
GK		 5228 rtx tmp;
5229 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 5230 }
802a0058 5231
230215f5
GK		 5232 emit_move_insn (lowword, operands[1]);
5233 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5234 emit_move_insn (operands[5], operands[4]);
5235 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5236 DONE;
230215f5
GK		 5237}"
5238 [(set_attr "length" "20")])
1fd4e8c1 5239
1fd4e8c1 5240(define_expand "fix_truncdfsi2"
045a8eb3 5241 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
802a0058
MM		 5242 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5243 (clobber (match_dup 2))
9ebbca7d 5244 (clobber (match_dup 3))])]
99176a91
AH		 5245 "(TARGET_POWER2 || TARGET_POWERPC)
5246 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5247 "
5248{
99176a91
AH		 5249 if (TARGET_E500_DOUBLE)
5250 {
5251 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5252 DONE;
5253 }
802a0058 5254 operands[2] = gen_reg_rtx (DImode);
da4c340c
GK		 5255 if (TARGET_PPC_GFXOPT)
5256 {
5257 rtx orig_dest = operands[0];
045a8eb3 5258 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
da4c340c
GK		 5259 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5260 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5261 operands[2]));
5262 if (operands[0] != orig_dest)
5263 emit_move_insn (orig_dest, operands[0]);
5264 DONE;
5265 }
9ebbca7d 5266 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 5267}")
5268
da4c340c 5269(define_insn_and_split "*fix_truncdfsi2_internal"
802a0058
MM		 5270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5271 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 5272 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
9ebbca7d 5273 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
a3170dc6 5274 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5275 "#"
230215f5 5276 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
da4c340c 5277 [(pc)]
9ebbca7d 5278 "
802a0058 5279{
9ebbca7d 5280 rtx lowword;
230215f5
GK		 5281 gcc_assert (MEM_P (operands[3]));
5282 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
802a0058 5283
9ebbca7d
GK		 5284 emit_insn (gen_fctiwz (operands[2], operands[1]));
5285 emit_move_insn (operands[3], operands[2]);
230215f5 5286 emit_move_insn (operands[0], lowword);
9ebbca7d 5287 DONE;
da4c340c
GK		 5288}"
5289 [(set_attr "length" "16")])
5290
5291(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5292 [(set (match_operand:SI 0 "memory_operand" "=Z")
5293 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5294 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5295 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5296 && TARGET_PPC_GFXOPT"
5297 "#"
5298 "&& 1"
5299 [(pc)]
5300 "
5301{
5302 emit_insn (gen_fctiwz (operands[2], operands[1]));
5303 emit_insn (gen_stfiwx (operands[0], operands[2]));
5304 DONE;
5305}"
5306 [(set_attr "length" "16")])
802a0058 5307
615158e2 5308; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 5309; rather than (set (subreg:SI (reg)) (fix:SI ...))
5310; because the first makes it clear that operand 0 is not live
5311; before the instruction.
5312(define_insn "fctiwz"
da4c340c 5313 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
615158e2
JJ		 5314 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5315 UNSPEC_FCTIWZ))]
a3170dc6 5316 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
a260abc9
DE		 5317 "{fcirz|fctiwz} %0,%1"
5318 [(set_attr "type" "fp")])
5319
da4c340c
GK		 5320; An UNSPEC is used so we don't have to support SImode in FP registers.
5321(define_insn "stfiwx"
5322 [(set (match_operand:SI 0 "memory_operand" "=Z")
5323 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5324 UNSPEC_STFIWX))]
5325 "TARGET_PPC_GFXOPT"
5326 "stfiwx %1,%y0"
5327 [(set_attr "type" "fpstore")])
5328
a3170dc6
AH		 5329(define_expand "floatsisf2"
5330 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5331 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5332 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5333 "")
5334
a473029f
RK		 5335(define_insn "floatdidf2"
5336 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
61c07d3c 5337 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
a3170dc6 5338 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 5339 "fcfid %0,%1"
5340 [(set_attr "type" "fp")])
5341
05d49501
AM		 5342(define_insn_and_split "floatsidf_ppc64"
5343 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5344 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5345 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5346 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5347 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 5348 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 5349 "#"
ecb62ae7 5350 "&& 1"
05d49501
AM		 5351 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5352 (set (match_dup 2) (match_dup 3))
5353 (set (match_dup 4) (match_dup 2))
5354 (set (match_dup 0) (float:DF (match_dup 4)))]
5355 "")
5356
5357(define_insn_and_split "floatunssidf_ppc64"
5358 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5359 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5360 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5361 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5362 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 5363 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 5364 "#"
ecb62ae7 5365 "&& 1"
05d49501
AM		 5366 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5367 (set (match_dup 2) (match_dup 3))
5368 (set (match_dup 4) (match_dup 2))
5369 (set (match_dup 0) (float:DF (match_dup 4)))]
5370 "")
5371
a473029f 5372(define_insn "fix_truncdfdi2"
61c07d3c 5373 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
a473029f 5374 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5375 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 5376 "fctidz %0,%1"
5377 [(set_attr "type" "fp")])
ea112fc4 5378
678b7733
AM		 5379(define_expand "floatdisf2"
5380 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5381 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
994cf173 5382 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 5383 "
5384{
994cf173 5385 rtx val = operands[1];
678b7733
AM		 5386 if (!flag_unsafe_math_optimizations)
5387 {
5388 rtx label = gen_label_rtx ();
994cf173
AM		 5389 val = gen_reg_rtx (DImode);
5390 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
678b7733
AM		 5391 emit_label (label);
5392 }
994cf173 5393 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
678b7733
AM		 5394 DONE;
5395}")
5396
5397;; This is not IEEE compliant if rounding mode is "round to nearest".
5398;; If the DI->DF conversion is inexact, then it's possible to suffer
5399;; from double rounding.
5400(define_insn_and_split "floatdisf2_internal1"
ea112fc4 5401 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
61c07d3c 5402 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
ea112fc4 5403 (clobber (match_scratch:DF 2 "=f"))]
678b7733 5404 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
ea112fc4
DE		 5405 "#"
5406 "&& reload_completed"
5407 [(set (match_dup 2)
5408 (float:DF (match_dup 1)))
5409 (set (match_dup 0)
5410 (float_truncate:SF (match_dup 2)))]
5411 "")
678b7733
AM		 5412
5413;; Twiddles bits to avoid double rounding.
b6d08ca1 5414;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 5415;; by a bit that won't be lost at that stage, but is below the SFmode
5416;; rounding position.
5417(define_expand "floatdisf2_internal2"
994cf173
AM		 5418 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5419 (const_int 53)))
5420 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5421 (const_int 2047)))
5422 (clobber (scratch:CC))])
5423 (set (match_dup 3) (plus:DI (match_dup 3)
5424 (const_int 1)))
5425 (set (match_dup 0) (plus:DI (match_dup 0)
5426 (const_int 2047)))
5427 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5428 (const_int 3)))
5429 (set (match_dup 0) (ior:DI (match_dup 0)
5430 (match_dup 1)))
5431 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5432 (const_int -2048)))
5433 (clobber (scratch:CC))])
5434 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5435 (label_ref (match_operand:DI 2 "" ""))
678b7733 5436 (pc)))
994cf173
AM		 5437 (set (match_dup 0) (match_dup 1))]
5438 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 5439 "
5440{
678b7733 5441 operands[3] = gen_reg_rtx (DImode);
994cf173 5442 operands[4] = gen_reg_rtx (CCUNSmode);
678b7733 5443}")
1fd4e8c1
RK		 5444\f
5445;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 5446;; of instructions. The & constraints are to prevent the register
5447;; allocator from allocating registers that overlap with the inputs
5448;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 5449;; also allow for the output being the same as one of the inputs.
a6ec530c 5450
266eb58a 5451(define_insn "*adddi3_noppc64"
a6ec530c
RK		 5452 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5453 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5454 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 5455 "! TARGET_POWERPC64"
0f645302
MM		 5456 "*
5457{
5458 if (WORDS_BIG_ENDIAN)
5459 return (GET_CODE (operands[2])) != CONST_INT
5460 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5461 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5462 else
5463 return (GET_CODE (operands[2])) != CONST_INT
5464 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5465 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5466}"
943c15ed
DE		 5467 [(set_attr "type" "two")
5468 (set_attr "length" "8")])
1fd4e8c1 5469
266eb58a 5470(define_insn "*subdi3_noppc64"
e7e5df70
RK		 5471 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5472 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5473 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 5474 "! TARGET_POWERPC64"
5502823b
RK		 5475 "*
5476{
0f645302
MM		 5477 if (WORDS_BIG_ENDIAN)
5478 return (GET_CODE (operands[1]) != CONST_INT)
5479 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5480 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5481 else
5482 return (GET_CODE (operands[1]) != CONST_INT)
5483 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5484 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 5485}"
943c15ed
DE		 5486 [(set_attr "type" "two")
5487 (set_attr "length" "8")])
ca7f5001 5488
266eb58a 5489(define_insn "*negdi2_noppc64"
a6ec530c
RK		 5490 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5491 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 5492 "! TARGET_POWERPC64"
5502823b
RK		 5493 "*
5494{
5495 return (WORDS_BIG_ENDIAN)
5496 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5497 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5498}"
943c15ed
DE		 5499 [(set_attr "type" "two")
5500 (set_attr "length" "8")])
ca7f5001 5501
8ffd9c51
RK		 5502(define_expand "mulsidi3"
5503 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5504 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5505 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 5506 "! TARGET_POWERPC64"
8ffd9c51
RK		 5507 "
5508{
5509 if (! TARGET_POWER && ! TARGET_POWERPC)
5510 {
39403d82
DE		 5511 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5512 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 5513 emit_insn (gen_mull_call ());
cf27b467 5514 if (WORDS_BIG_ENDIAN)
39403d82 5515 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 5516 else
5517 {
5518 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 5519 gen_rtx_REG (SImode, 3));
cf27b467 5520 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 5521 gen_rtx_REG (SImode, 4));
cf27b467 5522 }
8ffd9c51
RK		 5523 DONE;
5524 }
5525 else if (TARGET_POWER)
5526 {
5527 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5528 DONE;
5529 }
5530}")
deb9225a 5531
8ffd9c51 5532(define_insn "mulsidi3_mq"
cd2b37d9 5533 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 5534 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 5535 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 5536 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 5537 "TARGET_POWER"
b19003d8 5538 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 5539 [(set_attr "type" "imul")
5540 (set_attr "length" "8")])
deb9225a 5541
f192bf8b 5542(define_insn "*mulsidi3_no_mq"
425c176f 5543 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 5544 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5545 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 5546 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 5547 "*
5548{
5549 return (WORDS_BIG_ENDIAN)
5550 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5551 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5552}"
8ffd9c51
RK		 5553 [(set_attr "type" "imul")
5554 (set_attr "length" "8")])
deb9225a 5555
ebedb4dd
MM		 5556(define_split
5557 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5558 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5559 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 5560 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 5561 [(set (match_dup 3)
5562 (truncate:SI
5563 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5564 (sign_extend:DI (match_dup 2)))
5565 (const_int 32))))
5566 (set (match_dup 4)
5567 (mult:SI (match_dup 1)
5568 (match_dup 2)))]
5569 "
5570{
5571 int endian = (WORDS_BIG_ENDIAN == 0);
5572 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5573 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5574}")
5575
f192bf8b
DE		 5576(define_expand "umulsidi3"
5577 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5578 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5579 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5580 "TARGET_POWERPC && ! TARGET_POWERPC64"
5581 "
5582{
5583 if (TARGET_POWER)
5584 {
5585 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5586 DONE;
5587 }
5588}")
5589
5590(define_insn "umulsidi3_mq"
5591 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5592 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5593 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5594 (clobber (match_scratch:SI 3 "=q"))]
5595 "TARGET_POWERPC && TARGET_POWER"
5596 "*
5597{
5598 return (WORDS_BIG_ENDIAN)
5599 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5600 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5601}"
5602 [(set_attr "type" "imul")
5603 (set_attr "length" "8")])
5604
5605(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 5606 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5607 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5608 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 5609 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 5610 "*
5611{
5612 return (WORDS_BIG_ENDIAN)
5613 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5614 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5615}"
5616 [(set_attr "type" "imul")
5617 (set_attr "length" "8")])
5618
ebedb4dd
MM		 5619(define_split
5620 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5621 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5622 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 5623 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 5624 [(set (match_dup 3)
5625 (truncate:SI
5626 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5627 (zero_extend:DI (match_dup 2)))
5628 (const_int 32))))
5629 (set (match_dup 4)
5630 (mult:SI (match_dup 1)
5631 (match_dup 2)))]
5632 "
5633{
5634 int endian = (WORDS_BIG_ENDIAN == 0);
5635 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5636 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5637}")
5638
8ffd9c51
RK		 5639(define_expand "smulsi3_highpart"
5640 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5641 (truncate:SI
5642 (lshiftrt:DI (mult:DI (sign_extend:DI
5643 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5644 (sign_extend:DI
5645 (match_operand:SI 2 "gpc_reg_operand" "r")))
5646 (const_int 32))))]
5647 ""
5648 "
5649{
5650 if (! TARGET_POWER && ! TARGET_POWERPC)
5651 {
39403d82
DE		 5652 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5653 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 5654 emit_insn (gen_mulh_call ());
39403d82 5655 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 5656 DONE;
5657 }
5658 else if (TARGET_POWER)
5659 {
5660 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5661 DONE;
5662 }
5663}")
deb9225a 5664
8ffd9c51
RK		 5665(define_insn "smulsi3_highpart_mq"
5666 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5667 (truncate:SI
fada905b
MM		 5668 (lshiftrt:DI (mult:DI (sign_extend:DI
5669 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5670 (sign_extend:DI
5671 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 5672 (const_int 32))))
5673 (clobber (match_scratch:SI 3 "=q"))]
5674 "TARGET_POWER"
5675 "mul %0,%1,%2"
5676 [(set_attr "type" "imul")])
deb9225a 5677
f192bf8b 5678(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 5679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5680 (truncate:SI
fada905b
MM		 5681 (lshiftrt:DI (mult:DI (sign_extend:DI
5682 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5683 (sign_extend:DI
5684 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 5685 (const_int 32))))]
f192bf8b 5686 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 5687 "mulhw %0,%1,%2"
5688 [(set_attr "type" "imul")])
deb9225a 5689
f192bf8b
DE		 5690(define_expand "umulsi3_highpart"
5691 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5692 (truncate:SI
5693 (lshiftrt:DI (mult:DI (zero_extend:DI
5694 (match_operand:SI 1 "gpc_reg_operand" ""))
5695 (zero_extend:DI
5696 (match_operand:SI 2 "gpc_reg_operand" "")))
5697 (const_int 32))))]
5698 "TARGET_POWERPC"
5699 "
5700{
5701 if (TARGET_POWER)
5702 {
5703 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5704 DONE;
5705 }
5706}")
5707
5708(define_insn "umulsi3_highpart_mq"
5709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5710 (truncate:SI
5711 (lshiftrt:DI (mult:DI (zero_extend:DI
5712 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5713 (zero_extend:DI
5714 (match_operand:SI 2 "gpc_reg_operand" "r")))
5715 (const_int 32))))
5716 (clobber (match_scratch:SI 3 "=q"))]
5717 "TARGET_POWERPC && TARGET_POWER"
5718 "mulhwu %0,%1,%2"
5719 [(set_attr "type" "imul")])
5720
5721(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 5722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5723 (truncate:SI
5724 (lshiftrt:DI (mult:DI (zero_extend:DI
5725 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5726 (zero_extend:DI
5727 (match_operand:SI 2 "gpc_reg_operand" "r")))
5728 (const_int 32))))]
f192bf8b 5729 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 5730 "mulhwu %0,%1,%2"
5731 [(set_attr "type" "imul")])
5732
5733;; If operands 0 and 2 are in the same register, we have a problem. But
5734;; operands 0 and 1 (the usual case) can be in the same register. That's
5735;; why we have the strange constraints below.
5736(define_insn "ashldi3_power"
5737 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5738 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5739 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5740 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5741 "TARGET_POWER"
5742 "@
5743 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5744 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5745 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5746 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5747 [(set_attr "length" "8")])
5748
5749(define_insn "lshrdi3_power"
47ad8c61 5750 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 5751 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5752 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5753 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5754 "TARGET_POWER"
5755 "@
47ad8c61 5756 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 5757 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5758 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5759 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5760 [(set_attr "length" "8")])
5761
5762;; Shift by a variable amount is too complex to be worth open-coding. We
5763;; just handle shifts by constants.
5764(define_insn "ashrdi3_power"
7093ddee 5765 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 5766 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5767 (match_operand:SI 2 "const_int_operand" "M,i")))
5768 (clobber (match_scratch:SI 3 "=X,q"))]
5769 "TARGET_POWER"
5770 "@
5771 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5772 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5773 [(set_attr "length" "8")])
4aa74a4f
FS		 5774
5775(define_insn "ashrdi3_no_power"
5776 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5777 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5778 (match_operand:SI 2 "const_int_operand" "M,i")))]
97727e85 5779 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
4aa74a4f
FS		 5780 "@
5781 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5782 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
943c15ed
DE		 5783 [(set_attr "type" "two,three")
5784 (set_attr "length" "8,12")])
683bdff7
FJ		 5785
5786(define_insn "*ashrdisi3_noppc64"
5787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 5788 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
683bdff7
FJ		 5789 (const_int 32)) 4))]
5790 "TARGET_32BIT && !TARGET_POWERPC64"
5791 "*
5792{
5793 if (REGNO (operands[0]) == REGNO (operands[1]))
5794 return \"\";
5795 else
5796 return \"mr %0,%1\";
5797}"
6ae08853 5798 [(set_attr "length" "4")])
683bdff7 5799
266eb58a
DE		 5800\f
5801;; PowerPC64 DImode operations.
5802
ea112fc4 5803(define_insn_and_split "absdi2"
266eb58a 5804 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 5805 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 5806 (clobber (match_scratch:DI 2 "=&r,&r"))]
5807 "TARGET_POWERPC64"
ea112fc4
DE		 5808 "#"
5809 "&& reload_completed"
a260abc9 5810 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 5811 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 5812 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 5813 "")
5814
ea112fc4 5815(define_insn_and_split "*nabsdi2"
266eb58a 5816 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 5817 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 5818 (clobber (match_scratch:DI 2 "=&r,&r"))]
5819 "TARGET_POWERPC64"
ea112fc4
DE		 5820 "#"
5821 "&& reload_completed"
a260abc9 5822 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 5823 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 5824 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 5825 "")
5826
266eb58a
DE		 5827(define_insn "muldi3"
5828 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5829 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5830 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5831 "TARGET_POWERPC64"
5832 "mulld %0,%1,%2"
3cb999d8 5833 [(set_attr "type" "lmul")])
266eb58a 5834
9259f3b0
DE		 5835(define_insn "*muldi3_internal1"
5836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5837 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5838 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5839 (const_int 0)))
5840 (clobber (match_scratch:DI 3 "=r,r"))]
5841 "TARGET_POWERPC64"
5842 "@
5843 mulld. %3,%1,%2
5844 #"
5845 [(set_attr "type" "lmul_compare")
5846 (set_attr "length" "4,8")])
5847
5848(define_split
5849 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5850 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5851 (match_operand:DI 2 "gpc_reg_operand" ""))
5852 (const_int 0)))
5853 (clobber (match_scratch:DI 3 ""))]
5854 "TARGET_POWERPC64 && reload_completed"
5855 [(set (match_dup 3)
5856 (mult:DI (match_dup 1) (match_dup 2)))
5857 (set (match_dup 0)
5858 (compare:CC (match_dup 3)
5859 (const_int 0)))]
5860 "")
5861
5862(define_insn "*muldi3_internal2"
5863 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5864 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5865 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5866 (const_int 0)))
5867 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5868 (mult:DI (match_dup 1) (match_dup 2)))]
5869 "TARGET_POWERPC64"
5870 "@
5871 mulld. %0,%1,%2
5872 #"
5873 [(set_attr "type" "lmul_compare")
5874 (set_attr "length" "4,8")])
5875
5876(define_split
5877 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5878 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5879 (match_operand:DI 2 "gpc_reg_operand" ""))
5880 (const_int 0)))
5881 (set (match_operand:DI 0 "gpc_reg_operand" "")
5882 (mult:DI (match_dup 1) (match_dup 2)))]
5883 "TARGET_POWERPC64 && reload_completed"
5884 [(set (match_dup 0)
5885 (mult:DI (match_dup 1) (match_dup 2)))
5886 (set (match_dup 3)
5887 (compare:CC (match_dup 0)
5888 (const_int 0)))]
5889 "")
5890
266eb58a
DE		 5891(define_insn "smuldi3_highpart"
5892 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5893 (truncate:DI
5894 (lshiftrt:TI (mult:TI (sign_extend:TI
5895 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5896 (sign_extend:TI
5897 (match_operand:DI 2 "gpc_reg_operand" "r")))
5898 (const_int 64))))]
5899 "TARGET_POWERPC64"
5900 "mulhd %0,%1,%2"
3cb999d8 5901 [(set_attr "type" "lmul")])
266eb58a
DE		 5902
5903(define_insn "umuldi3_highpart"
5904 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5905 (truncate:DI
5906 (lshiftrt:TI (mult:TI (zero_extend:TI
5907 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5908 (zero_extend:TI
5909 (match_operand:DI 2 "gpc_reg_operand" "r")))
5910 (const_int 64))))]
5911 "TARGET_POWERPC64"
5912 "mulhdu %0,%1,%2"
3cb999d8 5913 [(set_attr "type" "lmul")])
266eb58a 5914
266eb58a
DE		 5915(define_insn "rotldi3"
5916 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5917 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5918 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
5919 "TARGET_POWERPC64"
a66078ee 5920 "rld%I2cl %0,%1,%H2,0")
266eb58a 5921
a260abc9 5922(define_insn "*rotldi3_internal2"
9ebbca7d
GK		 5923 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5924 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5925 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 5926 (const_int 0)))
9ebbca7d 5927 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 5928 "TARGET_64BIT"
9ebbca7d
GK		 5929 "@
5930 rld%I2cl. %3,%1,%H2,0
5931 #"
5932 [(set_attr "type" "delayed_compare")
5933 (set_attr "length" "4,8")])
5934
5935(define_split
5936 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5937 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
5938 (match_operand:DI 2 "reg_or_cint_operand" ""))
5939 (const_int 0)))
5940 (clobber (match_scratch:DI 3 ""))]
5941 "TARGET_POWERPC64 && reload_completed"
5942 [(set (match_dup 3)
5943 (rotate:DI (match_dup 1) (match_dup 2)))
5944 (set (match_dup 0)
5945 (compare:CC (match_dup 3)
5946 (const_int 0)))]
5947 "")
266eb58a 5948
a260abc9 5949(define_insn "*rotldi3_internal3"
9ebbca7d
GK		 5950 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5951 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5952 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 5953 (const_int 0)))
9ebbca7d 5954 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 5955 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 5956 "TARGET_64BIT"
9ebbca7d
GK		 5957 "@
5958 rld%I2cl. %0,%1,%H2,0
5959 #"
5960 [(set_attr "type" "delayed_compare")
5961 (set_attr "length" "4,8")])
5962
5963(define_split
5964 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5965 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
5966 (match_operand:DI 2 "reg_or_cint_operand" ""))
5967 (const_int 0)))
5968 (set (match_operand:DI 0 "gpc_reg_operand" "")
5969 (rotate:DI (match_dup 1) (match_dup 2)))]
5970 "TARGET_POWERPC64 && reload_completed"
5971 [(set (match_dup 0)
5972 (rotate:DI (match_dup 1) (match_dup 2)))
5973 (set (match_dup 3)
5974 (compare:CC (match_dup 0)
5975 (const_int 0)))]
5976 "")
266eb58a 5977
a260abc9
DE		 5978(define_insn "*rotldi3_internal4"
5979 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5980 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5981 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4ae234b0 5982 (match_operand:DI 3 "mask_operand" "n")))]
a260abc9
DE		 5983 "TARGET_POWERPC64"
5984 "rld%I2c%B3 %0,%1,%H2,%S3")
5985
5986(define_insn "*rotldi3_internal5"
9ebbca7d 5987 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9 5988 (compare:CC (and:DI
9ebbca7d
GK		 5989 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5990 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
4ae234b0 5991 (match_operand:DI 3 "mask_operand" "n,n"))
a260abc9 5992 (const_int 0)))
9ebbca7d 5993 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 5994 "TARGET_64BIT"
9ebbca7d
GK		 5995 "@
5996 rld%I2c%B3. %4,%1,%H2,%S3
5997 #"
5998 [(set_attr "type" "delayed_compare")
5999 (set_attr "length" "4,8")])
6000
6001(define_split
6002 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6003 (compare:CC (and:DI
6004 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6005 (match_operand:DI 2 "reg_or_cint_operand" ""))
4ae234b0 6006 (match_operand:DI 3 "mask_operand" ""))
9ebbca7d
GK		 6007 (const_int 0)))
6008 (clobber (match_scratch:DI 4 ""))]
6009 "TARGET_POWERPC64 && reload_completed"
6010 [(set (match_dup 4)
6011 (and:DI (rotate:DI (match_dup 1)
6012 (match_dup 2))
6013 (match_dup 3)))
6014 (set (match_dup 0)
6015 (compare:CC (match_dup 4)
6016 (const_int 0)))]
6017 "")
a260abc9
DE		 6018
6019(define_insn "*rotldi3_internal6"
9ebbca7d 6020 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9 6021 (compare:CC (and:DI
9ebbca7d
GK		 6022 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6023 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
4ae234b0 6024 (match_operand:DI 3 "mask_operand" "n,n"))
a260abc9 6025 (const_int 0)))
9ebbca7d 6026 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6027 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6028 "TARGET_64BIT"
9ebbca7d
GK		 6029 "@
6030 rld%I2c%B3. %0,%1,%H2,%S3
6031 #"
6032 [(set_attr "type" "delayed_compare")
6033 (set_attr "length" "4,8")])
6034
6035(define_split
6036 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6037 (compare:CC (and:DI
6038 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6039 (match_operand:DI 2 "reg_or_cint_operand" ""))
4ae234b0 6040 (match_operand:DI 3 "mask_operand" ""))
9ebbca7d
GK		 6041 (const_int 0)))
6042 (set (match_operand:DI 0 "gpc_reg_operand" "")
6043 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6044 "TARGET_POWERPC64 && reload_completed"
6045 [(set (match_dup 0)
6046 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6047 (set (match_dup 4)
6048 (compare:CC (match_dup 0)
6049 (const_int 0)))]
6050 "")
a260abc9
DE		 6051
6052(define_insn "*rotldi3_internal7"
6053 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6054 (zero_extend:DI
6055 (subreg:QI
6056 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6057 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6058 "TARGET_POWERPC64"
6059 "rld%I2cl %0,%1,%H2,56")
6060
6061(define_insn "*rotldi3_internal8"
9ebbca7d 6062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6063 (compare:CC (zero_extend:DI
6064 (subreg:QI
9ebbca7d
GK		 6065 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6066 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6067 (const_int 0)))
9ebbca7d 6068 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6069 "TARGET_64BIT"
9ebbca7d
GK		 6070 "@
6071 rld%I2cl. %3,%1,%H2,56
6072 #"
6073 [(set_attr "type" "delayed_compare")
6074 (set_attr "length" "4,8")])
6075
6076(define_split
6077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6078 (compare:CC (zero_extend:DI
6079 (subreg:QI
6080 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6081 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6082 (const_int 0)))
6083 (clobber (match_scratch:DI 3 ""))]
6084 "TARGET_POWERPC64 && reload_completed"
6085 [(set (match_dup 3)
6086 (zero_extend:DI (subreg:QI
6087 (rotate:DI (match_dup 1)
6088 (match_dup 2)) 0)))
6089 (set (match_dup 0)
6090 (compare:CC (match_dup 3)
6091 (const_int 0)))]
6092 "")
a260abc9
DE		 6093
6094(define_insn "*rotldi3_internal9"
9ebbca7d 6095 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6096 (compare:CC (zero_extend:DI
6097 (subreg:QI
9ebbca7d
GK		 6098 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6099 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6100 (const_int 0)))
9ebbca7d 6101 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6102 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6103 "TARGET_64BIT"
9ebbca7d
GK		 6104 "@
6105 rld%I2cl. %0,%1,%H2,56
6106 #"
6107 [(set_attr "type" "delayed_compare")
6108 (set_attr "length" "4,8")])
6109
6110(define_split
6111 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6112 (compare:CC (zero_extend:DI
6113 (subreg:QI
6114 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6115 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6116 (const_int 0)))
6117 (set (match_operand:DI 0 "gpc_reg_operand" "")
6118 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6119 "TARGET_POWERPC64 && reload_completed"
6120 [(set (match_dup 0)
6121 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6122 (set (match_dup 3)
6123 (compare:CC (match_dup 0)
6124 (const_int 0)))]
6125 "")
a260abc9
DE		 6126
6127(define_insn "*rotldi3_internal10"
6128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6129 (zero_extend:DI
6130 (subreg:HI
6131 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6132 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6133 "TARGET_POWERPC64"
6134 "rld%I2cl %0,%1,%H2,48")
6135
6136(define_insn "*rotldi3_internal11"
9ebbca7d 6137 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6138 (compare:CC (zero_extend:DI
6139 (subreg:HI
9ebbca7d
GK		 6140 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6141 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6142 (const_int 0)))
9ebbca7d 6143 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6144 "TARGET_64BIT"
9ebbca7d
GK		 6145 "@
6146 rld%I2cl. %3,%1,%H2,48
6147 #"
6148 [(set_attr "type" "delayed_compare")
6149 (set_attr "length" "4,8")])
6150
6151(define_split
6152 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6153 (compare:CC (zero_extend:DI
6154 (subreg:HI
6155 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6156 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6157 (const_int 0)))
6158 (clobber (match_scratch:DI 3 ""))]
6159 "TARGET_POWERPC64 && reload_completed"
6160 [(set (match_dup 3)
6161 (zero_extend:DI (subreg:HI
6162 (rotate:DI (match_dup 1)
6163 (match_dup 2)) 0)))
6164 (set (match_dup 0)
6165 (compare:CC (match_dup 3)
6166 (const_int 0)))]
6167 "")
a260abc9
DE		 6168
6169(define_insn "*rotldi3_internal12"
9ebbca7d 6170 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6171 (compare:CC (zero_extend:DI
6172 (subreg:HI
9ebbca7d
GK		 6173 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6174 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6175 (const_int 0)))
9ebbca7d 6176 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6177 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6178 "TARGET_64BIT"
9ebbca7d
GK		 6179 "@
6180 rld%I2cl. %0,%1,%H2,48
6181 #"
6182 [(set_attr "type" "delayed_compare")
6183 (set_attr "length" "4,8")])
6184
6185(define_split
6186 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6187 (compare:CC (zero_extend:DI
6188 (subreg:HI
6189 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6190 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6191 (const_int 0)))
6192 (set (match_operand:DI 0 "gpc_reg_operand" "")
6193 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6194 "TARGET_POWERPC64 && reload_completed"
6195 [(set (match_dup 0)
6196 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6197 (set (match_dup 3)
6198 (compare:CC (match_dup 0)
6199 (const_int 0)))]
6200 "")
a260abc9
DE		 6201
6202(define_insn "*rotldi3_internal13"
6203 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6204 (zero_extend:DI
6205 (subreg:SI
6206 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6207 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6208 "TARGET_POWERPC64"
6209 "rld%I2cl %0,%1,%H2,32")
6210
6211(define_insn "*rotldi3_internal14"
9ebbca7d 6212 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6213 (compare:CC (zero_extend:DI
6214 (subreg:SI
9ebbca7d
GK		 6215 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6216 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6217 (const_int 0)))
9ebbca7d 6218 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6219 "TARGET_64BIT"
9ebbca7d
GK		 6220 "@
6221 rld%I2cl. %3,%1,%H2,32
6222 #"
6223 [(set_attr "type" "delayed_compare")
6224 (set_attr "length" "4,8")])
6225
6226(define_split
6227 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6228 (compare:CC (zero_extend:DI
6229 (subreg:SI
6230 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6231 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6232 (const_int 0)))
6233 (clobber (match_scratch:DI 3 ""))]
6234 "TARGET_POWERPC64 && reload_completed"
6235 [(set (match_dup 3)
6236 (zero_extend:DI (subreg:SI
6237 (rotate:DI (match_dup 1)
6238 (match_dup 2)) 0)))
6239 (set (match_dup 0)
6240 (compare:CC (match_dup 3)
6241 (const_int 0)))]
6242 "")
a260abc9
DE		 6243
6244(define_insn "*rotldi3_internal15"
9ebbca7d 6245 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6246 (compare:CC (zero_extend:DI
6247 (subreg:SI
9ebbca7d
GK		 6248 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6249 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6250 (const_int 0)))
9ebbca7d 6251 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6252 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6253 "TARGET_64BIT"
9ebbca7d
GK		 6254 "@
6255 rld%I2cl. %0,%1,%H2,32
6256 #"
6257 [(set_attr "type" "delayed_compare")
6258 (set_attr "length" "4,8")])
6259
6260(define_split
6261 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6262 (compare:CC (zero_extend:DI
6263 (subreg:SI
6264 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6265 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6266 (const_int 0)))
6267 (set (match_operand:DI 0 "gpc_reg_operand" "")
6268 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6269 "TARGET_POWERPC64 && reload_completed"
6270 [(set (match_dup 0)
6271 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6272 (set (match_dup 3)
6273 (compare:CC (match_dup 0)
6274 (const_int 0)))]
6275 "")
a260abc9 6276
266eb58a
DE		 6277(define_expand "ashldi3"
6278 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6279 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6280 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6281 "TARGET_POWERPC64 || TARGET_POWER"
6282 "
6283{
6284 if (TARGET_POWERPC64)
6285 ;
6286 else if (TARGET_POWER)
6287 {
6288 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6289 DONE;
6290 }
6291 else
6292 FAIL;
6293}")
6294
e2c953b6 6295(define_insn "*ashldi3_internal1"
266eb58a
DE		 6296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6297 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6298 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6299 "TARGET_POWERPC64"
943c15ed 6300 "sld%I2 %0,%1,%H2")
6ae08853 6301
e2c953b6 6302(define_insn "*ashldi3_internal2"
9ebbca7d
GK		 6303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6304 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6305 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6306 (const_int 0)))
9ebbca7d 6307 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6308 "TARGET_64BIT"
9ebbca7d
GK		 6309 "@
6310 sld%I2. %3,%1,%H2
6311 #"
6312 [(set_attr "type" "delayed_compare")
6313 (set_attr "length" "4,8")])
6ae08853 6314
9ebbca7d
GK		 6315(define_split
6316 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6317 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6318 (match_operand:SI 2 "reg_or_cint_operand" ""))
6319 (const_int 0)))
6320 (clobber (match_scratch:DI 3 ""))]
6321 "TARGET_POWERPC64 && reload_completed"
6322 [(set (match_dup 3)
6323 (ashift:DI (match_dup 1) (match_dup 2)))
6324 (set (match_dup 0)
6325 (compare:CC (match_dup 3)
6326 (const_int 0)))]
6327 "")
6328
e2c953b6 6329(define_insn "*ashldi3_internal3"
9ebbca7d
GK		 6330 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6331 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6332 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6333 (const_int 0)))
9ebbca7d 6334 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 6335 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 6336 "TARGET_64BIT"
9ebbca7d
GK		 6337 "@
6338 sld%I2. %0,%1,%H2
6339 #"
6340 [(set_attr "type" "delayed_compare")
6341 (set_attr "length" "4,8")])
6342
6343(define_split
6344 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6345 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6346 (match_operand:SI 2 "reg_or_cint_operand" ""))
6347 (const_int 0)))
6348 (set (match_operand:DI 0 "gpc_reg_operand" "")
6349 (ashift:DI (match_dup 1) (match_dup 2)))]
6350 "TARGET_POWERPC64 && reload_completed"
6351 [(set (match_dup 0)
6352 (ashift:DI (match_dup 1) (match_dup 2)))
6353 (set (match_dup 3)
6354 (compare:CC (match_dup 0)
6355 (const_int 0)))]
6356 "")
266eb58a 6357
e2c953b6 6358(define_insn "*ashldi3_internal4"
3cb999d8
DE		 6359 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6360 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6361 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 6362 (match_operand:DI 3 "const_int_operand" "n")))]
6363 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 6364 "rldic %0,%1,%H2,%W3")
3cb999d8 6365
e2c953b6 6366(define_insn "ashldi3_internal5"
9ebbca7d 6367 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 6368 (compare:CC
9ebbca7d
GK		 6369 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6370 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 6371 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 6372 (const_int 0)))
9ebbca7d 6373 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 6374 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 6375 "@
e2c953b6 6376 rldic. %4,%1,%H2,%W3
9ebbca7d
GK		 6377 #"
6378 [(set_attr "type" "delayed_compare")
6379 (set_attr "length" "4,8")])
6380
6381(define_split
6382 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6383 (compare:CC
6384 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6385 (match_operand:SI 2 "const_int_operand" ""))
c5059423 6386 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 6387 (const_int 0)))
6388 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 6389 "TARGET_POWERPC64 && reload_completed
6390 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 6391 [(set (match_dup 4)
6392 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 6393 (match_dup 3)))
9ebbca7d
GK		 6394 (set (match_dup 0)
6395 (compare:CC (match_dup 4)
6396 (const_int 0)))]
6397 "")
3cb999d8 6398
e2c953b6 6399(define_insn "*ashldi3_internal6"
9ebbca7d 6400 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 6401 (compare:CC
9ebbca7d
GK		 6402 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6403 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 6404 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 6405 (const_int 0)))
9ebbca7d 6406 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 6407 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6408 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 6409 "@
e2c953b6 6410 rldic. %0,%1,%H2,%W3
9ebbca7d
GK		 6411 #"
6412 [(set_attr "type" "delayed_compare")
6413 (set_attr "length" "4,8")])
6414
6415(define_split
6416 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6417 (compare:CC
6418 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6419 (match_operand:SI 2 "const_int_operand" ""))
c5059423 6420 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 6421 (const_int 0)))
6422 (set (match_operand:DI 0 "gpc_reg_operand" "")
6423 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 6424 "TARGET_POWERPC64 && reload_completed
6425 && includes_rldic_lshift_p (operands[2], operands[3])"
6426 [(set (match_dup 0)
6427 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6428 (match_dup 3)))
6429 (set (match_dup 4)
6430 (compare:CC (match_dup 0)
6431 (const_int 0)))]
6432 "")
6433
6434(define_insn "*ashldi3_internal7"
6435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6436 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6437 (match_operand:SI 2 "const_int_operand" "i"))
4ae234b0 6438 (match_operand:DI 3 "mask_operand" "n")))]
c5059423
AM		 6439 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6440 "rldicr %0,%1,%H2,%S3")
6441
6442(define_insn "ashldi3_internal8"
6443 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6444 (compare:CC
6445 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6446 (match_operand:SI 2 "const_int_operand" "i,i"))
4ae234b0 6447 (match_operand:DI 3 "mask_operand" "n,n"))
c5059423
AM		 6448 (const_int 0)))
6449 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 6450 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 6451 "@
6452 rldicr. %4,%1,%H2,%S3
6453 #"
6454 [(set_attr "type" "delayed_compare")
6455 (set_attr "length" "4,8")])
6456
6457(define_split
6458 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6459 (compare:CC
6460 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6461 (match_operand:SI 2 "const_int_operand" ""))
4ae234b0 6462 (match_operand:DI 3 "mask_operand" ""))
c5059423
AM		 6463 (const_int 0)))
6464 (clobber (match_scratch:DI 4 ""))]
6465 "TARGET_POWERPC64 && reload_completed
6466 && includes_rldicr_lshift_p (operands[2], operands[3])"
6467 [(set (match_dup 4)
6468 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6469 (match_dup 3)))
6470 (set (match_dup 0)
6471 (compare:CC (match_dup 4)
6472 (const_int 0)))]
6473 "")
6474
6475(define_insn "*ashldi3_internal9"
6476 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6477 (compare:CC
6478 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6479 (match_operand:SI 2 "const_int_operand" "i,i"))
4ae234b0 6480 (match_operand:DI 3 "mask_operand" "n,n"))
c5059423
AM		 6481 (const_int 0)))
6482 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6483 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6484 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 6485 "@
6486 rldicr. %0,%1,%H2,%S3
6487 #"
6488 [(set_attr "type" "delayed_compare")
6489 (set_attr "length" "4,8")])
6490
6491(define_split
6492 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6493 (compare:CC
6494 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6495 (match_operand:SI 2 "const_int_operand" ""))
4ae234b0 6496 (match_operand:DI 3 "mask_operand" ""))
c5059423
AM		 6497 (const_int 0)))
6498 (set (match_operand:DI 0 "gpc_reg_operand" "")
6499 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6500 "TARGET_POWERPC64 && reload_completed
6501 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 6502 [(set (match_dup 0)
e2c953b6
DE		 6503 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6504 (match_dup 3)))
9ebbca7d
GK		 6505 (set (match_dup 4)
6506 (compare:CC (match_dup 0)
6507 (const_int 0)))]
6508 "")
6509
6510(define_expand "lshrdi3"
266eb58a
DE		 6511 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6512 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6513 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6514 "TARGET_POWERPC64 || TARGET_POWER"
6515 "
6516{
6517 if (TARGET_POWERPC64)
6518 ;
6519 else if (TARGET_POWER)
6520 {
6521 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6522 DONE;
6523 }
6524 else
6525 FAIL;
6526}")
6527
e2c953b6 6528(define_insn "*lshrdi3_internal1"
266eb58a
DE		 6529 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6530 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6531 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6532 "TARGET_POWERPC64"
a66078ee 6533 "srd%I2 %0,%1,%H2")
266eb58a 6534
e2c953b6 6535(define_insn "*lshrdi3_internal2"
9ebbca7d
GK		 6536 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6537 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6538 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
29ae5b89 6539 (const_int 0)))
9ebbca7d 6540 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6541 "TARGET_64BIT "
9ebbca7d
GK		 6542 "@
6543 srd%I2. %3,%1,%H2
6544 #"
6545 [(set_attr "type" "delayed_compare")
6546 (set_attr "length" "4,8")])
6547
6548(define_split
6549 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6550 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6551 (match_operand:SI 2 "reg_or_cint_operand" ""))
6552 (const_int 0)))
6553 (clobber (match_scratch:DI 3 ""))]
6554 "TARGET_POWERPC64 && reload_completed"
6555 [(set (match_dup 3)
6556 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6557 (set (match_dup 0)
6558 (compare:CC (match_dup 3)
6559 (const_int 0)))]
6560 "")
266eb58a 6561
e2c953b6 6562(define_insn "*lshrdi3_internal3"
9ebbca7d
GK		 6563 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6564 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6565 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6566 (const_int 0)))
9ebbca7d 6567 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
29ae5b89 6568 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 6569 "TARGET_64BIT"
9ebbca7d
GK		 6570 "@
6571 srd%I2. %0,%1,%H2
6572 #"
6573 [(set_attr "type" "delayed_compare")
6574 (set_attr "length" "4,8")])
6575
6576(define_split
6577 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6578 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6579 (match_operand:SI 2 "reg_or_cint_operand" ""))
6580 (const_int 0)))
6581 (set (match_operand:DI 0 "gpc_reg_operand" "")
6582 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6583 "TARGET_POWERPC64 && reload_completed"
6584 [(set (match_dup 0)
6585 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6586 (set (match_dup 3)
6587 (compare:CC (match_dup 0)
6588 (const_int 0)))]
6589 "")
266eb58a
DE		 6590
6591(define_expand "ashrdi3"
6592 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6593 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6594 (match_operand:SI 2 "reg_or_cint_operand" "")))]
97727e85 6595 "WORDS_BIG_ENDIAN"
266eb58a
DE		 6596 "
6597{
6598 if (TARGET_POWERPC64)
6599 ;
6600 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6601 {
6602 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6603 DONE;
6604 }
97727e85
AH		 6605 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6606 && WORDS_BIG_ENDIAN)
4aa74a4f
FS		 6607 {
6608 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6609 DONE;
6610 }
266eb58a
DE		 6611 else
6612 FAIL;
6613}")
6614
e2c953b6 6615(define_insn "*ashrdi3_internal1"
266eb58a
DE		 6616 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6617 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6618 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6619 "TARGET_POWERPC64"
375490e0 6620 "srad%I2 %0,%1,%H2")
266eb58a 6621
e2c953b6 6622(define_insn "*ashrdi3_internal2"
9ebbca7d
GK		 6623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6624 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6625 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6626 (const_int 0)))
9ebbca7d 6627 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6628 "TARGET_64BIT"
9ebbca7d
GK		 6629 "@
6630 srad%I2. %3,%1,%H2
6631 #"
6632 [(set_attr "type" "delayed_compare")
6633 (set_attr "length" "4,8")])
6634
6635(define_split
6636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6637 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6638 (match_operand:SI 2 "reg_or_cint_operand" ""))
6639 (const_int 0)))
6640 (clobber (match_scratch:DI 3 ""))]
6641 "TARGET_POWERPC64 && reload_completed"
6642 [(set (match_dup 3)
6643 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6644 (set (match_dup 0)
6645 (compare:CC (match_dup 3)
6646 (const_int 0)))]
6647 "")
266eb58a 6648
e2c953b6 6649(define_insn "*ashrdi3_internal3"
9ebbca7d
GK		 6650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6651 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6652 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6653 (const_int 0)))
9ebbca7d 6654 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 6655 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 6656 "TARGET_64BIT"
9ebbca7d
GK		 6657 "@
6658 srad%I2. %0,%1,%H2
6659 #"
6660 [(set_attr "type" "delayed_compare")
6661 (set_attr "length" "4,8")])
6662
6663(define_split
6664 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6665 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6666 (match_operand:SI 2 "reg_or_cint_operand" ""))
6667 (const_int 0)))
6668 (set (match_operand:DI 0 "gpc_reg_operand" "")
6669 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6670 "TARGET_POWERPC64 && reload_completed"
6671 [(set (match_dup 0)
6672 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6673 (set (match_dup 3)
6674 (compare:CC (match_dup 0)
6675 (const_int 0)))]
6676 "")
815cdc52 6677
29ae5b89 6678(define_insn "anddi3"
e1e2e653
NS		 6679 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6680 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6681 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6682 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6ffc8580 6683 "TARGET_POWERPC64"
266eb58a
DE		 6684 "@
6685 and %0,%1,%2
29ae5b89 6686 rldic%B2 %0,%1,0,%S2
e1e2e653 6687 rlwinm %0,%1,0,%m2,%M2
29ae5b89 6688 andi. %0,%1,%b2
0ba1b2ff
AM		 6689 andis. %0,%1,%u2
6690 #"
e1e2e653
NS		 6691 [(set_attr "type" "*,*,*,compare,compare,*")
6692 (set_attr "length" "4,4,4,4,4,8")])
0ba1b2ff
AM		 6693
6694(define_split
6695 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6696 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6697 (match_operand:DI 2 "mask64_2_operand" "")))
6698 (clobber (match_scratch:CC 3 ""))]
6699 "TARGET_POWERPC64
6700 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
4ae234b0 6701 && !mask_operand (operands[2], DImode)"
0ba1b2ff
AM		 6702 [(set (match_dup 0)
6703 (and:DI (rotate:DI (match_dup 1)
6704 (match_dup 4))
6705 (match_dup 5)))
6706 (set (match_dup 0)
6707 (and:DI (rotate:DI (match_dup 0)
6708 (match_dup 6))
6709 (match_dup 7)))]
0ba1b2ff
AM		 6710{
6711 build_mask64_2_operands (operands[2], &operands[4]);
e1e2e653 6712})
266eb58a 6713
a260abc9 6714(define_insn "*anddi3_internal2"
0ba1b2ff
AM		 6715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6716 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6717 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
266eb58a 6718 (const_int 0)))
0ba1b2ff
AM		 6719 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6720 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
683bdff7 6721 "TARGET_64BIT"
266eb58a
DE		 6722 "@
6723 and. %3,%1,%2
6c873122 6724 rldic%B2. %3,%1,0,%S2
6ffc8580
MM		 6725 andi. %3,%1,%b2
6726 andis. %3,%1,%u2
9ebbca7d
GK		 6727 #
6728 #
6729 #
0ba1b2ff
AM		 6730 #
6731 #
9ebbca7d 6732 #"
0ba1b2ff
AM		 6733 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6734 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
9ebbca7d 6735
0ba1b2ff
AM		 6736(define_split
6737 [(set (match_operand:CC 0 "cc_reg_operand" "")
6738 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6739 (match_operand:DI 2 "mask64_2_operand" ""))
6740 (const_int 0)))
6741 (clobber (match_scratch:DI 3 ""))
6742 (clobber (match_scratch:CC 4 ""))]
6743 "TARGET_POWERPC64 && reload_completed
6744 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
4ae234b0 6745 && !mask_operand (operands[2], DImode)"
0ba1b2ff
AM		 6746 [(set (match_dup 3)
6747 (and:DI (rotate:DI (match_dup 1)
6748 (match_dup 5))
6749 (match_dup 6)))
6750 (parallel [(set (match_dup 0)
6751 (compare:CC (and:DI (rotate:DI (match_dup 3)
6752 (match_dup 7))
6753 (match_dup 8))
6754 (const_int 0)))
6755 (clobber (match_dup 3))])]
6756 "
6757{
6758 build_mask64_2_operands (operands[2], &operands[5]);
6759}")
6760
a260abc9 6761(define_insn "*anddi3_internal3"
0ba1b2ff
AM		 6762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6763 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6764 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
266eb58a 6765 (const_int 0)))
0ba1b2ff 6766 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
9ebbca7d 6767 (and:DI (match_dup 1) (match_dup 2)))
0ba1b2ff 6768 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
683bdff7 6769 "TARGET_64BIT"
266eb58a
DE		 6770 "@
6771 and. %0,%1,%2
6c873122 6772 rldic%B2. %0,%1,0,%S2
6ffc8580
MM		 6773 andi. %0,%1,%b2
6774 andis. %0,%1,%u2
9ebbca7d
GK		 6775 #
6776 #
6777 #
0ba1b2ff
AM		 6778 #
6779 #
9ebbca7d 6780 #"
0ba1b2ff
AM		 6781 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6782 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
9ebbca7d
GK		 6783
6784(define_split
6785 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6786 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
4ae234b0 6787 (match_operand:DI 2 "and_operand" ""))
9ebbca7d
GK		 6788 (const_int 0)))
6789 (set (match_operand:DI 0 "gpc_reg_operand" "")
6790 (and:DI (match_dup 1) (match_dup 2)))
6791 (clobber (match_scratch:CC 4 ""))]
6792 "TARGET_POWERPC64 && reload_completed"
6793 [(parallel [(set (match_dup 0)
6794 (and:DI (match_dup 1) (match_dup 2)))
6795 (clobber (match_dup 4))])
6796 (set (match_dup 3)
6797 (compare:CC (match_dup 0)
6798 (const_int 0)))]
6799 "")
266eb58a 6800
0ba1b2ff
AM		 6801(define_split
6802 [(set (match_operand:CC 3 "cc_reg_operand" "")
6803 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6804 (match_operand:DI 2 "mask64_2_operand" ""))
6805 (const_int 0)))
6806 (set (match_operand:DI 0 "gpc_reg_operand" "")
6807 (and:DI (match_dup 1) (match_dup 2)))
6808 (clobber (match_scratch:CC 4 ""))]
6809 "TARGET_POWERPC64 && reload_completed
6810 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
4ae234b0 6811 && !mask_operand (operands[2], DImode)"
0ba1b2ff
AM		 6812 [(set (match_dup 0)
6813 (and:DI (rotate:DI (match_dup 1)
6814 (match_dup 5))
6815 (match_dup 6)))
6816 (parallel [(set (match_dup 3)
6817 (compare:CC (and:DI (rotate:DI (match_dup 0)
6818 (match_dup 7))
6819 (match_dup 8))
6820 (const_int 0)))
6821 (set (match_dup 0)
6822 (and:DI (rotate:DI (match_dup 0)
6823 (match_dup 7))
6824 (match_dup 8)))])]
6825 "
6826{
6827 build_mask64_2_operands (operands[2], &operands[5]);
6828}")
6829
a260abc9 6830(define_expand "iordi3"
266eb58a 6831 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 6832 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 6833 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 6834 "TARGET_POWERPC64"
266eb58a
DE		 6835 "
6836{
dfbdccdb 6837 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 6838 {
dfbdccdb 6839 HOST_WIDE_INT value;
677a9668 6840 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9 6841 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 6842
dfbdccdb
GK		 6843 if (GET_CODE (operands[2]) == CONST_INT)
6844 {
6845 value = INTVAL (operands[2]);
6846 emit_insn (gen_iordi3 (tmp, operands[1],
6847 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6848 }
e2c953b6 6849 else
dfbdccdb
GK		 6850 {
6851 value = CONST_DOUBLE_LOW (operands[2]);
6852 emit_insn (gen_iordi3 (tmp, operands[1],
6853 immed_double_const (value
6854 & (~ (HOST_WIDE_INT) 0xffff),
6855 0, DImode)));
6856 }
e2c953b6 6857
9ebbca7d
GK		 6858 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6859 DONE;
6860 }
266eb58a
DE		 6861}")
6862
a260abc9
DE		 6863(define_expand "xordi3"
6864 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6865 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 6866 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 6867 "TARGET_POWERPC64"
6868 "
6869{
dfbdccdb 6870 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 6871 {
dfbdccdb 6872 HOST_WIDE_INT value;
677a9668 6873 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 6874 ? operands[0] : gen_reg_rtx (DImode));
6875
dfbdccdb
GK		 6876 if (GET_CODE (operands[2]) == CONST_INT)
6877 {
6878 value = INTVAL (operands[2]);
6879 emit_insn (gen_xordi3 (tmp, operands[1],
6880 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6881 }
e2c953b6 6882 else
dfbdccdb
GK		 6883 {
6884 value = CONST_DOUBLE_LOW (operands[2]);
6885 emit_insn (gen_xordi3 (tmp, operands[1],
6886 immed_double_const (value
6887 & (~ (HOST_WIDE_INT) 0xffff),
6888 0, DImode)));
6889 }
e2c953b6 6890
9ebbca7d
GK		 6891 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6892 DONE;
6893 }
a260abc9
DE		 6894}")
6895
dfbdccdb 6896(define_insn "*booldi3_internal1"
266eb58a 6897 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 6898 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 6899 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
6900 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 6901 "TARGET_POWERPC64"
1fd4e8c1 6902 "@
dfbdccdb
GK		 6903 %q3 %0,%1,%2
6904 %q3i %0,%1,%b2
6905 %q3is %0,%1,%u2")
1fd4e8c1 6906
dfbdccdb 6907(define_insn "*booldi3_internal2"
9ebbca7d 6908 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 6909 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 6910 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
6911 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
6912 (const_int 0)))
9ebbca7d 6913 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6914 "TARGET_64BIT"
9ebbca7d 6915 "@
dfbdccdb 6916 %q4. %3,%1,%2
9ebbca7d
GK		 6917 #"
6918 [(set_attr "type" "compare")
6919 (set_attr "length" "4,8")])
6920
6921(define_split
6922 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 6923 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 6924 [(match_operand:DI 1 "gpc_reg_operand" "")
6925 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 6926 (const_int 0)))
9ebbca7d
GK		 6927 (clobber (match_scratch:DI 3 ""))]
6928 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 6929 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 6930 (set (match_dup 0)
6931 (compare:CC (match_dup 3)
6932 (const_int 0)))]
6933 "")
1fd4e8c1 6934
dfbdccdb 6935(define_insn "*booldi3_internal3"
9ebbca7d 6936 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 6937 (compare:CC (match_operator:DI 4 "boolean_operator"
6938 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
6939 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
6940 (const_int 0)))
9ebbca7d 6941 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 6942 (match_dup 4))]
683bdff7 6943 "TARGET_64BIT"
9ebbca7d 6944 "@
dfbdccdb 6945 %q4. %0,%1,%2
9ebbca7d
GK		 6946 #"
6947 [(set_attr "type" "compare")
6948 (set_attr "length" "4,8")])
6949
6950(define_split
e72247f4 6951 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 6952 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 6953 [(match_operand:DI 1 "gpc_reg_operand" "")
6954 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 6955 (const_int 0)))
75540af0 6956 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 6957 (match_dup 4))]
9ebbca7d 6958 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 6959 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 6960 (set (match_dup 3)
6961 (compare:CC (match_dup 0)
6962 (const_int 0)))]
6963 "")
1fd4e8c1 6964
6ae08853 6965;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 6966;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 6967
6968(define_split
6969 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 6970 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 6971 [(match_operand:DI 1 "gpc_reg_operand" "")
6972 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 6973 "TARGET_POWERPC64"
dfbdccdb
GK		 6974 [(set (match_dup 0) (match_dup 4))
6975 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 6976"
6977{
dfbdccdb 6978 rtx i3,i4;
6ae08853 6979
9ebbca7d
GK		 6980 if (GET_CODE (operands[2]) == CONST_DOUBLE)
6981 {
6982 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 6983 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 6984 0, DImode);
dfbdccdb 6985 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 6986 }
6987 else
6988 {
dfbdccdb 6989 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 6990 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 6991 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 6992 }
1c563bed 6993 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 6994 operands[1], i3);
1c563bed 6995 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 6996 operands[0], i4);
1fd4e8c1
RK		 6997}")
6998
dfbdccdb 6999(define_insn "*boolcdi3_internal1"
9ebbca7d 7000 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7001 (match_operator:DI 3 "boolean_operator"
7002 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7003 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7004 "TARGET_POWERPC64"
1d328b19 7005 "%q3 %0,%2,%1")
a473029f 7006
dfbdccdb 7007(define_insn "*boolcdi3_internal2"
9ebbca7d 7008 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7009 (compare:CC (match_operator:DI 4 "boolean_operator"
7010 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7011 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7012 (const_int 0)))
9ebbca7d 7013 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7014 "TARGET_64BIT"
9ebbca7d 7015 "@
1d328b19 7016 %q4. %3,%2,%1
9ebbca7d
GK		 7017 #"
7018 [(set_attr "type" "compare")
7019 (set_attr "length" "4,8")])
7020
7021(define_split
7022 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7023 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7024 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7025 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7026 (const_int 0)))
9ebbca7d
GK		 7027 (clobber (match_scratch:DI 3 ""))]
7028 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7029 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7030 (set (match_dup 0)
7031 (compare:CC (match_dup 3)
7032 (const_int 0)))]
7033 "")
a473029f 7034
dfbdccdb 7035(define_insn "*boolcdi3_internal3"
9ebbca7d 7036 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7037 (compare:CC (match_operator:DI 4 "boolean_operator"
7038 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7039 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7040 (const_int 0)))
9ebbca7d 7041 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7042 (match_dup 4))]
683bdff7 7043 "TARGET_64BIT"
9ebbca7d 7044 "@
1d328b19 7045 %q4. %0,%2,%1
9ebbca7d
GK		 7046 #"
7047 [(set_attr "type" "compare")
7048 (set_attr "length" "4,8")])
7049
7050(define_split
e72247f4 7051 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7052 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7053 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7054 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7055 (const_int 0)))
75540af0 7056 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7057 (match_dup 4))]
9ebbca7d 7058 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7059 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7060 (set (match_dup 3)
7061 (compare:CC (match_dup 0)
7062 (const_int 0)))]
7063 "")
266eb58a 7064
dfbdccdb 7065(define_insn "*boolccdi3_internal1"
a473029f 7066 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7067 (match_operator:DI 3 "boolean_operator"
7068 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7069 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 7070 "TARGET_POWERPC64"
dfbdccdb 7071 "%q3 %0,%1,%2")
a473029f 7072
dfbdccdb 7073(define_insn "*boolccdi3_internal2"
9ebbca7d 7074 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7075 (compare:CC (match_operator:DI 4 "boolean_operator"
7076 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7077 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7078 (const_int 0)))
9ebbca7d 7079 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7080 "TARGET_64BIT"
9ebbca7d 7081 "@
dfbdccdb 7082 %q4. %3,%1,%2
9ebbca7d
GK		 7083 #"
7084 [(set_attr "type" "compare")
7085 (set_attr "length" "4,8")])
7086
7087(define_split
7088 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7089 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7090 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7091 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7092 (const_int 0)))
9ebbca7d
GK		 7093 (clobber (match_scratch:DI 3 ""))]
7094 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7095 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7096 (set (match_dup 0)
7097 (compare:CC (match_dup 3)
7098 (const_int 0)))]
7099 "")
266eb58a 7100
dfbdccdb 7101(define_insn "*boolccdi3_internal3"
9ebbca7d 7102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7103 (compare:CC (match_operator:DI 4 "boolean_operator"
7104 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7105 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7106 (const_int 0)))
9ebbca7d 7107 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7108 (match_dup 4))]
683bdff7 7109 "TARGET_64BIT"
9ebbca7d 7110 "@
dfbdccdb 7111 %q4. %0,%1,%2
9ebbca7d
GK		 7112 #"
7113 [(set_attr "type" "compare")
7114 (set_attr "length" "4,8")])
7115
7116(define_split
e72247f4 7117 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7118 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7119 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7120 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7121 (const_int 0)))
75540af0 7122 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7123 (match_dup 4))]
9ebbca7d 7124 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7125 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7126 (set (match_dup 3)
7127 (compare:CC (match_dup 0)
7128 (const_int 0)))]
7129 "")
dfbdccdb 7130\f
1fd4e8c1 7131;; Now define ways of moving data around.
4697a36c 7132
766a866c
MM		 7133;; Set up a register with a value from the GOT table
7134
7135(define_expand "movsi_got"
52d3af72 7136 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7137 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 7138 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 7139 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7140 "
7141{
38c1f2d7
MM		 7142 if (GET_CODE (operands[1]) == CONST)
7143 {
7144 rtx offset = const0_rtx;
7145 HOST_WIDE_INT value;
7146
7147 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7148 value = INTVAL (offset);
7149 if (value != 0)
7150 {
677a9668 7151 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
38c1f2d7
MM		 7152 emit_insn (gen_movsi_got (tmp, operands[1]));
7153 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7154 DONE;
7155 }
7156 }
7157
c4c40373 7158 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 7159}")
7160
84f414bc 7161(define_insn "*movsi_got_internal"
52d3af72 7162 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 7163 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 7164 (match_operand:SI 2 "gpc_reg_operand" "b")]
7165 UNSPEC_MOVSI_GOT))]
f607bc57 7166 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7167 "{l|lwz} %0,%a1@got(%2)"
7168 [(set_attr "type" "load")])
7169
b22b9b3e
JL		 7170;; Used by sched, shorten_branches and final when the GOT pseudo reg
7171;; didn't get allocated to a hard register.
6ae08853 7172(define_split
75540af0 7173 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7174 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 7175 (match_operand:SI 2 "memory_operand" "")]
7176 UNSPEC_MOVSI_GOT))]
f607bc57 7177 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 7178 && flag_pic == 1
7179 && (reload_in_progress || reload_completed)"
7180 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 7181 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7182 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 7183 "")
7184
1fd4e8c1
RK		 7185;; For SI, we special-case integers that can't be loaded in one insn. We
7186;; do the load 16-bits at a time. We could do this by loading from memory,
7187;; and this is even supposed to be faster, but it is simpler not to get
7188;; integers in the TOC.
ee890fe2
SS		 7189(define_insn "movsi_low"
7190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 7191 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 7192 (match_operand 2 "" ""))))]
7193 "TARGET_MACHO && ! TARGET_64BIT"
7194 "{l|lwz} %0,lo16(%2)(%1)"
7195 [(set_attr "type" "load")
7196 (set_attr "length" "4")])
7197
acad7ed3 7198(define_insn "*movsi_internal1"
165a5bad 7199 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
a004eb82 7200 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
19d5775a
RK		 7201 "gpc_reg_operand (operands[0], SImode)
7202 || gpc_reg_operand (operands[1], SImode)"
1fd4e8c1 7203 "@
deb9225a 7204 mr %0,%1
b9442c72 7205 {cal|la} %0,%a1
ca7f5001
RK		 7206 {l%U1%X1|lwz%U1%X1} %0,%1
7207 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 7208 {lil|li} %0,%1
802a0058 7209 {liu|lis} %0,%v1
beaec479 7210 #
aee86b38 7211 {cal|la} %0,%a1
1fd4e8c1 7212 mf%1 %0
5c23c401 7213 mt%0 %1
e76e75bb 7214 mt%0 %1
a004eb82 7215 mt%0 %1
e34eaae5 7216 {cror 0,0,0|nop}"
02ca7595 7217 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 7218 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 7219
77fa0940
RK		 7220;; Split a load of a large constant into the appropriate two-insn
7221;; sequence.
7222
7223(define_split
7224 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7225 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 7226 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 7227 && (INTVAL (operands[1]) & 0xffff) != 0"
7228 [(set (match_dup 0)
7229 (match_dup 2))
7230 (set (match_dup 0)
7231 (ior:SI (match_dup 0)
7232 (match_dup 3)))]
7233 "
af8cb5c5
DE		 7234{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7235
7236 if (tem == operands[0])
7237 DONE;
7238 else
7239 FAIL;
77fa0940
RK		 7240}")
7241
4ae234b0 7242(define_insn "*mov<mode>_internal2"
bb84cb12 7243 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
4ae234b0 7244 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 7245 (const_int 0)))
4ae234b0
GK		 7246 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7247 ""
9ebbca7d 7248 "@
4ae234b0 7249 {cmpi|cmp<wd>i} %2,%0,0
9ebbca7d
GK		 7250 mr. %0,%1
7251 #"
bb84cb12
DE		 7252 [(set_attr "type" "cmp,compare,cmp")
7253 (set_attr "length" "4,4,8")])
7254
9ebbca7d
GK		 7255(define_split
7256 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
4ae234b0 7257 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9ebbca7d 7258 (const_int 0)))
4ae234b0
GK		 7259 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7260 "reload_completed"
9ebbca7d
GK		 7261 [(set (match_dup 0) (match_dup 1))
7262 (set (match_dup 2)
7263 (compare:CC (match_dup 0)
7264 (const_int 0)))]
7265 "")
bb84cb12 7266\f
e34eaae5 7267(define_insn "*movhi_internal"
fb81d7ce
RK		 7268 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7269 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 7270 "gpc_reg_operand (operands[0], HImode)
7271 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 7272 "@
deb9225a 7273 mr %0,%1
1fd4e8c1
RK		 7274 lhz%U1%X1 %0,%1
7275 sth%U0%X0 %1,%0
19d5775a 7276 {lil|li} %0,%w1
1fd4e8c1 7277 mf%1 %0
e76e75bb 7278 mt%0 %1
fb81d7ce 7279 mt%0 %1
e34eaae5 7280 {cror 0,0,0|nop}"
02ca7595 7281 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1 7282
4ae234b0
GK		 7283(define_expand "mov<mode>"
7284 [(set (match_operand:INT 0 "general_operand" "")
7285 (match_operand:INT 1 "any_operand" ""))]
1fd4e8c1 7286 ""
4ae234b0 7287 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
1fd4e8c1 7288
e34eaae5 7289(define_insn "*movqi_internal"
fb81d7ce
RK		 7290 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7291 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 7292 "gpc_reg_operand (operands[0], QImode)
7293 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 7294 "@
deb9225a 7295 mr %0,%1
1fd4e8c1
RK		 7296 lbz%U1%X1 %0,%1
7297 stb%U0%X0 %1,%0
19d5775a 7298 {lil|li} %0,%1
1fd4e8c1 7299 mf%1 %0
e76e75bb 7300 mt%0 %1
fb81d7ce 7301 mt%0 %1
e34eaae5 7302 {cror 0,0,0|nop}"
02ca7595 7303 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 7304\f
7305;; Here is how to move condition codes around. When we store CC data in
7306;; an integer register or memory, we store just the high-order 4 bits.
7307;; This lets us not shift in the most common case of CR0.
7308(define_expand "movcc"
7309 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7310 (match_operand:CC 1 "nonimmediate_operand" ""))]
7311 ""
7312 "")
7313
a65c591c 7314(define_insn "*movcc_internal1"
b54cf83a
DE		 7315 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7316 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
1fd4e8c1
RK		 7317 "register_operand (operands[0], CCmode)
7318 || register_operand (operands[1], CCmode)"
7319 "@
7320 mcrf %0,%1
7321 mtcrf 128,%1
ca7f5001 7322 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
2c4a9cff
DE		 7323 mfcr %0%Q1
7324 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 7325 mr %0,%1
b54cf83a 7326 mf%1 %0
b991a865
GK		 7327 mt%0 %1
7328 mt%0 %1
ca7f5001
RK		 7329 {l%U1%X1|lwz%U1%X1} %0,%1
7330 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff
DE		 7331 [(set (attr "type")
7332 (cond [(eq_attr "alternative" "0")
7333 (const_string "cr_logical")
7334 (eq_attr "alternative" "1,2")
7335 (const_string "mtcr")
7336 (eq_attr "alternative" "5,7")
7337 (const_string "integer")
7338 (eq_attr "alternative" "6")
7339 (const_string "mfjmpr")
7340 (eq_attr "alternative" "8")
7341 (const_string "mtjmpr")
7342 (eq_attr "alternative" "9")
7343 (const_string "load")
7344 (eq_attr "alternative" "10")
7345 (const_string "store")
7346 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7347 (const_string "mfcrf")
7348 ]
7349 (const_string "mfcr")))
b991a865 7350 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
1fd4e8c1 7351\f
e52e05ca
MM		 7352;; For floating-point, we normally deal with the floating-point registers
7353;; unless -msoft-float is used. The sole exception is that parameter passing
7354;; can produce floating-point values in fixed-point registers. Unless the
7355;; value is a simple constant or already in memory, we deal with this by
7356;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 7357(define_expand "movsf"
7358 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7359 (match_operand:SF 1 "any_operand" ""))]
7360 ""
fb4d4348 7361 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 7362
1fd4e8c1 7363(define_split
cd2b37d9 7364 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 7365 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 7366 "reload_completed
5ae4759c
MM		 7367 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7368 || (GET_CODE (operands[0]) == SUBREG
7369 && GET_CODE (SUBREG_REG (operands[0])) == REG
7370 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 7371 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 7372 "
7373{
7374 long l;
7375 REAL_VALUE_TYPE rv;
7376
7377 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7378 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 7379
f99f88e0
DE		 7380 if (! TARGET_POWERPC64)
7381 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7382 else
7383 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 7384
2496c7bd 7385 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 7386}")
7387
c4c40373 7388(define_insn "*movsf_hardfloat"
ae6669e7
DJ		 7389 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7390 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
d14a6d05 7391 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 7392 || gpc_reg_operand (operands[1], SFmode))
7393 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
1fd4e8c1 7394 "@
f99f88e0
DE		 7395 mr %0,%1
7396 {l%U1%X1|lwz%U1%X1} %0,%1
7397 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 7398 fmr %0,%1
7399 lfs%U1%X1 %0,%1
c4c40373 7400 stfs%U0%X0 %1,%0
b991a865
GK		 7401 mt%0 %1
7402 mt%0 %1
7403 mf%1 %0
e0740893 7404 {cror 0,0,0|nop}
c4c40373
MM		 7405 #
7406 #"
ae6669e7
DJ		 7407 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7408 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 7409
c4c40373 7410(define_insn "*movsf_softfloat"
dd0fbae2
MK		 7411 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7412 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 7413 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 7414 || gpc_reg_operand (operands[1], SFmode))
7415 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 7416 "@
7417 mr %0,%1
b991a865
GK		 7418 mt%0 %1
7419 mt%0 %1
7420 mf%1 %0
d14a6d05
MM		 7421 {l%U1%X1|lwz%U1%X1} %0,%1
7422 {st%U0%X0|stw%U0%X0} %1,%0
7423 {lil|li} %0,%1
802a0058 7424 {liu|lis} %0,%v1
aee86b38 7425 {cal|la} %0,%a1
c4c40373 7426 #
dd0fbae2
MK		 7427 #
7428 {cror 0,0,0|nop}"
7429 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7430 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 7431
1fd4e8c1
RK		 7432\f
7433(define_expand "movdf"
7434 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7435 (match_operand:DF 1 "any_operand" ""))]
7436 ""
fb4d4348 7437 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 7438
7439(define_split
cd2b37d9 7440 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 7441 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 7442 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7443 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7444 || (GET_CODE (operands[0]) == SUBREG
7445 && GET_CODE (SUBREG_REG (operands[0])) == REG
7446 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 7447 [(set (match_dup 2) (match_dup 4))
7448 (set (match_dup 3) (match_dup 1))]
7449 "
7450{
5ae4759c 7451 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 7452 HOST_WIDE_INT value = INTVAL (operands[1]);
7453
5ae4759c
MM		 7454 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7455 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 7456#if HOST_BITS_PER_WIDE_INT == 32
7457 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7458#else
7459 operands[4] = GEN_INT (value >> 32);
a65c591c 7460 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 7461#endif
c4c40373
MM		 7462}")
7463
c4c40373
MM		 7464(define_split
7465 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7466 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 7467 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7468 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7469 || (GET_CODE (operands[0]) == SUBREG
7470 && GET_CODE (SUBREG_REG (operands[0])) == REG
7471 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 7472 [(set (match_dup 2) (match_dup 4))
7473 (set (match_dup 3) (match_dup 5))]
7474 "
7475{
5ae4759c 7476 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 7477 long l[2];
7478 REAL_VALUE_TYPE rv;
7479
7480 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7481 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7482
5ae4759c
MM		 7483 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7484 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 7485 operands[4] = gen_int_mode (l[endian], SImode);
7486 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 7487}")
7488
efc08378
DE		 7489(define_split
7490 [(set (match_operand:DF 0 "gpc_reg_operand" "")
685f3906 7491 (match_operand:DF 1 "easy_fp_constant" ""))]
a260abc9 7492 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7493 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7494 || (GET_CODE (operands[0]) == SUBREG
7495 && GET_CODE (SUBREG_REG (operands[0])) == REG
7496 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 7497 [(set (match_dup 2) (match_dup 3))]
5ae4759c 7498 "
a260abc9
DE		 7499{
7500 int endian = (WORDS_BIG_ENDIAN == 0);
7501 long l[2];
7502 REAL_VALUE_TYPE rv;
4977bab6 7503#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 7504 HOST_WIDE_INT val;
4977bab6 7505#endif
a260abc9
DE		 7506
7507 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7508 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7509
7510 operands[2] = gen_lowpart (DImode, operands[0]);
7511 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 7512#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 7513 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7514 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 7515
f5264b52 7516 operands[3] = gen_int_mode (val, DImode);
5b029315 7517#else
a260abc9 7518 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 7519#endif
a260abc9 7520}")
efc08378 7521
4eae5fe1 7522;; Don't have reload use general registers to load a constant. First,
1427100a 7523;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 7524;; a non-offsettable memref, but also it is less efficient than loading
7525;; the constant into an FP register, since it will probably be used there.
7526;; The "??" is a kludge until we can figure out a more reasonable way
7527;; of handling these non-offsettable values.
c4c40373 7528(define_insn "*movdf_hardfloat32"
914a7297
DE		 7529 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7530 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
a3170dc6 7531 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 7532 && (gpc_reg_operand (operands[0], DFmode)
7533 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 7534 "*
7535{
7536 switch (which_alternative)
7537 {
a260abc9 7538 default:
37409796 7539 gcc_unreachable ();
e7113111
RK		 7540 case 0:
7541 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 7542 the first register operand 0 is the same as the second register
7543 of operand 1, we must copy in the opposite order. */
e7113111 7544 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 7545 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 7546 else
deb9225a 7547 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 7548 case 1:
819e019c
EC		 7549 if (GET_CODE (operands[1]) == MEM
7550 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7551 reload_completed || reload_in_progress)
0c380712 7552 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[1], 0))
819e019c
EC		 7553 || GET_CODE (XEXP (operands[1], 0)) == REG
7554 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
0c380712 7555 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
819e019c 7556 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
000034eb
DE		 7557 {
7558 /* If the low-address word is used in the address, we must load
7559 it last. Otherwise, load it first. Note that we cannot have
7560 auto-increment in that case since the address register is
7561 known to be dead. */
7562 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7563 operands[1], 0))
7564 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7565 else
7566 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7567 }
e7113111 7568 else
000034eb
DE		 7569 {
7570 rtx addreg;
7571
000034eb
DE		 7572 addreg = find_addr_reg (XEXP (operands[1], 0));
7573 if (refers_to_regno_p (REGNO (operands[0]),
7574 REGNO (operands[0]) + 1,
7575 operands[1], 0))
7576 {
7577 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 7578 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
000034eb 7579 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2b97222d 7580 return \"{lx|lwzx} %0,%1\";
000034eb
DE		 7581 }
7582 else
7583 {
2b97222d 7584 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
000034eb 7585 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 7586 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
000034eb
DE		 7587 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7588 return \"\";
7589 }
7590 }
e7113111 7591 case 2:
819e019c
EC		 7592 if (GET_CODE (operands[0]) == MEM
7593 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7594 reload_completed || reload_in_progress)
0c380712 7595 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[0], 0))
819e019c
EC		 7596 || GET_CODE (XEXP (operands[0], 0)) == REG
7597 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
0c380712 7598 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
819e019c 7599 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
000034eb
DE		 7600 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7601 else
7602 {
7603 rtx addreg;
7604
000034eb 7605 addreg = find_addr_reg (XEXP (operands[0], 0));
2b97222d 7606 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
000034eb 7607 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 7608 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
000034eb
DE		 7609 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7610 return \"\";
7611 }
e7113111 7612 case 3:
914a7297 7613 return \"fmr %0,%1\";
e7113111 7614 case 4:
914a7297 7615 return \"lfd%U1%X1 %0,%1\";
e7113111 7616 case 5:
914a7297 7617 return \"stfd%U0%X0 %1,%0\";
e7113111 7618 case 6:
c4c40373 7619 case 7:
c4c40373 7620 case 8:
914a7297 7621 return \"#\";
e7113111
RK		 7622 }
7623}"
943c15ed 7624 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
914a7297 7625 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 7626
c4c40373 7627(define_insn "*movdf_softfloat32"
1427100a
DE		 7628 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7629 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7a2f7870 7630 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
52d3af72
DE		 7631 && (gpc_reg_operand (operands[0], DFmode)
7632 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 7633 "*
7634{
7635 switch (which_alternative)
7636 {
a260abc9 7637 default:
37409796 7638 gcc_unreachable ();
dc4f83ca
MM		 7639 case 0:
7640 /* We normally copy the low-numbered register first. However, if
7641 the first register operand 0 is the same as the second register of
7642 operand 1, we must copy in the opposite order. */
7643 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7644 return \"mr %L0,%L1\;mr %0,%1\";
7645 else
7646 return \"mr %0,%1\;mr %L0,%L1\";
7647 case 1:
3cb999d8
DE		 7648 /* If the low-address word is used in the address, we must load
7649 it last. Otherwise, load it first. Note that we cannot have
7650 auto-increment in that case since the address register is
7651 known to be dead. */
dc4f83ca 7652 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 7653 operands[1], 0))
dc4f83ca
MM		 7654 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7655 else
7656 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7657 case 2:
7658 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7659 case 3:
c4c40373
MM		 7660 case 4:
7661 case 5:
dc4f83ca
MM		 7662 return \"#\";
7663 }
7664}"
943c15ed 7665 [(set_attr "type" "two,load,store,*,*,*")
c4c40373 7666 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 7667
d2288d5d
HP		 7668; ld/std require word-aligned displacements -> 'Y' constraint.
7669; List Y->r and r->Y before r->r for reload.
c4c40373 7670(define_insn "*movdf_hardfloat64"
ae6669e7
DJ		 7671 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
7672 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
a3170dc6 7673 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 7674 && (gpc_reg_operand (operands[0], DFmode)
7675 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 7676 "@
96bb8ed3 7677 std%U0%X0 %1,%0
3364872d
FJ		 7678 ld%U1%X1 %0,%1
7679 mr %0,%1
3d5570cb 7680 fmr %0,%1
f63184ac 7681 lfd%U1%X1 %0,%1
914a7297
DE		 7682 stfd%U0%X0 %1,%0
7683 mt%0 %1
7684 mf%1 %0
e0740893 7685 {cror 0,0,0|nop}
914a7297
DE		 7686 #
7687 #
7688 #"
ae6669e7
DJ		 7689 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
7690 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 7691
c4c40373 7692(define_insn "*movdf_softfloat64"
d2288d5d
HP		 7693 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7694 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
a3170dc6 7695 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 7696 && (gpc_reg_operand (operands[0], DFmode)
7697 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca 7698 "@
d2288d5d
HP		 7699 ld%U1%X1 %0,%1
7700 std%U0%X0 %1,%0
dc4f83ca 7701 mr %0,%1
914a7297
DE		 7702 mt%0 %1
7703 mf%1 %0
c4c40373
MM		 7704 #
7705 #
e2d0915c 7706 #
e0740893 7707 {cror 0,0,0|nop}"
d2288d5d 7708 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
e2d0915c 7709 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 7710\f
06f4e019
DE		 7711(define_expand "movtf"
7712 [(set (match_operand:TF 0 "general_operand" "")
7713 (match_operand:TF 1 "any_operand" ""))]
39e63627
GK		 7714 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7715 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 7716 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7717
a9baceb1
GK		 7718; It's important to list the o->f and f->o moves before f->f because
7719; otherwise reload, given m->f, will try to pick f->f and reload it,
409f61cd 7720; which doesn't make progress. Likewise r->Y must be before r->r.
a9baceb1 7721(define_insn_and_split "*movtf_internal"
409f61cd
AM		 7722 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7723 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
39e63627
GK		 7724 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7725 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 7726 && (gpc_reg_operand (operands[0], TFmode)
7727 || gpc_reg_operand (operands[1], TFmode))"
a9baceb1 7728 "#"
ecb62ae7 7729 "&& reload_completed"
a9baceb1
GK		 7730 [(pc)]
7731{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
112ccb83 7732 [(set_attr "length" "8,8,8,20,20,16")])
06f4e019 7733
ecb62ae7
GK		 7734(define_expand "extenddftf2"
7735 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7736 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
7737 (use (match_dup 2))])]
39e63627
GK		 7738 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7739 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 7740{
ecb62ae7
GK		 7741 operands[2] = CONST0_RTX (DFmode);
7742})
06f4e019 7743
ecb62ae7
GK		 7744(define_insn_and_split "*extenddftf2_internal"
7745 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
7746 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
97c54d9a 7747 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
39e63627
GK		 7748 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7749 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 7750 "#"
7751 "&& reload_completed"
7752 [(pc)]
06f4e019 7753{
ecb62ae7
GK		 7754 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7755 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7756 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
7757 operands[1]);
7758 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
7759 operands[2]);
7760 DONE;
6ae08853 7761})
ecb62ae7
GK		 7762
7763(define_expand "extendsftf2"
7764 [(set (match_operand:TF 0 "nonimmediate_operand" "")
7765 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
7766 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7767 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7768{
7769 rtx tmp = gen_reg_rtx (DFmode);
7770 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
7771 emit_insn (gen_extenddftf2 (operands[0], tmp));
7772 DONE;
7773})
06f4e019 7774
8cb320b8 7775(define_expand "trunctfdf2"
589b3fda
DE		 7776 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7777 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
39e63627
GK		 7778 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7779 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
589b3fda 7780 "")
8cb320b8
DE		 7781
7782(define_insn_and_split "trunctfdf2_internal1"
7783 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
7784 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
7785 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
7786 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7787 "@
7788 #
7789 fmr %0,%1"
7790 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
7791 [(const_int 0)]
7792{
7793 emit_note (NOTE_INSN_DELETED);
7794 DONE;
7795}
7796 [(set_attr "type" "fp")])
7797
7798(define_insn "trunctfdf2_internal2"
7799 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7800 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7801 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
7802 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 7803 "fadd %0,%1,%L1"
8cb320b8 7804 [(set_attr "type" "fp")])
06f4e019
DE		 7805
7806(define_insn_and_split "trunctfsf2"
7807 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 7808 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
7809 (clobber (match_scratch:DF 2 "=f"))]
39e63627
GK		 7810 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7811 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 7812 "#"
ea112fc4 7813 "&& reload_completed"
06f4e019
DE		 7814 [(set (match_dup 2)
7815 (float_truncate:DF (match_dup 1)))
7816 (set (match_dup 0)
7817 (float_truncate:SF (match_dup 2)))]
ea112fc4 7818 "")
06f4e019 7819
0c90aa3c 7820(define_expand "floatsitf2"
ea112fc4 7821 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
0c90aa3c 7822 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
39e63627
GK		 7823 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7824 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
0c90aa3c
GK		 7825{
7826 rtx tmp = gen_reg_rtx (DFmode);
7827 expand_float (tmp, operands[1], false);
7828 emit_insn (gen_extenddftf2 (operands[0], tmp));
7829 DONE;
7830})
06f4e019 7831
ecb62ae7
GK		 7832; fadd, but rounding towards zero.
7833; This is probably not the optimal code sequence.
7834(define_insn "fix_trunc_helper"
7835 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7836 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
7837 UNSPEC_FIX_TRUNC_TF))
7838 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
7839 "TARGET_HARD_FLOAT && TARGET_FPRS"
7840 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
7841 [(set_attr "type" "fp")
7842 (set_attr "length" "20")])
7843
0c90aa3c 7844(define_expand "fix_trunctfsi2"
ecb62ae7
GK		 7845 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
7846 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
7847 (clobber (match_dup 2))
7848 (clobber (match_dup 3))
7849 (clobber (match_dup 4))
7850 (clobber (match_dup 5))])]
7851 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7852 && (TARGET_POWER2 || TARGET_POWERPC)
7853 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7854{
7855 operands[2] = gen_reg_rtx (DFmode);
7856 operands[3] = gen_reg_rtx (DFmode);
7857 operands[4] = gen_reg_rtx (DImode);
7858 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
7859})
7860
7861(define_insn_and_split "*fix_trunctfsi2_internal"
61c07d3c 7862 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
ecb62ae7
GK		 7863 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
7864 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
7865 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
7866 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
7867 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
39e63627
GK		 7868 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7869 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 7870 "#"
230215f5 7871 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
ecb62ae7 7872 [(pc)]
0c90aa3c 7873{
ecb62ae7
GK		 7874 rtx lowword;
7875 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
7876
230215f5
GK		 7877 gcc_assert (MEM_P (operands[5]));
7878 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
ecb62ae7
GK		 7879
7880 emit_insn (gen_fctiwz (operands[4], operands[2]));
7881 emit_move_insn (operands[5], operands[4]);
230215f5 7882 emit_move_insn (operands[0], lowword);
0c90aa3c
GK		 7883 DONE;
7884})
06f4e019
DE		 7885
7886(define_insn "negtf2"
7887 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7888 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
39e63627
GK		 7889 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7890 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 7891 "*
7892{
7893 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7894 return \"fneg %L0,%L1\;fneg %0,%1\";
7895 else
7896 return \"fneg %0,%1\;fneg %L0,%L1\";
7897}"
7898 [(set_attr "type" "fp")
7899 (set_attr "length" "8")])
7900
1a402dc1 7901(define_expand "abstf2"
06f4e019
DE		 7902 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7903 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
39e63627
GK		 7904 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7905 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
1a402dc1 7906 "
06f4e019 7907{
1a402dc1
AM		 7908 rtx label = gen_label_rtx ();
7909 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
7910 emit_label (label);
7911 DONE;
7912}")
06f4e019 7913
1a402dc1 7914(define_expand "abstf2_internal"
06f4e019 7915 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
1a402dc1
AM		 7916 (match_operand:TF 1 "gpc_reg_operand" "f"))
7917 (set (match_dup 3) (match_dup 5))
7918 (set (match_dup 5) (abs:DF (match_dup 5)))
7919 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
7920 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
7921 (label_ref (match_operand 2 "" ""))
7922 (pc)))
7923 (set (match_dup 6) (neg:DF (match_dup 6)))]
39e63627
GK		 7924 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7925 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
1a402dc1 7926 "
06f4e019 7927{
1a402dc1
AM		 7928 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7929 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7930 operands[3] = gen_reg_rtx (DFmode);
7931 operands[4] = gen_reg_rtx (CCFPmode);
7932 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
7933 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
7934}")
06f4e019 7935\f
1fd4e8c1
RK		 7936;; Next come the multi-word integer load and store and the load and store
7937;; multiple insns.
1fd4e8c1 7938
112ccb83
GK		 7939; List r->r after r->"o<>", otherwise reload will try to reload a
7940; non-offsettable address by using r->r which won't make progress.
acad7ed3 7941(define_insn "*movdi_internal32"
343f6bbf 7942 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
112ccb83 7943 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
a260abc9 7944 "! TARGET_POWERPC64
4e74d8ec
MM		 7945 && (gpc_reg_operand (operands[0], DImode)
7946 || gpc_reg_operand (operands[1], DImode))"
112ccb83
GK		 7947 "@
7948 #
7949 #
7950 #
7951 fmr %0,%1
7952 lfd%U1%X1 %0,%1
7953 stfd%U0%X0 %1,%0
7954 #"
7955 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
4e74d8ec
MM		 7956
7957(define_split
7958 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7959 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 7960 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 7961 [(set (match_dup 2) (match_dup 4))
7962 (set (match_dup 3) (match_dup 1))]
7963 "
7964{
5f59ecb7 7965 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 7966 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7967 DImode);
7968 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7969 DImode);
75d39459 7970#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 7971 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 7972#else
5f59ecb7 7973 operands[4] = GEN_INT (value >> 32);
a65c591c 7974 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 7975#endif
4e74d8ec
MM		 7976}")
7977
3a1f863f
DE		 7978(define_split
7979 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7980 (match_operand:DI 1 "input_operand" ""))]
6ae08853 7981 "reload_completed && !TARGET_POWERPC64
3a1f863f 7982 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 7983 [(pc)]
7984{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
3a1f863f 7985
acad7ed3 7986(define_insn "*movdi_internal64"
343f6bbf 7987 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9615f239 7988 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
a260abc9 7989 "TARGET_POWERPC64
4e74d8ec
MM		 7990 && (gpc_reg_operand (operands[0], DImode)
7991 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 7992 "@
3d5570cb
RK		 7993 mr %0,%1
7994 ld%U1%X1 %0,%1
96bb8ed3 7995 std%U0%X0 %1,%0
3d5570cb 7996 li %0,%1
802a0058 7997 lis %0,%v1
e6ca2c17 7998 #
aee86b38 7999 {cal|la} %0,%a1
3d5570cb
RK		 8000 fmr %0,%1
8001 lfd%U1%X1 %0,%1
8002 stfd%U0%X0 %1,%0
8003 mf%1 %0
08075ead 8004 mt%0 %1
e34eaae5 8005 {cror 0,0,0|nop}"
02ca7595 8006 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 8007 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8008
5f59ecb7 8009;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 8010(define_insn ""
8011 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8012 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 8013 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8014 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 8015 && num_insns_constant (operands[1], DImode) == 1"
8016 "*
8017{
8018 return ((unsigned HOST_WIDE_INT)
8019 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8020 ? \"li %0,%1\" : \"lis %0,%v1\";
8021}")
8022
a260abc9
DE		 8023;; Generate all one-bits and clear left or right.
8024;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8025(define_split
8026 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4ae234b0 8027 (match_operand:DI 1 "mask_operand" ""))]
a260abc9
DE		 8028 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8029 [(set (match_dup 0) (const_int -1))
e6ca2c17 8030 (set (match_dup 0)
a260abc9
DE		 8031 (and:DI (rotate:DI (match_dup 0)
8032 (const_int 0))
8033 (match_dup 1)))]
8034 "")
8035
8036;; Split a load of a large constant into the appropriate five-instruction
8037;; sequence. Handle anything in a constant number of insns.
8038;; When non-easy constants can go in the TOC, this should use
8039;; easy_fp_constant predicate.
8040(define_split
8041 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 8042 (match_operand:DI 1 "const_int_operand" ""))]
8043 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8044 [(set (match_dup 0) (match_dup 2))
8045 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 8046 "
2bfcf297
DB		 8047{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8048
8049 if (tem == operands[0])
8050 DONE;
e8d791dd 8051 else
2bfcf297 8052 FAIL;
5f59ecb7 8053}")
e6ca2c17 8054
5f59ecb7
DE		 8055(define_split
8056 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 8057 (match_operand:DI 1 "const_double_operand" ""))]
8058 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8059 [(set (match_dup 0) (match_dup 2))
8060 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 8061 "
2bfcf297
DB		 8062{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8063
8064 if (tem == operands[0])
8065 DONE;
8066 else
8067 FAIL;
e6ca2c17 8068}")
acad7ed3 8069\f
1fd4e8c1
RK		 8070;; TImode is similar, except that we usually want to compute the address into
8071;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 8072;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 8073
8074;; We say that MQ is clobbered in the last alternative because the first
8075;; alternative would never get used otherwise since it would need a reload
8076;; while the 2nd alternative would not. We put memory cases first so they
8077;; are preferred. Otherwise, we'd try to reload the output instead of
8078;; giving the SCRATCH mq.
3a1f863f 8079
a260abc9 8080(define_insn "*movti_power"
7f514158
AM		 8081 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8082 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8083 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
6ae08853 8084 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 8085 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 8086 "*
8087{
8088 switch (which_alternative)
8089 {
dc4f83ca 8090 default:
37409796 8091 gcc_unreachable ();
dc4f83ca 8092
1fd4e8c1 8093 case 0:
3a1f863f
DE		 8094 if (TARGET_STRING)
8095 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 8096 case 1:
1fd4e8c1 8097 case 2:
3a1f863f 8098 return \"#\";
1fd4e8c1
RK		 8099 case 3:
8100 /* If the address is not used in the output, we can use lsi. Otherwise,
8101 fall through to generating four loads. */
e876481c
DE		 8102 if (TARGET_STRING
8103 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 8104 return \"{lsi|lswi} %0,%P1,16\";
82e41834 8105 /* ... fall through ... */
1fd4e8c1 8106 case 4:
7f514158 8107 case 5:
3a1f863f 8108 return \"#\";
1fd4e8c1
RK		 8109 }
8110}"
7f514158 8111 [(set_attr "type" "store,store,*,load,load,*")])
51b8fc2c 8112
a260abc9 8113(define_insn "*movti_string"
7f514158
AM		 8114 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8115 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
3a1f863f 8116 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 8117 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8118 "*
8119{
8120 switch (which_alternative)
8121 {
8122 default:
37409796 8123 gcc_unreachable ();
dc4f83ca 8124 case 0:
3a1f863f
DE		 8125 if (TARGET_STRING)
8126 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 8127 case 1:
cd1d3445 8128 case 2:
3a1f863f 8129 return \"#\";
cd1d3445
DE		 8130 case 3:
8131 /* If the address is not used in the output, we can use lsi. Otherwise,
8132 fall through to generating four loads. */
6ae08853 8133 if (TARGET_STRING
3a1f863f 8134 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 8135 return \"{lsi|lswi} %0,%P1,16\";
8136 /* ... fall through ... */
8137 case 4:
7f514158 8138 case 5:
3a1f863f 8139 return \"#\";
dc4f83ca
MM		 8140 }
8141}"
7f514158 8142 [(set_attr "type" "store,store,*,load,load,*")])
dc4f83ca 8143
a260abc9 8144(define_insn "*movti_ppc64"
112ccb83
GK		 8145 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8146 (match_operand:TI 1 "input_operand" "r,r,m"))]
51b8fc2c
RK		 8147 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8148 || gpc_reg_operand (operands[1], TImode))"
112ccb83 8149 "#"
3a1f863f
DE		 8150 [(set_attr "type" "*,load,store")])
8151
7f514158
AM		 8152(define_split
8153 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8154 (match_operand:TI 1 "const_double_operand" ""))]
8155 "TARGET_POWERPC64"
8156 [(set (match_dup 2) (match_dup 4))
8157 (set (match_dup 3) (match_dup 5))]
8158 "
8159{
8160 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8161 TImode);
8162 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8163 TImode);
8164 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8165 {
8166 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8167 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8168 }
8169 else if (GET_CODE (operands[1]) == CONST_INT)
8170 {
8171 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8172 operands[5] = operands[1];
8173 }
8174 else
8175 FAIL;
8176}")
8177
3a1f863f
DE		 8178(define_split
8179 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8180 (match_operand:TI 1 "input_operand" ""))]
a9baceb1 8181 "reload_completed
3a1f863f 8182 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 8183 [(pc)]
8184{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
1fd4e8c1
RK		 8185\f
8186(define_expand "load_multiple"
2f622005
RK		 8187 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8188 (match_operand:SI 1 "" ""))
8189 (use (match_operand:SI 2 "" ""))])]
09a625f7 8190 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 8191 "
8192{
8193 int regno;
8194 int count;
792760b9 8195 rtx op1;
1fd4e8c1
RK		 8196 int i;
8197
8198 /* Support only loading a constant number of fixed-point registers from
8199 memory and only bother with this if more than two; the machine
8200 doesn't support more than eight. */
8201 if (GET_CODE (operands[2]) != CONST_INT
8202 || INTVAL (operands[2]) <= 2
8203 || INTVAL (operands[2]) > 8
8204 || GET_CODE (operands[1]) != MEM
8205 || GET_CODE (operands[0]) != REG
8206 || REGNO (operands[0]) >= 32)
8207 FAIL;
8208
8209 count = INTVAL (operands[2]);
8210 regno = REGNO (operands[0]);
8211
39403d82 8212 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 8213 op1 = replace_equiv_address (operands[1],
8214 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 8215
8216 for (i = 0; i < count; i++)
8217 XVECEXP (operands[3], 0, i)
39403d82 8218 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 8219 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 8220}")
8221
9caa3eb2 8222(define_insn "*ldmsi8"
1fd4e8c1 8223 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 8224 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8225 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8226 (set (match_operand:SI 3 "gpc_reg_operand" "")
8227 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8228 (set (match_operand:SI 4 "gpc_reg_operand" "")
8229 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8230 (set (match_operand:SI 5 "gpc_reg_operand" "")
8231 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8232 (set (match_operand:SI 6 "gpc_reg_operand" "")
8233 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8234 (set (match_operand:SI 7 "gpc_reg_operand" "")
8235 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8236 (set (match_operand:SI 8 "gpc_reg_operand" "")
8237 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8238 (set (match_operand:SI 9 "gpc_reg_operand" "")
8239 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8240 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 8241 "*
9caa3eb2
DE		 8242{ return rs6000_output_load_multiple (operands); }"
8243 [(set_attr "type" "load")
8244 (set_attr "length" "32")])
1fd4e8c1 8245
9caa3eb2
DE		 8246(define_insn "*ldmsi7"
8247 [(match_parallel 0 "load_multiple_operation"
8248 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8249 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8250 (set (match_operand:SI 3 "gpc_reg_operand" "")
8251 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8252 (set (match_operand:SI 4 "gpc_reg_operand" "")
8253 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8254 (set (match_operand:SI 5 "gpc_reg_operand" "")
8255 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8256 (set (match_operand:SI 6 "gpc_reg_operand" "")
8257 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8258 (set (match_operand:SI 7 "gpc_reg_operand" "")
8259 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8260 (set (match_operand:SI 8 "gpc_reg_operand" "")
8261 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8262 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8263 "*
8264{ return rs6000_output_load_multiple (operands); }"
8265 [(set_attr "type" "load")
8266 (set_attr "length" "32")])
8267
8268(define_insn "*ldmsi6"
8269 [(match_parallel 0 "load_multiple_operation"
8270 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8271 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8272 (set (match_operand:SI 3 "gpc_reg_operand" "")
8273 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8274 (set (match_operand:SI 4 "gpc_reg_operand" "")
8275 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8276 (set (match_operand:SI 5 "gpc_reg_operand" "")
8277 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8278 (set (match_operand:SI 6 "gpc_reg_operand" "")
8279 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8280 (set (match_operand:SI 7 "gpc_reg_operand" "")
8281 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8282 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8283 "*
8284{ return rs6000_output_load_multiple (operands); }"
8285 [(set_attr "type" "load")
8286 (set_attr "length" "32")])
8287
8288(define_insn "*ldmsi5"
8289 [(match_parallel 0 "load_multiple_operation"
8290 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8291 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8292 (set (match_operand:SI 3 "gpc_reg_operand" "")
8293 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8294 (set (match_operand:SI 4 "gpc_reg_operand" "")
8295 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8296 (set (match_operand:SI 5 "gpc_reg_operand" "")
8297 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8298 (set (match_operand:SI 6 "gpc_reg_operand" "")
8299 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8300 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8301 "*
8302{ return rs6000_output_load_multiple (operands); }"
8303 [(set_attr "type" "load")
8304 (set_attr "length" "32")])
8305
8306(define_insn "*ldmsi4"
8307 [(match_parallel 0 "load_multiple_operation"
8308 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8309 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8310 (set (match_operand:SI 3 "gpc_reg_operand" "")
8311 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8312 (set (match_operand:SI 4 "gpc_reg_operand" "")
8313 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8314 (set (match_operand:SI 5 "gpc_reg_operand" "")
8315 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8316 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8317 "*
8318{ return rs6000_output_load_multiple (operands); }"
8319 [(set_attr "type" "load")
8320 (set_attr "length" "32")])
8321
8322(define_insn "*ldmsi3"
8323 [(match_parallel 0 "load_multiple_operation"
8324 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8325 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8326 (set (match_operand:SI 3 "gpc_reg_operand" "")
8327 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8328 (set (match_operand:SI 4 "gpc_reg_operand" "")
8329 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8330 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8331 "*
8332{ return rs6000_output_load_multiple (operands); }"
b19003d8 8333 [(set_attr "type" "load")
e82ee4cc 8334 (set_attr "length" "32")])
b19003d8 8335
1fd4e8c1 8336(define_expand "store_multiple"
2f622005
RK		 8337 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8338 (match_operand:SI 1 "" ""))
8339 (clobber (scratch:SI))
8340 (use (match_operand:SI 2 "" ""))])]
09a625f7 8341 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 8342 "
8343{
8344 int regno;
8345 int count;
8346 rtx to;
792760b9 8347 rtx op0;
1fd4e8c1
RK		 8348 int i;
8349
8350 /* Support only storing a constant number of fixed-point registers to
8351 memory and only bother with this if more than two; the machine
8352 doesn't support more than eight. */
8353 if (GET_CODE (operands[2]) != CONST_INT
8354 || INTVAL (operands[2]) <= 2
8355 || INTVAL (operands[2]) > 8
8356 || GET_CODE (operands[0]) != MEM
8357 || GET_CODE (operands[1]) != REG
8358 || REGNO (operands[1]) >= 32)
8359 FAIL;
8360
8361 count = INTVAL (operands[2]);
8362 regno = REGNO (operands[1]);
8363
39403d82 8364 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 8365 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 8366 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 8367
8368 XVECEXP (operands[3], 0, 0)
7ef788f0 8369 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 8370 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 8371 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 8372
8373 for (i = 1; i < count; i++)
8374 XVECEXP (operands[3], 0, i + 1)
39403d82 8375 = gen_rtx_SET (VOIDmode,
7ef788f0 8376 adjust_address_nv (op0, SImode, i * 4),
c5c76735 8377 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 8378}")
8379
9caa3eb2 8380(define_insn "*store_multiple_power"
1fd4e8c1
RK		 8381 [(match_parallel 0 "store_multiple_operation"
8382 [(set (match_operand:SI 1 "indirect_operand" "=Q")
cd2b37d9 8383 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 8384 (clobber (match_scratch:SI 3 "=q"))])]
7e69e155 8385 "TARGET_STRING && TARGET_POWER"
b7ff3d82
DE		 8386 "{stsi|stswi} %2,%P1,%O0"
8387 [(set_attr "type" "store")])
d14a6d05 8388
e46e3130 8389(define_insn "*stmsi8"
d14a6d05 8390 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 8391 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8392 (match_operand:SI 2 "gpc_reg_operand" "r"))
8393 (clobber (match_scratch:SI 3 "X"))
8394 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8395 (match_operand:SI 4 "gpc_reg_operand" "r"))
8396 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8397 (match_operand:SI 5 "gpc_reg_operand" "r"))
8398 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8399 (match_operand:SI 6 "gpc_reg_operand" "r"))
8400 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8401 (match_operand:SI 7 "gpc_reg_operand" "r"))
8402 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8403 (match_operand:SI 8 "gpc_reg_operand" "r"))
8404 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8405 (match_operand:SI 9 "gpc_reg_operand" "r"))
8406 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8407 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8408 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8409 "{stsi|stswi} %2,%1,%O0"
8410 [(set_attr "type" "store")])
8411
8412(define_insn "*stmsi7"
8413 [(match_parallel 0 "store_multiple_operation"
8414 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8415 (match_operand:SI 2 "gpc_reg_operand" "r"))
8416 (clobber (match_scratch:SI 3 "X"))
8417 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8418 (match_operand:SI 4 "gpc_reg_operand" "r"))
8419 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8420 (match_operand:SI 5 "gpc_reg_operand" "r"))
8421 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8422 (match_operand:SI 6 "gpc_reg_operand" "r"))
8423 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8424 (match_operand:SI 7 "gpc_reg_operand" "r"))
8425 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8426 (match_operand:SI 8 "gpc_reg_operand" "r"))
8427 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8428 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8429 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8430 "{stsi|stswi} %2,%1,%O0"
8431 [(set_attr "type" "store")])
8432
8433(define_insn "*stmsi6"
8434 [(match_parallel 0 "store_multiple_operation"
8435 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8436 (match_operand:SI 2 "gpc_reg_operand" "r"))
8437 (clobber (match_scratch:SI 3 "X"))
8438 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8439 (match_operand:SI 4 "gpc_reg_operand" "r"))
8440 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8441 (match_operand:SI 5 "gpc_reg_operand" "r"))
8442 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8443 (match_operand:SI 6 "gpc_reg_operand" "r"))
8444 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8445 (match_operand:SI 7 "gpc_reg_operand" "r"))
8446 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8447 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8448 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8449 "{stsi|stswi} %2,%1,%O0"
8450 [(set_attr "type" "store")])
8451
8452(define_insn "*stmsi5"
8453 [(match_parallel 0 "store_multiple_operation"
8454 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8455 (match_operand:SI 2 "gpc_reg_operand" "r"))
8456 (clobber (match_scratch:SI 3 "X"))
8457 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8458 (match_operand:SI 4 "gpc_reg_operand" "r"))
8459 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8460 (match_operand:SI 5 "gpc_reg_operand" "r"))
8461 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8462 (match_operand:SI 6 "gpc_reg_operand" "r"))
8463 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8464 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8465 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8466 "{stsi|stswi} %2,%1,%O0"
8467 [(set_attr "type" "store")])
8468
8469(define_insn "*stmsi4"
8470 [(match_parallel 0 "store_multiple_operation"
8471 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8472 (match_operand:SI 2 "gpc_reg_operand" "r"))
8473 (clobber (match_scratch:SI 3 "X"))
8474 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8475 (match_operand:SI 4 "gpc_reg_operand" "r"))
8476 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8477 (match_operand:SI 5 "gpc_reg_operand" "r"))
8478 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8479 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8480 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82
DE		 8481 "{stsi|stswi} %2,%1,%O0"
8482 [(set_attr "type" "store")])
7e69e155 8483
e46e3130
DJ		 8484(define_insn "*stmsi3"
8485 [(match_parallel 0 "store_multiple_operation"
8486 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8487 (match_operand:SI 2 "gpc_reg_operand" "r"))
8488 (clobber (match_scratch:SI 3 "X"))
8489 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8490 (match_operand:SI 4 "gpc_reg_operand" "r"))
8491 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8492 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8493 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8494 "{stsi|stswi} %2,%1,%O0"
8495 [(set_attr "type" "store")])
7e69e155 8496\f
57e84f18 8497(define_expand "setmemsi"
fba73eb1 8498 [(parallel [(set (match_operand:BLK 0 "" "")
98843c92 8499 (match_operand 2 "const_int_operand" ""))
fba73eb1 8500 (use (match_operand:SI 1 "" ""))
57e84f18 8501 (use (match_operand:SI 3 "" ""))])]
fba73eb1
DE		 8502 ""
8503 "
8504{
57e84f18 8505 /* If value to set is not zero, use the library routine. */
a05be2e0 8506 if (operands[2] != const0_rtx)
57e84f18
AS		 8507 FAIL;
8508
fba73eb1
DE		 8509 if (expand_block_clear (operands))
8510 DONE;
8511 else
8512 FAIL;
8513}")
8514
7e69e155
MM		 8515;; String/block move insn.
8516;; Argument 0 is the destination
8517;; Argument 1 is the source
8518;; Argument 2 is the length
8519;; Argument 3 is the alignment
8520
70128ad9 8521(define_expand "movmemsi"
b6c9286a
MM		 8522 [(parallel [(set (match_operand:BLK 0 "" "")
8523 (match_operand:BLK 1 "" ""))
8524 (use (match_operand:SI 2 "" ""))
8525 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 8526 ""
8527 "
8528{
8529 if (expand_block_move (operands))
8530 DONE;
8531 else
8532 FAIL;
8533}")
8534
8535;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 8536;; register allocator doesn't have a clue about allocating 8 word registers.
8537;; rD/rS = r5 is preferred, efficient form.
70128ad9 8538(define_expand "movmemsi_8reg"
b6c9286a
MM		 8539 [(parallel [(set (match_operand 0 "" "")
8540 (match_operand 1 "" ""))
8541 (use (match_operand 2 "" ""))
8542 (use (match_operand 3 "" ""))
7e69e155
MM		 8543 (clobber (reg:SI 5))
8544 (clobber (reg:SI 6))
8545 (clobber (reg:SI 7))
8546 (clobber (reg:SI 8))
8547 (clobber (reg:SI 9))
8548 (clobber (reg:SI 10))
8549 (clobber (reg:SI 11))
8550 (clobber (reg:SI 12))
3c67b673 8551 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 8552 "TARGET_STRING"
8553 "")
8554
8555(define_insn ""
52d3af72
DE		 8556 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8557 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 8558 (use (match_operand:SI 2 "immediate_operand" "i"))
8559 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 8560 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 8561 (clobber (reg:SI 6))
8562 (clobber (reg:SI 7))
8563 (clobber (reg:SI 8))
8564 (clobber (reg:SI 9))
8565 (clobber (reg:SI 10))
8566 (clobber (reg:SI 11))
8567 (clobber (reg:SI 12))
3c67b673 8568 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 8569 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 8570 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8571 || INTVAL (operands[2]) == 0)
7e69e155
MM		 8572 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8573 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 8574 && REGNO (operands[4]) == 5"
8575 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 8576 [(set_attr "type" "load")
8577 (set_attr "length" "8")])
7e69e155
MM		 8578
8579(define_insn ""
4ae234b0
GK		 8580 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8581 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 8582 (use (match_operand:SI 2 "immediate_operand" "i"))
8583 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 8584 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 8585 (clobber (reg:SI 6))
8586 (clobber (reg:SI 7))
8587 (clobber (reg:SI 8))
8588 (clobber (reg:SI 9))
8589 (clobber (reg:SI 10))
8590 (clobber (reg:SI 11))
8591 (clobber (reg:SI 12))
3c67b673 8592 (clobber (match_scratch:SI 5 "X"))]
0ad91047 8593 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 8594 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8595 || INTVAL (operands[2]) == 0)
7e69e155
MM		 8596 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8597 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 8598 && REGNO (operands[4]) == 5"
8599 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 8600 [(set_attr "type" "load")
8601 (set_attr "length" "8")])
7e69e155
MM		 8602
8603;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 8604;; register allocator doesn't have a clue about allocating 6 word registers.
8605;; rD/rS = r5 is preferred, efficient form.
70128ad9 8606(define_expand "movmemsi_6reg"
b6c9286a
MM		 8607 [(parallel [(set (match_operand 0 "" "")
8608 (match_operand 1 "" ""))
8609 (use (match_operand 2 "" ""))
8610 (use (match_operand 3 "" ""))
f9562f27
DE		 8611 (clobber (reg:SI 5))
8612 (clobber (reg:SI 6))
7e69e155
MM		 8613 (clobber (reg:SI 7))
8614 (clobber (reg:SI 8))
8615 (clobber (reg:SI 9))
8616 (clobber (reg:SI 10))
3c67b673 8617 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 8618 "TARGET_STRING"
8619 "")
8620
8621(define_insn ""
52d3af72
DE		 8622 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8623 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 8624 (use (match_operand:SI 2 "immediate_operand" "i"))
8625 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 8626 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 8627 (clobber (reg:SI 6))
8628 (clobber (reg:SI 7))
7e69e155
MM		 8629 (clobber (reg:SI 8))
8630 (clobber (reg:SI 9))
8631 (clobber (reg:SI 10))
3c67b673 8632 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 8633 "TARGET_STRING && TARGET_POWER
8634 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 8635 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8636 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8637 && REGNO (operands[4]) == 5"
3c67b673 8638 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 8639 [(set_attr "type" "load")
8640 (set_attr "length" "8")])
7e69e155
MM		 8641
8642(define_insn ""
4ae234b0
GK		 8643 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8644 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 8645 (use (match_operand:SI 2 "immediate_operand" "i"))
8646 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 8647 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 8648 (clobber (reg:SI 6))
8649 (clobber (reg:SI 7))
7e69e155
MM		 8650 (clobber (reg:SI 8))
8651 (clobber (reg:SI 9))
8652 (clobber (reg:SI 10))
3c67b673 8653 (clobber (match_scratch:SI 5 "X"))]
0ad91047 8654 "TARGET_STRING && ! TARGET_POWER
7e69e155 8655 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 8656 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8657 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8658 && REGNO (operands[4]) == 5"
3c67b673 8659 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 8660 [(set_attr "type" "load")
8661 (set_attr "length" "8")])
7e69e155 8662
f9562f27
DE		 8663;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8664;; problems with TImode.
8665;; rD/rS = r5 is preferred, efficient form.
70128ad9 8666(define_expand "movmemsi_4reg"
b6c9286a
MM		 8667 [(parallel [(set (match_operand 0 "" "")
8668 (match_operand 1 "" ""))
8669 (use (match_operand 2 "" ""))
8670 (use (match_operand 3 "" ""))
f9562f27
DE		 8671 (clobber (reg:SI 5))
8672 (clobber (reg:SI 6))
8673 (clobber (reg:SI 7))
8674 (clobber (reg:SI 8))
3c67b673 8675 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 8676 "TARGET_STRING"
8677 "")
8678
8679(define_insn ""
52d3af72
DE		 8680 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8681 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 8682 (use (match_operand:SI 2 "immediate_operand" "i"))
8683 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 8684 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 8685 (clobber (reg:SI 6))
8686 (clobber (reg:SI 7))
8687 (clobber (reg:SI 8))
3c67b673 8688 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 8689 "TARGET_STRING && TARGET_POWER
8690 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 8691 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8692 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8693 && REGNO (operands[4]) == 5"
3c67b673 8694 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 8695 [(set_attr "type" "load")
8696 (set_attr "length" "8")])
7e69e155
MM		 8697
8698(define_insn ""
4ae234b0
GK		 8699 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8700 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 8701 (use (match_operand:SI 2 "immediate_operand" "i"))
8702 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 8703 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 8704 (clobber (reg:SI 6))
8705 (clobber (reg:SI 7))
8706 (clobber (reg:SI 8))
3c67b673 8707 (clobber (match_scratch:SI 5 "X"))]
0ad91047 8708 "TARGET_STRING && ! TARGET_POWER
7e69e155 8709 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 8710 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8711 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8712 && REGNO (operands[4]) == 5"
3c67b673 8713 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 8714 [(set_attr "type" "load")
8715 (set_attr "length" "8")])
7e69e155
MM		 8716
8717;; Move up to 8 bytes at a time.
70128ad9 8718(define_expand "movmemsi_2reg"
b6c9286a
MM		 8719 [(parallel [(set (match_operand 0 "" "")
8720 (match_operand 1 "" ""))
8721 (use (match_operand 2 "" ""))
8722 (use (match_operand 3 "" ""))
3c67b673
RK		 8723 (clobber (match_scratch:DI 4 ""))
8724 (clobber (match_scratch:SI 5 ""))])]
f9562f27 8725 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 8726 "")
8727
8728(define_insn ""
52d3af72
DE		 8729 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8730 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 8731 (use (match_operand:SI 2 "immediate_operand" "i"))
8732 (use (match_operand:SI 3 "immediate_operand" "i"))
8733 (clobber (match_scratch:DI 4 "=&r"))
8734 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 8735 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 8736 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8737 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 8738 [(set_attr "type" "load")
8739 (set_attr "length" "8")])
7e69e155
MM		 8740
8741(define_insn ""
52d3af72
DE		 8742 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8743 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 8744 (use (match_operand:SI 2 "immediate_operand" "i"))
8745 (use (match_operand:SI 3 "immediate_operand" "i"))
8746 (clobber (match_scratch:DI 4 "=&r"))
8747 (clobber (match_scratch:SI 5 "X"))]
f9562f27 8748 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 8749 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 8750 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 8751 [(set_attr "type" "load")
8752 (set_attr "length" "8")])
7e69e155
MM		 8753
8754;; Move up to 4 bytes at a time.
70128ad9 8755(define_expand "movmemsi_1reg"
b6c9286a
MM		 8756 [(parallel [(set (match_operand 0 "" "")
8757 (match_operand 1 "" ""))
8758 (use (match_operand 2 "" ""))
8759 (use (match_operand 3 "" ""))
3c67b673
RK		 8760 (clobber (match_scratch:SI 4 ""))
8761 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 8762 "TARGET_STRING"
8763 "")
8764
8765(define_insn ""
52d3af72
DE		 8766 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8767 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 8768 (use (match_operand:SI 2 "immediate_operand" "i"))
8769 (use (match_operand:SI 3 "immediate_operand" "i"))
8770 (clobber (match_scratch:SI 4 "=&r"))
8771 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 8772 "TARGET_STRING && TARGET_POWER
8773 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 8774 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 8775 [(set_attr "type" "load")
8776 (set_attr "length" "8")])
7e69e155
MM		 8777
8778(define_insn ""
4ae234b0
GK		 8779 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8780 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 8781 (use (match_operand:SI 2 "immediate_operand" "i"))
8782 (use (match_operand:SI 3 "immediate_operand" "i"))
8783 (clobber (match_scratch:SI 4 "=&r"))
8784 (clobber (match_scratch:SI 5 "X"))]
0ad91047 8785 "TARGET_STRING && ! TARGET_POWER
7e69e155 8786 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7
TR		 8787 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8788 [(set_attr "type" "load")
8789 (set_attr "length" "8")])
1fd4e8c1 8790\f
7e69e155 8791;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 8792;; get by using pre-decrement or pre-increment, but the hardware can also
8793;; do cases where the increment is not the size of the object.
8794;;
8795;; In all these cases, we use operands 0 and 1 for the register being
8796;; incremented because those are the operands that local-alloc will
8797;; tie and these are the pair most likely to be tieable (and the ones
8798;; that will benefit the most).
8799
38c1f2d7 8800(define_insn "*movdi_update1"
51b8fc2c 8801 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 8802 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 8803 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 8804 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8805 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 8806 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 8807 "@
8808 ldux %3,%0,%2
8809 ldu %3,%2(%0)"
b54cf83a 8810 [(set_attr "type" "load_ux,load_u")])
287f13ff 8811
2e6c9641
FJ		 8812(define_insn "movdi_<mode>_update"
8813 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
8814 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c 8815 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
2e6c9641
FJ		 8816 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
8817 (plus:P (match_dup 1) (match_dup 2)))]
38c1f2d7 8818 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 8819 "@
8820 stdux %3,%0,%2
b7ff3d82 8821 stdu %3,%2(%0)"
b54cf83a 8822 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 8823
38c1f2d7 8824(define_insn "*movsi_update1"
cd2b37d9
RK		 8825 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8826 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8827 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 8828 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8829 (plus:SI (match_dup 1) (match_dup 2)))]
f7b3ab8a 8830 "TARGET_UPDATE"
1fd4e8c1 8831 "@
ca7f5001
RK		 8832 {lux|lwzux} %3,%0,%2
8833 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 8834 [(set_attr "type" "load_ux,load_u")])
8835
8836(define_insn "*movsi_update2"
8837 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8838 (sign_extend:DI
8839 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8840 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8841 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8842 (plus:DI (match_dup 1) (match_dup 2)))]
8843 "TARGET_POWERPC64"
8844 "lwaux %3,%0,%2"
8845 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 8846
4697a36c 8847(define_insn "movsi_update"
cd2b37d9 8848 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8849 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 8850 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8851 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8852 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 8853 "TARGET_UPDATE"
1fd4e8c1 8854 "@
ca7f5001 8855 {stux|stwux} %3,%0,%2
b7ff3d82 8856 {stu|stwu} %3,%2(%0)"
b54cf83a 8857 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 8858
b54cf83a 8859(define_insn "*movhi_update1"
cd2b37d9
RK		 8860 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8861 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8862 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 8863 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8864 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 8865 "TARGET_UPDATE"
1fd4e8c1 8866 "@
5f243543
RK		 8867 lhzux %3,%0,%2
8868 lhzu %3,%2(%0)"
b54cf83a 8869 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 8870
38c1f2d7 8871(define_insn "*movhi_update2"
cd2b37d9 8872 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 8873 (zero_extend:SI
cd2b37d9 8874 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8875 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 8876 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8877 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 8878 "TARGET_UPDATE"
1fd4e8c1 8879 "@
5f243543
RK		 8880 lhzux %3,%0,%2
8881 lhzu %3,%2(%0)"
b54cf83a 8882 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 8883
38c1f2d7 8884(define_insn "*movhi_update3"
cd2b37d9 8885 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 8886 (sign_extend:SI
cd2b37d9 8887 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8888 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 8889 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8890 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 8891 "TARGET_UPDATE"
1fd4e8c1 8892 "@
5f243543
RK		 8893 lhaux %3,%0,%2
8894 lhau %3,%2(%0)"
b54cf83a 8895 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 8896
38c1f2d7 8897(define_insn "*movhi_update4"
cd2b37d9 8898 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8899 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 8900 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
8901 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8902 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 8903 "TARGET_UPDATE"
1fd4e8c1 8904 "@
5f243543 8905 sthux %3,%0,%2
b7ff3d82 8906 sthu %3,%2(%0)"
b54cf83a 8907 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 8908
38c1f2d7 8909(define_insn "*movqi_update1"
cd2b37d9
RK		 8910 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
8911 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8912 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 8913 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8914 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 8915 "TARGET_UPDATE"
1fd4e8c1 8916 "@
5f243543
RK		 8917 lbzux %3,%0,%2
8918 lbzu %3,%2(%0)"
b54cf83a 8919 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 8920
38c1f2d7 8921(define_insn "*movqi_update2"
cd2b37d9 8922 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 8923 (zero_extend:SI
cd2b37d9 8924 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8925 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 8926 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8927 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 8928 "TARGET_UPDATE"
1fd4e8c1 8929 "@
5f243543
RK		 8930 lbzux %3,%0,%2
8931 lbzu %3,%2(%0)"
b54cf83a 8932 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 8933
38c1f2d7 8934(define_insn "*movqi_update3"
cd2b37d9 8935 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8936 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 8937 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
8938 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8939 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 8940 "TARGET_UPDATE"
1fd4e8c1 8941 "@
5f243543 8942 stbux %3,%0,%2
b7ff3d82 8943 stbu %3,%2(%0)"
b54cf83a 8944 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 8945
38c1f2d7 8946(define_insn "*movsf_update1"
cd2b37d9 8947 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 8948 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8949 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 8950 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8951 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 8952 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 8953 "@
5f243543
RK		 8954 lfsux %3,%0,%2
8955 lfsu %3,%2(%0)"
b54cf83a 8956 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 8957
38c1f2d7 8958(define_insn "*movsf_update2"
cd2b37d9 8959 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8960 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 8961 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
8962 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8963 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 8964 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 8965 "@
85fff2f3 8966 stfsux %3,%0,%2
b7ff3d82 8967 stfsu %3,%2(%0)"
b54cf83a 8968 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 8969
38c1f2d7
MM		 8970(define_insn "*movsf_update3"
8971 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
8972 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8973 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8974 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8975 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 8976 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 8977 "@
8978 {lux|lwzux} %3,%0,%2
8979 {lu|lwzu} %3,%2(%0)"
b54cf83a 8980 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 8981
8982(define_insn "*movsf_update4"
8983 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8984 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8985 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
8986 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8987 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 8988 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 8989 "@
8990 {stux|stwux} %3,%0,%2
8991 {stu|stwu} %3,%2(%0)"
b54cf83a 8992 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 8993
8994(define_insn "*movdf_update1"
cd2b37d9
RK		 8995 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
8996 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 8997 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 8998 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 8999 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9000 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9001 "@
5f243543
RK		 9002 lfdux %3,%0,%2
9003 lfdu %3,%2(%0)"
b54cf83a 9004 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 9005
38c1f2d7 9006(define_insn "*movdf_update2"
cd2b37d9 9007 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9008 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9009 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9010 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9011 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9012 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9013 "@
5f243543 9014 stfdux %3,%0,%2
b7ff3d82 9015 stfdu %3,%2(%0)"
b54cf83a 9016 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 9017
9018;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9019
90f81f99 9020(define_insn "*lfq_power2"
bb8df8a6
EC		 9021 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9022 (match_operand:V2DF 1 "memory_operand" ""))]
90f81f99
AP		 9023 "TARGET_POWER2
9024 && TARGET_HARD_FLOAT && TARGET_FPRS"
bb8df8a6 9025 "lfq%U1%X1 %0,%1")
90f81f99
AP		 9026
9027(define_peephole2
9028 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4c70a4f3 9029 (match_operand:DF 1 "memory_operand" ""))
90f81f99 9030 (set (match_operand:DF 2 "gpc_reg_operand" "")
4c70a4f3
RK		 9031 (match_operand:DF 3 "memory_operand" ""))]
9032 "TARGET_POWER2
a3170dc6 9033 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 9034 && registers_ok_for_quad_peep (operands[0], operands[2])
90f81f99
AP		 9035 && mems_ok_for_quad_peep (operands[1], operands[3])"
9036 [(set (match_dup 0)
bb8df8a6
EC		 9037 (match_dup 1))]
9038 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9039 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
4c70a4f3 9040
90f81f99 9041(define_insn "*stfq_power2"
bb8df8a6
EC		 9042 [(set (match_operand:V2DF 0 "memory_operand" "")
9043 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
90f81f99
AP		 9044 "TARGET_POWER2
9045 && TARGET_HARD_FLOAT && TARGET_FPRS"
9046 "stfq%U0%X0 %1,%0")
9047
9048
9049(define_peephole2
4c70a4f3 9050 [(set (match_operand:DF 0 "memory_operand" "")
90f81f99 9051 (match_operand:DF 1 "gpc_reg_operand" ""))
4c70a4f3 9052 (set (match_operand:DF 2 "memory_operand" "")
90f81f99 9053 (match_operand:DF 3 "gpc_reg_operand" ""))]
4c70a4f3 9054 "TARGET_POWER2
a3170dc6 9055 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 9056 && registers_ok_for_quad_peep (operands[1], operands[3])
90f81f99
AP		 9057 && mems_ok_for_quad_peep (operands[0], operands[2])"
9058 [(set (match_dup 0)
9059 (match_dup 1))]
bb8df8a6
EC		 9060 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9061 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
2f4d9502
NS		 9062
9063;; after inserting conditional returns we can sometimes have
9064;; unnecessary register moves. Unfortunately we cannot have a
9065;; modeless peephole here, because some single SImode sets have early
9066;; clobber outputs. Although those sets expand to multi-ppc-insn
9067;; sequences, using get_attr_length here will smash the operands
9068;; array. Neither is there an early_cobbler_p predicate.
9069(define_peephole2
9070 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9071 (match_operand:DF 1 "any_operand" ""))
9072 (set (match_operand:DF 2 "gpc_reg_operand" "")
9073 (match_dup 0))]
9074 "peep2_reg_dead_p (2, operands[0])"
9075 [(set (match_dup 2) (match_dup 1))])
9076
9077(define_peephole2
9078 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9079 (match_operand:SF 1 "any_operand" ""))
9080 (set (match_operand:SF 2 "gpc_reg_operand" "")
9081 (match_dup 0))]
9082 "peep2_reg_dead_p (2, operands[0])"
9083 [(set (match_dup 2) (match_dup 1))])
9084
1fd4e8c1 9085\f
c4501e62
JJ		 9086;; TLS support.
9087
9088;; "b" output constraint here and on tls_ld to support tls linker optimization.
9089(define_insn "tls_gd_32"
b150f4f3
DE		 9090 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9091 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9092 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9093 UNSPEC_TLSGD))]
9094 "HAVE_AS_TLS && !TARGET_64BIT"
9095 "addi %0,%1,%2@got@tlsgd")
9096
9097(define_insn "tls_gd_64"
b150f4f3
DE		 9098 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9099 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9100 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9101 UNSPEC_TLSGD))]
9102 "HAVE_AS_TLS && TARGET_64BIT"
9103 "addi %0,%1,%2@got@tlsgd")
9104
9105(define_insn "tls_ld_32"
b150f4f3
DE		 9106 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9107 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 9108 UNSPEC_TLSLD))]
9109 "HAVE_AS_TLS && !TARGET_64BIT"
9110 "addi %0,%1,%&@got@tlsld")
9111
9112(define_insn "tls_ld_64"
b150f4f3
DE		 9113 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9114 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 9115 UNSPEC_TLSLD))]
9116 "HAVE_AS_TLS && TARGET_64BIT"
9117 "addi %0,%1,%&@got@tlsld")
9118
9119(define_insn "tls_dtprel_32"
b150f4f3
DE		 9120 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9121 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9122 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9123 UNSPEC_TLSDTPREL))]
9124 "HAVE_AS_TLS && !TARGET_64BIT"
9125 "addi %0,%1,%2@dtprel")
9126
9127(define_insn "tls_dtprel_64"
b150f4f3
DE		 9128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9129 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9130 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9131 UNSPEC_TLSDTPREL))]
9132 "HAVE_AS_TLS && TARGET_64BIT"
9133 "addi %0,%1,%2@dtprel")
9134
9135(define_insn "tls_dtprel_ha_32"
b150f4f3
DE		 9136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9137 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9138 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9139 UNSPEC_TLSDTPRELHA))]
9140 "HAVE_AS_TLS && !TARGET_64BIT"
9141 "addis %0,%1,%2@dtprel@ha")
9142
9143(define_insn "tls_dtprel_ha_64"
b150f4f3
DE		 9144 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9145 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9146 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9147 UNSPEC_TLSDTPRELHA))]
9148 "HAVE_AS_TLS && TARGET_64BIT"
9149 "addis %0,%1,%2@dtprel@ha")
9150
9151(define_insn "tls_dtprel_lo_32"
b150f4f3
DE		 9152 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9153 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9154 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9155 UNSPEC_TLSDTPRELLO))]
9156 "HAVE_AS_TLS && !TARGET_64BIT"
9157 "addi %0,%1,%2@dtprel@l")
9158
9159(define_insn "tls_dtprel_lo_64"
b150f4f3
DE		 9160 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9161 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9162 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9163 UNSPEC_TLSDTPRELLO))]
9164 "HAVE_AS_TLS && TARGET_64BIT"
9165 "addi %0,%1,%2@dtprel@l")
9166
9167(define_insn "tls_got_dtprel_32"
b150f4f3
DE		 9168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9169 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9170 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9171 UNSPEC_TLSGOTDTPREL))]
9172 "HAVE_AS_TLS && !TARGET_64BIT"
9173 "lwz %0,%2@got@dtprel(%1)")
9174
9175(define_insn "tls_got_dtprel_64"
b150f4f3
DE		 9176 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9177 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9178 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9179 UNSPEC_TLSGOTDTPREL))]
9180 "HAVE_AS_TLS && TARGET_64BIT"
9181 "ld %0,%2@got@dtprel(%1)")
9182
9183(define_insn "tls_tprel_32"
b150f4f3
DE		 9184 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9185 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9186 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9187 UNSPEC_TLSTPREL))]
9188 "HAVE_AS_TLS && !TARGET_64BIT"
9189 "addi %0,%1,%2@tprel")
9190
9191(define_insn "tls_tprel_64"
b150f4f3
DE		 9192 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9193 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9194 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9195 UNSPEC_TLSTPREL))]
9196 "HAVE_AS_TLS && TARGET_64BIT"
9197 "addi %0,%1,%2@tprel")
9198
9199(define_insn "tls_tprel_ha_32"
b150f4f3
DE		 9200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9201 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9202 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9203 UNSPEC_TLSTPRELHA))]
9204 "HAVE_AS_TLS && !TARGET_64BIT"
9205 "addis %0,%1,%2@tprel@ha")
9206
9207(define_insn "tls_tprel_ha_64"
b150f4f3
DE		 9208 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9209 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9210 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9211 UNSPEC_TLSTPRELHA))]
9212 "HAVE_AS_TLS && TARGET_64BIT"
9213 "addis %0,%1,%2@tprel@ha")
9214
9215(define_insn "tls_tprel_lo_32"
b150f4f3
DE		 9216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9217 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9218 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9219 UNSPEC_TLSTPRELLO))]
9220 "HAVE_AS_TLS && !TARGET_64BIT"
9221 "addi %0,%1,%2@tprel@l")
9222
9223(define_insn "tls_tprel_lo_64"
b150f4f3
DE		 9224 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9225 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9226 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9227 UNSPEC_TLSTPRELLO))]
9228 "HAVE_AS_TLS && TARGET_64BIT"
9229 "addi %0,%1,%2@tprel@l")
9230
c1207243 9231;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 9232;; optimization. The linker may edit the instructions emitted by a
9233;; tls_got_tprel/tls_tls pair to addis,addi.
9234(define_insn "tls_got_tprel_32"
b150f4f3
DE		 9235 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9236 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9237 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9238 UNSPEC_TLSGOTTPREL))]
9239 "HAVE_AS_TLS && !TARGET_64BIT"
9240 "lwz %0,%2@got@tprel(%1)")
9241
9242(define_insn "tls_got_tprel_64"
b150f4f3
DE		 9243 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9244 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9245 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9246 UNSPEC_TLSGOTTPREL))]
9247 "HAVE_AS_TLS && TARGET_64BIT"
9248 "ld %0,%2@got@tprel(%1)")
9249
9250(define_insn "tls_tls_32"
b150f4f3
DE		 9251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9252 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9253 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9254 UNSPEC_TLSTLS))]
9255 "HAVE_AS_TLS && !TARGET_64BIT"
9256 "add %0,%1,%2@tls")
9257
9258(define_insn "tls_tls_64"
b150f4f3
DE		 9259 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9260 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 9261 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9262 UNSPEC_TLSTLS))]
9263 "HAVE_AS_TLS && TARGET_64BIT"
9264 "add %0,%1,%2@tls")
9265\f
1fd4e8c1
RK		 9266;; Next come insns related to the calling sequence.
9267;;
9268;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 9269;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 9270
9271(define_expand "allocate_stack"
52d3af72 9272 [(set (match_operand 0 "gpc_reg_operand" "=r")
a260abc9
DE		 9273 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9274 (set (reg 1)
9275 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 9276 ""
9277 "
4697a36c 9278{ rtx chain = gen_reg_rtx (Pmode);
39403d82 9279 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 9280 rtx neg_op0;
1fd4e8c1
RK		 9281
9282 emit_move_insn (chain, stack_bot);
4697a36c 9283
a157febd
GK		 9284 /* Check stack bounds if necessary. */
9285 if (current_function_limit_stack)
9286 {
9287 rtx available;
6ae08853 9288 available = expand_binop (Pmode, sub_optab,
a157febd
GK		 9289 stack_pointer_rtx, stack_limit_rtx,
9290 NULL_RTX, 1, OPTAB_WIDEN);
9291 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9292 }
9293
e9a25f70
JL		 9294 if (GET_CODE (operands[1]) != CONST_INT
9295 || INTVAL (operands[1]) < -32767
9296 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 9297 {
9298 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 9299 if (TARGET_32BIT)
e9a25f70 9300 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 9301 else
e9a25f70 9302 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 9303 }
9304 else
e9a25f70 9305 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 9306
38c1f2d7 9307 if (TARGET_UPDATE)
2e6c9641 9308 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
38c1f2d7 9309 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
4697a36c 9310
38c1f2d7
MM		 9311 else
9312 {
9313 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9314 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
39403d82 9315 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
38c1f2d7 9316 }
e9a25f70
JL		 9317
9318 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 9319 DONE;
9320}")
59257ff7
RK		 9321
9322;; These patterns say how to save and restore the stack pointer. We need not
9323;; save the stack pointer at function level since we are careful to
9324;; preserve the backchain. At block level, we have to restore the backchain
9325;; when we restore the stack pointer.
9326;;
9327;; For nonlocal gotos, we must save both the stack pointer and its
9328;; backchain and restore both. Note that in the nonlocal case, the
9329;; save area is a memory location.
9330
9331(define_expand "save_stack_function"
ff381587
MM		 9332 [(match_operand 0 "any_operand" "")
9333 (match_operand 1 "any_operand" "")]
59257ff7 9334 ""
ff381587 9335 "DONE;")
59257ff7
RK		 9336
9337(define_expand "restore_stack_function"
ff381587
MM		 9338 [(match_operand 0 "any_operand" "")
9339 (match_operand 1 "any_operand" "")]
59257ff7 9340 ""
ff381587 9341 "DONE;")
59257ff7
RK		 9342
9343(define_expand "restore_stack_block"
dfdfa60f
DE		 9344 [(use (match_operand 0 "register_operand" ""))
9345 (set (match_dup 2) (match_dup 3))
a260abc9 9346 (set (match_dup 0) (match_operand 1 "register_operand" ""))
dfdfa60f 9347 (set (match_dup 3) (match_dup 2))]
59257ff7
RK		 9348 ""
9349 "
dfdfa60f
DE		 9350{
9351 operands[2] = gen_reg_rtx (Pmode);
39403d82 9352 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
dfdfa60f 9353}")
59257ff7
RK		 9354
9355(define_expand "save_stack_nonlocal"
a260abc9
DE		 9356 [(match_operand 0 "memory_operand" "")
9357 (match_operand 1 "register_operand" "")]
59257ff7
RK		 9358 ""
9359 "
9360{
a260abc9 9361 rtx temp = gen_reg_rtx (Pmode);
11b25716 9362 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 9363
9364 /* Copy the backchain to the first word, sp to the second. */
39403d82 9365 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
39e453d7
DE		 9366 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9367 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
a260abc9 9368 operands[1]);
59257ff7
RK		 9369 DONE;
9370}")
7e69e155 9371
59257ff7 9372(define_expand "restore_stack_nonlocal"
a260abc9
DE		 9373 [(match_operand 0 "register_operand" "")
9374 (match_operand 1 "memory_operand" "")]
59257ff7
RK		 9375 ""
9376 "
9377{
a260abc9 9378 rtx temp = gen_reg_rtx (Pmode);
11b25716 9379 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 9380
9381 /* Restore the backchain from the first word, sp from the second. */
a260abc9 9382 emit_move_insn (temp,
39e453d7 9383 adjust_address_nv (operands[1], Pmode, 0));
a260abc9 9384 emit_move_insn (operands[0],
39e453d7 9385 adjust_address_nv (operands[1], Pmode, units_per_word));
39403d82 9386 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
59257ff7
RK		 9387 DONE;
9388}")
9ebbca7d
GK		 9389\f
9390;; TOC register handling.
b6c9286a 9391
9ebbca7d 9392;; Code to initialize the TOC register...
f0f6a223 9393
9ebbca7d 9394(define_insn "load_toc_aix_si"
e72247f4 9395 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 9396 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 9397 (use (reg:SI 2))])]
2bfcf297 9398 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 9399 "*
9400{
9ebbca7d
GK		 9401 char buf[30];
9402 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 9403 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 9404 operands[2] = gen_rtx_REG (Pmode, 2);
9405 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 9406}"
9407 [(set_attr "type" "load")])
9ebbca7d
GK		 9408
9409(define_insn "load_toc_aix_di"
e72247f4 9410 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 9411 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 9412 (use (reg:DI 2))])]
2bfcf297 9413 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 9414 "*
9415{
9416 char buf[30];
f585a356
DE		 9417#ifdef TARGET_RELOCATABLE
9418 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9419 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9420#else
9ebbca7d 9421 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 9422#endif
2bfcf297
DB		 9423 if (TARGET_ELF)
9424 strcat (buf, \"@toc\");
a8a05998 9425 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 9426 operands[2] = gen_rtx_REG (Pmode, 2);
9427 return \"ld %0,%1(%2)\";
9428}"
9429 [(set_attr "type" "load")])
9430
9431(define_insn "load_toc_v4_pic_si"
9432 [(set (match_operand:SI 0 "register_operand" "=l")
615158e2 9433 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 9434 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 9435 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9436 [(set_attr "type" "branch")
9437 (set_attr "length" "4")])
9438
9ebbca7d
GK		 9439(define_insn "load_toc_v4_PIC_1"
9440 [(set (match_operand:SI 0 "register_operand" "=l")
9441 (match_operand:SI 1 "immediate_operand" "s"))
c4501e62 9442 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
7f970b70
AM		 9443 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9444 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
df7a8989 9445 "bcl 20,31,%1\\n%1:"
9ebbca7d
GK		 9446 [(set_attr "type" "branch")
9447 (set_attr "length" "4")])
9448
9449(define_insn "load_toc_v4_PIC_1b"
9450 [(set (match_operand:SI 0 "register_operand" "=l")
0e5be35b 9451 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
c4501e62 9452 UNSPEC_TOCPTR))]
20b71b17 9453 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
0e5be35b 9454 "bcl 20,31,$+8\\n\\t.long %1-$"
9ebbca7d
GK		 9455 [(set_attr "type" "branch")
9456 (set_attr "length" "8")])
9457
9458(define_insn "load_toc_v4_PIC_2"
f585a356 9459 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 9460 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 9461 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9462 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 9463 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 9464 "{l|lwz} %0,%2-%3(%1)"
9465 [(set_attr "type" "load")])
9466
7f970b70
AM		 9467(define_insn "load_toc_v4_PIC_3b"
9468 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9469 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9470 (high:SI
9471 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9472 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9473 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9474 "{cau|addis} %0,%1,%2-%3@ha")
9475
9476(define_insn "load_toc_v4_PIC_3c"
9477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9478 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9479 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9480 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9481 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9482 "{cal|addi} %0,%1,%2-%3@l")
f51eee6a 9483
9ebbca7d
GK		 9484;; If the TOC is shared over a translation unit, as happens with all
9485;; the kinds of PIC that we support, we need to restore the TOC
9486;; pointer only when jumping over units of translation.
f51eee6a 9487;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 9488
9489(define_expand "builtin_setjmp_receiver"
9490 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 9491 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 9492 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9493 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 9494 "
9495{
84d7dd4a 9496#if TARGET_MACHO
f51eee6a
GK		 9497 if (DEFAULT_ABI == ABI_DARWIN)
9498 {
d24652ee 9499 const char *picbase = machopic_function_base_name ();
485bad26 9500 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
f51eee6a
GK		 9501 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9502 rtx tmplabrtx;
9503 char tmplab[20];
9504
9505 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9506 CODE_LABEL_NUMBER (operands[0]));
485bad26 9507 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a 9508
b8a55285
AP		 9509 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9510 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
f51eee6a
GK		 9511 }
9512 else
84d7dd4a 9513#endif
f51eee6a 9514 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 9515 DONE;
9516}")
7f970b70
AM		 9517
9518;; Elf specific ways of loading addresses for non-PIC code.
9519;; The output of this could be r0, but we make a very strong
9520;; preference for a base register because it will usually
9521;; be needed there.
9522(define_insn "elf_high"
9523 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
9524 (high:SI (match_operand 1 "" "")))]
9525 "TARGET_ELF && ! TARGET_64BIT"
9526 "{liu|lis} %0,%1@ha")
9527
9528(define_insn "elf_low"
9529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9530 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
9531 (match_operand 2 "" "")))]
9532 "TARGET_ELF && ! TARGET_64BIT"
9533 "@
9534 {cal|la} %0,%2@l(%1)
9535 {ai|addic} %0,%1,%K2")
9ebbca7d
GK		 9536\f
9537;; A function pointer under AIX is a pointer to a data area whose first word
9538;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 9539;; pointer to its TOC, and whose third word contains a value to place in the
9540;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 9541;; "trampoline" need not have any executable code.
b6c9286a 9542
cccf3bdc
DE		 9543(define_expand "call_indirect_aix32"
9544 [(set (match_dup 2)
9545 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9546 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9547 (reg:SI 2))
9548 (set (reg:SI 2)
9549 (mem:SI (plus:SI (match_dup 0)
9550 (const_int 4))))
9551 (set (reg:SI 11)
9552 (mem:SI (plus:SI (match_dup 0)
9553 (const_int 8))))
9554 (parallel [(call (mem:SI (match_dup 2))
9555 (match_operand 1 "" ""))
9556 (use (reg:SI 2))
9557 (use (reg:SI 11))
9558 (set (reg:SI 2)
9559 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9560 (clobber (scratch:SI))])]
9561 "TARGET_32BIT"
9562 "
9563{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 9564
cccf3bdc
DE		 9565(define_expand "call_indirect_aix64"
9566 [(set (match_dup 2)
9567 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9568 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9569 (reg:DI 2))
9570 (set (reg:DI 2)
9571 (mem:DI (plus:DI (match_dup 0)
9572 (const_int 8))))
9573 (set (reg:DI 11)
9574 (mem:DI (plus:DI (match_dup 0)
9575 (const_int 16))))
9576 (parallel [(call (mem:SI (match_dup 2))
9577 (match_operand 1 "" ""))
9578 (use (reg:DI 2))
9579 (use (reg:DI 11))
9580 (set (reg:DI 2)
9581 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9582 (clobber (scratch:SI))])]
9583 "TARGET_64BIT"
9584 "
9585{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 9586
cccf3bdc
DE		 9587(define_expand "call_value_indirect_aix32"
9588 [(set (match_dup 3)
9589 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9590 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9591 (reg:SI 2))
9592 (set (reg:SI 2)
9593 (mem:SI (plus:SI (match_dup 1)
9594 (const_int 4))))
9595 (set (reg:SI 11)
9596 (mem:SI (plus:SI (match_dup 1)
9597 (const_int 8))))
9598 (parallel [(set (match_operand 0 "" "")
9599 (call (mem:SI (match_dup 3))
9600 (match_operand 2 "" "")))
9601 (use (reg:SI 2))
9602 (use (reg:SI 11))
9603 (set (reg:SI 2)
9604 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9605 (clobber (scratch:SI))])]
9606 "TARGET_32BIT"
9607 "
9608{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 9609
cccf3bdc
DE		 9610(define_expand "call_value_indirect_aix64"
9611 [(set (match_dup 3)
9612 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9613 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9614 (reg:DI 2))
9615 (set (reg:DI 2)
9616 (mem:DI (plus:DI (match_dup 1)
9617 (const_int 8))))
9618 (set (reg:DI 11)
9619 (mem:DI (plus:DI (match_dup 1)
9620 (const_int 16))))
9621 (parallel [(set (match_operand 0 "" "")
9622 (call (mem:SI (match_dup 3))
9623 (match_operand 2 "" "")))
9624 (use (reg:DI 2))
9625 (use (reg:DI 11))
9626 (set (reg:DI 2)
9627 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9628 (clobber (scratch:SI))])]
9629 "TARGET_64BIT"
9630 "
9631{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 9632
b6c9286a 9633;; Now the definitions for the call and call_value insns
1fd4e8c1 9634(define_expand "call"
a260abc9 9635 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 9636 (match_operand 1 "" ""))
4697a36c 9637 (use (match_operand 2 "" ""))
1fd4e8c1
RK		 9638 (clobber (scratch:SI))])]
9639 ""
9640 "
9641{
ee890fe2 9642#if TARGET_MACHO
ab82a49f 9643 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 9644 operands[0] = machopic_indirect_call_target (operands[0]);
9645#endif
9646
37409796
NS		 9647 gcc_assert (GET_CODE (operands[0]) == MEM);
9648 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
1fd4e8c1
RK		 9649
9650 operands[0] = XEXP (operands[0], 0);
7509c759 9651
7f970b70
AM		 9652 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9653 && flag_pic
9654 && GET_CODE (operands[0]) == SYMBOL_REF
9655 && !SYMBOL_REF_LOCAL_P (operands[0]))
9656 {
9657 rtx call;
9658 rtvec tmp;
9659
9660 tmp = gen_rtvec (3,
9661 gen_rtx_CALL (VOIDmode,
9662 gen_rtx_MEM (SImode, operands[0]),
9663 operands[1]),
9664 gen_rtx_USE (VOIDmode, operands[2]),
9665 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9666 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9667 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9668 DONE;
9669 }
9670
6a4cee5f 9671 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 9672 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
efdba735 9673 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
1fd4e8c1 9674 {
6a4cee5f
MM		 9675 if (INTVAL (operands[2]) & CALL_LONG)
9676 operands[0] = rs6000_longcall_ref (operands[0]);
9677
37409796
NS		 9678 switch (DEFAULT_ABI)
9679 {
9680 case ABI_V4:
9681 case ABI_DARWIN:
9682 operands[0] = force_reg (Pmode, operands[0]);
9683 break;
1fd4e8c1 9684
37409796 9685 case ABI_AIX:
cccf3bdc
DE		 9686 /* AIX function pointers are really pointers to a three word
9687 area. */
9688 emit_call_insn (TARGET_32BIT
9689 ? gen_call_indirect_aix32 (force_reg (SImode,
9690 operands[0]),
9691 operands[1])
9692 : gen_call_indirect_aix64 (force_reg (DImode,
9693 operands[0]),
9694 operands[1]));
9695 DONE;
37409796
NS		 9696
9697 default:
9698 gcc_unreachable ();
b6c9286a 9699 }
1fd4e8c1
RK		 9700 }
9701}")
9702
9703(define_expand "call_value"
9704 [(parallel [(set (match_operand 0 "" "")
a260abc9 9705 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 9706 (match_operand 2 "" "")))
4697a36c 9707 (use (match_operand 3 "" ""))
1fd4e8c1
RK		 9708 (clobber (scratch:SI))])]
9709 ""
9710 "
9711{
ee890fe2 9712#if TARGET_MACHO
ab82a49f 9713 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 9714 operands[1] = machopic_indirect_call_target (operands[1]);
9715#endif
9716
37409796
NS		 9717 gcc_assert (GET_CODE (operands[1]) == MEM);
9718 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
1fd4e8c1
RK		 9719
9720 operands[1] = XEXP (operands[1], 0);
7509c759 9721
7f970b70
AM		 9722 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9723 && flag_pic
9724 && GET_CODE (operands[1]) == SYMBOL_REF
9725 && !SYMBOL_REF_LOCAL_P (operands[1]))
9726 {
9727 rtx call;
9728 rtvec tmp;
9729
9730 tmp = gen_rtvec (3,
9731 gen_rtx_SET (VOIDmode,
9732 operands[0],
9733 gen_rtx_CALL (VOIDmode,
9734 gen_rtx_MEM (SImode,
9735 operands[1]),
9736 operands[2])),
9737 gen_rtx_USE (VOIDmode, operands[3]),
9738 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9739 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9740 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9741 DONE;
9742 }
9743
6a4cee5f 9744 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 9745 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
efdba735 9746 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
1fd4e8c1 9747 {
6756293c 9748 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 9749 operands[1] = rs6000_longcall_ref (operands[1]);
9750
37409796
NS		 9751 switch (DEFAULT_ABI)
9752 {
9753 case ABI_V4:
9754 case ABI_DARWIN:
9755 operands[1] = force_reg (Pmode, operands[1]);
9756 break;
1fd4e8c1 9757
37409796 9758 case ABI_AIX:
cccf3bdc
DE		 9759 /* AIX function pointers are really pointers to a three word
9760 area. */
9761 emit_call_insn (TARGET_32BIT
9762 ? gen_call_value_indirect_aix32 (operands[0],
9763 force_reg (SImode,
9764 operands[1]),
9765 operands[2])
9766 : gen_call_value_indirect_aix64 (operands[0],
9767 force_reg (DImode,
9768 operands[1]),
9769 operands[2]));
9770 DONE;
37409796
NS		 9771
9772 default:
9773 gcc_unreachable ();
b6c9286a 9774 }
1fd4e8c1
RK		 9775 }
9776}")
9777
04780ee7 9778;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 9779;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 9780;; either the function was not prototyped, or it was prototyped as a
9781;; variable argument function. It is > 0 if FP registers were passed
9782;; and < 0 if they were not.
04780ee7 9783
a260abc9 9784(define_insn "*call_local32"
4697a36c
MM		 9785 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9786 (match_operand 1 "" "g,g"))
9787 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9788 (clobber (match_scratch:SI 3 "=l,l"))]
5a19791c 9789 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 9790 "*
9791{
6a4cee5f
MM		 9792 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9793 output_asm_insn (\"crxor 6,6,6\", operands);
9794
9795 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9796 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 9797
a226df46 9798 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 9799}"
b7ff3d82
DE		 9800 [(set_attr "type" "branch")
9801 (set_attr "length" "4,8")])
04780ee7 9802
a260abc9
DE		 9803(define_insn "*call_local64"
9804 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9805 (match_operand 1 "" "g,g"))
9806 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9807 (clobber (match_scratch:SI 3 "=l,l"))]
9808 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9809 "*
9810{
9811 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9812 output_asm_insn (\"crxor 6,6,6\", operands);
9813
9814 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9815 output_asm_insn (\"creqv 6,6,6\", operands);
9816
9817 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9818}"
9819 [(set_attr "type" "branch")
9820 (set_attr "length" "4,8")])
9821
cccf3bdc 9822(define_insn "*call_value_local32"
d18dba68 9823 [(set (match_operand 0 "" "")
a260abc9
DE		 9824 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9825 (match_operand 2 "" "g,g")))
9826 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9827 (clobber (match_scratch:SI 4 "=l,l"))]
9828 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9829 "*
9830{
9831 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9832 output_asm_insn (\"crxor 6,6,6\", operands);
9833
9834 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9835 output_asm_insn (\"creqv 6,6,6\", operands);
9836
9837 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9838}"
9839 [(set_attr "type" "branch")
9840 (set_attr "length" "4,8")])
9841
9842
cccf3bdc 9843(define_insn "*call_value_local64"
d18dba68 9844 [(set (match_operand 0 "" "")
a260abc9
DE		 9845 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9846 (match_operand 2 "" "g,g")))
9847 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9848 (clobber (match_scratch:SI 4 "=l,l"))]
9849 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9850 "*
9851{
9852 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9853 output_asm_insn (\"crxor 6,6,6\", operands);
9854
9855 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9856 output_asm_insn (\"creqv 6,6,6\", operands);
9857
9858 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9859}"
9860 [(set_attr "type" "branch")
9861 (set_attr "length" "4,8")])
9862
04780ee7 9863;; Call to function which may be in another module. Restore the TOC
911f679c 9864;; pointer (r2) after the call unless this is System V.
a0ab749a 9865;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 9866;; either the function was not prototyped, or it was prototyped as a
9867;; variable argument function. It is > 0 if FP registers were passed
9868;; and < 0 if they were not.
04780ee7 9869
cccf3bdc 9870(define_insn "*call_indirect_nonlocal_aix32"
70ae0191
DE		 9871 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
9872 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 9873 (use (reg:SI 2))
9874 (use (reg:SI 11))
9875 (set (reg:SI 2)
9876 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
70ae0191 9877 (clobber (match_scratch:SI 2 "=l,l"))]
cccf3bdc
DE		 9878 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9879 "b%T0l\;{l|lwz} 2,20(1)"
9880 [(set_attr "type" "jmpreg")
9881 (set_attr "length" "8")])
9882
a260abc9 9883(define_insn "*call_nonlocal_aix32"
cc4d5fec 9884 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 9885 (match_operand 1 "" "g"))
9886 (use (match_operand:SI 2 "immediate_operand" "O"))
9887 (clobber (match_scratch:SI 3 "=l"))]
9888 "TARGET_32BIT
9889 && DEFAULT_ABI == ABI_AIX
5a19791c 9890 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 9891 "bl %z0\;%."
b7ff3d82 9892 [(set_attr "type" "branch")
cccf3bdc
DE		 9893 (set_attr "length" "8")])
9894
9895(define_insn "*call_indirect_nonlocal_aix64"
70ae0191
DE		 9896 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
9897 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 9898 (use (reg:DI 2))
9899 (use (reg:DI 11))
9900 (set (reg:DI 2)
9901 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
70ae0191 9902 (clobber (match_scratch:SI 2 "=l,l"))]
cccf3bdc
DE		 9903 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9904 "b%T0l\;ld 2,40(1)"
9905 [(set_attr "type" "jmpreg")
9906 (set_attr "length" "8")])
59313e4e 9907
a260abc9 9908(define_insn "*call_nonlocal_aix64"
cc4d5fec 9909 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 9910 (match_operand 1 "" "g"))
9911 (use (match_operand:SI 2 "immediate_operand" "O"))
9912 (clobber (match_scratch:SI 3 "=l"))]
6ae08853 9913 "TARGET_64BIT
9ebbca7d 9914 && DEFAULT_ABI == ABI_AIX
a260abc9 9915 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 9916 "bl %z0\;%."
a260abc9 9917 [(set_attr "type" "branch")
cccf3bdc 9918 (set_attr "length" "8")])
7509c759 9919
cccf3bdc 9920(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 9921 [(set (match_operand 0 "" "")
70ae0191
DE		 9922 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
9923 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 9924 (use (reg:SI 2))
9925 (use (reg:SI 11))
9926 (set (reg:SI 2)
9927 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
70ae0191 9928 (clobber (match_scratch:SI 3 "=l,l"))]
cccf3bdc
DE		 9929 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9930 "b%T1l\;{l|lwz} 2,20(1)"
9931 [(set_attr "type" "jmpreg")
9932 (set_attr "length" "8")])
1fd4e8c1 9933
cccf3bdc 9934(define_insn "*call_value_nonlocal_aix32"
d18dba68 9935 [(set (match_operand 0 "" "")
cc4d5fec 9936 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 9937 (match_operand 2 "" "g")))
9938 (use (match_operand:SI 3 "immediate_operand" "O"))
9939 (clobber (match_scratch:SI 4 "=l"))]
9940 "TARGET_32BIT
9941 && DEFAULT_ABI == ABI_AIX
a260abc9 9942 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 9943 "bl %z1\;%."
b7ff3d82 9944 [(set_attr "type" "branch")
cccf3bdc 9945 (set_attr "length" "8")])
04780ee7 9946
cccf3bdc 9947(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 9948 [(set (match_operand 0 "" "")
70ae0191
DE		 9949 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
9950 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 9951 (use (reg:DI 2))
9952 (use (reg:DI 11))
9953 (set (reg:DI 2)
9954 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
70ae0191 9955 (clobber (match_scratch:SI 3 "=l,l"))]
cccf3bdc
DE		 9956 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9957 "b%T1l\;ld 2,40(1)"
9958 [(set_attr "type" "jmpreg")
9959 (set_attr "length" "8")])
9960
9961(define_insn "*call_value_nonlocal_aix64"
d18dba68 9962 [(set (match_operand 0 "" "")
cc4d5fec 9963 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 9964 (match_operand 2 "" "g")))
9965 (use (match_operand:SI 3 "immediate_operand" "O"))
9966 (clobber (match_scratch:SI 4 "=l"))]
6ae08853 9967 "TARGET_64BIT
9ebbca7d 9968 && DEFAULT_ABI == ABI_AIX
5a19791c 9969 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 9970 "bl %z1\;%."
9971 [(set_attr "type" "branch")
9972 (set_attr "length" "8")])
9973
9974;; A function pointer under System V is just a normal pointer
9975;; operands[0] is the function pointer
9976;; operands[1] is the stack size to clean up
9977;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
9978;; which indicates how to set cr1
9979
a5c76ee6 9980(define_insn "*call_indirect_nonlocal_sysv"
6d0a8091
DJ		 9981 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
9982 (match_operand 1 "" "g,g,g,g"))
9983 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
9984 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
50d440bc 9985 "DEFAULT_ABI == ABI_V4
f607bc57 9986 || DEFAULT_ABI == ABI_DARWIN"
911f679c 9987{
cccf3bdc 9988 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 9989 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 9990
cccf3bdc 9991 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 9992 output_asm_insn ("creqv 6,6,6", operands);
7509c759 9993
a5c76ee6
ZW		 9994 return "b%T0l";
9995}
6d0a8091
DJ		 9996 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
9997 (set_attr "length" "4,4,8,8")])
cccf3bdc 9998
a5c76ee6
ZW		 9999(define_insn "*call_nonlocal_sysv"
10000 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10001 (match_operand 1 "" "g,g"))
10002 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10003 (clobber (match_scratch:SI 3 "=l,l"))]
efdba735
SH		 10004 "(DEFAULT_ABI == ABI_DARWIN
10005 || (DEFAULT_ABI == ABI_V4
10006 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 10007{
10008 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10009 output_asm_insn ("crxor 6,6,6", operands);
10010
10011 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10012 output_asm_insn ("creqv 6,6,6", operands);
10013
c989f2f7 10014#if TARGET_MACHO
efdba735
SH		 10015 return output_call(insn, operands, 0, 2);
10016#else
7f970b70
AM		 10017 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10018 {
10019 if (TARGET_SECURE_PLT && flag_pic == 2)
10020 /* The magic 32768 offset here and in the other sysv call insns
10021 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10022 See sysv4.h:toc_section. */
10023 return "bl %z0+32768@plt";
10024 else
10025 return "bl %z0@plt";
10026 }
10027 else
10028 return "bl %z0";
6ae08853 10029#endif
a5c76ee6
ZW		 10030}
10031 [(set_attr "type" "branch,branch")
10032 (set_attr "length" "4,8")])
10033
10034(define_insn "*call_value_indirect_nonlocal_sysv"
d18dba68 10035 [(set (match_operand 0 "" "")
6d0a8091
DJ		 10036 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10037 (match_operand 2 "" "g,g,g,g")))
10038 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10039 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
50d440bc 10040 "DEFAULT_ABI == ABI_V4
f607bc57 10041 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 10042{
6a4cee5f 10043 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 10044 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 10045
10046 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 10047 output_asm_insn ("creqv 6,6,6", operands);
7509c759 10048
a5c76ee6
ZW		 10049 return "b%T1l";
10050}
6d0a8091
DJ		 10051 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10052 (set_attr "length" "4,4,8,8")])
a5c76ee6
ZW		 10053
10054(define_insn "*call_value_nonlocal_sysv"
10055 [(set (match_operand 0 "" "")
10056 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10057 (match_operand 2 "" "g,g")))
10058 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10059 (clobber (match_scratch:SI 4 "=l,l"))]
efdba735
SH		 10060 "(DEFAULT_ABI == ABI_DARWIN
10061 || (DEFAULT_ABI == ABI_V4
10062 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 10063{
10064 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10065 output_asm_insn ("crxor 6,6,6", operands);
10066
10067 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10068 output_asm_insn ("creqv 6,6,6", operands);
10069
c989f2f7 10070#if TARGET_MACHO
efdba735
SH		 10071 return output_call(insn, operands, 1, 3);
10072#else
7f970b70
AM		 10073 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10074 {
10075 if (TARGET_SECURE_PLT && flag_pic == 2)
10076 return "bl %z1+32768@plt";
10077 else
10078 return "bl %z1@plt";
10079 }
10080 else
10081 return "bl %z1";
6ae08853 10082#endif
a5c76ee6
ZW		 10083}
10084 [(set_attr "type" "branch,branch")
10085 (set_attr "length" "4,8")])
e6f948e3
RK		 10086
10087;; Call subroutine returning any type.
e6f948e3
RK		 10088(define_expand "untyped_call"
10089 [(parallel [(call (match_operand 0 "" "")
10090 (const_int 0))
10091 (match_operand 1 "" "")
10092 (match_operand 2 "" "")])]
10093 ""
10094 "
10095{
10096 int i;
10097
7d70b8b2 10098 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 10099
10100 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10101 {
10102 rtx set = XVECEXP (operands[2], 0, i);
10103 emit_move_insn (SET_DEST (set), SET_SRC (set));
10104 }
10105
10106 /* The optimizer does not know that the call sets the function value
10107 registers we stored in the result block. We avoid problems by
10108 claiming that all hard registers are used and clobbered at this
10109 point. */
10110 emit_insn (gen_blockage ());
10111
10112 DONE;
10113}")
10114
5e1bf043
DJ		 10115;; sibling call patterns
10116(define_expand "sibcall"
10117 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10118 (match_operand 1 "" ""))
10119 (use (match_operand 2 "" ""))
fe352c29 10120 (use (match_operand 3 "" ""))
5e1bf043
DJ		 10121 (return)])]
10122 ""
10123 "
10124{
10125#if TARGET_MACHO
ab82a49f 10126 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 10127 operands[0] = machopic_indirect_call_target (operands[0]);
10128#endif
10129
37409796
NS		 10130 gcc_assert (GET_CODE (operands[0]) == MEM);
10131 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5e1bf043
DJ		 10132
10133 operands[0] = XEXP (operands[0], 0);
fe352c29 10134 operands[3] = gen_reg_rtx (SImode);
5e1bf043
DJ		 10135
10136}")
10137
10138;; this and similar patterns must be marked as using LR, otherwise
10139;; dataflow will try to delete the store into it. This is true
10140;; even when the actual reg to jump to is in CTR, when LR was
10141;; saved and restored around the PIC-setting BCL.
10142(define_insn "*sibcall_local32"
10143 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10144 (match_operand 1 "" "g,g"))
10145 (use (match_operand:SI 2 "immediate_operand" "O,n"))
fe352c29 10146 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10147 (return)]
10148 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10149 "*
10150{
10151 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10152 output_asm_insn (\"crxor 6,6,6\", operands);
10153
10154 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10155 output_asm_insn (\"creqv 6,6,6\", operands);
10156
10157 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10158}"
10159 [(set_attr "type" "branch")
10160 (set_attr "length" "4,8")])
10161
10162(define_insn "*sibcall_local64"
10163 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10164 (match_operand 1 "" "g,g"))
10165 (use (match_operand:SI 2 "immediate_operand" "O,n"))
fe352c29 10166 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10167 (return)]
10168 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10169 "*
10170{
10171 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10172 output_asm_insn (\"crxor 6,6,6\", operands);
10173
10174 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10175 output_asm_insn (\"creqv 6,6,6\", operands);
10176
10177 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10178}"
10179 [(set_attr "type" "branch")
10180 (set_attr "length" "4,8")])
10181
10182(define_insn "*sibcall_value_local32"
10183 [(set (match_operand 0 "" "")
10184 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10185 (match_operand 2 "" "g,g")))
10186 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10187 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10188 (return)]
10189 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10190 "*
10191{
10192 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10193 output_asm_insn (\"crxor 6,6,6\", operands);
10194
10195 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10196 output_asm_insn (\"creqv 6,6,6\", operands);
10197
10198 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10199}"
10200 [(set_attr "type" "branch")
10201 (set_attr "length" "4,8")])
10202
10203
10204(define_insn "*sibcall_value_local64"
10205 [(set (match_operand 0 "" "")
10206 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10207 (match_operand 2 "" "g,g")))
10208 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10209 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10210 (return)]
10211 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10212 "*
10213{
10214 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10215 output_asm_insn (\"crxor 6,6,6\", operands);
10216
10217 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10218 output_asm_insn (\"creqv 6,6,6\", operands);
10219
10220 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10221}"
10222 [(set_attr "type" "branch")
10223 (set_attr "length" "4,8")])
10224
10225(define_insn "*sibcall_nonlocal_aix32"
10226 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10227 (match_operand 1 "" "g"))
10228 (use (match_operand:SI 2 "immediate_operand" "O"))
fe352c29 10229 (use (match_operand:SI 3 "register_operand" "l"))
5e1bf043
DJ		 10230 (return)]
10231 "TARGET_32BIT
10232 && DEFAULT_ABI == ABI_AIX
10233 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10234 "b %z0"
10235 [(set_attr "type" "branch")
10236 (set_attr "length" "4")])
10237
10238(define_insn "*sibcall_nonlocal_aix64"
10239 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10240 (match_operand 1 "" "g"))
10241 (use (match_operand:SI 2 "immediate_operand" "O"))
fe352c29 10242 (use (match_operand:SI 3 "register_operand" "l"))
5e1bf043 10243 (return)]
6ae08853 10244 "TARGET_64BIT
5e1bf043
DJ		 10245 && DEFAULT_ABI == ABI_AIX
10246 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10247 "b %z0"
10248 [(set_attr "type" "branch")
10249 (set_attr "length" "4")])
10250
10251(define_insn "*sibcall_value_nonlocal_aix32"
10252 [(set (match_operand 0 "" "")
10253 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10254 (match_operand 2 "" "g")))
10255 (use (match_operand:SI 3 "immediate_operand" "O"))
fe352c29 10256 (use (match_operand:SI 4 "register_operand" "l"))
5e1bf043
DJ		 10257 (return)]
10258 "TARGET_32BIT
10259 && DEFAULT_ABI == ABI_AIX
10260 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10261 "b %z1"
10262 [(set_attr "type" "branch")
10263 (set_attr "length" "4")])
10264
10265(define_insn "*sibcall_value_nonlocal_aix64"
10266 [(set (match_operand 0 "" "")
10267 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10268 (match_operand 2 "" "g")))
10269 (use (match_operand:SI 3 "immediate_operand" "O"))
fe352c29 10270 (use (match_operand:SI 4 "register_operand" "l"))
5e1bf043 10271 (return)]
6ae08853 10272 "TARGET_64BIT
5e1bf043
DJ		 10273 && DEFAULT_ABI == ABI_AIX
10274 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10275 "b %z1"
10276 [(set_attr "type" "branch")
10277 (set_attr "length" "4")])
10278
10279(define_insn "*sibcall_nonlocal_sysv"
10280 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10281 (match_operand 1 "" ""))
10282 (use (match_operand 2 "immediate_operand" "O,n"))
fe352c29 10283 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10284 (return)]
10285 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 10286 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 10287 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10288 "*
10289{
10290 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10291 output_asm_insn (\"crxor 6,6,6\", operands);
10292
10293 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10294 output_asm_insn (\"creqv 6,6,6\", operands);
10295
7f970b70
AM		 10296 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10297 {
10298 if (TARGET_SECURE_PLT && flag_pic == 2)
10299 return \"b %z0+32768@plt\";
10300 else
10301 return \"b %z0@plt\";
10302 }
10303 else
10304 return \"b %z0\";
5e1bf043
DJ		 10305}"
10306 [(set_attr "type" "branch,branch")
10307 (set_attr "length" "4,8")])
10308
10309(define_expand "sibcall_value"
10310 [(parallel [(set (match_operand 0 "register_operand" "")
10311 (call (mem:SI (match_operand 1 "address_operand" ""))
10312 (match_operand 2 "" "")))
10313 (use (match_operand 3 "" ""))
fe352c29 10314 (use (match_operand 4 "" ""))
5e1bf043
DJ		 10315 (return)])]
10316 ""
10317 "
10318{
10319#if TARGET_MACHO
ab82a49f 10320 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 10321 operands[1] = machopic_indirect_call_target (operands[1]);
10322#endif
10323
37409796
NS		 10324 gcc_assert (GET_CODE (operands[1]) == MEM);
10325 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5e1bf043
DJ		 10326
10327 operands[1] = XEXP (operands[1], 0);
fe352c29 10328 operands[4] = gen_reg_rtx (SImode);
5e1bf043
DJ		 10329
10330}")
10331
10332(define_insn "*sibcall_value_nonlocal_sysv"
10333 [(set (match_operand 0 "" "")
10334 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10335 (match_operand 2 "" "")))
10336 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10337 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10338 (return)]
10339 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 10340 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 10341 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10342 "*
10343{
10344 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10345 output_asm_insn (\"crxor 6,6,6\", operands);
10346
10347 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10348 output_asm_insn (\"creqv 6,6,6\", operands);
10349
7f970b70
AM		 10350 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10351 {
10352 if (TARGET_SECURE_PLT && flag_pic == 2)
10353 return \"b %z1+32768@plt\";
10354 else
10355 return \"b %z1@plt\";
10356 }
10357 else
10358 return \"b %z1\";
5e1bf043
DJ		 10359}"
10360 [(set_attr "type" "branch,branch")
10361 (set_attr "length" "4,8")])
10362
10363(define_expand "sibcall_epilogue"
10364 [(use (const_int 0))]
10365 "TARGET_SCHED_PROLOG"
10366 "
10367{
10368 rs6000_emit_epilogue (TRUE);
10369 DONE;
10370}")
10371
e6f948e3
RK		 10372;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10373;; all of memory. This blocks insns from being moved across this point.
10374
10375(define_insn "blockage"
615158e2 10376 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 10377 ""
10378 "")
1fd4e8c1
RK		 10379\f
10380;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 10381;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 10382;;
10383;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10384;; insns, and branches. We store the operands of compares until we see
10385;; how it is used.
4ae234b0 10386(define_expand "cmp<mode>"
1fd4e8c1 10387 [(set (cc0)
4ae234b0
GK		 10388 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
10389 (match_operand:GPR 1 "reg_or_short_operand" "")))]
1fd4e8c1
RK		 10390 ""
10391 "
10392{
10393 /* Take care of the possibility that operands[1] might be negative but
10394 this might be a logical operation. That insn doesn't exist. */
10395 if (GET_CODE (operands[1]) == CONST_INT
10396 && INTVAL (operands[1]) < 0)
4ae234b0 10397 operands[1] = force_reg (<MODE>mode, operands[1]);
1fd4e8c1
RK		 10398
10399 rs6000_compare_op0 = operands[0];
10400 rs6000_compare_op1 = operands[1];
10401 rs6000_compare_fp_p = 0;
10402 DONE;
10403}")
10404
4ae234b0
GK		 10405(define_expand "cmp<mode>"
10406 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
10407 (match_operand:FP 1 "gpc_reg_operand" "")))]
10408 ""
d6f99ca4
DE		 10409 "
10410{
10411 rs6000_compare_op0 = operands[0];
10412 rs6000_compare_op1 = operands[1];
10413 rs6000_compare_fp_p = 1;
10414 DONE;
10415}")
10416
1fd4e8c1 10417(define_expand "beq"
39a10a29 10418 [(use (match_operand 0 "" ""))]
1fd4e8c1 10419 ""
39a10a29 10420 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 10421
10422(define_expand "bne"
39a10a29 10423 [(use (match_operand 0 "" ""))]
1fd4e8c1 10424 ""
39a10a29 10425 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
1fd4e8c1 10426
39a10a29
GK		 10427(define_expand "bge"
10428 [(use (match_operand 0 "" ""))]
1fd4e8c1 10429 ""
39a10a29 10430 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
1fd4e8c1
RK		 10431
10432(define_expand "bgt"
39a10a29 10433 [(use (match_operand 0 "" ""))]
1fd4e8c1 10434 ""
39a10a29 10435 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
1fd4e8c1
RK		 10436
10437(define_expand "ble"
39a10a29 10438 [(use (match_operand 0 "" ""))]
1fd4e8c1 10439 ""
39a10a29 10440 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
1fd4e8c1 10441
39a10a29
GK		 10442(define_expand "blt"
10443 [(use (match_operand 0 "" ""))]
1fd4e8c1 10444 ""
39a10a29 10445 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
1fd4e8c1 10446
39a10a29
GK		 10447(define_expand "bgeu"
10448 [(use (match_operand 0 "" ""))]
1fd4e8c1 10449 ""
39a10a29 10450 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
1fd4e8c1 10451
39a10a29
GK		 10452(define_expand "bgtu"
10453 [(use (match_operand 0 "" ""))]
1fd4e8c1 10454 ""
39a10a29 10455 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
1fd4e8c1 10456
39a10a29
GK		 10457(define_expand "bleu"
10458 [(use (match_operand 0 "" ""))]
1fd4e8c1 10459 ""
39a10a29 10460 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
1fd4e8c1 10461
39a10a29
GK		 10462(define_expand "bltu"
10463 [(use (match_operand 0 "" ""))]
1fd4e8c1 10464 ""
39a10a29 10465 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
1fd4e8c1 10466
1c882ea4 10467(define_expand "bunordered"
39a10a29 10468 [(use (match_operand 0 "" ""))]
7a1bf2f9 10469 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
39a10a29 10470 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
1c882ea4
GK		 10471
10472(define_expand "bordered"
39a10a29 10473 [(use (match_operand 0 "" ""))]
7a1bf2f9 10474 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
39a10a29 10475 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
1c882ea4
GK		 10476
10477(define_expand "buneq"
39a10a29 10478 [(use (match_operand 0 "" ""))]
1c882ea4 10479 ""
39a10a29 10480 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
1c882ea4
GK		 10481
10482(define_expand "bunge"
39a10a29 10483 [(use (match_operand 0 "" ""))]
1c882ea4 10484 ""
39a10a29 10485 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
1c882ea4
GK		 10486
10487(define_expand "bungt"
39a10a29 10488 [(use (match_operand 0 "" ""))]
1c882ea4 10489 ""
39a10a29 10490 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
1c882ea4
GK		 10491
10492(define_expand "bunle"
39a10a29 10493 [(use (match_operand 0 "" ""))]
1c882ea4 10494 ""
39a10a29 10495 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
1c882ea4
GK		 10496
10497(define_expand "bunlt"
39a10a29 10498 [(use (match_operand 0 "" ""))]
1c882ea4 10499 ""
39a10a29 10500 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
1c882ea4
GK		 10501
10502(define_expand "bltgt"
39a10a29 10503 [(use (match_operand 0 "" ""))]
1c882ea4 10504 ""
39a10a29 10505 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
1c882ea4 10506
1fd4e8c1
RK		 10507;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10508;; For SEQ, likewise, except that comparisons with zero should be done
10509;; with an scc insns. However, due to the order that combine see the
10510;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10511;; the cases we don't want to handle.
10512(define_expand "seq"
39a10a29 10513 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10514 ""
39a10a29 10515 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 10516
10517(define_expand "sne"
39a10a29 10518 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 10519 ""
10520 "
6ae08853 10521{
39a10a29 10522 if (! rs6000_compare_fp_p)
1fd4e8c1
RK		 10523 FAIL;
10524
6ae08853 10525 rs6000_emit_sCOND (NE, operands[0]);
39a10a29 10526 DONE;
1fd4e8c1
RK		 10527}")
10528
b7053a3f
GK		 10529;; A >= 0 is best done the portable way for A an integer.
10530(define_expand "sge"
39a10a29 10531 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 10532 ""
10533 "
5638268e 10534{
e56d7409 10535 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 10536 FAIL;
10537
b7053a3f 10538 rs6000_emit_sCOND (GE, operands[0]);
39a10a29 10539 DONE;
1fd4e8c1
RK		 10540}")
10541
b7053a3f
GK		 10542;; A > 0 is best done using the portable sequence, so fail in that case.
10543(define_expand "sgt"
39a10a29 10544 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 10545 ""
10546 "
5638268e 10547{
e56d7409 10548 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 10549 FAIL;
10550
6ae08853 10551 rs6000_emit_sCOND (GT, operands[0]);
39a10a29 10552 DONE;
1fd4e8c1
RK		 10553}")
10554
b7053a3f
GK		 10555;; A <= 0 is best done the portable way for A an integer.
10556(define_expand "sle"
39a10a29 10557 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10558 ""
5638268e
DE		 10559 "
10560{
e56d7409 10561 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5638268e
DE		 10562 FAIL;
10563
6ae08853 10564 rs6000_emit_sCOND (LE, operands[0]);
5638268e
DE		 10565 DONE;
10566}")
1fd4e8c1 10567
b7053a3f
GK		 10568;; A < 0 is best done in the portable way for A an integer.
10569(define_expand "slt"
39a10a29 10570 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 10571 ""
10572 "
5638268e 10573{
e56d7409 10574 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 10575 FAIL;
10576
6ae08853 10577 rs6000_emit_sCOND (LT, operands[0]);
39a10a29 10578 DONE;
1fd4e8c1
RK		 10579}")
10580
b7053a3f
GK		 10581(define_expand "sgeu"
10582 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10583 ""
10584 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10585
1fd4e8c1 10586(define_expand "sgtu"
39a10a29 10587 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10588 ""
39a10a29 10589 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
1fd4e8c1 10590
b7053a3f
GK		 10591(define_expand "sleu"
10592 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10593 ""
10594 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10595
1fd4e8c1 10596(define_expand "sltu"
39a10a29 10597 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10598 ""
39a10a29 10599 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
1fd4e8c1 10600
b7053a3f 10601(define_expand "sunordered"
39a10a29 10602 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
7836a61f 10603 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
b7053a3f 10604 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
1fd4e8c1 10605
b7053a3f 10606(define_expand "sordered"
39a10a29 10607 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
7836a61f 10608 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
b7053a3f
GK		 10609 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
10610
10611(define_expand "suneq"
10612 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10613 ""
10614 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
10615
10616(define_expand "sunge"
10617 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10618 ""
10619 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
10620
10621(define_expand "sungt"
10622 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10623 ""
10624 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
10625
10626(define_expand "sunle"
10627 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10628 ""
10629 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
10630
10631(define_expand "sunlt"
10632 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10633 ""
10634 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
10635
10636(define_expand "sltgt"
10637 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10638 ""
10639 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
10640
3aebbe5f
JJ		 10641(define_expand "stack_protect_set"
10642 [(match_operand 0 "memory_operand" "")
10643 (match_operand 1 "memory_operand" "")]
10644 ""
10645{
77008252
JJ		 10646#ifdef TARGET_THREAD_SSP_OFFSET
10647 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10648 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10649 operands[1] = gen_rtx_MEM (Pmode, addr);
10650#endif
3aebbe5f
JJ		 10651 if (TARGET_64BIT)
10652 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10653 else
10654 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10655 DONE;
10656})
10657
10658(define_insn "stack_protect_setsi"
10659 [(set (match_operand:SI 0 "memory_operand" "=m")
10660 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10661 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10662 "TARGET_32BIT"
10663 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
10664 [(set_attr "type" "three")
10665 (set_attr "length" "12")])
10666
10667(define_insn "stack_protect_setdi"
10668 [(set (match_operand:DI 0 "memory_operand" "=m")
10669 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10670 (set (match_scratch:DI 2 "=&r") (const_int 0))]
10671 "TARGET_64BIT"
10672 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
10673 [(set_attr "type" "three")
10674 (set_attr "length" "12")])
10675
10676(define_expand "stack_protect_test"
10677 [(match_operand 0 "memory_operand" "")
10678 (match_operand 1 "memory_operand" "")
10679 (match_operand 2 "" "")]
10680 ""
10681{
77008252
JJ		 10682#ifdef TARGET_THREAD_SSP_OFFSET
10683 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10684 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10685 operands[1] = gen_rtx_MEM (Pmode, addr);
10686#endif
3aebbe5f
JJ		 10687 rs6000_compare_op0 = operands[0];
10688 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
10689 UNSPEC_SP_TEST);
10690 rs6000_compare_fp_p = 0;
10691 emit_jump_insn (gen_beq (operands[2]));
10692 DONE;
10693})
10694
10695(define_insn "stack_protect_testsi"
10696 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10697 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
10698 (match_operand:SI 2 "memory_operand" "m,m")]
10699 UNSPEC_SP_TEST))
41f12ed0
JJ		 10700 (set (match_scratch:SI 4 "=r,r") (const_int 0))
10701 (clobber (match_scratch:SI 3 "=&r,&r"))]
3aebbe5f
JJ		 10702 "TARGET_32BIT"
10703 "@
10704 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10705 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10706 [(set_attr "length" "16,20")])
10707
10708(define_insn "stack_protect_testdi"
10709 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10710 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
10711 (match_operand:DI 2 "memory_operand" "m,m")]
10712 UNSPEC_SP_TEST))
41f12ed0
JJ		 10713 (set (match_scratch:DI 4 "=r,r") (const_int 0))
10714 (clobber (match_scratch:DI 3 "=&r,&r"))]
3aebbe5f
JJ		 10715 "TARGET_64BIT"
10716 "@
10717 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10718 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10719 [(set_attr "length" "16,20")])
10720
1fd4e8c1
RK		 10721\f
10722;; Here are the actual compare insns.
4ae234b0 10723(define_insn "*cmp<mode>_internal1"
1fd4e8c1 10724 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
4ae234b0
GK		 10725 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
10726 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
1fd4e8c1 10727 ""
4ae234b0 10728 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
b54cf83a 10729 [(set_attr "type" "cmp")])
266eb58a 10730
f357808b 10731;; If we are comparing a register for equality with a large constant,
28d0e143
PB		 10732;; we can do this with an XOR followed by a compare. But this is profitable
10733;; only if the large constant is only used for the comparison (and in this
10734;; case we already have a register to reuse as scratch).
130869aa
PB		 10735;;
10736;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
10737;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
f357808b 10738
28d0e143 10739(define_peephole2
130869aa
PB		 10740 [(set (match_operand:SI 0 "register_operand")
10741 (match_operand:SI 1 "logical_operand" ""))
10742 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
28d0e143 10743 [(match_dup 0)
130869aa 10744 (match_operand:SI 2 "logical_operand" "")]))
28d0e143 10745 (set (match_operand:CC 4 "cc_reg_operand" "")
130869aa 10746 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
28d0e143
PB		 10747 (match_dup 0)))
10748 (set (pc)
10749 (if_then_else (match_operator 6 "equality_operator"
10750 [(match_dup 4) (const_int 0)])
10751 (match_operand 7 "" "")
10752 (match_operand 8 "" "")))]
130869aa
PB		 10753 "peep2_reg_dead_p (3, operands[0])
10754 && peep2_reg_dead_p (4, operands[4])"
10755 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
28d0e143
PB		 10756 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
10757 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
10758
10759{
10760 /* Get the constant we are comparing against, and see what it looks like
10761 when sign-extended from 16 to 32 bits. Then see what constant we could
10762 XOR with SEXTC to get the sign-extended value. */
10763 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
130869aa 10764 SImode,
28d0e143
PB		 10765 operands[1], operands[2]);
10766 HOST_WIDE_INT c = INTVAL (cnst);
a65c591c 10767 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 10768 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 10769
28d0e143
PB		 10770 operands[9] = GEN_INT (xorv);
10771 operands[10] = GEN_INT (sextc);
10772})
f357808b 10773
acad7ed3 10774(define_insn "*cmpsi_internal2"
1fd4e8c1 10775 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 10776 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 10777 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 10778 ""
e2c953b6 10779 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 10780 [(set_attr "type" "cmp")])
1fd4e8c1 10781
acad7ed3 10782(define_insn "*cmpdi_internal2"
266eb58a
DE		 10783 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10784 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 10785 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 10786 ""
e2c953b6 10787 "cmpld%I2 %0,%1,%b2"
b54cf83a 10788 [(set_attr "type" "cmp")])
266eb58a 10789
1fd4e8c1
RK		 10790;; The following two insns don't exist as single insns, but if we provide
10791;; them, we can swap an add and compare, which will enable us to overlap more
10792;; of the required delay between a compare and branch. We generate code for
10793;; them by splitting.
10794
10795(define_insn ""
10796 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 10797 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 10798 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 10799 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 10800 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10801 ""
baf97f86
RK		 10802 "#"
10803 [(set_attr "length" "8")])
7e69e155 10804
1fd4e8c1
RK		 10805(define_insn ""
10806 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 10807 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 10808 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 10809 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 10810 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10811 ""
baf97f86
RK		 10812 "#"
10813 [(set_attr "length" "8")])
7e69e155 10814
1fd4e8c1
RK		 10815(define_split
10816 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 10817 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 10818 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 10819 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 10820 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10821 ""
10822 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10823 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10824
10825(define_split
10826 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 10827 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 10828 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 10829 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 10830 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10831 ""
10832 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10833 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10834
acad7ed3 10835(define_insn "*cmpsf_internal1"
1fd4e8c1 10836 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 10837 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10838 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 10839 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 10840 "fcmpu %0,%1,%2"
10841 [(set_attr "type" "fpcompare")])
10842
acad7ed3 10843(define_insn "*cmpdf_internal1"
1fd4e8c1 10844 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 10845 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
10846 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 10847 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 10848 "fcmpu %0,%1,%2"
10849 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 10850
10851;; Only need to compare second words if first words equal
10852(define_insn "*cmptf_internal1"
10853 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10854 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10855 (match_operand:TF 2 "gpc_reg_operand" "f")))]
de17c25f 10856 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
39e63627 10857 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 10858 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 10859 [(set_attr "type" "fpcompare")
10860 (set_attr "length" "12")])
de17c25f
DE		 10861
10862(define_insn_and_split "*cmptf_internal2"
10863 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10864 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10865 (match_operand:TF 2 "gpc_reg_operand" "f")))
10866 (clobber (match_scratch:DF 3 "=f"))
10867 (clobber (match_scratch:DF 4 "=f"))
10868 (clobber (match_scratch:DF 5 "=f"))
10869 (clobber (match_scratch:DF 6 "=f"))
10870 (clobber (match_scratch:DF 7 "=f"))
10871 (clobber (match_scratch:DF 8 "=f"))
10872 (clobber (match_scratch:DF 9 "=f"))
10873 (clobber (match_scratch:DF 10 "=f"))]
10874 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
10875 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10876 "#"
10877 "&& reload_completed"
10878 [(set (match_dup 3) (match_dup 13))
10879 (set (match_dup 4) (match_dup 14))
10880 (set (match_dup 9) (abs:DF (match_dup 5)))
10881 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
10882 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
10883 (label_ref (match_dup 11))
10884 (pc)))
10885 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
10886 (set (pc) (label_ref (match_dup 12)))
10887 (match_dup 11)
10888 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
10889 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
10890 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
10891 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
10892 (match_dup 12)]
10893{
10894 REAL_VALUE_TYPE rv;
10895 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10896 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10897
10898 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
10899 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
10900 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
10901 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
10902 operands[11] = gen_label_rtx ();
10903 operands[12] = gen_label_rtx ();
10904 real_inf (&rv);
10905 operands[13] = force_const_mem (DFmode,
10906 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
10907 operands[14] = force_const_mem (DFmode,
10908 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
10909 DFmode));
10910 if (TARGET_TOC)
10911 {
10912 operands[13] = gen_const_mem (DFmode,
10913 create_TOC_reference (XEXP (operands[13], 0)));
10914 operands[14] = gen_const_mem (DFmode,
10915 create_TOC_reference (XEXP (operands[14], 0)));
10916 set_mem_alias_set (operands[13], get_TOC_alias_set ());
10917 set_mem_alias_set (operands[14], get_TOC_alias_set ());
10918 }
10919})
1fd4e8c1
RK		 10920\f
10921;; Now we have the scc insns. We can do some combinations because of the
10922;; way the machine works.
10923;;
10924;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 10925;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
10926;; cases the insns below which don't use an intermediate CR field will
10927;; be used instead.
1fd4e8c1 10928(define_insn ""
cd2b37d9 10929 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 10930 (match_operator:SI 1 "scc_comparison_operator"
10931 [(match_operand 2 "cc_reg_operand" "y")
10932 (const_int 0)]))]
10933 ""
2c4a9cff
DE		 10934 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
10935 [(set (attr "type")
10936 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
10937 (const_string "mfcrf")
10938 ]
10939 (const_string "mfcr")))
c1618c0c 10940 (set_attr "length" "8")])
1fd4e8c1 10941
423c1189 10942;; Same as above, but get the GT bit.
64022b5d 10943(define_insn "move_from_CR_gt_bit"
423c1189 10944 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
64022b5d 10945 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
423c1189 10946 "TARGET_E500"
64022b5d 10947 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
423c1189 10948 [(set_attr "type" "mfcr")
c1618c0c 10949 (set_attr "length" "8")])
423c1189 10950
a3170dc6
AH		 10951;; Same as above, but get the OV/ORDERED bit.
10952(define_insn "move_from_CR_ov_bit"
10953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 10954 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 10955 "TARGET_ISEL"
b7053a3f 10956 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a 10957 [(set_attr "type" "mfcr")
c1618c0c 10958 (set_attr "length" "8")])
a3170dc6 10959
1fd4e8c1 10960(define_insn ""
9ebbca7d
GK		 10961 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10962 (match_operator:DI 1 "scc_comparison_operator"
10963 [(match_operand 2 "cc_reg_operand" "y")
10964 (const_int 0)]))]
10965 "TARGET_POWERPC64"
2c4a9cff
DE		 10966 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
10967 [(set (attr "type")
10968 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
10969 (const_string "mfcrf")
10970 ]
10971 (const_string "mfcr")))
c1618c0c 10972 (set_attr "length" "8")])
9ebbca7d
GK		 10973
10974(define_insn ""
10975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 10976 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 10977 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 10978 (const_int 0)])
10979 (const_int 0)))
9ebbca7d 10980 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10981 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 10982 "TARGET_32BIT"
9ebbca7d 10983 "@
2c4a9cff 10984 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 10985 #"
b19003d8 10986 [(set_attr "type" "delayed_compare")
c1618c0c 10987 (set_attr "length" "8,16")])
9ebbca7d
GK		 10988
10989(define_split
10990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10991 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10992 [(match_operand 2 "cc_reg_operand" "")
10993 (const_int 0)])
10994 (const_int 0)))
10995 (set (match_operand:SI 3 "gpc_reg_operand" "")
10996 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 10997 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 10998 [(set (match_dup 3)
10999 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11000 (set (match_dup 0)
11001 (compare:CC (match_dup 3)
11002 (const_int 0)))]
11003 "")
1fd4e8c1
RK		 11004
11005(define_insn ""
cd2b37d9 11006 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11007 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11008 [(match_operand 2 "cc_reg_operand" "y")
11009 (const_int 0)])
11010 (match_operand:SI 3 "const_int_operand" "n")))]
11011 ""
11012 "*
11013{
11014 int is_bit = ccr_bit (operands[1], 1);
11015 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11016 int count;
11017
11018 if (is_bit >= put_bit)
11019 count = is_bit - put_bit;
11020 else
11021 count = 32 - (put_bit - is_bit);
11022
89e9f3a8
MM		 11023 operands[4] = GEN_INT (count);
11024 operands[5] = GEN_INT (put_bit);
1fd4e8c1 11025
2c4a9cff 11026 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 11027}"
2c4a9cff
DE		 11028 [(set (attr "type")
11029 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11030 (const_string "mfcrf")
11031 ]
11032 (const_string "mfcr")))
c1618c0c 11033 (set_attr "length" "8")])
1fd4e8c1
RK		 11034
11035(define_insn ""
9ebbca7d 11036 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11037 (compare:CC
11038 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 11039 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 11040 (const_int 0)])
9ebbca7d 11041 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 11042 (const_int 0)))
9ebbca7d 11043 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 11044 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11045 (match_dup 3)))]
ce71f754 11046 ""
1fd4e8c1
RK		 11047 "*
11048{
11049 int is_bit = ccr_bit (operands[1], 1);
11050 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11051 int count;
11052
9ebbca7d
GK		 11053 /* Force split for non-cc0 compare. */
11054 if (which_alternative == 1)
11055 return \"#\";
11056
1fd4e8c1
RK		 11057 if (is_bit >= put_bit)
11058 count = is_bit - put_bit;
11059 else
11060 count = 32 - (put_bit - is_bit);
11061
89e9f3a8
MM		 11062 operands[5] = GEN_INT (count);
11063 operands[6] = GEN_INT (put_bit);
1fd4e8c1 11064
2c4a9cff 11065 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 11066}"
b19003d8 11067 [(set_attr "type" "delayed_compare")
c1618c0c 11068 (set_attr "length" "8,16")])
9ebbca7d
GK		 11069
11070(define_split
11071 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11072 (compare:CC
11073 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11074 [(match_operand 2 "cc_reg_operand" "")
11075 (const_int 0)])
11076 (match_operand:SI 3 "const_int_operand" ""))
11077 (const_int 0)))
11078 (set (match_operand:SI 4 "gpc_reg_operand" "")
11079 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11080 (match_dup 3)))]
ce71f754 11081 "reload_completed"
9ebbca7d
GK		 11082 [(set (match_dup 4)
11083 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11084 (match_dup 3)))
11085 (set (match_dup 0)
11086 (compare:CC (match_dup 4)
11087 (const_int 0)))]
11088 "")
1fd4e8c1 11089
c5defebb
RK		 11090;; There is a 3 cycle delay between consecutive mfcr instructions
11091;; so it is useful to combine 2 scc instructions to use only one mfcr.
11092
11093(define_peephole
cd2b37d9 11094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 11095 (match_operator:SI 1 "scc_comparison_operator"
11096 [(match_operand 2 "cc_reg_operand" "y")
11097 (const_int 0)]))
cd2b37d9 11098 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 11099 (match_operator:SI 4 "scc_comparison_operator"
11100 [(match_operand 5 "cc_reg_operand" "y")
11101 (const_int 0)]))]
309323c2 11102 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 11103 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 11104 [(set_attr "type" "mfcr")
c1618c0c 11105 (set_attr "length" "12")])
c5defebb 11106
9ebbca7d
GK		 11107(define_peephole
11108 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11109 (match_operator:DI 1 "scc_comparison_operator"
11110 [(match_operand 2 "cc_reg_operand" "y")
11111 (const_int 0)]))
11112 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11113 (match_operator:DI 4 "scc_comparison_operator"
11114 [(match_operand 5 "cc_reg_operand" "y")
11115 (const_int 0)]))]
309323c2 11116 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 11117 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 11118 [(set_attr "type" "mfcr")
c1618c0c 11119 (set_attr "length" "12")])
9ebbca7d 11120
1fd4e8c1
RK		 11121;; There are some scc insns that can be done directly, without a compare.
11122;; These are faster because they don't involve the communications between
11123;; the FXU and branch units. In fact, we will be replacing all of the
11124;; integer scc insns here or in the portable methods in emit_store_flag.
11125;;
11126;; Also support (neg (scc ..)) since that construct is used to replace
11127;; branches, (plus (scc ..) ..) since that construct is common and
11128;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11129;; cases where it is no more expensive than (neg (scc ..)).
11130
11131;; Have reload force a constant into a register for the simple insns that
11132;; otherwise won't accept constants. We do this because it is faster than
11133;; the cmp/mfcr sequence we would otherwise generate.
11134
e9441276
DE		 11135(define_mode_attr scc_eq_op2 [(SI "rKLI")
11136 (DI "rKJI")])
a260abc9 11137
e9441276
DE		 11138(define_insn_and_split "*eq<mode>"
11139 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11140 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
d0515b39 11141 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
70ae0191 11142 ""
e9441276 11143 "#"
d0515b39
DE		 11144 ""
11145 [(set (match_dup 0)
11146 (clz:GPR (match_dup 3)))
70ae0191 11147 (set (match_dup 0)
d0515b39 11148 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
70ae0191 11149 {
e9441276
DE		 11150 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11151 {
d0515b39
DE		 11152 /* Use output operand as intermediate. */
11153 operands[3] = operands[0];
11154
e9441276 11155 if (logical_operand (operands[2], <MODE>mode))
d0515b39 11156 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 11157 gen_rtx_XOR (<MODE>mode,
11158 operands[1], operands[2])));
11159 else
d0515b39 11160 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 11161 gen_rtx_PLUS (<MODE>mode, operands[1],
11162 negate_rtx (<MODE>mode,
11163 operands[2]))));
11164 }
11165 else
d0515b39 11166 operands[3] = operands[1];
9ebbca7d 11167
d0515b39 11168 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
e9441276 11169 })
a260abc9 11170
e9441276 11171(define_insn_and_split "*eq<mode>_compare"
d0515b39 11172 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
70ae0191 11173 (compare:CC
1fa5c709
DE		 11174 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11175 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
70ae0191 11176 (const_int 0)))
1fa5c709 11177 (set (match_operand:P 0 "gpc_reg_operand" "=r")
d0515b39 11178 (eq:P (match_dup 1) (match_dup 2)))]
70ae0191 11179 ""
e9441276 11180 "#"
d0515b39
DE		 11181 ""
11182 [(set (match_dup 0)
1fa5c709 11183 (clz:P (match_dup 4)))
d0515b39
DE		 11184 (parallel [(set (match_dup 3)
11185 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
70ae0191
DE		 11186 (const_int 0)))
11187 (set (match_dup 0)
d0515b39 11188 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
70ae0191 11189 {
e9441276
DE		 11190 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11191 {
d0515b39
DE		 11192 /* Use output operand as intermediate. */
11193 operands[4] = operands[0];
11194
e9441276
DE		 11195 if (logical_operand (operands[2], <MODE>mode))
11196 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11197 gen_rtx_XOR (<MODE>mode,
11198 operands[1], operands[2])));
11199 else
11200 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11201 gen_rtx_PLUS (<MODE>mode, operands[1],
11202 negate_rtx (<MODE>mode,
11203 operands[2]))));
11204 }
11205 else
11206 operands[4] = operands[1];
11207
d0515b39 11208 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
70ae0191
DE		 11209 })
11210
b19003d8
RK		 11211;; We have insns of the form shown by the first define_insn below. If
11212;; there is something inside the comparison operation, we must split it.
11213(define_split
11214 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11215 (plus:SI (match_operator 1 "comparison_operator"
11216 [(match_operand:SI 2 "" "")
11217 (match_operand:SI 3
11218 "reg_or_cint_operand" "")])
11219 (match_operand:SI 4 "gpc_reg_operand" "")))
11220 (clobber (match_operand:SI 5 "register_operand" ""))]
11221 "! gpc_reg_operand (operands[2], SImode)"
11222 [(set (match_dup 5) (match_dup 2))
11223 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11224 (match_dup 4)))])
1fd4e8c1
RK		 11225
11226(define_insn ""
5276df18 11227 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 11228 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
56fc483e 11229 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
5276df18 11230 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
683bdff7 11231 "TARGET_32BIT"
1fd4e8c1 11232 "@
5276df18
DE		 11233 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11234 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11235 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11236 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11237 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
943c15ed
DE		 11238 [(set_attr "type" "three,two,three,three,three")
11239 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1
RK		 11240
11241(define_insn ""
9ebbca7d 11242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11243 (compare:CC
1fd4e8c1 11244 (plus:SI
9ebbca7d 11245 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 11246 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 11247 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 11248 (const_int 0)))
9ebbca7d 11249 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
683bdff7 11250 "TARGET_32BIT"
1fd4e8c1 11251 "@
ca7f5001 11252 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 11253 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 11254 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11255 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 11256 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11257 #
11258 #
11259 #
11260 #
11261 #"
b19003d8 11262 [(set_attr "type" "compare")
9ebbca7d
GK		 11263 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11264
11265(define_split
11266 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11267 (compare:CC
11268 (plus:SI
11269 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 11270 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 11271 (match_operand:SI 3 "gpc_reg_operand" ""))
11272 (const_int 0)))
11273 (clobber (match_scratch:SI 4 ""))]
683bdff7 11274 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 11275 [(set (match_dup 4)
11276 (plus:SI (eq:SI (match_dup 1)
11277 (match_dup 2))
11278 (match_dup 3)))
11279 (set (match_dup 0)
11280 (compare:CC (match_dup 4)
11281 (const_int 0)))]
11282 "")
1fd4e8c1
RK		 11283
11284(define_insn ""
0387639b 11285 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11286 (compare:CC
1fd4e8c1 11287 (plus:SI
9ebbca7d 11288 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 11289 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 11290 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 11291 (const_int 0)))
0387639b
DE		 11292 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11293 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 11294 "TARGET_32BIT"
1fd4e8c1 11295 "@
0387639b
DE		 11296 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11297 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11298 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11299 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11300 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 11301 #
11302 #
11303 #
11304 #
11305 #"
11306 [(set_attr "type" "compare")
11307 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11308
11309(define_split
0387639b 11310 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 11311 (compare:CC
11312 (plus:SI
11313 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 11314 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 11315 (match_operand:SI 3 "gpc_reg_operand" ""))
11316 (const_int 0)))
11317 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 11318 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 11319 "TARGET_32BIT && reload_completed"
0387639b 11320 [(set (match_dup 0)
9ebbca7d 11321 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 11322 (set (match_dup 4)
9ebbca7d
GK		 11323 (compare:CC (match_dup 0)
11324 (const_int 0)))]
11325 "")
11326
d0515b39
DE		 11327(define_insn "*neg_eq0<mode>"
11328 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11329 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11330 (const_int 0))))]
11331 ""
11332 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
11333 [(set_attr "type" "two")
11334 (set_attr "length" "8")])
11335
11336(define_insn_and_split "*neg_eq<mode>"
11337 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11338 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
11339 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
11340 ""
11341 "#"
11342 ""
11343 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
11344 {
11345 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11346 {
11347 /* Use output operand as intermediate. */
11348 operands[3] = operands[0];
11349
11350 if (logical_operand (operands[2], <MODE>mode))
11351 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11352 gen_rtx_XOR (<MODE>mode,
11353 operands[1], operands[2])));
11354 else
11355 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11356 gen_rtx_PLUS (<MODE>mode, operands[1],
11357 negate_rtx (<MODE>mode,
11358 operands[2]))));
11359 }
11360 else
11361 operands[3] = operands[1];
11362 })
1fd4e8c1 11363
ea9be077
MM		 11364;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11365;; since it nabs/sr is just as fast.
ce45ef46 11366(define_insn "*ne0si"
b4e95693 11367 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 11368 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11369 (const_int 31)))
11370 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 11371 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077 11372 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
943c15ed
DE		 11373 [(set_attr "type" "two")
11374 (set_attr "length" "8")])
ea9be077 11375
ce45ef46 11376(define_insn "*ne0di"
a260abc9
DE		 11377 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11378 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11379 (const_int 63)))
11380 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 11381 "TARGET_64BIT"
a260abc9 11382 "addic %2,%1,-1\;subfe %0,%2,%1"
943c15ed
DE		 11383 [(set_attr "type" "two")
11384 (set_attr "length" "8")])
a260abc9 11385
1fd4e8c1
RK		 11386;; This is what (plus (ne X (const_int 0)) Y) looks like.
11387(define_insn ""
cd2b37d9 11388 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 11389 (plus:SI (lshiftrt:SI
cd2b37d9 11390 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 11391 (const_int 31))
cd2b37d9 11392 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 11393 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 11394 "TARGET_32BIT"
ca7f5001 11395 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
943c15ed
DE		 11396 [(set_attr "type" "two")
11397 (set_attr "length" "8")])
1fd4e8c1 11398
a260abc9
DE		 11399(define_insn ""
11400 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11401 (plus:DI (lshiftrt:DI
11402 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11403 (const_int 63))
11404 (match_operand:DI 2 "gpc_reg_operand" "r")))
11405 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 11406 "TARGET_64BIT"
a260abc9 11407 "addic %3,%1,-1\;addze %0,%2"
943c15ed
DE		 11408 [(set_attr "type" "two")
11409 (set_attr "length" "8")])
a260abc9 11410
1fd4e8c1 11411(define_insn ""
9ebbca7d 11412 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11413 (compare:CC
11414 (plus:SI (lshiftrt:SI
9ebbca7d 11415 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 11416 (const_int 31))
9ebbca7d 11417 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 11418 (const_int 0)))
889b90a1
GK		 11419 (clobber (match_scratch:SI 3 "=&r,&r"))
11420 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 11421 "TARGET_32BIT"
9ebbca7d
GK		 11422 "@
11423 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11424 #"
b19003d8 11425 [(set_attr "type" "compare")
9ebbca7d
GK		 11426 (set_attr "length" "8,12")])
11427
11428(define_split
11429 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11430 (compare:CC
11431 (plus:SI (lshiftrt:SI
11432 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11433 (const_int 31))
11434 (match_operand:SI 2 "gpc_reg_operand" ""))
11435 (const_int 0)))
889b90a1
GK		 11436 (clobber (match_scratch:SI 3 ""))
11437 (clobber (match_scratch:SI 4 ""))]
683bdff7 11438 "TARGET_32BIT && reload_completed"
889b90a1 11439 [(parallel [(set (match_dup 3)
ce71f754
AM		 11440 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11441 (const_int 31))
11442 (match_dup 2)))
889b90a1 11443 (clobber (match_dup 4))])
9ebbca7d
GK		 11444 (set (match_dup 0)
11445 (compare:CC (match_dup 3)
11446 (const_int 0)))]
11447 "")
1fd4e8c1 11448
a260abc9 11449(define_insn ""
9ebbca7d 11450 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 11451 (compare:CC
11452 (plus:DI (lshiftrt:DI
9ebbca7d 11453 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 11454 (const_int 63))
9ebbca7d 11455 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 11456 (const_int 0)))
9ebbca7d 11457 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 11458 "TARGET_64BIT"
9ebbca7d
GK		 11459 "@
11460 addic %3,%1,-1\;addze. %3,%2
11461 #"
a260abc9 11462 [(set_attr "type" "compare")
9ebbca7d
GK		 11463 (set_attr "length" "8,12")])
11464
11465(define_split
11466 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11467 (compare:CC
11468 (plus:DI (lshiftrt:DI
11469 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11470 (const_int 63))
11471 (match_operand:DI 2 "gpc_reg_operand" ""))
11472 (const_int 0)))
11473 (clobber (match_scratch:DI 3 ""))]
683bdff7 11474 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 11475 [(set (match_dup 3)
11476 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11477 (const_int 63))
11478 (match_dup 2)))
11479 (set (match_dup 0)
11480 (compare:CC (match_dup 3)
11481 (const_int 0)))]
11482 "")
a260abc9 11483
1fd4e8c1 11484(define_insn ""
9ebbca7d 11485 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11486 (compare:CC
11487 (plus:SI (lshiftrt:SI
9ebbca7d 11488 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 11489 (const_int 31))
9ebbca7d 11490 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 11491 (const_int 0)))
9ebbca7d 11492 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 11493 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11494 (match_dup 2)))
9ebbca7d 11495 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 11496 "TARGET_32BIT"
9ebbca7d
GK		 11497 "@
11498 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11499 #"
b19003d8 11500 [(set_attr "type" "compare")
9ebbca7d
GK		 11501 (set_attr "length" "8,12")])
11502
11503(define_split
11504 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11505 (compare:CC
11506 (plus:SI (lshiftrt:SI
11507 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11508 (const_int 31))
11509 (match_operand:SI 2 "gpc_reg_operand" ""))
11510 (const_int 0)))
11511 (set (match_operand:SI 0 "gpc_reg_operand" "")
11512 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11513 (match_dup 2)))
11514 (clobber (match_scratch:SI 3 ""))]
683bdff7 11515 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 11516 [(parallel [(set (match_dup 0)
11517 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11518 (match_dup 2)))
11519 (clobber (match_dup 3))])
11520 (set (match_dup 4)
11521 (compare:CC (match_dup 0)
11522 (const_int 0)))]
11523 "")
1fd4e8c1 11524
a260abc9 11525(define_insn ""
9ebbca7d 11526 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 11527 (compare:CC
11528 (plus:DI (lshiftrt:DI
9ebbca7d 11529 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 11530 (const_int 63))
9ebbca7d 11531 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 11532 (const_int 0)))
9ebbca7d 11533 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 11534 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11535 (match_dup 2)))
9ebbca7d 11536 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 11537 "TARGET_64BIT"
9ebbca7d
GK		 11538 "@
11539 addic %3,%1,-1\;addze. %0,%2
11540 #"
a260abc9 11541 [(set_attr "type" "compare")
9ebbca7d
GK		 11542 (set_attr "length" "8,12")])
11543
11544(define_split
11545 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11546 (compare:CC
11547 (plus:DI (lshiftrt:DI
11548 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11549 (const_int 63))
11550 (match_operand:DI 2 "gpc_reg_operand" ""))
11551 (const_int 0)))
11552 (set (match_operand:DI 0 "gpc_reg_operand" "")
11553 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11554 (match_dup 2)))
11555 (clobber (match_scratch:DI 3 ""))]
683bdff7 11556 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 11557 [(parallel [(set (match_dup 0)
11558 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11559 (match_dup 2)))
11560 (clobber (match_dup 3))])
11561 (set (match_dup 4)
11562 (compare:CC (match_dup 0)
11563 (const_int 0)))]
11564 "")
a260abc9 11565
1fd4e8c1 11566(define_insn ""
cd2b37d9
RK		 11567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11568 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 11569 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11570 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 11571 "TARGET_POWER"
1fd4e8c1 11572 "@
ca7f5001 11573 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 11574 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 11575 [(set_attr "length" "12")])
1fd4e8c1
RK		 11576
11577(define_insn ""
9ebbca7d 11578 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 11579 (compare:CC
9ebbca7d
GK		 11580 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11581 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 11582 (const_int 0)))
9ebbca7d 11583 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 11584 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 11585 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 11586 "TARGET_POWER"
1fd4e8c1 11587 "@
ca7f5001 11588 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 11589 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11590 #
11591 #"
11592 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11593 (set_attr "length" "12,12,16,16")])
11594
11595(define_split
11596 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11597 (compare:CC
11598 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11599 (match_operand:SI 2 "reg_or_short_operand" ""))
11600 (const_int 0)))
11601 (set (match_operand:SI 0 "gpc_reg_operand" "")
11602 (le:SI (match_dup 1) (match_dup 2)))
11603 (clobber (match_scratch:SI 3 ""))]
11604 "TARGET_POWER && reload_completed"
11605 [(parallel [(set (match_dup 0)
11606 (le:SI (match_dup 1) (match_dup 2)))
11607 (clobber (match_dup 3))])
11608 (set (match_dup 4)
11609 (compare:CC (match_dup 0)
11610 (const_int 0)))]
11611 "")
1fd4e8c1
RK		 11612
11613(define_insn ""
097657c3 11614 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 11615 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 11616 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 11617 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 11618 "TARGET_POWER"
1fd4e8c1 11619 "@
097657c3
AM		 11620 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11621 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 11622 [(set_attr "length" "12")])
1fd4e8c1
RK		 11623
11624(define_insn ""
9ebbca7d 11625 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 11626 (compare:CC
9ebbca7d
GK		 11627 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11628 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11629 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 11630 (const_int 0)))
9ebbca7d 11631 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 11632 "TARGET_POWER"
1fd4e8c1 11633 "@
ca7f5001 11634 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 11635 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11636 #
11637 #"
b19003d8 11638 [(set_attr "type" "compare")
9ebbca7d
GK		 11639 (set_attr "length" "12,12,16,16")])
11640
11641(define_split
11642 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11643 (compare:CC
11644 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11645 (match_operand:SI 2 "reg_or_short_operand" ""))
11646 (match_operand:SI 3 "gpc_reg_operand" ""))
11647 (const_int 0)))
11648 (clobber (match_scratch:SI 4 ""))]
11649 "TARGET_POWER && reload_completed"
11650 [(set (match_dup 4)
11651 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 11652 (match_dup 3)))
9ebbca7d
GK		 11653 (set (match_dup 0)
11654 (compare:CC (match_dup 4)
11655 (const_int 0)))]
11656 "")
1fd4e8c1
RK		 11657
11658(define_insn ""
097657c3 11659 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 11660 (compare:CC
9ebbca7d
GK		 11661 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11662 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11663 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 11664 (const_int 0)))
097657c3
AM		 11665 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11666 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 11667 "TARGET_POWER"
1fd4e8c1 11668 "@
097657c3
AM		 11669 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11670 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 11671 #
11672 #"
b19003d8 11673 [(set_attr "type" "compare")
9ebbca7d
GK		 11674 (set_attr "length" "12,12,16,16")])
11675
11676(define_split
097657c3 11677 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 11678 (compare:CC
11679 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11680 (match_operand:SI 2 "reg_or_short_operand" ""))
11681 (match_operand:SI 3 "gpc_reg_operand" ""))
11682 (const_int 0)))
11683 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 11684 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 11685 "TARGET_POWER && reload_completed"
097657c3 11686 [(set (match_dup 0)
9ebbca7d 11687 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 11688 (set (match_dup 4)
9ebbca7d
GK		 11689 (compare:CC (match_dup 0)
11690 (const_int 0)))]
11691 "")
1fd4e8c1
RK		 11692
11693(define_insn ""
cd2b37d9
RK		 11694 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11695 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 11696 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 11697 "TARGET_POWER"
1fd4e8c1 11698 "@
ca7f5001
RK		 11699 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11700 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 11701 [(set_attr "length" "12")])
1fd4e8c1 11702
a2dba291
DE		 11703(define_insn "*leu<mode>"
11704 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11705 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11706 (match_operand:P 2 "reg_or_short_operand" "rI")))]
11707 ""
ca7f5001 11708 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 11709 [(set_attr "type" "three")
11710 (set_attr "length" "12")])
1fd4e8c1 11711
a2dba291 11712(define_insn "*leu<mode>_compare"
9ebbca7d 11713 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 11714 (compare:CC
a2dba291
DE		 11715 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
11716 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 11717 (const_int 0)))
a2dba291
DE		 11718 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
11719 (leu:P (match_dup 1) (match_dup 2)))]
11720 ""
9ebbca7d
GK		 11721 "@
11722 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11723 #"
b19003d8 11724 [(set_attr "type" "compare")
9ebbca7d
GK		 11725 (set_attr "length" "12,16")])
11726
11727(define_split
11728 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11729 (compare:CC
a2dba291
DE		 11730 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
11731 (match_operand:P 2 "reg_or_short_operand" ""))
9ebbca7d 11732 (const_int 0)))
a2dba291
DE		 11733 (set (match_operand:P 0 "gpc_reg_operand" "")
11734 (leu:P (match_dup 1) (match_dup 2)))]
11735 "reload_completed"
9ebbca7d 11736 [(set (match_dup 0)
a2dba291 11737 (leu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 11738 (set (match_dup 3)
11739 (compare:CC (match_dup 0)
11740 (const_int 0)))]
11741 "")
1fd4e8c1 11742
a2dba291
DE		 11743(define_insn "*plus_leu<mode>"
11744 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
11745 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11746 (match_operand:P 2 "reg_or_short_operand" "rI"))
11747 (match_operand:P 3 "gpc_reg_operand" "r")))]
11748 ""
80103f96 11749 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
943c15ed
DE		 11750 [(set_attr "type" "two")
11751 (set_attr "length" "8")])
1fd4e8c1
RK		 11752
11753(define_insn ""
9ebbca7d 11754 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 11755 (compare:CC
9ebbca7d
GK		 11756 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11757 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11758 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 11759 (const_int 0)))
9ebbca7d 11760 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 11761 "TARGET_32BIT"
9ebbca7d
GK		 11762 "@
11763 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11764 #"
b19003d8 11765 [(set_attr "type" "compare")
9ebbca7d
GK		 11766 (set_attr "length" "8,12")])
11767
11768(define_split
11769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11770 (compare:CC
11771 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11772 (match_operand:SI 2 "reg_or_short_operand" ""))
11773 (match_operand:SI 3 "gpc_reg_operand" ""))
11774 (const_int 0)))
11775 (clobber (match_scratch:SI 4 ""))]
683bdff7 11776 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 11777 [(set (match_dup 4)
11778 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11779 (match_dup 3)))
11780 (set (match_dup 0)
11781 (compare:CC (match_dup 4)
11782 (const_int 0)))]
11783 "")
1fd4e8c1
RK		 11784
11785(define_insn ""
097657c3 11786 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 11787 (compare:CC
9ebbca7d
GK		 11788 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11789 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11790 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 11791 (const_int 0)))
097657c3
AM		 11792 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11793 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 11794 "TARGET_32BIT"
9ebbca7d 11795 "@
097657c3 11796 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 11797 #"
b19003d8 11798 [(set_attr "type" "compare")
9ebbca7d
GK		 11799 (set_attr "length" "8,12")])
11800
11801(define_split
097657c3 11802 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 11803 (compare:CC
11804 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11805 (match_operand:SI 2 "reg_or_short_operand" ""))
11806 (match_operand:SI 3 "gpc_reg_operand" ""))
11807 (const_int 0)))
11808 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 11809 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 11810 "TARGET_32BIT && reload_completed"
097657c3 11811 [(set (match_dup 0)
9ebbca7d 11812 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 11813 (set (match_dup 4)
9ebbca7d
GK		 11814 (compare:CC (match_dup 0)
11815 (const_int 0)))]
11816 "")
1fd4e8c1 11817
a2dba291
DE		 11818(define_insn "*neg_leu<mode>"
11819 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11820 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11821 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
11822 ""
ca7f5001 11823 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
943c15ed
DE		 11824 [(set_attr "type" "three")
11825 (set_attr "length" "12")])
1fd4e8c1 11826
a2dba291
DE		 11827(define_insn "*and_neg_leu<mode>"
11828 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
11829 (and:P (neg:P
11830 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11831 (match_operand:P 2 "reg_or_short_operand" "rI")))
11832 (match_operand:P 3 "gpc_reg_operand" "r")))]
11833 ""
097657c3 11834 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 11835 [(set_attr "type" "three")
11836 (set_attr "length" "12")])
1fd4e8c1
RK		 11837
11838(define_insn ""
9ebbca7d 11839 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11840 (compare:CC
11841 (and:SI (neg:SI
9ebbca7d
GK		 11842 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11843 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11844 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 11845 (const_int 0)))
9ebbca7d 11846 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 11847 "TARGET_32BIT"
9ebbca7d
GK		 11848 "@
11849 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11850 #"
11851 [(set_attr "type" "compare")
11852 (set_attr "length" "12,16")])
11853
11854(define_split
11855 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11856 (compare:CC
11857 (and:SI (neg:SI
11858 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11859 (match_operand:SI 2 "reg_or_short_operand" "")))
11860 (match_operand:SI 3 "gpc_reg_operand" ""))
11861 (const_int 0)))
11862 (clobber (match_scratch:SI 4 ""))]
683bdff7 11863 "TARGET_32BIT && reload_completed"
9ebbca7d 11864 [(set (match_dup 4)
097657c3
AM		 11865 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11866 (match_dup 3)))
9ebbca7d
GK		 11867 (set (match_dup 0)
11868 (compare:CC (match_dup 4)
11869 (const_int 0)))]
11870 "")
1fd4e8c1
RK		 11871
11872(define_insn ""
097657c3 11873 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11874 (compare:CC
11875 (and:SI (neg:SI
9ebbca7d
GK		 11876 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11877 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11878 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 11879 (const_int 0)))
097657c3
AM		 11880 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11881 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 11882 "TARGET_32BIT"
9ebbca7d 11883 "@
097657c3 11884 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 11885 #"
b19003d8 11886 [(set_attr "type" "compare")
9ebbca7d
GK		 11887 (set_attr "length" "12,16")])
11888
11889(define_split
097657c3 11890 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 11891 (compare:CC
11892 (and:SI (neg:SI
11893 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11894 (match_operand:SI 2 "reg_or_short_operand" "")))
11895 (match_operand:SI 3 "gpc_reg_operand" ""))
11896 (const_int 0)))
11897 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 11898 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 11899 "TARGET_32BIT && reload_completed"
097657c3
AM		 11900 [(set (match_dup 0)
11901 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11902 (match_dup 3)))
11903 (set (match_dup 4)
9ebbca7d
GK		 11904 (compare:CC (match_dup 0)
11905 (const_int 0)))]
11906 "")
1fd4e8c1
RK		 11907
11908(define_insn ""
cd2b37d9
RK		 11909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11910 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11911 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 11912 "TARGET_POWER"
7f340546 11913 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 11914 [(set_attr "length" "12")])
1fd4e8c1
RK		 11915
11916(define_insn ""
9ebbca7d 11917 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 11918 (compare:CC
9ebbca7d
GK		 11919 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11920 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 11921 (const_int 0)))
9ebbca7d 11922 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 11923 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 11924 "TARGET_POWER"
9ebbca7d
GK		 11925 "@
11926 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11927 #"
29ae5b89 11928 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 11929 (set_attr "length" "12,16")])
11930
11931(define_split
11932 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11933 (compare:CC
11934 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11935 (match_operand:SI 2 "reg_or_short_operand" ""))
11936 (const_int 0)))
11937 (set (match_operand:SI 0 "gpc_reg_operand" "")
11938 (lt:SI (match_dup 1) (match_dup 2)))]
11939 "TARGET_POWER && reload_completed"
11940 [(set (match_dup 0)
11941 (lt:SI (match_dup 1) (match_dup 2)))
11942 (set (match_dup 3)
11943 (compare:CC (match_dup 0)
11944 (const_int 0)))]
11945 "")
1fd4e8c1
RK		 11946
11947(define_insn ""
097657c3 11948 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 11949 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11950 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 11951 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 11952 "TARGET_POWER"
097657c3 11953 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 11954 [(set_attr "length" "12")])
1fd4e8c1
RK		 11955
11956(define_insn ""
9ebbca7d 11957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 11958 (compare:CC
9ebbca7d
GK		 11959 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11960 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11961 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 11962 (const_int 0)))
9ebbca7d 11963 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 11964 "TARGET_POWER"
9ebbca7d
GK		 11965 "@
11966 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
11967 #"
b19003d8 11968 [(set_attr "type" "compare")
9ebbca7d
GK		 11969 (set_attr "length" "12,16")])
11970
11971(define_split
11972 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11973 (compare:CC
11974 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11975 (match_operand:SI 2 "reg_or_short_operand" ""))
11976 (match_operand:SI 3 "gpc_reg_operand" ""))
11977 (const_int 0)))
11978 (clobber (match_scratch:SI 4 ""))]
11979 "TARGET_POWER && reload_completed"
11980 [(set (match_dup 4)
11981 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 11982 (match_dup 3)))
9ebbca7d
GK		 11983 (set (match_dup 0)
11984 (compare:CC (match_dup 4)
11985 (const_int 0)))]
11986 "")
1fd4e8c1
RK		 11987
11988(define_insn ""
097657c3 11989 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 11990 (compare:CC
9ebbca7d
GK		 11991 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11992 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11993 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 11994 (const_int 0)))
097657c3
AM		 11995 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11996 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 11997 "TARGET_POWER"
9ebbca7d 11998 "@
097657c3 11999 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 12000 #"
b19003d8 12001 [(set_attr "type" "compare")
9ebbca7d
GK		 12002 (set_attr "length" "12,16")])
12003
12004(define_split
097657c3 12005 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12006 (compare:CC
12007 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12008 (match_operand:SI 2 "reg_or_short_operand" ""))
12009 (match_operand:SI 3 "gpc_reg_operand" ""))
12010 (const_int 0)))
12011 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12012 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12013 "TARGET_POWER && reload_completed"
097657c3 12014 [(set (match_dup 0)
9ebbca7d 12015 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12016 (set (match_dup 4)
9ebbca7d
GK		 12017 (compare:CC (match_dup 0)
12018 (const_int 0)))]
12019 "")
1fd4e8c1
RK		 12020
12021(define_insn ""
cd2b37d9
RK		 12022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12023 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12024 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 12025 "TARGET_POWER"
12026 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12027 [(set_attr "length" "12")])
1fd4e8c1 12028
ce45ef46
DE		 12029(define_insn_and_split "*ltu<mode>"
12030 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12031 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12032 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12033 ""
c0600ecd 12034 "#"
ce45ef46
DE		 12035 ""
12036 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12037 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 12038 "")
1fd4e8c1 12039
1e24ce83 12040(define_insn_and_split "*ltu<mode>_compare"
9ebbca7d 12041 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12042 (compare:CC
a2dba291
DE		 12043 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12044 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 12045 (const_int 0)))
a2dba291
DE		 12046 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12047 (ltu:P (match_dup 1) (match_dup 2)))]
12048 ""
1e24ce83
DE		 12049 "#"
12050 ""
12051 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12052 (parallel [(set (match_dup 3)
12053 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12054 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 12055 "")
1fd4e8c1 12056
a2dba291
DE		 12057(define_insn_and_split "*plus_ltu<mode>"
12058 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12059 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12060 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
1e24ce83 12061 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
a2dba291 12062 ""
c0600ecd 12063 "#"
04fa46cf 12064 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 12065 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12066 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 12067 "")
1fd4e8c1 12068
1e24ce83 12069(define_insn_and_split "*plus_ltu<mode>_compare"
097657c3 12070 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12071 (compare:CC
1e24ce83
DE		 12072 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12073 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12074 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12075 (const_int 0)))
1e24ce83
DE		 12076 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12077 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12078 ""
12079 "#"
12080 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12081 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12082 (parallel [(set (match_dup 4)
12083 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12084 (const_int 0)))
12085 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 12086 "")
1fd4e8c1 12087
ce45ef46
DE		 12088(define_insn "*neg_ltu<mode>"
12089 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12090 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12091 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12092 ""
c0600ecd
DE		 12093 "@
12094 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12095 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
943c15ed 12096 [(set_attr "type" "two")
c0600ecd 12097 (set_attr "length" "8")])
1fd4e8c1
RK		 12098
12099(define_insn ""
cd2b37d9
RK		 12100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12101 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 12102 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12103 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 12104 "TARGET_POWER"
12105 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 12106 [(set_attr "length" "12")])
1fd4e8c1 12107
9ebbca7d
GK		 12108(define_insn ""
12109 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12110 (compare:CC
9ebbca7d
GK		 12111 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12112 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12113 (const_int 0)))
9ebbca7d 12114 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12115 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12116 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 12117 "TARGET_POWER"
9ebbca7d
GK		 12118 "@
12119 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12120 #"
12121 [(set_attr "type" "compare")
12122 (set_attr "length" "12,16")])
12123
12124(define_split
12125 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12126 (compare:CC
12127 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12128 (match_operand:SI 2 "reg_or_short_operand" ""))
12129 (const_int 0)))
12130 (set (match_operand:SI 0 "gpc_reg_operand" "")
12131 (ge:SI (match_dup 1) (match_dup 2)))
12132 (clobber (match_scratch:SI 3 ""))]
12133 "TARGET_POWER && reload_completed"
12134 [(parallel [(set (match_dup 0)
097657c3
AM		 12135 (ge:SI (match_dup 1) (match_dup 2)))
12136 (clobber (match_dup 3))])
9ebbca7d
GK		 12137 (set (match_dup 4)
12138 (compare:CC (match_dup 0)
12139 (const_int 0)))]
12140 "")
12141
1fd4e8c1 12142(define_insn ""
097657c3 12143 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12144 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12145 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 12146 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 12147 "TARGET_POWER"
097657c3 12148 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 12149 [(set_attr "length" "12")])
1fd4e8c1
RK		 12150
12151(define_insn ""
9ebbca7d 12152 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12153 (compare:CC
9ebbca7d
GK		 12154 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12155 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12156 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12157 (const_int 0)))
9ebbca7d 12158 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 12159 "TARGET_POWER"
9ebbca7d
GK		 12160 "@
12161 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12162 #"
b19003d8 12163 [(set_attr "type" "compare")
9ebbca7d
GK		 12164 (set_attr "length" "12,16")])
12165
12166(define_split
12167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12168 (compare:CC
12169 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12170 (match_operand:SI 2 "reg_or_short_operand" ""))
12171 (match_operand:SI 3 "gpc_reg_operand" ""))
12172 (const_int 0)))
12173 (clobber (match_scratch:SI 4 ""))]
12174 "TARGET_POWER && reload_completed"
12175 [(set (match_dup 4)
12176 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 12177 (match_dup 3)))
9ebbca7d
GK		 12178 (set (match_dup 0)
12179 (compare:CC (match_dup 4)
12180 (const_int 0)))]
12181 "")
1fd4e8c1
RK		 12182
12183(define_insn ""
097657c3 12184 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12185 (compare:CC
9ebbca7d
GK		 12186 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12187 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12188 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12189 (const_int 0)))
097657c3
AM		 12190 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12191 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12192 "TARGET_POWER"
9ebbca7d 12193 "@
097657c3 12194 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 12195 #"
b19003d8 12196 [(set_attr "type" "compare")
9ebbca7d
GK		 12197 (set_attr "length" "12,16")])
12198
12199(define_split
097657c3 12200 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12201 (compare:CC
12202 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12203 (match_operand:SI 2 "reg_or_short_operand" ""))
12204 (match_operand:SI 3 "gpc_reg_operand" ""))
12205 (const_int 0)))
12206 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12207 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12208 "TARGET_POWER && reload_completed"
097657c3 12209 [(set (match_dup 0)
9ebbca7d 12210 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12211 (set (match_dup 4)
9ebbca7d
GK		 12212 (compare:CC (match_dup 0)
12213 (const_int 0)))]
12214 "")
1fd4e8c1
RK		 12215
12216(define_insn ""
cd2b37d9
RK		 12217 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12218 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12219 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 12220 "TARGET_POWER"
12221 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 12222 [(set_attr "length" "12")])
1fd4e8c1 12223
a2dba291
DE		 12224(define_insn "*geu<mode>"
12225 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12226 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12227 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12228 ""
1fd4e8c1 12229 "@
ca7f5001
RK		 12230 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12231 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 12232 [(set_attr "type" "three")
12233 (set_attr "length" "12")])
1fd4e8c1 12234
a2dba291 12235(define_insn "*geu<mode>_compare"
9ebbca7d 12236 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12237 (compare:CC
a2dba291
DE		 12238 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12239 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 12240 (const_int 0)))
a2dba291
DE		 12241 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12242 (geu:P (match_dup 1) (match_dup 2)))]
12243 ""
1fd4e8c1 12244 "@
ca7f5001 12245 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 12246 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12247 #
12248 #"
b19003d8 12249 [(set_attr "type" "compare")
9ebbca7d
GK		 12250 (set_attr "length" "12,12,16,16")])
12251
12252(define_split
12253 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12254 (compare:CC
a2dba291
DE		 12255 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12256 (match_operand:P 2 "reg_or_neg_short_operand" ""))
9ebbca7d 12257 (const_int 0)))
a2dba291
DE		 12258 (set (match_operand:P 0 "gpc_reg_operand" "")
12259 (geu:P (match_dup 1) (match_dup 2)))]
12260 "reload_completed"
9ebbca7d 12261 [(set (match_dup 0)
a2dba291 12262 (geu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 12263 (set (match_dup 3)
12264 (compare:CC (match_dup 0)
12265 (const_int 0)))]
12266 "")
f9562f27 12267
a2dba291
DE		 12268(define_insn "*plus_geu<mode>"
12269 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12270 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12271 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12272 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12273 ""
1fd4e8c1 12274 "@
80103f96
FS		 12275 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12276 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
943c15ed
DE		 12277 [(set_attr "type" "two")
12278 (set_attr "length" "8")])
1fd4e8c1
RK		 12279
12280(define_insn ""
9ebbca7d 12281 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12282 (compare:CC
9ebbca7d
GK		 12283 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12284 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12285 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12286 (const_int 0)))
9ebbca7d 12287 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 12288 "TARGET_32BIT"
1fd4e8c1 12289 "@
ca7f5001 12290 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12291 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12292 #
12293 #"
b19003d8 12294 [(set_attr "type" "compare")
9ebbca7d
GK		 12295 (set_attr "length" "8,8,12,12")])
12296
12297(define_split
12298 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12299 (compare:CC
12300 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12301 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12302 (match_operand:SI 3 "gpc_reg_operand" ""))
12303 (const_int 0)))
12304 (clobber (match_scratch:SI 4 ""))]
683bdff7 12305 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12306 [(set (match_dup 4)
12307 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12308 (match_dup 3)))
12309 (set (match_dup 0)
12310 (compare:CC (match_dup 4)
12311 (const_int 0)))]
12312 "")
1fd4e8c1
RK		 12313
12314(define_insn ""
097657c3 12315 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12316 (compare:CC
9ebbca7d
GK		 12317 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12318 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12319 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12320 (const_int 0)))
097657c3
AM		 12321 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12322 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12323 "TARGET_32BIT"
1fd4e8c1 12324 "@
097657c3
AM		 12325 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12326 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12327 #
12328 #"
b19003d8 12329 [(set_attr "type" "compare")
9ebbca7d
GK		 12330 (set_attr "length" "8,8,12,12")])
12331
12332(define_split
097657c3 12333 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12334 (compare:CC
12335 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12336 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12337 (match_operand:SI 3 "gpc_reg_operand" ""))
12338 (const_int 0)))
12339 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12340 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12341 "TARGET_32BIT && reload_completed"
097657c3 12342 [(set (match_dup 0)
9ebbca7d 12343 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12344 (set (match_dup 4)
9ebbca7d
GK		 12345 (compare:CC (match_dup 0)
12346 (const_int 0)))]
12347 "")
1fd4e8c1 12348
a2dba291
DE		 12349(define_insn "*neg_geu<mode>"
12350 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12351 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12352 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12353 ""
1fd4e8c1 12354 "@
ca7f5001 12355 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 12356 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
943c15ed
DE		 12357 [(set_attr "type" "three")
12358 (set_attr "length" "12")])
1fd4e8c1 12359
a2dba291
DE		 12360(define_insn "*and_neg_geu<mode>"
12361 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12362 (and:P (neg:P
12363 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12364 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12365 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12366 ""
1fd4e8c1 12367 "@
097657c3
AM		 12368 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12369 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 12370 [(set_attr "type" "three")
12371 (set_attr "length" "12")])
1fd4e8c1
RK		 12372
12373(define_insn ""
9ebbca7d 12374 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 12375 (compare:CC
12376 (and:SI (neg:SI
9ebbca7d
GK		 12377 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12378 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12379 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12380 (const_int 0)))
9ebbca7d 12381 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 12382 "TARGET_32BIT"
1fd4e8c1 12383 "@
ca7f5001 12384 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 12385 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12386 #
12387 #"
b19003d8 12388 [(set_attr "type" "compare")
9ebbca7d
GK		 12389 (set_attr "length" "12,12,16,16")])
12390
12391(define_split
12392 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12393 (compare:CC
12394 (and:SI (neg:SI
12395 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12396 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12397 (match_operand:SI 3 "gpc_reg_operand" ""))
12398 (const_int 0)))
12399 (clobber (match_scratch:SI 4 ""))]
683bdff7 12400 "TARGET_32BIT && reload_completed"
9ebbca7d 12401 [(set (match_dup 4)
097657c3
AM		 12402 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12403 (match_dup 3)))
9ebbca7d
GK		 12404 (set (match_dup 0)
12405 (compare:CC (match_dup 4)
12406 (const_int 0)))]
12407 "")
1fd4e8c1
RK		 12408
12409(define_insn ""
097657c3 12410 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 12411 (compare:CC
12412 (and:SI (neg:SI
9ebbca7d
GK		 12413 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12414 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12415 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12416 (const_int 0)))
097657c3
AM		 12417 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12418 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12419 "TARGET_32BIT"
1fd4e8c1 12420 "@
097657c3
AM		 12421 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12422 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 12423 #
12424 #"
b19003d8 12425 [(set_attr "type" "compare")
9ebbca7d
GK		 12426 (set_attr "length" "12,12,16,16")])
12427
12428(define_split
097657c3 12429 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12430 (compare:CC
12431 (and:SI (neg:SI
12432 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12433 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12434 (match_operand:SI 3 "gpc_reg_operand" ""))
12435 (const_int 0)))
12436 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12437 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12438 "TARGET_32BIT && reload_completed"
097657c3 12439 [(set (match_dup 0)
9ebbca7d 12440 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 12441 (set (match_dup 4)
9ebbca7d
GK		 12442 (compare:CC (match_dup 0)
12443 (const_int 0)))]
12444 "")
1fd4e8c1 12445
1fd4e8c1 12446(define_insn ""
cd2b37d9
RK		 12447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12448 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12449 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 12450 "TARGET_POWER"
12451 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12452 [(set_attr "length" "12")])
1fd4e8c1
RK		 12453
12454(define_insn ""
9ebbca7d 12455 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12456 (compare:CC
9ebbca7d
GK		 12457 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12458 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 12459 (const_int 0)))
9ebbca7d 12460 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12461 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 12462 "TARGET_POWER"
9ebbca7d
GK		 12463 "@
12464 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12465 #"
29ae5b89 12466 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 12467 (set_attr "length" "12,16")])
12468
12469(define_split
12470 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12471 (compare:CC
12472 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12473 (match_operand:SI 2 "reg_or_short_operand" ""))
12474 (const_int 0)))
12475 (set (match_operand:SI 0 "gpc_reg_operand" "")
12476 (gt:SI (match_dup 1) (match_dup 2)))]
12477 "TARGET_POWER && reload_completed"
12478 [(set (match_dup 0)
12479 (gt:SI (match_dup 1) (match_dup 2)))
12480 (set (match_dup 3)
12481 (compare:CC (match_dup 0)
12482 (const_int 0)))]
12483 "")
1fd4e8c1 12484
d0515b39 12485(define_insn "*plus_gt0<mode>"
a2dba291
DE		 12486 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12487 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12488 (const_int 0))
12489 (match_operand:P 2 "gpc_reg_operand" "r")))]
12490 ""
80103f96 12491 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
943c15ed
DE		 12492 [(set_attr "type" "three")
12493 (set_attr "length" "12")])
1fd4e8c1
RK		 12494
12495(define_insn ""
9ebbca7d 12496 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12497 (compare:CC
9ebbca7d 12498 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12499 (const_int 0))
9ebbca7d 12500 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12501 (const_int 0)))
9ebbca7d 12502 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 12503 "TARGET_32BIT"
9ebbca7d
GK		 12504 "@
12505 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12506 #"
b19003d8 12507 [(set_attr "type" "compare")
9ebbca7d
GK		 12508 (set_attr "length" "12,16")])
12509
12510(define_split
12511 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12512 (compare:CC
12513 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12514 (const_int 0))
12515 (match_operand:SI 2 "gpc_reg_operand" ""))
12516 (const_int 0)))
12517 (clobber (match_scratch:SI 3 ""))]
683bdff7 12518 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12519 [(set (match_dup 3)
12520 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12521 (match_dup 2)))
12522 (set (match_dup 0)
12523 (compare:CC (match_dup 3)
12524 (const_int 0)))]
12525 "")
1fd4e8c1 12526
f9562f27 12527(define_insn ""
9ebbca7d 12528 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 12529 (compare:CC
9ebbca7d 12530 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 12531 (const_int 0))
9ebbca7d 12532 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 12533 (const_int 0)))
9ebbca7d 12534 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12535 "TARGET_64BIT"
9ebbca7d
GK		 12536 "@
12537 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12538 #"
f9562f27 12539 [(set_attr "type" "compare")
9ebbca7d
GK		 12540 (set_attr "length" "12,16")])
12541
12542(define_split
12543 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12544 (compare:CC
12545 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12546 (const_int 0))
12547 (match_operand:DI 2 "gpc_reg_operand" ""))
12548 (const_int 0)))
12549 (clobber (match_scratch:DI 3 ""))]
683bdff7 12550 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12551 [(set (match_dup 3)
12552 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 12553 (match_dup 2)))
9ebbca7d
GK		 12554 (set (match_dup 0)
12555 (compare:CC (match_dup 3)
12556 (const_int 0)))]
12557 "")
f9562f27 12558
1fd4e8c1 12559(define_insn ""
097657c3 12560 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 12561 (compare:CC
12562 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12563 (const_int 0))
12564 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12565 (const_int 0)))
097657c3
AM		 12566 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12567 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 12568 "TARGET_32BIT"
9ebbca7d 12569 "@
097657c3 12570 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 12571 #"
12572 [(set_attr "type" "compare")
12573 (set_attr "length" "12,16")])
12574
12575(define_split
097657c3 12576 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 12577 (compare:CC
9ebbca7d 12578 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 12579 (const_int 0))
9ebbca7d 12580 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 12581 (const_int 0)))
9ebbca7d 12582 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12583 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 12584 "TARGET_32BIT && reload_completed"
097657c3 12585 [(set (match_dup 0)
9ebbca7d 12586 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 12587 (set (match_dup 3)
9ebbca7d
GK		 12588 (compare:CC (match_dup 0)
12589 (const_int 0)))]
12590 "")
1fd4e8c1 12591
f9562f27 12592(define_insn ""
097657c3 12593 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 12594 (compare:CC
9ebbca7d 12595 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 12596 (const_int 0))
9ebbca7d 12597 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 12598 (const_int 0)))
097657c3
AM		 12599 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12600 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 12601 "TARGET_64BIT"
9ebbca7d 12602 "@
097657c3 12603 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 12604 #"
f9562f27 12605 [(set_attr "type" "compare")
9ebbca7d
GK		 12606 (set_attr "length" "12,16")])
12607
12608(define_split
097657c3 12609 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12610 (compare:CC
12611 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12612 (const_int 0))
12613 (match_operand:DI 2 "gpc_reg_operand" ""))
12614 (const_int 0)))
12615 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 12616 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 12617 "TARGET_64BIT && reload_completed"
097657c3 12618 [(set (match_dup 0)
9ebbca7d 12619 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 12620 (set (match_dup 3)
9ebbca7d
GK		 12621 (compare:CC (match_dup 0)
12622 (const_int 0)))]
12623 "")
f9562f27 12624
1fd4e8c1 12625(define_insn ""
097657c3 12626 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12627 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12628 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 12629 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 12630 "TARGET_POWER"
097657c3 12631 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 12632 [(set_attr "length" "12")])
1fd4e8c1
RK		 12633
12634(define_insn ""
9ebbca7d 12635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12636 (compare:CC
9ebbca7d
GK		 12637 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12638 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12639 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12640 (const_int 0)))
9ebbca7d 12641 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 12642 "TARGET_POWER"
9ebbca7d
GK		 12643 "@
12644 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12645 #"
b19003d8 12646 [(set_attr "type" "compare")
9ebbca7d
GK		 12647 (set_attr "length" "12,16")])
12648
12649(define_split
12650 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12651 (compare:CC
12652 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12653 (match_operand:SI 2 "reg_or_short_operand" ""))
12654 (match_operand:SI 3 "gpc_reg_operand" ""))
12655 (const_int 0)))
12656 (clobber (match_scratch:SI 4 ""))]
12657 "TARGET_POWER && reload_completed"
12658 [(set (match_dup 4)
097657c3 12659 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 12660 (set (match_dup 0)
12661 (compare:CC (match_dup 4)
12662 (const_int 0)))]
12663 "")
1fd4e8c1
RK		 12664
12665(define_insn ""
097657c3 12666 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12667 (compare:CC
9ebbca7d
GK		 12668 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12669 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12670 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12671 (const_int 0)))
097657c3
AM		 12672 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12673 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12674 "TARGET_POWER"
9ebbca7d 12675 "@
097657c3 12676 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 12677 #"
b19003d8 12678 [(set_attr "type" "compare")
9ebbca7d
GK		 12679 (set_attr "length" "12,16")])
12680
12681(define_split
097657c3 12682 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12683 (compare:CC
12684 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12685 (match_operand:SI 2 "reg_or_short_operand" ""))
12686 (match_operand:SI 3 "gpc_reg_operand" ""))
12687 (const_int 0)))
12688 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12689 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12690 "TARGET_POWER && reload_completed"
097657c3 12691 [(set (match_dup 0)
9ebbca7d 12692 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12693 (set (match_dup 4)
9ebbca7d
GK		 12694 (compare:CC (match_dup 0)
12695 (const_int 0)))]
12696 "")
1fd4e8c1 12697
1fd4e8c1 12698(define_insn ""
cd2b37d9
RK		 12699 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12700 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12701 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 12702 "TARGET_POWER"
12703 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12704 [(set_attr "length" "12")])
1fd4e8c1 12705
ce45ef46
DE		 12706(define_insn_and_split "*gtu<mode>"
12707 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12708 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12709 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12710 ""
c0600ecd 12711 "#"
ce45ef46
DE		 12712 ""
12713 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12714 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 12715 "")
f9562f27 12716
1e24ce83 12717(define_insn_and_split "*gtu<mode>_compare"
9ebbca7d 12718 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12719 (compare:CC
a2dba291
DE		 12720 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12721 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12722 (const_int 0)))
a2dba291
DE		 12723 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12724 (gtu:P (match_dup 1) (match_dup 2)))]
12725 ""
1e24ce83
DE		 12726 "#"
12727 ""
12728 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12729 (parallel [(set (match_dup 3)
12730 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12731 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 12732 "")
f9562f27 12733
1e24ce83 12734(define_insn_and_split "*plus_gtu<mode>"
a2dba291
DE		 12735 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12736 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12737 (match_operand:P 2 "reg_or_short_operand" "rI"))
12738 (match_operand:P 3 "reg_or_short_operand" "rI")))]
12739 ""
c0600ecd 12740 "#"
04fa46cf 12741 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 12742 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12743 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 12744 "")
f9562f27 12745
1e24ce83 12746(define_insn_and_split "*plus_gtu<mode>_compare"
097657c3 12747 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 12748 (compare:CC
1e24ce83
DE		 12749 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12750 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
12751 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 12752 (const_int 0)))
1e24ce83
DE		 12753 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12754 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12755 ""
12756 "#"
12757 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12758 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12759 (parallel [(set (match_dup 4)
12760 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12761 (const_int 0)))
12762 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 12763 "")
f9562f27 12764
ce45ef46
DE		 12765(define_insn "*neg_gtu<mode>"
12766 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12767 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12768 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12769 ""
ca7f5001 12770 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
943c15ed 12771 [(set_attr "type" "two")
c0600ecd 12772 (set_attr "length" "8")])
f9562f27 12773
1fd4e8c1
RK		 12774\f
12775;; Define both directions of branch and return. If we need a reload
12776;; register, we'd rather use CR0 since it is much easier to copy a
12777;; register CC value to there.
12778
12779(define_insn ""
12780 [(set (pc)
12781 (if_then_else (match_operator 1 "branch_comparison_operator"
12782 [(match_operand 2
b54cf83a 12783 "cc_reg_operand" "y")
1fd4e8c1
RK		 12784 (const_int 0)])
12785 (label_ref (match_operand 0 "" ""))
12786 (pc)))]
12787 ""
b19003d8
RK		 12788 "*
12789{
12a4e8c5 12790 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 12791}"
12792 [(set_attr "type" "branch")])
12793
1fd4e8c1
RK		 12794(define_insn ""
12795 [(set (pc)
12796 (if_then_else (match_operator 0 "branch_comparison_operator"
12797 [(match_operand 1
b54cf83a 12798 "cc_reg_operand" "y")
1fd4e8c1
RK		 12799 (const_int 0)])
12800 (return)
12801 (pc)))]
12802 "direct_return ()"
12a4e8c5
GK		 12803 "*
12804{
12805 return output_cbranch (operands[0], NULL, 0, insn);
12806}"
b7ff3d82 12807 [(set_attr "type" "branch")
39a10a29 12808 (set_attr "length" "4")])
1fd4e8c1
RK		 12809
12810(define_insn ""
12811 [(set (pc)
12812 (if_then_else (match_operator 1 "branch_comparison_operator"
12813 [(match_operand 2
b54cf83a 12814 "cc_reg_operand" "y")
1fd4e8c1
RK		 12815 (const_int 0)])
12816 (pc)
12817 (label_ref (match_operand 0 "" ""))))]
12818 ""
b19003d8
RK		 12819 "*
12820{
12a4e8c5 12821 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 12822}"
12823 [(set_attr "type" "branch")])
1fd4e8c1
RK		 12824
12825(define_insn ""
12826 [(set (pc)
12827 (if_then_else (match_operator 0 "branch_comparison_operator"
12828 [(match_operand 1
b54cf83a 12829 "cc_reg_operand" "y")
1fd4e8c1
RK		 12830 (const_int 0)])
12831 (pc)
12832 (return)))]
12833 "direct_return ()"
12a4e8c5
GK		 12834 "*
12835{
12836 return output_cbranch (operands[0], NULL, 1, insn);
12837}"
b7ff3d82 12838 [(set_attr "type" "branch")
39a10a29
GK		 12839 (set_attr "length" "4")])
12840
12841;; Logic on condition register values.
12842
12843; This pattern matches things like
12844; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12845; (eq:SI (reg:CCFP 68) (const_int 0)))
12846; (const_int 1)))
12847; which are generated by the branch logic.
b54cf83a 12848; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29 12849
423c1189 12850(define_insn "*cceq_ior_compare"
b54cf83a 12851 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 12852 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 12853 [(match_operator:SI 2
39a10a29
GK		 12854 "branch_positive_comparison_operator"
12855 [(match_operand 3
b54cf83a 12856 "cc_reg_operand" "y,y")
39a10a29 12857 (const_int 0)])
b54cf83a 12858 (match_operator:SI 4
39a10a29
GK		 12859 "branch_positive_comparison_operator"
12860 [(match_operand 5
b54cf83a 12861 "cc_reg_operand" "0,y")
39a10a29
GK		 12862 (const_int 0)])])
12863 (const_int 1)))]
24fab1d3 12864 ""
39a10a29 12865 "cr%q1 %E0,%j2,%j4"
b54cf83a 12866 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 12867
12868; Why is the constant -1 here, but 1 in the previous pattern?
12869; Because ~1 has all but the low bit set.
12870(define_insn ""
b54cf83a 12871 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 12872 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 12873 [(not:SI (match_operator:SI 2
39a10a29
GK		 12874 "branch_positive_comparison_operator"
12875 [(match_operand 3
b54cf83a 12876 "cc_reg_operand" "y,y")
39a10a29
GK		 12877 (const_int 0)]))
12878 (match_operator:SI 4
12879 "branch_positive_comparison_operator"
12880 [(match_operand 5
b54cf83a 12881 "cc_reg_operand" "0,y")
39a10a29
GK		 12882 (const_int 0)])])
12883 (const_int -1)))]
12884 ""
12885 "cr%q1 %E0,%j2,%j4"
b54cf83a 12886 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29 12887
423c1189 12888(define_insn "*cceq_rev_compare"
b54cf83a 12889 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 12890 (compare:CCEQ (match_operator:SI 1
39a10a29 12891 "branch_positive_comparison_operator"
6c873122 12892 [(match_operand 2
b54cf83a 12893 "cc_reg_operand" "0,y")
39a10a29
GK		 12894 (const_int 0)])
12895 (const_int 0)))]
423c1189 12896 ""
251b3667 12897 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 12898 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 12899
12900;; If we are comparing the result of two comparisons, this can be done
12901;; using creqv or crxor.
12902
12903(define_insn_and_split ""
12904 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12905 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12906 [(match_operand 2 "cc_reg_operand" "y")
12907 (const_int 0)])
12908 (match_operator 3 "branch_comparison_operator"
12909 [(match_operand 4 "cc_reg_operand" "y")
12910 (const_int 0)])))]
12911 ""
12912 "#"
12913 ""
12914 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12915 (match_dup 5)))]
12916 "
12917{
12918 int positive_1, positive_2;
12919
364849ee
DE		 12920 positive_1 = branch_positive_comparison_operator (operands[1],
12921 GET_MODE (operands[1]));
12922 positive_2 = branch_positive_comparison_operator (operands[3],
12923 GET_MODE (operands[3]));
39a10a29
GK		 12924
12925 if (! positive_1)
1c563bed 12926 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
0f4c242b
KH		 12927 GET_CODE (operands[1])),
12928 SImode,
12929 operands[2], const0_rtx);
39a10a29 12930 else if (GET_MODE (operands[1]) != SImode)
0f4c242b
KH		 12931 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
12932 operands[2], const0_rtx);
39a10a29
GK		 12933
12934 if (! positive_2)
1c563bed 12935 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
0f4c242b
KH		 12936 GET_CODE (operands[3])),
12937 SImode,
12938 operands[4], const0_rtx);
39a10a29 12939 else if (GET_MODE (operands[3]) != SImode)
0f4c242b
KH		 12940 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
12941 operands[4], const0_rtx);
39a10a29
GK		 12942
12943 if (positive_1 == positive_2)
251b3667
DE		 12944 {
12945 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12946 operands[5] = constm1_rtx;
12947 }
12948 else
12949 {
12950 operands[5] = const1_rtx;
12951 }
39a10a29 12952}")
1fd4e8c1
RK		 12953
12954;; Unconditional branch and return.
12955
12956(define_insn "jump"
12957 [(set (pc)
12958 (label_ref (match_operand 0 "" "")))]
12959 ""
b7ff3d82
DE		 12960 "b %l0"
12961 [(set_attr "type" "branch")])
1fd4e8c1
RK		 12962
12963(define_insn "return"
12964 [(return)]
12965 "direct_return ()"
324e52cc
TG		 12966 "{br|blr}"
12967 [(set_attr "type" "jmpreg")])
1fd4e8c1 12968
0ad91047 12969(define_expand "indirect_jump"
4ae234b0 12970 [(set (pc) (match_operand 0 "register_operand" ""))])
0ad91047 12971
4ae234b0
GK		 12972(define_insn "*indirect_jump<mode>"
12973 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
12974 ""
b92b324d
DE		 12975 "@
12976 bctr
12977 {br|blr}"
324e52cc 12978 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 12979
12980;; Table jump for switch statements:
12981(define_expand "tablejump"
e6ca2c17
DE		 12982 [(use (match_operand 0 "" ""))
12983 (use (label_ref (match_operand 1 "" "")))]
12984 ""
12985 "
12986{
12987 if (TARGET_32BIT)
12988 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
12989 else
12990 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
12991 DONE;
12992}")
12993
12994(define_expand "tablejumpsi"
1fd4e8c1
RK		 12995 [(set (match_dup 3)
12996 (plus:SI (match_operand:SI 0 "" "")
12997 (match_dup 2)))
12998 (parallel [(set (pc) (match_dup 3))
12999 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 13000 "TARGET_32BIT"
1fd4e8c1
RK		 13001 "
13002{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 13003 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 13004 operands[3] = gen_reg_rtx (SImode);
13005}")
13006
e6ca2c17 13007(define_expand "tablejumpdi"
6ae08853 13008 [(set (match_dup 4)
9ebbca7d
GK		 13009 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13010 (set (match_dup 3)
13011 (plus:DI (match_dup 4)
e6ca2c17
DE		 13012 (match_dup 2)))
13013 (parallel [(set (pc) (match_dup 3))
13014 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 13015 "TARGET_64BIT"
e6ca2c17 13016 "
9ebbca7d 13017{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 13018 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 13019 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 13020}")
13021
ce45ef46 13022(define_insn "*tablejump<mode>_internal1"
1fd4e8c1 13023 [(set (pc)
4ae234b0 13024 (match_operand:P 0 "register_operand" "c,*l"))
1fd4e8c1 13025 (use (label_ref (match_operand 1 "" "")))]
4ae234b0 13026 ""
c859cda6
DJ		 13027 "@
13028 bctr
13029 {br|blr}"
a6845123 13030 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 13031
13032(define_insn "nop"
13033 [(const_int 0)]
13034 ""
ca7f5001 13035 "{cror 0,0,0|nop}")
1fd4e8c1 13036\f
7e69e155 13037;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 13038;; so loop.c knows what to generate.
13039
5527bf14
RH		 13040(define_expand "doloop_end"
13041 [(use (match_operand 0 "" "")) ; loop pseudo
13042 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13043 (use (match_operand 2 "" "")) ; max iterations
13044 (use (match_operand 3 "" "")) ; loop level
13045 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 13046 ""
13047 "
13048{
5527bf14
RH		 13049 /* Only use this on innermost loops. */
13050 if (INTVAL (operands[3]) > 1)
13051 FAIL;
683bdff7 13052 if (TARGET_64BIT)
5527bf14
RH		 13053 {
13054 if (GET_MODE (operands[0]) != DImode)
13055 FAIL;
13056 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13057 }
0ad91047 13058 else
5527bf14
RH		 13059 {
13060 if (GET_MODE (operands[0]) != SImode)
13061 FAIL;
13062 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13063 }
0ad91047
DE		 13064 DONE;
13065}")
13066
4ae234b0 13067(define_expand "ctr<mode>"
3cb999d8 13068 [(parallel [(set (pc)
4ae234b0 13069 (if_then_else (ne (match_operand:P 0 "register_operand" "")
3cb999d8
DE		 13070 (const_int 1))
13071 (label_ref (match_operand 1 "" ""))
13072 (pc)))
b6c9286a 13073 (set (match_dup 0)
4ae234b0 13074 (plus:P (match_dup 0)
b6c9286a 13075 (const_int -1)))
5f81043f 13076 (clobber (match_scratch:CC 2 ""))
4ae234b0
GK		 13077 (clobber (match_scratch:P 3 ""))])]
13078 ""
61c07d3c 13079 "")
c225ba7b 13080
1fd4e8c1
RK		 13081;; We need to be able to do this for any operand, including MEM, or we
13082;; will cause reload to blow up since we don't allow output reloads on
7e69e155 13083;; JUMP_INSNs.
0ad91047 13084;; For the length attribute to be calculated correctly, the
5f81043f
RK		 13085;; label MUST be operand 0.
13086
4ae234b0 13087(define_insn "*ctr<mode>_internal1"
0ad91047 13088 [(set (pc)
4ae234b0 13089 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 13090 (const_int 1))
13091 (label_ref (match_operand 0 "" ""))
13092 (pc)))
4ae234b0
GK		 13093 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13094 (plus:P (match_dup 1)
0ad91047 13095 (const_int -1)))
43b68ce5 13096 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 13097 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13098 ""
0ad91047
DE		 13099 "*
13100{
13101 if (which_alternative != 0)
13102 return \"#\";
856a6884 13103 else if (get_attr_length (insn) == 4)
0ad91047
DE		 13104 return \"{bdn|bdnz} %l0\";
13105 else
f607bc57 13106 return \"bdz $+8\;b %l0\";
0ad91047
DE		 13107}"
13108 [(set_attr "type" "branch")
5a195cb5 13109 (set_attr "length" "*,12,16,16")])
0ad91047 13110
4ae234b0 13111(define_insn "*ctr<mode>_internal2"
0ad91047 13112 [(set (pc)
4ae234b0 13113 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 13114 (const_int 1))
13115 (pc)
13116 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 13117 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13118 (plus:P (match_dup 1)
0ad91047 13119 (const_int -1)))
43b68ce5 13120 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 13121 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13122 ""
5f81043f
RK		 13123 "*
13124{
13125 if (which_alternative != 0)
13126 return \"#\";
856a6884 13127 else if (get_attr_length (insn) == 4)
5f81043f
RK		 13128 return \"bdz %l0\";
13129 else
f607bc57 13130 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 13131}"
13132 [(set_attr "type" "branch")
5a195cb5 13133 (set_attr "length" "*,12,16,16")])
5f81043f 13134
0ad91047
DE		 13135;; Similar but use EQ
13136
4ae234b0 13137(define_insn "*ctr<mode>_internal5"
5f81043f 13138 [(set (pc)
4ae234b0 13139 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 13140 (const_int 1))
a6845123 13141 (label_ref (match_operand 0 "" ""))
1fd4e8c1 13142 (pc)))
4ae234b0
GK		 13143 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13144 (plus:P (match_dup 1)
0ad91047 13145 (const_int -1)))
43b68ce5 13146 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 13147 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13148 ""
0ad91047
DE		 13149 "*
13150{
13151 if (which_alternative != 0)
13152 return \"#\";
856a6884 13153 else if (get_attr_length (insn) == 4)
0ad91047
DE		 13154 return \"bdz %l0\";
13155 else
f607bc57 13156 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 13157}"
13158 [(set_attr "type" "branch")
5a195cb5 13159 (set_attr "length" "*,12,16,16")])
0ad91047 13160
4ae234b0 13161(define_insn "*ctr<mode>_internal6"
0ad91047 13162 [(set (pc)
4ae234b0 13163 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 13164 (const_int 1))
13165 (pc)
13166 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 13167 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13168 (plus:P (match_dup 1)
0ad91047 13169 (const_int -1)))
43b68ce5 13170 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 13171 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13172 ""
5f81043f
RK		 13173 "*
13174{
13175 if (which_alternative != 0)
13176 return \"#\";
856a6884 13177 else if (get_attr_length (insn) == 4)
5f81043f
RK		 13178 return \"{bdn|bdnz} %l0\";
13179 else
f607bc57 13180 return \"bdz $+8\;b %l0\";
5f81043f
RK		 13181}"
13182 [(set_attr "type" "branch")
5a195cb5 13183 (set_attr "length" "*,12,16,16")])
5f81043f 13184
0ad91047
DE		 13185;; Now the splitters if we could not allocate the CTR register
13186
1fd4e8c1
RK		 13187(define_split
13188 [(set (pc)
13189 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 13190 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 13191 (const_int 1)])
61c07d3c
DE		 13192 (match_operand 5 "" "")
13193 (match_operand 6 "" "")))
4ae234b0
GK		 13194 (set (match_operand:P 0 "gpc_reg_operand" "")
13195 (plus:P (match_dup 1) (const_int -1)))
0ad91047 13196 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 13197 (clobber (match_scratch:P 4 ""))]
13198 "reload_completed"
0ad91047 13199 [(parallel [(set (match_dup 3)
4ae234b0 13200 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 13201 (const_int -1))
13202 (const_int 0)))
13203 (set (match_dup 0)
4ae234b0 13204 (plus:P (match_dup 1)
0ad91047 13205 (const_int -1)))])
61c07d3c
DE		 13206 (set (pc) (if_then_else (match_dup 7)
13207 (match_dup 5)
13208 (match_dup 6)))]
0ad91047 13209 "
0f4c242b
KH		 13210{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13211 operands[3], const0_rtx); }")
0ad91047
DE		 13212
13213(define_split
13214 [(set (pc)
13215 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 13216 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 13217 (const_int 1)])
61c07d3c
DE		 13218 (match_operand 5 "" "")
13219 (match_operand 6 "" "")))
4ae234b0
GK		 13220 (set (match_operand:P 0 "nonimmediate_operand" "")
13221 (plus:P (match_dup 1) (const_int -1)))
0ad91047 13222 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 13223 (clobber (match_scratch:P 4 ""))]
13224 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
0ad91047 13225 [(parallel [(set (match_dup 3)
4ae234b0 13226 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 13227 (const_int -1))
13228 (const_int 0)))
13229 (set (match_dup 4)
4ae234b0 13230 (plus:P (match_dup 1)
0ad91047
DE		 13231 (const_int -1)))])
13232 (set (match_dup 0)
13233 (match_dup 4))
61c07d3c
DE		 13234 (set (pc) (if_then_else (match_dup 7)
13235 (match_dup 5)
13236 (match_dup 6)))]
0ad91047 13237 "
0f4c242b
KH		 13238{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13239 operands[3], const0_rtx); }")
e0cd0770
JC		 13240\f
13241(define_insn "trap"
13242 [(trap_if (const_int 1) (const_int 0))]
13243 ""
13244 "{t 31,0,0|trap}")
13245
13246(define_expand "conditional_trap"
13247 [(trap_if (match_operator 0 "trap_comparison_operator"
13248 [(match_dup 2) (match_dup 3)])
13249 (match_operand 1 "const_int_operand" ""))]
13250 ""
13251 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13252 operands[2] = rs6000_compare_op0;
13253 operands[3] = rs6000_compare_op1;")
13254
13255(define_insn ""
13256 [(trap_if (match_operator 0 "trap_comparison_operator"
4ae234b0
GK		 13257 [(match_operand:GPR 1 "register_operand" "r")
13258 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
e0cd0770
JC		 13259 (const_int 0))]
13260 ""
4ae234b0 13261 "{t|t<wd>}%V0%I2 %1,%2")
9ebbca7d
GK		 13262\f
13263;; Insns related to generating the function prologue and epilogue.
13264
13265(define_expand "prologue"
13266 [(use (const_int 0))]
13267 "TARGET_SCHED_PROLOG"
13268 "
13269{
13270 rs6000_emit_prologue ();
13271 DONE;
13272}")
13273
2c4a9cff
DE		 13274(define_insn "*movesi_from_cr_one"
13275 [(match_parallel 0 "mfcr_operation"
13276 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13277 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13278 (match_operand 3 "immediate_operand" "n")]
13279 UNSPEC_MOVESI_FROM_CR))])]
13280 "TARGET_MFCRF"
13281 "*
13282{
13283 int mask = 0;
13284 int i;
13285 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13286 {
13287 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13288 operands[4] = GEN_INT (mask);
13289 output_asm_insn (\"mfcr %1,%4\", operands);
13290 }
13291 return \"\";
13292}"
13293 [(set_attr "type" "mfcrf")])
13294
9ebbca7d
GK		 13295(define_insn "movesi_from_cr"
13296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 13297 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
615158e2
JJ		 13298 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
13299 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 13300 ""
309323c2 13301 "mfcr %0"
b54cf83a 13302 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 13303
13304(define_insn "*stmw"
e033a023
DE		 13305 [(match_parallel 0 "stmw_operation"
13306 [(set (match_operand:SI 1 "memory_operand" "=m")
13307 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13308 "TARGET_MULTIPLE"
13309 "{stm|stmw} %2,%1")
6ae08853 13310
4ae234b0 13311(define_insn "*save_fpregs_<mode>"
85d346f1 13312 [(match_parallel 0 "any_parallel_operand"
4ae234b0
GK		 13313 [(clobber (match_operand:P 1 "register_operand" "=l"))
13314 (use (match_operand:P 2 "call_operand" "s"))
e033a023
DE		 13315 (set (match_operand:DF 3 "memory_operand" "=m")
13316 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
4ae234b0 13317 ""
e033a023
DE		 13318 "bl %z2"
13319 [(set_attr "type" "branch")
13320 (set_attr "length" "4")])
9ebbca7d
GK		 13321
13322; These are to explain that changes to the stack pointer should
13323; not be moved over stores to stack memory.
13324(define_insn "stack_tie"
13325 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 13326 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 13327 ""
13328 ""
13329 [(set_attr "length" "0")])
13330
13331
13332(define_expand "epilogue"
13333 [(use (const_int 0))]
13334 "TARGET_SCHED_PROLOG"
13335 "
13336{
13337 rs6000_emit_epilogue (FALSE);
13338 DONE;
13339}")
13340
13341; On some processors, doing the mtcrf one CC register at a time is
13342; faster (like on the 604e). On others, doing them all at once is
13343; faster; for instance, on the 601 and 750.
13344
13345(define_expand "movsi_to_cr_one"
35aba846
DE		 13346 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13347 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2 13348 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 13349 ""
13350 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 13351
13352(define_insn "*movsi_to_cr"
35aba846
DE		 13353 [(match_parallel 0 "mtcrf_operation"
13354 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13355 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13356 (match_operand 3 "immediate_operand" "n")]
615158e2 13357 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 13358 ""
e35b9579
GK		 13359 "*
13360{
13361 int mask = 0;
13362 int i;
13363 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13364 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13365 operands[4] = GEN_INT (mask);
13366 return \"mtcrf %4,%2\";
309323c2 13367}"
b54cf83a 13368 [(set_attr "type" "mtcr")])
9ebbca7d 13369
b54cf83a 13370(define_insn "*mtcrfsi"
309323c2
DE		 13371 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13372 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 13373 (match_operand 2 "immediate_operand" "n")]
13374 UNSPEC_MOVESI_TO_CR))]
6ae08853 13375 "GET_CODE (operands[0]) == REG
309323c2
DE		 13376 && CR_REGNO_P (REGNO (operands[0]))
13377 && GET_CODE (operands[2]) == CONST_INT
13378 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13379 "mtcrf %R0,%1"
b54cf83a 13380 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 13381
13382; The load-multiple instructions have similar properties.
13383; Note that "load_multiple" is a name known to the machine-independent
13384; code that actually corresponds to the powerpc load-string.
13385
13386(define_insn "*lmw"
35aba846
DE		 13387 [(match_parallel 0 "lmw_operation"
13388 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13389 (match_operand:SI 2 "memory_operand" "m"))])]
13390 "TARGET_MULTIPLE"
13391 "{lm|lmw} %1,%2")
6ae08853 13392
4ae234b0 13393(define_insn "*return_internal_<mode>"
e35b9579 13394 [(return)
4ae234b0
GK		 13395 (use (match_operand:P 0 "register_operand" "lc"))]
13396 ""
cccf3bdc 13397 "b%T0"
9ebbca7d
GK		 13398 [(set_attr "type" "jmpreg")])
13399
13400; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
85d346f1 13401; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
9ebbca7d 13402
4ae234b0 13403(define_insn "*return_and_restore_fpregs_<mode>"
85d346f1 13404 [(match_parallel 0 "any_parallel_operand"
e35b9579 13405 [(return)
4ae234b0
GK		 13406 (use (match_operand:P 1 "register_operand" "l"))
13407 (use (match_operand:P 2 "call_operand" "s"))
9ebbca7d
GK		 13408 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13409 (match_operand:DF 4 "memory_operand" "m"))])]
4ae234b0 13410 ""
9ebbca7d
GK		 13411 "b %z2")
13412
83720594
RH		 13413; This is used in compiling the unwind routines.
13414(define_expand "eh_return"
34dc173c 13415 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 13416 ""
13417 "
13418{
83720594 13419 if (TARGET_32BIT)
34dc173c 13420 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 13421 else
34dc173c 13422 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 13423 DONE;
13424}")
13425
83720594 13426; We can't expand this before we know where the link register is stored.
4ae234b0
GK		 13427(define_insn "eh_set_lr_<mode>"
13428 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
615158e2 13429 UNSPECV_EH_RR)
4ae234b0
GK		 13430 (clobber (match_scratch:P 1 "=&b"))]
13431 ""
83720594 13432 "#")
9ebbca7d
GK		 13433
13434(define_split
615158e2 13435 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 13436 (clobber (match_scratch 1 ""))]
13437 "reload_completed"
13438 [(const_int 0)]
9ebbca7d
GK		 13439 "
13440{
d1d0c603 13441 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 13442 DONE;
13443}")
0ac081f6 13444
01a2ccd0 13445(define_insn "prefetch"
3256a76e 13446 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
6041bf2f
DE		 13447 (match_operand:SI 1 "const_int_operand" "n")
13448 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 13449 "TARGET_POWERPC"
6041bf2f
DE		 13450 "*
13451{
01a2ccd0
DE		 13452 if (GET_CODE (operands[0]) == REG)
13453 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13454 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 13455}"
13456 [(set_attr "type" "load")])
915167f5 13457\f
a3170dc6 13458
f565b0a1 13459(include "sync.md")
10ed84db 13460(include "altivec.md")
a3170dc6 13461(include "spe.md")
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