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lib1funcs.asm (div0): Use ARM_FUNC_START and do_push.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
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996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
8ef65e3d 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
602ea4d3 4;; Free Software Foundation, Inc.
996a5f59 5;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 6
5de601cf 7;; This file is part of GCC.
1fd4e8c1 8
5de601cf
NC		 9;; GCC is free software; you can redistribute it and/or modify it
10;; under the terms of the GNU General Public License as published
11;; by the Free Software Foundation; either version 2, or (at your
12;; option) any later version.
1fd4e8c1 13
5de601cf
NC		 14;; GCC is distributed in the hope that it will be useful, but WITHOUT
15;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17;; License for more details.
1fd4e8c1
RK		 18
19;; You should have received a copy of the GNU General Public License
5de601cf 20;; along with GCC; see the file COPYING. If not, write to the
39d14dda
KC		 21;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22;; MA 02110-1301, USA.
1fd4e8c1
RK		 23
24;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 25
615158e2
JJ		 26;;
27;; UNSPEC usage
28;;
29
30(define_constants
31 [(UNSPEC_FRSP 0) ; frsp for POWER machines
32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MOVSI_GOT 8)
36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_FCTIWZ 10)
9719f3b7
DE		 38 (UNSPEC_FRIM 11)
39 (UNSPEC_FRIN 12)
40 (UNSPEC_FRIP 13)
41 (UNSPEC_FRIZ 14)
615158e2
JJ		 42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
44 (UNSPEC_TLSGD 17)
45 (UNSPEC_TLSLD 18)
46 (UNSPEC_MOVESI_FROM_CR 19)
47 (UNSPEC_MOVESI_TO_CR 20)
48 (UNSPEC_TLSDTPREL 21)
49 (UNSPEC_TLSDTPRELHA 22)
50 (UNSPEC_TLSDTPRELLO 23)
51 (UNSPEC_TLSGOTDTPREL 24)
52 (UNSPEC_TLSTPREL 25)
53 (UNSPEC_TLSTPRELHA 26)
54 (UNSPEC_TLSTPRELLO 27)
55 (UNSPEC_TLSGOTTPREL 28)
56 (UNSPEC_TLSTLS 29)
ecb62ae7 57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
cef6b86c 58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
da4c340c 59 (UNSPEC_STFIWX 32)
9f0076e5
DE		 60 (UNSPEC_POPCNTB 33)
61 (UNSPEC_FRES 34)
62 (UNSPEC_SP_SET 35)
63 (UNSPEC_SP_TEST 36)
64 (UNSPEC_SYNC 37)
65 (UNSPEC_LWSYNC 38)
66 (UNSPEC_ISYNC 39)
67 (UNSPEC_SYNC_OP 40)
68 (UNSPEC_ATOMIC 41)
69 (UNSPEC_CMPXCHG 42)
70 (UNSPEC_XCHG 43)
71 (UNSPEC_AND 44)
716019c0
JM		 72 (UNSPEC_DLMZB 45)
73 (UNSPEC_DLMZB_CR 46)
74 (UNSPEC_DLMZB_STRLEN 47)
615158e2
JJ		 75 ])
76
77;;
78;; UNSPEC_VOLATILE usage
79;;
80
81(define_constants
82 [(UNSPECV_BLOCK 0)
b52110d4
DE		 83 (UNSPECV_LL 1) ; load-locked
84 (UNSPECV_SC 2) ; store-conditional
615158e2
JJ		 85 (UNSPECV_EH_RR 9) ; eh_reg_restore
86 ])
1fd4e8c1
RK		 87\f
88;; Define an insn type attribute. This is used in function unit delay
89;; computations.
44cd321e 90(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
1fd4e8c1
RK		 91 (const_string "integer"))
92
b19003d8 93;; Length (in bytes).
6ae08853 94; '(pc)' in the following doesn't include the instruction itself; it is
6cbadf36 95; calculated as if the instruction had zero size.
b19003d8
RK		 96(define_attr "length" ""
97 (if_then_else (eq_attr "type" "branch")
6cbadf36 98 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 99 (const_int -32768))
6cbadf36
GK		 100 (lt (minus (match_dup 0) (pc))
101 (const_int 32764)))
39a10a29
GK		 102 (const_int 4)
103 (const_int 8))
b19003d8
RK		 104 (const_int 4)))
105
cfb557c4
RK		 106;; Processor type -- this attribute must exactly match the processor_type
107;; enumeration in rs6000.h.
108
d296e02e 109(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
cfb557c4
RK		 110 (const (symbol_ref "rs6000_cpu_attr")))
111
d296e02e
AP		 112
113;; If this instruction is microcoded on the CELL processor
114; The default for load and stores is conditional
115; The default for load extended and the recorded instructions is always microcoded
116(define_attr "cell_micro" "not,conditional,always"
117 (if_then_else (ior (ior (eq_attr "type" "load")
118 (eq_attr "type" "store"))
119 (ior (eq_attr "type" "fpload")
120 (eq_attr "type" "fpstore")))
121 (const_string "conditional")
122 (if_then_else (ior (eq_attr "type" "load_ext")
123 (ior (eq_attr "type" "compare")
124 (eq_attr "type" "delayed_compare")))
125 (const_string "always")
126 (const_string "not"))))
127
128
b54cf83a
DE		 129(automata_option "ndfa")
130
131(include "rios1.md")
132(include "rios2.md")
133(include "rs64.md")
134(include "mpc.md")
135(include "40x.md")
02ca7595 136(include "440.md")
b54cf83a
DE		 137(include "603.md")
138(include "6xx.md")
139(include "7xx.md")
140(include "7450.md")
5e8006fa 141(include "8540.md")
b54cf83a 142(include "power4.md")
ec507f2d 143(include "power5.md")
44cd321e 144(include "power6.md")
d296e02e 145(include "cell.md")
48d72335
DE		 146
147(include "predicates.md")
279bb624 148(include "constraints.md")
48d72335 149
ac9e2cff 150(include "darwin.md")
309323c2 151
1fd4e8c1 152\f
915167f5
GK		 153;; Mode macros
154
155; This mode macro allows :GPR to be used to indicate the allowable size
156; of whole values in GPRs.
157(define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
158
0354e5d8 159; Any supported integer mode.
915167f5
GK		 160(define_mode_macro INT [QI HI SI DI TI])
161
0354e5d8 162; Any supported integer mode that fits in one register.
915167f5
GK		 163(define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
164
b5568f07
DE		 165; extend modes for DImode
166(define_mode_macro QHSI [QI HI SI])
167
0354e5d8
GK		 168; SImode or DImode, even if DImode doesn't fit in GPRs.
169(define_mode_macro SDI [SI DI])
170
171; The size of a pointer. Also, the size of the value that a record-condition
172; (one with a '.') will compare.
173(define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
2e6c9641 174
4ae234b0
GK		 175; Any hardware-supported floating-point mode
176(define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
177 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
602ea4d3 178 (TF "!TARGET_IEEEQUAD
17caeff2
JM		 179 && TARGET_HARD_FLOAT
180 && (TARGET_FPRS || TARGET_E500_DOUBLE)
181 && TARGET_LONG_DOUBLE_128")])
4ae234b0 182
915167f5 183; Various instructions that come in SI and DI forms.
0354e5d8 184; A generic w/d attribute, for things like cmpw/cmpd.
b5568f07
DE		 185(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
186
187; DImode bits
188(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
915167f5
GK		 189
190\f
1fd4e8c1
RK		 191;; Start with fixed-point load and store insns. Here we put only the more
192;; complex forms. Basic data transfer is done later.
193
b5568f07 194(define_expand "zero_extend<mode>di2"
51b8fc2c 195 [(set (match_operand:DI 0 "gpc_reg_operand" "")
b5568f07 196 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
51b8fc2c
RK		 197 "TARGET_POWERPC64"
198 "")
199
b5568f07 200(define_insn "*zero_extend<mode>di2_internal1"
51b8fc2c 201 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
b5568f07 202 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
51b8fc2c
RK		 203 "TARGET_POWERPC64"
204 "@
b5568f07
DE		 205 l<wd>z%U1%X1 %0,%1
206 rldicl %0,%1,0,<dbits>"
51b8fc2c
RK		 207 [(set_attr "type" "load,*")])
208
b5568f07 209(define_insn "*zero_extend<mode>di2_internal2"
9ebbca7d 210 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
b5568f07 211 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
815cdc52 212 (const_int 0)))
9ebbca7d 213 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 214 "TARGET_64BIT"
9ebbca7d 215 "@
b5568f07 216 rldicl. %2,%1,0,<dbits>
9ebbca7d
GK		 217 #"
218 [(set_attr "type" "compare")
219 (set_attr "length" "4,8")])
220
221(define_split
222 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
b5568f07 223 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 224 (const_int 0)))
225 (clobber (match_scratch:DI 2 ""))]
226 "TARGET_POWERPC64 && reload_completed"
227 [(set (match_dup 2)
228 (zero_extend:DI (match_dup 1)))
229 (set (match_dup 0)
230 (compare:CC (match_dup 2)
231 (const_int 0)))]
232 "")
51b8fc2c 233
b5568f07 234(define_insn "*zero_extend<mode>di2_internal3"
9ebbca7d 235 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
b5568f07 236 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 237 (const_int 0)))
9ebbca7d 238 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 239 (zero_extend:DI (match_dup 1)))]
683bdff7 240 "TARGET_64BIT"
9ebbca7d 241 "@
b5568f07 242 rldicl. %0,%1,0,<dbits>
9ebbca7d
GK		 243 #"
244 [(set_attr "type" "compare")
245 (set_attr "length" "4,8")])
246
247(define_split
248 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
b5568f07 249 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 250 (const_int 0)))
251 (set (match_operand:DI 0 "gpc_reg_operand" "")
252 (zero_extend:DI (match_dup 1)))]
253 "TARGET_POWERPC64 && reload_completed"
254 [(set (match_dup 0)
255 (zero_extend:DI (match_dup 1)))
256 (set (match_dup 2)
257 (compare:CC (match_dup 0)
258 (const_int 0)))]
259 "")
51b8fc2c 260
2bee0449
RK		 261(define_insn "extendqidi2"
262 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
263 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 264 "TARGET_POWERPC64"
44cd321e
PS		 265 "extsb %0,%1"
266 [(set_attr "type" "exts")])
51b8fc2c
RK		 267
268(define_insn ""
9ebbca7d
GK		 269 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
270 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 271 (const_int 0)))
9ebbca7d 272 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 273 "TARGET_64BIT"
9ebbca7d
GK		 274 "@
275 extsb. %2,%1
276 #"
277 [(set_attr "type" "compare")
278 (set_attr "length" "4,8")])
279
280(define_split
281 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
282 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
283 (const_int 0)))
284 (clobber (match_scratch:DI 2 ""))]
285 "TARGET_POWERPC64 && reload_completed"
286 [(set (match_dup 2)
287 (sign_extend:DI (match_dup 1)))
288 (set (match_dup 0)
289 (compare:CC (match_dup 2)
290 (const_int 0)))]
291 "")
51b8fc2c
RK		 292
293(define_insn ""
9ebbca7d
GK		 294 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
295 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 296 (const_int 0)))
9ebbca7d 297 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 298 (sign_extend:DI (match_dup 1)))]
683bdff7 299 "TARGET_64BIT"
9ebbca7d
GK		 300 "@
301 extsb. %0,%1
302 #"
303 [(set_attr "type" "compare")
304 (set_attr "length" "4,8")])
305
306(define_split
307 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
308 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
309 (const_int 0)))
310 (set (match_operand:DI 0 "gpc_reg_operand" "")
311 (sign_extend:DI (match_dup 1)))]
312 "TARGET_POWERPC64 && reload_completed"
313 [(set (match_dup 0)
314 (sign_extend:DI (match_dup 1)))
315 (set (match_dup 2)
316 (compare:CC (match_dup 0)
317 (const_int 0)))]
318 "")
51b8fc2c 319
51b8fc2c
RK		 320(define_expand "extendhidi2"
321 [(set (match_operand:DI 0 "gpc_reg_operand" "")
322 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
323 "TARGET_POWERPC64"
324 "")
325
326(define_insn ""
327 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
328 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
329 "TARGET_POWERPC64"
330 "@
331 lha%U1%X1 %0,%1
332 extsh %0,%1"
44cd321e 333 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 334
335(define_insn ""
9ebbca7d
GK		 336 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
337 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 338 (const_int 0)))
9ebbca7d 339 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 340 "TARGET_64BIT"
9ebbca7d
GK		 341 "@
342 extsh. %2,%1
343 #"
344 [(set_attr "type" "compare")
345 (set_attr "length" "4,8")])
346
347(define_split
348 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
349 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
350 (const_int 0)))
351 (clobber (match_scratch:DI 2 ""))]
352 "TARGET_POWERPC64 && reload_completed"
353 [(set (match_dup 2)
354 (sign_extend:DI (match_dup 1)))
355 (set (match_dup 0)
356 (compare:CC (match_dup 2)
357 (const_int 0)))]
358 "")
51b8fc2c
RK		 359
360(define_insn ""
9ebbca7d
GK		 361 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
362 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 363 (const_int 0)))
9ebbca7d 364 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 365 (sign_extend:DI (match_dup 1)))]
683bdff7 366 "TARGET_64BIT"
9ebbca7d
GK		 367 "@
368 extsh. %0,%1
369 #"
370 [(set_attr "type" "compare")
371 (set_attr "length" "4,8")])
372
373(define_split
374 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
375 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
376 (const_int 0)))
377 (set (match_operand:DI 0 "gpc_reg_operand" "")
378 (sign_extend:DI (match_dup 1)))]
379 "TARGET_POWERPC64 && reload_completed"
380 [(set (match_dup 0)
381 (sign_extend:DI (match_dup 1)))
382 (set (match_dup 2)
383 (compare:CC (match_dup 0)
384 (const_int 0)))]
385 "")
51b8fc2c 386
51b8fc2c
RK		 387(define_expand "extendsidi2"
388 [(set (match_operand:DI 0 "gpc_reg_operand" "")
389 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
390 "TARGET_POWERPC64"
391 "")
392
393(define_insn ""
394 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 395 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
51b8fc2c
RK		 396 "TARGET_POWERPC64"
397 "@
398 lwa%U1%X1 %0,%1
399 extsw %0,%1"
44cd321e 400 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 401
402(define_insn ""
9ebbca7d
GK		 403 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
404 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 405 (const_int 0)))
9ebbca7d 406 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 407 "TARGET_64BIT"
9ebbca7d
GK		 408 "@
409 extsw. %2,%1
410 #"
411 [(set_attr "type" "compare")
412 (set_attr "length" "4,8")])
413
414(define_split
415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
416 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
417 (const_int 0)))
418 (clobber (match_scratch:DI 2 ""))]
419 "TARGET_POWERPC64 && reload_completed"
420 [(set (match_dup 2)
421 (sign_extend:DI (match_dup 1)))
422 (set (match_dup 0)
423 (compare:CC (match_dup 2)
424 (const_int 0)))]
425 "")
51b8fc2c
RK		 426
427(define_insn ""
9ebbca7d
GK		 428 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
429 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 430 (const_int 0)))
9ebbca7d 431 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 432 (sign_extend:DI (match_dup 1)))]
683bdff7 433 "TARGET_64BIT"
9ebbca7d
GK		 434 "@
435 extsw. %0,%1
436 #"
437 [(set_attr "type" "compare")
438 (set_attr "length" "4,8")])
439
440(define_split
441 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
442 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
443 (const_int 0)))
444 (set (match_operand:DI 0 "gpc_reg_operand" "")
445 (sign_extend:DI (match_dup 1)))]
446 "TARGET_POWERPC64 && reload_completed"
447 [(set (match_dup 0)
448 (sign_extend:DI (match_dup 1)))
449 (set (match_dup 2)
450 (compare:CC (match_dup 0)
451 (const_int 0)))]
452 "")
51b8fc2c 453
1fd4e8c1 454(define_expand "zero_extendqisi2"
cd2b37d9
RK		 455 [(set (match_operand:SI 0 "gpc_reg_operand" "")
456 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 457 ""
458 "")
459
460(define_insn ""
cd2b37d9 461 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 462 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
463 ""
464 "@
465 lbz%U1%X1 %0,%1
005a35b9 466 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 467 [(set_attr "type" "load,*")])
468
469(define_insn ""
9ebbca7d
GK		 470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
471 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 472 (const_int 0)))
9ebbca7d 473 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 474 ""
9ebbca7d
GK		 475 "@
476 {andil.|andi.} %2,%1,0xff
477 #"
478 [(set_attr "type" "compare")
479 (set_attr "length" "4,8")])
480
481(define_split
482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
483 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
484 (const_int 0)))
485 (clobber (match_scratch:SI 2 ""))]
486 "reload_completed"
487 [(set (match_dup 2)
488 (zero_extend:SI (match_dup 1)))
489 (set (match_dup 0)
490 (compare:CC (match_dup 2)
491 (const_int 0)))]
492 "")
1fd4e8c1
RK		 493
494(define_insn ""
9ebbca7d
GK		 495 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
496 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 497 (const_int 0)))
9ebbca7d 498 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 499 (zero_extend:SI (match_dup 1)))]
500 ""
9ebbca7d
GK		 501 "@
502 {andil.|andi.} %0,%1,0xff
503 #"
504 [(set_attr "type" "compare")
505 (set_attr "length" "4,8")])
506
507(define_split
508 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
509 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
510 (const_int 0)))
511 (set (match_operand:SI 0 "gpc_reg_operand" "")
512 (zero_extend:SI (match_dup 1)))]
513 "reload_completed"
514 [(set (match_dup 0)
515 (zero_extend:SI (match_dup 1)))
516 (set (match_dup 2)
517 (compare:CC (match_dup 0)
518 (const_int 0)))]
519 "")
1fd4e8c1 520
51b8fc2c
RK		 521(define_expand "extendqisi2"
522 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
523 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
524 ""
525 "
526{
527 if (TARGET_POWERPC)
528 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
529 else if (TARGET_POWER)
530 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
531 else
532 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
533 DONE;
534}")
535
536(define_insn "extendqisi2_ppc"
2bee0449
RK		 537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
538 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 539 "TARGET_POWERPC"
44cd321e
PS		 540 "extsb %0,%1"
541 [(set_attr "type" "exts")])
51b8fc2c
RK		 542
543(define_insn ""
9ebbca7d
GK		 544 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
545 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 546 (const_int 0)))
9ebbca7d 547 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 548 "TARGET_POWERPC"
9ebbca7d
GK		 549 "@
550 extsb. %2,%1
551 #"
552 [(set_attr "type" "compare")
553 (set_attr "length" "4,8")])
554
555(define_split
556 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
557 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
558 (const_int 0)))
559 (clobber (match_scratch:SI 2 ""))]
560 "TARGET_POWERPC && reload_completed"
561 [(set (match_dup 2)
562 (sign_extend:SI (match_dup 1)))
563 (set (match_dup 0)
564 (compare:CC (match_dup 2)
565 (const_int 0)))]
566 "")
51b8fc2c
RK		 567
568(define_insn ""
9ebbca7d
GK		 569 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
570 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 571 (const_int 0)))
9ebbca7d 572 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 573 (sign_extend:SI (match_dup 1)))]
574 "TARGET_POWERPC"
9ebbca7d
GK		 575 "@
576 extsb. %0,%1
577 #"
578 [(set_attr "type" "compare")
579 (set_attr "length" "4,8")])
580
581(define_split
582 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
583 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
584 (const_int 0)))
585 (set (match_operand:SI 0 "gpc_reg_operand" "")
586 (sign_extend:SI (match_dup 1)))]
587 "TARGET_POWERPC && reload_completed"
588 [(set (match_dup 0)
589 (sign_extend:SI (match_dup 1)))
590 (set (match_dup 2)
591 (compare:CC (match_dup 0)
592 (const_int 0)))]
593 "")
51b8fc2c
RK		 594
595(define_expand "extendqisi2_power"
596 [(parallel [(set (match_dup 2)
597 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
598 (const_int 24)))
599 (clobber (scratch:SI))])
600 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
601 (ashiftrt:SI (match_dup 2)
602 (const_int 24)))
603 (clobber (scratch:SI))])]
604 "TARGET_POWER"
605 "
606{ operands[1] = gen_lowpart (SImode, operands[1]);
607 operands[2] = gen_reg_rtx (SImode); }")
608
609(define_expand "extendqisi2_no_power"
610 [(set (match_dup 2)
611 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
612 (const_int 24)))
613 (set (match_operand:SI 0 "gpc_reg_operand" "")
614 (ashiftrt:SI (match_dup 2)
615 (const_int 24)))]
616 "! TARGET_POWER && ! TARGET_POWERPC"
617 "
618{ operands[1] = gen_lowpart (SImode, operands[1]);
619 operands[2] = gen_reg_rtx (SImode); }")
620
1fd4e8c1 621(define_expand "zero_extendqihi2"
cd2b37d9
RK		 622 [(set (match_operand:HI 0 "gpc_reg_operand" "")
623 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 624 ""
625 "")
626
627(define_insn ""
cd2b37d9 628 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 629 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
630 ""
631 "@
632 lbz%U1%X1 %0,%1
005a35b9 633 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 634 [(set_attr "type" "load,*")])
635
636(define_insn ""
9ebbca7d
GK		 637 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
638 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 639 (const_int 0)))
9ebbca7d 640 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 641 ""
9ebbca7d
GK		 642 "@
643 {andil.|andi.} %2,%1,0xff
644 #"
645 [(set_attr "type" "compare")
646 (set_attr "length" "4,8")])
647
648(define_split
649 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
650 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
651 (const_int 0)))
652 (clobber (match_scratch:HI 2 ""))]
653 "reload_completed"
654 [(set (match_dup 2)
655 (zero_extend:HI (match_dup 1)))
656 (set (match_dup 0)
657 (compare:CC (match_dup 2)
658 (const_int 0)))]
659 "")
1fd4e8c1 660
51b8fc2c 661(define_insn ""
9ebbca7d
GK		 662 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
663 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 664 (const_int 0)))
9ebbca7d 665 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 666 (zero_extend:HI (match_dup 1)))]
667 ""
9ebbca7d
GK		 668 "@
669 {andil.|andi.} %0,%1,0xff
670 #"
671 [(set_attr "type" "compare")
672 (set_attr "length" "4,8")])
673
674(define_split
675 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
676 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
677 (const_int 0)))
678 (set (match_operand:HI 0 "gpc_reg_operand" "")
679 (zero_extend:HI (match_dup 1)))]
680 "reload_completed"
681 [(set (match_dup 0)
682 (zero_extend:HI (match_dup 1)))
683 (set (match_dup 2)
684 (compare:CC (match_dup 0)
685 (const_int 0)))]
686 "")
815cdc52
MM		 687
688(define_expand "extendqihi2"
689 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
690 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
691 ""
692 "
693{
694 if (TARGET_POWERPC)
695 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
696 else if (TARGET_POWER)
697 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
698 else
699 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
700 DONE;
701}")
702
703(define_insn "extendqihi2_ppc"
704 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
705 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
706 "TARGET_POWERPC"
44cd321e
PS		 707 "extsb %0,%1"
708 [(set_attr "type" "exts")])
815cdc52
MM		 709
710(define_insn ""
9ebbca7d
GK		 711 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
712 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 713 (const_int 0)))
9ebbca7d 714 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 715 "TARGET_POWERPC"
9ebbca7d
GK		 716 "@
717 extsb. %2,%1
718 #"
719 [(set_attr "type" "compare")
720 (set_attr "length" "4,8")])
721
722(define_split
723 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
724 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
725 (const_int 0)))
726 (clobber (match_scratch:HI 2 ""))]
727 "TARGET_POWERPC && reload_completed"
728 [(set (match_dup 2)
729 (sign_extend:HI (match_dup 1)))
730 (set (match_dup 0)
731 (compare:CC (match_dup 2)
732 (const_int 0)))]
733 "")
815cdc52
MM		 734
735(define_insn ""
9ebbca7d
GK		 736 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
737 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 738 (const_int 0)))
9ebbca7d 739 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 740 (sign_extend:HI (match_dup 1)))]
741 "TARGET_POWERPC"
9ebbca7d
GK		 742 "@
743 extsb. %0,%1
744 #"
745 [(set_attr "type" "compare")
746 (set_attr "length" "4,8")])
747
748(define_split
749 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
750 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
751 (const_int 0)))
752 (set (match_operand:HI 0 "gpc_reg_operand" "")
753 (sign_extend:HI (match_dup 1)))]
754 "TARGET_POWERPC && reload_completed"
755 [(set (match_dup 0)
756 (sign_extend:HI (match_dup 1)))
757 (set (match_dup 2)
758 (compare:CC (match_dup 0)
759 (const_int 0)))]
760 "")
51b8fc2c
RK		 761
762(define_expand "extendqihi2_power"
763 [(parallel [(set (match_dup 2)
764 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
765 (const_int 24)))
766 (clobber (scratch:SI))])
767 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
768 (ashiftrt:SI (match_dup 2)
769 (const_int 24)))
770 (clobber (scratch:SI))])]
771 "TARGET_POWER"
772 "
773{ operands[0] = gen_lowpart (SImode, operands[0]);
774 operands[1] = gen_lowpart (SImode, operands[1]);
775 operands[2] = gen_reg_rtx (SImode); }")
776
777(define_expand "extendqihi2_no_power"
778 [(set (match_dup 2)
779 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
780 (const_int 24)))
781 (set (match_operand:HI 0 "gpc_reg_operand" "")
782 (ashiftrt:SI (match_dup 2)
783 (const_int 24)))]
784 "! TARGET_POWER && ! TARGET_POWERPC"
785 "
786{ operands[0] = gen_lowpart (SImode, operands[0]);
787 operands[1] = gen_lowpart (SImode, operands[1]);
788 operands[2] = gen_reg_rtx (SImode); }")
789
1fd4e8c1 790(define_expand "zero_extendhisi2"
5f243543 791 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 792 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 793 ""
794 "")
795
796(define_insn ""
cd2b37d9 797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 798 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
799 ""
800 "@
801 lhz%U1%X1 %0,%1
005a35b9 802 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 803 [(set_attr "type" "load,*")])
804
805(define_insn ""
9ebbca7d
GK		 806 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
807 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 808 (const_int 0)))
9ebbca7d 809 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 810 ""
9ebbca7d
GK		 811 "@
812 {andil.|andi.} %2,%1,0xffff
813 #"
814 [(set_attr "type" "compare")
815 (set_attr "length" "4,8")])
816
817(define_split
818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
819 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
820 (const_int 0)))
821 (clobber (match_scratch:SI 2 ""))]
822 "reload_completed"
823 [(set (match_dup 2)
824 (zero_extend:SI (match_dup 1)))
825 (set (match_dup 0)
826 (compare:CC (match_dup 2)
827 (const_int 0)))]
828 "")
1fd4e8c1
RK		 829
830(define_insn ""
9ebbca7d
GK		 831 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
832 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 833 (const_int 0)))
9ebbca7d 834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 835 (zero_extend:SI (match_dup 1)))]
836 ""
9ebbca7d
GK		 837 "@
838 {andil.|andi.} %0,%1,0xffff
839 #"
840 [(set_attr "type" "compare")
841 (set_attr "length" "4,8")])
842
843(define_split
844 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
845 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
846 (const_int 0)))
847 (set (match_operand:SI 0 "gpc_reg_operand" "")
848 (zero_extend:SI (match_dup 1)))]
849 "reload_completed"
850 [(set (match_dup 0)
851 (zero_extend:SI (match_dup 1)))
852 (set (match_dup 2)
853 (compare:CC (match_dup 0)
854 (const_int 0)))]
855 "")
1fd4e8c1
RK		 856
857(define_expand "extendhisi2"
cd2b37d9
RK		 858 [(set (match_operand:SI 0 "gpc_reg_operand" "")
859 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 860 ""
861 "")
862
863(define_insn ""
cd2b37d9 864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 865 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
866 ""
867 "@
868 lha%U1%X1 %0,%1
ca7f5001 869 {exts|extsh} %0,%1"
44cd321e 870 [(set_attr "type" "load_ext,exts")])
1fd4e8c1
RK		 871
872(define_insn ""
9ebbca7d
GK		 873 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
874 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 875 (const_int 0)))
9ebbca7d 876 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 877 ""
9ebbca7d
GK		 878 "@
879 {exts.|extsh.} %2,%1
880 #"
881 [(set_attr "type" "compare")
882 (set_attr "length" "4,8")])
883
884(define_split
885 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
886 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
887 (const_int 0)))
888 (clobber (match_scratch:SI 2 ""))]
889 "reload_completed"
890 [(set (match_dup 2)
891 (sign_extend:SI (match_dup 1)))
892 (set (match_dup 0)
893 (compare:CC (match_dup 2)
894 (const_int 0)))]
895 "")
1fd4e8c1
RK		 896
897(define_insn ""
9ebbca7d
GK		 898 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
899 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 900 (const_int 0)))
9ebbca7d 901 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 902 (sign_extend:SI (match_dup 1)))]
903 ""
9ebbca7d
GK		 904 "@
905 {exts.|extsh.} %0,%1
906 #"
907 [(set_attr "type" "compare")
908 (set_attr "length" "4,8")])
1fd4e8c1 909\f
131aeb82
JM		 910;; IBM 405 and 440 half-word multiplication operations.
911
912(define_insn "*macchwc"
913 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
914 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
915 (match_operand:SI 2 "gpc_reg_operand" "r")
916 (const_int 16))
917 (sign_extend:SI
918 (match_operand:HI 1 "gpc_reg_operand" "r")))
919 (match_operand:SI 4 "gpc_reg_operand" "0"))
920 (const_int 0)))
921 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
922 (plus:SI (mult:SI (ashiftrt:SI
923 (match_dup 2)
924 (const_int 16))
925 (sign_extend:SI
926 (match_dup 1)))
927 (match_dup 4)))]
928 "TARGET_MULHW"
929 "macchw. %0, %1, %2"
930 [(set_attr "type" "imul3")])
931
932(define_insn "*macchw"
933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
934 (plus:SI (mult:SI (ashiftrt:SI
935 (match_operand:SI 2 "gpc_reg_operand" "r")
936 (const_int 16))
937 (sign_extend:SI
938 (match_operand:HI 1 "gpc_reg_operand" "r")))
939 (match_operand:SI 3 "gpc_reg_operand" "0")))]
940 "TARGET_MULHW"
941 "macchw %0, %1, %2"
942 [(set_attr "type" "imul3")])
943
944(define_insn "*macchwuc"
945 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
946 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
947 (match_operand:SI 2 "gpc_reg_operand" "r")
948 (const_int 16))
949 (zero_extend:SI
950 (match_operand:HI 1 "gpc_reg_operand" "r")))
951 (match_operand:SI 4 "gpc_reg_operand" "0"))
952 (const_int 0)))
953 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
954 (plus:SI (mult:SI (lshiftrt:SI
955 (match_dup 2)
956 (const_int 16))
957 (zero_extend:SI
958 (match_dup 1)))
959 (match_dup 4)))]
960 "TARGET_MULHW"
961 "macchwu. %0, %1, %2"
962 [(set_attr "type" "imul3")])
963
964(define_insn "*macchwu"
965 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
966 (plus:SI (mult:SI (lshiftrt:SI
967 (match_operand:SI 2 "gpc_reg_operand" "r")
968 (const_int 16))
969 (zero_extend:SI
970 (match_operand:HI 1 "gpc_reg_operand" "r")))
971 (match_operand:SI 3 "gpc_reg_operand" "0")))]
972 "TARGET_MULHW"
973 "macchwu %0, %1, %2"
974 [(set_attr "type" "imul3")])
975
976(define_insn "*machhwc"
977 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
978 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
979 (match_operand:SI 1 "gpc_reg_operand" "%r")
980 (const_int 16))
981 (ashiftrt:SI
982 (match_operand:SI 2 "gpc_reg_operand" "r")
983 (const_int 16)))
984 (match_operand:SI 4 "gpc_reg_operand" "0"))
985 (const_int 0)))
986 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
987 (plus:SI (mult:SI (ashiftrt:SI
988 (match_dup 1)
989 (const_int 16))
990 (ashiftrt:SI
991 (match_dup 2)
992 (const_int 16)))
993 (match_dup 4)))]
994 "TARGET_MULHW"
995 "machhw. %0, %1, %2"
996 [(set_attr "type" "imul3")])
997
998(define_insn "*machhw"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1000 (plus:SI (mult:SI (ashiftrt:SI
1001 (match_operand:SI 1 "gpc_reg_operand" "%r")
1002 (const_int 16))
1003 (ashiftrt:SI
1004 (match_operand:SI 2 "gpc_reg_operand" "r")
1005 (const_int 16)))
1006 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1007 "TARGET_MULHW"
1008 "machhw %0, %1, %2"
1009 [(set_attr "type" "imul3")])
1010
1011(define_insn "*machhwuc"
1012 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1013 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1014 (match_operand:SI 1 "gpc_reg_operand" "%r")
1015 (const_int 16))
1016 (lshiftrt:SI
1017 (match_operand:SI 2 "gpc_reg_operand" "r")
1018 (const_int 16)))
1019 (match_operand:SI 4 "gpc_reg_operand" "0"))
1020 (const_int 0)))
1021 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1022 (plus:SI (mult:SI (lshiftrt:SI
1023 (match_dup 1)
1024 (const_int 16))
1025 (lshiftrt:SI
1026 (match_dup 2)
1027 (const_int 16)))
1028 (match_dup 4)))]
1029 "TARGET_MULHW"
1030 "machhwu. %0, %1, %2"
1031 [(set_attr "type" "imul3")])
1032
1033(define_insn "*machhwu"
1034 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1035 (plus:SI (mult:SI (lshiftrt:SI
1036 (match_operand:SI 1 "gpc_reg_operand" "%r")
1037 (const_int 16))
1038 (lshiftrt:SI
1039 (match_operand:SI 2 "gpc_reg_operand" "r")
1040 (const_int 16)))
1041 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1042 "TARGET_MULHW"
1043 "machhwu %0, %1, %2"
1044 [(set_attr "type" "imul3")])
1045
1046(define_insn "*maclhwc"
1047 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1048 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1049 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1050 (sign_extend:SI
1051 (match_operand:HI 2 "gpc_reg_operand" "r")))
1052 (match_operand:SI 4 "gpc_reg_operand" "0"))
1053 (const_int 0)))
1054 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1055 (plus:SI (mult:SI (sign_extend:SI
1056 (match_dup 1))
1057 (sign_extend:SI
1058 (match_dup 2)))
1059 (match_dup 4)))]
1060 "TARGET_MULHW"
1061 "maclhw. %0, %1, %2"
1062 [(set_attr "type" "imul3")])
1063
1064(define_insn "*maclhw"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1066 (plus:SI (mult:SI (sign_extend:SI
1067 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1068 (sign_extend:SI
1069 (match_operand:HI 2 "gpc_reg_operand" "r")))
1070 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1071 "TARGET_MULHW"
1072 "maclhw %0, %1, %2"
1073 [(set_attr "type" "imul3")])
1074
1075(define_insn "*maclhwuc"
1076 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1077 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1078 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1079 (zero_extend:SI
1080 (match_operand:HI 2 "gpc_reg_operand" "r")))
1081 (match_operand:SI 4 "gpc_reg_operand" "0"))
1082 (const_int 0)))
1083 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1084 (plus:SI (mult:SI (zero_extend:SI
1085 (match_dup 1))
1086 (zero_extend:SI
1087 (match_dup 2)))
1088 (match_dup 4)))]
1089 "TARGET_MULHW"
1090 "maclhwu. %0, %1, %2"
1091 [(set_attr "type" "imul3")])
1092
1093(define_insn "*maclhwu"
1094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1095 (plus:SI (mult:SI (zero_extend:SI
1096 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1097 (zero_extend:SI
1098 (match_operand:HI 2 "gpc_reg_operand" "r")))
1099 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1100 "TARGET_MULHW"
1101 "maclhwu %0, %1, %2"
1102 [(set_attr "type" "imul3")])
1103
1104(define_insn "*nmacchwc"
1105 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1106 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1107 (mult:SI (ashiftrt:SI
1108 (match_operand:SI 2 "gpc_reg_operand" "r")
1109 (const_int 16))
1110 (sign_extend:SI
1111 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1112 (const_int 0)))
1113 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1114 (minus:SI (match_dup 4)
1115 (mult:SI (ashiftrt:SI
1116 (match_dup 2)
1117 (const_int 16))
1118 (sign_extend:SI
1119 (match_dup 1)))))]
1120 "TARGET_MULHW"
1121 "nmacchw. %0, %1, %2"
1122 [(set_attr "type" "imul3")])
1123
1124(define_insn "*nmacchw"
1125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1126 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1127 (mult:SI (ashiftrt:SI
1128 (match_operand:SI 2 "gpc_reg_operand" "r")
1129 (const_int 16))
1130 (sign_extend:SI
1131 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1132 "TARGET_MULHW"
1133 "nmacchw %0, %1, %2"
1134 [(set_attr "type" "imul3")])
1135
1136(define_insn "*nmachhwc"
1137 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1138 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1139 (mult:SI (ashiftrt:SI
1140 (match_operand:SI 1 "gpc_reg_operand" "%r")
1141 (const_int 16))
1142 (ashiftrt:SI
1143 (match_operand:SI 2 "gpc_reg_operand" "r")
1144 (const_int 16))))
1145 (const_int 0)))
1146 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1147 (minus:SI (match_dup 4)
1148 (mult:SI (ashiftrt:SI
1149 (match_dup 1)
1150 (const_int 16))
1151 (ashiftrt:SI
1152 (match_dup 2)
1153 (const_int 16)))))]
1154 "TARGET_MULHW"
1155 "nmachhw. %0, %1, %2"
1156 [(set_attr "type" "imul3")])
1157
1158(define_insn "*nmachhw"
1159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1160 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1161 (mult:SI (ashiftrt:SI
1162 (match_operand:SI 1 "gpc_reg_operand" "%r")
1163 (const_int 16))
1164 (ashiftrt:SI
1165 (match_operand:SI 2 "gpc_reg_operand" "r")
1166 (const_int 16)))))]
1167 "TARGET_MULHW"
1168 "nmachhw %0, %1, %2"
1169 [(set_attr "type" "imul3")])
1170
1171(define_insn "*nmaclhwc"
1172 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1173 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1174 (mult:SI (sign_extend:SI
1175 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1176 (sign_extend:SI
1177 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1178 (const_int 0)))
1179 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1180 (minus:SI (match_dup 4)
1181 (mult:SI (sign_extend:SI
1182 (match_dup 1))
1183 (sign_extend:SI
1184 (match_dup 2)))))]
1185 "TARGET_MULHW"
1186 "nmaclhw. %0, %1, %2"
1187 [(set_attr "type" "imul3")])
1188
1189(define_insn "*nmaclhw"
1190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1192 (mult:SI (sign_extend:SI
1193 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1194 (sign_extend:SI
1195 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1196 "TARGET_MULHW"
1197 "nmaclhw %0, %1, %2"
1198 [(set_attr "type" "imul3")])
1199
1200(define_insn "*mulchwc"
1201 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1202 (compare:CC (mult:SI (ashiftrt:SI
1203 (match_operand:SI 2 "gpc_reg_operand" "r")
1204 (const_int 16))
1205 (sign_extend:SI
1206 (match_operand:HI 1 "gpc_reg_operand" "r")))
1207 (const_int 0)))
1208 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1209 (mult:SI (ashiftrt:SI
1210 (match_dup 2)
1211 (const_int 16))
1212 (sign_extend:SI
1213 (match_dup 1))))]
1214 "TARGET_MULHW"
1215 "mulchw. %0, %1, %2"
1216 [(set_attr "type" "imul3")])
1217
1218(define_insn "*mulchw"
1219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1220 (mult:SI (ashiftrt:SI
1221 (match_operand:SI 2 "gpc_reg_operand" "r")
1222 (const_int 16))
1223 (sign_extend:SI
1224 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1225 "TARGET_MULHW"
1226 "mulchw %0, %1, %2"
1227 [(set_attr "type" "imul3")])
1228
1229(define_insn "*mulchwuc"
1230 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1231 (compare:CC (mult:SI (lshiftrt:SI
1232 (match_operand:SI 2 "gpc_reg_operand" "r")
1233 (const_int 16))
1234 (zero_extend:SI
1235 (match_operand:HI 1 "gpc_reg_operand" "r")))
1236 (const_int 0)))
1237 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1238 (mult:SI (lshiftrt:SI
1239 (match_dup 2)
1240 (const_int 16))
1241 (zero_extend:SI
1242 (match_dup 1))))]
1243 "TARGET_MULHW"
1244 "mulchwu. %0, %1, %2"
1245 [(set_attr "type" "imul3")])
1246
1247(define_insn "*mulchwu"
1248 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1249 (mult:SI (lshiftrt:SI
1250 (match_operand:SI 2 "gpc_reg_operand" "r")
1251 (const_int 16))
1252 (zero_extend:SI
1253 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1254 "TARGET_MULHW"
1255 "mulchwu %0, %1, %2"
1256 [(set_attr "type" "imul3")])
1257
1258(define_insn "*mulhhwc"
1259 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1260 (compare:CC (mult:SI (ashiftrt:SI
1261 (match_operand:SI 1 "gpc_reg_operand" "%r")
1262 (const_int 16))
1263 (ashiftrt:SI
1264 (match_operand:SI 2 "gpc_reg_operand" "r")
1265 (const_int 16)))
1266 (const_int 0)))
1267 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1268 (mult:SI (ashiftrt:SI
1269 (match_dup 1)
1270 (const_int 16))
1271 (ashiftrt:SI
1272 (match_dup 2)
1273 (const_int 16))))]
1274 "TARGET_MULHW"
1275 "mulhhw. %0, %1, %2"
1276 [(set_attr "type" "imul3")])
1277
1278(define_insn "*mulhhw"
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1280 (mult:SI (ashiftrt:SI
1281 (match_operand:SI 1 "gpc_reg_operand" "%r")
1282 (const_int 16))
1283 (ashiftrt:SI
1284 (match_operand:SI 2 "gpc_reg_operand" "r")
1285 (const_int 16))))]
1286 "TARGET_MULHW"
1287 "mulhhw %0, %1, %2"
1288 [(set_attr "type" "imul3")])
1289
1290(define_insn "*mulhhwuc"
1291 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1292 (compare:CC (mult:SI (lshiftrt:SI
1293 (match_operand:SI 1 "gpc_reg_operand" "%r")
1294 (const_int 16))
1295 (lshiftrt:SI
1296 (match_operand:SI 2 "gpc_reg_operand" "r")
1297 (const_int 16)))
1298 (const_int 0)))
1299 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1300 (mult:SI (lshiftrt:SI
1301 (match_dup 1)
1302 (const_int 16))
1303 (lshiftrt:SI
1304 (match_dup 2)
1305 (const_int 16))))]
1306 "TARGET_MULHW"
1307 "mulhhwu. %0, %1, %2"
1308 [(set_attr "type" "imul3")])
1309
1310(define_insn "*mulhhwu"
1311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1312 (mult:SI (lshiftrt:SI
1313 (match_operand:SI 1 "gpc_reg_operand" "%r")
1314 (const_int 16))
1315 (lshiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16))))]
1318 "TARGET_MULHW"
1319 "mulhhwu %0, %1, %2"
1320 [(set_attr "type" "imul3")])
1321
1322(define_insn "*mullhwc"
1323 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1324 (compare:CC (mult:SI (sign_extend:SI
1325 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1326 (sign_extend:SI
1327 (match_operand:HI 2 "gpc_reg_operand" "r")))
1328 (const_int 0)))
1329 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1330 (mult:SI (sign_extend:SI
1331 (match_dup 1))
1332 (sign_extend:SI
1333 (match_dup 2))))]
1334 "TARGET_MULHW"
1335 "mullhw. %0, %1, %2"
1336 [(set_attr "type" "imul3")])
1337
1338(define_insn "*mullhw"
1339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1340 (mult:SI (sign_extend:SI
1341 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1342 (sign_extend:SI
1343 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1344 "TARGET_MULHW"
1345 "mullhw %0, %1, %2"
1346 [(set_attr "type" "imul3")])
1347
1348(define_insn "*mullhwuc"
1349 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1350 (compare:CC (mult:SI (zero_extend:SI
1351 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1352 (zero_extend:SI
1353 (match_operand:HI 2 "gpc_reg_operand" "r")))
1354 (const_int 0)))
1355 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 (mult:SI (zero_extend:SI
1357 (match_dup 1))
1358 (zero_extend:SI
1359 (match_dup 2))))]
1360 "TARGET_MULHW"
1361 "mullhwu. %0, %1, %2"
1362 [(set_attr "type" "imul3")])
1363
1364(define_insn "*mullhwu"
1365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1366 (mult:SI (zero_extend:SI
1367 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1368 (zero_extend:SI
1369 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1370 "TARGET_MULHW"
1371 "mullhwu %0, %1, %2"
1372 [(set_attr "type" "imul3")])
1373\f
716019c0
JM		 1374;; IBM 405 and 440 string-search dlmzb instruction support.
1375(define_insn "dlmzb"
1376 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1377 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1378 (match_operand:SI 2 "gpc_reg_operand" "r")]
1379 UNSPEC_DLMZB_CR))
1380 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1381 (unspec:SI [(match_dup 1)
1382 (match_dup 2)]
1383 UNSPEC_DLMZB))]
1384 "TARGET_DLMZB"
1385 "dlmzb. %0, %1, %2")
1386
1387(define_expand "strlensi"
1388 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1389 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1390 (match_operand:QI 2 "const_int_operand" "")
1391 (match_operand 3 "const_int_operand" "")]
1392 UNSPEC_DLMZB_STRLEN))
1393 (clobber (match_scratch:CC 4 "=x"))]
1394 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1395{
1396 rtx result = operands[0];
1397 rtx src = operands[1];
1398 rtx search_char = operands[2];
1399 rtx align = operands[3];
1400 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1401 rtx loop_label, end_label, mem, cr0, cond;
1402 if (search_char != const0_rtx
1403 || GET_CODE (align) != CONST_INT
1404 || INTVAL (align) < 8)
1405 FAIL;
1406 word1 = gen_reg_rtx (SImode);
1407 word2 = gen_reg_rtx (SImode);
1408 scratch_dlmzb = gen_reg_rtx (SImode);
1409 scratch_string = gen_reg_rtx (Pmode);
1410 loop_label = gen_label_rtx ();
1411 end_label = gen_label_rtx ();
1412 addr = force_reg (Pmode, XEXP (src, 0));
1413 emit_move_insn (scratch_string, addr);
1414 emit_label (loop_label);
1415 mem = change_address (src, SImode, scratch_string);
1416 emit_move_insn (word1, mem);
1417 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1418 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1419 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1420 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1421 emit_jump_insn (gen_rtx_SET (VOIDmode,
1422 pc_rtx,
1423 gen_rtx_IF_THEN_ELSE (VOIDmode,
1424 cond,
1425 gen_rtx_LABEL_REF
1426 (VOIDmode,
1427 end_label),
1428 pc_rtx)));
1429 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1430 emit_jump_insn (gen_rtx_SET (VOIDmode,
1431 pc_rtx,
1432 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
ea5bd0d8 1433 emit_barrier ();
716019c0
JM		 1434 emit_label (end_label);
1435 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1436 emit_insn (gen_subsi3 (result, scratch_string, addr));
1437 emit_insn (gen_subsi3 (result, result, const1_rtx));
1438 DONE;
1439})
1440\f
9ebbca7d
GK		 1441(define_split
1442 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1443 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1444 (const_int 0)))
1445 (set (match_operand:SI 0 "gpc_reg_operand" "")
1446 (sign_extend:SI (match_dup 1)))]
1447 "reload_completed"
1448 [(set (match_dup 0)
1449 (sign_extend:SI (match_dup 1)))
1450 (set (match_dup 2)
1451 (compare:CC (match_dup 0)
1452 (const_int 0)))]
1453 "")
1454
1fd4e8c1 1455;; Fixed-point arithmetic insns.
deb9225a 1456
0354e5d8
GK		 1457(define_expand "add<mode>3"
1458 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1459 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
4ae234b0 1460 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
7cd5235b 1461 ""
7cd5235b 1462{
0354e5d8
GK		 1463 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1464 {
1465 if (non_short_cint_operand (operands[2], DImode))
1466 FAIL;
1467 }
1468 else if (GET_CODE (operands[2]) == CONST_INT
1469 && ! add_operand (operands[2], <MODE>mode))
7cd5235b 1470 {
677a9668 1471 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
0354e5d8 1472 ? operands[0] : gen_reg_rtx (<MODE>mode));
7cd5235b 1473
2bfcf297 1474 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1475 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8
GK		 1476 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1477
279bb624 1478 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1479 FAIL;
7cd5235b 1480
9ebbca7d
GK		 1481 /* The ordering here is important for the prolog expander.
1482 When space is allocated from the stack, adding 'low' first may
1483 produce a temporary deallocation (which would be bad). */
0354e5d8
GK		 1484 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1485 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
7cd5235b
MM		 1486 DONE;
1487 }
279bb624 1488})
7cd5235b 1489
0354e5d8
GK		 1490;; Discourage ai/addic because of carry but provide it in an alternative
1491;; allowing register zero as source.
1492(define_insn "*add<mode>3_internal1"
1493 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1494 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1495 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
7393f7f8 1496 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1fd4e8c1 1497 "@
deb9225a
RK		 1498 {cax|add} %0,%1,%2
1499 {cal %0,%2(%1)|addi %0,%1,%2}
1500 {ai|addic} %0,%1,%2
7cd5235b
MM		 1501 {cau|addis} %0,%1,%v2"
1502 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 1503
ee890fe2
SS		 1504(define_insn "addsi3_high"
1505 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1506 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1507 (high:SI (match_operand 2 "" ""))))]
1508 "TARGET_MACHO && !TARGET_64BIT"
1509 "{cau|addis} %0,%1,ha16(%2)"
1510 [(set_attr "length" "4")])
1511
0354e5d8 1512(define_insn "*add<mode>3_internal2"
cb8cc086 1513 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1514 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1515 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1516 (const_int 0)))
0354e5d8
GK		 1517 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1518 ""
deb9225a
RK		 1519 "@
1520 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1521 {ai.|addic.} %3,%1,%2
1522 #
1523 #"
a62bfff2 1524 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1525 (set_attr "length" "4,4,8,8")])
1526
1527(define_split
1528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1529 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1530 (match_operand:GPR 2 "reg_or_short_operand" ""))
cb8cc086 1531 (const_int 0)))
0354e5d8
GK		 1532 (clobber (match_scratch:GPR 3 ""))]
1533 "reload_completed"
cb8cc086 1534 [(set (match_dup 3)
0354e5d8 1535 (plus:GPR (match_dup 1)
cb8cc086
MM		 1536 (match_dup 2)))
1537 (set (match_dup 0)
1538 (compare:CC (match_dup 3)
1539 (const_int 0)))]
1540 "")
7e69e155 1541
0354e5d8 1542(define_insn "*add<mode>3_internal3"
cb8cc086 1543 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1544 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1545 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1546 (const_int 0)))
0354e5d8
GK		 1547 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1548 (plus:P (match_dup 1)
1549 (match_dup 2)))]
1550 ""
deb9225a
RK		 1551 "@
1552 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1553 {ai.|addic.} %0,%1,%2
1554 #
1555 #"
a62bfff2 1556 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1557 (set_attr "length" "4,4,8,8")])
1558
1559(define_split
1560 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1561 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1562 (match_operand:P 2 "reg_or_short_operand" ""))
cb8cc086 1563 (const_int 0)))
0354e5d8
GK		 1564 (set (match_operand:P 0 "gpc_reg_operand" "")
1565 (plus:P (match_dup 1) (match_dup 2)))]
1566 "reload_completed"
cb8cc086 1567 [(set (match_dup 0)
0354e5d8
GK		 1568 (plus:P (match_dup 1)
1569 (match_dup 2)))
cb8cc086
MM		 1570 (set (match_dup 3)
1571 (compare:CC (match_dup 0)
1572 (const_int 0)))]
1573 "")
7e69e155 1574
f357808b
RK		 1575;; Split an add that we can't do in one insn into two insns, each of which
1576;; does one 16-bit part. This is used by combine. Note that the low-order
1577;; add should be last in case the result gets used in an address.
1578
1579(define_split
0354e5d8
GK		 1580 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1581 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1582 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1fd4e8c1 1583 ""
0354e5d8
GK		 1584 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1585 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1fd4e8c1 1586{
2bfcf297 1587 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1588 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8 1589 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1fd4e8c1 1590
e6ca2c17 1591 operands[4] = GEN_INT (low);
279bb624 1592 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
0354e5d8
GK		 1593 operands[3] = GEN_INT (rest);
1594 else if (! no_new_pseudos)
1595 {
1596 operands[3] = gen_reg_rtx (DImode);
1597 emit_move_insn (operands[3], operands[2]);
1598 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1599 DONE;
1600 }
1601 else
1602 FAIL;
279bb624 1603})
1fd4e8c1 1604
0354e5d8
GK		 1605(define_insn "one_cmpl<mode>2"
1606 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1607 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1608 ""
ca7f5001
RK		 1609 "nor %0,%1,%1")
1610
1611(define_insn ""
52d3af72 1612 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 1613 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
ca7f5001 1614 (const_int 0)))
0354e5d8
GK		 1615 (clobber (match_scratch:P 2 "=r,r"))]
1616 ""
52d3af72
DE		 1617 "@
1618 nor. %2,%1,%1
1619 #"
1620 [(set_attr "type" "compare")
1621 (set_attr "length" "4,8")])
1622
1623(define_split
1624 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 1625 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1626 (const_int 0)))
0354e5d8
GK		 1627 (clobber (match_scratch:P 2 ""))]
1628 "reload_completed"
52d3af72 1629 [(set (match_dup 2)
0354e5d8 1630 (not:P (match_dup 1)))
52d3af72
DE		 1631 (set (match_dup 0)
1632 (compare:CC (match_dup 2)
1633 (const_int 0)))]
1634 "")
ca7f5001
RK		 1635
1636(define_insn ""
52d3af72 1637 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 1638 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 1639 (const_int 0)))
0354e5d8
GK		 1640 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1641 (not:P (match_dup 1)))]
1642 ""
52d3af72
DE		 1643 "@
1644 nor. %0,%1,%1
1645 #"
1646 [(set_attr "type" "compare")
1647 (set_attr "length" "4,8")])
1648
1649(define_split
1650 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 1651 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1652 (const_int 0)))
0354e5d8
GK		 1653 (set (match_operand:P 0 "gpc_reg_operand" "")
1654 (not:P (match_dup 1)))]
1655 "reload_completed"
52d3af72 1656 [(set (match_dup 0)
0354e5d8 1657 (not:P (match_dup 1)))
52d3af72
DE		 1658 (set (match_dup 2)
1659 (compare:CC (match_dup 0)
1660 (const_int 0)))]
1661 "")
1fd4e8c1
RK		 1662
1663(define_insn ""
3d91674b
RK		 1664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1665 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1666 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1667 "! TARGET_POWERPC"
ca7f5001 1668 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1669
deb9225a 1670(define_insn ""
0354e5d8
GK		 1671 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1672 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1673 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
deb9225a
RK		 1674 "TARGET_POWERPC"
1675 "@
1676 subf %0,%2,%1
1677 subfic %0,%2,%1")
1678
1fd4e8c1 1679(define_insn ""
cb8cc086
MM		 1680 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1681 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1682 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1683 (const_int 0)))
cb8cc086 1684 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1685 "! TARGET_POWERPC"
cb8cc086
MM		 1686 "@
1687 {sf.|subfc.} %3,%2,%1
1688 #"
1689 [(set_attr "type" "compare")
1690 (set_attr "length" "4,8")])
1fd4e8c1 1691
deb9225a 1692(define_insn ""
cb8cc086 1693 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1694 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1695 (match_operand:P 2 "gpc_reg_operand" "r,r"))
deb9225a 1696 (const_int 0)))
0354e5d8
GK		 1697 (clobber (match_scratch:P 3 "=r,r"))]
1698 "TARGET_POWERPC"
cb8cc086
MM		 1699 "@
1700 subf. %3,%2,%1
1701 #"
a62bfff2 1702 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1703 (set_attr "length" "4,8")])
1704
1705(define_split
1706 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1707 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1708 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1709 (const_int 0)))
0354e5d8
GK		 1710 (clobber (match_scratch:P 3 ""))]
1711 "reload_completed"
cb8cc086 1712 [(set (match_dup 3)
0354e5d8 1713 (minus:P (match_dup 1)
cb8cc086
MM		 1714 (match_dup 2)))
1715 (set (match_dup 0)
1716 (compare:CC (match_dup 3)
1717 (const_int 0)))]
1718 "")
deb9225a 1719
1fd4e8c1 1720(define_insn ""
cb8cc086
MM		 1721 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1722 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1723 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1724 (const_int 0)))
cb8cc086 1725 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1726 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1727 "! TARGET_POWERPC"
cb8cc086
MM		 1728 "@
1729 {sf.|subfc.} %0,%2,%1
1730 #"
1731 [(set_attr "type" "compare")
1732 (set_attr "length" "4,8")])
815cdc52 1733
29ae5b89 1734(define_insn ""
cb8cc086 1735 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1736 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1737 (match_operand:P 2 "gpc_reg_operand" "r,r"))
815cdc52 1738 (const_int 0)))
0354e5d8
GK		 1739 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1740 (minus:P (match_dup 1)
cb8cc086 1741 (match_dup 2)))]
0354e5d8 1742 "TARGET_POWERPC"
90612787
DE		 1743 "@
1744 subf. %0,%2,%1
1745 #"
a62bfff2 1746 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1747 (set_attr "length" "4,8")])
1748
1749(define_split
1750 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1751 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1752 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1753 (const_int 0)))
0354e5d8
GK		 1754 (set (match_operand:P 0 "gpc_reg_operand" "")
1755 (minus:P (match_dup 1)
cb8cc086 1756 (match_dup 2)))]
0354e5d8 1757 "reload_completed"
cb8cc086 1758 [(set (match_dup 0)
0354e5d8 1759 (minus:P (match_dup 1)
cb8cc086
MM		 1760 (match_dup 2)))
1761 (set (match_dup 3)
1762 (compare:CC (match_dup 0)
1763 (const_int 0)))]
1764 "")
deb9225a 1765
0354e5d8
GK		 1766(define_expand "sub<mode>3"
1767 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1768 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
4ae234b0 1769 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1fd4e8c1 1770 ""
a0044fb1
RK		 1771 "
1772{
1773 if (GET_CODE (operands[2]) == CONST_INT)
1774 {
0354e5d8
GK		 1775 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1776 negate_rtx (<MODE>mode, operands[2])));
a0044fb1
RK		 1777 DONE;
1778 }
1779}")
1fd4e8c1
RK		 1780
1781;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1782;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1783;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1784;; combine.
1fd4e8c1
RK		 1785
1786(define_expand "sminsi3"
1787 [(set (match_dup 3)
cd2b37d9 1788 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1789 (match_operand:SI 2 "reg_or_short_operand" ""))
1790 (const_int 0)
1791 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1792 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1793 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1794 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1795 "
a3170dc6
AH		 1796{
1797 if (TARGET_ISEL)
1798 {
1799 operands[2] = force_reg (SImode, operands[2]);
1800 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1801 DONE;
1802 }
1803
1804 operands[3] = gen_reg_rtx (SImode);
1805}")
1fd4e8c1 1806
95ac8e67
RK		 1807(define_split
1808 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1809 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1810 (match_operand:SI 2 "reg_or_short_operand" "")))
1811 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1812 "TARGET_POWER"
95ac8e67
RK		 1813 [(set (match_dup 3)
1814 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1815 (const_int 0)
1816 (minus:SI (match_dup 2) (match_dup 1))))
1817 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1818 "")
1819
1fd4e8c1
RK		 1820(define_expand "smaxsi3"
1821 [(set (match_dup 3)
cd2b37d9 1822 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1823 (match_operand:SI 2 "reg_or_short_operand" ""))
1824 (const_int 0)
1825 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1826 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1827 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1828 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1829 "
a3170dc6
AH		 1830{
1831 if (TARGET_ISEL)
1832 {
1833 operands[2] = force_reg (SImode, operands[2]);
1834 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1835 DONE;
1836 }
1837 operands[3] = gen_reg_rtx (SImode);
1838}")
1fd4e8c1 1839
95ac8e67
RK		 1840(define_split
1841 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1842 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1843 (match_operand:SI 2 "reg_or_short_operand" "")))
1844 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1845 "TARGET_POWER"
95ac8e67
RK		 1846 [(set (match_dup 3)
1847 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1848 (const_int 0)
1849 (minus:SI (match_dup 2) (match_dup 1))))
1850 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1851 "")
1852
1fd4e8c1 1853(define_expand "uminsi3"
cd2b37d9 1854 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1855 (match_dup 5)))
cd2b37d9 1856 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1857 (match_dup 5)))
1fd4e8c1
RK		 1858 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1859 (const_int 0)
1860 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1861 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1862 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1863 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1864 "
bb68ff55 1865{
a3170dc6
AH		 1866 if (TARGET_ISEL)
1867 {
1868 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1869 DONE;
1870 }
bb68ff55
MM		 1871 operands[3] = gen_reg_rtx (SImode);
1872 operands[4] = gen_reg_rtx (SImode);
1873 operands[5] = GEN_INT (-2147483647 - 1);
1874}")
1fd4e8c1
RK		 1875
1876(define_expand "umaxsi3"
cd2b37d9 1877 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1878 (match_dup 5)))
cd2b37d9 1879 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1880 (match_dup 5)))
1fd4e8c1
RK		 1881 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1882 (const_int 0)
1883 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1884 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1885 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1886 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1887 "
bb68ff55 1888{
a3170dc6
AH		 1889 if (TARGET_ISEL)
1890 {
1891 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1892 DONE;
1893 }
bb68ff55
MM		 1894 operands[3] = gen_reg_rtx (SImode);
1895 operands[4] = gen_reg_rtx (SImode);
1896 operands[5] = GEN_INT (-2147483647 - 1);
1897}")
1fd4e8c1
RK		 1898
1899(define_insn ""
cd2b37d9
RK		 1900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1901 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1902 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1903 (const_int 0)
1904 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1905 "TARGET_POWER"
1fd4e8c1
RK		 1906 "doz%I2 %0,%1,%2")
1907
1908(define_insn ""
9ebbca7d 1909 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1910 (compare:CC
9ebbca7d
GK		 1911 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1912 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1913 (const_int 0)
1914 (minus:SI (match_dup 2) (match_dup 1)))
1915 (const_int 0)))
9ebbca7d 1916 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1917 "TARGET_POWER"
9ebbca7d
GK		 1918 "@
1919 doz%I2. %3,%1,%2
1920 #"
1921 [(set_attr "type" "delayed_compare")
1922 (set_attr "length" "4,8")])
1923
1924(define_split
1925 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1926 (compare:CC
1927 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1928 (match_operand:SI 2 "reg_or_short_operand" ""))
1929 (const_int 0)
1930 (minus:SI (match_dup 2) (match_dup 1)))
1931 (const_int 0)))
1932 (clobber (match_scratch:SI 3 ""))]
1933 "TARGET_POWER && reload_completed"
1934 [(set (match_dup 3)
1935 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1936 (const_int 0)
1937 (minus:SI (match_dup 2) (match_dup 1))))
1938 (set (match_dup 0)
1939 (compare:CC (match_dup 3)
1940 (const_int 0)))]
1941 "")
1fd4e8c1
RK		 1942
1943(define_insn ""
9ebbca7d 1944 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1945 (compare:CC
9ebbca7d
GK		 1946 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1947 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1948 (const_int 0)
1949 (minus:SI (match_dup 2) (match_dup 1)))
1950 (const_int 0)))
9ebbca7d 1951 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1952 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1953 (const_int 0)
1954 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1955 "TARGET_POWER"
9ebbca7d
GK		 1956 "@
1957 doz%I2. %0,%1,%2
1958 #"
1959 [(set_attr "type" "delayed_compare")
1960 (set_attr "length" "4,8")])
1961
1962(define_split
1963 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1964 (compare:CC
1965 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1966 (match_operand:SI 2 "reg_or_short_operand" ""))
1967 (const_int 0)
1968 (minus:SI (match_dup 2) (match_dup 1)))
1969 (const_int 0)))
1970 (set (match_operand:SI 0 "gpc_reg_operand" "")
1971 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1972 (const_int 0)
1973 (minus:SI (match_dup 2) (match_dup 1))))]
1974 "TARGET_POWER && reload_completed"
1975 [(set (match_dup 0)
1976 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1977 (const_int 0)
1978 (minus:SI (match_dup 2) (match_dup 1))))
1979 (set (match_dup 3)
1980 (compare:CC (match_dup 0)
1981 (const_int 0)))]
1982 "")
1fd4e8c1
RK		 1983
1984;; We don't need abs with condition code because such comparisons should
1985;; never be done.
ea9be077
MM		 1986(define_expand "abssi2"
1987 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1988 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1989 ""
1990 "
1991{
a3170dc6
AH		 1992 if (TARGET_ISEL)
1993 {
1994 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1995 DONE;
1996 }
1997 else if (! TARGET_POWER)
ea9be077
MM		 1998 {
1999 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2000 DONE;
2001 }
2002}")
2003
ea112fc4 2004(define_insn "*abssi2_power"
cd2b37d9
RK		 2005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2006 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 2007 "TARGET_POWER"
1fd4e8c1
RK		 2008 "abs %0,%1")
2009
a3170dc6
AH		 2010(define_insn_and_split "abssi2_isel"
2011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2012 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 2013 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 2014 (clobber (match_scratch:CC 3 "=y"))]
2015 "TARGET_ISEL"
2016 "#"
2017 "&& reload_completed"
2018 [(set (match_dup 2) (neg:SI (match_dup 1)))
2019 (set (match_dup 3)
2020 (compare:CC (match_dup 1)
2021 (const_int 0)))
2022 (set (match_dup 0)
2023 (if_then_else:SI (ge (match_dup 3)
2024 (const_int 0))
2025 (match_dup 1)
2026 (match_dup 2)))]
2027 "")
2028
ea112fc4 2029(define_insn_and_split "abssi2_nopower"
ea9be077 2030 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2031 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 2032 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 2033 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 2034 "#"
2035 "&& reload_completed"
ea9be077
MM		 2036 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2037 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2038 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 2039 "")
2040
463b558b 2041(define_insn "*nabs_power"
cd2b37d9
RK		 2042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2043 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 2044 "TARGET_POWER"
1fd4e8c1
RK		 2045 "nabs %0,%1")
2046
ea112fc4 2047(define_insn_and_split "*nabs_nopower"
ea9be077 2048 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2049 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 2050 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 2051 "! TARGET_POWER"
ea112fc4
DE		 2052 "#"
2053 "&& reload_completed"
ea9be077
MM		 2054 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2055 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2056 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 2057 "")
2058
0354e5d8
GK		 2059(define_expand "neg<mode>2"
2060 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2061 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2062 ""
2063 "")
2064
2065(define_insn "*neg<mode>2_internal"
2066 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2067 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 2068 ""
2069 "neg %0,%1")
2070
2071(define_insn ""
9ebbca7d 2072 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 2073 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 2074 (const_int 0)))
0354e5d8
GK		 2075 (clobber (match_scratch:P 2 "=r,r"))]
2076 ""
9ebbca7d
GK		 2077 "@
2078 neg. %2,%1
2079 #"
a62bfff2 2080 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2081 (set_attr "length" "4,8")])
2082
2083(define_split
2084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 2085 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2086 (const_int 0)))
0354e5d8
GK		 2087 (clobber (match_scratch:P 2 ""))]
2088 "reload_completed"
9ebbca7d 2089 [(set (match_dup 2)
0354e5d8 2090 (neg:P (match_dup 1)))
9ebbca7d
GK		 2091 (set (match_dup 0)
2092 (compare:CC (match_dup 2)
2093 (const_int 0)))]
2094 "")
1fd4e8c1
RK		 2095
2096(define_insn ""
9ebbca7d 2097 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 2098 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 2099 (const_int 0)))
0354e5d8
GK		 2100 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2101 (neg:P (match_dup 1)))]
2102 ""
9ebbca7d
GK		 2103 "@
2104 neg. %0,%1
2105 #"
a62bfff2 2106 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2107 (set_attr "length" "4,8")])
2108
2109(define_split
2110 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 2111 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2112 (const_int 0)))
0354e5d8
GK		 2113 (set (match_operand:P 0 "gpc_reg_operand" "")
2114 (neg:P (match_dup 1)))]
66859ace 2115 "reload_completed"
9ebbca7d 2116 [(set (match_dup 0)
0354e5d8 2117 (neg:P (match_dup 1)))
9ebbca7d
GK		 2118 (set (match_dup 2)
2119 (compare:CC (match_dup 0)
2120 (const_int 0)))]
2121 "")
1fd4e8c1 2122
0354e5d8
GK		 2123(define_insn "clz<mode>2"
2124 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2125 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1b1edcfa 2126 ""
44cd321e
PS		 2127 "{cntlz|cntlz<wd>} %0,%1"
2128 [(set_attr "type" "cntlz")])
1b1edcfa 2129
0354e5d8 2130(define_expand "ctz<mode>2"
4977bab6 2131 [(set (match_dup 2)
e42ac3de 2132 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2133 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2134 (match_dup 2)))
1b1edcfa 2135 (clobber (scratch:CC))])
0354e5d8 2136 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2137 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2138 (minus:GPR (match_dup 5) (match_dup 4)))]
1fd4e8c1 2139 ""
4977bab6 2140 {
0354e5d8
GK		 2141 operands[2] = gen_reg_rtx (<MODE>mode);
2142 operands[3] = gen_reg_rtx (<MODE>mode);
2143 operands[4] = gen_reg_rtx (<MODE>mode);
2144 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
4977bab6 2145 })
6ae08853 2146
0354e5d8 2147(define_expand "ffs<mode>2"
1b1edcfa 2148 [(set (match_dup 2)
e42ac3de 2149 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2150 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2151 (match_dup 2)))
1b1edcfa 2152 (clobber (scratch:CC))])
0354e5d8 2153 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2154 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2155 (minus:GPR (match_dup 5) (match_dup 4)))]
4977bab6 2156 ""
1b1edcfa 2157 {
0354e5d8
GK		 2158 operands[2] = gen_reg_rtx (<MODE>mode);
2159 operands[3] = gen_reg_rtx (<MODE>mode);
2160 operands[4] = gen_reg_rtx (<MODE>mode);
2161 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1b1edcfa 2162 })
6ae08853 2163
432218ba
DE		 2164(define_insn "popcntb<mode>2"
2165 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2166 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2167 UNSPEC_POPCNTB))]
2168 "TARGET_POPCNTB"
2169 "popcntb %0,%1")
2170
565ef4ba 2171(define_expand "popcount<mode>2"
e42ac3de
RS		 2172 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2173 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2174 "TARGET_POPCNTB"
2175 {
2176 rs6000_emit_popcount (operands[0], operands[1]);
2177 DONE;
2178 })
2179
2180(define_expand "parity<mode>2"
e42ac3de
RS		 2181 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2182 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2183 "TARGET_POPCNTB"
2184 {
2185 rs6000_emit_parity (operands[0], operands[1]);
2186 DONE;
2187 })
2188
03f79051
DE		 2189(define_insn "bswapsi2"
2190 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2191 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2192 ""
2193 "@
2194 {lbrx|lwbrx} %0,%y1
2195 {stbrx|stwbrx} %1,%y0
2196 #"
2197 [(set_attr "length" "4,4,12")])
2198
2199(define_split
2200 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2201 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2202 "reload_completed"
2203 [(set (match_dup 0)
2204 (rotate:SI (match_dup 1) (const_int 8)))
2205 (set (zero_extract:SI (match_dup 0)
2206 (const_int 8)
2207 (const_int 0))
2208 (match_dup 1))
2209 (set (zero_extract:SI (match_dup 0)
2210 (const_int 8)
2211 (const_int 16))
2212 (rotate:SI (match_dup 1)
2213 (const_int 16)))]
2214 "")
2215
ca7f5001
RK		 2216(define_expand "mulsi3"
2217 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2218 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2219 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2220 ""
2221 "
2222{
2223 if (TARGET_POWER)
68b40e7e 2224 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 2225 else
68b40e7e 2226 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 2227 DONE;
2228}")
2229
68b40e7e 2230(define_insn "mulsi3_mq"
cd2b37d9
RK		 2231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2232 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 2233 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2234 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 2235 "TARGET_POWER"
2236 "@
2237 {muls|mullw} %0,%1,%2
2238 {muli|mulli} %0,%1,%2"
6ae08853 2239 [(set (attr "type")
c859cda6
DJ		 2240 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2241 (const_string "imul3")
6ae08853 2242 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2243 (const_string "imul2")]
2244 (const_string "imul")))])
ca7f5001 2245
68b40e7e 2246(define_insn "mulsi3_no_mq"
ca7f5001
RK		 2247 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2248 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2249 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 2250 "! TARGET_POWER"
1fd4e8c1 2251 "@
d904e9ed
RK		 2252 {muls|mullw} %0,%1,%2
2253 {muli|mulli} %0,%1,%2"
6ae08853 2254 [(set (attr "type")
c859cda6
DJ		 2255 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2256 (const_string "imul3")
6ae08853 2257 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2258 (const_string "imul2")]
2259 (const_string "imul")))])
1fd4e8c1 2260
9259f3b0 2261(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 2262 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2263 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2264 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2265 (const_int 0)))
9ebbca7d
GK		 2266 (clobber (match_scratch:SI 3 "=r,r"))
2267 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2268 "TARGET_POWER"
9ebbca7d
GK		 2269 "@
2270 {muls.|mullw.} %3,%1,%2
2271 #"
9259f3b0 2272 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2273 (set_attr "length" "4,8")])
2274
2275(define_split
2276 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2277 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2278 (match_operand:SI 2 "gpc_reg_operand" ""))
2279 (const_int 0)))
2280 (clobber (match_scratch:SI 3 ""))
2281 (clobber (match_scratch:SI 4 ""))]
2282 "TARGET_POWER && reload_completed"
2283 [(parallel [(set (match_dup 3)
2284 (mult:SI (match_dup 1) (match_dup 2)))
2285 (clobber (match_dup 4))])
2286 (set (match_dup 0)
2287 (compare:CC (match_dup 3)
2288 (const_int 0)))]
2289 "")
ca7f5001 2290
9259f3b0 2291(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 2292 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2293 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2294 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2295 (const_int 0)))
9ebbca7d 2296 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 2297 "! TARGET_POWER"
9ebbca7d
GK		 2298 "@
2299 {muls.|mullw.} %3,%1,%2
2300 #"
9259f3b0 2301 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2302 (set_attr "length" "4,8")])
2303
2304(define_split
2305 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2306 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2307 (match_operand:SI 2 "gpc_reg_operand" ""))
2308 (const_int 0)))
2309 (clobber (match_scratch:SI 3 ""))]
2310 "! TARGET_POWER && reload_completed"
2311 [(set (match_dup 3)
2312 (mult:SI (match_dup 1) (match_dup 2)))
2313 (set (match_dup 0)
2314 (compare:CC (match_dup 3)
2315 (const_int 0)))]
2316 "")
1fd4e8c1 2317
9259f3b0 2318(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 2319 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2320 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2321 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2322 (const_int 0)))
9ebbca7d 2323 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 2324 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 2325 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2326 "TARGET_POWER"
9ebbca7d
GK		 2327 "@
2328 {muls.|mullw.} %0,%1,%2
2329 #"
9259f3b0 2330 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2331 (set_attr "length" "4,8")])
2332
2333(define_split
2334 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2335 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2336 (match_operand:SI 2 "gpc_reg_operand" ""))
2337 (const_int 0)))
2338 (set (match_operand:SI 0 "gpc_reg_operand" "")
2339 (mult:SI (match_dup 1) (match_dup 2)))
2340 (clobber (match_scratch:SI 4 ""))]
2341 "TARGET_POWER && reload_completed"
2342 [(parallel [(set (match_dup 0)
2343 (mult:SI (match_dup 1) (match_dup 2)))
2344 (clobber (match_dup 4))])
2345 (set (match_dup 3)
2346 (compare:CC (match_dup 0)
2347 (const_int 0)))]
2348 "")
ca7f5001 2349
9259f3b0 2350(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 2351 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2352 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2353 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2354 (const_int 0)))
9ebbca7d 2355 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 2356 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 2357 "! TARGET_POWER"
9ebbca7d
GK		 2358 "@
2359 {muls.|mullw.} %0,%1,%2
2360 #"
9259f3b0 2361 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2362 (set_attr "length" "4,8")])
2363
2364(define_split
2365 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2366 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2367 (match_operand:SI 2 "gpc_reg_operand" ""))
2368 (const_int 0)))
2369 (set (match_operand:SI 0 "gpc_reg_operand" "")
2370 (mult:SI (match_dup 1) (match_dup 2)))]
2371 "! TARGET_POWER && reload_completed"
2372 [(set (match_dup 0)
2373 (mult:SI (match_dup 1) (match_dup 2)))
2374 (set (match_dup 3)
2375 (compare:CC (match_dup 0)
2376 (const_int 0)))]
2377 "")
1fd4e8c1
RK		 2378
2379;; Operand 1 is divided by operand 2; quotient goes to operand
2380;; 0 and remainder to operand 3.
2381;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2382
8ffd9c51
RK		 2383(define_expand "divmodsi4"
2384 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2385 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2386 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 2387 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 2388 (mod:SI (match_dup 1) (match_dup 2)))])]
2389 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2390 "
2391{
2392 if (! TARGET_POWER && ! TARGET_POWERPC)
2393 {
39403d82
DE		 2394 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2395 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2396 emit_insn (gen_divss_call ());
39403d82
DE		 2397 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2398 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 2399 DONE;
2400 }
2401}")
deb9225a 2402
bb157ff4 2403(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 2404 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2405 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2406 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 2407 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 2408 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 2409 "TARGET_POWER"
cfb557c4
RK		 2410 "divs %0,%1,%2"
2411 [(set_attr "type" "idiv")])
1fd4e8c1 2412
4ae234b0
GK		 2413(define_expand "udiv<mode>3"
2414 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2415 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2416 (match_operand:GPR 2 "gpc_reg_operand" "")))]
8ffd9c51
RK		 2417 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2418 "
2419{
2420 if (! TARGET_POWER && ! TARGET_POWERPC)
2421 {
39403d82
DE		 2422 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2423 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2424 emit_insn (gen_quous_call ());
39403d82 2425 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2426 DONE;
2427 }
f192bf8b
DE		 2428 else if (TARGET_POWER)
2429 {
2430 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2431 DONE;
2432 }
8ffd9c51 2433}")
deb9225a 2434
f192bf8b
DE		 2435(define_insn "udivsi3_mq"
2436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2437 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2438 (match_operand:SI 2 "gpc_reg_operand" "r")))
2439 (clobber (match_scratch:SI 3 "=q"))]
2440 "TARGET_POWERPC && TARGET_POWER"
2441 "divwu %0,%1,%2"
2442 [(set_attr "type" "idiv")])
2443
2444(define_insn "*udivsi3_no_mq"
4ae234b0
GK		 2445 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2446 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2447 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2448 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2449 "div<wd>u %0,%1,%2"
44cd321e
PS		 2450 [(set (attr "type")
2451 (cond [(match_operand:SI 0 "" "")
2452 (const_string "idiv")]
2453 (const_string "ldiv")))])
2454
ca7f5001 2455
1fd4e8c1 2456;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 2457;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 2458;; used; for PowerPC, force operands into register and do a normal divide;
2459;; for AIX common-mode, use quoss call on register operands.
4ae234b0
GK		 2460(define_expand "div<mode>3"
2461 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2462 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2463 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1fd4e8c1
RK		 2464 ""
2465 "
2466{
ca7f5001 2467 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 2468 && INTVAL (operands[2]) > 0
ca7f5001
RK		 2469 && exact_log2 (INTVAL (operands[2])) >= 0)
2470 ;
b6c9286a 2471 else if (TARGET_POWERPC)
f192bf8b 2472 {
99e8e649 2473 operands[2] = force_reg (<MODE>mode, operands[2]);
f192bf8b
DE		 2474 if (TARGET_POWER)
2475 {
2476 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2477 DONE;
2478 }
2479 }
b6c9286a 2480 else if (TARGET_POWER)
1fd4e8c1 2481 FAIL;
405c5495 2482 else
8ffd9c51 2483 {
39403d82
DE		 2484 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2485 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2486 emit_insn (gen_quoss_call ());
39403d82 2487 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2488 DONE;
2489 }
1fd4e8c1
RK		 2490}")
2491
f192bf8b
DE		 2492(define_insn "divsi3_mq"
2493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2494 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2495 (match_operand:SI 2 "gpc_reg_operand" "r")))
2496 (clobber (match_scratch:SI 3 "=q"))]
2497 "TARGET_POWERPC && TARGET_POWER"
2498 "divw %0,%1,%2"
2499 [(set_attr "type" "idiv")])
2500
4ae234b0
GK		 2501(define_insn "*div<mode>3_no_mq"
2502 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2503 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2504 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2505 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2506 "div<wd> %0,%1,%2"
44cd321e
PS		 2507 [(set (attr "type")
2508 (cond [(match_operand:SI 0 "" "")
2509 (const_string "idiv")]
2510 (const_string "ldiv")))])
f192bf8b 2511
4ae234b0
GK		 2512(define_expand "mod<mode>3"
2513 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2514 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2515 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
39b52ba2 2516 ""
1fd4e8c1
RK		 2517 "
2518{
481c7efa 2519 int i;
39b52ba2
RK		 2520 rtx temp1;
2521 rtx temp2;
2522
2bfcf297 2523 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 2524 || INTVAL (operands[2]) <= 0
2bfcf297 2525 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 2526 FAIL;
2527
4ae234b0
GK		 2528 temp1 = gen_reg_rtx (<MODE>mode);
2529 temp2 = gen_reg_rtx (<MODE>mode);
1fd4e8c1 2530
4ae234b0
GK		 2531 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2532 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2533 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
85644414 2534 DONE;
1fd4e8c1
RK		 2535}")
2536
2537(define_insn ""
4ae234b0
GK		 2538 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2539 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2540 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2bfcf297 2541 ""
4ae234b0 2542 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
943c15ed
DE		 2543 [(set_attr "type" "two")
2544 (set_attr "length" "8")])
1fd4e8c1
RK		 2545
2546(define_insn ""
9ebbca7d 2547 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2548 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2549 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2550 (const_int 0)))
4ae234b0 2551 (clobber (match_scratch:P 3 "=r,r"))]
2bfcf297 2552 ""
9ebbca7d 2553 "@
4ae234b0 2554 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
9ebbca7d 2555 #"
b19003d8 2556 [(set_attr "type" "compare")
9ebbca7d
GK		 2557 (set_attr "length" "8,12")])
2558
2559(define_split
2560 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2561 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2562 (match_operand:GPR 2 "exact_log2_cint_operand"
2563 ""))
9ebbca7d 2564 (const_int 0)))
4ae234b0 2565 (clobber (match_scratch:GPR 3 ""))]
2bfcf297 2566 "reload_completed"
9ebbca7d 2567 [(set (match_dup 3)
4ae234b0 2568 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2569 (set (match_dup 0)
2570 (compare:CC (match_dup 3)
2571 (const_int 0)))]
2572 "")
1fd4e8c1
RK		 2573
2574(define_insn ""
9ebbca7d 2575 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2576 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2577 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2578 (const_int 0)))
4ae234b0
GK		 2579 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2580 (div:P (match_dup 1) (match_dup 2)))]
2bfcf297 2581 ""
9ebbca7d 2582 "@
4ae234b0 2583 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
9ebbca7d 2584 #"
b19003d8 2585 [(set_attr "type" "compare")
9ebbca7d
GK		 2586 (set_attr "length" "8,12")])
2587
2588(define_split
2589 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2590 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2591 (match_operand:GPR 2 "exact_log2_cint_operand"
2592 ""))
9ebbca7d 2593 (const_int 0)))
4ae234b0
GK		 2594 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2595 (div:GPR (match_dup 1) (match_dup 2)))]
2bfcf297 2596 "reload_completed"
9ebbca7d 2597 [(set (match_dup 0)
4ae234b0 2598 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2599 (set (match_dup 3)
2600 (compare:CC (match_dup 0)
2601 (const_int 0)))]
2602 "")
1fd4e8c1
RK		 2603
2604(define_insn ""
cd2b37d9 2605 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2606 (udiv:SI
996a5f59 2607 (plus:DI (ashift:DI
cd2b37d9 2608 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2609 (const_int 32))
23a900dc 2610 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2611 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2612 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2613 (umod:SI
996a5f59 2614 (plus:DI (ashift:DI
1fd4e8c1 2615 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2616 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2617 (match_dup 3)))]
ca7f5001 2618 "TARGET_POWER"
cfb557c4
RK		 2619 "div %0,%1,%3"
2620 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2621
2622;; To do unsigned divide we handle the cases of the divisor looking like a
2623;; negative number. If it is a constant that is less than 2**31, we don't
2624;; have to worry about the branches. So make a few subroutines here.
2625;;
2626;; First comes the normal case.
2627(define_expand "udivmodsi4_normal"
2628 [(set (match_dup 4) (const_int 0))
2629 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2630 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2631 (const_int 32))
2632 (zero_extend:DI (match_operand:SI 1 "" "")))
2633 (match_operand:SI 2 "" "")))
2634 (set (match_operand:SI 3 "" "")
996a5f59 2635 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2636 (const_int 32))
2637 (zero_extend:DI (match_dup 1)))
2638 (match_dup 2)))])]
ca7f5001 2639 "TARGET_POWER"
1fd4e8c1
RK		 2640 "
2641{ operands[4] = gen_reg_rtx (SImode); }")
2642
2643;; This handles the branches.
2644(define_expand "udivmodsi4_tests"
2645 [(set (match_operand:SI 0 "" "") (const_int 0))
2646 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2647 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2648 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2649 (label_ref (match_operand:SI 4 "" "")) (pc)))
2650 (set (match_dup 0) (const_int 1))
2651 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2652 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2653 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2654 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2655 "TARGET_POWER"
1fd4e8c1
RK		 2656 "
2657{ operands[5] = gen_reg_rtx (CCUNSmode);
2658 operands[6] = gen_reg_rtx (CCmode);
2659}")
2660
2661(define_expand "udivmodsi4"
cd2b37d9
RK		 2662 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2663 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2664 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2665 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2666 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2667 ""
1fd4e8c1
RK		 2668 "
2669{
2670 rtx label = 0;
2671
8ffd9c51 2672 if (! TARGET_POWER)
c4d38ccb
MM		 2673 {
2674 if (! TARGET_POWERPC)
2675 {
39403d82
DE		 2676 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2677 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2678 emit_insn (gen_divus_call ());
39403d82
DE		 2679 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2680 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2681 DONE;
2682 }
2683 else
2684 FAIL;
2685 }
0081a354 2686
1fd4e8c1
RK		 2687 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2688 {
2689 operands[2] = force_reg (SImode, operands[2]);
2690 label = gen_label_rtx ();
2691 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2692 operands[3], label));
2693 }
2694 else
2695 operands[2] = force_reg (SImode, operands[2]);
2696
2697 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2698 operands[3]));
2699 if (label)
2700 emit_label (label);
2701
2702 DONE;
2703}")
0081a354 2704
fada905b
MM		 2705;; AIX architecture-independent common-mode multiply (DImode),
2706;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2707;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2708;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2709;; assumed unused if generating common-mode, so ignore.
2710(define_insn "mulh_call"
2711 [(set (reg:SI 3)
2712 (truncate:SI
2713 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2714 (sign_extend:DI (reg:SI 4)))
2715 (const_int 32))))
cf27b467 2716 (clobber (match_scratch:SI 0 "=l"))]
fada905b 2717 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2718 "bla __mulh"
2719 [(set_attr "type" "imul")])
fada905b
MM		 2720
2721(define_insn "mull_call"
2722 [(set (reg:DI 3)
2723 (mult:DI (sign_extend:DI (reg:SI 3))
2724 (sign_extend:DI (reg:SI 4))))
2725 (clobber (match_scratch:SI 0 "=l"))
2726 (clobber (reg:SI 0))]
2727 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2728 "bla __mull"
2729 [(set_attr "type" "imul")])
fada905b
MM		 2730
2731(define_insn "divss_call"
2732 [(set (reg:SI 3)
2733 (div:SI (reg:SI 3) (reg:SI 4)))
2734 (set (reg:SI 4)
2735 (mod:SI (reg:SI 3) (reg:SI 4)))
2736 (clobber (match_scratch:SI 0 "=l"))
2737 (clobber (reg:SI 0))]
2738 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2739 "bla __divss"
2740 [(set_attr "type" "idiv")])
fada905b
MM		 2741
2742(define_insn "divus_call"
8ffd9c51
RK		 2743 [(set (reg:SI 3)
2744 (udiv:SI (reg:SI 3) (reg:SI 4)))
2745 (set (reg:SI 4)
2746 (umod:SI (reg:SI 3) (reg:SI 4)))
2747 (clobber (match_scratch:SI 0 "=l"))
fada905b
MM		 2748 (clobber (reg:SI 0))
2749 (clobber (match_scratch:CC 1 "=x"))
2750 (clobber (reg:CC 69))]
2751 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2752 "bla __divus"
2753 [(set_attr "type" "idiv")])
fada905b
MM		 2754
2755(define_insn "quoss_call"
2756 [(set (reg:SI 3)
2757 (div:SI (reg:SI 3) (reg:SI 4)))
cf27b467 2758 (clobber (match_scratch:SI 0 "=l"))]
8ffd9c51 2759 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2760 "bla __quoss"
2761 [(set_attr "type" "idiv")])
0081a354 2762
fada905b
MM		 2763(define_insn "quous_call"
2764 [(set (reg:SI 3)
2765 (udiv:SI (reg:SI 3) (reg:SI 4)))
2766 (clobber (match_scratch:SI 0 "=l"))
2767 (clobber (reg:SI 0))
2768 (clobber (match_scratch:CC 1 "=x"))
2769 (clobber (reg:CC 69))]
2770 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2771 "bla __quous"
2772 [(set_attr "type" "idiv")])
8ffd9c51 2773\f
bb21487f 2774;; Logical instructions
dfbdccdb
GK		 2775;; The logical instructions are mostly combined by using match_operator,
2776;; but the plain AND insns are somewhat different because there is no
2777;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2778;; those rotate-and-mask operations. Thus, the AND insns come first.
2779
29ae5b89
JL		 2780(define_insn "andsi3"
2781 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2782 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2783 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2784 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1fd4e8c1
RK		 2785 ""
2786 "@
2787 and %0,%1,%2
ca7f5001
RK		 2788 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2789 {andil.|andi.} %0,%1,%b2
520308bc
DE		 2790 {andiu.|andis.} %0,%1,%u2"
2791 [(set_attr "type" "*,*,compare,compare")])
52d3af72
DE		 2792
2793;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2794;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2795;; machines causes an execution serialization
1fd4e8c1 2796
7cd5235b 2797(define_insn "*andsi3_internal2"
52d3af72
DE		 2798 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2799 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2800 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2801 (const_int 0)))
52d3af72
DE		 2802 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2803 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2804 "TARGET_32BIT"
1fd4e8c1
RK		 2805 "@
2806 and. %3,%1,%2
ca7f5001
RK		 2807 {andil.|andi.} %3,%1,%b2
2808 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2809 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2810 #
2811 #
2812 #
2813 #"
2814 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2815 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2816
0ba1b2ff
AM		 2817(define_insn "*andsi3_internal3"
2818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2819 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2820 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2821 (const_int 0)))
2822 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2823 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2824 "TARGET_64BIT"
0ba1b2ff
AM		 2825 "@
2826 #
2827 {andil.|andi.} %3,%1,%b2
2828 {andiu.|andis.} %3,%1,%u2
2829 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2830 #
2831 #
2832 #
2833 #"
2834 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2835 (set_attr "length" "8,4,4,4,8,8,8,8")])
2836
52d3af72
DE		 2837(define_split
2838 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2839 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2840 (match_operand:GPR 2 "and_operand" ""))
1fd4e8c1 2841 (const_int 0)))
4ae234b0 2842 (clobber (match_scratch:GPR 3 ""))
52d3af72 2843 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2844 "reload_completed"
52d3af72 2845 [(parallel [(set (match_dup 3)
4ae234b0
GK		 2846 (and:<MODE> (match_dup 1)
2847 (match_dup 2)))
52d3af72
DE		 2848 (clobber (match_dup 4))])
2849 (set (match_dup 0)
2850 (compare:CC (match_dup 3)
2851 (const_int 0)))]
2852 "")
2853
0ba1b2ff
AM		 2854;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2855;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2856
2857(define_split
2858 [(set (match_operand:CC 0 "cc_reg_operand" "")
2859 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2860 (match_operand:SI 2 "gpc_reg_operand" ""))
2861 (const_int 0)))
2862 (clobber (match_scratch:SI 3 ""))
2863 (clobber (match_scratch:CC 4 ""))]
2864 "TARGET_POWERPC64 && reload_completed"
2865 [(parallel [(set (match_dup 3)
2866 (and:SI (match_dup 1)
2867 (match_dup 2)))
2868 (clobber (match_dup 4))])
2869 (set (match_dup 0)
2870 (compare:CC (match_dup 3)
2871 (const_int 0)))]
2872 "")
2873
2874(define_insn "*andsi3_internal4"
52d3af72
DE		 2875 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2876 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2877 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2878 (const_int 0)))
2879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2880 (and:SI (match_dup 1)
2881 (match_dup 2)))
2882 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2883 "TARGET_32BIT"
1fd4e8c1
RK		 2884 "@
2885 and. %0,%1,%2
ca7f5001
RK		 2886 {andil.|andi.} %0,%1,%b2
2887 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2888 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2889 #
2890 #
2891 #
2892 #"
2893 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2894 (set_attr "length" "4,4,4,4,8,8,8,8")])
2895
0ba1b2ff
AM		 2896(define_insn "*andsi3_internal5"
2897 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2898 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2899 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2900 (const_int 0)))
2901 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2902 (and:SI (match_dup 1)
2903 (match_dup 2)))
2904 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2905 "TARGET_64BIT"
0ba1b2ff
AM		 2906 "@
2907 #
2908 {andil.|andi.} %0,%1,%b2
2909 {andiu.|andis.} %0,%1,%u2
2910 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2911 #
2912 #
2913 #
2914 #"
2915 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2916 (set_attr "length" "8,4,4,4,8,8,8,8")])
2917
52d3af72
DE		 2918(define_split
2919 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2920 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2921 (match_operand:SI 2 "and_operand" ""))
2922 (const_int 0)))
2923 (set (match_operand:SI 0 "gpc_reg_operand" "")
2924 (and:SI (match_dup 1)
2925 (match_dup 2)))
2926 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2927 "reload_completed"
52d3af72
DE		 2928 [(parallel [(set (match_dup 0)
2929 (and:SI (match_dup 1)
2930 (match_dup 2)))
2931 (clobber (match_dup 4))])
2932 (set (match_dup 3)
2933 (compare:CC (match_dup 0)
2934 (const_int 0)))]
2935 "")
1fd4e8c1 2936
0ba1b2ff
AM		 2937(define_split
2938 [(set (match_operand:CC 3 "cc_reg_operand" "")
2939 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2940 (match_operand:SI 2 "gpc_reg_operand" ""))
2941 (const_int 0)))
2942 (set (match_operand:SI 0 "gpc_reg_operand" "")
2943 (and:SI (match_dup 1)
2944 (match_dup 2)))
2945 (clobber (match_scratch:CC 4 ""))]
2946 "TARGET_POWERPC64 && reload_completed"
2947 [(parallel [(set (match_dup 0)
2948 (and:SI (match_dup 1)
2949 (match_dup 2)))
2950 (clobber (match_dup 4))])
2951 (set (match_dup 3)
2952 (compare:CC (match_dup 0)
2953 (const_int 0)))]
2954 "")
2955
2956;; Handle the PowerPC64 rlwinm corner case
2957
2958(define_insn_and_split "*andsi3_internal6"
2959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2960 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2961 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2962 "TARGET_POWERPC64"
2963 "#"
2964 "TARGET_POWERPC64"
2965 [(set (match_dup 0)
2966 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2967 (match_dup 4)))
2968 (set (match_dup 0)
2969 (rotate:SI (match_dup 0) (match_dup 5)))]
2970 "
2971{
2972 int mb = extract_MB (operands[2]);
2973 int me = extract_ME (operands[2]);
2974 operands[3] = GEN_INT (me + 1);
2975 operands[5] = GEN_INT (32 - (me + 1));
2976 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2977}"
2978 [(set_attr "length" "8")])
2979
7cd5235b 2980(define_expand "iorsi3"
cd2b37d9 2981 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 2982 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 2983 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 2984 ""
f357808b
RK		 2985 "
2986{
7cd5235b 2987 if (GET_CODE (operands[2]) == CONST_INT
677a9668 2988 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 2989 {
2990 HOST_WIDE_INT value = INTVAL (operands[2]);
677a9668 2991 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 2992 ? operands[0] : gen_reg_rtx (SImode));
2993
a260abc9
DE		 2994 emit_insn (gen_iorsi3 (tmp, operands[1],
2995 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2996 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 2997 DONE;
2998 }
f357808b
RK		 2999}")
3000
7cd5235b 3001(define_expand "xorsi3"
cd2b37d9 3002 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3003 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3004 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 3005 ""
7cd5235b 3006 "
1fd4e8c1 3007{
7cd5235b 3008 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3009 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3010 {
3011 HOST_WIDE_INT value = INTVAL (operands[2]);
677a9668 3012 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3013 ? operands[0] : gen_reg_rtx (SImode));
3014
a260abc9
DE		 3015 emit_insn (gen_xorsi3 (tmp, operands[1],
3016 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3017 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3018 DONE;
3019 }
1fd4e8c1
RK		 3020}")
3021
dfbdccdb 3022(define_insn "*boolsi3_internal1"
7cd5235b 3023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 3024 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3025 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3026 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 3027 ""
3028 "@
dfbdccdb
GK		 3029 %q3 %0,%1,%2
3030 {%q3il|%q3i} %0,%1,%b2
3031 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 3032
dfbdccdb 3033(define_insn "*boolsi3_internal2"
52d3af72 3034 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 3035 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 3036 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3037 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3038 (const_int 0)))
52d3af72 3039 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3040 "TARGET_32BIT"
52d3af72 3041 "@
dfbdccdb 3042 %q4. %3,%1,%2
52d3af72
DE		 3043 #"
3044 [(set_attr "type" "compare")
3045 (set_attr "length" "4,8")])
3046
3047(define_split
3048 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3049 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3050 [(match_operand:SI 1 "gpc_reg_operand" "")
3051 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3052 (const_int 0)))
52d3af72 3053 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3054 "TARGET_32BIT && reload_completed"
dfbdccdb 3055 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3056 (set (match_dup 0)
3057 (compare:CC (match_dup 3)
3058 (const_int 0)))]
3059 "")
815cdc52 3060
dfbdccdb 3061(define_insn "*boolsi3_internal3"
52d3af72 3062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3063 (compare:CC (match_operator:SI 4 "boolean_operator"
3064 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3065 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3066 (const_int 0)))
52d3af72 3067 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3068 (match_dup 4))]
4b8a63d6 3069 "TARGET_32BIT"
52d3af72 3070 "@
dfbdccdb 3071 %q4. %0,%1,%2
52d3af72
DE		 3072 #"
3073 [(set_attr "type" "compare")
3074 (set_attr "length" "4,8")])
3075
3076(define_split
e72247f4 3077 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3078 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3079 [(match_operand:SI 1 "gpc_reg_operand" "")
3080 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3081 (const_int 0)))
75540af0 3082 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3083 (match_dup 4))]
4b8a63d6 3084 "TARGET_32BIT && reload_completed"
dfbdccdb 3085 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3086 (set (match_dup 3)
3087 (compare:CC (match_dup 0)
3088 (const_int 0)))]
3089 "")
1fd4e8c1 3090
6ae08853 3091;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 3092;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 3093
3094(define_split
3095 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 3096 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3097 [(match_operand:SI 1 "gpc_reg_operand" "")
3098 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 3099 ""
dfbdccdb
GK		 3100 [(set (match_dup 0) (match_dup 4))
3101 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 3102"
3103{
dfbdccdb
GK		 3104 rtx i;
3105 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1c563bed 3106 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3107 operands[1], i);
dfbdccdb 3108 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
1c563bed 3109 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3110 operands[0], i);
a260abc9
DE		 3111}")
3112
dfbdccdb 3113(define_insn "*boolcsi3_internal1"
cd2b37d9 3114 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3115 (match_operator:SI 3 "boolean_operator"
3116 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3117 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 3118 ""
dfbdccdb 3119 "%q3 %0,%2,%1")
1fd4e8c1 3120
dfbdccdb 3121(define_insn "*boolcsi3_internal2"
52d3af72 3122 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3123 (compare:CC (match_operator:SI 4 "boolean_operator"
3124 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3125 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3126 (const_int 0)))
52d3af72 3127 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3128 "TARGET_32BIT"
52d3af72 3129 "@
dfbdccdb 3130 %q4. %3,%2,%1
52d3af72
DE		 3131 #"
3132 [(set_attr "type" "compare")
3133 (set_attr "length" "4,8")])
3134
3135(define_split
3136 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3137 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3138 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3139 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3140 (const_int 0)))
52d3af72 3141 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3142 "TARGET_32BIT && reload_completed"
dfbdccdb 3143 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3144 (set (match_dup 0)
3145 (compare:CC (match_dup 3)
3146 (const_int 0)))]
3147 "")
1fd4e8c1 3148
dfbdccdb 3149(define_insn "*boolcsi3_internal3"
52d3af72 3150 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3151 (compare:CC (match_operator:SI 4 "boolean_operator"
3152 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3153 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3154 (const_int 0)))
52d3af72 3155 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3156 (match_dup 4))]
4b8a63d6 3157 "TARGET_32BIT"
52d3af72 3158 "@
dfbdccdb 3159 %q4. %0,%2,%1
52d3af72
DE		 3160 #"
3161 [(set_attr "type" "compare")
3162 (set_attr "length" "4,8")])
3163
3164(define_split
e72247f4 3165 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3166 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3167 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3168 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3169 (const_int 0)))
75540af0 3170 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3171 (match_dup 4))]
4b8a63d6 3172 "TARGET_32BIT && reload_completed"
dfbdccdb 3173 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3174 (set (match_dup 3)
3175 (compare:CC (match_dup 0)
3176 (const_int 0)))]
3177 "")
3178
dfbdccdb 3179(define_insn "*boolccsi3_internal1"
cd2b37d9 3180 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3181 (match_operator:SI 3 "boolean_operator"
3182 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3183 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 3184 ""
dfbdccdb 3185 "%q3 %0,%1,%2")
1fd4e8c1 3186
dfbdccdb 3187(define_insn "*boolccsi3_internal2"
52d3af72 3188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3189 (compare:CC (match_operator:SI 4 "boolean_operator"
3190 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3191 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3192 (const_int 0)))
52d3af72 3193 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3194 "TARGET_32BIT"
52d3af72 3195 "@
dfbdccdb 3196 %q4. %3,%1,%2
52d3af72
DE		 3197 #"
3198 [(set_attr "type" "compare")
3199 (set_attr "length" "4,8")])
3200
3201(define_split
3202 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3203 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3204 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3205 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3206 (const_int 0)))
52d3af72 3207 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3208 "TARGET_32BIT && reload_completed"
dfbdccdb 3209 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3210 (set (match_dup 0)
3211 (compare:CC (match_dup 3)
3212 (const_int 0)))]
3213 "")
1fd4e8c1 3214
dfbdccdb 3215(define_insn "*boolccsi3_internal3"
52d3af72 3216 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3217 (compare:CC (match_operator:SI 4 "boolean_operator"
3218 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3219 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3220 (const_int 0)))
52d3af72 3221 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3222 (match_dup 4))]
4b8a63d6 3223 "TARGET_32BIT"
52d3af72 3224 "@
dfbdccdb 3225 %q4. %0,%1,%2
52d3af72
DE		 3226 #"
3227 [(set_attr "type" "compare")
3228 (set_attr "length" "4,8")])
3229
3230(define_split
e72247f4 3231 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3232 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3233 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3234 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3235 (const_int 0)))
75540af0 3236 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3237 (match_dup 4))]
4b8a63d6 3238 "TARGET_32BIT && reload_completed"
dfbdccdb 3239 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3240 (set (match_dup 3)
3241 (compare:CC (match_dup 0)
3242 (const_int 0)))]
3243 "")
1fd4e8c1
RK		 3244
3245;; maskir insn. We need four forms because things might be in arbitrary
3246;; orders. Don't define forms that only set CR fields because these
3247;; would modify an input register.
3248
7cd5235b 3249(define_insn "*maskir_internal1"
cd2b37d9 3250 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3251 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3252 (match_operand:SI 1 "gpc_reg_operand" "0"))
3253 (and:SI (match_dup 2)
cd2b37d9 3254 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 3255 "TARGET_POWER"
01def764 3256 "maskir %0,%3,%2")
1fd4e8c1 3257
7cd5235b 3258(define_insn "*maskir_internal2"
242e8072 3259 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3260 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3261 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 3262 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 3263 (match_dup 2))))]
ca7f5001 3264 "TARGET_POWER"
01def764 3265 "maskir %0,%3,%2")
1fd4e8c1 3266
7cd5235b 3267(define_insn "*maskir_internal3"
cd2b37d9 3268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 3269 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 3270 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 3271 (and:SI (not:SI (match_dup 2))
3272 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3273 "TARGET_POWER"
01def764 3274 "maskir %0,%3,%2")
1fd4e8c1 3275
7cd5235b 3276(define_insn "*maskir_internal4"
cd2b37d9
RK		 3277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3278 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 3279 (match_operand:SI 2 "gpc_reg_operand" "r"))
3280 (and:SI (not:SI (match_dup 2))
3281 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3282 "TARGET_POWER"
01def764 3283 "maskir %0,%3,%2")
1fd4e8c1 3284
7cd5235b 3285(define_insn "*maskir_internal5"
9ebbca7d 3286 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3287 (compare:CC
9ebbca7d
GK		 3288 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3289 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 3290 (and:SI (match_dup 2)
9ebbca7d 3291 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 3292 (const_int 0)))
9ebbca7d 3293 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3294 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3295 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 3296 "TARGET_POWER"
9ebbca7d
GK		 3297 "@
3298 maskir. %0,%3,%2
3299 #"
3300 [(set_attr "type" "compare")
3301 (set_attr "length" "4,8")])
3302
3303(define_split
3304 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3305 (compare:CC
3306 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3307 (match_operand:SI 1 "gpc_reg_operand" ""))
3308 (and:SI (match_dup 2)
3309 (match_operand:SI 3 "gpc_reg_operand" "")))
3310 (const_int 0)))
3311 (set (match_operand:SI 0 "gpc_reg_operand" "")
3312 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3313 (and:SI (match_dup 2) (match_dup 3))))]
3314 "TARGET_POWER && reload_completed"
3315 [(set (match_dup 0)
3316 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3317 (and:SI (match_dup 2) (match_dup 3))))
3318 (set (match_dup 4)
3319 (compare:CC (match_dup 0)
3320 (const_int 0)))]
3321 "")
1fd4e8c1 3322
7cd5235b 3323(define_insn "*maskir_internal6"
9ebbca7d 3324 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3325 (compare:CC
9ebbca7d
GK		 3326 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3327 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3328 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 3329 (match_dup 2)))
1fd4e8c1 3330 (const_int 0)))
9ebbca7d 3331 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3332 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3333 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 3334 "TARGET_POWER"
9ebbca7d
GK		 3335 "@
3336 maskir. %0,%3,%2
3337 #"
3338 [(set_attr "type" "compare")
3339 (set_attr "length" "4,8")])
3340
3341(define_split
3342 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3343 (compare:CC
3344 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3345 (match_operand:SI 1 "gpc_reg_operand" ""))
3346 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3347 (match_dup 2)))
3348 (const_int 0)))
3349 (set (match_operand:SI 0 "gpc_reg_operand" "")
3350 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3351 (and:SI (match_dup 3) (match_dup 2))))]
3352 "TARGET_POWER && reload_completed"
3353 [(set (match_dup 0)
3354 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3355 (and:SI (match_dup 3) (match_dup 2))))
3356 (set (match_dup 4)
3357 (compare:CC (match_dup 0)
3358 (const_int 0)))]
3359 "")
1fd4e8c1 3360
7cd5235b 3361(define_insn "*maskir_internal7"
9ebbca7d 3362 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 3363 (compare:CC
9ebbca7d
GK		 3364 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3365 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 3366 (and:SI (not:SI (match_dup 2))
9ebbca7d 3367 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 3368 (const_int 0)))
9ebbca7d 3369 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 3370 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3371 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3372 "TARGET_POWER"
9ebbca7d
GK		 3373 "@
3374 maskir. %0,%3,%2
3375 #"
3376 [(set_attr "type" "compare")
3377 (set_attr "length" "4,8")])
3378
3379(define_split
3380 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3381 (compare:CC
3382 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3383 (match_operand:SI 3 "gpc_reg_operand" ""))
3384 (and:SI (not:SI (match_dup 2))
3385 (match_operand:SI 1 "gpc_reg_operand" "")))
3386 (const_int 0)))
3387 (set (match_operand:SI 0 "gpc_reg_operand" "")
3388 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3389 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3390 "TARGET_POWER && reload_completed"
3391 [(set (match_dup 0)
3392 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3393 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3394 (set (match_dup 4)
3395 (compare:CC (match_dup 0)
3396 (const_int 0)))]
3397 "")
1fd4e8c1 3398
7cd5235b 3399(define_insn "*maskir_internal8"
9ebbca7d 3400 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3401 (compare:CC
9ebbca7d
GK		 3402 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3403 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 3404 (and:SI (not:SI (match_dup 2))
9ebbca7d 3405 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 3406 (const_int 0)))
9ebbca7d 3407 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3408 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3409 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 3410 "TARGET_POWER"
9ebbca7d
GK		 3411 "@
3412 maskir. %0,%3,%2
3413 #"
3414 [(set_attr "type" "compare")
3415 (set_attr "length" "4,8")])
fcce224d 3416
9ebbca7d
GK		 3417(define_split
3418 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3419 (compare:CC
3420 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3421 (match_operand:SI 2 "gpc_reg_operand" ""))
3422 (and:SI (not:SI (match_dup 2))
3423 (match_operand:SI 1 "gpc_reg_operand" "")))
3424 (const_int 0)))
3425 (set (match_operand:SI 0 "gpc_reg_operand" "")
3426 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3427 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3428 "TARGET_POWER && reload_completed"
3429 [(set (match_dup 0)
3430 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3431 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3432 (set (match_dup 4)
3433 (compare:CC (match_dup 0)
3434 (const_int 0)))]
3435 "")
fcce224d 3436\f
1fd4e8c1
RK		 3437;; Rotate and shift insns, in all their variants. These support shifts,
3438;; field inserts and extracts, and various combinations thereof.
034c1be0 3439(define_expand "insv"
0ad91047
DE		 3440 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3441 (match_operand:SI 1 "const_int_operand" "")
3442 (match_operand:SI 2 "const_int_operand" ""))
3443 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 3444 ""
3445 "
3446{
3447 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3448 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
14502dad
JM		 3449 compiler if the address of the structure is taken later. Likewise, do
3450 not handle invalid E500 subregs. */
034c1be0 3451 if (GET_CODE (operands[0]) == SUBREG
14502dad
JM		 3452 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3453 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3454 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
034c1be0 3455 FAIL;
a78e33fc
DE		 3456
3457 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3458 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3459 else
3460 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3461 DONE;
034c1be0
MM		 3462}")
3463
a78e33fc 3464(define_insn "insvsi"
cd2b37d9 3465 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 3466 (match_operand:SI 1 "const_int_operand" "i")
3467 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 3468 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 3469 ""
3470 "*
3471{
3472 int start = INTVAL (operands[2]) & 31;
3473 int size = INTVAL (operands[1]) & 31;
3474
89e9f3a8
MM		 3475 operands[4] = GEN_INT (32 - start - size);
3476 operands[1] = GEN_INT (start + size - 1);
a66078ee 3477 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3478}"
3479 [(set_attr "type" "insert_word")])
1fd4e8c1 3480
a78e33fc 3481(define_insn "*insvsi_internal1"
d56d506a
RK		 3482 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3483 (match_operand:SI 1 "const_int_operand" "i")
3484 (match_operand:SI 2 "const_int_operand" "i"))
6d0a8091 3485 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
d56d506a 3486 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3487 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3488 "*
3489{
3490 int shift = INTVAL (operands[4]) & 31;
3491 int start = INTVAL (operands[2]) & 31;
3492 int size = INTVAL (operands[1]) & 31;
3493
89e9f3a8 3494 operands[4] = GEN_INT (shift - start - size);
6d0a8091 3495 operands[1] = GEN_INT (start + size - 1);
a66078ee 3496 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3497}"
3498 [(set_attr "type" "insert_word")])
d56d506a 3499
a78e33fc 3500(define_insn "*insvsi_internal2"
d56d506a
RK		 3501 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3502 (match_operand:SI 1 "const_int_operand" "i")
3503 (match_operand:SI 2 "const_int_operand" "i"))
3504 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3505 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3506 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3507 "*
3508{
3509 int shift = INTVAL (operands[4]) & 31;
3510 int start = INTVAL (operands[2]) & 31;
3511 int size = INTVAL (operands[1]) & 31;
3512
89e9f3a8
MM		 3513 operands[4] = GEN_INT (32 - shift - start - size);
3514 operands[1] = GEN_INT (start + size - 1);
a66078ee 3515 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3516}"
3517 [(set_attr "type" "insert_word")])
d56d506a 3518
a78e33fc 3519(define_insn "*insvsi_internal3"
d56d506a
RK		 3520 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3521 (match_operand:SI 1 "const_int_operand" "i")
3522 (match_operand:SI 2 "const_int_operand" "i"))
3523 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3524 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 3525 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3526 "*
3527{
3528 int shift = INTVAL (operands[4]) & 31;
3529 int start = INTVAL (operands[2]) & 31;
3530 int size = INTVAL (operands[1]) & 31;
3531
89e9f3a8
MM		 3532 operands[4] = GEN_INT (32 - shift - start - size);
3533 operands[1] = GEN_INT (start + size - 1);
a66078ee 3534 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3535}"
3536 [(set_attr "type" "insert_word")])
d56d506a 3537
a78e33fc 3538(define_insn "*insvsi_internal4"
d56d506a
RK		 3539 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3540 (match_operand:SI 1 "const_int_operand" "i")
3541 (match_operand:SI 2 "const_int_operand" "i"))
3542 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3543 (match_operand:SI 4 "const_int_operand" "i")
3544 (match_operand:SI 5 "const_int_operand" "i")))]
3545 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3546 "*
3547{
3548 int extract_start = INTVAL (operands[5]) & 31;
3549 int extract_size = INTVAL (operands[4]) & 31;
3550 int insert_start = INTVAL (operands[2]) & 31;
3551 int insert_size = INTVAL (operands[1]) & 31;
3552
3553/* Align extract field with insert field */
3a598fbe 3554 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3555 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3556 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 3557}"
3558 [(set_attr "type" "insert_word")])
d56d506a 3559
f241bf89
EC		 3560;; combine patterns for rlwimi
3561(define_insn "*insvsi_internal5"
3562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3563 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3564 (match_operand:SI 1 "mask_operand" "i"))
3565 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3566 (match_operand:SI 2 "const_int_operand" "i"))
3567 (match_operand:SI 5 "mask_operand" "i"))))]
3568 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3569 "*
3570{
3571 int me = extract_ME(operands[5]);
3572 int mb = extract_MB(operands[5]);
3573 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3574 operands[2] = GEN_INT(mb);
3575 operands[1] = GEN_INT(me);
3576 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3577}"
3578 [(set_attr "type" "insert_word")])
3579
3580(define_insn "*insvsi_internal6"
3581 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3582 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3583 (match_operand:SI 2 "const_int_operand" "i"))
3584 (match_operand:SI 5 "mask_operand" "i"))
3585 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3586 (match_operand:SI 1 "mask_operand" "i"))))]
3587 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3588 "*
3589{
3590 int me = extract_ME(operands[5]);
3591 int mb = extract_MB(operands[5]);
3592 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3593 operands[2] = GEN_INT(mb);
3594 operands[1] = GEN_INT(me);
3595 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3596}"
3597 [(set_attr "type" "insert_word")])
3598
a78e33fc 3599(define_insn "insvdi"
685f3906 3600 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3601 (match_operand:SI 1 "const_int_operand" "i")
3602 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3603 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3604 "TARGET_POWERPC64"
3605 "*
3606{
3607 int start = INTVAL (operands[2]) & 63;
3608 int size = INTVAL (operands[1]) & 63;
3609
a78e33fc
DE		 3610 operands[1] = GEN_INT (64 - start - size);
3611 return \"rldimi %0,%3,%H1,%H2\";
44cd321e
PS		 3612}"
3613 [(set_attr "type" "insert_dword")])
685f3906 3614
11ac38b2
DE		 3615(define_insn "*insvdi_internal2"
3616 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3617 (match_operand:SI 1 "const_int_operand" "i")
3618 (match_operand:SI 2 "const_int_operand" "i"))
3619 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3620 (match_operand:SI 4 "const_int_operand" "i")))]
3621 "TARGET_POWERPC64
3622 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3623 "*
3624{
3625 int shift = INTVAL (operands[4]) & 63;
3626 int start = (INTVAL (operands[2]) & 63) - 32;
3627 int size = INTVAL (operands[1]) & 63;
3628
3629 operands[4] = GEN_INT (64 - shift - start - size);
3630 operands[2] = GEN_INT (start);
3631 operands[1] = GEN_INT (start + size - 1);
3632 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3633}")
3634
3635(define_insn "*insvdi_internal3"
3636 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3637 (match_operand:SI 1 "const_int_operand" "i")
3638 (match_operand:SI 2 "const_int_operand" "i"))
3639 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3640 (match_operand:SI 4 "const_int_operand" "i")))]
3641 "TARGET_POWERPC64
3642 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3643 "*
3644{
3645 int shift = INTVAL (operands[4]) & 63;
3646 int start = (INTVAL (operands[2]) & 63) - 32;
3647 int size = INTVAL (operands[1]) & 63;
3648
3649 operands[4] = GEN_INT (64 - shift - start - size);
3650 operands[2] = GEN_INT (start);
3651 operands[1] = GEN_INT (start + size - 1);
3652 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3653}")
3654
034c1be0 3655(define_expand "extzv"
0ad91047
DE		 3656 [(set (match_operand 0 "gpc_reg_operand" "")
3657 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3658 (match_operand:SI 2 "const_int_operand" "")
3659 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3660 ""
3661 "
3662{
3663 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3664 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3665 compiler if the address of the structure is taken later. */
3666 if (GET_CODE (operands[0]) == SUBREG
3667 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3668 FAIL;
a78e33fc
DE		 3669
3670 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3671 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3672 else
3673 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3674 DONE;
034c1be0
MM		 3675}")
3676
a78e33fc 3677(define_insn "extzvsi"
cd2b37d9
RK		 3678 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3679 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3680 (match_operand:SI 2 "const_int_operand" "i")
3681 (match_operand:SI 3 "const_int_operand" "i")))]
3682 ""
3683 "*
3684{
3685 int start = INTVAL (operands[3]) & 31;
3686 int size = INTVAL (operands[2]) & 31;
3687
3688 if (start + size >= 32)
3689 operands[3] = const0_rtx;
3690 else
89e9f3a8 3691 operands[3] = GEN_INT (start + size);
ca7f5001 3692 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3693}")
3694
a78e33fc 3695(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3696 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3697 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3698 (match_operand:SI 2 "const_int_operand" "i,i")
3699 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3700 (const_int 0)))
9ebbca7d 3701 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3702 ""
1fd4e8c1
RK		 3703 "*
3704{
3705 int start = INTVAL (operands[3]) & 31;
3706 int size = INTVAL (operands[2]) & 31;
3707
9ebbca7d
GK		 3708 /* Force split for non-cc0 compare. */
3709 if (which_alternative == 1)
3710 return \"#\";
3711
43a88a8c 3712 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3713 word, it is possible to use andiu. or andil. to test it. This is
3714 useful because the condition register set-use delay is smaller for
3715 andi[ul]. than for rlinm. This doesn't work when the starting bit
3716 position is 0 because the LT and GT bits may be set wrong. */
3717
3718 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3719 {
3a598fbe 3720 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3721 - (1 << (16 - (start & 15) - size))));
3722 if (start < 16)
ca7f5001 3723 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3724 else
ca7f5001 3725 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3726 }
7e69e155 3727
1fd4e8c1
RK		 3728 if (start + size >= 32)
3729 operands[3] = const0_rtx;
3730 else
89e9f3a8 3731 operands[3] = GEN_INT (start + size);
ca7f5001 3732 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3733}"
44cd321e 3734 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3735 (set_attr "length" "4,8")])
3736
3737(define_split
3738 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3739 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3740 (match_operand:SI 2 "const_int_operand" "")
3741 (match_operand:SI 3 "const_int_operand" ""))
3742 (const_int 0)))
3743 (clobber (match_scratch:SI 4 ""))]
ce71f754 3744 "reload_completed"
9ebbca7d
GK		 3745 [(set (match_dup 4)
3746 (zero_extract:SI (match_dup 1) (match_dup 2)
3747 (match_dup 3)))
3748 (set (match_dup 0)
3749 (compare:CC (match_dup 4)
3750 (const_int 0)))]
3751 "")
1fd4e8c1 3752
a78e33fc 3753(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3754 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3755 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3756 (match_operand:SI 2 "const_int_operand" "i,i")
3757 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3758 (const_int 0)))
9ebbca7d 3759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3760 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3761 ""
1fd4e8c1
RK		 3762 "*
3763{
3764 int start = INTVAL (operands[3]) & 31;
3765 int size = INTVAL (operands[2]) & 31;
3766
9ebbca7d
GK		 3767 /* Force split for non-cc0 compare. */
3768 if (which_alternative == 1)
3769 return \"#\";
3770
bc401279 3771 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3772 a shift. The bit-field must end at the LSB. */
bc401279 3773 if (start >= 16 && start + size == 32)
df031c43 3774 {
bc401279
AM		 3775 operands[3] = GEN_INT ((1 << size) - 1);
3776 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3777 }
7e69e155 3778
1fd4e8c1
RK		 3779 if (start + size >= 32)
3780 operands[3] = const0_rtx;
3781 else
89e9f3a8 3782 operands[3] = GEN_INT (start + size);
ca7f5001 3783 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3784}"
44cd321e 3785 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3786 (set_attr "length" "4,8")])
3787
3788(define_split
3789 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3790 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3791 (match_operand:SI 2 "const_int_operand" "")
3792 (match_operand:SI 3 "const_int_operand" ""))
3793 (const_int 0)))
3794 (set (match_operand:SI 0 "gpc_reg_operand" "")
3795 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3796 "reload_completed"
9ebbca7d
GK		 3797 [(set (match_dup 0)
3798 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3799 (set (match_dup 4)
3800 (compare:CC (match_dup 0)
3801 (const_int 0)))]
3802 "")
1fd4e8c1 3803
a78e33fc 3804(define_insn "extzvdi"
685f3906
DE		 3805 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3806 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3807 (match_operand:SI 2 "const_int_operand" "i")
3808 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3809 "TARGET_POWERPC64"
3810 "*
3811{
3812 int start = INTVAL (operands[3]) & 63;
3813 int size = INTVAL (operands[2]) & 63;
3814
3815 if (start + size >= 64)
3816 operands[3] = const0_rtx;
3817 else
89e9f3a8
MM		 3818 operands[3] = GEN_INT (start + size);
3819 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3820 return \"rldicl %0,%1,%3,%2\";
3821}")
3822
a78e33fc 3823(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3824 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3825 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3826 (match_operand:SI 2 "const_int_operand" "i")
3827 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3828 (const_int 0)))
29ae5b89 3829 (clobber (match_scratch:DI 4 "=r"))]
683bdff7 3830 "TARGET_64BIT"
685f3906
DE		 3831 "*
3832{
3833 int start = INTVAL (operands[3]) & 63;
3834 int size = INTVAL (operands[2]) & 63;
3835
3836 if (start + size >= 64)
3837 operands[3] = const0_rtx;
3838 else
89e9f3a8
MM		 3839 operands[3] = GEN_INT (start + size);
3840 operands[2] = GEN_INT (64 - size);
685f3906 3841 return \"rldicl. %4,%1,%3,%2\";
9a3c428b
DE		 3842}"
3843 [(set_attr "type" "compare")])
685f3906 3844
a78e33fc 3845(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3846 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3847 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3848 (match_operand:SI 2 "const_int_operand" "i")
3849 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3850 (const_int 0)))
29ae5b89 3851 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3852 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
683bdff7 3853 "TARGET_64BIT"
685f3906
DE		 3854 "*
3855{
3856 int start = INTVAL (operands[3]) & 63;
3857 int size = INTVAL (operands[2]) & 63;
3858
3859 if (start + size >= 64)
3860 operands[3] = const0_rtx;
3861 else
89e9f3a8
MM		 3862 operands[3] = GEN_INT (start + size);
3863 operands[2] = GEN_INT (64 - size);
685f3906 3864 return \"rldicl. %0,%1,%3,%2\";
9a3c428b
DE		 3865}"
3866 [(set_attr "type" "compare")])
685f3906 3867
1fd4e8c1 3868(define_insn "rotlsi3"
44cd321e
PS		 3869 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3870 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3871 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
1fd4e8c1 3872 ""
44cd321e
PS		 3873 "@
3874 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3875 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3876 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3877
a260abc9 3878(define_insn "*rotlsi3_internal2"
44cd321e
PS		 3879 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3880 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3881 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3882 (const_int 0)))
44cd321e 3883 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
ce71f754 3884 ""
9ebbca7d 3885 "@
44cd321e
PS		 3886 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3887 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3888 #
9ebbca7d 3889 #"
44cd321e
PS		 3890 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3891 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3892
3893(define_split
3894 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3895 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3896 (match_operand:SI 2 "reg_or_cint_operand" ""))
3897 (const_int 0)))
3898 (clobber (match_scratch:SI 3 ""))]
ce71f754 3899 "reload_completed"
9ebbca7d
GK		 3900 [(set (match_dup 3)
3901 (rotate:SI (match_dup 1) (match_dup 2)))
3902 (set (match_dup 0)
3903 (compare:CC (match_dup 3)
3904 (const_int 0)))]
3905 "")
1fd4e8c1 3906
a260abc9 3907(define_insn "*rotlsi3_internal3"
44cd321e
PS		 3908 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3909 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3910 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3911 (const_int 0)))
44cd321e 3912 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3913 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3914 ""
9ebbca7d 3915 "@
44cd321e
PS		 3916 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3917 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3918 #
9ebbca7d 3919 #"
44cd321e
PS		 3920 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3921 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3922
3923(define_split
3924 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3925 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3926 (match_operand:SI 2 "reg_or_cint_operand" ""))
3927 (const_int 0)))
3928 (set (match_operand:SI 0 "gpc_reg_operand" "")
3929 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3930 "reload_completed"
9ebbca7d
GK		 3931 [(set (match_dup 0)
3932 (rotate:SI (match_dup 1) (match_dup 2)))
3933 (set (match_dup 3)
3934 (compare:CC (match_dup 0)
3935 (const_int 0)))]
3936 "")
1fd4e8c1 3937
a260abc9 3938(define_insn "*rotlsi3_internal4"
44cd321e
PS		 3939 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3940 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3941 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3942 (match_operand:SI 3 "mask_operand" "n,n")))]
1fd4e8c1 3943 ""
44cd321e
PS		 3944 "@
3945 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3946 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3947 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3948
a260abc9 3949(define_insn "*rotlsi3_internal5"
44cd321e 3950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 3951 (compare:CC (and:SI
44cd321e
PS		 3952 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3953 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3954 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 3955 (const_int 0)))
44cd321e 3956 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
ce71f754 3957 ""
9ebbca7d 3958 "@
44cd321e
PS		 3959 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3960 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3961 #
9ebbca7d 3962 #"
44cd321e
PS		 3963 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3964 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3965
3966(define_split
3967 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3968 (compare:CC (and:SI
3969 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3970 (match_operand:SI 2 "reg_or_cint_operand" ""))
3971 (match_operand:SI 3 "mask_operand" ""))
3972 (const_int 0)))
3973 (clobber (match_scratch:SI 4 ""))]
ce71f754 3974 "reload_completed"
9ebbca7d
GK		 3975 [(set (match_dup 4)
3976 (and:SI (rotate:SI (match_dup 1)
3977 (match_dup 2))
3978 (match_dup 3)))
3979 (set (match_dup 0)
3980 (compare:CC (match_dup 4)
3981 (const_int 0)))]
3982 "")
1fd4e8c1 3983
a260abc9 3984(define_insn "*rotlsi3_internal6"
44cd321e 3985 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 3986 (compare:CC (and:SI
44cd321e
PS		 3987 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3988 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3989 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 3990 (const_int 0)))
44cd321e 3991 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3992 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3993 ""
9ebbca7d 3994 "@
44cd321e
PS		 3995 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
3996 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3997 #
9ebbca7d 3998 #"
44cd321e
PS		 3999 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4000 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4001
4002(define_split
4003 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4004 (compare:CC (and:SI
4005 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4006 (match_operand:SI 2 "reg_or_cint_operand" ""))
4007 (match_operand:SI 3 "mask_operand" ""))
4008 (const_int 0)))
4009 (set (match_operand:SI 0 "gpc_reg_operand" "")
4010 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4011 "reload_completed"
9ebbca7d
GK		 4012 [(set (match_dup 0)
4013 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4014 (set (match_dup 4)
4015 (compare:CC (match_dup 0)
4016 (const_int 0)))]
4017 "")
1fd4e8c1 4018
a260abc9 4019(define_insn "*rotlsi3_internal7"
cd2b37d9 4020 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4021 (zero_extend:SI
4022 (subreg:QI
cd2b37d9 4023 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4024 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4025 ""
ca7f5001 4026 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1 4027
a260abc9 4028(define_insn "*rotlsi3_internal8"
44cd321e 4029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4030 (compare:CC (zero_extend:SI
4031 (subreg:QI
44cd321e
PS		 4032 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4033 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4034 (const_int 0)))
44cd321e 4035 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4036 ""
9ebbca7d 4037 "@
44cd321e
PS		 4038 {rlnm.|rlwnm.} %3,%1,%2,0xff
4039 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4040 #
9ebbca7d 4041 #"
44cd321e
PS		 4042 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4043 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4044
4045(define_split
4046 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4047 (compare:CC (zero_extend:SI
4048 (subreg:QI
4049 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4050 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4051 (const_int 0)))
4052 (clobber (match_scratch:SI 3 ""))]
4053 "reload_completed"
4054 [(set (match_dup 3)
4055 (zero_extend:SI (subreg:QI
4056 (rotate:SI (match_dup 1)
4057 (match_dup 2)) 0)))
4058 (set (match_dup 0)
4059 (compare:CC (match_dup 3)
4060 (const_int 0)))]
4061 "")
1fd4e8c1 4062
a260abc9 4063(define_insn "*rotlsi3_internal9"
44cd321e 4064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4065 (compare:CC (zero_extend:SI
4066 (subreg:QI
44cd321e
PS		 4067 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4068 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4069 (const_int 0)))
44cd321e 4070 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4071 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4072 ""
9ebbca7d 4073 "@
44cd321e
PS		 4074 {rlnm.|rlwnm.} %0,%1,%2,0xff
4075 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4076 #
9ebbca7d 4077 #"
44cd321e
PS		 4078 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4079 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4080
4081(define_split
4082 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4083 (compare:CC (zero_extend:SI
4084 (subreg:QI
4085 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4086 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4087 (const_int 0)))
4088 (set (match_operand:SI 0 "gpc_reg_operand" "")
4089 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4090 "reload_completed"
4091 [(set (match_dup 0)
4092 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4093 (set (match_dup 3)
4094 (compare:CC (match_dup 0)
4095 (const_int 0)))]
4096 "")
1fd4e8c1 4097
a260abc9 4098(define_insn "*rotlsi3_internal10"
44cd321e 4099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4100 (zero_extend:SI
4101 (subreg:HI
44cd321e
PS		 4102 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4103 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
1fd4e8c1 4104 ""
44cd321e
PS		 4105 "@
4106 {rlnm|rlwnm} %0,%1,%2,0xffff
4107 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4108 [(set_attr "type" "var_shift_rotate,integer")])
4109
1fd4e8c1 4110
a260abc9 4111(define_insn "*rotlsi3_internal11"
44cd321e 4112 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4113 (compare:CC (zero_extend:SI
4114 (subreg:HI
44cd321e
PS		 4115 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4116 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4117 (const_int 0)))
44cd321e 4118 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4119 ""
9ebbca7d 4120 "@
44cd321e
PS		 4121 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4122 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4123 #
9ebbca7d 4124 #"
44cd321e
PS		 4125 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4126 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4127
4128(define_split
4129 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4130 (compare:CC (zero_extend:SI
4131 (subreg:HI
4132 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4133 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4134 (const_int 0)))
4135 (clobber (match_scratch:SI 3 ""))]
4136 "reload_completed"
4137 [(set (match_dup 3)
4138 (zero_extend:SI (subreg:HI
4139 (rotate:SI (match_dup 1)
4140 (match_dup 2)) 0)))
4141 (set (match_dup 0)
4142 (compare:CC (match_dup 3)
4143 (const_int 0)))]
4144 "")
1fd4e8c1 4145
a260abc9 4146(define_insn "*rotlsi3_internal12"
44cd321e 4147 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4148 (compare:CC (zero_extend:SI
4149 (subreg:HI
44cd321e
PS		 4150 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4151 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4152 (const_int 0)))
44cd321e 4153 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4154 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4155 ""
9ebbca7d 4156 "@
44cd321e
PS		 4157 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4158 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4159 #
9ebbca7d 4160 #"
44cd321e
PS		 4161 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4162 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4163
4164(define_split
4165 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4166 (compare:CC (zero_extend:SI
4167 (subreg:HI
4168 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4169 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4170 (const_int 0)))
4171 (set (match_operand:SI 0 "gpc_reg_operand" "")
4172 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4173 "reload_completed"
4174 [(set (match_dup 0)
4175 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4176 (set (match_dup 3)
4177 (compare:CC (match_dup 0)
4178 (const_int 0)))]
4179 "")
1fd4e8c1
RK		 4180
4181;; Note that we use "sle." instead of "sl." so that we can set
4182;; SHIFT_COUNT_TRUNCATED.
4183
ca7f5001
RK		 4184(define_expand "ashlsi3"
4185 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4186 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4187 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4188 ""
4189 "
4190{
4191 if (TARGET_POWER)
4192 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4193 else
25c341fa 4194 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4195 DONE;
4196}")
4197
4198(define_insn "ashlsi3_power"
cd2b37d9
RK		 4199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4200 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4201 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4202 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4203 "TARGET_POWER"
1fd4e8c1
RK		 4204 "@
4205 sle %0,%1,%2
9ebbca7d 4206 {sli|slwi} %0,%1,%h2")
ca7f5001 4207
25c341fa 4208(define_insn "ashlsi3_no_power"
44cd321e
PS		 4209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4210 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4211 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4212 "! TARGET_POWER"
44cd321e
PS		 4213 "@
4214 {sl|slw} %0,%1,%2
4215 {sli|slwi} %0,%1,%h2"
4216 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4217
4218(define_insn ""
9ebbca7d
GK		 4219 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4220 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4221 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4222 (const_int 0)))
9ebbca7d
GK		 4223 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4224 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4225 "TARGET_POWER"
1fd4e8c1
RK		 4226 "@
4227 sle. %3,%1,%2
9ebbca7d
GK		 4228 {sli.|slwi.} %3,%1,%h2
4229 #
4230 #"
4231 [(set_attr "type" "delayed_compare")
4232 (set_attr "length" "4,4,8,8")])
4233
4234(define_split
4235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4236 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4237 (match_operand:SI 2 "reg_or_cint_operand" ""))
4238 (const_int 0)))
4239 (clobber (match_scratch:SI 3 ""))
4240 (clobber (match_scratch:SI 4 ""))]
4241 "TARGET_POWER && reload_completed"
4242 [(parallel [(set (match_dup 3)
4243 (ashift:SI (match_dup 1) (match_dup 2)))
4244 (clobber (match_dup 4))])
4245 (set (match_dup 0)
4246 (compare:CC (match_dup 3)
4247 (const_int 0)))]
4248 "")
25c341fa 4249
ca7f5001 4250(define_insn ""
44cd321e
PS		 4251 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4252 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4253 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4254 (const_int 0)))
44cd321e 4255 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4b8a63d6 4256 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4257 "@
44cd321e
PS		 4258 {sl.|slw.} %3,%1,%2
4259 {sli.|slwi.} %3,%1,%h2
4260 #
9ebbca7d 4261 #"
44cd321e
PS		 4262 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4263 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4264
4265(define_split
4266 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4267 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4268 (match_operand:SI 2 "reg_or_cint_operand" ""))
4269 (const_int 0)))
4270 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4271 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4272 [(set (match_dup 3)
4273 (ashift:SI (match_dup 1) (match_dup 2)))
4274 (set (match_dup 0)
4275 (compare:CC (match_dup 3)
4276 (const_int 0)))]
4277 "")
1fd4e8c1
RK		 4278
4279(define_insn ""
9ebbca7d
GK		 4280 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4281 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4282 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4283 (const_int 0)))
9ebbca7d 4284 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4285 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4286 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4287 "TARGET_POWER"
1fd4e8c1
RK		 4288 "@
4289 sle. %0,%1,%2
9ebbca7d
GK		 4290 {sli.|slwi.} %0,%1,%h2
4291 #
4292 #"
4293 [(set_attr "type" "delayed_compare")
4294 (set_attr "length" "4,4,8,8")])
4295
4296(define_split
4297 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4298 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4299 (match_operand:SI 2 "reg_or_cint_operand" ""))
4300 (const_int 0)))
4301 (set (match_operand:SI 0 "gpc_reg_operand" "")
4302 (ashift:SI (match_dup 1) (match_dup 2)))
4303 (clobber (match_scratch:SI 4 ""))]
4304 "TARGET_POWER && reload_completed"
4305 [(parallel [(set (match_dup 0)
4306 (ashift:SI (match_dup 1) (match_dup 2)))
4307 (clobber (match_dup 4))])
4308 (set (match_dup 3)
4309 (compare:CC (match_dup 0)
4310 (const_int 0)))]
4311 "")
25c341fa 4312
ca7f5001 4313(define_insn ""
44cd321e
PS		 4314 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4315 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4316 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4317 (const_int 0)))
44cd321e 4318 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 4319 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4320 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4321 "@
44cd321e
PS		 4322 {sl.|slw.} %0,%1,%2
4323 {sli.|slwi.} %0,%1,%h2
4324 #
9ebbca7d 4325 #"
44cd321e
PS		 4326 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4327 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4328
4329(define_split
4330 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4331 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4332 (match_operand:SI 2 "reg_or_cint_operand" ""))
4333 (const_int 0)))
4334 (set (match_operand:SI 0 "gpc_reg_operand" "")
4335 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4336 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4337 [(set (match_dup 0)
4338 (ashift:SI (match_dup 1) (match_dup 2)))
4339 (set (match_dup 3)
4340 (compare:CC (match_dup 0)
4341 (const_int 0)))]
4342 "")
1fd4e8c1 4343
915167f5 4344(define_insn "rlwinm"
cd2b37d9
RK		 4345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4346 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4347 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4348 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4349 "includes_lshift_p (operands[2], operands[3])"
d56d506a 4350 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 4351
4352(define_insn ""
9ebbca7d 4353 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4354 (compare:CC
9ebbca7d
GK		 4355 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4356 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4357 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4358 (const_int 0)))
9ebbca7d 4359 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4360 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4361 "@
4362 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4363 #"
4364 [(set_attr "type" "delayed_compare")
4365 (set_attr "length" "4,8")])
4366
4367(define_split
4368 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4369 (compare:CC
4370 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4371 (match_operand:SI 2 "const_int_operand" ""))
4372 (match_operand:SI 3 "mask_operand" ""))
4373 (const_int 0)))
4374 (clobber (match_scratch:SI 4 ""))]
ce71f754 4375 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4376 [(set (match_dup 4)
4377 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4378 (match_dup 3)))
4379 (set (match_dup 0)
4380 (compare:CC (match_dup 4)
4381 (const_int 0)))]
4382 "")
1fd4e8c1
RK		 4383
4384(define_insn ""
9ebbca7d 4385 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4386 (compare:CC
9ebbca7d
GK		 4387 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4388 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4389 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4390 (const_int 0)))
9ebbca7d 4391 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4392 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4393 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4394 "@
4395 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4396 #"
4397 [(set_attr "type" "delayed_compare")
4398 (set_attr "length" "4,8")])
4399
4400(define_split
4401 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4402 (compare:CC
4403 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4404 (match_operand:SI 2 "const_int_operand" ""))
4405 (match_operand:SI 3 "mask_operand" ""))
4406 (const_int 0)))
4407 (set (match_operand:SI 0 "gpc_reg_operand" "")
4408 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4409 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4410 [(set (match_dup 0)
4411 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4412 (set (match_dup 4)
4413 (compare:CC (match_dup 0)
4414 (const_int 0)))]
4415 "")
1fd4e8c1 4416
ca7f5001 4417;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 4418;; "sli x,x,0".
ca7f5001
RK		 4419(define_expand "lshrsi3"
4420 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4421 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4422 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4423 ""
4424 "
4425{
4426 if (TARGET_POWER)
4427 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4428 else
25c341fa 4429 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4430 DONE;
4431}")
4432
4433(define_insn "lshrsi3_power"
bdf423cb
MM		 4434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4435 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4436 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4437 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 4438 "TARGET_POWER"
1fd4e8c1
RK		 4439 "@
4440 sre %0,%1,%2
bdf423cb 4441 mr %0,%1
ca7f5001
RK		 4442 {s%A2i|s%A2wi} %0,%1,%h2")
4443
25c341fa 4444(define_insn "lshrsi3_no_power"
44cd321e
PS		 4445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4446 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4447 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
25c341fa 4448 "! TARGET_POWER"
bdf423cb
MM		 4449 "@
4450 mr %0,%1
44cd321e
PS		 4451 {sr|srw} %0,%1,%2
4452 {sri|srwi} %0,%1,%h2"
4453 [(set_attr "type" "integer,var_shift_rotate,shift")])
1fd4e8c1
RK		 4454
4455(define_insn ""
9ebbca7d
GK		 4456 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4457 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4458 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4459 (const_int 0)))
9ebbca7d
GK		 4460 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4461 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4462 "TARGET_POWER"
1fd4e8c1 4463 "@
29ae5b89
JL		 4464 sre. %3,%1,%2
4465 mr. %1,%1
9ebbca7d
GK		 4466 {s%A2i.|s%A2wi.} %3,%1,%h2
4467 #
4468 #
4469 #"
4470 [(set_attr "type" "delayed_compare")
4471 (set_attr "length" "4,4,4,8,8,8")])
4472
4473(define_split
4474 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4475 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4476 (match_operand:SI 2 "reg_or_cint_operand" ""))
4477 (const_int 0)))
4478 (clobber (match_scratch:SI 3 ""))
4479 (clobber (match_scratch:SI 4 ""))]
4480 "TARGET_POWER && reload_completed"
4481 [(parallel [(set (match_dup 3)
4482 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4483 (clobber (match_dup 4))])
4484 (set (match_dup 0)
4485 (compare:CC (match_dup 3)
4486 (const_int 0)))]
4487 "")
ca7f5001
RK		 4488
4489(define_insn ""
44cd321e
PS		 4490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4491 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4492 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
ca7f5001 4493 (const_int 0)))
44cd321e 4494 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4b8a63d6 4495 "! TARGET_POWER && TARGET_32BIT"
bdf423cb
MM		 4496 "@
4497 mr. %1,%1
44cd321e
PS		 4498 {sr.|srw.} %3,%1,%2
4499 {sri.|srwi.} %3,%1,%h2
4500 #
9ebbca7d
GK		 4501 #
4502 #"
44cd321e
PS		 4503 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4504 (set_attr "length" "4,4,4,8,8,8")])
1fd4e8c1 4505
9ebbca7d
GK		 4506(define_split
4507 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4508 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4509 (match_operand:SI 2 "reg_or_cint_operand" ""))
4510 (const_int 0)))
4511 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4512 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4513 [(set (match_dup 3)
4514 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4515 (set (match_dup 0)
4516 (compare:CC (match_dup 3)
4517 (const_int 0)))]
4518 "")
4519
4520(define_insn ""
4521 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4522 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4523 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4524 (const_int 0)))
9ebbca7d 4525 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 4526 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4527 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4528 "TARGET_POWER"
1fd4e8c1 4529 "@
29ae5b89
JL		 4530 sre. %0,%1,%2
4531 mr. %0,%1
9ebbca7d
GK		 4532 {s%A2i.|s%A2wi.} %0,%1,%h2
4533 #
4534 #
4535 #"
4536 [(set_attr "type" "delayed_compare")
4537 (set_attr "length" "4,4,4,8,8,8")])
4538
4539(define_split
4540 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4541 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4542 (match_operand:SI 2 "reg_or_cint_operand" ""))
4543 (const_int 0)))
4544 (set (match_operand:SI 0 "gpc_reg_operand" "")
4545 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4546 (clobber (match_scratch:SI 4 ""))]
4547 "TARGET_POWER && reload_completed"
4548 [(parallel [(set (match_dup 0)
4549 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4550 (clobber (match_dup 4))])
4551 (set (match_dup 3)
4552 (compare:CC (match_dup 0)
4553 (const_int 0)))]
4554 "")
ca7f5001
RK		 4555
4556(define_insn ""
44cd321e
PS		 4557 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4558 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4559 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
815cdc52 4560 (const_int 0)))
44cd321e 4561 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
29ae5b89 4562 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4563 "! TARGET_POWER && TARGET_32BIT"
29ae5b89
JL		 4564 "@
4565 mr. %0,%1
44cd321e
PS		 4566 {sr.|srw.} %0,%1,%2
4567 {sri.|srwi.} %0,%1,%h2
4568 #
9ebbca7d
GK		 4569 #
4570 #"
44cd321e
PS		 4571 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4572 (set_attr "length" "4,4,4,8,8,8")])
9ebbca7d
GK		 4573
4574(define_split
4575 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4576 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4577 (match_operand:SI 2 "reg_or_cint_operand" ""))
4578 (const_int 0)))
4579 (set (match_operand:SI 0 "gpc_reg_operand" "")
4580 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4581 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4582 [(set (match_dup 0)
4583 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4584 (set (match_dup 3)
4585 (compare:CC (match_dup 0)
4586 (const_int 0)))]
4587 "")
1fd4e8c1
RK		 4588
4589(define_insn ""
cd2b37d9
RK		 4590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4591 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4592 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4593 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4594 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 4595 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 4596
4597(define_insn ""
9ebbca7d 4598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4599 (compare:CC
9ebbca7d
GK		 4600 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4601 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4602 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4603 (const_int 0)))
9ebbca7d 4604 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4605 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4606 "@
4607 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4608 #"
4609 [(set_attr "type" "delayed_compare")
4610 (set_attr "length" "4,8")])
4611
4612(define_split
4613 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4614 (compare:CC
4615 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4616 (match_operand:SI 2 "const_int_operand" ""))
4617 (match_operand:SI 3 "mask_operand" ""))
4618 (const_int 0)))
4619 (clobber (match_scratch:SI 4 ""))]
ce71f754 4620 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4621 [(set (match_dup 4)
4622 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4623 (match_dup 3)))
4624 (set (match_dup 0)
4625 (compare:CC (match_dup 4)
4626 (const_int 0)))]
4627 "")
1fd4e8c1
RK		 4628
4629(define_insn ""
9ebbca7d 4630 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4631 (compare:CC
9ebbca7d
GK		 4632 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4633 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4634 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4635 (const_int 0)))
9ebbca7d 4636 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4637 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4638 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4639 "@
4640 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4641 #"
4642 [(set_attr "type" "delayed_compare")
4643 (set_attr "length" "4,8")])
4644
4645(define_split
4646 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4647 (compare:CC
4648 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4649 (match_operand:SI 2 "const_int_operand" ""))
4650 (match_operand:SI 3 "mask_operand" ""))
4651 (const_int 0)))
4652 (set (match_operand:SI 0 "gpc_reg_operand" "")
4653 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4654 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4655 [(set (match_dup 0)
4656 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4657 (set (match_dup 4)
4658 (compare:CC (match_dup 0)
4659 (const_int 0)))]
4660 "")
1fd4e8c1
RK		 4661
4662(define_insn ""
cd2b37d9 4663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4664 (zero_extend:SI
4665 (subreg:QI
cd2b37d9 4666 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4667 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4668 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4669 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4670
4671(define_insn ""
9ebbca7d 4672 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4673 (compare:CC
4674 (zero_extend:SI
4675 (subreg:QI
9ebbca7d
GK		 4676 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4677 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4678 (const_int 0)))
9ebbca7d 4679 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4680 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4681 "@
4682 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4683 #"
4684 [(set_attr "type" "delayed_compare")
4685 (set_attr "length" "4,8")])
4686
4687(define_split
4688 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4689 (compare:CC
4690 (zero_extend:SI
4691 (subreg:QI
4692 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4693 (match_operand:SI 2 "const_int_operand" "")) 0))
4694 (const_int 0)))
4695 (clobber (match_scratch:SI 3 ""))]
4696 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4697 [(set (match_dup 3)
4698 (zero_extend:SI (subreg:QI
4699 (lshiftrt:SI (match_dup 1)
4700 (match_dup 2)) 0)))
4701 (set (match_dup 0)
4702 (compare:CC (match_dup 3)
4703 (const_int 0)))]
4704 "")
1fd4e8c1
RK		 4705
4706(define_insn ""
9ebbca7d 4707 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4708 (compare:CC
4709 (zero_extend:SI
4710 (subreg:QI
9ebbca7d
GK		 4711 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4712 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4713 (const_int 0)))
9ebbca7d 4714 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4715 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4716 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4717 "@
4718 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4719 #"
4720 [(set_attr "type" "delayed_compare")
4721 (set_attr "length" "4,8")])
4722
4723(define_split
4724 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4725 (compare:CC
4726 (zero_extend:SI
4727 (subreg:QI
4728 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4729 (match_operand:SI 2 "const_int_operand" "")) 0))
4730 (const_int 0)))
4731 (set (match_operand:SI 0 "gpc_reg_operand" "")
4732 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4733 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4734 [(set (match_dup 0)
4735 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4736 (set (match_dup 3)
4737 (compare:CC (match_dup 0)
4738 (const_int 0)))]
4739 "")
1fd4e8c1
RK		 4740
4741(define_insn ""
cd2b37d9 4742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4743 (zero_extend:SI
4744 (subreg:HI
cd2b37d9 4745 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4746 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4747 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4748 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4749
4750(define_insn ""
9ebbca7d 4751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4752 (compare:CC
4753 (zero_extend:SI
4754 (subreg:HI
9ebbca7d
GK		 4755 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4756 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4757 (const_int 0)))
9ebbca7d 4758 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4759 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4760 "@
4761 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4762 #"
4763 [(set_attr "type" "delayed_compare")
4764 (set_attr "length" "4,8")])
4765
4766(define_split
4767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4768 (compare:CC
4769 (zero_extend:SI
4770 (subreg:HI
4771 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4772 (match_operand:SI 2 "const_int_operand" "")) 0))
4773 (const_int 0)))
4774 (clobber (match_scratch:SI 3 ""))]
4775 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4776 [(set (match_dup 3)
4777 (zero_extend:SI (subreg:HI
4778 (lshiftrt:SI (match_dup 1)
4779 (match_dup 2)) 0)))
4780 (set (match_dup 0)
4781 (compare:CC (match_dup 3)
4782 (const_int 0)))]
4783 "")
1fd4e8c1
RK		 4784
4785(define_insn ""
9ebbca7d 4786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4787 (compare:CC
4788 (zero_extend:SI
4789 (subreg:HI
9ebbca7d
GK		 4790 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4791 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4792 (const_int 0)))
9ebbca7d 4793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4794 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4795 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4796 "@
4797 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4798 #"
4799 [(set_attr "type" "delayed_compare")
4800 (set_attr "length" "4,8")])
4801
4802(define_split
4803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4804 (compare:CC
4805 (zero_extend:SI
4806 (subreg:HI
4807 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4808 (match_operand:SI 2 "const_int_operand" "")) 0))
4809 (const_int 0)))
4810 (set (match_operand:SI 0 "gpc_reg_operand" "")
4811 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4812 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4813 [(set (match_dup 0)
4814 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4815 (set (match_dup 3)
4816 (compare:CC (match_dup 0)
4817 (const_int 0)))]
4818 "")
1fd4e8c1
RK		 4819
4820(define_insn ""
cd2b37d9 4821 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4822 (const_int 1)
cd2b37d9
RK		 4823 (match_operand:SI 1 "gpc_reg_operand" "r"))
4824 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4825 (const_int 31)))]
ca7f5001 4826 "TARGET_POWER"
1fd4e8c1
RK		 4827 "rrib %0,%1,%2")
4828
4829(define_insn ""
cd2b37d9 4830 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4831 (const_int 1)
cd2b37d9
RK		 4832 (match_operand:SI 1 "gpc_reg_operand" "r"))
4833 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4834 (const_int 31)))]
ca7f5001 4835 "TARGET_POWER"
1fd4e8c1
RK		 4836 "rrib %0,%1,%2")
4837
4838(define_insn ""
cd2b37d9 4839 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4840 (const_int 1)
cd2b37d9
RK		 4841 (match_operand:SI 1 "gpc_reg_operand" "r"))
4842 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4843 (const_int 1)
4844 (const_int 0)))]
ca7f5001 4845 "TARGET_POWER"
1fd4e8c1
RK		 4846 "rrib %0,%1,%2")
4847
ca7f5001
RK		 4848(define_expand "ashrsi3"
4849 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4850 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4851 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4852 ""
4853 "
4854{
4855 if (TARGET_POWER)
4856 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4857 else
25c341fa 4858 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4859 DONE;
4860}")
4861
4862(define_insn "ashrsi3_power"
cd2b37d9
RK		 4863 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4864 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4865 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4866 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4867 "TARGET_POWER"
1fd4e8c1
RK		 4868 "@
4869 srea %0,%1,%2
44cd321e
PS		 4870 {srai|srawi} %0,%1,%h2"
4871 [(set_attr "type" "shift")])
ca7f5001 4872
25c341fa 4873(define_insn "ashrsi3_no_power"
44cd321e
PS		 4874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4875 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4876 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4877 "! TARGET_POWER"
44cd321e
PS		 4878 "@
4879 {sra|sraw} %0,%1,%2
4880 {srai|srawi} %0,%1,%h2"
4881 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4882
4883(define_insn ""
9ebbca7d
GK		 4884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4885 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4886 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4887 (const_int 0)))
9ebbca7d
GK		 4888 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4889 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4890 "TARGET_POWER"
1fd4e8c1
RK		 4891 "@
4892 srea. %3,%1,%2
9ebbca7d
GK		 4893 {srai.|srawi.} %3,%1,%h2
4894 #
4895 #"
4896 [(set_attr "type" "delayed_compare")
4897 (set_attr "length" "4,4,8,8")])
4898
4899(define_split
4900 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4901 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4902 (match_operand:SI 2 "reg_or_cint_operand" ""))
4903 (const_int 0)))
4904 (clobber (match_scratch:SI 3 ""))
4905 (clobber (match_scratch:SI 4 ""))]
4906 "TARGET_POWER && reload_completed"
4907 [(parallel [(set (match_dup 3)
4908 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4909 (clobber (match_dup 4))])
4910 (set (match_dup 0)
4911 (compare:CC (match_dup 3)
4912 (const_int 0)))]
4913 "")
ca7f5001
RK		 4914
4915(define_insn ""
44cd321e
PS		 4916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4917 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4918 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4919 (const_int 0)))
44cd321e 4920 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
25c341fa 4921 "! TARGET_POWER"
9ebbca7d 4922 "@
44cd321e
PS		 4923 {sra.|sraw.} %3,%1,%2
4924 {srai.|srawi.} %3,%1,%h2
4925 #
9ebbca7d 4926 #"
44cd321e
PS		 4927 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4928 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4929
4930(define_split
4931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4932 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4933 (match_operand:SI 2 "reg_or_cint_operand" ""))
4934 (const_int 0)))
4935 (clobber (match_scratch:SI 3 ""))]
4936 "! TARGET_POWER && reload_completed"
4937 [(set (match_dup 3)
4938 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4939 (set (match_dup 0)
4940 (compare:CC (match_dup 3)
4941 (const_int 0)))]
4942 "")
1fd4e8c1
RK		 4943
4944(define_insn ""
9ebbca7d
GK		 4945 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4946 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4947 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4948 (const_int 0)))
9ebbca7d 4949 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4950 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4951 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4952 "TARGET_POWER"
1fd4e8c1
RK		 4953 "@
4954 srea. %0,%1,%2
9ebbca7d
GK		 4955 {srai.|srawi.} %0,%1,%h2
4956 #
4957 #"
4958 [(set_attr "type" "delayed_compare")
4959 (set_attr "length" "4,4,8,8")])
4960
4961(define_split
4962 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4963 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4964 (match_operand:SI 2 "reg_or_cint_operand" ""))
4965 (const_int 0)))
4966 (set (match_operand:SI 0 "gpc_reg_operand" "")
4967 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4968 (clobber (match_scratch:SI 4 ""))]
4969 "TARGET_POWER && reload_completed"
4970 [(parallel [(set (match_dup 0)
4971 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4972 (clobber (match_dup 4))])
4973 (set (match_dup 3)
4974 (compare:CC (match_dup 0)
4975 (const_int 0)))]
4976 "")
1fd4e8c1 4977
ca7f5001 4978(define_insn ""
44cd321e
PS		 4979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4980 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4981 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4982 (const_int 0)))
44cd321e 4983 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 4984 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 4985 "! TARGET_POWER"
9ebbca7d 4986 "@
44cd321e
PS		 4987 {sra.|sraw.} %0,%1,%2
4988 {srai.|srawi.} %0,%1,%h2
4989 #
9ebbca7d 4990 #"
44cd321e
PS		 4991 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4992 (set_attr "length" "4,4,8,8")])
1fd4e8c1 4993\f
9ebbca7d
GK		 4994(define_split
4995 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4996 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4997 (match_operand:SI 2 "reg_or_cint_operand" ""))
4998 (const_int 0)))
4999 (set (match_operand:SI 0 "gpc_reg_operand" "")
5000 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5001 "! TARGET_POWER && reload_completed"
5002 [(set (match_dup 0)
5003 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5004 (set (match_dup 3)
5005 (compare:CC (match_dup 0)
5006 (const_int 0)))]
5007 "")
5008
1fd4e8c1
RK		 5009;; Floating-point insns, excluding normal data motion.
5010;;
ca7f5001
RK		 5011;; PowerPC has a full set of single-precision floating point instructions.
5012;;
5013;; For the POWER architecture, we pretend that we have both SFmode and
5014;; DFmode insns, while, in fact, all fp insns are actually done in double.
5015;; The only conversions we will do will be when storing to memory. In that
5016;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 5017;;
5018;; Note that when we store into a single-precision memory location, we need to
5019;; use the frsp insn first. If the register being stored isn't dead, we
5020;; need a scratch register for the frsp. But this is difficult when the store
5021;; is done by reload. It is not incorrect to do the frsp on the register in
5022;; this case, we just lose precision that we would have otherwise gotten but
5023;; is not guaranteed. Perhaps this should be tightened up at some point.
5024
99176a91
AH		 5025(define_expand "extendsfdf2"
5026 [(set (match_operand:DF 0 "gpc_reg_operand" "")
97c54d9a 5027 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
99176a91
AH		 5028 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5029 "")
5030
5031(define_insn_and_split "*extendsfdf2_fpr"
97c54d9a
DE		 5032 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5033 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
a3170dc6 5034 "TARGET_HARD_FLOAT && TARGET_FPRS"
11ac38b2
DE		 5035 "@
5036 #
97c54d9a
DE		 5037 fmr %0,%1
5038 lfs%U1%X1 %0,%1"
d7b1468b 5039 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
11ac38b2 5040 [(const_int 0)]
5c30aff8 5041{
11ac38b2
DE		 5042 emit_note (NOTE_INSN_DELETED);
5043 DONE;
5044}
97c54d9a 5045 [(set_attr "type" "fp,fp,fpload")])
1fd4e8c1 5046
7a2f7870
AH		 5047(define_expand "truncdfsf2"
5048 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5049 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5050 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5051 "")
5052
99176a91 5053(define_insn "*truncdfsf2_fpr"
cd2b37d9
RK		 5054 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5055 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5056 "TARGET_HARD_FLOAT && TARGET_FPRS"
dcac138d 5057 "frsp %0,%1"
1fd4e8c1
RK		 5058 [(set_attr "type" "fp")])
5059
455350f4
RK		 5060(define_insn "aux_truncdfsf2"
5061 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 5062 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
a3170dc6 5063 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 5064 "frsp %0,%1"
5065 [(set_attr "type" "fp")])
5066
a3170dc6
AH		 5067(define_expand "negsf2"
5068 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5069 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5070 "TARGET_HARD_FLOAT"
5071 "")
5072
5073(define_insn "*negsf2"
cd2b37d9
RK		 5074 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5075 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5076 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5077 "fneg %0,%1"
5078 [(set_attr "type" "fp")])
5079
a3170dc6
AH		 5080(define_expand "abssf2"
5081 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5082 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5083 "TARGET_HARD_FLOAT"
5084 "")
5085
5086(define_insn "*abssf2"
cd2b37d9
RK		 5087 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5088 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5089 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5090 "fabs %0,%1"
5091 [(set_attr "type" "fp")])
5092
5093(define_insn ""
cd2b37d9
RK		 5094 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5095 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
a3170dc6 5096 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5097 "fnabs %0,%1"
5098 [(set_attr "type" "fp")])
5099
ca7f5001
RK		 5100(define_expand "addsf3"
5101 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5102 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5103 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5104 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5105 "")
5106
5107(define_insn ""
cd2b37d9
RK		 5108 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5109 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5110 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5111 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5112 "fadds %0,%1,%2"
ca7f5001
RK		 5113 [(set_attr "type" "fp")])
5114
5115(define_insn ""
5116 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5117 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5118 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5119 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5120 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 5121 [(set_attr "type" "fp")])
5122
5123(define_expand "subsf3"
5124 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5125 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5126 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5127 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5128 "")
5129
5130(define_insn ""
5131 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5132 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5133 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5134 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5135 "fsubs %0,%1,%2"
1fd4e8c1
RK		 5136 [(set_attr "type" "fp")])
5137
ca7f5001 5138(define_insn ""
cd2b37d9
RK		 5139 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5140 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5141 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5142 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5143 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 5144 [(set_attr "type" "fp")])
5145
5146(define_expand "mulsf3"
5147 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5148 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5149 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5150 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5151 "")
5152
5153(define_insn ""
5154 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5155 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5156 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5157 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5158 "fmuls %0,%1,%2"
1fd4e8c1
RK		 5159 [(set_attr "type" "fp")])
5160
ca7f5001 5161(define_insn ""
cd2b37d9
RK		 5162 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5163 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5164 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5165 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5166 "{fm|fmul} %0,%1,%2"
0780f386 5167 [(set_attr "type" "dmul")])
1fd4e8c1 5168
ef765ea9
DE		 5169(define_insn "fres"
5170 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5171 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5172 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5173 "fres %0,%1"
5174 [(set_attr "type" "fp")])
5175
ca7f5001
RK		 5176(define_expand "divsf3"
5177 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5178 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5179 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5180 "TARGET_HARD_FLOAT"
ef765ea9
DE		 5181{
5182 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5183 && flag_finite_math_only && !flag_trapping_math)
5184 {
5185 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5186 DONE;
5187 }
5188})
ca7f5001
RK		 5189
5190(define_insn ""
cd2b37d9
RK		 5191 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5192 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5193 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5194 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5195 "fdivs %0,%1,%2"
ca7f5001
RK		 5196 [(set_attr "type" "sdiv")])
5197
5198(define_insn ""
5199 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5200 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5201 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5202 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5203 "{fd|fdiv} %0,%1,%2"
0780f386 5204 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 5205
5206(define_insn ""
cd2b37d9
RK		 5207 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5208 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5209 (match_operand:SF 2 "gpc_reg_operand" "f"))
5210 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5211 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5212 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 5213 [(set_attr "type" "fp")])
5214
5215(define_insn ""
5216 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5217 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5218 (match_operand:SF 2 "gpc_reg_operand" "f"))
5219 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5220 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5221 "{fma|fmadd} %0,%1,%2,%3"
cf27b467 5222 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5223
5224(define_insn ""
cd2b37d9
RK		 5225 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5226 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5227 (match_operand:SF 2 "gpc_reg_operand" "f"))
5228 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5229 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5230 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 5231 [(set_attr "type" "fp")])
5232
5233(define_insn ""
5234 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5235 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5236 (match_operand:SF 2 "gpc_reg_operand" "f"))
5237 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5238 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5239 "{fms|fmsub} %0,%1,%2,%3"
cf27b467 5240 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5241
5242(define_insn ""
cd2b37d9
RK		 5243 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5244 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5245 (match_operand:SF 2 "gpc_reg_operand" "f"))
5246 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5247 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5248 && HONOR_SIGNED_ZEROS (SFmode)"
5249 "fnmadds %0,%1,%2,%3"
5250 [(set_attr "type" "fp")])
5251
5252(define_insn ""
5253 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5254 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5255 (match_operand:SF 2 "gpc_reg_operand" "f"))
5256 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5257 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5258 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5259 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 5260 [(set_attr "type" "fp")])
5261
5262(define_insn ""
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5265 (match_operand:SF 2 "gpc_reg_operand" "f"))
5266 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 5267 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5268 "{fnma|fnmadd} %0,%1,%2,%3"
cf27b467 5269 [(set_attr "type" "dmul")])
1fd4e8c1 5270
16823694
GK		 5271(define_insn ""
5272 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5273 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5274 (match_operand:SF 2 "gpc_reg_operand" "f"))
5275 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5276 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5277 && ! HONOR_SIGNED_ZEROS (SFmode)"
5278 "{fnma|fnmadd} %0,%1,%2,%3"
5279 [(set_attr "type" "dmul")])
5280
1fd4e8c1 5281(define_insn ""
cd2b37d9
RK		 5282 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5283 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5284 (match_operand:SF 2 "gpc_reg_operand" "f"))
5285 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5286 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5287 && HONOR_SIGNED_ZEROS (SFmode)"
5288 "fnmsubs %0,%1,%2,%3"
5289 [(set_attr "type" "fp")])
5290
5291(define_insn ""
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5293 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5294 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5295 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5296 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5297 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5298 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 5299 [(set_attr "type" "fp")])
5300
5301(define_insn ""
5302 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5303 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5304 (match_operand:SF 2 "gpc_reg_operand" "f"))
5305 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 5306 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5307 "{fnms|fnmsub} %0,%1,%2,%3"
cf27b467 5308 [(set_attr "type" "dmul")])
1fd4e8c1 5309
16823694
GK		 5310(define_insn ""
5311 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5312 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5313 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5314 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5315 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5316 && ! HONOR_SIGNED_ZEROS (SFmode)"
5317 "{fnms|fnmsub} %0,%1,%2,%3"
9c6fdb46 5318 [(set_attr "type" "dmul")])
16823694 5319
ca7f5001
RK		 5320(define_expand "sqrtsf2"
5321 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5322 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
a3170dc6 5323 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5324 "")
5325
5326(define_insn ""
5327 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5328 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5329 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5330 "fsqrts %0,%1"
5331 [(set_attr "type" "ssqrt")])
5332
5333(define_insn ""
5334 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5335 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5336 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5337 "fsqrt %0,%1"
5338 [(set_attr "type" "dsqrt")])
5339
0530bc70
AP		 5340(define_expand "copysignsf3"
5341 [(set (match_dup 3)
5342 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5343 (set (match_dup 4)
5344 (neg:SF (abs:SF (match_dup 1))))
5345 (set (match_operand:SF 0 "gpc_reg_operand" "")
5346 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5347 (match_dup 5))
5348 (match_dup 3)
5349 (match_dup 4)))]
5350 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
bb8df8a6 5351 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
0530bc70
AP		 5352 {
5353 operands[3] = gen_reg_rtx (SFmode);
5354 operands[4] = gen_reg_rtx (SFmode);
5355 operands[5] = CONST0_RTX (SFmode);
5356 })
5357
5358(define_expand "copysigndf3"
5359 [(set (match_dup 3)
5360 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5361 (set (match_dup 4)
5362 (neg:DF (abs:DF (match_dup 1))))
5363 (set (match_operand:DF 0 "gpc_reg_operand" "")
5364 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5365 (match_dup 5))
5366 (match_dup 3)
5367 (match_dup 4)))]
5368 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5369 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5370 {
5371 operands[3] = gen_reg_rtx (DFmode);
5372 operands[4] = gen_reg_rtx (DFmode);
5373 operands[5] = CONST0_RTX (DFmode);
5374 })
5375
94d7001a
RK		 5376;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5377;; fsel instruction and some auxiliary computations. Then we just have a
5378;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05 5379;; combine.
7ae4d8d4 5380(define_expand "smaxsf3"
8e871c05 5381 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5382 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5383 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5384 (match_dup 1)
5385 (match_dup 2)))]
89e73849 5386 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5387 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 5388
7ae4d8d4 5389(define_expand "sminsf3"
50a0b056
GK		 5390 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5391 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5392 (match_operand:SF 2 "gpc_reg_operand" ""))
5393 (match_dup 2)
5394 (match_dup 1)))]
89e73849 5395 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5396 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 5397
8e871c05
RK		 5398(define_split
5399 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5400 (match_operator:SF 3 "min_max_operator"
5401 [(match_operand:SF 1 "gpc_reg_operand" "")
5402 (match_operand:SF 2 "gpc_reg_operand" "")]))]
89e73849 5403 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5404 [(const_int 0)]
5405 "
6ae08853 5406{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5407 operands[1], operands[2]);
5408 DONE;
5409}")
2f607b94 5410
a3170dc6
AH		 5411(define_expand "movsicc"
5412 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5413 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5414 (match_operand:SI 2 "gpc_reg_operand" "")
5415 (match_operand:SI 3 "gpc_reg_operand" "")))]
5416 "TARGET_ISEL"
5417 "
5418{
5419 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5420 DONE;
5421 else
5422 FAIL;
5423}")
5424
5425;; We use the BASE_REGS for the isel input operands because, if rA is
5426;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5427;; because we may switch the operands and rB may end up being rA.
5428;;
5429;; We need 2 patterns: an unsigned and a signed pattern. We could
5430;; leave out the mode in operand 4 and use one pattern, but reload can
5431;; change the mode underneath our feet and then gets confused trying
5432;; to reload the value.
5433(define_insn "isel_signed"
5434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5435 (if_then_else:SI
5436 (match_operator 1 "comparison_operator"
5437 [(match_operand:CC 4 "cc_reg_operand" "y")
5438 (const_int 0)])
5439 (match_operand:SI 2 "gpc_reg_operand" "b")
5440 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5441 "TARGET_ISEL"
5442 "*
5443{ return output_isel (operands); }"
5444 [(set_attr "length" "4")])
5445
5446(define_insn "isel_unsigned"
5447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5448 (if_then_else:SI
5449 (match_operator 1 "comparison_operator"
5450 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5451 (const_int 0)])
5452 (match_operand:SI 2 "gpc_reg_operand" "b")
5453 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5454 "TARGET_ISEL"
5455 "*
5456{ return output_isel (operands); }"
5457 [(set_attr "length" "4")])
5458
94d7001a 5459(define_expand "movsfcc"
0ad91047 5460 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 5461 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5462 (match_operand:SF 2 "gpc_reg_operand" "")
5463 (match_operand:SF 3 "gpc_reg_operand" "")))]
a3170dc6 5464 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5465 "
5466{
50a0b056
GK		 5467 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5468 DONE;
94d7001a 5469 else
50a0b056 5470 FAIL;
94d7001a 5471}")
d56d506a 5472
50a0b056 5473(define_insn "*fselsfsf4"
8e871c05
RK		 5474 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5475 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5476 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5477 (match_operand:SF 2 "gpc_reg_operand" "f")
5478 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5479 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5480 "fsel %0,%1,%2,%3"
5481 [(set_attr "type" "fp")])
2f607b94 5482
50a0b056 5483(define_insn "*fseldfsf4"
94d7001a
RK		 5484 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5485 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 5486 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5487 (match_operand:SF 2 "gpc_reg_operand" "f")
5488 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5489 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5490 "fsel %0,%1,%2,%3"
5491 [(set_attr "type" "fp")])
d56d506a 5492
7a2f7870
AH		 5493(define_expand "negdf2"
5494 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5495 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5496 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5497 "")
5498
99176a91 5499(define_insn "*negdf2_fpr"
cd2b37d9
RK		 5500 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5501 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5502 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5503 "fneg %0,%1"
5504 [(set_attr "type" "fp")])
5505
7a2f7870
AH		 5506(define_expand "absdf2"
5507 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5508 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5509 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5510 "")
5511
99176a91 5512(define_insn "*absdf2_fpr"
cd2b37d9
RK		 5513 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5514 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5515 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5516 "fabs %0,%1"
5517 [(set_attr "type" "fp")])
5518
99176a91 5519(define_insn "*nabsdf2_fpr"
cd2b37d9
RK		 5520 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5521 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
a3170dc6 5522 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5523 "fnabs %0,%1"
5524 [(set_attr "type" "fp")])
5525
7a2f7870
AH		 5526(define_expand "adddf3"
5527 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5528 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5529 (match_operand:DF 2 "gpc_reg_operand" "")))]
5530 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5531 "")
5532
99176a91 5533(define_insn "*adddf3_fpr"
cd2b37d9
RK		 5534 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5535 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5536 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5537 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5538 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 5539 [(set_attr "type" "fp")])
5540
7a2f7870
AH		 5541(define_expand "subdf3"
5542 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5543 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5544 (match_operand:DF 2 "gpc_reg_operand" "")))]
5545 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5546 "")
5547
99176a91 5548(define_insn "*subdf3_fpr"
cd2b37d9
RK		 5549 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5550 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5551 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5552 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5553 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 5554 [(set_attr "type" "fp")])
5555
7a2f7870
AH		 5556(define_expand "muldf3"
5557 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5558 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5559 (match_operand:DF 2 "gpc_reg_operand" "")))]
5560 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5561 "")
5562
99176a91 5563(define_insn "*muldf3_fpr"
cd2b37d9
RK		 5564 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5565 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5566 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5567 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5568 "{fm|fmul} %0,%1,%2"
cfb557c4 5569 [(set_attr "type" "dmul")])
1fd4e8c1 5570
ef765ea9
DE		 5571(define_insn "fred"
5572 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5573 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5574 "TARGET_POPCNTB && flag_finite_math_only"
5575 "fre %0,%1"
5576 [(set_attr "type" "fp")])
5577
7a2f7870
AH		 5578(define_expand "divdf3"
5579 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5580 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5581 (match_operand:DF 2 "gpc_reg_operand" "")))]
5582 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
ef765ea9
DE		 5583{
5584 if (swdiv && !optimize_size && TARGET_POPCNTB
5585 && flag_finite_math_only && !flag_trapping_math)
5586 {
5587 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5588 DONE;
5589 }
5590})
7a2f7870 5591
99176a91 5592(define_insn "*divdf3_fpr"
cd2b37d9
RK		 5593 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5594 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5595 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5596 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5597 "{fd|fdiv} %0,%1,%2"
cfb557c4 5598 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 5599
5600(define_insn ""
cd2b37d9
RK		 5601 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5602 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5603 (match_operand:DF 2 "gpc_reg_operand" "f"))
5604 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5605 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5606 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 5607 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5608
5609(define_insn ""
cd2b37d9
RK		 5610 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5611 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5612 (match_operand:DF 2 "gpc_reg_operand" "f"))
5613 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5614 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5615 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 5616 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5617
5618(define_insn ""
cd2b37d9
RK		 5619 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5620 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5621 (match_operand:DF 2 "gpc_reg_operand" "f"))
5622 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5623 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5624 && HONOR_SIGNED_ZEROS (DFmode)"
5625 "{fnma|fnmadd} %0,%1,%2,%3"
5626 [(set_attr "type" "dmul")])
5627
5628(define_insn ""
5629 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5630 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5631 (match_operand:DF 2 "gpc_reg_operand" "f"))
5632 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5633 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5634 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5635 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 5636 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5637
5638(define_insn ""
cd2b37d9
RK		 5639 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5640 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5641 (match_operand:DF 2 "gpc_reg_operand" "f"))
5642 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5643 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5644 && HONOR_SIGNED_ZEROS (DFmode)"
5645 "{fnms|fnmsub} %0,%1,%2,%3"
5646 [(set_attr "type" "dmul")])
5647
5648(define_insn ""
5649 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5650 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5651 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5652 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
6ae08853 5653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5654 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5655 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 5656 [(set_attr "type" "dmul")])
ca7f5001
RK		 5657
5658(define_insn "sqrtdf2"
5659 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5660 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5661 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5662 "fsqrt %0,%1"
5663 [(set_attr "type" "dsqrt")])
b77dfefc 5664
50a0b056 5665;; The conditional move instructions allow us to perform max and min
6ae08853 5666;; operations even when
b77dfefc 5667
7ae4d8d4 5668(define_expand "smaxdf3"
8e871c05 5669 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5670 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5671 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5672 (match_dup 1)
5673 (match_dup 2)))]
89e73849 5674 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5675 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 5676
7ae4d8d4 5677(define_expand "smindf3"
50a0b056
GK		 5678 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5679 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5680 (match_operand:DF 2 "gpc_reg_operand" ""))
5681 (match_dup 2)
5682 (match_dup 1)))]
89e73849 5683 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5684 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 5685
8e871c05
RK		 5686(define_split
5687 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5688 (match_operator:DF 3 "min_max_operator"
5689 [(match_operand:DF 1 "gpc_reg_operand" "")
5690 (match_operand:DF 2 "gpc_reg_operand" "")]))]
89e73849 5691 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5692 [(const_int 0)]
5693 "
6ae08853 5694{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5695 operands[1], operands[2]);
5696 DONE;
5697}")
b77dfefc 5698
94d7001a 5699(define_expand "movdfcc"
0ad91047 5700 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 5701 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5702 (match_operand:DF 2 "gpc_reg_operand" "")
5703 (match_operand:DF 3 "gpc_reg_operand" "")))]
a3170dc6 5704 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5705 "
5706{
50a0b056
GK		 5707 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5708 DONE;
94d7001a 5709 else
50a0b056 5710 FAIL;
94d7001a 5711}")
d56d506a 5712
50a0b056 5713(define_insn "*fseldfdf4"
8e871c05
RK		 5714 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5715 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 5716 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5717 (match_operand:DF 2 "gpc_reg_operand" "f")
5718 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5719 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5720 "fsel %0,%1,%2,%3"
5721 [(set_attr "type" "fp")])
d56d506a 5722
50a0b056 5723(define_insn "*fselsfdf4"
94d7001a
RK		 5724 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5725 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5726 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5727 (match_operand:DF 2 "gpc_reg_operand" "f")
5728 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5729 "TARGET_PPC_GFXOPT"
5730 "fsel %0,%1,%2,%3"
5731 [(set_attr "type" "fp")])
1fd4e8c1 5732\f
d095928f
AH		 5733;; Conversions to and from floating-point.
5734
5735(define_expand "fixuns_truncsfsi2"
5736 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5737 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5738 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5739 "")
5740
5741(define_expand "fix_truncsfsi2"
5742 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5743 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5744 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5745 "")
5746
9ebbca7d
GK		 5747; For each of these conversions, there is a define_expand, a define_insn
5748; with a '#' template, and a define_split (with C code). The idea is
5749; to allow constant folding with the template of the define_insn,
5750; then to have the insns split later (between sched1 and final).
5751
1fd4e8c1 5752(define_expand "floatsidf2"
802a0058
MM		 5753 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5754 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5755 (use (match_dup 2))
5756 (use (match_dup 3))
208c89ce 5757 (clobber (match_dup 4))
a7df97e6 5758 (clobber (match_dup 5))
9ebbca7d 5759 (clobber (match_dup 6))])]
17caeff2 5760 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5761 "
5762{
99176a91
AH		 5763 if (TARGET_E500_DOUBLE)
5764 {
5765 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5766 DONE;
5767 }
44cd321e
PS		 5768 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5769 {
5770 rtx t1 = gen_reg_rtx (DImode);
5771 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5772 DONE;
5773 }
05d49501
AM		 5774 if (TARGET_POWERPC64)
5775 {
5776 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5777 rtx t1 = gen_reg_rtx (DImode);
5778 rtx t2 = gen_reg_rtx (DImode);
5779 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5780 DONE;
5781 }
5782
802a0058 5783 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5784 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5785 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5786 operands[5] = gen_reg_rtx (DFmode);
5787 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5788}")
5789
230215f5 5790(define_insn_and_split "*floatsidf2_internal"
802a0058
MM		 5791 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5792 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5793 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5794 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5795 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5
DJ		 5796 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5797 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
a3170dc6 5798 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5799 "#"
230215f5
GK		 5800 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5801 [(pc)]
208c89ce
MM		 5802 "
5803{
9ebbca7d 5804 rtx lowword, highword;
230215f5
GK		 5805 gcc_assert (MEM_P (operands[4]));
5806 highword = adjust_address (operands[4], SImode, 0);
5807 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d
GK		 5808 if (! WORDS_BIG_ENDIAN)
5809 {
5810 rtx tmp;
5811 tmp = highword; highword = lowword; lowword = tmp;
5812 }
5813
6ae08853 5814 emit_insn (gen_xorsi3 (operands[6], operands[1],
9ebbca7d 5815 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
230215f5
GK		 5816 emit_move_insn (lowword, operands[6]);
5817 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5818 emit_move_insn (operands[5], operands[4]);
5819 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5820 DONE;
230215f5
GK		 5821}"
5822 [(set_attr "length" "24")])
802a0058 5823
a3170dc6
AH		 5824(define_expand "floatunssisf2"
5825 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5826 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5827 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5828 "")
5829
802a0058
MM		 5830(define_expand "floatunssidf2"
5831 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5832 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5833 (use (match_dup 2))
5834 (use (match_dup 3))
a7df97e6 5835 (clobber (match_dup 4))
9ebbca7d 5836 (clobber (match_dup 5))])]
99176a91 5837 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5838 "
5839{
99176a91
AH		 5840 if (TARGET_E500_DOUBLE)
5841 {
5842 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5843 DONE;
5844 }
05d49501
AM		 5845 if (TARGET_POWERPC64)
5846 {
5847 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5848 rtx t1 = gen_reg_rtx (DImode);
5849 rtx t2 = gen_reg_rtx (DImode);
5850 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5851 t1, t2));
5852 DONE;
5853 }
5854
802a0058 5855 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5856 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 5857 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5858 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 5859}")
5860
230215f5 5861(define_insn_and_split "*floatunssidf2_internal"
802a0058
MM		 5862 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5863 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5864 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5865 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5866 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5 5867 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
a3170dc6 5868 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5869 "#"
230215f5
GK		 5870 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5871 [(pc)]
9ebbca7d 5872 "
802a0058 5873{
9ebbca7d 5874 rtx lowword, highword;
230215f5
GK		 5875 gcc_assert (MEM_P (operands[4]));
5876 highword = adjust_address (operands[4], SImode, 0);
5877 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d 5878 if (! WORDS_BIG_ENDIAN)
f6968f59 5879 {
9ebbca7d
GK		 5880 rtx tmp;
5881 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 5882 }
802a0058 5883
230215f5
GK		 5884 emit_move_insn (lowword, operands[1]);
5885 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5886 emit_move_insn (operands[5], operands[4]);
5887 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5888 DONE;
230215f5
GK		 5889}"
5890 [(set_attr "length" "20")])
1fd4e8c1 5891
1fd4e8c1 5892(define_expand "fix_truncdfsi2"
045a8eb3 5893 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
802a0058
MM		 5894 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5895 (clobber (match_dup 2))
9ebbca7d 5896 (clobber (match_dup 3))])]
99176a91
AH		 5897 "(TARGET_POWER2 || TARGET_POWERPC)
5898 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5899 "
5900{
99176a91
AH		 5901 if (TARGET_E500_DOUBLE)
5902 {
5903 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5904 DONE;
5905 }
802a0058 5906 operands[2] = gen_reg_rtx (DImode);
44cd321e
PS		 5907 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5908 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5909 {
5910 operands[3] = gen_reg_rtx (DImode);
5911 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5912 operands[2], operands[3]));
5913 DONE;
5914 }
da4c340c
GK		 5915 if (TARGET_PPC_GFXOPT)
5916 {
5917 rtx orig_dest = operands[0];
045a8eb3 5918 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
da4c340c
GK		 5919 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5920 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5921 operands[2]));
5922 if (operands[0] != orig_dest)
5923 emit_move_insn (orig_dest, operands[0]);
5924 DONE;
5925 }
9ebbca7d 5926 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 5927}")
5928
da4c340c 5929(define_insn_and_split "*fix_truncdfsi2_internal"
802a0058
MM		 5930 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5931 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 5932 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
9ebbca7d 5933 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
a3170dc6 5934 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5935 "#"
230215f5 5936 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
da4c340c 5937 [(pc)]
9ebbca7d 5938 "
802a0058 5939{
9ebbca7d 5940 rtx lowword;
230215f5
GK		 5941 gcc_assert (MEM_P (operands[3]));
5942 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
802a0058 5943
9ebbca7d
GK		 5944 emit_insn (gen_fctiwz (operands[2], operands[1]));
5945 emit_move_insn (operands[3], operands[2]);
230215f5 5946 emit_move_insn (operands[0], lowword);
9ebbca7d 5947 DONE;
da4c340c
GK		 5948}"
5949 [(set_attr "length" "16")])
5950
5951(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5952 [(set (match_operand:SI 0 "memory_operand" "=Z")
5953 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5954 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5955 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5956 && TARGET_PPC_GFXOPT"
5957 "#"
5958 "&& 1"
5959 [(pc)]
5960 "
5961{
5962 emit_insn (gen_fctiwz (operands[2], operands[1]));
5963 emit_insn (gen_stfiwx (operands[0], operands[2]));
5964 DONE;
5965}"
5966 [(set_attr "length" "16")])
802a0058 5967
44cd321e
PS		 5968(define_insn_and_split "fix_truncdfsi2_mfpgpr"
5969 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5970 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5971 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5972 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
5973 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
5974 "#"
5975 "&& 1"
5976 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
5977 (set (match_dup 3) (match_dup 2))
5978 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
5979 ""
5980 [(set_attr "length" "12")])
5981
615158e2 5982; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 5983; rather than (set (subreg:SI (reg)) (fix:SI ...))
5984; because the first makes it clear that operand 0 is not live
5985; before the instruction.
5986(define_insn "fctiwz"
da4c340c 5987 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
615158e2
JJ		 5988 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5989 UNSPEC_FCTIWZ))]
a3170dc6 5990 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
a260abc9
DE		 5991 "{fcirz|fctiwz} %0,%1"
5992 [(set_attr "type" "fp")])
5993
9719f3b7
DE		 5994(define_insn "btruncdf2"
5995 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5996 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5997 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5998 "friz %0,%1"
5999 [(set_attr "type" "fp")])
6000
6001(define_insn "btruncsf2"
6002 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6003 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6004 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6005 "friz %0,%1"
9719f3b7
DE		 6006 [(set_attr "type" "fp")])
6007
6008(define_insn "ceildf2"
6009 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6010 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6011 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6012 "frip %0,%1"
6013 [(set_attr "type" "fp")])
6014
6015(define_insn "ceilsf2"
833126ad 6016 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9719f3b7
DE		 6017 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6018 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6019 "frip %0,%1"
9719f3b7
DE		 6020 [(set_attr "type" "fp")])
6021
6022(define_insn "floordf2"
6023 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6024 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6025 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6026 "frim %0,%1"
6027 [(set_attr "type" "fp")])
6028
6029(define_insn "floorsf2"
6030 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6031 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6032 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6033 "frim %0,%1"
9719f3b7
DE		 6034 [(set_attr "type" "fp")])
6035
6036(define_insn "rounddf2"
6037 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6038 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6039 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6040 "frin %0,%1"
6041 [(set_attr "type" "fp")])
6042
6043(define_insn "roundsf2"
6044 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6045 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6046 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6047 "frin %0,%1"
9719f3b7
DE		 6048 [(set_attr "type" "fp")])
6049
da4c340c
GK		 6050; An UNSPEC is used so we don't have to support SImode in FP registers.
6051(define_insn "stfiwx"
6052 [(set (match_operand:SI 0 "memory_operand" "=Z")
6053 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6054 UNSPEC_STFIWX))]
6055 "TARGET_PPC_GFXOPT"
6056 "stfiwx %1,%y0"
6057 [(set_attr "type" "fpstore")])
6058
a3170dc6
AH		 6059(define_expand "floatsisf2"
6060 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6061 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6062 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6063 "")
6064
a473029f
RK		 6065(define_insn "floatdidf2"
6066 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
61c07d3c 6067 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
a3170dc6 6068 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6069 "fcfid %0,%1"
6070 [(set_attr "type" "fp")])
6071
44cd321e
PS		 6072(define_insn_and_split "floatsidf_ppc64_mfpgpr"
6073 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6074 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6075 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6076 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6077 "#"
6078 "&& 1"
6079 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6080 (set (match_dup 0) (float:DF (match_dup 2)))]
6081 "")
6082
05d49501
AM		 6083(define_insn_and_split "floatsidf_ppc64"
6084 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6085 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6086 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6087 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6088 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
44cd321e 6089 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 6090 "#"
ecb62ae7 6091 "&& 1"
05d49501
AM		 6092 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6093 (set (match_dup 2) (match_dup 3))
6094 (set (match_dup 4) (match_dup 2))
6095 (set (match_dup 0) (float:DF (match_dup 4)))]
6096 "")
6097
6098(define_insn_and_split "floatunssidf_ppc64"
6099 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6100 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6101 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6102 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6103 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 6104 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 6105 "#"
ecb62ae7 6106 "&& 1"
05d49501
AM		 6107 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6108 (set (match_dup 2) (match_dup 3))
6109 (set (match_dup 4) (match_dup 2))
6110 (set (match_dup 0) (float:DF (match_dup 4)))]
6111 "")
6112
a473029f 6113(define_insn "fix_truncdfdi2"
61c07d3c 6114 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
a473029f 6115 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 6116 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6117 "fctidz %0,%1"
6118 [(set_attr "type" "fp")])
ea112fc4 6119
678b7733
AM		 6120(define_expand "floatdisf2"
6121 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6122 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
994cf173 6123 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6124 "
6125{
994cf173 6126 rtx val = operands[1];
678b7733
AM		 6127 if (!flag_unsafe_math_optimizations)
6128 {
6129 rtx label = gen_label_rtx ();
994cf173
AM		 6130 val = gen_reg_rtx (DImode);
6131 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
678b7733
AM		 6132 emit_label (label);
6133 }
994cf173 6134 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
678b7733
AM		 6135 DONE;
6136}")
6137
6138;; This is not IEEE compliant if rounding mode is "round to nearest".
6139;; If the DI->DF conversion is inexact, then it's possible to suffer
6140;; from double rounding.
6141(define_insn_and_split "floatdisf2_internal1"
ea112fc4 6142 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
61c07d3c 6143 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
ea112fc4 6144 (clobber (match_scratch:DF 2 "=f"))]
678b7733 6145 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
ea112fc4
DE		 6146 "#"
6147 "&& reload_completed"
6148 [(set (match_dup 2)
6149 (float:DF (match_dup 1)))
6150 (set (match_dup 0)
6151 (float_truncate:SF (match_dup 2)))]
6152 "")
678b7733
AM		 6153
6154;; Twiddles bits to avoid double rounding.
b6d08ca1 6155;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 6156;; by a bit that won't be lost at that stage, but is below the SFmode
6157;; rounding position.
6158(define_expand "floatdisf2_internal2"
994cf173
AM		 6159 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6160 (const_int 53)))
6161 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6162 (const_int 2047)))
6163 (clobber (scratch:CC))])
6164 (set (match_dup 3) (plus:DI (match_dup 3)
6165 (const_int 1)))
6166 (set (match_dup 0) (plus:DI (match_dup 0)
6167 (const_int 2047)))
6168 (set (match_dup 4) (compare:CCUNS (match_dup 3)
c22e62a6 6169 (const_int 2)))
994cf173
AM		 6170 (set (match_dup 0) (ior:DI (match_dup 0)
6171 (match_dup 1)))
6172 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6173 (const_int -2048)))
6174 (clobber (scratch:CC))])
6175 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6176 (label_ref (match_operand:DI 2 "" ""))
678b7733 6177 (pc)))
994cf173
AM		 6178 (set (match_dup 0) (match_dup 1))]
6179 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6180 "
6181{
678b7733 6182 operands[3] = gen_reg_rtx (DImode);
994cf173 6183 operands[4] = gen_reg_rtx (CCUNSmode);
678b7733 6184}")
1fd4e8c1
RK		 6185\f
6186;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 6187;; of instructions. The & constraints are to prevent the register
6188;; allocator from allocating registers that overlap with the inputs
6189;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 6190;; also allow for the output being the same as one of the inputs.
a6ec530c 6191
266eb58a 6192(define_insn "*adddi3_noppc64"
a6ec530c
RK		 6193 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6194 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6195 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 6196 "! TARGET_POWERPC64"
0f645302
MM		 6197 "*
6198{
6199 if (WORDS_BIG_ENDIAN)
6200 return (GET_CODE (operands[2])) != CONST_INT
6201 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6202 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6203 else
6204 return (GET_CODE (operands[2])) != CONST_INT
6205 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6206 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6207}"
943c15ed
DE		 6208 [(set_attr "type" "two")
6209 (set_attr "length" "8")])
1fd4e8c1 6210
266eb58a 6211(define_insn "*subdi3_noppc64"
e7e5df70
RK		 6212 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6213 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6214 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 6215 "! TARGET_POWERPC64"
5502823b
RK		 6216 "*
6217{
0f645302
MM		 6218 if (WORDS_BIG_ENDIAN)
6219 return (GET_CODE (operands[1]) != CONST_INT)
6220 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6221 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6222 else
6223 return (GET_CODE (operands[1]) != CONST_INT)
6224 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6225 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 6226}"
943c15ed
DE		 6227 [(set_attr "type" "two")
6228 (set_attr "length" "8")])
ca7f5001 6229
266eb58a 6230(define_insn "*negdi2_noppc64"
a6ec530c
RK		 6231 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6232 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 6233 "! TARGET_POWERPC64"
5502823b
RK		 6234 "*
6235{
6236 return (WORDS_BIG_ENDIAN)
6237 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6238 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6239}"
943c15ed
DE		 6240 [(set_attr "type" "two")
6241 (set_attr "length" "8")])
ca7f5001 6242
8ffd9c51
RK		 6243(define_expand "mulsidi3"
6244 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6245 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6246 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 6247 "! TARGET_POWERPC64"
8ffd9c51
RK		 6248 "
6249{
6250 if (! TARGET_POWER && ! TARGET_POWERPC)
6251 {
39403d82
DE		 6252 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6253 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6254 emit_insn (gen_mull_call ());
cf27b467 6255 if (WORDS_BIG_ENDIAN)
39403d82 6256 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 6257 else
6258 {
6259 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 6260 gen_rtx_REG (SImode, 3));
cf27b467 6261 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 6262 gen_rtx_REG (SImode, 4));
cf27b467 6263 }
8ffd9c51
RK		 6264 DONE;
6265 }
6266 else if (TARGET_POWER)
6267 {
6268 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6269 DONE;
6270 }
6271}")
deb9225a 6272
8ffd9c51 6273(define_insn "mulsidi3_mq"
cd2b37d9 6274 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 6275 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 6276 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 6277 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 6278 "TARGET_POWER"
b19003d8 6279 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 6280 [(set_attr "type" "imul")
6281 (set_attr "length" "8")])
deb9225a 6282
f192bf8b 6283(define_insn "*mulsidi3_no_mq"
425c176f 6284 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 6285 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6286 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6287 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 6288 "*
6289{
6290 return (WORDS_BIG_ENDIAN)
6291 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6292 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6293}"
8ffd9c51
RK		 6294 [(set_attr "type" "imul")
6295 (set_attr "length" "8")])
deb9225a 6296
ebedb4dd
MM		 6297(define_split
6298 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6299 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6300 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6301 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6302 [(set (match_dup 3)
6303 (truncate:SI
6304 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6305 (sign_extend:DI (match_dup 2)))
6306 (const_int 32))))
6307 (set (match_dup 4)
6308 (mult:SI (match_dup 1)
6309 (match_dup 2)))]
6310 "
6311{
6312 int endian = (WORDS_BIG_ENDIAN == 0);
6313 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6314 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6315}")
6316
f192bf8b
DE		 6317(define_expand "umulsidi3"
6318 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6319 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6320 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6321 "TARGET_POWERPC && ! TARGET_POWERPC64"
6322 "
6323{
6324 if (TARGET_POWER)
6325 {
6326 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6327 DONE;
6328 }
6329}")
6330
6331(define_insn "umulsidi3_mq"
6332 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6333 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6334 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6335 (clobber (match_scratch:SI 3 "=q"))]
6336 "TARGET_POWERPC && TARGET_POWER"
6337 "*
6338{
6339 return (WORDS_BIG_ENDIAN)
6340 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6341 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6342}"
6343 [(set_attr "type" "imul")
6344 (set_attr "length" "8")])
6345
6346(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 6347 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6348 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6349 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6350 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 6351 "*
6352{
6353 return (WORDS_BIG_ENDIAN)
6354 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6355 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6356}"
6357 [(set_attr "type" "imul")
6358 (set_attr "length" "8")])
6359
ebedb4dd
MM		 6360(define_split
6361 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6362 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6363 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6364 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6365 [(set (match_dup 3)
6366 (truncate:SI
6367 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6368 (zero_extend:DI (match_dup 2)))
6369 (const_int 32))))
6370 (set (match_dup 4)
6371 (mult:SI (match_dup 1)
6372 (match_dup 2)))]
6373 "
6374{
6375 int endian = (WORDS_BIG_ENDIAN == 0);
6376 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6377 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6378}")
6379
8ffd9c51
RK		 6380(define_expand "smulsi3_highpart"
6381 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6382 (truncate:SI
6383 (lshiftrt:DI (mult:DI (sign_extend:DI
e42ac3de 6384 (match_operand:SI 1 "gpc_reg_operand" ""))
8ffd9c51 6385 (sign_extend:DI
e42ac3de 6386 (match_operand:SI 2 "gpc_reg_operand" "")))
8ffd9c51
RK		 6387 (const_int 32))))]
6388 ""
6389 "
6390{
6391 if (! TARGET_POWER && ! TARGET_POWERPC)
6392 {
39403d82
DE		 6393 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6394 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6395 emit_insn (gen_mulh_call ());
39403d82 6396 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 6397 DONE;
6398 }
6399 else if (TARGET_POWER)
6400 {
6401 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6402 DONE;
6403 }
6404}")
deb9225a 6405
8ffd9c51
RK		 6406(define_insn "smulsi3_highpart_mq"
6407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6408 (truncate:SI
fada905b
MM		 6409 (lshiftrt:DI (mult:DI (sign_extend:DI
6410 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6411 (sign_extend:DI
6412 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 6413 (const_int 32))))
6414 (clobber (match_scratch:SI 3 "=q"))]
6415 "TARGET_POWER"
6416 "mul %0,%1,%2"
6417 [(set_attr "type" "imul")])
deb9225a 6418
f192bf8b 6419(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 6420 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6421 (truncate:SI
fada905b
MM		 6422 (lshiftrt:DI (mult:DI (sign_extend:DI
6423 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6424 (sign_extend:DI
6425 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 6426 (const_int 32))))]
f192bf8b 6427 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 6428 "mulhw %0,%1,%2"
6429 [(set_attr "type" "imul")])
deb9225a 6430
f192bf8b
DE		 6431(define_expand "umulsi3_highpart"
6432 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6433 (truncate:SI
6434 (lshiftrt:DI (mult:DI (zero_extend:DI
6435 (match_operand:SI 1 "gpc_reg_operand" ""))
6436 (zero_extend:DI
6437 (match_operand:SI 2 "gpc_reg_operand" "")))
6438 (const_int 32))))]
6439 "TARGET_POWERPC"
6440 "
6441{
6442 if (TARGET_POWER)
6443 {
6444 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6445 DONE;
6446 }
6447}")
6448
6449(define_insn "umulsi3_highpart_mq"
6450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6451 (truncate:SI
6452 (lshiftrt:DI (mult:DI (zero_extend:DI
6453 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6454 (zero_extend:DI
6455 (match_operand:SI 2 "gpc_reg_operand" "r")))
6456 (const_int 32))))
6457 (clobber (match_scratch:SI 3 "=q"))]
6458 "TARGET_POWERPC && TARGET_POWER"
6459 "mulhwu %0,%1,%2"
6460 [(set_attr "type" "imul")])
6461
6462(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 6463 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6464 (truncate:SI
6465 (lshiftrt:DI (mult:DI (zero_extend:DI
6466 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6467 (zero_extend:DI
6468 (match_operand:SI 2 "gpc_reg_operand" "r")))
6469 (const_int 32))))]
f192bf8b 6470 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 6471 "mulhwu %0,%1,%2"
6472 [(set_attr "type" "imul")])
6473
6474;; If operands 0 and 2 are in the same register, we have a problem. But
6475;; operands 0 and 1 (the usual case) can be in the same register. That's
6476;; why we have the strange constraints below.
6477(define_insn "ashldi3_power"
6478 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6479 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6480 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6481 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6482 "TARGET_POWER"
6483 "@
6484 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6485 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6486 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6487 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6488 [(set_attr "length" "8")])
6489
6490(define_insn "lshrdi3_power"
47ad8c61 6491 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 6492 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6493 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6494 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6495 "TARGET_POWER"
6496 "@
47ad8c61 6497 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 6498 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6499 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6500 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6501 [(set_attr "length" "8")])
6502
6503;; Shift by a variable amount is too complex to be worth open-coding. We
6504;; just handle shifts by constants.
6505(define_insn "ashrdi3_power"
7093ddee 6506 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 6507 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6508 (match_operand:SI 2 "const_int_operand" "M,i")))
6509 (clobber (match_scratch:SI 3 "=X,q"))]
6510 "TARGET_POWER"
6511 "@
6512 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6513 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
44cd321e
PS		 6514 [(set_attr "type" "shift")
6515 (set_attr "length" "8")])
4aa74a4f
FS		 6516
6517(define_insn "ashrdi3_no_power"
6518 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6519 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6520 (match_operand:SI 2 "const_int_operand" "M,i")))]
97727e85 6521 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
4aa74a4f
FS		 6522 "@
6523 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6524 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
943c15ed
DE		 6525 [(set_attr "type" "two,three")
6526 (set_attr "length" "8,12")])
683bdff7
FJ		 6527
6528(define_insn "*ashrdisi3_noppc64"
6529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 6530 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
683bdff7
FJ		 6531 (const_int 32)) 4))]
6532 "TARGET_32BIT && !TARGET_POWERPC64"
6533 "*
6534{
6535 if (REGNO (operands[0]) == REGNO (operands[1]))
6536 return \"\";
6537 else
6538 return \"mr %0,%1\";
6539}"
6ae08853 6540 [(set_attr "length" "4")])
683bdff7 6541
266eb58a
DE		 6542\f
6543;; PowerPC64 DImode operations.
6544
ea112fc4 6545(define_insn_and_split "absdi2"
266eb58a 6546 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6547 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 6548 (clobber (match_scratch:DI 2 "=&r,&r"))]
6549 "TARGET_POWERPC64"
ea112fc4
DE		 6550 "#"
6551 "&& reload_completed"
a260abc9 6552 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6553 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 6554 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 6555 "")
6556
ea112fc4 6557(define_insn_and_split "*nabsdi2"
266eb58a 6558 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6559 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 6560 (clobber (match_scratch:DI 2 "=&r,&r"))]
6561 "TARGET_POWERPC64"
ea112fc4
DE		 6562 "#"
6563 "&& reload_completed"
a260abc9 6564 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6565 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 6566 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 6567 "")
6568
266eb58a 6569(define_insn "muldi3"
c9692532
DE		 6570 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6571 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6572 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
266eb58a 6573 "TARGET_POWERPC64"
c9692532
DE		 6574 "@
6575 mulld %0,%1,%2
6576 mulli %0,%1,%2"
6577 [(set (attr "type")
6578 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6579 (const_string "imul3")
6580 (match_operand:SI 2 "short_cint_operand" "")
6581 (const_string "imul2")]
6582 (const_string "lmul")))])
266eb58a 6583
9259f3b0
DE		 6584(define_insn "*muldi3_internal1"
6585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6586 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6587 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6588 (const_int 0)))
6589 (clobber (match_scratch:DI 3 "=r,r"))]
6590 "TARGET_POWERPC64"
6591 "@
6592 mulld. %3,%1,%2
6593 #"
6594 [(set_attr "type" "lmul_compare")
6595 (set_attr "length" "4,8")])
6596
6597(define_split
6598 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6599 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6600 (match_operand:DI 2 "gpc_reg_operand" ""))
6601 (const_int 0)))
6602 (clobber (match_scratch:DI 3 ""))]
6603 "TARGET_POWERPC64 && reload_completed"
6604 [(set (match_dup 3)
6605 (mult:DI (match_dup 1) (match_dup 2)))
6606 (set (match_dup 0)
6607 (compare:CC (match_dup 3)
6608 (const_int 0)))]
6609 "")
6610
6611(define_insn "*muldi3_internal2"
6612 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6613 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6614 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6615 (const_int 0)))
6616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6617 (mult:DI (match_dup 1) (match_dup 2)))]
6618 "TARGET_POWERPC64"
6619 "@
6620 mulld. %0,%1,%2
6621 #"
6622 [(set_attr "type" "lmul_compare")
6623 (set_attr "length" "4,8")])
6624
6625(define_split
6626 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6627 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6628 (match_operand:DI 2 "gpc_reg_operand" ""))
6629 (const_int 0)))
6630 (set (match_operand:DI 0 "gpc_reg_operand" "")
6631 (mult:DI (match_dup 1) (match_dup 2)))]
6632 "TARGET_POWERPC64 && reload_completed"
6633 [(set (match_dup 0)
6634 (mult:DI (match_dup 1) (match_dup 2)))
6635 (set (match_dup 3)
6636 (compare:CC (match_dup 0)
6637 (const_int 0)))]
6638 "")
6639
266eb58a
DE		 6640(define_insn "smuldi3_highpart"
6641 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6642 (truncate:DI
6643 (lshiftrt:TI (mult:TI (sign_extend:TI
6644 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6645 (sign_extend:TI
6646 (match_operand:DI 2 "gpc_reg_operand" "r")))
6647 (const_int 64))))]
6648 "TARGET_POWERPC64"
6649 "mulhd %0,%1,%2"
3cb999d8 6650 [(set_attr "type" "lmul")])
266eb58a
DE		 6651
6652(define_insn "umuldi3_highpart"
6653 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6654 (truncate:DI
6655 (lshiftrt:TI (mult:TI (zero_extend:TI
6656 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6657 (zero_extend:TI
6658 (match_operand:DI 2 "gpc_reg_operand" "r")))
6659 (const_int 64))))]
6660 "TARGET_POWERPC64"
6661 "mulhdu %0,%1,%2"
3cb999d8 6662 [(set_attr "type" "lmul")])
266eb58a 6663
266eb58a 6664(define_insn "rotldi3"
44cd321e
PS		 6665 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6666 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6667 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 6668 "TARGET_POWERPC64"
44cd321e
PS		 6669 "@
6670 rldcl %0,%1,%2,0
6671 rldicl %0,%1,%H2,0"
6672 [(set_attr "type" "var_shift_rotate,integer")])
266eb58a 6673
a260abc9 6674(define_insn "*rotldi3_internal2"
44cd321e
PS		 6675 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6676 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6677 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6678 (const_int 0)))
44cd321e 6679 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6680 "TARGET_64BIT"
9ebbca7d 6681 "@
44cd321e
PS		 6682 rldcl. %3,%1,%2,0
6683 rldicl. %3,%1,%H2,0
6684 #
9ebbca7d 6685 #"
44cd321e
PS		 6686 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6687 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6688
6689(define_split
6690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6691 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6692 (match_operand:DI 2 "reg_or_cint_operand" ""))
6693 (const_int 0)))
6694 (clobber (match_scratch:DI 3 ""))]
6695 "TARGET_POWERPC64 && reload_completed"
6696 [(set (match_dup 3)
6697 (rotate:DI (match_dup 1) (match_dup 2)))
6698 (set (match_dup 0)
6699 (compare:CC (match_dup 3)
6700 (const_int 0)))]
6701 "")
266eb58a 6702
a260abc9 6703(define_insn "*rotldi3_internal3"
44cd321e
PS		 6704 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6705 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6706 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6707 (const_int 0)))
44cd321e 6708 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 6709 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 6710 "TARGET_64BIT"
9ebbca7d 6711 "@
44cd321e
PS		 6712 rldcl. %0,%1,%2,0
6713 rldicl. %0,%1,%H2,0
6714 #
9ebbca7d 6715 #"
44cd321e
PS		 6716 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6717 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6718
6719(define_split
6720 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6721 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6722 (match_operand:DI 2 "reg_or_cint_operand" ""))
6723 (const_int 0)))
6724 (set (match_operand:DI 0 "gpc_reg_operand" "")
6725 (rotate:DI (match_dup 1) (match_dup 2)))]
6726 "TARGET_POWERPC64 && reload_completed"
6727 [(set (match_dup 0)
6728 (rotate:DI (match_dup 1) (match_dup 2)))
6729 (set (match_dup 3)
6730 (compare:CC (match_dup 0)
6731 (const_int 0)))]
6732 "")
266eb58a 6733
a260abc9 6734(define_insn "*rotldi3_internal4"
44cd321e
PS		 6735 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6736 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6737 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6738 (match_operand:DI 3 "mask64_operand" "n,n")))]
a260abc9 6739 "TARGET_POWERPC64"
44cd321e
PS		 6740 "@
6741 rldc%B3 %0,%1,%2,%S3
6742 rldic%B3 %0,%1,%H2,%S3"
6743 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6744
6745(define_insn "*rotldi3_internal5"
44cd321e 6746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6747 (compare:CC (and:DI
44cd321e
PS		 6748 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6749 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6750 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6751 (const_int 0)))
44cd321e 6752 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
683bdff7 6753 "TARGET_64BIT"
9ebbca7d 6754 "@
44cd321e
PS		 6755 rldc%B3. %4,%1,%2,%S3
6756 rldic%B3. %4,%1,%H2,%S3
6757 #
9ebbca7d 6758 #"
44cd321e
PS		 6759 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6760 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6761
6762(define_split
6763 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6764 (compare:CC (and:DI
6765 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6766 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6767 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6768 (const_int 0)))
6769 (clobber (match_scratch:DI 4 ""))]
6770 "TARGET_POWERPC64 && reload_completed"
6771 [(set (match_dup 4)
6772 (and:DI (rotate:DI (match_dup 1)
6773 (match_dup 2))
6774 (match_dup 3)))
6775 (set (match_dup 0)
6776 (compare:CC (match_dup 4)
6777 (const_int 0)))]
6778 "")
a260abc9
DE		 6779
6780(define_insn "*rotldi3_internal6"
44cd321e 6781 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6782 (compare:CC (and:DI
44cd321e
PS		 6783 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6784 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6785 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6786 (const_int 0)))
44cd321e 6787 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6788 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6789 "TARGET_64BIT"
9ebbca7d 6790 "@
44cd321e
PS		 6791 rldc%B3. %0,%1,%2,%S3
6792 rldic%B3. %0,%1,%H2,%S3
6793 #
9ebbca7d 6794 #"
44cd321e
PS		 6795 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6796 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6797
6798(define_split
6799 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6800 (compare:CC (and:DI
6801 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6802 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6803 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6804 (const_int 0)))
6805 (set (match_operand:DI 0 "gpc_reg_operand" "")
6806 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6807 "TARGET_POWERPC64 && reload_completed"
6808 [(set (match_dup 0)
6809 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6810 (set (match_dup 4)
6811 (compare:CC (match_dup 0)
6812 (const_int 0)))]
6813 "")
a260abc9
DE		 6814
6815(define_insn "*rotldi3_internal7"
44cd321e 6816 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6817 (zero_extend:DI
6818 (subreg:QI
44cd321e
PS		 6819 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6820 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6821 "TARGET_POWERPC64"
44cd321e
PS		 6822 "@
6823 rldcl %0,%1,%2,56
6824 rldicl %0,%1,%H2,56"
6825 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6826
6827(define_insn "*rotldi3_internal8"
44cd321e 6828 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6829 (compare:CC (zero_extend:DI
6830 (subreg:QI
44cd321e
PS		 6831 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6832 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6833 (const_int 0)))
44cd321e 6834 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6835 "TARGET_64BIT"
9ebbca7d 6836 "@
44cd321e
PS		 6837 rldcl. %3,%1,%2,56
6838 rldicl. %3,%1,%H2,56
6839 #
9ebbca7d 6840 #"
44cd321e
PS		 6841 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6842 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6843
6844(define_split
6845 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6846 (compare:CC (zero_extend:DI
6847 (subreg:QI
6848 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6849 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6850 (const_int 0)))
6851 (clobber (match_scratch:DI 3 ""))]
6852 "TARGET_POWERPC64 && reload_completed"
6853 [(set (match_dup 3)
6854 (zero_extend:DI (subreg:QI
6855 (rotate:DI (match_dup 1)
6856 (match_dup 2)) 0)))
6857 (set (match_dup 0)
6858 (compare:CC (match_dup 3)
6859 (const_int 0)))]
6860 "")
a260abc9
DE		 6861
6862(define_insn "*rotldi3_internal9"
44cd321e 6863 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6864 (compare:CC (zero_extend:DI
6865 (subreg:QI
44cd321e
PS		 6866 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6867 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6868 (const_int 0)))
44cd321e 6869 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6870 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6871 "TARGET_64BIT"
9ebbca7d 6872 "@
44cd321e
PS		 6873 rldcl. %0,%1,%2,56
6874 rldicl. %0,%1,%H2,56
6875 #
9ebbca7d 6876 #"
44cd321e
PS		 6877 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6878 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6879
6880(define_split
6881 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6882 (compare:CC (zero_extend:DI
6883 (subreg:QI
6884 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6885 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6886 (const_int 0)))
6887 (set (match_operand:DI 0 "gpc_reg_operand" "")
6888 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6889 "TARGET_POWERPC64 && reload_completed"
6890 [(set (match_dup 0)
6891 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6892 (set (match_dup 3)
6893 (compare:CC (match_dup 0)
6894 (const_int 0)))]
6895 "")
a260abc9
DE		 6896
6897(define_insn "*rotldi3_internal10"
44cd321e 6898 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6899 (zero_extend:DI
6900 (subreg:HI
44cd321e
PS		 6901 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6902 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6903 "TARGET_POWERPC64"
44cd321e
PS		 6904 "@
6905 rldcl %0,%1,%2,48
6906 rldicl %0,%1,%H2,48"
6907 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6908
6909(define_insn "*rotldi3_internal11"
44cd321e 6910 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6911 (compare:CC (zero_extend:DI
6912 (subreg:HI
44cd321e
PS		 6913 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6914 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6915 (const_int 0)))
44cd321e 6916 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6917 "TARGET_64BIT"
9ebbca7d 6918 "@
44cd321e
PS		 6919 rldcl. %3,%1,%2,48
6920 rldicl. %3,%1,%H2,48
6921 #
9ebbca7d 6922 #"
44cd321e
PS		 6923 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6924 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6925
6926(define_split
6927 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6928 (compare:CC (zero_extend:DI
6929 (subreg:HI
6930 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6931 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6932 (const_int 0)))
6933 (clobber (match_scratch:DI 3 ""))]
6934 "TARGET_POWERPC64 && reload_completed"
6935 [(set (match_dup 3)
6936 (zero_extend:DI (subreg:HI
6937 (rotate:DI (match_dup 1)
6938 (match_dup 2)) 0)))
6939 (set (match_dup 0)
6940 (compare:CC (match_dup 3)
6941 (const_int 0)))]
6942 "")
a260abc9
DE		 6943
6944(define_insn "*rotldi3_internal12"
44cd321e 6945 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6946 (compare:CC (zero_extend:DI
6947 (subreg:HI
44cd321e
PS		 6948 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6949 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6950 (const_int 0)))
44cd321e 6951 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6952 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6953 "TARGET_64BIT"
9ebbca7d 6954 "@
44cd321e
PS		 6955 rldcl. %0,%1,%2,48
6956 rldicl. %0,%1,%H2,48
6957 #
9ebbca7d 6958 #"
44cd321e
PS		 6959 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6960 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6961
6962(define_split
6963 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6964 (compare:CC (zero_extend:DI
6965 (subreg:HI
6966 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6967 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6968 (const_int 0)))
6969 (set (match_operand:DI 0 "gpc_reg_operand" "")
6970 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6971 "TARGET_POWERPC64 && reload_completed"
6972 [(set (match_dup 0)
6973 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6974 (set (match_dup 3)
6975 (compare:CC (match_dup 0)
6976 (const_int 0)))]
6977 "")
a260abc9
DE		 6978
6979(define_insn "*rotldi3_internal13"
44cd321e 6980 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6981 (zero_extend:DI
6982 (subreg:SI
44cd321e
PS		 6983 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6984 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6985 "TARGET_POWERPC64"
44cd321e
PS		 6986 "@
6987 rldcl %0,%1,%2,32
6988 rldicl %0,%1,%H2,32"
6989 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6990
6991(define_insn "*rotldi3_internal14"
44cd321e 6992 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6993 (compare:CC (zero_extend:DI
6994 (subreg:SI
44cd321e
PS		 6995 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6996 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6997 (const_int 0)))
44cd321e 6998 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6999 "TARGET_64BIT"
9ebbca7d 7000 "@
44cd321e
PS		 7001 rldcl. %3,%1,%2,32
7002 rldicl. %3,%1,%H2,32
7003 #
9ebbca7d 7004 #"
44cd321e
PS		 7005 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7006 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7007
7008(define_split
7009 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7010 (compare:CC (zero_extend:DI
7011 (subreg:SI
7012 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7013 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7014 (const_int 0)))
7015 (clobber (match_scratch:DI 3 ""))]
7016 "TARGET_POWERPC64 && reload_completed"
7017 [(set (match_dup 3)
7018 (zero_extend:DI (subreg:SI
7019 (rotate:DI (match_dup 1)
7020 (match_dup 2)) 0)))
7021 (set (match_dup 0)
7022 (compare:CC (match_dup 3)
7023 (const_int 0)))]
7024 "")
a260abc9
DE		 7025
7026(define_insn "*rotldi3_internal15"
44cd321e 7027 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7028 (compare:CC (zero_extend:DI
7029 (subreg:SI
44cd321e
PS		 7030 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7031 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7032 (const_int 0)))
44cd321e 7033 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7034 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7035 "TARGET_64BIT"
9ebbca7d 7036 "@
44cd321e
PS		 7037 rldcl. %0,%1,%2,32
7038 rldicl. %0,%1,%H2,32
7039 #
9ebbca7d 7040 #"
44cd321e
PS		 7041 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7042 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7043
7044(define_split
7045 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7046 (compare:CC (zero_extend:DI
7047 (subreg:SI
7048 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7049 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7050 (const_int 0)))
7051 (set (match_operand:DI 0 "gpc_reg_operand" "")
7052 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7053 "TARGET_POWERPC64 && reload_completed"
7054 [(set (match_dup 0)
7055 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7056 (set (match_dup 3)
7057 (compare:CC (match_dup 0)
7058 (const_int 0)))]
7059 "")
a260abc9 7060
266eb58a
DE		 7061(define_expand "ashldi3"
7062 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7063 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7064 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7065 "TARGET_POWERPC64 || TARGET_POWER"
7066 "
7067{
7068 if (TARGET_POWERPC64)
7069 ;
7070 else if (TARGET_POWER)
7071 {
7072 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7073 DONE;
7074 }
7075 else
7076 FAIL;
7077}")
7078
e2c953b6 7079(define_insn "*ashldi3_internal1"
44cd321e
PS		 7080 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7081 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7082 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7083 "TARGET_POWERPC64"
44cd321e
PS		 7084 "@
7085 sld %0,%1,%2
7086 sldi %0,%1,%H2"
7087 [(set_attr "type" "var_shift_rotate,shift")])
6ae08853 7088
e2c953b6 7089(define_insn "*ashldi3_internal2"
44cd321e
PS		 7090 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7091 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7092 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7093 (const_int 0)))
44cd321e 7094 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7095 "TARGET_64BIT"
9ebbca7d 7096 "@
44cd321e
PS		 7097 sld. %3,%1,%2
7098 sldi. %3,%1,%H2
7099 #
9ebbca7d 7100 #"
44cd321e
PS		 7101 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7102 (set_attr "length" "4,4,8,8")])
6ae08853 7103
9ebbca7d
GK		 7104(define_split
7105 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7106 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7107 (match_operand:SI 2 "reg_or_cint_operand" ""))
7108 (const_int 0)))
7109 (clobber (match_scratch:DI 3 ""))]
7110 "TARGET_POWERPC64 && reload_completed"
7111 [(set (match_dup 3)
7112 (ashift:DI (match_dup 1) (match_dup 2)))
7113 (set (match_dup 0)
7114 (compare:CC (match_dup 3)
7115 (const_int 0)))]
7116 "")
7117
e2c953b6 7118(define_insn "*ashldi3_internal3"
44cd321e
PS		 7119 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7120 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7121 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7122 (const_int 0)))
44cd321e 7123 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7124 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 7125 "TARGET_64BIT"
9ebbca7d 7126 "@
44cd321e
PS		 7127 sld. %0,%1,%2
7128 sldi. %0,%1,%H2
7129 #
9ebbca7d 7130 #"
44cd321e
PS		 7131 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7132 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7133
7134(define_split
7135 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7136 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7137 (match_operand:SI 2 "reg_or_cint_operand" ""))
7138 (const_int 0)))
7139 (set (match_operand:DI 0 "gpc_reg_operand" "")
7140 (ashift:DI (match_dup 1) (match_dup 2)))]
7141 "TARGET_POWERPC64 && reload_completed"
7142 [(set (match_dup 0)
7143 (ashift:DI (match_dup 1) (match_dup 2)))
7144 (set (match_dup 3)
7145 (compare:CC (match_dup 0)
7146 (const_int 0)))]
7147 "")
266eb58a 7148
e2c953b6 7149(define_insn "*ashldi3_internal4"
3cb999d8
DE		 7150 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7151 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7152 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 7153 (match_operand:DI 3 "const_int_operand" "n")))]
7154 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 7155 "rldic %0,%1,%H2,%W3")
3cb999d8 7156
e2c953b6 7157(define_insn "ashldi3_internal5"
9ebbca7d 7158 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 7159 (compare:CC
9ebbca7d
GK		 7160 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7161 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7162 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7163 (const_int 0)))
9ebbca7d 7164 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7165 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7166 "@
e2c953b6 7167 rldic. %4,%1,%H2,%W3
9ebbca7d 7168 #"
9c6fdb46 7169 [(set_attr "type" "compare")
9ebbca7d
GK		 7170 (set_attr "length" "4,8")])
7171
7172(define_split
7173 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7174 (compare:CC
7175 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7176 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7177 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7178 (const_int 0)))
7179 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 7180 "TARGET_POWERPC64 && reload_completed
7181 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 7182 [(set (match_dup 4)
7183 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 7184 (match_dup 3)))
9ebbca7d
GK		 7185 (set (match_dup 0)
7186 (compare:CC (match_dup 4)
7187 (const_int 0)))]
7188 "")
3cb999d8 7189
e2c953b6 7190(define_insn "*ashldi3_internal6"
9ebbca7d 7191 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 7192 (compare:CC
9ebbca7d
GK		 7193 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7194 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7195 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7196 (const_int 0)))
9ebbca7d 7197 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 7198 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7199 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7200 "@
e2c953b6 7201 rldic. %0,%1,%H2,%W3
9ebbca7d 7202 #"
9c6fdb46 7203 [(set_attr "type" "compare")
9ebbca7d
GK		 7204 (set_attr "length" "4,8")])
7205
7206(define_split
7207 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7208 (compare:CC
7209 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7210 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7211 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7212 (const_int 0)))
7213 (set (match_operand:DI 0 "gpc_reg_operand" "")
7214 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 7215 "TARGET_POWERPC64 && reload_completed
7216 && includes_rldic_lshift_p (operands[2], operands[3])"
7217 [(set (match_dup 0)
7218 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7219 (match_dup 3)))
7220 (set (match_dup 4)
7221 (compare:CC (match_dup 0)
7222 (const_int 0)))]
7223 "")
7224
7225(define_insn "*ashldi3_internal7"
7226 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7227 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7228 (match_operand:SI 2 "const_int_operand" "i"))
1990cd79 7229 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 7230 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7231 "rldicr %0,%1,%H2,%S3")
7232
7233(define_insn "ashldi3_internal8"
7234 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7235 (compare:CC
7236 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7237 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7238 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7239 (const_int 0)))
7240 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7241 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7242 "@
7243 rldicr. %4,%1,%H2,%S3
7244 #"
9c6fdb46 7245 [(set_attr "type" "compare")
c5059423
AM		 7246 (set_attr "length" "4,8")])
7247
7248(define_split
7249 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7250 (compare:CC
7251 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7252 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7253 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7254 (const_int 0)))
7255 (clobber (match_scratch:DI 4 ""))]
7256 "TARGET_POWERPC64 && reload_completed
7257 && includes_rldicr_lshift_p (operands[2], operands[3])"
7258 [(set (match_dup 4)
7259 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7260 (match_dup 3)))
7261 (set (match_dup 0)
7262 (compare:CC (match_dup 4)
7263 (const_int 0)))]
7264 "")
7265
7266(define_insn "*ashldi3_internal9"
7267 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7268 (compare:CC
7269 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7270 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7271 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7272 (const_int 0)))
7273 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7274 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7275 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7276 "@
7277 rldicr. %0,%1,%H2,%S3
7278 #"
9c6fdb46 7279 [(set_attr "type" "compare")
c5059423
AM		 7280 (set_attr "length" "4,8")])
7281
7282(define_split
7283 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7284 (compare:CC
7285 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7286 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7287 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7288 (const_int 0)))
7289 (set (match_operand:DI 0 "gpc_reg_operand" "")
7290 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7291 "TARGET_POWERPC64 && reload_completed
7292 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 7293 [(set (match_dup 0)
e2c953b6
DE		 7294 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7295 (match_dup 3)))
9ebbca7d
GK		 7296 (set (match_dup 4)
7297 (compare:CC (match_dup 0)
7298 (const_int 0)))]
7299 "")
7300
7301(define_expand "lshrdi3"
266eb58a
DE		 7302 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7303 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7304 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7305 "TARGET_POWERPC64 || TARGET_POWER"
7306 "
7307{
7308 if (TARGET_POWERPC64)
7309 ;
7310 else if (TARGET_POWER)
7311 {
7312 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7313 DONE;
7314 }
7315 else
7316 FAIL;
7317}")
7318
e2c953b6 7319(define_insn "*lshrdi3_internal1"
44cd321e
PS		 7320 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7321 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7322 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7323 "TARGET_POWERPC64"
44cd321e
PS		 7324 "@
7325 srd %0,%1,%2
7326 srdi %0,%1,%H2"
7327 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7328
e2c953b6 7329(define_insn "*lshrdi3_internal2"
44cd321e
PS		 7330 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7331 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7332 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
29ae5b89 7333 (const_int 0)))
44cd321e 7334 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7335 "TARGET_64BIT "
9ebbca7d 7336 "@
44cd321e
PS		 7337 srd. %3,%1,%2
7338 srdi. %3,%1,%H2
7339 #
9ebbca7d 7340 #"
44cd321e
PS		 7341 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7342 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7343
7344(define_split
7345 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7346 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7347 (match_operand:SI 2 "reg_or_cint_operand" ""))
7348 (const_int 0)))
7349 (clobber (match_scratch:DI 3 ""))]
7350 "TARGET_POWERPC64 && reload_completed"
7351 [(set (match_dup 3)
7352 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7353 (set (match_dup 0)
7354 (compare:CC (match_dup 3)
7355 (const_int 0)))]
7356 "")
266eb58a 7357
e2c953b6 7358(define_insn "*lshrdi3_internal3"
44cd321e
PS		 7359 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7360 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7361 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7362 (const_int 0)))
44cd321e 7363 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 7364 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7365 "TARGET_64BIT"
9ebbca7d 7366 "@
44cd321e
PS		 7367 srd. %0,%1,%2
7368 srdi. %0,%1,%H2
7369 #
9ebbca7d 7370 #"
44cd321e
PS		 7371 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7372 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7373
7374(define_split
7375 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7376 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7377 (match_operand:SI 2 "reg_or_cint_operand" ""))
7378 (const_int 0)))
7379 (set (match_operand:DI 0 "gpc_reg_operand" "")
7380 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7381 "TARGET_POWERPC64 && reload_completed"
7382 [(set (match_dup 0)
7383 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7384 (set (match_dup 3)
7385 (compare:CC (match_dup 0)
7386 (const_int 0)))]
7387 "")
266eb58a
DE		 7388
7389(define_expand "ashrdi3"
7390 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7391 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7392 (match_operand:SI 2 "reg_or_cint_operand" "")))]
97727e85 7393 "WORDS_BIG_ENDIAN"
266eb58a
DE		 7394 "
7395{
7396 if (TARGET_POWERPC64)
7397 ;
7398 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7399 {
7400 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7401 DONE;
7402 }
97727e85
AH		 7403 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7404 && WORDS_BIG_ENDIAN)
4aa74a4f
FS		 7405 {
7406 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7407 DONE;
7408 }
266eb58a
DE		 7409 else
7410 FAIL;
7411}")
7412
e2c953b6 7413(define_insn "*ashrdi3_internal1"
44cd321e
PS		 7414 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7415 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7416 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7417 "TARGET_POWERPC64"
44cd321e
PS		 7418 "@
7419 srad %0,%1,%2
7420 sradi %0,%1,%H2"
7421 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7422
e2c953b6 7423(define_insn "*ashrdi3_internal2"
44cd321e
PS		 7424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7425 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7426 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7427 (const_int 0)))
44cd321e 7428 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7429 "TARGET_64BIT"
9ebbca7d 7430 "@
44cd321e
PS		 7431 srad. %3,%1,%2
7432 sradi. %3,%1,%H2
7433 #
9ebbca7d 7434 #"
44cd321e
PS		 7435 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7436 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7437
7438(define_split
7439 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7440 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7441 (match_operand:SI 2 "reg_or_cint_operand" ""))
7442 (const_int 0)))
7443 (clobber (match_scratch:DI 3 ""))]
7444 "TARGET_POWERPC64 && reload_completed"
7445 [(set (match_dup 3)
7446 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7447 (set (match_dup 0)
7448 (compare:CC (match_dup 3)
7449 (const_int 0)))]
7450 "")
266eb58a 7451
e2c953b6 7452(define_insn "*ashrdi3_internal3"
44cd321e
PS		 7453 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7454 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7455 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7456 (const_int 0)))
44cd321e 7457 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7458 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7459 "TARGET_64BIT"
9ebbca7d 7460 "@
44cd321e
PS		 7461 srad. %0,%1,%2
7462 sradi. %0,%1,%H2
7463 #
9ebbca7d 7464 #"
44cd321e
PS		 7465 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7466 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7467
7468(define_split
7469 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7470 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7471 (match_operand:SI 2 "reg_or_cint_operand" ""))
7472 (const_int 0)))
7473 (set (match_operand:DI 0 "gpc_reg_operand" "")
7474 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7475 "TARGET_POWERPC64 && reload_completed"
7476 [(set (match_dup 0)
7477 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7478 (set (match_dup 3)
7479 (compare:CC (match_dup 0)
7480 (const_int 0)))]
7481 "")
815cdc52 7482
29ae5b89 7483(define_insn "anddi3"
e1e2e653
NS		 7484 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7485 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7486 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7487 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6ffc8580 7488 "TARGET_POWERPC64"
266eb58a
DE		 7489 "@
7490 and %0,%1,%2
29ae5b89 7491 rldic%B2 %0,%1,0,%S2
e1e2e653 7492 rlwinm %0,%1,0,%m2,%M2
29ae5b89 7493 andi. %0,%1,%b2
0ba1b2ff
AM		 7494 andis. %0,%1,%u2
7495 #"
e1e2e653
NS		 7496 [(set_attr "type" "*,*,*,compare,compare,*")
7497 (set_attr "length" "4,4,4,4,4,8")])
0ba1b2ff
AM		 7498
7499(define_split
7500 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7501 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7502 (match_operand:DI 2 "mask64_2_operand" "")))
7503 (clobber (match_scratch:CC 3 ""))]
7504 "TARGET_POWERPC64
7505 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7506 && !mask_operand (operands[2], DImode)
7507 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7508 [(set (match_dup 0)
7509 (and:DI (rotate:DI (match_dup 1)
7510 (match_dup 4))
7511 (match_dup 5)))
7512 (set (match_dup 0)
7513 (and:DI (rotate:DI (match_dup 0)
7514 (match_dup 6))
7515 (match_dup 7)))]
0ba1b2ff
AM		 7516{
7517 build_mask64_2_operands (operands[2], &operands[4]);
e1e2e653 7518})
266eb58a 7519
a260abc9 7520(define_insn "*anddi3_internal2"
1990cd79
AM		 7521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7522 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7523 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7524 (const_int 0)))
1990cd79
AM		 7525 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7526 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7527 "TARGET_64BIT"
266eb58a
DE		 7528 "@
7529 and. %3,%1,%2
6c873122 7530 rldic%B2. %3,%1,0,%S2
1990cd79 7531 rlwinm. %3,%1,0,%m2,%M2
6ffc8580
MM		 7532 andi. %3,%1,%b2
7533 andis. %3,%1,%u2
9ebbca7d
GK		 7534 #
7535 #
7536 #
0ba1b2ff
AM		 7537 #
7538 #
1990cd79 7539 #
9ebbca7d 7540 #"
44cd321e 7541 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7542 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d 7543
0ba1b2ff
AM		 7544(define_split
7545 [(set (match_operand:CC 0 "cc_reg_operand" "")
7546 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7547 (match_operand:DI 2 "mask64_2_operand" ""))
7548 (const_int 0)))
7549 (clobber (match_scratch:DI 3 ""))
7550 (clobber (match_scratch:CC 4 ""))]
1990cd79 7551 "TARGET_64BIT && reload_completed
0ba1b2ff 7552 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7553 && !mask_operand (operands[2], DImode)
7554 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7555 [(set (match_dup 3)
7556 (and:DI (rotate:DI (match_dup 1)
7557 (match_dup 5))
7558 (match_dup 6)))
7559 (parallel [(set (match_dup 0)
7560 (compare:CC (and:DI (rotate:DI (match_dup 3)
7561 (match_dup 7))
7562 (match_dup 8))
7563 (const_int 0)))
7564 (clobber (match_dup 3))])]
7565 "
7566{
7567 build_mask64_2_operands (operands[2], &operands[5]);
7568}")
7569
a260abc9 7570(define_insn "*anddi3_internal3"
1990cd79
AM		 7571 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7572 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7573 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7574 (const_int 0)))
1990cd79 7575 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7576 (and:DI (match_dup 1) (match_dup 2)))
1990cd79 7577 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7578 "TARGET_64BIT"
266eb58a
DE		 7579 "@
7580 and. %0,%1,%2
6c873122 7581 rldic%B2. %0,%1,0,%S2
1990cd79 7582 rlwinm. %0,%1,0,%m2,%M2
6ffc8580
MM		 7583 andi. %0,%1,%b2
7584 andis. %0,%1,%u2
9ebbca7d
GK		 7585 #
7586 #
7587 #
0ba1b2ff
AM		 7588 #
7589 #
1990cd79 7590 #
9ebbca7d 7591 #"
44cd321e 7592 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7593 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d
GK		 7594
7595(define_split
7596 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7597 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
1990cd79 7598 (match_operand:DI 2 "and64_2_operand" ""))
9ebbca7d
GK		 7599 (const_int 0)))
7600 (set (match_operand:DI 0 "gpc_reg_operand" "")
7601 (and:DI (match_dup 1) (match_dup 2)))
7602 (clobber (match_scratch:CC 4 ""))]
1990cd79 7603 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 7604 [(parallel [(set (match_dup 0)
7605 (and:DI (match_dup 1) (match_dup 2)))
7606 (clobber (match_dup 4))])
7607 (set (match_dup 3)
7608 (compare:CC (match_dup 0)
7609 (const_int 0)))]
7610 "")
266eb58a 7611
0ba1b2ff
AM		 7612(define_split
7613 [(set (match_operand:CC 3 "cc_reg_operand" "")
7614 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7615 (match_operand:DI 2 "mask64_2_operand" ""))
7616 (const_int 0)))
7617 (set (match_operand:DI 0 "gpc_reg_operand" "")
7618 (and:DI (match_dup 1) (match_dup 2)))
7619 (clobber (match_scratch:CC 4 ""))]
1990cd79 7620 "TARGET_64BIT && reload_completed
0ba1b2ff 7621 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7622 && !mask_operand (operands[2], DImode)
7623 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7624 [(set (match_dup 0)
7625 (and:DI (rotate:DI (match_dup 1)
7626 (match_dup 5))
7627 (match_dup 6)))
7628 (parallel [(set (match_dup 3)
7629 (compare:CC (and:DI (rotate:DI (match_dup 0)
7630 (match_dup 7))
7631 (match_dup 8))
7632 (const_int 0)))
7633 (set (match_dup 0)
7634 (and:DI (rotate:DI (match_dup 0)
7635 (match_dup 7))
7636 (match_dup 8)))])]
7637 "
7638{
7639 build_mask64_2_operands (operands[2], &operands[5]);
7640}")
7641
a260abc9 7642(define_expand "iordi3"
266eb58a 7643 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7644 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7645 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7646 "TARGET_POWERPC64"
266eb58a
DE		 7647 "
7648{
dfbdccdb 7649 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7650 {
dfbdccdb 7651 HOST_WIDE_INT value;
677a9668 7652 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9 7653 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7654
dfbdccdb
GK		 7655 if (GET_CODE (operands[2]) == CONST_INT)
7656 {
7657 value = INTVAL (operands[2]);
7658 emit_insn (gen_iordi3 (tmp, operands[1],
7659 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7660 }
e2c953b6 7661 else
dfbdccdb
GK		 7662 {
7663 value = CONST_DOUBLE_LOW (operands[2]);
7664 emit_insn (gen_iordi3 (tmp, operands[1],
7665 immed_double_const (value
7666 & (~ (HOST_WIDE_INT) 0xffff),
7667 0, DImode)));
7668 }
e2c953b6 7669
9ebbca7d
GK		 7670 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7671 DONE;
7672 }
266eb58a
DE		 7673}")
7674
a260abc9
DE		 7675(define_expand "xordi3"
7676 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7677 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7678 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7679 "TARGET_POWERPC64"
7680 "
7681{
dfbdccdb 7682 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7683 {
dfbdccdb 7684 HOST_WIDE_INT value;
677a9668 7685 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7686 ? operands[0] : gen_reg_rtx (DImode));
7687
dfbdccdb
GK		 7688 if (GET_CODE (operands[2]) == CONST_INT)
7689 {
7690 value = INTVAL (operands[2]);
7691 emit_insn (gen_xordi3 (tmp, operands[1],
7692 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7693 }
e2c953b6 7694 else
dfbdccdb
GK		 7695 {
7696 value = CONST_DOUBLE_LOW (operands[2]);
7697 emit_insn (gen_xordi3 (tmp, operands[1],
7698 immed_double_const (value
7699 & (~ (HOST_WIDE_INT) 0xffff),
7700 0, DImode)));
7701 }
e2c953b6 7702
9ebbca7d
GK		 7703 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7704 DONE;
7705 }
a260abc9
DE		 7706}")
7707
dfbdccdb 7708(define_insn "*booldi3_internal1"
266eb58a 7709 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7710 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7711 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7712 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7713 "TARGET_POWERPC64"
1fd4e8c1 7714 "@
dfbdccdb
GK		 7715 %q3 %0,%1,%2
7716 %q3i %0,%1,%b2
7717 %q3is %0,%1,%u2")
1fd4e8c1 7718
dfbdccdb 7719(define_insn "*booldi3_internal2"
9ebbca7d 7720 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7721 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7722 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7723 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7724 (const_int 0)))
9ebbca7d 7725 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7726 "TARGET_64BIT"
9ebbca7d 7727 "@
dfbdccdb 7728 %q4. %3,%1,%2
9ebbca7d
GK		 7729 #"
7730 [(set_attr "type" "compare")
7731 (set_attr "length" "4,8")])
7732
7733(define_split
7734 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7735 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7736 [(match_operand:DI 1 "gpc_reg_operand" "")
7737 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7738 (const_int 0)))
9ebbca7d
GK		 7739 (clobber (match_scratch:DI 3 ""))]
7740 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7741 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7742 (set (match_dup 0)
7743 (compare:CC (match_dup 3)
7744 (const_int 0)))]
7745 "")
1fd4e8c1 7746
dfbdccdb 7747(define_insn "*booldi3_internal3"
9ebbca7d 7748 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7749 (compare:CC (match_operator:DI 4 "boolean_operator"
7750 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7751 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7752 (const_int 0)))
9ebbca7d 7753 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7754 (match_dup 4))]
683bdff7 7755 "TARGET_64BIT"
9ebbca7d 7756 "@
dfbdccdb 7757 %q4. %0,%1,%2
9ebbca7d
GK		 7758 #"
7759 [(set_attr "type" "compare")
7760 (set_attr "length" "4,8")])
7761
7762(define_split
e72247f4 7763 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7764 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7765 [(match_operand:DI 1 "gpc_reg_operand" "")
7766 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7767 (const_int 0)))
75540af0 7768 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7769 (match_dup 4))]
9ebbca7d 7770 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7771 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7772 (set (match_dup 3)
7773 (compare:CC (match_dup 0)
7774 (const_int 0)))]
7775 "")
1fd4e8c1 7776
6ae08853 7777;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7778;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7779
7780(define_split
7781 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7782 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7783 [(match_operand:DI 1 "gpc_reg_operand" "")
7784 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7785 "TARGET_POWERPC64"
dfbdccdb
GK		 7786 [(set (match_dup 0) (match_dup 4))
7787 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7788"
7789{
dfbdccdb 7790 rtx i3,i4;
6ae08853 7791
9ebbca7d
GK		 7792 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7793 {
7794 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7795 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7796 0, DImode);
dfbdccdb 7797 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7798 }
7799 else
7800 {
dfbdccdb 7801 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7802 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7803 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7804 }
1c563bed 7805 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7806 operands[1], i3);
1c563bed 7807 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7808 operands[0], i4);
1fd4e8c1
RK		 7809}")
7810
dfbdccdb 7811(define_insn "*boolcdi3_internal1"
9ebbca7d 7812 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7813 (match_operator:DI 3 "boolean_operator"
7814 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7815 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7816 "TARGET_POWERPC64"
1d328b19 7817 "%q3 %0,%2,%1")
a473029f 7818
dfbdccdb 7819(define_insn "*boolcdi3_internal2"
9ebbca7d 7820 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7821 (compare:CC (match_operator:DI 4 "boolean_operator"
7822 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7823 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7824 (const_int 0)))
9ebbca7d 7825 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7826 "TARGET_64BIT"
9ebbca7d 7827 "@
1d328b19 7828 %q4. %3,%2,%1
9ebbca7d
GK		 7829 #"
7830 [(set_attr "type" "compare")
7831 (set_attr "length" "4,8")])
7832
7833(define_split
7834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7835 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7836 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7837 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7838 (const_int 0)))
9ebbca7d
GK		 7839 (clobber (match_scratch:DI 3 ""))]
7840 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7841 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7842 (set (match_dup 0)
7843 (compare:CC (match_dup 3)
7844 (const_int 0)))]
7845 "")
a473029f 7846
dfbdccdb 7847(define_insn "*boolcdi3_internal3"
9ebbca7d 7848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7849 (compare:CC (match_operator:DI 4 "boolean_operator"
7850 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7851 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7852 (const_int 0)))
9ebbca7d 7853 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7854 (match_dup 4))]
683bdff7 7855 "TARGET_64BIT"
9ebbca7d 7856 "@
1d328b19 7857 %q4. %0,%2,%1
9ebbca7d
GK		 7858 #"
7859 [(set_attr "type" "compare")
7860 (set_attr "length" "4,8")])
7861
7862(define_split
e72247f4 7863 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7864 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7865 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7866 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7867 (const_int 0)))
75540af0 7868 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7869 (match_dup 4))]
9ebbca7d 7870 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7871 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7872 (set (match_dup 3)
7873 (compare:CC (match_dup 0)
7874 (const_int 0)))]
7875 "")
266eb58a 7876
dfbdccdb 7877(define_insn "*boolccdi3_internal1"
a473029f 7878 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7879 (match_operator:DI 3 "boolean_operator"
7880 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7881 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 7882 "TARGET_POWERPC64"
dfbdccdb 7883 "%q3 %0,%1,%2")
a473029f 7884
dfbdccdb 7885(define_insn "*boolccdi3_internal2"
9ebbca7d 7886 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7887 (compare:CC (match_operator:DI 4 "boolean_operator"
7888 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7889 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7890 (const_int 0)))
9ebbca7d 7891 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7892 "TARGET_64BIT"
9ebbca7d 7893 "@
dfbdccdb 7894 %q4. %3,%1,%2
9ebbca7d
GK		 7895 #"
7896 [(set_attr "type" "compare")
7897 (set_attr "length" "4,8")])
7898
7899(define_split
7900 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7901 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7902 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7903 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7904 (const_int 0)))
9ebbca7d
GK		 7905 (clobber (match_scratch:DI 3 ""))]
7906 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7907 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7908 (set (match_dup 0)
7909 (compare:CC (match_dup 3)
7910 (const_int 0)))]
7911 "")
266eb58a 7912
dfbdccdb 7913(define_insn "*boolccdi3_internal3"
9ebbca7d 7914 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7915 (compare:CC (match_operator:DI 4 "boolean_operator"
7916 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7917 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7918 (const_int 0)))
9ebbca7d 7919 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7920 (match_dup 4))]
683bdff7 7921 "TARGET_64BIT"
9ebbca7d 7922 "@
dfbdccdb 7923 %q4. %0,%1,%2
9ebbca7d
GK		 7924 #"
7925 [(set_attr "type" "compare")
7926 (set_attr "length" "4,8")])
7927
7928(define_split
e72247f4 7929 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7930 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7931 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7932 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7933 (const_int 0)))
75540af0 7934 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7935 (match_dup 4))]
9ebbca7d 7936 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7937 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7938 (set (match_dup 3)
7939 (compare:CC (match_dup 0)
7940 (const_int 0)))]
7941 "")
dfbdccdb 7942\f
1fd4e8c1 7943;; Now define ways of moving data around.
4697a36c 7944
766a866c
MM		 7945;; Set up a register with a value from the GOT table
7946
7947(define_expand "movsi_got"
52d3af72 7948 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7949 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 7950 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 7951 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7952 "
7953{
38c1f2d7
MM		 7954 if (GET_CODE (operands[1]) == CONST)
7955 {
7956 rtx offset = const0_rtx;
7957 HOST_WIDE_INT value;
7958
7959 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7960 value = INTVAL (offset);
7961 if (value != 0)
7962 {
677a9668 7963 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
38c1f2d7
MM		 7964 emit_insn (gen_movsi_got (tmp, operands[1]));
7965 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7966 DONE;
7967 }
7968 }
7969
c4c40373 7970 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 7971}")
7972
84f414bc 7973(define_insn "*movsi_got_internal"
52d3af72 7974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 7975 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 7976 (match_operand:SI 2 "gpc_reg_operand" "b")]
7977 UNSPEC_MOVSI_GOT))]
f607bc57 7978 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7979 "{l|lwz} %0,%a1@got(%2)"
7980 [(set_attr "type" "load")])
7981
b22b9b3e
JL		 7982;; Used by sched, shorten_branches and final when the GOT pseudo reg
7983;; didn't get allocated to a hard register.
6ae08853 7984(define_split
75540af0 7985 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7986 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 7987 (match_operand:SI 2 "memory_operand" "")]
7988 UNSPEC_MOVSI_GOT))]
f607bc57 7989 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 7990 && flag_pic == 1
7991 && (reload_in_progress || reload_completed)"
7992 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 7993 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7994 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 7995 "")
7996
1fd4e8c1
RK		 7997;; For SI, we special-case integers that can't be loaded in one insn. We
7998;; do the load 16-bits at a time. We could do this by loading from memory,
7999;; and this is even supposed to be faster, but it is simpler not to get
8000;; integers in the TOC.
ee890fe2
SS		 8001(define_insn "movsi_low"
8002 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 8003 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 8004 (match_operand 2 "" ""))))]
8005 "TARGET_MACHO && ! TARGET_64BIT"
8006 "{l|lwz} %0,lo16(%2)(%1)"
8007 [(set_attr "type" "load")
8008 (set_attr "length" "4")])
8009
acad7ed3 8010(define_insn "*movsi_internal1"
165a5bad 8011 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
a004eb82 8012 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
19d5775a
RK		 8013 "gpc_reg_operand (operands[0], SImode)
8014 || gpc_reg_operand (operands[1], SImode)"
1fd4e8c1 8015 "@
deb9225a 8016 mr %0,%1
b9442c72 8017 {cal|la} %0,%a1
ca7f5001
RK		 8018 {l%U1%X1|lwz%U1%X1} %0,%1
8019 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 8020 {lil|li} %0,%1
802a0058 8021 {liu|lis} %0,%v1
beaec479 8022 #
aee86b38 8023 {cal|la} %0,%a1
1fd4e8c1 8024 mf%1 %0
5c23c401 8025 mt%0 %1
e76e75bb 8026 mt%0 %1
a004eb82 8027 mt%0 %1
e34eaae5 8028 {cror 0,0,0|nop}"
02ca7595 8029 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 8030 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 8031
77fa0940
RK		 8032;; Split a load of a large constant into the appropriate two-insn
8033;; sequence.
8034
8035(define_split
8036 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8037 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 8038 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 8039 && (INTVAL (operands[1]) & 0xffff) != 0"
8040 [(set (match_dup 0)
8041 (match_dup 2))
8042 (set (match_dup 0)
8043 (ior:SI (match_dup 0)
8044 (match_dup 3)))]
8045 "
af8cb5c5
DE		 8046{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8047
8048 if (tem == operands[0])
8049 DONE;
8050 else
8051 FAIL;
77fa0940
RK		 8052}")
8053
4ae234b0 8054(define_insn "*mov<mode>_internal2"
bb84cb12 8055 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
4ae234b0 8056 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 8057 (const_int 0)))
4ae234b0
GK		 8058 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8059 ""
9ebbca7d 8060 "@
4ae234b0 8061 {cmpi|cmp<wd>i} %2,%0,0
9ebbca7d
GK		 8062 mr. %0,%1
8063 #"
bb84cb12
DE		 8064 [(set_attr "type" "cmp,compare,cmp")
8065 (set_attr "length" "4,4,8")])
8066
9ebbca7d
GK		 8067(define_split
8068 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
4ae234b0 8069 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9ebbca7d 8070 (const_int 0)))
4ae234b0
GK		 8071 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8072 "reload_completed"
9ebbca7d
GK		 8073 [(set (match_dup 0) (match_dup 1))
8074 (set (match_dup 2)
8075 (compare:CC (match_dup 0)
8076 (const_int 0)))]
8077 "")
bb84cb12 8078\f
e34eaae5 8079(define_insn "*movhi_internal"
fb81d7ce
RK		 8080 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8081 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8082 "gpc_reg_operand (operands[0], HImode)
8083 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 8084 "@
deb9225a 8085 mr %0,%1
1fd4e8c1
RK		 8086 lhz%U1%X1 %0,%1
8087 sth%U0%X0 %1,%0
19d5775a 8088 {lil|li} %0,%w1
1fd4e8c1 8089 mf%1 %0
e76e75bb 8090 mt%0 %1
fb81d7ce 8091 mt%0 %1
e34eaae5 8092 {cror 0,0,0|nop}"
02ca7595 8093 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1 8094
4ae234b0
GK		 8095(define_expand "mov<mode>"
8096 [(set (match_operand:INT 0 "general_operand" "")
8097 (match_operand:INT 1 "any_operand" ""))]
1fd4e8c1 8098 ""
4ae234b0 8099 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
1fd4e8c1 8100
e34eaae5 8101(define_insn "*movqi_internal"
fb81d7ce
RK		 8102 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8103 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8104 "gpc_reg_operand (operands[0], QImode)
8105 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 8106 "@
deb9225a 8107 mr %0,%1
1fd4e8c1
RK		 8108 lbz%U1%X1 %0,%1
8109 stb%U0%X0 %1,%0
19d5775a 8110 {lil|li} %0,%1
1fd4e8c1 8111 mf%1 %0
e76e75bb 8112 mt%0 %1
fb81d7ce 8113 mt%0 %1
e34eaae5 8114 {cror 0,0,0|nop}"
02ca7595 8115 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 8116\f
8117;; Here is how to move condition codes around. When we store CC data in
8118;; an integer register or memory, we store just the high-order 4 bits.
8119;; This lets us not shift in the most common case of CR0.
8120(define_expand "movcc"
8121 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8122 (match_operand:CC 1 "nonimmediate_operand" ""))]
8123 ""
8124 "")
8125
a65c591c 8126(define_insn "*movcc_internal1"
4eb585a4
DE		 8127 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8128 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
1fd4e8c1
RK		 8129 "register_operand (operands[0], CCmode)
8130 || register_operand (operands[1], CCmode)"
8131 "@
8132 mcrf %0,%1
8133 mtcrf 128,%1
ca7f5001 8134 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
4eb585a4 8135 crxor %0,%0,%0
2c4a9cff
DE		 8136 mfcr %0%Q1
8137 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 8138 mr %0,%1
4eb585a4 8139 {lil|li} %0,%1
b54cf83a 8140 mf%1 %0
b991a865
GK		 8141 mt%0 %1
8142 mt%0 %1
ca7f5001
RK		 8143 {l%U1%X1|lwz%U1%X1} %0,%1
8144 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff 8145 [(set (attr "type")
4eb585a4 8146 (cond [(eq_attr "alternative" "0,3")
2c4a9cff
DE		 8147 (const_string "cr_logical")
8148 (eq_attr "alternative" "1,2")
8149 (const_string "mtcr")
4eb585a4 8150 (eq_attr "alternative" "6,7,9")
2c4a9cff 8151 (const_string "integer")
2c4a9cff 8152 (eq_attr "alternative" "8")
4eb585a4
DE		 8153 (const_string "mfjmpr")
8154 (eq_attr "alternative" "10")
2c4a9cff 8155 (const_string "mtjmpr")
4eb585a4 8156 (eq_attr "alternative" "11")
2c4a9cff 8157 (const_string "load")
4eb585a4 8158 (eq_attr "alternative" "12")
2c4a9cff
DE		 8159 (const_string "store")
8160 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8161 (const_string "mfcrf")
8162 ]
8163 (const_string "mfcr")))
4eb585a4 8164 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
1fd4e8c1 8165\f
e52e05ca
MM		 8166;; For floating-point, we normally deal with the floating-point registers
8167;; unless -msoft-float is used. The sole exception is that parameter passing
8168;; can produce floating-point values in fixed-point registers. Unless the
8169;; value is a simple constant or already in memory, we deal with this by
8170;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 8171(define_expand "movsf"
8172 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8173 (match_operand:SF 1 "any_operand" ""))]
8174 ""
fb4d4348 8175 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 8176
1fd4e8c1 8177(define_split
cd2b37d9 8178 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 8179 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 8180 "reload_completed
5ae4759c
MM		 8181 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8182 || (GET_CODE (operands[0]) == SUBREG
8183 && GET_CODE (SUBREG_REG (operands[0])) == REG
8184 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 8185 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 8186 "
8187{
8188 long l;
8189 REAL_VALUE_TYPE rv;
8190
8191 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8192 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 8193
f99f88e0
DE		 8194 if (! TARGET_POWERPC64)
8195 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8196 else
8197 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 8198
2496c7bd 8199 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 8200}")
8201
c4c40373 8202(define_insn "*movsf_hardfloat"
fb3249ef 8203 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
ae6669e7 8204 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
d14a6d05 8205 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8206 || gpc_reg_operand (operands[1], SFmode))
8207 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
1fd4e8c1 8208 "@
f99f88e0
DE		 8209 mr %0,%1
8210 {l%U1%X1|lwz%U1%X1} %0,%1
8211 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 8212 fmr %0,%1
8213 lfs%U1%X1 %0,%1
c4c40373 8214 stfs%U0%X0 %1,%0
b991a865
GK		 8215 mt%0 %1
8216 mt%0 %1
8217 mf%1 %0
e0740893 8218 {cror 0,0,0|nop}
c4c40373
MM		 8219 #
8220 #"
9c6fdb46 8221 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
ae6669e7 8222 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 8223
c4c40373 8224(define_insn "*movsf_softfloat"
dd0fbae2
MK		 8225 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8226 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 8227 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8228 || gpc_reg_operand (operands[1], SFmode))
8229 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 8230 "@
8231 mr %0,%1
b991a865
GK		 8232 mt%0 %1
8233 mt%0 %1
8234 mf%1 %0
d14a6d05
MM		 8235 {l%U1%X1|lwz%U1%X1} %0,%1
8236 {st%U0%X0|stw%U0%X0} %1,%0
8237 {lil|li} %0,%1
802a0058 8238 {liu|lis} %0,%v1
aee86b38 8239 {cal|la} %0,%a1
c4c40373 8240 #
dd0fbae2
MK		 8241 #
8242 {cror 0,0,0|nop}"
9c6fdb46 8243 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
dd0fbae2 8244 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 8245
1fd4e8c1
RK		 8246\f
8247(define_expand "movdf"
8248 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8249 (match_operand:DF 1 "any_operand" ""))]
8250 ""
fb4d4348 8251 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 8252
8253(define_split
cd2b37d9 8254 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 8255 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 8256 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8257 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8258 || (GET_CODE (operands[0]) == SUBREG
8259 && GET_CODE (SUBREG_REG (operands[0])) == REG
8260 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8261 [(set (match_dup 2) (match_dup 4))
8262 (set (match_dup 3) (match_dup 1))]
8263 "
8264{
5ae4759c 8265 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 8266 HOST_WIDE_INT value = INTVAL (operands[1]);
8267
5ae4759c
MM		 8268 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8269 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 8270#if HOST_BITS_PER_WIDE_INT == 32
8271 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8272#else
8273 operands[4] = GEN_INT (value >> 32);
a65c591c 8274 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 8275#endif
c4c40373
MM		 8276}")
8277
c4c40373
MM		 8278(define_split
8279 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8280 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8281 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8282 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8283 || (GET_CODE (operands[0]) == SUBREG
8284 && GET_CODE (SUBREG_REG (operands[0])) == REG
8285 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8286 [(set (match_dup 2) (match_dup 4))
8287 (set (match_dup 3) (match_dup 5))]
8288 "
8289{
5ae4759c 8290 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 8291 long l[2];
8292 REAL_VALUE_TYPE rv;
8293
8294 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8295 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8296
5ae4759c
MM		 8297 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8298 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 8299 operands[4] = gen_int_mode (l[endian], SImode);
8300 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 8301}")
8302
efc08378
DE		 8303(define_split
8304 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8308679f 8305 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8306 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8307 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8308 || (GET_CODE (operands[0]) == SUBREG
8309 && GET_CODE (SUBREG_REG (operands[0])) == REG
8310 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 8311 [(set (match_dup 2) (match_dup 3))]
5ae4759c 8312 "
a260abc9
DE		 8313{
8314 int endian = (WORDS_BIG_ENDIAN == 0);
8315 long l[2];
8316 REAL_VALUE_TYPE rv;
4977bab6 8317#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 8318 HOST_WIDE_INT val;
4977bab6 8319#endif
a260abc9
DE		 8320
8321 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8322 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8323
8324 operands[2] = gen_lowpart (DImode, operands[0]);
8325 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 8326#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8327 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8328 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 8329
f5264b52 8330 operands[3] = gen_int_mode (val, DImode);
5b029315 8331#else
a260abc9 8332 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 8333#endif
a260abc9 8334}")
efc08378 8335
4eae5fe1 8336;; Don't have reload use general registers to load a constant. First,
1427100a 8337;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 8338;; a non-offsettable memref, but also it is less efficient than loading
8339;; the constant into an FP register, since it will probably be used there.
8340;; The "??" is a kludge until we can figure out a more reasonable way
8341;; of handling these non-offsettable values.
c4c40373 8342(define_insn "*movdf_hardfloat32"
914a7297
DE		 8343 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8344 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
a3170dc6 8345 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8346 && (gpc_reg_operand (operands[0], DFmode)
8347 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 8348 "*
8349{
8350 switch (which_alternative)
8351 {
a260abc9 8352 default:
37409796 8353 gcc_unreachable ();
e7113111
RK		 8354 case 0:
8355 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 8356 the first register operand 0 is the same as the second register
8357 of operand 1, we must copy in the opposite order. */
e7113111 8358 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8359 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 8360 else
deb9225a 8361 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 8362 case 1:
d04b6e6e
EB		 8363 if (rs6000_offsettable_memref_p (operands[1])
8364 || (GET_CODE (operands[1]) == MEM
8365 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8366 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8367 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
000034eb
DE		 8368 {
8369 /* If the low-address word is used in the address, we must load
8370 it last. Otherwise, load it first. Note that we cannot have
8371 auto-increment in that case since the address register is
8372 known to be dead. */
8373 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8374 operands[1], 0))
8375 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8376 else
8377 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8378 }
e7113111 8379 else
000034eb
DE		 8380 {
8381 rtx addreg;
8382
000034eb
DE		 8383 addreg = find_addr_reg (XEXP (operands[1], 0));
8384 if (refers_to_regno_p (REGNO (operands[0]),
8385 REGNO (operands[0]) + 1,
8386 operands[1], 0))
8387 {
8388 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8389 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb 8390 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2284bd2b 8391 return \"{l%X1|lwz%X1} %0,%1\";
000034eb
DE		 8392 }
8393 else
8394 {
2284bd2b 8395 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
000034eb 8396 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8397 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb
DE		 8398 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8399 return \"\";
8400 }
8401 }
e7113111 8402 case 2:
d04b6e6e
EB		 8403 if (rs6000_offsettable_memref_p (operands[0])
8404 || (GET_CODE (operands[0]) == MEM
8405 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8406 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8407 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
000034eb
DE		 8408 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8409 else
8410 {
8411 rtx addreg;
8412
000034eb 8413 addreg = find_addr_reg (XEXP (operands[0], 0));
2284bd2b 8414 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
000034eb 8415 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8416 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
000034eb
DE		 8417 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8418 return \"\";
8419 }
e7113111 8420 case 3:
914a7297 8421 return \"fmr %0,%1\";
e7113111 8422 case 4:
914a7297 8423 return \"lfd%U1%X1 %0,%1\";
e7113111 8424 case 5:
914a7297 8425 return \"stfd%U0%X0 %1,%0\";
e7113111 8426 case 6:
c4c40373 8427 case 7:
c4c40373 8428 case 8:
914a7297 8429 return \"#\";
e7113111
RK		 8430 }
8431}"
943c15ed 8432 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
914a7297 8433 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 8434
c4c40373 8435(define_insn "*movdf_softfloat32"
1427100a
DE		 8436 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8437 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7a2f7870 8438 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
52d3af72
DE		 8439 && (gpc_reg_operand (operands[0], DFmode)
8440 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8441 "*
8442{
8443 switch (which_alternative)
8444 {
a260abc9 8445 default:
37409796 8446 gcc_unreachable ();
dc4f83ca
MM		 8447 case 0:
8448 /* We normally copy the low-numbered register first. However, if
8449 the first register operand 0 is the same as the second register of
8450 operand 1, we must copy in the opposite order. */
8451 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8452 return \"mr %L0,%L1\;mr %0,%1\";
8453 else
8454 return \"mr %0,%1\;mr %L0,%L1\";
8455 case 1:
3cb999d8
DE		 8456 /* If the low-address word is used in the address, we must load
8457 it last. Otherwise, load it first. Note that we cannot have
8458 auto-increment in that case since the address register is
8459 known to be dead. */
dc4f83ca 8460 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8461 operands[1], 0))
dc4f83ca
MM		 8462 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8463 else
8464 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8465 case 2:
8466 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8467 case 3:
c4c40373
MM		 8468 case 4:
8469 case 5:
dc4f83ca
MM		 8470 return \"#\";
8471 }
8472}"
943c15ed 8473 [(set_attr "type" "two,load,store,*,*,*")
c4c40373 8474 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8475
44cd321e
PS		 8476; ld/std require word-aligned displacements -> 'Y' constraint.
8477; List Y->r and r->Y before r->r for reload.
8478(define_insn "*movdf_hardfloat64_mfpgpr"
8479 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8480 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8481 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8482 && (gpc_reg_operand (operands[0], DFmode)
8483 || gpc_reg_operand (operands[1], DFmode))"
8484 "@
8485 std%U0%X0 %1,%0
8486 ld%U1%X1 %0,%1
8487 mr %0,%1
8488 fmr %0,%1
8489 lfd%U1%X1 %0,%1
8490 stfd%U0%X0 %1,%0
8491 mt%0 %1
8492 mf%1 %0
8493 {cror 0,0,0|nop}
8494 #
8495 #
8496 #
8497 mftgpr %0,%1
8498 mffgpr %0,%1"
8499 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8500 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8501
d2288d5d
HP		 8502; ld/std require word-aligned displacements -> 'Y' constraint.
8503; List Y->r and r->Y before r->r for reload.
c4c40373 8504(define_insn "*movdf_hardfloat64"
fb3249ef 8505 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
ae6669e7 8506 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
44cd321e 8507 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8508 && (gpc_reg_operand (operands[0], DFmode)
8509 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8510 "@
96bb8ed3 8511 std%U0%X0 %1,%0
3364872d
FJ		 8512 ld%U1%X1 %0,%1
8513 mr %0,%1
3d5570cb 8514 fmr %0,%1
f63184ac 8515 lfd%U1%X1 %0,%1
914a7297
DE		 8516 stfd%U0%X0 %1,%0
8517 mt%0 %1
8518 mf%1 %0
e0740893 8519 {cror 0,0,0|nop}
914a7297
DE		 8520 #
8521 #
8522 #"
9c6fdb46 8523 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
ae6669e7 8524 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8525
c4c40373 8526(define_insn "*movdf_softfloat64"
d2288d5d
HP		 8527 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8528 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
a3170dc6 8529 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8530 && (gpc_reg_operand (operands[0], DFmode)
8531 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca 8532 "@
d2288d5d
HP		 8533 ld%U1%X1 %0,%1
8534 std%U0%X0 %1,%0
dc4f83ca 8535 mr %0,%1
914a7297
DE		 8536 mt%0 %1
8537 mf%1 %0
c4c40373
MM		 8538 #
8539 #
e2d0915c 8540 #
e0740893 8541 {cror 0,0,0|nop}"
9c6fdb46 8542 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
e2d0915c 8543 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 8544\f
06f4e019
DE		 8545(define_expand "movtf"
8546 [(set (match_operand:TF 0 "general_operand" "")
8547 (match_operand:TF 1 "any_operand" ""))]
8521c414 8548 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8549 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8550
a9baceb1
GK		 8551; It's important to list the o->f and f->o moves before f->f because
8552; otherwise reload, given m->f, will try to pick f->f and reload it,
409f61cd 8553; which doesn't make progress. Likewise r->Y must be before r->r.
a9baceb1 8554(define_insn_and_split "*movtf_internal"
409f61cd
AM		 8555 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8556 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
602ea4d3 8557 "!TARGET_IEEEQUAD
39e63627 8558 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8559 && (gpc_reg_operand (operands[0], TFmode)
8560 || gpc_reg_operand (operands[1], TFmode))"
a9baceb1 8561 "#"
ecb62ae7 8562 "&& reload_completed"
a9baceb1
GK		 8563 [(pc)]
8564{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
112ccb83 8565 [(set_attr "length" "8,8,8,20,20,16")])
06f4e019 8566
8521c414 8567(define_insn_and_split "*movtf_softfloat"
17caeff2 8568 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8521c414
JM		 8569 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8570 "!TARGET_IEEEQUAD
8571 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8572 && (gpc_reg_operand (operands[0], TFmode)
8573 || gpc_reg_operand (operands[1], TFmode))"
8574 "#"
8575 "&& reload_completed"
8576 [(pc)]
8577{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8578 [(set_attr "length" "20,20,16")])
8579
ecb62ae7 8580(define_expand "extenddftf2"
17caeff2
JM		 8581 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8582 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8583 "!TARGET_IEEEQUAD
8584 && TARGET_HARD_FLOAT
8585 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8586 && TARGET_LONG_DOUBLE_128"
8587{
8588 if (TARGET_E500_DOUBLE)
8589 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8590 else
8591 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8592 DONE;
8593})
8594
8595(define_expand "extenddftf2_fprs"
ecb62ae7
GK		 8596 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8597 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8598 (use (match_dup 2))])]
602ea4d3 8599 "!TARGET_IEEEQUAD
39e63627 8600 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8601{
ecb62ae7 8602 operands[2] = CONST0_RTX (DFmode);
aa9cf005
DE		 8603 /* Generate GOT reference early for SVR4 PIC. */
8604 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8605 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
ecb62ae7 8606})
06f4e019 8607
ecb62ae7
GK		 8608(define_insn_and_split "*extenddftf2_internal"
8609 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8610 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
97c54d9a 8611 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
602ea4d3 8612 "!TARGET_IEEEQUAD
39e63627 8613 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8614 "#"
8615 "&& reload_completed"
8616 [(pc)]
06f4e019 8617{
ecb62ae7
GK		 8618 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8619 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8620 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8621 operands[1]);
8622 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8623 operands[2]);
8624 DONE;
6ae08853 8625})
ecb62ae7
GK		 8626
8627(define_expand "extendsftf2"
8628 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8629 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
602ea4d3 8630 "!TARGET_IEEEQUAD
17caeff2
JM		 8631 && TARGET_HARD_FLOAT
8632 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8633 && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8634{
8635 rtx tmp = gen_reg_rtx (DFmode);
8636 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8637 emit_insn (gen_extenddftf2 (operands[0], tmp));
8638 DONE;
8639})
06f4e019 8640
8cb320b8 8641(define_expand "trunctfdf2"
589b3fda
DE		 8642 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8643 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8644 "!TARGET_IEEEQUAD
17caeff2
JM		 8645 && TARGET_HARD_FLOAT
8646 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8647 && TARGET_LONG_DOUBLE_128"
589b3fda 8648 "")
8cb320b8
DE		 8649
8650(define_insn_and_split "trunctfdf2_internal1"
8651 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8652 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
602ea4d3 8653 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8cb320b8
DE		 8654 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8655 "@
8656 #
8657 fmr %0,%1"
8658 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8659 [(const_int 0)]
8660{
8661 emit_note (NOTE_INSN_DELETED);
8662 DONE;
8663}
8664 [(set_attr "type" "fp")])
8665
8666(define_insn "trunctfdf2_internal2"
8667 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8668 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8669 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8cb320b8 8670 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8671 "fadd %0,%1,%L1"
8cb320b8 8672 [(set_attr "type" "fp")])
06f4e019 8673
17caeff2
JM		 8674(define_expand "trunctfsf2"
8675 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8676 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8677 "!TARGET_IEEEQUAD
8678 && TARGET_HARD_FLOAT
8679 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8680 && TARGET_LONG_DOUBLE_128"
8681{
8682 if (TARGET_E500_DOUBLE)
8683 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8684 else
8685 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8686 DONE;
8687})
8688
8689(define_insn_and_split "trunctfsf2_fprs"
06f4e019 8690 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 8691 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8692 (clobber (match_scratch:DF 2 "=f"))]
602ea4d3 8693 "!TARGET_IEEEQUAD
39e63627 8694 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8695 "#"
ea112fc4 8696 "&& reload_completed"
06f4e019
DE		 8697 [(set (match_dup 2)
8698 (float_truncate:DF (match_dup 1)))
8699 (set (match_dup 0)
8700 (float_truncate:SF (match_dup 2)))]
ea112fc4 8701 "")
06f4e019 8702
0c90aa3c 8703(define_expand "floatsitf2"
d29b7f64
DE		 8704 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8705 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
602ea4d3 8706 "!TARGET_IEEEQUAD
17caeff2
JM		 8707 && TARGET_HARD_FLOAT
8708 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8709 && TARGET_LONG_DOUBLE_128"
0c90aa3c
GK		 8710{
8711 rtx tmp = gen_reg_rtx (DFmode);
8712 expand_float (tmp, operands[1], false);
8713 emit_insn (gen_extenddftf2 (operands[0], tmp));
8714 DONE;
8715})
06f4e019 8716
ecb62ae7
GK		 8717; fadd, but rounding towards zero.
8718; This is probably not the optimal code sequence.
8719(define_insn "fix_trunc_helper"
8720 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8721 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8722 UNSPEC_FIX_TRUNC_TF))
8723 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8724 "TARGET_HARD_FLOAT && TARGET_FPRS"
8725 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8726 [(set_attr "type" "fp")
8727 (set_attr "length" "20")])
8728
0c90aa3c 8729(define_expand "fix_trunctfsi2"
17caeff2
JM		 8730 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8731 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8732 "!TARGET_IEEEQUAD
8733 && (TARGET_POWER2 || TARGET_POWERPC)
8734 && TARGET_HARD_FLOAT
8735 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8736 && TARGET_LONG_DOUBLE_128"
8737{
8738 if (TARGET_E500_DOUBLE)
8739 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8740 else
8741 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8742 DONE;
8743})
8744
8745(define_expand "fix_trunctfsi2_fprs"
ecb62ae7
GK		 8746 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8747 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8748 (clobber (match_dup 2))
8749 (clobber (match_dup 3))
8750 (clobber (match_dup 4))
8751 (clobber (match_dup 5))])]
602ea4d3 8752 "!TARGET_IEEEQUAD
ecb62ae7
GK		 8753 && (TARGET_POWER2 || TARGET_POWERPC)
8754 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8755{
8756 operands[2] = gen_reg_rtx (DFmode);
8757 operands[3] = gen_reg_rtx (DFmode);
8758 operands[4] = gen_reg_rtx (DImode);
8759 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8760})
8761
8762(define_insn_and_split "*fix_trunctfsi2_internal"
61c07d3c 8763 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
ecb62ae7
GK		 8764 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8765 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8766 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8767 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8768 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
602ea4d3 8769 "!TARGET_IEEEQUAD
39e63627 8770 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 8771 "#"
230215f5 8772 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
ecb62ae7 8773 [(pc)]
0c90aa3c 8774{
ecb62ae7
GK		 8775 rtx lowword;
8776 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8777
230215f5
GK		 8778 gcc_assert (MEM_P (operands[5]));
8779 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
ecb62ae7
GK		 8780
8781 emit_insn (gen_fctiwz (operands[4], operands[2]));
8782 emit_move_insn (operands[5], operands[4]);
230215f5 8783 emit_move_insn (operands[0], lowword);
0c90aa3c
GK		 8784 DONE;
8785})
06f4e019 8786
17caeff2
JM		 8787(define_expand "negtf2"
8788 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8789 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8790 "!TARGET_IEEEQUAD
8791 && TARGET_HARD_FLOAT
8792 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8793 && TARGET_LONG_DOUBLE_128"
8794 "")
8795
8796(define_insn "negtf2_internal"
06f4e019
DE		 8797 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8798 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8799 "!TARGET_IEEEQUAD
39e63627 8800 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8801 "*
8802{
8803 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8804 return \"fneg %L0,%L1\;fneg %0,%1\";
8805 else
8806 return \"fneg %0,%1\;fneg %L0,%L1\";
8807}"
8808 [(set_attr "type" "fp")
8809 (set_attr "length" "8")])
8810
1a402dc1 8811(define_expand "abstf2"
17caeff2
JM		 8812 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8813 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8814 "!TARGET_IEEEQUAD
17caeff2
JM		 8815 && TARGET_HARD_FLOAT
8816 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8817 && TARGET_LONG_DOUBLE_128"
1a402dc1 8818 "
06f4e019 8819{
1a402dc1 8820 rtx label = gen_label_rtx ();
17caeff2
JM		 8821 if (TARGET_E500_DOUBLE)
8822 {
8823 if (flag_unsafe_math_optimizations)
8824 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8825 else
8826 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8827 }
8828 else
8829 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
1a402dc1
AM		 8830 emit_label (label);
8831 DONE;
8832}")
06f4e019 8833
1a402dc1 8834(define_expand "abstf2_internal"
e42ac3de
RS		 8835 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8836 (match_operand:TF 1 "gpc_reg_operand" ""))
1a402dc1
AM		 8837 (set (match_dup 3) (match_dup 5))
8838 (set (match_dup 5) (abs:DF (match_dup 5)))
8839 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8840 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8841 (label_ref (match_operand 2 "" ""))
8842 (pc)))
8843 (set (match_dup 6) (neg:DF (match_dup 6)))]
602ea4d3 8844 "!TARGET_IEEEQUAD
39e63627 8845 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
1a402dc1 8846 "
06f4e019 8847{
1a402dc1
AM		 8848 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8849 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8850 operands[3] = gen_reg_rtx (DFmode);
8851 operands[4] = gen_reg_rtx (CCFPmode);
8852 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8853 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8854}")
06f4e019 8855\f
1fd4e8c1
RK		 8856;; Next come the multi-word integer load and store and the load and store
8857;; multiple insns.
1fd4e8c1 8858
112ccb83
GK		 8859; List r->r after r->"o<>", otherwise reload will try to reload a
8860; non-offsettable address by using r->r which won't make progress.
acad7ed3 8861(define_insn "*movdi_internal32"
17caeff2 8862 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
112ccb83 8863 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
a260abc9 8864 "! TARGET_POWERPC64
4e74d8ec
MM		 8865 && (gpc_reg_operand (operands[0], DImode)
8866 || gpc_reg_operand (operands[1], DImode))"
112ccb83
GK		 8867 "@
8868 #
8869 #
8870 #
8871 fmr %0,%1
8872 lfd%U1%X1 %0,%1
8873 stfd%U0%X0 %1,%0
8874 #"
8875 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
4e74d8ec
MM		 8876
8877(define_split
8878 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8879 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 8880 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8881 [(set (match_dup 2) (match_dup 4))
8882 (set (match_dup 3) (match_dup 1))]
8883 "
8884{
5f59ecb7 8885 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 8886 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8887 DImode);
8888 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8889 DImode);
75d39459 8890#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 8891 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 8892#else
5f59ecb7 8893 operands[4] = GEN_INT (value >> 32);
a65c591c 8894 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 8895#endif
4e74d8ec
MM		 8896}")
8897
3a1f863f 8898(define_split
17caeff2 8899 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
3a1f863f 8900 (match_operand:DI 1 "input_operand" ""))]
6ae08853 8901 "reload_completed && !TARGET_POWERPC64
3a1f863f 8902 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 8903 [(pc)]
8904{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
3a1f863f 8905
44cd321e
PS		 8906(define_insn "*movdi_mfpgpr"
8907 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8908 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8909 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8910 && (gpc_reg_operand (operands[0], DImode)
8911 || gpc_reg_operand (operands[1], DImode))"
8912 "@
8913 mr %0,%1
8914 ld%U1%X1 %0,%1
8915 std%U0%X0 %1,%0
8916 li %0,%1
8917 lis %0,%v1
8918 #
8919 {cal|la} %0,%a1
8920 fmr %0,%1
8921 lfd%U1%X1 %0,%1
8922 stfd%U0%X0 %1,%0
8923 mf%1 %0
8924 mt%0 %1
8925 {cror 0,0,0|nop}
8926 mftgpr %0,%1
8927 mffgpr %0,%1"
8928 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8929 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8930
acad7ed3 8931(define_insn "*movdi_internal64"
343f6bbf 8932 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9615f239 8933 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
44cd321e 8934 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
4e74d8ec
MM		 8935 && (gpc_reg_operand (operands[0], DImode)
8936 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 8937 "@
3d5570cb
RK		 8938 mr %0,%1
8939 ld%U1%X1 %0,%1
96bb8ed3 8940 std%U0%X0 %1,%0
3d5570cb 8941 li %0,%1
802a0058 8942 lis %0,%v1
e6ca2c17 8943 #
aee86b38 8944 {cal|la} %0,%a1
3d5570cb
RK		 8945 fmr %0,%1
8946 lfd%U1%X1 %0,%1
8947 stfd%U0%X0 %1,%0
8948 mf%1 %0
08075ead 8949 mt%0 %1
e34eaae5 8950 {cror 0,0,0|nop}"
02ca7595 8951 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 8952 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8953
5f59ecb7 8954;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 8955(define_insn ""
8956 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8957 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 8958 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8959 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 8960 && num_insns_constant (operands[1], DImode) == 1"
8961 "*
8962{
8963 return ((unsigned HOST_WIDE_INT)
8964 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8965 ? \"li %0,%1\" : \"lis %0,%v1\";
8966}")
8967
a260abc9
DE		 8968;; Generate all one-bits and clear left or right.
8969;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8970(define_split
8971 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1990cd79 8972 (match_operand:DI 1 "mask64_operand" ""))]
a260abc9
DE		 8973 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8974 [(set (match_dup 0) (const_int -1))
e6ca2c17 8975 (set (match_dup 0)
a260abc9
DE		 8976 (and:DI (rotate:DI (match_dup 0)
8977 (const_int 0))
8978 (match_dup 1)))]
8979 "")
8980
8981;; Split a load of a large constant into the appropriate five-instruction
8982;; sequence. Handle anything in a constant number of insns.
8983;; When non-easy constants can go in the TOC, this should use
8984;; easy_fp_constant predicate.
8985(define_split
8986 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 8987 (match_operand:DI 1 "const_int_operand" ""))]
8988 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8989 [(set (match_dup 0) (match_dup 2))
8990 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 8991 "
2bfcf297
DB		 8992{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8993
8994 if (tem == operands[0])
8995 DONE;
e8d791dd 8996 else
2bfcf297 8997 FAIL;
5f59ecb7 8998}")
e6ca2c17 8999
5f59ecb7
DE		 9000(define_split
9001 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9002 (match_operand:DI 1 "const_double_operand" ""))]
9003 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9004 [(set (match_dup 0) (match_dup 2))
9005 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 9006 "
2bfcf297
DB		 9007{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9008
9009 if (tem == operands[0])
9010 DONE;
9011 else
9012 FAIL;
e6ca2c17 9013}")
acad7ed3 9014\f
1fd4e8c1
RK		 9015;; TImode is similar, except that we usually want to compute the address into
9016;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 9017;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 9018
9019;; We say that MQ is clobbered in the last alternative because the first
9020;; alternative would never get used otherwise since it would need a reload
9021;; while the 2nd alternative would not. We put memory cases first so they
9022;; are preferred. Otherwise, we'd try to reload the output instead of
9023;; giving the SCRATCH mq.
3a1f863f 9024
a260abc9 9025(define_insn "*movti_power"
7f514158
AM		 9026 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9027 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9028 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
6ae08853 9029 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 9030 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 9031 "*
9032{
9033 switch (which_alternative)
9034 {
dc4f83ca 9035 default:
37409796 9036 gcc_unreachable ();
dc4f83ca 9037
1fd4e8c1 9038 case 0:
3a1f863f
DE		 9039 if (TARGET_STRING)
9040 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 9041 case 1:
1fd4e8c1 9042 case 2:
3a1f863f 9043 return \"#\";
1fd4e8c1
RK		 9044 case 3:
9045 /* If the address is not used in the output, we can use lsi. Otherwise,
9046 fall through to generating four loads. */
e876481c
DE		 9047 if (TARGET_STRING
9048 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 9049 return \"{lsi|lswi} %0,%P1,16\";
82e41834 9050 /* ... fall through ... */
1fd4e8c1 9051 case 4:
7f514158 9052 case 5:
3a1f863f 9053 return \"#\";
1fd4e8c1
RK		 9054 }
9055}"
7f514158 9056 [(set_attr "type" "store,store,*,load,load,*")])
51b8fc2c 9057
a260abc9 9058(define_insn "*movti_string"
7f514158
AM		 9059 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9060 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
3a1f863f 9061 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 9062 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9063 "*
9064{
9065 switch (which_alternative)
9066 {
9067 default:
37409796 9068 gcc_unreachable ();
dc4f83ca 9069 case 0:
3a1f863f
DE		 9070 if (TARGET_STRING)
9071 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 9072 case 1:
cd1d3445 9073 case 2:
3a1f863f 9074 return \"#\";
cd1d3445
DE		 9075 case 3:
9076 /* If the address is not used in the output, we can use lsi. Otherwise,
9077 fall through to generating four loads. */
6ae08853 9078 if (TARGET_STRING
3a1f863f 9079 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 9080 return \"{lsi|lswi} %0,%P1,16\";
9081 /* ... fall through ... */
9082 case 4:
7f514158 9083 case 5:
3a1f863f 9084 return \"#\";
dc4f83ca
MM		 9085 }
9086}"
9c6fdb46 9087 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
dc4f83ca 9088
a260abc9 9089(define_insn "*movti_ppc64"
112ccb83
GK		 9090 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9091 (match_operand:TI 1 "input_operand" "r,r,m"))]
51b8fc2c
RK		 9092 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9093 || gpc_reg_operand (operands[1], TImode))"
112ccb83 9094 "#"
3a1f863f
DE		 9095 [(set_attr "type" "*,load,store")])
9096
7f514158
AM		 9097(define_split
9098 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9099 (match_operand:TI 1 "const_double_operand" ""))]
9100 "TARGET_POWERPC64"
9101 [(set (match_dup 2) (match_dup 4))
9102 (set (match_dup 3) (match_dup 5))]
9103 "
9104{
9105 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9106 TImode);
9107 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9108 TImode);
9109 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9110 {
9111 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9112 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9113 }
9114 else if (GET_CODE (operands[1]) == CONST_INT)
9115 {
9116 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9117 operands[5] = operands[1];
9118 }
9119 else
9120 FAIL;
9121}")
9122
3a1f863f
DE		 9123(define_split
9124 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9125 (match_operand:TI 1 "input_operand" ""))]
a9baceb1 9126 "reload_completed
3a1f863f 9127 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 9128 [(pc)]
9129{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
1fd4e8c1
RK		 9130\f
9131(define_expand "load_multiple"
2f622005
RK		 9132 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9133 (match_operand:SI 1 "" ""))
9134 (use (match_operand:SI 2 "" ""))])]
09a625f7 9135 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9136 "
9137{
9138 int regno;
9139 int count;
792760b9 9140 rtx op1;
1fd4e8c1
RK		 9141 int i;
9142
9143 /* Support only loading a constant number of fixed-point registers from
9144 memory and only bother with this if more than two; the machine
9145 doesn't support more than eight. */
9146 if (GET_CODE (operands[2]) != CONST_INT
9147 || INTVAL (operands[2]) <= 2
9148 || INTVAL (operands[2]) > 8
9149 || GET_CODE (operands[1]) != MEM
9150 || GET_CODE (operands[0]) != REG
9151 || REGNO (operands[0]) >= 32)
9152 FAIL;
9153
9154 count = INTVAL (operands[2]);
9155 regno = REGNO (operands[0]);
9156
39403d82 9157 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 9158 op1 = replace_equiv_address (operands[1],
9159 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 9160
9161 for (i = 0; i < count; i++)
9162 XVECEXP (operands[3], 0, i)
39403d82 9163 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 9164 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 9165}")
9166
9caa3eb2 9167(define_insn "*ldmsi8"
1fd4e8c1 9168 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 9169 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9170 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9171 (set (match_operand:SI 3 "gpc_reg_operand" "")
9172 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9173 (set (match_operand:SI 4 "gpc_reg_operand" "")
9174 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9175 (set (match_operand:SI 5 "gpc_reg_operand" "")
9176 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9177 (set (match_operand:SI 6 "gpc_reg_operand" "")
9178 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9179 (set (match_operand:SI 7 "gpc_reg_operand" "")
9180 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9181 (set (match_operand:SI 8 "gpc_reg_operand" "")
9182 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9183 (set (match_operand:SI 9 "gpc_reg_operand" "")
9184 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9185 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 9186 "*
9caa3eb2 9187{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9188 [(set_attr "type" "load_ux")
9caa3eb2 9189 (set_attr "length" "32")])
1fd4e8c1 9190
9caa3eb2
DE		 9191(define_insn "*ldmsi7"
9192 [(match_parallel 0 "load_multiple_operation"
9193 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9194 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9195 (set (match_operand:SI 3 "gpc_reg_operand" "")
9196 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9197 (set (match_operand:SI 4 "gpc_reg_operand" "")
9198 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9199 (set (match_operand:SI 5 "gpc_reg_operand" "")
9200 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9201 (set (match_operand:SI 6 "gpc_reg_operand" "")
9202 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9203 (set (match_operand:SI 7 "gpc_reg_operand" "")
9204 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9205 (set (match_operand:SI 8 "gpc_reg_operand" "")
9206 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9207 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9208 "*
9209{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9210 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9211 (set_attr "length" "32")])
9212
9213(define_insn "*ldmsi6"
9214 [(match_parallel 0 "load_multiple_operation"
9215 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9216 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9217 (set (match_operand:SI 3 "gpc_reg_operand" "")
9218 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9219 (set (match_operand:SI 4 "gpc_reg_operand" "")
9220 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9221 (set (match_operand:SI 5 "gpc_reg_operand" "")
9222 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9223 (set (match_operand:SI 6 "gpc_reg_operand" "")
9224 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9225 (set (match_operand:SI 7 "gpc_reg_operand" "")
9226 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9227 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9228 "*
9229{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9230 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9231 (set_attr "length" "32")])
9232
9233(define_insn "*ldmsi5"
9234 [(match_parallel 0 "load_multiple_operation"
9235 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9236 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9237 (set (match_operand:SI 3 "gpc_reg_operand" "")
9238 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9239 (set (match_operand:SI 4 "gpc_reg_operand" "")
9240 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9241 (set (match_operand:SI 5 "gpc_reg_operand" "")
9242 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9243 (set (match_operand:SI 6 "gpc_reg_operand" "")
9244 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9245 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9246 "*
9247{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9248 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9249 (set_attr "length" "32")])
9250
9251(define_insn "*ldmsi4"
9252 [(match_parallel 0 "load_multiple_operation"
9253 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9254 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9255 (set (match_operand:SI 3 "gpc_reg_operand" "")
9256 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9257 (set (match_operand:SI 4 "gpc_reg_operand" "")
9258 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9259 (set (match_operand:SI 5 "gpc_reg_operand" "")
9260 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9261 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9262 "*
9263{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9264 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9265 (set_attr "length" "32")])
9266
9267(define_insn "*ldmsi3"
9268 [(match_parallel 0 "load_multiple_operation"
9269 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9270 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9271 (set (match_operand:SI 3 "gpc_reg_operand" "")
9272 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9273 (set (match_operand:SI 4 "gpc_reg_operand" "")
9274 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9275 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9276 "*
9277{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9278 [(set_attr "type" "load_ux")
e82ee4cc 9279 (set_attr "length" "32")])
b19003d8 9280
1fd4e8c1 9281(define_expand "store_multiple"
2f622005
RK		 9282 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9283 (match_operand:SI 1 "" ""))
9284 (clobber (scratch:SI))
9285 (use (match_operand:SI 2 "" ""))])]
09a625f7 9286 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9287 "
9288{
9289 int regno;
9290 int count;
9291 rtx to;
792760b9 9292 rtx op0;
1fd4e8c1
RK		 9293 int i;
9294
9295 /* Support only storing a constant number of fixed-point registers to
9296 memory and only bother with this if more than two; the machine
9297 doesn't support more than eight. */
9298 if (GET_CODE (operands[2]) != CONST_INT
9299 || INTVAL (operands[2]) <= 2
9300 || INTVAL (operands[2]) > 8
9301 || GET_CODE (operands[0]) != MEM
9302 || GET_CODE (operands[1]) != REG
9303 || REGNO (operands[1]) >= 32)
9304 FAIL;
9305
9306 count = INTVAL (operands[2]);
9307 regno = REGNO (operands[1]);
9308
39403d82 9309 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 9310 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 9311 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 9312
9313 XVECEXP (operands[3], 0, 0)
7ef788f0 9314 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 9315 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 9316 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 9317
9318 for (i = 1; i < count; i++)
9319 XVECEXP (operands[3], 0, i + 1)
39403d82 9320 = gen_rtx_SET (VOIDmode,
7ef788f0 9321 adjust_address_nv (op0, SImode, i * 4),
c5c76735 9322 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 9323}")
9324
e46e3130 9325(define_insn "*stmsi8"
d14a6d05 9326 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 9327 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9328 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9329 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9330 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9331 (match_operand:SI 4 "gpc_reg_operand" "r"))
9332 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9333 (match_operand:SI 5 "gpc_reg_operand" "r"))
9334 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9335 (match_operand:SI 6 "gpc_reg_operand" "r"))
9336 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9337 (match_operand:SI 7 "gpc_reg_operand" "r"))
9338 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9339 (match_operand:SI 8 "gpc_reg_operand" "r"))
9340 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9341 (match_operand:SI 9 "gpc_reg_operand" "r"))
9342 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9343 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9344 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9345 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9346 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9347
9348(define_insn "*stmsi7"
9349 [(match_parallel 0 "store_multiple_operation"
9350 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9351 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9352 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9353 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9354 (match_operand:SI 4 "gpc_reg_operand" "r"))
9355 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9356 (match_operand:SI 5 "gpc_reg_operand" "r"))
9357 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9358 (match_operand:SI 6 "gpc_reg_operand" "r"))
9359 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9360 (match_operand:SI 7 "gpc_reg_operand" "r"))
9361 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9362 (match_operand:SI 8 "gpc_reg_operand" "r"))
9363 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9364 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9365 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9366 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9367 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9368
9369(define_insn "*stmsi6"
9370 [(match_parallel 0 "store_multiple_operation"
9371 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9372 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9373 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9374 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9375 (match_operand:SI 4 "gpc_reg_operand" "r"))
9376 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9377 (match_operand:SI 5 "gpc_reg_operand" "r"))
9378 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9379 (match_operand:SI 6 "gpc_reg_operand" "r"))
9380 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9381 (match_operand:SI 7 "gpc_reg_operand" "r"))
9382 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9383 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9384 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9385 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9386 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9387
9388(define_insn "*stmsi5"
9389 [(match_parallel 0 "store_multiple_operation"
9390 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9391 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9392 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9393 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9394 (match_operand:SI 4 "gpc_reg_operand" "r"))
9395 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9396 (match_operand:SI 5 "gpc_reg_operand" "r"))
9397 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9398 (match_operand:SI 6 "gpc_reg_operand" "r"))
9399 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9400 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9401 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9402 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9403 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9404
9405(define_insn "*stmsi4"
9406 [(match_parallel 0 "store_multiple_operation"
9407 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9408 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9409 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9410 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9411 (match_operand:SI 4 "gpc_reg_operand" "r"))
9412 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9413 (match_operand:SI 5 "gpc_reg_operand" "r"))
9414 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9415 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9416 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82 9417 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9418 [(set_attr "type" "store_ux")])
7e69e155 9419
e46e3130
DJ		 9420(define_insn "*stmsi3"
9421 [(match_parallel 0 "store_multiple_operation"
9422 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9423 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9424 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9425 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9426 (match_operand:SI 4 "gpc_reg_operand" "r"))
9427 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9428 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9429 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9430 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9431 [(set_attr "type" "store_ux")])
d2894ab5
DE		 9432
9433(define_insn "*stmsi8_power"
9434 [(match_parallel 0 "store_multiple_operation"
9435 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9436 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9437 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9438 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9439 (match_operand:SI 4 "gpc_reg_operand" "r"))
9440 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9441 (match_operand:SI 5 "gpc_reg_operand" "r"))
9442 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9443 (match_operand:SI 6 "gpc_reg_operand" "r"))
9444 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9445 (match_operand:SI 7 "gpc_reg_operand" "r"))
9446 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9447 (match_operand:SI 8 "gpc_reg_operand" "r"))
9448 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9449 (match_operand:SI 9 "gpc_reg_operand" "r"))
9450 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9451 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9452 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9453 "{stsi|stswi} %2,%1,%O0"
9454 [(set_attr "type" "store_ux")])
9455
9456(define_insn "*stmsi7_power"
9457 [(match_parallel 0 "store_multiple_operation"
9458 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9459 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9460 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9461 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9462 (match_operand:SI 4 "gpc_reg_operand" "r"))
9463 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9464 (match_operand:SI 5 "gpc_reg_operand" "r"))
9465 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9466 (match_operand:SI 6 "gpc_reg_operand" "r"))
9467 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9468 (match_operand:SI 7 "gpc_reg_operand" "r"))
9469 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9470 (match_operand:SI 8 "gpc_reg_operand" "r"))
9471 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9472 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9473 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9474 "{stsi|stswi} %2,%1,%O0"
9475 [(set_attr "type" "store_ux")])
9476
9477(define_insn "*stmsi6_power"
9478 [(match_parallel 0 "store_multiple_operation"
9479 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9480 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9481 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9482 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9483 (match_operand:SI 4 "gpc_reg_operand" "r"))
9484 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9485 (match_operand:SI 5 "gpc_reg_operand" "r"))
9486 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9487 (match_operand:SI 6 "gpc_reg_operand" "r"))
9488 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9489 (match_operand:SI 7 "gpc_reg_operand" "r"))
9490 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9491 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9492 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9493 "{stsi|stswi} %2,%1,%O0"
9494 [(set_attr "type" "store_ux")])
9495
9496(define_insn "*stmsi5_power"
9497 [(match_parallel 0 "store_multiple_operation"
9498 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9499 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9500 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9501 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9502 (match_operand:SI 4 "gpc_reg_operand" "r"))
9503 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9504 (match_operand:SI 5 "gpc_reg_operand" "r"))
9505 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9506 (match_operand:SI 6 "gpc_reg_operand" "r"))
9507 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9508 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9509 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9510 "{stsi|stswi} %2,%1,%O0"
9511 [(set_attr "type" "store_ux")])
9512
9513(define_insn "*stmsi4_power"
9514 [(match_parallel 0 "store_multiple_operation"
9515 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9516 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9517 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9518 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9519 (match_operand:SI 4 "gpc_reg_operand" "r"))
9520 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9521 (match_operand:SI 5 "gpc_reg_operand" "r"))
9522 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9523 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9524 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9525 "{stsi|stswi} %2,%1,%O0"
9526 [(set_attr "type" "store_ux")])
9527
9528(define_insn "*stmsi3_power"
9529 [(match_parallel 0 "store_multiple_operation"
9530 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9531 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9532 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9533 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9534 (match_operand:SI 4 "gpc_reg_operand" "r"))
9535 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9536 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9537 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9538 "{stsi|stswi} %2,%1,%O0"
9539 [(set_attr "type" "store_ux")])
7e69e155 9540\f
57e84f18 9541(define_expand "setmemsi"
fba73eb1 9542 [(parallel [(set (match_operand:BLK 0 "" "")
98843c92 9543 (match_operand 2 "const_int_operand" ""))
fba73eb1 9544 (use (match_operand:SI 1 "" ""))
57e84f18 9545 (use (match_operand:SI 3 "" ""))])]
fba73eb1
DE		 9546 ""
9547 "
9548{
57e84f18 9549 /* If value to set is not zero, use the library routine. */
a05be2e0 9550 if (operands[2] != const0_rtx)
57e84f18
AS		 9551 FAIL;
9552
fba73eb1
DE		 9553 if (expand_block_clear (operands))
9554 DONE;
9555 else
9556 FAIL;
9557}")
9558
7e69e155
MM		 9559;; String/block move insn.
9560;; Argument 0 is the destination
9561;; Argument 1 is the source
9562;; Argument 2 is the length
9563;; Argument 3 is the alignment
9564
70128ad9 9565(define_expand "movmemsi"
b6c9286a
MM		 9566 [(parallel [(set (match_operand:BLK 0 "" "")
9567 (match_operand:BLK 1 "" ""))
9568 (use (match_operand:SI 2 "" ""))
9569 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9570 ""
9571 "
9572{
9573 if (expand_block_move (operands))
9574 DONE;
9575 else
9576 FAIL;
9577}")
9578
9579;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9580;; register allocator doesn't have a clue about allocating 8 word registers.
9581;; rD/rS = r5 is preferred, efficient form.
70128ad9 9582(define_expand "movmemsi_8reg"
b6c9286a
MM		 9583 [(parallel [(set (match_operand 0 "" "")
9584 (match_operand 1 "" ""))
9585 (use (match_operand 2 "" ""))
9586 (use (match_operand 3 "" ""))
7e69e155
MM		 9587 (clobber (reg:SI 5))
9588 (clobber (reg:SI 6))
9589 (clobber (reg:SI 7))
9590 (clobber (reg:SI 8))
9591 (clobber (reg:SI 9))
9592 (clobber (reg:SI 10))
9593 (clobber (reg:SI 11))
9594 (clobber (reg:SI 12))
3c67b673 9595 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9596 "TARGET_STRING"
9597 "")
9598
9599(define_insn ""
52d3af72
DE		 9600 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9601 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9602 (use (match_operand:SI 2 "immediate_operand" "i"))
9603 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9604 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9605 (clobber (reg:SI 6))
9606 (clobber (reg:SI 7))
9607 (clobber (reg:SI 8))
9608 (clobber (reg:SI 9))
9609 (clobber (reg:SI 10))
9610 (clobber (reg:SI 11))
9611 (clobber (reg:SI 12))
3c67b673 9612 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9613 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9614 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9615 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9616 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9617 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9618 && REGNO (operands[4]) == 5"
9619 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9620 [(set_attr "type" "store_ux")
b7ff3d82 9621 (set_attr "length" "8")])
7e69e155
MM		 9622
9623(define_insn ""
4ae234b0
GK		 9624 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9625 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9626 (use (match_operand:SI 2 "immediate_operand" "i"))
9627 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9628 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9629 (clobber (reg:SI 6))
9630 (clobber (reg:SI 7))
9631 (clobber (reg:SI 8))
9632 (clobber (reg:SI 9))
9633 (clobber (reg:SI 10))
9634 (clobber (reg:SI 11))
9635 (clobber (reg:SI 12))
edd54d25 9636 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9637 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9638 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9639 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9640 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9641 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9642 && REGNO (operands[4]) == 5"
9643 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9644 [(set_attr "type" "store_ux")
b7ff3d82 9645 (set_attr "length" "8")])
7e69e155
MM		 9646
9647;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9648;; register allocator doesn't have a clue about allocating 6 word registers.
9649;; rD/rS = r5 is preferred, efficient form.
70128ad9 9650(define_expand "movmemsi_6reg"
b6c9286a
MM		 9651 [(parallel [(set (match_operand 0 "" "")
9652 (match_operand 1 "" ""))
9653 (use (match_operand 2 "" ""))
9654 (use (match_operand 3 "" ""))
f9562f27
DE		 9655 (clobber (reg:SI 5))
9656 (clobber (reg:SI 6))
7e69e155
MM		 9657 (clobber (reg:SI 7))
9658 (clobber (reg:SI 8))
9659 (clobber (reg:SI 9))
9660 (clobber (reg:SI 10))
3c67b673 9661 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9662 "TARGET_STRING"
9663 "")
9664
9665(define_insn ""
52d3af72
DE		 9666 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9667 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9668 (use (match_operand:SI 2 "immediate_operand" "i"))
9669 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9670 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9671 (clobber (reg:SI 6))
9672 (clobber (reg:SI 7))
7e69e155
MM		 9673 (clobber (reg:SI 8))
9674 (clobber (reg:SI 9))
9675 (clobber (reg:SI 10))
3c67b673 9676 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9677 "TARGET_STRING && TARGET_POWER
9678 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9679 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9680 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9681 && REGNO (operands[4]) == 5"
3c67b673 9682 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9683 [(set_attr "type" "store_ux")
b7ff3d82 9684 (set_attr "length" "8")])
7e69e155
MM		 9685
9686(define_insn ""
4ae234b0
GK		 9687 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9688 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9689 (use (match_operand:SI 2 "immediate_operand" "i"))
9690 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9691 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9692 (clobber (reg:SI 6))
9693 (clobber (reg:SI 7))
7e69e155
MM		 9694 (clobber (reg:SI 8))
9695 (clobber (reg:SI 9))
9696 (clobber (reg:SI 10))
edd54d25 9697 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9698 "TARGET_STRING && ! TARGET_POWER
7e69e155 9699 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9700 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9701 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9702 && REGNO (operands[4]) == 5"
3c67b673 9703 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9704 [(set_attr "type" "store_ux")
b7ff3d82 9705 (set_attr "length" "8")])
7e69e155 9706
f9562f27
DE		 9707;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9708;; problems with TImode.
9709;; rD/rS = r5 is preferred, efficient form.
70128ad9 9710(define_expand "movmemsi_4reg"
b6c9286a
MM		 9711 [(parallel [(set (match_operand 0 "" "")
9712 (match_operand 1 "" ""))
9713 (use (match_operand 2 "" ""))
9714 (use (match_operand 3 "" ""))
f9562f27
DE		 9715 (clobber (reg:SI 5))
9716 (clobber (reg:SI 6))
9717 (clobber (reg:SI 7))
9718 (clobber (reg:SI 8))
3c67b673 9719 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9720 "TARGET_STRING"
9721 "")
9722
9723(define_insn ""
52d3af72
DE		 9724 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9725 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9726 (use (match_operand:SI 2 "immediate_operand" "i"))
9727 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9728 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9729 (clobber (reg:SI 6))
9730 (clobber (reg:SI 7))
9731 (clobber (reg:SI 8))
3c67b673 9732 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9733 "TARGET_STRING && TARGET_POWER
9734 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9735 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9736 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9737 && REGNO (operands[4]) == 5"
3c67b673 9738 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9739 [(set_attr "type" "store_ux")
b7ff3d82 9740 (set_attr "length" "8")])
7e69e155
MM		 9741
9742(define_insn ""
4ae234b0
GK		 9743 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9744 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9745 (use (match_operand:SI 2 "immediate_operand" "i"))
9746 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9747 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9748 (clobber (reg:SI 6))
9749 (clobber (reg:SI 7))
9750 (clobber (reg:SI 8))
edd54d25 9751 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9752 "TARGET_STRING && ! TARGET_POWER
7e69e155 9753 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9754 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9755 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9756 && REGNO (operands[4]) == 5"
3c67b673 9757 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9758 [(set_attr "type" "store_ux")
b7ff3d82 9759 (set_attr "length" "8")])
7e69e155
MM		 9760
9761;; Move up to 8 bytes at a time.
70128ad9 9762(define_expand "movmemsi_2reg"
b6c9286a
MM		 9763 [(parallel [(set (match_operand 0 "" "")
9764 (match_operand 1 "" ""))
9765 (use (match_operand 2 "" ""))
9766 (use (match_operand 3 "" ""))
3c67b673
RK		 9767 (clobber (match_scratch:DI 4 ""))
9768 (clobber (match_scratch:SI 5 ""))])]
f9562f27 9769 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 9770 "")
9771
9772(define_insn ""
52d3af72
DE		 9773 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9774 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9775 (use (match_operand:SI 2 "immediate_operand" "i"))
9776 (use (match_operand:SI 3 "immediate_operand" "i"))
9777 (clobber (match_scratch:DI 4 "=&r"))
9778 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 9779 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 9780 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9781 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9782 [(set_attr "type" "store_ux")
b7ff3d82 9783 (set_attr "length" "8")])
7e69e155
MM		 9784
9785(define_insn ""
52d3af72
DE		 9786 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9787 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9788 (use (match_operand:SI 2 "immediate_operand" "i"))
9789 (use (match_operand:SI 3 "immediate_operand" "i"))
9790 (clobber (match_scratch:DI 4 "=&r"))
edd54d25 9791 (clobber (match_scratch:SI 5 "=X"))]
f9562f27 9792 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 9793 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 9794 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9795 [(set_attr "type" "store_ux")
b7ff3d82 9796 (set_attr "length" "8")])
7e69e155
MM		 9797
9798;; Move up to 4 bytes at a time.
70128ad9 9799(define_expand "movmemsi_1reg"
b6c9286a
MM		 9800 [(parallel [(set (match_operand 0 "" "")
9801 (match_operand 1 "" ""))
9802 (use (match_operand 2 "" ""))
9803 (use (match_operand 3 "" ""))
3c67b673
RK		 9804 (clobber (match_scratch:SI 4 ""))
9805 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 9806 "TARGET_STRING"
9807 "")
9808
9809(define_insn ""
52d3af72
DE		 9810 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9811 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9812 (use (match_operand:SI 2 "immediate_operand" "i"))
9813 (use (match_operand:SI 3 "immediate_operand" "i"))
9814 (clobber (match_scratch:SI 4 "=&r"))
9815 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9816 "TARGET_STRING && TARGET_POWER
9817 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9818 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9819 [(set_attr "type" "store_ux")
b7ff3d82 9820 (set_attr "length" "8")])
7e69e155
MM		 9821
9822(define_insn ""
4ae234b0
GK		 9823 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9824 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9825 (use (match_operand:SI 2 "immediate_operand" "i"))
9826 (use (match_operand:SI 3 "immediate_operand" "i"))
9827 (clobber (match_scratch:SI 4 "=&r"))
edd54d25 9828 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9829 "TARGET_STRING && ! TARGET_POWER
7e69e155 9830 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7 9831 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9832 [(set_attr "type" "store_ux")
09a625f7 9833 (set_attr "length" "8")])
1fd4e8c1 9834\f
7e69e155 9835;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 9836;; get by using pre-decrement or pre-increment, but the hardware can also
9837;; do cases where the increment is not the size of the object.
9838;;
9839;; In all these cases, we use operands 0 and 1 for the register being
9840;; incremented because those are the operands that local-alloc will
9841;; tie and these are the pair most likely to be tieable (and the ones
9842;; that will benefit the most).
9843
38c1f2d7 9844(define_insn "*movdi_update1"
51b8fc2c 9845 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 9846 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9847 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 9848 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9849 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9850 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9851 "@
9852 ldux %3,%0,%2
9853 ldu %3,%2(%0)"
b54cf83a 9854 [(set_attr "type" "load_ux,load_u")])
287f13ff 9855
2e6c9641
FJ		 9856(define_insn "movdi_<mode>_update"
9857 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9858 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c 9859 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
2e6c9641
FJ		 9860 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9861 (plus:P (match_dup 1) (match_dup 2)))]
38c1f2d7 9862 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9863 "@
9864 stdux %3,%0,%2
b7ff3d82 9865 stdu %3,%2(%0)"
b54cf83a 9866 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 9867
38c1f2d7 9868(define_insn "*movsi_update1"
cd2b37d9
RK		 9869 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9870 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9871 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9872 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9873 (plus:SI (match_dup 1) (match_dup 2)))]
f7b3ab8a 9874 "TARGET_UPDATE"
1fd4e8c1 9875 "@
ca7f5001
RK		 9876 {lux|lwzux} %3,%0,%2
9877 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 9878 [(set_attr "type" "load_ux,load_u")])
9879
9880(define_insn "*movsi_update2"
9881 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9882 (sign_extend:DI
9883 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9884 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9885 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9886 (plus:DI (match_dup 1) (match_dup 2)))]
9887 "TARGET_POWERPC64"
9888 "lwaux %3,%0,%2"
9889 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 9890
4697a36c 9891(define_insn "movsi_update"
cd2b37d9 9892 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9893 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9894 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9895 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9896 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9897 "TARGET_UPDATE"
1fd4e8c1 9898 "@
ca7f5001 9899 {stux|stwux} %3,%0,%2
b7ff3d82 9900 {stu|stwu} %3,%2(%0)"
b54cf83a 9901 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9902
b54cf83a 9903(define_insn "*movhi_update1"
cd2b37d9
RK		 9904 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9905 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9906 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9907 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9908 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9909 "TARGET_UPDATE"
1fd4e8c1 9910 "@
5f243543
RK		 9911 lhzux %3,%0,%2
9912 lhzu %3,%2(%0)"
b54cf83a 9913 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9914
38c1f2d7 9915(define_insn "*movhi_update2"
cd2b37d9 9916 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9917 (zero_extend:SI
cd2b37d9 9918 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9919 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9920 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9921 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9922 "TARGET_UPDATE"
1fd4e8c1 9923 "@
5f243543
RK		 9924 lhzux %3,%0,%2
9925 lhzu %3,%2(%0)"
b54cf83a 9926 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9927
38c1f2d7 9928(define_insn "*movhi_update3"
cd2b37d9 9929 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9930 (sign_extend:SI
cd2b37d9 9931 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9932 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9933 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9934 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9935 "TARGET_UPDATE"
1fd4e8c1 9936 "@
5f243543
RK		 9937 lhaux %3,%0,%2
9938 lhau %3,%2(%0)"
b54cf83a 9939 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 9940
38c1f2d7 9941(define_insn "*movhi_update4"
cd2b37d9 9942 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9943 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9944 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9945 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9946 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9947 "TARGET_UPDATE"
1fd4e8c1 9948 "@
5f243543 9949 sthux %3,%0,%2
b7ff3d82 9950 sthu %3,%2(%0)"
b54cf83a 9951 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9952
38c1f2d7 9953(define_insn "*movqi_update1"
cd2b37d9
RK		 9954 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9955 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9956 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9957 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9958 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9959 "TARGET_UPDATE"
1fd4e8c1 9960 "@
5f243543
RK		 9961 lbzux %3,%0,%2
9962 lbzu %3,%2(%0)"
b54cf83a 9963 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9964
38c1f2d7 9965(define_insn "*movqi_update2"
cd2b37d9 9966 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9967 (zero_extend:SI
cd2b37d9 9968 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9969 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9970 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9971 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9972 "TARGET_UPDATE"
1fd4e8c1 9973 "@
5f243543
RK		 9974 lbzux %3,%0,%2
9975 lbzu %3,%2(%0)"
b54cf83a 9976 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9977
38c1f2d7 9978(define_insn "*movqi_update3"
cd2b37d9 9979 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9980 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9981 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9982 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9983 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9984 "TARGET_UPDATE"
1fd4e8c1 9985 "@
5f243543 9986 stbux %3,%0,%2
b7ff3d82 9987 stbu %3,%2(%0)"
b54cf83a 9988 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9989
38c1f2d7 9990(define_insn "*movsf_update1"
cd2b37d9 9991 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 9992 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9993 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9994 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9995 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9996 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9997 "@
5f243543
RK		 9998 lfsux %3,%0,%2
9999 lfsu %3,%2(%0)"
b54cf83a 10000 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10001
38c1f2d7 10002(define_insn "*movsf_update2"
cd2b37d9 10003 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10004 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10005 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10006 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10007 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10008 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10009 "@
85fff2f3 10010 stfsux %3,%0,%2
b7ff3d82 10011 stfsu %3,%2(%0)"
b54cf83a 10012 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 10013
38c1f2d7
MM		 10014(define_insn "*movsf_update3"
10015 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10016 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10017 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10018 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10019 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10020 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10021 "@
10022 {lux|lwzux} %3,%0,%2
10023 {lu|lwzu} %3,%2(%0)"
b54cf83a 10024 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 10025
10026(define_insn "*movsf_update4"
10027 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10028 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10029 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10030 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10031 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10032 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10033 "@
10034 {stux|stwux} %3,%0,%2
10035 {stu|stwu} %3,%2(%0)"
b54cf83a 10036 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 10037
10038(define_insn "*movdf_update1"
cd2b37d9
RK		 10039 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10040 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10041 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10042 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10043 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10044 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10045 "@
5f243543
RK		 10046 lfdux %3,%0,%2
10047 lfdu %3,%2(%0)"
b54cf83a 10048 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10049
38c1f2d7 10050(define_insn "*movdf_update2"
cd2b37d9 10051 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10052 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10053 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10054 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10055 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10056 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10057 "@
5f243543 10058 stfdux %3,%0,%2
b7ff3d82 10059 stfdu %3,%2(%0)"
b54cf83a 10060 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 10061
10062;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10063
90f81f99 10064(define_insn "*lfq_power2"
bb8df8a6
EC		 10065 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10066 (match_operand:V2DF 1 "memory_operand" ""))]
90f81f99
AP		 10067 "TARGET_POWER2
10068 && TARGET_HARD_FLOAT && TARGET_FPRS"
bb8df8a6 10069 "lfq%U1%X1 %0,%1")
90f81f99
AP		 10070
10071(define_peephole2
10072 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4c70a4f3 10073 (match_operand:DF 1 "memory_operand" ""))
90f81f99 10074 (set (match_operand:DF 2 "gpc_reg_operand" "")
4c70a4f3
RK		 10075 (match_operand:DF 3 "memory_operand" ""))]
10076 "TARGET_POWER2
a3170dc6 10077 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10078 && registers_ok_for_quad_peep (operands[0], operands[2])
90f81f99
AP		 10079 && mems_ok_for_quad_peep (operands[1], operands[3])"
10080 [(set (match_dup 0)
bb8df8a6
EC		 10081 (match_dup 1))]
10082 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10083 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
4c70a4f3 10084
90f81f99 10085(define_insn "*stfq_power2"
bb8df8a6
EC		 10086 [(set (match_operand:V2DF 0 "memory_operand" "")
10087 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
90f81f99
AP		 10088 "TARGET_POWER2
10089 && TARGET_HARD_FLOAT && TARGET_FPRS"
10090 "stfq%U0%X0 %1,%0")
10091
10092
10093(define_peephole2
4c70a4f3 10094 [(set (match_operand:DF 0 "memory_operand" "")
90f81f99 10095 (match_operand:DF 1 "gpc_reg_operand" ""))
4c70a4f3 10096 (set (match_operand:DF 2 "memory_operand" "")
90f81f99 10097 (match_operand:DF 3 "gpc_reg_operand" ""))]
4c70a4f3 10098 "TARGET_POWER2
a3170dc6 10099 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10100 && registers_ok_for_quad_peep (operands[1], operands[3])
90f81f99
AP		 10101 && mems_ok_for_quad_peep (operands[0], operands[2])"
10102 [(set (match_dup 0)
10103 (match_dup 1))]
bb8df8a6
EC		 10104 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10105 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
2f4d9502 10106
036aadfc 10107;; After inserting conditional returns we can sometimes have
2f4d9502
NS		 10108;; unnecessary register moves. Unfortunately we cannot have a
10109;; modeless peephole here, because some single SImode sets have early
10110;; clobber outputs. Although those sets expand to multi-ppc-insn
10111;; sequences, using get_attr_length here will smash the operands
10112;; array. Neither is there an early_cobbler_p predicate.
036aadfc 10113;; Disallow subregs for E500 so we don't munge frob_di_df_2.
2f4d9502
NS		 10114(define_peephole2
10115 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10116 (match_operand:DF 1 "any_operand" ""))
10117 (set (match_operand:DF 2 "gpc_reg_operand" "")
10118 (match_dup 0))]
036aadfc
AM		 10119 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10120 && peep2_reg_dead_p (2, operands[0])"
2f4d9502
NS		 10121 [(set (match_dup 2) (match_dup 1))])
10122
10123(define_peephole2
10124 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10125 (match_operand:SF 1 "any_operand" ""))
10126 (set (match_operand:SF 2 "gpc_reg_operand" "")
10127 (match_dup 0))]
10128 "peep2_reg_dead_p (2, operands[0])"
10129 [(set (match_dup 2) (match_dup 1))])
10130
1fd4e8c1 10131\f
c4501e62
JJ		 10132;; TLS support.
10133
10134;; "b" output constraint here and on tls_ld to support tls linker optimization.
10135(define_insn "tls_gd_32"
b150f4f3
DE		 10136 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10137 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10138 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10139 UNSPEC_TLSGD))]
10140 "HAVE_AS_TLS && !TARGET_64BIT"
10141 "addi %0,%1,%2@got@tlsgd")
10142
10143(define_insn "tls_gd_64"
b150f4f3
DE		 10144 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10145 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10146 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10147 UNSPEC_TLSGD))]
10148 "HAVE_AS_TLS && TARGET_64BIT"
10149 "addi %0,%1,%2@got@tlsgd")
10150
10151(define_insn "tls_ld_32"
b150f4f3
DE		 10152 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10153 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 10154 UNSPEC_TLSLD))]
10155 "HAVE_AS_TLS && !TARGET_64BIT"
10156 "addi %0,%1,%&@got@tlsld")
10157
10158(define_insn "tls_ld_64"
b150f4f3
DE		 10159 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10160 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 10161 UNSPEC_TLSLD))]
10162 "HAVE_AS_TLS && TARGET_64BIT"
10163 "addi %0,%1,%&@got@tlsld")
10164
10165(define_insn "tls_dtprel_32"
b150f4f3
DE		 10166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10167 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10168 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10169 UNSPEC_TLSDTPREL))]
10170 "HAVE_AS_TLS && !TARGET_64BIT"
10171 "addi %0,%1,%2@dtprel")
10172
10173(define_insn "tls_dtprel_64"
b150f4f3
DE		 10174 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10175 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10176 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10177 UNSPEC_TLSDTPREL))]
10178 "HAVE_AS_TLS && TARGET_64BIT"
10179 "addi %0,%1,%2@dtprel")
10180
10181(define_insn "tls_dtprel_ha_32"
b150f4f3
DE		 10182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10183 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10184 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10185 UNSPEC_TLSDTPRELHA))]
10186 "HAVE_AS_TLS && !TARGET_64BIT"
10187 "addis %0,%1,%2@dtprel@ha")
10188
10189(define_insn "tls_dtprel_ha_64"
b150f4f3
DE		 10190 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10191 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10192 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10193 UNSPEC_TLSDTPRELHA))]
10194 "HAVE_AS_TLS && TARGET_64BIT"
10195 "addis %0,%1,%2@dtprel@ha")
10196
10197(define_insn "tls_dtprel_lo_32"
b150f4f3
DE		 10198 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10199 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10200 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10201 UNSPEC_TLSDTPRELLO))]
10202 "HAVE_AS_TLS && !TARGET_64BIT"
10203 "addi %0,%1,%2@dtprel@l")
10204
10205(define_insn "tls_dtprel_lo_64"
b150f4f3
DE		 10206 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10207 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10208 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10209 UNSPEC_TLSDTPRELLO))]
10210 "HAVE_AS_TLS && TARGET_64BIT"
10211 "addi %0,%1,%2@dtprel@l")
10212
10213(define_insn "tls_got_dtprel_32"
b150f4f3
DE		 10214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10215 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10216 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10217 UNSPEC_TLSGOTDTPREL))]
10218 "HAVE_AS_TLS && !TARGET_64BIT"
10219 "lwz %0,%2@got@dtprel(%1)")
10220
10221(define_insn "tls_got_dtprel_64"
b150f4f3
DE		 10222 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10223 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10224 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10225 UNSPEC_TLSGOTDTPREL))]
10226 "HAVE_AS_TLS && TARGET_64BIT"
10227 "ld %0,%2@got@dtprel(%1)")
10228
10229(define_insn "tls_tprel_32"
b150f4f3
DE		 10230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10231 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10232 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10233 UNSPEC_TLSTPREL))]
10234 "HAVE_AS_TLS && !TARGET_64BIT"
10235 "addi %0,%1,%2@tprel")
10236
10237(define_insn "tls_tprel_64"
b150f4f3
DE		 10238 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10239 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10240 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10241 UNSPEC_TLSTPREL))]
10242 "HAVE_AS_TLS && TARGET_64BIT"
10243 "addi %0,%1,%2@tprel")
10244
10245(define_insn "tls_tprel_ha_32"
b150f4f3
DE		 10246 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10247 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10248 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10249 UNSPEC_TLSTPRELHA))]
10250 "HAVE_AS_TLS && !TARGET_64BIT"
10251 "addis %0,%1,%2@tprel@ha")
10252
10253(define_insn "tls_tprel_ha_64"
b150f4f3
DE		 10254 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10255 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10256 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10257 UNSPEC_TLSTPRELHA))]
10258 "HAVE_AS_TLS && TARGET_64BIT"
10259 "addis %0,%1,%2@tprel@ha")
10260
10261(define_insn "tls_tprel_lo_32"
b150f4f3
DE		 10262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10263 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10264 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10265 UNSPEC_TLSTPRELLO))]
10266 "HAVE_AS_TLS && !TARGET_64BIT"
10267 "addi %0,%1,%2@tprel@l")
10268
10269(define_insn "tls_tprel_lo_64"
b150f4f3
DE		 10270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10271 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10272 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10273 UNSPEC_TLSTPRELLO))]
10274 "HAVE_AS_TLS && TARGET_64BIT"
10275 "addi %0,%1,%2@tprel@l")
10276
c1207243 10277;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 10278;; optimization. The linker may edit the instructions emitted by a
10279;; tls_got_tprel/tls_tls pair to addis,addi.
10280(define_insn "tls_got_tprel_32"
b150f4f3
DE		 10281 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10282 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10283 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10284 UNSPEC_TLSGOTTPREL))]
10285 "HAVE_AS_TLS && !TARGET_64BIT"
10286 "lwz %0,%2@got@tprel(%1)")
10287
10288(define_insn "tls_got_tprel_64"
b150f4f3
DE		 10289 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10290 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10291 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10292 UNSPEC_TLSGOTTPREL))]
10293 "HAVE_AS_TLS && TARGET_64BIT"
10294 "ld %0,%2@got@tprel(%1)")
10295
10296(define_insn "tls_tls_32"
b150f4f3
DE		 10297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10298 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10299 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10300 UNSPEC_TLSTLS))]
10301 "HAVE_AS_TLS && !TARGET_64BIT"
10302 "add %0,%1,%2@tls")
10303
10304(define_insn "tls_tls_64"
b150f4f3
DE		 10305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10306 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10307 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10308 UNSPEC_TLSTLS))]
10309 "HAVE_AS_TLS && TARGET_64BIT"
10310 "add %0,%1,%2@tls")
10311\f
1fd4e8c1
RK		 10312;; Next come insns related to the calling sequence.
10313;;
10314;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 10315;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 10316
10317(define_expand "allocate_stack"
e42ac3de 10318 [(set (match_operand 0 "gpc_reg_operand" "")
a260abc9
DE		 10319 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10320 (set (reg 1)
10321 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 10322 ""
10323 "
4697a36c 10324{ rtx chain = gen_reg_rtx (Pmode);
39403d82 10325 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 10326 rtx neg_op0;
1fd4e8c1
RK		 10327
10328 emit_move_insn (chain, stack_bot);
4697a36c 10329
a157febd
GK		 10330 /* Check stack bounds if necessary. */
10331 if (current_function_limit_stack)
10332 {
10333 rtx available;
6ae08853 10334 available = expand_binop (Pmode, sub_optab,
a157febd
GK		 10335 stack_pointer_rtx, stack_limit_rtx,
10336 NULL_RTX, 1, OPTAB_WIDEN);
10337 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10338 }
10339
e9a25f70
JL		 10340 if (GET_CODE (operands[1]) != CONST_INT
10341 || INTVAL (operands[1]) < -32767
10342 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 10343 {
10344 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 10345 if (TARGET_32BIT)
e9a25f70 10346 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 10347 else
e9a25f70 10348 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 10349 }
10350 else
e9a25f70 10351 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 10352
38c1f2d7 10353 if (TARGET_UPDATE)
2e6c9641 10354 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
38c1f2d7 10355 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
4697a36c 10356
38c1f2d7
MM		 10357 else
10358 {
10359 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10360 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
39403d82 10361 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
38c1f2d7 10362 }
e9a25f70
JL		 10363
10364 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 10365 DONE;
10366}")
59257ff7
RK		 10367
10368;; These patterns say how to save and restore the stack pointer. We need not
10369;; save the stack pointer at function level since we are careful to
10370;; preserve the backchain. At block level, we have to restore the backchain
10371;; when we restore the stack pointer.
10372;;
10373;; For nonlocal gotos, we must save both the stack pointer and its
10374;; backchain and restore both. Note that in the nonlocal case, the
10375;; save area is a memory location.
10376
10377(define_expand "save_stack_function"
ff381587
MM		 10378 [(match_operand 0 "any_operand" "")
10379 (match_operand 1 "any_operand" "")]
59257ff7 10380 ""
ff381587 10381 "DONE;")
59257ff7
RK		 10382
10383(define_expand "restore_stack_function"
ff381587
MM		 10384 [(match_operand 0 "any_operand" "")
10385 (match_operand 1 "any_operand" "")]
59257ff7 10386 ""
ff381587 10387 "DONE;")
59257ff7 10388
2eef28ec
AM		 10389;; Adjust stack pointer (op0) to a new value (op1).
10390;; First copy old stack backchain to new location, and ensure that the
10391;; scheduler won't reorder the sp assignment before the backchain write.
59257ff7 10392(define_expand "restore_stack_block"
2eef28ec
AM		 10393 [(set (match_dup 2) (match_dup 3))
10394 (set (match_dup 4) (match_dup 2))
10395 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10396 (set (match_operand 0 "register_operand" "")
10397 (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10398 ""
10399 "
dfdfa60f
DE		 10400{
10401 operands[2] = gen_reg_rtx (Pmode);
2eef28ec
AM		 10402 operands[3] = gen_frame_mem (Pmode, operands[0]);
10403 operands[4] = gen_frame_mem (Pmode, operands[1]);
10404 operands[5] = gen_frame_mem (BLKmode, operands[0]);
dfdfa60f 10405}")
59257ff7
RK		 10406
10407(define_expand "save_stack_nonlocal"
2eef28ec
AM		 10408 [(set (match_dup 3) (match_dup 4))
10409 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10410 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10411 ""
10412 "
10413{
11b25716 10414 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10415
10416 /* Copy the backchain to the first word, sp to the second. */
2eef28ec
AM		 10417 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10418 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10419 operands[3] = gen_reg_rtx (Pmode);
10420 operands[4] = gen_frame_mem (Pmode, operands[1]);
59257ff7 10421}")
7e69e155 10422
59257ff7 10423(define_expand "restore_stack_nonlocal"
2eef28ec
AM		 10424 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10425 (set (match_dup 3) (match_dup 4))
10426 (set (match_dup 5) (match_dup 2))
10427 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10428 (set (match_operand 0 "register_operand" "") (match_dup 3))]
59257ff7
RK		 10429 ""
10430 "
10431{
11b25716 10432 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10433
10434 /* Restore the backchain from the first word, sp from the second. */
2eef28ec
AM		 10435 operands[2] = gen_reg_rtx (Pmode);
10436 operands[3] = gen_reg_rtx (Pmode);
10437 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10438 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10439 operands[5] = gen_frame_mem (Pmode, operands[3]);
10440 operands[6] = gen_frame_mem (BLKmode, operands[0]);
59257ff7 10441}")
9ebbca7d
GK		 10442\f
10443;; TOC register handling.
b6c9286a 10444
9ebbca7d 10445;; Code to initialize the TOC register...
f0f6a223 10446
9ebbca7d 10447(define_insn "load_toc_aix_si"
e72247f4 10448 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 10449 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10450 (use (reg:SI 2))])]
2bfcf297 10451 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 10452 "*
10453{
9ebbca7d
GK		 10454 char buf[30];
10455 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 10456 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10457 operands[2] = gen_rtx_REG (Pmode, 2);
10458 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 10459}"
10460 [(set_attr "type" "load")])
9ebbca7d
GK		 10461
10462(define_insn "load_toc_aix_di"
e72247f4 10463 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 10464 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10465 (use (reg:DI 2))])]
2bfcf297 10466 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 10467 "*
10468{
10469 char buf[30];
f585a356
DE		 10470#ifdef TARGET_RELOCATABLE
10471 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10472 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10473#else
9ebbca7d 10474 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 10475#endif
2bfcf297
DB		 10476 if (TARGET_ELF)
10477 strcat (buf, \"@toc\");
a8a05998 10478 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10479 operands[2] = gen_rtx_REG (Pmode, 2);
10480 return \"ld %0,%1(%2)\";
10481}"
10482 [(set_attr "type" "load")])
10483
10484(define_insn "load_toc_v4_pic_si"
10485 [(set (match_operand:SI 0 "register_operand" "=l")
615158e2 10486 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 10487 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 10488 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10489 [(set_attr "type" "branch")
10490 (set_attr "length" "4")])
10491
9ebbca7d
GK		 10492(define_insn "load_toc_v4_PIC_1"
10493 [(set (match_operand:SI 0 "register_operand" "=l")
10494 (match_operand:SI 1 "immediate_operand" "s"))
c4501e62 10495 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
7f970b70
AM		 10496 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10497 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
df7a8989 10498 "bcl 20,31,%1\\n%1:"
9ebbca7d
GK		 10499 [(set_attr "type" "branch")
10500 (set_attr "length" "4")])
10501
10502(define_insn "load_toc_v4_PIC_1b"
10503 [(set (match_operand:SI 0 "register_operand" "=l")
0e5be35b 10504 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
c4501e62 10505 UNSPEC_TOCPTR))]
20b71b17 10506 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
0e5be35b 10507 "bcl 20,31,$+8\\n\\t.long %1-$"
9ebbca7d
GK		 10508 [(set_attr "type" "branch")
10509 (set_attr "length" "8")])
10510
10511(define_insn "load_toc_v4_PIC_2"
f585a356 10512 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 10513 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 10514 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10515 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 10516 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 10517 "{l|lwz} %0,%2-%3(%1)"
10518 [(set_attr "type" "load")])
10519
7f970b70
AM		 10520(define_insn "load_toc_v4_PIC_3b"
10521 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10522 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10523 (high:SI
10524 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10525 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10526 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10527 "{cau|addis} %0,%1,%2-%3@ha")
10528
10529(define_insn "load_toc_v4_PIC_3c"
10530 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10531 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10532 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10533 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10534 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10535 "{cal|addi} %0,%1,%2-%3@l")
f51eee6a 10536
9ebbca7d
GK		 10537;; If the TOC is shared over a translation unit, as happens with all
10538;; the kinds of PIC that we support, we need to restore the TOC
10539;; pointer only when jumping over units of translation.
f51eee6a 10540;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 10541
10542(define_expand "builtin_setjmp_receiver"
10543 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 10544 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 10545 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10546 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 10547 "
10548{
84d7dd4a 10549#if TARGET_MACHO
f51eee6a
GK		 10550 if (DEFAULT_ABI == ABI_DARWIN)
10551 {
d24652ee 10552 const char *picbase = machopic_function_base_name ();
485bad26 10553 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
f51eee6a
GK		 10554 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10555 rtx tmplabrtx;
10556 char tmplab[20];
10557
10558 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10559 CODE_LABEL_NUMBER (operands[0]));
485bad26 10560 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a 10561
b8a55285
AP		 10562 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10563 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
f51eee6a
GK		 10564 }
10565 else
84d7dd4a 10566#endif
f51eee6a 10567 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 10568 DONE;
10569}")
7f970b70
AM		 10570
10571;; Elf specific ways of loading addresses for non-PIC code.
10572;; The output of this could be r0, but we make a very strong
10573;; preference for a base register because it will usually
10574;; be needed there.
10575(define_insn "elf_high"
10576 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10577 (high:SI (match_operand 1 "" "")))]
10578 "TARGET_ELF && ! TARGET_64BIT"
10579 "{liu|lis} %0,%1@ha")
10580
10581(define_insn "elf_low"
10582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10583 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10584 (match_operand 2 "" "")))]
10585 "TARGET_ELF && ! TARGET_64BIT"
10586 "@
10587 {cal|la} %0,%2@l(%1)
10588 {ai|addic} %0,%1,%K2")
9ebbca7d
GK		 10589\f
10590;; A function pointer under AIX is a pointer to a data area whose first word
10591;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 10592;; pointer to its TOC, and whose third word contains a value to place in the
10593;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 10594;; "trampoline" need not have any executable code.
b6c9286a 10595
cccf3bdc
DE		 10596(define_expand "call_indirect_aix32"
10597 [(set (match_dup 2)
10598 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10599 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10600 (reg:SI 2))
10601 (set (reg:SI 2)
10602 (mem:SI (plus:SI (match_dup 0)
10603 (const_int 4))))
10604 (set (reg:SI 11)
10605 (mem:SI (plus:SI (match_dup 0)
10606 (const_int 8))))
10607 (parallel [(call (mem:SI (match_dup 2))
10608 (match_operand 1 "" ""))
10609 (use (reg:SI 2))
10610 (use (reg:SI 11))
10611 (set (reg:SI 2)
10612 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10613 (clobber (scratch:SI))])]
10614 "TARGET_32BIT"
10615 "
10616{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 10617
cccf3bdc
DE		 10618(define_expand "call_indirect_aix64"
10619 [(set (match_dup 2)
10620 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10621 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10622 (reg:DI 2))
10623 (set (reg:DI 2)
10624 (mem:DI (plus:DI (match_dup 0)
10625 (const_int 8))))
10626 (set (reg:DI 11)
10627 (mem:DI (plus:DI (match_dup 0)
10628 (const_int 16))))
10629 (parallel [(call (mem:SI (match_dup 2))
10630 (match_operand 1 "" ""))
10631 (use (reg:DI 2))
10632 (use (reg:DI 11))
10633 (set (reg:DI 2)
10634 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10635 (clobber (scratch:SI))])]
10636 "TARGET_64BIT"
10637 "
10638{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 10639
cccf3bdc
DE		 10640(define_expand "call_value_indirect_aix32"
10641 [(set (match_dup 3)
10642 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10643 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10644 (reg:SI 2))
10645 (set (reg:SI 2)
10646 (mem:SI (plus:SI (match_dup 1)
10647 (const_int 4))))
10648 (set (reg:SI 11)
10649 (mem:SI (plus:SI (match_dup 1)
10650 (const_int 8))))
10651 (parallel [(set (match_operand 0 "" "")
10652 (call (mem:SI (match_dup 3))
10653 (match_operand 2 "" "")))
10654 (use (reg:SI 2))
10655 (use (reg:SI 11))
10656 (set (reg:SI 2)
10657 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10658 (clobber (scratch:SI))])]
10659 "TARGET_32BIT"
10660 "
10661{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 10662
cccf3bdc
DE		 10663(define_expand "call_value_indirect_aix64"
10664 [(set (match_dup 3)
10665 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10666 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10667 (reg:DI 2))
10668 (set (reg:DI 2)
10669 (mem:DI (plus:DI (match_dup 1)
10670 (const_int 8))))
10671 (set (reg:DI 11)
10672 (mem:DI (plus:DI (match_dup 1)
10673 (const_int 16))))
10674 (parallel [(set (match_operand 0 "" "")
10675 (call (mem:SI (match_dup 3))
10676 (match_operand 2 "" "")))
10677 (use (reg:DI 2))
10678 (use (reg:DI 11))
10679 (set (reg:DI 2)
10680 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10681 (clobber (scratch:SI))])]
10682 "TARGET_64BIT"
10683 "
10684{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 10685
b6c9286a 10686;; Now the definitions for the call and call_value insns
1fd4e8c1 10687(define_expand "call"
a260abc9 10688 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 10689 (match_operand 1 "" ""))
4697a36c 10690 (use (match_operand 2 "" ""))
1fd4e8c1
RK		 10691 (clobber (scratch:SI))])]
10692 ""
10693 "
10694{
ee890fe2 10695#if TARGET_MACHO
ab82a49f 10696 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10697 operands[0] = machopic_indirect_call_target (operands[0]);
10698#endif
10699
37409796
NS		 10700 gcc_assert (GET_CODE (operands[0]) == MEM);
10701 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
1fd4e8c1
RK		 10702
10703 operands[0] = XEXP (operands[0], 0);
7509c759 10704
7f970b70
AM		 10705 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10706 && flag_pic
10707 && GET_CODE (operands[0]) == SYMBOL_REF
10708 && !SYMBOL_REF_LOCAL_P (operands[0]))
10709 {
10710 rtx call;
10711 rtvec tmp;
10712
10713 tmp = gen_rtvec (3,
10714 gen_rtx_CALL (VOIDmode,
10715 gen_rtx_MEM (SImode, operands[0]),
10716 operands[1]),
10717 gen_rtx_USE (VOIDmode, operands[2]),
10718 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10719 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10720 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10721 DONE;
10722 }
10723
6a4cee5f 10724 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 10725 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
efdba735 10726 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
1fd4e8c1 10727 {
6a4cee5f
MM		 10728 if (INTVAL (operands[2]) & CALL_LONG)
10729 operands[0] = rs6000_longcall_ref (operands[0]);
10730
37409796
NS		 10731 switch (DEFAULT_ABI)
10732 {
10733 case ABI_V4:
10734 case ABI_DARWIN:
10735 operands[0] = force_reg (Pmode, operands[0]);
10736 break;
1fd4e8c1 10737
37409796 10738 case ABI_AIX:
cccf3bdc
DE		 10739 /* AIX function pointers are really pointers to a three word
10740 area. */
10741 emit_call_insn (TARGET_32BIT
10742 ? gen_call_indirect_aix32 (force_reg (SImode,
10743 operands[0]),
10744 operands[1])
10745 : gen_call_indirect_aix64 (force_reg (DImode,
10746 operands[0]),
10747 operands[1]));
10748 DONE;
37409796
NS		 10749
10750 default:
10751 gcc_unreachable ();
b6c9286a 10752 }
1fd4e8c1
RK		 10753 }
10754}")
10755
10756(define_expand "call_value"
10757 [(parallel [(set (match_operand 0 "" "")
a260abc9 10758 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 10759 (match_operand 2 "" "")))
4697a36c 10760 (use (match_operand 3 "" ""))
1fd4e8c1
RK		 10761 (clobber (scratch:SI))])]
10762 ""
10763 "
10764{
ee890fe2 10765#if TARGET_MACHO
ab82a49f 10766 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10767 operands[1] = machopic_indirect_call_target (operands[1]);
10768#endif
10769
37409796
NS		 10770 gcc_assert (GET_CODE (operands[1]) == MEM);
10771 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
1fd4e8c1
RK		 10772
10773 operands[1] = XEXP (operands[1], 0);
7509c759 10774
7f970b70
AM		 10775 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10776 && flag_pic
10777 && GET_CODE (operands[1]) == SYMBOL_REF
10778 && !SYMBOL_REF_LOCAL_P (operands[1]))
10779 {
10780 rtx call;
10781 rtvec tmp;
10782
10783 tmp = gen_rtvec (3,
10784 gen_rtx_SET (VOIDmode,
10785 operands[0],
10786 gen_rtx_CALL (VOIDmode,
10787 gen_rtx_MEM (SImode,
10788 operands[1]),
10789 operands[2])),
10790 gen_rtx_USE (VOIDmode, operands[3]),
10791 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10792 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10793 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10794 DONE;
10795 }
10796
6a4cee5f 10797 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 10798 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
efdba735 10799 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
1fd4e8c1 10800 {
6756293c 10801 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 10802 operands[1] = rs6000_longcall_ref (operands[1]);
10803
37409796
NS		 10804 switch (DEFAULT_ABI)
10805 {
10806 case ABI_V4:
10807 case ABI_DARWIN:
10808 operands[1] = force_reg (Pmode, operands[1]);
10809 break;
1fd4e8c1 10810
37409796 10811 case ABI_AIX:
cccf3bdc
DE		 10812 /* AIX function pointers are really pointers to a three word
10813 area. */
10814 emit_call_insn (TARGET_32BIT
10815 ? gen_call_value_indirect_aix32 (operands[0],
10816 force_reg (SImode,
10817 operands[1]),
10818 operands[2])
10819 : gen_call_value_indirect_aix64 (operands[0],
10820 force_reg (DImode,
10821 operands[1]),
10822 operands[2]));
10823 DONE;
37409796
NS		 10824
10825 default:
10826 gcc_unreachable ();
b6c9286a 10827 }
1fd4e8c1
RK		 10828 }
10829}")
10830
04780ee7 10831;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 10832;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10833;; either the function was not prototyped, or it was prototyped as a
10834;; variable argument function. It is > 0 if FP registers were passed
10835;; and < 0 if they were not.
04780ee7 10836
a260abc9 10837(define_insn "*call_local32"
4697a36c
MM		 10838 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10839 (match_operand 1 "" "g,g"))
10840 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10841 (clobber (match_scratch:SI 3 "=l,l"))]
5a19791c 10842 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 10843 "*
10844{
6a4cee5f
MM		 10845 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10846 output_asm_insn (\"crxor 6,6,6\", operands);
10847
10848 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10849 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 10850
a226df46 10851 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 10852}"
b7ff3d82
DE		 10853 [(set_attr "type" "branch")
10854 (set_attr "length" "4,8")])
04780ee7 10855
a260abc9
DE		 10856(define_insn "*call_local64"
10857 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10858 (match_operand 1 "" "g,g"))
10859 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10860 (clobber (match_scratch:SI 3 "=l,l"))]
10861 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10862 "*
10863{
10864 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10865 output_asm_insn (\"crxor 6,6,6\", operands);
10866
10867 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10868 output_asm_insn (\"creqv 6,6,6\", operands);
10869
10870 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10871}"
10872 [(set_attr "type" "branch")
10873 (set_attr "length" "4,8")])
10874
cccf3bdc 10875(define_insn "*call_value_local32"
d18dba68 10876 [(set (match_operand 0 "" "")
a260abc9
DE		 10877 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10878 (match_operand 2 "" "g,g")))
10879 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10880 (clobber (match_scratch:SI 4 "=l,l"))]
10881 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10882 "*
10883{
10884 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10885 output_asm_insn (\"crxor 6,6,6\", operands);
10886
10887 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10888 output_asm_insn (\"creqv 6,6,6\", operands);
10889
10890 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10891}"
10892 [(set_attr "type" "branch")
10893 (set_attr "length" "4,8")])
10894
10895
cccf3bdc 10896(define_insn "*call_value_local64"
d18dba68 10897 [(set (match_operand 0 "" "")
a260abc9
DE		 10898 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10899 (match_operand 2 "" "g,g")))
10900 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10901 (clobber (match_scratch:SI 4 "=l,l"))]
10902 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10903 "*
10904{
10905 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10906 output_asm_insn (\"crxor 6,6,6\", operands);
10907
10908 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10909 output_asm_insn (\"creqv 6,6,6\", operands);
10910
10911 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10912}"
10913 [(set_attr "type" "branch")
10914 (set_attr "length" "4,8")])
10915
04780ee7 10916;; Call to function which may be in another module. Restore the TOC
911f679c 10917;; pointer (r2) after the call unless this is System V.
a0ab749a 10918;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10919;; either the function was not prototyped, or it was prototyped as a
10920;; variable argument function. It is > 0 if FP registers were passed
10921;; and < 0 if they were not.
04780ee7 10922
cccf3bdc 10923(define_insn "*call_indirect_nonlocal_aix32"
70ae0191
DE		 10924 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10925 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 10926 (use (reg:SI 2))
10927 (use (reg:SI 11))
10928 (set (reg:SI 2)
10929 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
70ae0191 10930 (clobber (match_scratch:SI 2 "=l,l"))]
cccf3bdc
DE		 10931 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10932 "b%T0l\;{l|lwz} 2,20(1)"
10933 [(set_attr "type" "jmpreg")
10934 (set_attr "length" "8")])
10935
a260abc9 10936(define_insn "*call_nonlocal_aix32"
cc4d5fec 10937 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10938 (match_operand 1 "" "g"))
10939 (use (match_operand:SI 2 "immediate_operand" "O"))
10940 (clobber (match_scratch:SI 3 "=l"))]
10941 "TARGET_32BIT
10942 && DEFAULT_ABI == ABI_AIX
5a19791c 10943 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10944 "bl %z0\;%."
b7ff3d82 10945 [(set_attr "type" "branch")
cccf3bdc
DE		 10946 (set_attr "length" "8")])
10947
10948(define_insn "*call_indirect_nonlocal_aix64"
70ae0191
DE		 10949 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10950 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 10951 (use (reg:DI 2))
10952 (use (reg:DI 11))
10953 (set (reg:DI 2)
10954 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
70ae0191 10955 (clobber (match_scratch:SI 2 "=l,l"))]
cccf3bdc
DE		 10956 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10957 "b%T0l\;ld 2,40(1)"
10958 [(set_attr "type" "jmpreg")
10959 (set_attr "length" "8")])
59313e4e 10960
a260abc9 10961(define_insn "*call_nonlocal_aix64"
cc4d5fec 10962 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10963 (match_operand 1 "" "g"))
10964 (use (match_operand:SI 2 "immediate_operand" "O"))
10965 (clobber (match_scratch:SI 3 "=l"))]
6ae08853 10966 "TARGET_64BIT
9ebbca7d 10967 && DEFAULT_ABI == ABI_AIX
a260abc9 10968 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10969 "bl %z0\;%."
a260abc9 10970 [(set_attr "type" "branch")
cccf3bdc 10971 (set_attr "length" "8")])
7509c759 10972
cccf3bdc 10973(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 10974 [(set (match_operand 0 "" "")
70ae0191
DE		 10975 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10976 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 10977 (use (reg:SI 2))
10978 (use (reg:SI 11))
10979 (set (reg:SI 2)
10980 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
70ae0191 10981 (clobber (match_scratch:SI 3 "=l,l"))]
cccf3bdc
DE		 10982 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10983 "b%T1l\;{l|lwz} 2,20(1)"
10984 [(set_attr "type" "jmpreg")
10985 (set_attr "length" "8")])
1fd4e8c1 10986
cccf3bdc 10987(define_insn "*call_value_nonlocal_aix32"
d18dba68 10988 [(set (match_operand 0 "" "")
cc4d5fec 10989 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10990 (match_operand 2 "" "g")))
10991 (use (match_operand:SI 3 "immediate_operand" "O"))
10992 (clobber (match_scratch:SI 4 "=l"))]
10993 "TARGET_32BIT
10994 && DEFAULT_ABI == ABI_AIX
a260abc9 10995 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 10996 "bl %z1\;%."
b7ff3d82 10997 [(set_attr "type" "branch")
cccf3bdc 10998 (set_attr "length" "8")])
04780ee7 10999
cccf3bdc 11000(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 11001 [(set (match_operand 0 "" "")
70ae0191
DE		 11002 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11003 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11004 (use (reg:DI 2))
11005 (use (reg:DI 11))
11006 (set (reg:DI 2)
11007 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
70ae0191 11008 (clobber (match_scratch:SI 3 "=l,l"))]
cccf3bdc
DE		 11009 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11010 "b%T1l\;ld 2,40(1)"
11011 [(set_attr "type" "jmpreg")
11012 (set_attr "length" "8")])
11013
11014(define_insn "*call_value_nonlocal_aix64"
d18dba68 11015 [(set (match_operand 0 "" "")
cc4d5fec 11016 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11017 (match_operand 2 "" "g")))
11018 (use (match_operand:SI 3 "immediate_operand" "O"))
11019 (clobber (match_scratch:SI 4 "=l"))]
6ae08853 11020 "TARGET_64BIT
9ebbca7d 11021 && DEFAULT_ABI == ABI_AIX
5a19791c 11022 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 11023 "bl %z1\;%."
11024 [(set_attr "type" "branch")
11025 (set_attr "length" "8")])
11026
11027;; A function pointer under System V is just a normal pointer
11028;; operands[0] is the function pointer
11029;; operands[1] is the stack size to clean up
11030;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11031;; which indicates how to set cr1
11032
9613eaff
SH		 11033(define_insn "*call_indirect_nonlocal_sysv<mode>"
11034 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11035 (match_operand 1 "" "g,g,g,g"))
11036 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11037 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
50d440bc 11038 "DEFAULT_ABI == ABI_V4
f607bc57 11039 || DEFAULT_ABI == ABI_DARWIN"
911f679c 11040{
cccf3bdc 11041 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11042 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 11043
cccf3bdc 11044 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11045 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11046
a5c76ee6
ZW		 11047 return "b%T0l";
11048}
6d0a8091
DJ		 11049 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11050 (set_attr "length" "4,4,8,8")])
cccf3bdc 11051
9613eaff
SH		 11052(define_insn "*call_nonlocal_sysv<mode>"
11053 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11054 (match_operand 1 "" "g,g"))
11055 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11056 (clobber (match_scratch:SI 3 "=l,l"))]
efdba735
SH		 11057 "(DEFAULT_ABI == ABI_DARWIN
11058 || (DEFAULT_ABI == ABI_V4
11059 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11060{
11061 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11062 output_asm_insn ("crxor 6,6,6", operands);
11063
11064 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11065 output_asm_insn ("creqv 6,6,6", operands);
11066
c989f2f7 11067#if TARGET_MACHO
efdba735
SH		 11068 return output_call(insn, operands, 0, 2);
11069#else
7f970b70
AM		 11070 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11071 {
11072 if (TARGET_SECURE_PLT && flag_pic == 2)
11073 /* The magic 32768 offset here and in the other sysv call insns
11074 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11075 See sysv4.h:toc_section. */
11076 return "bl %z0+32768@plt";
11077 else
11078 return "bl %z0@plt";
11079 }
11080 else
11081 return "bl %z0";
6ae08853 11082#endif
a5c76ee6
ZW		 11083}
11084 [(set_attr "type" "branch,branch")
11085 (set_attr "length" "4,8")])
11086
9613eaff 11087(define_insn "*call_value_indirect_nonlocal_sysv<mode>"
d18dba68 11088 [(set (match_operand 0 "" "")
9613eaff 11089 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11090 (match_operand 2 "" "g,g,g,g")))
11091 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11092 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
50d440bc 11093 "DEFAULT_ABI == ABI_V4
f607bc57 11094 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 11095{
6a4cee5f 11096 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11097 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 11098
11099 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11100 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11101
a5c76ee6
ZW		 11102 return "b%T1l";
11103}
6d0a8091
DJ		 11104 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11105 (set_attr "length" "4,4,8,8")])
a5c76ee6 11106
9613eaff 11107(define_insn "*call_value_nonlocal_sysv<mode>"
a5c76ee6 11108 [(set (match_operand 0 "" "")
9613eaff 11109 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11110 (match_operand 2 "" "g,g")))
11111 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11112 (clobber (match_scratch:SI 4 "=l,l"))]
efdba735
SH		 11113 "(DEFAULT_ABI == ABI_DARWIN
11114 || (DEFAULT_ABI == ABI_V4
11115 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11116{
11117 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11118 output_asm_insn ("crxor 6,6,6", operands);
11119
11120 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11121 output_asm_insn ("creqv 6,6,6", operands);
11122
c989f2f7 11123#if TARGET_MACHO
efdba735
SH		 11124 return output_call(insn, operands, 1, 3);
11125#else
7f970b70
AM		 11126 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11127 {
11128 if (TARGET_SECURE_PLT && flag_pic == 2)
11129 return "bl %z1+32768@plt";
11130 else
11131 return "bl %z1@plt";
11132 }
11133 else
11134 return "bl %z1";
6ae08853 11135#endif
a5c76ee6
ZW		 11136}
11137 [(set_attr "type" "branch,branch")
11138 (set_attr "length" "4,8")])
e6f948e3
RK		 11139
11140;; Call subroutine returning any type.
e6f948e3
RK		 11141(define_expand "untyped_call"
11142 [(parallel [(call (match_operand 0 "" "")
11143 (const_int 0))
11144 (match_operand 1 "" "")
11145 (match_operand 2 "" "")])]
11146 ""
11147 "
11148{
11149 int i;
11150
7d70b8b2 11151 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 11152
11153 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11154 {
11155 rtx set = XVECEXP (operands[2], 0, i);
11156 emit_move_insn (SET_DEST (set), SET_SRC (set));
11157 }
11158
11159 /* The optimizer does not know that the call sets the function value
11160 registers we stored in the result block. We avoid problems by
11161 claiming that all hard registers are used and clobbered at this
11162 point. */
11163 emit_insn (gen_blockage ());
11164
11165 DONE;
11166}")
11167
5e1bf043
DJ		 11168;; sibling call patterns
11169(define_expand "sibcall"
11170 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11171 (match_operand 1 "" ""))
11172 (use (match_operand 2 "" ""))
fe352c29 11173 (use (match_operand 3 "" ""))
5e1bf043
DJ		 11174 (return)])]
11175 ""
11176 "
11177{
11178#if TARGET_MACHO
ab82a49f 11179 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11180 operands[0] = machopic_indirect_call_target (operands[0]);
11181#endif
11182
37409796
NS		 11183 gcc_assert (GET_CODE (operands[0]) == MEM);
11184 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5e1bf043
DJ		 11185
11186 operands[0] = XEXP (operands[0], 0);
fe352c29 11187 operands[3] = gen_reg_rtx (SImode);
5e1bf043
DJ		 11188
11189}")
11190
11191;; this and similar patterns must be marked as using LR, otherwise
11192;; dataflow will try to delete the store into it. This is true
11193;; even when the actual reg to jump to is in CTR, when LR was
11194;; saved and restored around the PIC-setting BCL.
11195(define_insn "*sibcall_local32"
11196 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11197 (match_operand 1 "" "g,g"))
11198 (use (match_operand:SI 2 "immediate_operand" "O,n"))
fe352c29 11199 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 11200 (return)]
11201 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11202 "*
11203{
11204 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11205 output_asm_insn (\"crxor 6,6,6\", operands);
11206
11207 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11208 output_asm_insn (\"creqv 6,6,6\", operands);
11209
11210 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11211}"
11212 [(set_attr "type" "branch")
11213 (set_attr "length" "4,8")])
11214
11215(define_insn "*sibcall_local64"
11216 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11217 (match_operand 1 "" "g,g"))
11218 (use (match_operand:SI 2 "immediate_operand" "O,n"))
fe352c29 11219 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 11220 (return)]
11221 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11222 "*
11223{
11224 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11225 output_asm_insn (\"crxor 6,6,6\", operands);
11226
11227 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11228 output_asm_insn (\"creqv 6,6,6\", operands);
11229
11230 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11231}"
11232 [(set_attr "type" "branch")
11233 (set_attr "length" "4,8")])
11234
11235(define_insn "*sibcall_value_local32"
11236 [(set (match_operand 0 "" "")
11237 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11238 (match_operand 2 "" "g,g")))
11239 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 11240 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 11241 (return)]
11242 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11243 "*
11244{
11245 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11246 output_asm_insn (\"crxor 6,6,6\", operands);
11247
11248 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11249 output_asm_insn (\"creqv 6,6,6\", operands);
11250
11251 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11252}"
11253 [(set_attr "type" "branch")
11254 (set_attr "length" "4,8")])
11255
11256
11257(define_insn "*sibcall_value_local64"
11258 [(set (match_operand 0 "" "")
11259 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11260 (match_operand 2 "" "g,g")))
11261 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 11262 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 11263 (return)]
11264 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11265 "*
11266{
11267 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11268 output_asm_insn (\"crxor 6,6,6\", operands);
11269
11270 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11271 output_asm_insn (\"creqv 6,6,6\", operands);
11272
11273 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11274}"
11275 [(set_attr "type" "branch")
11276 (set_attr "length" "4,8")])
11277
11278(define_insn "*sibcall_nonlocal_aix32"
11279 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11280 (match_operand 1 "" "g"))
11281 (use (match_operand:SI 2 "immediate_operand" "O"))
fe352c29 11282 (use (match_operand:SI 3 "register_operand" "l"))
5e1bf043
DJ		 11283 (return)]
11284 "TARGET_32BIT
11285 && DEFAULT_ABI == ABI_AIX
11286 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11287 "b %z0"
11288 [(set_attr "type" "branch")
11289 (set_attr "length" "4")])
11290
11291(define_insn "*sibcall_nonlocal_aix64"
11292 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11293 (match_operand 1 "" "g"))
11294 (use (match_operand:SI 2 "immediate_operand" "O"))
fe352c29 11295 (use (match_operand:SI 3 "register_operand" "l"))
5e1bf043 11296 (return)]
6ae08853 11297 "TARGET_64BIT
5e1bf043
DJ		 11298 && DEFAULT_ABI == ABI_AIX
11299 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11300 "b %z0"
11301 [(set_attr "type" "branch")
11302 (set_attr "length" "4")])
11303
11304(define_insn "*sibcall_value_nonlocal_aix32"
11305 [(set (match_operand 0 "" "")
11306 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11307 (match_operand 2 "" "g")))
11308 (use (match_operand:SI 3 "immediate_operand" "O"))
fe352c29 11309 (use (match_operand:SI 4 "register_operand" "l"))
5e1bf043
DJ		 11310 (return)]
11311 "TARGET_32BIT
11312 && DEFAULT_ABI == ABI_AIX
11313 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11314 "b %z1"
11315 [(set_attr "type" "branch")
11316 (set_attr "length" "4")])
11317
11318(define_insn "*sibcall_value_nonlocal_aix64"
11319 [(set (match_operand 0 "" "")
11320 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11321 (match_operand 2 "" "g")))
11322 (use (match_operand:SI 3 "immediate_operand" "O"))
fe352c29 11323 (use (match_operand:SI 4 "register_operand" "l"))
5e1bf043 11324 (return)]
6ae08853 11325 "TARGET_64BIT
5e1bf043
DJ		 11326 && DEFAULT_ABI == ABI_AIX
11327 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11328 "b %z1"
11329 [(set_attr "type" "branch")
11330 (set_attr "length" "4")])
11331
9613eaff
SH		 11332(define_insn "*sibcall_nonlocal_sysv<mode>"
11333 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11334 (match_operand 1 "" ""))
11335 (use (match_operand 2 "immediate_operand" "O,n"))
fe352c29 11336 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 11337 (return)]
11338 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11339 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11340 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11341 "*
11342{
11343 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11344 output_asm_insn (\"crxor 6,6,6\", operands);
11345
11346 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11347 output_asm_insn (\"creqv 6,6,6\", operands);
11348
7f970b70
AM		 11349 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11350 {
11351 if (TARGET_SECURE_PLT && flag_pic == 2)
11352 return \"b %z0+32768@plt\";
11353 else
11354 return \"b %z0@plt\";
11355 }
11356 else
11357 return \"b %z0\";
5e1bf043
DJ		 11358}"
11359 [(set_attr "type" "branch,branch")
11360 (set_attr "length" "4,8")])
11361
11362(define_expand "sibcall_value"
11363 [(parallel [(set (match_operand 0 "register_operand" "")
11364 (call (mem:SI (match_operand 1 "address_operand" ""))
11365 (match_operand 2 "" "")))
11366 (use (match_operand 3 "" ""))
fe352c29 11367 (use (match_operand 4 "" ""))
5e1bf043
DJ		 11368 (return)])]
11369 ""
11370 "
11371{
11372#if TARGET_MACHO
ab82a49f 11373 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11374 operands[1] = machopic_indirect_call_target (operands[1]);
11375#endif
11376
37409796
NS		 11377 gcc_assert (GET_CODE (operands[1]) == MEM);
11378 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5e1bf043
DJ		 11379
11380 operands[1] = XEXP (operands[1], 0);
fe352c29 11381 operands[4] = gen_reg_rtx (SImode);
5e1bf043
DJ		 11382
11383}")
11384
9613eaff 11385(define_insn "*sibcall_value_nonlocal_sysv<mode>"
5e1bf043 11386 [(set (match_operand 0 "" "")
9613eaff 11387 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11388 (match_operand 2 "" "")))
11389 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 11390 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 11391 (return)]
11392 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11393 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11394 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11395 "*
11396{
11397 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11398 output_asm_insn (\"crxor 6,6,6\", operands);
11399
11400 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11401 output_asm_insn (\"creqv 6,6,6\", operands);
11402
7f970b70
AM		 11403 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11404 {
11405 if (TARGET_SECURE_PLT && flag_pic == 2)
11406 return \"b %z1+32768@plt\";
11407 else
11408 return \"b %z1@plt\";
11409 }
11410 else
11411 return \"b %z1\";
5e1bf043
DJ		 11412}"
11413 [(set_attr "type" "branch,branch")
11414 (set_attr "length" "4,8")])
11415
11416(define_expand "sibcall_epilogue"
11417 [(use (const_int 0))]
11418 "TARGET_SCHED_PROLOG"
11419 "
11420{
11421 rs6000_emit_epilogue (TRUE);
11422 DONE;
11423}")
11424
e6f948e3
RK		 11425;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11426;; all of memory. This blocks insns from being moved across this point.
11427
11428(define_insn "blockage"
615158e2 11429 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 11430 ""
11431 "")
1fd4e8c1
RK		 11432\f
11433;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 11434;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 11435;;
11436;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11437;; insns, and branches. We store the operands of compares until we see
11438;; how it is used.
4ae234b0 11439(define_expand "cmp<mode>"
1fd4e8c1 11440 [(set (cc0)
4ae234b0
GK		 11441 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11442 (match_operand:GPR 1 "reg_or_short_operand" "")))]
1fd4e8c1
RK		 11443 ""
11444 "
11445{
11446 /* Take care of the possibility that operands[1] might be negative but
11447 this might be a logical operation. That insn doesn't exist. */
11448 if (GET_CODE (operands[1]) == CONST_INT
11449 && INTVAL (operands[1]) < 0)
4ae234b0 11450 operands[1] = force_reg (<MODE>mode, operands[1]);
1fd4e8c1
RK		 11451
11452 rs6000_compare_op0 = operands[0];
11453 rs6000_compare_op1 = operands[1];
11454 rs6000_compare_fp_p = 0;
11455 DONE;
11456}")
11457
4ae234b0
GK		 11458(define_expand "cmp<mode>"
11459 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11460 (match_operand:FP 1 "gpc_reg_operand" "")))]
11461 ""
d6f99ca4
DE		 11462 "
11463{
11464 rs6000_compare_op0 = operands[0];
11465 rs6000_compare_op1 = operands[1];
11466 rs6000_compare_fp_p = 1;
11467 DONE;
11468}")
11469
1fd4e8c1 11470(define_expand "beq"
39a10a29 11471 [(use (match_operand 0 "" ""))]
1fd4e8c1 11472 ""
39a10a29 11473 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11474
11475(define_expand "bne"
39a10a29 11476 [(use (match_operand 0 "" ""))]
1fd4e8c1 11477 ""
39a10a29 11478 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
1fd4e8c1 11479
39a10a29
GK		 11480(define_expand "bge"
11481 [(use (match_operand 0 "" ""))]
1fd4e8c1 11482 ""
39a10a29 11483 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
1fd4e8c1
RK		 11484
11485(define_expand "bgt"
39a10a29 11486 [(use (match_operand 0 "" ""))]
1fd4e8c1 11487 ""
39a10a29 11488 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
1fd4e8c1
RK		 11489
11490(define_expand "ble"
39a10a29 11491 [(use (match_operand 0 "" ""))]
1fd4e8c1 11492 ""
39a10a29 11493 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
1fd4e8c1 11494
39a10a29
GK		 11495(define_expand "blt"
11496 [(use (match_operand 0 "" ""))]
1fd4e8c1 11497 ""
39a10a29 11498 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
1fd4e8c1 11499
39a10a29
GK		 11500(define_expand "bgeu"
11501 [(use (match_operand 0 "" ""))]
1fd4e8c1 11502 ""
39a10a29 11503 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
1fd4e8c1 11504
39a10a29
GK		 11505(define_expand "bgtu"
11506 [(use (match_operand 0 "" ""))]
1fd4e8c1 11507 ""
39a10a29 11508 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
1fd4e8c1 11509
39a10a29
GK		 11510(define_expand "bleu"
11511 [(use (match_operand 0 "" ""))]
1fd4e8c1 11512 ""
39a10a29 11513 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
1fd4e8c1 11514
39a10a29
GK		 11515(define_expand "bltu"
11516 [(use (match_operand 0 "" ""))]
1fd4e8c1 11517 ""
39a10a29 11518 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
1fd4e8c1 11519
1c882ea4 11520(define_expand "bunordered"
39a10a29 11521 [(use (match_operand 0 "" ""))]
8ef65e3d 11522 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11523 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11524
11525(define_expand "bordered"
39a10a29 11526 [(use (match_operand 0 "" ""))]
8ef65e3d 11527 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11528 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11529
11530(define_expand "buneq"
39a10a29 11531 [(use (match_operand 0 "" ""))]
1c882ea4 11532 ""
39a10a29 11533 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
1c882ea4
GK		 11534
11535(define_expand "bunge"
39a10a29 11536 [(use (match_operand 0 "" ""))]
1c882ea4 11537 ""
39a10a29 11538 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
1c882ea4
GK		 11539
11540(define_expand "bungt"
39a10a29 11541 [(use (match_operand 0 "" ""))]
1c882ea4 11542 ""
39a10a29 11543 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
1c882ea4
GK		 11544
11545(define_expand "bunle"
39a10a29 11546 [(use (match_operand 0 "" ""))]
1c882ea4 11547 ""
39a10a29 11548 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
1c882ea4
GK		 11549
11550(define_expand "bunlt"
39a10a29 11551 [(use (match_operand 0 "" ""))]
1c882ea4 11552 ""
39a10a29 11553 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
1c882ea4
GK		 11554
11555(define_expand "bltgt"
39a10a29 11556 [(use (match_operand 0 "" ""))]
1c882ea4 11557 ""
39a10a29 11558 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
1c882ea4 11559
1fd4e8c1
RK		 11560;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11561;; For SEQ, likewise, except that comparisons with zero should be done
11562;; with an scc insns. However, due to the order that combine see the
11563;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11564;; the cases we don't want to handle.
11565(define_expand "seq"
39a10a29 11566 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11567 ""
39a10a29 11568 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11569
11570(define_expand "sne"
39a10a29 11571 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11572 ""
11573 "
6ae08853 11574{
39a10a29 11575 if (! rs6000_compare_fp_p)
1fd4e8c1
RK		 11576 FAIL;
11577
6ae08853 11578 rs6000_emit_sCOND (NE, operands[0]);
39a10a29 11579 DONE;
1fd4e8c1
RK		 11580}")
11581
b7053a3f
GK		 11582;; A >= 0 is best done the portable way for A an integer.
11583(define_expand "sge"
39a10a29 11584 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11585 ""
11586 "
5638268e 11587{
e56d7409 11588 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11589 FAIL;
11590
b7053a3f 11591 rs6000_emit_sCOND (GE, operands[0]);
39a10a29 11592 DONE;
1fd4e8c1
RK		 11593}")
11594
b7053a3f
GK		 11595;; A > 0 is best done using the portable sequence, so fail in that case.
11596(define_expand "sgt"
39a10a29 11597 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11598 ""
11599 "
5638268e 11600{
e56d7409 11601 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11602 FAIL;
11603
6ae08853 11604 rs6000_emit_sCOND (GT, operands[0]);
39a10a29 11605 DONE;
1fd4e8c1
RK		 11606}")
11607
b7053a3f
GK		 11608;; A <= 0 is best done the portable way for A an integer.
11609(define_expand "sle"
39a10a29 11610 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11611 ""
5638268e
DE		 11612 "
11613{
e56d7409 11614 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5638268e
DE		 11615 FAIL;
11616
6ae08853 11617 rs6000_emit_sCOND (LE, operands[0]);
5638268e
DE		 11618 DONE;
11619}")
1fd4e8c1 11620
b7053a3f
GK		 11621;; A < 0 is best done in the portable way for A an integer.
11622(define_expand "slt"
39a10a29 11623 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11624 ""
11625 "
5638268e 11626{
e56d7409 11627 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11628 FAIL;
11629
6ae08853 11630 rs6000_emit_sCOND (LT, operands[0]);
39a10a29 11631 DONE;
1fd4e8c1
RK		 11632}")
11633
b7053a3f
GK		 11634(define_expand "sgeu"
11635 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11636 ""
11637 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11638
1fd4e8c1 11639(define_expand "sgtu"
39a10a29 11640 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11641 ""
39a10a29 11642 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
1fd4e8c1 11643
b7053a3f
GK		 11644(define_expand "sleu"
11645 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11646 ""
11647 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11648
1fd4e8c1 11649(define_expand "sltu"
39a10a29 11650 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11651 ""
39a10a29 11652 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
1fd4e8c1 11653
b7053a3f 11654(define_expand "sunordered"
39a10a29 11655 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11656 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f 11657 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
1fd4e8c1 11658
b7053a3f 11659(define_expand "sordered"
39a10a29 11660 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11661 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11662 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11663
11664(define_expand "suneq"
11665 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11666 ""
11667 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11668
11669(define_expand "sunge"
11670 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11671 ""
11672 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11673
11674(define_expand "sungt"
11675 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11676 ""
11677 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11678
11679(define_expand "sunle"
11680 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11681 ""
11682 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11683
11684(define_expand "sunlt"
11685 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11686 ""
11687 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11688
11689(define_expand "sltgt"
11690 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11691 ""
11692 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11693
3aebbe5f
JJ		 11694(define_expand "stack_protect_set"
11695 [(match_operand 0 "memory_operand" "")
11696 (match_operand 1 "memory_operand" "")]
11697 ""
11698{
77008252
JJ		 11699#ifdef TARGET_THREAD_SSP_OFFSET
11700 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11701 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11702 operands[1] = gen_rtx_MEM (Pmode, addr);
11703#endif
3aebbe5f
JJ		 11704 if (TARGET_64BIT)
11705 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11706 else
11707 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11708 DONE;
11709})
11710
11711(define_insn "stack_protect_setsi"
11712 [(set (match_operand:SI 0 "memory_operand" "=m")
11713 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11714 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11715 "TARGET_32BIT"
11716 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11717 [(set_attr "type" "three")
11718 (set_attr "length" "12")])
11719
11720(define_insn "stack_protect_setdi"
11721 [(set (match_operand:DI 0 "memory_operand" "=m")
11722 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11723 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11724 "TARGET_64BIT"
11725 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11726 [(set_attr "type" "three")
11727 (set_attr "length" "12")])
11728
11729(define_expand "stack_protect_test"
11730 [(match_operand 0 "memory_operand" "")
11731 (match_operand 1 "memory_operand" "")
11732 (match_operand 2 "" "")]
11733 ""
11734{
77008252
JJ		 11735#ifdef TARGET_THREAD_SSP_OFFSET
11736 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11737 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11738 operands[1] = gen_rtx_MEM (Pmode, addr);
11739#endif
3aebbe5f
JJ		 11740 rs6000_compare_op0 = operands[0];
11741 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11742 UNSPEC_SP_TEST);
11743 rs6000_compare_fp_p = 0;
11744 emit_jump_insn (gen_beq (operands[2]));
11745 DONE;
11746})
11747
11748(define_insn "stack_protect_testsi"
11749 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11750 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11751 (match_operand:SI 2 "memory_operand" "m,m")]
11752 UNSPEC_SP_TEST))
41f12ed0
JJ		 11753 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11754 (clobber (match_scratch:SI 3 "=&r,&r"))]
3aebbe5f
JJ		 11755 "TARGET_32BIT"
11756 "@
11757 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11758 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11759 [(set_attr "length" "16,20")])
11760
11761(define_insn "stack_protect_testdi"
11762 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11763 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11764 (match_operand:DI 2 "memory_operand" "m,m")]
11765 UNSPEC_SP_TEST))
41f12ed0
JJ		 11766 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11767 (clobber (match_scratch:DI 3 "=&r,&r"))]
3aebbe5f
JJ		 11768 "TARGET_64BIT"
11769 "@
11770 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11771 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11772 [(set_attr "length" "16,20")])
11773
1fd4e8c1
RK		 11774\f
11775;; Here are the actual compare insns.
4ae234b0 11776(define_insn "*cmp<mode>_internal1"
1fd4e8c1 11777 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
4ae234b0
GK		 11778 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11779 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
1fd4e8c1 11780 ""
4ae234b0 11781 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
b54cf83a 11782 [(set_attr "type" "cmp")])
266eb58a 11783
f357808b 11784;; If we are comparing a register for equality with a large constant,
28d0e143
PB		 11785;; we can do this with an XOR followed by a compare. But this is profitable
11786;; only if the large constant is only used for the comparison (and in this
11787;; case we already have a register to reuse as scratch).
130869aa
PB		 11788;;
11789;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11790;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
f357808b 11791
28d0e143 11792(define_peephole2
130869aa 11793 [(set (match_operand:SI 0 "register_operand")
410c459d 11794 (match_operand:SI 1 "logical_const_operand" ""))
130869aa 11795 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
28d0e143 11796 [(match_dup 0)
410c459d 11797 (match_operand:SI 2 "logical_const_operand" "")]))
28d0e143 11798 (set (match_operand:CC 4 "cc_reg_operand" "")
130869aa 11799 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
28d0e143
PB		 11800 (match_dup 0)))
11801 (set (pc)
11802 (if_then_else (match_operator 6 "equality_operator"
11803 [(match_dup 4) (const_int 0)])
11804 (match_operand 7 "" "")
11805 (match_operand 8 "" "")))]
130869aa
PB		 11806 "peep2_reg_dead_p (3, operands[0])
11807 && peep2_reg_dead_p (4, operands[4])"
11808 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
28d0e143
PB		 11809 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11810 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11811
11812{
11813 /* Get the constant we are comparing against, and see what it looks like
11814 when sign-extended from 16 to 32 bits. Then see what constant we could
11815 XOR with SEXTC to get the sign-extended value. */
11816 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
130869aa 11817 SImode,
28d0e143
PB		 11818 operands[1], operands[2]);
11819 HOST_WIDE_INT c = INTVAL (cnst);
a65c591c 11820 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 11821 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 11822
28d0e143
PB		 11823 operands[9] = GEN_INT (xorv);
11824 operands[10] = GEN_INT (sextc);
11825})
f357808b 11826
acad7ed3 11827(define_insn "*cmpsi_internal2"
1fd4e8c1 11828 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 11829 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 11830 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 11831 ""
e2c953b6 11832 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 11833 [(set_attr "type" "cmp")])
1fd4e8c1 11834
acad7ed3 11835(define_insn "*cmpdi_internal2"
266eb58a
DE		 11836 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11837 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 11838 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 11839 ""
e2c953b6 11840 "cmpld%I2 %0,%1,%b2"
b54cf83a 11841 [(set_attr "type" "cmp")])
266eb58a 11842
1fd4e8c1
RK		 11843;; The following two insns don't exist as single insns, but if we provide
11844;; them, we can swap an add and compare, which will enable us to overlap more
11845;; of the required delay between a compare and branch. We generate code for
11846;; them by splitting.
11847
11848(define_insn ""
11849 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 11850 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11851 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 11852 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11853 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11854 ""
baf97f86
RK		 11855 "#"
11856 [(set_attr "length" "8")])
7e69e155 11857
1fd4e8c1
RK		 11858(define_insn ""
11859 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 11860 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11861 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 11862 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11863 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11864 ""
baf97f86
RK		 11865 "#"
11866 [(set_attr "length" "8")])
7e69e155 11867
1fd4e8c1
RK		 11868(define_split
11869 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 11870 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11871 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 11872 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11873 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11874 ""
11875 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11876 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11877
11878(define_split
11879 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 11880 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11881 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 11882 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11883 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11884 ""
11885 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11886 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11887
acad7ed3 11888(define_insn "*cmpsf_internal1"
1fd4e8c1 11889 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11890 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11891 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 11892 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11893 "fcmpu %0,%1,%2"
11894 [(set_attr "type" "fpcompare")])
11895
acad7ed3 11896(define_insn "*cmpdf_internal1"
1fd4e8c1 11897 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11898 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11899 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 11900 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11901 "fcmpu %0,%1,%2"
11902 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 11903
11904;; Only need to compare second words if first words equal
11905(define_insn "*cmptf_internal1"
11906 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11907 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11908 (match_operand:TF 2 "gpc_reg_operand" "f")))]
602ea4d3 11909 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
39e63627 11910 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 11911 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 11912 [(set_attr "type" "fpcompare")
11913 (set_attr "length" "12")])
de17c25f
DE		 11914
11915(define_insn_and_split "*cmptf_internal2"
11916 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11917 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11918 (match_operand:TF 2 "gpc_reg_operand" "f")))
11919 (clobber (match_scratch:DF 3 "=f"))
11920 (clobber (match_scratch:DF 4 "=f"))
11921 (clobber (match_scratch:DF 5 "=f"))
11922 (clobber (match_scratch:DF 6 "=f"))
11923 (clobber (match_scratch:DF 7 "=f"))
11924 (clobber (match_scratch:DF 8 "=f"))
11925 (clobber (match_scratch:DF 9 "=f"))
11926 (clobber (match_scratch:DF 10 "=f"))]
602ea4d3 11927 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
de17c25f
DE		 11928 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11929 "#"
11930 "&& reload_completed"
11931 [(set (match_dup 3) (match_dup 13))
11932 (set (match_dup 4) (match_dup 14))
11933 (set (match_dup 9) (abs:DF (match_dup 5)))
11934 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11935 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11936 (label_ref (match_dup 11))
11937 (pc)))
11938 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11939 (set (pc) (label_ref (match_dup 12)))
11940 (match_dup 11)
11941 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11942 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11943 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11944 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11945 (match_dup 12)]
11946{
11947 REAL_VALUE_TYPE rv;
11948 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11949 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11950
11951 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11952 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11953 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11954 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11955 operands[11] = gen_label_rtx ();
11956 operands[12] = gen_label_rtx ();
11957 real_inf (&rv);
11958 operands[13] = force_const_mem (DFmode,
11959 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11960 operands[14] = force_const_mem (DFmode,
11961 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11962 DFmode));
11963 if (TARGET_TOC)
11964 {
11965 operands[13] = gen_const_mem (DFmode,
11966 create_TOC_reference (XEXP (operands[13], 0)));
11967 operands[14] = gen_const_mem (DFmode,
11968 create_TOC_reference (XEXP (operands[14], 0)));
11969 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11970 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11971 }
11972})
1fd4e8c1
RK		 11973\f
11974;; Now we have the scc insns. We can do some combinations because of the
11975;; way the machine works.
11976;;
11977;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 11978;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11979;; cases the insns below which don't use an intermediate CR field will
11980;; be used instead.
1fd4e8c1 11981(define_insn ""
cd2b37d9 11982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11983 (match_operator:SI 1 "scc_comparison_operator"
11984 [(match_operand 2 "cc_reg_operand" "y")
11985 (const_int 0)]))]
11986 ""
2c4a9cff
DE		 11987 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11988 [(set (attr "type")
11989 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11990 (const_string "mfcrf")
11991 ]
11992 (const_string "mfcr")))
c1618c0c 11993 (set_attr "length" "8")])
1fd4e8c1 11994
423c1189 11995;; Same as above, but get the GT bit.
64022b5d 11996(define_insn "move_from_CR_gt_bit"
423c1189 11997 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
64022b5d 11998 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
423c1189 11999 "TARGET_E500"
64022b5d 12000 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
423c1189 12001 [(set_attr "type" "mfcr")
c1618c0c 12002 (set_attr "length" "8")])
423c1189 12003
a3170dc6
AH		 12004;; Same as above, but get the OV/ORDERED bit.
12005(define_insn "move_from_CR_ov_bit"
12006 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 12007 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 12008 "TARGET_ISEL"
b7053a3f 12009 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a 12010 [(set_attr "type" "mfcr")
c1618c0c 12011 (set_attr "length" "8")])
a3170dc6 12012
1fd4e8c1 12013(define_insn ""
9ebbca7d
GK		 12014 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12015 (match_operator:DI 1 "scc_comparison_operator"
12016 [(match_operand 2 "cc_reg_operand" "y")
12017 (const_int 0)]))]
12018 "TARGET_POWERPC64"
2c4a9cff
DE		 12019 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12020 [(set (attr "type")
12021 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12022 (const_string "mfcrf")
12023 ]
12024 (const_string "mfcr")))
c1618c0c 12025 (set_attr "length" "8")])
9ebbca7d
GK		 12026
12027(define_insn ""
12028 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12029 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12030 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 12031 (const_int 0)])
12032 (const_int 0)))
9ebbca7d 12033 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 12034 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12035 "TARGET_32BIT"
9ebbca7d 12036 "@
2c4a9cff 12037 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 12038 #"
b19003d8 12039 [(set_attr "type" "delayed_compare")
c1618c0c 12040 (set_attr "length" "8,16")])
9ebbca7d
GK		 12041
12042(define_split
12043 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12044 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12045 [(match_operand 2 "cc_reg_operand" "")
12046 (const_int 0)])
12047 (const_int 0)))
12048 (set (match_operand:SI 3 "gpc_reg_operand" "")
12049 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12050 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12051 [(set (match_dup 3)
12052 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12053 (set (match_dup 0)
12054 (compare:CC (match_dup 3)
12055 (const_int 0)))]
12056 "")
1fd4e8c1
RK		 12057
12058(define_insn ""
cd2b37d9 12059 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12060 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12061 [(match_operand 2 "cc_reg_operand" "y")
12062 (const_int 0)])
12063 (match_operand:SI 3 "const_int_operand" "n")))]
12064 ""
12065 "*
12066{
12067 int is_bit = ccr_bit (operands[1], 1);
12068 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12069 int count;
12070
12071 if (is_bit >= put_bit)
12072 count = is_bit - put_bit;
12073 else
12074 count = 32 - (put_bit - is_bit);
12075
89e9f3a8
MM		 12076 operands[4] = GEN_INT (count);
12077 operands[5] = GEN_INT (put_bit);
1fd4e8c1 12078
2c4a9cff 12079 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 12080}"
2c4a9cff
DE		 12081 [(set (attr "type")
12082 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12083 (const_string "mfcrf")
12084 ]
12085 (const_string "mfcr")))
c1618c0c 12086 (set_attr "length" "8")])
1fd4e8c1
RK		 12087
12088(define_insn ""
9ebbca7d 12089 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12090 (compare:CC
12091 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12092 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 12093 (const_int 0)])
9ebbca7d 12094 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 12095 (const_int 0)))
9ebbca7d 12096 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12097 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12098 (match_dup 3)))]
ce71f754 12099 ""
1fd4e8c1
RK		 12100 "*
12101{
12102 int is_bit = ccr_bit (operands[1], 1);
12103 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12104 int count;
12105
9ebbca7d
GK		 12106 /* Force split for non-cc0 compare. */
12107 if (which_alternative == 1)
12108 return \"#\";
12109
1fd4e8c1
RK		 12110 if (is_bit >= put_bit)
12111 count = is_bit - put_bit;
12112 else
12113 count = 32 - (put_bit - is_bit);
12114
89e9f3a8
MM		 12115 operands[5] = GEN_INT (count);
12116 operands[6] = GEN_INT (put_bit);
1fd4e8c1 12117
2c4a9cff 12118 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 12119}"
b19003d8 12120 [(set_attr "type" "delayed_compare")
c1618c0c 12121 (set_attr "length" "8,16")])
9ebbca7d
GK		 12122
12123(define_split
12124 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12125 (compare:CC
12126 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12127 [(match_operand 2 "cc_reg_operand" "")
12128 (const_int 0)])
12129 (match_operand:SI 3 "const_int_operand" ""))
12130 (const_int 0)))
12131 (set (match_operand:SI 4 "gpc_reg_operand" "")
12132 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12133 (match_dup 3)))]
ce71f754 12134 "reload_completed"
9ebbca7d
GK		 12135 [(set (match_dup 4)
12136 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12137 (match_dup 3)))
12138 (set (match_dup 0)
12139 (compare:CC (match_dup 4)
12140 (const_int 0)))]
12141 "")
1fd4e8c1 12142
c5defebb
RK		 12143;; There is a 3 cycle delay between consecutive mfcr instructions
12144;; so it is useful to combine 2 scc instructions to use only one mfcr.
12145
12146(define_peephole
cd2b37d9 12147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 12148 (match_operator:SI 1 "scc_comparison_operator"
12149 [(match_operand 2 "cc_reg_operand" "y")
12150 (const_int 0)]))
cd2b37d9 12151 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 12152 (match_operator:SI 4 "scc_comparison_operator"
12153 [(match_operand 5 "cc_reg_operand" "y")
12154 (const_int 0)]))]
309323c2 12155 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12156 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12157 [(set_attr "type" "mfcr")
c1618c0c 12158 (set_attr "length" "12")])
c5defebb 12159
9ebbca7d
GK		 12160(define_peephole
12161 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12162 (match_operator:DI 1 "scc_comparison_operator"
12163 [(match_operand 2 "cc_reg_operand" "y")
12164 (const_int 0)]))
12165 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12166 (match_operator:DI 4 "scc_comparison_operator"
12167 [(match_operand 5 "cc_reg_operand" "y")
12168 (const_int 0)]))]
309323c2 12169 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12170 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12171 [(set_attr "type" "mfcr")
c1618c0c 12172 (set_attr "length" "12")])
9ebbca7d 12173
1fd4e8c1
RK		 12174;; There are some scc insns that can be done directly, without a compare.
12175;; These are faster because they don't involve the communications between
12176;; the FXU and branch units. In fact, we will be replacing all of the
12177;; integer scc insns here or in the portable methods in emit_store_flag.
12178;;
12179;; Also support (neg (scc ..)) since that construct is used to replace
12180;; branches, (plus (scc ..) ..) since that construct is common and
12181;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12182;; cases where it is no more expensive than (neg (scc ..)).
12183
12184;; Have reload force a constant into a register for the simple insns that
12185;; otherwise won't accept constants. We do this because it is faster than
12186;; the cmp/mfcr sequence we would otherwise generate.
12187
e9441276
DE		 12188(define_mode_attr scc_eq_op2 [(SI "rKLI")
12189 (DI "rKJI")])
a260abc9 12190
e9441276
DE		 12191(define_insn_and_split "*eq<mode>"
12192 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12193 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
d0515b39 12194 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
27f0fe7f 12195 "!TARGET_POWER"
e9441276 12196 "#"
27f0fe7f 12197 "!TARGET_POWER"
d0515b39
DE		 12198 [(set (match_dup 0)
12199 (clz:GPR (match_dup 3)))
70ae0191 12200 (set (match_dup 0)
d0515b39 12201 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
70ae0191 12202 {
e9441276
DE		 12203 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12204 {
d0515b39
DE		 12205 /* Use output operand as intermediate. */
12206 operands[3] = operands[0];
12207
e9441276 12208 if (logical_operand (operands[2], <MODE>mode))
d0515b39 12209 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12210 gen_rtx_XOR (<MODE>mode,
12211 operands[1], operands[2])));
12212 else
d0515b39 12213 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12214 gen_rtx_PLUS (<MODE>mode, operands[1],
12215 negate_rtx (<MODE>mode,
12216 operands[2]))));
12217 }
12218 else
d0515b39 12219 operands[3] = operands[1];
9ebbca7d 12220
d0515b39 12221 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
e9441276 12222 })
a260abc9 12223
e9441276 12224(define_insn_and_split "*eq<mode>_compare"
d0515b39 12225 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
70ae0191 12226 (compare:CC
1fa5c709
DE		 12227 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12228 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
70ae0191 12229 (const_int 0)))
1fa5c709 12230 (set (match_operand:P 0 "gpc_reg_operand" "=r")
d0515b39 12231 (eq:P (match_dup 1) (match_dup 2)))]
27f0fe7f 12232 "!TARGET_POWER && optimize_size"
e9441276 12233 "#"
27f0fe7f 12234 "!TARGET_POWER && optimize_size"
d0515b39 12235 [(set (match_dup 0)
1fa5c709 12236 (clz:P (match_dup 4)))
d0515b39
DE		 12237 (parallel [(set (match_dup 3)
12238 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
70ae0191
DE		 12239 (const_int 0)))
12240 (set (match_dup 0)
d0515b39 12241 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
70ae0191 12242 {
e9441276
DE		 12243 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12244 {
d0515b39
DE		 12245 /* Use output operand as intermediate. */
12246 operands[4] = operands[0];
12247
e9441276
DE		 12248 if (logical_operand (operands[2], <MODE>mode))
12249 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12250 gen_rtx_XOR (<MODE>mode,
12251 operands[1], operands[2])));
12252 else
12253 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12254 gen_rtx_PLUS (<MODE>mode, operands[1],
12255 negate_rtx (<MODE>mode,
12256 operands[2]))));
12257 }
12258 else
12259 operands[4] = operands[1];
12260
d0515b39 12261 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
70ae0191
DE		 12262 })
12263
05f68097
DE		 12264(define_insn "*eqsi_power"
12265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12266 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12267 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12268 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12269 "TARGET_POWER"
12270 "@
12271 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12272 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12273 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12274 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12275 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12276 [(set_attr "type" "three,two,three,three,three")
12277 (set_attr "length" "12,8,12,12,12")])
12278
b19003d8
RK		 12279;; We have insns of the form shown by the first define_insn below. If
12280;; there is something inside the comparison operation, we must split it.
12281(define_split
12282 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12283 (plus:SI (match_operator 1 "comparison_operator"
12284 [(match_operand:SI 2 "" "")
12285 (match_operand:SI 3
12286 "reg_or_cint_operand" "")])
12287 (match_operand:SI 4 "gpc_reg_operand" "")))
12288 (clobber (match_operand:SI 5 "register_operand" ""))]
12289 "! gpc_reg_operand (operands[2], SImode)"
12290 [(set (match_dup 5) (match_dup 2))
12291 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12292 (match_dup 4)))])
1fd4e8c1 12293
297abd0d 12294(define_insn "*plus_eqsi"
5276df18 12295 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 12296 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
56fc483e 12297 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
5276df18 12298 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
59d6560b 12299 "TARGET_32BIT"
1fd4e8c1 12300 "@
5276df18
DE		 12301 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12302 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12303 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12304 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12305 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
943c15ed
DE		 12306 [(set_attr "type" "three,two,three,three,three")
12307 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1 12308
297abd0d 12309(define_insn "*compare_plus_eqsi"
9ebbca7d 12310 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12311 (compare:CC
1fd4e8c1 12312 (plus:SI
9ebbca7d 12313 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12314 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12315 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12316 (const_int 0)))
9ebbca7d 12317 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
297abd0d 12318 "TARGET_32BIT && optimize_size"
1fd4e8c1 12319 "@
ca7f5001 12320 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 12321 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 12322 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12323 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12324 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12325 #
12326 #
12327 #
12328 #
12329 #"
b19003d8 12330 [(set_attr "type" "compare")
9ebbca7d
GK		 12331 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12332
12333(define_split
12334 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12335 (compare:CC
12336 (plus:SI
12337 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12338 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12339 (match_operand:SI 3 "gpc_reg_operand" ""))
12340 (const_int 0)))
12341 (clobber (match_scratch:SI 4 ""))]
297abd0d 12342 "TARGET_32BIT && optimize_size && reload_completed"
9ebbca7d
GK		 12343 [(set (match_dup 4)
12344 (plus:SI (eq:SI (match_dup 1)
12345 (match_dup 2))
12346 (match_dup 3)))
12347 (set (match_dup 0)
12348 (compare:CC (match_dup 4)
12349 (const_int 0)))]
12350 "")
1fd4e8c1 12351
297abd0d 12352(define_insn "*plus_eqsi_compare"
0387639b 12353 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12354 (compare:CC
1fd4e8c1 12355 (plus:SI
9ebbca7d 12356 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12357 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12358 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12359 (const_int 0)))
0387639b
DE		 12360 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12361 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12362 "TARGET_32BIT && optimize_size"
1fd4e8c1 12363 "@
0387639b
DE		 12364 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12365 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12366 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12367 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12368 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12369 #
12370 #
12371 #
12372 #
12373 #"
12374 [(set_attr "type" "compare")
12375 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12376
12377(define_split
0387639b 12378 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12379 (compare:CC
12380 (plus:SI
12381 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12382 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12383 (match_operand:SI 3 "gpc_reg_operand" ""))
12384 (const_int 0)))
12385 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 12386 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12387 "TARGET_32BIT && optimize_size && reload_completed"
0387639b 12388 [(set (match_dup 0)
9ebbca7d 12389 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 12390 (set (match_dup 4)
9ebbca7d
GK		 12391 (compare:CC (match_dup 0)
12392 (const_int 0)))]
12393 "")
12394
d0515b39
DE		 12395(define_insn "*neg_eq0<mode>"
12396 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12397 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12398 (const_int 0))))]
59d6560b 12399 ""
d0515b39
DE		 12400 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12401 [(set_attr "type" "two")
12402 (set_attr "length" "8")])
12403
12404(define_insn_and_split "*neg_eq<mode>"
12405 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12406 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12407 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
59d6560b 12408 ""
d0515b39 12409 "#"
59d6560b 12410 ""
d0515b39
DE		 12411 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12412 {
12413 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12414 {
12415 /* Use output operand as intermediate. */
12416 operands[3] = operands[0];
12417
12418 if (logical_operand (operands[2], <MODE>mode))
12419 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12420 gen_rtx_XOR (<MODE>mode,
12421 operands[1], operands[2])));
12422 else
12423 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12424 gen_rtx_PLUS (<MODE>mode, operands[1],
12425 negate_rtx (<MODE>mode,
12426 operands[2]))));
12427 }
12428 else
12429 operands[3] = operands[1];
12430 })
1fd4e8c1 12431
ea9be077
MM		 12432;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12433;; since it nabs/sr is just as fast.
ce45ef46 12434(define_insn "*ne0si"
b4e95693 12435 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 12436 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12437 (const_int 31)))
12438 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 12439 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077 12440 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
943c15ed
DE		 12441 [(set_attr "type" "two")
12442 (set_attr "length" "8")])
ea9be077 12443
ce45ef46 12444(define_insn "*ne0di"
a260abc9
DE		 12445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12446 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12447 (const_int 63)))
12448 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 12449 "TARGET_64BIT"
a260abc9 12450 "addic %2,%1,-1\;subfe %0,%2,%1"
943c15ed
DE		 12451 [(set_attr "type" "two")
12452 (set_attr "length" "8")])
a260abc9 12453
1fd4e8c1 12454;; This is what (plus (ne X (const_int 0)) Y) looks like.
297abd0d 12455(define_insn "*plus_ne0si"
cd2b37d9 12456 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 12457 (plus:SI (lshiftrt:SI
cd2b37d9 12458 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 12459 (const_int 31))
cd2b37d9 12460 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 12461 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 12462 "TARGET_32BIT"
ca7f5001 12463 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
943c15ed
DE		 12464 [(set_attr "type" "two")
12465 (set_attr "length" "8")])
1fd4e8c1 12466
297abd0d 12467(define_insn "*plus_ne0di"
a260abc9
DE		 12468 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12469 (plus:DI (lshiftrt:DI
12470 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12471 (const_int 63))
12472 (match_operand:DI 2 "gpc_reg_operand" "r")))
12473 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 12474 "TARGET_64BIT"
a260abc9 12475 "addic %3,%1,-1\;addze %0,%2"
943c15ed
DE		 12476 [(set_attr "type" "two")
12477 (set_attr "length" "8")])
a260abc9 12478
297abd0d 12479(define_insn "*compare_plus_ne0si"
9ebbca7d 12480 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12481 (compare:CC
12482 (plus:SI (lshiftrt:SI
9ebbca7d 12483 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12484 (const_int 31))
9ebbca7d 12485 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12486 (const_int 0)))
889b90a1
GK		 12487 (clobber (match_scratch:SI 3 "=&r,&r"))
12488 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 12489 "TARGET_32BIT"
9ebbca7d
GK		 12490 "@
12491 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12492 #"
b19003d8 12493 [(set_attr "type" "compare")
9ebbca7d
GK		 12494 (set_attr "length" "8,12")])
12495
12496(define_split
12497 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12498 (compare:CC
12499 (plus:SI (lshiftrt:SI
12500 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12501 (const_int 31))
12502 (match_operand:SI 2 "gpc_reg_operand" ""))
12503 (const_int 0)))
889b90a1
GK		 12504 (clobber (match_scratch:SI 3 ""))
12505 (clobber (match_scratch:SI 4 ""))]
683bdff7 12506 "TARGET_32BIT && reload_completed"
889b90a1 12507 [(parallel [(set (match_dup 3)
ce71f754
AM		 12508 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12509 (const_int 31))
12510 (match_dup 2)))
889b90a1 12511 (clobber (match_dup 4))])
9ebbca7d
GK		 12512 (set (match_dup 0)
12513 (compare:CC (match_dup 3)
12514 (const_int 0)))]
12515 "")
1fd4e8c1 12516
297abd0d 12517(define_insn "*compare_plus_ne0di"
9ebbca7d 12518 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12519 (compare:CC
12520 (plus:DI (lshiftrt:DI
9ebbca7d 12521 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12522 (const_int 63))
9ebbca7d 12523 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12524 (const_int 0)))
9ebbca7d 12525 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12526 "TARGET_64BIT"
9ebbca7d
GK		 12527 "@
12528 addic %3,%1,-1\;addze. %3,%2
12529 #"
a260abc9 12530 [(set_attr "type" "compare")
9ebbca7d
GK		 12531 (set_attr "length" "8,12")])
12532
12533(define_split
12534 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12535 (compare:CC
12536 (plus:DI (lshiftrt:DI
12537 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12538 (const_int 63))
12539 (match_operand:DI 2 "gpc_reg_operand" ""))
12540 (const_int 0)))
12541 (clobber (match_scratch:DI 3 ""))]
683bdff7 12542 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12543 [(set (match_dup 3)
12544 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12545 (const_int 63))
12546 (match_dup 2)))
12547 (set (match_dup 0)
12548 (compare:CC (match_dup 3)
12549 (const_int 0)))]
12550 "")
a260abc9 12551
297abd0d 12552(define_insn "*plus_ne0si_compare"
9ebbca7d 12553 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12554 (compare:CC
12555 (plus:SI (lshiftrt:SI
9ebbca7d 12556 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12557 (const_int 31))
9ebbca7d 12558 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12559 (const_int 0)))
9ebbca7d 12560 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12561 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12562 (match_dup 2)))
9ebbca7d 12563 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 12564 "TARGET_32BIT"
9ebbca7d
GK		 12565 "@
12566 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12567 #"
b19003d8 12568 [(set_attr "type" "compare")
9ebbca7d
GK		 12569 (set_attr "length" "8,12")])
12570
12571(define_split
12572 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12573 (compare:CC
12574 (plus:SI (lshiftrt:SI
12575 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12576 (const_int 31))
12577 (match_operand:SI 2 "gpc_reg_operand" ""))
12578 (const_int 0)))
12579 (set (match_operand:SI 0 "gpc_reg_operand" "")
12580 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12581 (match_dup 2)))
12582 (clobber (match_scratch:SI 3 ""))]
683bdff7 12583 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12584 [(parallel [(set (match_dup 0)
12585 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12586 (match_dup 2)))
12587 (clobber (match_dup 3))])
12588 (set (match_dup 4)
12589 (compare:CC (match_dup 0)
12590 (const_int 0)))]
12591 "")
1fd4e8c1 12592
297abd0d 12593(define_insn "*plus_ne0di_compare"
9ebbca7d 12594 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12595 (compare:CC
12596 (plus:DI (lshiftrt:DI
9ebbca7d 12597 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12598 (const_int 63))
9ebbca7d 12599 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12600 (const_int 0)))
9ebbca7d 12601 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 12602 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12603 (match_dup 2)))
9ebbca7d 12604 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12605 "TARGET_64BIT"
9ebbca7d
GK		 12606 "@
12607 addic %3,%1,-1\;addze. %0,%2
12608 #"
a260abc9 12609 [(set_attr "type" "compare")
9ebbca7d
GK		 12610 (set_attr "length" "8,12")])
12611
12612(define_split
12613 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12614 (compare:CC
12615 (plus:DI (lshiftrt:DI
12616 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12617 (const_int 63))
12618 (match_operand:DI 2 "gpc_reg_operand" ""))
12619 (const_int 0)))
12620 (set (match_operand:DI 0 "gpc_reg_operand" "")
12621 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12622 (match_dup 2)))
12623 (clobber (match_scratch:DI 3 ""))]
683bdff7 12624 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12625 [(parallel [(set (match_dup 0)
12626 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12627 (match_dup 2)))
12628 (clobber (match_dup 3))])
12629 (set (match_dup 4)
12630 (compare:CC (match_dup 0)
12631 (const_int 0)))]
12632 "")
a260abc9 12633
1fd4e8c1 12634(define_insn ""
cd2b37d9
RK		 12635 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12636 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 12637 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12638 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 12639 "TARGET_POWER"
1fd4e8c1 12640 "@
ca7f5001 12641 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 12642 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12643 [(set_attr "length" "12")])
1fd4e8c1
RK		 12644
12645(define_insn ""
9ebbca7d 12646 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12647 (compare:CC
9ebbca7d
GK		 12648 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12649 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 12650 (const_int 0)))
9ebbca7d 12651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12652 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12653 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 12654 "TARGET_POWER"
1fd4e8c1 12655 "@
ca7f5001 12656 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 12657 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12658 #
12659 #"
12660 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12661 (set_attr "length" "12,12,16,16")])
12662
12663(define_split
12664 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12665 (compare:CC
12666 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12667 (match_operand:SI 2 "reg_or_short_operand" ""))
12668 (const_int 0)))
12669 (set (match_operand:SI 0 "gpc_reg_operand" "")
12670 (le:SI (match_dup 1) (match_dup 2)))
12671 (clobber (match_scratch:SI 3 ""))]
12672 "TARGET_POWER && reload_completed"
12673 [(parallel [(set (match_dup 0)
12674 (le:SI (match_dup 1) (match_dup 2)))
12675 (clobber (match_dup 3))])
12676 (set (match_dup 4)
12677 (compare:CC (match_dup 0)
12678 (const_int 0)))]
12679 "")
1fd4e8c1
RK		 12680
12681(define_insn ""
097657c3 12682 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12683 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12684 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 12685 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 12686 "TARGET_POWER"
1fd4e8c1 12687 "@
097657c3
AM		 12688 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12689 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 12690 [(set_attr "length" "12")])
1fd4e8c1
RK		 12691
12692(define_insn ""
9ebbca7d 12693 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12694 (compare:CC
9ebbca7d
GK		 12695 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12696 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12697 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12698 (const_int 0)))
9ebbca7d 12699 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 12700 "TARGET_POWER"
1fd4e8c1 12701 "@
ca7f5001 12702 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12703 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12704 #
12705 #"
b19003d8 12706 [(set_attr "type" "compare")
9ebbca7d
GK		 12707 (set_attr "length" "12,12,16,16")])
12708
12709(define_split
12710 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12711 (compare:CC
12712 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12713 (match_operand:SI 2 "reg_or_short_operand" ""))
12714 (match_operand:SI 3 "gpc_reg_operand" ""))
12715 (const_int 0)))
12716 (clobber (match_scratch:SI 4 ""))]
12717 "TARGET_POWER && reload_completed"
12718 [(set (match_dup 4)
12719 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 12720 (match_dup 3)))
9ebbca7d
GK		 12721 (set (match_dup 0)
12722 (compare:CC (match_dup 4)
12723 (const_int 0)))]
12724 "")
1fd4e8c1
RK		 12725
12726(define_insn ""
097657c3 12727 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12728 (compare:CC
9ebbca7d
GK		 12729 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12730 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12731 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12732 (const_int 0)))
097657c3
AM		 12733 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12734 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12735 "TARGET_POWER"
1fd4e8c1 12736 "@
097657c3
AM		 12737 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12738 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12739 #
12740 #"
b19003d8 12741 [(set_attr "type" "compare")
9ebbca7d
GK		 12742 (set_attr "length" "12,12,16,16")])
12743
12744(define_split
097657c3 12745 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12746 (compare:CC
12747 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12748 (match_operand:SI 2 "reg_or_short_operand" ""))
12749 (match_operand:SI 3 "gpc_reg_operand" ""))
12750 (const_int 0)))
12751 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12752 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12753 "TARGET_POWER && reload_completed"
097657c3 12754 [(set (match_dup 0)
9ebbca7d 12755 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12756 (set (match_dup 4)
9ebbca7d
GK		 12757 (compare:CC (match_dup 0)
12758 (const_int 0)))]
12759 "")
1fd4e8c1
RK		 12760
12761(define_insn ""
cd2b37d9
RK		 12762 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12763 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12764 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 12765 "TARGET_POWER"
1fd4e8c1 12766 "@
ca7f5001
RK		 12767 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12768 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12769 [(set_attr "length" "12")])
1fd4e8c1 12770
a2dba291
DE		 12771(define_insn "*leu<mode>"
12772 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12773 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12774 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12775 ""
ca7f5001 12776 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 12777 [(set_attr "type" "three")
12778 (set_attr "length" "12")])
1fd4e8c1 12779
a2dba291 12780(define_insn "*leu<mode>_compare"
9ebbca7d 12781 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12782 (compare:CC
a2dba291
DE		 12783 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12784 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12785 (const_int 0)))
a2dba291
DE		 12786 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12787 (leu:P (match_dup 1) (match_dup 2)))]
12788 ""
9ebbca7d
GK		 12789 "@
12790 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12791 #"
b19003d8 12792 [(set_attr "type" "compare")
9ebbca7d
GK		 12793 (set_attr "length" "12,16")])
12794
12795(define_split
12796 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12797 (compare:CC
a2dba291
DE		 12798 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12799 (match_operand:P 2 "reg_or_short_operand" ""))
9ebbca7d 12800 (const_int 0)))
a2dba291
DE		 12801 (set (match_operand:P 0 "gpc_reg_operand" "")
12802 (leu:P (match_dup 1) (match_dup 2)))]
12803 "reload_completed"
9ebbca7d 12804 [(set (match_dup 0)
a2dba291 12805 (leu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 12806 (set (match_dup 3)
12807 (compare:CC (match_dup 0)
12808 (const_int 0)))]
12809 "")
1fd4e8c1 12810
a2dba291
DE		 12811(define_insn "*plus_leu<mode>"
12812 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12813 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12814 (match_operand:P 2 "reg_or_short_operand" "rI"))
12815 (match_operand:P 3 "gpc_reg_operand" "r")))]
12816 ""
80103f96 12817 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
943c15ed
DE		 12818 [(set_attr "type" "two")
12819 (set_attr "length" "8")])
1fd4e8c1
RK		 12820
12821(define_insn ""
9ebbca7d 12822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12823 (compare:CC
9ebbca7d
GK		 12824 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12825 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12826 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12827 (const_int 0)))
9ebbca7d 12828 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12829 "TARGET_32BIT"
9ebbca7d
GK		 12830 "@
12831 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12832 #"
b19003d8 12833 [(set_attr "type" "compare")
9ebbca7d
GK		 12834 (set_attr "length" "8,12")])
12835
12836(define_split
12837 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12838 (compare:CC
12839 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12840 (match_operand:SI 2 "reg_or_short_operand" ""))
12841 (match_operand:SI 3 "gpc_reg_operand" ""))
12842 (const_int 0)))
12843 (clobber (match_scratch:SI 4 ""))]
683bdff7 12844 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12845 [(set (match_dup 4)
12846 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12847 (match_dup 3)))
12848 (set (match_dup 0)
12849 (compare:CC (match_dup 4)
12850 (const_int 0)))]
12851 "")
1fd4e8c1
RK		 12852
12853(define_insn ""
097657c3 12854 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12855 (compare:CC
9ebbca7d
GK		 12856 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12857 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12858 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12859 (const_int 0)))
097657c3
AM		 12860 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12861 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12862 "TARGET_32BIT"
9ebbca7d 12863 "@
097657c3 12864 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 12865 #"
b19003d8 12866 [(set_attr "type" "compare")
9ebbca7d
GK		 12867 (set_attr "length" "8,12")])
12868
12869(define_split
097657c3 12870 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12871 (compare:CC
12872 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12873 (match_operand:SI 2 "reg_or_short_operand" ""))
12874 (match_operand:SI 3 "gpc_reg_operand" ""))
12875 (const_int 0)))
12876 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12877 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12878 "TARGET_32BIT && reload_completed"
097657c3 12879 [(set (match_dup 0)
9ebbca7d 12880 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12881 (set (match_dup 4)
9ebbca7d
GK		 12882 (compare:CC (match_dup 0)
12883 (const_int 0)))]
12884 "")
1fd4e8c1 12885
a2dba291
DE		 12886(define_insn "*neg_leu<mode>"
12887 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12888 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12889 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12890 ""
ca7f5001 12891 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
943c15ed
DE		 12892 [(set_attr "type" "three")
12893 (set_attr "length" "12")])
1fd4e8c1 12894
a2dba291
DE		 12895(define_insn "*and_neg_leu<mode>"
12896 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12897 (and:P (neg:P
12898 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12899 (match_operand:P 2 "reg_or_short_operand" "rI")))
12900 (match_operand:P 3 "gpc_reg_operand" "r")))]
12901 ""
097657c3 12902 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 12903 [(set_attr "type" "three")
12904 (set_attr "length" "12")])
1fd4e8c1
RK		 12905
12906(define_insn ""
9ebbca7d 12907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12908 (compare:CC
12909 (and:SI (neg:SI
9ebbca7d
GK		 12910 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12911 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12912 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12913 (const_int 0)))
9ebbca7d 12914 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12915 "TARGET_32BIT"
9ebbca7d
GK		 12916 "@
12917 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12918 #"
12919 [(set_attr "type" "compare")
12920 (set_attr "length" "12,16")])
12921
12922(define_split
12923 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12924 (compare:CC
12925 (and:SI (neg:SI
12926 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12927 (match_operand:SI 2 "reg_or_short_operand" "")))
12928 (match_operand:SI 3 "gpc_reg_operand" ""))
12929 (const_int 0)))
12930 (clobber (match_scratch:SI 4 ""))]
683bdff7 12931 "TARGET_32BIT && reload_completed"
9ebbca7d 12932 [(set (match_dup 4)
097657c3
AM		 12933 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12934 (match_dup 3)))
9ebbca7d
GK		 12935 (set (match_dup 0)
12936 (compare:CC (match_dup 4)
12937 (const_int 0)))]
12938 "")
1fd4e8c1
RK		 12939
12940(define_insn ""
097657c3 12941 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12942 (compare:CC
12943 (and:SI (neg:SI
9ebbca7d
GK		 12944 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12945 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12946 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12947 (const_int 0)))
097657c3
AM		 12948 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12949 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12950 "TARGET_32BIT"
9ebbca7d 12951 "@
097657c3 12952 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 12953 #"
b19003d8 12954 [(set_attr "type" "compare")
9ebbca7d
GK		 12955 (set_attr "length" "12,16")])
12956
12957(define_split
097657c3 12958 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12959 (compare:CC
12960 (and:SI (neg:SI
12961 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12962 (match_operand:SI 2 "reg_or_short_operand" "")))
12963 (match_operand:SI 3 "gpc_reg_operand" ""))
12964 (const_int 0)))
12965 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12966 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12967 "TARGET_32BIT && reload_completed"
097657c3
AM		 12968 [(set (match_dup 0)
12969 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12970 (match_dup 3)))
12971 (set (match_dup 4)
9ebbca7d
GK		 12972 (compare:CC (match_dup 0)
12973 (const_int 0)))]
12974 "")
1fd4e8c1
RK		 12975
12976(define_insn ""
cd2b37d9
RK		 12977 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12978 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12979 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 12980 "TARGET_POWER"
7f340546 12981 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12982 [(set_attr "length" "12")])
1fd4e8c1
RK		 12983
12984(define_insn ""
9ebbca7d 12985 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12986 (compare:CC
9ebbca7d
GK		 12987 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12988 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12989 (const_int 0)))
9ebbca7d 12990 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12991 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 12992 "TARGET_POWER"
9ebbca7d
GK		 12993 "@
12994 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12995 #"
29ae5b89 12996 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 12997 (set_attr "length" "12,16")])
12998
12999(define_split
13000 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13001 (compare:CC
13002 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13003 (match_operand:SI 2 "reg_or_short_operand" ""))
13004 (const_int 0)))
13005 (set (match_operand:SI 0 "gpc_reg_operand" "")
13006 (lt:SI (match_dup 1) (match_dup 2)))]
13007 "TARGET_POWER && reload_completed"
13008 [(set (match_dup 0)
13009 (lt:SI (match_dup 1) (match_dup 2)))
13010 (set (match_dup 3)
13011 (compare:CC (match_dup 0)
13012 (const_int 0)))]
13013 "")
1fd4e8c1
RK		 13014
13015(define_insn ""
097657c3 13016 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13017 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13018 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13019 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13020 "TARGET_POWER"
097657c3 13021 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13022 [(set_attr "length" "12")])
1fd4e8c1
RK		 13023
13024(define_insn ""
9ebbca7d 13025 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13026 (compare:CC
9ebbca7d
GK		 13027 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13028 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13029 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13030 (const_int 0)))
9ebbca7d 13031 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13032 "TARGET_POWER"
9ebbca7d
GK		 13033 "@
13034 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13035 #"
b19003d8 13036 [(set_attr "type" "compare")
9ebbca7d
GK		 13037 (set_attr "length" "12,16")])
13038
13039(define_split
13040 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13041 (compare:CC
13042 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13043 (match_operand:SI 2 "reg_or_short_operand" ""))
13044 (match_operand:SI 3 "gpc_reg_operand" ""))
13045 (const_int 0)))
13046 (clobber (match_scratch:SI 4 ""))]
13047 "TARGET_POWER && reload_completed"
13048 [(set (match_dup 4)
13049 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 13050 (match_dup 3)))
9ebbca7d
GK		 13051 (set (match_dup 0)
13052 (compare:CC (match_dup 4)
13053 (const_int 0)))]
13054 "")
1fd4e8c1
RK		 13055
13056(define_insn ""
097657c3 13057 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13058 (compare:CC
9ebbca7d
GK		 13059 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13060 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13061 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13062 (const_int 0)))
097657c3
AM		 13063 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13064 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13065 "TARGET_POWER"
9ebbca7d 13066 "@
097657c3 13067 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13068 #"
b19003d8 13069 [(set_attr "type" "compare")
9ebbca7d
GK		 13070 (set_attr "length" "12,16")])
13071
13072(define_split
097657c3 13073 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13074 (compare:CC
13075 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13076 (match_operand:SI 2 "reg_or_short_operand" ""))
13077 (match_operand:SI 3 "gpc_reg_operand" ""))
13078 (const_int 0)))
13079 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13080 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13081 "TARGET_POWER && reload_completed"
097657c3 13082 [(set (match_dup 0)
9ebbca7d 13083 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13084 (set (match_dup 4)
9ebbca7d
GK		 13085 (compare:CC (match_dup 0)
13086 (const_int 0)))]
13087 "")
1fd4e8c1
RK		 13088
13089(define_insn ""
cd2b37d9
RK		 13090 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13091 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13092 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13093 "TARGET_POWER"
13094 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13095 [(set_attr "length" "12")])
1fd4e8c1 13096
ce45ef46
DE		 13097(define_insn_and_split "*ltu<mode>"
13098 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13099 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13100 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13101 ""
c0600ecd 13102 "#"
ce45ef46
DE		 13103 ""
13104 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13105 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13106 "")
1fd4e8c1 13107
1e24ce83 13108(define_insn_and_split "*ltu<mode>_compare"
9ebbca7d 13109 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13110 (compare:CC
a2dba291
DE		 13111 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13112 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13113 (const_int 0)))
a2dba291
DE		 13114 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13115 (ltu:P (match_dup 1) (match_dup 2)))]
13116 ""
1e24ce83
DE		 13117 "#"
13118 ""
13119 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13120 (parallel [(set (match_dup 3)
13121 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13122 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13123 "")
1fd4e8c1 13124
a2dba291
DE		 13125(define_insn_and_split "*plus_ltu<mode>"
13126 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13127 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13128 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
1e24ce83 13129 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
a2dba291 13130 ""
c0600ecd 13131 "#"
04fa46cf 13132 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13133 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13134 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13135 "")
1fd4e8c1 13136
1e24ce83 13137(define_insn_and_split "*plus_ltu<mode>_compare"
097657c3 13138 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13139 (compare:CC
1e24ce83
DE		 13140 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13141 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13142 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13143 (const_int 0)))
1e24ce83
DE		 13144 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13145 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13146 ""
13147 "#"
13148 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13149 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13150 (parallel [(set (match_dup 4)
13151 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13152 (const_int 0)))
13153 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13154 "")
1fd4e8c1 13155
ce45ef46
DE		 13156(define_insn "*neg_ltu<mode>"
13157 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13158 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13159 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13160 ""
c0600ecd
DE		 13161 "@
13162 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13163 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
943c15ed 13164 [(set_attr "type" "two")
c0600ecd 13165 (set_attr "length" "8")])
1fd4e8c1
RK		 13166
13167(define_insn ""
cd2b37d9
RK		 13168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13169 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 13170 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13171 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 13172 "TARGET_POWER"
13173 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 13174 [(set_attr "length" "12")])
1fd4e8c1 13175
9ebbca7d
GK		 13176(define_insn ""
13177 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13178 (compare:CC
9ebbca7d
GK		 13179 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13180 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13181 (const_int 0)))
9ebbca7d 13182 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13183 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 13184 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 13185 "TARGET_POWER"
9ebbca7d
GK		 13186 "@
13187 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13188 #"
13189 [(set_attr "type" "compare")
13190 (set_attr "length" "12,16")])
13191
13192(define_split
13193 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13194 (compare:CC
13195 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13196 (match_operand:SI 2 "reg_or_short_operand" ""))
13197 (const_int 0)))
13198 (set (match_operand:SI 0 "gpc_reg_operand" "")
13199 (ge:SI (match_dup 1) (match_dup 2)))
13200 (clobber (match_scratch:SI 3 ""))]
13201 "TARGET_POWER && reload_completed"
13202 [(parallel [(set (match_dup 0)
097657c3
AM		 13203 (ge:SI (match_dup 1) (match_dup 2)))
13204 (clobber (match_dup 3))])
9ebbca7d
GK		 13205 (set (match_dup 4)
13206 (compare:CC (match_dup 0)
13207 (const_int 0)))]
13208 "")
13209
1fd4e8c1 13210(define_insn ""
097657c3 13211 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13212 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13213 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13214 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13215 "TARGET_POWER"
097657c3 13216 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 13217 [(set_attr "length" "12")])
1fd4e8c1
RK		 13218
13219(define_insn ""
9ebbca7d 13220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13221 (compare:CC
9ebbca7d
GK		 13222 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13223 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13224 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13225 (const_int 0)))
9ebbca7d 13226 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13227 "TARGET_POWER"
9ebbca7d
GK		 13228 "@
13229 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13230 #"
b19003d8 13231 [(set_attr "type" "compare")
9ebbca7d
GK		 13232 (set_attr "length" "12,16")])
13233
13234(define_split
13235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13236 (compare:CC
13237 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13238 (match_operand:SI 2 "reg_or_short_operand" ""))
13239 (match_operand:SI 3 "gpc_reg_operand" ""))
13240 (const_int 0)))
13241 (clobber (match_scratch:SI 4 ""))]
13242 "TARGET_POWER && reload_completed"
13243 [(set (match_dup 4)
13244 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 13245 (match_dup 3)))
9ebbca7d
GK		 13246 (set (match_dup 0)
13247 (compare:CC (match_dup 4)
13248 (const_int 0)))]
13249 "")
1fd4e8c1
RK		 13250
13251(define_insn ""
097657c3 13252 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13253 (compare:CC
9ebbca7d
GK		 13254 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13255 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13256 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13257 (const_int 0)))
097657c3
AM		 13258 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13259 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13260 "TARGET_POWER"
9ebbca7d 13261 "@
097657c3 13262 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 13263 #"
b19003d8 13264 [(set_attr "type" "compare")
9ebbca7d
GK		 13265 (set_attr "length" "12,16")])
13266
13267(define_split
097657c3 13268 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13269 (compare:CC
13270 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13271 (match_operand:SI 2 "reg_or_short_operand" ""))
13272 (match_operand:SI 3 "gpc_reg_operand" ""))
13273 (const_int 0)))
13274 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13275 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13276 "TARGET_POWER && reload_completed"
097657c3 13277 [(set (match_dup 0)
9ebbca7d 13278 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13279 (set (match_dup 4)
9ebbca7d
GK		 13280 (compare:CC (match_dup 0)
13281 (const_int 0)))]
13282 "")
1fd4e8c1
RK		 13283
13284(define_insn ""
cd2b37d9
RK		 13285 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13286 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13287 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13288 "TARGET_POWER"
13289 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 13290 [(set_attr "length" "12")])
1fd4e8c1 13291
a2dba291
DE		 13292(define_insn "*geu<mode>"
13293 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13294 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13295 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13296 ""
1fd4e8c1 13297 "@
ca7f5001
RK		 13298 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13299 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 13300 [(set_attr "type" "three")
13301 (set_attr "length" "12")])
1fd4e8c1 13302
a2dba291 13303(define_insn "*geu<mode>_compare"
9ebbca7d 13304 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13305 (compare:CC
a2dba291
DE		 13306 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13307 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13308 (const_int 0)))
a2dba291
DE		 13309 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13310 (geu:P (match_dup 1) (match_dup 2)))]
13311 ""
1fd4e8c1 13312 "@
ca7f5001 13313 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 13314 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13315 #
13316 #"
b19003d8 13317 [(set_attr "type" "compare")
9ebbca7d
GK		 13318 (set_attr "length" "12,12,16,16")])
13319
13320(define_split
13321 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13322 (compare:CC
a2dba291
DE		 13323 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13324 (match_operand:P 2 "reg_or_neg_short_operand" ""))
9ebbca7d 13325 (const_int 0)))
a2dba291
DE		 13326 (set (match_operand:P 0 "gpc_reg_operand" "")
13327 (geu:P (match_dup 1) (match_dup 2)))]
13328 "reload_completed"
9ebbca7d 13329 [(set (match_dup 0)
a2dba291 13330 (geu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 13331 (set (match_dup 3)
13332 (compare:CC (match_dup 0)
13333 (const_int 0)))]
13334 "")
f9562f27 13335
a2dba291
DE		 13336(define_insn "*plus_geu<mode>"
13337 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13338 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13339 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13340 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13341 ""
1fd4e8c1 13342 "@
80103f96
FS		 13343 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13344 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
943c15ed
DE		 13345 [(set_attr "type" "two")
13346 (set_attr "length" "8")])
1fd4e8c1
RK		 13347
13348(define_insn ""
9ebbca7d 13349 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13350 (compare:CC
9ebbca7d
GK		 13351 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13352 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13353 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13354 (const_int 0)))
9ebbca7d 13355 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13356 "TARGET_32BIT"
1fd4e8c1 13357 "@
ca7f5001 13358 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13359 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13360 #
13361 #"
b19003d8 13362 [(set_attr "type" "compare")
9ebbca7d
GK		 13363 (set_attr "length" "8,8,12,12")])
13364
13365(define_split
13366 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13367 (compare:CC
13368 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13369 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13370 (match_operand:SI 3 "gpc_reg_operand" ""))
13371 (const_int 0)))
13372 (clobber (match_scratch:SI 4 ""))]
683bdff7 13373 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13374 [(set (match_dup 4)
13375 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13376 (match_dup 3)))
13377 (set (match_dup 0)
13378 (compare:CC (match_dup 4)
13379 (const_int 0)))]
13380 "")
1fd4e8c1
RK		 13381
13382(define_insn ""
097657c3 13383 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13384 (compare:CC
9ebbca7d
GK		 13385 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13386 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13387 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13388 (const_int 0)))
097657c3
AM		 13389 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13390 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13391 "TARGET_32BIT"
1fd4e8c1 13392 "@
097657c3
AM		 13393 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13394 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 13395 #
13396 #"
b19003d8 13397 [(set_attr "type" "compare")
9ebbca7d
GK		 13398 (set_attr "length" "8,8,12,12")])
13399
13400(define_split
097657c3 13401 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13402 (compare:CC
13403 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13404 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13405 (match_operand:SI 3 "gpc_reg_operand" ""))
13406 (const_int 0)))
13407 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13408 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13409 "TARGET_32BIT && reload_completed"
097657c3 13410 [(set (match_dup 0)
9ebbca7d 13411 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13412 (set (match_dup 4)
9ebbca7d
GK		 13413 (compare:CC (match_dup 0)
13414 (const_int 0)))]
13415 "")
1fd4e8c1 13416
a2dba291
DE		 13417(define_insn "*neg_geu<mode>"
13418 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13419 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13420 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13421 ""
1fd4e8c1 13422 "@
ca7f5001 13423 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 13424 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
943c15ed
DE		 13425 [(set_attr "type" "three")
13426 (set_attr "length" "12")])
1fd4e8c1 13427
a2dba291
DE		 13428(define_insn "*and_neg_geu<mode>"
13429 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13430 (and:P (neg:P
13431 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13432 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13433 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13434 ""
1fd4e8c1 13435 "@
097657c3
AM		 13436 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13437 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 13438 [(set_attr "type" "three")
13439 (set_attr "length" "12")])
1fd4e8c1
RK		 13440
13441(define_insn ""
9ebbca7d 13442 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13443 (compare:CC
13444 (and:SI (neg:SI
9ebbca7d
GK		 13445 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13446 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13447 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13448 (const_int 0)))
9ebbca7d 13449 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13450 "TARGET_32BIT"
1fd4e8c1 13451 "@
ca7f5001 13452 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 13453 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13454 #
13455 #"
b19003d8 13456 [(set_attr "type" "compare")
9ebbca7d
GK		 13457 (set_attr "length" "12,12,16,16")])
13458
13459(define_split
13460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13461 (compare:CC
13462 (and:SI (neg:SI
13463 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13464 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13465 (match_operand:SI 3 "gpc_reg_operand" ""))
13466 (const_int 0)))
13467 (clobber (match_scratch:SI 4 ""))]
683bdff7 13468 "TARGET_32BIT && reload_completed"
9ebbca7d 13469 [(set (match_dup 4)
097657c3
AM		 13470 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13471 (match_dup 3)))
9ebbca7d
GK		 13472 (set (match_dup 0)
13473 (compare:CC (match_dup 4)
13474 (const_int 0)))]
13475 "")
1fd4e8c1
RK		 13476
13477(define_insn ""
097657c3 13478 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13479 (compare:CC
13480 (and:SI (neg:SI
9ebbca7d
GK		 13481 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13482 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13483 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13484 (const_int 0)))
097657c3
AM		 13485 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13486 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13487 "TARGET_32BIT"
1fd4e8c1 13488 "@
097657c3
AM		 13489 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13490 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 13491 #
13492 #"
b19003d8 13493 [(set_attr "type" "compare")
9ebbca7d
GK		 13494 (set_attr "length" "12,12,16,16")])
13495
13496(define_split
097657c3 13497 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13498 (compare:CC
13499 (and:SI (neg:SI
13500 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13501 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13502 (match_operand:SI 3 "gpc_reg_operand" ""))
13503 (const_int 0)))
13504 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13505 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13506 "TARGET_32BIT && reload_completed"
097657c3 13507 [(set (match_dup 0)
9ebbca7d 13508 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 13509 (set (match_dup 4)
9ebbca7d
GK		 13510 (compare:CC (match_dup 0)
13511 (const_int 0)))]
13512 "")
1fd4e8c1 13513
1fd4e8c1 13514(define_insn ""
cd2b37d9
RK		 13515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13516 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13517 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 13518 "TARGET_POWER"
13519 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13520 [(set_attr "length" "12")])
1fd4e8c1
RK		 13521
13522(define_insn ""
9ebbca7d 13523 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13524 (compare:CC
9ebbca7d
GK		 13525 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13526 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 13527 (const_int 0)))
9ebbca7d 13528 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13529 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13530 "TARGET_POWER"
9ebbca7d
GK		 13531 "@
13532 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13533 #"
29ae5b89 13534 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13535 (set_attr "length" "12,16")])
13536
13537(define_split
13538 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13539 (compare:CC
13540 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13541 (match_operand:SI 2 "reg_or_short_operand" ""))
13542 (const_int 0)))
13543 (set (match_operand:SI 0 "gpc_reg_operand" "")
13544 (gt:SI (match_dup 1) (match_dup 2)))]
13545 "TARGET_POWER && reload_completed"
13546 [(set (match_dup 0)
13547 (gt:SI (match_dup 1) (match_dup 2)))
13548 (set (match_dup 3)
13549 (compare:CC (match_dup 0)
13550 (const_int 0)))]
13551 "")
1fd4e8c1 13552
d0515b39 13553(define_insn "*plus_gt0<mode>"
a2dba291
DE		 13554 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13555 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13556 (const_int 0))
13557 (match_operand:P 2 "gpc_reg_operand" "r")))]
13558 ""
80103f96 13559 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
943c15ed
DE		 13560 [(set_attr "type" "three")
13561 (set_attr "length" "12")])
1fd4e8c1
RK		 13562
13563(define_insn ""
9ebbca7d 13564 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13565 (compare:CC
9ebbca7d 13566 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13567 (const_int 0))
9ebbca7d 13568 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 13569 (const_int 0)))
9ebbca7d 13570 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 13571 "TARGET_32BIT"
9ebbca7d
GK		 13572 "@
13573 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13574 #"
b19003d8 13575 [(set_attr "type" "compare")
9ebbca7d
GK		 13576 (set_attr "length" "12,16")])
13577
13578(define_split
13579 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13580 (compare:CC
13581 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13582 (const_int 0))
13583 (match_operand:SI 2 "gpc_reg_operand" ""))
13584 (const_int 0)))
13585 (clobber (match_scratch:SI 3 ""))]
683bdff7 13586 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13587 [(set (match_dup 3)
13588 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13589 (match_dup 2)))
13590 (set (match_dup 0)
13591 (compare:CC (match_dup 3)
13592 (const_int 0)))]
13593 "")
1fd4e8c1 13594
f9562f27 13595(define_insn ""
9ebbca7d 13596 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 13597 (compare:CC
9ebbca7d 13598 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13599 (const_int 0))
9ebbca7d 13600 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13601 (const_int 0)))
9ebbca7d 13602 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 13603 "TARGET_64BIT"
9ebbca7d
GK		 13604 "@
13605 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13606 #"
f9562f27 13607 [(set_attr "type" "compare")
9ebbca7d
GK		 13608 (set_attr "length" "12,16")])
13609
13610(define_split
13611 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13612 (compare:CC
13613 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13614 (const_int 0))
13615 (match_operand:DI 2 "gpc_reg_operand" ""))
13616 (const_int 0)))
13617 (clobber (match_scratch:DI 3 ""))]
683bdff7 13618 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13619 [(set (match_dup 3)
13620 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 13621 (match_dup 2)))
9ebbca7d
GK		 13622 (set (match_dup 0)
13623 (compare:CC (match_dup 3)
13624 (const_int 0)))]
13625 "")
f9562f27 13626
1fd4e8c1 13627(define_insn ""
097657c3 13628 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 13629 (compare:CC
13630 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13631 (const_int 0))
13632 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13633 (const_int 0)))
097657c3
AM		 13634 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13635 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13636 "TARGET_32BIT"
9ebbca7d 13637 "@
097657c3 13638 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 13639 #"
13640 [(set_attr "type" "compare")
13641 (set_attr "length" "12,16")])
13642
13643(define_split
097657c3 13644 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 13645 (compare:CC
9ebbca7d 13646 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 13647 (const_int 0))
9ebbca7d 13648 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 13649 (const_int 0)))
9ebbca7d 13650 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13651 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13652 "TARGET_32BIT && reload_completed"
097657c3 13653 [(set (match_dup 0)
9ebbca7d 13654 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13655 (set (match_dup 3)
9ebbca7d
GK		 13656 (compare:CC (match_dup 0)
13657 (const_int 0)))]
13658 "")
1fd4e8c1 13659
f9562f27 13660(define_insn ""
097657c3 13661 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13662 (compare:CC
9ebbca7d 13663 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13664 (const_int 0))
9ebbca7d 13665 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13666 (const_int 0)))
097657c3
AM		 13667 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13668 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13669 "TARGET_64BIT"
9ebbca7d 13670 "@
097657c3 13671 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 13672 #"
f9562f27 13673 [(set_attr "type" "compare")
9ebbca7d
GK		 13674 (set_attr "length" "12,16")])
13675
13676(define_split
097657c3 13677 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13678 (compare:CC
13679 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13680 (const_int 0))
13681 (match_operand:DI 2 "gpc_reg_operand" ""))
13682 (const_int 0)))
13683 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13684 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13685 "TARGET_64BIT && reload_completed"
097657c3 13686 [(set (match_dup 0)
9ebbca7d 13687 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13688 (set (match_dup 3)
9ebbca7d
GK		 13689 (compare:CC (match_dup 0)
13690 (const_int 0)))]
13691 "")
f9562f27 13692
1fd4e8c1 13693(define_insn ""
097657c3 13694 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13695 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13696 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 13697 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13698 "TARGET_POWER"
097657c3 13699 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13700 [(set_attr "length" "12")])
1fd4e8c1
RK		 13701
13702(define_insn ""
9ebbca7d 13703 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13704 (compare:CC
9ebbca7d
GK		 13705 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13706 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13707 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13708 (const_int 0)))
9ebbca7d 13709 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13710 "TARGET_POWER"
9ebbca7d
GK		 13711 "@
13712 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13713 #"
b19003d8 13714 [(set_attr "type" "compare")
9ebbca7d
GK		 13715 (set_attr "length" "12,16")])
13716
13717(define_split
13718 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13719 (compare:CC
13720 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13721 (match_operand:SI 2 "reg_or_short_operand" ""))
13722 (match_operand:SI 3 "gpc_reg_operand" ""))
13723 (const_int 0)))
13724 (clobber (match_scratch:SI 4 ""))]
13725 "TARGET_POWER && reload_completed"
13726 [(set (match_dup 4)
097657c3 13727 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 13728 (set (match_dup 0)
13729 (compare:CC (match_dup 4)
13730 (const_int 0)))]
13731 "")
1fd4e8c1
RK		 13732
13733(define_insn ""
097657c3 13734 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13735 (compare:CC
9ebbca7d
GK		 13736 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13737 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13738 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13739 (const_int 0)))
097657c3
AM		 13740 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13741 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13742 "TARGET_POWER"
9ebbca7d 13743 "@
097657c3 13744 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13745 #"
b19003d8 13746 [(set_attr "type" "compare")
9ebbca7d
GK		 13747 (set_attr "length" "12,16")])
13748
13749(define_split
097657c3 13750 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13751 (compare:CC
13752 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13753 (match_operand:SI 2 "reg_or_short_operand" ""))
13754 (match_operand:SI 3 "gpc_reg_operand" ""))
13755 (const_int 0)))
13756 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13757 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13758 "TARGET_POWER && reload_completed"
097657c3 13759 [(set (match_dup 0)
9ebbca7d 13760 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13761 (set (match_dup 4)
9ebbca7d
GK		 13762 (compare:CC (match_dup 0)
13763 (const_int 0)))]
13764 "")
1fd4e8c1 13765
1fd4e8c1 13766(define_insn ""
cd2b37d9
RK		 13767 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13768 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13769 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 13770 "TARGET_POWER"
13771 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13772 [(set_attr "length" "12")])
1fd4e8c1 13773
ce45ef46
DE		 13774(define_insn_and_split "*gtu<mode>"
13775 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13776 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13777 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13778 ""
c0600ecd 13779 "#"
ce45ef46
DE		 13780 ""
13781 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13782 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13783 "")
f9562f27 13784
1e24ce83 13785(define_insn_and_split "*gtu<mode>_compare"
9ebbca7d 13786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13787 (compare:CC
a2dba291
DE		 13788 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13789 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13790 (const_int 0)))
a2dba291
DE		 13791 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13792 (gtu:P (match_dup 1) (match_dup 2)))]
13793 ""
1e24ce83
DE		 13794 "#"
13795 ""
13796 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13797 (parallel [(set (match_dup 3)
13798 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13799 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13800 "")
f9562f27 13801
1e24ce83 13802(define_insn_and_split "*plus_gtu<mode>"
a2dba291
DE		 13803 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13804 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13805 (match_operand:P 2 "reg_or_short_operand" "rI"))
13806 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13807 ""
c0600ecd 13808 "#"
04fa46cf 13809 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13810 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13811 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13812 "")
f9562f27 13813
1e24ce83 13814(define_insn_and_split "*plus_gtu<mode>_compare"
097657c3 13815 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13816 (compare:CC
1e24ce83
DE		 13817 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13818 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13819 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13820 (const_int 0)))
1e24ce83
DE		 13821 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13822 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13823 ""
13824 "#"
13825 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13826 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13827 (parallel [(set (match_dup 4)
13828 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13829 (const_int 0)))
13830 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13831 "")
f9562f27 13832
ce45ef46
DE		 13833(define_insn "*neg_gtu<mode>"
13834 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13835 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13836 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13837 ""
ca7f5001 13838 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
943c15ed 13839 [(set_attr "type" "two")
c0600ecd 13840 (set_attr "length" "8")])
f9562f27 13841
1fd4e8c1
RK		 13842\f
13843;; Define both directions of branch and return. If we need a reload
13844;; register, we'd rather use CR0 since it is much easier to copy a
13845;; register CC value to there.
13846
13847(define_insn ""
13848 [(set (pc)
13849 (if_then_else (match_operator 1 "branch_comparison_operator"
13850 [(match_operand 2
b54cf83a 13851 "cc_reg_operand" "y")
1fd4e8c1
RK		 13852 (const_int 0)])
13853 (label_ref (match_operand 0 "" ""))
13854 (pc)))]
13855 ""
b19003d8
RK		 13856 "*
13857{
12a4e8c5 13858 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 13859}"
13860 [(set_attr "type" "branch")])
13861
1fd4e8c1
RK		 13862(define_insn ""
13863 [(set (pc)
13864 (if_then_else (match_operator 0 "branch_comparison_operator"
13865 [(match_operand 1
b54cf83a 13866 "cc_reg_operand" "y")
1fd4e8c1
RK		 13867 (const_int 0)])
13868 (return)
13869 (pc)))]
13870 "direct_return ()"
12a4e8c5
GK		 13871 "*
13872{
13873 return output_cbranch (operands[0], NULL, 0, insn);
13874}"
9c6fdb46 13875 [(set_attr "type" "jmpreg")
39a10a29 13876 (set_attr "length" "4")])
1fd4e8c1
RK		 13877
13878(define_insn ""
13879 [(set (pc)
13880 (if_then_else (match_operator 1 "branch_comparison_operator"
13881 [(match_operand 2
b54cf83a 13882 "cc_reg_operand" "y")
1fd4e8c1
RK		 13883 (const_int 0)])
13884 (pc)
13885 (label_ref (match_operand 0 "" ""))))]
13886 ""
b19003d8
RK		 13887 "*
13888{
12a4e8c5 13889 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 13890}"
13891 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13892
13893(define_insn ""
13894 [(set (pc)
13895 (if_then_else (match_operator 0 "branch_comparison_operator"
13896 [(match_operand 1
b54cf83a 13897 "cc_reg_operand" "y")
1fd4e8c1
RK		 13898 (const_int 0)])
13899 (pc)
13900 (return)))]
13901 "direct_return ()"
12a4e8c5
GK		 13902 "*
13903{
13904 return output_cbranch (operands[0], NULL, 1, insn);
13905}"
9c6fdb46 13906 [(set_attr "type" "jmpreg")
39a10a29
GK		 13907 (set_attr "length" "4")])
13908
13909;; Logic on condition register values.
13910
13911; This pattern matches things like
13912; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13913; (eq:SI (reg:CCFP 68) (const_int 0)))
13914; (const_int 1)))
13915; which are generated by the branch logic.
b54cf83a 13916; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29 13917
423c1189 13918(define_insn "*cceq_ior_compare"
b54cf83a 13919 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13920 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 13921 [(match_operator:SI 2
39a10a29
GK		 13922 "branch_positive_comparison_operator"
13923 [(match_operand 3
b54cf83a 13924 "cc_reg_operand" "y,y")
39a10a29 13925 (const_int 0)])
b54cf83a 13926 (match_operator:SI 4
39a10a29
GK		 13927 "branch_positive_comparison_operator"
13928 [(match_operand 5
b54cf83a 13929 "cc_reg_operand" "0,y")
39a10a29
GK		 13930 (const_int 0)])])
13931 (const_int 1)))]
24fab1d3 13932 ""
39a10a29 13933 "cr%q1 %E0,%j2,%j4"
b54cf83a 13934 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13935
13936; Why is the constant -1 here, but 1 in the previous pattern?
13937; Because ~1 has all but the low bit set.
13938(define_insn ""
b54cf83a 13939 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13940 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 13941 [(not:SI (match_operator:SI 2
39a10a29
GK		 13942 "branch_positive_comparison_operator"
13943 [(match_operand 3
b54cf83a 13944 "cc_reg_operand" "y,y")
39a10a29
GK		 13945 (const_int 0)]))
13946 (match_operator:SI 4
13947 "branch_positive_comparison_operator"
13948 [(match_operand 5
b54cf83a 13949 "cc_reg_operand" "0,y")
39a10a29
GK		 13950 (const_int 0)])])
13951 (const_int -1)))]
13952 ""
13953 "cr%q1 %E0,%j2,%j4"
b54cf83a 13954 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29 13955
423c1189 13956(define_insn "*cceq_rev_compare"
b54cf83a 13957 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 13958 (compare:CCEQ (match_operator:SI 1
39a10a29 13959 "branch_positive_comparison_operator"
6c873122 13960 [(match_operand 2
b54cf83a 13961 "cc_reg_operand" "0,y")
39a10a29
GK		 13962 (const_int 0)])
13963 (const_int 0)))]
423c1189 13964 ""
251b3667 13965 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 13966 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13967
13968;; If we are comparing the result of two comparisons, this can be done
13969;; using creqv or crxor.
13970
13971(define_insn_and_split ""
13972 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13973 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13974 [(match_operand 2 "cc_reg_operand" "y")
13975 (const_int 0)])
13976 (match_operator 3 "branch_comparison_operator"
13977 [(match_operand 4 "cc_reg_operand" "y")
13978 (const_int 0)])))]
13979 ""
13980 "#"
13981 ""
13982 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13983 (match_dup 5)))]
13984 "
13985{
13986 int positive_1, positive_2;
13987
364849ee
DE		 13988 positive_1 = branch_positive_comparison_operator (operands[1],
13989 GET_MODE (operands[1]));
13990 positive_2 = branch_positive_comparison_operator (operands[3],
13991 GET_MODE (operands[3]));
39a10a29
GK		 13992
13993 if (! positive_1)
1c563bed 13994 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
0f4c242b
KH		 13995 GET_CODE (operands[1])),
13996 SImode,
13997 operands[2], const0_rtx);
39a10a29 13998 else if (GET_MODE (operands[1]) != SImode)
0f4c242b
KH		 13999 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14000 operands[2], const0_rtx);
39a10a29
GK		 14001
14002 if (! positive_2)
1c563bed 14003 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
0f4c242b
KH		 14004 GET_CODE (operands[3])),
14005 SImode,
14006 operands[4], const0_rtx);
39a10a29 14007 else if (GET_MODE (operands[3]) != SImode)
0f4c242b
KH		 14008 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14009 operands[4], const0_rtx);
39a10a29
GK		 14010
14011 if (positive_1 == positive_2)
251b3667
DE		 14012 {
14013 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14014 operands[5] = constm1_rtx;
14015 }
14016 else
14017 {
14018 operands[5] = const1_rtx;
14019 }
39a10a29 14020}")
1fd4e8c1
RK		 14021
14022;; Unconditional branch and return.
14023
14024(define_insn "jump"
14025 [(set (pc)
14026 (label_ref (match_operand 0 "" "")))]
14027 ""
b7ff3d82
DE		 14028 "b %l0"
14029 [(set_attr "type" "branch")])
1fd4e8c1
RK		 14030
14031(define_insn "return"
14032 [(return)]
14033 "direct_return ()"
324e52cc
TG		 14034 "{br|blr}"
14035 [(set_attr "type" "jmpreg")])
1fd4e8c1 14036
0ad91047 14037(define_expand "indirect_jump"
4ae234b0 14038 [(set (pc) (match_operand 0 "register_operand" ""))])
0ad91047 14039
4ae234b0
GK		 14040(define_insn "*indirect_jump<mode>"
14041 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14042 ""
b92b324d
DE		 14043 "@
14044 bctr
14045 {br|blr}"
324e52cc 14046 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14047
14048;; Table jump for switch statements:
14049(define_expand "tablejump"
e6ca2c17
DE		 14050 [(use (match_operand 0 "" ""))
14051 (use (label_ref (match_operand 1 "" "")))]
14052 ""
14053 "
14054{
14055 if (TARGET_32BIT)
14056 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14057 else
14058 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14059 DONE;
14060}")
14061
14062(define_expand "tablejumpsi"
1fd4e8c1
RK		 14063 [(set (match_dup 3)
14064 (plus:SI (match_operand:SI 0 "" "")
14065 (match_dup 2)))
14066 (parallel [(set (pc) (match_dup 3))
14067 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14068 "TARGET_32BIT"
1fd4e8c1
RK		 14069 "
14070{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 14071 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 14072 operands[3] = gen_reg_rtx (SImode);
14073}")
14074
e6ca2c17 14075(define_expand "tablejumpdi"
6ae08853 14076 [(set (match_dup 4)
e42ac3de 14077 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
9ebbca7d
GK		 14078 (set (match_dup 3)
14079 (plus:DI (match_dup 4)
e6ca2c17
DE		 14080 (match_dup 2)))
14081 (parallel [(set (pc) (match_dup 3))
14082 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14083 "TARGET_64BIT"
e6ca2c17 14084 "
9ebbca7d 14085{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 14086 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 14087 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 14088}")
14089
ce45ef46 14090(define_insn "*tablejump<mode>_internal1"
1fd4e8c1 14091 [(set (pc)
4ae234b0 14092 (match_operand:P 0 "register_operand" "c,*l"))
1fd4e8c1 14093 (use (label_ref (match_operand 1 "" "")))]
4ae234b0 14094 ""
c859cda6
DJ		 14095 "@
14096 bctr
14097 {br|blr}"
a6845123 14098 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14099
14100(define_insn "nop"
14101 [(const_int 0)]
14102 ""
ca7f5001 14103 "{cror 0,0,0|nop}")
1fd4e8c1 14104\f
7e69e155 14105;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 14106;; so loop.c knows what to generate.
14107
5527bf14
RH		 14108(define_expand "doloop_end"
14109 [(use (match_operand 0 "" "")) ; loop pseudo
14110 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14111 (use (match_operand 2 "" "")) ; max iterations
14112 (use (match_operand 3 "" "")) ; loop level
14113 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 14114 ""
14115 "
14116{
5527bf14
RH		 14117 /* Only use this on innermost loops. */
14118 if (INTVAL (operands[3]) > 1)
14119 FAIL;
683bdff7 14120 if (TARGET_64BIT)
5527bf14
RH		 14121 {
14122 if (GET_MODE (operands[0]) != DImode)
14123 FAIL;
14124 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14125 }
0ad91047 14126 else
5527bf14
RH		 14127 {
14128 if (GET_MODE (operands[0]) != SImode)
14129 FAIL;
14130 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14131 }
0ad91047
DE		 14132 DONE;
14133}")
14134
4ae234b0 14135(define_expand "ctr<mode>"
3cb999d8 14136 [(parallel [(set (pc)
4ae234b0 14137 (if_then_else (ne (match_operand:P 0 "register_operand" "")
3cb999d8
DE		 14138 (const_int 1))
14139 (label_ref (match_operand 1 "" ""))
14140 (pc)))
b6c9286a 14141 (set (match_dup 0)
4ae234b0 14142 (plus:P (match_dup 0)
b6c9286a 14143 (const_int -1)))
5f81043f 14144 (clobber (match_scratch:CC 2 ""))
4ae234b0
GK		 14145 (clobber (match_scratch:P 3 ""))])]
14146 ""
61c07d3c 14147 "")
c225ba7b 14148
1fd4e8c1
RK		 14149;; We need to be able to do this for any operand, including MEM, or we
14150;; will cause reload to blow up since we don't allow output reloads on
7e69e155 14151;; JUMP_INSNs.
0ad91047 14152;; For the length attribute to be calculated correctly, the
5f81043f
RK		 14153;; label MUST be operand 0.
14154
4ae234b0 14155(define_insn "*ctr<mode>_internal1"
0ad91047 14156 [(set (pc)
4ae234b0 14157 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14158 (const_int 1))
14159 (label_ref (match_operand 0 "" ""))
14160 (pc)))
4ae234b0
GK		 14161 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14162 (plus:P (match_dup 1)
0ad91047 14163 (const_int -1)))
43b68ce5 14164 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14165 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14166 ""
0ad91047
DE		 14167 "*
14168{
14169 if (which_alternative != 0)
14170 return \"#\";
856a6884 14171 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14172 return \"{bdn|bdnz} %l0\";
14173 else
f607bc57 14174 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14175}"
14176 [(set_attr "type" "branch")
5a195cb5 14177 (set_attr "length" "*,12,16,16")])
0ad91047 14178
4ae234b0 14179(define_insn "*ctr<mode>_internal2"
0ad91047 14180 [(set (pc)
4ae234b0 14181 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14182 (const_int 1))
14183 (pc)
14184 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14185 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14186 (plus:P (match_dup 1)
0ad91047 14187 (const_int -1)))
43b68ce5 14188 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14189 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14190 ""
5f81043f
RK		 14191 "*
14192{
14193 if (which_alternative != 0)
14194 return \"#\";
856a6884 14195 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14196 return \"bdz %l0\";
14197 else
f607bc57 14198 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14199}"
14200 [(set_attr "type" "branch")
5a195cb5 14201 (set_attr "length" "*,12,16,16")])
5f81043f 14202
0ad91047
DE		 14203;; Similar but use EQ
14204
4ae234b0 14205(define_insn "*ctr<mode>_internal5"
5f81043f 14206 [(set (pc)
4ae234b0 14207 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14208 (const_int 1))
a6845123 14209 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14210 (pc)))
4ae234b0
GK		 14211 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14212 (plus:P (match_dup 1)
0ad91047 14213 (const_int -1)))
43b68ce5 14214 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14215 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14216 ""
0ad91047
DE		 14217 "*
14218{
14219 if (which_alternative != 0)
14220 return \"#\";
856a6884 14221 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14222 return \"bdz %l0\";
14223 else
f607bc57 14224 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14225}"
14226 [(set_attr "type" "branch")
5a195cb5 14227 (set_attr "length" "*,12,16,16")])
0ad91047 14228
4ae234b0 14229(define_insn "*ctr<mode>_internal6"
0ad91047 14230 [(set (pc)
4ae234b0 14231 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14232 (const_int 1))
14233 (pc)
14234 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14235 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14236 (plus:P (match_dup 1)
0ad91047 14237 (const_int -1)))
43b68ce5 14238 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14239 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14240 ""
5f81043f
RK		 14241 "*
14242{
14243 if (which_alternative != 0)
14244 return \"#\";
856a6884 14245 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14246 return \"{bdn|bdnz} %l0\";
14247 else
f607bc57 14248 return \"bdz $+8\;b %l0\";
5f81043f
RK		 14249}"
14250 [(set_attr "type" "branch")
5a195cb5 14251 (set_attr "length" "*,12,16,16")])
5f81043f 14252
0ad91047
DE		 14253;; Now the splitters if we could not allocate the CTR register
14254
1fd4e8c1
RK		 14255(define_split
14256 [(set (pc)
14257 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14258 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14259 (const_int 1)])
61c07d3c
DE		 14260 (match_operand 5 "" "")
14261 (match_operand 6 "" "")))
4ae234b0
GK		 14262 (set (match_operand:P 0 "gpc_reg_operand" "")
14263 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14264 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14265 (clobber (match_scratch:P 4 ""))]
14266 "reload_completed"
0ad91047 14267 [(parallel [(set (match_dup 3)
4ae234b0 14268 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14269 (const_int -1))
14270 (const_int 0)))
14271 (set (match_dup 0)
4ae234b0 14272 (plus:P (match_dup 1)
0ad91047 14273 (const_int -1)))])
61c07d3c
DE		 14274 (set (pc) (if_then_else (match_dup 7)
14275 (match_dup 5)
14276 (match_dup 6)))]
0ad91047 14277 "
0f4c242b
KH		 14278{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14279 operands[3], const0_rtx); }")
0ad91047
DE		 14280
14281(define_split
14282 [(set (pc)
14283 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14284 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14285 (const_int 1)])
61c07d3c
DE		 14286 (match_operand 5 "" "")
14287 (match_operand 6 "" "")))
4ae234b0
GK		 14288 (set (match_operand:P 0 "nonimmediate_operand" "")
14289 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14290 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14291 (clobber (match_scratch:P 4 ""))]
14292 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
0ad91047 14293 [(parallel [(set (match_dup 3)
4ae234b0 14294 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14295 (const_int -1))
14296 (const_int 0)))
14297 (set (match_dup 4)
4ae234b0 14298 (plus:P (match_dup 1)
0ad91047
DE		 14299 (const_int -1)))])
14300 (set (match_dup 0)
14301 (match_dup 4))
61c07d3c
DE		 14302 (set (pc) (if_then_else (match_dup 7)
14303 (match_dup 5)
14304 (match_dup 6)))]
0ad91047 14305 "
0f4c242b
KH		 14306{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14307 operands[3], const0_rtx); }")
e0cd0770
JC		 14308\f
14309(define_insn "trap"
14310 [(trap_if (const_int 1) (const_int 0))]
14311 ""
44cd321e
PS		 14312 "{t 31,0,0|trap}"
14313 [(set_attr "type" "trap")])
e0cd0770
JC		 14314
14315(define_expand "conditional_trap"
14316 [(trap_if (match_operator 0 "trap_comparison_operator"
14317 [(match_dup 2) (match_dup 3)])
14318 (match_operand 1 "const_int_operand" ""))]
14319 ""
14320 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14321 operands[2] = rs6000_compare_op0;
14322 operands[3] = rs6000_compare_op1;")
14323
14324(define_insn ""
14325 [(trap_if (match_operator 0 "trap_comparison_operator"
4ae234b0
GK		 14326 [(match_operand:GPR 1 "register_operand" "r")
14327 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
e0cd0770
JC		 14328 (const_int 0))]
14329 ""
44cd321e
PS		 14330 "{t|t<wd>}%V0%I2 %1,%2"
14331 [(set_attr "type" "trap")])
9ebbca7d
GK		 14332\f
14333;; Insns related to generating the function prologue and epilogue.
14334
14335(define_expand "prologue"
14336 [(use (const_int 0))]
14337 "TARGET_SCHED_PROLOG"
14338 "
14339{
14340 rs6000_emit_prologue ();
14341 DONE;
14342}")
14343
2c4a9cff
DE		 14344(define_insn "*movesi_from_cr_one"
14345 [(match_parallel 0 "mfcr_operation"
14346 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14347 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14348 (match_operand 3 "immediate_operand" "n")]
14349 UNSPEC_MOVESI_FROM_CR))])]
14350 "TARGET_MFCRF"
14351 "*
14352{
14353 int mask = 0;
14354 int i;
14355 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14356 {
14357 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14358 operands[4] = GEN_INT (mask);
14359 output_asm_insn (\"mfcr %1,%4\", operands);
14360 }
14361 return \"\";
14362}"
14363 [(set_attr "type" "mfcrf")])
14364
9ebbca7d
GK		 14365(define_insn "movesi_from_cr"
14366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 14367 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
615158e2
JJ		 14368 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14369 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 14370 ""
309323c2 14371 "mfcr %0"
b54cf83a 14372 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14373
14374(define_insn "*stmw"
e033a023
DE		 14375 [(match_parallel 0 "stmw_operation"
14376 [(set (match_operand:SI 1 "memory_operand" "=m")
14377 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14378 "TARGET_MULTIPLE"
9c6fdb46
DE		 14379 "{stm|stmw} %2,%1"
14380 [(set_attr "type" "store_ux")])
6ae08853 14381
4ae234b0 14382(define_insn "*save_fpregs_<mode>"
85d346f1 14383 [(match_parallel 0 "any_parallel_operand"
4ae234b0
GK		 14384 [(clobber (match_operand:P 1 "register_operand" "=l"))
14385 (use (match_operand:P 2 "call_operand" "s"))
e033a023
DE		 14386 (set (match_operand:DF 3 "memory_operand" "=m")
14387 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
4ae234b0 14388 ""
e033a023
DE		 14389 "bl %z2"
14390 [(set_attr "type" "branch")
14391 (set_attr "length" "4")])
9ebbca7d
GK		 14392
14393; These are to explain that changes to the stack pointer should
14394; not be moved over stores to stack memory.
14395(define_insn "stack_tie"
14396 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 14397 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 14398 ""
14399 ""
14400 [(set_attr "length" "0")])
14401
14402
14403(define_expand "epilogue"
14404 [(use (const_int 0))]
14405 "TARGET_SCHED_PROLOG"
14406 "
14407{
14408 rs6000_emit_epilogue (FALSE);
14409 DONE;
14410}")
14411
14412; On some processors, doing the mtcrf one CC register at a time is
14413; faster (like on the 604e). On others, doing them all at once is
14414; faster; for instance, on the 601 and 750.
14415
14416(define_expand "movsi_to_cr_one"
e42ac3de
RS		 14417 [(set (match_operand:CC 0 "cc_reg_operand" "")
14418 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
615158e2 14419 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 14420 ""
14421 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14422
14423(define_insn "*movsi_to_cr"
35aba846
DE		 14424 [(match_parallel 0 "mtcrf_operation"
14425 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14426 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14427 (match_operand 3 "immediate_operand" "n")]
615158e2 14428 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 14429 ""
e35b9579
GK		 14430 "*
14431{
14432 int mask = 0;
14433 int i;
14434 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14435 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14436 operands[4] = GEN_INT (mask);
14437 return \"mtcrf %4,%2\";
309323c2 14438}"
b54cf83a 14439 [(set_attr "type" "mtcr")])
9ebbca7d 14440
b54cf83a 14441(define_insn "*mtcrfsi"
309323c2
DE		 14442 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14443 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 14444 (match_operand 2 "immediate_operand" "n")]
14445 UNSPEC_MOVESI_TO_CR))]
6ae08853 14446 "GET_CODE (operands[0]) == REG
309323c2
DE		 14447 && CR_REGNO_P (REGNO (operands[0]))
14448 && GET_CODE (operands[2]) == CONST_INT
14449 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14450 "mtcrf %R0,%1"
b54cf83a 14451 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14452
14453; The load-multiple instructions have similar properties.
14454; Note that "load_multiple" is a name known to the machine-independent
9c6fdb46 14455; code that actually corresponds to the PowerPC load-string.
9ebbca7d
GK		 14456
14457(define_insn "*lmw"
35aba846
DE		 14458 [(match_parallel 0 "lmw_operation"
14459 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14460 (match_operand:SI 2 "memory_operand" "m"))])]
14461 "TARGET_MULTIPLE"
9c6fdb46
DE		 14462 "{lm|lmw} %1,%2"
14463 [(set_attr "type" "load_ux")])
6ae08853 14464
4ae234b0 14465(define_insn "*return_internal_<mode>"
e35b9579 14466 [(return)
4ae234b0
GK		 14467 (use (match_operand:P 0 "register_operand" "lc"))]
14468 ""
cccf3bdc 14469 "b%T0"
9ebbca7d
GK		 14470 [(set_attr "type" "jmpreg")])
14471
14472; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
85d346f1 14473; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
9ebbca7d 14474
4ae234b0 14475(define_insn "*return_and_restore_fpregs_<mode>"
85d346f1 14476 [(match_parallel 0 "any_parallel_operand"
e35b9579 14477 [(return)
4ae234b0
GK		 14478 (use (match_operand:P 1 "register_operand" "l"))
14479 (use (match_operand:P 2 "call_operand" "s"))
9ebbca7d
GK		 14480 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14481 (match_operand:DF 4 "memory_operand" "m"))])]
4ae234b0 14482 ""
9ebbca7d
GK		 14483 "b %z2")
14484
83720594
RH		 14485; This is used in compiling the unwind routines.
14486(define_expand "eh_return"
34dc173c 14487 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 14488 ""
14489 "
14490{
83720594 14491 if (TARGET_32BIT)
34dc173c 14492 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 14493 else
34dc173c 14494 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 14495 DONE;
14496}")
14497
83720594 14498; We can't expand this before we know where the link register is stored.
4ae234b0
GK		 14499(define_insn "eh_set_lr_<mode>"
14500 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
615158e2 14501 UNSPECV_EH_RR)
4ae234b0
GK		 14502 (clobber (match_scratch:P 1 "=&b"))]
14503 ""
83720594 14504 "#")
9ebbca7d
GK		 14505
14506(define_split
615158e2 14507 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 14508 (clobber (match_scratch 1 ""))]
14509 "reload_completed"
14510 [(const_int 0)]
9ebbca7d
GK		 14511 "
14512{
d1d0c603 14513 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 14514 DONE;
14515}")
0ac081f6 14516
01a2ccd0 14517(define_insn "prefetch"
3256a76e 14518 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
6041bf2f
DE		 14519 (match_operand:SI 1 "const_int_operand" "n")
14520 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14521 "TARGET_POWERPC"
6041bf2f
DE		 14522 "*
14523{
01a2ccd0
DE		 14524 if (GET_CODE (operands[0]) == REG)
14525 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14526 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14527}"
14528 [(set_attr "type" "load")])
915167f5 14529\f
a3170dc6 14530
f565b0a1 14531(include "sync.md")
10ed84db 14532(include "altivec.md")
a3170dc6 14533(include "spe.md")
7393f7f8 14534(include "dfp.md")
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