]>
Commit | Line | Data |
---|---|---|
996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee GK |
2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | ;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. | |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 | 5 | |
5de601cf | 6 | ;; This file is part of GCC. |
1fd4e8c1 | 7 | |
5de601cf NC |
8 | ;; GCC is free software; you can redistribute it and/or modify it |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
1fd4e8c1 | 12 | |
5de601cf NC |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
1fd4e8c1 RK |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
5de601cf NC |
19 | ;; along with GCC; see the file COPYING. If not, write to the |
20 | ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | ;; MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d | 24 | |
615158e2 JJ |
25 | ;; |
26 | ;; UNSPEC usage | |
27 | ;; | |
28 | ||
29 | (define_constants | |
30 | [(UNSPEC_FRSP 0) ; frsp for POWER machines | |
31 | (UNSPEC_TIE 5) ; tie stack contents and stack pointer | |
32 | (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC | |
33 | (UNSPEC_TOC 7) ; address of the TOC (more-or-less) | |
34 | (UNSPEC_MOVSI_GOT 8) | |
35 | (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit | |
36 | (UNSPEC_FCTIWZ 10) | |
37 | (UNSPEC_LD_MPIC 15) ; load_macho_picbase | |
38 | (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic | |
39 | (UNSPEC_TLSGD 17) | |
40 | (UNSPEC_TLSLD 18) | |
41 | (UNSPEC_MOVESI_FROM_CR 19) | |
42 | (UNSPEC_MOVESI_TO_CR 20) | |
43 | (UNSPEC_TLSDTPREL 21) | |
44 | (UNSPEC_TLSDTPRELHA 22) | |
45 | (UNSPEC_TLSDTPRELLO 23) | |
46 | (UNSPEC_TLSGOTDTPREL 24) | |
47 | (UNSPEC_TLSTPREL 25) | |
48 | (UNSPEC_TLSTPRELHA 26) | |
49 | (UNSPEC_TLSTPRELLO 27) | |
50 | (UNSPEC_TLSGOTTPREL 28) | |
51 | (UNSPEC_TLSTLS 29) | |
52 | ]) | |
53 | ||
54 | ;; | |
55 | ;; UNSPEC_VOLATILE usage | |
56 | ;; | |
57 | ||
58 | (define_constants | |
59 | [(UNSPECV_BLOCK 0) | |
60 | (UNSPECV_EH_RR 9) ; eh_reg_restore | |
61 | ]) | |
1fd4e8c1 RK |
62 | \f |
63 | ;; Define an insn type attribute. This is used in function unit delay | |
64 | ;; computations. | |
8e8238f1 | 65 | (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" |
1fd4e8c1 RK |
66 | (const_string "integer")) |
67 | ||
b19003d8 | 68 | ;; Length (in bytes). |
6cbadf36 GK |
69 | ; '(pc)' in the following doesn't include the instruction itself; it is |
70 | ; calculated as if the instruction had zero size. | |
b19003d8 RK |
71 | (define_attr "length" "" |
72 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 73 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 74 | (const_int -32768)) |
6cbadf36 GK |
75 | (lt (minus (match_dup 0) (pc)) |
76 | (const_int 32764))) | |
39a10a29 GK |
77 | (const_int 4) |
78 | (const_int 8)) | |
b19003d8 RK |
79 | (const_int 4))) |
80 | ||
cfb557c4 RK |
81 | ;; Processor type -- this attribute must exactly match the processor_type |
82 | ;; enumeration in rs6000.h. | |
83 | ||
b54cf83a | 84 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4" |
cfb557c4 RK |
85 | (const (symbol_ref "rs6000_cpu_attr"))) |
86 | ||
b54cf83a DE |
87 | (automata_option "ndfa") |
88 | ||
89 | (include "rios1.md") | |
90 | (include "rios2.md") | |
91 | (include "rs64.md") | |
92 | (include "mpc.md") | |
93 | (include "40x.md") | |
02ca7595 | 94 | (include "440.md") |
b54cf83a DE |
95 | (include "603.md") |
96 | (include "6xx.md") | |
97 | (include "7xx.md") | |
98 | (include "7450.md") | |
5e8006fa | 99 | (include "8540.md") |
b54cf83a | 100 | (include "power4.md") |
309323c2 | 101 | |
1fd4e8c1 RK |
102 | \f |
103 | ;; Start with fixed-point load and store insns. Here we put only the more | |
104 | ;; complex forms. Basic data transfer is done later. | |
105 | ||
51b8fc2c RK |
106 | (define_expand "zero_extendqidi2" |
107 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
108 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
109 | "TARGET_POWERPC64" | |
110 | "") | |
111 | ||
112 | (define_insn "" | |
113 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
114 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
115 | "TARGET_POWERPC64" | |
116 | "@ | |
117 | lbz%U1%X1 %0,%1 | |
4371f8af | 118 | rldicl %0,%1,0,56" |
51b8fc2c RK |
119 | [(set_attr "type" "load,*")]) |
120 | ||
121 | (define_insn "" | |
9ebbca7d GK |
122 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
123 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 124 | (const_int 0))) |
9ebbca7d | 125 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 126 | "TARGET_POWERPC64" |
9ebbca7d GK |
127 | "@ |
128 | rldicl. %2,%1,0,56 | |
129 | #" | |
130 | [(set_attr "type" "compare") | |
131 | (set_attr "length" "4,8")]) | |
132 | ||
133 | (define_split | |
134 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
135 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
136 | (const_int 0))) | |
137 | (clobber (match_scratch:DI 2 ""))] | |
138 | "TARGET_POWERPC64 && reload_completed" | |
139 | [(set (match_dup 2) | |
140 | (zero_extend:DI (match_dup 1))) | |
141 | (set (match_dup 0) | |
142 | (compare:CC (match_dup 2) | |
143 | (const_int 0)))] | |
144 | "") | |
51b8fc2c RK |
145 | |
146 | (define_insn "" | |
9ebbca7d GK |
147 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
148 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 149 | (const_int 0))) |
9ebbca7d | 150 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 151 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 152 | "TARGET_POWERPC64" |
9ebbca7d GK |
153 | "@ |
154 | rldicl. %0,%1,0,56 | |
155 | #" | |
156 | [(set_attr "type" "compare") | |
157 | (set_attr "length" "4,8")]) | |
158 | ||
159 | (define_split | |
160 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
161 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
162 | (const_int 0))) | |
163 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
164 | (zero_extend:DI (match_dup 1)))] | |
165 | "TARGET_POWERPC64 && reload_completed" | |
166 | [(set (match_dup 0) | |
167 | (zero_extend:DI (match_dup 1))) | |
168 | (set (match_dup 2) | |
169 | (compare:CC (match_dup 0) | |
170 | (const_int 0)))] | |
171 | "") | |
51b8fc2c | 172 | |
2bee0449 RK |
173 | (define_insn "extendqidi2" |
174 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
175 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 176 | "TARGET_POWERPC64" |
2bee0449 | 177 | "extsb %0,%1") |
51b8fc2c RK |
178 | |
179 | (define_insn "" | |
9ebbca7d GK |
180 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
181 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 182 | (const_int 0))) |
9ebbca7d | 183 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 184 | "TARGET_POWERPC64" |
9ebbca7d GK |
185 | "@ |
186 | extsb. %2,%1 | |
187 | #" | |
188 | [(set_attr "type" "compare") | |
189 | (set_attr "length" "4,8")]) | |
190 | ||
191 | (define_split | |
192 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
193 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
194 | (const_int 0))) | |
195 | (clobber (match_scratch:DI 2 ""))] | |
196 | "TARGET_POWERPC64 && reload_completed" | |
197 | [(set (match_dup 2) | |
198 | (sign_extend:DI (match_dup 1))) | |
199 | (set (match_dup 0) | |
200 | (compare:CC (match_dup 2) | |
201 | (const_int 0)))] | |
202 | "") | |
51b8fc2c RK |
203 | |
204 | (define_insn "" | |
9ebbca7d GK |
205 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
206 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 207 | (const_int 0))) |
9ebbca7d | 208 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
209 | (sign_extend:DI (match_dup 1)))] |
210 | "TARGET_POWERPC64" | |
9ebbca7d GK |
211 | "@ |
212 | extsb. %0,%1 | |
213 | #" | |
214 | [(set_attr "type" "compare") | |
215 | (set_attr "length" "4,8")]) | |
216 | ||
217 | (define_split | |
218 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
219 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
220 | (const_int 0))) | |
221 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
222 | (sign_extend:DI (match_dup 1)))] | |
223 | "TARGET_POWERPC64 && reload_completed" | |
224 | [(set (match_dup 0) | |
225 | (sign_extend:DI (match_dup 1))) | |
226 | (set (match_dup 2) | |
227 | (compare:CC (match_dup 0) | |
228 | (const_int 0)))] | |
229 | "") | |
51b8fc2c RK |
230 | |
231 | (define_expand "zero_extendhidi2" | |
232 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
233 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
234 | "TARGET_POWERPC64" | |
235 | "") | |
236 | ||
237 | (define_insn "" | |
238 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
239 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
240 | "TARGET_POWERPC64" | |
241 | "@ | |
242 | lhz%U1%X1 %0,%1 | |
4371f8af | 243 | rldicl %0,%1,0,48" |
51b8fc2c RK |
244 | [(set_attr "type" "load,*")]) |
245 | ||
246 | (define_insn "" | |
9ebbca7d GK |
247 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
248 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 249 | (const_int 0))) |
9ebbca7d | 250 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 251 | "TARGET_POWERPC64" |
9ebbca7d GK |
252 | "@ |
253 | rldicl. %2,%1,0,48 | |
254 | #" | |
255 | [(set_attr "type" "compare") | |
256 | (set_attr "length" "4,8")]) | |
257 | ||
258 | (define_split | |
259 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
260 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
261 | (const_int 0))) | |
262 | (clobber (match_scratch:DI 2 ""))] | |
263 | "TARGET_POWERPC64 && reload_completed" | |
264 | [(set (match_dup 2) | |
265 | (zero_extend:DI (match_dup 1))) | |
266 | (set (match_dup 0) | |
267 | (compare:CC (match_dup 2) | |
268 | (const_int 0)))] | |
269 | "") | |
51b8fc2c RK |
270 | |
271 | (define_insn "" | |
9ebbca7d GK |
272 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
273 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 274 | (const_int 0))) |
9ebbca7d | 275 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
276 | (zero_extend:DI (match_dup 1)))] |
277 | "TARGET_POWERPC64" | |
9ebbca7d GK |
278 | "@ |
279 | rldicl. %0,%1,0,48 | |
280 | #" | |
281 | [(set_attr "type" "compare") | |
282 | (set_attr "length" "4,8")]) | |
283 | ||
284 | (define_split | |
285 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
286 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
287 | (const_int 0))) | |
288 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
289 | (zero_extend:DI (match_dup 1)))] | |
290 | "TARGET_POWERPC64 && reload_completed" | |
291 | [(set (match_dup 0) | |
292 | (zero_extend:DI (match_dup 1))) | |
293 | (set (match_dup 2) | |
294 | (compare:CC (match_dup 0) | |
295 | (const_int 0)))] | |
296 | "") | |
51b8fc2c RK |
297 | |
298 | (define_expand "extendhidi2" | |
299 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
300 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
301 | "TARGET_POWERPC64" | |
302 | "") | |
303 | ||
304 | (define_insn "" | |
305 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
306 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
307 | "TARGET_POWERPC64" | |
308 | "@ | |
309 | lha%U1%X1 %0,%1 | |
310 | extsh %0,%1" | |
b54cf83a | 311 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
312 | |
313 | (define_insn "" | |
9ebbca7d GK |
314 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
315 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 316 | (const_int 0))) |
9ebbca7d | 317 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 318 | "TARGET_POWERPC64" |
9ebbca7d GK |
319 | "@ |
320 | extsh. %2,%1 | |
321 | #" | |
322 | [(set_attr "type" "compare") | |
323 | (set_attr "length" "4,8")]) | |
324 | ||
325 | (define_split | |
326 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
327 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
328 | (const_int 0))) | |
329 | (clobber (match_scratch:DI 2 ""))] | |
330 | "TARGET_POWERPC64 && reload_completed" | |
331 | [(set (match_dup 2) | |
332 | (sign_extend:DI (match_dup 1))) | |
333 | (set (match_dup 0) | |
334 | (compare:CC (match_dup 2) | |
335 | (const_int 0)))] | |
336 | "") | |
51b8fc2c RK |
337 | |
338 | (define_insn "" | |
9ebbca7d GK |
339 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
340 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 341 | (const_int 0))) |
9ebbca7d | 342 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
343 | (sign_extend:DI (match_dup 1)))] |
344 | "TARGET_POWERPC64" | |
9ebbca7d GK |
345 | "@ |
346 | extsh. %0,%1 | |
347 | #" | |
348 | [(set_attr "type" "compare") | |
349 | (set_attr "length" "4,8")]) | |
350 | ||
351 | (define_split | |
352 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
353 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
354 | (const_int 0))) | |
355 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
356 | (sign_extend:DI (match_dup 1)))] | |
357 | "TARGET_POWERPC64 && reload_completed" | |
358 | [(set (match_dup 0) | |
359 | (sign_extend:DI (match_dup 1))) | |
360 | (set (match_dup 2) | |
361 | (compare:CC (match_dup 0) | |
362 | (const_int 0)))] | |
363 | "") | |
51b8fc2c RK |
364 | |
365 | (define_expand "zero_extendsidi2" | |
366 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
367 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
368 | "TARGET_POWERPC64" | |
369 | "") | |
370 | ||
371 | (define_insn "" | |
372 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
373 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
374 | "TARGET_POWERPC64" | |
375 | "@ | |
376 | lwz%U1%X1 %0,%1 | |
377 | rldicl %0,%1,0,32" | |
378 | [(set_attr "type" "load,*")]) | |
379 | ||
380 | (define_insn "" | |
9ebbca7d GK |
381 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
382 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 383 | (const_int 0))) |
9ebbca7d | 384 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 385 | "TARGET_POWERPC64" |
9ebbca7d GK |
386 | "@ |
387 | rldicl. %2,%1,0,32 | |
388 | #" | |
389 | [(set_attr "type" "compare") | |
390 | (set_attr "length" "4,8")]) | |
391 | ||
392 | (define_split | |
393 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
394 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
395 | (const_int 0))) | |
396 | (clobber (match_scratch:DI 2 ""))] | |
397 | "TARGET_POWERPC64 && reload_completed" | |
398 | [(set (match_dup 2) | |
399 | (zero_extend:DI (match_dup 1))) | |
400 | (set (match_dup 0) | |
401 | (compare:CC (match_dup 2) | |
402 | (const_int 0)))] | |
403 | "") | |
51b8fc2c RK |
404 | |
405 | (define_insn "" | |
9ebbca7d GK |
406 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
407 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 408 | (const_int 0))) |
9ebbca7d | 409 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
410 | (zero_extend:DI (match_dup 1)))] |
411 | "TARGET_POWERPC64" | |
9ebbca7d GK |
412 | "@ |
413 | rldicl. %0,%1,0,32 | |
414 | #" | |
415 | [(set_attr "type" "compare") | |
416 | (set_attr "length" "4,8")]) | |
417 | ||
418 | (define_split | |
419 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
420 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
421 | (const_int 0))) | |
422 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
423 | (zero_extend:DI (match_dup 1)))] | |
424 | "TARGET_POWERPC64 && reload_completed" | |
425 | [(set (match_dup 0) | |
426 | (zero_extend:DI (match_dup 1))) | |
427 | (set (match_dup 2) | |
428 | (compare:CC (match_dup 0) | |
429 | (const_int 0)))] | |
430 | "") | |
51b8fc2c RK |
431 | |
432 | (define_expand "extendsidi2" | |
433 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
434 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
435 | "TARGET_POWERPC64" | |
436 | "") | |
437 | ||
438 | (define_insn "" | |
439 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 440 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
441 | "TARGET_POWERPC64" |
442 | "@ | |
443 | lwa%U1%X1 %0,%1 | |
444 | extsw %0,%1" | |
b54cf83a | 445 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
446 | |
447 | (define_insn "" | |
9ebbca7d GK |
448 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
449 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 450 | (const_int 0))) |
9ebbca7d | 451 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 452 | "TARGET_POWERPC64" |
9ebbca7d GK |
453 | "@ |
454 | extsw. %2,%1 | |
455 | #" | |
456 | [(set_attr "type" "compare") | |
457 | (set_attr "length" "4,8")]) | |
458 | ||
459 | (define_split | |
460 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
461 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
462 | (const_int 0))) | |
463 | (clobber (match_scratch:DI 2 ""))] | |
464 | "TARGET_POWERPC64 && reload_completed" | |
465 | [(set (match_dup 2) | |
466 | (sign_extend:DI (match_dup 1))) | |
467 | (set (match_dup 0) | |
468 | (compare:CC (match_dup 2) | |
469 | (const_int 0)))] | |
470 | "") | |
51b8fc2c RK |
471 | |
472 | (define_insn "" | |
9ebbca7d GK |
473 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
474 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 475 | (const_int 0))) |
9ebbca7d | 476 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
477 | (sign_extend:DI (match_dup 1)))] |
478 | "TARGET_POWERPC64" | |
9ebbca7d GK |
479 | "@ |
480 | extsw. %0,%1 | |
481 | #" | |
482 | [(set_attr "type" "compare") | |
483 | (set_attr "length" "4,8")]) | |
484 | ||
485 | (define_split | |
486 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
487 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
488 | (const_int 0))) | |
489 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
490 | (sign_extend:DI (match_dup 1)))] | |
491 | "TARGET_POWERPC64 && reload_completed" | |
492 | [(set (match_dup 0) | |
493 | (sign_extend:DI (match_dup 1))) | |
494 | (set (match_dup 2) | |
495 | (compare:CC (match_dup 0) | |
496 | (const_int 0)))] | |
497 | "") | |
51b8fc2c | 498 | |
1fd4e8c1 | 499 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
500 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
501 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
502 | "" |
503 | "") | |
504 | ||
505 | (define_insn "" | |
cd2b37d9 | 506 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
507 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
508 | "" | |
509 | "@ | |
510 | lbz%U1%X1 %0,%1 | |
005a35b9 | 511 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
512 | [(set_attr "type" "load,*")]) |
513 | ||
514 | (define_insn "" | |
9ebbca7d GK |
515 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
516 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 517 | (const_int 0))) |
9ebbca7d | 518 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 519 | "" |
9ebbca7d GK |
520 | "@ |
521 | {andil.|andi.} %2,%1,0xff | |
522 | #" | |
523 | [(set_attr "type" "compare") | |
524 | (set_attr "length" "4,8")]) | |
525 | ||
526 | (define_split | |
527 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
528 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
529 | (const_int 0))) | |
530 | (clobber (match_scratch:SI 2 ""))] | |
531 | "reload_completed" | |
532 | [(set (match_dup 2) | |
533 | (zero_extend:SI (match_dup 1))) | |
534 | (set (match_dup 0) | |
535 | (compare:CC (match_dup 2) | |
536 | (const_int 0)))] | |
537 | "") | |
1fd4e8c1 RK |
538 | |
539 | (define_insn "" | |
9ebbca7d GK |
540 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
541 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 542 | (const_int 0))) |
9ebbca7d | 543 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
544 | (zero_extend:SI (match_dup 1)))] |
545 | "" | |
9ebbca7d GK |
546 | "@ |
547 | {andil.|andi.} %0,%1,0xff | |
548 | #" | |
549 | [(set_attr "type" "compare") | |
550 | (set_attr "length" "4,8")]) | |
551 | ||
552 | (define_split | |
553 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
554 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
555 | (const_int 0))) | |
556 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
557 | (zero_extend:SI (match_dup 1)))] | |
558 | "reload_completed" | |
559 | [(set (match_dup 0) | |
560 | (zero_extend:SI (match_dup 1))) | |
561 | (set (match_dup 2) | |
562 | (compare:CC (match_dup 0) | |
563 | (const_int 0)))] | |
564 | "") | |
1fd4e8c1 | 565 | |
51b8fc2c RK |
566 | (define_expand "extendqisi2" |
567 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
568 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
569 | "" | |
570 | " | |
571 | { | |
572 | if (TARGET_POWERPC) | |
573 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
574 | else if (TARGET_POWER) | |
575 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
576 | else | |
577 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
578 | DONE; | |
579 | }") | |
580 | ||
581 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
582 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
583 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 584 | "TARGET_POWERPC" |
2bee0449 | 585 | "extsb %0,%1") |
51b8fc2c RK |
586 | |
587 | (define_insn "" | |
9ebbca7d GK |
588 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
589 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 590 | (const_int 0))) |
9ebbca7d | 591 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 592 | "TARGET_POWERPC" |
9ebbca7d GK |
593 | "@ |
594 | extsb. %2,%1 | |
595 | #" | |
596 | [(set_attr "type" "compare") | |
597 | (set_attr "length" "4,8")]) | |
598 | ||
599 | (define_split | |
600 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
601 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
602 | (const_int 0))) | |
603 | (clobber (match_scratch:SI 2 ""))] | |
604 | "TARGET_POWERPC && reload_completed" | |
605 | [(set (match_dup 2) | |
606 | (sign_extend:SI (match_dup 1))) | |
607 | (set (match_dup 0) | |
608 | (compare:CC (match_dup 2) | |
609 | (const_int 0)))] | |
610 | "") | |
51b8fc2c RK |
611 | |
612 | (define_insn "" | |
9ebbca7d GK |
613 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
614 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 615 | (const_int 0))) |
9ebbca7d | 616 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
617 | (sign_extend:SI (match_dup 1)))] |
618 | "TARGET_POWERPC" | |
9ebbca7d GK |
619 | "@ |
620 | extsb. %0,%1 | |
621 | #" | |
622 | [(set_attr "type" "compare") | |
623 | (set_attr "length" "4,8")]) | |
624 | ||
625 | (define_split | |
626 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
627 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
628 | (const_int 0))) | |
629 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
630 | (sign_extend:SI (match_dup 1)))] | |
631 | "TARGET_POWERPC && reload_completed" | |
632 | [(set (match_dup 0) | |
633 | (sign_extend:SI (match_dup 1))) | |
634 | (set (match_dup 2) | |
635 | (compare:CC (match_dup 0) | |
636 | (const_int 0)))] | |
637 | "") | |
51b8fc2c RK |
638 | |
639 | (define_expand "extendqisi2_power" | |
640 | [(parallel [(set (match_dup 2) | |
641 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
642 | (const_int 24))) | |
643 | (clobber (scratch:SI))]) | |
644 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
645 | (ashiftrt:SI (match_dup 2) | |
646 | (const_int 24))) | |
647 | (clobber (scratch:SI))])] | |
648 | "TARGET_POWER" | |
649 | " | |
650 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
651 | operands[2] = gen_reg_rtx (SImode); }") | |
652 | ||
653 | (define_expand "extendqisi2_no_power" | |
654 | [(set (match_dup 2) | |
655 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
656 | (const_int 24))) | |
657 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
658 | (ashiftrt:SI (match_dup 2) | |
659 | (const_int 24)))] | |
660 | "! TARGET_POWER && ! TARGET_POWERPC" | |
661 | " | |
662 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
663 | operands[2] = gen_reg_rtx (SImode); }") | |
664 | ||
1fd4e8c1 | 665 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
666 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
667 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
668 | "" |
669 | "") | |
670 | ||
671 | (define_insn "" | |
cd2b37d9 | 672 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
673 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
674 | "" | |
675 | "@ | |
676 | lbz%U1%X1 %0,%1 | |
005a35b9 | 677 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
678 | [(set_attr "type" "load,*")]) |
679 | ||
680 | (define_insn "" | |
9ebbca7d GK |
681 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
682 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 683 | (const_int 0))) |
9ebbca7d | 684 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 685 | "" |
9ebbca7d GK |
686 | "@ |
687 | {andil.|andi.} %2,%1,0xff | |
688 | #" | |
689 | [(set_attr "type" "compare") | |
690 | (set_attr "length" "4,8")]) | |
691 | ||
692 | (define_split | |
693 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
694 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
695 | (const_int 0))) | |
696 | (clobber (match_scratch:HI 2 ""))] | |
697 | "reload_completed" | |
698 | [(set (match_dup 2) | |
699 | (zero_extend:HI (match_dup 1))) | |
700 | (set (match_dup 0) | |
701 | (compare:CC (match_dup 2) | |
702 | (const_int 0)))] | |
703 | "") | |
1fd4e8c1 | 704 | |
51b8fc2c | 705 | (define_insn "" |
9ebbca7d GK |
706 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
707 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 708 | (const_int 0))) |
9ebbca7d | 709 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
710 | (zero_extend:HI (match_dup 1)))] |
711 | "" | |
9ebbca7d GK |
712 | "@ |
713 | {andil.|andi.} %0,%1,0xff | |
714 | #" | |
715 | [(set_attr "type" "compare") | |
716 | (set_attr "length" "4,8")]) | |
717 | ||
718 | (define_split | |
719 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
720 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
721 | (const_int 0))) | |
722 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
723 | (zero_extend:HI (match_dup 1)))] | |
724 | "reload_completed" | |
725 | [(set (match_dup 0) | |
726 | (zero_extend:HI (match_dup 1))) | |
727 | (set (match_dup 2) | |
728 | (compare:CC (match_dup 0) | |
729 | (const_int 0)))] | |
730 | "") | |
815cdc52 MM |
731 | |
732 | (define_expand "extendqihi2" | |
733 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
734 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
735 | "" | |
736 | " | |
737 | { | |
738 | if (TARGET_POWERPC) | |
739 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
740 | else if (TARGET_POWER) | |
741 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
742 | else | |
743 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
744 | DONE; | |
745 | }") | |
746 | ||
747 | (define_insn "extendqihi2_ppc" | |
748 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
749 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
750 | "TARGET_POWERPC" | |
751 | "extsb %0,%1") | |
752 | ||
753 | (define_insn "" | |
9ebbca7d GK |
754 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
755 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 756 | (const_int 0))) |
9ebbca7d | 757 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 758 | "TARGET_POWERPC" |
9ebbca7d GK |
759 | "@ |
760 | extsb. %2,%1 | |
761 | #" | |
762 | [(set_attr "type" "compare") | |
763 | (set_attr "length" "4,8")]) | |
764 | ||
765 | (define_split | |
766 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
767 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
768 | (const_int 0))) | |
769 | (clobber (match_scratch:HI 2 ""))] | |
770 | "TARGET_POWERPC && reload_completed" | |
771 | [(set (match_dup 2) | |
772 | (sign_extend:HI (match_dup 1))) | |
773 | (set (match_dup 0) | |
774 | (compare:CC (match_dup 2) | |
775 | (const_int 0)))] | |
776 | "") | |
815cdc52 MM |
777 | |
778 | (define_insn "" | |
9ebbca7d GK |
779 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
780 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 781 | (const_int 0))) |
9ebbca7d | 782 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
783 | (sign_extend:HI (match_dup 1)))] |
784 | "TARGET_POWERPC" | |
9ebbca7d GK |
785 | "@ |
786 | extsb. %0,%1 | |
787 | #" | |
788 | [(set_attr "type" "compare") | |
789 | (set_attr "length" "4,8")]) | |
790 | ||
791 | (define_split | |
792 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
793 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
794 | (const_int 0))) | |
795 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
796 | (sign_extend:HI (match_dup 1)))] | |
797 | "TARGET_POWERPC && reload_completed" | |
798 | [(set (match_dup 0) | |
799 | (sign_extend:HI (match_dup 1))) | |
800 | (set (match_dup 2) | |
801 | (compare:CC (match_dup 0) | |
802 | (const_int 0)))] | |
803 | "") | |
51b8fc2c RK |
804 | |
805 | (define_expand "extendqihi2_power" | |
806 | [(parallel [(set (match_dup 2) | |
807 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
808 | (const_int 24))) | |
809 | (clobber (scratch:SI))]) | |
810 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
811 | (ashiftrt:SI (match_dup 2) | |
812 | (const_int 24))) | |
813 | (clobber (scratch:SI))])] | |
814 | "TARGET_POWER" | |
815 | " | |
816 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
817 | operands[1] = gen_lowpart (SImode, operands[1]); | |
818 | operands[2] = gen_reg_rtx (SImode); }") | |
819 | ||
820 | (define_expand "extendqihi2_no_power" | |
821 | [(set (match_dup 2) | |
822 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
823 | (const_int 24))) | |
824 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
825 | (ashiftrt:SI (match_dup 2) | |
826 | (const_int 24)))] | |
827 | "! TARGET_POWER && ! TARGET_POWERPC" | |
828 | " | |
829 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
830 | operands[1] = gen_lowpart (SImode, operands[1]); | |
831 | operands[2] = gen_reg_rtx (SImode); }") | |
832 | ||
1fd4e8c1 | 833 | (define_expand "zero_extendhisi2" |
5f243543 | 834 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 835 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
836 | "" |
837 | "") | |
838 | ||
839 | (define_insn "" | |
cd2b37d9 | 840 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
841 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
842 | "" | |
843 | "@ | |
844 | lhz%U1%X1 %0,%1 | |
005a35b9 | 845 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
846 | [(set_attr "type" "load,*")]) |
847 | ||
848 | (define_insn "" | |
9ebbca7d GK |
849 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
850 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 851 | (const_int 0))) |
9ebbca7d | 852 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 853 | "" |
9ebbca7d GK |
854 | "@ |
855 | {andil.|andi.} %2,%1,0xffff | |
856 | #" | |
857 | [(set_attr "type" "compare") | |
858 | (set_attr "length" "4,8")]) | |
859 | ||
860 | (define_split | |
861 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
862 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
863 | (const_int 0))) | |
864 | (clobber (match_scratch:SI 2 ""))] | |
865 | "reload_completed" | |
866 | [(set (match_dup 2) | |
867 | (zero_extend:SI (match_dup 1))) | |
868 | (set (match_dup 0) | |
869 | (compare:CC (match_dup 2) | |
870 | (const_int 0)))] | |
871 | "") | |
1fd4e8c1 RK |
872 | |
873 | (define_insn "" | |
9ebbca7d GK |
874 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
875 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 876 | (const_int 0))) |
9ebbca7d | 877 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
878 | (zero_extend:SI (match_dup 1)))] |
879 | "" | |
9ebbca7d GK |
880 | "@ |
881 | {andil.|andi.} %0,%1,0xffff | |
882 | #" | |
883 | [(set_attr "type" "compare") | |
884 | (set_attr "length" "4,8")]) | |
885 | ||
886 | (define_split | |
887 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
888 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
889 | (const_int 0))) | |
890 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
891 | (zero_extend:SI (match_dup 1)))] | |
892 | "reload_completed" | |
893 | [(set (match_dup 0) | |
894 | (zero_extend:SI (match_dup 1))) | |
895 | (set (match_dup 2) | |
896 | (compare:CC (match_dup 0) | |
897 | (const_int 0)))] | |
898 | "") | |
1fd4e8c1 RK |
899 | |
900 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
901 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
902 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
903 | "" |
904 | "") | |
905 | ||
906 | (define_insn "" | |
cd2b37d9 | 907 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
908 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
909 | "" | |
910 | "@ | |
911 | lha%U1%X1 %0,%1 | |
ca7f5001 | 912 | {exts|extsh} %0,%1" |
b54cf83a | 913 | [(set_attr "type" "load_ext,*")]) |
1fd4e8c1 RK |
914 | |
915 | (define_insn "" | |
9ebbca7d GK |
916 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
917 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 918 | (const_int 0))) |
9ebbca7d | 919 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 920 | "" |
9ebbca7d GK |
921 | "@ |
922 | {exts.|extsh.} %2,%1 | |
923 | #" | |
924 | [(set_attr "type" "compare") | |
925 | (set_attr "length" "4,8")]) | |
926 | ||
927 | (define_split | |
928 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
929 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
930 | (const_int 0))) | |
931 | (clobber (match_scratch:SI 2 ""))] | |
932 | "reload_completed" | |
933 | [(set (match_dup 2) | |
934 | (sign_extend:SI (match_dup 1))) | |
935 | (set (match_dup 0) | |
936 | (compare:CC (match_dup 2) | |
937 | (const_int 0)))] | |
938 | "") | |
1fd4e8c1 RK |
939 | |
940 | (define_insn "" | |
9ebbca7d GK |
941 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
942 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 943 | (const_int 0))) |
9ebbca7d | 944 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
945 | (sign_extend:SI (match_dup 1)))] |
946 | "" | |
9ebbca7d GK |
947 | "@ |
948 | {exts.|extsh.} %0,%1 | |
949 | #" | |
950 | [(set_attr "type" "compare") | |
951 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 952 | \f |
9ebbca7d GK |
953 | (define_split |
954 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
955 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
956 | (const_int 0))) | |
957 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
958 | (sign_extend:SI (match_dup 1)))] | |
959 | "reload_completed" | |
960 | [(set (match_dup 0) | |
961 | (sign_extend:SI (match_dup 1))) | |
962 | (set (match_dup 2) | |
963 | (compare:CC (match_dup 0) | |
964 | (const_int 0)))] | |
965 | "") | |
966 | ||
1fd4e8c1 | 967 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
968 | |
969 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
970 | ;; allowing register zero as source. | |
7cd5235b MM |
971 | (define_expand "addsi3" |
972 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
973 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 974 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
975 | "" |
976 | " | |
977 | { | |
677a9668 DE |
978 | if (GET_CODE (operands[2]) == CONST_INT |
979 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 980 | { |
677a9668 | 981 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
982 | ? operands[0] : gen_reg_rtx (SImode)); |
983 | ||
2bfcf297 | 984 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 985 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 986 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
7cd5235b | 987 | |
9ebbca7d GK |
988 | /* The ordering here is important for the prolog expander. |
989 | When space is allocated from the stack, adding 'low' first may | |
990 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 991 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
992 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
993 | DONE; | |
994 | } | |
995 | }") | |
996 | ||
997 | (define_insn "*addsi3_internal1" | |
998 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
999 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1000 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1001 | "" |
1002 | "@ | |
deb9225a RK |
1003 | {cax|add} %0,%1,%2 |
1004 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1005 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1006 | {cau|addis} %0,%1,%v2" |
1007 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1008 | |
ee890fe2 SS |
1009 | (define_insn "addsi3_high" |
1010 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1011 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1012 | (high:SI (match_operand 2 "" ""))))] | |
1013 | "TARGET_MACHO && !TARGET_64BIT" | |
1014 | "{cau|addis} %0,%1,ha16(%2)" | |
1015 | [(set_attr "length" "4")]) | |
1016 | ||
7cd5235b | 1017 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1018 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1019 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1020 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1021 | (const_int 0))) |
cb8cc086 | 1022 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1023 | "! TARGET_POWERPC64" |
deb9225a RK |
1024 | "@ |
1025 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1026 | {ai.|addic.} %3,%1,%2 |
1027 | # | |
1028 | #" | |
a62bfff2 | 1029 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1030 | (set_attr "length" "4,4,8,8")]) |
1031 | ||
1032 | (define_split | |
1033 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1034 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1035 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1036 | (const_int 0))) | |
1037 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1038 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1039 | [(set (match_dup 3) |
1040 | (plus:SI (match_dup 1) | |
1041 | (match_dup 2))) | |
1042 | (set (match_dup 0) | |
1043 | (compare:CC (match_dup 3) | |
1044 | (const_int 0)))] | |
1045 | "") | |
7e69e155 | 1046 | |
7cd5235b | 1047 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1048 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1049 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1050 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1051 | (const_int 0))) |
cb8cc086 MM |
1052 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1053 | (plus:SI (match_dup 1) | |
1054 | (match_dup 2)))] | |
0ad91047 | 1055 | "! TARGET_POWERPC64" |
deb9225a RK |
1056 | "@ |
1057 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1058 | {ai.|addic.} %0,%1,%2 |
1059 | # | |
1060 | #" | |
a62bfff2 | 1061 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1062 | (set_attr "length" "4,4,8,8")]) |
1063 | ||
1064 | (define_split | |
1065 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1066 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1067 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1068 | (const_int 0))) | |
1069 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1070 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1071 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1072 | [(set (match_dup 0) |
1073 | (plus:SI (match_dup 1) | |
1074 | (match_dup 2))) | |
1075 | (set (match_dup 3) | |
1076 | (compare:CC (match_dup 0) | |
1077 | (const_int 0)))] | |
1078 | "") | |
7e69e155 | 1079 | |
f357808b RK |
1080 | ;; Split an add that we can't do in one insn into two insns, each of which |
1081 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1082 | ;; add should be last in case the result gets used in an address. | |
1083 | ||
1084 | (define_split | |
cd2b37d9 RK |
1085 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1086 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1087 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1088 | "" |
f357808b RK |
1089 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1090 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1091 | " | |
1fd4e8c1 | 1092 | { |
2bfcf297 | 1093 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1094 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1095 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
1fd4e8c1 | 1096 | |
2bfcf297 | 1097 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1098 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1099 | }") |
1100 | ||
8de2a197 | 1101 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1102 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1103 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1104 | "" |
ca7f5001 RK |
1105 | "nor %0,%1,%1") |
1106 | ||
1107 | (define_insn "" | |
52d3af72 DE |
1108 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1109 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1110 | (const_int 0))) |
52d3af72 | 1111 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1112 | "! TARGET_POWERPC64" |
52d3af72 DE |
1113 | "@ |
1114 | nor. %2,%1,%1 | |
1115 | #" | |
1116 | [(set_attr "type" "compare") | |
1117 | (set_attr "length" "4,8")]) | |
1118 | ||
1119 | (define_split | |
1120 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1121 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1122 | (const_int 0))) | |
1123 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1124 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1125 | [(set (match_dup 2) |
1126 | (not:SI (match_dup 1))) | |
1127 | (set (match_dup 0) | |
1128 | (compare:CC (match_dup 2) | |
1129 | (const_int 0)))] | |
1130 | "") | |
ca7f5001 RK |
1131 | |
1132 | (define_insn "" | |
52d3af72 DE |
1133 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1134 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1135 | (const_int 0))) |
52d3af72 | 1136 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1137 | (not:SI (match_dup 1)))] |
0ad91047 | 1138 | "! TARGET_POWERPC64" |
52d3af72 DE |
1139 | "@ |
1140 | nor. %0,%1,%1 | |
1141 | #" | |
1142 | [(set_attr "type" "compare") | |
1143 | (set_attr "length" "4,8")]) | |
1144 | ||
1145 | (define_split | |
1146 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1147 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1148 | (const_int 0))) | |
1cb18e3c | 1149 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1150 | (not:SI (match_dup 1)))] |
0ad91047 | 1151 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1152 | [(set (match_dup 0) |
1153 | (not:SI (match_dup 1))) | |
1154 | (set (match_dup 2) | |
1155 | (compare:CC (match_dup 0) | |
1156 | (const_int 0)))] | |
1157 | "") | |
1fd4e8c1 RK |
1158 | |
1159 | (define_insn "" | |
3d91674b RK |
1160 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1161 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1162 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1163 | "! TARGET_POWERPC" |
ca7f5001 | 1164 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1165 | |
deb9225a RK |
1166 | (define_insn "" |
1167 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1168 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1169 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1170 | "TARGET_POWERPC" | |
1171 | "@ | |
1172 | subf %0,%2,%1 | |
1173 | subfic %0,%2,%1") | |
1174 | ||
1fd4e8c1 | 1175 | (define_insn "" |
cb8cc086 MM |
1176 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1177 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1178 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1179 | (const_int 0))) |
cb8cc086 | 1180 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1181 | "! TARGET_POWERPC" |
cb8cc086 MM |
1182 | "@ |
1183 | {sf.|subfc.} %3,%2,%1 | |
1184 | #" | |
1185 | [(set_attr "type" "compare") | |
1186 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1187 | |
deb9225a | 1188 | (define_insn "" |
cb8cc086 MM |
1189 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1190 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1191 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1192 | (const_int 0))) |
cb8cc086 | 1193 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1194 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1195 | "@ |
1196 | subf. %3,%2,%1 | |
1197 | #" | |
a62bfff2 | 1198 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1199 | (set_attr "length" "4,8")]) |
1200 | ||
1201 | (define_split | |
1202 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1203 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1204 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1205 | (const_int 0))) | |
1206 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1207 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1208 | [(set (match_dup 3) |
1209 | (minus:SI (match_dup 1) | |
1210 | (match_dup 2))) | |
1211 | (set (match_dup 0) | |
1212 | (compare:CC (match_dup 3) | |
1213 | (const_int 0)))] | |
1214 | "") | |
deb9225a | 1215 | |
1fd4e8c1 | 1216 | (define_insn "" |
cb8cc086 MM |
1217 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1218 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1219 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1220 | (const_int 0))) |
cb8cc086 | 1221 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1222 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1223 | "! TARGET_POWERPC" |
cb8cc086 MM |
1224 | "@ |
1225 | {sf.|subfc.} %0,%2,%1 | |
1226 | #" | |
1227 | [(set_attr "type" "compare") | |
1228 | (set_attr "length" "4,8")]) | |
815cdc52 | 1229 | |
29ae5b89 | 1230 | (define_insn "" |
cb8cc086 MM |
1231 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1232 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1233 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1234 | (const_int 0))) |
cb8cc086 MM |
1235 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1236 | (minus:SI (match_dup 1) | |
1237 | (match_dup 2)))] | |
0ad91047 | 1238 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1239 | "@ |
1240 | subf. %0,%2,%1 | |
1241 | #" | |
a62bfff2 | 1242 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1243 | (set_attr "length" "4,8")]) |
1244 | ||
1245 | (define_split | |
1246 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1247 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1248 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1249 | (const_int 0))) | |
1250 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1251 | (minus:SI (match_dup 1) | |
1252 | (match_dup 2)))] | |
0ad91047 | 1253 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1254 | [(set (match_dup 0) |
1255 | (minus:SI (match_dup 1) | |
1256 | (match_dup 2))) | |
1257 | (set (match_dup 3) | |
1258 | (compare:CC (match_dup 0) | |
1259 | (const_int 0)))] | |
1260 | "") | |
deb9225a | 1261 | |
1fd4e8c1 | 1262 | (define_expand "subsi3" |
cd2b37d9 | 1263 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1264 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1265 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1266 | "" |
a0044fb1 RK |
1267 | " |
1268 | { | |
1269 | if (GET_CODE (operands[2]) == CONST_INT) | |
1270 | { | |
1271 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1272 | negate_rtx (SImode, operands[2]))); | |
1273 | DONE; | |
1274 | } | |
1275 | }") | |
1fd4e8c1 RK |
1276 | |
1277 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1278 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1279 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1280 | ;; combine. | |
1fd4e8c1 RK |
1281 | |
1282 | (define_expand "sminsi3" | |
1283 | [(set (match_dup 3) | |
cd2b37d9 | 1284 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1285 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1286 | (const_int 0) | |
1287 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1288 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1289 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1290 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1291 | " |
a3170dc6 AH |
1292 | { |
1293 | if (TARGET_ISEL) | |
1294 | { | |
1295 | operands[2] = force_reg (SImode, operands[2]); | |
1296 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
1297 | DONE; | |
1298 | } | |
1299 | ||
1300 | operands[3] = gen_reg_rtx (SImode); | |
1301 | }") | |
1fd4e8c1 | 1302 | |
95ac8e67 RK |
1303 | (define_split |
1304 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1305 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1306 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1307 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1308 | "TARGET_POWER" |
95ac8e67 RK |
1309 | [(set (match_dup 3) |
1310 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1311 | (const_int 0) | |
1312 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1313 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1314 | "") | |
1315 | ||
1fd4e8c1 RK |
1316 | (define_expand "smaxsi3" |
1317 | [(set (match_dup 3) | |
cd2b37d9 | 1318 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1319 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1320 | (const_int 0) | |
1321 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1322 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1323 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1324 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1325 | " |
a3170dc6 AH |
1326 | { |
1327 | if (TARGET_ISEL) | |
1328 | { | |
1329 | operands[2] = force_reg (SImode, operands[2]); | |
1330 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
1331 | DONE; | |
1332 | } | |
1333 | operands[3] = gen_reg_rtx (SImode); | |
1334 | }") | |
1fd4e8c1 | 1335 | |
95ac8e67 RK |
1336 | (define_split |
1337 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1338 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1339 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1340 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1341 | "TARGET_POWER" |
95ac8e67 RK |
1342 | [(set (match_dup 3) |
1343 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1344 | (const_int 0) | |
1345 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1346 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1347 | "") | |
1348 | ||
1fd4e8c1 | 1349 | (define_expand "uminsi3" |
cd2b37d9 | 1350 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1351 | (match_dup 5))) |
cd2b37d9 | 1352 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1353 | (match_dup 5))) |
1fd4e8c1 RK |
1354 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1355 | (const_int 0) | |
1356 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1357 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1358 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1359 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1360 | " |
bb68ff55 | 1361 | { |
a3170dc6 AH |
1362 | if (TARGET_ISEL) |
1363 | { | |
1364 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
1365 | DONE; | |
1366 | } | |
bb68ff55 MM |
1367 | operands[3] = gen_reg_rtx (SImode); |
1368 | operands[4] = gen_reg_rtx (SImode); | |
1369 | operands[5] = GEN_INT (-2147483647 - 1); | |
1370 | }") | |
1fd4e8c1 RK |
1371 | |
1372 | (define_expand "umaxsi3" | |
cd2b37d9 | 1373 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1374 | (match_dup 5))) |
cd2b37d9 | 1375 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1376 | (match_dup 5))) |
1fd4e8c1 RK |
1377 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1378 | (const_int 0) | |
1379 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1380 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1381 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1382 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1383 | " |
bb68ff55 | 1384 | { |
a3170dc6 AH |
1385 | if (TARGET_ISEL) |
1386 | { | |
1387 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
1388 | DONE; | |
1389 | } | |
bb68ff55 MM |
1390 | operands[3] = gen_reg_rtx (SImode); |
1391 | operands[4] = gen_reg_rtx (SImode); | |
1392 | operands[5] = GEN_INT (-2147483647 - 1); | |
1393 | }") | |
1fd4e8c1 RK |
1394 | |
1395 | (define_insn "" | |
cd2b37d9 RK |
1396 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1397 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1398 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1399 | (const_int 0) |
1400 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1401 | "TARGET_POWER" |
1fd4e8c1 RK |
1402 | "doz%I2 %0,%1,%2") |
1403 | ||
1404 | (define_insn "" | |
9ebbca7d | 1405 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1406 | (compare:CC |
9ebbca7d GK |
1407 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1408 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1409 | (const_int 0) |
1410 | (minus:SI (match_dup 2) (match_dup 1))) | |
1411 | (const_int 0))) | |
9ebbca7d | 1412 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1413 | "TARGET_POWER" |
9ebbca7d GK |
1414 | "@ |
1415 | doz%I2. %3,%1,%2 | |
1416 | #" | |
1417 | [(set_attr "type" "delayed_compare") | |
1418 | (set_attr "length" "4,8")]) | |
1419 | ||
1420 | (define_split | |
1421 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1422 | (compare:CC | |
1423 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1424 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1425 | (const_int 0) | |
1426 | (minus:SI (match_dup 2) (match_dup 1))) | |
1427 | (const_int 0))) | |
1428 | (clobber (match_scratch:SI 3 ""))] | |
1429 | "TARGET_POWER && reload_completed" | |
1430 | [(set (match_dup 3) | |
1431 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1432 | (const_int 0) | |
1433 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1434 | (set (match_dup 0) | |
1435 | (compare:CC (match_dup 3) | |
1436 | (const_int 0)))] | |
1437 | "") | |
1fd4e8c1 RK |
1438 | |
1439 | (define_insn "" | |
9ebbca7d | 1440 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1441 | (compare:CC |
9ebbca7d GK |
1442 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1443 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1444 | (const_int 0) |
1445 | (minus:SI (match_dup 2) (match_dup 1))) | |
1446 | (const_int 0))) | |
9ebbca7d | 1447 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1448 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1449 | (const_int 0) | |
1450 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1451 | "TARGET_POWER" |
9ebbca7d GK |
1452 | "@ |
1453 | doz%I2. %0,%1,%2 | |
1454 | #" | |
1455 | [(set_attr "type" "delayed_compare") | |
1456 | (set_attr "length" "4,8")]) | |
1457 | ||
1458 | (define_split | |
1459 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1460 | (compare:CC | |
1461 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1462 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1463 | (const_int 0) | |
1464 | (minus:SI (match_dup 2) (match_dup 1))) | |
1465 | (const_int 0))) | |
1466 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1467 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1468 | (const_int 0) | |
1469 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1470 | "TARGET_POWER && reload_completed" | |
1471 | [(set (match_dup 0) | |
1472 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1473 | (const_int 0) | |
1474 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1475 | (set (match_dup 3) | |
1476 | (compare:CC (match_dup 0) | |
1477 | (const_int 0)))] | |
1478 | "") | |
1fd4e8c1 RK |
1479 | |
1480 | ;; We don't need abs with condition code because such comparisons should | |
1481 | ;; never be done. | |
ea9be077 MM |
1482 | (define_expand "abssi2" |
1483 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1484 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1485 | "" | |
1486 | " | |
1487 | { | |
a3170dc6 AH |
1488 | if (TARGET_ISEL) |
1489 | { | |
1490 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
1491 | DONE; | |
1492 | } | |
1493 | else if (! TARGET_POWER) | |
ea9be077 MM |
1494 | { |
1495 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1496 | DONE; | |
1497 | } | |
1498 | }") | |
1499 | ||
ea112fc4 | 1500 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
1501 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1502 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1503 | "TARGET_POWER" |
1fd4e8c1 RK |
1504 | "abs %0,%1") |
1505 | ||
a3170dc6 AH |
1506 | (define_insn_and_split "abssi2_isel" |
1507 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1508 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
1509 | (clobber (match_scratch:SI 2 "=b")) | |
1510 | (clobber (match_scratch:CC 3 "=y"))] | |
1511 | "TARGET_ISEL" | |
1512 | "#" | |
1513 | "&& reload_completed" | |
1514 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
1515 | (set (match_dup 3) | |
1516 | (compare:CC (match_dup 1) | |
1517 | (const_int 0))) | |
1518 | (set (match_dup 0) | |
1519 | (if_then_else:SI (ge (match_dup 3) | |
1520 | (const_int 0)) | |
1521 | (match_dup 1) | |
1522 | (match_dup 2)))] | |
1523 | "") | |
1524 | ||
ea112fc4 | 1525 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 1526 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1527 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 1528 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 1529 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
1530 | "#" |
1531 | "&& reload_completed" | |
ea9be077 MM |
1532 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1533 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1534 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1535 | "") |
1536 | ||
463b558b | 1537 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1538 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1539 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1540 | "TARGET_POWER" |
1fd4e8c1 RK |
1541 | "nabs %0,%1") |
1542 | ||
ea112fc4 | 1543 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 1544 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1545 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 1546 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 1547 | "! TARGET_POWER" |
ea112fc4 DE |
1548 | "#" |
1549 | "&& reload_completed" | |
ea9be077 MM |
1550 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1551 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1552 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1553 | "") |
1554 | ||
1fd4e8c1 | 1555 | (define_insn "negsi2" |
cd2b37d9 RK |
1556 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1557 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1558 | "" |
1559 | "neg %0,%1") | |
1560 | ||
1561 | (define_insn "" | |
9ebbca7d GK |
1562 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1563 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1564 | (const_int 0))) |
9ebbca7d | 1565 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1566 | "! TARGET_POWERPC64" |
9ebbca7d GK |
1567 | "@ |
1568 | neg. %2,%1 | |
1569 | #" | |
a62bfff2 | 1570 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1571 | (set_attr "length" "4,8")]) |
1572 | ||
1573 | (define_split | |
1574 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1575 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1576 | (const_int 0))) | |
1577 | (clobber (match_scratch:SI 2 ""))] | |
1578 | "! TARGET_POWERPC64 && reload_completed" | |
1579 | [(set (match_dup 2) | |
1580 | (neg:SI (match_dup 1))) | |
1581 | (set (match_dup 0) | |
1582 | (compare:CC (match_dup 2) | |
1583 | (const_int 0)))] | |
1584 | "") | |
1fd4e8c1 RK |
1585 | |
1586 | (define_insn "" | |
9ebbca7d GK |
1587 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1588 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1589 | (const_int 0))) |
9ebbca7d | 1590 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1591 | (neg:SI (match_dup 1)))] |
0ad91047 | 1592 | "! TARGET_POWERPC64" |
9ebbca7d GK |
1593 | "@ |
1594 | neg. %0,%1 | |
1595 | #" | |
a62bfff2 | 1596 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1597 | (set_attr "length" "4,8")]) |
1598 | ||
1599 | (define_split | |
1600 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1601 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1602 | (const_int 0))) | |
1603 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1604 | (neg:SI (match_dup 1)))] | |
1605 | "! TARGET_POWERPC64 && reload_completed" | |
1606 | [(set (match_dup 0) | |
1607 | (neg:SI (match_dup 1))) | |
1608 | (set (match_dup 2) | |
1609 | (compare:CC (match_dup 0) | |
1610 | (const_int 0)))] | |
1611 | "") | |
1fd4e8c1 | 1612 | |
1b1edcfa DE |
1613 | (define_insn "clzsi2" |
1614 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1615 | (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1616 | "" | |
1617 | "{cntlz|cntlzw} %0,%1") | |
1618 | ||
1619 | (define_expand "ctzsi2" | |
4977bab6 | 1620 | [(set (match_dup 2) |
1b1edcfa | 1621 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 1622 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) |
1b1edcfa DE |
1623 | (match_dup 2))) |
1624 | (clobber (scratch:CC))]) | |
d865b122 | 1625 | (set (match_dup 4) (clz:SI (match_dup 3))) |
4977bab6 | 1626 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 1627 | (minus:SI (const_int 31) (match_dup 4)))] |
1fd4e8c1 | 1628 | "" |
4977bab6 ZW |
1629 | { |
1630 | operands[2] = gen_reg_rtx (SImode); | |
1631 | operands[3] = gen_reg_rtx (SImode); | |
1632 | operands[4] = gen_reg_rtx (SImode); | |
1633 | }) | |
1634 | ||
1b1edcfa DE |
1635 | (define_expand "ffssi2" |
1636 | [(set (match_dup 2) | |
1637 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
1638 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) | |
1639 | (match_dup 2))) | |
1640 | (clobber (scratch:CC))]) | |
1641 | (set (match_dup 4) (clz:SI (match_dup 3))) | |
1642 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1643 | (minus:SI (const_int 32) (match_dup 4)))] | |
4977bab6 | 1644 | "" |
1b1edcfa DE |
1645 | { |
1646 | operands[2] = gen_reg_rtx (SImode); | |
1647 | operands[3] = gen_reg_rtx (SImode); | |
1648 | operands[4] = gen_reg_rtx (SImode); | |
1649 | }) | |
1650 | ||
ca7f5001 RK |
1651 | (define_expand "mulsi3" |
1652 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1653 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1654 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1655 | "" | |
1656 | " | |
1657 | { | |
1658 | if (TARGET_POWER) | |
68b40e7e | 1659 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1660 | else |
68b40e7e | 1661 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1662 | DONE; |
1663 | }") | |
1664 | ||
68b40e7e | 1665 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1666 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1667 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1668 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1669 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1670 | "TARGET_POWER" |
1671 | "@ | |
1672 | {muls|mullw} %0,%1,%2 | |
1673 | {muli|mulli} %0,%1,%2" | |
c859cda6 DJ |
1674 | [(set (attr "type") |
1675 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
1676 | (const_string "imul3") | |
1677 | (match_operand:SI 2 "short_cint_operand" "") | |
1678 | (const_string "imul2")] | |
1679 | (const_string "imul")))]) | |
ca7f5001 | 1680 | |
68b40e7e | 1681 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1682 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1683 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1684 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1685 | "! TARGET_POWER" |
1fd4e8c1 | 1686 | "@ |
d904e9ed RK |
1687 | {muls|mullw} %0,%1,%2 |
1688 | {muli|mulli} %0,%1,%2" | |
c859cda6 DJ |
1689 | [(set (attr "type") |
1690 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
1691 | (const_string "imul3") | |
1692 | (match_operand:SI 2 "short_cint_operand" "") | |
1693 | (const_string "imul2")] | |
1694 | (const_string "imul")))]) | |
1fd4e8c1 | 1695 | |
9259f3b0 | 1696 | (define_insn "*mulsi3_mq_internal1" |
9ebbca7d GK |
1697 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1698 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1699 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1700 | (const_int 0))) |
9ebbca7d GK |
1701 | (clobber (match_scratch:SI 3 "=r,r")) |
1702 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 1703 | "TARGET_POWER" |
9ebbca7d GK |
1704 | "@ |
1705 | {muls.|mullw.} %3,%1,%2 | |
1706 | #" | |
9259f3b0 | 1707 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1708 | (set_attr "length" "4,8")]) |
1709 | ||
1710 | (define_split | |
1711 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1712 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1713 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1714 | (const_int 0))) | |
1715 | (clobber (match_scratch:SI 3 "")) | |
1716 | (clobber (match_scratch:SI 4 ""))] | |
1717 | "TARGET_POWER && reload_completed" | |
1718 | [(parallel [(set (match_dup 3) | |
1719 | (mult:SI (match_dup 1) (match_dup 2))) | |
1720 | (clobber (match_dup 4))]) | |
1721 | (set (match_dup 0) | |
1722 | (compare:CC (match_dup 3) | |
1723 | (const_int 0)))] | |
1724 | "") | |
ca7f5001 | 1725 | |
9259f3b0 | 1726 | (define_insn "*mulsi3_no_mq_internal1" |
9ebbca7d GK |
1727 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1728 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1729 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1730 | (const_int 0))) |
9ebbca7d | 1731 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 1732 | "! TARGET_POWER" |
9ebbca7d GK |
1733 | "@ |
1734 | {muls.|mullw.} %3,%1,%2 | |
1735 | #" | |
9259f3b0 | 1736 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1737 | (set_attr "length" "4,8")]) |
1738 | ||
1739 | (define_split | |
1740 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1741 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1742 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1743 | (const_int 0))) | |
1744 | (clobber (match_scratch:SI 3 ""))] | |
1745 | "! TARGET_POWER && reload_completed" | |
1746 | [(set (match_dup 3) | |
1747 | (mult:SI (match_dup 1) (match_dup 2))) | |
1748 | (set (match_dup 0) | |
1749 | (compare:CC (match_dup 3) | |
1750 | (const_int 0)))] | |
1751 | "") | |
1fd4e8c1 | 1752 | |
9259f3b0 | 1753 | (define_insn "*mulsi3_mq_internal2" |
9ebbca7d GK |
1754 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1755 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1756 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1757 | (const_int 0))) |
9ebbca7d | 1758 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 1759 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 1760 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 1761 | "TARGET_POWER" |
9ebbca7d GK |
1762 | "@ |
1763 | {muls.|mullw.} %0,%1,%2 | |
1764 | #" | |
9259f3b0 | 1765 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1766 | (set_attr "length" "4,8")]) |
1767 | ||
1768 | (define_split | |
1769 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1770 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1771 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1772 | (const_int 0))) | |
1773 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1774 | (mult:SI (match_dup 1) (match_dup 2))) | |
1775 | (clobber (match_scratch:SI 4 ""))] | |
1776 | "TARGET_POWER && reload_completed" | |
1777 | [(parallel [(set (match_dup 0) | |
1778 | (mult:SI (match_dup 1) (match_dup 2))) | |
1779 | (clobber (match_dup 4))]) | |
1780 | (set (match_dup 3) | |
1781 | (compare:CC (match_dup 0) | |
1782 | (const_int 0)))] | |
1783 | "") | |
ca7f5001 | 1784 | |
9259f3b0 | 1785 | (define_insn "*mulsi3_no_mq_internal2" |
9ebbca7d GK |
1786 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1787 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1788 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1789 | (const_int 0))) |
9ebbca7d | 1790 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 1791 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1792 | "! TARGET_POWER" |
9ebbca7d GK |
1793 | "@ |
1794 | {muls.|mullw.} %0,%1,%2 | |
1795 | #" | |
9259f3b0 | 1796 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1797 | (set_attr "length" "4,8")]) |
1798 | ||
1799 | (define_split | |
1800 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1801 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1802 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1803 | (const_int 0))) | |
1804 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1805 | (mult:SI (match_dup 1) (match_dup 2)))] | |
1806 | "! TARGET_POWER && reload_completed" | |
1807 | [(set (match_dup 0) | |
1808 | (mult:SI (match_dup 1) (match_dup 2))) | |
1809 | (set (match_dup 3) | |
1810 | (compare:CC (match_dup 0) | |
1811 | (const_int 0)))] | |
1812 | "") | |
1fd4e8c1 RK |
1813 | |
1814 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1815 | ;; 0 and remainder to operand 3. | |
1816 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1817 | ||
8ffd9c51 RK |
1818 | (define_expand "divmodsi4" |
1819 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1820 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1821 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 1822 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
1823 | (mod:SI (match_dup 1) (match_dup 2)))])] |
1824 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1825 | " | |
1826 | { | |
1827 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1828 | { | |
39403d82 DE |
1829 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1830 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1831 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1832 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1833 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1834 | DONE; |
1835 | } | |
1836 | }") | |
deb9225a | 1837 | |
bb157ff4 | 1838 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
1839 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1840 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1841 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 1842 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 1843 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1844 | "TARGET_POWER" |
cfb557c4 RK |
1845 | "divs %0,%1,%2" |
1846 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1847 | |
8ffd9c51 RK |
1848 | (define_expand "udivsi3" |
1849 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1850 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1851 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1852 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1853 | " | |
1854 | { | |
1855 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1856 | { | |
39403d82 DE |
1857 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1858 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1859 | emit_insn (gen_quous_call ()); |
39403d82 | 1860 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1861 | DONE; |
1862 | } | |
f192bf8b DE |
1863 | else if (TARGET_POWER) |
1864 | { | |
1865 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1866 | DONE; | |
1867 | } | |
8ffd9c51 | 1868 | }") |
deb9225a | 1869 | |
f192bf8b DE |
1870 | (define_insn "udivsi3_mq" |
1871 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1872 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1873 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1874 | (clobber (match_scratch:SI 3 "=q"))] | |
1875 | "TARGET_POWERPC && TARGET_POWER" | |
1876 | "divwu %0,%1,%2" | |
1877 | [(set_attr "type" "idiv")]) | |
1878 | ||
1879 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1880 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1881 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1882 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1883 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1884 | "divwu %0,%1,%2" |
ca7f5001 RK |
1885 | [(set_attr "type" "idiv")]) |
1886 | ||
1fd4e8c1 | 1887 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1888 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1889 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1890 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1891 | (define_expand "divsi3" |
cd2b37d9 RK |
1892 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1893 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1894 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1895 | "" | |
1896 | " | |
1897 | { | |
ca7f5001 | 1898 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 1899 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
1900 | && exact_log2 (INTVAL (operands[2])) >= 0) |
1901 | ; | |
b6c9286a | 1902 | else if (TARGET_POWERPC) |
f192bf8b DE |
1903 | { |
1904 | operands[2] = force_reg (SImode, operands[2]); | |
1905 | if (TARGET_POWER) | |
1906 | { | |
1907 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1908 | DONE; | |
1909 | } | |
1910 | } | |
b6c9286a | 1911 | else if (TARGET_POWER) |
1fd4e8c1 | 1912 | FAIL; |
405c5495 | 1913 | else |
8ffd9c51 | 1914 | { |
39403d82 DE |
1915 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1916 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1917 | emit_insn (gen_quoss_call ()); |
39403d82 | 1918 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1919 | DONE; |
1920 | } | |
1fd4e8c1 RK |
1921 | }") |
1922 | ||
f192bf8b DE |
1923 | (define_insn "divsi3_mq" |
1924 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1925 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1926 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1927 | (clobber (match_scratch:SI 3 "=q"))] | |
1928 | "TARGET_POWERPC && TARGET_POWER" | |
1929 | "divw %0,%1,%2" | |
1930 | [(set_attr "type" "idiv")]) | |
1931 | ||
1932 | (define_insn "*divsi3_no_mq" | |
1933 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1934 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1935 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1936 | "TARGET_POWERPC && ! TARGET_POWER" | |
1937 | "divw %0,%1,%2" | |
1938 | [(set_attr "type" "idiv")]) | |
1939 | ||
1fd4e8c1 | 1940 | (define_expand "modsi3" |
85644414 RK |
1941 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1942 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1943 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1944 | "" |
1fd4e8c1 RK |
1945 | " |
1946 | { | |
481c7efa | 1947 | int i; |
39b52ba2 RK |
1948 | rtx temp1; |
1949 | rtx temp2; | |
1950 | ||
2bfcf297 | 1951 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 1952 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 1953 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
1954 | FAIL; |
1955 | ||
1956 | temp1 = gen_reg_rtx (SImode); | |
1957 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1958 | |
85644414 | 1959 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1960 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1961 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1962 | DONE; | |
1fd4e8c1 RK |
1963 | }") |
1964 | ||
1965 | (define_insn "" | |
cd2b37d9 RK |
1966 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1967 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
1968 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
1969 | "" | |
ca7f5001 | 1970 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 1971 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
1972 | |
1973 | (define_insn "" | |
9ebbca7d GK |
1974 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1975 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 1976 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 1977 | (const_int 0))) |
9ebbca7d | 1978 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 1979 | "" |
9ebbca7d GK |
1980 | "@ |
1981 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
1982 | #" | |
b19003d8 | 1983 | [(set_attr "type" "compare") |
9ebbca7d GK |
1984 | (set_attr "length" "8,12")]) |
1985 | ||
1986 | (define_split | |
1987 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1988 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 1989 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
1990 | (const_int 0))) |
1991 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 1992 | "reload_completed" |
9ebbca7d GK |
1993 | [(set (match_dup 3) |
1994 | (div:SI (match_dup 1) (match_dup 2))) | |
1995 | (set (match_dup 0) | |
1996 | (compare:CC (match_dup 3) | |
1997 | (const_int 0)))] | |
1998 | "") | |
1fd4e8c1 RK |
1999 | |
2000 | (define_insn "" | |
9ebbca7d GK |
2001 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2002 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2003 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2004 | (const_int 0))) |
9ebbca7d | 2005 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2006 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2007 | "" |
9ebbca7d GK |
2008 | "@ |
2009 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2010 | #" | |
b19003d8 | 2011 | [(set_attr "type" "compare") |
9ebbca7d GK |
2012 | (set_attr "length" "8,12")]) |
2013 | ||
2014 | (define_split | |
2015 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2016 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2017 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2018 | (const_int 0))) |
2019 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2020 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2021 | "reload_completed" |
9ebbca7d GK |
2022 | [(set (match_dup 0) |
2023 | (div:SI (match_dup 1) (match_dup 2))) | |
2024 | (set (match_dup 3) | |
2025 | (compare:CC (match_dup 0) | |
2026 | (const_int 0)))] | |
2027 | "") | |
1fd4e8c1 RK |
2028 | |
2029 | (define_insn "" | |
cd2b37d9 | 2030 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2031 | (udiv:SI |
996a5f59 | 2032 | (plus:DI (ashift:DI |
cd2b37d9 | 2033 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2034 | (const_int 32)) |
23a900dc | 2035 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2036 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2037 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2038 | (umod:SI |
996a5f59 | 2039 | (plus:DI (ashift:DI |
1fd4e8c1 | 2040 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2041 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2042 | (match_dup 3)))] |
ca7f5001 | 2043 | "TARGET_POWER" |
cfb557c4 RK |
2044 | "div %0,%1,%3" |
2045 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2046 | |
2047 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2048 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2049 | ;; have to worry about the branches. So make a few subroutines here. | |
2050 | ;; | |
2051 | ;; First comes the normal case. | |
2052 | (define_expand "udivmodsi4_normal" | |
2053 | [(set (match_dup 4) (const_int 0)) | |
2054 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2055 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2056 | (const_int 32)) |
2057 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2058 | (match_operand:SI 2 "" ""))) | |
2059 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2060 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2061 | (const_int 32)) |
2062 | (zero_extend:DI (match_dup 1))) | |
2063 | (match_dup 2)))])] | |
ca7f5001 | 2064 | "TARGET_POWER" |
1fd4e8c1 RK |
2065 | " |
2066 | { operands[4] = gen_reg_rtx (SImode); }") | |
2067 | ||
2068 | ;; This handles the branches. | |
2069 | (define_expand "udivmodsi4_tests" | |
2070 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2071 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2072 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2073 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2074 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2075 | (set (match_dup 0) (const_int 1)) | |
2076 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2077 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2078 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2079 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2080 | "TARGET_POWER" |
1fd4e8c1 RK |
2081 | " |
2082 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2083 | operands[6] = gen_reg_rtx (CCmode); | |
2084 | }") | |
2085 | ||
2086 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2087 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2088 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2089 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2090 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2091 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2092 | "" |
1fd4e8c1 RK |
2093 | " |
2094 | { | |
2095 | rtx label = 0; | |
2096 | ||
8ffd9c51 | 2097 | if (! TARGET_POWER) |
c4d38ccb MM |
2098 | { |
2099 | if (! TARGET_POWERPC) | |
2100 | { | |
39403d82 DE |
2101 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2102 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2103 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2104 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2105 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2106 | DONE; |
2107 | } | |
2108 | else | |
2109 | FAIL; | |
2110 | } | |
0081a354 | 2111 | |
1fd4e8c1 RK |
2112 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2113 | { | |
2114 | operands[2] = force_reg (SImode, operands[2]); | |
2115 | label = gen_label_rtx (); | |
2116 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2117 | operands[3], label)); | |
2118 | } | |
2119 | else | |
2120 | operands[2] = force_reg (SImode, operands[2]); | |
2121 | ||
2122 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2123 | operands[3])); | |
2124 | if (label) | |
2125 | emit_label (label); | |
2126 | ||
2127 | DONE; | |
2128 | }") | |
0081a354 | 2129 | |
fada905b MM |
2130 | ;; AIX architecture-independent common-mode multiply (DImode), |
2131 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2132 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2133 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2134 | ;; assumed unused if generating common-mode, so ignore. | |
2135 | (define_insn "mulh_call" | |
2136 | [(set (reg:SI 3) | |
2137 | (truncate:SI | |
2138 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2139 | (sign_extend:DI (reg:SI 4))) | |
2140 | (const_int 32)))) | |
cf27b467 | 2141 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2142 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2143 | "bla __mulh" |
2144 | [(set_attr "type" "imul")]) | |
fada905b MM |
2145 | |
2146 | (define_insn "mull_call" | |
2147 | [(set (reg:DI 3) | |
2148 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2149 | (sign_extend:DI (reg:SI 4)))) | |
2150 | (clobber (match_scratch:SI 0 "=l")) | |
2151 | (clobber (reg:SI 0))] | |
2152 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2153 | "bla __mull" |
2154 | [(set_attr "type" "imul")]) | |
fada905b MM |
2155 | |
2156 | (define_insn "divss_call" | |
2157 | [(set (reg:SI 3) | |
2158 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2159 | (set (reg:SI 4) | |
2160 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2161 | (clobber (match_scratch:SI 0 "=l")) | |
2162 | (clobber (reg:SI 0))] | |
2163 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2164 | "bla __divss" |
2165 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2166 | |
2167 | (define_insn "divus_call" | |
8ffd9c51 RK |
2168 | [(set (reg:SI 3) |
2169 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2170 | (set (reg:SI 4) | |
2171 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2172 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2173 | (clobber (reg:SI 0)) |
2174 | (clobber (match_scratch:CC 1 "=x")) | |
2175 | (clobber (reg:CC 69))] | |
2176 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2177 | "bla __divus" |
2178 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2179 | |
2180 | (define_insn "quoss_call" | |
2181 | [(set (reg:SI 3) | |
2182 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2183 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2184 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2185 | "bla __quoss" |
2186 | [(set_attr "type" "idiv")]) | |
0081a354 | 2187 | |
fada905b MM |
2188 | (define_insn "quous_call" |
2189 | [(set (reg:SI 3) | |
2190 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2191 | (clobber (match_scratch:SI 0 "=l")) | |
2192 | (clobber (reg:SI 0)) | |
2193 | (clobber (match_scratch:CC 1 "=x")) | |
2194 | (clobber (reg:CC 69))] | |
2195 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2196 | "bla __quous" |
2197 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2198 | \f |
bb21487f | 2199 | ;; Logical instructions |
dfbdccdb GK |
2200 | ;; The logical instructions are mostly combined by using match_operator, |
2201 | ;; but the plain AND insns are somewhat different because there is no | |
2202 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2203 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2204 | ||
29ae5b89 JL |
2205 | (define_insn "andsi3" |
2206 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2207 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2208 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2209 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2210 | "" |
2211 | "@ | |
2212 | and %0,%1,%2 | |
ca7f5001 RK |
2213 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2214 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2215 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2216 | |
2217 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2218 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2219 | ;; machines causes an execution serialization |
1fd4e8c1 | 2220 | |
7cd5235b | 2221 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2222 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2223 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2224 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2225 | (const_int 0))) |
52d3af72 DE |
2226 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2227 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2228 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2229 | "@ |
2230 | and. %3,%1,%2 | |
ca7f5001 RK |
2231 | {andil.|andi.} %3,%1,%b2 |
2232 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2233 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2234 | # | |
2235 | # | |
2236 | # | |
2237 | #" | |
2238 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2239 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2240 | |
0ba1b2ff AM |
2241 | (define_insn "*andsi3_internal3" |
2242 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2243 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2244 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2245 | (const_int 0))) | |
2246 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2247 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
2248 | "TARGET_POWERPC64" | |
2249 | "@ | |
2250 | # | |
2251 | {andil.|andi.} %3,%1,%b2 | |
2252 | {andiu.|andis.} %3,%1,%u2 | |
2253 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2254 | # | |
2255 | # | |
2256 | # | |
2257 | #" | |
2258 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2259 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2260 | ||
52d3af72 DE |
2261 | (define_split |
2262 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2263 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2264 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2265 | (const_int 0))) |
52d3af72 DE |
2266 | (clobber (match_scratch:SI 3 "")) |
2267 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2268 | "reload_completed" |
52d3af72 DE |
2269 | [(parallel [(set (match_dup 3) |
2270 | (and:SI (match_dup 1) | |
2271 | (match_dup 2))) | |
2272 | (clobber (match_dup 4))]) | |
2273 | (set (match_dup 0) | |
2274 | (compare:CC (match_dup 3) | |
2275 | (const_int 0)))] | |
2276 | "") | |
2277 | ||
0ba1b2ff AM |
2278 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2279 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2280 | ||
2281 | (define_split | |
2282 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2283 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2284 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2285 | (const_int 0))) | |
2286 | (clobber (match_scratch:SI 3 "")) | |
2287 | (clobber (match_scratch:CC 4 ""))] | |
2288 | "TARGET_POWERPC64 && reload_completed" | |
2289 | [(parallel [(set (match_dup 3) | |
2290 | (and:SI (match_dup 1) | |
2291 | (match_dup 2))) | |
2292 | (clobber (match_dup 4))]) | |
2293 | (set (match_dup 0) | |
2294 | (compare:CC (match_dup 3) | |
2295 | (const_int 0)))] | |
2296 | "") | |
2297 | ||
2298 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2299 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2300 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2301 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2302 | (const_int 0))) |
2303 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2304 | (and:SI (match_dup 1) | |
2305 | (match_dup 2))) | |
2306 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2307 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2308 | "@ |
2309 | and. %0,%1,%2 | |
ca7f5001 RK |
2310 | {andil.|andi.} %0,%1,%b2 |
2311 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2312 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2313 | # | |
2314 | # | |
2315 | # | |
2316 | #" | |
2317 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2318 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2319 | ||
0ba1b2ff AM |
2320 | (define_insn "*andsi3_internal5" |
2321 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2322 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2323 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2324 | (const_int 0))) | |
2325 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2326 | (and:SI (match_dup 1) | |
2327 | (match_dup 2))) | |
2328 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
2329 | "TARGET_POWERPC64" | |
2330 | "@ | |
2331 | # | |
2332 | {andil.|andi.} %0,%1,%b2 | |
2333 | {andiu.|andis.} %0,%1,%u2 | |
2334 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
2335 | # | |
2336 | # | |
2337 | # | |
2338 | #" | |
2339 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2340 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2341 | ||
52d3af72 DE |
2342 | (define_split |
2343 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2344 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2345 | (match_operand:SI 2 "and_operand" "")) | |
2346 | (const_int 0))) | |
2347 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2348 | (and:SI (match_dup 1) | |
2349 | (match_dup 2))) | |
2350 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2351 | "reload_completed" |
52d3af72 DE |
2352 | [(parallel [(set (match_dup 0) |
2353 | (and:SI (match_dup 1) | |
2354 | (match_dup 2))) | |
2355 | (clobber (match_dup 4))]) | |
2356 | (set (match_dup 3) | |
2357 | (compare:CC (match_dup 0) | |
2358 | (const_int 0)))] | |
2359 | "") | |
1fd4e8c1 | 2360 | |
0ba1b2ff AM |
2361 | (define_split |
2362 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
2363 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2364 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2365 | (const_int 0))) | |
2366 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2367 | (and:SI (match_dup 1) | |
2368 | (match_dup 2))) | |
2369 | (clobber (match_scratch:CC 4 ""))] | |
2370 | "TARGET_POWERPC64 && reload_completed" | |
2371 | [(parallel [(set (match_dup 0) | |
2372 | (and:SI (match_dup 1) | |
2373 | (match_dup 2))) | |
2374 | (clobber (match_dup 4))]) | |
2375 | (set (match_dup 3) | |
2376 | (compare:CC (match_dup 0) | |
2377 | (const_int 0)))] | |
2378 | "") | |
2379 | ||
2380 | ;; Handle the PowerPC64 rlwinm corner case | |
2381 | ||
2382 | (define_insn_and_split "*andsi3_internal6" | |
2383 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2384 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2385 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
2386 | "TARGET_POWERPC64" | |
2387 | "#" | |
2388 | "TARGET_POWERPC64" | |
2389 | [(set (match_dup 0) | |
2390 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
2391 | (match_dup 4))) | |
2392 | (set (match_dup 0) | |
2393 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
2394 | " | |
2395 | { | |
2396 | int mb = extract_MB (operands[2]); | |
2397 | int me = extract_ME (operands[2]); | |
2398 | operands[3] = GEN_INT (me + 1); | |
2399 | operands[5] = GEN_INT (32 - (me + 1)); | |
2400 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2401 | }" | |
2402 | [(set_attr "length" "8")]) | |
2403 | ||
2404 | (define_insn_and_split "*andsi3_internal7" | |
2405 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") | |
2406 | (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r") | |
2407 | (match_operand:SI 1 "mask_operand_wrap" "i,i")) | |
2408 | (const_int 0))) | |
2409 | (clobber (match_scratch:SI 3 "=r,r"))] | |
2410 | "TARGET_POWERPC64" | |
2411 | "#" | |
2412 | "TARGET_POWERPC64" | |
2413 | [(parallel [(set (match_dup 2) | |
2414 | (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4)) | |
2415 | (match_dup 5)) | |
2416 | (const_int 0))) | |
2417 | (clobber (match_dup 3))])] | |
2418 | " | |
2419 | { | |
2420 | int mb = extract_MB (operands[1]); | |
2421 | int me = extract_ME (operands[1]); | |
2422 | operands[4] = GEN_INT (me + 1); | |
2423 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2424 | }" | |
2425 | [(set_attr "type" "delayed_compare,compare") | |
2426 | (set_attr "length" "4,8")]) | |
2427 | ||
2428 | (define_insn_and_split "*andsi3_internal8" | |
2429 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") | |
2430 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2431 | (match_operand:SI 2 "mask_operand_wrap" "i,i")) | |
2432 | (const_int 0))) | |
2433 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
2434 | (and:SI (match_dup 1) | |
2435 | (match_dup 2)))] | |
2436 | "TARGET_POWERPC64" | |
2437 | "#" | |
2438 | "TARGET_POWERPC64" | |
2439 | [(parallel [(set (match_dup 3) | |
2440 | (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
2441 | (match_dup 5)) | |
2442 | (const_int 0))) | |
2443 | (set (match_dup 0) | |
2444 | (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
2445 | (match_dup 5)))]) | |
2446 | (set (match_dup 0) | |
2447 | (rotate:SI (match_dup 0) (match_dup 6)))] | |
2448 | " | |
2449 | { | |
2450 | int mb = extract_MB (operands[2]); | |
2451 | int me = extract_ME (operands[2]); | |
2452 | operands[4] = GEN_INT (me + 1); | |
2453 | operands[6] = GEN_INT (32 - (me + 1)); | |
2454 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2455 | }" | |
2456 | [(set_attr "type" "delayed_compare,compare") | |
2457 | (set_attr "length" "8,12")]) | |
2458 | ||
7cd5235b | 2459 | (define_expand "iorsi3" |
cd2b37d9 | 2460 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2461 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2462 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2463 | "" |
f357808b RK |
2464 | " |
2465 | { | |
7cd5235b | 2466 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2467 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2468 | { |
2469 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2470 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2471 | ? operands[0] : gen_reg_rtx (SImode)); |
2472 | ||
a260abc9 DE |
2473 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2474 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2475 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2476 | DONE; |
2477 | } | |
f357808b RK |
2478 | }") |
2479 | ||
7cd5235b | 2480 | (define_expand "xorsi3" |
cd2b37d9 | 2481 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2482 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2483 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2484 | "" |
7cd5235b | 2485 | " |
1fd4e8c1 | 2486 | { |
7cd5235b | 2487 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2488 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2489 | { |
2490 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2491 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2492 | ? operands[0] : gen_reg_rtx (SImode)); |
2493 | ||
a260abc9 DE |
2494 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2495 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2496 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2497 | DONE; |
2498 | } | |
1fd4e8c1 RK |
2499 | }") |
2500 | ||
dfbdccdb | 2501 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2502 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2503 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2504 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2505 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2506 | "" |
2507 | "@ | |
dfbdccdb GK |
2508 | %q3 %0,%1,%2 |
2509 | {%q3il|%q3i} %0,%1,%b2 | |
2510 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2511 | |
dfbdccdb | 2512 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2513 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2514 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2515 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2516 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2517 | (const_int 0))) | |
52d3af72 | 2518 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2519 | "! TARGET_POWERPC64" |
52d3af72 | 2520 | "@ |
dfbdccdb | 2521 | %q4. %3,%1,%2 |
52d3af72 DE |
2522 | #" |
2523 | [(set_attr "type" "compare") | |
2524 | (set_attr "length" "4,8")]) | |
2525 | ||
2526 | (define_split | |
2527 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2528 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2529 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2530 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2531 | (const_int 0))) |
52d3af72 | 2532 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2533 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2534 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2535 | (set (match_dup 0) |
2536 | (compare:CC (match_dup 3) | |
2537 | (const_int 0)))] | |
2538 | "") | |
815cdc52 | 2539 | |
dfbdccdb | 2540 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2541 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2542 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2543 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2544 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2545 | (const_int 0))) | |
52d3af72 | 2546 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2547 | (match_dup 4))] |
0ad91047 | 2548 | "! TARGET_POWERPC64" |
52d3af72 | 2549 | "@ |
dfbdccdb | 2550 | %q4. %0,%1,%2 |
52d3af72 DE |
2551 | #" |
2552 | [(set_attr "type" "compare") | |
2553 | (set_attr "length" "4,8")]) | |
2554 | ||
2555 | (define_split | |
e72247f4 | 2556 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2557 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2558 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2559 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2560 | (const_int 0))) |
75540af0 | 2561 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2562 | (match_dup 4))] |
0ad91047 | 2563 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2564 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2565 | (set (match_dup 3) |
2566 | (compare:CC (match_dup 0) | |
2567 | (const_int 0)))] | |
2568 | "") | |
1fd4e8c1 | 2569 | |
5bdc5878 | 2570 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 2571 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
2572 | |
2573 | (define_split | |
2574 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2575 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2576 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2577 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2578 | "" |
dfbdccdb GK |
2579 | [(set (match_dup 0) (match_dup 4)) |
2580 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2581 | " |
2582 | { | |
dfbdccdb GK |
2583 | rtx i; |
2584 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2585 | operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2586 | operands[1], i); | |
2587 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2588 | operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2589 | operands[0], i); | |
a260abc9 DE |
2590 | }") |
2591 | ||
dfbdccdb | 2592 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2593 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2594 | (match_operator:SI 3 "boolean_operator" |
2595 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2596 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2597 | "" |
dfbdccdb | 2598 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2599 | |
dfbdccdb | 2600 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2601 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2602 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2603 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2604 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2605 | (const_int 0))) | |
52d3af72 | 2606 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2607 | "! TARGET_POWERPC64" |
52d3af72 | 2608 | "@ |
dfbdccdb | 2609 | %q4. %3,%2,%1 |
52d3af72 DE |
2610 | #" |
2611 | [(set_attr "type" "compare") | |
2612 | (set_attr "length" "4,8")]) | |
2613 | ||
2614 | (define_split | |
2615 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2616 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2617 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2618 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2619 | (const_int 0))) |
52d3af72 | 2620 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2621 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2622 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2623 | (set (match_dup 0) |
2624 | (compare:CC (match_dup 3) | |
2625 | (const_int 0)))] | |
2626 | "") | |
1fd4e8c1 | 2627 | |
dfbdccdb | 2628 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2629 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2630 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2631 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2632 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2633 | (const_int 0))) | |
52d3af72 | 2634 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2635 | (match_dup 4))] |
0ad91047 | 2636 | "! TARGET_POWERPC64" |
52d3af72 | 2637 | "@ |
dfbdccdb | 2638 | %q4. %0,%2,%1 |
52d3af72 DE |
2639 | #" |
2640 | [(set_attr "type" "compare") | |
2641 | (set_attr "length" "4,8")]) | |
2642 | ||
2643 | (define_split | |
e72247f4 | 2644 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2645 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2646 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2647 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2648 | (const_int 0))) |
75540af0 | 2649 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2650 | (match_dup 4))] |
0ad91047 | 2651 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2652 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2653 | (set (match_dup 3) |
2654 | (compare:CC (match_dup 0) | |
2655 | (const_int 0)))] | |
2656 | "") | |
2657 | ||
dfbdccdb | 2658 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2659 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2660 | (match_operator:SI 3 "boolean_operator" |
2661 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2662 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2663 | "" |
dfbdccdb | 2664 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2665 | |
dfbdccdb | 2666 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2667 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2668 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2669 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2670 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2671 | (const_int 0))) | |
52d3af72 | 2672 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2673 | "! TARGET_POWERPC64" |
52d3af72 | 2674 | "@ |
dfbdccdb | 2675 | %q4. %3,%1,%2 |
52d3af72 DE |
2676 | #" |
2677 | [(set_attr "type" "compare") | |
2678 | (set_attr "length" "4,8")]) | |
2679 | ||
2680 | (define_split | |
2681 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2682 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2683 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2684 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2685 | (const_int 0))) |
52d3af72 | 2686 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2687 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2688 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2689 | (set (match_dup 0) |
2690 | (compare:CC (match_dup 3) | |
2691 | (const_int 0)))] | |
2692 | "") | |
1fd4e8c1 | 2693 | |
dfbdccdb | 2694 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2695 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2696 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2697 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2698 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2699 | (const_int 0))) | |
52d3af72 | 2700 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2701 | (match_dup 4))] |
0ad91047 | 2702 | "! TARGET_POWERPC64" |
52d3af72 | 2703 | "@ |
dfbdccdb | 2704 | %q4. %0,%1,%2 |
52d3af72 DE |
2705 | #" |
2706 | [(set_attr "type" "compare") | |
2707 | (set_attr "length" "4,8")]) | |
2708 | ||
2709 | (define_split | |
e72247f4 | 2710 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2711 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2712 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2713 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2714 | (const_int 0))) |
75540af0 | 2715 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2716 | (match_dup 4))] |
0ad91047 | 2717 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2718 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2719 | (set (match_dup 3) |
2720 | (compare:CC (match_dup 0) | |
2721 | (const_int 0)))] | |
2722 | "") | |
1fd4e8c1 RK |
2723 | |
2724 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2725 | ;; orders. Don't define forms that only set CR fields because these | |
2726 | ;; would modify an input register. | |
2727 | ||
7cd5235b | 2728 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2729 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2730 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2731 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2732 | (and:SI (match_dup 2) | |
cd2b37d9 | 2733 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2734 | "TARGET_POWER" |
01def764 | 2735 | "maskir %0,%3,%2") |
1fd4e8c1 | 2736 | |
7cd5235b | 2737 | (define_insn "*maskir_internal2" |
242e8072 | 2738 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2739 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2740 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2741 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2742 | (match_dup 2))))] |
ca7f5001 | 2743 | "TARGET_POWER" |
01def764 | 2744 | "maskir %0,%3,%2") |
1fd4e8c1 | 2745 | |
7cd5235b | 2746 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2747 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2748 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2749 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2750 | (and:SI (not:SI (match_dup 2)) |
2751 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2752 | "TARGET_POWER" |
01def764 | 2753 | "maskir %0,%3,%2") |
1fd4e8c1 | 2754 | |
7cd5235b | 2755 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2756 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2757 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2758 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2759 | (and:SI (not:SI (match_dup 2)) | |
2760 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2761 | "TARGET_POWER" |
01def764 | 2762 | "maskir %0,%3,%2") |
1fd4e8c1 | 2763 | |
7cd5235b | 2764 | (define_insn "*maskir_internal5" |
9ebbca7d | 2765 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2766 | (compare:CC |
9ebbca7d GK |
2767 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2768 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2769 | (and:SI (match_dup 2) |
9ebbca7d | 2770 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2771 | (const_int 0))) |
9ebbca7d | 2772 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2773 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2774 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2775 | "TARGET_POWER" |
9ebbca7d GK |
2776 | "@ |
2777 | maskir. %0,%3,%2 | |
2778 | #" | |
2779 | [(set_attr "type" "compare") | |
2780 | (set_attr "length" "4,8")]) | |
2781 | ||
2782 | (define_split | |
2783 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2784 | (compare:CC | |
2785 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2786 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2787 | (and:SI (match_dup 2) | |
2788 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2789 | (const_int 0))) | |
2790 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2791 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2792 | (and:SI (match_dup 2) (match_dup 3))))] | |
2793 | "TARGET_POWER && reload_completed" | |
2794 | [(set (match_dup 0) | |
2795 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2796 | (and:SI (match_dup 2) (match_dup 3)))) | |
2797 | (set (match_dup 4) | |
2798 | (compare:CC (match_dup 0) | |
2799 | (const_int 0)))] | |
2800 | "") | |
1fd4e8c1 | 2801 | |
7cd5235b | 2802 | (define_insn "*maskir_internal6" |
9ebbca7d | 2803 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2804 | (compare:CC |
9ebbca7d GK |
2805 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2806 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2807 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2808 | (match_dup 2))) |
1fd4e8c1 | 2809 | (const_int 0))) |
9ebbca7d | 2810 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2811 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2812 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2813 | "TARGET_POWER" |
9ebbca7d GK |
2814 | "@ |
2815 | maskir. %0,%3,%2 | |
2816 | #" | |
2817 | [(set_attr "type" "compare") | |
2818 | (set_attr "length" "4,8")]) | |
2819 | ||
2820 | (define_split | |
2821 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2822 | (compare:CC | |
2823 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2824 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2825 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2826 | (match_dup 2))) | |
2827 | (const_int 0))) | |
2828 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2829 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2830 | (and:SI (match_dup 3) (match_dup 2))))] | |
2831 | "TARGET_POWER && reload_completed" | |
2832 | [(set (match_dup 0) | |
2833 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2834 | (and:SI (match_dup 3) (match_dup 2)))) | |
2835 | (set (match_dup 4) | |
2836 | (compare:CC (match_dup 0) | |
2837 | (const_int 0)))] | |
2838 | "") | |
1fd4e8c1 | 2839 | |
7cd5235b | 2840 | (define_insn "*maskir_internal7" |
9ebbca7d | 2841 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 2842 | (compare:CC |
9ebbca7d GK |
2843 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
2844 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2845 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2846 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 2847 | (const_int 0))) |
9ebbca7d | 2848 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
2849 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2850 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2851 | "TARGET_POWER" | |
9ebbca7d GK |
2852 | "@ |
2853 | maskir. %0,%3,%2 | |
2854 | #" | |
2855 | [(set_attr "type" "compare") | |
2856 | (set_attr "length" "4,8")]) | |
2857 | ||
2858 | (define_split | |
2859 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2860 | (compare:CC | |
2861 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
2862 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
2863 | (and:SI (not:SI (match_dup 2)) | |
2864 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2865 | (const_int 0))) | |
2866 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2867 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2868 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2869 | "TARGET_POWER && reload_completed" | |
2870 | [(set (match_dup 0) | |
2871 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2872 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2873 | (set (match_dup 4) | |
2874 | (compare:CC (match_dup 0) | |
2875 | (const_int 0)))] | |
2876 | "") | |
1fd4e8c1 | 2877 | |
7cd5235b | 2878 | (define_insn "*maskir_internal8" |
9ebbca7d | 2879 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2880 | (compare:CC |
9ebbca7d GK |
2881 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
2882 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 2883 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2884 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 2885 | (const_int 0))) |
9ebbca7d | 2886 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2887 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2888 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2889 | "TARGET_POWER" |
9ebbca7d GK |
2890 | "@ |
2891 | maskir. %0,%3,%2 | |
2892 | #" | |
2893 | [(set_attr "type" "compare") | |
2894 | (set_attr "length" "4,8")]) | |
fcce224d | 2895 | |
9ebbca7d GK |
2896 | (define_split |
2897 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2898 | (compare:CC | |
2899 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2900 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2901 | (and:SI (not:SI (match_dup 2)) | |
2902 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2903 | (const_int 0))) | |
2904 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2905 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2906 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2907 | "TARGET_POWER && reload_completed" | |
2908 | [(set (match_dup 0) | |
2909 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2910 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2911 | (set (match_dup 4) | |
2912 | (compare:CC (match_dup 0) | |
2913 | (const_int 0)))] | |
2914 | "") | |
fcce224d | 2915 | \f |
1fd4e8c1 RK |
2916 | ;; Rotate and shift insns, in all their variants. These support shifts, |
2917 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2918 | (define_expand "insv" |
0ad91047 DE |
2919 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2920 | (match_operand:SI 1 "const_int_operand" "") | |
2921 | (match_operand:SI 2 "const_int_operand" "")) | |
2922 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2923 | "" |
2924 | " | |
2925 | { | |
2926 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2927 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2928 | compiler if the address of the structure is taken later. */ | |
2929 | if (GET_CODE (operands[0]) == SUBREG | |
2930 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2931 | FAIL; | |
a78e33fc DE |
2932 | |
2933 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2934 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2935 | else | |
2936 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2937 | DONE; | |
034c1be0 MM |
2938 | }") |
2939 | ||
a78e33fc | 2940 | (define_insn "insvsi" |
cd2b37d9 | 2941 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2942 | (match_operand:SI 1 "const_int_operand" "i") |
2943 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2944 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2945 | "" |
2946 | "* | |
2947 | { | |
2948 | int start = INTVAL (operands[2]) & 31; | |
2949 | int size = INTVAL (operands[1]) & 31; | |
2950 | ||
89e9f3a8 MM |
2951 | operands[4] = GEN_INT (32 - start - size); |
2952 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2953 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2954 | }" |
2955 | [(set_attr "type" "insert_word")]) | |
1fd4e8c1 | 2956 | |
a78e33fc | 2957 | (define_insn "*insvsi_internal1" |
d56d506a RK |
2958 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2959 | (match_operand:SI 1 "const_int_operand" "i") | |
2960 | (match_operand:SI 2 "const_int_operand" "i")) | |
2961 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2962 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2963 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2964 | "* |
2965 | { | |
2966 | int shift = INTVAL (operands[4]) & 31; | |
2967 | int start = INTVAL (operands[2]) & 31; | |
2968 | int size = INTVAL (operands[1]) & 31; | |
2969 | ||
89e9f3a8 MM |
2970 | operands[4] = GEN_INT (shift - start - size); |
2971 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2972 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2973 | }" |
2974 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2975 | |
a78e33fc | 2976 | (define_insn "*insvsi_internal2" |
d56d506a RK |
2977 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2978 | (match_operand:SI 1 "const_int_operand" "i") | |
2979 | (match_operand:SI 2 "const_int_operand" "i")) | |
2980 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2981 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2982 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2983 | "* |
2984 | { | |
2985 | int shift = INTVAL (operands[4]) & 31; | |
2986 | int start = INTVAL (operands[2]) & 31; | |
2987 | int size = INTVAL (operands[1]) & 31; | |
2988 | ||
89e9f3a8 MM |
2989 | operands[4] = GEN_INT (32 - shift - start - size); |
2990 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2991 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2992 | }" |
2993 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2994 | |
a78e33fc | 2995 | (define_insn "*insvsi_internal3" |
d56d506a RK |
2996 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2997 | (match_operand:SI 1 "const_int_operand" "i") | |
2998 | (match_operand:SI 2 "const_int_operand" "i")) | |
2999 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3000 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3001 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3002 | "* |
3003 | { | |
3004 | int shift = INTVAL (operands[4]) & 31; | |
3005 | int start = INTVAL (operands[2]) & 31; | |
3006 | int size = INTVAL (operands[1]) & 31; | |
3007 | ||
89e9f3a8 MM |
3008 | operands[4] = GEN_INT (32 - shift - start - size); |
3009 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3010 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3011 | }" |
3012 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3013 | |
a78e33fc | 3014 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3015 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3016 | (match_operand:SI 1 "const_int_operand" "i") | |
3017 | (match_operand:SI 2 "const_int_operand" "i")) | |
3018 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3019 | (match_operand:SI 4 "const_int_operand" "i") | |
3020 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3021 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3022 | "* | |
3023 | { | |
3024 | int extract_start = INTVAL (operands[5]) & 31; | |
3025 | int extract_size = INTVAL (operands[4]) & 31; | |
3026 | int insert_start = INTVAL (operands[2]) & 31; | |
3027 | int insert_size = INTVAL (operands[1]) & 31; | |
3028 | ||
3029 | /* Align extract field with insert field */ | |
3a598fbe | 3030 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3031 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3032 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
8e8238f1 DE |
3033 | }" |
3034 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3035 | |
a78e33fc | 3036 | (define_insn "insvdi" |
685f3906 | 3037 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3038 | (match_operand:SI 1 "const_int_operand" "i") |
3039 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3040 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3041 | "TARGET_POWERPC64" | |
3042 | "* | |
3043 | { | |
3044 | int start = INTVAL (operands[2]) & 63; | |
3045 | int size = INTVAL (operands[1]) & 63; | |
3046 | ||
a78e33fc DE |
3047 | operands[1] = GEN_INT (64 - start - size); |
3048 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3049 | }") |
3050 | ||
034c1be0 | 3051 | (define_expand "extzv" |
0ad91047 DE |
3052 | [(set (match_operand 0 "gpc_reg_operand" "") |
3053 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3054 | (match_operand:SI 2 "const_int_operand" "") | |
3055 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3056 | "" |
3057 | " | |
3058 | { | |
3059 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3060 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3061 | compiler if the address of the structure is taken later. */ | |
3062 | if (GET_CODE (operands[0]) == SUBREG | |
3063 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3064 | FAIL; | |
a78e33fc DE |
3065 | |
3066 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3067 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3068 | else | |
3069 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3070 | DONE; | |
034c1be0 MM |
3071 | }") |
3072 | ||
a78e33fc | 3073 | (define_insn "extzvsi" |
cd2b37d9 RK |
3074 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3075 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3076 | (match_operand:SI 2 "const_int_operand" "i") |
3077 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3078 | "" | |
3079 | "* | |
3080 | { | |
3081 | int start = INTVAL (operands[3]) & 31; | |
3082 | int size = INTVAL (operands[2]) & 31; | |
3083 | ||
3084 | if (start + size >= 32) | |
3085 | operands[3] = const0_rtx; | |
3086 | else | |
89e9f3a8 | 3087 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3088 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3089 | }") |
3090 | ||
a78e33fc | 3091 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3092 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3093 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3094 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3095 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3096 | (const_int 0))) |
9ebbca7d | 3097 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3098 | "" |
1fd4e8c1 RK |
3099 | "* |
3100 | { | |
3101 | int start = INTVAL (operands[3]) & 31; | |
3102 | int size = INTVAL (operands[2]) & 31; | |
3103 | ||
9ebbca7d GK |
3104 | /* Force split for non-cc0 compare. */ |
3105 | if (which_alternative == 1) | |
3106 | return \"#\"; | |
3107 | ||
43a88a8c | 3108 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3109 | word, it is possible to use andiu. or andil. to test it. This is |
3110 | useful because the condition register set-use delay is smaller for | |
3111 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3112 | position is 0 because the LT and GT bits may be set wrong. */ | |
3113 | ||
3114 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3115 | { |
3a598fbe | 3116 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3117 | - (1 << (16 - (start & 15) - size)))); |
3118 | if (start < 16) | |
ca7f5001 | 3119 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3120 | else |
ca7f5001 | 3121 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3122 | } |
7e69e155 | 3123 | |
1fd4e8c1 RK |
3124 | if (start + size >= 32) |
3125 | operands[3] = const0_rtx; | |
3126 | else | |
89e9f3a8 | 3127 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3128 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3129 | }" |
9ebbca7d GK |
3130 | [(set_attr "type" "compare") |
3131 | (set_attr "length" "4,8")]) | |
3132 | ||
3133 | (define_split | |
3134 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3135 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3136 | (match_operand:SI 2 "const_int_operand" "") | |
3137 | (match_operand:SI 3 "const_int_operand" "")) | |
3138 | (const_int 0))) | |
3139 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3140 | "reload_completed" |
9ebbca7d GK |
3141 | [(set (match_dup 4) |
3142 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3143 | (match_dup 3))) | |
3144 | (set (match_dup 0) | |
3145 | (compare:CC (match_dup 4) | |
3146 | (const_int 0)))] | |
3147 | "") | |
1fd4e8c1 | 3148 | |
a78e33fc | 3149 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3150 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3151 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3152 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3153 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3154 | (const_int 0))) |
9ebbca7d | 3155 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3156 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3157 | "" |
1fd4e8c1 RK |
3158 | "* |
3159 | { | |
3160 | int start = INTVAL (operands[3]) & 31; | |
3161 | int size = INTVAL (operands[2]) & 31; | |
3162 | ||
9ebbca7d GK |
3163 | /* Force split for non-cc0 compare. */ |
3164 | if (which_alternative == 1) | |
3165 | return \"#\"; | |
3166 | ||
bc401279 | 3167 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3168 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3169 | if (start >= 16 && start + size == 32) |
df031c43 | 3170 | { |
bc401279 AM |
3171 | operands[3] = GEN_INT ((1 << size) - 1); |
3172 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3173 | } |
7e69e155 | 3174 | |
1fd4e8c1 RK |
3175 | if (start + size >= 32) |
3176 | operands[3] = const0_rtx; | |
3177 | else | |
89e9f3a8 | 3178 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3179 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3180 | }" |
ce71f754 | 3181 | [(set_attr "type" "compare") |
9ebbca7d GK |
3182 | (set_attr "length" "4,8")]) |
3183 | ||
3184 | (define_split | |
3185 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3186 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3187 | (match_operand:SI 2 "const_int_operand" "") | |
3188 | (match_operand:SI 3 "const_int_operand" "")) | |
3189 | (const_int 0))) | |
3190 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3191 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3192 | "reload_completed" |
9ebbca7d GK |
3193 | [(set (match_dup 0) |
3194 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3195 | (set (match_dup 4) | |
3196 | (compare:CC (match_dup 0) | |
3197 | (const_int 0)))] | |
3198 | "") | |
1fd4e8c1 | 3199 | |
a78e33fc | 3200 | (define_insn "extzvdi" |
685f3906 DE |
3201 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3202 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3203 | (match_operand:SI 2 "const_int_operand" "i") |
3204 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3205 | "TARGET_POWERPC64" |
3206 | "* | |
3207 | { | |
3208 | int start = INTVAL (operands[3]) & 63; | |
3209 | int size = INTVAL (operands[2]) & 63; | |
3210 | ||
3211 | if (start + size >= 64) | |
3212 | operands[3] = const0_rtx; | |
3213 | else | |
89e9f3a8 MM |
3214 | operands[3] = GEN_INT (start + size); |
3215 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3216 | return \"rldicl %0,%1,%3,%2\"; |
3217 | }") | |
3218 | ||
a78e33fc | 3219 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3220 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3221 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3222 | (match_operand:SI 2 "const_int_operand" "i") |
3223 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3224 | (const_int 0))) |
29ae5b89 | 3225 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
3226 | "TARGET_POWERPC64" |
3227 | "* | |
3228 | { | |
3229 | int start = INTVAL (operands[3]) & 63; | |
3230 | int size = INTVAL (operands[2]) & 63; | |
3231 | ||
3232 | if (start + size >= 64) | |
3233 | operands[3] = const0_rtx; | |
3234 | else | |
89e9f3a8 MM |
3235 | operands[3] = GEN_INT (start + size); |
3236 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3237 | return \"rldicl. %4,%1,%3,%2\"; |
3238 | }") | |
3239 | ||
a78e33fc | 3240 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3241 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3242 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3243 | (match_operand:SI 2 "const_int_operand" "i") |
3244 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3245 | (const_int 0))) |
29ae5b89 | 3246 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
3247 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
3248 | "TARGET_POWERPC64" | |
3249 | "* | |
3250 | { | |
3251 | int start = INTVAL (operands[3]) & 63; | |
3252 | int size = INTVAL (operands[2]) & 63; | |
3253 | ||
3254 | if (start + size >= 64) | |
3255 | operands[3] = const0_rtx; | |
3256 | else | |
89e9f3a8 MM |
3257 | operands[3] = GEN_INT (start + size); |
3258 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3259 | return \"rldicl. %0,%1,%3,%2\"; |
3260 | }") | |
3261 | ||
1fd4e8c1 | 3262 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3263 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3264 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3265 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3266 | "" | |
ca7f5001 | 3267 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3268 | |
a260abc9 | 3269 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3270 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3271 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3272 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3273 | (const_int 0))) |
9ebbca7d | 3274 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 3275 | "" |
9ebbca7d GK |
3276 | "@ |
3277 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3278 | #" | |
3279 | [(set_attr "type" "delayed_compare") | |
3280 | (set_attr "length" "4,8")]) | |
3281 | ||
3282 | (define_split | |
3283 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3284 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3285 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3286 | (const_int 0))) | |
3287 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 3288 | "reload_completed" |
9ebbca7d GK |
3289 | [(set (match_dup 3) |
3290 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3291 | (set (match_dup 0) | |
3292 | (compare:CC (match_dup 3) | |
3293 | (const_int 0)))] | |
3294 | "") | |
1fd4e8c1 | 3295 | |
a260abc9 | 3296 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3297 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3298 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3299 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3300 | (const_int 0))) |
9ebbca7d | 3301 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3302 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 3303 | "" |
9ebbca7d GK |
3304 | "@ |
3305 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3306 | #" | |
3307 | [(set_attr "type" "delayed_compare") | |
3308 | (set_attr "length" "4,8")]) | |
3309 | ||
3310 | (define_split | |
3311 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3312 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3313 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3314 | (const_int 0))) | |
3315 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3316 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 3317 | "reload_completed" |
9ebbca7d GK |
3318 | [(set (match_dup 0) |
3319 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3320 | (set (match_dup 3) | |
3321 | (compare:CC (match_dup 0) | |
3322 | (const_int 0)))] | |
3323 | "") | |
1fd4e8c1 | 3324 | |
a260abc9 | 3325 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3326 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3327 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3328 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 3329 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3330 | "" |
ca7f5001 | 3331 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3332 | |
a260abc9 | 3333 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3334 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3335 | (compare:CC (and:SI |
9ebbca7d GK |
3336 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3337 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3338 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3339 | (const_int 0))) |
9ebbca7d | 3340 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3341 | "" |
9ebbca7d GK |
3342 | "@ |
3343 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3344 | #" | |
3345 | [(set_attr "type" "delayed_compare") | |
3346 | (set_attr "length" "4,8")]) | |
3347 | ||
3348 | (define_split | |
3349 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3350 | (compare:CC (and:SI | |
3351 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3352 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3353 | (match_operand:SI 3 "mask_operand" "")) | |
3354 | (const_int 0))) | |
3355 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3356 | "reload_completed" |
9ebbca7d GK |
3357 | [(set (match_dup 4) |
3358 | (and:SI (rotate:SI (match_dup 1) | |
3359 | (match_dup 2)) | |
3360 | (match_dup 3))) | |
3361 | (set (match_dup 0) | |
3362 | (compare:CC (match_dup 4) | |
3363 | (const_int 0)))] | |
3364 | "") | |
1fd4e8c1 | 3365 | |
a260abc9 | 3366 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3367 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3368 | (compare:CC (and:SI |
9ebbca7d GK |
3369 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3370 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3371 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3372 | (const_int 0))) |
9ebbca7d | 3373 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3374 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3375 | "" |
9ebbca7d GK |
3376 | "@ |
3377 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3378 | #" | |
3379 | [(set_attr "type" "delayed_compare") | |
3380 | (set_attr "length" "4,8")]) | |
3381 | ||
3382 | (define_split | |
3383 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3384 | (compare:CC (and:SI | |
3385 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3386 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3387 | (match_operand:SI 3 "mask_operand" "")) | |
3388 | (const_int 0))) | |
3389 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3390 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3391 | "reload_completed" |
9ebbca7d GK |
3392 | [(set (match_dup 0) |
3393 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3394 | (set (match_dup 4) | |
3395 | (compare:CC (match_dup 0) | |
3396 | (const_int 0)))] | |
3397 | "") | |
1fd4e8c1 | 3398 | |
a260abc9 | 3399 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3400 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3401 | (zero_extend:SI |
3402 | (subreg:QI | |
cd2b37d9 | 3403 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3404 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3405 | "" | |
ca7f5001 | 3406 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3407 | |
a260abc9 | 3408 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3409 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3410 | (compare:CC (zero_extend:SI |
3411 | (subreg:QI | |
9ebbca7d GK |
3412 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3413 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3414 | (const_int 0))) |
9ebbca7d | 3415 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3416 | "" |
9ebbca7d GK |
3417 | "@ |
3418 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3419 | #" | |
3420 | [(set_attr "type" "delayed_compare") | |
3421 | (set_attr "length" "4,8")]) | |
3422 | ||
3423 | (define_split | |
3424 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3425 | (compare:CC (zero_extend:SI | |
3426 | (subreg:QI | |
3427 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3428 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3429 | (const_int 0))) | |
3430 | (clobber (match_scratch:SI 3 ""))] | |
3431 | "reload_completed" | |
3432 | [(set (match_dup 3) | |
3433 | (zero_extend:SI (subreg:QI | |
3434 | (rotate:SI (match_dup 1) | |
3435 | (match_dup 2)) 0))) | |
3436 | (set (match_dup 0) | |
3437 | (compare:CC (match_dup 3) | |
3438 | (const_int 0)))] | |
3439 | "") | |
1fd4e8c1 | 3440 | |
a260abc9 | 3441 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3442 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3443 | (compare:CC (zero_extend:SI |
3444 | (subreg:QI | |
9ebbca7d GK |
3445 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3446 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3447 | (const_int 0))) |
9ebbca7d | 3448 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3449 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3450 | "" | |
9ebbca7d GK |
3451 | "@ |
3452 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3453 | #" | |
3454 | [(set_attr "type" "delayed_compare") | |
3455 | (set_attr "length" "4,8")]) | |
3456 | ||
3457 | (define_split | |
3458 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3459 | (compare:CC (zero_extend:SI | |
3460 | (subreg:QI | |
3461 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3462 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3463 | (const_int 0))) | |
3464 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3465 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3466 | "reload_completed" | |
3467 | [(set (match_dup 0) | |
3468 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3469 | (set (match_dup 3) | |
3470 | (compare:CC (match_dup 0) | |
3471 | (const_int 0)))] | |
3472 | "") | |
1fd4e8c1 | 3473 | |
a260abc9 | 3474 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3475 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3476 | (zero_extend:SI |
3477 | (subreg:HI | |
cd2b37d9 | 3478 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3479 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3480 | "" | |
ca7f5001 | 3481 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3482 | |
a260abc9 | 3483 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3484 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3485 | (compare:CC (zero_extend:SI |
3486 | (subreg:HI | |
9ebbca7d GK |
3487 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3488 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3489 | (const_int 0))) |
9ebbca7d | 3490 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3491 | "" |
9ebbca7d GK |
3492 | "@ |
3493 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3494 | #" | |
3495 | [(set_attr "type" "delayed_compare") | |
3496 | (set_attr "length" "4,8")]) | |
3497 | ||
3498 | (define_split | |
3499 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3500 | (compare:CC (zero_extend:SI | |
3501 | (subreg:HI | |
3502 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3503 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3504 | (const_int 0))) | |
3505 | (clobber (match_scratch:SI 3 ""))] | |
3506 | "reload_completed" | |
3507 | [(set (match_dup 3) | |
3508 | (zero_extend:SI (subreg:HI | |
3509 | (rotate:SI (match_dup 1) | |
3510 | (match_dup 2)) 0))) | |
3511 | (set (match_dup 0) | |
3512 | (compare:CC (match_dup 3) | |
3513 | (const_int 0)))] | |
3514 | "") | |
1fd4e8c1 | 3515 | |
a260abc9 | 3516 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3517 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3518 | (compare:CC (zero_extend:SI |
3519 | (subreg:HI | |
9ebbca7d GK |
3520 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3521 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3522 | (const_int 0))) |
9ebbca7d | 3523 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3524 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3525 | "" | |
9ebbca7d GK |
3526 | "@ |
3527 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3528 | #" | |
3529 | [(set_attr "type" "delayed_compare") | |
3530 | (set_attr "length" "4,8")]) | |
3531 | ||
3532 | (define_split | |
3533 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3534 | (compare:CC (zero_extend:SI | |
3535 | (subreg:HI | |
3536 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3537 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3538 | (const_int 0))) | |
3539 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3540 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3541 | "reload_completed" | |
3542 | [(set (match_dup 0) | |
3543 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3544 | (set (match_dup 3) | |
3545 | (compare:CC (match_dup 0) | |
3546 | (const_int 0)))] | |
3547 | "") | |
1fd4e8c1 RK |
3548 | |
3549 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3550 | ;; SHIFT_COUNT_TRUNCATED. | |
3551 | ||
ca7f5001 RK |
3552 | (define_expand "ashlsi3" |
3553 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3554 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3555 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3556 | "" | |
3557 | " | |
3558 | { | |
3559 | if (TARGET_POWER) | |
3560 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3561 | else | |
25c341fa | 3562 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3563 | DONE; |
3564 | }") | |
3565 | ||
3566 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3567 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3568 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3569 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3570 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3571 | "TARGET_POWER" |
1fd4e8c1 RK |
3572 | "@ |
3573 | sle %0,%1,%2 | |
9ebbca7d | 3574 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3575 | |
25c341fa | 3576 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3577 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3578 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3579 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3580 | "! TARGET_POWER" |
9ebbca7d | 3581 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3582 | |
3583 | (define_insn "" | |
9ebbca7d GK |
3584 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3585 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3586 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3587 | (const_int 0))) |
9ebbca7d GK |
3588 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3589 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3590 | "TARGET_POWER" |
1fd4e8c1 RK |
3591 | "@ |
3592 | sle. %3,%1,%2 | |
9ebbca7d GK |
3593 | {sli.|slwi.} %3,%1,%h2 |
3594 | # | |
3595 | #" | |
3596 | [(set_attr "type" "delayed_compare") | |
3597 | (set_attr "length" "4,4,8,8")]) | |
3598 | ||
3599 | (define_split | |
3600 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3601 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3602 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3603 | (const_int 0))) | |
3604 | (clobber (match_scratch:SI 3 "")) | |
3605 | (clobber (match_scratch:SI 4 ""))] | |
3606 | "TARGET_POWER && reload_completed" | |
3607 | [(parallel [(set (match_dup 3) | |
3608 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3609 | (clobber (match_dup 4))]) | |
3610 | (set (match_dup 0) | |
3611 | (compare:CC (match_dup 3) | |
3612 | (const_int 0)))] | |
3613 | "") | |
25c341fa | 3614 | |
ca7f5001 | 3615 | (define_insn "" |
9ebbca7d GK |
3616 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3617 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3618 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3619 | (const_int 0))) |
9ebbca7d | 3620 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3621 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3622 | "@ |
3623 | {sl|slw}%I2. %3,%1,%h2 | |
3624 | #" | |
3625 | [(set_attr "type" "delayed_compare") | |
3626 | (set_attr "length" "4,8")]) | |
3627 | ||
3628 | (define_split | |
3629 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3630 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3631 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3632 | (const_int 0))) | |
3633 | (clobber (match_scratch:SI 3 ""))] | |
3634 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3635 | [(set (match_dup 3) | |
3636 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3637 | (set (match_dup 0) | |
3638 | (compare:CC (match_dup 3) | |
3639 | (const_int 0)))] | |
3640 | "") | |
1fd4e8c1 RK |
3641 | |
3642 | (define_insn "" | |
9ebbca7d GK |
3643 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3644 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3645 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3646 | (const_int 0))) |
9ebbca7d | 3647 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3648 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3649 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3650 | "TARGET_POWER" |
1fd4e8c1 RK |
3651 | "@ |
3652 | sle. %0,%1,%2 | |
9ebbca7d GK |
3653 | {sli.|slwi.} %0,%1,%h2 |
3654 | # | |
3655 | #" | |
3656 | [(set_attr "type" "delayed_compare") | |
3657 | (set_attr "length" "4,4,8,8")]) | |
3658 | ||
3659 | (define_split | |
3660 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3661 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3662 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3663 | (const_int 0))) | |
3664 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3665 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3666 | (clobber (match_scratch:SI 4 ""))] | |
3667 | "TARGET_POWER && reload_completed" | |
3668 | [(parallel [(set (match_dup 0) | |
3669 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3670 | (clobber (match_dup 4))]) | |
3671 | (set (match_dup 3) | |
3672 | (compare:CC (match_dup 0) | |
3673 | (const_int 0)))] | |
3674 | "") | |
25c341fa | 3675 | |
ca7f5001 | 3676 | (define_insn "" |
9ebbca7d GK |
3677 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3678 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3679 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3680 | (const_int 0))) |
9ebbca7d | 3681 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3682 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3683 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3684 | "@ |
3685 | {sl|slw}%I2. %0,%1,%h2 | |
3686 | #" | |
3687 | [(set_attr "type" "delayed_compare") | |
3688 | (set_attr "length" "4,8")]) | |
3689 | ||
3690 | (define_split | |
3691 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3692 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3693 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3694 | (const_int 0))) | |
3695 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3696 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
3697 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3698 | [(set (match_dup 0) | |
3699 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3700 | (set (match_dup 3) | |
3701 | (compare:CC (match_dup 0) | |
3702 | (const_int 0)))] | |
3703 | "") | |
1fd4e8c1 RK |
3704 | |
3705 | (define_insn "" | |
cd2b37d9 RK |
3706 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3707 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3708 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3709 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3710 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3711 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3712 | |
3713 | (define_insn "" | |
9ebbca7d | 3714 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3715 | (compare:CC |
9ebbca7d GK |
3716 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3717 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3718 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3719 | (const_int 0))) |
9ebbca7d | 3720 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3721 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3722 | "@ |
3723 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3724 | #" | |
3725 | [(set_attr "type" "delayed_compare") | |
3726 | (set_attr "length" "4,8")]) | |
3727 | ||
3728 | (define_split | |
3729 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3730 | (compare:CC | |
3731 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3732 | (match_operand:SI 2 "const_int_operand" "")) | |
3733 | (match_operand:SI 3 "mask_operand" "")) | |
3734 | (const_int 0))) | |
3735 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3736 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3737 | [(set (match_dup 4) |
3738 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3739 | (match_dup 3))) | |
3740 | (set (match_dup 0) | |
3741 | (compare:CC (match_dup 4) | |
3742 | (const_int 0)))] | |
3743 | "") | |
1fd4e8c1 RK |
3744 | |
3745 | (define_insn "" | |
9ebbca7d | 3746 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3747 | (compare:CC |
9ebbca7d GK |
3748 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3749 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3750 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3751 | (const_int 0))) |
9ebbca7d | 3752 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3753 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3754 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3755 | "@ |
3756 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3757 | #" | |
3758 | [(set_attr "type" "delayed_compare") | |
3759 | (set_attr "length" "4,8")]) | |
3760 | ||
3761 | (define_split | |
3762 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3763 | (compare:CC | |
3764 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3765 | (match_operand:SI 2 "const_int_operand" "")) | |
3766 | (match_operand:SI 3 "mask_operand" "")) | |
3767 | (const_int 0))) | |
3768 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3769 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3770 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3771 | [(set (match_dup 0) |
3772 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3773 | (set (match_dup 4) | |
3774 | (compare:CC (match_dup 0) | |
3775 | (const_int 0)))] | |
3776 | "") | |
1fd4e8c1 | 3777 | |
ca7f5001 | 3778 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3779 | ;; "sli x,x,0". |
ca7f5001 RK |
3780 | (define_expand "lshrsi3" |
3781 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3782 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3783 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3784 | "" | |
3785 | " | |
3786 | { | |
3787 | if (TARGET_POWER) | |
3788 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3789 | else | |
25c341fa | 3790 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3791 | DONE; |
3792 | }") | |
3793 | ||
3794 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3795 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3796 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3797 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3798 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3799 | "TARGET_POWER" |
1fd4e8c1 RK |
3800 | "@ |
3801 | sre %0,%1,%2 | |
bdf423cb | 3802 | mr %0,%1 |
ca7f5001 RK |
3803 | {s%A2i|s%A2wi} %0,%1,%h2") |
3804 | ||
25c341fa | 3805 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3806 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3807 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3808 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3809 | "! TARGET_POWER" |
bdf423cb MM |
3810 | "@ |
3811 | mr %0,%1 | |
3812 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3813 | |
3814 | (define_insn "" | |
9ebbca7d GK |
3815 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3816 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3817 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3818 | (const_int 0))) |
9ebbca7d GK |
3819 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3820 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3821 | "TARGET_POWER" |
1fd4e8c1 | 3822 | "@ |
29ae5b89 JL |
3823 | sre. %3,%1,%2 |
3824 | mr. %1,%1 | |
9ebbca7d GK |
3825 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
3826 | # | |
3827 | # | |
3828 | #" | |
3829 | [(set_attr "type" "delayed_compare") | |
3830 | (set_attr "length" "4,4,4,8,8,8")]) | |
3831 | ||
3832 | (define_split | |
3833 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3834 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3835 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3836 | (const_int 0))) | |
3837 | (clobber (match_scratch:SI 3 "")) | |
3838 | (clobber (match_scratch:SI 4 ""))] | |
3839 | "TARGET_POWER && reload_completed" | |
3840 | [(parallel [(set (match_dup 3) | |
3841 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3842 | (clobber (match_dup 4))]) | |
3843 | (set (match_dup 0) | |
3844 | (compare:CC (match_dup 3) | |
3845 | (const_int 0)))] | |
3846 | "") | |
ca7f5001 RK |
3847 | |
3848 | (define_insn "" | |
9ebbca7d GK |
3849 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3850 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3851 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 3852 | (const_int 0))) |
9ebbca7d | 3853 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
0ad91047 | 3854 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
3855 | "@ |
3856 | mr. %1,%1 | |
9ebbca7d GK |
3857 | {sr|srw}%I2. %3,%1,%h2 |
3858 | # | |
3859 | #" | |
3860 | [(set_attr "type" "delayed_compare") | |
3861 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 3862 | |
9ebbca7d GK |
3863 | (define_split |
3864 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3865 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3866 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3867 | (const_int 0))) | |
3868 | (clobber (match_scratch:SI 3 ""))] | |
3869 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3870 | [(set (match_dup 3) | |
3871 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3872 | (set (match_dup 0) | |
3873 | (compare:CC (match_dup 3) | |
3874 | (const_int 0)))] | |
3875 | "") | |
3876 | ||
3877 | (define_insn "" | |
3878 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
3879 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3880 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3881 | (const_int 0))) |
9ebbca7d | 3882 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 3883 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3884 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 3885 | "TARGET_POWER" |
1fd4e8c1 | 3886 | "@ |
29ae5b89 JL |
3887 | sre. %0,%1,%2 |
3888 | mr. %0,%1 | |
9ebbca7d GK |
3889 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
3890 | # | |
3891 | # | |
3892 | #" | |
3893 | [(set_attr "type" "delayed_compare") | |
3894 | (set_attr "length" "4,4,4,8,8,8")]) | |
3895 | ||
3896 | (define_split | |
3897 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3898 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3899 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3900 | (const_int 0))) | |
3901 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3902 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3903 | (clobber (match_scratch:SI 4 ""))] | |
3904 | "TARGET_POWER && reload_completed" | |
3905 | [(parallel [(set (match_dup 0) | |
3906 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3907 | (clobber (match_dup 4))]) | |
3908 | (set (match_dup 3) | |
3909 | (compare:CC (match_dup 0) | |
3910 | (const_int 0)))] | |
3911 | "") | |
ca7f5001 RK |
3912 | |
3913 | (define_insn "" | |
9ebbca7d GK |
3914 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3915 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3916 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 3917 | (const_int 0))) |
9ebbca7d | 3918 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 3919 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3920 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
3921 | "@ |
3922 | mr. %0,%1 | |
9ebbca7d GK |
3923 | {sr|srw}%I2. %0,%1,%h2 |
3924 | # | |
3925 | #" | |
3926 | [(set_attr "type" "delayed_compare") | |
3927 | (set_attr "length" "4,4,8,8")]) | |
3928 | ||
3929 | (define_split | |
3930 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3931 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3932 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3933 | (const_int 0))) | |
3934 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3935 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
3936 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3937 | [(set (match_dup 0) | |
3938 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3939 | (set (match_dup 3) | |
3940 | (compare:CC (match_dup 0) | |
3941 | (const_int 0)))] | |
3942 | "") | |
1fd4e8c1 RK |
3943 | |
3944 | (define_insn "" | |
cd2b37d9 RK |
3945 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3946 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3947 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3948 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3949 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 3950 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
3951 | |
3952 | (define_insn "" | |
9ebbca7d | 3953 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3954 | (compare:CC |
9ebbca7d GK |
3955 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3956 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3957 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3958 | (const_int 0))) |
9ebbca7d | 3959 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3960 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3961 | "@ |
3962 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
3963 | #" | |
3964 | [(set_attr "type" "delayed_compare") | |
3965 | (set_attr "length" "4,8")]) | |
3966 | ||
3967 | (define_split | |
3968 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3969 | (compare:CC | |
3970 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3971 | (match_operand:SI 2 "const_int_operand" "")) | |
3972 | (match_operand:SI 3 "mask_operand" "")) | |
3973 | (const_int 0))) | |
3974 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3975 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3976 | [(set (match_dup 4) |
3977 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
3978 | (match_dup 3))) | |
3979 | (set (match_dup 0) | |
3980 | (compare:CC (match_dup 4) | |
3981 | (const_int 0)))] | |
3982 | "") | |
1fd4e8c1 RK |
3983 | |
3984 | (define_insn "" | |
9ebbca7d | 3985 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3986 | (compare:CC |
9ebbca7d GK |
3987 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3988 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3989 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3990 | (const_int 0))) |
9ebbca7d | 3991 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3992 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3993 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3994 | "@ |
3995 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
3996 | #" | |
3997 | [(set_attr "type" "delayed_compare") | |
3998 | (set_attr "length" "4,8")]) | |
3999 | ||
4000 | (define_split | |
4001 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4002 | (compare:CC | |
4003 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4004 | (match_operand:SI 2 "const_int_operand" "")) | |
4005 | (match_operand:SI 3 "mask_operand" "")) | |
4006 | (const_int 0))) | |
4007 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4008 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4009 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4010 | [(set (match_dup 0) |
4011 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4012 | (set (match_dup 4) | |
4013 | (compare:CC (match_dup 0) | |
4014 | (const_int 0)))] | |
4015 | "") | |
1fd4e8c1 RK |
4016 | |
4017 | (define_insn "" | |
cd2b37d9 | 4018 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4019 | (zero_extend:SI |
4020 | (subreg:QI | |
cd2b37d9 | 4021 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4022 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4023 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4024 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4025 | |
4026 | (define_insn "" | |
9ebbca7d | 4027 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4028 | (compare:CC |
4029 | (zero_extend:SI | |
4030 | (subreg:QI | |
9ebbca7d GK |
4031 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4032 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4033 | (const_int 0))) |
9ebbca7d | 4034 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4035 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4036 | "@ |
4037 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4038 | #" | |
4039 | [(set_attr "type" "delayed_compare") | |
4040 | (set_attr "length" "4,8")]) | |
4041 | ||
4042 | (define_split | |
4043 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4044 | (compare:CC | |
4045 | (zero_extend:SI | |
4046 | (subreg:QI | |
4047 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4048 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4049 | (const_int 0))) | |
4050 | (clobber (match_scratch:SI 3 ""))] | |
4051 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4052 | [(set (match_dup 3) | |
4053 | (zero_extend:SI (subreg:QI | |
4054 | (lshiftrt:SI (match_dup 1) | |
4055 | (match_dup 2)) 0))) | |
4056 | (set (match_dup 0) | |
4057 | (compare:CC (match_dup 3) | |
4058 | (const_int 0)))] | |
4059 | "") | |
1fd4e8c1 RK |
4060 | |
4061 | (define_insn "" | |
9ebbca7d | 4062 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4063 | (compare:CC |
4064 | (zero_extend:SI | |
4065 | (subreg:QI | |
9ebbca7d GK |
4066 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4067 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4068 | (const_int 0))) |
9ebbca7d | 4069 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4070 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4071 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4072 | "@ |
4073 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4074 | #" | |
4075 | [(set_attr "type" "delayed_compare") | |
4076 | (set_attr "length" "4,8")]) | |
4077 | ||
4078 | (define_split | |
4079 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4080 | (compare:CC | |
4081 | (zero_extend:SI | |
4082 | (subreg:QI | |
4083 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4084 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4085 | (const_int 0))) | |
4086 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4087 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4088 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4089 | [(set (match_dup 0) | |
4090 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4091 | (set (match_dup 3) | |
4092 | (compare:CC (match_dup 0) | |
4093 | (const_int 0)))] | |
4094 | "") | |
1fd4e8c1 RK |
4095 | |
4096 | (define_insn "" | |
cd2b37d9 | 4097 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4098 | (zero_extend:SI |
4099 | (subreg:HI | |
cd2b37d9 | 4100 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4101 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4102 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4103 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4104 | |
4105 | (define_insn "" | |
9ebbca7d | 4106 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4107 | (compare:CC |
4108 | (zero_extend:SI | |
4109 | (subreg:HI | |
9ebbca7d GK |
4110 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4111 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4112 | (const_int 0))) |
9ebbca7d | 4113 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4114 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4115 | "@ |
4116 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4117 | #" | |
4118 | [(set_attr "type" "delayed_compare") | |
4119 | (set_attr "length" "4,8")]) | |
4120 | ||
4121 | (define_split | |
4122 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4123 | (compare:CC | |
4124 | (zero_extend:SI | |
4125 | (subreg:HI | |
4126 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4127 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4128 | (const_int 0))) | |
4129 | (clobber (match_scratch:SI 3 ""))] | |
4130 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4131 | [(set (match_dup 3) | |
4132 | (zero_extend:SI (subreg:HI | |
4133 | (lshiftrt:SI (match_dup 1) | |
4134 | (match_dup 2)) 0))) | |
4135 | (set (match_dup 0) | |
4136 | (compare:CC (match_dup 3) | |
4137 | (const_int 0)))] | |
4138 | "") | |
1fd4e8c1 RK |
4139 | |
4140 | (define_insn "" | |
9ebbca7d | 4141 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4142 | (compare:CC |
4143 | (zero_extend:SI | |
4144 | (subreg:HI | |
9ebbca7d GK |
4145 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4146 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4147 | (const_int 0))) |
9ebbca7d | 4148 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4149 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4150 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4151 | "@ |
4152 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4153 | #" | |
4154 | [(set_attr "type" "delayed_compare") | |
4155 | (set_attr "length" "4,8")]) | |
4156 | ||
4157 | (define_split | |
4158 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4159 | (compare:CC | |
4160 | (zero_extend:SI | |
4161 | (subreg:HI | |
4162 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4163 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4164 | (const_int 0))) | |
4165 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4166 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4167 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4168 | [(set (match_dup 0) | |
4169 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4170 | (set (match_dup 3) | |
4171 | (compare:CC (match_dup 0) | |
4172 | (const_int 0)))] | |
4173 | "") | |
1fd4e8c1 RK |
4174 | |
4175 | (define_insn "" | |
cd2b37d9 | 4176 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4177 | (const_int 1) |
cd2b37d9 RK |
4178 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4179 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4180 | (const_int 31)))] |
ca7f5001 | 4181 | "TARGET_POWER" |
1fd4e8c1 RK |
4182 | "rrib %0,%1,%2") |
4183 | ||
4184 | (define_insn "" | |
cd2b37d9 | 4185 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4186 | (const_int 1) |
cd2b37d9 RK |
4187 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4188 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4189 | (const_int 31)))] |
ca7f5001 | 4190 | "TARGET_POWER" |
1fd4e8c1 RK |
4191 | "rrib %0,%1,%2") |
4192 | ||
4193 | (define_insn "" | |
cd2b37d9 | 4194 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4195 | (const_int 1) |
cd2b37d9 RK |
4196 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4197 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4198 | (const_int 1) |
4199 | (const_int 0)))] | |
ca7f5001 | 4200 | "TARGET_POWER" |
1fd4e8c1 RK |
4201 | "rrib %0,%1,%2") |
4202 | ||
ca7f5001 RK |
4203 | (define_expand "ashrsi3" |
4204 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4205 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4206 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4207 | "" | |
4208 | " | |
4209 | { | |
4210 | if (TARGET_POWER) | |
4211 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4212 | else | |
25c341fa | 4213 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4214 | DONE; |
4215 | }") | |
4216 | ||
4217 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4218 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4219 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4220 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4221 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4222 | "TARGET_POWER" |
1fd4e8c1 RK |
4223 | "@ |
4224 | srea %0,%1,%2 | |
ca7f5001 RK |
4225 | {srai|srawi} %0,%1,%h2") |
4226 | ||
25c341fa | 4227 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4228 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4229 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4230 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4231 | "! TARGET_POWER" |
d904e9ed | 4232 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4233 | |
4234 | (define_insn "" | |
9ebbca7d GK |
4235 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4236 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4237 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4238 | (const_int 0))) |
9ebbca7d GK |
4239 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4240 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4241 | "TARGET_POWER" |
1fd4e8c1 RK |
4242 | "@ |
4243 | srea. %3,%1,%2 | |
9ebbca7d GK |
4244 | {srai.|srawi.} %3,%1,%h2 |
4245 | # | |
4246 | #" | |
4247 | [(set_attr "type" "delayed_compare") | |
4248 | (set_attr "length" "4,4,8,8")]) | |
4249 | ||
4250 | (define_split | |
4251 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4252 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4253 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4254 | (const_int 0))) | |
4255 | (clobber (match_scratch:SI 3 "")) | |
4256 | (clobber (match_scratch:SI 4 ""))] | |
4257 | "TARGET_POWER && reload_completed" | |
4258 | [(parallel [(set (match_dup 3) | |
4259 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4260 | (clobber (match_dup 4))]) | |
4261 | (set (match_dup 0) | |
4262 | (compare:CC (match_dup 3) | |
4263 | (const_int 0)))] | |
4264 | "") | |
ca7f5001 RK |
4265 | |
4266 | (define_insn "" | |
9ebbca7d GK |
4267 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4268 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4269 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4270 | (const_int 0))) |
9ebbca7d | 4271 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4272 | "! TARGET_POWER" |
9ebbca7d GK |
4273 | "@ |
4274 | {sra|sraw}%I2. %3,%1,%h2 | |
4275 | #" | |
4276 | [(set_attr "type" "delayed_compare") | |
4277 | (set_attr "length" "4,8")]) | |
4278 | ||
4279 | (define_split | |
4280 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4281 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4282 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4283 | (const_int 0))) | |
4284 | (clobber (match_scratch:SI 3 ""))] | |
4285 | "! TARGET_POWER && reload_completed" | |
4286 | [(set (match_dup 3) | |
4287 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4288 | (set (match_dup 0) | |
4289 | (compare:CC (match_dup 3) | |
4290 | (const_int 0)))] | |
4291 | "") | |
1fd4e8c1 RK |
4292 | |
4293 | (define_insn "" | |
9ebbca7d GK |
4294 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4295 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4296 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4297 | (const_int 0))) |
9ebbca7d | 4298 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4299 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4300 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4301 | "TARGET_POWER" |
1fd4e8c1 RK |
4302 | "@ |
4303 | srea. %0,%1,%2 | |
9ebbca7d GK |
4304 | {srai.|srawi.} %0,%1,%h2 |
4305 | # | |
4306 | #" | |
4307 | [(set_attr "type" "delayed_compare") | |
4308 | (set_attr "length" "4,4,8,8")]) | |
4309 | ||
4310 | (define_split | |
4311 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4312 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4313 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4314 | (const_int 0))) | |
4315 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4316 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4317 | (clobber (match_scratch:SI 4 ""))] | |
4318 | "TARGET_POWER && reload_completed" | |
4319 | [(parallel [(set (match_dup 0) | |
4320 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4321 | (clobber (match_dup 4))]) | |
4322 | (set (match_dup 3) | |
4323 | (compare:CC (match_dup 0) | |
4324 | (const_int 0)))] | |
4325 | "") | |
1fd4e8c1 | 4326 | |
ca7f5001 | 4327 | (define_insn "" |
9ebbca7d GK |
4328 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4329 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4330 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4331 | (const_int 0))) |
9ebbca7d | 4332 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4333 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4334 | "! TARGET_POWER" |
9ebbca7d GK |
4335 | "@ |
4336 | {sra|sraw}%I2. %0,%1,%h2 | |
4337 | #" | |
4338 | [(set_attr "type" "delayed_compare") | |
4339 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4340 | \f |
9ebbca7d GK |
4341 | (define_split |
4342 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4343 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4344 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4345 | (const_int 0))) | |
4346 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4347 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4348 | "! TARGET_POWER && reload_completed" | |
4349 | [(set (match_dup 0) | |
4350 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4351 | (set (match_dup 3) | |
4352 | (compare:CC (match_dup 0) | |
4353 | (const_int 0)))] | |
4354 | "") | |
4355 | ||
1fd4e8c1 RK |
4356 | ;; Floating-point insns, excluding normal data motion. |
4357 | ;; | |
ca7f5001 RK |
4358 | ;; PowerPC has a full set of single-precision floating point instructions. |
4359 | ;; | |
4360 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4361 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4362 | ;; The only conversions we will do will be when storing to memory. In that | |
4363 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4364 | ;; |
4365 | ;; Note that when we store into a single-precision memory location, we need to | |
4366 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4367 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4368 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4369 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4370 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4371 | ||
e8112008 | 4372 | (define_insn "extendsfdf2" |
cd2b37d9 | 4373 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 4374 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 4375 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
e8112008 | 4376 | "* |
5c30aff8 | 4377 | { |
e8112008 RK |
4378 | if (REGNO (operands[0]) == REGNO (operands[1])) |
4379 | return \"\"; | |
4380 | else | |
4381 | return \"fmr %0,%1\"; | |
4382 | }" | |
4383 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4384 | |
4385 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
4386 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4387 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4388 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 4389 | "frsp %0,%1" |
1fd4e8c1 RK |
4390 | [(set_attr "type" "fp")]) |
4391 | ||
455350f4 RK |
4392 | (define_insn "aux_truncdfsf2" |
4393 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
615158e2 | 4394 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] |
a3170dc6 | 4395 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
4396 | "frsp %0,%1" |
4397 | [(set_attr "type" "fp")]) | |
4398 | ||
a3170dc6 AH |
4399 | (define_expand "negsf2" |
4400 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4401 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4402 | "TARGET_HARD_FLOAT" | |
4403 | "") | |
4404 | ||
4405 | (define_insn "*negsf2" | |
cd2b37d9 RK |
4406 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4407 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4408 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4409 | "fneg %0,%1" |
4410 | [(set_attr "type" "fp")]) | |
4411 | ||
a3170dc6 AH |
4412 | (define_expand "abssf2" |
4413 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4414 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4415 | "TARGET_HARD_FLOAT" | |
4416 | "") | |
4417 | ||
4418 | (define_insn "*abssf2" | |
cd2b37d9 RK |
4419 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4420 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4421 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4422 | "fabs %0,%1" |
4423 | [(set_attr "type" "fp")]) | |
4424 | ||
4425 | (define_insn "" | |
cd2b37d9 RK |
4426 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4427 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4428 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4429 | "fnabs %0,%1" |
4430 | [(set_attr "type" "fp")]) | |
4431 | ||
ca7f5001 RK |
4432 | (define_expand "addsf3" |
4433 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4434 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4435 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4436 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4437 | "") |
4438 | ||
4439 | (define_insn "" | |
cd2b37d9 RK |
4440 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4441 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4442 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4443 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4444 | "fadds %0,%1,%2" |
ca7f5001 RK |
4445 | [(set_attr "type" "fp")]) |
4446 | ||
4447 | (define_insn "" | |
4448 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4449 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4450 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4451 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4452 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4453 | [(set_attr "type" "fp")]) |
4454 | ||
4455 | (define_expand "subsf3" | |
4456 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4457 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4458 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4459 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4460 | "") |
4461 | ||
4462 | (define_insn "" | |
4463 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4464 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4465 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4466 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4467 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4468 | [(set_attr "type" "fp")]) |
4469 | ||
ca7f5001 | 4470 | (define_insn "" |
cd2b37d9 RK |
4471 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4472 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4473 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4474 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4475 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4476 | [(set_attr "type" "fp")]) |
4477 | ||
4478 | (define_expand "mulsf3" | |
4479 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4480 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4481 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4482 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4483 | "") |
4484 | ||
4485 | (define_insn "" | |
4486 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4487 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4488 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4489 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4490 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4491 | [(set_attr "type" "fp")]) |
4492 | ||
ca7f5001 | 4493 | (define_insn "" |
cd2b37d9 RK |
4494 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4495 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4496 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4497 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4498 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4499 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4500 | |
ca7f5001 RK |
4501 | (define_expand "divsf3" |
4502 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4503 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4504 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4505 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4506 | "") |
4507 | ||
4508 | (define_insn "" | |
cd2b37d9 RK |
4509 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4510 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4511 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4512 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4513 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4514 | [(set_attr "type" "sdiv")]) |
4515 | ||
4516 | (define_insn "" | |
4517 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4518 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4519 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4520 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4521 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4522 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4523 | |
4524 | (define_insn "" | |
cd2b37d9 RK |
4525 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4526 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4527 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4528 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4529 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4530 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4531 | [(set_attr "type" "fp")]) |
4532 | ||
4533 | (define_insn "" | |
4534 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4535 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4536 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4537 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4538 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4539 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4540 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4541 | |
4542 | (define_insn "" | |
cd2b37d9 RK |
4543 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4544 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4545 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4546 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4547 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4548 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4549 | [(set_attr "type" "fp")]) |
4550 | ||
4551 | (define_insn "" | |
4552 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4553 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4554 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4555 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4556 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4557 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4558 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4559 | |
4560 | (define_insn "" | |
cd2b37d9 RK |
4561 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4562 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4563 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4564 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4565 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4566 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4567 | "fnmadds %0,%1,%2,%3" | |
4568 | [(set_attr "type" "fp")]) | |
4569 | ||
4570 | (define_insn "" | |
4571 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4572 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4573 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4574 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4575 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4576 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4577 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4578 | [(set_attr "type" "fp")]) |
4579 | ||
4580 | (define_insn "" | |
4581 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4582 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4583 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4584 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4585 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4586 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4587 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4588 | |
16823694 GK |
4589 | (define_insn "" |
4590 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4591 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4592 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4593 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4594 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4595 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4596 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4597 | [(set_attr "type" "dmul")]) | |
4598 | ||
1fd4e8c1 | 4599 | (define_insn "" |
cd2b37d9 RK |
4600 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4601 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4602 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4603 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4604 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4605 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4606 | "fnmsubs %0,%1,%2,%3" | |
4607 | [(set_attr "type" "fp")]) | |
4608 | ||
4609 | (define_insn "" | |
4610 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4611 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4612 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4613 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4614 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4615 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4616 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4617 | [(set_attr "type" "fp")]) |
4618 | ||
4619 | (define_insn "" | |
4620 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4621 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4622 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4623 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4624 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4625 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4626 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4627 | |
16823694 GK |
4628 | (define_insn "" |
4629 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4630 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4631 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4632 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4633 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4634 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4635 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4636 | [(set_attr "type" "fp")]) | |
4637 | ||
ca7f5001 RK |
4638 | (define_expand "sqrtsf2" |
4639 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4640 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 4641 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4642 | "") |
4643 | ||
4644 | (define_insn "" | |
4645 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4646 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4647 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4648 | "fsqrts %0,%1" |
4649 | [(set_attr "type" "ssqrt")]) | |
4650 | ||
4651 | (define_insn "" | |
4652 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4653 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4654 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4655 | "fsqrt %0,%1" |
4656 | [(set_attr "type" "dsqrt")]) | |
4657 | ||
94d7001a RK |
4658 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4659 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4660 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4661 | ;; combine. |
4662 | (define_expand "maxsf3" | |
8e871c05 | 4663 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4664 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4665 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4666 | (match_dup 1) |
4667 | (match_dup 2)))] | |
a3170dc6 | 4668 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4669 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 4670 | |
8e871c05 | 4671 | (define_expand "minsf3" |
50a0b056 GK |
4672 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4673 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4674 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4675 | (match_dup 2) | |
4676 | (match_dup 1)))] | |
a3170dc6 | 4677 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4678 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4679 | |
8e871c05 RK |
4680 | (define_split |
4681 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4682 | (match_operator:SF 3 "min_max_operator" |
4683 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4684 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
a3170dc6 | 4685 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 GK |
4686 | [(const_int 0)] |
4687 | " | |
4688 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
4689 | operands[1], operands[2]); | |
4690 | DONE; | |
4691 | }") | |
2f607b94 | 4692 | |
a3170dc6 AH |
4693 | (define_expand "movsicc" |
4694 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4695 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
4696 | (match_operand:SI 2 "gpc_reg_operand" "") | |
4697 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
4698 | "TARGET_ISEL" | |
4699 | " | |
4700 | { | |
4701 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
4702 | DONE; | |
4703 | else | |
4704 | FAIL; | |
4705 | }") | |
4706 | ||
4707 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
4708 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
4709 | ;; because we may switch the operands and rB may end up being rA. | |
4710 | ;; | |
4711 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
4712 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
4713 | ;; change the mode underneath our feet and then gets confused trying | |
4714 | ;; to reload the value. | |
4715 | (define_insn "isel_signed" | |
4716 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4717 | (if_then_else:SI | |
4718 | (match_operator 1 "comparison_operator" | |
4719 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
4720 | (const_int 0)]) | |
4721 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4722 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4723 | "TARGET_ISEL" | |
4724 | "* | |
4725 | { return output_isel (operands); }" | |
4726 | [(set_attr "length" "4")]) | |
4727 | ||
4728 | (define_insn "isel_unsigned" | |
4729 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4730 | (if_then_else:SI | |
4731 | (match_operator 1 "comparison_operator" | |
4732 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
4733 | (const_int 0)]) | |
4734 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4735 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4736 | "TARGET_ISEL" | |
4737 | "* | |
4738 | { return output_isel (operands); }" | |
4739 | [(set_attr "length" "4")]) | |
4740 | ||
94d7001a | 4741 | (define_expand "movsfcc" |
0ad91047 | 4742 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4743 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4744 | (match_operand:SF 2 "gpc_reg_operand" "") |
4745 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4746 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4747 | " |
4748 | { | |
50a0b056 GK |
4749 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4750 | DONE; | |
94d7001a | 4751 | else |
50a0b056 | 4752 | FAIL; |
94d7001a | 4753 | }") |
d56d506a | 4754 | |
50a0b056 | 4755 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4756 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4757 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4758 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4759 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4760 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4761 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4762 | "fsel %0,%1,%2,%3" |
4763 | [(set_attr "type" "fp")]) | |
2f607b94 | 4764 | |
50a0b056 | 4765 | (define_insn "*fseldfsf4" |
94d7001a RK |
4766 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4767 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4768 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4769 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4770 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4771 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4772 | "fsel %0,%1,%2,%3" |
4773 | [(set_attr "type" "fp")]) | |
d56d506a | 4774 | |
1fd4e8c1 | 4775 | (define_insn "negdf2" |
cd2b37d9 RK |
4776 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4777 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4778 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4779 | "fneg %0,%1" |
4780 | [(set_attr "type" "fp")]) | |
4781 | ||
4782 | (define_insn "absdf2" | |
cd2b37d9 RK |
4783 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4784 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4785 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4786 | "fabs %0,%1" |
4787 | [(set_attr "type" "fp")]) | |
4788 | ||
4789 | (define_insn "" | |
cd2b37d9 RK |
4790 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4791 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4792 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4793 | "fnabs %0,%1" |
4794 | [(set_attr "type" "fp")]) | |
4795 | ||
4796 | (define_insn "adddf3" | |
cd2b37d9 RK |
4797 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4798 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4799 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4800 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4801 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4802 | [(set_attr "type" "fp")]) |
4803 | ||
4804 | (define_insn "subdf3" | |
cd2b37d9 RK |
4805 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4806 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4807 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4808 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4809 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4810 | [(set_attr "type" "fp")]) |
4811 | ||
4812 | (define_insn "muldf3" | |
cd2b37d9 RK |
4813 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4814 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4815 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4816 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4817 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4818 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4819 | |
4820 | (define_insn "divdf3" | |
cd2b37d9 RK |
4821 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4822 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4823 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4824 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4825 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4826 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4827 | |
4828 | (define_insn "" | |
cd2b37d9 RK |
4829 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4830 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4831 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4832 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4833 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4834 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4835 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4836 | |
4837 | (define_insn "" | |
cd2b37d9 RK |
4838 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4839 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4840 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4841 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4842 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4843 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4844 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4845 | |
4846 | (define_insn "" | |
cd2b37d9 RK |
4847 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4848 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4849 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4850 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4851 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4852 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4853 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4854 | [(set_attr "type" "dmul")]) | |
4855 | ||
4856 | (define_insn "" | |
4857 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4858 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
4859 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4860 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4861 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4862 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 4863 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 4864 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4865 | |
4866 | (define_insn "" | |
cd2b37d9 RK |
4867 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4868 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4869 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4870 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4871 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4872 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4873 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4874 | [(set_attr "type" "dmul")]) | |
4875 | ||
4876 | (define_insn "" | |
4877 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4878 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
4879 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4880 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
4881 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4882 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 4883 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 4884 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
4885 | |
4886 | (define_insn "sqrtdf2" | |
4887 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4888 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4889 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4890 | "fsqrt %0,%1" |
4891 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 4892 | |
50a0b056 GK |
4893 | ;; The conditional move instructions allow us to perform max and min |
4894 | ;; operations even when | |
b77dfefc | 4895 | |
8e871c05 | 4896 | (define_expand "maxdf3" |
8e871c05 | 4897 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4898 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
4899 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4900 | (match_dup 1) |
4901 | (match_dup 2)))] | |
a3170dc6 | 4902 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4903 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 4904 | |
8e871c05 | 4905 | (define_expand "mindf3" |
50a0b056 GK |
4906 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4907 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
4908 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
4909 | (match_dup 2) | |
4910 | (match_dup 1)))] | |
a3170dc6 | 4911 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4912 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 4913 | |
8e871c05 RK |
4914 | (define_split |
4915 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4916 | (match_operator:DF 3 "min_max_operator" |
4917 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
4918 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
a3170dc6 | 4919 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 GK |
4920 | [(const_int 0)] |
4921 | " | |
4922 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
4923 | operands[1], operands[2]); | |
4924 | DONE; | |
4925 | }") | |
b77dfefc | 4926 | |
94d7001a | 4927 | (define_expand "movdfcc" |
0ad91047 | 4928 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 4929 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4930 | (match_operand:DF 2 "gpc_reg_operand" "") |
4931 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4932 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4933 | " |
4934 | { | |
50a0b056 GK |
4935 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4936 | DONE; | |
94d7001a | 4937 | else |
50a0b056 | 4938 | FAIL; |
94d7001a | 4939 | }") |
d56d506a | 4940 | |
50a0b056 | 4941 | (define_insn "*fseldfdf4" |
8e871c05 RK |
4942 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4943 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4944 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4945 | (match_operand:DF 2 "gpc_reg_operand" "f") |
4946 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4947 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4948 | "fsel %0,%1,%2,%3" |
4949 | [(set_attr "type" "fp")]) | |
d56d506a | 4950 | |
50a0b056 | 4951 | (define_insn "*fselsfdf4" |
94d7001a RK |
4952 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4953 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4954 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4955 | (match_operand:DF 2 "gpc_reg_operand" "f") |
4956 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4957 | "TARGET_PPC_GFXOPT" | |
4958 | "fsel %0,%1,%2,%3" | |
4959 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4960 | \f |
4961 | ;; Conversions to and from floating-point. | |
802a0058 | 4962 | |
a3170dc6 AH |
4963 | (define_expand "fixunssfsi2" |
4964 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4965 | (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" ""))))] | |
4966 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
4967 | "") | |
4968 | ||
4969 | (define_expand "fix_truncsfsi2" | |
4970 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4971 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4972 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
4973 | "") | |
4974 | ||
9ebbca7d GK |
4975 | ; For each of these conversions, there is a define_expand, a define_insn |
4976 | ; with a '#' template, and a define_split (with C code). The idea is | |
4977 | ; to allow constant folding with the template of the define_insn, | |
4978 | ; then to have the insns split later (between sched1 and final). | |
4979 | ||
1fd4e8c1 | 4980 | (define_expand "floatsidf2" |
802a0058 MM |
4981 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4982 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
4983 | (use (match_dup 2)) | |
4984 | (use (match_dup 3)) | |
208c89ce | 4985 | (clobber (match_dup 4)) |
a7df97e6 | 4986 | (clobber (match_dup 5)) |
9ebbca7d | 4987 | (clobber (match_dup 6))])] |
a3170dc6 | 4988 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4989 | " |
4990 | { | |
05d49501 AM |
4991 | if (TARGET_POWERPC64) |
4992 | { | |
4993 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
4994 | rtx t1 = gen_reg_rtx (DImode); | |
4995 | rtx t2 = gen_reg_rtx (DImode); | |
4996 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
4997 | DONE; | |
4998 | } | |
4999 | ||
802a0058 | 5000 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5001 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5002 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5003 | operands[5] = gen_reg_rtx (DFmode); | |
5004 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5005 | }") |
5006 | ||
802a0058 MM |
5007 | (define_insn "*floatsidf2_internal" |
5008 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5009 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5010 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5011 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5012 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5013 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5014 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5015 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5016 | "#" |
a7df97e6 | 5017 | [(set_attr "length" "24")]) |
802a0058 MM |
5018 | |
5019 | (define_split | |
dbe3df29 | 5020 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5021 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5022 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5023 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5024 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5025 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5026 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
a3170dc6 | 5027 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5028 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5029 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5030 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5031 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5032 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5033 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5034 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5035 | " |
5036 | { | |
9ebbca7d GK |
5037 | rtx lowword, highword; |
5038 | if (GET_CODE (operands[4]) != MEM) | |
5039 | abort(); | |
5040 | highword = XEXP (operands[4], 0); | |
5041 | lowword = plus_constant (highword, 4); | |
5042 | if (! WORDS_BIG_ENDIAN) | |
5043 | { | |
5044 | rtx tmp; | |
5045 | tmp = highword; highword = lowword; lowword = tmp; | |
5046 | } | |
5047 | ||
5048 | emit_insn (gen_xorsi3 (operands[6], operands[1], | |
5049 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); | |
5050 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5051 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5052 | emit_move_insn (operands[5], operands[4]); | |
5053 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5054 | DONE; | |
208c89ce | 5055 | }") |
802a0058 | 5056 | |
a3170dc6 AH |
5057 | (define_expand "floatunssisf2" |
5058 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5059 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5060 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5061 | "") | |
5062 | ||
802a0058 MM |
5063 | (define_expand "floatunssidf2" |
5064 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5065 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5066 | (use (match_dup 2)) | |
5067 | (use (match_dup 3)) | |
a7df97e6 | 5068 | (clobber (match_dup 4)) |
9ebbca7d | 5069 | (clobber (match_dup 5))])] |
a3170dc6 | 5070 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5071 | " |
5072 | { | |
05d49501 AM |
5073 | if (TARGET_POWERPC64) |
5074 | { | |
5075 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5076 | rtx t1 = gen_reg_rtx (DImode); | |
5077 | rtx t2 = gen_reg_rtx (DImode); | |
5078 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5079 | t1, t2)); | |
5080 | DONE; | |
5081 | } | |
5082 | ||
802a0058 | 5083 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5084 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5085 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5086 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5087 | }") |
5088 | ||
802a0058 MM |
5089 | (define_insn "*floatunssidf2_internal" |
5090 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5091 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5092 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5093 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5094 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5095 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5096 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5097 | "#" |
a7df97e6 | 5098 | [(set_attr "length" "20")]) |
802a0058 MM |
5099 | |
5100 | (define_split | |
5101 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5102 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5103 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5104 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5105 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5106 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
a3170dc6 | 5107 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5108 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5109 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5110 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5111 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5112 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5113 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5114 | " | |
802a0058 | 5115 | { |
9ebbca7d GK |
5116 | rtx lowword, highword; |
5117 | if (GET_CODE (operands[4]) != MEM) | |
5118 | abort(); | |
5119 | highword = XEXP (operands[4], 0); | |
5120 | lowword = plus_constant (highword, 4); | |
5121 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5122 | { |
9ebbca7d GK |
5123 | rtx tmp; |
5124 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5125 | } |
802a0058 | 5126 | |
9ebbca7d GK |
5127 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5128 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5129 | emit_move_insn (operands[5], operands[4]); | |
5130 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5131 | DONE; | |
5132 | }") | |
1fd4e8c1 | 5133 | |
1fd4e8c1 | 5134 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5135 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5136 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5137 | (clobber (match_dup 2)) | |
9ebbca7d | 5138 | (clobber (match_dup 3))])] |
a3170dc6 | 5139 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5140 | " |
5141 | { | |
802a0058 | 5142 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5143 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5144 | }") |
5145 | ||
802a0058 MM |
5146 | (define_insn "*fix_truncdfsi2_internal" |
5147 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5148 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5149 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5150 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5151 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5152 | "#" |
9ebbca7d | 5153 | [(set_attr "length" "16")]) |
802a0058 MM |
5154 | |
5155 | (define_split | |
5156 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5157 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5158 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5159 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
a3170dc6 | 5160 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d | 5161 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5162 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5163 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5164 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5165 | " | |
802a0058 | 5166 | { |
9ebbca7d GK |
5167 | rtx lowword; |
5168 | if (GET_CODE (operands[3]) != MEM) | |
5169 | abort(); | |
5170 | lowword = XEXP (operands[3], 0); | |
5171 | if (WORDS_BIG_ENDIAN) | |
5172 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5173 | |
9ebbca7d GK |
5174 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5175 | emit_move_insn (operands[3], operands[2]); | |
5176 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5177 | DONE; | |
5178 | }") | |
802a0058 | 5179 | |
615158e2 | 5180 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) |
9ebbca7d GK |
5181 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) |
5182 | ; because the first makes it clear that operand 0 is not live | |
5183 | ; before the instruction. | |
5184 | (define_insn "fctiwz" | |
61c07d3c | 5185 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
615158e2 JJ |
5186 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] |
5187 | UNSPEC_FCTIWZ))] | |
a3170dc6 | 5188 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5189 | "{fcirz|fctiwz} %0,%1" |
5190 | [(set_attr "type" "fp")]) | |
5191 | ||
a3170dc6 AH |
5192 | (define_expand "floatsisf2" |
5193 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5194 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5195 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5196 | "") | |
5197 | ||
a473029f RK |
5198 | (define_insn "floatdidf2" |
5199 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5200 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5201 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5202 | "fcfid %0,%1" |
5203 | [(set_attr "type" "fp")]) | |
5204 | ||
05d49501 AM |
5205 | (define_insn_and_split "floatsidf_ppc64" |
5206 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5207 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5208 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5209 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5210 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5211 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 AM |
5212 | "#" |
5213 | "" | |
5214 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) | |
5215 | (set (match_dup 2) (match_dup 3)) | |
5216 | (set (match_dup 4) (match_dup 2)) | |
5217 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5218 | "") | |
5219 | ||
5220 | (define_insn_and_split "floatunssidf_ppc64" | |
5221 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5222 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5223 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5224 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5225 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5226 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 AM |
5227 | "#" |
5228 | "" | |
5229 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) | |
5230 | (set (match_dup 2) (match_dup 3)) | |
5231 | (set (match_dup 4) (match_dup 2)) | |
5232 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5233 | "") | |
5234 | ||
a473029f | 5235 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5236 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5237 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5238 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5239 | "fctidz %0,%1" |
5240 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5241 | |
678b7733 AM |
5242 | (define_expand "floatdisf2" |
5243 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5244 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
5245 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
5246 | " | |
5247 | { | |
5248 | if (!flag_unsafe_math_optimizations) | |
5249 | { | |
5250 | rtx label = gen_label_rtx (); | |
5251 | emit_insn (gen_floatdisf2_internal2 (operands[1], label)); | |
5252 | emit_label (label); | |
5253 | } | |
5254 | emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1])); | |
5255 | DONE; | |
5256 | }") | |
5257 | ||
5258 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
5259 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
5260 | ;; from double rounding. | |
5261 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 5262 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 5263 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 5264 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 5265 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
5266 | "#" |
5267 | "&& reload_completed" | |
5268 | [(set (match_dup 2) | |
5269 | (float:DF (match_dup 1))) | |
5270 | (set (match_dup 0) | |
5271 | (float_truncate:SF (match_dup 2)))] | |
5272 | "") | |
678b7733 AM |
5273 | |
5274 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 5275 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
5276 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
5277 | ;; rounding position. | |
5278 | (define_expand "floatdisf2_internal2" | |
42a6388c AM |
5279 | [(parallel [(set (match_dup 4) |
5280 | (compare:CC (and:DI (match_operand:DI 0 "" "") | |
5281 | (const_int 2047)) | |
5282 | (const_int 0))) | |
5283 | (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047))) | |
5284 | (clobber (match_scratch:CC 7 ""))]) | |
678b7733 AM |
5285 | (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53))) |
5286 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) | |
5287 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
5288 | (label_ref (match_operand:DI 1 "" "")) | |
5289 | (pc))) | |
5290 | (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2))) | |
5291 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
5292 | (label_ref (match_dup 1)) | |
5293 | (pc))) | |
5294 | (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2))) | |
5295 | (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))] | |
5296 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
5297 | " | |
5298 | { | |
5299 | operands[2] = gen_reg_rtx (DImode); | |
5300 | operands[3] = gen_reg_rtx (DImode); | |
5301 | operands[4] = gen_reg_rtx (CCmode); | |
5302 | operands[5] = gen_reg_rtx (CCUNSmode); | |
5303 | }") | |
1fd4e8c1 RK |
5304 | \f |
5305 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5306 | ;; of instructions. The & constraints are to prevent the register |
5307 | ;; allocator from allocating registers that overlap with the inputs | |
5308 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5309 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5310 | |
266eb58a | 5311 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5312 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5313 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5314 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5315 | "! TARGET_POWERPC64" |
0f645302 MM |
5316 | "* |
5317 | { | |
5318 | if (WORDS_BIG_ENDIAN) | |
5319 | return (GET_CODE (operands[2])) != CONST_INT | |
5320 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5321 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5322 | else | |
5323 | return (GET_CODE (operands[2])) != CONST_INT | |
5324 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5325 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5326 | }" | |
b19003d8 | 5327 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5328 | |
266eb58a | 5329 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5330 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5331 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5332 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5333 | "! TARGET_POWERPC64" |
5502823b RK |
5334 | "* |
5335 | { | |
0f645302 MM |
5336 | if (WORDS_BIG_ENDIAN) |
5337 | return (GET_CODE (operands[1]) != CONST_INT) | |
5338 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5339 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5340 | else | |
5341 | return (GET_CODE (operands[1]) != CONST_INT) | |
5342 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5343 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5344 | }" |
ca7f5001 RK |
5345 | [(set_attr "length" "8")]) |
5346 | ||
266eb58a | 5347 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5348 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5349 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5350 | "! TARGET_POWERPC64" |
5502823b RK |
5351 | "* |
5352 | { | |
5353 | return (WORDS_BIG_ENDIAN) | |
5354 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5355 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5356 | }" | |
ca7f5001 RK |
5357 | [(set_attr "length" "8")]) |
5358 | ||
8ffd9c51 RK |
5359 | (define_expand "mulsidi3" |
5360 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5361 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5362 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5363 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5364 | " |
5365 | { | |
5366 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5367 | { | |
39403d82 DE |
5368 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5369 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5370 | emit_insn (gen_mull_call ()); |
cf27b467 | 5371 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5372 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5373 | else |
5374 | { | |
5375 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5376 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5377 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5378 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5379 | } |
8ffd9c51 RK |
5380 | DONE; |
5381 | } | |
5382 | else if (TARGET_POWER) | |
5383 | { | |
5384 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5385 | DONE; | |
5386 | } | |
5387 | }") | |
deb9225a | 5388 | |
8ffd9c51 | 5389 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5390 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5391 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5392 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5393 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5394 | "TARGET_POWER" |
b19003d8 | 5395 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5396 | [(set_attr "type" "imul") |
5397 | (set_attr "length" "8")]) | |
deb9225a | 5398 | |
f192bf8b | 5399 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5400 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5401 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5402 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5403 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5404 | "* |
5405 | { | |
5406 | return (WORDS_BIG_ENDIAN) | |
5407 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5408 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5409 | }" | |
8ffd9c51 RK |
5410 | [(set_attr "type" "imul") |
5411 | (set_attr "length" "8")]) | |
deb9225a | 5412 | |
ebedb4dd MM |
5413 | (define_split |
5414 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5415 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5416 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5417 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5418 | [(set (match_dup 3) |
5419 | (truncate:SI | |
5420 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5421 | (sign_extend:DI (match_dup 2))) | |
5422 | (const_int 32)))) | |
5423 | (set (match_dup 4) | |
5424 | (mult:SI (match_dup 1) | |
5425 | (match_dup 2)))] | |
5426 | " | |
5427 | { | |
5428 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5429 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5430 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5431 | }") | |
5432 | ||
f192bf8b DE |
5433 | (define_expand "umulsidi3" |
5434 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5435 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5436 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5437 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5438 | " | |
5439 | { | |
5440 | if (TARGET_POWER) | |
5441 | { | |
5442 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5443 | DONE; | |
5444 | } | |
5445 | }") | |
5446 | ||
5447 | (define_insn "umulsidi3_mq" | |
5448 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5449 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5450 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5451 | (clobber (match_scratch:SI 3 "=q"))] | |
5452 | "TARGET_POWERPC && TARGET_POWER" | |
5453 | "* | |
5454 | { | |
5455 | return (WORDS_BIG_ENDIAN) | |
5456 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5457 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5458 | }" | |
5459 | [(set_attr "type" "imul") | |
5460 | (set_attr "length" "8")]) | |
5461 | ||
5462 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5463 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5464 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5465 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5466 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5467 | "* |
5468 | { | |
5469 | return (WORDS_BIG_ENDIAN) | |
5470 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5471 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5472 | }" | |
5473 | [(set_attr "type" "imul") | |
5474 | (set_attr "length" "8")]) | |
5475 | ||
ebedb4dd MM |
5476 | (define_split |
5477 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5478 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5479 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5480 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5481 | [(set (match_dup 3) |
5482 | (truncate:SI | |
5483 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5484 | (zero_extend:DI (match_dup 2))) | |
5485 | (const_int 32)))) | |
5486 | (set (match_dup 4) | |
5487 | (mult:SI (match_dup 1) | |
5488 | (match_dup 2)))] | |
5489 | " | |
5490 | { | |
5491 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5492 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5493 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5494 | }") | |
5495 | ||
8ffd9c51 RK |
5496 | (define_expand "smulsi3_highpart" |
5497 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5498 | (truncate:SI | |
5499 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5500 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5501 | (sign_extend:DI | |
5502 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5503 | (const_int 32))))] | |
5504 | "" | |
5505 | " | |
5506 | { | |
5507 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5508 | { | |
39403d82 DE |
5509 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5510 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5511 | emit_insn (gen_mulh_call ()); |
39403d82 | 5512 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5513 | DONE; |
5514 | } | |
5515 | else if (TARGET_POWER) | |
5516 | { | |
5517 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5518 | DONE; | |
5519 | } | |
5520 | }") | |
deb9225a | 5521 | |
8ffd9c51 RK |
5522 | (define_insn "smulsi3_highpart_mq" |
5523 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5524 | (truncate:SI | |
fada905b MM |
5525 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5526 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5527 | (sign_extend:DI | |
5528 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5529 | (const_int 32)))) |
5530 | (clobber (match_scratch:SI 3 "=q"))] | |
5531 | "TARGET_POWER" | |
5532 | "mul %0,%1,%2" | |
5533 | [(set_attr "type" "imul")]) | |
deb9225a | 5534 | |
f192bf8b | 5535 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5536 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5537 | (truncate:SI | |
fada905b MM |
5538 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5539 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5540 | (sign_extend:DI | |
5541 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5542 | (const_int 32))))] |
f192bf8b | 5543 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5544 | "mulhw %0,%1,%2" |
5545 | [(set_attr "type" "imul")]) | |
deb9225a | 5546 | |
f192bf8b DE |
5547 | (define_expand "umulsi3_highpart" |
5548 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5549 | (truncate:SI | |
5550 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5551 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5552 | (zero_extend:DI | |
5553 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5554 | (const_int 32))))] | |
5555 | "TARGET_POWERPC" | |
5556 | " | |
5557 | { | |
5558 | if (TARGET_POWER) | |
5559 | { | |
5560 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5561 | DONE; | |
5562 | } | |
5563 | }") | |
5564 | ||
5565 | (define_insn "umulsi3_highpart_mq" | |
5566 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5567 | (truncate:SI | |
5568 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5569 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5570 | (zero_extend:DI | |
5571 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5572 | (const_int 32)))) | |
5573 | (clobber (match_scratch:SI 3 "=q"))] | |
5574 | "TARGET_POWERPC && TARGET_POWER" | |
5575 | "mulhwu %0,%1,%2" | |
5576 | [(set_attr "type" "imul")]) | |
5577 | ||
5578 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5579 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5580 | (truncate:SI | |
5581 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5582 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5583 | (zero_extend:DI | |
5584 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5585 | (const_int 32))))] | |
f192bf8b | 5586 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5587 | "mulhwu %0,%1,%2" |
5588 | [(set_attr "type" "imul")]) | |
5589 | ||
5590 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5591 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5592 | ;; why we have the strange constraints below. | |
5593 | (define_insn "ashldi3_power" | |
5594 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5595 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5596 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5597 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5598 | "TARGET_POWER" | |
5599 | "@ | |
5600 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5601 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5602 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5603 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5604 | [(set_attr "length" "8")]) | |
5605 | ||
5606 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5607 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5608 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5609 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5610 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5611 | "TARGET_POWER" | |
5612 | "@ | |
47ad8c61 | 5613 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5614 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5615 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5616 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5617 | [(set_attr "length" "8")]) | |
5618 | ||
5619 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5620 | ;; just handle shifts by constants. | |
5621 | (define_insn "ashrdi3_power" | |
7093ddee | 5622 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5623 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5624 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5625 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5626 | "TARGET_POWER" | |
5627 | "@ | |
5628 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5629 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5630 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
5631 | |
5632 | (define_insn "ashrdi3_no_power" | |
5633 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
5634 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5635 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
5636 | "TARGET_32BIT && !TARGET_POWER" | |
5637 | "@ | |
5638 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5639 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
5640 | [(set_attr "length" "8,12")]) | |
266eb58a DE |
5641 | \f |
5642 | ;; PowerPC64 DImode operations. | |
5643 | ||
5644 | (define_expand "adddi3" | |
5645 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5646 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 5647 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
5648 | "" |
5649 | " | |
5650 | { | |
a260abc9 DE |
5651 | if (! TARGET_POWERPC64) |
5652 | { | |
5653 | if (non_short_cint_operand (operands[2], DImode)) | |
5654 | FAIL; | |
5655 | } | |
5656 | else | |
5657 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5658 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5659 | { |
677a9668 | 5660 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5661 | ? operands[0] : gen_reg_rtx (DImode)); |
5662 | ||
2bfcf297 | 5663 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5664 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5665 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
a260abc9 | 5666 | |
2bfcf297 DB |
5667 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
5668 | FAIL; | |
a260abc9 | 5669 | |
2bfcf297 DB |
5670 | /* The ordering here is important for the prolog expander. |
5671 | When space is allocated from the stack, adding 'low' first may | |
5672 | produce a temporary deallocation (which would be bad). */ | |
5673 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
5674 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
5675 | DONE; | |
5676 | } | |
266eb58a DE |
5677 | }") |
5678 | ||
5679 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5680 | ;; allowing register zero as source. | |
5681 | ||
a260abc9 | 5682 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5683 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5684 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5685 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5686 | "TARGET_POWERPC64" |
5687 | "@ | |
5688 | add %0,%1,%2 | |
5689 | addi %0,%1,%2 | |
5690 | addic %0,%1,%2 | |
802a0058 | 5691 | addis %0,%1,%v2") |
266eb58a | 5692 | |
a260abc9 | 5693 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5694 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5695 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5696 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5697 | (const_int 0))) |
9ebbca7d | 5698 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
266eb58a DE |
5699 | "TARGET_POWERPC64" |
5700 | "@ | |
5701 | add. %3,%1,%2 | |
9ebbca7d GK |
5702 | addic. %3,%1,%2 |
5703 | # | |
5704 | #" | |
a62bfff2 | 5705 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5706 | (set_attr "length" "4,4,8,8")]) |
5707 | ||
5708 | (define_split | |
5709 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5710 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5711 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5712 | (const_int 0))) | |
5713 | (clobber (match_scratch:DI 3 ""))] | |
5714 | "TARGET_POWERPC64 && reload_completed" | |
5715 | [(set (match_dup 3) | |
5716 | (plus:DI (match_dup 1) (match_dup 2))) | |
5717 | (set (match_dup 0) | |
5718 | (compare:CC (match_dup 3) | |
5719 | (const_int 0)))] | |
5720 | "") | |
266eb58a | 5721 | |
a260abc9 | 5722 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5723 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5724 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5725 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5726 | (const_int 0))) |
9ebbca7d | 5727 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a DE |
5728 | (plus:DI (match_dup 1) (match_dup 2)))] |
5729 | "TARGET_POWERPC64" | |
5730 | "@ | |
5731 | add. %0,%1,%2 | |
9ebbca7d GK |
5732 | addic. %0,%1,%2 |
5733 | # | |
5734 | #" | |
a62bfff2 | 5735 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5736 | (set_attr "length" "4,4,8,8")]) |
5737 | ||
5738 | (define_split | |
5739 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5740 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5741 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5742 | (const_int 0))) | |
5743 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5744 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5745 | "TARGET_POWERPC64 && reload_completed" | |
5746 | [(set (match_dup 0) | |
5747 | (plus:DI (match_dup 1) (match_dup 2))) | |
5748 | (set (match_dup 3) | |
5749 | (compare:CC (match_dup 0) | |
5750 | (const_int 0)))] | |
5751 | "") | |
266eb58a DE |
5752 | |
5753 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5754 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5755 | ;; add should be last in case the result gets used in an address. | |
5756 | ||
5757 | (define_split | |
5758 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5759 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5760 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5761 | "TARGET_POWERPC64" | |
5762 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5763 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5764 | " | |
5765 | { | |
2bfcf297 | 5766 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5767 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5768 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
266eb58a | 5769 | |
2bfcf297 DB |
5770 | operands[4] = GEN_INT (low); |
5771 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
5772 | operands[3] = GEN_INT (rest); | |
5773 | else if (! no_new_pseudos) | |
38886f37 | 5774 | { |
2bfcf297 DB |
5775 | operands[3] = gen_reg_rtx (DImode); |
5776 | emit_move_insn (operands[3], operands[2]); | |
5777 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
5778 | DONE; | |
38886f37 | 5779 | } |
2bfcf297 DB |
5780 | else |
5781 | FAIL; | |
266eb58a DE |
5782 | }") |
5783 | ||
5784 | (define_insn "one_cmpldi2" | |
5785 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5786 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5787 | "TARGET_POWERPC64" | |
5788 | "nor %0,%1,%1") | |
5789 | ||
5790 | (define_insn "" | |
9ebbca7d GK |
5791 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5792 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5793 | (const_int 0))) |
9ebbca7d | 5794 | (clobber (match_scratch:DI 2 "=r,r"))] |
266eb58a | 5795 | "TARGET_POWERPC64" |
9ebbca7d GK |
5796 | "@ |
5797 | nor. %2,%1,%1 | |
5798 | #" | |
5799 | [(set_attr "type" "compare") | |
5800 | (set_attr "length" "4,8")]) | |
5801 | ||
5802 | (define_split | |
5803 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5804 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5805 | (const_int 0))) | |
5806 | (clobber (match_scratch:DI 2 ""))] | |
5807 | "TARGET_POWERPC64 && reload_completed" | |
5808 | [(set (match_dup 2) | |
5809 | (not:DI (match_dup 1))) | |
5810 | (set (match_dup 0) | |
5811 | (compare:CC (match_dup 2) | |
5812 | (const_int 0)))] | |
5813 | "") | |
266eb58a DE |
5814 | |
5815 | (define_insn "" | |
9ebbca7d GK |
5816 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5817 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5818 | (const_int 0))) |
9ebbca7d | 5819 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5820 | (not:DI (match_dup 1)))] |
5821 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5822 | "@ |
5823 | nor. %0,%1,%1 | |
5824 | #" | |
5825 | [(set_attr "type" "compare") | |
5826 | (set_attr "length" "4,8")]) | |
5827 | ||
5828 | (define_split | |
5829 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5830 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5831 | (const_int 0))) | |
5832 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5833 | (not:DI (match_dup 1)))] | |
5834 | "TARGET_POWERPC64 && reload_completed" | |
5835 | [(set (match_dup 0) | |
5836 | (not:DI (match_dup 1))) | |
5837 | (set (match_dup 2) | |
5838 | (compare:CC (match_dup 0) | |
5839 | (const_int 0)))] | |
5840 | "") | |
266eb58a DE |
5841 | |
5842 | (define_insn "" | |
5843 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5844 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5845 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5846 | "TARGET_POWERPC64" | |
5847 | "@ | |
5848 | subf %0,%2,%1 | |
5849 | subfic %0,%2,%1") | |
5850 | ||
5851 | (define_insn "" | |
9ebbca7d GK |
5852 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5853 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5854 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5855 | (const_int 0))) |
9ebbca7d | 5856 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 5857 | "TARGET_POWERPC64" |
9ebbca7d GK |
5858 | "@ |
5859 | subf. %3,%2,%1 | |
5860 | #" | |
a62bfff2 | 5861 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5862 | (set_attr "length" "4,8")]) |
5863 | ||
5864 | (define_split | |
5865 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5866 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5867 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5868 | (const_int 0))) | |
5869 | (clobber (match_scratch:DI 3 ""))] | |
5870 | "TARGET_POWERPC64 && reload_completed" | |
5871 | [(set (match_dup 3) | |
5872 | (minus:DI (match_dup 1) (match_dup 2))) | |
5873 | (set (match_dup 0) | |
5874 | (compare:CC (match_dup 3) | |
5875 | (const_int 0)))] | |
5876 | "") | |
266eb58a DE |
5877 | |
5878 | (define_insn "" | |
9ebbca7d GK |
5879 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5880 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5881 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5882 | (const_int 0))) |
9ebbca7d | 5883 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5884 | (minus:DI (match_dup 1) (match_dup 2)))] |
5885 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5886 | "@ |
5887 | subf. %0,%2,%1 | |
5888 | #" | |
a62bfff2 | 5889 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5890 | (set_attr "length" "4,8")]) |
5891 | ||
5892 | (define_split | |
5893 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5894 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5895 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5896 | (const_int 0))) | |
5897 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5898 | (minus:DI (match_dup 1) (match_dup 2)))] | |
5899 | "TARGET_POWERPC64 && reload_completed" | |
5900 | [(set (match_dup 0) | |
5901 | (minus:DI (match_dup 1) (match_dup 2))) | |
5902 | (set (match_dup 3) | |
5903 | (compare:CC (match_dup 0) | |
5904 | (const_int 0)))] | |
5905 | "") | |
266eb58a DE |
5906 | |
5907 | (define_expand "subdi3" | |
5908 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5909 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 5910 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
5911 | "" |
5912 | " | |
5913 | { | |
5914 | if (GET_CODE (operands[2]) == CONST_INT) | |
5915 | { | |
5916 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
5917 | negate_rtx (DImode, operands[2]))); | |
5918 | DONE; | |
5919 | } | |
5920 | }") | |
5921 | ||
ea112fc4 | 5922 | (define_insn_and_split "absdi2" |
266eb58a | 5923 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5924 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
5925 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5926 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5927 | "#" |
5928 | "&& reload_completed" | |
a260abc9 | 5929 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5930 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 5931 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
5932 | "") |
5933 | ||
ea112fc4 | 5934 | (define_insn_and_split "*nabsdi2" |
266eb58a | 5935 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5936 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
5937 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5938 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5939 | "#" |
5940 | "&& reload_completed" | |
a260abc9 | 5941 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5942 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 5943 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
5944 | "") |
5945 | ||
5946 | (define_expand "negdi2" | |
5947 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5948 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
5949 | "" | |
5950 | "") | |
5951 | ||
5952 | (define_insn "" | |
5953 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5954 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5955 | "TARGET_POWERPC64" | |
5956 | "neg %0,%1") | |
5957 | ||
5958 | (define_insn "" | |
9ebbca7d GK |
5959 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5960 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5961 | (const_int 0))) |
9ebbca7d | 5962 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 5963 | "TARGET_POWERPC64" |
9ebbca7d GK |
5964 | "@ |
5965 | neg. %2,%1 | |
5966 | #" | |
a62bfff2 | 5967 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5968 | (set_attr "length" "4,8")]) |
5969 | ||
5970 | (define_split | |
5971 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5972 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5973 | (const_int 0))) | |
5974 | (clobber (match_scratch:DI 2 ""))] | |
5975 | "TARGET_POWERPC64 && reload_completed" | |
5976 | [(set (match_dup 2) | |
5977 | (neg:DI (match_dup 1))) | |
5978 | (set (match_dup 0) | |
5979 | (compare:CC (match_dup 2) | |
5980 | (const_int 0)))] | |
5981 | "") | |
815cdc52 | 5982 | |
29ae5b89 | 5983 | (define_insn "" |
9ebbca7d GK |
5984 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5985 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 5986 | (const_int 0))) |
9ebbca7d | 5987 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 5988 | (neg:DI (match_dup 1)))] |
29ae5b89 | 5989 | "TARGET_POWERPC64" |
9ebbca7d GK |
5990 | "@ |
5991 | neg. %0,%1 | |
5992 | #" | |
a62bfff2 | 5993 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5994 | (set_attr "length" "4,8")]) |
5995 | ||
5996 | (define_split | |
5997 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5998 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5999 | (const_int 0))) | |
6000 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6001 | (neg:DI (match_dup 1)))] | |
6002 | "TARGET_POWERPC64 && reload_completed" | |
6003 | [(set (match_dup 0) | |
6004 | (neg:DI (match_dup 1))) | |
6005 | (set (match_dup 2) | |
6006 | (compare:CC (match_dup 0) | |
6007 | (const_int 0)))] | |
6008 | "") | |
266eb58a | 6009 | |
1b1edcfa DE |
6010 | (define_insn "clzdi2" |
6011 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6012 | (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6013 | "TARGET_POWERPC64" | |
6014 | "cntlzd %0,%1") | |
6015 | ||
6016 | (define_expand "ctzdi2" | |
4977bab6 | 6017 | [(set (match_dup 2) |
1b1edcfa | 6018 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 6019 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
1b1edcfa DE |
6020 | (match_dup 2))) |
6021 | (clobber (scratch:CC))]) | |
d865b122 | 6022 | (set (match_dup 4) (clz:DI (match_dup 3))) |
4977bab6 | 6023 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 6024 | (minus:DI (const_int 63) (match_dup 4)))] |
266eb58a | 6025 | "TARGET_POWERPC64" |
4977bab6 ZW |
6026 | { |
6027 | operands[2] = gen_reg_rtx (DImode); | |
6028 | operands[3] = gen_reg_rtx (DImode); | |
6029 | operands[4] = gen_reg_rtx (DImode); | |
6030 | }) | |
6031 | ||
1b1edcfa DE |
6032 | (define_expand "ffsdi2" |
6033 | [(set (match_dup 2) | |
6034 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
6035 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) | |
6036 | (match_dup 2))) | |
6037 | (clobber (scratch:CC))]) | |
6038 | (set (match_dup 4) (clz:DI (match_dup 3))) | |
6039 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6040 | (minus:DI (const_int 64) (match_dup 4)))] | |
4977bab6 | 6041 | "TARGET_POWERPC64" |
1b1edcfa DE |
6042 | { |
6043 | operands[2] = gen_reg_rtx (DImode); | |
6044 | operands[3] = gen_reg_rtx (DImode); | |
6045 | operands[4] = gen_reg_rtx (DImode); | |
6046 | }) | |
266eb58a DE |
6047 | |
6048 | (define_insn "muldi3" | |
6049 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6050 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6051 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6052 | "TARGET_POWERPC64" | |
6053 | "mulld %0,%1,%2" | |
3cb999d8 | 6054 | [(set_attr "type" "lmul")]) |
266eb58a | 6055 | |
9259f3b0 DE |
6056 | (define_insn "*muldi3_internal1" |
6057 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6058 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6059 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6060 | (const_int 0))) | |
6061 | (clobber (match_scratch:DI 3 "=r,r"))] | |
6062 | "TARGET_POWERPC64" | |
6063 | "@ | |
6064 | mulld. %3,%1,%2 | |
6065 | #" | |
6066 | [(set_attr "type" "lmul_compare") | |
6067 | (set_attr "length" "4,8")]) | |
6068 | ||
6069 | (define_split | |
6070 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6071 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6072 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6073 | (const_int 0))) | |
6074 | (clobber (match_scratch:DI 3 ""))] | |
6075 | "TARGET_POWERPC64 && reload_completed" | |
6076 | [(set (match_dup 3) | |
6077 | (mult:DI (match_dup 1) (match_dup 2))) | |
6078 | (set (match_dup 0) | |
6079 | (compare:CC (match_dup 3) | |
6080 | (const_int 0)))] | |
6081 | "") | |
6082 | ||
6083 | (define_insn "*muldi3_internal2" | |
6084 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | |
6085 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6086 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6087 | (const_int 0))) | |
6088 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6089 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6090 | "TARGET_POWERPC64" | |
6091 | "@ | |
6092 | mulld. %0,%1,%2 | |
6093 | #" | |
6094 | [(set_attr "type" "lmul_compare") | |
6095 | (set_attr "length" "4,8")]) | |
6096 | ||
6097 | (define_split | |
6098 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6099 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6100 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6101 | (const_int 0))) | |
6102 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6103 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6104 | "TARGET_POWERPC64 && reload_completed" | |
6105 | [(set (match_dup 0) | |
6106 | (mult:DI (match_dup 1) (match_dup 2))) | |
6107 | (set (match_dup 3) | |
6108 | (compare:CC (match_dup 0) | |
6109 | (const_int 0)))] | |
6110 | "") | |
6111 | ||
266eb58a DE |
6112 | (define_insn "smuldi3_highpart" |
6113 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6114 | (truncate:DI | |
6115 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6116 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6117 | (sign_extend:TI | |
6118 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6119 | (const_int 64))))] | |
6120 | "TARGET_POWERPC64" | |
6121 | "mulhd %0,%1,%2" | |
3cb999d8 | 6122 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6123 | |
6124 | (define_insn "umuldi3_highpart" | |
6125 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6126 | (truncate:DI | |
6127 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6128 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6129 | (zero_extend:TI | |
6130 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6131 | (const_int 64))))] | |
6132 | "TARGET_POWERPC64" | |
6133 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6134 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6135 | |
6136 | (define_expand "divdi3" | |
6137 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6138 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6139 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6140 | "TARGET_POWERPC64" | |
6141 | " | |
6142 | { | |
6143 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6144 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6145 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6146 | ; | |
6147 | else | |
6148 | operands[2] = force_reg (DImode, operands[2]); | |
6149 | }") | |
6150 | ||
6151 | (define_expand "moddi3" | |
6152 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6153 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6154 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6155 | "TARGET_POWERPC64" | |
6156 | " | |
6157 | { | |
2bfcf297 | 6158 | int i; |
266eb58a DE |
6159 | rtx temp1; |
6160 | rtx temp2; | |
6161 | ||
2bfcf297 DB |
6162 | if (GET_CODE (operands[2]) != CONST_INT |
6163 | || INTVAL (operands[2]) <= 0 | |
6164 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6165 | FAIL; |
6166 | ||
6167 | temp1 = gen_reg_rtx (DImode); | |
6168 | temp2 = gen_reg_rtx (DImode); | |
6169 | ||
6170 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6171 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6172 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6173 | DONE; | |
6174 | }") | |
6175 | ||
6176 | (define_insn "" | |
6177 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6178 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6179 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6180 | "TARGET_POWERPC64" | |
266eb58a DE |
6181 | "sradi %0,%1,%p2\;addze %0,%0" |
6182 | [(set_attr "length" "8")]) | |
6183 | ||
6184 | (define_insn "" | |
9ebbca7d GK |
6185 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6186 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6187 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6188 | (const_int 0))) |
9ebbca7d | 6189 | (clobber (match_scratch:DI 3 "=r,r"))] |
2bfcf297 | 6190 | "TARGET_POWERPC64" |
9ebbca7d GK |
6191 | "@ |
6192 | sradi %3,%1,%p2\;addze. %3,%3 | |
6193 | #" | |
266eb58a | 6194 | [(set_attr "type" "compare") |
9ebbca7d GK |
6195 | (set_attr "length" "8,12")]) |
6196 | ||
6197 | (define_split | |
6198 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6199 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6200 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6201 | (const_int 0))) |
6202 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6203 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6204 | [(set (match_dup 3) |
6205 | (div:DI (match_dup 1) (match_dup 2))) | |
6206 | (set (match_dup 0) | |
6207 | (compare:CC (match_dup 3) | |
6208 | (const_int 0)))] | |
6209 | "") | |
266eb58a DE |
6210 | |
6211 | (define_insn "" | |
9ebbca7d GK |
6212 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6213 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6214 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6215 | (const_int 0))) |
9ebbca7d | 6216 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6217 | (div:DI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 6218 | "TARGET_POWERPC64" |
9ebbca7d GK |
6219 | "@ |
6220 | sradi %0,%1,%p2\;addze. %0,%0 | |
6221 | #" | |
266eb58a | 6222 | [(set_attr "type" "compare") |
9ebbca7d | 6223 | (set_attr "length" "8,12")]) |
266eb58a | 6224 | |
9ebbca7d GK |
6225 | (define_split |
6226 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6227 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6228 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6229 | (const_int 0))) |
6230 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6231 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6232 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6233 | [(set (match_dup 0) |
6234 | (div:DI (match_dup 1) (match_dup 2))) | |
6235 | (set (match_dup 3) | |
6236 | (compare:CC (match_dup 0) | |
6237 | (const_int 0)))] | |
6238 | "") | |
6239 | ||
6240 | (define_insn "" | |
6241 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6242 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6243 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6244 | "TARGET_POWERPC64" |
6245 | "divd %0,%1,%2" | |
3cb999d8 | 6246 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6247 | |
6248 | (define_insn "udivdi3" | |
6249 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6250 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6251 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6252 | "TARGET_POWERPC64" | |
6253 | "divdu %0,%1,%2" | |
3cb999d8 | 6254 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6255 | |
6256 | (define_insn "rotldi3" | |
6257 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6258 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6259 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6260 | "TARGET_POWERPC64" | |
a66078ee | 6261 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6262 | |
a260abc9 | 6263 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6264 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6265 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6266 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6267 | (const_int 0))) |
9ebbca7d | 6268 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6269 | "TARGET_POWERPC64" |
9ebbca7d GK |
6270 | "@ |
6271 | rld%I2cl. %3,%1,%H2,0 | |
6272 | #" | |
6273 | [(set_attr "type" "delayed_compare") | |
6274 | (set_attr "length" "4,8")]) | |
6275 | ||
6276 | (define_split | |
6277 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6278 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6279 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6280 | (const_int 0))) | |
6281 | (clobber (match_scratch:DI 3 ""))] | |
6282 | "TARGET_POWERPC64 && reload_completed" | |
6283 | [(set (match_dup 3) | |
6284 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6285 | (set (match_dup 0) | |
6286 | (compare:CC (match_dup 3) | |
6287 | (const_int 0)))] | |
6288 | "") | |
266eb58a | 6289 | |
a260abc9 | 6290 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6291 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6292 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6293 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6294 | (const_int 0))) |
9ebbca7d | 6295 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6296 | (rotate:DI (match_dup 1) (match_dup 2)))] |
6297 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6298 | "@ |
6299 | rld%I2cl. %0,%1,%H2,0 | |
6300 | #" | |
6301 | [(set_attr "type" "delayed_compare") | |
6302 | (set_attr "length" "4,8")]) | |
6303 | ||
6304 | (define_split | |
6305 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6306 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6307 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6308 | (const_int 0))) | |
6309 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6310 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6311 | "TARGET_POWERPC64 && reload_completed" | |
6312 | [(set (match_dup 0) | |
6313 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6314 | (set (match_dup 3) | |
6315 | (compare:CC (match_dup 0) | |
6316 | (const_int 0)))] | |
6317 | "") | |
266eb58a | 6318 | |
a260abc9 DE |
6319 | (define_insn "*rotldi3_internal4" |
6320 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6321 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6322 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
ce71f754 | 6323 | (match_operand:DI 3 "mask64_operand" "n")))] |
a260abc9 DE |
6324 | "TARGET_POWERPC64" |
6325 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6326 | ||
6327 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6328 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6329 | (compare:CC (and:DI |
9ebbca7d GK |
6330 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6331 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6332 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6333 | (const_int 0))) |
9ebbca7d | 6334 | (clobber (match_scratch:DI 4 "=r,r"))] |
a260abc9 | 6335 | "TARGET_POWERPC64" |
9ebbca7d GK |
6336 | "@ |
6337 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6338 | #" | |
6339 | [(set_attr "type" "delayed_compare") | |
6340 | (set_attr "length" "4,8")]) | |
6341 | ||
6342 | (define_split | |
6343 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6344 | (compare:CC (and:DI | |
6345 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6346 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6347 | (match_operand:DI 3 "mask64_operand" "")) | |
6348 | (const_int 0))) | |
6349 | (clobber (match_scratch:DI 4 ""))] | |
6350 | "TARGET_POWERPC64 && reload_completed" | |
6351 | [(set (match_dup 4) | |
6352 | (and:DI (rotate:DI (match_dup 1) | |
6353 | (match_dup 2)) | |
6354 | (match_dup 3))) | |
6355 | (set (match_dup 0) | |
6356 | (compare:CC (match_dup 4) | |
6357 | (const_int 0)))] | |
6358 | "") | |
a260abc9 DE |
6359 | |
6360 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6361 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6362 | (compare:CC (and:DI |
9ebbca7d GK |
6363 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6364 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6365 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6366 | (const_int 0))) |
9ebbca7d | 6367 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6368 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
6369 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6370 | "@ |
6371 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6372 | #" | |
6373 | [(set_attr "type" "delayed_compare") | |
6374 | (set_attr "length" "4,8")]) | |
6375 | ||
6376 | (define_split | |
6377 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6378 | (compare:CC (and:DI | |
6379 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6380 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6381 | (match_operand:DI 3 "mask64_operand" "")) | |
6382 | (const_int 0))) | |
6383 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6384 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6385 | "TARGET_POWERPC64 && reload_completed" | |
6386 | [(set (match_dup 0) | |
6387 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6388 | (set (match_dup 4) | |
6389 | (compare:CC (match_dup 0) | |
6390 | (const_int 0)))] | |
6391 | "") | |
a260abc9 DE |
6392 | |
6393 | (define_insn "*rotldi3_internal7" | |
6394 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6395 | (zero_extend:DI | |
6396 | (subreg:QI | |
6397 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6398 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6399 | "TARGET_POWERPC64" | |
6400 | "rld%I2cl %0,%1,%H2,56") | |
6401 | ||
6402 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6403 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6404 | (compare:CC (zero_extend:DI |
6405 | (subreg:QI | |
9ebbca7d GK |
6406 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6407 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6408 | (const_int 0))) |
9ebbca7d | 6409 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6410 | "TARGET_POWERPC64" |
9ebbca7d GK |
6411 | "@ |
6412 | rld%I2cl. %3,%1,%H2,56 | |
6413 | #" | |
6414 | [(set_attr "type" "delayed_compare") | |
6415 | (set_attr "length" "4,8")]) | |
6416 | ||
6417 | (define_split | |
6418 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6419 | (compare:CC (zero_extend:DI | |
6420 | (subreg:QI | |
6421 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6422 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6423 | (const_int 0))) | |
6424 | (clobber (match_scratch:DI 3 ""))] | |
6425 | "TARGET_POWERPC64 && reload_completed" | |
6426 | [(set (match_dup 3) | |
6427 | (zero_extend:DI (subreg:QI | |
6428 | (rotate:DI (match_dup 1) | |
6429 | (match_dup 2)) 0))) | |
6430 | (set (match_dup 0) | |
6431 | (compare:CC (match_dup 3) | |
6432 | (const_int 0)))] | |
6433 | "") | |
a260abc9 DE |
6434 | |
6435 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6436 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6437 | (compare:CC (zero_extend:DI |
6438 | (subreg:QI | |
9ebbca7d GK |
6439 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6440 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6441 | (const_int 0))) |
9ebbca7d | 6442 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6443 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6444 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6445 | "@ |
6446 | rld%I2cl. %0,%1,%H2,56 | |
6447 | #" | |
6448 | [(set_attr "type" "delayed_compare") | |
6449 | (set_attr "length" "4,8")]) | |
6450 | ||
6451 | (define_split | |
6452 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6453 | (compare:CC (zero_extend:DI | |
6454 | (subreg:QI | |
6455 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6456 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6457 | (const_int 0))) | |
6458 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6459 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6460 | "TARGET_POWERPC64 && reload_completed" | |
6461 | [(set (match_dup 0) | |
6462 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6463 | (set (match_dup 3) | |
6464 | (compare:CC (match_dup 0) | |
6465 | (const_int 0)))] | |
6466 | "") | |
a260abc9 DE |
6467 | |
6468 | (define_insn "*rotldi3_internal10" | |
6469 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6470 | (zero_extend:DI | |
6471 | (subreg:HI | |
6472 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6473 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6474 | "TARGET_POWERPC64" | |
6475 | "rld%I2cl %0,%1,%H2,48") | |
6476 | ||
6477 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6478 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6479 | (compare:CC (zero_extend:DI |
6480 | (subreg:HI | |
9ebbca7d GK |
6481 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6482 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6483 | (const_int 0))) |
9ebbca7d | 6484 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6485 | "TARGET_POWERPC64" |
9ebbca7d GK |
6486 | "@ |
6487 | rld%I2cl. %3,%1,%H2,48 | |
6488 | #" | |
6489 | [(set_attr "type" "delayed_compare") | |
6490 | (set_attr "length" "4,8")]) | |
6491 | ||
6492 | (define_split | |
6493 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6494 | (compare:CC (zero_extend:DI | |
6495 | (subreg:HI | |
6496 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6497 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6498 | (const_int 0))) | |
6499 | (clobber (match_scratch:DI 3 ""))] | |
6500 | "TARGET_POWERPC64 && reload_completed" | |
6501 | [(set (match_dup 3) | |
6502 | (zero_extend:DI (subreg:HI | |
6503 | (rotate:DI (match_dup 1) | |
6504 | (match_dup 2)) 0))) | |
6505 | (set (match_dup 0) | |
6506 | (compare:CC (match_dup 3) | |
6507 | (const_int 0)))] | |
6508 | "") | |
a260abc9 DE |
6509 | |
6510 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6511 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6512 | (compare:CC (zero_extend:DI |
6513 | (subreg:HI | |
9ebbca7d GK |
6514 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6515 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6516 | (const_int 0))) |
9ebbca7d | 6517 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6518 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6519 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6520 | "@ |
6521 | rld%I2cl. %0,%1,%H2,48 | |
6522 | #" | |
6523 | [(set_attr "type" "delayed_compare") | |
6524 | (set_attr "length" "4,8")]) | |
6525 | ||
6526 | (define_split | |
6527 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6528 | (compare:CC (zero_extend:DI | |
6529 | (subreg:HI | |
6530 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6531 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6532 | (const_int 0))) | |
6533 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6534 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6535 | "TARGET_POWERPC64 && reload_completed" | |
6536 | [(set (match_dup 0) | |
6537 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6538 | (set (match_dup 3) | |
6539 | (compare:CC (match_dup 0) | |
6540 | (const_int 0)))] | |
6541 | "") | |
a260abc9 DE |
6542 | |
6543 | (define_insn "*rotldi3_internal13" | |
6544 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6545 | (zero_extend:DI | |
6546 | (subreg:SI | |
6547 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6548 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6549 | "TARGET_POWERPC64" | |
6550 | "rld%I2cl %0,%1,%H2,32") | |
6551 | ||
6552 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6553 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6554 | (compare:CC (zero_extend:DI |
6555 | (subreg:SI | |
9ebbca7d GK |
6556 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6557 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6558 | (const_int 0))) |
9ebbca7d | 6559 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6560 | "TARGET_POWERPC64" |
9ebbca7d GK |
6561 | "@ |
6562 | rld%I2cl. %3,%1,%H2,32 | |
6563 | #" | |
6564 | [(set_attr "type" "delayed_compare") | |
6565 | (set_attr "length" "4,8")]) | |
6566 | ||
6567 | (define_split | |
6568 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6569 | (compare:CC (zero_extend:DI | |
6570 | (subreg:SI | |
6571 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6572 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6573 | (const_int 0))) | |
6574 | (clobber (match_scratch:DI 3 ""))] | |
6575 | "TARGET_POWERPC64 && reload_completed" | |
6576 | [(set (match_dup 3) | |
6577 | (zero_extend:DI (subreg:SI | |
6578 | (rotate:DI (match_dup 1) | |
6579 | (match_dup 2)) 0))) | |
6580 | (set (match_dup 0) | |
6581 | (compare:CC (match_dup 3) | |
6582 | (const_int 0)))] | |
6583 | "") | |
a260abc9 DE |
6584 | |
6585 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6586 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6587 | (compare:CC (zero_extend:DI |
6588 | (subreg:SI | |
9ebbca7d GK |
6589 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6590 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6591 | (const_int 0))) |
9ebbca7d | 6592 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6593 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6594 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6595 | "@ |
6596 | rld%I2cl. %0,%1,%H2,32 | |
6597 | #" | |
6598 | [(set_attr "type" "delayed_compare") | |
6599 | (set_attr "length" "4,8")]) | |
6600 | ||
6601 | (define_split | |
6602 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6603 | (compare:CC (zero_extend:DI | |
6604 | (subreg:SI | |
6605 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6606 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6607 | (const_int 0))) | |
6608 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6609 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6610 | "TARGET_POWERPC64 && reload_completed" | |
6611 | [(set (match_dup 0) | |
6612 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6613 | (set (match_dup 3) | |
6614 | (compare:CC (match_dup 0) | |
6615 | (const_int 0)))] | |
6616 | "") | |
a260abc9 | 6617 | |
266eb58a DE |
6618 | (define_expand "ashldi3" |
6619 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6620 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6621 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6622 | "TARGET_POWERPC64 || TARGET_POWER" | |
6623 | " | |
6624 | { | |
6625 | if (TARGET_POWERPC64) | |
6626 | ; | |
6627 | else if (TARGET_POWER) | |
6628 | { | |
6629 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6630 | DONE; | |
6631 | } | |
6632 | else | |
6633 | FAIL; | |
6634 | }") | |
6635 | ||
e2c953b6 | 6636 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6637 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6638 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6639 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6640 | "TARGET_POWERPC64" | |
a66078ee | 6641 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
6642 | [(set_attr "length" "8")]) |
6643 | ||
e2c953b6 | 6644 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6645 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6646 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6647 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6648 | (const_int 0))) |
9ebbca7d | 6649 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6650 | "TARGET_POWERPC64" |
9ebbca7d GK |
6651 | "@ |
6652 | sld%I2. %3,%1,%H2 | |
6653 | #" | |
6654 | [(set_attr "type" "delayed_compare") | |
6655 | (set_attr "length" "4,8")]) | |
29ae5b89 | 6656 | |
9ebbca7d GK |
6657 | (define_split |
6658 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6659 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6660 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6661 | (const_int 0))) | |
6662 | (clobber (match_scratch:DI 3 ""))] | |
6663 | "TARGET_POWERPC64 && reload_completed" | |
6664 | [(set (match_dup 3) | |
6665 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6666 | (set (match_dup 0) | |
6667 | (compare:CC (match_dup 3) | |
6668 | (const_int 0)))] | |
6669 | "") | |
6670 | ||
e2c953b6 | 6671 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6672 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6673 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6674 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6675 | (const_int 0))) |
9ebbca7d | 6676 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6677 | (ashift:DI (match_dup 1) (match_dup 2)))] |
6678 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6679 | "@ |
6680 | sld%I2. %0,%1,%H2 | |
6681 | #" | |
6682 | [(set_attr "type" "delayed_compare") | |
6683 | (set_attr "length" "4,8")]) | |
6684 | ||
6685 | (define_split | |
6686 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6687 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6688 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6689 | (const_int 0))) | |
6690 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6691 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6692 | "TARGET_POWERPC64 && reload_completed" | |
6693 | [(set (match_dup 0) | |
6694 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6695 | (set (match_dup 3) | |
6696 | (compare:CC (match_dup 0) | |
6697 | (const_int 0)))] | |
6698 | "") | |
266eb58a | 6699 | |
e2c953b6 | 6700 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6701 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6702 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6703 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6704 | (match_operand:DI 3 "const_int_operand" "n")))] |
6705 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6706 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6707 | |
e2c953b6 | 6708 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6709 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6710 | (compare:CC |
9ebbca7d GK |
6711 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6712 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6713 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6714 | (const_int 0))) |
9ebbca7d | 6715 | (clobber (match_scratch:DI 4 "=r,r"))] |
c5059423 | 6716 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6717 | "@ |
e2c953b6 | 6718 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6719 | #" |
6720 | [(set_attr "type" "delayed_compare") | |
6721 | (set_attr "length" "4,8")]) | |
6722 | ||
6723 | (define_split | |
6724 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6725 | (compare:CC | |
6726 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6727 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6728 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6729 | (const_int 0))) |
6730 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6731 | "TARGET_POWERPC64 && reload_completed |
6732 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6733 | [(set (match_dup 4) |
6734 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6735 | (match_dup 3))) |
9ebbca7d GK |
6736 | (set (match_dup 0) |
6737 | (compare:CC (match_dup 4) | |
6738 | (const_int 0)))] | |
6739 | "") | |
3cb999d8 | 6740 | |
e2c953b6 | 6741 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6742 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6743 | (compare:CC |
9ebbca7d GK |
6744 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6745 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6746 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6747 | (const_int 0))) |
9ebbca7d | 6748 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6749 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
c5059423 | 6750 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6751 | "@ |
e2c953b6 | 6752 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6753 | #" |
6754 | [(set_attr "type" "delayed_compare") | |
6755 | (set_attr "length" "4,8")]) | |
6756 | ||
6757 | (define_split | |
6758 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6759 | (compare:CC | |
6760 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6761 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6762 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6763 | (const_int 0))) |
6764 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6765 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6766 | "TARGET_POWERPC64 && reload_completed |
6767 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6768 | [(set (match_dup 0) | |
6769 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6770 | (match_dup 3))) | |
6771 | (set (match_dup 4) | |
6772 | (compare:CC (match_dup 0) | |
6773 | (const_int 0)))] | |
6774 | "") | |
6775 | ||
6776 | (define_insn "*ashldi3_internal7" | |
6777 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6778 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6779 | (match_operand:SI 2 "const_int_operand" "i")) | |
ce71f754 | 6780 | (match_operand:DI 3 "mask64_operand" "n")))] |
c5059423 AM |
6781 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
6782 | "rldicr %0,%1,%H2,%S3") | |
6783 | ||
6784 | (define_insn "ashldi3_internal8" | |
6785 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6786 | (compare:CC | |
6787 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6788 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6789 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6790 | (const_int 0))) |
6791 | (clobber (match_scratch:DI 4 "=r,r"))] | |
6792 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6793 | "@ | |
6794 | rldicr. %4,%1,%H2,%S3 | |
6795 | #" | |
6796 | [(set_attr "type" "delayed_compare") | |
6797 | (set_attr "length" "4,8")]) | |
6798 | ||
6799 | (define_split | |
6800 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6801 | (compare:CC | |
6802 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6803 | (match_operand:SI 2 "const_int_operand" "")) | |
6804 | (match_operand:DI 3 "mask64_operand" "")) | |
6805 | (const_int 0))) | |
6806 | (clobber (match_scratch:DI 4 ""))] | |
6807 | "TARGET_POWERPC64 && reload_completed | |
6808 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6809 | [(set (match_dup 4) | |
6810 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6811 | (match_dup 3))) | |
6812 | (set (match_dup 0) | |
6813 | (compare:CC (match_dup 4) | |
6814 | (const_int 0)))] | |
6815 | "") | |
6816 | ||
6817 | (define_insn "*ashldi3_internal9" | |
6818 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6819 | (compare:CC | |
6820 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6821 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6822 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6823 | (const_int 0))) |
6824 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6825 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6826 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6827 | "@ | |
6828 | rldicr. %0,%1,%H2,%S3 | |
6829 | #" | |
6830 | [(set_attr "type" "delayed_compare") | |
6831 | (set_attr "length" "4,8")]) | |
6832 | ||
6833 | (define_split | |
6834 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6835 | (compare:CC | |
6836 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6837 | (match_operand:SI 2 "const_int_operand" "")) | |
6838 | (match_operand:DI 3 "mask64_operand" "")) | |
6839 | (const_int 0))) | |
6840 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6841 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6842 | "TARGET_POWERPC64 && reload_completed | |
6843 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6844 | [(set (match_dup 0) |
e2c953b6 DE |
6845 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6846 | (match_dup 3))) | |
9ebbca7d GK |
6847 | (set (match_dup 4) |
6848 | (compare:CC (match_dup 0) | |
6849 | (const_int 0)))] | |
6850 | "") | |
6851 | ||
6852 | (define_expand "lshrdi3" | |
266eb58a DE |
6853 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6854 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6855 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6856 | "TARGET_POWERPC64 || TARGET_POWER" | |
6857 | " | |
6858 | { | |
6859 | if (TARGET_POWERPC64) | |
6860 | ; | |
6861 | else if (TARGET_POWER) | |
6862 | { | |
6863 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6864 | DONE; | |
6865 | } | |
6866 | else | |
6867 | FAIL; | |
6868 | }") | |
6869 | ||
e2c953b6 | 6870 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6871 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6872 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6873 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6874 | "TARGET_POWERPC64" | |
a66078ee | 6875 | "srd%I2 %0,%1,%H2") |
266eb58a | 6876 | |
e2c953b6 | 6877 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6878 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6879 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6880 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6881 | (const_int 0))) |
9ebbca7d | 6882 | (clobber (match_scratch:DI 3 "=r,r"))] |
29ae5b89 | 6883 | "TARGET_POWERPC64" |
9ebbca7d GK |
6884 | "@ |
6885 | srd%I2. %3,%1,%H2 | |
6886 | #" | |
6887 | [(set_attr "type" "delayed_compare") | |
6888 | (set_attr "length" "4,8")]) | |
6889 | ||
6890 | (define_split | |
6891 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6892 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6893 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6894 | (const_int 0))) | |
6895 | (clobber (match_scratch:DI 3 ""))] | |
6896 | "TARGET_POWERPC64 && reload_completed" | |
6897 | [(set (match_dup 3) | |
6898 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6899 | (set (match_dup 0) | |
6900 | (compare:CC (match_dup 3) | |
6901 | (const_int 0)))] | |
6902 | "") | |
266eb58a | 6903 | |
e2c953b6 | 6904 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6905 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6906 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6907 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6908 | (const_int 0))) |
9ebbca7d | 6909 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 JL |
6910 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
6911 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6912 | "@ |
6913 | srd%I2. %0,%1,%H2 | |
6914 | #" | |
6915 | [(set_attr "type" "delayed_compare") | |
6916 | (set_attr "length" "4,8")]) | |
6917 | ||
6918 | (define_split | |
6919 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6920 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6921 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6922 | (const_int 0))) | |
6923 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6924 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6925 | "TARGET_POWERPC64 && reload_completed" | |
6926 | [(set (match_dup 0) | |
6927 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6928 | (set (match_dup 3) | |
6929 | (compare:CC (match_dup 0) | |
6930 | (const_int 0)))] | |
6931 | "") | |
266eb58a DE |
6932 | |
6933 | (define_expand "ashrdi3" | |
6934 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6935 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6936 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4aa74a4f | 6937 | "" |
266eb58a DE |
6938 | " |
6939 | { | |
6940 | if (TARGET_POWERPC64) | |
6941 | ; | |
6942 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6943 | { | |
6944 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6945 | DONE; | |
6946 | } | |
4aa74a4f FS |
6947 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT) |
6948 | { | |
6949 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
6950 | DONE; | |
6951 | } | |
266eb58a DE |
6952 | else |
6953 | FAIL; | |
6954 | }") | |
6955 | ||
e2c953b6 | 6956 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
6957 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6958 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6959 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6960 | "TARGET_POWERPC64" | |
375490e0 | 6961 | "srad%I2 %0,%1,%H2") |
266eb58a | 6962 | |
e2c953b6 | 6963 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
6964 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6965 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6966 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6967 | (const_int 0))) |
9ebbca7d | 6968 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6969 | "TARGET_POWERPC64" |
9ebbca7d GK |
6970 | "@ |
6971 | srad%I2. %3,%1,%H2 | |
6972 | #" | |
6973 | [(set_attr "type" "delayed_compare") | |
6974 | (set_attr "length" "4,8")]) | |
6975 | ||
6976 | (define_split | |
6977 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6978 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6979 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6980 | (const_int 0))) | |
6981 | (clobber (match_scratch:DI 3 ""))] | |
6982 | "TARGET_POWERPC64 && reload_completed" | |
6983 | [(set (match_dup 3) | |
6984 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6985 | (set (match_dup 0) | |
6986 | (compare:CC (match_dup 3) | |
6987 | (const_int 0)))] | |
6988 | "") | |
266eb58a | 6989 | |
e2c953b6 | 6990 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
6991 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6992 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6993 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6994 | (const_int 0))) |
9ebbca7d | 6995 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6996 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6997 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6998 | "@ |
6999 | srad%I2. %0,%1,%H2 | |
7000 | #" | |
7001 | [(set_attr "type" "delayed_compare") | |
7002 | (set_attr "length" "4,8")]) | |
7003 | ||
7004 | (define_split | |
7005 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7006 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7007 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7008 | (const_int 0))) | |
7009 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7010 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7011 | "TARGET_POWERPC64 && reload_completed" | |
7012 | [(set (match_dup 0) | |
7013 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7014 | (set (match_dup 3) | |
7015 | (compare:CC (match_dup 0) | |
7016 | (const_int 0)))] | |
7017 | "") | |
815cdc52 | 7018 | |
29ae5b89 | 7019 | (define_insn "anddi3" |
0ba1b2ff AM |
7020 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") |
7021 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
7022 | (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t"))) | |
7023 | (clobber (match_scratch:CC 3 "=X,X,x,x,X"))] | |
6ffc8580 | 7024 | "TARGET_POWERPC64" |
266eb58a DE |
7025 | "@ |
7026 | and %0,%1,%2 | |
29ae5b89 JL |
7027 | rldic%B2 %0,%1,0,%S2 |
7028 | andi. %0,%1,%b2 | |
0ba1b2ff AM |
7029 | andis. %0,%1,%u2 |
7030 | #" | |
7031 | [(set_attr "length" "4,4,4,4,8")]) | |
7032 | ||
7033 | (define_split | |
7034 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7035 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7036 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
7037 | (clobber (match_scratch:CC 3 ""))] | |
7038 | "TARGET_POWERPC64 | |
7039 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7040 | && !mask64_operand (operands[2], DImode)" | |
7041 | [(set (match_dup 0) | |
7042 | (and:DI (rotate:DI (match_dup 1) | |
7043 | (match_dup 4)) | |
7044 | (match_dup 5))) | |
7045 | (set (match_dup 0) | |
7046 | (and:DI (rotate:DI (match_dup 0) | |
7047 | (match_dup 6)) | |
7048 | (match_dup 7)))] | |
7049 | " | |
7050 | { | |
7051 | build_mask64_2_operands (operands[2], &operands[4]); | |
7052 | }") | |
266eb58a | 7053 | |
a260abc9 | 7054 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
7055 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7056 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7057 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7058 | (const_int 0))) |
0ba1b2ff AM |
7059 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
7060 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
6ffc8580 | 7061 | "TARGET_POWERPC64" |
266eb58a DE |
7062 | "@ |
7063 | and. %3,%1,%2 | |
6c873122 | 7064 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
7065 | andi. %3,%1,%b2 |
7066 | andis. %3,%1,%u2 | |
9ebbca7d GK |
7067 | # |
7068 | # | |
7069 | # | |
0ba1b2ff AM |
7070 | # |
7071 | # | |
9ebbca7d | 7072 | #" |
0ba1b2ff AM |
7073 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7074 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7075 | |
7076 | (define_split | |
7077 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7078 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7079 | (match_operand:DI 2 "and64_operand" "")) | |
7080 | (const_int 0))) | |
7081 | (clobber (match_scratch:DI 3 "")) | |
7082 | (clobber (match_scratch:CC 4 ""))] | |
7083 | "TARGET_POWERPC64 && reload_completed" | |
7084 | [(parallel [(set (match_dup 3) | |
7085 | (and:DI (match_dup 1) | |
7086 | (match_dup 2))) | |
7087 | (clobber (match_dup 4))]) | |
7088 | (set (match_dup 0) | |
7089 | (compare:CC (match_dup 3) | |
7090 | (const_int 0)))] | |
7091 | "") | |
266eb58a | 7092 | |
0ba1b2ff AM |
7093 | (define_split |
7094 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
7095 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7096 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7097 | (const_int 0))) | |
7098 | (clobber (match_scratch:DI 3 "")) | |
7099 | (clobber (match_scratch:CC 4 ""))] | |
7100 | "TARGET_POWERPC64 && reload_completed | |
7101 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7102 | && !mask64_operand (operands[2], DImode)" | |
7103 | [(set (match_dup 3) | |
7104 | (and:DI (rotate:DI (match_dup 1) | |
7105 | (match_dup 5)) | |
7106 | (match_dup 6))) | |
7107 | (parallel [(set (match_dup 0) | |
7108 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
7109 | (match_dup 7)) | |
7110 | (match_dup 8)) | |
7111 | (const_int 0))) | |
7112 | (clobber (match_dup 3))])] | |
7113 | " | |
7114 | { | |
7115 | build_mask64_2_operands (operands[2], &operands[5]); | |
7116 | }") | |
7117 | ||
a260abc9 | 7118 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
7119 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7120 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7121 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7122 | (const_int 0))) |
0ba1b2ff | 7123 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 7124 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 7125 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
6ffc8580 | 7126 | "TARGET_POWERPC64" |
266eb58a DE |
7127 | "@ |
7128 | and. %0,%1,%2 | |
6c873122 | 7129 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7130 | andi. %0,%1,%b2 |
7131 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7132 | # |
7133 | # | |
7134 | # | |
0ba1b2ff AM |
7135 | # |
7136 | # | |
9ebbca7d | 7137 | #" |
0ba1b2ff AM |
7138 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7139 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7140 | |
7141 | (define_split | |
7142 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7143 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7144 | (match_operand:DI 2 "and64_operand" "")) | |
7145 | (const_int 0))) | |
7146 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7147 | (and:DI (match_dup 1) (match_dup 2))) | |
7148 | (clobber (match_scratch:CC 4 ""))] | |
7149 | "TARGET_POWERPC64 && reload_completed" | |
7150 | [(parallel [(set (match_dup 0) | |
7151 | (and:DI (match_dup 1) (match_dup 2))) | |
7152 | (clobber (match_dup 4))]) | |
7153 | (set (match_dup 3) | |
7154 | (compare:CC (match_dup 0) | |
7155 | (const_int 0)))] | |
7156 | "") | |
266eb58a | 7157 | |
0ba1b2ff AM |
7158 | (define_split |
7159 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
7160 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7161 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7162 | (const_int 0))) | |
7163 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7164 | (and:DI (match_dup 1) (match_dup 2))) | |
7165 | (clobber (match_scratch:CC 4 ""))] | |
7166 | "TARGET_POWERPC64 && reload_completed | |
7167 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7168 | && !mask64_operand (operands[2], DImode)" | |
7169 | [(set (match_dup 0) | |
7170 | (and:DI (rotate:DI (match_dup 1) | |
7171 | (match_dup 5)) | |
7172 | (match_dup 6))) | |
7173 | (parallel [(set (match_dup 3) | |
7174 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
7175 | (match_dup 7)) | |
7176 | (match_dup 8)) | |
7177 | (const_int 0))) | |
7178 | (set (match_dup 0) | |
7179 | (and:DI (rotate:DI (match_dup 0) | |
7180 | (match_dup 7)) | |
7181 | (match_dup 8)))])] | |
7182 | " | |
7183 | { | |
7184 | build_mask64_2_operands (operands[2], &operands[5]); | |
7185 | }") | |
7186 | ||
a260abc9 | 7187 | (define_expand "iordi3" |
266eb58a | 7188 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7189 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7190 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7191 | "TARGET_POWERPC64" |
266eb58a DE |
7192 | " |
7193 | { | |
dfbdccdb | 7194 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7195 | { |
dfbdccdb | 7196 | HOST_WIDE_INT value; |
677a9668 | 7197 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7198 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7199 | |
dfbdccdb GK |
7200 | if (GET_CODE (operands[2]) == CONST_INT) |
7201 | { | |
7202 | value = INTVAL (operands[2]); | |
7203 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7204 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7205 | } | |
e2c953b6 | 7206 | else |
dfbdccdb GK |
7207 | { |
7208 | value = CONST_DOUBLE_LOW (operands[2]); | |
7209 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7210 | immed_double_const (value | |
7211 | & (~ (HOST_WIDE_INT) 0xffff), | |
7212 | 0, DImode))); | |
7213 | } | |
e2c953b6 | 7214 | |
9ebbca7d GK |
7215 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7216 | DONE; | |
7217 | } | |
266eb58a DE |
7218 | }") |
7219 | ||
a260abc9 DE |
7220 | (define_expand "xordi3" |
7221 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7222 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7223 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7224 | "TARGET_POWERPC64" |
7225 | " | |
7226 | { | |
dfbdccdb | 7227 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7228 | { |
dfbdccdb | 7229 | HOST_WIDE_INT value; |
677a9668 | 7230 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7231 | ? operands[0] : gen_reg_rtx (DImode)); |
7232 | ||
dfbdccdb GK |
7233 | if (GET_CODE (operands[2]) == CONST_INT) |
7234 | { | |
7235 | value = INTVAL (operands[2]); | |
7236 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7237 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7238 | } | |
e2c953b6 | 7239 | else |
dfbdccdb GK |
7240 | { |
7241 | value = CONST_DOUBLE_LOW (operands[2]); | |
7242 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7243 | immed_double_const (value | |
7244 | & (~ (HOST_WIDE_INT) 0xffff), | |
7245 | 0, DImode))); | |
7246 | } | |
e2c953b6 | 7247 | |
9ebbca7d GK |
7248 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7249 | DONE; | |
7250 | } | |
a260abc9 DE |
7251 | }") |
7252 | ||
dfbdccdb | 7253 | (define_insn "*booldi3_internal1" |
266eb58a | 7254 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7255 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7256 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7257 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7258 | "TARGET_POWERPC64" |
1fd4e8c1 | 7259 | "@ |
dfbdccdb GK |
7260 | %q3 %0,%1,%2 |
7261 | %q3i %0,%1,%b2 | |
7262 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7263 | |
dfbdccdb | 7264 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7265 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7266 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7267 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7268 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7269 | (const_int 0))) | |
9ebbca7d | 7270 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7271 | "TARGET_POWERPC64" |
9ebbca7d | 7272 | "@ |
dfbdccdb | 7273 | %q4. %3,%1,%2 |
9ebbca7d GK |
7274 | #" |
7275 | [(set_attr "type" "compare") | |
7276 | (set_attr "length" "4,8")]) | |
7277 | ||
7278 | (define_split | |
7279 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7280 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7281 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7282 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7283 | (const_int 0))) |
9ebbca7d GK |
7284 | (clobber (match_scratch:DI 3 ""))] |
7285 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7286 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7287 | (set (match_dup 0) |
7288 | (compare:CC (match_dup 3) | |
7289 | (const_int 0)))] | |
7290 | "") | |
1fd4e8c1 | 7291 | |
dfbdccdb | 7292 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7293 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7294 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7295 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7296 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7297 | (const_int 0))) | |
9ebbca7d | 7298 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7299 | (match_dup 4))] |
266eb58a | 7300 | "TARGET_POWERPC64" |
9ebbca7d | 7301 | "@ |
dfbdccdb | 7302 | %q4. %0,%1,%2 |
9ebbca7d GK |
7303 | #" |
7304 | [(set_attr "type" "compare") | |
7305 | (set_attr "length" "4,8")]) | |
7306 | ||
7307 | (define_split | |
e72247f4 | 7308 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7309 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7310 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7311 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7312 | (const_int 0))) |
75540af0 | 7313 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7314 | (match_dup 4))] |
9ebbca7d | 7315 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7316 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7317 | (set (match_dup 3) |
7318 | (compare:CC (match_dup 0) | |
7319 | (const_int 0)))] | |
7320 | "") | |
1fd4e8c1 | 7321 | |
5bdc5878 | 7322 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 7323 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
7324 | |
7325 | (define_split | |
7326 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7327 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7328 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7329 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7330 | "TARGET_POWERPC64" |
dfbdccdb GK |
7331 | [(set (match_dup 0) (match_dup 4)) |
7332 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7333 | " |
7334 | { | |
dfbdccdb GK |
7335 | rtx i3,i4; |
7336 | ||
9ebbca7d GK |
7337 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7338 | { | |
7339 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7340 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7341 | 0, DImode); |
dfbdccdb | 7342 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7343 | } |
7344 | else | |
7345 | { | |
dfbdccdb | 7346 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7347 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7348 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7349 | } |
dfbdccdb GK |
7350 | operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, |
7351 | operands[1], i3); | |
7352 | operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, | |
7353 | operands[0], i4); | |
1fd4e8c1 RK |
7354 | }") |
7355 | ||
dfbdccdb | 7356 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7357 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7358 | (match_operator:DI 3 "boolean_operator" |
7359 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7360 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7361 | "TARGET_POWERPC64" |
1d328b19 | 7362 | "%q3 %0,%2,%1") |
a473029f | 7363 | |
dfbdccdb | 7364 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7365 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7366 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7367 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7368 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7369 | (const_int 0))) | |
9ebbca7d | 7370 | (clobber (match_scratch:DI 3 "=r,r"))] |
a473029f | 7371 | "TARGET_POWERPC64" |
9ebbca7d | 7372 | "@ |
1d328b19 | 7373 | %q4. %3,%2,%1 |
9ebbca7d GK |
7374 | #" |
7375 | [(set_attr "type" "compare") | |
7376 | (set_attr "length" "4,8")]) | |
7377 | ||
7378 | (define_split | |
7379 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7380 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7381 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7382 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7383 | (const_int 0))) |
9ebbca7d GK |
7384 | (clobber (match_scratch:DI 3 ""))] |
7385 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7386 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7387 | (set (match_dup 0) |
7388 | (compare:CC (match_dup 3) | |
7389 | (const_int 0)))] | |
7390 | "") | |
a473029f | 7391 | |
dfbdccdb | 7392 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7393 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7394 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7395 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7396 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7397 | (const_int 0))) | |
9ebbca7d | 7398 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7399 | (match_dup 4))] |
a473029f | 7400 | "TARGET_POWERPC64" |
9ebbca7d | 7401 | "@ |
1d328b19 | 7402 | %q4. %0,%2,%1 |
9ebbca7d GK |
7403 | #" |
7404 | [(set_attr "type" "compare") | |
7405 | (set_attr "length" "4,8")]) | |
7406 | ||
7407 | (define_split | |
e72247f4 | 7408 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7409 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7410 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7411 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7412 | (const_int 0))) |
75540af0 | 7413 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7414 | (match_dup 4))] |
9ebbca7d | 7415 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7416 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7417 | (set (match_dup 3) |
7418 | (compare:CC (match_dup 0) | |
7419 | (const_int 0)))] | |
7420 | "") | |
266eb58a | 7421 | |
dfbdccdb | 7422 | (define_insn "*boolccdi3_internal1" |
a473029f | 7423 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7424 | (match_operator:DI 3 "boolean_operator" |
7425 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7426 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7427 | "TARGET_POWERPC64" |
dfbdccdb | 7428 | "%q3 %0,%1,%2") |
a473029f | 7429 | |
dfbdccdb | 7430 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7431 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7432 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7433 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7434 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7435 | (const_int 0))) | |
9ebbca7d | 7436 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7437 | "TARGET_POWERPC64" |
9ebbca7d | 7438 | "@ |
dfbdccdb | 7439 | %q4. %3,%1,%2 |
9ebbca7d GK |
7440 | #" |
7441 | [(set_attr "type" "compare") | |
7442 | (set_attr "length" "4,8")]) | |
7443 | ||
7444 | (define_split | |
7445 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7446 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7447 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7448 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7449 | (const_int 0))) |
9ebbca7d GK |
7450 | (clobber (match_scratch:DI 3 ""))] |
7451 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7452 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7453 | (set (match_dup 0) |
7454 | (compare:CC (match_dup 3) | |
7455 | (const_int 0)))] | |
7456 | "") | |
266eb58a | 7457 | |
dfbdccdb | 7458 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7459 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7460 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7461 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7462 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7463 | (const_int 0))) | |
9ebbca7d | 7464 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7465 | (match_dup 4))] |
29ae5b89 | 7466 | "TARGET_POWERPC64" |
9ebbca7d | 7467 | "@ |
dfbdccdb | 7468 | %q4. %0,%1,%2 |
9ebbca7d GK |
7469 | #" |
7470 | [(set_attr "type" "compare") | |
7471 | (set_attr "length" "4,8")]) | |
7472 | ||
7473 | (define_split | |
e72247f4 | 7474 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7475 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7476 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7477 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7478 | (const_int 0))) |
75540af0 | 7479 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7480 | (match_dup 4))] |
9ebbca7d | 7481 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7482 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7483 | (set (match_dup 3) |
7484 | (compare:CC (match_dup 0) | |
7485 | (const_int 0)))] | |
7486 | "") | |
dfbdccdb | 7487 | \f |
1fd4e8c1 | 7488 | ;; Now define ways of moving data around. |
4697a36c MM |
7489 | |
7490 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7491 | ;; The output of this could be r0, but we make a very strong |
7492 | ;; preference for a base register because it will usually | |
7493 | ;; be needed there. | |
4697a36c | 7494 | (define_insn "elf_high" |
9ebbca7d | 7495 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7496 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7497 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7498 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7499 | |
7500 | (define_insn "elf_low" | |
9ebbca7d GK |
7501 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7502 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7503 | (match_operand 2 "" "")))] |
0ad91047 | 7504 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7505 | "@ |
7506 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7507 | {ai|addic} %0,%1,%K2") |
4697a36c | 7508 | |
ee890fe2 SS |
7509 | ;; Mach-O PIC trickery. |
7510 | (define_insn "macho_high" | |
7511 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
7512 | (high:SI (match_operand 1 "" "")))] | |
7513 | "TARGET_MACHO && ! TARGET_64BIT" | |
7514 | "{liu|lis} %0,ha16(%1)") | |
7515 | ||
7516 | (define_insn "macho_low" | |
7517 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
7518 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
7519 | (match_operand 2 "" "")))] | |
7520 | "TARGET_MACHO && ! TARGET_64BIT" | |
7521 | "@ | |
7522 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
7523 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
7524 | ||
766a866c MM |
7525 | ;; Set up a register with a value from the GOT table |
7526 | ||
7527 | (define_expand "movsi_got" | |
52d3af72 | 7528 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7529 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
615158e2 | 7530 | (match_dup 2)] UNSPEC_MOVSI_GOT))] |
f607bc57 | 7531 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7532 | " |
7533 | { | |
38c1f2d7 MM |
7534 | if (GET_CODE (operands[1]) == CONST) |
7535 | { | |
7536 | rtx offset = const0_rtx; | |
7537 | HOST_WIDE_INT value; | |
7538 | ||
7539 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7540 | value = INTVAL (offset); | |
7541 | if (value != 0) | |
7542 | { | |
677a9668 | 7543 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7544 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7545 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7546 | DONE; | |
7547 | } | |
7548 | } | |
7549 | ||
c4c40373 | 7550 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7551 | }") |
7552 | ||
84f414bc | 7553 | (define_insn "*movsi_got_internal" |
52d3af72 | 7554 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d | 7555 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7556 | (match_operand:SI 2 "gpc_reg_operand" "b")] |
7557 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7558 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7559 | "{l|lwz} %0,%a1@got(%2)" |
7560 | [(set_attr "type" "load")]) | |
7561 | ||
b22b9b3e JL |
7562 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7563 | ;; didn't get allocated to a hard register. | |
7564 | (define_split | |
75540af0 | 7565 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7566 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7567 | (match_operand:SI 2 "memory_operand" "")] |
7568 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7569 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7570 | && flag_pic == 1 |
7571 | && (reload_in_progress || reload_completed)" | |
7572 | [(set (match_dup 0) (match_dup 2)) | |
615158e2 JJ |
7573 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] |
7574 | UNSPEC_MOVSI_GOT))] | |
b22b9b3e JL |
7575 | "") |
7576 | ||
1fd4e8c1 RK |
7577 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7578 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7579 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7580 | ;; integers in the TOC. | |
7581 | (define_expand "movsi" | |
7582 | [(set (match_operand:SI 0 "general_operand" "") | |
7583 | (match_operand:SI 1 "any_operand" ""))] | |
7584 | "" | |
fb4d4348 | 7585 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7586 | |
ee890fe2 SS |
7587 | (define_insn "movsi_low" |
7588 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7589 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7590 | (match_operand 2 "" ""))))] |
7591 | "TARGET_MACHO && ! TARGET_64BIT" | |
7592 | "{l|lwz} %0,lo16(%2)(%1)" | |
7593 | [(set_attr "type" "load") | |
7594 | (set_attr "length" "4")]) | |
7595 | ||
c859cda6 | 7596 | (define_insn "movsi_low_st" |
f585a356 | 7597 | [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7598 | (match_operand 2 "" ""))) |
7599 | (match_operand:SI 0 "gpc_reg_operand" "r"))] | |
7600 | "TARGET_MACHO && ! TARGET_64BIT" | |
7601 | "{st|stw} %0,lo16(%2)(%1)" | |
7602 | [(set_attr "type" "store") | |
7603 | (set_attr "length" "4")]) | |
7604 | ||
7605 | (define_insn "movdf_low" | |
234e114c | 7606 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7607 | (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7608 | (match_operand 2 "" ""))))] |
a3170dc6 | 7609 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
234e114c DJ |
7610 | "* |
7611 | { | |
7612 | switch (which_alternative) | |
7613 | { | |
7614 | case 0: | |
7615 | return \"lfd %0,lo16(%2)(%1)\"; | |
7616 | case 1: | |
7617 | { | |
7618 | rtx operands2[4]; | |
7619 | operands2[0] = operands[0]; | |
7620 | operands2[1] = operands[1]; | |
7621 | operands2[2] = operands[2]; | |
1db02437 | 7622 | operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
234e114c | 7623 | output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); |
ab82a49f AP |
7624 | #if TARGET_MACHO |
7625 | if (MACHO_DYNAMIC_NO_PIC_P) | |
7626 | output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands); | |
7627 | else | |
234e114c DJ |
7628 | /* We cannot rely on ha16(low half)==ha16(high half), alas, |
7629 | although in practice it almost always is. */ | |
7630 | output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); | |
ab82a49f | 7631 | #endif |
234e114c DJ |
7632 | return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); |
7633 | } | |
7634 | default: | |
7635 | abort(); | |
7636 | } | |
7637 | }" | |
c859cda6 | 7638 | [(set_attr "type" "load") |
234e114c | 7639 | (set_attr "length" "4,12")]) |
c859cda6 DJ |
7640 | |
7641 | (define_insn "movdf_low_st" | |
f585a356 | 7642 | [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7643 | (match_operand 2 "" ""))) |
7644 | (match_operand:DF 0 "gpc_reg_operand" "f"))] | |
a3170dc6 | 7645 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
c859cda6 DJ |
7646 | "stfd %0,lo16(%2)(%1)" |
7647 | [(set_attr "type" "store") | |
7648 | (set_attr "length" "4")]) | |
7649 | ||
7650 | (define_insn "movsf_low" | |
fd3b43f2 | 7651 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7652 | (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7653 | (match_operand 2 "" ""))))] |
a3170dc6 | 7654 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
fd3b43f2 DJ |
7655 | "@ |
7656 | lfs %0,lo16(%2)(%1) | |
7657 | {l|lwz} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
7658 | [(set_attr "type" "load") |
7659 | (set_attr "length" "4")]) | |
7660 | ||
7661 | (define_insn "movsf_low_st" | |
f585a356 | 7662 | [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7663 | (match_operand 2 "" ""))) |
fd3b43f2 | 7664 | (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] |
a3170dc6 | 7665 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
fd3b43f2 DJ |
7666 | "@ |
7667 | stfs %0,lo16(%2)(%1) | |
7668 | {st|stw} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
7669 | [(set_attr "type" "store") |
7670 | (set_attr "length" "4")]) | |
7671 | ||
acad7ed3 | 7672 | (define_insn "*movsi_internal1" |
a004eb82 AH |
7673 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
7674 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] | |
19d5775a RK |
7675 | "gpc_reg_operand (operands[0], SImode) |
7676 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7677 | "@ |
deb9225a | 7678 | mr %0,%1 |
b9442c72 | 7679 | {cal|la} %0,%a1 |
ca7f5001 RK |
7680 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7681 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7682 | {lil|li} %0,%1 |
802a0058 | 7683 | {liu|lis} %0,%v1 |
beaec479 | 7684 | # |
aee86b38 | 7685 | {cal|la} %0,%a1 |
1fd4e8c1 | 7686 | mf%1 %0 |
5c23c401 | 7687 | mt%0 %1 |
e76e75bb | 7688 | mt%0 %1 |
a004eb82 | 7689 | mt%0 %1 |
e34eaae5 | 7690 | {cror 0,0,0|nop}" |
02ca7595 | 7691 | [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") |
a004eb82 | 7692 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7693 | |
77fa0940 RK |
7694 | ;; Split a load of a large constant into the appropriate two-insn |
7695 | ;; sequence. | |
7696 | ||
7697 | (define_split | |
7698 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7699 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7700 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7701 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7702 | [(set (match_dup 0) | |
7703 | (match_dup 2)) | |
7704 | (set (match_dup 0) | |
7705 | (ior:SI (match_dup 0) | |
7706 | (match_dup 3)))] | |
7707 | " | |
af8cb5c5 DE |
7708 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
7709 | ||
7710 | if (tem == operands[0]) | |
7711 | DONE; | |
7712 | else | |
7713 | FAIL; | |
77fa0940 RK |
7714 | }") |
7715 | ||
acad7ed3 | 7716 | (define_insn "*movsi_internal2" |
bb84cb12 DE |
7717 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
7718 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r") | |
1fd4e8c1 | 7719 | (const_int 0))) |
bb84cb12 | 7720 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
0ad91047 | 7721 | "! TARGET_POWERPC64" |
9ebbca7d | 7722 | "@ |
bb84cb12 | 7723 | {cmpi|cmpwi} %2,%0,0 |
9ebbca7d GK |
7724 | mr. %0,%1 |
7725 | #" | |
bb84cb12 DE |
7726 | [(set_attr "type" "cmp,compare,cmp") |
7727 | (set_attr "length" "4,4,8")]) | |
7728 | ||
9ebbca7d GK |
7729 | (define_split |
7730 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7731 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7732 | (const_int 0))) | |
7733 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
7734 | "! TARGET_POWERPC64 && reload_completed" | |
7735 | [(set (match_dup 0) (match_dup 1)) | |
7736 | (set (match_dup 2) | |
7737 | (compare:CC (match_dup 0) | |
7738 | (const_int 0)))] | |
7739 | "") | |
bb84cb12 | 7740 | \f |
1fd4e8c1 RK |
7741 | (define_expand "movhi" |
7742 | [(set (match_operand:HI 0 "general_operand" "") | |
7743 | (match_operand:HI 1 "any_operand" ""))] | |
7744 | "" | |
fb4d4348 | 7745 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 | 7746 | |
e34eaae5 | 7747 | (define_insn "*movhi_internal" |
fb81d7ce RK |
7748 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7749 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7750 | "gpc_reg_operand (operands[0], HImode) |
7751 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7752 | "@ |
deb9225a | 7753 | mr %0,%1 |
1fd4e8c1 RK |
7754 | lhz%U1%X1 %0,%1 |
7755 | sth%U0%X0 %1,%0 | |
19d5775a | 7756 | {lil|li} %0,%w1 |
1fd4e8c1 | 7757 | mf%1 %0 |
e76e75bb | 7758 | mt%0 %1 |
fb81d7ce | 7759 | mt%0 %1 |
e34eaae5 | 7760 | {cror 0,0,0|nop}" |
02ca7595 | 7761 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7762 | |
7763 | (define_expand "movqi" | |
7764 | [(set (match_operand:QI 0 "general_operand" "") | |
7765 | (match_operand:QI 1 "any_operand" ""))] | |
7766 | "" | |
fb4d4348 | 7767 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 | 7768 | |
e34eaae5 | 7769 | (define_insn "*movqi_internal" |
fb81d7ce RK |
7770 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7771 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7772 | "gpc_reg_operand (operands[0], QImode) |
7773 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7774 | "@ |
deb9225a | 7775 | mr %0,%1 |
1fd4e8c1 RK |
7776 | lbz%U1%X1 %0,%1 |
7777 | stb%U0%X0 %1,%0 | |
19d5775a | 7778 | {lil|li} %0,%1 |
1fd4e8c1 | 7779 | mf%1 %0 |
e76e75bb | 7780 | mt%0 %1 |
fb81d7ce | 7781 | mt%0 %1 |
e34eaae5 | 7782 | {cror 0,0,0|nop}" |
02ca7595 | 7783 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7784 | \f |
7785 | ;; Here is how to move condition codes around. When we store CC data in | |
7786 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7787 | ;; This lets us not shift in the most common case of CR0. | |
7788 | (define_expand "movcc" | |
7789 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7790 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7791 | "" | |
7792 | "") | |
7793 | ||
a65c591c | 7794 | (define_insn "*movcc_internal1" |
b54cf83a DE |
7795 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") |
7796 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] | |
1fd4e8c1 RK |
7797 | "register_operand (operands[0], CCmode) |
7798 | || register_operand (operands[1], CCmode)" | |
7799 | "@ | |
7800 | mcrf %0,%1 | |
7801 | mtcrf 128,%1 | |
ca7f5001 | 7802 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 7803 | mfcr %0 |
ca7f5001 | 7804 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 7805 | mr %0,%1 |
b54cf83a | 7806 | mf%1 %0 |
b991a865 GK |
7807 | mt%0 %1 |
7808 | mt%0 %1 | |
ca7f5001 RK |
7809 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7810 | {st%U0%U1|stw%U0%U1} %1,%0" | |
02ca7595 | 7811 | [(set_attr "type" "cr_logical,mtcr,mtcr,mfcr,mfcr,*,mfjmpr,*,mtjmpr,load,store") |
b991a865 | 7812 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7813 | \f |
e52e05ca MM |
7814 | ;; For floating-point, we normally deal with the floating-point registers |
7815 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7816 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7817 | ;; value is a simple constant or already in memory, we deal with this by | |
7818 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7819 | (define_expand "movsf" |
7820 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7821 | (match_operand:SF 1 "any_operand" ""))] | |
7822 | "" | |
fb4d4348 | 7823 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7824 | |
1fd4e8c1 | 7825 | (define_split |
cd2b37d9 | 7826 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7827 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7828 | "reload_completed |
5ae4759c MM |
7829 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7830 | || (GET_CODE (operands[0]) == SUBREG | |
7831 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7832 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7833 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7834 | " |
7835 | { | |
7836 | long l; | |
7837 | REAL_VALUE_TYPE rv; | |
7838 | ||
7839 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7840 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7841 | |
f99f88e0 DE |
7842 | if (! TARGET_POWERPC64) |
7843 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7844 | else | |
7845 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7846 | |
2496c7bd | 7847 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7848 | }") |
7849 | ||
c4c40373 | 7850 | (define_insn "*movsf_hardfloat" |
b991a865 GK |
7851 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r") |
7852 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))] | |
d14a6d05 | 7853 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7854 | || gpc_reg_operand (operands[1], SFmode)) |
7855 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 7856 | "@ |
f99f88e0 DE |
7857 | mr %0,%1 |
7858 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7859 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7860 | fmr %0,%1 |
7861 | lfs%U1%X1 %0,%1 | |
c4c40373 | 7862 | stfs%U0%X0 %1,%0 |
b991a865 GK |
7863 | mt%0 %1 |
7864 | mt%0 %1 | |
7865 | mf%1 %0 | |
c4c40373 MM |
7866 | # |
7867 | #" | |
b991a865 GK |
7868 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*") |
7869 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7870 | |
c4c40373 | 7871 | (define_insn "*movsf_softfloat" |
dd0fbae2 MK |
7872 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") |
7873 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
d14a6d05 | 7874 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7875 | || gpc_reg_operand (operands[1], SFmode)) |
7876 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
7877 | "@ |
7878 | mr %0,%1 | |
b991a865 GK |
7879 | mt%0 %1 |
7880 | mt%0 %1 | |
7881 | mf%1 %0 | |
d14a6d05 MM |
7882 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7883 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7884 | {lil|li} %0,%1 | |
802a0058 | 7885 | {liu|lis} %0,%v1 |
aee86b38 | 7886 | {cal|la} %0,%a1 |
c4c40373 | 7887 | # |
dd0fbae2 MK |
7888 | # |
7889 | {cror 0,0,0|nop}" | |
7890 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") | |
7891 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
d14a6d05 | 7892 | |
1fd4e8c1 RK |
7893 | \f |
7894 | (define_expand "movdf" | |
7895 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7896 | (match_operand:DF 1 "any_operand" ""))] | |
7897 | "" | |
fb4d4348 | 7898 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7899 | |
7900 | (define_split | |
cd2b37d9 | 7901 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7902 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7903 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7904 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7905 | || (GET_CODE (operands[0]) == SUBREG | |
7906 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7907 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7908 | [(set (match_dup 2) (match_dup 4)) |
7909 | (set (match_dup 3) (match_dup 1))] | |
7910 | " | |
7911 | { | |
5ae4759c | 7912 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7913 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7914 | ||
5ae4759c MM |
7915 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7916 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7917 | #if HOST_BITS_PER_WIDE_INT == 32 |
7918 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7919 | #else | |
7920 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 7921 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 7922 | #endif |
c4c40373 MM |
7923 | }") |
7924 | ||
c4c40373 MM |
7925 | (define_split |
7926 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7927 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7928 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7929 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7930 | || (GET_CODE (operands[0]) == SUBREG | |
7931 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7932 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7933 | [(set (match_dup 2) (match_dup 4)) |
7934 | (set (match_dup 3) (match_dup 5))] | |
7935 | " | |
7936 | { | |
5ae4759c | 7937 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7938 | long l[2]; |
7939 | REAL_VALUE_TYPE rv; | |
7940 | ||
7941 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7942 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7943 | ||
5ae4759c MM |
7944 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7945 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
7946 | operands[4] = gen_int_mode (l[endian], SImode); |
7947 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
7948 | }") |
7949 | ||
efc08378 DE |
7950 | (define_split |
7951 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7952 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7953 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7954 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7955 | || (GET_CODE (operands[0]) == SUBREG | |
7956 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7957 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7958 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7959 | " |
a260abc9 DE |
7960 | { |
7961 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7962 | long l[2]; | |
7963 | REAL_VALUE_TYPE rv; | |
4977bab6 | 7964 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 7965 | HOST_WIDE_INT val; |
4977bab6 | 7966 | #endif |
a260abc9 DE |
7967 | |
7968 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7969 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7970 | ||
7971 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7972 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 7973 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
7974 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
7975 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 7976 | |
f5264b52 | 7977 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 7978 | #else |
a260abc9 | 7979 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 7980 | #endif |
a260abc9 | 7981 | }") |
efc08378 | 7982 | |
4eae5fe1 | 7983 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7984 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7985 | ;; a non-offsettable memref, but also it is less efficient than loading |
7986 | ;; the constant into an FP register, since it will probably be used there. | |
7987 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7988 | ;; of handling these non-offsettable values. | |
c4c40373 | 7989 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
7990 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
7991 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 7992 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
7993 | && (gpc_reg_operand (operands[0], DFmode) |
7994 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7995 | "* |
7996 | { | |
7997 | switch (which_alternative) | |
7998 | { | |
a260abc9 | 7999 | default: |
a6c2a102 | 8000 | abort (); |
e7113111 RK |
8001 | case 0: |
8002 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
8003 | the first register operand 0 is the same as the second register |
8004 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 8005 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 8006 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 8007 | else |
deb9225a | 8008 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 8009 | case 1: |
2b97222d DE |
8010 | if (offsettable_memref_p (operands[1]) |
8011 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
8012 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
8013 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
8014 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
8015 | { |
8016 | /* If the low-address word is used in the address, we must load | |
8017 | it last. Otherwise, load it first. Note that we cannot have | |
8018 | auto-increment in that case since the address register is | |
8019 | known to be dead. */ | |
8020 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8021 | operands[1], 0)) | |
8022 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
8023 | else | |
8024 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8025 | } | |
e7113111 | 8026 | else |
000034eb DE |
8027 | { |
8028 | rtx addreg; | |
8029 | ||
000034eb DE |
8030 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
8031 | if (refers_to_regno_p (REGNO (operands[0]), | |
8032 | REGNO (operands[0]) + 1, | |
8033 | operands[1], 0)) | |
8034 | { | |
8035 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 8036 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 8037 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 8038 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
8039 | } |
8040 | else | |
8041 | { | |
2b97222d | 8042 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 8043 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8044 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
8045 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8046 | return \"\"; | |
8047 | } | |
8048 | } | |
e7113111 | 8049 | case 2: |
2b97222d DE |
8050 | if (offsettable_memref_p (operands[0]) |
8051 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
8052 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
8053 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
8054 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
8055 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8056 | else | |
8057 | { | |
8058 | rtx addreg; | |
8059 | ||
000034eb | 8060 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8061 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8062 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8063 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8064 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8065 | return \"\"; | |
8066 | } | |
e7113111 | 8067 | case 3: |
914a7297 | 8068 | return \"fmr %0,%1\"; |
e7113111 | 8069 | case 4: |
914a7297 | 8070 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 8071 | case 5: |
914a7297 | 8072 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 8073 | case 6: |
c4c40373 | 8074 | case 7: |
c4c40373 | 8075 | case 8: |
914a7297 | 8076 | return \"#\"; |
e7113111 RK |
8077 | } |
8078 | }" | |
914a7297 DE |
8079 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*") |
8080 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) | |
51b8fc2c | 8081 | |
c4c40373 | 8082 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8083 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8084 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
a3170dc6 | 8085 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8086 | && (gpc_reg_operand (operands[0], DFmode) |
8087 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8088 | "* |
8089 | { | |
8090 | switch (which_alternative) | |
8091 | { | |
a260abc9 | 8092 | default: |
a6c2a102 | 8093 | abort (); |
dc4f83ca MM |
8094 | case 0: |
8095 | /* We normally copy the low-numbered register first. However, if | |
8096 | the first register operand 0 is the same as the second register of | |
8097 | operand 1, we must copy in the opposite order. */ | |
8098 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8099 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8100 | else | |
8101 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8102 | case 1: | |
3cb999d8 DE |
8103 | /* If the low-address word is used in the address, we must load |
8104 | it last. Otherwise, load it first. Note that we cannot have | |
8105 | auto-increment in that case since the address register is | |
8106 | known to be dead. */ | |
dc4f83ca | 8107 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8108 | operands[1], 0)) |
dc4f83ca MM |
8109 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8110 | else | |
8111 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8112 | case 2: | |
8113 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8114 | case 3: | |
c4c40373 MM |
8115 | case 4: |
8116 | case 5: | |
dc4f83ca MM |
8117 | return \"#\"; |
8118 | } | |
8119 | }" | |
c4c40373 MM |
8120 | [(set_attr "type" "*,load,store,*,*,*") |
8121 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 8122 | |
c4c40373 | 8123 | (define_insn "*movdf_hardfloat64" |
914a7297 DE |
8124 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r") |
8125 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))] | |
a3170dc6 | 8126 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8127 | && (gpc_reg_operand (operands[0], DFmode) |
8128 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8129 | "@ |
3d5570cb RK |
8130 | mr %0,%1 |
8131 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8132 | std%U0%X0 %1,%0 |
3d5570cb | 8133 | fmr %0,%1 |
f63184ac | 8134 | lfd%U1%X1 %0,%1 |
914a7297 DE |
8135 | stfd%U0%X0 %1,%0 |
8136 | mt%0 %1 | |
8137 | mf%1 %0 | |
8138 | # | |
8139 | # | |
8140 | #" | |
8141 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*") | |
8142 | (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 8143 | |
c4c40373 | 8144 | (define_insn "*movdf_softfloat64" |
914a7297 DE |
8145 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r") |
8146 | (match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F"))] | |
a3170dc6 | 8147 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8148 | && (gpc_reg_operand (operands[0], DFmode) |
8149 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8150 | "@ |
8151 | mr %0,%1 | |
914a7297 DE |
8152 | mt%0 %1 |
8153 | mf%1 %0 | |
dc4f83ca | 8154 | ld%U1%X1 %0,%1 |
96bb8ed3 | 8155 | std%U0%X0 %1,%0 |
c4c40373 MM |
8156 | # |
8157 | # | |
dc4f83ca | 8158 | #" |
914a7297 DE |
8159 | [(set_attr "type" "*,*,*,load,store,*,*,*") |
8160 | (set_attr "length" "4,4,4,4,4,8,12,16")]) | |
1fd4e8c1 | 8161 | \f |
06f4e019 DE |
8162 | (define_expand "movtf" |
8163 | [(set (match_operand:TF 0 "general_operand" "") | |
8164 | (match_operand:TF 1 "any_operand" ""))] | |
a3170dc6 AH |
8165 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8166 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8167 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
8168 | ||
8169 | (define_insn "*movtf_internal" | |
8170 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r") | |
8171 | (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))] | |
a3170dc6 AH |
8172 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8173 | && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
8174 | && (gpc_reg_operand (operands[0], TFmode) |
8175 | || gpc_reg_operand (operands[1], TFmode))" | |
8176 | "* | |
8177 | { | |
8178 | switch (which_alternative) | |
8179 | { | |
8180 | default: | |
8181 | abort (); | |
8182 | case 0: | |
8183 | /* We normally copy the low-numbered register first. However, if | |
8184 | the first register operand 0 is the same as the second register of | |
8185 | operand 1, we must copy in the opposite order. */ | |
8186 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8187 | return \"fmr %L0,%L1\;fmr %0,%1\"; | |
8188 | else | |
8189 | return \"fmr %0,%1\;fmr %L0,%L1\"; | |
8190 | case 1: | |
f5264b52 | 8191 | return \"lfd %0,%1\;lfd %L0,%Y1\"; |
06f4e019 | 8192 | case 2: |
f5264b52 | 8193 | return \"stfd %1,%0\;stfd %L1,%Y0\"; |
06f4e019 DE |
8194 | case 3: |
8195 | case 4: | |
8196 | case 5: | |
8197 | return \"#\"; | |
8198 | } | |
8199 | }" | |
8200 | [(set_attr "type" "fp,fpload,fpstore,*,*,*") | |
8201 | (set_attr "length" "8,8,8,12,16,20")]) | |
8202 | ||
8203 | (define_split | |
8204 | [(set (match_operand:TF 0 "gpc_reg_operand" "") | |
f5264b52 | 8205 | (match_operand:TF 1 "easy_fp_constant" ""))] |
fcce224d DE |
8206 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8207 | && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_POWERPC64 | |
8208 | && TARGET_LONG_DOUBLE_128 && reload_completed | |
8209 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) | |
8210 | || (GET_CODE (operands[0]) == SUBREG | |
8211 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8212 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
8213 | [(set (match_dup 2) (match_dup 6)) | |
8214 | (set (match_dup 3) (match_dup 7)) | |
8215 | (set (match_dup 4) (match_dup 8)) | |
8216 | (set (match_dup 5) (match_dup 9))] | |
8217 | " | |
8218 | { | |
8219 | long l[4]; | |
8220 | REAL_VALUE_TYPE rv; | |
8221 | ||
8222 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8223 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l); | |
8224 | ||
8225 | operands[2] = operand_subword (operands[0], 0, 0, TFmode); | |
8226 | operands[3] = operand_subword (operands[0], 1, 0, TFmode); | |
8227 | operands[4] = operand_subword (operands[0], 2, 0, TFmode); | |
8228 | operands[5] = operand_subword (operands[0], 3, 0, TFmode); | |
8229 | operands[6] = gen_int_mode (l[0], SImode); | |
8230 | operands[7] = gen_int_mode (l[1], SImode); | |
8231 | operands[8] = gen_int_mode (l[2], SImode); | |
8232 | operands[9] = gen_int_mode (l[3], SImode); | |
8233 | }") | |
8234 | ||
8235 | (define_split | |
8236 | [(set (match_operand:TF 0 "gpc_reg_operand" "") | |
8237 | (match_operand:TF 1 "easy_fp_constant" ""))] | |
8238 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8239 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 | |
8240 | && TARGET_LONG_DOUBLE_128 && reload_completed | |
8241 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) | |
8242 | || (GET_CODE (operands[0]) == SUBREG | |
8243 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8244 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
8245 | [(set (match_dup 2) (match_dup 4)) | |
8246 | (set (match_dup 3) (match_dup 5))] | |
06f4e019 DE |
8247 | " |
8248 | { | |
fcce224d DE |
8249 | long l[4]; |
8250 | REAL_VALUE_TYPE rv; | |
d24652ee | 8251 | #if HOST_BITS_PER_WIDE_INT >= 64 |
f5264b52 | 8252 | HOST_WIDE_INT val; |
d24652ee | 8253 | #endif |
fcce224d DE |
8254 | |
8255 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8256 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l); | |
8257 | ||
f5264b52 DE |
8258 | operands[2] = gen_lowpart (DImode, operands[0]); |
8259 | operands[3] = gen_highpart (DImode, operands[0]); | |
8260 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
a2419b96 DE |
8261 | val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32 |
8262 | | ((HOST_WIDE_INT)(unsigned long)l[1])); | |
f5264b52 DE |
8263 | operands[4] = gen_int_mode (val, DImode); |
8264 | ||
a2419b96 DE |
8265 | val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32 |
8266 | | ((HOST_WIDE_INT)(unsigned long)l[3])); | |
f5264b52 DE |
8267 | operands[5] = gen_int_mode (val, DImode); |
8268 | #else | |
8269 | operands[4] = immed_double_const (l[1], l[0], DImode); | |
8270 | operands[5] = immed_double_const (l[3], l[2], DImode); | |
8271 | #endif | |
06f4e019 DE |
8272 | }") |
8273 | ||
a2419b96 | 8274 | (define_insn "extenddftf2" |
06f4e019 DE |
8275 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8276 | (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8277 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8278 | && TARGET_LONG_DOUBLE_128" | |
a2419b96 | 8279 | "* |
06f4e019 | 8280 | { |
a2419b96 DE |
8281 | if (REGNO (operands[0]) == REGNO (operands[1])) |
8282 | return \"fsub %L0,%L0,%L0\"; | |
8283 | else | |
8284 | return \"fmr %0,%1\;fsub %L0,%L0,%L0\"; | |
8285 | }" | |
8286 | [(set_attr "type" "fp")]) | |
06f4e019 | 8287 | |
a2419b96 | 8288 | (define_insn "extendsftf2" |
06f4e019 DE |
8289 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8290 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8291 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8292 | && TARGET_LONG_DOUBLE_128" | |
a2419b96 | 8293 | "* |
06f4e019 | 8294 | { |
a2419b96 DE |
8295 | if (REGNO (operands[0]) == REGNO (operands[1])) |
8296 | return \"fsub %L0,%L0,%L0\"; | |
8297 | else | |
8298 | return \"fmr %0,%1\;fsub %L0,%L0,%L0\"; | |
8299 | }" | |
8300 | [(set_attr "type" "fp")]) | |
06f4e019 DE |
8301 | |
8302 | (define_insn "trunctfdf2" | |
8303 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8304 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8305 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8306 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8307 | "fadd %0,%1,%L1" |
8308 | [(set_attr "type" "fp") | |
8309 | (set_attr "length" "8")]) | |
8310 | ||
8311 | (define_insn_and_split "trunctfsf2" | |
8312 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
8313 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8314 | (clobber (match_scratch:DF 2 "=f"))] | |
a3170dc6 AH |
8315 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT |
8316 | && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8317 | "#" |
ea112fc4 | 8318 | "&& reload_completed" |
06f4e019 DE |
8319 | [(set (match_dup 2) |
8320 | (float_truncate:DF (match_dup 1))) | |
8321 | (set (match_dup 0) | |
8322 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 8323 | "") |
06f4e019 | 8324 | |
ea112fc4 DE |
8325 | (define_insn_and_split "floatditf2" |
8326 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 8327 | (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 DE |
8328 | (clobber (match_scratch:DF 2 "=f"))] |
8329 | "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 | |
a3170dc6 | 8330 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" |
ea112fc4 DE |
8331 | "#" |
8332 | "&& reload_completed" | |
06f4e019 | 8333 | [(set (match_dup 2) |
a2419b96 DE |
8334 | (float:DF (match_dup 1))) |
8335 | (set (match_dup 0) | |
06f4e019 | 8336 | (float_extend:TF (match_dup 2)))] |
ea112fc4 | 8337 | "") |
06f4e019 | 8338 | |
ea112fc4 DE |
8339 | (define_insn_and_split "floatsitf2" |
8340 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 8341 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r"))) |
ea112fc4 | 8342 | (clobber (match_scratch:DF 2 "=f"))] |
a3170dc6 AH |
8343 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8344 | && TARGET_LONG_DOUBLE_128" | |
ea112fc4 DE |
8345 | "#" |
8346 | "&& reload_completed" | |
06f4e019 | 8347 | [(set (match_dup 2) |
a2419b96 DE |
8348 | (float:DF (match_dup 1))) |
8349 | (set (match_dup 0) | |
06f4e019 | 8350 | (float_extend:TF (match_dup 2)))] |
ea112fc4 | 8351 | "") |
06f4e019 | 8352 | |
ea112fc4 | 8353 | (define_insn_and_split "fix_trunctfdi2" |
61c07d3c | 8354 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a2419b96 DE |
8355 | (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8356 | (clobber (match_scratch:DF 2 "=f"))] | |
ea112fc4 | 8357 | "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 |
a3170dc6 | 8358 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" |
ea112fc4 DE |
8359 | "#" |
8360 | "&& reload_completed" | |
06f4e019 | 8361 | [(set (match_dup 2) |
a2419b96 DE |
8362 | (float_truncate:DF (match_dup 1))) |
8363 | (set (match_dup 0) | |
8364 | (fix:DI (match_dup 2)))] | |
ea112fc4 | 8365 | "") |
06f4e019 | 8366 | |
ea112fc4 | 8367 | (define_insn_and_split "fix_trunctfsi2" |
61c07d3c | 8368 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2419b96 DE |
8369 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8370 | (clobber (match_scratch:DF 2 "=f"))] | |
a3170dc6 AH |
8371 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8372 | && TARGET_LONG_DOUBLE_128" | |
ea112fc4 DE |
8373 | "#" |
8374 | "&& reload_completed" | |
06f4e019 | 8375 | [(set (match_dup 2) |
a2419b96 DE |
8376 | (float_truncate:DF (match_dup 1))) |
8377 | (set (match_dup 0) | |
06f4e019 | 8378 | (fix:SI (match_dup 2)))] |
ea112fc4 | 8379 | "") |
06f4e019 DE |
8380 | |
8381 | (define_insn "negtf2" | |
8382 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8383 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8384 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8385 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8386 | "* |
8387 | { | |
8388 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8389 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8390 | else | |
8391 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8392 | }" | |
8393 | [(set_attr "type" "fp") | |
8394 | (set_attr "length" "8")]) | |
8395 | ||
8396 | (define_insn "abstf2" | |
8397 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8398 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8399 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8400 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8401 | "* |
8402 | { | |
8403 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8404 | return \"fabs %L0,%L1\;fabs %0,%1\"; | |
8405 | else | |
8406 | return \"fabs %0,%1\;fabs %L0,%L1\"; | |
8407 | }" | |
8408 | [(set_attr "type" "fp") | |
8409 | (set_attr "length" "8")]) | |
8410 | ||
8411 | (define_insn "" | |
8412 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8413 | (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 AH |
8414 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8415 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8416 | "* |
8417 | { | |
8418 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8419 | return \"fnabs %L0,%L1\;fnabs %0,%1\"; | |
8420 | else | |
8421 | return \"fnabs %0,%1\;fnabs %L0,%L1\"; | |
8422 | }" | |
8423 | [(set_attr "type" "fp") | |
8424 | (set_attr "length" "8")]) | |
8425 | \f | |
1fd4e8c1 RK |
8426 | ;; Next come the multi-word integer load and store and the load and store |
8427 | ;; multiple insns. | |
8428 | (define_expand "movdi" | |
8429 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8430 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 8431 | "" |
fb4d4348 | 8432 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 8433 | |
acad7ed3 | 8434 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
8435 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
8436 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 8437 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8438 | && (gpc_reg_operand (operands[0], DImode) |
8439 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
8440 | "* |
8441 | { | |
8442 | switch (which_alternative) | |
8443 | { | |
a260abc9 | 8444 | default: |
a6c2a102 | 8445 | abort (); |
1fd4e8c1 RK |
8446 | case 0: |
8447 | /* We normally copy the low-numbered register first. However, if | |
8448 | the first register operand 0 is the same as the second register of | |
8449 | operand 1, we must copy in the opposite order. */ | |
8450 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 8451 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8452 | else |
deb9225a | 8453 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
8454 | case 1: |
8455 | /* If the low-address word is used in the address, we must load it | |
8456 | last. Otherwise, load it first. Note that we cannot have | |
8457 | auto-increment in that case since the address register is known to be | |
8458 | dead. */ | |
8459 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8460 | operands[1], 0)) |
ca7f5001 | 8461 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 8462 | else |
ca7f5001 | 8463 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 8464 | case 2: |
ca7f5001 | 8465 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
8466 | case 3: |
8467 | return \"fmr %0,%1\"; | |
8468 | case 4: | |
8469 | return \"lfd%U1%X1 %0,%1\"; | |
8470 | case 5: | |
8471 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
8472 | case 6: |
8473 | case 7: | |
8474 | case 8: | |
8475 | case 9: | |
8476 | case 10: | |
8477 | return \"#\"; | |
1fd4e8c1 RK |
8478 | } |
8479 | }" | |
4e74d8ec | 8480 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
914a7297 | 8481 | (set_attr "length" "8,8,8,4,4,4,8,12,8,12,16")]) |
4e74d8ec MM |
8482 | |
8483 | (define_split | |
8484 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8485 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8486 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8487 | [(set (match_dup 2) (match_dup 4)) |
8488 | (set (match_dup 3) (match_dup 1))] | |
8489 | " | |
8490 | { | |
5f59ecb7 | 8491 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8492 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8493 | DImode); | |
8494 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8495 | DImode); | |
75d39459 | 8496 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8497 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8498 | #else |
5f59ecb7 | 8499 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8500 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8501 | #endif |
4e74d8ec MM |
8502 | }") |
8503 | ||
4e74d8ec MM |
8504 | (define_split |
8505 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8506 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 8507 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8508 | [(set (match_dup 2) (match_dup 4)) |
8509 | (set (match_dup 3) (match_dup 5))] | |
8510 | " | |
8511 | { | |
bdaa0181 GK |
8512 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8513 | DImode); | |
8514 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8515 | DImode); | |
f6968f59 MM |
8516 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
8517 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
8518 | }") |
8519 | ||
6fc19dc9 AM |
8520 | (define_split |
8521 | [(set (match_operand:TI 0 "gpc_reg_operand" "") | |
8522 | (match_operand:TI 1 "const_double_operand" ""))] | |
8523 | "TARGET_POWERPC64" | |
8524 | [(set (match_dup 2) (match_dup 4)) | |
8525 | (set (match_dup 3) (match_dup 5))] | |
8526 | " | |
8527 | { | |
8528 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, | |
8529 | TImode); | |
8530 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8531 | TImode); | |
8532 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
8533 | { | |
8534 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8535 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8536 | } | |
8537 | else if (GET_CODE (operands[1]) == CONST_INT) | |
8538 | { | |
8539 | operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); | |
8540 | operands[5] = operands[1]; | |
8541 | } | |
8542 | else | |
8543 | FAIL; | |
8544 | }") | |
8545 | ||
acad7ed3 | 8546 | (define_insn "*movdi_internal64" |
5d7e6254 | 8547 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h") |
9615f239 | 8548 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8549 | "TARGET_POWERPC64 |
4e74d8ec MM |
8550 | && (gpc_reg_operand (operands[0], DImode) |
8551 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8552 | "@ |
3d5570cb RK |
8553 | mr %0,%1 |
8554 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8555 | std%U0%X0 %1,%0 |
3d5570cb | 8556 | li %0,%1 |
802a0058 | 8557 | lis %0,%v1 |
e6ca2c17 | 8558 | # |
aee86b38 | 8559 | {cal|la} %0,%a1 |
3d5570cb RK |
8560 | fmr %0,%1 |
8561 | lfd%U1%X1 %0,%1 | |
8562 | stfd%U0%X0 %1,%0 | |
8563 | mf%1 %0 | |
08075ead | 8564 | mt%0 %1 |
e34eaae5 | 8565 | {cror 0,0,0|nop}" |
02ca7595 | 8566 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") |
e6ca2c17 DE |
8567 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8568 | ||
5f59ecb7 | 8569 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8570 | (define_insn "" |
8571 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8572 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8573 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8574 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8575 | && num_insns_constant (operands[1], DImode) == 1" |
8576 | "* | |
8577 | { | |
8578 | return ((unsigned HOST_WIDE_INT) | |
8579 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8580 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8581 | }") | |
8582 | ||
a260abc9 DE |
8583 | ;; Generate all one-bits and clear left or right. |
8584 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8585 | (define_split | |
8586 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8587 | (match_operand:DI 1 "mask64_operand" ""))] | |
8588 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8589 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8590 | (set (match_dup 0) |
a260abc9 DE |
8591 | (and:DI (rotate:DI (match_dup 0) |
8592 | (const_int 0)) | |
8593 | (match_dup 1)))] | |
8594 | "") | |
8595 | ||
8596 | ;; Split a load of a large constant into the appropriate five-instruction | |
8597 | ;; sequence. Handle anything in a constant number of insns. | |
8598 | ;; When non-easy constants can go in the TOC, this should use | |
8599 | ;; easy_fp_constant predicate. | |
8600 | (define_split | |
8601 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8602 | (match_operand:DI 1 "const_int_operand" ""))] |
8603 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8604 | [(set (match_dup 0) (match_dup 2)) | |
8605 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8606 | " |
2bfcf297 DB |
8607 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8608 | ||
8609 | if (tem == operands[0]) | |
8610 | DONE; | |
e8d791dd | 8611 | else |
2bfcf297 | 8612 | FAIL; |
5f59ecb7 | 8613 | }") |
e6ca2c17 | 8614 | |
5f59ecb7 DE |
8615 | (define_split |
8616 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8617 | (match_operand:DI 1 "const_double_operand" ""))] |
8618 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8619 | [(set (match_dup 0) (match_dup 2)) | |
8620 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8621 | " |
2bfcf297 DB |
8622 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8623 | ||
8624 | if (tem == operands[0]) | |
8625 | DONE; | |
8626 | else | |
8627 | FAIL; | |
e6ca2c17 | 8628 | }") |
08075ead | 8629 | |
acad7ed3 | 8630 | (define_insn "*movdi_internal2" |
bb84cb12 DE |
8631 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
8632 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r") | |
08075ead | 8633 | (const_int 0))) |
bb84cb12 | 8634 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
08075ead | 8635 | "TARGET_POWERPC64" |
9ebbca7d | 8636 | "@ |
bb84cb12 | 8637 | cmpdi %2,%0,0 |
9ebbca7d GK |
8638 | mr. %0,%1 |
8639 | #" | |
bb84cb12 DE |
8640 | [(set_attr "type" "cmp,compare,cmp") |
8641 | (set_attr "length" "4,4,8")]) | |
acad7ed3 | 8642 | |
9ebbca7d GK |
8643 | (define_split |
8644 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8645 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8646 | (const_int 0))) | |
8647 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8648 | "TARGET_POWERPC64 && reload_completed" | |
8649 | [(set (match_dup 0) (match_dup 1)) | |
8650 | (set (match_dup 2) | |
8651 | (compare:CC (match_dup 0) | |
8652 | (const_int 0)))] | |
8653 | "") | |
acad7ed3 | 8654 | \f |
1fd4e8c1 RK |
8655 | ;; TImode is similar, except that we usually want to compute the address into |
8656 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8657 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8658 | (define_expand "movti" |
8659 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8660 | (match_operand:TI 1 "general_operand" "")) | |
8661 | (clobber (scratch:SI))])] | |
7e69e155 | 8662 | "TARGET_STRING || TARGET_POWERPC64" |
fb4d4348 | 8663 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8664 | |
8665 | ;; We say that MQ is clobbered in the last alternative because the first | |
8666 | ;; alternative would never get used otherwise since it would need a reload | |
8667 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8668 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8669 | ;; giving the SCRATCH mq. | |
a260abc9 | 8670 | (define_insn "*movti_power" |
e1469d0d | 8671 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8672 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8673 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 8674 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8675 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8676 | "* |
8677 | { | |
8678 | switch (which_alternative) | |
8679 | { | |
dc4f83ca MM |
8680 | default: |
8681 | abort (); | |
8682 | ||
1fd4e8c1 | 8683 | case 0: |
ca7f5001 | 8684 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 | 8685 | case 1: |
ca7f5001 | 8686 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
8687 | case 2: |
8688 | /* Normally copy registers with lowest numbered register copied first. | |
8689 | But copy in the other order if the first register of the output | |
8690 | is the second, third, or fourth register in the input. */ | |
8691 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8692 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 8693 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8694 | else |
deb9225a | 8695 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
8696 | case 3: |
8697 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8698 | fall through to generating four loads. */ | |
8699 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8700 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8701 | /* ... fall through ... */ |
1fd4e8c1 RK |
8702 | case 4: |
8703 | /* If the address register is the same as the register for the lowest- | |
8704 | addressed word, load it last. Similarly for the next two words. | |
8705 | Otherwise load lowest address to highest. */ | |
8706 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8707 | operands[1], 0)) | |
ca7f5001 | 8708 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
8709 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
8710 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 8711 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
8712 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
8713 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 8714 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 8715 | else |
ca7f5001 | 8716 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
8717 | } |
8718 | }" | |
b7ff3d82 | 8719 | [(set_attr "type" "store,store,*,load,load") |
914a7297 | 8720 | (set_attr "length" "4,16,16,4,16")]) |
51b8fc2c | 8721 | |
a260abc9 | 8722 | (define_insn "*movti_string" |
cd1d3445 | 8723 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
27dc0551 | 8724 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))] |
0ad91047 | 8725 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8726 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8727 | "* | |
8728 | { | |
8729 | switch (which_alternative) | |
8730 | { | |
8731 | default: | |
8732 | abort (); | |
8733 | ||
8734 | case 0: | |
cd1d3445 | 8735 | return \"{stsi|stswi} %1,%P0,16\"; |
dc4f83ca | 8736 | case 1: |
cd1d3445 DE |
8737 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
8738 | case 2: | |
dc4f83ca MM |
8739 | /* Normally copy registers with lowest numbered register copied first. |
8740 | But copy in the other order if the first register of the output | |
8741 | is the second, third, or fourth register in the input. */ | |
8742 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8743 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
8744 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
8745 | else | |
8746 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
cd1d3445 DE |
8747 | case 3: |
8748 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8749 | fall through to generating four loads. */ | |
8750 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
8751 | return \"{lsi|lswi} %0,%P1,16\"; | |
8752 | /* ... fall through ... */ | |
8753 | case 4: | |
dc4f83ca MM |
8754 | /* If the address register is the same as the register for the lowest- |
8755 | addressed word, load it last. Similarly for the next two words. | |
8756 | Otherwise load lowest address to highest. */ | |
8757 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8758 | operands[1], 0)) | |
8759 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
8760 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
8761 | REGNO (operands[0]) + 2, operands[1], 0)) | |
8762 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
8763 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
8764 | REGNO (operands[0]) + 3, operands[1], 0)) | |
8765 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
8766 | else | |
8767 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
8768 | } | |
8769 | }" | |
cd1d3445 DE |
8770 | [(set_attr "type" "store,store,*,load,load") |
8771 | (set_attr "length" "4,16,16,4,16")]) | |
dc4f83ca | 8772 | |
a260abc9 | 8773 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
8774 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
8775 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
8776 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
8777 | || gpc_reg_operand (operands[1], TImode))" | |
8778 | "* | |
8779 | { | |
8780 | switch (which_alternative) | |
8781 | { | |
a260abc9 | 8782 | default: |
a6c2a102 | 8783 | abort (); |
51b8fc2c RK |
8784 | case 0: |
8785 | /* We normally copy the low-numbered register first. However, if | |
8786 | the first register operand 0 is the same as the second register of | |
8787 | operand 1, we must copy in the opposite order. */ | |
8788 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8789 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8790 | else | |
8791 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8792 | case 1: | |
8793 | /* If the low-address word is used in the address, we must load it | |
8794 | last. Otherwise, load it first. Note that we cannot have | |
8795 | auto-increment in that case since the address register is known to be | |
8796 | dead. */ | |
8797 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8798 | operands[1], 0)) |
51b8fc2c RK |
8799 | return \"ld %L0,%L1\;ld %0,%1\"; |
8800 | else | |
8801 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
8802 | case 2: | |
8803 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
8804 | } | |
8805 | }" | |
b7ff3d82 | 8806 | [(set_attr "type" "*,load,store") |
51b8fc2c | 8807 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
8808 | \f |
8809 | (define_expand "load_multiple" | |
2f622005 RK |
8810 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8811 | (match_operand:SI 1 "" "")) | |
8812 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8813 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8814 | " |
8815 | { | |
8816 | int regno; | |
8817 | int count; | |
792760b9 | 8818 | rtx op1; |
1fd4e8c1 RK |
8819 | int i; |
8820 | ||
8821 | /* Support only loading a constant number of fixed-point registers from | |
8822 | memory and only bother with this if more than two; the machine | |
8823 | doesn't support more than eight. */ | |
8824 | if (GET_CODE (operands[2]) != CONST_INT | |
8825 | || INTVAL (operands[2]) <= 2 | |
8826 | || INTVAL (operands[2]) > 8 | |
8827 | || GET_CODE (operands[1]) != MEM | |
8828 | || GET_CODE (operands[0]) != REG | |
8829 | || REGNO (operands[0]) >= 32) | |
8830 | FAIL; | |
8831 | ||
8832 | count = INTVAL (operands[2]); | |
8833 | regno = REGNO (operands[0]); | |
8834 | ||
39403d82 | 8835 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8836 | op1 = replace_equiv_address (operands[1], |
8837 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8838 | |
8839 | for (i = 0; i < count; i++) | |
8840 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8841 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 8842 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8843 | }") |
8844 | ||
9caa3eb2 | 8845 | (define_insn "*ldmsi8" |
1fd4e8c1 | 8846 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
8847 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
8848 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8849 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8850 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8851 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8852 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8853 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8854 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8855 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8856 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8857 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8858 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8859 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8860 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
8861 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
8862 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
8863 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 8864 | "* |
9caa3eb2 DE |
8865 | { return rs6000_output_load_multiple (operands); }" |
8866 | [(set_attr "type" "load") | |
8867 | (set_attr "length" "32")]) | |
1fd4e8c1 | 8868 | |
9caa3eb2 DE |
8869 | (define_insn "*ldmsi7" |
8870 | [(match_parallel 0 "load_multiple_operation" | |
8871 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8872 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8873 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8874 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8875 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8876 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8877 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8878 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8879 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8880 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8881 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8882 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8883 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8884 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
8885 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
8886 | "* | |
8887 | { return rs6000_output_load_multiple (operands); }" | |
8888 | [(set_attr "type" "load") | |
8889 | (set_attr "length" "32")]) | |
8890 | ||
8891 | (define_insn "*ldmsi6" | |
8892 | [(match_parallel 0 "load_multiple_operation" | |
8893 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8894 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8895 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8896 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8897 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8898 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8899 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8900 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8901 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8902 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8903 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8904 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
8905 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
8906 | "* | |
8907 | { return rs6000_output_load_multiple (operands); }" | |
8908 | [(set_attr "type" "load") | |
8909 | (set_attr "length" "32")]) | |
8910 | ||
8911 | (define_insn "*ldmsi5" | |
8912 | [(match_parallel 0 "load_multiple_operation" | |
8913 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8914 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8915 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8916 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8917 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8918 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8919 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8920 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8921 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8922 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
8923 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
8924 | "* | |
8925 | { return rs6000_output_load_multiple (operands); }" | |
8926 | [(set_attr "type" "load") | |
8927 | (set_attr "length" "32")]) | |
8928 | ||
8929 | (define_insn "*ldmsi4" | |
8930 | [(match_parallel 0 "load_multiple_operation" | |
8931 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8932 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8933 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8934 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8935 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8936 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8937 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8938 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
8939 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
8940 | "* | |
8941 | { return rs6000_output_load_multiple (operands); }" | |
8942 | [(set_attr "type" "load") | |
8943 | (set_attr "length" "32")]) | |
8944 | ||
8945 | (define_insn "*ldmsi3" | |
8946 | [(match_parallel 0 "load_multiple_operation" | |
8947 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8948 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8949 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8950 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8951 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8952 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
8953 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
8954 | "* | |
8955 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 8956 | [(set_attr "type" "load") |
e82ee4cc | 8957 | (set_attr "length" "32")]) |
b19003d8 | 8958 | |
1fd4e8c1 | 8959 | (define_expand "store_multiple" |
2f622005 RK |
8960 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8961 | (match_operand:SI 1 "" "")) | |
8962 | (clobber (scratch:SI)) | |
8963 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8964 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8965 | " |
8966 | { | |
8967 | int regno; | |
8968 | int count; | |
8969 | rtx to; | |
792760b9 | 8970 | rtx op0; |
1fd4e8c1 RK |
8971 | int i; |
8972 | ||
8973 | /* Support only storing a constant number of fixed-point registers to | |
8974 | memory and only bother with this if more than two; the machine | |
8975 | doesn't support more than eight. */ | |
8976 | if (GET_CODE (operands[2]) != CONST_INT | |
8977 | || INTVAL (operands[2]) <= 2 | |
8978 | || INTVAL (operands[2]) > 8 | |
8979 | || GET_CODE (operands[0]) != MEM | |
8980 | || GET_CODE (operands[1]) != REG | |
8981 | || REGNO (operands[1]) >= 32) | |
8982 | FAIL; | |
8983 | ||
8984 | count = INTVAL (operands[2]); | |
8985 | regno = REGNO (operands[1]); | |
8986 | ||
39403d82 | 8987 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8988 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8989 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8990 | |
8991 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 8992 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 8993 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8994 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8995 | |
8996 | for (i = 1; i < count; i++) | |
8997 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8998 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 8999 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 9000 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
9001 | }") |
9002 | ||
9caa3eb2 | 9003 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
9004 | [(match_parallel 0 "store_multiple_operation" |
9005 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 9006 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9007 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 9008 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
9009 | "{stsi|stswi} %2,%P1,%O0" |
9010 | [(set_attr "type" "store")]) | |
d14a6d05 | 9011 | |
e46e3130 | 9012 | (define_insn "*stmsi8" |
d14a6d05 | 9013 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
9014 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
9015 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9016 | (clobber (match_scratch:SI 3 "X")) | |
9017 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9018 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9019 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9020 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9021 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9022 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9023 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9024 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9025 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9026 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
9027 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
9028 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
9029 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
9030 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
9031 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
9032 | "{stsi|stswi} %2,%1,%O0" | |
9033 | [(set_attr "type" "store")]) | |
9034 | ||
9035 | (define_insn "*stmsi7" | |
9036 | [(match_parallel 0 "store_multiple_operation" | |
9037 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9038 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9039 | (clobber (match_scratch:SI 3 "X")) | |
9040 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9041 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9042 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9043 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9044 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9045 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9046 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9047 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9048 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9049 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
9050 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
9051 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
9052 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
9053 | "{stsi|stswi} %2,%1,%O0" | |
9054 | [(set_attr "type" "store")]) | |
9055 | ||
9056 | (define_insn "*stmsi6" | |
9057 | [(match_parallel 0 "store_multiple_operation" | |
9058 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9059 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9060 | (clobber (match_scratch:SI 3 "X")) | |
9061 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9062 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9063 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9064 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9065 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9066 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9067 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9068 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9069 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9070 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
9071 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
9072 | "{stsi|stswi} %2,%1,%O0" | |
9073 | [(set_attr "type" "store")]) | |
9074 | ||
9075 | (define_insn "*stmsi5" | |
9076 | [(match_parallel 0 "store_multiple_operation" | |
9077 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9078 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9079 | (clobber (match_scratch:SI 3 "X")) | |
9080 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9081 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9082 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9083 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9084 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9085 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9086 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9087 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
9088 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
9089 | "{stsi|stswi} %2,%1,%O0" | |
9090 | [(set_attr "type" "store")]) | |
9091 | ||
9092 | (define_insn "*stmsi4" | |
9093 | [(match_parallel 0 "store_multiple_operation" | |
9094 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9095 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9096 | (clobber (match_scratch:SI 3 "X")) | |
9097 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9098 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9099 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9100 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9101 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9102 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
9103 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
9104 | "{stsi|stswi} %2,%1,%O0" |
9105 | [(set_attr "type" "store")]) | |
7e69e155 | 9106 | |
e46e3130 DJ |
9107 | (define_insn "*stmsi3" |
9108 | [(match_parallel 0 "store_multiple_operation" | |
9109 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9110 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9111 | (clobber (match_scratch:SI 3 "X")) | |
9112 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9113 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9114 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9115 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
9116 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
9117 | "{stsi|stswi} %2,%1,%O0" | |
9118 | [(set_attr "type" "store")]) | |
7e69e155 MM |
9119 | \f |
9120 | ;; String/block move insn. | |
9121 | ;; Argument 0 is the destination | |
9122 | ;; Argument 1 is the source | |
9123 | ;; Argument 2 is the length | |
9124 | ;; Argument 3 is the alignment | |
9125 | ||
9126 | (define_expand "movstrsi" | |
b6c9286a MM |
9127 | [(parallel [(set (match_operand:BLK 0 "" "") |
9128 | (match_operand:BLK 1 "" "")) | |
9129 | (use (match_operand:SI 2 "" "")) | |
9130 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
9131 | "" |
9132 | " | |
9133 | { | |
9134 | if (expand_block_move (operands)) | |
9135 | DONE; | |
9136 | else | |
9137 | FAIL; | |
9138 | }") | |
9139 | ||
9140 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
9141 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
9142 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9143 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
9144 | [(parallel [(set (match_operand 0 "" "") |
9145 | (match_operand 1 "" "")) | |
9146 | (use (match_operand 2 "" "")) | |
9147 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
9148 | (clobber (reg:SI 5)) |
9149 | (clobber (reg:SI 6)) | |
9150 | (clobber (reg:SI 7)) | |
9151 | (clobber (reg:SI 8)) | |
9152 | (clobber (reg:SI 9)) | |
9153 | (clobber (reg:SI 10)) | |
9154 | (clobber (reg:SI 11)) | |
9155 | (clobber (reg:SI 12)) | |
3c67b673 | 9156 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9157 | "TARGET_STRING" |
9158 | "") | |
9159 | ||
9160 | (define_insn "" | |
52d3af72 DE |
9161 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9162 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9163 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9164 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9165 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9166 | (clobber (reg:SI 6)) |
9167 | (clobber (reg:SI 7)) | |
9168 | (clobber (reg:SI 8)) | |
9169 | (clobber (reg:SI 9)) | |
9170 | (clobber (reg:SI 10)) | |
9171 | (clobber (reg:SI 11)) | |
9172 | (clobber (reg:SI 12)) | |
3c67b673 | 9173 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 9174 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
9175 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9176 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9177 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9178 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9179 | && REGNO (operands[4]) == 5" |
9180 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9181 | [(set_attr "type" "load") |
9182 | (set_attr "length" "8")]) | |
7e69e155 MM |
9183 | |
9184 | (define_insn "" | |
52d3af72 DE |
9185 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9186 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9187 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9188 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9189 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9190 | (clobber (reg:SI 6)) |
9191 | (clobber (reg:SI 7)) | |
9192 | (clobber (reg:SI 8)) | |
9193 | (clobber (reg:SI 9)) | |
9194 | (clobber (reg:SI 10)) | |
9195 | (clobber (reg:SI 11)) | |
9196 | (clobber (reg:SI 12)) | |
3c67b673 | 9197 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9198 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
9199 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9200 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9201 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9202 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9203 | && REGNO (operands[4]) == 5" |
9204 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9205 | [(set_attr "type" "load") |
9206 | (set_attr "length" "8")]) | |
7e69e155 | 9207 | |
09a625f7 TR |
9208 | (define_insn "" |
9209 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9210 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9211 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9212 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9213 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9214 | (clobber (reg:SI 6)) | |
9215 | (clobber (reg:SI 7)) | |
9216 | (clobber (reg:SI 8)) | |
9217 | (clobber (reg:SI 9)) | |
9218 | (clobber (reg:SI 10)) | |
9219 | (clobber (reg:SI 11)) | |
9220 | (clobber (reg:SI 12)) | |
9221 | (clobber (match_scratch:SI 5 "X"))] | |
9222 | "TARGET_STRING && TARGET_POWERPC64 | |
9223 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
9224 | || INTVAL (operands[2]) == 0) | |
9225 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
9226 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
9227 | && REGNO (operands[4]) == 5" | |
9228 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9229 | [(set_attr "type" "load") | |
9230 | (set_attr "length" "8")]) | |
9231 | ||
7e69e155 | 9232 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
9233 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
9234 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9235 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
9236 | [(parallel [(set (match_operand 0 "" "") |
9237 | (match_operand 1 "" "")) | |
9238 | (use (match_operand 2 "" "")) | |
9239 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9240 | (clobber (reg:SI 5)) |
9241 | (clobber (reg:SI 6)) | |
7e69e155 MM |
9242 | (clobber (reg:SI 7)) |
9243 | (clobber (reg:SI 8)) | |
9244 | (clobber (reg:SI 9)) | |
9245 | (clobber (reg:SI 10)) | |
3c67b673 | 9246 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9247 | "TARGET_STRING" |
9248 | "") | |
9249 | ||
9250 | (define_insn "" | |
52d3af72 DE |
9251 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9252 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9253 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9254 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9255 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9256 | (clobber (reg:SI 6)) |
9257 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9258 | (clobber (reg:SI 8)) |
9259 | (clobber (reg:SI 9)) | |
9260 | (clobber (reg:SI 10)) | |
3c67b673 | 9261 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9262 | "TARGET_STRING && TARGET_POWER |
9263 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
9264 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9265 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9266 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9267 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9268 | [(set_attr "type" "load") |
9269 | (set_attr "length" "8")]) | |
7e69e155 MM |
9270 | |
9271 | (define_insn "" | |
52d3af72 DE |
9272 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9273 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9274 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9275 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9276 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9277 | (clobber (reg:SI 6)) |
9278 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9279 | (clobber (reg:SI 8)) |
9280 | (clobber (reg:SI 9)) | |
9281 | (clobber (reg:SI 10)) | |
3c67b673 | 9282 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9283 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9284 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
9285 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9286 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9287 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9288 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9289 | [(set_attr "type" "load") |
9290 | (set_attr "length" "8")]) | |
7e69e155 | 9291 | |
09a625f7 TR |
9292 | (define_insn "" |
9293 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9294 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9295 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9296 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9297 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9298 | (clobber (reg:SI 6)) | |
9299 | (clobber (reg:SI 7)) | |
9300 | (clobber (reg:SI 8)) | |
9301 | (clobber (reg:SI 9)) | |
9302 | (clobber (reg:SI 10)) | |
9303 | (clobber (match_scratch:SI 5 "X"))] | |
9304 | "TARGET_STRING && TARGET_POWERPC64 | |
9305 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
9306 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
9307 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9308 | && REGNO (operands[4]) == 5" | |
9309 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9310 | [(set_attr "type" "load") | |
9311 | (set_attr "length" "8")]) | |
9312 | ||
f9562f27 DE |
9313 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9314 | ;; problems with TImode. | |
9315 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9316 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
9317 | [(parallel [(set (match_operand 0 "" "") |
9318 | (match_operand 1 "" "")) | |
9319 | (use (match_operand 2 "" "")) | |
9320 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9321 | (clobber (reg:SI 5)) |
9322 | (clobber (reg:SI 6)) | |
9323 | (clobber (reg:SI 7)) | |
9324 | (clobber (reg:SI 8)) | |
3c67b673 | 9325 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9326 | "TARGET_STRING" |
9327 | "") | |
9328 | ||
9329 | (define_insn "" | |
52d3af72 DE |
9330 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9331 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9332 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9333 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9334 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9335 | (clobber (reg:SI 6)) |
9336 | (clobber (reg:SI 7)) | |
9337 | (clobber (reg:SI 8)) | |
3c67b673 | 9338 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9339 | "TARGET_STRING && TARGET_POWER |
9340 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9341 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9342 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9343 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9344 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9345 | [(set_attr "type" "load") |
9346 | (set_attr "length" "8")]) | |
7e69e155 MM |
9347 | |
9348 | (define_insn "" | |
52d3af72 DE |
9349 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9350 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9351 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9352 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9353 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9354 | (clobber (reg:SI 6)) |
9355 | (clobber (reg:SI 7)) | |
9356 | (clobber (reg:SI 8)) | |
3c67b673 | 9357 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9358 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9359 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9360 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9361 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9362 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9363 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9364 | [(set_attr "type" "load") |
9365 | (set_attr "length" "8")]) | |
7e69e155 | 9366 | |
09a625f7 TR |
9367 | (define_insn "" |
9368 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9369 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9370 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9371 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9372 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9373 | (clobber (reg:SI 6)) | |
9374 | (clobber (reg:SI 7)) | |
9375 | (clobber (reg:SI 8)) | |
9376 | (clobber (match_scratch:SI 5 "X"))] | |
9377 | "TARGET_STRING && TARGET_POWERPC64 | |
9378 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
9379 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
9380 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9381 | && REGNO (operands[4]) == 5" | |
9382 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9383 | [(set_attr "type" "load") | |
9384 | (set_attr "length" "8")]) | |
9385 | ||
7e69e155 MM |
9386 | ;; Move up to 8 bytes at a time. |
9387 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
9388 | [(parallel [(set (match_operand 0 "" "") |
9389 | (match_operand 1 "" "")) | |
9390 | (use (match_operand 2 "" "")) | |
9391 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9392 | (clobber (match_scratch:DI 4 "")) |
9393 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9394 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9395 | "") |
9396 | ||
9397 | (define_insn "" | |
52d3af72 DE |
9398 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9399 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9400 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9401 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9402 | (clobber (match_scratch:DI 4 "=&r")) | |
9403 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9404 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9405 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9406 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9407 | [(set_attr "type" "load") |
9408 | (set_attr "length" "8")]) | |
7e69e155 MM |
9409 | |
9410 | (define_insn "" | |
52d3af72 DE |
9411 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9412 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9413 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9414 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9415 | (clobber (match_scratch:DI 4 "=&r")) | |
9416 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9417 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9418 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9419 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9420 | [(set_attr "type" "load") |
9421 | (set_attr "length" "8")]) | |
7e69e155 MM |
9422 | |
9423 | ;; Move up to 4 bytes at a time. | |
9424 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
9425 | [(parallel [(set (match_operand 0 "" "") |
9426 | (match_operand 1 "" "")) | |
9427 | (use (match_operand 2 "" "")) | |
9428 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9429 | (clobber (match_scratch:SI 4 "")) |
9430 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9431 | "TARGET_STRING" |
9432 | "") | |
9433 | ||
9434 | (define_insn "" | |
52d3af72 DE |
9435 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9436 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9437 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9438 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9439 | (clobber (match_scratch:SI 4 "=&r")) | |
9440 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9441 | "TARGET_STRING && TARGET_POWER |
9442 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9443 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9444 | [(set_attr "type" "load") |
9445 | (set_attr "length" "8")]) | |
7e69e155 MM |
9446 | |
9447 | (define_insn "" | |
52d3af72 DE |
9448 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9449 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9450 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9451 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9452 | (clobber (match_scratch:SI 4 "=&r")) | |
9453 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9454 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9455 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
9456 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
9457 | [(set_attr "type" "load") | |
9458 | (set_attr "length" "8")]) | |
9459 | ||
9460 | (define_insn "" | |
9461 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9462 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9463 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9464 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9465 | (clobber (match_scratch:SI 4 "=&r")) | |
9466 | (clobber (match_scratch:SI 5 "X"))] | |
9467 | "TARGET_STRING && TARGET_POWERPC64 | |
9468 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9469 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9470 | [(set_attr "type" "load") |
9471 | (set_attr "length" "8")]) | |
7e69e155 | 9472 | |
1fd4e8c1 | 9473 | \f |
7e69e155 | 9474 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9475 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9476 | ;; do cases where the increment is not the size of the object. | |
9477 | ;; | |
9478 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9479 | ;; incremented because those are the operands that local-alloc will | |
9480 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9481 | ;; that will benefit the most). | |
9482 | ||
38c1f2d7 | 9483 | (define_insn "*movdi_update1" |
51b8fc2c | 9484 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9485 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9486 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
9487 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
9488 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9489 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9490 | "@ |
9491 | ldux %3,%0,%2 | |
9492 | ldu %3,%2(%0)" | |
b54cf83a | 9493 | [(set_attr "type" "load_ux,load_u")]) |
287f13ff | 9494 | |
4697a36c | 9495 | (define_insn "movdi_update" |
51b8fc2c | 9496 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9497 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))) |
51b8fc2c RK |
9498 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
9499 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
9500 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9501 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9502 | "@ |
9503 | stdux %3,%0,%2 | |
b7ff3d82 | 9504 | stdu %3,%2(%0)" |
b54cf83a | 9505 | [(set_attr "type" "store_ux,store_u")]) |
51b8fc2c | 9506 | |
38c1f2d7 | 9507 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9508 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9509 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9510 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9511 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9512 | (plus:SI (match_dup 1) (match_dup 2)))] |
f7b3ab8a | 9513 | "TARGET_UPDATE" |
1fd4e8c1 | 9514 | "@ |
ca7f5001 RK |
9515 | {lux|lwzux} %3,%0,%2 |
9516 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a DE |
9517 | [(set_attr "type" "load_ux,load_u")]) |
9518 | ||
9519 | (define_insn "*movsi_update2" | |
9520 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
9521 | (sign_extend:DI | |
9522 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9523 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9524 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9525 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9526 | "TARGET_POWERPC64" | |
9527 | "lwaux %3,%0,%2" | |
9528 | [(set_attr "type" "load_ext_ux")]) | |
1fd4e8c1 | 9529 | |
4697a36c | 9530 | (define_insn "movsi_update" |
cd2b37d9 | 9531 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9532 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9533 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9534 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9535 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9536 | "TARGET_UPDATE" |
1fd4e8c1 | 9537 | "@ |
ca7f5001 | 9538 | {stux|stwux} %3,%0,%2 |
b7ff3d82 | 9539 | {stu|stwu} %3,%2(%0)" |
b54cf83a | 9540 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9541 | |
b54cf83a | 9542 | (define_insn "*movhi_update1" |
cd2b37d9 RK |
9543 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9544 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9545 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9546 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9547 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9548 | "TARGET_UPDATE" |
1fd4e8c1 | 9549 | "@ |
5f243543 RK |
9550 | lhzux %3,%0,%2 |
9551 | lhzu %3,%2(%0)" | |
b54cf83a | 9552 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9553 | |
38c1f2d7 | 9554 | (define_insn "*movhi_update2" |
cd2b37d9 | 9555 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9556 | (zero_extend:SI |
cd2b37d9 | 9557 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9558 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9559 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9560 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9561 | "TARGET_UPDATE" |
1fd4e8c1 | 9562 | "@ |
5f243543 RK |
9563 | lhzux %3,%0,%2 |
9564 | lhzu %3,%2(%0)" | |
b54cf83a | 9565 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9566 | |
38c1f2d7 | 9567 | (define_insn "*movhi_update3" |
cd2b37d9 | 9568 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9569 | (sign_extend:SI |
cd2b37d9 | 9570 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9571 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9572 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9573 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9574 | "TARGET_UPDATE" |
1fd4e8c1 | 9575 | "@ |
5f243543 RK |
9576 | lhaux %3,%0,%2 |
9577 | lhau %3,%2(%0)" | |
b54cf83a | 9578 | [(set_attr "type" "load_ext_ux,load_ext_u")]) |
1fd4e8c1 | 9579 | |
38c1f2d7 | 9580 | (define_insn "*movhi_update4" |
cd2b37d9 | 9581 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9582 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9583 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9584 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9585 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9586 | "TARGET_UPDATE" |
1fd4e8c1 | 9587 | "@ |
5f243543 | 9588 | sthux %3,%0,%2 |
b7ff3d82 | 9589 | sthu %3,%2(%0)" |
b54cf83a | 9590 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9591 | |
38c1f2d7 | 9592 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9593 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9594 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9595 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9596 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9597 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9598 | "TARGET_UPDATE" |
1fd4e8c1 | 9599 | "@ |
5f243543 RK |
9600 | lbzux %3,%0,%2 |
9601 | lbzu %3,%2(%0)" | |
b54cf83a | 9602 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9603 | |
38c1f2d7 | 9604 | (define_insn "*movqi_update2" |
cd2b37d9 | 9605 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9606 | (zero_extend:SI |
cd2b37d9 | 9607 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9608 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9609 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9610 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9611 | "TARGET_UPDATE" |
1fd4e8c1 | 9612 | "@ |
5f243543 RK |
9613 | lbzux %3,%0,%2 |
9614 | lbzu %3,%2(%0)" | |
b54cf83a | 9615 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9616 | |
38c1f2d7 | 9617 | (define_insn "*movqi_update3" |
cd2b37d9 | 9618 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9619 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9620 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9621 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9622 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9623 | "TARGET_UPDATE" |
1fd4e8c1 | 9624 | "@ |
5f243543 | 9625 | stbux %3,%0,%2 |
b7ff3d82 | 9626 | stbu %3,%2(%0)" |
b54cf83a | 9627 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9628 | |
38c1f2d7 | 9629 | (define_insn "*movsf_update1" |
cd2b37d9 | 9630 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9631 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9632 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9633 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9634 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9635 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9636 | "@ |
5f243543 RK |
9637 | lfsux %3,%0,%2 |
9638 | lfsu %3,%2(%0)" | |
b54cf83a | 9639 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9640 | |
38c1f2d7 | 9641 | (define_insn "*movsf_update2" |
cd2b37d9 | 9642 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9643 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9644 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9645 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9646 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9647 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9648 | "@ |
85fff2f3 | 9649 | stfsux %3,%0,%2 |
b7ff3d82 | 9650 | stfsu %3,%2(%0)" |
b54cf83a | 9651 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
1fd4e8c1 | 9652 | |
38c1f2d7 MM |
9653 | (define_insn "*movsf_update3" |
9654 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9655 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9656 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9657 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9658 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9659 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9660 | "@ |
9661 | {lux|lwzux} %3,%0,%2 | |
9662 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a | 9663 | [(set_attr "type" "load_ux,load_u")]) |
38c1f2d7 MM |
9664 | |
9665 | (define_insn "*movsf_update4" | |
9666 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9667 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9668 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9669 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9670 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9671 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9672 | "@ |
9673 | {stux|stwux} %3,%0,%2 | |
9674 | {stu|stwu} %3,%2(%0)" | |
b54cf83a | 9675 | [(set_attr "type" "store_ux,store_u")]) |
38c1f2d7 MM |
9676 | |
9677 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9678 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9679 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9680 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9681 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9682 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9683 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9684 | "@ |
5f243543 RK |
9685 | lfdux %3,%0,%2 |
9686 | lfdu %3,%2(%0)" | |
b54cf83a | 9687 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9688 | |
38c1f2d7 | 9689 | (define_insn "*movdf_update2" |
cd2b37d9 | 9690 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9691 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9692 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9693 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9694 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9695 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9696 | "@ |
5f243543 | 9697 | stfdux %3,%0,%2 |
b7ff3d82 | 9698 | stfdu %3,%2(%0)" |
b54cf83a | 9699 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
4c70a4f3 RK |
9700 | |
9701 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9702 | ||
9703 | (define_peephole | |
9704 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
9705 | (match_operand:DF 1 "memory_operand" "")) | |
9706 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
9707 | (match_operand:DF 3 "memory_operand" ""))] | |
9708 | "TARGET_POWER2 | |
a3170dc6 | 9709 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 RK |
9710 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
9711 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
9712 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
9713 | "lfq%U1%X1 %0,%1") | |
9714 | ||
9715 | (define_peephole | |
9716 | [(set (match_operand:DF 0 "memory_operand" "") | |
9717 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
9718 | (set (match_operand:DF 2 "memory_operand" "") | |
9719 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
9720 | "TARGET_POWER2 | |
a3170dc6 | 9721 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 RK |
9722 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
9723 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
9724 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
9725 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 | 9726 | \f |
c4501e62 JJ |
9727 | ;; TLS support. |
9728 | ||
9729 | ;; "b" output constraint here and on tls_ld to support tls linker optimization. | |
9730 | (define_insn "tls_gd_32" | |
9731 | [(set (match_operand:SI 0 "register_operand" "=b") | |
9732 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
9733 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] | |
9734 | UNSPEC_TLSGD))] | |
9735 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9736 | "addi %0,%1,%2@got@tlsgd") | |
9737 | ||
9738 | (define_insn "tls_gd_64" | |
9739 | [(set (match_operand:DI 0 "register_operand" "=b") | |
9740 | (unspec:DI [(match_operand:DI 1 "register_operand" "b") | |
9741 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] | |
9742 | UNSPEC_TLSGD))] | |
9743 | "HAVE_AS_TLS && TARGET_64BIT" | |
9744 | "addi %0,%1,%2@got@tlsgd") | |
9745 | ||
9746 | (define_insn "tls_ld_32" | |
9747 | [(set (match_operand:SI 0 "register_operand" "=b") | |
9748 | (unspec:SI [(match_operand:SI 1 "register_operand" "b")] | |
9749 | UNSPEC_TLSLD))] | |
9750 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9751 | "addi %0,%1,%&@got@tlsld") | |
9752 | ||
9753 | (define_insn "tls_ld_64" | |
9754 | [(set (match_operand:DI 0 "register_operand" "=b") | |
9755 | (unspec:DI [(match_operand:DI 1 "register_operand" "b")] | |
9756 | UNSPEC_TLSLD))] | |
9757 | "HAVE_AS_TLS && TARGET_64BIT" | |
9758 | "addi %0,%1,%&@got@tlsld") | |
9759 | ||
9760 | (define_insn "tls_dtprel_32" | |
9761 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9762 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
9763 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] | |
9764 | UNSPEC_TLSDTPREL))] | |
9765 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9766 | "addi %0,%1,%2@dtprel") | |
9767 | ||
9768 | (define_insn "tls_dtprel_64" | |
9769 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9770 | (unspec:DI [(match_operand:DI 1 "register_operand" "b") | |
9771 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] | |
9772 | UNSPEC_TLSDTPREL))] | |
9773 | "HAVE_AS_TLS && TARGET_64BIT" | |
9774 | "addi %0,%1,%2@dtprel") | |
9775 | ||
9776 | (define_insn "tls_dtprel_ha_32" | |
9777 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9778 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
9779 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] | |
9780 | UNSPEC_TLSDTPRELHA))] | |
9781 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9782 | "addis %0,%1,%2@dtprel@ha") | |
9783 | ||
9784 | (define_insn "tls_dtprel_ha_64" | |
9785 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9786 | (unspec:DI [(match_operand:DI 1 "register_operand" "b") | |
9787 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] | |
9788 | UNSPEC_TLSDTPRELHA))] | |
9789 | "HAVE_AS_TLS && TARGET_64BIT" | |
9790 | "addis %0,%1,%2@dtprel@ha") | |
9791 | ||
9792 | (define_insn "tls_dtprel_lo_32" | |
9793 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9794 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
9795 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] | |
9796 | UNSPEC_TLSDTPRELLO))] | |
9797 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9798 | "addi %0,%1,%2@dtprel@l") | |
9799 | ||
9800 | (define_insn "tls_dtprel_lo_64" | |
9801 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9802 | (unspec:DI [(match_operand:DI 1 "register_operand" "b") | |
9803 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] | |
9804 | UNSPEC_TLSDTPRELLO))] | |
9805 | "HAVE_AS_TLS && TARGET_64BIT" | |
9806 | "addi %0,%1,%2@dtprel@l") | |
9807 | ||
9808 | (define_insn "tls_got_dtprel_32" | |
9809 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9810 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
9811 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] | |
9812 | UNSPEC_TLSGOTDTPREL))] | |
9813 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9814 | "lwz %0,%2@got@dtprel(%1)") | |
9815 | ||
9816 | (define_insn "tls_got_dtprel_64" | |
9817 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9818 | (unspec:DI [(match_operand:DI 1 "register_operand" "b") | |
9819 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] | |
9820 | UNSPEC_TLSGOTDTPREL))] | |
9821 | "HAVE_AS_TLS && TARGET_64BIT" | |
9822 | "ld %0,%2@got@dtprel(%1)") | |
9823 | ||
9824 | (define_insn "tls_tprel_32" | |
9825 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9826 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
9827 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] | |
9828 | UNSPEC_TLSTPREL))] | |
9829 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9830 | "addi %0,%1,%2@tprel") | |
9831 | ||
9832 | (define_insn "tls_tprel_64" | |
9833 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9834 | (unspec:DI [(match_operand:DI 1 "register_operand" "b") | |
9835 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] | |
9836 | UNSPEC_TLSTPREL))] | |
9837 | "HAVE_AS_TLS && TARGET_64BIT" | |
9838 | "addi %0,%1,%2@tprel") | |
9839 | ||
9840 | (define_insn "tls_tprel_ha_32" | |
9841 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9842 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
9843 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] | |
9844 | UNSPEC_TLSTPRELHA))] | |
9845 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9846 | "addis %0,%1,%2@tprel@ha") | |
9847 | ||
9848 | (define_insn "tls_tprel_ha_64" | |
9849 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9850 | (unspec:DI [(match_operand:DI 1 "register_operand" "b") | |
9851 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] | |
9852 | UNSPEC_TLSTPRELHA))] | |
9853 | "HAVE_AS_TLS && TARGET_64BIT" | |
9854 | "addis %0,%1,%2@tprel@ha") | |
9855 | ||
9856 | (define_insn "tls_tprel_lo_32" | |
9857 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9858 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
9859 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] | |
9860 | UNSPEC_TLSTPRELLO))] | |
9861 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9862 | "addi %0,%1,%2@tprel@l") | |
9863 | ||
9864 | (define_insn "tls_tprel_lo_64" | |
9865 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9866 | (unspec:DI [(match_operand:DI 1 "register_operand" "b") | |
9867 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] | |
9868 | UNSPEC_TLSTPRELLO))] | |
9869 | "HAVE_AS_TLS && TARGET_64BIT" | |
9870 | "addi %0,%1,%2@tprel@l") | |
9871 | ||
9872 | ;; "b" output contraint here and on tls_tls input to support linker tls | |
9873 | ;; optimization. The linker may edit the instructions emitted by a | |
9874 | ;; tls_got_tprel/tls_tls pair to addis,addi. | |
9875 | (define_insn "tls_got_tprel_32" | |
9876 | [(set (match_operand:SI 0 "register_operand" "=b") | |
9877 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
9878 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] | |
9879 | UNSPEC_TLSGOTTPREL))] | |
9880 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9881 | "lwz %0,%2@got@tprel(%1)") | |
9882 | ||
9883 | (define_insn "tls_got_tprel_64" | |
9884 | [(set (match_operand:DI 0 "register_operand" "=b") | |
9885 | (unspec:DI [(match_operand:DI 1 "register_operand" "b") | |
9886 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] | |
9887 | UNSPEC_TLSGOTTPREL))] | |
9888 | "HAVE_AS_TLS && TARGET_64BIT" | |
9889 | "ld %0,%2@got@tprel(%1)") | |
9890 | ||
9891 | (define_insn "tls_tls_32" | |
9892 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9893 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
9894 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] | |
9895 | UNSPEC_TLSTLS))] | |
9896 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9897 | "add %0,%1,%2@tls") | |
9898 | ||
9899 | (define_insn "tls_tls_64" | |
9900 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9901 | (unspec:DI [(match_operand:DI 1 "register_operand" "b") | |
9902 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] | |
9903 | UNSPEC_TLSTLS))] | |
9904 | "HAVE_AS_TLS && TARGET_64BIT" | |
9905 | "add %0,%1,%2@tls") | |
9906 | \f | |
1fd4e8c1 RK |
9907 | ;; Next come insns related to the calling sequence. |
9908 | ;; | |
9909 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9910 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9911 | |
9912 | (define_expand "allocate_stack" | |
52d3af72 | 9913 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9914 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9915 | (set (reg 1) | |
9916 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9917 | "" |
9918 | " | |
4697a36c | 9919 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9920 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9921 | rtx neg_op0; |
1fd4e8c1 RK |
9922 | |
9923 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9924 | |
a157febd GK |
9925 | /* Check stack bounds if necessary. */ |
9926 | if (current_function_limit_stack) | |
9927 | { | |
9928 | rtx available; | |
9929 | available = expand_binop (Pmode, sub_optab, | |
9930 | stack_pointer_rtx, stack_limit_rtx, | |
9931 | NULL_RTX, 1, OPTAB_WIDEN); | |
9932 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9933 | } | |
9934 | ||
e9a25f70 JL |
9935 | if (GET_CODE (operands[1]) != CONST_INT |
9936 | || INTVAL (operands[1]) < -32767 | |
9937 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9938 | { |
9939 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9940 | if (TARGET_32BIT) |
e9a25f70 | 9941 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9942 | else |
e9a25f70 | 9943 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9944 | } |
9945 | else | |
e9a25f70 | 9946 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9947 | |
38c1f2d7 MM |
9948 | if (TARGET_UPDATE) |
9949 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
9950 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 9951 | |
38c1f2d7 MM |
9952 | else |
9953 | { | |
9954 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9955 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9956 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9957 | } |
e9a25f70 JL |
9958 | |
9959 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9960 | DONE; |
9961 | }") | |
59257ff7 RK |
9962 | |
9963 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9964 | ;; save the stack pointer at function level since we are careful to | |
9965 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9966 | ;; when we restore the stack pointer. | |
9967 | ;; | |
9968 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9969 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9970 | ;; save area is a memory location. | |
9971 | ||
9972 | (define_expand "save_stack_function" | |
ff381587 MM |
9973 | [(match_operand 0 "any_operand" "") |
9974 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9975 | "" |
ff381587 | 9976 | "DONE;") |
59257ff7 RK |
9977 | |
9978 | (define_expand "restore_stack_function" | |
ff381587 MM |
9979 | [(match_operand 0 "any_operand" "") |
9980 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9981 | "" |
ff381587 | 9982 | "DONE;") |
59257ff7 RK |
9983 | |
9984 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9985 | [(use (match_operand 0 "register_operand" "")) |
9986 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9987 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9988 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9989 | "" |
9990 | " | |
dfdfa60f DE |
9991 | { |
9992 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9993 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9994 | }") |
59257ff7 RK |
9995 | |
9996 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9997 | [(match_operand 0 "memory_operand" "") |
9998 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9999 | "" |
10000 | " | |
10001 | { | |
a260abc9 | 10002 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
10003 | |
10004 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 10005 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
10006 | emit_move_insn (operand_subword (operands[0], 0, 0, |
10007 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
10008 | temp); |
10009 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
10010 | operands[1]); | |
59257ff7 RK |
10011 | DONE; |
10012 | }") | |
7e69e155 | 10013 | |
59257ff7 | 10014 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
10015 | [(match_operand 0 "register_operand" "") |
10016 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
10017 | "" |
10018 | " | |
10019 | { | |
a260abc9 | 10020 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
10021 | |
10022 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
10023 | emit_move_insn (temp, |
10024 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
10025 | emit_move_insn (operands[0], | |
c5c76735 JL |
10026 | operand_subword (operands[1], 1, 0, |
10027 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 10028 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
10029 | DONE; |
10030 | }") | |
9ebbca7d GK |
10031 | \f |
10032 | ;; TOC register handling. | |
b6c9286a | 10033 | |
9ebbca7d | 10034 | ;; Code to initialize the TOC register... |
f0f6a223 | 10035 | |
9ebbca7d | 10036 | (define_insn "load_toc_aix_si" |
e72247f4 | 10037 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
615158e2 | 10038 | (unspec:SI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 10039 | (use (reg:SI 2))])] |
2bfcf297 | 10040 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
10041 | "* |
10042 | { | |
9ebbca7d GK |
10043 | char buf[30]; |
10044 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 10045 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10046 | operands[2] = gen_rtx_REG (Pmode, 2); |
10047 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
10048 | }" |
10049 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
10050 | |
10051 | (define_insn "load_toc_aix_di" | |
e72247f4 | 10052 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
615158e2 | 10053 | (unspec:DI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 10054 | (use (reg:DI 2))])] |
2bfcf297 | 10055 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
10056 | "* |
10057 | { | |
10058 | char buf[30]; | |
f585a356 DE |
10059 | #ifdef TARGET_RELOCATABLE |
10060 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
10061 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
10062 | #else | |
9ebbca7d | 10063 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 10064 | #endif |
2bfcf297 DB |
10065 | if (TARGET_ELF) |
10066 | strcat (buf, \"@toc\"); | |
a8a05998 | 10067 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10068 | operands[2] = gen_rtx_REG (Pmode, 2); |
10069 | return \"ld %0,%1(%2)\"; | |
10070 | }" | |
10071 | [(set_attr "type" "load")]) | |
10072 | ||
10073 | (define_insn "load_toc_v4_pic_si" | |
10074 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 | 10075 | (unspec:SI [(const_int 0)] UNSPEC_TOC))] |
f607bc57 | 10076 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
10077 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
10078 | [(set_attr "type" "branch") | |
10079 | (set_attr "length" "4")]) | |
10080 | ||
9ebbca7d GK |
10081 | (define_insn "load_toc_v4_PIC_1" |
10082 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10083 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 | 10084 | (use (unspec [(match_dup 1)] UNSPEC_TOC))] |
20b71b17 | 10085 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 10086 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
10087 | [(set_attr "type" "branch") |
10088 | (set_attr "length" "4")]) | |
10089 | ||
10090 | (define_insn "load_toc_v4_PIC_1b" | |
10091 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10092 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 JJ |
10093 | (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] |
10094 | UNSPEC_TOCPTR))] | |
20b71b17 | 10095 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
c4501e62 | 10096 | "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1" |
9ebbca7d GK |
10097 | [(set_attr "type" "branch") |
10098 | (set_attr "length" "8")]) | |
10099 | ||
10100 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 10101 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 10102 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
10103 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
10104 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 10105 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
10106 | "{l|lwz} %0,%2-%3(%1)" |
10107 | [(set_attr "type" "load")]) | |
10108 | ||
ee890fe2 SS |
10109 | (define_insn "load_macho_picbase" |
10110 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 JJ |
10111 | (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] |
10112 | UNSPEC_LD_MPIC))] | |
ee890fe2 | 10113 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" |
f51eee6a | 10114 | "bcl 20,31,%1\\n%1:" |
ee890fe2 SS |
10115 | [(set_attr "type" "branch") |
10116 | (set_attr "length" "4")]) | |
10117 | ||
f51eee6a GK |
10118 | (define_insn "macho_correct_pic" |
10119 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
8291cc0e | 10120 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
f51eee6a GK |
10121 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "s") |
10122 | (match_operand:SI 3 "immediate_operand" "s")] | |
615158e2 | 10123 | UNSPEC_MPIC_CORRECT)))] |
f51eee6a | 10124 | "DEFAULT_ABI == ABI_DARWIN" |
8291cc0e | 10125 | "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)" |
f51eee6a GK |
10126 | [(set_attr "length" "8")]) |
10127 | ||
9ebbca7d GK |
10128 | ;; If the TOC is shared over a translation unit, as happens with all |
10129 | ;; the kinds of PIC that we support, we need to restore the TOC | |
10130 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 10131 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
10132 | |
10133 | (define_expand "builtin_setjmp_receiver" | |
10134 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 10135 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
10136 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
10137 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
10138 | " |
10139 | { | |
84d7dd4a | 10140 | #if TARGET_MACHO |
f51eee6a GK |
10141 | if (DEFAULT_ABI == ABI_DARWIN) |
10142 | { | |
d24652ee | 10143 | const char *picbase = machopic_function_base_name (); |
485bad26 | 10144 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); |
f51eee6a GK |
10145 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
10146 | rtx tmplabrtx; | |
10147 | char tmplab[20]; | |
10148 | ||
10149 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
10150 | CODE_LABEL_NUMBER (operands[0])); | |
485bad26 | 10151 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); |
f51eee6a GK |
10152 | |
10153 | emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); | |
10154 | emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
10155 | } | |
10156 | else | |
84d7dd4a | 10157 | #endif |
f51eee6a | 10158 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
10159 | DONE; |
10160 | }") | |
10161 | \f | |
10162 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
10163 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
10164 | ;; pointer to its TOC, and whose third word contains a value to place in the |
10165 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 10166 | ;; "trampoline" need not have any executable code. |
b6c9286a | 10167 | |
cccf3bdc DE |
10168 | (define_expand "call_indirect_aix32" |
10169 | [(set (match_dup 2) | |
10170 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
10171 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10172 | (reg:SI 2)) | |
10173 | (set (reg:SI 2) | |
10174 | (mem:SI (plus:SI (match_dup 0) | |
10175 | (const_int 4)))) | |
10176 | (set (reg:SI 11) | |
10177 | (mem:SI (plus:SI (match_dup 0) | |
10178 | (const_int 8)))) | |
10179 | (parallel [(call (mem:SI (match_dup 2)) | |
10180 | (match_operand 1 "" "")) | |
10181 | (use (reg:SI 2)) | |
10182 | (use (reg:SI 11)) | |
10183 | (set (reg:SI 2) | |
10184 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10185 | (clobber (scratch:SI))])] | |
10186 | "TARGET_32BIT" | |
10187 | " | |
10188 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10189 | |
cccf3bdc DE |
10190 | (define_expand "call_indirect_aix64" |
10191 | [(set (match_dup 2) | |
10192 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
10193 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10194 | (reg:DI 2)) | |
10195 | (set (reg:DI 2) | |
10196 | (mem:DI (plus:DI (match_dup 0) | |
10197 | (const_int 8)))) | |
10198 | (set (reg:DI 11) | |
10199 | (mem:DI (plus:DI (match_dup 0) | |
10200 | (const_int 16)))) | |
10201 | (parallel [(call (mem:SI (match_dup 2)) | |
10202 | (match_operand 1 "" "")) | |
10203 | (use (reg:DI 2)) | |
10204 | (use (reg:DI 11)) | |
10205 | (set (reg:DI 2) | |
10206 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10207 | (clobber (scratch:SI))])] | |
10208 | "TARGET_64BIT" | |
10209 | " | |
10210 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 10211 | |
cccf3bdc DE |
10212 | (define_expand "call_value_indirect_aix32" |
10213 | [(set (match_dup 3) | |
10214 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10215 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10216 | (reg:SI 2)) | |
10217 | (set (reg:SI 2) | |
10218 | (mem:SI (plus:SI (match_dup 1) | |
10219 | (const_int 4)))) | |
10220 | (set (reg:SI 11) | |
10221 | (mem:SI (plus:SI (match_dup 1) | |
10222 | (const_int 8)))) | |
10223 | (parallel [(set (match_operand 0 "" "") | |
10224 | (call (mem:SI (match_dup 3)) | |
10225 | (match_operand 2 "" ""))) | |
10226 | (use (reg:SI 2)) | |
10227 | (use (reg:SI 11)) | |
10228 | (set (reg:SI 2) | |
10229 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10230 | (clobber (scratch:SI))])] | |
10231 | "TARGET_32BIT" | |
10232 | " | |
10233 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10234 | |
cccf3bdc DE |
10235 | (define_expand "call_value_indirect_aix64" |
10236 | [(set (match_dup 3) | |
10237 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10238 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10239 | (reg:DI 2)) | |
10240 | (set (reg:DI 2) | |
10241 | (mem:DI (plus:DI (match_dup 1) | |
10242 | (const_int 8)))) | |
10243 | (set (reg:DI 11) | |
10244 | (mem:DI (plus:DI (match_dup 1) | |
10245 | (const_int 16)))) | |
10246 | (parallel [(set (match_operand 0 "" "") | |
10247 | (call (mem:SI (match_dup 3)) | |
10248 | (match_operand 2 "" ""))) | |
10249 | (use (reg:DI 2)) | |
10250 | (use (reg:DI 11)) | |
10251 | (set (reg:DI 2) | |
10252 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10253 | (clobber (scratch:SI))])] | |
10254 | "TARGET_64BIT" | |
10255 | " | |
10256 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 10257 | |
b6c9286a | 10258 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 10259 | (define_expand "call" |
a260abc9 | 10260 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 10261 | (match_operand 1 "" "")) |
4697a36c | 10262 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
10263 | (clobber (scratch:SI))])] |
10264 | "" | |
10265 | " | |
10266 | { | |
ee890fe2 | 10267 | #if TARGET_MACHO |
ab82a49f | 10268 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10269 | operands[0] = machopic_indirect_call_target (operands[0]); |
10270 | #endif | |
10271 | ||
1fd4e8c1 RK |
10272 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
10273 | abort (); | |
10274 | ||
10275 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 10276 | |
6a4cee5f | 10277 | if (GET_CODE (operands[0]) != SYMBOL_REF |
473f51b6 | 10278 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) |
6a4cee5f | 10279 | || (INTVAL (operands[2]) & CALL_LONG) != 0) |
1fd4e8c1 | 10280 | { |
6a4cee5f MM |
10281 | if (INTVAL (operands[2]) & CALL_LONG) |
10282 | operands[0] = rs6000_longcall_ref (operands[0]); | |
10283 | ||
cccf3bdc | 10284 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10285 | || DEFAULT_ABI == ABI_DARWIN) |
cccf3bdc | 10286 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10287 | |
cccf3bdc DE |
10288 | else if (DEFAULT_ABI == ABI_AIX) |
10289 | { | |
10290 | /* AIX function pointers are really pointers to a three word | |
10291 | area. */ | |
10292 | emit_call_insn (TARGET_32BIT | |
10293 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
10294 | operands[0]), | |
10295 | operands[1]) | |
10296 | : gen_call_indirect_aix64 (force_reg (DImode, | |
10297 | operands[0]), | |
10298 | operands[1])); | |
10299 | DONE; | |
b6c9286a | 10300 | } |
cccf3bdc DE |
10301 | else |
10302 | abort (); | |
1fd4e8c1 RK |
10303 | } |
10304 | }") | |
10305 | ||
10306 | (define_expand "call_value" | |
10307 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 10308 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 10309 | (match_operand 2 "" ""))) |
4697a36c | 10310 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
10311 | (clobber (scratch:SI))])] |
10312 | "" | |
10313 | " | |
10314 | { | |
ee890fe2 | 10315 | #if TARGET_MACHO |
ab82a49f | 10316 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10317 | operands[1] = machopic_indirect_call_target (operands[1]); |
10318 | #endif | |
10319 | ||
1fd4e8c1 RK |
10320 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
10321 | abort (); | |
10322 | ||
10323 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 10324 | |
6a4cee5f | 10325 | if (GET_CODE (operands[1]) != SYMBOL_REF |
473f51b6 | 10326 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) |
6a4cee5f | 10327 | || (INTVAL (operands[3]) & CALL_LONG) != 0) |
1fd4e8c1 | 10328 | { |
6756293c | 10329 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
10330 | operands[1] = rs6000_longcall_ref (operands[1]); |
10331 | ||
cccf3bdc | 10332 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10333 | || DEFAULT_ABI == ABI_DARWIN) |
cccf3bdc | 10334 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10335 | |
cccf3bdc DE |
10336 | else if (DEFAULT_ABI == ABI_AIX) |
10337 | { | |
10338 | /* AIX function pointers are really pointers to a three word | |
10339 | area. */ | |
10340 | emit_call_insn (TARGET_32BIT | |
10341 | ? gen_call_value_indirect_aix32 (operands[0], | |
10342 | force_reg (SImode, | |
10343 | operands[1]), | |
10344 | operands[2]) | |
10345 | : gen_call_value_indirect_aix64 (operands[0], | |
10346 | force_reg (DImode, | |
10347 | operands[1]), | |
10348 | operands[2])); | |
10349 | DONE; | |
b6c9286a | 10350 | } |
cccf3bdc DE |
10351 | else |
10352 | abort (); | |
1fd4e8c1 RK |
10353 | } |
10354 | }") | |
10355 | ||
04780ee7 | 10356 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 10357 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10358 | ;; either the function was not prototyped, or it was prototyped as a |
10359 | ;; variable argument function. It is > 0 if FP registers were passed | |
10360 | ;; and < 0 if they were not. | |
04780ee7 | 10361 | |
a260abc9 | 10362 | (define_insn "*call_local32" |
4697a36c MM |
10363 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
10364 | (match_operand 1 "" "g,g")) | |
10365 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10366 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 10367 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
10368 | "* |
10369 | { | |
6a4cee5f MM |
10370 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
10371 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10372 | ||
10373 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10374 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 10375 | |
a226df46 | 10376 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 10377 | }" |
b7ff3d82 DE |
10378 | [(set_attr "type" "branch") |
10379 | (set_attr "length" "4,8")]) | |
04780ee7 | 10380 | |
a260abc9 DE |
10381 | (define_insn "*call_local64" |
10382 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10383 | (match_operand 1 "" "g,g")) | |
10384 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10385 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10386 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10387 | "* | |
10388 | { | |
10389 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10390 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10391 | ||
10392 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10393 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10394 | ||
10395 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
10396 | }" | |
10397 | [(set_attr "type" "branch") | |
10398 | (set_attr "length" "4,8")]) | |
10399 | ||
cccf3bdc | 10400 | (define_insn "*call_value_local32" |
d18dba68 | 10401 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10402 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
10403 | (match_operand 2 "" "g,g"))) | |
10404 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10405 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10406 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10407 | "* | |
10408 | { | |
10409 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10410 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10411 | ||
10412 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10413 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10414 | ||
10415 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10416 | }" | |
10417 | [(set_attr "type" "branch") | |
10418 | (set_attr "length" "4,8")]) | |
10419 | ||
10420 | ||
cccf3bdc | 10421 | (define_insn "*call_value_local64" |
d18dba68 | 10422 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10423 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
10424 | (match_operand 2 "" "g,g"))) | |
10425 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10426 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10427 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10428 | "* | |
10429 | { | |
10430 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10431 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10432 | ||
10433 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10434 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10435 | ||
10436 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10437 | }" | |
10438 | [(set_attr "type" "branch") | |
10439 | (set_attr "length" "4,8")]) | |
10440 | ||
04780ee7 | 10441 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 10442 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 10443 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10444 | ;; either the function was not prototyped, or it was prototyped as a |
10445 | ;; variable argument function. It is > 0 if FP registers were passed | |
10446 | ;; and < 0 if they were not. | |
04780ee7 | 10447 | |
cccf3bdc DE |
10448 | (define_insn "*call_indirect_nonlocal_aix32" |
10449 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
10450 | (match_operand 1 "" "g")) | |
10451 | (use (reg:SI 2)) | |
10452 | (use (reg:SI 11)) | |
10453 | (set (reg:SI 2) | |
10454 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 10455 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10456 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10457 | "b%T0l\;{l|lwz} 2,20(1)" | |
10458 | [(set_attr "type" "jmpreg") | |
10459 | (set_attr "length" "8")]) | |
10460 | ||
a260abc9 | 10461 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10462 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10463 | (match_operand 1 "" "g")) |
10464 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10465 | (clobber (match_scratch:SI 3 "=l"))] | |
10466 | "TARGET_32BIT | |
10467 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10468 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10469 | "bl %z0\;%." |
b7ff3d82 | 10470 | [(set_attr "type" "branch") |
cccf3bdc DE |
10471 | (set_attr "length" "8")]) |
10472 | ||
10473 | (define_insn "*call_indirect_nonlocal_aix64" | |
10474 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
10475 | (match_operand 1 "" "g")) | |
10476 | (use (reg:DI 2)) | |
10477 | (use (reg:DI 11)) | |
10478 | (set (reg:DI 2) | |
10479 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 10480 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10481 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10482 | "b%T0l\;ld 2,40(1)" | |
10483 | [(set_attr "type" "jmpreg") | |
10484 | (set_attr "length" "8")]) | |
59313e4e | 10485 | |
a260abc9 | 10486 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10487 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10488 | (match_operand 1 "" "g")) |
10489 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10490 | (clobber (match_scratch:SI 3 "=l"))] | |
9ebbca7d GK |
10491 | "TARGET_64BIT |
10492 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10493 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10494 | "bl %z0\;%." |
a260abc9 | 10495 | [(set_attr "type" "branch") |
cccf3bdc | 10496 | (set_attr "length" "8")]) |
7509c759 | 10497 | |
cccf3bdc | 10498 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10499 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10500 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
10501 | (match_operand 2 "" "g"))) | |
10502 | (use (reg:SI 2)) | |
10503 | (use (reg:SI 11)) | |
10504 | (set (reg:SI 2) | |
10505 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10506 | (clobber (match_scratch:SI 3 "=l"))] | |
10507 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
10508 | "b%T1l\;{l|lwz} 2,20(1)" | |
10509 | [(set_attr "type" "jmpreg") | |
10510 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10511 | |
cccf3bdc | 10512 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10513 | [(set (match_operand 0 "" "") |
cc4d5fec | 10514 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10515 | (match_operand 2 "" "g"))) |
10516 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10517 | (clobber (match_scratch:SI 4 "=l"))] | |
10518 | "TARGET_32BIT | |
10519 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10520 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10521 | "bl %z1\;%." |
b7ff3d82 | 10522 | [(set_attr "type" "branch") |
cccf3bdc | 10523 | (set_attr "length" "8")]) |
04780ee7 | 10524 | |
cccf3bdc | 10525 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10526 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10527 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
10528 | (match_operand 2 "" "g"))) | |
10529 | (use (reg:DI 2)) | |
10530 | (use (reg:DI 11)) | |
10531 | (set (reg:DI 2) | |
10532 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10533 | (clobber (match_scratch:SI 3 "=l"))] | |
10534 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
10535 | "b%T1l\;ld 2,40(1)" | |
10536 | [(set_attr "type" "jmpreg") | |
10537 | (set_attr "length" "8")]) | |
10538 | ||
10539 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10540 | [(set (match_operand 0 "" "") |
cc4d5fec | 10541 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10542 | (match_operand 2 "" "g"))) |
10543 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10544 | (clobber (match_scratch:SI 4 "=l"))] | |
9ebbca7d GK |
10545 | "TARGET_64BIT |
10546 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10547 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10548 | "bl %z1\;%." |
10549 | [(set_attr "type" "branch") | |
10550 | (set_attr "length" "8")]) | |
10551 | ||
10552 | ;; A function pointer under System V is just a normal pointer | |
10553 | ;; operands[0] is the function pointer | |
10554 | ;; operands[1] is the stack size to clean up | |
10555 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10556 | ;; which indicates how to set cr1 | |
10557 | ||
a5c76ee6 ZW |
10558 | (define_insn "*call_indirect_nonlocal_sysv" |
10559 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) | |
10560 | (match_operand 1 "" "g,g")) | |
10561 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10562 | (clobber (match_scratch:SI 3 "=l,l"))] | |
50d440bc | 10563 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10564 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10565 | { |
cccf3bdc | 10566 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10567 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10568 | |
cccf3bdc | 10569 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10570 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10571 | |
a5c76ee6 ZW |
10572 | return "b%T0l"; |
10573 | } | |
10574 | [(set_attr "type" "jmpreg,jmpreg") | |
10575 | (set_attr "length" "4,8")]) | |
cccf3bdc | 10576 | |
a5c76ee6 ZW |
10577 | (define_insn "*call_nonlocal_sysv" |
10578 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10579 | (match_operand 1 "" "g,g")) | |
10580 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10581 | (clobber (match_scratch:SI 3 "=l,l"))] | |
50d440bc | 10582 | "(DEFAULT_ABI == ABI_V4 |
a5c76ee6 ZW |
10583 | || DEFAULT_ABI == ABI_DARWIN) |
10584 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10585 | { | |
10586 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10587 | output_asm_insn ("crxor 6,6,6", operands); | |
10588 | ||
10589 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10590 | output_asm_insn ("creqv 6,6,6", operands); | |
10591 | ||
10592 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; | |
10593 | } | |
10594 | [(set_attr "type" "branch,branch") | |
10595 | (set_attr "length" "4,8")]) | |
10596 | ||
10597 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10598 | [(set (match_operand 0 "" "") |
a5c76ee6 ZW |
10599 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) |
10600 | (match_operand 2 "" "g,g"))) | |
10601 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10602 | (clobber (match_scratch:SI 4 "=l,l"))] | |
50d440bc | 10603 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10604 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10605 | { |
6a4cee5f | 10606 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10607 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10608 | |
10609 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10610 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10611 | |
a5c76ee6 ZW |
10612 | return "b%T1l"; |
10613 | } | |
10614 | [(set_attr "type" "jmpreg,jmpreg") | |
10615 | (set_attr "length" "4,8")]) | |
10616 | ||
10617 | (define_insn "*call_value_nonlocal_sysv" | |
10618 | [(set (match_operand 0 "" "") | |
10619 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10620 | (match_operand 2 "" "g,g"))) | |
10621 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10622 | (clobber (match_scratch:SI 4 "=l,l"))] | |
50d440bc | 10623 | "(DEFAULT_ABI == ABI_V4 |
a5c76ee6 ZW |
10624 | || DEFAULT_ABI == ABI_DARWIN) |
10625 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10626 | { | |
10627 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10628 | output_asm_insn ("crxor 6,6,6", operands); | |
10629 | ||
10630 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10631 | output_asm_insn ("creqv 6,6,6", operands); | |
10632 | ||
10633 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; | |
10634 | } | |
10635 | [(set_attr "type" "branch,branch") | |
10636 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10637 | |
10638 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10639 | (define_expand "untyped_call" |
10640 | [(parallel [(call (match_operand 0 "" "") | |
10641 | (const_int 0)) | |
10642 | (match_operand 1 "" "") | |
10643 | (match_operand 2 "" "")])] | |
10644 | "" | |
10645 | " | |
10646 | { | |
10647 | int i; | |
10648 | ||
7d70b8b2 | 10649 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10650 | |
10651 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10652 | { | |
10653 | rtx set = XVECEXP (operands[2], 0, i); | |
10654 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10655 | } | |
10656 | ||
10657 | /* The optimizer does not know that the call sets the function value | |
10658 | registers we stored in the result block. We avoid problems by | |
10659 | claiming that all hard registers are used and clobbered at this | |
10660 | point. */ | |
10661 | emit_insn (gen_blockage ()); | |
10662 | ||
10663 | DONE; | |
10664 | }") | |
10665 | ||
5e1bf043 DJ |
10666 | ;; sibling call patterns |
10667 | (define_expand "sibcall" | |
10668 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
10669 | (match_operand 1 "" "")) | |
10670 | (use (match_operand 2 "" "")) | |
fe352c29 | 10671 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
10672 | (return)])] |
10673 | "" | |
10674 | " | |
10675 | { | |
10676 | #if TARGET_MACHO | |
ab82a49f | 10677 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10678 | operands[0] = machopic_indirect_call_target (operands[0]); |
10679 | #endif | |
10680 | ||
10681 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
10682 | abort (); | |
10683 | ||
10684 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 10685 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10686 | |
10687 | }") | |
10688 | ||
10689 | ;; this and similar patterns must be marked as using LR, otherwise | |
10690 | ;; dataflow will try to delete the store into it. This is true | |
10691 | ;; even when the actual reg to jump to is in CTR, when LR was | |
10692 | ;; saved and restored around the PIC-setting BCL. | |
10693 | (define_insn "*sibcall_local32" | |
10694 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
10695 | (match_operand 1 "" "g,g")) | |
10696 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10697 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10698 | (return)] |
10699 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
10700 | "* | |
10701 | { | |
10702 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10703 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10704 | ||
10705 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10706 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10707 | ||
10708 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10709 | }" | |
10710 | [(set_attr "type" "branch") | |
10711 | (set_attr "length" "4,8")]) | |
10712 | ||
10713 | (define_insn "*sibcall_local64" | |
10714 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10715 | (match_operand 1 "" "g,g")) | |
10716 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10717 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10718 | (return)] |
10719 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10720 | "* | |
10721 | { | |
10722 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10723 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10724 | ||
10725 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10726 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10727 | ||
10728 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10729 | }" | |
10730 | [(set_attr "type" "branch") | |
10731 | (set_attr "length" "4,8")]) | |
10732 | ||
10733 | (define_insn "*sibcall_value_local32" | |
10734 | [(set (match_operand 0 "" "") | |
10735 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
10736 | (match_operand 2 "" "g,g"))) | |
10737 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10738 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10739 | (return)] |
10740 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10741 | "* | |
10742 | { | |
10743 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10744 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10745 | ||
10746 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10747 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10748 | ||
10749 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10750 | }" | |
10751 | [(set_attr "type" "branch") | |
10752 | (set_attr "length" "4,8")]) | |
10753 | ||
10754 | ||
10755 | (define_insn "*sibcall_value_local64" | |
10756 | [(set (match_operand 0 "" "") | |
10757 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
10758 | (match_operand 2 "" "g,g"))) | |
10759 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10760 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10761 | (return)] |
10762 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10763 | "* | |
10764 | { | |
10765 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10766 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10767 | ||
10768 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10769 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10770 | ||
10771 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10772 | }" | |
10773 | [(set_attr "type" "branch") | |
10774 | (set_attr "length" "4,8")]) | |
10775 | ||
10776 | (define_insn "*sibcall_nonlocal_aix32" | |
10777 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
10778 | (match_operand 1 "" "g")) | |
10779 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10780 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10781 | (return)] |
10782 | "TARGET_32BIT | |
10783 | && DEFAULT_ABI == ABI_AIX | |
10784 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10785 | "b %z0" | |
10786 | [(set_attr "type" "branch") | |
10787 | (set_attr "length" "4")]) | |
10788 | ||
10789 | (define_insn "*sibcall_nonlocal_aix64" | |
10790 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
10791 | (match_operand 1 "" "g")) | |
10792 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10793 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10794 | (return)] |
10795 | "TARGET_64BIT | |
10796 | && DEFAULT_ABI == ABI_AIX | |
10797 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10798 | "b %z0" | |
10799 | [(set_attr "type" "branch") | |
10800 | (set_attr "length" "4")]) | |
10801 | ||
10802 | (define_insn "*sibcall_value_nonlocal_aix32" | |
10803 | [(set (match_operand 0 "" "") | |
10804 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
10805 | (match_operand 2 "" "g"))) | |
10806 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10807 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10808 | (return)] |
10809 | "TARGET_32BIT | |
10810 | && DEFAULT_ABI == ABI_AIX | |
10811 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10812 | "b %z1" | |
10813 | [(set_attr "type" "branch") | |
10814 | (set_attr "length" "4")]) | |
10815 | ||
10816 | (define_insn "*sibcall_value_nonlocal_aix64" | |
10817 | [(set (match_operand 0 "" "") | |
10818 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
10819 | (match_operand 2 "" "g"))) | |
10820 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10821 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10822 | (return)] |
10823 | "TARGET_64BIT | |
10824 | && DEFAULT_ABI == ABI_AIX | |
10825 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10826 | "b %z1" | |
10827 | [(set_attr "type" "branch") | |
10828 | (set_attr "length" "4")]) | |
10829 | ||
10830 | (define_insn "*sibcall_nonlocal_sysv" | |
10831 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10832 | (match_operand 1 "" "")) | |
10833 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 10834 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10835 | (return)] |
10836 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10837 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10838 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
10839 | "* | |
10840 | { | |
10841 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10842 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10843 | ||
10844 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10845 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10846 | ||
10847 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; | |
10848 | }" | |
10849 | [(set_attr "type" "branch,branch") | |
10850 | (set_attr "length" "4,8")]) | |
10851 | ||
10852 | (define_expand "sibcall_value" | |
10853 | [(parallel [(set (match_operand 0 "register_operand" "") | |
10854 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
10855 | (match_operand 2 "" ""))) | |
10856 | (use (match_operand 3 "" "")) | |
fe352c29 | 10857 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
10858 | (return)])] |
10859 | "" | |
10860 | " | |
10861 | { | |
10862 | #if TARGET_MACHO | |
ab82a49f | 10863 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10864 | operands[1] = machopic_indirect_call_target (operands[1]); |
10865 | #endif | |
10866 | ||
10867 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
10868 | abort (); | |
10869 | ||
10870 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 10871 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10872 | |
10873 | }") | |
10874 | ||
10875 | (define_insn "*sibcall_value_nonlocal_sysv" | |
10876 | [(set (match_operand 0 "" "") | |
10877 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10878 | (match_operand 2 "" ""))) | |
10879 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10880 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10881 | (return)] |
10882 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10883 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10884 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
10885 | "* | |
10886 | { | |
10887 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10888 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10889 | ||
10890 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10891 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10892 | ||
10893 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; | |
10894 | }" | |
10895 | [(set_attr "type" "branch,branch") | |
10896 | (set_attr "length" "4,8")]) | |
10897 | ||
10898 | (define_expand "sibcall_epilogue" | |
10899 | [(use (const_int 0))] | |
10900 | "TARGET_SCHED_PROLOG" | |
10901 | " | |
10902 | { | |
10903 | rs6000_emit_epilogue (TRUE); | |
10904 | DONE; | |
10905 | }") | |
10906 | ||
e6f948e3 RK |
10907 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
10908 | ;; all of memory. This blocks insns from being moved across this point. | |
10909 | ||
10910 | (define_insn "blockage" | |
615158e2 | 10911 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] |
e6f948e3 RK |
10912 | "" |
10913 | "") | |
1fd4e8c1 RK |
10914 | \f |
10915 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10916 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10917 | ;; |
10918 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10919 | ;; insns, and branches. We store the operands of compares until we see | |
10920 | ;; how it is used. | |
10921 | (define_expand "cmpsi" | |
10922 | [(set (cc0) | |
cd2b37d9 | 10923 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10924 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10925 | "" | |
10926 | " | |
10927 | { | |
10928 | /* Take care of the possibility that operands[1] might be negative but | |
10929 | this might be a logical operation. That insn doesn't exist. */ | |
10930 | if (GET_CODE (operands[1]) == CONST_INT | |
10931 | && INTVAL (operands[1]) < 0) | |
10932 | operands[1] = force_reg (SImode, operands[1]); | |
10933 | ||
10934 | rs6000_compare_op0 = operands[0]; | |
10935 | rs6000_compare_op1 = operands[1]; | |
10936 | rs6000_compare_fp_p = 0; | |
10937 | DONE; | |
10938 | }") | |
10939 | ||
266eb58a DE |
10940 | (define_expand "cmpdi" |
10941 | [(set (cc0) | |
10942 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10943 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10944 | "TARGET_POWERPC64" | |
10945 | " | |
10946 | { | |
10947 | /* Take care of the possibility that operands[1] might be negative but | |
10948 | this might be a logical operation. That insn doesn't exist. */ | |
10949 | if (GET_CODE (operands[1]) == CONST_INT | |
10950 | && INTVAL (operands[1]) < 0) | |
10951 | operands[1] = force_reg (DImode, operands[1]); | |
10952 | ||
10953 | rs6000_compare_op0 = operands[0]; | |
10954 | rs6000_compare_op1 = operands[1]; | |
10955 | rs6000_compare_fp_p = 0; | |
10956 | DONE; | |
10957 | }") | |
10958 | ||
1fd4e8c1 | 10959 | (define_expand "cmpsf" |
cd2b37d9 RK |
10960 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
10961 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10962 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10963 | " |
10964 | { | |
10965 | rs6000_compare_op0 = operands[0]; | |
10966 | rs6000_compare_op1 = operands[1]; | |
10967 | rs6000_compare_fp_p = 1; | |
10968 | DONE; | |
10969 | }") | |
10970 | ||
10971 | (define_expand "cmpdf" | |
cd2b37d9 RK |
10972 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
10973 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 10974 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
10975 | " |
10976 | { | |
10977 | rs6000_compare_op0 = operands[0]; | |
10978 | rs6000_compare_op1 = operands[1]; | |
10979 | rs6000_compare_fp_p = 1; | |
10980 | DONE; | |
10981 | }") | |
10982 | ||
d6f99ca4 | 10983 | (define_expand "cmptf" |
e7a4130e DE |
10984 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
10985 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
a3170dc6 AH |
10986 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT |
10987 | && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
d6f99ca4 DE |
10988 | " |
10989 | { | |
10990 | rs6000_compare_op0 = operands[0]; | |
10991 | rs6000_compare_op1 = operands[1]; | |
10992 | rs6000_compare_fp_p = 1; | |
10993 | DONE; | |
10994 | }") | |
10995 | ||
1fd4e8c1 | 10996 | (define_expand "beq" |
39a10a29 | 10997 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10998 | "" |
39a10a29 | 10999 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11000 | |
11001 | (define_expand "bne" | |
39a10a29 | 11002 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11003 | "" |
39a10a29 | 11004 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 11005 | |
39a10a29 GK |
11006 | (define_expand "bge" |
11007 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11008 | "" |
39a10a29 | 11009 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
11010 | |
11011 | (define_expand "bgt" | |
39a10a29 | 11012 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11013 | "" |
39a10a29 | 11014 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
11015 | |
11016 | (define_expand "ble" | |
39a10a29 | 11017 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11018 | "" |
39a10a29 | 11019 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 11020 | |
39a10a29 GK |
11021 | (define_expand "blt" |
11022 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11023 | "" |
39a10a29 | 11024 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 11025 | |
39a10a29 GK |
11026 | (define_expand "bgeu" |
11027 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11028 | "" |
39a10a29 | 11029 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 11030 | |
39a10a29 GK |
11031 | (define_expand "bgtu" |
11032 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11033 | "" |
39a10a29 | 11034 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 11035 | |
39a10a29 GK |
11036 | (define_expand "bleu" |
11037 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11038 | "" |
39a10a29 | 11039 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 11040 | |
39a10a29 GK |
11041 | (define_expand "bltu" |
11042 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11043 | "" |
39a10a29 | 11044 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11045 | |
1c882ea4 | 11046 | (define_expand "bunordered" |
39a10a29 | 11047 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11048 | "" |
39a10a29 | 11049 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11050 | |
11051 | (define_expand "bordered" | |
39a10a29 | 11052 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11053 | "" |
39a10a29 | 11054 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11055 | |
11056 | (define_expand "buneq" | |
39a10a29 | 11057 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11058 | "" |
39a10a29 | 11059 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
11060 | |
11061 | (define_expand "bunge" | |
39a10a29 | 11062 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11063 | "" |
39a10a29 | 11064 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
11065 | |
11066 | (define_expand "bungt" | |
39a10a29 | 11067 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11068 | "" |
39a10a29 | 11069 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
11070 | |
11071 | (define_expand "bunle" | |
39a10a29 | 11072 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11073 | "" |
39a10a29 | 11074 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
11075 | |
11076 | (define_expand "bunlt" | |
39a10a29 | 11077 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11078 | "" |
39a10a29 | 11079 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
11080 | |
11081 | (define_expand "bltgt" | |
39a10a29 | 11082 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11083 | "" |
39a10a29 | 11084 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 11085 | |
1fd4e8c1 RK |
11086 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
11087 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
11088 | ;; with an scc insns. However, due to the order that combine see the | |
11089 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
11090 | ;; the cases we don't want to handle. | |
11091 | (define_expand "seq" | |
39a10a29 | 11092 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11093 | "" |
39a10a29 | 11094 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11095 | |
11096 | (define_expand "sne" | |
39a10a29 | 11097 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11098 | "" |
11099 | " | |
39a10a29 GK |
11100 | { |
11101 | if (! rs6000_compare_fp_p) | |
1fd4e8c1 RK |
11102 | FAIL; |
11103 | ||
39a10a29 GK |
11104 | rs6000_emit_sCOND (NE, operands[0]); |
11105 | DONE; | |
1fd4e8c1 RK |
11106 | }") |
11107 | ||
b7053a3f GK |
11108 | ;; A >= 0 is best done the portable way for A an integer. |
11109 | (define_expand "sge" | |
39a10a29 | 11110 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11111 | "" |
11112 | " | |
5638268e DE |
11113 | { |
11114 | if (! rs6000_compare_fp_p | |
11115 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
11116 | FAIL; |
11117 | ||
b7053a3f | 11118 | rs6000_emit_sCOND (GE, operands[0]); |
39a10a29 | 11119 | DONE; |
1fd4e8c1 RK |
11120 | }") |
11121 | ||
b7053a3f GK |
11122 | ;; A > 0 is best done using the portable sequence, so fail in that case. |
11123 | (define_expand "sgt" | |
39a10a29 | 11124 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11125 | "" |
11126 | " | |
5638268e | 11127 | { |
b7053a3f | 11128 | if (! rs6000_compare_fp_p |
5638268e | 11129 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) |
1fd4e8c1 RK |
11130 | FAIL; |
11131 | ||
b7053a3f | 11132 | rs6000_emit_sCOND (GT, operands[0]); |
39a10a29 | 11133 | DONE; |
1fd4e8c1 RK |
11134 | }") |
11135 | ||
b7053a3f GK |
11136 | ;; A <= 0 is best done the portable way for A an integer. |
11137 | (define_expand "sle" | |
39a10a29 | 11138 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11139 | "" |
5638268e DE |
11140 | " |
11141 | { | |
11142 | if (! rs6000_compare_fp_p | |
11143 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
11144 | FAIL; | |
11145 | ||
b7053a3f | 11146 | rs6000_emit_sCOND (LE, operands[0]); |
5638268e DE |
11147 | DONE; |
11148 | }") | |
1fd4e8c1 | 11149 | |
b7053a3f GK |
11150 | ;; A < 0 is best done in the portable way for A an integer. |
11151 | (define_expand "slt" | |
39a10a29 | 11152 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11153 | "" |
11154 | " | |
5638268e | 11155 | { |
b7053a3f | 11156 | if (! rs6000_compare_fp_p |
5638268e | 11157 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) |
1fd4e8c1 RK |
11158 | FAIL; |
11159 | ||
b7053a3f | 11160 | rs6000_emit_sCOND (LT, operands[0]); |
39a10a29 | 11161 | DONE; |
1fd4e8c1 RK |
11162 | }") |
11163 | ||
b7053a3f GK |
11164 | (define_expand "sgeu" |
11165 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11166 | "" | |
11167 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") | |
11168 | ||
1fd4e8c1 | 11169 | (define_expand "sgtu" |
39a10a29 | 11170 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11171 | "" |
39a10a29 | 11172 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 11173 | |
b7053a3f GK |
11174 | (define_expand "sleu" |
11175 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11176 | "" | |
11177 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") | |
11178 | ||
1fd4e8c1 | 11179 | (define_expand "sltu" |
39a10a29 | 11180 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11181 | "" |
39a10a29 | 11182 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11183 | |
b7053a3f | 11184 | (define_expand "sunordered" |
39a10a29 | 11185 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11186 | "" |
b7053a3f | 11187 | "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") |
1fd4e8c1 | 11188 | |
b7053a3f | 11189 | (define_expand "sordered" |
39a10a29 | 11190 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11191 | "" |
b7053a3f GK |
11192 | "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") |
11193 | ||
11194 | (define_expand "suneq" | |
11195 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11196 | "" | |
11197 | "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") | |
11198 | ||
11199 | (define_expand "sunge" | |
11200 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11201 | "" | |
11202 | "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") | |
11203 | ||
11204 | (define_expand "sungt" | |
11205 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11206 | "" | |
11207 | "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") | |
11208 | ||
11209 | (define_expand "sunle" | |
11210 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11211 | "" | |
11212 | "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") | |
11213 | ||
11214 | (define_expand "sunlt" | |
11215 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11216 | "" | |
11217 | "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") | |
11218 | ||
11219 | (define_expand "sltgt" | |
11220 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11221 | "" | |
11222 | "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") | |
11223 | ||
1fd4e8c1 RK |
11224 | \f |
11225 | ;; Here are the actual compare insns. | |
acad7ed3 | 11226 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 11227 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11228 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
11229 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
11230 | "" | |
7f340546 | 11231 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
b54cf83a | 11232 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11233 | |
acad7ed3 | 11234 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
11235 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
11236 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
11237 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11238 | "TARGET_POWERPC64" | |
11239 | "cmpd%I2 %0,%1,%2" | |
b54cf83a | 11240 | [(set_attr "type" "cmp")]) |
266eb58a | 11241 | |
f357808b RK |
11242 | ;; If we are comparing a register for equality with a large constant, |
11243 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
11244 | ;; register for the result of the XOR. | |
11245 | ||
11246 | (define_split | |
11247 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 11248 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 11249 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 11250 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
11251 | "find_single_use (operands[0], insn, 0) |
11252 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
11253 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
11254 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
11255 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
11256 | " | |
11257 | { | |
11258 | /* Get the constant we are comparing against, C, and see what it looks like | |
11259 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
11260 | with C to get the sign-extended value. */ | |
11261 | ||
5f59ecb7 | 11262 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 11263 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 11264 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 11265 | |
89e9f3a8 MM |
11266 | operands[4] = GEN_INT (xorv); |
11267 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
11268 | }") |
11269 | ||
acad7ed3 | 11270 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 11271 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11272 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 11273 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 11274 | "" |
e2c953b6 | 11275 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
b54cf83a | 11276 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11277 | |
acad7ed3 | 11278 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
11279 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
11280 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 11281 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 11282 | "" |
e2c953b6 | 11283 | "cmpld%I2 %0,%1,%b2" |
b54cf83a | 11284 | [(set_attr "type" "cmp")]) |
266eb58a | 11285 | |
1fd4e8c1 RK |
11286 | ;; The following two insns don't exist as single insns, but if we provide |
11287 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
11288 | ;; of the required delay between a compare and branch. We generate code for | |
11289 | ;; them by splitting. | |
11290 | ||
11291 | (define_insn "" | |
11292 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11293 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11294 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 11295 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11296 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11297 | "" | |
baf97f86 RK |
11298 | "#" |
11299 | [(set_attr "length" "8")]) | |
7e69e155 | 11300 | |
1fd4e8c1 RK |
11301 | (define_insn "" |
11302 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11303 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11304 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 11305 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11306 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11307 | "" | |
baf97f86 RK |
11308 | "#" |
11309 | [(set_attr "length" "8")]) | |
7e69e155 | 11310 | |
1fd4e8c1 RK |
11311 | (define_split |
11312 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 11313 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11314 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 11315 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11316 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11317 | "" | |
11318 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
11319 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11320 | ||
11321 | (define_split | |
11322 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 11323 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11324 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 11325 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11326 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11327 | "" | |
11328 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
11329 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11330 | ||
acad7ed3 | 11331 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 11332 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11333 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
11334 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11335 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11336 | "fcmpu %0,%1,%2" |
11337 | [(set_attr "type" "fpcompare")]) | |
11338 | ||
acad7ed3 | 11339 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 11340 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11341 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
11342 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11343 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11344 | "fcmpu %0,%1,%2" |
11345 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
11346 | |
11347 | ;; Only need to compare second words if first words equal | |
11348 | (define_insn "*cmptf_internal1" | |
11349 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11350 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11351 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
11352 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
11353 | && TARGET_LONG_DOUBLE_128" | |
2e7d5318 | 11354 | "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
11355 | [(set_attr "type" "fpcompare") |
11356 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11357 | \f |
11358 | ;; Now we have the scc insns. We can do some combinations because of the | |
11359 | ;; way the machine works. | |
11360 | ;; | |
11361 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
11362 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
11363 | ;; cases the insns below which don't use an intermediate CR field will | |
11364 | ;; be used instead. | |
1fd4e8c1 | 11365 | (define_insn "" |
cd2b37d9 | 11366 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11367 | (match_operator:SI 1 "scc_comparison_operator" |
11368 | [(match_operand 2 "cc_reg_operand" "y") | |
11369 | (const_int 0)]))] | |
11370 | "" | |
b7053a3f | 11371 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b54cf83a | 11372 | [(set_attr "type" "mfcr") |
309323c2 | 11373 | (set_attr "length" "12")]) |
1fd4e8c1 | 11374 | |
a3170dc6 AH |
11375 | ;; Same as above, but get the OV/ORDERED bit. |
11376 | (define_insn "move_from_CR_ov_bit" | |
11377 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
615158e2 | 11378 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] |
a3170dc6 | 11379 | "TARGET_ISEL" |
b7053a3f | 11380 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" |
b54cf83a DE |
11381 | [(set_attr "type" "mfcr") |
11382 | (set_attr "length" "12")]) | |
a3170dc6 | 11383 | |
1fd4e8c1 | 11384 | (define_insn "" |
9ebbca7d GK |
11385 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11386 | (match_operator:DI 1 "scc_comparison_operator" | |
11387 | [(match_operand 2 "cc_reg_operand" "y") | |
11388 | (const_int 0)]))] | |
11389 | "TARGET_POWERPC64" | |
b7053a3f | 11390 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b54cf83a | 11391 | [(set_attr "type" "mfcr") |
309323c2 | 11392 | (set_attr "length" "12")]) |
9ebbca7d GK |
11393 | |
11394 | (define_insn "" | |
11395 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11396 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 11397 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
11398 | (const_int 0)]) |
11399 | (const_int 0))) | |
9ebbca7d | 11400 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11401 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 11402 | "! TARGET_POWERPC64" |
9ebbca7d | 11403 | "@ |
b7053a3f | 11404 | mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 |
9ebbca7d | 11405 | #" |
b19003d8 | 11406 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11407 | (set_attr "length" "12,16")]) |
11408 | ||
11409 | (define_split | |
11410 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11411 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11412 | [(match_operand 2 "cc_reg_operand" "") | |
11413 | (const_int 0)]) | |
11414 | (const_int 0))) | |
11415 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11416 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
11417 | "! TARGET_POWERPC64 && reload_completed" | |
11418 | [(set (match_dup 3) | |
11419 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11420 | (set (match_dup 0) | |
11421 | (compare:CC (match_dup 3) | |
11422 | (const_int 0)))] | |
11423 | "") | |
1fd4e8c1 RK |
11424 | |
11425 | (define_insn "" | |
cd2b37d9 | 11426 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11427 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11428 | [(match_operand 2 "cc_reg_operand" "y") | |
11429 | (const_int 0)]) | |
11430 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11431 | "" | |
11432 | "* | |
11433 | { | |
11434 | int is_bit = ccr_bit (operands[1], 1); | |
11435 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11436 | int count; | |
11437 | ||
11438 | if (is_bit >= put_bit) | |
11439 | count = is_bit - put_bit; | |
11440 | else | |
11441 | count = 32 - (put_bit - is_bit); | |
11442 | ||
89e9f3a8 MM |
11443 | operands[4] = GEN_INT (count); |
11444 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11445 | |
b7053a3f | 11446 | return \"mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11447 | }" |
b54cf83a | 11448 | [(set_attr "type" "mfcr") |
309323c2 | 11449 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
11450 | |
11451 | (define_insn "" | |
9ebbca7d | 11452 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11453 | (compare:CC |
11454 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11455 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11456 | (const_int 0)]) |
9ebbca7d | 11457 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11458 | (const_int 0))) |
9ebbca7d | 11459 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11460 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11461 | (match_dup 3)))] | |
ce71f754 | 11462 | "" |
1fd4e8c1 RK |
11463 | "* |
11464 | { | |
11465 | int is_bit = ccr_bit (operands[1], 1); | |
11466 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11467 | int count; | |
11468 | ||
9ebbca7d GK |
11469 | /* Force split for non-cc0 compare. */ |
11470 | if (which_alternative == 1) | |
11471 | return \"#\"; | |
11472 | ||
1fd4e8c1 RK |
11473 | if (is_bit >= put_bit) |
11474 | count = is_bit - put_bit; | |
11475 | else | |
11476 | count = 32 - (put_bit - is_bit); | |
11477 | ||
89e9f3a8 MM |
11478 | operands[5] = GEN_INT (count); |
11479 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11480 | |
b7053a3f | 11481 | return \"mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11482 | }" |
b19003d8 | 11483 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11484 | (set_attr "length" "12,16")]) |
11485 | ||
11486 | (define_split | |
11487 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11488 | (compare:CC | |
11489 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11490 | [(match_operand 2 "cc_reg_operand" "") | |
11491 | (const_int 0)]) | |
11492 | (match_operand:SI 3 "const_int_operand" "")) | |
11493 | (const_int 0))) | |
11494 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11495 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11496 | (match_dup 3)))] | |
ce71f754 | 11497 | "reload_completed" |
9ebbca7d GK |
11498 | [(set (match_dup 4) |
11499 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11500 | (match_dup 3))) | |
11501 | (set (match_dup 0) | |
11502 | (compare:CC (match_dup 4) | |
11503 | (const_int 0)))] | |
11504 | "") | |
1fd4e8c1 | 11505 | |
c5defebb RK |
11506 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11507 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11508 | ||
11509 | (define_peephole | |
cd2b37d9 | 11510 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11511 | (match_operator:SI 1 "scc_comparison_operator" |
11512 | [(match_operand 2 "cc_reg_operand" "y") | |
11513 | (const_int 0)])) | |
cd2b37d9 | 11514 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11515 | (match_operator:SI 4 "scc_comparison_operator" |
11516 | [(match_operand 5 "cc_reg_operand" "y") | |
11517 | (const_int 0)]))] | |
309323c2 | 11518 | "REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11519 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11520 | [(set_attr "type" "mfcr") |
309323c2 | 11521 | (set_attr "length" "20")]) |
c5defebb | 11522 | |
9ebbca7d GK |
11523 | (define_peephole |
11524 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11525 | (match_operator:DI 1 "scc_comparison_operator" | |
11526 | [(match_operand 2 "cc_reg_operand" "y") | |
11527 | (const_int 0)])) | |
11528 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11529 | (match_operator:DI 4 "scc_comparison_operator" | |
11530 | [(match_operand 5 "cc_reg_operand" "y") | |
11531 | (const_int 0)]))] | |
309323c2 | 11532 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11533 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11534 | [(set_attr "type" "mfcr") |
309323c2 | 11535 | (set_attr "length" "20")]) |
9ebbca7d | 11536 | |
1fd4e8c1 RK |
11537 | ;; There are some scc insns that can be done directly, without a compare. |
11538 | ;; These are faster because they don't involve the communications between | |
11539 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11540 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11541 | ;; | |
11542 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11543 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11544 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11545 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11546 | ||
11547 | ;; Have reload force a constant into a register for the simple insns that | |
11548 | ;; otherwise won't accept constants. We do this because it is faster than | |
11549 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11550 | ||
11551 | (define_insn "" | |
cd2b37d9 RK |
11552 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11553 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11554 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11555 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
f9562f27 | 11556 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11557 | "@ |
ca7f5001 | 11558 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11559 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11560 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11561 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
11562 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 11563 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11564 | |
a260abc9 DE |
11565 | (define_insn "" |
11566 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
11567 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
11568 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
11569 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
11570 | "TARGET_POWERPC64" | |
11571 | "@ | |
11572 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11573 | subfic %3,%1,0\;adde %0,%3,%1 | |
11574 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11575 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11576 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
11577 | [(set_attr "length" "12,8,12,12,12")]) | |
11578 | ||
1fd4e8c1 | 11579 | (define_insn "" |
9ebbca7d | 11580 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11581 | (compare:CC |
9ebbca7d GK |
11582 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11583 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 11584 | (const_int 0))) |
9ebbca7d | 11585 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11586 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11587 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
f9562f27 | 11588 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11589 | "@ |
ca7f5001 RK |
11590 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11591 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
11592 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
11593 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
11594 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11595 | # | |
11596 | # | |
11597 | # | |
11598 | # | |
11599 | #" | |
b19003d8 | 11600 | [(set_attr "type" "compare") |
9ebbca7d GK |
11601 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11602 | ||
11603 | (define_split | |
11604 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11605 | (compare:CC | |
11606 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11607 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11608 | (const_int 0))) | |
11609 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11610 | (eq:SI (match_dup 1) (match_dup 2))) | |
11611 | (clobber (match_scratch:SI 3 ""))] | |
11612 | "! TARGET_POWERPC64 && reload_completed" | |
11613 | [(parallel [(set (match_dup 0) | |
11614 | (eq:SI (match_dup 1) (match_dup 2))) | |
11615 | (clobber (match_dup 3))]) | |
11616 | (set (match_dup 4) | |
11617 | (compare:CC (match_dup 0) | |
11618 | (const_int 0)))] | |
11619 | "") | |
b19003d8 | 11620 | |
a260abc9 | 11621 | (define_insn "" |
9ebbca7d | 11622 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 11623 | (compare:CC |
9ebbca7d GK |
11624 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11625 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 11626 | (const_int 0))) |
9ebbca7d | 11627 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 11628 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11629 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
a260abc9 DE |
11630 | "TARGET_POWERPC64" |
11631 | "@ | |
11632 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11633 | subfic %3,%1,0\;adde. %0,%3,%1 | |
11634 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11635 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
11636 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
11637 | # | |
11638 | # | |
11639 | # | |
11640 | # | |
11641 | #" | |
a260abc9 | 11642 | [(set_attr "type" "compare") |
9ebbca7d GK |
11643 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11644 | ||
11645 | (define_split | |
11646 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11647 | (compare:CC | |
11648 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11649 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
11650 | (const_int 0))) | |
11651 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11652 | (eq:DI (match_dup 1) (match_dup 2))) | |
11653 | (clobber (match_scratch:DI 3 ""))] | |
11654 | "TARGET_POWERPC64 && reload_completed" | |
11655 | [(parallel [(set (match_dup 0) | |
11656 | (eq:DI (match_dup 1) (match_dup 2))) | |
11657 | (clobber (match_dup 3))]) | |
11658 | (set (match_dup 4) | |
11659 | (compare:CC (match_dup 0) | |
11660 | (const_int 0)))] | |
11661 | "") | |
a260abc9 | 11662 | |
b19003d8 RK |
11663 | ;; We have insns of the form shown by the first define_insn below. If |
11664 | ;; there is something inside the comparison operation, we must split it. | |
11665 | (define_split | |
11666 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11667 | (plus:SI (match_operator 1 "comparison_operator" | |
11668 | [(match_operand:SI 2 "" "") | |
11669 | (match_operand:SI 3 | |
11670 | "reg_or_cint_operand" "")]) | |
11671 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11672 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11673 | "! gpc_reg_operand (operands[2], SImode)" | |
11674 | [(set (match_dup 5) (match_dup 2)) | |
11675 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11676 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11677 | |
11678 | (define_insn "" | |
5276df18 | 11679 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11680 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11681 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 11682 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
f9562f27 | 11683 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11684 | "@ |
5276df18 DE |
11685 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11686 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11687 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11688 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11689 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
b19003d8 | 11690 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
11691 | |
11692 | (define_insn "" | |
9ebbca7d | 11693 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11694 | (compare:CC |
1fd4e8c1 | 11695 | (plus:SI |
9ebbca7d GK |
11696 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11697 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11698 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11699 | (const_int 0))) |
9ebbca7d | 11700 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 11701 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11702 | "@ |
ca7f5001 | 11703 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11704 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11705 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11706 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11707 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11708 | # | |
11709 | # | |
11710 | # | |
11711 | # | |
11712 | #" | |
b19003d8 | 11713 | [(set_attr "type" "compare") |
9ebbca7d GK |
11714 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11715 | ||
11716 | (define_split | |
11717 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11718 | (compare:CC | |
11719 | (plus:SI | |
11720 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11721 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11722 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11723 | (const_int 0))) | |
11724 | (clobber (match_scratch:SI 4 ""))] | |
11725 | "! TARGET_POWERPC64 && reload_completed" | |
11726 | [(set (match_dup 4) | |
11727 | (plus:SI (eq:SI (match_dup 1) | |
11728 | (match_dup 2)) | |
11729 | (match_dup 3))) | |
11730 | (set (match_dup 0) | |
11731 | (compare:CC (match_dup 4) | |
11732 | (const_int 0)))] | |
11733 | "") | |
1fd4e8c1 RK |
11734 | |
11735 | (define_insn "" | |
0387639b | 11736 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11737 | (compare:CC |
1fd4e8c1 | 11738 | (plus:SI |
9ebbca7d GK |
11739 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11740 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11741 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11742 | (const_int 0))) |
0387639b DE |
11743 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11744 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 11745 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11746 | "@ |
0387639b DE |
11747 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11748 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11749 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11750 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11751 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11752 | # |
11753 | # | |
11754 | # | |
11755 | # | |
11756 | #" | |
11757 | [(set_attr "type" "compare") | |
11758 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11759 | ||
11760 | (define_split | |
0387639b | 11761 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11762 | (compare:CC |
11763 | (plus:SI | |
11764 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11765 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11766 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11767 | (const_int 0))) | |
11768 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11769 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 11770 | "! TARGET_POWERPC64 && reload_completed" |
0387639b | 11771 | [(set (match_dup 0) |
9ebbca7d | 11772 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11773 | (set (match_dup 4) |
9ebbca7d GK |
11774 | (compare:CC (match_dup 0) |
11775 | (const_int 0)))] | |
11776 | "") | |
11777 | ||
1fd4e8c1 | 11778 | (define_insn "" |
cd2b37d9 | 11779 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11780 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11781 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
f9562f27 | 11782 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11783 | "@ |
ca7f5001 RK |
11784 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11785 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11786 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11787 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11788 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11789 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11790 | |
ea9be077 MM |
11791 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11792 | ;; since it nabs/sr is just as fast. | |
463b558b | 11793 | (define_insn "*ne0" |
b4e95693 | 11794 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11795 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11796 | (const_int 31))) | |
11797 | (clobber (match_scratch:SI 2 "=&r"))] | |
a3170dc6 | 11798 | "! TARGET_POWER && ! TARGET_POWERPC64 && !TARGET_ISEL" |
ea9be077 MM |
11799 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
11800 | [(set_attr "length" "8")]) | |
11801 | ||
a260abc9 DE |
11802 | (define_insn "" |
11803 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11804 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11805 | (const_int 63))) | |
11806 | (clobber (match_scratch:DI 2 "=&r"))] | |
11807 | "TARGET_POWERPC64" | |
11808 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
11809 | [(set_attr "length" "8")]) | |
11810 | ||
1fd4e8c1 RK |
11811 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11812 | (define_insn "" | |
cd2b37d9 | 11813 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11814 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11815 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11816 | (const_int 31)) |
cd2b37d9 | 11817 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11818 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 11819 | "! TARGET_POWERPC64" |
ca7f5001 | 11820 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 11821 | [(set_attr "length" "8")]) |
1fd4e8c1 | 11822 | |
a260abc9 DE |
11823 | (define_insn "" |
11824 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11825 | (plus:DI (lshiftrt:DI | |
11826 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11827 | (const_int 63)) | |
11828 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11829 | (clobber (match_scratch:DI 3 "=&r"))] | |
11830 | "TARGET_POWERPC64" | |
11831 | "addic %3,%1,-1\;addze %0,%2" | |
11832 | [(set_attr "length" "8")]) | |
11833 | ||
1fd4e8c1 | 11834 | (define_insn "" |
9ebbca7d | 11835 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11836 | (compare:CC |
11837 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11838 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11839 | (const_int 31)) |
9ebbca7d | 11840 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11841 | (const_int 0))) |
889b90a1 GK |
11842 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11843 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
f9562f27 | 11844 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11845 | "@ |
11846 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11847 | #" | |
b19003d8 | 11848 | [(set_attr "type" "compare") |
9ebbca7d GK |
11849 | (set_attr "length" "8,12")]) |
11850 | ||
11851 | (define_split | |
11852 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11853 | (compare:CC | |
11854 | (plus:SI (lshiftrt:SI | |
11855 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11856 | (const_int 31)) | |
11857 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11858 | (const_int 0))) | |
889b90a1 GK |
11859 | (clobber (match_scratch:SI 3 "")) |
11860 | (clobber (match_scratch:SI 4 ""))] | |
9ebbca7d | 11861 | "! TARGET_POWERPC64 && reload_completed" |
889b90a1 | 11862 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
11863 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
11864 | (const_int 31)) | |
11865 | (match_dup 2))) | |
889b90a1 | 11866 | (clobber (match_dup 4))]) |
9ebbca7d GK |
11867 | (set (match_dup 0) |
11868 | (compare:CC (match_dup 3) | |
11869 | (const_int 0)))] | |
11870 | "") | |
1fd4e8c1 | 11871 | |
a260abc9 | 11872 | (define_insn "" |
9ebbca7d | 11873 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11874 | (compare:CC |
11875 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11876 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11877 | (const_int 63)) |
9ebbca7d | 11878 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11879 | (const_int 0))) |
9ebbca7d | 11880 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 11881 | "TARGET_POWERPC64" |
9ebbca7d GK |
11882 | "@ |
11883 | addic %3,%1,-1\;addze. %3,%2 | |
11884 | #" | |
a260abc9 | 11885 | [(set_attr "type" "compare") |
9ebbca7d GK |
11886 | (set_attr "length" "8,12")]) |
11887 | ||
11888 | (define_split | |
11889 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11890 | (compare:CC | |
11891 | (plus:DI (lshiftrt:DI | |
11892 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11893 | (const_int 63)) | |
11894 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11895 | (const_int 0))) | |
11896 | (clobber (match_scratch:DI 3 ""))] | |
11897 | "TARGET_POWERPC64 && reload_completed" | |
11898 | [(set (match_dup 3) | |
11899 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11900 | (const_int 63)) | |
11901 | (match_dup 2))) | |
11902 | (set (match_dup 0) | |
11903 | (compare:CC (match_dup 3) | |
11904 | (const_int 0)))] | |
11905 | "") | |
a260abc9 | 11906 | |
1fd4e8c1 | 11907 | (define_insn "" |
9ebbca7d | 11908 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11909 | (compare:CC |
11910 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11911 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11912 | (const_int 31)) |
9ebbca7d | 11913 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11914 | (const_int 0))) |
9ebbca7d | 11915 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11916 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11917 | (match_dup 2))) | |
9ebbca7d | 11918 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 11919 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11920 | "@ |
11921 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11922 | #" | |
b19003d8 | 11923 | [(set_attr "type" "compare") |
9ebbca7d GK |
11924 | (set_attr "length" "8,12")]) |
11925 | ||
11926 | (define_split | |
11927 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11928 | (compare:CC | |
11929 | (plus:SI (lshiftrt:SI | |
11930 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11931 | (const_int 31)) | |
11932 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11933 | (const_int 0))) | |
11934 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11935 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11936 | (match_dup 2))) | |
11937 | (clobber (match_scratch:SI 3 ""))] | |
11938 | "! TARGET_POWERPC64 && reload_completed" | |
11939 | [(parallel [(set (match_dup 0) | |
11940 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11941 | (match_dup 2))) | |
11942 | (clobber (match_dup 3))]) | |
11943 | (set (match_dup 4) | |
11944 | (compare:CC (match_dup 0) | |
11945 | (const_int 0)))] | |
11946 | "") | |
1fd4e8c1 | 11947 | |
a260abc9 | 11948 | (define_insn "" |
9ebbca7d | 11949 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11950 | (compare:CC |
11951 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11952 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11953 | (const_int 63)) |
9ebbca7d | 11954 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11955 | (const_int 0))) |
9ebbca7d | 11956 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11957 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11958 | (match_dup 2))) | |
9ebbca7d | 11959 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 11960 | "TARGET_POWERPC64" |
9ebbca7d GK |
11961 | "@ |
11962 | addic %3,%1,-1\;addze. %0,%2 | |
11963 | #" | |
a260abc9 | 11964 | [(set_attr "type" "compare") |
9ebbca7d GK |
11965 | (set_attr "length" "8,12")]) |
11966 | ||
11967 | (define_split | |
11968 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11969 | (compare:CC | |
11970 | (plus:DI (lshiftrt:DI | |
11971 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11972 | (const_int 63)) | |
11973 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11974 | (const_int 0))) | |
11975 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11976 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11977 | (match_dup 2))) | |
11978 | (clobber (match_scratch:DI 3 ""))] | |
11979 | "TARGET_POWERPC64 && reload_completed" | |
11980 | [(parallel [(set (match_dup 0) | |
11981 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11982 | (match_dup 2))) | |
11983 | (clobber (match_dup 3))]) | |
11984 | (set (match_dup 4) | |
11985 | (compare:CC (match_dup 0) | |
11986 | (const_int 0)))] | |
11987 | "") | |
a260abc9 | 11988 | |
1fd4e8c1 | 11989 | (define_insn "" |
cd2b37d9 RK |
11990 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11991 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11992 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11993 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11994 | "TARGET_POWER" |
1fd4e8c1 | 11995 | "@ |
ca7f5001 | 11996 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11997 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11998 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11999 | |
12000 | (define_insn "" | |
9ebbca7d | 12001 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12002 | (compare:CC |
9ebbca7d GK |
12003 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12004 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 12005 | (const_int 0))) |
9ebbca7d | 12006 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12007 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12008 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 12009 | "TARGET_POWER" |
1fd4e8c1 | 12010 | "@ |
ca7f5001 | 12011 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
12012 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
12013 | # | |
12014 | #" | |
12015 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
12016 | (set_attr "length" "12,12,16,16")]) | |
12017 | ||
12018 | (define_split | |
12019 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12020 | (compare:CC | |
12021 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12022 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12023 | (const_int 0))) | |
12024 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12025 | (le:SI (match_dup 1) (match_dup 2))) | |
12026 | (clobber (match_scratch:SI 3 ""))] | |
12027 | "TARGET_POWER && reload_completed" | |
12028 | [(parallel [(set (match_dup 0) | |
12029 | (le:SI (match_dup 1) (match_dup 2))) | |
12030 | (clobber (match_dup 3))]) | |
12031 | (set (match_dup 4) | |
12032 | (compare:CC (match_dup 0) | |
12033 | (const_int 0)))] | |
12034 | "") | |
1fd4e8c1 RK |
12035 | |
12036 | (define_insn "" | |
097657c3 | 12037 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12038 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12039 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 12040 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 12041 | "TARGET_POWER" |
1fd4e8c1 | 12042 | "@ |
097657c3 AM |
12043 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
12044 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 12045 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12046 | |
12047 | (define_insn "" | |
9ebbca7d | 12048 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12049 | (compare:CC |
9ebbca7d GK |
12050 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12051 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12052 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12053 | (const_int 0))) |
9ebbca7d | 12054 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 12055 | "TARGET_POWER" |
1fd4e8c1 | 12056 | "@ |
ca7f5001 | 12057 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12058 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
12059 | # | |
12060 | #" | |
b19003d8 | 12061 | [(set_attr "type" "compare") |
9ebbca7d GK |
12062 | (set_attr "length" "12,12,16,16")]) |
12063 | ||
12064 | (define_split | |
12065 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12066 | (compare:CC | |
12067 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12068 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12069 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12070 | (const_int 0))) | |
12071 | (clobber (match_scratch:SI 4 ""))] | |
12072 | "TARGET_POWER && reload_completed" | |
12073 | [(set (match_dup 4) | |
12074 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12075 | (match_dup 3))) |
9ebbca7d GK |
12076 | (set (match_dup 0) |
12077 | (compare:CC (match_dup 4) | |
12078 | (const_int 0)))] | |
12079 | "") | |
1fd4e8c1 RK |
12080 | |
12081 | (define_insn "" | |
097657c3 | 12082 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12083 | (compare:CC |
9ebbca7d GK |
12084 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12085 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12086 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12087 | (const_int 0))) |
097657c3 AM |
12088 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12089 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12090 | "TARGET_POWER" |
1fd4e8c1 | 12091 | "@ |
097657c3 AM |
12092 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
12093 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12094 | # |
12095 | #" | |
b19003d8 | 12096 | [(set_attr "type" "compare") |
9ebbca7d GK |
12097 | (set_attr "length" "12,12,16,16")]) |
12098 | ||
12099 | (define_split | |
097657c3 | 12100 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12101 | (compare:CC |
12102 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12103 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12104 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12105 | (const_int 0))) | |
12106 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12107 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12108 | "TARGET_POWER && reload_completed" |
097657c3 | 12109 | [(set (match_dup 0) |
9ebbca7d | 12110 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12111 | (set (match_dup 4) |
9ebbca7d GK |
12112 | (compare:CC (match_dup 0) |
12113 | (const_int 0)))] | |
12114 | "") | |
1fd4e8c1 RK |
12115 | |
12116 | (define_insn "" | |
cd2b37d9 RK |
12117 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12118 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12119 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 12120 | "TARGET_POWER" |
1fd4e8c1 | 12121 | "@ |
ca7f5001 RK |
12122 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
12123 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12124 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12125 | |
12126 | (define_insn "" | |
cd2b37d9 RK |
12127 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12128 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12129 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 12130 | "! TARGET_POWERPC64" |
ca7f5001 | 12131 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 12132 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12133 | |
f9562f27 DE |
12134 | (define_insn "" |
12135 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12136 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12137 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
12138 | "TARGET_POWERPC64" | |
12139 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" | |
12140 | [(set_attr "length" "12")]) | |
12141 | ||
12142 | (define_insn "" | |
9ebbca7d | 12143 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12144 | (compare:CC |
9ebbca7d GK |
12145 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12146 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12147 | (const_int 0))) |
9ebbca7d | 12148 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12149 | (leu:DI (match_dup 1) (match_dup 2)))] |
12150 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12151 | "@ |
12152 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
12153 | #" | |
f9562f27 | 12154 | [(set_attr "type" "compare") |
9ebbca7d GK |
12155 | (set_attr "length" "12,16")]) |
12156 | ||
12157 | (define_split | |
12158 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12159 | (compare:CC | |
12160 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12161 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12162 | (const_int 0))) | |
12163 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12164 | (leu:DI (match_dup 1) (match_dup 2)))] | |
12165 | "TARGET_POWERPC64 && reload_completed" | |
12166 | [(set (match_dup 0) | |
12167 | (leu:DI (match_dup 1) (match_dup 2))) | |
12168 | (set (match_dup 3) | |
12169 | (compare:CC (match_dup 0) | |
12170 | (const_int 0)))] | |
12171 | "") | |
f9562f27 | 12172 | |
1fd4e8c1 | 12173 | (define_insn "" |
9ebbca7d | 12174 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12175 | (compare:CC |
9ebbca7d GK |
12176 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12177 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12178 | (const_int 0))) |
9ebbca7d | 12179 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12180 | (leu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12181 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12182 | "@ |
12183 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
12184 | #" | |
b19003d8 | 12185 | [(set_attr "type" "compare") |
9ebbca7d GK |
12186 | (set_attr "length" "12,16")]) |
12187 | ||
12188 | (define_split | |
12189 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12190 | (compare:CC | |
12191 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12192 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12193 | (const_int 0))) | |
12194 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12195 | (leu:SI (match_dup 1) (match_dup 2)))] | |
12196 | "! TARGET_POWERPC64 && reload_completed" | |
12197 | [(set (match_dup 0) | |
12198 | (leu:SI (match_dup 1) (match_dup 2))) | |
12199 | (set (match_dup 3) | |
12200 | (compare:CC (match_dup 0) | |
12201 | (const_int 0)))] | |
12202 | "") | |
1fd4e8c1 | 12203 | |
f9562f27 | 12204 | (define_insn "" |
9ebbca7d | 12205 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12206 | (compare:CC |
9ebbca7d GK |
12207 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12208 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12209 | (const_int 0))) |
9ebbca7d | 12210 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12211 | (leu:DI (match_dup 1) (match_dup 2)))] |
12212 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12213 | "@ |
12214 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
12215 | #" | |
f9562f27 | 12216 | [(set_attr "type" "compare") |
9ebbca7d | 12217 | (set_attr "length" "12,16")]) |
f9562f27 | 12218 | |
1fd4e8c1 | 12219 | (define_insn "" |
80103f96 | 12220 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12221 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12222 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 12223 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
f9562f27 | 12224 | "! TARGET_POWERPC64" |
80103f96 | 12225 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 12226 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12227 | |
12228 | (define_insn "" | |
9ebbca7d | 12229 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12230 | (compare:CC |
9ebbca7d GK |
12231 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12232 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12233 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12234 | (const_int 0))) |
9ebbca7d | 12235 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 12236 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12237 | "@ |
12238 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
12239 | #" | |
b19003d8 | 12240 | [(set_attr "type" "compare") |
9ebbca7d GK |
12241 | (set_attr "length" "8,12")]) |
12242 | ||
12243 | (define_split | |
12244 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12245 | (compare:CC | |
12246 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12247 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12248 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12249 | (const_int 0))) | |
12250 | (clobber (match_scratch:SI 4 ""))] | |
12251 | "! TARGET_POWERPC64 && reload_completed" | |
12252 | [(set (match_dup 4) | |
12253 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
12254 | (match_dup 3))) | |
12255 | (set (match_dup 0) | |
12256 | (compare:CC (match_dup 4) | |
12257 | (const_int 0)))] | |
12258 | "") | |
1fd4e8c1 RK |
12259 | |
12260 | (define_insn "" | |
097657c3 | 12261 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12262 | (compare:CC |
9ebbca7d GK |
12263 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12264 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12265 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12266 | (const_int 0))) |
097657c3 AM |
12267 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12268 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 12269 | "! TARGET_POWERPC64" |
9ebbca7d | 12270 | "@ |
097657c3 | 12271 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 12272 | #" |
b19003d8 | 12273 | [(set_attr "type" "compare") |
9ebbca7d GK |
12274 | (set_attr "length" "8,12")]) |
12275 | ||
12276 | (define_split | |
097657c3 | 12277 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12278 | (compare:CC |
12279 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12280 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12281 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12282 | (const_int 0))) | |
12283 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12284 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12285 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12286 | [(set (match_dup 0) |
9ebbca7d | 12287 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12288 | (set (match_dup 4) |
9ebbca7d GK |
12289 | (compare:CC (match_dup 0) |
12290 | (const_int 0)))] | |
12291 | "") | |
1fd4e8c1 RK |
12292 | |
12293 | (define_insn "" | |
cd2b37d9 RK |
12294 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12295 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12296 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 12297 | "! TARGET_POWERPC64" |
ca7f5001 | 12298 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 12299 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12300 | |
12301 | (define_insn "" | |
097657c3 | 12302 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 12303 | (and:SI (neg:SI |
cd2b37d9 | 12304 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12305 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 12306 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
f9562f27 | 12307 | "! TARGET_POWERPC64" |
097657c3 | 12308 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
b19003d8 | 12309 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12310 | |
12311 | (define_insn "" | |
9ebbca7d | 12312 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12313 | (compare:CC |
12314 | (and:SI (neg:SI | |
9ebbca7d GK |
12315 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12316 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12317 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12318 | (const_int 0))) |
9ebbca7d | 12319 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 12320 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12321 | "@ |
12322 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
12323 | #" | |
12324 | [(set_attr "type" "compare") | |
12325 | (set_attr "length" "12,16")]) | |
12326 | ||
12327 | (define_split | |
12328 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12329 | (compare:CC | |
12330 | (and:SI (neg:SI | |
12331 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12332 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12333 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12334 | (const_int 0))) | |
12335 | (clobber (match_scratch:SI 4 ""))] | |
12336 | "! TARGET_POWERPC64 && reload_completed" | |
12337 | [(set (match_dup 4) | |
097657c3 AM |
12338 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
12339 | (match_dup 3))) | |
9ebbca7d GK |
12340 | (set (match_dup 0) |
12341 | (compare:CC (match_dup 4) | |
12342 | (const_int 0)))] | |
12343 | "") | |
1fd4e8c1 RK |
12344 | |
12345 | (define_insn "" | |
097657c3 | 12346 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12347 | (compare:CC |
12348 | (and:SI (neg:SI | |
9ebbca7d GK |
12349 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12350 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12351 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12352 | (const_int 0))) |
097657c3 AM |
12353 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12354 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
f9562f27 | 12355 | "! TARGET_POWERPC64" |
9ebbca7d | 12356 | "@ |
097657c3 | 12357 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 12358 | #" |
b19003d8 | 12359 | [(set_attr "type" "compare") |
9ebbca7d GK |
12360 | (set_attr "length" "12,16")]) |
12361 | ||
12362 | (define_split | |
097657c3 | 12363 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12364 | (compare:CC |
12365 | (and:SI (neg:SI | |
12366 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12367 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12368 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12369 | (const_int 0))) | |
12370 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12371 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
9ebbca7d | 12372 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 AM |
12373 | [(set (match_dup 0) |
12374 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
12375 | (match_dup 3))) | |
12376 | (set (match_dup 4) | |
9ebbca7d GK |
12377 | (compare:CC (match_dup 0) |
12378 | (const_int 0)))] | |
12379 | "") | |
1fd4e8c1 RK |
12380 | |
12381 | (define_insn "" | |
cd2b37d9 RK |
12382 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12383 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12384 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 12385 | "TARGET_POWER" |
7f340546 | 12386 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12387 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12388 | |
12389 | (define_insn "" | |
9ebbca7d | 12390 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12391 | (compare:CC |
9ebbca7d GK |
12392 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12393 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12394 | (const_int 0))) |
9ebbca7d | 12395 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12396 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12397 | "TARGET_POWER" |
9ebbca7d GK |
12398 | "@ |
12399 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12400 | #" | |
29ae5b89 | 12401 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12402 | (set_attr "length" "12,16")]) |
12403 | ||
12404 | (define_split | |
12405 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12406 | (compare:CC | |
12407 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12408 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12409 | (const_int 0))) | |
12410 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12411 | (lt:SI (match_dup 1) (match_dup 2)))] | |
12412 | "TARGET_POWER && reload_completed" | |
12413 | [(set (match_dup 0) | |
12414 | (lt:SI (match_dup 1) (match_dup 2))) | |
12415 | (set (match_dup 3) | |
12416 | (compare:CC (match_dup 0) | |
12417 | (const_int 0)))] | |
12418 | "") | |
1fd4e8c1 RK |
12419 | |
12420 | (define_insn "" | |
097657c3 | 12421 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12422 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12423 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12424 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12425 | "TARGET_POWER" |
097657c3 | 12426 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12427 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12428 | |
12429 | (define_insn "" | |
9ebbca7d | 12430 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12431 | (compare:CC |
9ebbca7d GK |
12432 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12433 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12434 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12435 | (const_int 0))) |
9ebbca7d | 12436 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12437 | "TARGET_POWER" |
9ebbca7d GK |
12438 | "@ |
12439 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12440 | #" | |
b19003d8 | 12441 | [(set_attr "type" "compare") |
9ebbca7d GK |
12442 | (set_attr "length" "12,16")]) |
12443 | ||
12444 | (define_split | |
12445 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12446 | (compare:CC | |
12447 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12448 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12449 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12450 | (const_int 0))) | |
12451 | (clobber (match_scratch:SI 4 ""))] | |
12452 | "TARGET_POWER && reload_completed" | |
12453 | [(set (match_dup 4) | |
12454 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12455 | (match_dup 3))) |
9ebbca7d GK |
12456 | (set (match_dup 0) |
12457 | (compare:CC (match_dup 4) | |
12458 | (const_int 0)))] | |
12459 | "") | |
1fd4e8c1 RK |
12460 | |
12461 | (define_insn "" | |
097657c3 | 12462 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12463 | (compare:CC |
9ebbca7d GK |
12464 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12465 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12466 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12467 | (const_int 0))) |
097657c3 AM |
12468 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12469 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12470 | "TARGET_POWER" |
9ebbca7d | 12471 | "@ |
097657c3 | 12472 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12473 | #" |
b19003d8 | 12474 | [(set_attr "type" "compare") |
9ebbca7d GK |
12475 | (set_attr "length" "12,16")]) |
12476 | ||
12477 | (define_split | |
097657c3 | 12478 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12479 | (compare:CC |
12480 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12481 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12482 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12483 | (const_int 0))) | |
12484 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12485 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12486 | "TARGET_POWER && reload_completed" |
097657c3 | 12487 | [(set (match_dup 0) |
9ebbca7d | 12488 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12489 | (set (match_dup 4) |
9ebbca7d GK |
12490 | (compare:CC (match_dup 0) |
12491 | (const_int 0)))] | |
12492 | "") | |
1fd4e8c1 RK |
12493 | |
12494 | (define_insn "" | |
cd2b37d9 RK |
12495 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12496 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12497 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12498 | "TARGET_POWER" |
12499 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12500 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12501 | |
12502 | (define_insn "" | |
cd2b37d9 RK |
12503 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12504 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12505 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 12506 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12507 | "@ |
ca7f5001 RK |
12508 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
12509 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 12510 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12511 | |
12512 | (define_insn "" | |
9ebbca7d | 12513 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12514 | (compare:CC |
9ebbca7d GK |
12515 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12516 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12517 | (const_int 0))) |
9ebbca7d | 12518 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12519 | (ltu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12520 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12521 | "@ |
ca7f5001 | 12522 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12523 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12524 | # | |
12525 | #" | |
b19003d8 | 12526 | [(set_attr "type" "compare") |
9ebbca7d GK |
12527 | (set_attr "length" "12,12,16,16")]) |
12528 | ||
12529 | (define_split | |
12530 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12531 | (compare:CC | |
12532 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12533 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12534 | (const_int 0))) | |
12535 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12536 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
12537 | "! TARGET_POWERPC64 && reload_completed" | |
12538 | [(set (match_dup 0) | |
12539 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12540 | (set (match_dup 3) | |
12541 | (compare:CC (match_dup 0) | |
12542 | (const_int 0)))] | |
12543 | "") | |
1fd4e8c1 RK |
12544 | |
12545 | (define_insn "" | |
80103f96 | 12546 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
12547 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12548 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
80103f96 | 12549 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] |
f9562f27 | 12550 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12551 | "@ |
80103f96 FS |
12552 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3 |
12553 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
b19003d8 | 12554 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12555 | |
12556 | (define_insn "" | |
9ebbca7d | 12557 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12558 | (compare:CC |
9ebbca7d GK |
12559 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12560 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12561 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12562 | (const_int 0))) |
9ebbca7d | 12563 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12564 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12565 | "@ |
ca7f5001 | 12566 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
12567 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12568 | # | |
12569 | #" | |
b19003d8 | 12570 | [(set_attr "type" "compare") |
9ebbca7d GK |
12571 | (set_attr "length" "12,12,16,16")]) |
12572 | ||
12573 | (define_split | |
12574 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12575 | (compare:CC | |
12576 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12577 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12578 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12579 | (const_int 0))) | |
12580 | (clobber (match_scratch:SI 4 ""))] | |
12581 | "! TARGET_POWERPC64 && reload_completed" | |
12582 | [(set (match_dup 4) | |
12583 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12584 | (match_dup 3))) |
9ebbca7d GK |
12585 | (set (match_dup 0) |
12586 | (compare:CC (match_dup 4) | |
12587 | (const_int 0)))] | |
12588 | "") | |
1fd4e8c1 RK |
12589 | |
12590 | (define_insn "" | |
097657c3 | 12591 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12592 | (compare:CC |
9ebbca7d GK |
12593 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12594 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12595 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12596 | (const_int 0))) |
097657c3 AM |
12597 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12598 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 12599 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12600 | "@ |
097657c3 AM |
12601 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 |
12602 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
12603 | # |
12604 | #" | |
b19003d8 | 12605 | [(set_attr "type" "compare") |
9ebbca7d GK |
12606 | (set_attr "length" "12,12,16,16")]) |
12607 | ||
12608 | (define_split | |
097657c3 | 12609 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12610 | (compare:CC |
12611 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12612 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12613 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12614 | (const_int 0))) | |
12615 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12616 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12617 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12618 | [(set (match_dup 0) |
9ebbca7d | 12619 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12620 | (set (match_dup 4) |
9ebbca7d GK |
12621 | (compare:CC (match_dup 0) |
12622 | (const_int 0)))] | |
12623 | "") | |
1fd4e8c1 RK |
12624 | |
12625 | (define_insn "" | |
cd2b37d9 RK |
12626 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12627 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12628 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
f9562f27 | 12629 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12630 | "@ |
ca7f5001 RK |
12631 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12632 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12633 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12634 | |
12635 | (define_insn "" | |
cd2b37d9 RK |
12636 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12637 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12638 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12639 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12640 | "TARGET_POWER" |
12641 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12642 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12643 | |
9ebbca7d GK |
12644 | (define_insn "" |
12645 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12646 | (compare:CC |
9ebbca7d GK |
12647 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12648 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12649 | (const_int 0))) |
9ebbca7d | 12650 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12651 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12652 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12653 | "TARGET_POWER" |
9ebbca7d GK |
12654 | "@ |
12655 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12656 | #" | |
12657 | [(set_attr "type" "compare") | |
12658 | (set_attr "length" "12,16")]) | |
12659 | ||
12660 | (define_split | |
12661 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12662 | (compare:CC | |
12663 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12664 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12665 | (const_int 0))) | |
12666 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12667 | (ge:SI (match_dup 1) (match_dup 2))) | |
12668 | (clobber (match_scratch:SI 3 ""))] | |
12669 | "TARGET_POWER && reload_completed" | |
12670 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12671 | (ge:SI (match_dup 1) (match_dup 2))) |
12672 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12673 | (set (match_dup 4) |
12674 | (compare:CC (match_dup 0) | |
12675 | (const_int 0)))] | |
12676 | "") | |
12677 | ||
1fd4e8c1 | 12678 | (define_insn "" |
097657c3 | 12679 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12680 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12681 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12682 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12683 | "TARGET_POWER" |
097657c3 | 12684 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12685 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12686 | |
12687 | (define_insn "" | |
9ebbca7d | 12688 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12689 | (compare:CC |
9ebbca7d GK |
12690 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12691 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12692 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12693 | (const_int 0))) |
9ebbca7d | 12694 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12695 | "TARGET_POWER" |
9ebbca7d GK |
12696 | "@ |
12697 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12698 | #" | |
b19003d8 | 12699 | [(set_attr "type" "compare") |
9ebbca7d GK |
12700 | (set_attr "length" "12,16")]) |
12701 | ||
12702 | (define_split | |
12703 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12704 | (compare:CC | |
12705 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12706 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12707 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12708 | (const_int 0))) | |
12709 | (clobber (match_scratch:SI 4 ""))] | |
12710 | "TARGET_POWER && reload_completed" | |
12711 | [(set (match_dup 4) | |
12712 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12713 | (match_dup 3))) |
9ebbca7d GK |
12714 | (set (match_dup 0) |
12715 | (compare:CC (match_dup 4) | |
12716 | (const_int 0)))] | |
12717 | "") | |
1fd4e8c1 RK |
12718 | |
12719 | (define_insn "" | |
097657c3 | 12720 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12721 | (compare:CC |
9ebbca7d GK |
12722 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12723 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12724 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12725 | (const_int 0))) |
097657c3 AM |
12726 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12727 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12728 | "TARGET_POWER" |
9ebbca7d | 12729 | "@ |
097657c3 | 12730 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12731 | #" |
b19003d8 | 12732 | [(set_attr "type" "compare") |
9ebbca7d GK |
12733 | (set_attr "length" "12,16")]) |
12734 | ||
12735 | (define_split | |
097657c3 | 12736 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12737 | (compare:CC |
12738 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12739 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12740 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12741 | (const_int 0))) | |
12742 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12743 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12744 | "TARGET_POWER && reload_completed" |
097657c3 | 12745 | [(set (match_dup 0) |
9ebbca7d | 12746 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12747 | (set (match_dup 4) |
9ebbca7d GK |
12748 | (compare:CC (match_dup 0) |
12749 | (const_int 0)))] | |
12750 | "") | |
1fd4e8c1 RK |
12751 | |
12752 | (define_insn "" | |
cd2b37d9 RK |
12753 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12754 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12755 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12756 | "TARGET_POWER" |
12757 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12758 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12759 | |
1fd4e8c1 | 12760 | (define_insn "" |
cd2b37d9 RK |
12761 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12762 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12763 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 12764 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12765 | "@ |
ca7f5001 RK |
12766 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12767 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 12768 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12769 | |
f9562f27 DE |
12770 | (define_insn "" |
12771 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12772 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12773 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
12774 | "TARGET_POWERPC64" | |
12775 | "@ | |
12776 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12777 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
12778 | [(set_attr "length" "12")]) | |
12779 | ||
1fd4e8c1 | 12780 | (define_insn "" |
9ebbca7d | 12781 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12782 | (compare:CC |
9ebbca7d GK |
12783 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12784 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12785 | (const_int 0))) |
9ebbca7d | 12786 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12787 | (geu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12788 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12789 | "@ |
ca7f5001 | 12790 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12791 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12792 | # | |
12793 | #" | |
b19003d8 | 12794 | [(set_attr "type" "compare") |
9ebbca7d GK |
12795 | (set_attr "length" "12,12,16,16")]) |
12796 | ||
12797 | (define_split | |
12798 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12799 | (compare:CC | |
12800 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12801 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12802 | (const_int 0))) | |
12803 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12804 | (geu:SI (match_dup 1) (match_dup 2)))] | |
12805 | "! TARGET_POWERPC64 && reload_completed" | |
12806 | [(set (match_dup 0) | |
12807 | (geu:SI (match_dup 1) (match_dup 2))) | |
12808 | (set (match_dup 3) | |
12809 | (compare:CC (match_dup 0) | |
12810 | (const_int 0)))] | |
12811 | "") | |
1fd4e8c1 | 12812 | |
f9562f27 | 12813 | (define_insn "" |
9ebbca7d | 12814 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12815 | (compare:CC |
9ebbca7d GK |
12816 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12817 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12818 | (const_int 0))) |
9ebbca7d | 12819 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 DE |
12820 | (geu:DI (match_dup 1) (match_dup 2)))] |
12821 | "TARGET_POWERPC64" | |
12822 | "@ | |
12823 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12824 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12825 | # | |
12826 | #" | |
f9562f27 | 12827 | [(set_attr "type" "compare") |
9ebbca7d GK |
12828 | (set_attr "length" "12,12,16,16")]) |
12829 | ||
12830 | (define_split | |
12831 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12832 | (compare:CC | |
12833 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12834 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12835 | (const_int 0))) | |
12836 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12837 | (geu:DI (match_dup 1) (match_dup 2)))] | |
12838 | "TARGET_POWERPC64 && reload_completed" | |
12839 | [(set (match_dup 0) | |
12840 | (geu:DI (match_dup 1) (match_dup 2))) | |
12841 | (set (match_dup 3) | |
12842 | (compare:CC (match_dup 0) | |
12843 | (const_int 0)))] | |
12844 | "") | |
f9562f27 | 12845 | |
1fd4e8c1 | 12846 | (define_insn "" |
80103f96 | 12847 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12848 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12849 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 12850 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
f9562f27 | 12851 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12852 | "@ |
80103f96 FS |
12853 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
12854 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 12855 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12856 | |
12857 | (define_insn "" | |
9ebbca7d | 12858 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12859 | (compare:CC |
9ebbca7d GK |
12860 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12861 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12862 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12863 | (const_int 0))) |
9ebbca7d | 12864 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12865 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12866 | "@ |
ca7f5001 | 12867 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12868 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12869 | # | |
12870 | #" | |
b19003d8 | 12871 | [(set_attr "type" "compare") |
9ebbca7d GK |
12872 | (set_attr "length" "8,8,12,12")]) |
12873 | ||
12874 | (define_split | |
12875 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12876 | (compare:CC | |
12877 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12878 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12879 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12880 | (const_int 0))) | |
12881 | (clobber (match_scratch:SI 4 ""))] | |
12882 | "! TARGET_POWERPC64 && reload_completed" | |
12883 | [(set (match_dup 4) | |
12884 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12885 | (match_dup 3))) | |
12886 | (set (match_dup 0) | |
12887 | (compare:CC (match_dup 4) | |
12888 | (const_int 0)))] | |
12889 | "") | |
1fd4e8c1 RK |
12890 | |
12891 | (define_insn "" | |
097657c3 | 12892 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12893 | (compare:CC |
9ebbca7d GK |
12894 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12895 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12896 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12897 | (const_int 0))) |
097657c3 AM |
12898 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12899 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 12900 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12901 | "@ |
097657c3 AM |
12902 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
12903 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12904 | # |
12905 | #" | |
b19003d8 | 12906 | [(set_attr "type" "compare") |
9ebbca7d GK |
12907 | (set_attr "length" "8,8,12,12")]) |
12908 | ||
12909 | (define_split | |
097657c3 | 12910 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12911 | (compare:CC |
12912 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12913 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12914 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12915 | (const_int 0))) | |
12916 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12917 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12918 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12919 | [(set (match_dup 0) |
9ebbca7d | 12920 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12921 | (set (match_dup 4) |
9ebbca7d GK |
12922 | (compare:CC (match_dup 0) |
12923 | (const_int 0)))] | |
12924 | "") | |
1fd4e8c1 RK |
12925 | |
12926 | (define_insn "" | |
cd2b37d9 RK |
12927 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12928 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12929 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
f9562f27 | 12930 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12931 | "@ |
ca7f5001 | 12932 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12933 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12934 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12935 | |
12936 | (define_insn "" | |
097657c3 | 12937 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 12938 | (and:SI (neg:SI |
cd2b37d9 | 12939 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12940 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 12941 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
f9562f27 | 12942 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12943 | "@ |
097657c3 AM |
12944 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
12945 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
b19003d8 | 12946 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12947 | |
12948 | (define_insn "" | |
9ebbca7d | 12949 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12950 | (compare:CC |
12951 | (and:SI (neg:SI | |
9ebbca7d GK |
12952 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12953 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12954 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12955 | (const_int 0))) |
9ebbca7d | 12956 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12957 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12958 | "@ |
ca7f5001 | 12959 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12960 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12961 | # | |
12962 | #" | |
b19003d8 | 12963 | [(set_attr "type" "compare") |
9ebbca7d GK |
12964 | (set_attr "length" "12,12,16,16")]) |
12965 | ||
12966 | (define_split | |
12967 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12968 | (compare:CC | |
12969 | (and:SI (neg:SI | |
12970 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12971 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12972 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12973 | (const_int 0))) | |
12974 | (clobber (match_scratch:SI 4 ""))] | |
12975 | "! TARGET_POWERPC64 && reload_completed" | |
12976 | [(set (match_dup 4) | |
097657c3 AM |
12977 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
12978 | (match_dup 3))) | |
9ebbca7d GK |
12979 | (set (match_dup 0) |
12980 | (compare:CC (match_dup 4) | |
12981 | (const_int 0)))] | |
12982 | "") | |
1fd4e8c1 RK |
12983 | |
12984 | (define_insn "" | |
097657c3 | 12985 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12986 | (compare:CC |
12987 | (and:SI (neg:SI | |
9ebbca7d GK |
12988 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12989 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12990 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12991 | (const_int 0))) |
097657c3 AM |
12992 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12993 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
f9562f27 | 12994 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12995 | "@ |
097657c3 AM |
12996 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
12997 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
12998 | # |
12999 | #" | |
b19003d8 | 13000 | [(set_attr "type" "compare") |
9ebbca7d GK |
13001 | (set_attr "length" "12,12,16,16")]) |
13002 | ||
13003 | (define_split | |
097657c3 | 13004 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13005 | (compare:CC |
13006 | (and:SI (neg:SI | |
13007 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13008 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
13009 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13010 | (const_int 0))) | |
13011 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13012 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
9ebbca7d | 13013 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 13014 | [(set (match_dup 0) |
9ebbca7d | 13015 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 13016 | (set (match_dup 4) |
9ebbca7d GK |
13017 | (compare:CC (match_dup 0) |
13018 | (const_int 0)))] | |
13019 | "") | |
1fd4e8c1 RK |
13020 | |
13021 | (define_insn "" | |
cd2b37d9 RK |
13022 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13023 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13024 | (const_int 0)))] |
f9562f27 | 13025 | "! TARGET_POWERPC64" |
ca7f5001 | 13026 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 13027 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13028 | |
f9562f27 DE |
13029 | (define_insn "" |
13030 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13031 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13032 | (const_int 0)))] | |
13033 | "TARGET_POWERPC64" | |
13034 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" | |
13035 | [(set_attr "length" "12")]) | |
13036 | ||
1fd4e8c1 | 13037 | (define_insn "" |
9ebbca7d | 13038 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13039 | (compare:CC |
9ebbca7d | 13040 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
13041 | (const_int 0)) |
13042 | (const_int 0))) | |
9ebbca7d | 13043 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13044 | (gt:SI (match_dup 1) (const_int 0)))] |
f9562f27 | 13045 | "! TARGET_POWERPC64" |
9ebbca7d GK |
13046 | "@ |
13047 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
13048 | #" | |
29ae5b89 | 13049 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13050 | (set_attr "length" "12,16")]) |
13051 | ||
13052 | (define_split | |
13053 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13054 | (compare:CC | |
13055 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13056 | (const_int 0)) | |
13057 | (const_int 0))) | |
13058 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13059 | (gt:SI (match_dup 1) (const_int 0)))] | |
13060 | "! TARGET_POWERPC64 && reload_completed" | |
13061 | [(set (match_dup 0) | |
13062 | (gt:SI (match_dup 1) (const_int 0))) | |
13063 | (set (match_dup 2) | |
13064 | (compare:CC (match_dup 0) | |
13065 | (const_int 0)))] | |
13066 | "") | |
1fd4e8c1 | 13067 | |
f9562f27 | 13068 | (define_insn "" |
9ebbca7d | 13069 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 13070 | (compare:CC |
9ebbca7d | 13071 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
13072 | (const_int 0)) |
13073 | (const_int 0))) | |
9ebbca7d | 13074 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
13075 | (gt:DI (match_dup 1) (const_int 0)))] |
13076 | "TARGET_POWERPC64" | |
9ebbca7d GK |
13077 | "@ |
13078 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
13079 | #" | |
f9562f27 | 13080 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13081 | (set_attr "length" "12,16")]) |
13082 | ||
13083 | (define_split | |
13084 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13085 | (compare:CC | |
13086 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13087 | (const_int 0)) | |
13088 | (const_int 0))) | |
13089 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13090 | (gt:DI (match_dup 1) (const_int 0)))] | |
13091 | "TARGET_POWERPC64 && reload_completed" | |
13092 | [(set (match_dup 0) | |
13093 | (gt:DI (match_dup 1) (const_int 0))) | |
13094 | (set (match_dup 2) | |
13095 | (compare:CC (match_dup 0) | |
13096 | (const_int 0)))] | |
13097 | "") | |
f9562f27 | 13098 | |
1fd4e8c1 | 13099 | (define_insn "" |
cd2b37d9 RK |
13100 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13101 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13102 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
13103 | "TARGET_POWER" |
13104 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 13105 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13106 | |
13107 | (define_insn "" | |
9ebbca7d | 13108 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13109 | (compare:CC |
9ebbca7d GK |
13110 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13111 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 13112 | (const_int 0))) |
9ebbca7d | 13113 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13114 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 13115 | "TARGET_POWER" |
9ebbca7d GK |
13116 | "@ |
13117 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
13118 | #" | |
29ae5b89 | 13119 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13120 | (set_attr "length" "12,16")]) |
13121 | ||
13122 | (define_split | |
13123 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13124 | (compare:CC | |
13125 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13126 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13127 | (const_int 0))) | |
13128 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13129 | (gt:SI (match_dup 1) (match_dup 2)))] | |
13130 | "TARGET_POWER && reload_completed" | |
13131 | [(set (match_dup 0) | |
13132 | (gt:SI (match_dup 1) (match_dup 2))) | |
13133 | (set (match_dup 3) | |
13134 | (compare:CC (match_dup 0) | |
13135 | (const_int 0)))] | |
13136 | "") | |
1fd4e8c1 RK |
13137 | |
13138 | (define_insn "" | |
80103f96 | 13139 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13140 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13141 | (const_int 0)) |
80103f96 | 13142 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
f9562f27 | 13143 | "! TARGET_POWERPC64" |
80103f96 | 13144 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
b19003d8 | 13145 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13146 | |
f9562f27 | 13147 | (define_insn "" |
097657c3 | 13148 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
13149 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13150 | (const_int 0)) | |
097657c3 | 13151 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
f9562f27 | 13152 | "TARGET_POWERPC64" |
097657c3 | 13153 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
f9562f27 DE |
13154 | [(set_attr "length" "12")]) |
13155 | ||
1fd4e8c1 | 13156 | (define_insn "" |
9ebbca7d | 13157 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13158 | (compare:CC |
9ebbca7d | 13159 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13160 | (const_int 0)) |
9ebbca7d | 13161 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 13162 | (const_int 0))) |
9ebbca7d | 13163 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 13164 | "! TARGET_POWERPC64" |
9ebbca7d GK |
13165 | "@ |
13166 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
13167 | #" | |
b19003d8 | 13168 | [(set_attr "type" "compare") |
9ebbca7d GK |
13169 | (set_attr "length" "12,16")]) |
13170 | ||
13171 | (define_split | |
13172 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13173 | (compare:CC | |
13174 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13175 | (const_int 0)) | |
13176 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
13177 | (const_int 0))) | |
13178 | (clobber (match_scratch:SI 3 ""))] | |
13179 | "! TARGET_POWERPC64 && reload_completed" | |
13180 | [(set (match_dup 3) | |
13181 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
13182 | (match_dup 2))) | |
13183 | (set (match_dup 0) | |
13184 | (compare:CC (match_dup 3) | |
13185 | (const_int 0)))] | |
13186 | "") | |
1fd4e8c1 | 13187 | |
f9562f27 | 13188 | (define_insn "" |
9ebbca7d | 13189 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 13190 | (compare:CC |
9ebbca7d | 13191 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13192 | (const_int 0)) |
9ebbca7d | 13193 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13194 | (const_int 0))) |
9ebbca7d | 13195 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 13196 | "TARGET_POWERPC64" |
9ebbca7d GK |
13197 | "@ |
13198 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
13199 | #" | |
f9562f27 | 13200 | [(set_attr "type" "compare") |
9ebbca7d GK |
13201 | (set_attr "length" "12,16")]) |
13202 | ||
13203 | (define_split | |
13204 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13205 | (compare:CC | |
13206 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13207 | (const_int 0)) | |
13208 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13209 | (const_int 0))) | |
13210 | (clobber (match_scratch:DI 3 ""))] | |
13211 | "TARGET_POWERPC64 && reload_completed" | |
13212 | [(set (match_dup 3) | |
13213 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 13214 | (match_dup 2))) |
9ebbca7d GK |
13215 | (set (match_dup 0) |
13216 | (compare:CC (match_dup 3) | |
13217 | (const_int 0)))] | |
13218 | "") | |
f9562f27 | 13219 | |
1fd4e8c1 | 13220 | (define_insn "" |
097657c3 | 13221 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
13222 | (compare:CC |
13223 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
13224 | (const_int 0)) | |
13225 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
13226 | (const_int 0))) | |
097657c3 AM |
13227 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13228 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
9ebbca7d GK |
13229 | "! TARGET_POWERPC64" |
13230 | "@ | |
097657c3 | 13231 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
13232 | #" |
13233 | [(set_attr "type" "compare") | |
13234 | (set_attr "length" "12,16")]) | |
13235 | ||
13236 | (define_split | |
097657c3 | 13237 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 13238 | (compare:CC |
9ebbca7d | 13239 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 13240 | (const_int 0)) |
9ebbca7d | 13241 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 13242 | (const_int 0))) |
9ebbca7d | 13243 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 13244 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
9ebbca7d | 13245 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 13246 | [(set (match_dup 0) |
9ebbca7d | 13247 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13248 | (set (match_dup 3) |
9ebbca7d GK |
13249 | (compare:CC (match_dup 0) |
13250 | (const_int 0)))] | |
13251 | "") | |
1fd4e8c1 | 13252 | |
f9562f27 | 13253 | (define_insn "" |
097657c3 | 13254 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13255 | (compare:CC |
9ebbca7d | 13256 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13257 | (const_int 0)) |
9ebbca7d | 13258 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13259 | (const_int 0))) |
097657c3 AM |
13260 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
13261 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
f9562f27 | 13262 | "TARGET_POWERPC64" |
9ebbca7d | 13263 | "@ |
097657c3 | 13264 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 13265 | #" |
f9562f27 | 13266 | [(set_attr "type" "compare") |
9ebbca7d GK |
13267 | (set_attr "length" "12,16")]) |
13268 | ||
13269 | (define_split | |
097657c3 | 13270 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13271 | (compare:CC |
13272 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13273 | (const_int 0)) | |
13274 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13275 | (const_int 0))) | |
13276 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13277 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
9ebbca7d | 13278 | "TARGET_POWERPC64 && reload_completed" |
097657c3 | 13279 | [(set (match_dup 0) |
9ebbca7d | 13280 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13281 | (set (match_dup 3) |
9ebbca7d GK |
13282 | (compare:CC (match_dup 0) |
13283 | (const_int 0)))] | |
13284 | "") | |
f9562f27 | 13285 | |
1fd4e8c1 | 13286 | (define_insn "" |
097657c3 | 13287 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13288 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13289 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 13290 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 13291 | "TARGET_POWER" |
097657c3 | 13292 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 13293 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13294 | |
13295 | (define_insn "" | |
9ebbca7d | 13296 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13297 | (compare:CC |
9ebbca7d GK |
13298 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13299 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13300 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13301 | (const_int 0))) |
9ebbca7d | 13302 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13303 | "TARGET_POWER" |
9ebbca7d GK |
13304 | "@ |
13305 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
13306 | #" | |
b19003d8 | 13307 | [(set_attr "type" "compare") |
9ebbca7d GK |
13308 | (set_attr "length" "12,16")]) |
13309 | ||
13310 | (define_split | |
13311 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13312 | (compare:CC | |
13313 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13314 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13315 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13316 | (const_int 0))) | |
13317 | (clobber (match_scratch:SI 4 ""))] | |
13318 | "TARGET_POWER && reload_completed" | |
13319 | [(set (match_dup 4) | |
097657c3 | 13320 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
13321 | (set (match_dup 0) |
13322 | (compare:CC (match_dup 4) | |
13323 | (const_int 0)))] | |
13324 | "") | |
1fd4e8c1 RK |
13325 | |
13326 | (define_insn "" | |
097657c3 | 13327 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13328 | (compare:CC |
9ebbca7d GK |
13329 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13330 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13331 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13332 | (const_int 0))) |
097657c3 AM |
13333 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13334 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 13335 | "TARGET_POWER" |
9ebbca7d | 13336 | "@ |
097657c3 | 13337 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 13338 | #" |
b19003d8 | 13339 | [(set_attr "type" "compare") |
9ebbca7d GK |
13340 | (set_attr "length" "12,16")]) |
13341 | ||
13342 | (define_split | |
097657c3 | 13343 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13344 | (compare:CC |
13345 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13346 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13347 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13348 | (const_int 0))) | |
13349 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13350 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13351 | "TARGET_POWER && reload_completed" |
097657c3 | 13352 | [(set (match_dup 0) |
9ebbca7d | 13353 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13354 | (set (match_dup 4) |
9ebbca7d GK |
13355 | (compare:CC (match_dup 0) |
13356 | (const_int 0)))] | |
13357 | "") | |
1fd4e8c1 RK |
13358 | |
13359 | (define_insn "" | |
cd2b37d9 RK |
13360 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13361 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13362 | (const_int 0))))] |
f9562f27 | 13363 | "! TARGET_POWERPC64" |
ca7f5001 | 13364 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 13365 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13366 | |
f9562f27 DE |
13367 | (define_insn "" |
13368 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13369 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13370 | (const_int 0))))] | |
13371 | "TARGET_POWERPC64" | |
8377288b | 13372 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
f9562f27 DE |
13373 | [(set_attr "length" "12")]) |
13374 | ||
1fd4e8c1 | 13375 | (define_insn "" |
cd2b37d9 RK |
13376 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13377 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13378 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
13379 | "TARGET_POWER" |
13380 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 13381 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13382 | |
13383 | (define_insn "" | |
cd2b37d9 RK |
13384 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13385 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13386 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 13387 | "! TARGET_POWERPC64" |
ca7f5001 | 13388 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 13389 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13390 | |
f9562f27 DE |
13391 | (define_insn "" |
13392 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13393 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13394 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
13395 | "TARGET_POWERPC64" | |
13396 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" | |
13397 | [(set_attr "length" "12")]) | |
13398 | ||
1fd4e8c1 | 13399 | (define_insn "" |
9ebbca7d | 13400 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13401 | (compare:CC |
9ebbca7d GK |
13402 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13403 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13404 | (const_int 0))) |
9ebbca7d | 13405 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13406 | (gtu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 13407 | "! TARGET_POWERPC64" |
9ebbca7d GK |
13408 | "@ |
13409 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13410 | #" | |
b19003d8 | 13411 | [(set_attr "type" "compare") |
9ebbca7d GK |
13412 | (set_attr "length" "12,16")]) |
13413 | ||
13414 | (define_split | |
13415 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13416 | (compare:CC | |
13417 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13418 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13419 | (const_int 0))) | |
13420 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13421 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
13422 | "! TARGET_POWERPC64 && reload_completed" | |
13423 | [(set (match_dup 0) | |
13424 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13425 | (set (match_dup 3) | |
13426 | (compare:CC (match_dup 0) | |
13427 | (const_int 0)))] | |
13428 | "") | |
1fd4e8c1 | 13429 | |
f9562f27 | 13430 | (define_insn "" |
9ebbca7d | 13431 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13432 | (compare:CC |
9ebbca7d GK |
13433 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13434 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13435 | (const_int 0))) |
9ebbca7d | 13436 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
13437 | (gtu:DI (match_dup 1) (match_dup 2)))] |
13438 | "TARGET_POWERPC64" | |
9ebbca7d GK |
13439 | "@ |
13440 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13441 | #" | |
f9562f27 | 13442 | [(set_attr "type" "compare") |
9ebbca7d GK |
13443 | (set_attr "length" "12,16")]) |
13444 | ||
13445 | (define_split | |
13446 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13447 | (compare:CC | |
13448 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13449 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13450 | (const_int 0))) | |
13451 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13452 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
13453 | "TARGET_POWERPC64 && reload_completed" | |
13454 | [(set (match_dup 0) | |
13455 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13456 | (set (match_dup 3) | |
13457 | (compare:CC (match_dup 0) | |
13458 | (const_int 0)))] | |
13459 | "") | |
f9562f27 | 13460 | |
1fd4e8c1 | 13461 | (define_insn "" |
80103f96 | 13462 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
13463 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13464 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
80103f96 | 13465 | (match_operand:SI 3 "reg_or_short_operand" "r,rI")))] |
f9562f27 | 13466 | "! TARGET_POWERPC64" |
00751805 | 13467 | "@ |
80103f96 FS |
13468 | {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3 |
13469 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
19378cf8 | 13470 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 13471 | |
f9562f27 | 13472 | (define_insn "" |
097657c3 | 13473 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
f9562f27 DE |
13474 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13475 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
097657c3 | 13476 | (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] |
f9562f27 DE |
13477 | "TARGET_POWERPC64" |
13478 | "@ | |
097657c3 AM |
13479 | addic %0,%1,%k2\;addze %0,%3 |
13480 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" | |
f9562f27 DE |
13481 | [(set_attr "length" "8,12")]) |
13482 | ||
1fd4e8c1 | 13483 | (define_insn "" |
9ebbca7d | 13484 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13485 | (compare:CC |
9ebbca7d GK |
13486 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13487 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13488 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13489 | (const_int 0))) |
9ebbca7d | 13490 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 13491 | "! TARGET_POWERPC64" |
00751805 | 13492 | "@ |
19378cf8 | 13493 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
13494 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
13495 | # | |
13496 | #" | |
b19003d8 | 13497 | [(set_attr "type" "compare") |
9ebbca7d GK |
13498 | (set_attr "length" "8,12,12,16")]) |
13499 | ||
13500 | (define_split | |
13501 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13502 | (compare:CC | |
13503 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13504 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13505 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13506 | (const_int 0))) | |
13507 | (clobber (match_scratch:SI 4 ""))] | |
13508 | "! TARGET_POWERPC64 && reload_completed" | |
13509 | [(set (match_dup 4) | |
13510 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13511 | (match_dup 3))) |
9ebbca7d GK |
13512 | (set (match_dup 0) |
13513 | (compare:CC (match_dup 4) | |
13514 | (const_int 0)))] | |
13515 | "") | |
1fd4e8c1 | 13516 | |
f9562f27 | 13517 | (define_insn "" |
9ebbca7d | 13518 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13519 | (compare:CC |
9ebbca7d GK |
13520 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13521 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13522 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13523 | (const_int 0))) |
9ebbca7d | 13524 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
13525 | "TARGET_POWERPC64" |
13526 | "@ | |
13527 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
13528 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
13529 | # | |
13530 | #" | |
f9562f27 | 13531 | [(set_attr "type" "compare") |
9ebbca7d GK |
13532 | (set_attr "length" "8,12,12,16")]) |
13533 | ||
13534 | (define_split | |
13535 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13536 | (compare:CC | |
13537 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13538 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13539 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13540 | (const_int 0))) | |
13541 | (clobber (match_scratch:DI 4 ""))] | |
13542 | "TARGET_POWERPC64 && reload_completed" | |
13543 | [(set (match_dup 4) | |
13544 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13545 | (match_dup 3))) | |
13546 | (set (match_dup 0) | |
13547 | (compare:CC (match_dup 4) | |
13548 | (const_int 0)))] | |
13549 | "") | |
f9562f27 | 13550 | |
1fd4e8c1 | 13551 | (define_insn "" |
097657c3 | 13552 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13553 | (compare:CC |
9ebbca7d GK |
13554 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13555 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13556 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13557 | (const_int 0))) |
097657c3 AM |
13558 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13559 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 13560 | "! TARGET_POWERPC64" |
00751805 | 13561 | "@ |
097657c3 AM |
13562 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
13563 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
13564 | # |
13565 | #" | |
b19003d8 | 13566 | [(set_attr "type" "compare") |
9ebbca7d GK |
13567 | (set_attr "length" "8,12,12,16")]) |
13568 | ||
13569 | (define_split | |
097657c3 | 13570 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13571 | (compare:CC |
13572 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13573 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13574 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13575 | (const_int 0))) | |
13576 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13577 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13578 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 13579 | [(set (match_dup 0) |
9ebbca7d | 13580 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13581 | (set (match_dup 4) |
9ebbca7d GK |
13582 | (compare:CC (match_dup 0) |
13583 | (const_int 0)))] | |
13584 | "") | |
1fd4e8c1 | 13585 | |
f9562f27 | 13586 | (define_insn "" |
097657c3 | 13587 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13588 | (compare:CC |
9ebbca7d GK |
13589 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13590 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13591 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13592 | (const_int 0))) |
097657c3 AM |
13593 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13594 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 DE |
13595 | "TARGET_POWERPC64" |
13596 | "@ | |
097657c3 AM |
13597 | addic %0,%1,%k2\;addze. %0,%3 |
13598 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 | |
9ebbca7d GK |
13599 | # |
13600 | #" | |
f9562f27 | 13601 | [(set_attr "type" "compare") |
9ebbca7d GK |
13602 | (set_attr "length" "8,12,12,16")]) |
13603 | ||
13604 | (define_split | |
097657c3 | 13605 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13606 | (compare:CC |
13607 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13608 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13609 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13610 | (const_int 0))) | |
13611 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13612 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13613 | "TARGET_POWERPC64 && reload_completed" |
097657c3 | 13614 | [(set (match_dup 0) |
9ebbca7d | 13615 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13616 | (set (match_dup 4) |
9ebbca7d GK |
13617 | (compare:CC (match_dup 0) |
13618 | (const_int 0)))] | |
13619 | "") | |
f9562f27 | 13620 | |
1fd4e8c1 | 13621 | (define_insn "" |
cd2b37d9 RK |
13622 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13623 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13624 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 13625 | "! TARGET_POWERPC64" |
ca7f5001 | 13626 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 13627 | [(set_attr "length" "8")]) |
f9562f27 DE |
13628 | |
13629 | (define_insn "" | |
13630 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13631 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13632 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
13633 | "TARGET_POWERPC64" | |
13634 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" | |
13635 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
13636 | \f |
13637 | ;; Define both directions of branch and return. If we need a reload | |
13638 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13639 | ;; register CC value to there. | |
13640 | ||
13641 | (define_insn "" | |
13642 | [(set (pc) | |
13643 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13644 | [(match_operand 2 | |
b54cf83a | 13645 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13646 | (const_int 0)]) |
13647 | (label_ref (match_operand 0 "" "")) | |
13648 | (pc)))] | |
13649 | "" | |
b19003d8 RK |
13650 | "* |
13651 | { | |
12a4e8c5 | 13652 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13653 | }" |
13654 | [(set_attr "type" "branch")]) | |
13655 | ||
1fd4e8c1 RK |
13656 | (define_insn "" |
13657 | [(set (pc) | |
13658 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13659 | [(match_operand 1 | |
b54cf83a | 13660 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13661 | (const_int 0)]) |
13662 | (return) | |
13663 | (pc)))] | |
13664 | "direct_return ()" | |
12a4e8c5 GK |
13665 | "* |
13666 | { | |
13667 | return output_cbranch (operands[0], NULL, 0, insn); | |
13668 | }" | |
b7ff3d82 | 13669 | [(set_attr "type" "branch") |
39a10a29 | 13670 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
13671 | |
13672 | (define_insn "" | |
13673 | [(set (pc) | |
13674 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13675 | [(match_operand 2 | |
b54cf83a | 13676 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13677 | (const_int 0)]) |
13678 | (pc) | |
13679 | (label_ref (match_operand 0 "" ""))))] | |
13680 | "" | |
b19003d8 RK |
13681 | "* |
13682 | { | |
12a4e8c5 | 13683 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13684 | }" |
13685 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13686 | |
13687 | (define_insn "" | |
13688 | [(set (pc) | |
13689 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13690 | [(match_operand 1 | |
b54cf83a | 13691 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13692 | (const_int 0)]) |
13693 | (pc) | |
13694 | (return)))] | |
13695 | "direct_return ()" | |
12a4e8c5 GK |
13696 | "* |
13697 | { | |
13698 | return output_cbranch (operands[0], NULL, 1, insn); | |
13699 | }" | |
b7ff3d82 | 13700 | [(set_attr "type" "branch") |
39a10a29 GK |
13701 | (set_attr "length" "4")]) |
13702 | ||
13703 | ;; Logic on condition register values. | |
13704 | ||
13705 | ; This pattern matches things like | |
13706 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
13707 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
13708 | ; (const_int 1))) | |
13709 | ; which are generated by the branch logic. | |
b54cf83a | 13710 | ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) |
39a10a29 GK |
13711 | |
13712 | (define_insn "" | |
b54cf83a | 13713 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13714 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" |
b54cf83a | 13715 | [(match_operator:SI 2 |
39a10a29 GK |
13716 | "branch_positive_comparison_operator" |
13717 | [(match_operand 3 | |
b54cf83a | 13718 | "cc_reg_operand" "y,y") |
39a10a29 | 13719 | (const_int 0)]) |
b54cf83a | 13720 | (match_operator:SI 4 |
39a10a29 GK |
13721 | "branch_positive_comparison_operator" |
13722 | [(match_operand 5 | |
b54cf83a | 13723 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13724 | (const_int 0)])]) |
13725 | (const_int 1)))] | |
13726 | "" | |
13727 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13728 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13729 | |
13730 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
13731 | ; Because ~1 has all but the low bit set. | |
13732 | (define_insn "" | |
b54cf83a | 13733 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13734 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" |
b54cf83a | 13735 | [(not:SI (match_operator:SI 2 |
39a10a29 GK |
13736 | "branch_positive_comparison_operator" |
13737 | [(match_operand 3 | |
b54cf83a | 13738 | "cc_reg_operand" "y,y") |
39a10a29 GK |
13739 | (const_int 0)])) |
13740 | (match_operator:SI 4 | |
13741 | "branch_positive_comparison_operator" | |
13742 | [(match_operand 5 | |
b54cf83a | 13743 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13744 | (const_int 0)])]) |
13745 | (const_int -1)))] | |
13746 | "" | |
13747 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13748 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13749 | |
13750 | (define_insn "" | |
b54cf83a | 13751 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
6c873122 | 13752 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 13753 | "branch_positive_comparison_operator" |
6c873122 | 13754 | [(match_operand 2 |
b54cf83a | 13755 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13756 | (const_int 0)]) |
13757 | (const_int 0)))] | |
fe6b547a | 13758 | "!TARGET_SPE" |
251b3667 | 13759 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
b54cf83a | 13760 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13761 | |
13762 | ;; If we are comparing the result of two comparisons, this can be done | |
13763 | ;; using creqv or crxor. | |
13764 | ||
13765 | (define_insn_and_split "" | |
13766 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13767 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
13768 | [(match_operand 2 "cc_reg_operand" "y") | |
13769 | (const_int 0)]) | |
13770 | (match_operator 3 "branch_comparison_operator" | |
13771 | [(match_operand 4 "cc_reg_operand" "y") | |
13772 | (const_int 0)])))] | |
13773 | "" | |
13774 | "#" | |
13775 | "" | |
13776 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13777 | (match_dup 5)))] | |
13778 | " | |
13779 | { | |
13780 | int positive_1, positive_2; | |
13781 | ||
13782 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
13783 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
13784 | ||
13785 | if (! positive_1) | |
2d4368e6 | 13786 | operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]), |
39a10a29 | 13787 | GET_CODE (operands[1])), |
2d4368e6 DE |
13788 | SImode, |
13789 | operands[2], const0_rtx); | |
39a10a29 | 13790 | else if (GET_MODE (operands[1]) != SImode) |
2d4368e6 DE |
13791 | operands[1] = gen_rtx (GET_CODE (operands[1]), |
13792 | SImode, | |
13793 | operands[2], const0_rtx); | |
39a10a29 GK |
13794 | |
13795 | if (! positive_2) | |
2d4368e6 | 13796 | operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]), |
39a10a29 | 13797 | GET_CODE (operands[3])), |
2d4368e6 DE |
13798 | SImode, |
13799 | operands[4], const0_rtx); | |
39a10a29 | 13800 | else if (GET_MODE (operands[3]) != SImode) |
2d4368e6 DE |
13801 | operands[3] = gen_rtx (GET_CODE (operands[3]), |
13802 | SImode, | |
13803 | operands[4], const0_rtx); | |
39a10a29 GK |
13804 | |
13805 | if (positive_1 == positive_2) | |
251b3667 DE |
13806 | { |
13807 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13808 | operands[5] = constm1_rtx; | |
13809 | } | |
13810 | else | |
13811 | { | |
13812 | operands[5] = const1_rtx; | |
13813 | } | |
39a10a29 | 13814 | }") |
1fd4e8c1 RK |
13815 | |
13816 | ;; Unconditional branch and return. | |
13817 | ||
13818 | (define_insn "jump" | |
13819 | [(set (pc) | |
13820 | (label_ref (match_operand 0 "" "")))] | |
13821 | "" | |
b7ff3d82 DE |
13822 | "b %l0" |
13823 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13824 | |
13825 | (define_insn "return" | |
13826 | [(return)] | |
13827 | "direct_return ()" | |
324e52cc TG |
13828 | "{br|blr}" |
13829 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13830 | |
0ad91047 DE |
13831 | (define_expand "indirect_jump" |
13832 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 13833 | "" |
0ad91047 DE |
13834 | " |
13835 | { | |
13836 | if (TARGET_32BIT) | |
13837 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
13838 | else | |
13839 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
13840 | DONE; | |
13841 | }") | |
13842 | ||
13843 | (define_insn "indirect_jumpsi" | |
b92b324d | 13844 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 13845 | "TARGET_32BIT" |
b92b324d DE |
13846 | "@ |
13847 | bctr | |
13848 | {br|blr}" | |
324e52cc | 13849 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13850 | |
0ad91047 | 13851 | (define_insn "indirect_jumpdi" |
b92b324d | 13852 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 13853 | "TARGET_64BIT" |
b92b324d DE |
13854 | "@ |
13855 | bctr | |
13856 | blr" | |
266eb58a DE |
13857 | [(set_attr "type" "jmpreg")]) |
13858 | ||
1fd4e8c1 RK |
13859 | ;; Table jump for switch statements: |
13860 | (define_expand "tablejump" | |
e6ca2c17 DE |
13861 | [(use (match_operand 0 "" "")) |
13862 | (use (label_ref (match_operand 1 "" "")))] | |
13863 | "" | |
13864 | " | |
13865 | { | |
13866 | if (TARGET_32BIT) | |
13867 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13868 | else | |
13869 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13870 | DONE; | |
13871 | }") | |
13872 | ||
13873 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13874 | [(set (match_dup 3) |
13875 | (plus:SI (match_operand:SI 0 "" "") | |
13876 | (match_dup 2))) | |
13877 | (parallel [(set (pc) (match_dup 3)) | |
13878 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13879 | "TARGET_32BIT" |
1fd4e8c1 RK |
13880 | " |
13881 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13882 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13883 | operands[3] = gen_reg_rtx (SImode); |
13884 | }") | |
13885 | ||
e6ca2c17 | 13886 | (define_expand "tablejumpdi" |
9ebbca7d GK |
13887 | [(set (match_dup 4) |
13888 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) | |
13889 | (set (match_dup 3) | |
13890 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13891 | (match_dup 2))) |
13892 | (parallel [(set (pc) (match_dup 3)) | |
13893 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13894 | "TARGET_64BIT" |
e6ca2c17 | 13895 | " |
9ebbca7d | 13896 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13897 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13898 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13899 | }") |
13900 | ||
1fd4e8c1 RK |
13901 | (define_insn "" |
13902 | [(set (pc) | |
c859cda6 | 13903 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13904 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13905 | "TARGET_32BIT" |
c859cda6 DJ |
13906 | "@ |
13907 | bctr | |
13908 | {br|blr}" | |
a6845123 | 13909 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13910 | |
266eb58a DE |
13911 | (define_insn "" |
13912 | [(set (pc) | |
c859cda6 | 13913 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 13914 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13915 | "TARGET_64BIT" |
c859cda6 DJ |
13916 | "@ |
13917 | bctr | |
13918 | blr" | |
266eb58a DE |
13919 | [(set_attr "type" "jmpreg")]) |
13920 | ||
1fd4e8c1 RK |
13921 | (define_insn "nop" |
13922 | [(const_int 0)] | |
13923 | "" | |
ca7f5001 | 13924 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13925 | \f |
7e69e155 | 13926 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13927 | ;; so loop.c knows what to generate. |
13928 | ||
5527bf14 RH |
13929 | (define_expand "doloop_end" |
13930 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13931 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13932 | (use (match_operand 2 "" "")) ; max iterations | |
13933 | (use (match_operand 3 "" "")) ; loop level | |
13934 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13935 | "" |
13936 | " | |
13937 | { | |
5527bf14 RH |
13938 | /* Only use this on innermost loops. */ |
13939 | if (INTVAL (operands[3]) > 1) | |
13940 | FAIL; | |
0ad91047 | 13941 | if (TARGET_POWERPC64) |
5527bf14 RH |
13942 | { |
13943 | if (GET_MODE (operands[0]) != DImode) | |
13944 | FAIL; | |
13945 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13946 | } | |
0ad91047 | 13947 | else |
5527bf14 RH |
13948 | { |
13949 | if (GET_MODE (operands[0]) != SImode) | |
13950 | FAIL; | |
13951 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13952 | } | |
0ad91047 DE |
13953 | DONE; |
13954 | }") | |
13955 | ||
13956 | (define_expand "ctrsi" | |
3cb999d8 DE |
13957 | [(parallel [(set (pc) |
13958 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
13959 | (const_int 1)) | |
13960 | (label_ref (match_operand 1 "" "")) | |
13961 | (pc))) | |
b6c9286a MM |
13962 | (set (match_dup 0) |
13963 | (plus:SI (match_dup 0) | |
13964 | (const_int -1))) | |
5f81043f RK |
13965 | (clobber (match_scratch:CC 2 "")) |
13966 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
13967 | "! TARGET_POWERPC64" |
13968 | "") | |
13969 | ||
13970 | (define_expand "ctrdi" | |
3cb999d8 DE |
13971 | [(parallel [(set (pc) |
13972 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
13973 | (const_int 1)) | |
13974 | (label_ref (match_operand 1 "" "")) | |
13975 | (pc))) | |
0ad91047 DE |
13976 | (set (match_dup 0) |
13977 | (plus:DI (match_dup 0) | |
13978 | (const_int -1))) | |
13979 | (clobber (match_scratch:CC 2 "")) | |
61c07d3c | 13980 | (clobber (match_scratch:DI 3 ""))])] |
0ad91047 | 13981 | "TARGET_POWERPC64" |
61c07d3c | 13982 | "") |
c225ba7b | 13983 | |
1fd4e8c1 RK |
13984 | ;; We need to be able to do this for any operand, including MEM, or we |
13985 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 13986 | ;; JUMP_INSNs. |
0ad91047 | 13987 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
13988 | ;; label MUST be operand 0. |
13989 | ||
0ad91047 | 13990 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 13991 | [(set (pc) |
5f81043f | 13992 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 13993 | (const_int 1)) |
a6845123 | 13994 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13995 | (pc))) |
5f81043f RK |
13996 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13997 | (plus:SI (match_dup 1) | |
13998 | (const_int -1))) | |
1fd4e8c1 RK |
13999 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14000 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 14001 | "! TARGET_POWERPC64" |
b19003d8 RK |
14002 | "* |
14003 | { | |
af87a13e | 14004 | if (which_alternative != 0) |
b19003d8 | 14005 | return \"#\"; |
856a6884 | 14006 | else if (get_attr_length (insn) == 4) |
a6845123 | 14007 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 14008 | else |
f607bc57 | 14009 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 14010 | }" |
baf97f86 | 14011 | [(set_attr "type" "branch") |
914a7297 | 14012 | (set_attr "length" "4,12,16")]) |
7e69e155 | 14013 | |
0ad91047 | 14014 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
14015 | [(set (pc) |
14016 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
14017 | (const_int 1)) | |
14018 | (pc) | |
14019 | (label_ref (match_operand 0 "" "")))) | |
14020 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
14021 | (plus:SI (match_dup 1) | |
14022 | (const_int -1))) | |
14023 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
14024 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
14025 | "! TARGET_POWERPC64" |
14026 | "* | |
14027 | { | |
14028 | if (which_alternative != 0) | |
14029 | return \"#\"; | |
856a6884 | 14030 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14031 | return \"bdz %l0\"; |
14032 | else | |
f607bc57 | 14033 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14034 | }" |
14035 | [(set_attr "type" "branch") | |
914a7297 | 14036 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14037 | |
14038 | (define_insn "*ctrdi_internal1" | |
14039 | [(set (pc) | |
61c07d3c | 14040 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14041 | (const_int 1)) |
14042 | (label_ref (match_operand 0 "" "")) | |
14043 | (pc))) | |
61c07d3c | 14044 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14045 | (plus:DI (match_dup 1) |
14046 | (const_int -1))) | |
61c07d3c DE |
14047 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14048 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
14049 | "TARGET_POWERPC64" |
14050 | "* | |
14051 | { | |
14052 | if (which_alternative != 0) | |
14053 | return \"#\"; | |
856a6884 | 14054 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14055 | return \"{bdn|bdnz} %l0\"; |
14056 | else | |
f607bc57 | 14057 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14058 | }" |
14059 | [(set_attr "type" "branch") | |
914a7297 | 14060 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14061 | |
14062 | (define_insn "*ctrdi_internal2" | |
14063 | [(set (pc) | |
61c07d3c | 14064 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14065 | (const_int 1)) |
14066 | (pc) | |
14067 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 14068 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14069 | (plus:DI (match_dup 1) |
14070 | (const_int -1))) | |
61c07d3c DE |
14071 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14072 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 | 14073 | "TARGET_POWERPC64" |
5f81043f RK |
14074 | "* |
14075 | { | |
14076 | if (which_alternative != 0) | |
14077 | return \"#\"; | |
856a6884 | 14078 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14079 | return \"bdz %l0\"; |
14080 | else | |
f607bc57 | 14081 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
14082 | }" |
14083 | [(set_attr "type" "branch") | |
914a7297 | 14084 | (set_attr "length" "4,12,16")]) |
5f81043f | 14085 | |
c225ba7b | 14086 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
14087 | |
14088 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 14089 | [(set (pc) |
5f81043f | 14090 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 14091 | (const_int 0)) |
a6845123 | 14092 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14093 | (pc))) |
5f81043f RK |
14094 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
14095 | (plus:SI (match_dup 1) | |
14096 | (const_int -1))) | |
1fd4e8c1 RK |
14097 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
14098 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 14099 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
14100 | "* |
14101 | { | |
af87a13e | 14102 | if (which_alternative != 0) |
b19003d8 | 14103 | return \"#\"; |
856a6884 | 14104 | else if (get_attr_length (insn) == 4) |
a6845123 | 14105 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 14106 | else |
f607bc57 | 14107 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 14108 | }" |
baf97f86 | 14109 | [(set_attr "type" "branch") |
914a7297 | 14110 | (set_attr "length" "4,12,16")]) |
7e69e155 | 14111 | |
0ad91047 | 14112 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 14113 | [(set (pc) |
5f81043f RK |
14114 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
14115 | (const_int 0)) | |
14116 | (pc) | |
14117 | (label_ref (match_operand 0 "" "")))) | |
14118 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
14119 | (plus:SI (match_dup 1) | |
14120 | (const_int -1))) | |
14121 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
14122 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 14123 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
14124 | "* |
14125 | { | |
14126 | if (which_alternative != 0) | |
14127 | return \"#\"; | |
856a6884 | 14128 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14129 | return \"bdz %l0\"; |
14130 | else | |
f607bc57 | 14131 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
14132 | }" |
14133 | [(set_attr "type" "branch") | |
914a7297 | 14134 | (set_attr "length" "4,12,16")]) |
5f81043f | 14135 | |
0ad91047 DE |
14136 | (define_insn "*ctrdi_internal3" |
14137 | [(set (pc) | |
61c07d3c | 14138 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14139 | (const_int 0)) |
14140 | (label_ref (match_operand 0 "" "")) | |
14141 | (pc))) | |
61c07d3c | 14142 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14143 | (plus:DI (match_dup 1) |
14144 | (const_int -1))) | |
61c07d3c DE |
14145 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14146 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
14147 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
14148 | "* | |
14149 | { | |
14150 | if (which_alternative != 0) | |
14151 | return \"#\"; | |
856a6884 | 14152 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14153 | return \"{bdn|bdnz} %l0\"; |
14154 | else | |
f607bc57 | 14155 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14156 | }" |
14157 | [(set_attr "type" "branch") | |
914a7297 | 14158 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14159 | |
14160 | (define_insn "*ctrdi_internal4" | |
14161 | [(set (pc) | |
61c07d3c | 14162 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14163 | (const_int 0)) |
14164 | (pc) | |
14165 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 14166 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14167 | (plus:DI (match_dup 1) |
14168 | (const_int -1))) | |
61c07d3c DE |
14169 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14170 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
14171 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
14172 | "* | |
14173 | { | |
14174 | if (which_alternative != 0) | |
14175 | return \"#\"; | |
856a6884 | 14176 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14177 | return \"bdz %l0\"; |
14178 | else | |
f607bc57 | 14179 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14180 | }" |
14181 | [(set_attr "type" "branch") | |
914a7297 | 14182 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14183 | |
14184 | ;; Similar but use EQ | |
14185 | ||
14186 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
14187 | [(set (pc) |
14188 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 14189 | (const_int 1)) |
a6845123 | 14190 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14191 | (pc))) |
5f81043f RK |
14192 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
14193 | (plus:SI (match_dup 1) | |
14194 | (const_int -1))) | |
1fd4e8c1 RK |
14195 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14196 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 14197 | "! TARGET_POWERPC64" |
b19003d8 RK |
14198 | "* |
14199 | { | |
af87a13e | 14200 | if (which_alternative != 0) |
b19003d8 | 14201 | return \"#\"; |
856a6884 | 14202 | else if (get_attr_length (insn) == 4) |
a6845123 | 14203 | return \"bdz %l0\"; |
b19003d8 | 14204 | else |
f607bc57 | 14205 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 14206 | }" |
baf97f86 | 14207 | [(set_attr "type" "branch") |
914a7297 | 14208 | (set_attr "length" "4,12,16")]) |
1fd4e8c1 | 14209 | |
0ad91047 | 14210 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
14211 | [(set (pc) |
14212 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
14213 | (const_int 1)) | |
14214 | (pc) | |
14215 | (label_ref (match_operand 0 "" "")))) | |
14216 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
14217 | (plus:SI (match_dup 1) | |
14218 | (const_int -1))) | |
14219 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
14220 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
14221 | "! TARGET_POWERPC64" |
14222 | "* | |
14223 | { | |
14224 | if (which_alternative != 0) | |
14225 | return \"#\"; | |
856a6884 | 14226 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14227 | return \"{bdn|bdnz} %l0\"; |
14228 | else | |
f607bc57 | 14229 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14230 | }" |
14231 | [(set_attr "type" "branch") | |
914a7297 | 14232 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14233 | |
14234 | (define_insn "*ctrdi_internal5" | |
14235 | [(set (pc) | |
61c07d3c | 14236 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14237 | (const_int 1)) |
14238 | (label_ref (match_operand 0 "" "")) | |
14239 | (pc))) | |
61c07d3c | 14240 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14241 | (plus:DI (match_dup 1) |
14242 | (const_int -1))) | |
61c07d3c DE |
14243 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14244 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
14245 | "TARGET_POWERPC64" |
14246 | "* | |
14247 | { | |
14248 | if (which_alternative != 0) | |
14249 | return \"#\"; | |
856a6884 | 14250 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14251 | return \"bdz %l0\"; |
14252 | else | |
f607bc57 | 14253 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14254 | }" |
14255 | [(set_attr "type" "branch") | |
914a7297 | 14256 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14257 | |
14258 | (define_insn "*ctrdi_internal6" | |
14259 | [(set (pc) | |
61c07d3c | 14260 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14261 | (const_int 1)) |
14262 | (pc) | |
14263 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 14264 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14265 | (plus:DI (match_dup 1) |
14266 | (const_int -1))) | |
61c07d3c DE |
14267 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14268 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 | 14269 | "TARGET_POWERPC64" |
5f81043f RK |
14270 | "* |
14271 | { | |
14272 | if (which_alternative != 0) | |
14273 | return \"#\"; | |
856a6884 | 14274 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14275 | return \"{bdn|bdnz} %l0\"; |
14276 | else | |
f607bc57 | 14277 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
14278 | }" |
14279 | [(set_attr "type" "branch") | |
914a7297 | 14280 | (set_attr "length" "4,12,16")]) |
5f81043f | 14281 | |
0ad91047 DE |
14282 | ;; Now the splitters if we could not allocate the CTR register |
14283 | ||
1fd4e8c1 RK |
14284 | (define_split |
14285 | [(set (pc) | |
14286 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14287 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14288 | (const_int 1)]) |
14289 | (match_operand 5 "" "") | |
14290 | (match_operand 6 "" ""))) | |
cd2b37d9 | 14291 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
14292 | (plus:SI (match_dup 1) |
14293 | (const_int -1))) | |
1fd4e8c1 RK |
14294 | (clobber (match_scratch:CC 3 "")) |
14295 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 14296 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 14297 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14298 | (compare:CC (plus:SI (match_dup 1) |
14299 | (const_int -1)) | |
1fd4e8c1 | 14300 | (const_int 0))) |
5f81043f RK |
14301 | (set (match_dup 0) |
14302 | (plus:SI (match_dup 1) | |
14303 | (const_int -1)))]) | |
14304 | (set (pc) (if_then_else (match_dup 7) | |
14305 | (match_dup 5) | |
14306 | (match_dup 6)))] | |
1fd4e8c1 RK |
14307 | " |
14308 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
14309 | const0_rtx); }") | |
14310 | ||
14311 | (define_split | |
14312 | [(set (pc) | |
14313 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14314 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14315 | (const_int 1)]) |
14316 | (match_operand 5 "" "") | |
14317 | (match_operand 6 "" ""))) | |
9ebbca7d | 14318 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
14319 | (plus:SI (match_dup 1) (const_int -1))) |
14320 | (clobber (match_scratch:CC 3 "")) | |
14321 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
14322 | "! TARGET_POWERPC64 && reload_completed |
14323 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 14324 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14325 | (compare:CC (plus:SI (match_dup 1) |
14326 | (const_int -1)) | |
1fd4e8c1 | 14327 | (const_int 0))) |
5f81043f RK |
14328 | (set (match_dup 4) |
14329 | (plus:SI (match_dup 1) | |
14330 | (const_int -1)))]) | |
14331 | (set (match_dup 0) | |
14332 | (match_dup 4)) | |
14333 | (set (pc) (if_then_else (match_dup 7) | |
14334 | (match_dup 5) | |
14335 | (match_dup 6)))] | |
1fd4e8c1 RK |
14336 | " |
14337 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
14338 | const0_rtx); }") | |
0ad91047 DE |
14339 | (define_split |
14340 | [(set (pc) | |
14341 | (if_then_else (match_operator 2 "comparison_operator" | |
14342 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14343 | (const_int 1)]) | |
61c07d3c DE |
14344 | (match_operand 5 "" "") |
14345 | (match_operand 6 "" ""))) | |
0ad91047 DE |
14346 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
14347 | (plus:DI (match_dup 1) | |
14348 | (const_int -1))) | |
14349 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c DE |
14350 | (clobber (match_scratch:DI 4 ""))] |
14351 | "TARGET_POWERPC64 && reload_completed" | |
0ad91047 DE |
14352 | [(parallel [(set (match_dup 3) |
14353 | (compare:CC (plus:DI (match_dup 1) | |
14354 | (const_int -1)) | |
14355 | (const_int 0))) | |
14356 | (set (match_dup 0) | |
14357 | (plus:DI (match_dup 1) | |
14358 | (const_int -1)))]) | |
61c07d3c DE |
14359 | (set (pc) (if_then_else (match_dup 7) |
14360 | (match_dup 5) | |
14361 | (match_dup 6)))] | |
0ad91047 | 14362 | " |
61c07d3c | 14363 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], |
0ad91047 DE |
14364 | const0_rtx); }") |
14365 | ||
14366 | (define_split | |
14367 | [(set (pc) | |
14368 | (if_then_else (match_operator 2 "comparison_operator" | |
14369 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14370 | (const_int 1)]) | |
61c07d3c DE |
14371 | (match_operand 5 "" "") |
14372 | (match_operand 6 "" ""))) | |
9ebbca7d | 14373 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
14374 | (plus:DI (match_dup 1) (const_int -1))) |
14375 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14376 | (clobber (match_scratch:DI 4 ""))] |
0ad91047 DE |
14377 | "TARGET_POWERPC64 && reload_completed |
14378 | && ! gpc_reg_operand (operands[0], DImode)" | |
14379 | [(parallel [(set (match_dup 3) | |
14380 | (compare:CC (plus:DI (match_dup 1) | |
14381 | (const_int -1)) | |
14382 | (const_int 0))) | |
14383 | (set (match_dup 4) | |
14384 | (plus:DI (match_dup 1) | |
14385 | (const_int -1)))]) | |
14386 | (set (match_dup 0) | |
14387 | (match_dup 4)) | |
61c07d3c DE |
14388 | (set (pc) (if_then_else (match_dup 7) |
14389 | (match_dup 5) | |
14390 | (match_dup 6)))] | |
0ad91047 | 14391 | " |
61c07d3c | 14392 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], |
0ad91047 | 14393 | const0_rtx); }") |
c94ccb87 | 14394 | |
e0cd0770 JC |
14395 | \f |
14396 | (define_insn "trap" | |
14397 | [(trap_if (const_int 1) (const_int 0))] | |
14398 | "" | |
14399 | "{t 31,0,0|trap}") | |
14400 | ||
14401 | (define_expand "conditional_trap" | |
14402 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14403 | [(match_dup 2) (match_dup 3)]) | |
14404 | (match_operand 1 "const_int_operand" ""))] | |
14405 | "" | |
14406 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14407 | operands[2] = rs6000_compare_op0; | |
14408 | operands[3] = rs6000_compare_op1;") | |
14409 | ||
14410 | (define_insn "" | |
14411 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14412 | [(match_operand:SI 1 "register_operand" "r") | |
14413 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14414 | (const_int 0))] | |
14415 | "" | |
a157febd GK |
14416 | "{t|tw}%V0%I2 %1,%2") |
14417 | ||
14418 | (define_insn "" | |
14419 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14420 | [(match_operand:DI 1 "register_operand" "r") | |
14421 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14422 | (const_int 0))] | |
14423 | "TARGET_POWERPC64" | |
14424 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14425 | \f |
14426 | ;; Insns related to generating the function prologue and epilogue. | |
14427 | ||
14428 | (define_expand "prologue" | |
14429 | [(use (const_int 0))] | |
14430 | "TARGET_SCHED_PROLOG" | |
14431 | " | |
14432 | { | |
14433 | rs6000_emit_prologue (); | |
14434 | DONE; | |
14435 | }") | |
14436 | ||
14437 | (define_insn "movesi_from_cr" | |
14438 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
14439 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) | |
615158e2 JJ |
14440 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] |
14441 | UNSPEC_MOVESI_FROM_CR))] | |
9ebbca7d | 14442 | "" |
309323c2 | 14443 | "mfcr %0" |
b54cf83a | 14444 | [(set_attr "type" "mfcr")]) |
9ebbca7d GK |
14445 | |
14446 | (define_insn "*stmw" | |
e033a023 DE |
14447 | [(match_parallel 0 "stmw_operation" |
14448 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14449 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14450 | "TARGET_MULTIPLE" | |
14451 | "{stm|stmw} %2,%1") | |
9ebbca7d GK |
14452 | |
14453 | (define_insn "*save_fpregs_si" | |
e033a023 DE |
14454 | [(match_parallel 0 "any_operand" |
14455 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
14456 | (use (match_operand:SI 2 "call_operand" "s")) | |
14457 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14458 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14459 | "TARGET_32BIT" | |
14460 | "bl %z2" | |
14461 | [(set_attr "type" "branch") | |
14462 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14463 | |
14464 | (define_insn "*save_fpregs_di" | |
e033a023 DE |
14465 | [(match_parallel 0 "any_operand" |
14466 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
14467 | (use (match_operand:DI 2 "call_operand" "s")) | |
14468 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14469 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14470 | "TARGET_64BIT" | |
14471 | "bl %z2" | |
14472 | [(set_attr "type" "branch") | |
14473 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14474 | |
14475 | ; These are to explain that changes to the stack pointer should | |
14476 | ; not be moved over stores to stack memory. | |
14477 | (define_insn "stack_tie" | |
14478 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
615158e2 | 14479 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] |
9ebbca7d GK |
14480 | "" |
14481 | "" | |
14482 | [(set_attr "length" "0")]) | |
14483 | ||
14484 | ||
14485 | (define_expand "epilogue" | |
14486 | [(use (const_int 0))] | |
14487 | "TARGET_SCHED_PROLOG" | |
14488 | " | |
14489 | { | |
14490 | rs6000_emit_epilogue (FALSE); | |
14491 | DONE; | |
14492 | }") | |
14493 | ||
14494 | ; On some processors, doing the mtcrf one CC register at a time is | |
14495 | ; faster (like on the 604e). On others, doing them all at once is | |
14496 | ; faster; for instance, on the 601 and 750. | |
14497 | ||
14498 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
14499 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14500 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 | 14501 | (match_dup 2)] UNSPEC_MOVESI_TO_CR))] |
35aba846 DE |
14502 | "" |
14503 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
14504 | |
14505 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
14506 | [(match_parallel 0 "mtcrf_operation" |
14507 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
14508 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
14509 | (match_operand 3 "immediate_operand" "n")] | |
615158e2 | 14510 | UNSPEC_MOVESI_TO_CR))])] |
9ebbca7d | 14511 | "" |
e35b9579 GK |
14512 | "* |
14513 | { | |
14514 | int mask = 0; | |
14515 | int i; | |
14516 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14517 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14518 | operands[4] = GEN_INT (mask); | |
14519 | return \"mtcrf %4,%2\"; | |
309323c2 | 14520 | }" |
b54cf83a | 14521 | [(set_attr "type" "mtcr")]) |
9ebbca7d | 14522 | |
b54cf83a | 14523 | (define_insn "*mtcrfsi" |
309323c2 DE |
14524 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14525 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 JJ |
14526 | (match_operand 2 "immediate_operand" "n")] |
14527 | UNSPEC_MOVESI_TO_CR))] | |
309323c2 DE |
14528 | "GET_CODE (operands[0]) == REG |
14529 | && CR_REGNO_P (REGNO (operands[0])) | |
14530 | && GET_CODE (operands[2]) == CONST_INT | |
14531 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14532 | "mtcrf %R0,%1" | |
b54cf83a | 14533 | [(set_attr "type" "mtcr")]) |
9ebbca7d GK |
14534 | |
14535 | ; The load-multiple instructions have similar properties. | |
14536 | ; Note that "load_multiple" is a name known to the machine-independent | |
14537 | ; code that actually corresponds to the powerpc load-string. | |
14538 | ||
14539 | (define_insn "*lmw" | |
35aba846 DE |
14540 | [(match_parallel 0 "lmw_operation" |
14541 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14542 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14543 | "TARGET_MULTIPLE" | |
14544 | "{lm|lmw} %1,%2") | |
9ebbca7d GK |
14545 | |
14546 | (define_insn "*return_internal_si" | |
e35b9579 GK |
14547 | [(return) |
14548 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 14549 | "TARGET_32BIT" |
cccf3bdc | 14550 | "b%T0" |
9ebbca7d GK |
14551 | [(set_attr "type" "jmpreg")]) |
14552 | ||
14553 | (define_insn "*return_internal_di" | |
e35b9579 GK |
14554 | [(return) |
14555 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 14556 | "TARGET_64BIT" |
cccf3bdc | 14557 | "b%T0" |
9ebbca7d GK |
14558 | [(set_attr "type" "jmpreg")]) |
14559 | ||
14560 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
14561 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
14562 | ||
14563 | (define_insn "*return_and_restore_fpregs_si" | |
14564 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
14565 | [(return) |
14566 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
14567 | (use (match_operand:SI 2 "call_operand" "s")) |
14568 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14569 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14570 | "TARGET_32BIT" | |
14571 | "b %z2") | |
14572 | ||
14573 | (define_insn "*return_and_restore_fpregs_di" | |
14574 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
14575 | [(return) |
14576 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
14577 | (use (match_operand:DI 2 "call_operand" "s")) |
14578 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14579 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14580 | "TARGET_64BIT" | |
14581 | "b %z2") | |
14582 | ||
83720594 RH |
14583 | ; This is used in compiling the unwind routines. |
14584 | (define_expand "eh_return" | |
34dc173c | 14585 | [(use (match_operand 0 "general_operand" ""))] |
9ebbca7d GK |
14586 | "" |
14587 | " | |
14588 | { | |
9739c90c JJ |
14589 | if (TARGET_AIX) |
14590 | rs6000_emit_eh_toc_restore (EH_RETURN_STACKADJ_RTX); | |
83720594 | 14591 | if (TARGET_32BIT) |
34dc173c | 14592 | emit_insn (gen_eh_set_lr_si (operands[0])); |
9ebbca7d | 14593 | else |
34dc173c | 14594 | emit_insn (gen_eh_set_lr_di (operands[0])); |
9ebbca7d GK |
14595 | DONE; |
14596 | }") | |
14597 | ||
83720594 RH |
14598 | ; We can't expand this before we know where the link register is stored. |
14599 | (define_insn "eh_set_lr_si" | |
615158e2 JJ |
14600 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] |
14601 | UNSPECV_EH_RR) | |
466eb3e0 | 14602 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
14603 | "TARGET_32BIT" |
14604 | "#") | |
14605 | ||
14606 | (define_insn "eh_set_lr_di" | |
615158e2 JJ |
14607 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
14608 | UNSPECV_EH_RR) | |
466eb3e0 | 14609 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
14610 | "TARGET_64BIT" |
14611 | "#") | |
9ebbca7d GK |
14612 | |
14613 | (define_split | |
615158e2 | 14614 | [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) |
83720594 RH |
14615 | (clobber (match_scratch 1 ""))] |
14616 | "reload_completed" | |
14617 | [(const_int 0)] | |
9ebbca7d GK |
14618 | " |
14619 | { | |
83720594 | 14620 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d | 14621 | |
83720594 RH |
14622 | if (info->lr_save_p) |
14623 | { | |
14624 | rtx frame_rtx = stack_pointer_rtx; | |
14625 | int sp_offset = 0; | |
14626 | rtx tmp; | |
9ebbca7d | 14627 | |
83720594 RH |
14628 | if (frame_pointer_needed |
14629 | || current_function_calls_alloca | |
14630 | || info->total_size > 32767) | |
14631 | { | |
14632 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
14633 | frame_rtx = operands[1]; | |
14634 | } | |
14635 | else if (info->push_p) | |
14636 | sp_offset = info->total_size; | |
9ebbca7d | 14637 | |
83720594 RH |
14638 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); |
14639 | tmp = gen_rtx_MEM (Pmode, tmp); | |
14640 | emit_move_insn (tmp, operands[0]); | |
14641 | } | |
14642 | else | |
14643 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
14644 | DONE; | |
14645 | }") | |
0ac081f6 | 14646 | |
01a2ccd0 DE |
14647 | (define_insn "prefetch" |
14648 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
14649 | (match_operand:SI 1 "const_int_operand" "n") |
14650 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 14651 | "TARGET_POWERPC" |
6041bf2f DE |
14652 | "* |
14653 | { | |
01a2ccd0 DE |
14654 | if (GET_CODE (operands[0]) == REG) |
14655 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
14656 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
14657 | }" |
14658 | [(set_attr "type" "load")]) | |
a3170dc6 | 14659 | |
10ed84db | 14660 | (include "altivec.md") |
a3170dc6 | 14661 | (include "spe.md") |